OMAP4 Tesla Bridge code formatting fix

This patch fixes coding style and compilation
warnings.

Signed-off-by: Ramesh Gupta G <grgupta@ti.com>

5 files changed, 79 insertions, 335 deletions

diff --git a/drivers/dsp/bridge/hw/hw_prcm.c b/drivers/dsp/bridge/hw/hw_prcm.c
index 25c196af3eca..3a6279e967ab 100644
--- a/drivers/dsp/bridge/hw/hw_prcm.c
+++ b/drivers/dsp/bridge/hw/hw_prcm.c
@@ -189,7 +189,6 @@ HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
 #ifdef OMAP44XX
 
 static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val);
-static HW_STATUS HW_CLK_AutoIdleWriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val);
 
 
 HW_STATUS HW_CLK_Enable(const u32 baseAddress, enum HW_ClkModule_t c)
@@ -367,286 +366,3 @@ HW_STATUS HW_PWR_ForceStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
 
 #endif
 
-
-
-
-
-#if 0
-HW_STATUS HW_CLK_AutoIdleEnable(const u32 baseAddress, enum HW_ClkModule_t c)
-{
-	return HW_CLK_AutoIdleWriteVal(baseAddress, c, HW_SET);
-}
-
-HW_STATUS HW_CLK_AutoIdleDisable(const u32 baseAddress, enum  HW_ClkModule_t c)
-{
-	return HW_CLK_AutoIdleWriteVal(baseAddress, c, HW_CLEAR);
-}
-
-static HW_STATUS HW_CLK_AutoIdleWriteVal(const u32 baseAddress, enum HW_ClkModule_t c,
-				enum HW_SetClear_t val)
-{
-	HW_STATUS status = RET_OK;
-
-	switch (c) {
-
-	default:
-	status = RET_FAIL;
-	break;
-	}
-
-	return status;
-}
-
-HW_STATUS HW_CLK_StbyStatus(const u32 baseAddress, enum HW_SetClear_t *stbyState)
-{
-	HW_STATUS status = RET_OK;
-
-	*stbyState = (enum HW_SetClear_t)CM_TESLA_STBYST_Read32(baseAddress);
-
-	return status;
-}
-
-
-HW_STATUS HW_CLK_IdleStatus(const u32 baseAddress, enum HW_IdleStatus_t *idleState)
-{
-	HW_STATUS status = RET_OK;
-
-	*idleState = (enum HW_IdleStatus_t)CM_TESLA_IDLEST_Read32(baseAddress);
-
-	return status;
-}
-
-
-HW_STATUS HW_RST_Reset(const u32 baseAddress, enum HW_RstModule_t r)
-{
-	return HW_RST_WriteVal(baseAddress, r, HW_SET);
-}
-
-HW_STATUS HW_RST_UnReset(const u32 baseAddress, enum HW_RstModule_t r)
-{
-	return HW_RST_WriteVal(baseAddress, r, HW_CLEAR);
-}
-
-HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, u32 *value)
-{
-	HW_STATUS status = RET_OK;
-
-	*value = PRM_TESLA_RSTCTRLReadRegister32(baseAddress);
-
-	return status;
-}
-
-
-static HW_STATUS HW_RST_WriteVal(const u32 baseAddress, enum HW_RstModule_t p,
-				enum HW_SetClear_t value)
-{
-	HW_STATUS status = RET_OK;
-
-	switch (p) {
-	case HW_RST1_TESLA:
-	PRM_TESLA_RSTCTRL_RST1_Write32(baseAddress, value);
-	break;
-	case HW_RST2_TESLA:
-	PRM_TESLA_RSTCTRL_RST2_Write32(baseAddress, value);
-	break;
-
-	default:
-	status = RET_FAIL;
-	break;
-	}
-
-	return status;
-}
-
-
-HW_STATUS HW_RSTST_RegGet (const u32 baseAddress, u32 *value)
-{
-	HW_STATUS status = RET_OK;
-
-
-
-	return status;
-}
-
-
-
-HW_STATUS HW_RSTST_RegClear (const u32 baseAddress)
-{
-	HW_STATUS status = RET_OK;
-
-	PRM_TESLA_RSTST_Clear32(baseAddress);
-
-	return status;
-}
-
-
-
-
-
-HW_STATUS HW_PWR_RetentionStateSet(const u32 baseAddress,
-	enum HW_PwrModule_t p, enum  HW_RetState_t src, enum HW_SetClear_t  value)
-{
-	HW_STATUS status = RET_OK;
-
-	switch (p) {
-	case HW_PWR_DOMAIN_TESLA:
-		switch (src) {
-		case HW_RETSTATE_LOGIC:
-		PRM_TESLA_PWRSTCTRLWriteLOGICRETSTATE32(baseAddress, value);
-		break;
-		case HW_RETSTATE_L1:
-		PRM_TESLA_PWRSTCTRLWriteL1RETSTATE32(baseAddress, value);
-		break;
-		case HW_RETSTATE_L2:
-		PRM_TESLA_PWRSTCTRLWriteL2RETSTATE32(baseAddress, value);
-		break;
-		default:
-		status = RET_FAIL;
-		break;
-		}
-	break;
-
-	default:
-	status = RET_FAIL;
-	break;
-	}
-
-	return status;
-}
-
-
-
-HW_STATUS HW_PWRST_RegGet(const u32 baseAddress, enum HW_PwrModule_t p, u32 *value)
-{
-	HW_STATUS status = RET_OK;
-	switch (p) {
-	case HW_PWR_DOMAIN_TESLA:
-	*value = PRM_TESLA_PWRSTSTReadRegister32(baseAddress);
-	break;
-
-	default:
-	status = RET_FAIL;
-	break;
-	}
-
-	return status;
-}
-
-HW_STATUS HW_PWR_WkupDependency_RegGet(const u32 baseAddress, u32 *value)
-{
-	HW_STATUS status = RET_OK;
-
-	*value = PRM_WKUP_IVA_ReadRegister32(baseAddress);
-
-	return status;
-}
-
-
-HW_STATUS HW_PWR_WkupDependencySet(const u32 baseAddress, enum HW_PwrModule_t p,
-	enum HW_WeakUpDep_t src, enum HW_SetClear_t value)
-{
-	HW_STATUS status = RET_OK;
-	switch (p) {
-	case HW_PWR_DOMAIN_TESLA:
-		switch (src) {
-		case HW_WKUP_IVA_MPU:
-		PRM_WKUP_IVA_MPU_Write32(baseAddress, value);
-		break;
-		case HW_WKUP_IVA_DUCATI:
-		PRM_WKUP_IVA_DUCATI_Write32(baseAddress, value);
-		break;
-		default:
-		status = RET_FAIL;
-		break;
-		}
-	break;
-
-	default:
-	status = RET_FAIL;
-	break;
-	}
-
-	return status;
-}
-
-
-
-
-HW_STATUS HW_TESLA_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
-{
-	HW_STATUS status = RET_OK;
-
-	*value = PRM_TESLA_CONTEXTReadRegister32(baseAddress);
-
-	return status;
-}
-
-HW_STATUS HW_TESLA_CONTEXT_ClrSet(const u32 baseAddress)
-{
-	HW_STATUS status = RET_OK;
-
-	PRM_TESLA_CONTEXT_Clear32(baseAddress);
-
-	return status;
-}
-
-
-
-HW_STATUS HW_ALWON_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
-{
-	HW_STATUS status = RET_OK;
-
-	*value = PRM_ALWON_CONTEXTReadRegister32(baseAddress);
-
-	return status;
-}
-
-
-
-HW_STATUS HW_IVA_DVFSSet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 value)
-{
-	HW_STATUS status = RET_OK;
-	switch (src) {
-	case HW_DVFS_PERF_TESLA:
-	CM_IVA_DVFS_PERFTESTLA_Write32(baseAddress, value);
-	break;
-	case HW_DVFS_PERF_IVAHD:
-	CM_IVA_DVFS_PERFIVAHD_Write32(baseAddress, value);
-	break;
-	case HW_DVFS_PERF_ABE:
-	CM_IVA_DVFS_PERFABE_Write32(baseAddress, value);
-	break;
-	default:
-	status = RET_FAIL;
-	break;
-	}
-	return status;
-}
-
-HW_STATUS HW_IVA_DVFS_RegGet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 *value)
-{
-	HW_STATUS status = RET_OK;
-	switch (src) {
-	case HW_DVFS_PERF_TESLA:
-	*value = CM_IVA_DVFS_PERFTESTLA_Read32(baseAddress);
-	break;
-	case HW_DVFS_PERF_IVAHD:
-	*value = CM_IVA_DVFS_PERFIVAHD_Read32(baseAddress);
-	break;
-	case HW_DVFS_PERF_ABE:
-	*value = CM_IVA_DVFS_PERFABE_Read32(baseAddress);
-	break;
-	case HW_DVFS_RESULT:
-	*value = CM_IVA_DVFS_RESULT_Read32(baseAddress);
-	break;
-	case HW_DVFS_CURRENT:
-	*value = CM_IVA_DVFS_CURRENT_Read32(baseAddress);
-	break;
-	default:
-	status = RET_FAIL;
-	break;
-	}
-	return status;
-
-}
-#endif
diff --git a/drivers/dsp/bridge/services/services.c b/drivers/dsp/bridge/services/services.c
index 3f8f9c686120..4902b2fb6516 100644
--- a/drivers/dsp/bridge/services/services.c
+++ b/drivers/dsp/bridge/services/services.c
@@ -111,8 +111,11 @@ void SERVICES_Exit(void)
 bool SERVICES_Init(void)
 {
 	bool fInit = true;
-       bool fCFG, fCSL, fDBG, fDPC, fKFILE, fLST, fMEM;
-       bool fREG, fSYNC, fCLK, fUTIL, fNTFY;
+	bool fCFG, fCSL, fDBG, fDPC, fKFILE, fLST, fMEM;
+	bool fREG, fSYNC, fUTIL, fNTFY;
+#ifdef OMAP_3430
+	bool fCLK;
+#endif
 
 	DBC_Require(cRefs >= 0);
 
diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c
index e6dfd0cc8a15..fd033aaf49fa 100755
--- a/drivers/dsp/bridge/wmd/io_sm.c
+++ b/drivers/dsp/bridge/wmd/io_sm.c
@@ -226,8 +226,8 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 	struct notify_config ntfy_config;
 	struct notify_tesladrv_config tesla_cfg;
 	struct notify_tesladrv_params params;
-	u32 mem_va;
-	u32 mem_pa;
+	dma_addr_t mem_pa;
+	void *mem_va = NULL;
 	char driverName[32] = "NOTIFYMBXDRV";
 	int ntfystatus;
 	irq_handler = (void *) IO_ISR;
@@ -325,14 +325,14 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 	if (mem_va == NULL)
 		pr_err("Memory allocation for communication failed\n");
 	
-	params.num_events          = 32;
+	params.num_events = 32;
 	params.num_reserved_events  = 0;
 	params.send_event_poll_count = (int) -1;
-	params.recv_int_id          = 26;
-	params.send_int_id          = 55;
-	params.shared_addr_size     = 0x4000;
-	params.shared_addr                = mem_va;
-	params.remote_proc_id         = 0;
+	params.recv_int_id = 26;
+	params.send_int_id = 55;
+	params.shared_addr_size = 0x4000;
+	params.shared_addr = (int)mem_va;
+	params.remote_proc_id = 0;
 
 	handle = notify_tesladrv_create(driverName, &params);
 	if (handle == NULL) {
@@ -1124,8 +1124,10 @@ void IO_ISR(IN  unsigned long int procId,
         pRefData = external_piomgr;
         hIOMgr = (struct IO_MGR *)pRefData;
 	
+#ifdef OMAP_3430
 	bool fSchedDPC;
-//       DBC_Require(irq == INT_MAIL_MPU_IRQ);
+	DBC_Require(irq == INT_MAIL_MPU_IRQ);
+#endif
 	DBC_Require(MEM_IsValidHandle(hIOMgr, IO_MGRSIGNATURE));
 	DBG_Trace(DBG_LEVEL3, "Entering IO_ISR(0x%x)\n", pRefData);
 
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
index f619b2091301..a04c3019b834 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -141,7 +141,9 @@ static DSP_STATUS PteSet(struct PgTableAttrs *pt, u32 pa, u32 va,
 static DSP_STATUS MemMapVmalloc(struct WMD_DEV_CONTEXT *hDevContext,
 			u32 ulMpuAddr, u32 ulVirtAddr,
 			u32 ulNumBytes, struct HW_MMUMapAttrs_t *hwAttrs);
-void GetHWRegs(u32 prcm_base, u32 cm1_base, u32 cm2_base);
+#ifdef OMAP44XX
+void GetHWRegs(void __iomem *prm_base, u32 cm1_base, u32 cm2_base);
+#endif
 
 /*  ----------------------------------- Globals */
 
@@ -249,7 +251,9 @@ static inline void tlb_flush_all(const void __iomem *base)
 static inline void flush_all(struct WMD_DEV_CONTEXT *pDevContext)
 {
 	struct CFG_HOSTRES resources;
+#ifdef OMAP_3430
 	u32 temp = 0;
+#endif
 
 	CFG_GetHostResources((struct CFG_DEVNODE *)DRV_GetFirstDevExtension(),
 				&resources);
@@ -265,7 +269,7 @@ static inline void flush_all(struct WMD_DEV_CONTEXT *pDevContext)
 	} else
 		tlb_flush_all(pDevContext->dwDSPMmuBase);
 #else
-		tlb_flush_all(pDevContext->dwDSPMmuBase);
+		tlb_flush_all((void __iomem *)pDevContext->dwDSPMmuBase);
 #endif
 }
 
@@ -316,8 +320,10 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext)
 	DSP_STATUS status = DSP_SOK;
 	struct WMD_DEV_CONTEXT *pDevContext = hDevContext;
 	struct CFG_HOSTRES resources;
+#ifdef OMAP_3430
 	u32 temp;
 	enum HW_PwrState_t    pwrState;
+#endif
 
 	DBG_Trace(DBG_ENTER, "Board in the monitor state  \n");
 	status = CFG_GetHostResources(
@@ -326,19 +332,20 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext)
 		goto error_return;
 
 #ifdef OMAP44XX
-	printk("Disabling Clocks... and resources.dwCm1Base = 0x%x \n  resources.dwCm2Base= 0x%x\n"
-		"resources.dwPrmBase = 0x%x", resources.dwCm1Base, resources.dwCm2Base, resources.dwPrmBase);
-	HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
+	printk(KERN_ERR "Disabling Clocks... and resources.dwCm1Base = 0x%x\n"
+		"resources.dwCm2Base= 0x%x\n"
+		"resources.dwPrmBase = 0x%x\n",
+		(unsigned int)resources.dwCm1Base,
+		(unsigned int)resources.dwCm2Base,
+		(unsigned int)resources.dwPrmBase);
+	HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA);
 	printk("Resetting DSP...");
 	HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
 	printk("Enabling Clocks...");
-	HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
-
-
-	HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);/*TODO check if it is correct*/
-	HW_RST_Reset(resources.dwPrmBase, HW_RST2_TESLA);/*Just to ensure that the RST's are enabled*/
+	HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA);
+	HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
+	HW_RST_Reset(resources.dwPrmBase, HW_RST2_TESLA);
 	HW_RST_UnReset(resources.dwPrmBase, HW_RST2_TESLA);
-
 	*((REG_UWORD32 *)((u32)(resources.dwDmmuBase)+0x50)) = 0x400;
 #else
 	
@@ -457,21 +464,22 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 	u32 ulShmBaseVirt;	/* Dsp Virt SM base addr */
 	u32 ulTLBBaseVirt;	/* Base of MMU TLB entry */
 	u32 ulShmOffsetVirt;	/* offset of ulShmBaseVirt from ulTLBBaseVirt */
+	u32 temp;
+	struct CFG_HOSTRES resources;
 	s32 iEntryNdx;
 	s32 itmpEntryNdx = 0;	/* DSP-MMU TLB entry base address */
-	struct CFG_HOSTRES resources;
-	u32 temp;
+#ifdef OMAP_3430
 	u32 ulDspClkRate;
 	u32 ulDspClkAddr;
 	u32 ulBiosGpTimer;
 	u32 uClkCmd;
-	struct IO_MGR *hIOMgr;
-	register u32 newAdress = ((u32)(dwDSPAddr));
-
 	u32 ulLoadMonitorTimer;
 	u32 extClkId = 0;
 	u32 tmpIndex;
 	u32 clkIdIndex = MBX_PM_MAX_RESOURCES;
+#endif
+	struct IO_MGR *hIOMgr;
+	register u32 newAdress = ((u32)(dwDSPAddr));
 
 	DBG_Trace(DBG_ENTER, "Entering WMD_BRD_Start:\n hDevContext: 0x%x\n\t "
 			     "dwDSPAddr: 0x%x\n", hDevContext, dwDSPAddr);
@@ -851,10 +859,11 @@ static DSP_STATUS WMD_BRD_Stop(struct WMD_DEV_CONTEXT *hDevContext)
 	DSP_STATUS status = DSP_SOK;
 	struct WMD_DEV_CONTEXT *pDevContext = hDevContext;
 	struct CFG_HOSTRES resources;
+#ifdef OMAP_3430
 	struct PgTableAttrs *pPtAttrs;
 	u32 dspPwrState;
 	DSP_STATUS clk_status;
-
+#endif
 	DBG_Trace(DBG_ENTER, "Entering WMD_BRD_Stop:\nhDevContext: 0x%x\n",
 		  hDevContext);
 
@@ -948,7 +957,9 @@ static DSP_STATUS WMD_BRD_Delete(struct WMD_DEV_CONTEXT *hDevContext)
 	struct WMD_DEV_CONTEXT *pDevContext = hDevContext;
 	struct CFG_HOSTRES resources;
 	struct PgTableAttrs *pPtAttrs;
+#ifdef OMAP_3430
 	DSP_STATUS clk_status;
+#endif
 
 	DBG_Trace(DBG_ENTER, "Entering WMD_BRD_Delete:\nhDevContext: 0x%x\n",
 		  hDevContext);
@@ -1208,18 +1219,28 @@ static DSP_STATUS WMD_DEV_Create(OUT struct WMD_DEV_CONTEXT **ppDevContext,
 		DBG_Trace(DBG_LEVEL7, "WMD_DEV_create:Reset mail box and "
 			  "enable the clock \n");
 #ifdef OMAP44XX
-			HW_PWR_ForceStateSet(resources.dwCm1Base, HW_PWR_DOMAIN_TESLA, HW_SW_SUP_WAKEUP);
-			HW_PWR_PowerStateSet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA, HW_PWR_STATE_ON);
-			HW_PWR_PowerStateGet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA, &pwrState);
+			HW_PWR_ForceStateSet((u32)resources.dwCm1Base,
+				HW_PWR_DOMAIN_TESLA, HW_SW_SUP_WAKEUP);
+			HW_PWR_PowerStateSet((u32)resources.dwPrmBase,
+				HW_PWR_DOMAIN_TESLA, HW_PWR_STATE_ON);
+			HW_PWR_PowerStateGet((u32)resources.dwPrmBase,
+				HW_PWR_DOMAIN_TESLA, &pwrState);
 				while (HW_PWR_STATE_ON != pwrState) {
-						iIterations++;
-						if (iIterations >= 500) {
-							HW_PWRSTCTRL_RegGet(resources.dwPrmBase, &PwrCtrl);
-							printk("Error: Failed to put the DSP domain into ON"
-								"state PRM_TESLA_PWRSTCTRL = 0x%x", PwrCtrl);
-								return DSP_EFAIL;
-						}
-						HW_PWR_PowerStateGet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA, &pwrState);
+					iIterations++;
+					if (iIterations >= 500) {
+						HW_PWRSTCTRL_RegGet((u32)
+							resources.dwPrmBase,
+							&PwrCtrl);
+						printk("Error: Failed to put"
+							" the DSP domain in ON"
+							"state"
+							" PRM_TESLA_PWRSTCTRL ="
+							" 0x%x", PwrCtrl);
+						return DSP_EFAIL;
+					}
+					HW_PWR_PowerStateGet((u32)
+						resources.dwPrmBase,
+						HW_PWR_DOMAIN_TESLA, &pwrState);
 				}
 /*			HW_CLK_Enable (resources.dwPrmBase, HW_CLK_IF_MBOX);*/
 #else
@@ -1233,7 +1254,7 @@ static DSP_STATUS WMD_DEV_Create(OUT struct WMD_DEV_CONTEXT **ppDevContext,
 		/* 24xx-Linux MMU address is obtained from the host
 		 * resources struct */
 #endif
-		pDevContext->dwDSPMmuBase = resources.dwDmmuBase;
+		pDevContext->dwDSPMmuBase = (u32)resources.dwDmmuBase;
 	}
 	if (DSP_SUCCEEDED(status)) {
 		pDevContext->hDevObject = hDevObject;
@@ -2130,7 +2151,7 @@ static DSP_STATUS MemMapVmalloc(struct WMD_DEV_CONTEXT *pDevContext,
 	return status;
 }
 #ifdef OMAP44XX
-void GetHWRegs(u32 prm_base, u32 cm1_base, u32 cm2_base) { }
+void GetHWRegs(void __iomem *prm_base, u32 cm1_base, u32 cm2_base) { }
 
 #else
 static void GetHWRegs(void __iomem *prm_base, void __iomem *cm_base)
@@ -2183,9 +2204,9 @@ void configureDspMmu(struct WMD_DEV_CONTEXT *pDevContext, u32 dataBasePhys,
 		 endianism, elemSize, mixedSize);
 	status = CFG_GetHostResources(
 		 (struct CFG_DEVNODE *)DRV_GetFirstDevExtension(), &resources);
-	status = HW_MMU_TLBAdd(pDevContext->dwDSPMmuBase, dataBasePhys,
-				dspBaseVirt, sizeInBytes, nEntryStart,
-				&mapAttrs, HW_SET, HW_SET);
+	status = HW_MMU_TLBAdd((const void __iomem *)pDevContext->dwDSPMmuBase,
+				dataBasePhys, dspBaseVirt, sizeInBytes,
+				nEntryStart, &mapAttrs, HW_SET, HW_SET);
 }
 
 /*
diff --git a/drivers/dsp/bridge/wmd/tiomap_sm.c b/drivers/dsp/bridge/wmd/tiomap_sm.c
index 11e42b967aaf..573d54b476e9 100644
--- a/drivers/dsp/bridge/wmd/tiomap_sm.c
+++ b/drivers/dsp/bridge/wmd/tiomap_sm.c
@@ -75,13 +75,15 @@ static inline unsigned int fifo_full(void __iomem *mbox_base, int mbox_id)
 DSP_STATUS CHNLSM_EnableInterrupt(struct WMD_DEV_CONTEXT *pDevContext)
 {
 	DSP_STATUS status = DSP_SOK;
+#ifdef OMAP_3430
 	u32 numMbxMsg;
 	u32 mbxValue;
+	u32 hwStatus;
+#endif
 	struct CFG_HOSTRES resources;
 	u32 devType;
 	struct IO_MGR *hIOMgr;
 	u32 eventNo;
-	u32 hwStatus;
 
 	DBG_Trace(DBG_ENTER, "CHNLSM_EnableInterrupt(0x%x)\n", pDevContext);
 
@@ -115,11 +117,8 @@ DSP_STATUS CHNLSM_EnableInterrupt(struct WMD_DEV_CONTEXT *pDevContext)
 
 DSP_STATUS CHNLSM_DisableInterrupt(struct WMD_DEV_CONTEXT *pDevContext)
 {
-        DSP_STATUS status = DSP_SOK;
-        int  Notifystatus;
         u32 eventNo;
         struct CFG_HOSTRES resources;
-        u32 hwStatus;
 
 	DBG_Trace(DBG_ENTER, "CHNLSM_DisableInterrupt(0x%x)\n", pDevContext);
 
@@ -141,6 +140,11 @@ DSP_STATUS CHNLSM_DisableInterrupt(struct WMD_DEV_CONTEXT *pDevContext)
 DSP_STATUS CHNLSM_InterruptDSP2(struct WMD_DEV_CONTEXT *pDevContext,
 				u16 wMbVal)
 {
+	struct CFG_HOSTRES resources;
+	DSP_STATUS status = DSP_SOK;
+	int  notifyStatus;
+
+#ifdef OMAP_3430
 #ifndef CONFIG_DISABLE_BRIDGE_PM
 #ifdef CONFIG_BRIDGE_DVFS
 	struct dspbridge_platform_data *pdata =
@@ -148,11 +152,9 @@ DSP_STATUS CHNLSM_InterruptDSP2(struct WMD_DEV_CONTEXT *pDevContext,
 	u32 opplevel = 0;
 #endif
 #endif
-	struct CFG_HOSTRES resources;
-	DSP_STATUS status = DSP_SOK;
 	unsigned long timeout;
 	u32 temp;
-	int  notifyStatus;
+#endif
 
 	status = CFG_GetHostResources((struct CFG_DEVNODE *)DRV_GetFirstDevExtension(),
 				      &resources);