Bridge changes cleanup prcm Bridge changes cleanup prcm

Signed-off-by: Ramesh Gupta G <grgupta@ti.com>

6 files changed, 521 insertions, 643 deletions

diff --git a/drivers/dsp/bridge/hw/PRCMAccInt.h b/drivers/dsp/bridge/hw/PRCMAccInt.h
index cd9203c4c088..73f8b676c1ff 100644
--- a/drivers/dsp/bridge/hw/PRCMAccInt.h
+++ b/drivers/dsp/bridge/hw/PRCMAccInt.h
@@ -252,206 +252,201 @@
 /* The following represent the enumerated values for each bitfield */
 
 enum PRCMPRCM_CLKCFG_CTRLValid_configE {
-    PRCMPRCM_CLKCFG_CTRLValid_configUpdated = 0x0000,
-    PRCMPRCM_CLKCFG_CTRLValid_configClk_valid = 0x0001
+	PRCMPRCM_CLKCFG_CTRLValid_configUpdated = 0x0000,
+	PRCMPRCM_CLKCFG_CTRLValid_configClk_valid = 0x0001
 } ;
 
 enum PRCMCM_CLKSEL2_CORECLKSEL_GPT8E {
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT832k = 0x0000,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys = 0x0001,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext = 0x0002,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT8Reserved = 0x0003
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT832k = 0x0000,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys = 0x0001,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext = 0x0002,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT8Reserved = 0x0003
 } ;
 
 enum PRCMCM_CLKSEL2_CORECLKSEL_GPT7E {
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT732k = 0x0000,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys = 0x0001,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext = 0x0002,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT7Reserved = 0x0003
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT732k = 0x0000,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys = 0x0001,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext = 0x0002,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT7Reserved = 0x0003
 } ;
 
 enum PRCMCM_CLKSEL2_CORECLKSEL_GPT6E {
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT632k = 0x0000,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys = 0x0001,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext = 0x0002,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT6Reserved = 0x0003
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT632k = 0x0000,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys = 0x0001,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext = 0x0002,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT6Reserved = 0x0003
 } ;
 
 enum PRCMCM_CLKSEL2_CORECLKSEL_GPT5E {
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT532k = 0x0000,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys = 0x0001,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext = 0x0002,
-    PRCMCM_CLKSEL2_CORECLKSEL_GPT5Reserved = 0x0003
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT532k = 0x0000,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys = 0x0001,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext = 0x0002,
+	PRCMCM_CLKSEL2_CORECLKSEL_GPT5Reserved = 0x0003
 } ;
 
 enum PRCMPM_PWSTCTRL_DSPPowerStateE {
-    PRCMPM_PWSTCTRL_DSPPowerStateON = 0x0000,
-    PRCMPM_PWSTCTRL_DSPPowerStateRET = 0x0001,
-    PRCMPM_PWSTCTRL_DSPPowerStateReserved = 0x0002,
-    PRCMPM_PWSTCTRL_DSPPowerStateOFF = 0x0003
+	PRCMPM_PWSTCTRL_DSPPowerStateON = 0x0000,
+	PRCMPM_PWSTCTRL_DSPPowerStateRET = 0x0001,
+	PRCMPM_PWSTCTRL_DSPPowerStateReserved = 0x0002,
+	PRCMPM_PWSTCTRL_DSPPowerStateOFF = 0x0003
 } ;
 
 enum PRCMPM_PWSTCTRL_IVA2PowerStateE {
-    PRCMPM_PWSTCTRL_IVA2PowerStateON = 0x0003,
-    PRCMPM_PWSTCTRL_IVA2PowerStateRET = 0x0001,
-    PRCMPM_PWSTCTRL_IVA2PowerStateReserved = 0x0002,
-    PRCMPM_PWSTCTRL_IVA2PowerStateOFF = 0x0000
+	PRCMPM_PWSTCTRL_IVA2PowerStateON = 0x0003,
+	PRCMPM_PWSTCTRL_IVA2PowerStateRET = 0x0001,
+	PRCMPM_PWSTCTRL_IVA2PowerStateReserved = 0x0002,
+	PRCMPM_PWSTCTRL_IVA2PowerStateOFF = 0x0000
 } ;
 
 #else
 
-#define PRM_PRM_IRQSTATUS_TESLA_OFFSET 			 (u32)(0x030)
-#define PRM_PRM_IRQENABLE_TESLA_OFFSET           (u32)(0x038)
+#define PRM_PRM_IRQSTATUS_TESLA_OFFSET 		(u32)(0x030)
+#define PRM_PRM_IRQENABLE_TESLA_OFFSET		(u32)(0x038)
 
 /*TESLA_PRM*/
-#define PRM_PM_TESLA_PWRSTCTRL_OFFSET            (u32)(0x400)
-#define PRM_PM_TESLA_PWRSTST_OFFSET              (u32)(0x404)
-#define PRM_RM_TESLA_RSTCTRL_OFFSET              (u32)(0x410)
-#define PRM_RM_TESLA_RSTST_OFFSET                (u32)(0x414)
-#define PRM_RM_TESLA_TESLA_CONTEXT_OFFSET        (u32)(0x424)
+#define PRM_PM_TESLA_PWRSTCTRL_OFFSET		(u32)(0x400)
+#define PRM_PM_TESLA_PWRSTST_OFFSET		(u32)(0x404)
+#define PRM_RM_TESLA_RSTCTRL_OFFSET		(u32)(0x410)
+#define PRM_RM_TESLA_RSTST_OFFSET		(u32)(0x414)
+#define PRM_RM_TESLA_TESLA_CONTEXT_OFFSET	(u32)(0x424)
 
 /*CORE_PRM*/
-#define PRM_PM_CORE_PWRSTCTRL_OFFSET             (u32)(0x700)
+#define PRM_PM_CORE_PWRSTCTRL_OFFSET		(u32)(0x700)
 
 /*ALWAYS_ON_PRM*/
-#define PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET         (u32)(0x630)
-#define PRM_RM_ALWON_SR_IVA_CONTEXT_OFFSET       (u32)(0x634)
+#define PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET	(u32)(0x630)
+#define PRM_RM_ALWON_SR_IVA_CONTEXT_OFFSET	(u32)(0x634)
 
 
 /*CM1*/
 /*base address = 0x4A00_5000*/
 
 /*CKGEN_CM1*/
-#define CM1_CM_CLKMODE_DPLL_IVA_OFFSET           (u32)(0x1A0)
-#define CM1_CM_IDLEST_DPLL_IVA_OFFSET            (u32)(0x1A4)
-#define CM1_CM_AUTOIDLE_DPLL_IVA_OFFSET          (u32)(0x1A8)
-#define CM1_CM_CLKSEL_DPLL_IVA_OFFSET            (u32)(0x1AC)
-#define CM1_CM_DIV_M2_DPLL_IVA_OFFSET            (u32)(0x1B0)
-#define CM1_CM_DIV_M4_DPLL_IVA_OFFSET            (u32)(0x1B8)
-#define CM1_CM_DIV_M5_DPLL_IVA_OFFSET            (u32)(0x1BC)
-#define CM1_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET    (u32)(0x1C8)
-#define CM1_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET    (u32)(0x1CC)
-#define CM1_CM_BYPCLK_DPLL_IVA_OFFSET            (u32)(0x1DC)
+#define CM1_CM_CLKMODE_DPLL_IVA_OFFSET		(u32)(0x1A0)
+#define CM1_CM_IDLEST_DPLL_IVA_OFFSET		(u32)(0x1A4)
+#define CM1_CM_AUTOIDLE_DPLL_IVA_OFFSET		(u32)(0x1A8)
+#define CM1_CM_CLKSEL_DPLL_IVA_OFFSET		(u32)(0x1AC)
+#define CM1_CM_DIV_M2_DPLL_IVA_OFFSET		(u32)(0x1B0)
+#define CM1_CM_DIV_M4_DPLL_IVA_OFFSET		(u32)(0x1B8)
+#define CM1_CM_DIV_M5_DPLL_IVA_OFFSET		(u32)(0x1BC)
+#define CM1_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET	(u32)(0x1C8)
+#define CM1_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET	(u32)(0x1CC)
+#define CM1_CM_BYPCLK_DPLL_IVA_OFFSET		(u32)(0x1DC)
 
 /*TESLA_CM1*/
-#define CM1_CM_TESLA_CLKSTCTRL_OFFSET            (u32)(0x400)
-#define CM1_CM_TESLA_STATICDEP_OFFSET            (u32)(0x404)
-#define CM1_CM_TESLA_DYNAMICDEP_OFFSET           (u32)(0x408)
-#define CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET        (u32)(0x420)
+#define CM1_CM_TESLA_CLKSTCTRL_OFFSET		(u32)(0x400)
+#define CM1_CM_TESLA_STATICDEP_OFFSET		(u32)(0x404)
+#define CM1_CM_TESLA_DYNAMICDEP_OFFSET		(u32)(0x408)
+#define CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET	(u32)(0x420)
 
 /*ABE_CM1*/
-#define CM1_CM1_ABE_CLKSTCTRL_OFFSET             (u32)(0x500)
-#define CM1_CM1_ABE_MCBSP1_CLKCTRL_OFFSET        (u32)(0x548)
-#define CM1_CM1_ABE_MCBSP2_CLKCTRL_OFFSET        (u32)(0x550)
-#define CM1_CM1_ABE_MCBSP3_CLKCTRL_OFFSET        (u32)(0x558)
-#define CM1_CM1_ABE_TIMER5_CLKCTRL_OFFSET        (u32)(0x568)
-#define CM1_CM1_ABE_TIMER6_CLKCTRL_OFFSET        (u32)(0x570)
-#define CM1_CM1_ABE_TIMER7_CLKCTRL_OFFSET        (u32)(0x578)
-#define CM1_CM1_ABE_TIMER8_CLKCTRL_OFFSET        (u32)(0x580)
+#define CM1_CM1_ABE_CLKSTCTRL_OFFSET		(u32)(0x500)
+#define CM1_CM1_ABE_MCBSP1_CLKCTRL_OFFSET	(u32)(0x548)
+#define CM1_CM1_ABE_MCBSP2_CLKCTRL_OFFSET	(u32)(0x550)
+#define CM1_CM1_ABE_MCBSP3_CLKCTRL_OFFSET	(u32)(0x558)
+#define CM1_CM1_ABE_TIMER5_CLKCTRL_OFFSET	(u32)(0x568)
+#define CM1_CM1_ABE_TIMER6_CLKCTRL_OFFSET	(u32)(0x570)
+#define CM1_CM1_ABE_TIMER7_CLKCTRL_OFFSET	(u32)(0x578)
+#define CM1_CM1_ABE_TIMER8_CLKCTRL_OFFSET	(u32)(0x580)
 
 /*CM2*/
 /*base address = 0x4A00_8000*/
 
 /*CKGEN_CM2*/
-#define CM2_CM_IVA_DVFS_PERF_TESLA_OFFSET        (u32)(0x128)
-#define CM2_CM_IVA_DVFS_PERF_IVAHD_OFFSET        (u32)(0x12C)
-#define CM2_CM_IVA_DVFS_PERF_ABE_OFFSET          (u32)(0x130)
-#define CM2_CM_IVA_DVFS_RESULT_OFFSET            (u32)(0x134)
-#define CM2_CM_IVA_DVFS_CURRENT_OFFSET           (u32)(0x138)
+#define CM2_CM_IVA_DVFS_PERF_TESLA_OFFSET	(u32)(0x128)
+#define CM2_CM_IVA_DVFS_PERF_IVAHD_OFFSET	(u32)(0x12C)
+#define CM2_CM_IVA_DVFS_PERF_ABE_OFFSET		(u32)(0x130)
+#define CM2_CM_IVA_DVFS_RESULT_OFFSET		(u32)(0x134)
+#define CM2_CM_IVA_DVFS_CURRENT_OFFSET		(u32)(0x138)
 
 /*L4PER_CM2*/
-#define CM2_CM_L4PER_CLKSTCTRL_OFFSET            (u32)(0x1400)
-#define CM2_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET    (u32)(0x1428)
-#define CM2_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET    (u32)(0x1430)
-#define CM2_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET     (u32)(0x1438)
-#define CM2_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET     (u32)(0x1440)
-#define CM2_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET     (u32)(0x1448)
-#define CM2_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET     (u32)(0x1450)
-#define CM2_CM_L4PER_MCBSP4_CLKCTRL_OFFSET       (u32)(0x14E0)
-#define CM2_CM_L4PER_MCBSP5_CLKCTRL_OFFSET       (u32)(0x14E8)
+#define CM2_CM_L4PER_CLKSTCTRL_OFFSET		(u32)(0x1400)
+#define CM2_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET	(u32)(0x1428)
+#define CM2_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET	(u32)(0x1430)
+#define CM2_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET	(u32)(0x1438)
+#define CM2_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET	(u32)(0x1440)
+#define CM2_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET	(u32)(0x1448)
+#define CM2_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET	(u32)(0x1450)
+#define CM2_CM_L4PER_MCBSP4_CLKCTRL_OFFSET	(u32)(0x14E0)
+#define CM2_CM_L4PER_MCBSP5_CLKCTRL_OFFSET	(u32)(0x14E8)
 
 
 /*BITS MASKS & OFFSETS*/
 
-/******************PM_TESLA_PWRSTCTRL***********/
-#define PM_TESLA_PWRSTCTRL_PowerState_OFFSET            (u32)(0x0)
-#define PM_TESLA_PWRSTCTRL_PowerState_MASK              (u32)(0x3)
-#define PM_TESLA_PWRSTCTRL_LogicRetState_OFFSET         (u32)(0x2)
-#define PM_TESLA_PWRSTCTRL_LogicRetState_MASK           (u32)(0x4)
-#define PM_TESLA_PWRSTCTRL_L1RetState_OFFSET            (u32)(0x8)
-#define PM_TESLA_PWRSTCTRL_L1RetState_MASK              (u32)(0x100)
-#define PM_TESLA_PWRSTCTRL_L2RetState_OFFSET            (u32)(0x9)
-#define PM_TESLA_PWRSTCTRL_L2RetState_MASK              (u32)(0x200)
+/*PM_TESLA_PWRSTCTRL*/
+#define PM_TESLA_PWRSTCTRL_PowerState_OFFSET	(u32)(0x0)
+#define PM_TESLA_PWRSTCTRL_PowerState_MASK	(u32)(0x3)
+#define PM_TESLA_PWRSTCTRL_LogicRetState_OFFSET	(u32)(0x2)
+#define PM_TESLA_PWRSTCTRL_LogicRetState_MASK	(u32)(0x4)
+#define PM_TESLA_PWRSTCTRL_L1RetState_OFFSET	(u32)(0x8)
+#define PM_TESLA_PWRSTCTRL_L1RetState_MASK	(u32)(0x100)
+#define PM_TESLA_PWRSTCTRL_L2RetState_OFFSET	(u32)(0x9)
+#define PM_TESLA_PWRSTCTRL_L2RetState_MASK	(u32)(0x200)
 
-/******************PRM_PM_TESLA_PWRSTST*********/
-#define PM_TESLA_PWRSTST_PowerState_OFFSET              (u32)(0x0)
-#define PM_TESLA_PWRSTST_PowerState_MASK                (u32)(0x3)
+/*PRM_PM_TESLA_PWRSTST*/
+#define PM_TESLA_PWRSTST_PowerState_OFFSET	(u32)(0x0)
+#define PM_TESLA_PWRSTST_PowerState_MASK	(u32)(0x3)
 
-/******************RM_TESLA_RSTCTRL*************/
-#define RM_TESLA_RSTCTRL_RST1_MASK                      (u32)(0x1)
-#define RM_TESLA_RSTCTRL_RST1_OFFSET                    (u32)(0x0)
-#define RM_TESLA_RSTCTRL_RST2_MASK                      (u32)(0x2)
-#define RM_TESLA_RSTCTRL_RST2_OFFSET                    (u32)(0x1)
+/*RM_TESLA_RSTCTRL*/
+#define RM_TESLA_RSTCTRL_RST1_MASK		(u32)(0x1)
+#define RM_TESLA_RSTCTRL_RST1_OFFSET		(u32)(0x0)
+#define RM_TESLA_RSTCTRL_RST2_MASK		(u32)(0x2)
+#define RM_TESLA_RSTCTRL_RST2_OFFSET		(u32)(0x1)
 
-/******************RM_TESLA_RSTST***************/
+/*RM_TESLA_RSTST*/
 
-#define RM_TESLA_RSTST_Clear_MASK                       (u32)(0x0F)
+#define RM_TESLA_RSTST_Clear_MASK		(u32)(0x0F)
 
-/******************RM_TESLA_TESLA_CONTEXT*******/
+/*RM_TESLA_TESLA_CONTEXT*/
 
-#define RM_TESLA_TESLA_CONTEXT_Clear_MASK               (u32)(0x701)
+#define RM_TESLA_TESLA_CONTEXT_Clear_MASK	(u32)(0x701)
 
-/******************PM_CORE_PWRSTCTRL************/
+/*PM_CORE_PWRSTCTRL*/
 
-#define PRM_PM_CORE_PWRSTCTRL_PowerControl_OFFSET       (u32)(0x0)
-#define PRM_PM_CORE_PWRSTCTRL_PowerControl_MASK         (u32)(0x3)
+#define PRM_PM_CORE_PWRSTCTRL_PowerControl_OFFSET	(u32)(0x0)
+#define PRM_PM_CORE_PWRSTCTRL_PowerControl_MASK		(u32)(0x3)
 
-/******************PM_ALWON_SR_IVA_WKDEP********/
+/*PM_ALWON_SR_IVA_WKDEP*/
 
-#define PM_ALWON_SR_IVA_WKDEP_MPU_OFFSET                (u32)(0x0)
-#define PM_ALWON_SR_IVA_WKDEP_MPU_MASK                  (u32)(0x1)
-#define PM_ALWON_SR_IVA_WKDEP_DUCATI_OFFSET             (u32)(0x1)
-#define PM_ALWON_SR_IVA_WKDEP_DUCATI_MASK               (u32)(0x2)
+#define PM_ALWON_SR_IVA_WKDEP_MPU_OFFSET	(u32)(0x0)
+#define PM_ALWON_SR_IVA_WKDEP_MPU_MASK		(u32)(0x1)
+#define PM_ALWON_SR_IVA_WKDEP_DUCATI_OFFSET	(u32)(0x1)
+#define PM_ALWON_SR_IVA_WKDEP_DUCATI_MASK	(u32)(0x2)
 
-/******************CM_TESLA_CLKSTCTRL***********/
+/*CM_TESLA_CLKSTCTRL*/
 
-#define CM_TESLA_CLKSTCTRL_Transition_OFFSET            (u32)(0x0)
-#define CM_TESLA_CLKSTCTRL_Transition_MASK              (u32)(0x3)
+#define CM_TESLA_CLKSTCTRL_Transition_OFFSET	(u32)(0x0)
+#define CM_TESLA_CLKSTCTRL_Transition_MASK	(u32)(0x3)
 
-/******************CM_TESLA_TESLA_CLKCTRL*******/
-#define CM_TESLA_TESLA_CLKCTRL_STBY_MASK                (u32)(0x40000)
-#define CM_TESLA_TESLA_CLKCTRL_STBY_OFFSET              (u32)(0x18)
-#define CM_TESLA_TESLA_CLKCTRL_IDLE_MASK                (u32)(0x30000)
-#define CM_TESLA_TESLA_CLKCTRL_IDLE_OFFSET              (u32)(0x16)
-#define CM_TESLA_TESLA_CLKCTRL_MODMODE_OFFSET           (u32)(0x0)
-#define CM_TESLA_TESLA_CLKCTRL_MODMODE_MASK             (u32)(0x03)
+/*CM_TESLA_TESLA_CLKCTRL*/
+#define CM_TESLA_TESLA_CLKCTRL_STBY_MASK	(u32)(0x40000)
+#define CM_TESLA_TESLA_CLKCTRL_STBY_OFFSET	(u32)(0x18)
+#define CM_TESLA_TESLA_CLKCTRL_IDLE_MASK	(u32)(0x30000)
+#define CM_TESLA_TESLA_CLKCTRL_IDLE_OFFSET	(u32)(0x16)
+#define CM_TESLA_TESLA_CLKCTRL_MODMODE_OFFSET	(u32)(0x0)
+#define CM_TESLA_TESLA_CLKCTRL_MODMODE_MASK	(u32)(0x03)
 
-/******************CM1_ABE_CLKSTCTRL************/
+/*CM1_ABE_CLKSTCTRL*/
 
-#define CM1_ABE_CLKSTCTRL_Transition_OFFSET             (u32)(0x0)
-#define CM1_ABE_CLKSTCTRL_Transition_MASK               (u32)(0x3)
+#define CM1_ABE_CLKSTCTRL_Transition_OFFSET	(u32)(0x0)
+#define CM1_ABE_CLKSTCTRL_Transition_MASK	(u32)(0x3)
 
-/******************CM1_ABE_MCBSPX&TIMERX_CLKCTRL*/
-#define CM1_ABE_CLKCTRL_OFFSET                          (u32)(0x0)
-#define CM1_ABE_CLKCTRL_MASK                            (u32)(0x3)
+/*CM1_ABE_MCBSPX&TIMERX_CLKCTRL*/
+#define CM1_ABE_CLKCTRL_OFFSET		(u32)(0x0)
+#define CM1_ABE_CLKCTRL_MASK		(u32)(0x3)
 
-/******************CM1_L4PER_CLKSTCTRL************/
+/*CM1_L4PER_CLKSTCTRL*/
 
-#define CM1_L4PER_CLKSTCTRL_Transition_OFFSET             (u32)(0x0)
-#define CM1_L4PER_CLKSTCTRL_Transition_MASK               (u32)(0x3)
+#define CM1_L4PER_CLKSTCTRL_Transition_OFFSET	(u32)(0x0)
+#define CM1_L4PER_CLKSTCTRL_Transition_MASK	(u32)(0x3)
 
-/******************CM1_L4PER_MCBSPX&DMTIMERX_CLKCTRL*/
-#define CM1_L4PER_CLKCTRL_OFFSET                          (u32)(0x0)
-#define CM1_L4PER_CLKCTRL_MASK                            (u32)(0x3)
+/*CM1_L4PER_MCBSPX&DMTIMERX_CLKCTRL*/
+#define CM1_L4PER_CLKCTRL_OFFSET	(u32)(0x0)
+#define CM1_L4PER_CLKCTRL_MASK		(u32)(0x3)
 
-/******************CM_IVA_DVFS_PERF*************/
-#define CM_IVA_DVFS_PERF_OFFSET                         (u32)(0x0)
-#define CM_IVA_DVFS_PERF_MASK                           (u32)(0xFF)
-
-/*****************************************************************************
-* EXPORTED TYPES
-******************************************************************************
-*/
+/*CM_IVA_DVFS_PERF*/
+#define CM_IVA_DVFS_PERF_OFFSET		(u32)(0x0)
+#define CM_IVA_DVFS_PERF_MASK		(u32)(0xFF)
 
 /* The following type definitions represent the 
 * enumerated values for each bitfield 
diff --git a/drivers/dsp/bridge/hw/PRCMRegAcM.h b/drivers/dsp/bridge/hw/PRCMRegAcM.h
index 58d2b6117abc..b811377d7da5 100644
--- a/drivers/dsp/bridge/hw/PRCMRegAcM.h
+++ b/drivers/dsp/bridge/hw/PRCMRegAcM.h
@@ -667,12 +667,11 @@
       PRCM_PM_PWSTST_IVA2_PowerStateSt_OFFSET))
 
 #else
-/********************************************************************/
 
 #define PRM_TESLA_PWRSTCTRLReadRegister32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_PM_TESLA_PWRSTCTRL_OFFSET))
 
-/********************************************************************/
+
 
 #define PRM_TESLA_PWRSTCTRLWriteON32(baseAddress)\
 {\
@@ -685,7 +684,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
 }
 
-/********************************************************************/
 
 #define PRM_TESLA_PWRSTCTRLWriteINACTIVE32(baseAddress)\
 {\
@@ -698,7 +696,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
 }
 
-/********************************************************************/
 
 #define PRM_TESLA_PWRSTCTRLWriteRET32(baseAddress)\
 {\
@@ -711,7 +708,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
 }
 
-/********************************************************************/
 
 #define PRM_TESLA_PWRSTCTRLWriteOFF32(baseAddress)\
 {\
@@ -724,7 +720,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
 }
 
-/********************************************************************/
 
 #define PRM_TESLA_PWRSTCTRLWriteLOGICRETSTATE32(baseAddress, value)\
 {\
@@ -739,7 +734,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
 
 #define PRM_TESLA_PWRSTCTRLWriteL1RETSTATE32(baseAddress, value)\
 {\
@@ -754,7 +748,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
 
 #define PRM_TESLA_PWRSTCTRLWriteL2RETSTATE32(baseAddress, value)\
 {\
@@ -770,21 +763,16 @@
 }
 
 
-/********************************************************************/
-
 
 #define PRM_TESLA_PWRSTSTReadRegister32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_PM_TESLA_PWRSTST_OFFSET))
 
-/********************************************************************/
-
 
 #define PRM_TESLA_PWRSTSTGet32(baseAddress)\
 	(((RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_PM_TESLA_PWRSTST_OFFSET))&\
 	PM_TESLA_PWRSTST_PowerState_MASK) >>\
 	PM_TESLA_PWRSTST_PowerState_OFFSET)
 
-/********************************************************************/
 
 #define PRM_CORE_PWRSTCTRLWrite32(baseAddress, value)\
 {\
@@ -815,8 +803,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define PRM_TESLA_RSTCTRL_RST2_Write32(baseAddress, value)\
 {\
 	const u32 offset = PRM_RM_TESLA_RSTCTRL_OFFSET;\
@@ -830,12 +816,10 @@
 }
 
 
-/********************************************************************/
 
 #define PRM_TESLA_RSTSTReadRegister32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_RM_TESLA_RSTST_OFFSET))
 
-/********************************************************************/
 
 #define PRM_TESLA_RSTST_Clear32(baseAddress)\
 {\
@@ -845,12 +829,10 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
 
 #define PRM_TESLA_CONTEXTReadRegister32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_RM_TESLA_TESLA_CONTEXT_OFFSET))
 
-/********************************************************************/
 
 #define PRM_TESLA_CONTEXT_Clear32(baseAddress)\
 {\
@@ -860,15 +842,10 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
-
 #define PRM_WKUP_IVA_ReadRegister32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET))
 
 
-/********************************************************************/
-
 #define PRM_WKUP_IVA_MPU_Write32(baseAddress, value)\
 {\
 	const u32 offset = PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET;\
@@ -881,8 +858,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define PRM_WKUP_IVA_DUCATI_Write32(baseAddress, value)\
 {\
 	const u32 offset = PRM_PM_ALWON_SR_IVA_WKDEP_OFFSET;\
@@ -895,14 +870,10 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define PRM_ALWON_CONTEXTReadRegister32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRM_RM_ALWON_SR_IVA_CONTEXT_OFFSET))
 
 
-/**********************************************************************/
-
 #define CM_CLKSTCTRL_TESLAWriteRegister32(baseAddress, value)\
 {\
 	const u32 offset = CM1_CM_TESLA_CLKSTCTRL_OFFSET;\
@@ -916,8 +887,6 @@
 }
 
 
-/**********************************************************************/
-
 #define CM_TESLA_TESLA_CLKCTRLWriteRegister32(baseAddress, value)\
 {\
 	const u32 offset = CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET;\
@@ -930,16 +899,11 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_TESLA_STBYST_Read32(baseAddress)\
 	(((RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET))&\
 	CM_TESLA_TESLA_CLKCTRL_STBY_MASK) >>\
 	CM_TESLA_TESLA_CLKCTRL_STBY_OFFSET)
 
-/********************************************************************/
-
-
 #define CM_TESLA_IDLEST_Read32(baseAddress)\
 	(((RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM1_CM_TESLA_TESLA_CLKCTRL_OFFSET))&\
 	CM_TESLA_TESLA_CLKCTRL_IDLE_MASK) >>\
@@ -952,8 +916,6 @@
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_PERF_TESLA_OFFSET))
 
 
-/********************************************************************/
-
 #define CM_IVA_DVFS_PERFTESTLA_Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_IVA_DVFS_PERF_TESLA_OFFSET;\
@@ -966,12 +928,9 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_IVA_DVFS_PERFIVAHD_Read32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_PERF_IVAHD_OFFSET))
 
-/********************************************************************/
 
 #define CM_IVA_DVFS_PERFIVAHD_Write32(baseAddress, value)\
 {\
@@ -985,12 +944,10 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
 
 #define CM_IVA_DVFS_PERFABE_Read32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_PERF_ABE_OFFSET))
 
-/********************************************************************/
 
 #define CM_IVA_DVFS_PERFABE_Write32(baseAddress, value)\
 {\
@@ -1004,18 +961,15 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
 
 #define CM_IVA_DVFS_RESULT_Read32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_RESULT_OFFSET))
 
-/********************************************************************/
 
 #define CM_IVA_DVFS_CURRENT_Read32(baseAddress)\
 	(RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM2_CM_IVA_DVFS_CURRENT_OFFSET))
 
 
-/**********************************************************************/
 
 #define CM_CLKSTCTRL_ABEWriteRegister32(baseAddress, value)\
 {\
@@ -1029,7 +983,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
 
 #define CM_ABEEN_MCBSP1Write32(baseAddress, value)\
 {\
@@ -1043,7 +996,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
 
 
 #define CM_ABEEN_MCBSP2Write32(baseAddress, value)\
@@ -1058,9 +1010,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
-
 #define CM_ABEEN_MCBSP3Write32(baseAddress, value)\
 {\
 	const u32 offset = CM1_CM1_ABE_MCBSP3_CLKCTRL_OFFSET;\
@@ -1073,8 +1022,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_ABEEN_TIMER5Write32(baseAddress, value)\
 {\
 	const u32 offset = CM1_CM1_ABE_TIMER5_CLKCTRL_OFFSET;\
@@ -1087,8 +1034,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_ABEEN_TIMER6Write32(baseAddress, value)\
 {\
 	const u32 offset = CM1_CM1_ABE_TIMER6_CLKCTRL_OFFSET;\
@@ -1101,8 +1046,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_ABEEN_TIMER7Write32(baseAddress, value)\
 {\
 	const u32 offset = CM1_CM1_ABE_TIMER7_CLKCTRL_OFFSET;\
@@ -1115,8 +1058,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_ABEEN_TIMER8Write32(baseAddress, value)\
 {\
 	const u32 offset = CM1_CM1_ABE_TIMER8_CLKCTRL_OFFSET;\
@@ -1129,8 +1070,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/**********************************************************************/
-
 #define CM_CLKSTCTRL_L4PERWriteRegister32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_CLKSTCTRL_OFFSET;\
@@ -1143,8 +1082,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_L4PEREN_MCBSP4Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_MCBSP4_CLKCTRL_OFFSET;\
@@ -1157,8 +1094,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_L4PEREN_MCBSP5Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_MCBSP5_CLKCTRL_OFFSET;\
@@ -1171,8 +1106,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_L4PEREN_DMTIMER2Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET;\
@@ -1185,8 +1118,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_L4PEREN_DMTIMER3Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET;\
@@ -1199,8 +1130,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_L4PEREN_DMTIMER4Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET;\
@@ -1213,8 +1142,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_L4PEREN_DMTIMER9Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET;\
@@ -1227,8 +1154,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_L4PEREN_DMTIMER10Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET;\
@@ -1241,8 +1166,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
-
 #define CM_L4PEREN_DMTIMER11Write32(baseAddress, value)\
 {\
 	const u32 offset = CM2_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET;\
@@ -1255,7 +1178,6 @@
 	WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
 }
 
-/********************************************************************/
 
 
 #endif
diff --git a/drivers/dsp/bridge/hw/hw_prcm.c b/drivers/dsp/bridge/hw/hw_prcm.c
index 55a2592bbba9..25c196af3eca 100644
--- a/drivers/dsp/bridge/hw/hw_prcm.c
+++ b/drivers/dsp/bridge/hw/hw_prcm.c
@@ -29,11 +29,11 @@
 #include <hw_defs.h>
 #include <hw_prcm.h>
 
-#ifdef OMAP_3430
+
 
 static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
-				    enum HW_RstModule_t r,
-				    enum HW_SetClear_t val);
+				enum HW_RstModule_t r,
+				enum HW_SetClear_t val);
 
 HW_STATUS HW_RST_Reset(const void __iomem *baseAddress, enum HW_RstModule_t r)
 {
@@ -46,28 +46,38 @@ HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress, enum HW_RstModule_t r)
 }
 
 static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
-				    enum HW_RstModule_t r,
-				    enum HW_SetClear_t val)
+				enum HW_RstModule_t r,
+				enum HW_SetClear_t val)
 {
 	HW_STATUS status = RET_OK;
 
 	switch (r) {
+#ifdef OMAP44XX
+	case HW_RST1_TESLA:
+		PRM_TESLA_RSTCTRL_RST1_Write32(baseAddress, val);
+		break;
+	case HW_RST2_TESLA:
+		PRM_TESLA_RSTCTRL_RST2_Write32(baseAddress, val);
+		break;
+#else
 	case HW_RST1_IVA2:
-	    PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, val);
-	    break;
+		PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, val);
+		break;
 	case HW_RST2_IVA2:
-	    PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, val);
-	    break;
+		PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, val);
+		break;
 	case HW_RST3_IVA2:
-	    PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, val);
-	    break;
+		PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, val);
+		break;
+#endif
 	default:
-	    status = RET_FAIL;
-	    break;
+		status = RET_FAIL;
+		break;
 	}
 	return status;
 }
 
+#ifdef OMAP_3430
 HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
 		enum HW_PwrModule_t p, enum HW_PwrState_t *value)
 {
@@ -83,7 +93,6 @@ HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
 				(baseAddress);
 
 		} while (temp);
-
 		temp = PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress);
 		*value = PRCMPM_PWSTST_IVA2PowerStateStGet32(temp);
 		break;
@@ -147,13 +156,18 @@ HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
 	return status;
 
 }
+#endif
 
 HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
 		enum HW_RstModule_t m, u32 *value)
 {
 	HW_STATUS status = RET_OK;
+#ifdef OMAP44XX
+	*value = PRM_TESLA_RSTSTReadRegister32(baseAddress);
 
+#else
 	*value = PRCMRM_RSTST_DSPReadRegister32(baseAddress);
+#endif
 
 	return status;
 }
@@ -162,21 +176,21 @@ HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
 		enum HW_RstModule_t m, u32 *value)
 {
 	HW_STATUS status = RET_OK;
-
+#ifdef OMAP44XX
+	*value = PRM_TESLA_RSTCTRLReadRegister32(baseAddress);
+#else
 	*value = PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress);
+#endif
+
 
 	return status;
 }
 
-#else
+#ifdef OMAP44XX
+
 static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val);
 static HW_STATUS HW_CLK_AutoIdleWriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val);
-static HW_STATUS HW_RST_WriteVal (const u32 baseAddress, enum HW_RstModule_t r, enum HW_SetClear_t val);
 
-/* ============================================================================
-* EXPORTED FUNCTIONS
-* =============================================================================
-*/
 
 HW_STATUS HW_CLK_Enable(const u32 baseAddress, enum HW_ClkModule_t c)
 {
@@ -196,7 +210,6 @@ static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c,
 	if (val == HW_SET)
 		val_clk = 0x2;
 
-
 	switch (c) {
 	case HW_CLK_TESLA:
 	CM_TESLA_TESLA_CLKCTRLWriteRegister32(baseAddress, val);
@@ -246,6 +259,33 @@ static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c,
 	case HW_CLK_DMTIMER11:
 	CM_L4PEREN_DMTIMER11Write32(baseAddress, val_clk);
 	break;
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+
+HW_STATUS HW_PWRSTCTRL_RegGet(const u32 baseAddress, u32 *value)
+{
+	HW_STATUS status = RET_OK;
+
+	*value = PRM_TESLA_PWRSTCTRLReadRegister32(baseAddress);
+
+	return status;
+}
+
+
+HW_STATUS HW_PWR_PowerStateGet(const u32 baseAddress,
+	enum HW_PwrModule_t p, enum  HW_PwrState_t *value)
+{
+	HW_STATUS status = RET_OK;
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+	*value = (enum HW_PwrState_t)PRM_TESLA_PWRSTSTGet32(baseAddress);
+	break;
 
 	default:
 	status = RET_FAIL;
@@ -255,8 +295,83 @@ static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c,
 	return status;
 }
 
+HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
+	enum HW_PwrModule_t p, enum HW_PwrState_t value)
+{
+	HW_STATUS status = RET_OK;
+
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+		switch (value) {
+		case HW_PWR_STATE_ON:
+		PRM_TESLA_PWRSTCTRLWriteON32(baseAddress);
+		break;
+		case HW_PWR_STATE_INACT:
+		PRM_TESLA_PWRSTCTRLWriteINACTIVE32(baseAddress);
+		break;
+		case HW_PWR_STATE_RET:
+		PRM_TESLA_PWRSTCTRLWriteRET32(baseAddress);
+		break;
+		case HW_PWR_STATE_OFF:
+		PRM_TESLA_PWRSTCTRLWriteOFF32(baseAddress);
+		break;
+		default:
+		status = RET_FAIL;
+		break;
+		}
+	break;
+	case HW_PWR_DOMAIN_CORE:
+		switch (value) {
+		case HW_PWR_STATE_ON:
+		case HW_PWR_STATE_INACT:
+		case HW_PWR_STATE_RET:
+		case HW_PWR_STATE_OFF:
+		PRM_CORE_PWRSTCTRLWrite32(baseAddress, value);
+		break;
+		default:
+		status = RET_FAIL;
+		break;
+		}
+	break;
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
 
+HW_STATUS HW_PWR_ForceStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
+	enum HW_TransitionState_t value)
+{
+	HW_STATUS status = RET_OK;
 
+	switch (p) {
+	case HW_PWR_DOMAIN_TESLA:
+	CM_CLKSTCTRL_TESLAWriteRegister32(baseAddress, value);
+	break;
+	case HW_PWR_DOMAIN_ABE:
+	CM_CLKSTCTRL_ABEWriteRegister32(baseAddress, value);
+	break;
+	case HW_PWR_DOMAIN_L4PER:
+	CM_CLKSTCTRL_L4PERWriteRegister32(baseAddress, value);
+	break;
+	default:
+	status = RET_FAIL;
+	break;
+	}
+
+	return status;
+}
+
+
+#endif
+
+
+
+
+
+#if 0
 HW_STATUS HW_CLK_AutoIdleEnable(const u32 baseAddress, enum HW_ClkModule_t c)
 {
 	return HW_CLK_AutoIdleWriteVal(baseAddress, c, HW_SET);
@@ -321,6 +436,7 @@ HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, u32 *value)
 	return status;
 }
 
+
 static HW_STATUS HW_RST_WriteVal(const u32 baseAddress, enum HW_RstModule_t p,
 				enum HW_SetClear_t value)
 {
@@ -342,16 +458,18 @@ static HW_STATUS HW_RST_WriteVal(const u32 baseAddress, enum HW_RstModule_t p,
 	return status;
 }
 
+
 HW_STATUS HW_RSTST_RegGet (const u32 baseAddress, u32 *value)
 {
 	HW_STATUS status = RET_OK;
 
-	*value = PRM_TESLA_RSTSTReadRegister32(baseAddress);
+
 
 	return status;
 }
 
 
+
 HW_STATUS HW_RSTST_RegClear (const u32 baseAddress)
 {
 	HW_STATUS status = RET_OK;
@@ -362,77 +480,7 @@ HW_STATUS HW_RSTST_RegClear (const u32 baseAddress)
 }
 
 
-HW_STATUS HW_PWRSTCTRL_RegGet(const u32 baseAddress, u32 *value)
-{
-	HW_STATUS status = RET_OK;
 
-	*value = PRM_TESLA_PWRSTCTRLReadRegister32(baseAddress);
-
-	return status;
-}
-
-HW_STATUS HW_PWR_PowerStateGet(const u32 baseAddress,
-	enum HW_PwrModule_t p, enum  HW_PwrState_t *value)
-{
-	HW_STATUS status = RET_OK;
-	switch (p) {
-	case HW_PWR_DOMAIN_TESLA:
-	*value = (enum HW_PwrState_t)PRM_TESLA_PWRSTSTGet32(baseAddress);
-	break;
-
-	default:
-	status = RET_FAIL;
-	break;
-	}
-
-	return status;
-}
-
-HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
-	enum HW_PwrModule_t p, enum HW_PwrState_t value)
-{
-	HW_STATUS status = RET_OK;
-
-	switch (p) {
-	case HW_PWR_DOMAIN_TESLA:
-		switch (value) {
-		case HW_PWR_STATE_ON:
-		PRM_TESLA_PWRSTCTRLWriteON32(baseAddress);
-		break;
-		case HW_PWR_STATE_INACT:
-		PRM_TESLA_PWRSTCTRLWriteINACTIVE32(baseAddress);
-		break;
-		case HW_PWR_STATE_RET:
-		PRM_TESLA_PWRSTCTRLWriteRET32(baseAddress);
-		break;
-		case HW_PWR_STATE_OFF:
-		PRM_TESLA_PWRSTCTRLWriteOFF32(baseAddress);
-		break;
-		default:
-		status = RET_FAIL;
-		break;
-		}
-	break;
-	case HW_PWR_DOMAIN_CORE:
-		switch (value) {
-		case HW_PWR_STATE_ON:
-		case HW_PWR_STATE_INACT:
-		case HW_PWR_STATE_RET:
-		case HW_PWR_STATE_OFF:
-		PRM_CORE_PWRSTCTRLWrite32(baseAddress, value);
-		break;
-		default:
-		status = RET_FAIL;
-		break;
-		}
-	break;
-	default:
-	status = RET_FAIL;
-	break;
-	}
-
-	return status;
-}
 
 
 HW_STATUS HW_PWR_RetentionStateSet(const u32 baseAddress,
@@ -467,6 +515,7 @@ HW_STATUS HW_PWR_RetentionStateSet(const u32 baseAddress,
 }
 
 
+
 HW_STATUS HW_PWRST_RegGet(const u32 baseAddress, enum HW_PwrModule_t p, u32 *value)
 {
 	HW_STATUS status = RET_OK;
@@ -492,6 +541,7 @@ HW_STATUS HW_PWR_WkupDependency_RegGet(const u32 baseAddress, u32 *value)
 	return status;
 }
 
+
 HW_STATUS HW_PWR_WkupDependencySet(const u32 baseAddress, enum HW_PwrModule_t p,
 	enum HW_WeakUpDep_t src, enum HW_SetClear_t value)
 {
@@ -519,28 +569,7 @@ HW_STATUS HW_PWR_WkupDependencySet(const u32 baseAddress, enum HW_PwrModule_t p,
 	return status;
 }
 
-HW_STATUS HW_PWR_ForceStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
-	enum HW_PWR_TransState_t value)
-{
-	HW_STATUS status = RET_OK;
-
-	switch (p) {
-	case HW_PWR_DOMAIN_TESLA:
-	CM_CLKSTCTRL_TESLAWriteRegister32(baseAddress, value);
-	break;
-	case HW_PWR_DOMAIN_ABE:
-	CM_CLKSTCTRL_ABEWriteRegister32(baseAddress, value);
-	break;
-	case HW_PWR_DOMAIN_L4PER:
-	CM_CLKSTCTRL_L4PERWriteRegister32(baseAddress, value);
-	break;
-	default:
-	status = RET_FAIL;
-	break;
-	}
 
-	return status;
-}
 
 
 HW_STATUS HW_TESLA_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
@@ -562,6 +591,7 @@ HW_STATUS HW_TESLA_CONTEXT_ClrSet(const u32 baseAddress)
 }
 
 
+
 HW_STATUS HW_ALWON_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
 {
 	HW_STATUS status = RET_OK;
@@ -572,6 +602,7 @@ HW_STATUS HW_ALWON_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
 }
 
 
+
 HW_STATUS HW_IVA_DVFSSet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 value)
 {
 	HW_STATUS status = RET_OK;
diff --git a/drivers/dsp/bridge/hw/hw_prcm.h b/drivers/dsp/bridge/hw/hw_prcm.h
index 5508eba3a5d8..61cace2b0355 100644
--- a/drivers/dsp/bridge/hw/hw_prcm.h
+++ b/drivers/dsp/bridge/hw/hw_prcm.h
@@ -29,146 +29,8 @@
 
 /* HW_ClkModule:  Enumerated Type used to specify the clock domain */
 
-#ifdef OMAP_3430
-enum HW_ClkModule_t {
-/* DSP Domain */
-    HW_CLK_DSP_CPU,
-    HW_CLK_DSP_IPI_MMU,
-    HW_CLK_IVA_ARM,
-    HW_CLK_IVA_COP,	/* IVA Coprocessor */
-
-/* Core Domain */
-    HW_CLK_FN_WDT4,	/* Functional Clock */
-    HW_CLK_FN_WDT3,
-    HW_CLK_FN_UART2,
-    HW_CLK_FN_UART1,
-    HW_CLK_GPT5,
-    HW_CLK_GPT6,
-    HW_CLK_GPT7,
-    HW_CLK_GPT8,
-
-    HW_CLK_IF_WDT4,	/* Interface Clock */
-    HW_CLK_IF_WDT3,
-    HW_CLK_IF_UART2,
-    HW_CLK_IF_UART1,
-    HW_CLK_IF_MBOX
-
-} ;
-
-enum HW_ClkSubsys_t {
-    HW_CLK_DSPSS,
-    HW_CLK_IVASS
-} ;
-
-/* HW_GPtimers:  General purpose timers */
-enum HW_GPtimer_t {
-    HW_GPT5 = 5,
-    HW_GPT6 = 6,
-    HW_GPT7 = 7,
-    HW_GPT8 = 8
-} ;
-
-
-/* GP timers Input clock type:  General purpose timers */
-enum HW_Clocktype_t {
-    HW_CLK_32KHz = 0,
-    HW_CLK_SYS   = 1,
-    HW_CLK_EXT   = 2
-} ;
-
-/* HW_ClkDiv:  Clock divisors */
-enum HW_ClkDiv_t {
-    HW_CLK_DIV_1 = 0x1,
-    HW_CLK_DIV_2 = 0x2,
-    HW_CLK_DIV_3 = 0x3,
-    HW_CLK_DIV_4 = 0x4,
-    HW_CLK_DIV_6 = 0x6,
-    HW_CLK_DIV_8 = 0x8,
-    HW_CLK_DIV_12 = 0xC
-} ;
-
-/* HW_RstModule:  Enumerated Type used to specify the module to be reset */
-enum HW_RstModule_t {
-    HW_RST1_IVA2,  /* Reset the DSP */
-    HW_RST2_IVA2,  /* Reset MMU and LEON HWa */
-    HW_RST3_IVA2   /* Reset LEON sequencer */
-} ;
-
-/* HW_PwrModule:  Enumerated Type used to specify the power domain */
-enum HW_PwrModule_t {
-/* Domains */
-    HW_PWR_DOMAIN_CORE,
-    HW_PWR_DOMAIN_MPU,
-    HW_PWR_DOMAIN_WAKEUP,
-    HW_PWR_DOMAIN_DSP,
-
-/* Sub-domains */
-    HW_PWR_DSP_IPI,	/* IPI = Intrusive Port Interface */
-    HW_PWR_IVA_ISP	 /* ISP = Intrusive Slave Port */
-} ;
-
-enum HW_PwrState_t {
-    HW_PWR_STATE_OFF,
-    HW_PWR_STATE_RET,
-    HW_PWR_STATE_INACT,
-    HW_PWR_STATE_ON = 3
-} ;
-
-enum HW_ForceState_t {
-    HW_FORCE_OFF,
-    HW_FORCE_ON
-} ;
-
-enum HW_IdleState_t {
-    HW_ACTIVE,
-    HW_STANDBY
-
-} ;
-
-enum HW_TransitionState_t {
-    HW_AUTOTRANS_DIS,
-    HW_SW_SUP_SLEEP,
-    HW_SW_SUP_WAKEUP,
-    HW_AUTOTRANS_EN
-} ;
-
-
-extern HW_STATUS HW_RST_Reset(const void __iomem *baseAddress,
-				 enum HW_RstModule_t r);
-
-extern HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress,
-				   enum HW_RstModule_t r);
-
-extern HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
-					     enum HW_RstModule_t p,
-					     u32 *value);
-extern HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
-					   enum HW_RstModule_t p, u32 *value);
-
-extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
-						enum HW_PwrModule_t p,
-						enum HW_PwrState_t value);
-
-extern HW_STATUS HW_CLK_SetInputClock(const u32 baseAddress,
-					enum HW_GPtimer_t gpt,
-					enum HW_Clocktype_t c);
-
-extern HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
-					enum HW_PwrModule_t p,
-					enum HW_PwrState_t *value);
-
-extern HW_STATUS HW_PWRST_IVA2RegGet(const void __iomem *baseAddress,
-						u32 *value);
-
-extern HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
-					    enum HW_PwrModule_t p,
-					    enum HW_PwrState_t value);
-
-extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
-					     enum HW_TransitionState_t val);
-#else
 enum HW_ClkModule_t {
-
+#ifdef OMAP44XX
 /*CM1 ABE*/
 	HW_CLK_TESLA,
 	HW_CLK_AESS,
@@ -184,9 +46,7 @@ enum HW_ClkModule_t {
 	HW_CLK_TIMER7,
 	HW_CLK_TIMER8,
 	HW_CLK_WDT3,
-
 /*CM2 L4PER*/
-
 	HW_CLK_DMTIMER2,
 	HW_CLK_DMTIMER3,
 	HW_CLK_DMTIMER4,
@@ -196,54 +56,119 @@ enum HW_ClkModule_t {
 	HW_CLK_MCBSP4,
 	HW_CLK_MCBSP5,
 
+#else
+	/* DSP Domain */
+	HW_CLK_DSP_CPU,
+	HW_CLK_DSP_IPI_MMU,
+	HW_CLK_IVA_ARM,
+	HW_CLK_IVA_COP,	/* IVA Coprocessor */
+
+	/* Core Domain */
+	HW_CLK_FN_WDT4,	/* Functional Clock */
+	HW_CLK_FN_WDT3,
+	HW_CLK_FN_UART2,
+	HW_CLK_FN_UART1,
+	HW_CLK_GPT5,
+	HW_CLK_GPT6,
+	HW_CLK_GPT7,
+	HW_CLK_GPT8,
+
+	HW_CLK_IF_WDT4,	/* Interface Clock */
+	HW_CLK_IF_WDT3,
+	HW_CLK_IF_UART2,
+	HW_CLK_IF_UART1,
+	HW_CLK_IF_MBOX
+#endif
+} ;
 
-};
-
+enum HW_ClkSubsys_t {
+	HW_CLK_DSPSS,
+	HW_CLK_IVASS
+} ;
 
+/* HW_GPtimers:  General purpose timers */
+enum HW_GPtimer_t {
+	HW_GPT5 = 5,
+	HW_GPT6 = 6,
+	HW_GPT7 = 7,
+	HW_GPT8 = 8
+} ;
 
-/* ----------------------------------------------------------------------------
-* TYPE:         HW_RstModule
-*
-* DESCRIPTION:  Enumerated Type used to specify the module to be reset
-*
-* -----------------------------------------------------------------------------
-*/
-enum HW_RstModule_t {
-	HW_RST1_TESLA,  /*Reset the DSP*/
-	HW_RST2_TESLA,  /* Reset MMU */
-};
 
+/* GP timers Input clock type:  General purpose timers */
+enum HW_Clocktype_t {
+	HW_CLK_32KHz = 0,
+	HW_CLK_SYS   = 1,
+	HW_CLK_EXT   = 2
+} ;
 
+/* HW_ClkDiv:  Clock divisors */
+enum HW_ClkDiv_t {
+	HW_CLK_DIV_1 = 0x1,
+	HW_CLK_DIV_2 = 0x2,
+	HW_CLK_DIV_3 = 0x3,
+	HW_CLK_DIV_4 = 0x4,
+	HW_CLK_DIV_6 = 0x6,
+	HW_CLK_DIV_8 = 0x8,
+	HW_CLK_DIV_12 = 0xC
+} ;
 
-/* ----------------------------------------------------------------------------
-* TYPE:         HW_PwrModule
-*
-* DESCRIPTION:  Enumerated Type used to specify the power domain
-*
-* -----------------------------------------------------------------------------
-*/
+/* HW_RstModule:  Enumerated Type used to specify the module to be reset */
+enum HW_RstModule_t {
+#ifdef OMAP44XX
+	HW_RST1_TESLA,	/*Reset the DSP*/
+	HW_RST2_TESLA,	/* Reset MMU */
+#else
+	HW_RST1_IVA2,	/* Reset the DSP */
+	HW_RST2_IVA2,	/* Reset MMU and LEON HWa */
+	HW_RST3_IVA2	/* Reset LEON sequencer */
+#endif
+} ;
 
+/* HW_PwrModule:  Enumerated Type used to specify the power domain */
 enum HW_PwrModule_t {
-/* Domains*/
+/* Domains */
 	HW_PWR_DOMAIN_CORE,
 	HW_PWR_DOMAIN_MPU,
 	HW_PWR_DOMAIN_WAKEUP,
+#ifdef OMAP44XX
 	HW_PWR_DOMAIN_TESLA,
 	HW_PWR_DOMAIN_ABE,
 	HW_PWR_DOMAIN_L4PER,
+#else
+	HW_PWR_DOMAIN_DSP,
+#endif
+
 /* Sub-domains */
-	HW_PWR_DSP_IPI,        /* IPI = Intrusive Port Interface */
-	HW_PWR_IVA_ISP         /* ISP = Intrusive Slave Port*/
+	HW_PWR_DSP_IPI,	/* IPI = Intrusive Port Interface */
+	HW_PWR_IVA_ISP	 /* ISP = Intrusive Slave Port */
 } ;
 
-
 enum HW_PwrState_t {
 	HW_PWR_STATE_OFF,
 	HW_PWR_STATE_RET,
 	HW_PWR_STATE_INACT,
 	HW_PWR_STATE_ON = 3
-};
+} ;
+
+enum HW_ForceState_t {
+	HW_FORCE_OFF,
+	HW_FORCE_ON
+} ;
 
+enum HW_IdleState_t {
+	HW_ACTIVE,
+	HW_STANDBY
+} ;
+
+enum HW_TransitionState_t {
+	HW_AUTOTRANS_DIS,
+	HW_SW_SUP_SLEEP,
+	HW_SW_SUP_WAKEUP,
+	HW_AUTOTRANS_EN
+} ;
+
+#ifdef OMAP44XX
 enum HW_RetState_t {
 	HW_RETSTATE_LOGIC,
 	HW_RETSTATE_L1,
@@ -263,21 +188,51 @@ enum HW_IvaDVFS_t {
 	HW_DVFS_CURRENT
 };
 
-enum HW_PWR_TransState_t {
-	HW_AUTOTRANS_DIS = 0x0,
-	HW_SW_SUP_SLEEP,
-	HW_SW_SUP_WAKEUP,
-	HW_AUTOTRANS_EN
-};
-
 enum HW_IdleStatus_t {
 	HW_TESLA_FULLFUNC = 0x0, /* Module is fully functional, including OCP*/
 	HW_TESLA_TRANSITIONING, /* Transitioning (weakup, sleep or sleep abortion)*/
 	HW_TESLA_IDLE,/* Idle mode(only OCP)*/
 	HW_TESLA_DISABLED/*Module is disabled and cannot be accessed*/
 };
+#endif
+
+extern HW_STATUS HW_RST_Reset(const void __iomem *baseAddress,
+					enum HW_RstModule_t r);
+
+extern HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress,
+					enum HW_RstModule_t r);
+
+extern HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
+					enum HW_RstModule_t p,
+					u32 *value);
+extern HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
+					enum HW_RstModule_t p, u32 *value);
+
+extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
+					enum HW_PwrModule_t p,
+					enum HW_PwrState_t value);
+
+extern HW_STATUS HW_CLK_SetInputClock(const u32 baseAddress,
+					enum HW_GPtimer_t gpt,
+					enum HW_Clocktype_t c);
+
+#ifdef OMAP_3430
+extern HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
+					enum HW_PwrModule_t p,
+					enum HW_PwrState_t *value);
+
+extern HW_STATUS HW_PWRST_IVA2RegGet(const void __iomem *baseAddress,
+						u32 *value);
 
+extern HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
+					    enum HW_PwrModule_t p,
+					    enum HW_PwrState_t value);
 
+extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
+					     enum HW_TransitionState_t val);
+#endif
+
+#ifdef OMAP44XX
 extern HW_STATUS HW_CLK_Enable(const u32 baseAddress,
 				enum HW_ClkModule_t c);
 
@@ -289,20 +244,11 @@ extern HW_STATUS HW_CLK_AutoIdleEnable(const u32 baseAddress,
 
 extern HW_STATUS HW_CLK_AutoIdleDisable(const u32 baseAddress,
 				enum HW_ClkModule_t c);
-
-extern HW_STATUS HW_CLK_StbyStatus(const u32 baseAddress,  enum HW_SetClear_t *stbyState);
-
-extern HW_STATUS HW_CLK_IdleStatus(const u32 baseAddress,  enum HW_IdleStatus_t *idleState);
-
-extern HW_STATUS HW_RST_Reset(const u32 baseAddress,
-				enum HW_RstModule_t r);
-
-extern HW_STATUS HW_RST_UnReset (const u32 baseAddress,
-				enum HW_RstModule_t r);
-
+#if 0
 extern HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, u32 *value);
 
 extern HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, u32 *value);
+#endif
 
 extern HW_STATUS HW_RSTST_RegClear(const u32 baseAddress);
 
@@ -313,33 +259,25 @@ extern HW_STATUS HW_PWR_PowerStateGet(const u32 baseAddress,
 
 extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
 				enum HW_PwrState_t value);
+#if 0
 
 extern HW_STATUS HW_PWR_RetentionStateSet(const u32 baseAddress,
 				enum HW_PwrModule_t p, enum HW_RetState_t src, enum HW_SetClear_t  value);
+#endif
 
 extern HW_STATUS HW_PWRST_RegGet(const u32 baseAddress, enum HW_PwrModule_t p, u32 *value);
 
-extern HW_STATUS HW_PWR_WkupDependency_RegGet(const u32 baseAddress, u32 *value);
-
-extern HW_STATUS HW_PWR_WkupDependencySet(const u32 baseAddress, enum HW_PwrModule_t p,
-				enum HW_WeakUpDep_t src, enum HW_SetClear_t value);
 
 extern HW_STATUS HW_PWR_ForceStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
-				enum HW_PWR_TransState_t value);
+				enum HW_TransitionState_t value);
 
 extern HW_STATUS HW_TESLA_RST_WriteVal(const u32 baseAddress, enum HW_RstModule_t p,
 				enum HW_SetClear_t value);
-
+#if 0
 extern HW_STATUS HW_TESLA_CONTEXT_RegGet(const u32 baseAddress, u32 *value);
 
 extern HW_STATUS HW_TESLA_CONTEXT_ClrSet(const u32 baseAddress);
-
-extern HW_STATUS HW_ALWON_CONTEXT_RegGet(const u32 baseAddress, u32 *value);
-
-extern HW_STATUS HW_IVA_DVFSSet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 value);
-
-extern HW_STATUS HW_IVA_DVFS_RegGet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 *value);
-
+#endif
 
 #endif
 
diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c
index 2d5ab9529690..e6dfd0cc8a15 100755
--- a/drivers/dsp/bridge/wmd/io_sm.c
+++ b/drivers/dsp/bridge/wmd/io_sm.c
@@ -220,17 +220,17 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 	struct CFG_HOSTRES hostRes;
 	struct CFG_DEVNODE *hDevNode;
 	struct CHNL_MGR *hChnlMgr;
-       static int ref_count;
+	static int ref_count;
 	u32 devType;
 
-        struct notify_config ntfy_config;
-        struct notify_tesladrv_config tesla_cfg;
-        struct notify_tesladrv_params params;
-        u32 mem_va;
-        u32 mem_pa;
-        char  driverName[32] = "NOTIFYMBXDRV";
-        int  ntfystatus;
-        irq_handler = (void *) IO_ISR;
+	struct notify_config ntfy_config;
+	struct notify_tesladrv_config tesla_cfg;
+	struct notify_tesladrv_params params;
+	u32 mem_va;
+	u32 mem_pa;
+	char driverName[32] = "NOTIFYMBXDRV";
+	int ntfystatus;
+	irq_handler = (void *) IO_ISR;
 
 
 	/* Check DBC requirements:  */
@@ -256,16 +256,16 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 	if (DSP_FAILED(status))
 		goto func_cont;
 
-    /*
-     *  Create a Single Threaded Work Queue
-     */
+/*
+ *  Create a Single Threaded Work Queue
+ */
 
-       if (ref_count == 0)
-               bridge_workqueue = create_workqueue("bridge_work-queue");
+	if (ref_count == 0)
+		bridge_workqueue = create_workqueue("bridge_work-queue");
 
-       if (bridge_workqueue <= 0)
-               DBG_Trace(DBG_LEVEL1, "Workque Create"
-                       " failed 0x%d \n", bridge_workqueue);
+	if (bridge_workqueue <= 0)
+		DBG_Trace(DBG_LEVEL1, "Workque Create"
+			" failed 0x%d \n", bridge_workqueue);
 
 
 	/* Allocate IO manager object: */
@@ -274,14 +274,14 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 		status = DSP_EMEMORY;
 		goto func_cont;
 	}
-       /*Intializing Work Element*/
-       if (ref_count == 0) {
-               INIT_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM);
-               ref_count = 1;
-       } else
-               PREPARE_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM);
-
-	/* Initialize CHNL_MGR object:    */
+	/*Intializing Work Element*/
+	if (ref_count == 0) {
+		INIT_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM);
+		ref_count = 1;
+	} else
+		PREPARE_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM);
+
+	/* Initialize CHNL_MGR object:*/
 #ifndef DSP_TRACEBUF_DISABLED
 	pIOMgr->pMsg = NULL;
 #endif
@@ -301,50 +301,55 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 		pIOMgr->iQuePowerTail = 0;
 	}
 
-	        notify_get_config(&ntfy_config);
-        ntfystatus = notify_setup(&ntfy_config);
-
-        if (NOTIFY_FAILED(ntfystatus)) {
-                DBG_Trace(DBG_LEVEL7, "Failed notify_setup ntfystatus 0x%x \n",
-                          ntfystatus);
-        } else
-                printk("%s:%d:PASS\n",__func__,__LINE__);
+	notify_get_config(&ntfy_config);
+	ntfystatus = notify_setup(&ntfy_config);
 
-        notify_tesladrv_getconfig(&tesla_cfg);
-
-        ntfystatus = notify_tesladrv_setup(&tesla_cfg);
+	if (ntfystatus != NOTIFY_SUCCESS) {
+		pr_err("Failed notify_setup ntfystatus\n");
+		goto func_cont;
+	}
 
-        notify_tesladrv_params_init(NULL, &params);
+	notify_tesladrv_getconfig(&tesla_cfg);
 
-        mem_va = dma_alloc_coherent(NULL, 0x4000, &mem_pa,GFP_ATOMIC);
-        if (mem_va == NULL)
-                pr_err("Memory allocation for communication failed\n");
-        params.num_events          = 32;
-        params.num_reserved_events  = 0;
-        params.send_event_poll_count = (int) -1;
-        params.recv_int_id          = 26;
-        params.send_int_id          = 55;
-        params.shared_addr_size     = 0x4000;
-        params.shared_addr                = mem_va;
-        params.remote_proc_id         = 0;
+	ntfystatus = notify_tesladrv_setup(&tesla_cfg);
 
-        handle = notify_tesladrv_create(driverName,&params);
-        if (NOTIFY_FAILED(ntfystatus)) {
-                DBG_Trace(DBG_LEVEL7, "Failed notify_get_driver_handle  ntfystatus 0x%x \n",
-                          ntfystatus);
-        } 
+	if (ntfystatus != 0) {
+			pr_err("Failed notify_tesladrv_setup\n");
+			goto func_cont;
+	}
 
-        eventNo = ((NOTIFY_SYSTEM_KEY<<16)|NOTIFY_TESLA_EVENTNUMBER);
+	notify_tesladrv_params_init(NULL, &params);
 
-        ntfystatus = notify_register_event(handle, /*PROC_TESLA*/0, eventNo,(void*)IO_ISR, NULL);
+	mem_va = dma_alloc_coherent(NULL, 0x4000, &mem_pa, GFP_ATOMIC);
+	
+	if (mem_va == NULL)
+		pr_err("Memory allocation for communication failed\n");
+	
+	params.num_events          = 32;
+	params.num_reserved_events  = 0;
+	params.send_event_poll_count = (int) -1;
+	params.recv_int_id          = 26;
+	params.send_int_id          = 55;
+	params.shared_addr_size     = 0x4000;
+	params.shared_addr                = mem_va;
+	params.remote_proc_id         = 0;
+
+	handle = notify_tesladrv_create(driverName, &params);
+	if (handle == NULL) {
+		pr_err("Failed notify_tesladrv_create\n");
+		goto func_cont;
+	}
 
-        if (NOTIFY_FAILED(ntfystatus)) {
-                DBG_Trace(DBG_LEVEL7, "Failed notify_register_event ntfystatus 0x%x \n",
-                          ntfystatus);
-        } 
+	eventNo = ((NOTIFY_SYSTEM_KEY<<16)|NOTIFY_TESLA_EVENTNUMBER);
 
-        notify_disable_event(handle, 0, eventNo);
+	ntfystatus = notify_register_event(handle, /*PROC_TESLA*/0,
+					eventNo, (void *)IO_ISR, NULL);
 
+	if (ntfystatus != NOTIFY_SUCCESS) {
+		pr_err("Failed notify_register_event\n");
+		goto func_cont;
+	}
+	notify_disable_event(handle, 0, eventNo);
 
 	if (DSP_SUCCEEDED(status)) {
 		status = CFG_GetHostResources((struct CFG_DEVNODE *)
@@ -360,19 +365,19 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
 		IO_DisableInterrupt(hWmdContext);
 		if (devType == DSP_UNIT) {
 			/* Plug the channel ISR:. */
-                       if ((request_irq(INT_MAIL_MPU_IRQ, IO_ISR, 0,
-                               "DspBridge\tmailbox", (void *)pIOMgr)) == 0)
-                               status = DSP_SOK;
-                       else
-                               status = DSP_EFAIL;
+			if ((request_irq(INT_MAIL_MPU_IRQ, IO_ISR, 0,
+				"DspBridge\tmailbox", (void *)pIOMgr)) == 0)
+				status = DSP_SOK;
+			else
+				status = DSP_EFAIL;
 		}
 #endif
-       if (DSP_SUCCEEDED(status))
-               DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n",
-                               pIOMgr);
-       else
-               status = CHNL_E_ISR;
-       } else
+		if (DSP_SUCCEEDED(status))
+			DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n",
+				pIOMgr);
+		else
+			status = CHNL_E_ISR;
+	} else
 		status = CHNL_E_ISR;
 func_cont:
 	if (DSP_FAILED(status)) {
@@ -395,23 +400,24 @@ func_cont:
 DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr)
 {
 	DSP_STATUS status = DSP_SOK;
+	u32 notify_status;
 #ifdef OMAP44XX
-	status = notify_tesladrv_delete(&handle);
-        status = notify_tesladrv_destroy();
-        status = notify_destroy();
+	notify_status = notify_tesladrv_delete(&handle);
+	notify_status = notify_tesladrv_destroy();
+	notify_status = notify_destroy();
 #else
 	struct WMD_DEV_CONTEXT *hWmdContext;
 	if (MEM_IsValidHandle(hIOMgr, IO_MGRSIGNATURE)) {
 		/* Unplug IRQ:    */
-               /* Disable interrupts from the board:  */
-               if (DSP_SUCCEEDED(DEV_GetWMDContext(hIOMgr->hDevObject,
-                      &hWmdContext)))
-                               DBC_Assert(hWmdContext);
-               (void)CHNLSM_DisableInterrupt(hWmdContext);
-               destroy_workqueue(bridge_workqueue);
-               /* Linux function to uninstall ISR */
-               free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr);
-               (void)DPC_Destroy(hIOMgr->hDPC);
+		/* Disable interrupts from the board:  */
+		if (DSP_SUCCEEDED(DEV_GetWMDContext(hIOMgr->hDevObject,
+			&hWmdContext)))
+			DBC_Assert(hWmdContext);
+		(void)CHNLSM_DisableInterrupt(hWmdContext);
+		destroy_workqueue(bridge_workqueue);
+		/* uninstall ISR */
+		free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr);
+		(void)DPC_Destroy(hIOMgr->hDPC);
 #ifndef DSP_TRACEBUF_DISABLED
 		if (hIOMgr->pMsg)
 			MEM_Free(hIOMgr->pMsg);
@@ -419,7 +425,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr)
 		SYNC_DeleteCS(hIOMgr->hCSObj); 	/* Leak Fix. */
 		/* Free this IO manager object: */
 		MEM_FreeObject(hIOMgr);
-       } else
+	} else
 		status = DSP_EHANDLE;
 #endif
 	return status;
@@ -626,7 +632,7 @@ func_cont1:
 			 "numBytes %x\n", allBits, paCurr, vaCurr, numBytes);
 		for (i = 0; i < 4; i++) {
 			if ((numBytes >= pgSize[i]) && ((allBits &
-			   (pgSize[i] - 1)) == 0)) {
+				(pgSize[i] - 1)) == 0)) {
 				status = hIOMgr->pIntfFxns->pfnBrdMemMap
 					(hIOMgr->hWmdContext, paCurr, vaCurr,
 					pgSize[i], mapAttrs);
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
index 74d62d905a01..f619b2091301 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -326,21 +326,19 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext)
 		goto error_return;
 
 #ifdef OMAP44XX
-    printk("Disabling Clocks... and resources.dwCm1Base = 0x%x \n  resources.dwCm2Base= 0x%x\n"
+	printk("Disabling Clocks... and resources.dwCm1Base = 0x%x \n  resources.dwCm2Base= 0x%x\n"
 		"resources.dwPrmBase = 0x%x", resources.dwCm1Base, resources.dwCm2Base, resources.dwPrmBase);
-    HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
-    printk("Resetting DSP...");
-    HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
-    printk("Enabling Clocks...");
-    HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
+	HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
+	printk("Resetting DSP...");
+	HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
+	printk("Enabling Clocks...");
+	HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
 
 
-    HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);/*TODO check if it is correct*/
-    HW_RST_Reset(resources.dwPrmBase, HW_RST2_TESLA);/*Just to ensure that the RST's are enabled*/
+	HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);/*TODO check if it is correct*/
+	HW_RST_Reset(resources.dwPrmBase, HW_RST2_TESLA);/*Just to ensure that the RST's are enabled*/
 	HW_RST_UnReset(resources.dwPrmBase, HW_RST2_TESLA);
 
-	printk("Calling the MMU_LOCK BaseValue");
-
 	*((REG_UWORD32 *)((u32)(resources.dwDmmuBase)+0x50)) = 0x400;
 #else
 	
@@ -352,24 +350,16 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext)
 	if ((temp & 0x03) != 0x03 || (temp & 0x03) != 0x02) {
 		/* IVA2 is not in ON state */
 		/* Read and set PM_PWSTCTRL_IVA2  to ON */
-		HW_PWR_PowerStateGet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA,
-				     &pwrState);
-
-		HW_PWR_PowerStateSet(resources.dwPrmBase,
-					  HW_PWR_DOMAIN_TESLA,
-					  HW_PWR_STATE_ON);
-
+		HW_PWR_IVA2StateGet(resources.dwPrmBase, HW_PWR_DOMAIN_DSP,
+					&pwrState);
 		HW_PWR_IVA2PowerStateSet(resources.dwPrmBase,
 					  HW_PWR_DOMAIN_DSP,
 					  HW_PWR_STATE_ON);
 		/* Set the SW supervised state transition */
-
-
-
 		HW_PWR_CLKCTRL_IVA2RegSet(resources.dwCmBase, HW_SW_SUP_WAKEUP);
 		/* Wait until the state has moved to ON */
 		HW_PWR_IVA2StateGet(resources.dwPrmBase, HW_PWR_DOMAIN_DSP,
-				     &pwrState);
+					&pwrState);
 		/* Disable Automatic transition */
 		HW_PWR_CLKCTRL_IVA2RegSet(resources.dwCmBase, HW_AUTOTRANS_DIS);
 	}
@@ -616,6 +606,7 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 #endif
 		/* Let the DSP MMU run */
 		HW_MMU_Enable(resources.dwDmmuBase);
+		(void)CHNLSM_EnableInterrupt(pDevContext);
 
 
 #ifdef OMAP_3430
@@ -768,8 +759,6 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 		 * stale messages */
 		(void)CHNLSM_EnableInterrupt(pDevContext);
 	}
-#else
-		(void)CHNLSM_EnableInterrupt(pDevContext);
 #endif
 	if (DSP_SUCCEEDED(status)) {
 #ifdef OMAP_3430
@@ -780,13 +769,13 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 		DBG_Trace(DBG_LEVEL7, "BRD_Start0: RM_RSTST_DSP = 0x%x \n",
 				temp);
 #else
-        HW_RSTCTRL_RegGet(resources.dwPrmBase, &temp);
-        DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTCTRL_DSP = 0x%x \n",
-                temp);
-        HW_RSTST_RegGet(resources.dwPrmBase, &temp);
-        DBG_Trace(DBG_LEVEL7, "BRD_Start0: RM_RSTST_DSP = 0x%x \n",
-                temp);
-        /* Let DSP go */
+		HW_RSTCTRL_RegGet(resources.dwPrmBase, HW_RST1_TESLA, &temp);
+		DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTCTRL_DSP = 0x%x \n",
+					temp);
+		HW_RSTST_RegGet(resources.dwPrmBase, HW_RST1_TESLA, &temp);
+		DBG_Trace(DBG_LEVEL7, "BRD_Start0: RM_RSTST_DSP = 0x%x \n",
+					temp);
+		/* Let DSP go */
 #endif
 		/* Let DSP go */
 		DBG_Trace(DBG_LEVEL7, "Unreset, WMD_BRD_Start\n");
@@ -796,10 +785,10 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
 		/* release the RST1, DSP starts executing now .. */
 #ifdef OMAP44XX
 		HW_RST_UnReset(resources.dwPrmBase, HW_RST1_TESLA);
-        HW_RSTST_RegGet(resources.dwPrmBase, &temp);
-        DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTST_DSP = 0x%x \n",
-                temp);
-        HW_RSTCTRL_RegGet(resources.dwPrmBase, &temp);
+		HW_RSTST_RegGet(resources.dwPrmBase, HW_RST1_TESLA, &temp);
+		DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTST_DSP = 0x%x \n",
+				temp);
+		HW_RSTCTRL_RegGet(resources.dwPrmBase, HW_RST1_TESLA, &temp);
 #else
 		HW_RST_UnReset(resources.dwPrmBase, HW_RST1_IVA2);
 		HW_RSTST_RegGet(resources.dwPrmBase, HW_RST1_IVA2, &temp);
@@ -890,12 +879,9 @@ static DSP_STATUS WMD_BRD_Stop(struct WMD_DEV_CONTEXT *hDevContext)
 
 #ifdef OMAP44XX
         DBG_Trace(DBG_LEVEL7, "Resetting DSP...");
-        printk("Stop:Disabling Clocks...");
          HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
-         printk("Stop:Resetting DSP...");
          HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
          /*  Enable DSP */
-         printk("Stop:Enabling Clocks...");
          HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
 #else
 	HW_PWRST_IVA2RegGet(resources.dwPrmBase, &dspPwrState);