diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-13 09:57:48 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-13 09:57:48 -0600 |
| commit | fd785c64f3554a15a70a27486f81d38af397feca (patch) | |
| tree | 8fae5e2e99678d6652e6272febf95f7571b09d54 /drivers | |
| parent | 0dfa6f6e68858e8a7a22cde98e2c0866c29cc9eb (diff) | |
| parent | 65ace9a85fa7f88aec4d9d842061108161fa47bc (diff) | |
Merge branch 'remotes/lorenzo/pci/mediatek'
- Assert PERST# for 100ms to allow power and clock to stabilize (qizhong
cheng)
* remotes/lorenzo/pci/mediatek:
PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/controller/pcie-mediatek.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 2f3f974977a3..b18935e8da89 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) */ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should + * be delayed 100ms (TPVPERL) for the power and clock to become stable. + */ + msleep(100); + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ val = readl(port->base + PCIE_RST_CTRL); val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | |