diff options
| author | Misael Lopez Cruz <misael.lopez@ti.com> | 2012-08-14 17:15:10 +0200 |
|---|---|---|
| committer | Andy Green <andy.green@linaro.org> | 2012-09-07 13:06:15 +0800 |
| commit | 927fac729155015bdedb3bc05df1d40e5071a225 (patch) | |
| tree | fb9f665cb594846826df91b437a2b942c9b607a3 /drivers | |
| parent | 33a9324ad147bf3d7cdac7ce34d5d12cb313ebb7 (diff) | |
MFD: twl6040-codec: Implement PDMCLK cold temp errata
No PDM clock output is generated when operating in cold temperatures.
The suggested workaround consists of resetting LPPLL and HPPLL after
Sleep/Deep-Sleep mode transitions, before entering in application
mode.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Sebastien Jan <s-jan@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mfd/twl6040-core.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/mfd/twl6040-core.c b/drivers/mfd/twl6040-core.c index ea5a97d791e3..51ef1b2b2c38 100644 --- a/drivers/mfd/twl6040-core.c +++ b/drivers/mfd/twl6040-core.c @@ -270,6 +270,20 @@ int twl6040_power(struct twl6040 *twl6040, int on) goto out; } } + + /* Errata: PDMCLK can fail to generate at cold temperatures + * The workaround consists of resetting HPPLL and LPPLL + * after Sleep/Deep-Sleep mode and before application mode. + */ + twl6040_set_bits(twl6040, TWL6040_REG_HPPLLCTL, + TWL6040_HPLLRST); + twl6040_clear_bits(twl6040, TWL6040_REG_HPPLLCTL, + TWL6040_HPLLRST); + twl6040_set_bits(twl6040, TWL6040_REG_LPPLLCTL, + TWL6040_LPLLRST); + twl6040_clear_bits(twl6040, TWL6040_REG_LPPLLCTL, + TWL6040_LPLLRST); + /* Default PLL configuration after power up */ twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; twl6040->sysclk = 19200000; |