diff options
| author | Sebastien Jan <s-jan@ti.com> | 2012-01-06 15:33:24 +0100 |
|---|---|---|
| committer | Sebastien Jan <s-jan@ti.com> | 2012-01-06 16:15:32 +0100 |
| commit | 68ae5192ee832c42b3303aa5995312be8187a86c (patch) | |
| tree | 676dba81e2b3d635d17ae507ad2321e05b80e18b /drivers | |
| parent | afb8d19cc67621bf2093389ac40da8f1b533d810 (diff) | |
ipu-pm: clean and adapt clock set to new framework
(this patch enables camera support through Ducati/syslink/omx)
Now that clock framework is available and supports aux clk diviser
configuration, use the framework dedicated function.
Also remove the parent change (not sure why this was done, but it does
not seem to be an issue to remove that). Anyway it was broken with the
aux_clk diviser support patch:
ad03f1cb2d44257afa63a2171e84daad931c48cb
OMAP4: clock data: Add missing divider selection for auxclks
Signed-off-by: Sebastien Jan <s-jan@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/dsp/syslink/ipu_pm/ipu_pm.c | 33 |
1 files changed, 7 insertions, 26 deletions
diff --git a/drivers/dsp/syslink/ipu_pm/ipu_pm.c b/drivers/dsp/syslink/ipu_pm/ipu_pm.c index 2f0da6d6ff35..4ea14a018533 100644 --- a/drivers/dsp/syslink/ipu_pm/ipu_pm.c +++ b/drivers/dsp/syslink/ipu_pm/ipu_pm.c @@ -1101,7 +1101,6 @@ static inline int ipu_pm_get_aux_clk(struct ipu_pm_object *handle, struct rcb_block *rcb_p, struct ipu_pm_params *params) { - u32 a_clk = 0; int ret; int pm_aux_clk_num; @@ -1116,7 +1115,6 @@ static inline int ipu_pm_get_aux_clk(struct ipu_pm_object *handle, if (AUX_CLK_USE_MASK & (1 << pm_aux_clk_num)) { struct clk *aux_clk; - struct clk *aux_clk_src_ptr; aux_clk = clk_get(NULL, aux_clk_name[pm_aux_clk_num]); if (!aux_clk) { @@ -1131,31 +1129,14 @@ static inline int ipu_pm_get_aux_clk(struct ipu_pm_object *handle, aux_clk->usecount); } - aux_clk_src_ptr = clk_get(NULL, - aux_clk_source_name[PER_DPLL_CLK]); - if (!aux_clk_src_ptr) { - pr_err("%s %d Unable to get aux_clk source %s\n" - , __func__, __LINE__ - , aux_clk_source_name[PER_DPLL_CLK]); - return PM_NO_AUX_CLK; - } - ret = clk_set_parent(aux_clk, aux_clk_src_ptr); - if (ret) { - pr_err("%s %d Unable to set clk %s" - " as parent of aux_clk %s\n" - , __func__, __LINE__ - , aux_clk_source_name[PER_DPLL_CLK] - , aux_clk_name[pm_aux_clk_num]); - return PM_NO_AUX_CLK; - } + if (clk_set_rate(aux_clk, + clk_round_rate(aux_clk, 24000000))) { + pr_err("%s %d Unable to set %s clk rate\n", + __func__, __LINE__, + aux_clk_name[pm_aux_clk_num]); - /* update divisor manually until API available */ - a_clk = __raw_readl(AUX_CLK_REG(pm_aux_clk_num)); - MASK_CLEAR_FIELD(a_clk, AUX_CLK_CLKDIV); - MASK_SET_FIELD(a_clk, AUX_CLK_CLKDIV, 0xA); - - /* Enable and configure aux clock */ - __raw_writel(a_clk, AUX_CLK_REG(pm_aux_clk_num)); + return -EINVAL; + } ret = clk_enable(aux_clk); if (ret) { |