diff options
| author | Ingo Molnar <mingo@elte.hu> | 2008-07-30 19:33:48 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-30 19:33:48 +0200 |
| commit | 15dd859cacf312f606f54502d1f66537a1e5c78c (patch) | |
| tree | e50e125eaa6da83fa715704e53c1bde013d1ef8e /include/asm-arm/cacheflush.h | |
| parent | b2d9d33412b9d13a40cd314d93ab517950fc5950 (diff) | |
| parent | 6e86841d05f371b5b9b86ce76c02aaee83352298 (diff) | |
Merge commit 'v2.6.27-rc1' into x86/core
Conflicts:
include/asm-x86/dma-mapping.h
include/asm-x86/namei.h
include/asm-x86/uaccess.h
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-arm/cacheflush.h')
| -rw-r--r-- | include/asm-arm/cacheflush.h | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 70b0fe724b62..e68a1cbcc852 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -424,9 +424,9 @@ static inline void flush_anon_page(struct vm_area_struct *vma, } #define flush_dcache_mmap_lock(mapping) \ - write_lock_irq(&(mapping)->tree_lock) + spin_lock_irq(&(mapping)->tree_lock) #define flush_dcache_mmap_unlock(mapping) \ - write_unlock_irq(&(mapping)->tree_lock) + spin_unlock_irq(&(mapping)->tree_lock) #define flush_icache_user_range(vma,page,addr,len) \ flush_dcache_page(page) @@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, #define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0) #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) - +/* + * VIVT caches only + */ #define cache_is_vivt() 1 #define cache_is_vipt() 0 #define cache_is_vipt_nonaliasing() 0 #define cache_is_vipt_aliasing() 0 #define icache_is_vivt_asid_tagged() 0 -#elif defined(CONFIG_CPU_CACHE_VIPT) - +#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT) +/* + * VIPT caches only + */ #define cache_is_vivt() 0 #define cache_is_vipt() 1 #define cache_is_vipt_nonaliasing() \ @@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, }) #else - +/* + * VIVT or VIPT caches. Note that this is unreliable since ARM926 + * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test. + * There's no way to tell from the CacheType register what type (!) + * the cache is. + */ #define cache_is_vivt() \ ({ \ unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ |