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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 23:46:15 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 23:46:15 +0100
commit49a89efbbbcc178a39555c43bd59a7593c429664 (patch)
tree93ab78ec340d3f2fe23f9f853edd0bd62dcc64bb /include/asm-mips/mach-pnx8550
parent10cc3529072d5415fb040018a8a99aa7a60190b6 (diff)
[MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-pnx8550')
-rw-r--r--include/asm-mips/mach-pnx8550/kernel-entry-init.h24
1 files changed, 12 insertions, 12 deletions
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
index 57102fa9da51..982079f410b5 100644
--- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h
+++ b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
@@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated:
icache_invd_loop:
/* 9 == register t1 */
- .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
- (0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */
- .word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
- (1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */
+ .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
+ (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
+ .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
+ (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
@@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated:
dcache_wbinvd_loop:
/* 9 == register t1 */
- .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
- (0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */
- .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
- (1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */
- .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
- (2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */
- .word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
- (3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */
+ .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+ (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
+ .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+ (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
+ .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+ (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
+ .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+ (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */