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authorRalf Baechle <ralf@linux-mips.org>2007-08-06 16:35:23 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-08-27 02:16:55 +0100
commitfe56b954eadefb8b93b7d6b9244af38a352c8799 (patch)
tree9a39ce014e6e3e05534535ef872732f857a030d1 /include/asm-mips/smtc.h
parent45a98eb2b775caa3d6113cb7a5c2ff4361e09c91 (diff)
[MIPS] SMTC: Move MIPS_CPU_IPI_IRQ definition into header.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/smtc.h')
-rw-r--r--include/asm-mips/smtc.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 44dfa4adecf3..ff3e8936b493 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
#define PARKED_INDEX ((unsigned int)0x80000000)
+/*
+ * Define low-level interrupt mask for IPIs, if necessary.
+ * By default, use SW interrupt 1, which requires no external
+ * hardware support, but which works only for single-core
+ * MIPS MT systems.
+ */
+#ifndef MIPS_CPU_IPI_IRQ
+#define MIPS_CPU_IPI_IRQ 1
+#endif
+
#endif /* _ASM_SMTC_MT_H */