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authorYinghai Lu <Yinghai.Lu@Sun.COM>2008-02-19 03:21:20 -0800
committerIngo Molnar <mingo@elte.hu>2008-04-23 09:01:23 +0200
commitb74d07c05a041482dfacc649203ac1d62ef068f6 (patch)
tree71fd416c6f351efa326ce147b772a79f1d4ce0c3 /include/asm-x86/topology.h
parent246330db3c87db0a7ef8eced160ed09ecc1c7dcb (diff)
x86: multi pci root bus with different io resource range, on 64-bit
scan AMD opteron io/mmio routing to make sure every pci root bus get correct resource range. So later pci scan could assign correct resource to device with unassigned resource. this some kind make up for system without _CRS for multi pci root bus. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/asm-x86/topology.h')
-rw-r--r--include/asm-x86/topology.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
index 4793ae745a78..0e6d6b03affe 100644
--- a/include/asm-x86/topology.h
+++ b/include/asm-x86/topology.h
@@ -193,6 +193,9 @@ extern cpumask_t cpu_coregroup_map(int cpu);
#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
#endif
+struct pci_bus;
+void set_pci_bus_resources_arch_default(struct pci_bus *b);
+
#ifdef CONFIG_SMP
#define mc_capable() (boot_cpu_data.x86_max_cores > 1)
#define smt_capable() (smp_num_siblings > 1)