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authorStephen Boyd <sboyd@kernel.org>2018-03-19 13:41:56 -0700
committerStephen Boyd <sboyd@kernel.org>2018-03-19 13:41:56 -0700
commitdd1137fe794ee80119165d05bb683f9a0783838b (patch)
tree04d79fae23c6e56751c7865c35a914c0deda3053 /include/dt-bindings
parent0805408e47841628cf0f27b656471d695b1d77c9 (diff)
parent9cb12501f38f924567ea7ba10041d32ecd7bf809 (diff)
Merge branch 'clk-mediatek' into clk-next
* clk-mediatek: dt-bindings: clock: mediatek: add audsys support for MT2701 dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device clk: mediatek: update missing clock data for MT7622 audsys clk: mediatek: fix PWM clock source by adding a fixed-factor clock dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/mt2701-clk.h3
-rw-r--r--include/dt-bindings/clock/mt7622-clk.h3
2 files changed, 4 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
index 551f7600ab58..24e93dfcee9f 100644
--- a/include/dt-bindings/clock/mt2701-clk.h
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -176,7 +176,8 @@
#define CLK_TOP_AUD_EXT1 156
#define CLK_TOP_AUD_EXT2 157
#define CLK_TOP_NFI1X_PAD 158
-#define CLK_TOP_NR 159
+#define CLK_TOP_AXISEL_D4 159
+#define CLK_TOP_NR 160
/* APMIXEDSYS */
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index 3e514ed51d15..e9d77f0e8bce 100644
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -235,7 +235,8 @@
#define CLK_AUDIO_MEM_ASRC3 43
#define CLK_AUDIO_MEM_ASRC4 44
#define CLK_AUDIO_MEM_ASRC5 45
-#define CLK_AUDIO_NR_CLK 46
+#define CLK_AUDIO_AFE_CONN 46
+#define CLK_AUDIO_NR_CLK 47
/* SSUSBSYS */