diff options
| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-09-22 14:56:16 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-09-27 12:55:50 +0200 |
| commit | 8e5470c9839caff94fe334e67ff7e7ace587282a (patch) | |
| tree | d96d839061310f9c2e94f7fc24fc906d338f4d01 /include/uapi | |
| parent | ffea043965e4634617485b4d313d6c0099d817f0 (diff) | |
serial: 8250: Set Altera 16550 TX FIFO Threshold
The Altera 16550 soft IP UART requires 2 additional registers for
TX FIFO threshold support. These 2 registers enable the TX FIFO
Low Watermark and set the TX FIFO Low Watermark.
Set the TX FIFO threshold to the FIFO size - tx_loadsz.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/linux/serial_reg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h index 1e5ac4e776da..b4c04842a8c0 100644 --- a/include/uapi/linux/serial_reg.h +++ b/include/uapi/linux/serial_reg.h @@ -376,5 +376,13 @@ #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ +/* + * These are definitions for the Altera ALTR_16550_F32/F64/F128 + * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs). + */ +#define UART_ALTR_AFR 0x40 /* Additional Features Register */ +#define UART_ALTR_EN_TXFIFO_LW 0x01 /* Enable the TX FIFO Low Watermark */ +#define UART_ALTR_TX_LOW 0x41 /* Tx FIFO Low Watermark */ + #endif /* _LINUX_SERIAL_REG_H */ |