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authorDave Airlie <airlied@redhat.com>2019-07-19 17:21:48 +1000
committerDave Airlie <airlied@redhat.com>2019-07-19 17:21:48 +1000
commit9fb7dc73b923ef5e9251ee7c58239a790720904c (patch)
tree95da4a08432a4b6a3d17733dd6b53ffba889428b /include
parentb3c8a40cfc4a7051ac8b7b3fc5fe1ee1467bef25 (diff)
parent41a5a2a8531f95d18bb4efddea581ccb469e8ee5 (diff)
Merge tag 'drm-next-5.3-2019-07-18' of git://people.freedesktop.org/~agd5f/linux into drm-next
drm-next-5.3-2019-07-18: amdgpu: - Navi DC fix for secondary adapters - Fix Navi flickering with high res panels - Navi SMU fixes - Vega20 SMU fixes - Fixes for audio hotplug on HG systems - Fix for potential integer overflows on large buffer migrations - debugfs fixes for umr - Various other small fixes amdkfd: - Apply noretry setting consistently - Fix hang in eviction - Properly clean up GWS on uninit UAPI: - clarify a comment on ctx priority Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190718211525.3374-1-alexander.deucher@amd.com
Diffstat (limited to 'include')
-rw-r--r--include/uapi/drm/amdgpu_drm.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index d799858b9e53..11cc57322962 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -219,7 +219,10 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
#define AMDGPU_CTX_PRIORITY_LOW -512
#define AMDGPU_CTX_PRIORITY_NORMAL 0
-/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
+/*
+ * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
+ * CAP_SYS_NICE or DRM_MASTER
+*/
#define AMDGPU_CTX_PRIORITY_HIGH 512
#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
@@ -229,6 +232,7 @@ struct drm_amdgpu_ctx_in {
/** For future use, no flags defined so far */
__u32 flags;
__u32 ctx_id;
+ /** AMDGPU_CTX_PRIORITY_* */
__s32 priority;
};
@@ -281,6 +285,7 @@ struct drm_amdgpu_sched_in {
/* AMDGPU_SCHED_OP_* */
__u32 op;
__u32 fd;
+ /** AMDGPU_CTX_PRIORITY_* */
__s32 priority;
__u32 ctx_id;
};