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authorThomas Gleixner <tglx@linutronix.de>2017-06-20 01:37:52 +0200
committerThomas Gleixner <tglx@linutronix.de>2017-06-22 18:21:25 +0200
commitd52dd44175bd27ad9d8e34a994fb80877c1f6d61 (patch)
treed9418a898e1a4653d9ed83aac1e4f179640999c0 /kernel/irq
parentc5cb83bb337c25caae995d992d1cdf9b317f83de (diff)
genirq: Introduce IRQD_SINGLE_TARGET flag
Many interrupt chips allow only a single CPU as interrupt target. The core code has no knowledge about that. That's unfortunate as it could avoid trying to readd a newly online CPU to the effective affinity mask. Add the status flag and the necessary accessors. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jens Axboe <axboe@kernel.dk> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Keith Busch <keith.busch@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Christoph Hellwig <hch@lst.de> Link: http://lkml.kernel.org/r/20170619235447.352343969@linutronix.de
Diffstat (limited to 'kernel/irq')
-rw-r--r--kernel/irq/debugfs.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c
index edbef252d0c4..dbd6e78db213 100644
--- a/kernel/irq/debugfs.c
+++ b/kernel/irq/debugfs.c
@@ -105,6 +105,7 @@ static const struct irq_bit_descr irqdata_states[] = {
BIT_MASK_DESCR(IRQD_PER_CPU),
BIT_MASK_DESCR(IRQD_NO_BALANCING),
+ BIT_MASK_DESCR(IRQD_SINGLE_TARGET),
BIT_MASK_DESCR(IRQD_MOVE_PCNTXT),
BIT_MASK_DESCR(IRQD_AFFINITY_SET),
BIT_MASK_DESCR(IRQD_SETAFFINITY_PENDING),