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authorFenghua Yu <fenghua.yu@intel.com>2020-01-02 13:27:06 -0800
committerDavid S. Miller <davem@davemloft.net>2020-01-05 14:21:23 -0800
commitf11421ba4af706cb4f5703de34fa77fba8472776 (patch)
treed2f06c690724be44d1d520f7e14ae15f38db436f /net/qrtr
parentb54ef37b1ce892fdf6b632d566246d2f2f539910 (diff)
drivers/net/b44: Change to non-atomic bit operations on pwol_mask
Atomic operations that span cache lines are super-expensive on x86 (not just to the current processor, but also to other processes as all memory operations are blocked until the operation completes). Upcoming x86 processors have a switch to cause such operations to generate a #AC trap. It is expected that some real time systems will enable this mode in BIOS. In preparation for this, it is necessary to fix code that may execute atomic instructions with operands that cross cachelines because the #AC trap will crash the kernel. Since "pwol_mask" is local and never exposed to concurrency, there is no need to set bits in pwol_mask using atomic operations. Directly operate on the byte which contains the bit instead of using __set_bit() to avoid any big endian concern due to type cast to unsigned long in __set_bit(). Suggested-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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