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authorRadim Krčmář <rkrcmar@redhat.com>2018-02-01 15:04:17 +0100
committerRadim Krčmář <rkrcmar@redhat.com>2018-02-01 15:04:17 +0100
commit7bf14c28ee776be567855bd39ed8ff795ea19f55 (patch)
tree6113748c673e85fccc2c56c050697789c00c6bc2 /tools/perf/pmu-events/arch/x86/broadwellx/other.json
parent87cedc6be55954c6efd6eca2e694132513f65a2a (diff)
parent5fa4ec9cb2e6679e2f828033726f758ea314b9c5 (diff)
Merge branch 'x86/hyperv' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Topic branch for stable KVM clockource under Hyper-V. Thanks to Christoffer Dall for resolving the ARM conflict.
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/broadwellx/other.json')
-rw-r--r--tools/perf/pmu-events/arch/x86/broadwellx/other.json20
1 files changed, 10 insertions, 10 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/perf/pmu-events/arch/x86/broadwellx/other.json
index 718fcb1db2ee..4475249ea9da 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json
@@ -10,16 +10,6 @@
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
- "EventCode": "0x5C",
- "UMask": "0x2",
- "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "EventName": "CPL_CYCLES.RING123",
- "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
- "SampleAfterValue": "2000003",
- "CounterHTOff": "0,1,2,3,4,5,6,7"
- },
- {
"EdgeDetect": "1",
"EventCode": "0x5C",
"UMask": "0x1",
@@ -32,6 +22,16 @@
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
+ "EventCode": "0x5C",
+ "UMask": "0x2",
+ "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
+ "Counter": "0,1,2,3",
+ "EventName": "CPL_CYCLES.RING123",
+ "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
+ "SampleAfterValue": "2000003",
+ "CounterHTOff": "0,1,2,3,4,5,6,7"
+ },
+ {
"EventCode": "0x63",
"UMask": "0x1",
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",