diff options
| author | Ian Rogers <irogers@google.com> | 2022-07-27 15:08:11 -0700 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2022-07-28 16:07:27 -0300 |
| commit | ae54f70dd9d5a962e823a3577271c5dddf046522 (patch) | |
| tree | af3c4bbf4678c4d4b83f25b659cb3588d39b809c /tools/perf | |
| parent | beb2db9bed367ea28433f4a1088f0be2069529e5 (diff) | |
perf vendor events: Update goldmontplus mapfile.csv
Align end of file whitespace with what is generated by:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py
Correct the version in mapfile.csv.
Event json remains at v1.01, there are no goldmontplus metrics.
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-10-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf')
7 files changed, 7 insertions, 7 deletions
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json index 59c039169eb8..16e8913c0434 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json @@ -1462,4 +1462,4 @@ "SampleAfterValue": "100007", "UMask": "0x1" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json index c1f00c9470f4..9c3d22439530 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json @@ -35,4 +35,4 @@ "SampleAfterValue": "2000003", "UMask": "0x8" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json index 3fdc788a2b20..4c2abfbac8f8 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json @@ -95,4 +95,4 @@ "SampleAfterValue": "200003", "UMask": "0x1" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json index e26763d16d52..ae0cb3451866 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json @@ -35,4 +35,4 @@ "SampleAfterValue": "200003", "UMask": "0x4" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json index 4d7e3129e5ac..2b712b12cc1f 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json @@ -428,7 +428,7 @@ "EventName": "MACHINE_CLEARS.SMC", "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.", + "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.", "SampleAfterValue": "20003", "UMask": "0x1" }, diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json index 36eaec87eead..1f7db22c15e6 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json @@ -218,4 +218,4 @@ "SampleAfterValue": "20003", "UMask": "0x20" } -]
\ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 17047a972c16..9a69ecc95d66 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -7,7 +7,7 @@ GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core GenuineIntel-6-96,v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core -GenuineIntel-6-7A,v1,goldmontplus,core +GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-3C,v24,haswell,core GenuineIntel-6-45,v24,haswell,core GenuineIntel-6-46,v24,haswell,core |