diff options
author | Joerg Roedel <jroedel@suse.de> | 2019-06-24 10:23:16 +0200 |
---|---|---|
committer | Joerg Roedel <jroedel@suse.de> | 2019-06-24 10:23:16 +0200 |
commit | ceedd5f74d8cfe34db4e654a7808e3c5de40d6f5 (patch) | |
tree | e19c18292231202e9cd8d484ee43f46b2c9c9ad1 /tools/testing/selftests/powerpc/tm/tm-trap.c | |
parent | 1b961423158caaae49d3900b7c9c37477bbfa9b3 (diff) | |
parent | 4b972a01a7da614b4796475f933094751a295a2f (diff) |
Merge tag 'v5.2-rc6' into generic-dma-ops
Linux 5.2-rc6
Diffstat (limited to 'tools/testing/selftests/powerpc/tm/tm-trap.c')
-rw-r--r-- | tools/testing/selftests/powerpc/tm/tm-trap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/testing/selftests/powerpc/tm/tm-trap.c b/tools/testing/selftests/powerpc/tm/tm-trap.c index 179d592f0073..601f0c1d450d 100644 --- a/tools/testing/selftests/powerpc/tm/tm-trap.c +++ b/tools/testing/selftests/powerpc/tm/tm-trap.c @@ -1,6 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2017, Gustavo Romero, IBM Corp. - * Licensed under GPLv2. * * Check if thread endianness is flipped inadvertently to BE on trap * caught in TM whilst MSR.FP and MSR.VEC are zero (i.e. just after |