diff options
| author | jacek.tomaka@poczta.fm <jacek.tomaka@poczta.fm> | 2018-04-24 00:14:25 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-06-21 04:02:49 +0900 |
| commit | 09daf2df8db88672ae8060eee7802d93a371f244 (patch) | |
| tree | 3d9dee4e6531f766add3e05ba3d61d7f618526bd /tools | |
| parent | 75b0436b24d6806c10108c4743c1c816aa026289 (diff) | |
x86/cpu/intel: Add missing TLB cpuid values
[ Upstream commit b837913fc2d9061bf9b8c0dd6bf2d24e2f98b84a ]
Make kernel print the correct number of TLB entries on Intel Xeon Phi 7210
(and others)
Before:
[ 0.320005] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
After:
[ 0.320005] Last level dTLB entries: 4KB 256, 2MB 128, 4MB 128, 1GB 16
The entries do exist in the official Intel SMD but the type column there is
incorrect (states "Cache" where it should read "TLB"), but the entries for
the values 0x6B, 0x6C and 0x6D are correctly described as 'Data TLB'.
Signed-off-by: Jacek Tomaka <jacek.tomaka@poczta.fm>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20180423161425.24366-1-jacekt@dugeo.com
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions