diff options
| author | Manoj Iyer <manoj.iyer@canonical.com> | 2010-03-02 00:01:41 -0600 |
|---|---|---|
| committer | Leann Ogasawara <leann.ogasawara@canonical.com> | 2010-08-20 15:58:36 -0700 |
| commit | 1390d5a95c775cdd1361746b2c9fef94e6679aaf (patch) | |
| tree | 80881f7cecadfde42a3d8caacedb5a7d3c0a4bcf /ubuntu/rtl8192se/rtl8192s | |
| parent | fe01ac5daaf6d7b5ada3f2ba1216e856b7ebb793 (diff) | |
UBUNTU: ubuntu: rtl8192se -- version 2010-0115,0014
ExternalDriver: rtl8192se_pci
Description: Driver for RTL8191/92 or RTL8171 wifi nic
Url: http://www.realtek.com/
Mask:
Version: 2010-0115,0014
Buglink: http://launchpad.net/bugs/530275
Signed-off-by: Manoj Iyer <manoj.iyer@canonical.com>
Signed-off-by: Andy Whitcroft <apw@canonical.com>
Diffstat (limited to 'ubuntu/rtl8192se/rtl8192s')
24 files changed, 31641 insertions, 0 deletions
diff --git a/ubuntu/rtl8192se/rtl8192s/Makefile b/ubuntu/rtl8192se/rtl8192s/Makefile new file mode 100644 index 000000000000..86754af2a758 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/Makefile @@ -0,0 +1,10 @@ +.PHONY:clean +clean: + rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~ + rm -fr .tmp_versions + rm -fr Modules.symvers + rm -fr Module.symvers + rm -fr Module.markers + rm -fr modules.order + rm -fr tags + diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_Efuse.c b/ubuntu/rtl8192se/rtl8192s/r8192S_Efuse.c new file mode 100644 index 000000000000..0b7c0d8208c2 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_Efuse.c @@ -0,0 +1,1869 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#include "../rtl_core.h"
+#include "r8192S_Efuse.h"
+
+#include <linux/types.h>
+
+#ifdef RTL8192SE
+/*---------------------------Define Local Constant---------------------------*/
+#define _POWERON_DELAY_
+#define _PRE_EXECUTE_READ_CMD_
+
+#define EFUSE_REPEAT_THRESHOLD_ 3
+#define EFUSE_ERROE_HANDLE 1
+
+
+typedef struct _EFUSE_MAP_A{
+ u8 offset; + u8 word_start; + u8 byte_start; + u8 byte_cnts;
+
+}EFUSE_MAP, *PEFUSE_MAP;
+
+typedef struct PG_PKT_STRUCT_A{
+ u8 offset;
+ u8 word_en;
+ u8 data[8];
+}PGPKT_STRUCT,*PPGPKT_STRUCT;
+
+typedef enum _EFUSE_DATA_ITEM{
+ EFUSE_CHIP_ID=0,
+ EFUSE_LDO_SETTING,
+ EFUSE_CLK_SETTING,
+ EFUSE_SDIO_SETTING,
+ EFUSE_CCCR,
+ EFUSE_SDIO_MODE,
+ EFUSE_OCR,
+ EFUSE_F0CIS,
+ EFUSE_F1CIS,
+ EFUSE_MAC_ADDR,
+ EFUSE_EEPROM_VER,
+ EFUSE_CHAN_PLAN,
+ EFUSE_TXPW_TAB
+} EFUSE_DATA_ITEM;
+
+struct efuse_priv
+{
+ u8 id[2];
+ u8 ldo_setting[2];
+ u8 clk_setting[2];
+ u8 cccr;
+ u8 sdio_mode;
+ u8 ocr[3];
+ u8 cis0[17];
+ u8 cis1[48];
+ u8 mac_addr[6];
+ u8 eeprom_verno;
+ u8 channel_plan;
+ u8 tx_power_b[14];
+ u8 tx_power_g[14];
+};
+
+/*---------------------------Define Local Constant---------------------------*/
+
+
+/*------------------------Define global variable-----------------------------*/
+const u8 MAX_PGPKT_SIZE = 9; +const u8 PGPKT_DATA_SIZE = 8; +const u32 EFUSE_MAX_SIZE = 512;
+
+const u8 EFUSE_OOB_PROTECT_BYTES = 15;
+
+
+const EFUSE_MAP RTL8712_SDIO_EFUSE_TABLE[]={
+/*ID*/ {0 ,0 ,0 ,2 }, +/*LDO Setting*/ {0 ,1 ,0 ,2 }, +/*CLK Setting*/ {0 ,2 ,0 ,2 }, +/*SDIO Setting*/{1 ,0 ,0 ,1 }, +/*CCCR*/ {1 ,0 ,1 ,1 }, +/*SDIO MODE*/ {1 ,1 ,0 ,1 }, +/*OCR*/ {1 ,1 ,1 ,3 }, +/*CCIS*/ {1 ,3 ,0 ,17 }, +/*F1CIS*/ {3 ,3 ,1 ,48 }, +/*MAC Addr*/ {10 ,0 ,0 ,6 }, +/*EEPROM ver*/ {10 ,3 ,0 ,1 }, +/*Channel plan*/{10 ,3 ,1 ,1 }, +/*TxPwIndex */ {11 ,0 ,0 ,28 } +};
+
+/*------------------------Define global variable-----------------------------*/
+
+
+/*------------------------Define local variable------------------------------*/
+
+/*------------------------Define local variable------------------------------*/
+
+
+/*--------------------Define function prototype-----------------------*/
+extern void
+EFUSE_Initialize(struct net_device* dev);
+extern u8
+EFUSE_Read1Byte(struct net_device* dev, u16 Address);
+extern void
+EFUSE_Write1Byte(struct net_device* dev, u16 Address,u8 Value);
+
+static void
+efuse_ShadowRead1Byte(struct net_device* dev,u16 Offset,u8 *Value);
+static void
+efuse_ShadowRead2Byte(struct net_device* dev, u16 Offset,u16 *Value );
+static void
+efuse_ShadowRead4Byte(struct net_device* dev, u16 Offset,u32 *Value );
+static void
+efuse_ShadowWrite1Byte(struct net_device* dev, u16 Offset, u8 Value);
+static void
+efuse_ShadowWrite2Byte(struct net_device* dev, u16 Offset,u16 Value);
+static void
+efuse_ShadowWrite4Byte(struct net_device* dev, u16 Offset,u32 Value);
+
+static u8
+efuse_OneByteRead(struct net_device* dev,u16 addr,u8 *data);
+static u8
+efuse_OneByteWrite(struct net_device* dev,u16 addr, u8 data);
+
+static void
+efuse_ReadAllMap(struct net_device* dev,u8 *Efuse);
+#ifdef TO_DO_LIST
+static void
+efuse_WriteAllMap(struct net_device* dev,u8 *eeprom,u32 eeprom_size);
+static bool
+efuse_ParsingMap(char* szStr,u32* pu4bVal,u32* pu4bMove);
+#endif
+static u8
+efuse_PgPacketRead( struct net_device* dev,u8 offset,u8 *data);
+static u8
+efuse_PgPacketWrite(struct net_device* dev,u8 offset,u8 word_en,u8 *data);
+static void
+efuse_WordEnableDataRead( u8 word_en,u8 *sourdata,u8 *targetdata);
+static u8
+efuse_WordEnableDataWrite( struct net_device* dev, u16 efuse_addr, u8 word_en, u8 *data);
+static void
+efuse_PowerSwitch(struct net_device* dev,u8 PwrState);
+static u16
+efuse_GetCurrentSize(struct net_device* dev);
+static u8
+efuse_CalculateWordCnts(u8 word_en);
+#if 0
+static void
+efuse_ResetLoader(struct net_device* dev);
+#endif
+#ifdef TO_DO_LIST
+static void efuse_reg_ctrl(struct net_device* dev, u8 bPowerOn);
+#endif
+/*--------------------Define function prototype-----------------------*/
+
+
+
+extern void
+EFUSE_Initialize(struct net_device* dev)
+{
+ u8 Bytetemp = {0x00};
+ u8 temp = {0x00};
+
+ Bytetemp = read_nic_byte(dev, SYS_FUNC_EN+1);
+ temp = Bytetemp | 0x20;
+ write_nic_byte(dev, SYS_FUNC_EN+1, temp);
+
+ Bytetemp = read_nic_byte(dev, SYS_ISO_CTRL+1);
+ temp = Bytetemp & 0xFE;
+ write_nic_byte(dev, SYS_ISO_CTRL+1, temp);
+
+
+ Bytetemp = read_nic_byte(dev, EFUSE_TEST+3);
+ temp = Bytetemp | 0x80;
+ write_nic_byte(dev, EFUSE_TEST+3, temp);
+
+ write_nic_byte(dev, 0x2F8, 0x3);
+
+ write_nic_byte(dev, EFUSE_CTRL+3, 0x72);
+
+} /* EFUSE_Initialize */
+
+
+extern u8
+EFUSE_Read1Byte(struct net_device* dev, u16 Address)
+{
+ u8 data;
+ u8 Bytetemp = {0x00};
+ u8 temp = {0x00};
+ u32 k=0;
+
+ if (Address < EFUSE_REAL_CONTENT_LEN) + {
+ temp = Address & 0xFF;
+ write_nic_byte(dev, EFUSE_CTRL+1, temp);
+ Bytetemp = read_nic_byte(dev, EFUSE_CTRL+2);
+ temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
+ write_nic_byte(dev, EFUSE_CTRL+2, temp);
+
+ Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
+ temp = Bytetemp & 0x7F;
+ write_nic_byte(dev, EFUSE_CTRL+3, temp);
+
+ Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
+ while(!(Bytetemp & 0x80))
+ {
+ Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
+ k++;
+ if(k==1000)
+ {
+ k=0;
+ break;
+ }
+ }
+ data=read_nic_byte(dev, EFUSE_CTRL);
+ return data;
+ }
+ else
+ return 0xFF;
+
+} /* EFUSE_Read1Byte */
+
+
+extern void
+EFUSE_Write1Byte(struct net_device* dev, u16 Address,u8 Value)
+{
+ u8 Bytetemp = {0x00};
+ u8 temp = {0x00};
+ u32 k=0;
+
+
+ if( Address < EFUSE_REAL_CONTENT_LEN) + {
+ write_nic_byte(dev, EFUSE_CTRL, Value);
+
+ temp = Address & 0xFF;
+ write_nic_byte(dev, EFUSE_CTRL+1, temp);
+ Bytetemp = read_nic_byte(dev, EFUSE_CTRL+2);
+
+ temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
+ write_nic_byte(dev, EFUSE_CTRL+2, temp);
+
+ Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
+ temp = Bytetemp | 0x80;
+ write_nic_byte(dev, EFUSE_CTRL+3, temp);
+
+ Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
+ while(Bytetemp & 0x80)
+ {
+ Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3);
+ k++;
+ if(k==100)
+ {
+ k=0;
+ break;
+ }
+ }
+ }
+
+} /* EFUSE_Write1Byte */
+
+
+#ifdef EFUSE_FOR_92SU
+void do_93c46(struct net_device* dev, u8 addorvalue)
+{
+ u8 cs[1] = {0x88}; + u8 cssk[1] = {0x8c}; + u8 csdi[1] = {0x8a}; + u8 csskdi[1] = {0x8e}; + u8 count;
+
+ for(count=0 ; count<8 ; count++)
+ {
+ if((addorvalue&0x80)!=0)
+ {
+ write_nic_byte(dev, EPROM_CMD, csdi[0]);
+ write_nic_byte(dev, EPROM_CMD, csskdi[0]);
+ }
+ else
+ {
+ write_nic_byte(dev, EPROM_CMD, cs[0]);
+ write_nic_byte(dev, EPROM_CMD, cssk[0]);
+ }
+ addorvalue = addorvalue << 1;
+ }
+}
+
+
+u16 Read93C46(struct net_device* dev, u16 Reg )
+{
+
+ u8 clear[1] = {0x0}; + u8 cs[1] = {0x88}; + u8 cssk[1] = {0x8c}; + u8 csdi[1] = {0x8a}; + u8 csskdi[1] = {0x8e}; + u8 EepromSEL[1]={0x00};
+ u8 address;
+
+ u16 storedataF[1] = {0x0}; + u8 t,data[1],storedata[1];
+
+
+ address = (u8)Reg;
+
+ *EepromSEL= read_nic_byte(dev, EPROM_CMD);
+
+ if((*EepromSEL & 0x10) == 0x10) + {
+ address = address | 0x80;
+
+ write_nic_byte(dev, EPROM_CMD, csdi[0]);
+ write_nic_byte(dev, EPROM_CMD, csskdi[0]);
+ do_93c46(dev, address);
+ }
+
+
+ for(t=0 ; t<16 ; t++) + {
+ write_nic_byte(dev, EPROM_CMD, cs[0]);
+ write_nic_byte(dev, EPROM_CMD, cssk[0]);
+ *data= read_nic_byte(dev, EPROM_CMD);
+
+ if(*data & 0x8d) + {
+ *data = *data & 0x01;
+ *storedata = *data;
+ }
+ else
+ {
+ *data = *data & 0x01 ;
+ *storedata = *data;
+ }
+ *storedataF = (*storedataF << 1 ) + *storedata;
+ }
+ write_nic_byte(dev, EPROM_CMD, cs[0]);
+ write_nic_byte(dev, EPROM_CMD, clear[0]);
+
+ return *storedataF;
+}
+
+
+void
+ReadEFuseByte(struct net_device* dev,u16 _offset, u8 *pbuf)
+{
+
+ u32 value32;
+ u8 readbyte;
+ u16 retry;
+
+
+ write_nic_byte(dev, EFUSE_CTRL+1, (_offset & 0xff));
+ readbyte = read_nic_byte(dev, EFUSE_CTRL+2);
+ write_nic_byte(dev, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
+
+ readbyte = read_nic_byte(dev, EFUSE_CTRL+3);
+ write_nic_byte(dev, EFUSE_CTRL+3, (readbyte & 0x7f));
+
+ retry = 0;
+ value32 = read_nic_dword(dev, EFUSE_CTRL);
+ while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10000))
+ {
+ value32 = read_nic_dword(dev, EFUSE_CTRL);
+ retry++;
+ }
+ *pbuf = (u8)(value32 & 0xff);
+}
+
+
+#define EFUSE_READ_SWITCH 1
+void
+ReadEFuse(struct net_device* dev, u16 _offset, u16 _size_byte, u8 *pbuf)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 efuseTbl[EFUSE_MAP_LEN];
+ u8 rtemp8[1];
+ u16 eFuse_Addr = 0;
+ u8 offset, wren;
+ u16 i, j;
+ u16 eFuseWord[EFUSE_MAX_SECTION][EFUSE_MAX_WORD_UNIT]; + u16 efuse_utilized = 0;
+ u16 efuse_usage = 0;
+#ifdef EFUSE_REPG_WORKAROUND
+ u16 sec1_addr = 0, sec5_addr = 0;
+#endif
+
+ if((_offset + _size_byte)>EFUSE_MAP_LEN)
+ { + printk("ReadEFuse(): Invalid offset with read bytes!!\n");
+ return;
+ }
+
+ for (i = 0; i < EFUSE_MAX_SECTION; i++)
+ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
+ eFuseWord[i][j]=0xFFFF;
+
+ for (i = 0; i < EFUSE_MAP_LEN; i++)
+ efuseTbl[i] = 0xFF;
+
+ ReadEFuseByte(dev, eFuse_Addr, rtemp8);
+ if(*rtemp8 != 0xFF)
+ {
+ efuse_utilized++;
+ eFuse_Addr++;
+ }
+ while((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN))
+ {
+ offset = ((*rtemp8 >> 4) & 0x0f);
+#ifdef EFUSE_REPG_WORKAROUND
+ if (IS_HARDWARE_TYPE_8192SE(dev))
+ {
+ if (offset == 1)
+ {
+ sec1_addr = eFuse_Addr; + }
+ else if (offset == 5)
+ {
+ sec5_addr = eFuse_Addr;
+ }
+
+ if (sec1_addr > sec5_addr)
+ {
+ priv->efuse_RePGSec1Flag = false;
+ }
+ else
+ {
+ priv->efuse_RePGSec1Flag = true;
+ }
+ }
+#endif
+ if(offset < EFUSE_MAX_SECTION){
+ wren = (*rtemp8 & 0x0f);
+ for(i=0; i<4; i++){
+ if(!(wren & 0x01)){
+ ReadEFuseByte(dev, eFuse_Addr, rtemp8); eFuse_Addr++;
+ efuse_utilized++;
+ eFuseWord[offset][i] = (*rtemp8 & 0xff);
+ if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN) break;
+ ReadEFuseByte(dev, eFuse_Addr, rtemp8); eFuse_Addr++;
+ efuse_utilized++;
+ eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00);
+ if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN) break;
+ }
+ wren >>= 1;
+ }
+ }
+ ReadEFuseByte(dev, eFuse_Addr, rtemp8);
+ if(*rtemp8 != 0xFF && (eFuse_Addr < 512))
+ {
+ efuse_utilized++;
+ eFuse_Addr++;
+ }
+ }
+
+ for(i=0; i<EFUSE_MAX_SECTION; i++){
+ for(j=0; j<EFUSE_MAX_WORD_UNIT; j++){
+ efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
+ efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
+#ifdef FUSE_REPG_WORKAROUND
+ if ((i == 1) && (priv->efuse_RePGSec1Flag == true))
+ {
+ priv->efuse_RePGData[j*2]=(eFuseWord[i][j] & 0xff);
+ priv->efuse_RePGData[(j*2)+1]=((eFuseWord[i][j] >> 8) & 0xff);
+ }
+#endif
+ }
+ }
+ for(i=0; i<_size_byte; i++)
+ pbuf[i] = efuseTbl[_offset+i];
+ priv->EfuseUsedBytes = efuse_utilized;
+ efuse_usage = (u8)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN);
+ priv->EfuseUsedPercentage = efuse_usage;
+}
+#endif +
+extern bool EFUSE_ShadowUpdateChk(struct net_device *dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 SectionIdx, i, Base;
+ u16 WordsNeed = 0, HdrNum = 0, TotalBytes = 0, EfuseUsed = 0;
+ bool bWordChanged, bResult = true;
+
+ for (SectionIdx = 0; SectionIdx < 16; SectionIdx++) {
+ Base = SectionIdx * 8;
+ bWordChanged = false;
+
+ for (i = 0; i < 8; i=i+2) {
+ if((priv->EfuseMap[EFUSE_INIT_MAP][Base+i] !=
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Base+i]) ||
+ (priv->EfuseMap[EFUSE_INIT_MAP][Base+i+1] !=
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Base+i+1])) {
+ WordsNeed++;
+ bWordChanged = true;
+ }
+ }
+
+ if( bWordChanged == true )
+ HdrNum++;
+ }
+
+ TotalBytes = HdrNum + WordsNeed * 2;
+ EfuseUsed = priv->EfuseUsedBytes;
+
+ if ((TotalBytes + EfuseUsed) >= (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES))
+ bResult = false;
+
+ return bResult;
+}
+
+extern void
+EFUSE_ShadowRead( struct net_device* dev, u8 Type, u16 Offset, u32 *Value)
+{
+
+ if (Type == 1)
+ efuse_ShadowRead1Byte(dev, Offset, (u8 *)Value);
+ else if (Type == 2)
+ efuse_ShadowRead2Byte(dev, Offset, (u16 *)Value);
+ else if (Type == 4)
+ efuse_ShadowRead4Byte(dev, Offset, (u32 *)Value);
+
+} +
+
+extern void
+EFUSE_ShadowWrite( struct net_device* dev, u8 Type, u16 Offset,u32 Value)
+{
+
+ if (Offset >= 0x18 && Offset <= 0x1F)
+ return;
+
+ if (Type == 1)
+ efuse_ShadowWrite1Byte(dev, Offset, (u8)Value);
+ else if (Type == 2)
+ efuse_ShadowWrite2Byte(dev, Offset, (u16)Value);
+ else if (Type == 4)
+ efuse_ShadowWrite4Byte(dev, Offset, (u32)Value);
+
+} +
+
+extern bool EFUSE_ShadowUpdate(struct net_device* dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u16 i, offset, base = 0;
+ u8 word_en = 0x0F;
+ bool first_pg = false;
+
+ if (!EFUSE_ShadowUpdateChk(dev)) {
+ efuse_ReadAllMap(dev, &priv->EfuseMap[EFUSE_INIT_MAP][0]);
+ memcpy(&priv->EfuseMap[EFUSE_MODIFY_MAP][0],
+ (void *)&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
+
+ printk("<---EFUSE_ShadowUpdate(): Efuse out of capacity!!\n");
+ return false;
+ }
+
+ efuse_PowerSwitch(dev, true);
+
+ for (offset = 0; offset < 16; offset++)
+ {
+ if(IS_HARDWARE_TYPE_8192SE(dev)){
+ if (offset == 3)
+ continue;
+ }
+ word_en = 0x0F;
+ base = offset * 8;
+
+ for (i = 0; i < 8; i++)
+ {
+ if (offset == 0 && priv->EfuseMap[EFUSE_INIT_MAP][base+i] == 0xFF)
+ {
+ first_pg = true;
+ }
+
+ if (first_pg == true && offset == 1 && IS_HARDWARE_TYPE_8192SE(dev))
+ {
+ continue;
+ }
+
+ if (first_pg == true)
+ {
+ word_en &= ~(BIT(i/2));
+ priv->EfuseMap[EFUSE_INIT_MAP][base+i] =
+ priv->EfuseMap[EFUSE_MODIFY_MAP][base+i];
+ }else
+ {
+ if ( priv->EfuseMap[EFUSE_INIT_MAP][base+i] !=
+ priv->EfuseMap[EFUSE_MODIFY_MAP][base+i])
+ {
+ word_en &= ~(EFUSE_BIT(i/2));
+
+ priv->EfuseMap[EFUSE_INIT_MAP][base+i] =
+ priv->EfuseMap[EFUSE_MODIFY_MAP][base+i];
+ }
+ }
+ }
+
+ if (word_en != 0x0F)
+ {
+ u8 tmpdata[8];
+
+ memcpy(tmpdata, &(priv->EfuseMap[EFUSE_MODIFY_MAP][base]), 8);
+ efuse_PgPacketWrite(dev,(u8)offset,word_en,tmpdata);
+ }
+
+ }
+ if (first_pg == true && IS_HARDWARE_TYPE_8192SE(dev))
+ {
+ u8 tmpdata[8];
+
+ memcpy(tmpdata, (&priv->EfuseMap[EFUSE_MODIFY_MAP][8]), 8);
+ efuse_PgPacketWrite(dev, 1, 0x0, tmpdata);
+#if 0
+ u1Byte tmpdata[8] = {0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF};
+
+ efuse_PgPacketWrite(pAdapter, 1, 0xD, tmpdata);
+#endif
+ }
+
+
+ efuse_PowerSwitch(dev, false);
+ efuse_ReadAllMap(dev, &priv->EfuseMap[EFUSE_INIT_MAP][0]);
+ memcpy(&priv->EfuseMap[EFUSE_MODIFY_MAP][0],
+ (void *)&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
+
+ return true;
+} +
+
+extern void EFUSE_ShadowMapUpdate(struct net_device* dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ if (priv->AutoloadFailFlag == true){
+ memset(&(priv->EfuseMap[EFUSE_INIT_MAP][0]), 0xff, 128);
+ }else{
+ efuse_ReadAllMap(dev, &priv->EfuseMap[EFUSE_INIT_MAP][0]);
+ }
+ memcpy(&priv->EfuseMap[EFUSE_MODIFY_MAP][0],
+ &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);
+
+} +
+
+extern void
+EFUSE_ForceWriteVendorId( struct net_device* dev)
+{
+ u8 tmpdata[8] = {0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF};
+
+ efuse_PowerSwitch(dev, true);
+
+ efuse_PgPacketWrite(dev, 1, 0xD, tmpdata);
+
+ efuse_PowerSwitch(dev, false);
+
+} +
+extern void
+EFUSE_RePgSection1(struct net_device* dev)
+{
+#ifdef EFUSE_REPG_WORKAROUND
+
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ if (priv->efuse_RePGSec1Flag == true)
+ {
+ efuse_PowerSwitch(dev, true);
+ RT_TRACE(COMP_INIT, "EFUSE REPG: %p, %u\n", priv->efuse_RePGData, 8);
+
+ efuse_PgPacketWrite(dev, 1, 0x0d, priv->efuse_RePGData);
+ efuse_PowerSwitch(dev, false);
+ priv->efuse_RePGSec1Flag = false;
+ }
+#endif
+} +
+
+static void
+efuse_ShadowRead1Byte(struct net_device* dev, u16 Offset, u8 *Value)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset];
+
+} +
+static void
+efuse_ShadowRead2Byte(struct net_device* dev, u16 Offset, u16 *Value)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset];
+ *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1]<<8;
+
+} +
+static void
+efuse_ShadowRead4Byte(struct net_device* dev, u16 Offset, u32 *Value)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset];
+ *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1]<<8;
+ *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+2]<<16;
+ *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+3]<<24;
+
+} +
+
+
+static void
+efuse_ShadowWrite1Byte(struct net_device* dev, u16 Offset, u8 Value)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = Value;
+
+} +
+static void
+efuse_ShadowWrite2Byte(struct net_device* dev, u16 Offset, u16 Value)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = Value&0x00FF;
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1] = Value>>8;
+
+} +
+static void
+efuse_ShadowWrite4Byte(struct net_device* dev, u16 Offset, u32 Value)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = (u8)(Value&0x000000FF);
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1] = (u8)((Value>>8)&0x0000FF);
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+2] = (u8)((Value>>16)&0x00FF);
+ priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+3] = (u8)((Value>>24)&0xFF);
+
+} +
+
+static u8
+efuse_OneByteRead(struct net_device* dev, u16 addr,u8 *data)
+{
+ u8 tmpidx = 0;
+ u8 bResult;
+
+ write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff));
+ write_nic_byte(dev, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03) ) |
+ (read_nic_byte(dev, EFUSE_CTRL+2)&0xFC ));
+
+ write_nic_byte(dev, EFUSE_CTRL+3, 0x72); +
+ while(!(0x80 &read_nic_byte(dev, EFUSE_CTRL+3))&&(tmpidx<100))
+ {
+ tmpidx++;
+ }
+ if(tmpidx<100)
+ {
+ *data=read_nic_byte(dev, EFUSE_CTRL);
+ bResult = true;
+ }
+ else
+ {
+ *data = 0xff;
+ bResult = false;
+ }
+ return bResult;
+} +
+static u8
+efuse_OneByteWrite(struct net_device* dev, u16 addr, u8 data)
+{
+ u8 tmpidx = 0;
+ u8 bResult;
+
+
+
+ write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff));
+ write_nic_byte(dev, EFUSE_CTRL+2,
+ read_nic_byte(dev, EFUSE_CTRL+2)|(u8)((addr>>8)&0x03) );
+
+ write_nic_byte(dev, EFUSE_CTRL, data); + write_nic_byte(dev, EFUSE_CTRL+3, 0xF2); +
+ while((0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){
+ tmpidx++;
+ }
+
+ if(tmpidx<100)
+ {
+ bResult = true;
+ }
+ else
+ {
+ bResult = false;
+ }
+
+ return bResult;
+} +
+
+static void
+efuse_ReadAllMap(struct net_device* dev, u8 *Efuse)
+{
+
+ efuse_PowerSwitch(dev, true);
+ ReadEFuse(dev, 0, 128, Efuse);
+ efuse_PowerSwitch(dev, false);
+#if 0
+ RT_TRACE(COMP_INIT, "efuse_ResetLoader\n");
+ efuse_ResetLoader(dev);
+
+ write_nic_byte(dev, EFUSE_CLK, 0x03);
+
+ ReadEFuse(dev, 0, 128, Efuse);
+
+ write_nic_byte(dev, EFUSE_CLK, 0x02);
+#if 0 + for(offset = 0;offset<16;offset++) + {
+ PlatformFillMemory((PVOID)pg_data, 8, 0xff);
+ efuse_PgPacketRead(pAdapter,offset,pg_data);
+
+ PlatformMoveMemory((PVOID)&Efuse[offset*8], (PVOID)pg_data, 8);
+ }
+#endif
+
+ if (Efuse[0] != 0x29 || Efuse[1] != 0x81)
+ {
+ if (index ++ < 5)
+ {
+ RT_TRACE(COMP_INIT, "EFUSE R FAIL %d\n", index);
+ efuse_ReadAllMap(dev, Efuse);
+ }
+ }
+ else
+ {
+ index = 0;
+ }
+
+#endif
+} +
+
+#ifdef TO_DO_LIST
+static void
+efuse_WriteAllMap(struct net_device* dev,u8 *eeprom, u32 eeprom_size)
+{
+ unsigned char word_en = 0x00;
+
+ unsigned char tmpdata[8];
+ unsigned char offset;
+
+ efuse_PowerSwitch(dev, true);
+
+ for(offset=0 ; offset< eeprom_size/PGPKT_DATA_SIZE ; offset++)
+ {
+ if (IS_HARDWARE_TYPE_8192SE(dev))
+ {
+ if (offset == 3/* || offset > 9*/)
+ continue; + else
+ word_en = 0x00;
+ }
+
+ memcpy(tmpdata, (eeprom+(offset*PGPKT_DATA_SIZE)), 8);
+
+
+ efuse_PgPacketWrite(dev,offset,word_en,tmpdata);
+
+
+ }
+
+ efuse_PowerSwitch(dev, false);
+
+} +#endif
+static u8
+efuse_PgPacketRead( struct net_device* dev, u8 offset, u8 *data)
+{
+ u8 ReadState = PG_STATE_HEADER;
+
+ bool bContinual = true;
+ bool bDataEmpty = true ;
+
+ u8 efuse_data,word_cnts=0;
+ u16 efuse_addr = 0;
+ u8 hoffset=0,hworden=0;
+ u8 tmpidx=0;
+ u8 tmpdata[8];
+
+ if(data==NULL) return false;
+ if(offset>15) return false;
+
+ memset(data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
+ memset(tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
+
+
+ while(bContinual && (efuse_addr < EFUSE_MAX_SIZE) )
+ {
+ if(ReadState & PG_STATE_HEADER)
+ {
+ if(efuse_OneByteRead(dev, efuse_addr ,&efuse_data)&&(efuse_data!=0xFF)){
+ hoffset = (efuse_data>>4) & 0x0F;
+ hworden = efuse_data & 0x0F;
+ word_cnts = efuse_CalculateWordCnts(hworden);
+ bDataEmpty = true ;
+
+ if(hoffset==offset){
+ for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++){
+ if(efuse_OneByteRead(dev, efuse_addr+1+tmpidx ,&efuse_data) ){
+ tmpdata[tmpidx] = efuse_data;
+ if(efuse_data!=0xff){
+ bDataEmpty = false;
+ }
+ }
+ }
+ if(bDataEmpty==false){
+ ReadState = PG_STATE_DATA;
+ }else{ + efuse_addr = efuse_addr + (word_cnts*2)+1;
+ ReadState = PG_STATE_HEADER;
+ }
+ }
+ else{ + efuse_addr = efuse_addr + (word_cnts*2)+1;
+ ReadState = PG_STATE_HEADER;
+ }
+
+ }
+ else{
+ bContinual = false ;
+ }
+ }
+ else if(ReadState & PG_STATE_DATA)
+ {
+ efuse_WordEnableDataRead(hworden,tmpdata,data);
+ efuse_addr = efuse_addr + (word_cnts*2)+1;
+ ReadState = PG_STATE_HEADER;
+ }
+
+ }
+
+
+ if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) &&
+ (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff))
+ return false;
+ else
+ return true;
+
+} +
+
+static u8 efuse_PgPacketWrite(struct net_device* dev, u8 offset, u8 word_en,u8 *data)
+{
+ u8 WriteState = PG_STATE_HEADER;
+ bool bContinual = true,bDataEmpty=true, bResult = true;
+ u16 efuse_addr = 0;
+ u8 efuse_data;
+
+ u8 pg_header = 0;
+
+ u8 tmp_word_cnts=0,target_word_cnts=0;
+ u8 tmp_header,match_word_en,tmp_word_en;
+
+ PGPKT_STRUCT target_pkt;
+ PGPKT_STRUCT tmp_pkt;
+
+ u8 originaldata[sizeof(u8)*8];
+ u8 tmpindex = 0,badworden = 0x0F;
+
+ static u32 repeat_times = 0;
+
+ if (efuse_GetCurrentSize(dev) >= EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES) {
+ printk("efuse_PgPacketWrite error \n");
+ return false;
+ }
+
+ target_pkt.offset = offset;
+ target_pkt.word_en= word_en;
+
+ memset(target_pkt.data,0xFF,sizeof(u8)*8);
+
+ efuse_WordEnableDataRead(word_en,data,target_pkt.data);
+ target_word_cnts = efuse_CalculateWordCnts(target_pkt.word_en);
+
+ printk("EFUSE Power ON\n");
+
+ while (bContinual && (efuse_addr < (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES)))
+ {
+ if(WriteState==PG_STATE_HEADER)
+ {
+ bDataEmpty=true;
+ badworden = 0x0F;
+ printk("EFUSE PG_STATE_HEADER\n");
+ if ( efuse_OneByteRead(dev, efuse_addr ,&efuse_data) &&
+ (efuse_data!=0xFF))
+ {
+ tmp_header = efuse_data;
+
+ tmp_pkt.offset = (tmp_header>>4) & 0x0F;
+ tmp_pkt.word_en = tmp_header & 0x0F;
+ tmp_word_cnts = efuse_CalculateWordCnts(tmp_pkt.word_en);
+
+ if(tmp_pkt.offset != target_pkt.offset)
+ {
+ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; + #if (EFUSE_ERROE_HANDLE == 1)
+ WriteState = PG_STATE_HEADER;
+ #endif
+ }
+ else
+ {
+ for(tmpindex=0 ; tmpindex<(tmp_word_cnts*2) ; tmpindex++)
+ {
+ if(efuse_OneByteRead(dev, (efuse_addr+1+tmpindex) ,&efuse_data)&&(efuse_data != 0xFF)){
+ bDataEmpty = false;
+ }
+ }
+ if(bDataEmpty == false)
+ {
+ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; + #if (EFUSE_ERROE_HANDLE == 1)
+ WriteState=PG_STATE_HEADER;
+ #endif
+ }
+ else
+ { + match_word_en = 0x0F;
+ if( !( (target_pkt.word_en&BIT0)|(tmp_pkt.word_en&BIT0) ))
+ {
+ match_word_en &= (~BIT0);
+ }
+ if( !( (target_pkt.word_en&BIT1)|(tmp_pkt.word_en&BIT1) ))
+ {
+ match_word_en &= (~BIT1);
+ }
+ if( !( (target_pkt.word_en&BIT2)|(tmp_pkt.word_en&BIT2) ))
+ {
+ match_word_en &= (~BIT2);
+ }
+ if( !( (target_pkt.word_en&BIT3)|(tmp_pkt.word_en&BIT3) ))
+ {
+ match_word_en &= (~BIT3);
+ }
+
+ if((match_word_en&0x0F)!=0x0F)
+ {
+ badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1, tmp_pkt.word_en ,target_pkt.data);
+
+ if(0x0F != (badworden&0x0F))
+ {
+ u8 reorg_offset = offset;
+ u8 reorg_worden=badworden;
+ efuse_PgPacketWrite(dev,reorg_offset,reorg_worden,originaldata);
+ }
+
+ tmp_word_en = 0x0F;
+ if( (target_pkt.word_en&BIT0)^(match_word_en&BIT0) )
+ {
+ tmp_word_en &= (~BIT0);
+ }
+ if( (target_pkt.word_en&BIT1)^(match_word_en&BIT1) )
+ {
+ tmp_word_en &= (~BIT1);
+ }
+ if( (target_pkt.word_en&BIT2)^(match_word_en&BIT2) )
+ {
+ tmp_word_en &= (~BIT2);
+ }
+ if( (target_pkt.word_en&BIT3)^(match_word_en&BIT3) )
+ {
+ tmp_word_en &=(~BIT3);
+ }
+
+ if((tmp_word_en&0x0F)!=0x0F){
+ efuse_addr = efuse_GetCurrentSize(dev);
+ target_pkt.offset = offset;
+ target_pkt.word_en= tmp_word_en;
+ }else{
+ bContinual = false;
+ }
+ #if (EFUSE_ERROE_HANDLE == 1)
+ WriteState=PG_STATE_HEADER;
+ repeat_times++;
+ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
+ bContinual = false;
+ bResult = false;
+ }
+ #endif
+ }
+ else{ + efuse_addr = efuse_addr + (2*tmp_word_cnts) +1; + target_pkt.offset = offset;
+ target_pkt.word_en= target_pkt.word_en;
+ #if (EFUSE_ERROE_HANDLE == 1)
+ WriteState=PG_STATE_HEADER;
+ #endif
+ }
+ }
+ }
+ printk("EFUSE PG_STATE_HEADER-1\n");
+ }
+ else + {
+ pg_header = ((target_pkt.offset << 4)&0xf0) |target_pkt.word_en;
+
+ efuse_OneByteWrite(dev,efuse_addr, pg_header);
+ efuse_OneByteRead(dev,efuse_addr, &tmp_header);
+
+ if(tmp_header == pg_header)
+ { + WriteState = PG_STATE_DATA;
+ }
+ #if (EFUSE_ERROE_HANDLE == 1)
+ else if(tmp_header == 0xFF){ + WriteState = PG_STATE_HEADER;
+ repeat_times++;
+ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
+ bContinual = false;
+ bResult = false;
+ }
+ }
+ #endif
+ else
+ { + tmp_pkt.offset = (tmp_header>>4) & 0x0F;
+ tmp_pkt.word_en= tmp_header & 0x0F;
+ tmp_word_cnts = efuse_CalculateWordCnts(tmp_pkt.word_en);
+
+ memset(originaldata,0xff,sizeof(u8)*8);
+
+ if(efuse_PgPacketRead( dev, tmp_pkt.offset,originaldata))
+ { + badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1,tmp_pkt.word_en,originaldata);
+ if(0x0F != (badworden&0x0F))
+ {
+ u8 reorg_offset = tmp_pkt.offset;
+ u8 reorg_worden=badworden;
+ efuse_PgPacketWrite(dev,reorg_offset,reorg_worden,originaldata);
+ efuse_addr = efuse_GetCurrentSize(dev);
+ }
+ else{
+ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; + }
+ }
+ else
+ {
+ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; + }
+
+ #if (EFUSE_ERROE_HANDLE == 1)
+ WriteState=PG_STATE_HEADER;
+ repeat_times++;
+ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
+ bContinual = false;
+ bResult = false;
+ }
+ #endif
+
+ printk("EFUSE PG_STATE_HEADER-2\n");
+ }
+
+ }
+
+ }
+ else if(WriteState==PG_STATE_DATA)
+ { + printk("EFUSE PG_STATE_DATA\n");
+ badworden = 0x0f;
+ badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1,target_pkt.word_en,target_pkt.data);
+ if((badworden&0x0F)==0x0F)
+ { + bContinual = false;
+ }
+ else
+ { + efuse_addr = efuse_addr + (2*target_word_cnts) +1; +
+ target_pkt.offset = offset;
+ target_pkt.word_en= badworden;
+ target_word_cnts = efuse_CalculateWordCnts(target_pkt.word_en);
+ #if (EFUSE_ERROE_HANDLE == 1)
+ WriteState=PG_STATE_HEADER;
+ repeat_times++;
+ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){
+ bContinual = false;
+ bResult = false;
+ }
+ #endif
+ printk("EFUSE PG_STATE_HEADER-3\n");
+ }
+ }
+ }
+
+
+ return true;
+} +
+
+static void
+efuse_WordEnableDataRead( u8 word_en,u8 *sourdata,u8 *targetdata)
+{
+
+
+
+ if (!(word_en&BIT0))
+ {
+ targetdata[0] = sourdata[0]; + targetdata[1] = sourdata[1]; + }
+ if (!(word_en&BIT1))
+ {
+ targetdata[2] = sourdata[2]; + targetdata[3] = sourdata[3]; + }
+ if (!(word_en&BIT2))
+ {
+ targetdata[4] = sourdata[4]; + targetdata[5] = sourdata[5]; + }
+ if (!(word_en&BIT3))
+ {
+ targetdata[6] = sourdata[6]; + targetdata[7] = sourdata[7]; + }
+} +
+
+static u8
+efuse_WordEnableDataWrite( struct net_device* dev, u16 efuse_addr, u8 word_en, u8 *data)
+{
+ u16 tmpaddr = 0;
+ u16 start_addr = efuse_addr;
+ u8 badworden = 0x0F;
+ u8 tmpdata[8];
+
+ memset(tmpdata,0xff,PGPKT_DATA_SIZE);
+
+
+
+ if(!(word_en&BIT0))
+ {
+ tmpaddr = start_addr;
+ efuse_OneByteWrite(dev,start_addr++, data[0]);
+ efuse_OneByteWrite(dev,start_addr++, data[1]);
+
+ efuse_OneByteRead(dev,tmpaddr, &tmpdata[0]);
+ efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[1]);
+ if((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])){
+ badworden &= (~BIT0);
+ }
+ }
+ if(!(word_en&BIT1))
+ {
+ tmpaddr = start_addr;
+ efuse_OneByteWrite(dev,start_addr++, data[2]);
+ efuse_OneByteWrite(dev,start_addr++, data[3]);
+
+ efuse_OneByteRead(dev,tmpaddr , &tmpdata[2]);
+ efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[3]);
+ if((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])){
+ badworden &=( ~BIT1);
+ }
+ }
+ if(!(word_en&BIT2))
+ {
+ tmpaddr = start_addr;
+ efuse_OneByteWrite(dev,start_addr++, data[4]);
+ efuse_OneByteWrite(dev,start_addr++, data[5]);
+
+ efuse_OneByteRead(dev,tmpaddr, &tmpdata[4]);
+ efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[5]);
+ if((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])){
+ badworden &=( ~BIT2);
+ }
+ }
+ if(!(word_en&BIT3))
+ {
+ tmpaddr = start_addr;
+ efuse_OneByteWrite(dev,start_addr++, data[6]);
+ efuse_OneByteWrite(dev,start_addr++, data[7]);
+
+ efuse_OneByteRead(dev,tmpaddr, &tmpdata[6]);
+ efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[7]);
+ if((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])){
+ badworden &=( ~BIT3);
+ }
+ }
+ return badworden;
+} +
+
+static void
+efuse_PowerSwitch(struct net_device* dev, u8 PwrState)
+{
+ u8 tempval;
+ if (PwrState == true)
+ {
+ tempval = read_nic_byte(dev, EFUSE_TEST+3);
+ write_nic_byte(dev, EFUSE_TEST+3, (tempval | 0x80));
+
+ write_nic_byte(dev, EFUSE_CLK, 0x03);
+ }
+ else
+ {
+ tempval = read_nic_byte(dev, EFUSE_TEST+3);
+ write_nic_byte(dev, EFUSE_TEST+3, (tempval & 0x7F));
+
+ write_nic_byte(dev, EFUSE_CLK, 0x02);
+ }
+
+} /* efuse_PowerSwitch */
+
+
+static u16
+efuse_GetCurrentSize(struct net_device* dev)
+{
+ bool bContinual = true;
+
+ u16 efuse_addr = 0;
+ u8 hoffset=0,hworden=0;
+ u8 efuse_data,word_cnts=0;
+
+
+ while ( bContinual &&
+ efuse_OneByteRead(dev, efuse_addr ,&efuse_data) &&
+ (efuse_addr < EFUSE_MAX_SIZE) )
+ {
+ if(efuse_data!=0xFF)
+ {
+ hoffset = (efuse_data>>4) & 0x0F;
+ hworden = efuse_data & 0x0F;
+ word_cnts = efuse_CalculateWordCnts(hworden);
+ efuse_addr = efuse_addr + (word_cnts*2)+1;
+ }
+ else
+ {
+ bContinual = false ;
+ }
+ }
+
+
+ return efuse_addr;
+
+} +
+
+static u8
+efuse_CalculateWordCnts(u8 word_en)
+{
+ u8 word_cnts = 0;
+ if(!(word_en & BIT0)) word_cnts++; + if(!(word_en & BIT1)) word_cnts++;
+ if(!(word_en & BIT2)) word_cnts++;
+ if(!(word_en & BIT3)) word_cnts++;
+ return word_cnts;
+} +
+
+#if 0
+static void efuse_ResetLoader(struct net_device* dev)
+{
+ u16 tmpU2b;
+
+ tmpU2b = read_nic_word(dev, SYS_FUNC_EN);
+ write_nic_word(dev, SYS_FUNC_EN, (tmpU2b&~(BIT12)));
+ mdelay(10);
+ write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|BIT12));
+ mdelay(10);
+
+} +#endif
+
+ #ifdef TO_DO_LIST
+extern bool +EFUSE_ProgramMap(struct net_device* dev, char* pFileName,u8 TableType)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ s4Byte nLinesRead, ithLine;
+ RT_STATUS rtStatus = RT_STATUS_SUCCESS;
+ char* szLine;
+ u32 u4bRegValue, u4RegMask;
+ u32 u4bMove;
+ u16 index = 0;
+ u16 i;
+ u8 eeprom[HWSET_MAX_SIZE_92S];
+
+ rtStatus = PlatformReadFile(
+ dev,
+ pFileName,
+ (u8*)(priv->BufOfLines),
+ MAX_LINES_HWCONFIG_TXT,
+ MAX_BYTES_LINE_HWCONFIG_TXT,
+ &nLinesRead
+ );
+
+ if(rtStatus == RT_STATUS_SUCCESS)
+ {
+ memcp(pHalData->BufOfLines3, pHalData->BufOfLines,
+ nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT);
+ pHalData->nLinesRead3 = nLinesRead;
+ }
+
+ if(rtStatus == RT_STATUS_SUCCESS)
+ {
+ printk("szEepromFile(): read %s ok\n", pFileName);
+ for(ithLine = 0; ithLine < nLinesRead; ithLine++)
+ {
+ szLine = pHalData->BufOfLines[ithLine];
+ printk("Line-%d String =%s\n", ithLine, szLine);
+
+ if(!IsCommentString(szLine))
+ {
+ for (i = 0; i < 8; i++)
+ {
+ u32 j;
+
+ efuse_ParsingMap(szLine, &u4bRegValue, &u4bMove);
+
+ szLine += u4bMove;
+ eeprom[index++] = (u8)(u4bRegValue&0xff);
+ eeprom[index++] = (u8)((u4bRegValue>>8)&0xff);
+
+ printk("Addr-%d = %x\n", (ithLine*8+i), u4bRegValue);
+ }
+ }
+
+ }
+
+ }
+ else
+ {
+ printk("szEepromFile(): Fail read%s\n", pFileName);
+ return RT_STATUS_FAILURE;
+ }
+
+
+
+ if (TableType == 1)
+ {
+ efuse_WriteAllMap(dev, eeprom, HWSET_MAX_SIZE_92S);
+ }
+ else
+ {
+ for (i = 0; i < HWSET_MAX_SIZE_92S; i++)
+ EFUSE_ShadowWrite(dev, 1, i, (u32)eeprom[i]);
+ }
+
+ return rtStatus;
+} /* EFUSE_ProgramMap */
+
+#endif
+
+bool IsHexDigit( char chTmp)
+{
+ if( (chTmp >= '0' && chTmp <= '9') ||
+ (chTmp >= 'a' && chTmp <= 'f') ||
+ (chTmp >= 'A' && chTmp <= 'F') )
+ {
+ return true;
+ }
+ else
+ {
+ return false;
+ }
+}
+
+u32 MapCharToHexDigit(char chTmp)
+{
+ if(chTmp >= '0' && chTmp <= '9')
+ return (chTmp - '0');
+ else if(chTmp >= 'a' && chTmp <= 'f')
+ return (10 + (chTmp - 'a'));
+ else if(chTmp >= 'A' && chTmp <= 'F')
+ return (10 + (chTmp - 'A'));
+ else
+ return 0;
+}
+
+#ifdef TO_DO_LIST
+static bool
+efuse_ParsingMap(char* szStr,u32* pu4bVal,u32* pu4bMove)
+{
+ char* szScan = szStr;
+
+ if(szStr == NULL || pu4bVal == NULL || pu4bMove == NULL)
+ {
+ return false;
+ }
+
+ *pu4bMove = 0;
+ *pu4bVal = 0;
+
+ while( *szScan != '\0' &&
+ (*szScan == ' ' || *szScan == '\t') )
+ {
+ szScan++;
+ (*pu4bMove)++;
+ }
+
+ if(!IsHexDigit(*szScan))
+ {
+ return false;
+ }
+
+ do
+ {
+ (*pu4bVal) <<= 4;
+ *pu4bVal += MapCharToHexDigit(*szScan);
+
+ szScan++;
+ (*pu4bMove)++;
+ } while(IsHexDigit(*szScan));
+
+ return true;
+
+} /* efuse_ParsingMap */
+#endif
+
+int efuse_one_byte_rw(struct net_device* dev, u8 bRead, u16 addr, u8 *data)
+{
+ u32 bResult;
+ u8 tmpidx = 0;
+ u8 tmpv8=0;
+
+
+ write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff)); + tmpv8 = ((u8)((addr>>8) &0x03) ) | (read_nic_byte(dev, EFUSE_CTRL+2)&0xFC );
+ write_nic_byte(dev, EFUSE_CTRL+2, tmpv8);
+
+ if(true==bRead){
+
+ write_nic_byte(dev, EFUSE_CTRL+3, 0x72); +
+ while(!(0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){
+ tmpidx++;
+ }
+ if(tmpidx<100){
+ *data=read_nic_byte(dev, EFUSE_CTRL);
+ bResult = true;
+ }
+ else
+ {
+ *data = 0;
+ bResult = false;
+ }
+
+ }
+ else{
+ write_nic_byte(dev, EFUSE_CTRL, *data); +
+ write_nic_byte(dev, EFUSE_CTRL+3, 0xF2); +
+ while((0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){
+ tmpidx++;
+ }
+ if(tmpidx<100)
+ {
+ *data=read_nic_byte(dev, EFUSE_CTRL);
+ bResult = true;
+ }
+ else
+ {
+ *data = 0;
+ bResult = false;
+ }
+
+ }
+ return bResult;
+}
+void efuse_access(struct net_device* dev, u8 bRead,u16 start_addr, u8 cnts, u8 *data)
+{
+ u8 efuse_clk_ori,efuse_clk_new; + u32 i = 0;
+
+ if(start_addr>0x200) return;
+ efuse_clk_ori = read_nic_byte(dev,SYS_FUNC_EN+1);
+ efuse_clk_new = efuse_clk_ori|0x20;
+
+ if(efuse_clk_new!= efuse_clk_ori){
+ write_nic_byte(dev, SYS_FUNC_EN+1, efuse_clk_new);
+ }
+#ifdef _POWERON_DELAY_
+ mdelay(10);
+#endif
+ write_nic_byte(dev, EFUSE_TEST+3, (read_nic_byte(dev, EFUSE_TEST+3)|0x80));
+ write_nic_byte(dev, EFUSE_CLK_CTRL, (read_nic_byte(dev, EFUSE_CLK_CTRL)|0x03));
+
+#ifdef _PRE_EXECUTE_READ_CMD_
+ {
+ unsigned char tmpdata;
+ efuse_OneByteRead(dev, 0,&tmpdata);
+ }
+#endif
+
+ for(i=0;i<cnts;i++){
+ efuse_one_byte_rw(dev,bRead, start_addr+i , data+i);
+ }
+ write_nic_byte(dev, EFUSE_TEST+3, read_nic_byte(dev, EFUSE_TEST+3)&0x7f);
+ write_nic_byte(dev, EFUSE_CLK_CTRL, read_nic_byte(dev, EFUSE_CLK_CTRL)&0xfd);
+
+ if(efuse_clk_new != efuse_clk_ori) write_nic_byte(dev, 0x10250003, efuse_clk_ori);
+
+}
+
+#ifdef TO_DO_LIST
+static void efuse_reg_ctrl(struct net_device* dev, u8 bPowerOn)
+{
+ if(true==bPowerOn){
+ write_nic_byte(dev, SYS_FUNC_EN+1, read_nic_byte(dev,SYS_FUNC_EN+1)|0x20);
+#ifdef _POWERON_DELAY_
+ mdelay(10);
+#endif
+ write_nic_byte(dev, EFUSE_TEST+4, (read_nic_byte(dev, EFUSE_TEST+4)|0x80));
+ write_nic_byte(dev, EFUSE_CLK_CTRL, (read_nic_byte(dev, EFUSE_CLK_CTRL)|0x03));
+#ifdef _PRE_EXECUTE_READ_CMD_
+ {
+ unsigned char tmpdata;
+ efuse_OneByteRead(dev, 0,&tmpdata);
+ }
+
+#endif
+ }
+ else{
+ write_nic_byte(dev, EFUSE_TEST+4, read_nic_byte(dev, EFUSE_TEST+4)&0x7f);
+ write_nic_byte(dev, EFUSE_CLK_CTRL, read_nic_byte(dev, EFUSE_CLK_CTRL)&0xfd);
+
+ }
+
+
+}
+#endif
+
+void efuse_read_data(struct net_device* dev,u8 efuse_read_item,u8 *data,u32 data_size)
+{
+ u8 offset, word_start,byte_start,byte_cnts;
+ u8 efusedata[EFUSE_REAL_CONTENT_LEN];
+ u8 *tmpdata = NULL;
+
+ u8 pg_pkt_cnts ;
+
+ u8 tmpidx;
+ u8 pg_data[8];
+
+ if(efuse_read_item> (sizeof(RTL8712_SDIO_EFUSE_TABLE)/sizeof(EFUSE_MAP))){
+ return ;
+ }
+
+ offset = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].offset ;
+ word_start = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].word_start;
+ byte_start = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].byte_start;
+ byte_cnts = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].byte_cnts;
+
+ if(data_size!=byte_cnts){
+ return;
+ }
+
+ pg_pkt_cnts = (byte_cnts /PGPKT_DATA_SIZE) +1;
+
+ if(pg_pkt_cnts > 1){
+ tmpdata = efusedata;
+
+ if(tmpdata!=NULL)
+ {
+ memset(tmpdata,0xff,pg_pkt_cnts*PGPKT_DATA_SIZE);
+
+ for(tmpidx=0;tmpidx<pg_pkt_cnts;tmpidx++)
+ {
+ memset(pg_data,0xff,PGPKT_DATA_SIZE);
+ if(true== efuse_PgPacketRead(dev,offset+tmpidx,pg_data))
+ {
+ memcpy(tmpdata+(PGPKT_DATA_SIZE*tmpidx),pg_data,PGPKT_DATA_SIZE);
+ }
+ }
+ memcpy(data,(tmpdata+ (2*word_start)+byte_start ),data_size);
+ }
+ }
+ else
+ {
+ memset(pg_data,0xff,PGPKT_DATA_SIZE);
+ if(true==efuse_PgPacketRead(dev,offset,pg_data)){
+ memcpy(data,pg_data+ (2*word_start)+byte_start ,data_size);
+ }
+ }
+
+}
+void efuse_write_data(struct net_device* dev,u8 efuse_write_item,u8 *data,u32 data_size,u32 bWordUnit)
+{
+ u8 offset, word_start,byte_start,byte_cnts;
+ u8 word_en = 0x0f,word_cnts;
+ u8 pg_pkt_cnts ;
+
+ u8 tmpidx,tmpbitmask;
+ u8 pg_data[8],tmpbytes=0;
+
+ if(efuse_write_item> (sizeof(RTL8712_SDIO_EFUSE_TABLE)/sizeof(EFUSE_MAP))){
+ return ;
+ }
+
+ offset = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].offset ;
+ word_start = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].word_start;
+ byte_start = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].byte_start;
+ byte_cnts = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].byte_cnts;
+
+ if(data_size > byte_cnts){
+ return;
+ }
+ pg_pkt_cnts = (byte_cnts /PGPKT_DATA_SIZE) +1;
+ word_cnts = byte_cnts /2 ;
+
+ if(byte_cnts %2){
+ word_cnts+=1;
+ }
+ if((byte_start==1)||((byte_cnts%2)==1)){ +
+ if((efuse_write_item==EFUSE_F0CIS)||(efuse_write_item==EFUSE_F1CIS)){
+ memset(pg_data,0xff,PGPKT_DATA_SIZE);
+ efuse_PgPacketRead(dev,offset,pg_data);
+
+ if(efuse_write_item==EFUSE_F0CIS){
+ word_en = 0x07;
+ memcpy(pg_data+word_start*2+byte_start,data,sizeof(u8)*2);
+ efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2));
+
+ word_en = 0x00;
+ efuse_PgPacketWrite(dev,(offset+1),word_en,data+2);
+
+ word_en = 0x00;
+ efuse_PgPacketRead(dev,offset+2,pg_data);
+ memcpy(pg_data,data+2+8,sizeof(u8)*7);
+
+ efuse_PgPacketWrite(dev,(offset+2),word_en,pg_data);
+ }
+ else if(efuse_write_item==EFUSE_F1CIS){
+ word_en = 0x07;
+ efuse_PgPacketRead(dev,offset,pg_data);
+ pg_data[7] = data[0];
+ efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2));
+
+ word_en = 0x00;
+ for(tmpidx = 0 ;tmpidx<(word_cnts/4);tmpidx++){
+ efuse_PgPacketWrite(dev,(offset+1+tmpidx),word_en,data+1+(tmpidx*PGPKT_DATA_SIZE));
+ }
+ }
+
+ }
+ else{
+ memset(pg_data,0xff,PGPKT_DATA_SIZE);
+ if((efuse_write_item==EFUSE_SDIO_SETTING)||(efuse_write_item==EFUSE_CCCR)){
+ word_en = 0x0e ;
+ tmpbytes = 2;
+ }
+ else if(efuse_write_item == EFUSE_SDIO_MODE){
+ word_en = 0x0d ;
+ tmpbytes = 2;
+ }
+ else if(efuse_write_item == EFUSE_OCR){
+ word_en = 0x09 ;
+ tmpbytes = 4;
+ }
+ else if((efuse_write_item == EFUSE_EEPROM_VER)||(efuse_write_item==EFUSE_CHAN_PLAN)){
+ word_en = 0x07 ;
+ tmpbytes = 2;
+ }
+ if(bWordUnit==true){
+ memcpy(pg_data+word_start*2 ,data,sizeof(u8)*tmpbytes);
+ }
+ else{
+ efuse_PgPacketRead(dev,offset,pg_data);
+ memcpy(pg_data+(2*word_start)+byte_start,data,sizeof(u8)*byte_cnts);
+ }
+
+ efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2));
+
+ }
+
+ }
+ else if(pg_pkt_cnts>1){ + if(word_start==0){
+ word_en = 0x00;
+ for(tmpidx = 0 ;tmpidx<(word_cnts/4);tmpidx++)
+ {
+ efuse_PgPacketWrite(dev,(offset+tmpidx),word_en,data+(tmpidx*PGPKT_DATA_SIZE));
+ }
+ word_en = 0x0f;
+ for(tmpidx= 0; tmpidx<(word_cnts%4) ; tmpidx++)
+ {
+ tmpbitmask =tmpidx;
+ word_en &= (~(EFUSE_BIT(tmpbitmask)));
+ }
+ efuse_PgPacketWrite(dev,offset+(word_cnts/4),word_en,data+((word_cnts/4)*PGPKT_DATA_SIZE));
+ }else
+ {
+
+ }
+ }
+ else{ + word_en = 0x0f;
+ for(tmpidx= 0; tmpidx<word_cnts ; tmpidx++)
+ {
+ tmpbitmask = word_start + tmpidx ;
+ word_en &= (~(EFUSE_BIT(tmpbitmask)));
+ }
+ efuse_PgPacketWrite(dev,offset,word_en,data);
+ }
+
+}
+
+void efuset_test_func_read(struct net_device* dev)
+{
+ u8 chipid[2];
+ u8 ocr[3];
+ u8 macaddr[6];
+ u8 txpowertable[28];
+
+ memset(chipid,0,sizeof(u8)*2);
+ efuse_read_data(dev,EFUSE_CHIP_ID,chipid,sizeof(chipid));
+
+ memset(ocr,0,sizeof(u8)*3);
+ efuse_read_data(dev,EFUSE_CCCR,ocr,sizeof(ocr));
+
+ memset(macaddr,0,sizeof(u8)*6);
+ efuse_read_data(dev,EFUSE_MAC_ADDR,macaddr,sizeof(macaddr));
+
+ memset(txpowertable,0,sizeof(u8)*28);
+ efuse_read_data(dev,EFUSE_TXPW_TAB,txpowertable,sizeof(txpowertable));
+}
+
+void efuset_test_func_write(struct net_device* dev)
+{
+ u32 bWordUnit = true;
+ u8 CCCR=0x02,SDIO_SETTING = 0xFF;
+ u8 tmpdata[2];
+
+ u8 macaddr[6] = {0x00,0xe0,0x4c,0x87,0x12,0x66};
+ efuse_write_data(dev,EFUSE_MAC_ADDR,macaddr,sizeof(macaddr),bWordUnit);
+
+ bWordUnit = false;
+ efuse_write_data(dev,EFUSE_CCCR,&CCCR,sizeof(u8),bWordUnit);
+
+ bWordUnit = false;
+ efuse_write_data(dev,EFUSE_SDIO_SETTING,&SDIO_SETTING,sizeof(u8),bWordUnit);
+
+ bWordUnit = true;
+ tmpdata[0] =SDIO_SETTING ;
+ tmpdata[1] =CCCR ;
+ efuse_write_data(dev,EFUSE_SDIO_SETTING,tmpdata,sizeof(tmpdata),bWordUnit);
+
+}
+#endif diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_Efuse.h b/ubuntu/rtl8192se/rtl8192s/r8192S_Efuse.h new file mode 100644 index 000000000000..405f076f0f69 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_Efuse.h @@ -0,0 +1,98 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+
+#ifndef __INC_EFUSE_H
+#define __INC_EFUSE_H
+
+#define EFUSE_FOR_92SU 1
+
+/*--------------------------Define Parameters-------------------------------*/
+#define EFUSE_REAL_CONTENT_LEN 512
+#define EFUSE_MAP_LEN 128
+#define EFUSE_MAX_SECTION 16
+#define EFUSE_MAX_WORD_UNIT 4
+#define EFUSE_IC_ID_OFFSET 506 +
+#define EFUSE_INIT_MAP 0
+#define EFUSE_MODIFY_MAP 1
+
+#define EFUSE_CLK_CTRL EFUSE_CTRL
+#define EFUSE_BIT(x) (1 << (x))
+
+#define PG_STATE_HEADER 0x01
+#define PG_STATE_WORD_0 0x02
+#define PG_STATE_WORD_1 0x04
+#define PG_STATE_WORD_2 0x08
+#define PG_STATE_WORD_3 0x10
+#define PG_STATE_DATA 0x20
+
+#define PG_SWBYTE_H 0x01
+#define PG_SWBYTE_L 0x02
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+
+/*------------------------------Define structure----------------------------*/
+
+
+/*------------------------Export global variable----------------------------*/
+/*------------------------Export global variable----------------------------*/
+
+/*------------------------Export Marco Definition---------------------------*/
+
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+extern void
+EFUSE_Initialize(struct net_device* dev);
+extern u8
+EFUSE_Read1Byte(struct net_device* dev,u16 Address);
+extern void
+EFUSE_Write1Byte(struct net_device* dev,u16 Address,u8 Value);
+
+#ifdef EFUSE_FOR_92SU
+extern void
+ReadEFuse(struct net_device* dev,u16 _offset,u16 _size_byte,u8* pbuf);
+extern void
+ReadEFuseByte(struct net_device* dev,u16 _offset,u8 *pbuf);
+#endif +
+extern void
+EFUSE_ShadowRead(struct net_device* dev,unsigned char Type,unsigned short Offset,u32 *Value);
+extern void
+EFUSE_ShadowWrite(struct net_device* dev,unsigned char Type,unsigned short Offset,u32 Value);
+extern bool
+EFUSE_ShadowUpdate(struct net_device* dev);
+extern bool
+EFUSE_ShadowUpdateChk(struct net_device* dev);
+extern void
+EFUSE_ShadowMapUpdate(struct net_device* dev);
+extern void
+EFUSE_RePgSection1(struct net_device* dev);
+
+extern bool
+EFUSE_ProgramMap(struct net_device* dev,char* pFileName, u8 TableType); +/*--------------------------Exported Function prototype---------------------*/
+
+/* End of Efuse.h */
+
+#endif diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_def.h b/ubuntu/rtl8192se/rtl8192s/r8192S_def.h new file mode 100644 index 000000000000..c775b46282aa --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_def.h @@ -0,0 +1,760 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef R8192SE_DEF_H +#define R8192SE_DEF_H + +#include <linux/types.h> +#include "../rtl_endianfree.h" + +#define HAL_RETRY_LIMIT_INFRA 48 +#define HAL_RETRY_LIMIT_AP_ADHOC 7 + +#define HAL_DM_DIG_DISABLE BIT0 +#define HAL_DM_HIPWR_DISABLE BIT1 + +#define RX_DESC_SIZE 24 +#define RX_DRV_INFO_SIZE_UNIT 8 + + +#define TX_DESC_SIZE 32 + +#define SET_TX_DESC_PKT_SIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) +#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_DESC_TYPE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 2, __Value) +#define SET_TX_DESC_LAST_SEG(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) +#define SET_TX_DESC_FIRST_SEG(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) +#define SET_TX_DESC_LINIP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) +#define SET_TX_DESC_AMSDU(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) +#define SET_TX_DESC_GREEN_FIELD(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) +#define SET_TX_DESC_OWN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +#define SET_TX_DESC_MACID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 5, __Value) +#define SET_TX_DESC_MORE_DATA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 5, 1, __Value) +#define SET_TX_DESC_MORE_FRAG(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 6, 1, __Value) +#define SET_TX_DESC_PIFS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 7, 1, __Value) +#define SET_TX_DESC_QUEUE_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) +#define SET_TX_DESC_ACK_POLICY(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 2, __Value) +#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) +#define SET_TX_DESC_NON_QOS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 1, __Value) +#define SET_TX_DESC_KEY_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 17, 2, __Value) +#define SET_TX_DESC_OUI(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 19, 1, __Value) +#define SET_TX_DESC_PKT_TYPE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 20, 1, __Value) +#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) +#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) +#define SET_TX_DESC_WDS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 1, __Value) +#define SET_TX_DESC_HTC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 25, 1, __Value) +#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 26, 5, __Value) +#define SET_TX_DESC_HWPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 27, 1, __Value) + +#define SET_TX_DESC_DATA_RETRY_LIMIT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 6, __Value) +#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 6, 1, __Value) +#define SET_TX_DESC_TSFL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 7, 5, __Value) +#define SET_TX_DESC_RTS_RETRY_COUNT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 6, __Value) +#define SET_TX_DESC_DATA_RETRY_COUNT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 6, __Value) +#define SET_TX_DESC_RSVD_MACID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(((__pTxDesc) + 8), 24, 5, __Value) +#define SET_TX_DESC_AGG_ENABLE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 29, 1, __Value) +#define SET_TX_DESC_AGG_BREAK(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value) +#define SET_TX_DESC_OWN_MAC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 31, 1, __Value) + +#define SET_TX_DESC_NEXT_HEAP_PAGE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 8, __Value) +#define SET_TX_DESC_TAIL_PAGE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 8, __Value) +#define SET_TX_DESC_SEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 12, __Value) +#define SET_TX_DESC_FRAG(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 28, 4, __Value) + +#define SET_TX_DESC_RTS_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 6, __Value) +#define SET_TX_DESC_DISABLE_RTS_FB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 6, 1, __Value) +#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 4, __Value) +#define SET_TX_DESC_CTS_ENABLE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 11, 1, __Value) +#define SET_TX_DESC_RTS_ENABLE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 12, 1, __Value) +#define SET_TX_DESC_RA_BRSR_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 3, __Value) +#define SET_TX_DESC_TXHT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 16, 1, __Value) +#define SET_TX_DESC_TX_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) +#define SET_TX_DESC_TX_BANDWIDTH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 1, __Value) +#define SET_TX_DESC_TX_SUB_CARRIER(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 19, 2, __Value) +#define SET_TX_DESC_TX_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 21, 2, __Value) +#define SET_TX_DESC_TX_REVERSE_DIRECTION(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 23, 1, __Value) +#define SET_TX_DESC_RTS_HT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 1, __Value) +#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 25, 1, __Value) +#define SET_TX_DESC_RTS_BANDWIDTH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 26, 1, __Value) +#define SET_TX_DESC_RTS_SUB_CARRIER(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 27, 2, __Value) +#define SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 2, __Value) +#define SET_TX_DESC_USER_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 31, 1, __Value) + +#define SET_TX_DESC_PACKET_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 9, __Value) +#define SET_TX_DESC_TX_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 9, 6, __Value) +#define SET_TX_DESC_DISABLE_FB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 15, 1, __Value) +#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 16, 5, __Value) +#define SET_TX_DESC_TX_AGC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 11, __Value) + +#define SET_TX_DESC_IP_CHECK_SUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 16, __Value) +#define SET_TX_DESC_TCP_CHECK_SUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 16, __Value) + +#define SET_TX_DESC_TX_BUFFER_SIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#define SET_TX_DESC_IP_HEADER_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) +#define SET_TX_DESC_TCP_ENABLE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 31, 1, __Value) + +#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 32, __Value) + + +#define TX_DESC_NEXT_DESC_OFFSET 36 +#define CLEAR_PCI_TX_DESC_CONTENT(__pTxDesc, _size) \ + { \ + if(_size > TX_DESC_NEXT_DESC_OFFSET) \ + memset((void*)__pTxDesc, 0, TX_DESC_NEXT_DESC_OFFSET); \ + else \ + memset((void*)__pTxDesc, 0, _size); \ + if(_size > (TX_DESC_NEXT_DESC_OFFSET + 4)) \ + memset((void*)(__pTxDesc + (TX_DESC_NEXT_DESC_OFFSET + 4)), 0, (_size - TX_DESC_NEXT_DESC_OFFSET)); \ + } + +#define C2H_RX_CMD_HDR_LEN 8 +#define GET_C2H_CMD_CMD_LEN(__pRxHeader) LE_BITS_TO_4BYTE((__pRxHeader), 0, 16) +#define GET_C2H_CMD_ELEMENT_ID(__pRxHeader) LE_BITS_TO_4BYTE((__pRxHeader), 16, 8) +#define GET_C2H_CMD_CMD_SEQ(__pRxHeader) LE_BITS_TO_4BYTE((__pRxHeader), 24, 7) +#define GET_C2H_CMD_CONTINUE(__pRxHeader) LE_BITS_TO_4BYTE((__pRxHeader), 31, 1) +#define GET_C2H_CMD_CONTENT(__pRxHeader) ((u8*)(__pRxHeader) + C2H_RX_CMD_HDR_LEN) + +#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pCmdFBHeader) LE_BITS_TO_4BYTE((__pCmdFBHeader), 0, 8) +#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pCmdFBHeader) LE_BITS_TO_4BYTE((__pCmdFBHeader), 8, 8) +#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pCmdFBHeader) LE_BITS_TO_4BYTE((__pCmdFBHeader), 16, 16) +#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pCmdFBHeader) LE_BITS_TO_4BYTE(((__pCmdFBHeader) + 4), 0, 5) +#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pCmdFBHeader) LE_BITS_TO_4BYTE(((__pCmdFBHeader) + 4), 7, 1) +#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pCmdFBHeader) LE_BITS_TO_4BYTE(((__pCmdFBHeader) + 4), 8, 5) +#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pCmdFBHeader) LE_BITS_TO_4BYTE(((__pCmdFBHeader) + 4), 15, 1) +#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pCmdFBHeader) LE_BITS_TO_4BYTE(((__pCmdFBHeader) + 4), 16, 4) +#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pCmdFBHeader) LE_BITS_TO_4BYTE(((__pCmdFBHeader) + 4), 20, 12) + + +#if 0 +#define BK_QUEUE 0 +#define BE_QUEUE 1 +#define VI_QUEUE 2 +#define VO_QUEUE 3 +#define BEACON_QUEUE 4 +#define TXCMD_QUEUE 5 +#define MGNT_QUEUE 6 +#define HIGH_QUEUE 7 +#define HCCA_QUEUE 8 + +#define LOW_QUEUE BE_QUEUE +#define NORMAL_QUEUE MGNT_QUEUE +#endif + +#define RX_MPDU_QUEUE 0 +#define RX_CMD_QUEUE 1 +#define RX_MAX_QUEUE 2 + + +typedef enum _rtl819x_loopback{ + RTL819X_NO_LOOPBACK = 0, + RTL819X_MAC_LOOPBACK = 1, + RTL819X_DMA_LOOPBACK = 2, + RTL819X_CCK_LOOPBACK = 3, +}rtl819x_loopback_e; + +#define RESET_DELAY_8185 20 + +#define RT_IBSS_INT_MASKS 0 + +#define DESC92S_RATE1M 0x00 +#define DESC92S_RATE2M 0x01 +#define DESC92S_RATE5_5M 0x02 +#define DESC92S_RATE11M 0x03 +#define DESC92S_RATE6M 0x04 +#define DESC92S_RATE9M 0x05 +#define DESC92S_RATE12M 0x06 +#define DESC92S_RATE18M 0x07 +#define DESC92S_RATE24M 0x08 +#define DESC92S_RATE36M 0x09 +#define DESC92S_RATE48M 0x0a +#define DESC92S_RATE54M 0x0b +#define DESC92S_RATEMCS0 0x0c +#define DESC92S_RATEMCS1 0x0d +#define DESC92S_RATEMCS2 0x0e +#define DESC92S_RATEMCS3 0x0f +#define DESC92S_RATEMCS4 0x10 +#define DESC92S_RATEMCS5 0x11 +#define DESC92S_RATEMCS6 0x12 +#define DESC92S_RATEMCS7 0x13 +#define DESC92S_RATEMCS8 0x14 +#define DESC92S_RATEMCS9 0x15 +#define DESC92S_RATEMCS10 0x16 +#define DESC92S_RATEMCS11 0x17 +#define DESC92S_RATEMCS12 0x18 +#define DESC92S_RATEMCS13 0x19 +#define DESC92S_RATEMCS14 0x1a +#define DESC92S_RATEMCS15 0x1b +#define DESC92S_RATEMCS15_SG 0x1c +#define DESC92S_RATEMCS32 0x20 + +#define SHORT_SLOT_TIME 9 +#define NON_SHORT_SLOT_TIME 20 + + +#define MAX_LINES_HWCONFIG_TXT 1000 +#define MAX_BYTES_LINE_HWCONFIG_TXT 256 + +#define SW_THREE_WIRE 0 +#define HW_THREE_WIRE 2 + +#define BT_DEMO_BOARD 0 +#define BT_QA_BOARD 1 +#define BT_FPGA 2 + +#define Rx_Smooth_Factor 20 + +#define QSLT_BK 0x2 +#define QSLT_BE 0x0 +#define QSLT_VI 0x5 +#define QSLT_VO 0x7 +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +#define NUM_OF_FIRMWARE_QUEUE 10 +#define NUM_OF_PAGES_IN_FW 0x100 +#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07 +#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07 +#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07 +#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07 +#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0 +#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0 +#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02 +#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02 +#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2 +#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1 + +#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026 +#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048 +#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048 +#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026 +#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00 + +#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 +#define HAL_PRIME_CHNL_OFFSET_LOWER 1 +#define HAL_PRIME_CHNL_OFFSET_UPPER 2 + + + +#define MAX_SILENT_RESET_RX_SLOT_NUM 10 +typedef enum tag_Rf_OpType +{ + RF_OP_By_SW_3wire = 0, + RF_OP_By_FW, + RF_OP_MAX +}RF_OpType_E; + + +typedef enum _POWER_SAVE_MODE +{ + POWER_SAVE_MODE_ACTIVE, + POWER_SAVE_MODE_SAVE, +}POWER_SAVE_MODE; + +typedef enum _INTERFACE_SELECT_8190PCI{ + INTF_SEL1_MINICARD = 0, + INTF_SEL0_PCIE = 1, + INTF_SEL2_RSV = 2, + INTF_SEL3_RSV = 3, +} INTERFACE_SELECT_8190PCI, *PINTERFACE_SELECT_8190PCI; + + +typedef struct _BB_REGISTER_DEFINITION{ + u32 rfintfs; + u32 rfintfi; + u32 rfintfo; + u32 rfintfe; + u32 rf3wireOffset; + u32 rfLSSI_Select; + u32 rfTxGainStage; + u32 rfHSSIPara1; + u32 rfHSSIPara2; + u32 rfSwitchControl; + u32 rfAGCControl1; + u32 rfAGCControl2; + u32 rfRxIQImbalance; + u32 rfRxAFE; + u32 rfTxIQImbalance; + u32 rfTxAFE; + u32 rfLSSIReadBack; + u32 rfLSSIReadBackPi; +}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; + + + + +typedef struct _rx_fwinfo_8192s{ + + /*u32 gain_0:7; + u32 trsw_0:1; + u32 gain_1:7; + u32 trsw_1:1; + u32 gain_2:7; + u32 trsw_2:1; + u32 gain_3:7; + u32 trsw_3:1; */ + u8 gain_trsw[4]; + + /*u32 pwdb_all:8; + u32 cfosho_0:8; + u32 cfosho_1:8; + u32 cfosho_2:8;*/ + u8 pwdb_all; + u8 cfosho[4]; + + /*u32 cfosho_3:8; + u32 cfotail_0:8; + u32 cfotail_1:8; + u32 cfotail_2:8;*/ + u8 cfotail[4]; + + /*u32 cfotail_3:8; + u32 rxevm_0:8; + u32 rxevm_1:8; + u32 rxsnr_0:8;*/ + s8 rxevm[2]; + s8 rxsnr[4]; + + /*u32 rxsnr_1:8; + u32 rxsnr_2:8; + u32 rxsnr_3:8; + u32 pdsnr_0:8;*/ + u8 pdsnr[2]; + + /*u32 pdsnr_1:8; + u32 csi_current_0:8; + u32 csi_current_1:8; + u32 csi_target_0:8;*/ + u8 csi_current[2]; + u8 csi_target[2]; + + /*u32 csi_target_1:8; + u32 sigevm:8; + u32 max_ex_pwr:8; + u32 ex_intf_flag:1; + u32 sgi_en:1; + u32 rxsc:2; + u32 reserve:4;*/ + u8 sigevm; + u8 max_ex_pwr; + u8 ex_intf_flag:1; + u8 sgi_en:1; + u8 rxsc:2; + u8 reserve:4; + +}rx_fwinfo, *prx_fwinfo; + +typedef struct _LOG_INTERRUPT_8190 +{ + u32 nIMR_COMDOK; + u32 nIMR_MGNTDOK; + u32 nIMR_HIGH; + u32 nIMR_VODOK; + u32 nIMR_VIDOK; + u32 nIMR_BEDOK; + u32 nIMR_BKDOK; + u32 nIMR_ROK; + u32 nIMR_RCOK; + u32 nIMR_TBDOK; + u32 nIMR_BDOK; + u32 nIMR_RXFOVW; +} LOG_INTERRUPT_8190_T, *PLOG_INTERRUPT_8190_T; + +typedef struct _phy_cck_rx_status_report_819xpci +{ + u8 adc_pwdb_X[4]; + u8 sq_rpt; + u8 cck_agc_rpt; +}phy_sts_cck_819xpci_t, phy_sts_cck_8192s_t; + +#define PHY_RSSI_SLID_WIN_MAX 100 +#define PHY_LINKQUALITY_SLID_WIN_MAX 20 +#define PHY_Beacon_RSSI_SLID_WIN_MAX 10 + +typedef struct _tx_desc_8192se{ + + u32 PktSize:16; + u32 Offset:8; + u32 Type:2; + u32 LastSeg:1; + u32 FirstSeg:1; + u32 LINIP:1; + u32 AMSDU:1; + u32 GF:1; + u32 OWN:1; + + u32 MacID:5; + u32 MoreData:1; + u32 MoreFrag:1; + u32 PIFS:1; + u32 QueueSel:5; + u32 AckPolicy:2; + u32 NoACM:1; + u32 NonQos:1; + u32 KeyID:2; + u32 OUI:1; + u32 PktType:1; + u32 EnDescID:1; + u32 SecType:2; + u32 HTC:1; + u32 WDS:1; + u32 PktOffset:5; + u32 HWPC:1; + + u32 DataRetryLmt:6; + u32 RetryLmtEn:1; + u32 TSFL:5; + u32 RTSRC:6; + u32 DATARC:6; +#ifdef _RTL8192_EXT_PATCH_ + u32 Rsvd_MacID:5; +#else + u32 Rsvd1:5; +#endif + u32 AggEn:1; + u32 BK:1; + u32 OwnMAC:1; + + u32 NextHeadPage:8; + u32 TailPage:8; + u32 Seq:12; + u32 Frag:4; + + u32 RTSRate:6; + u32 DisRTSFB:1; + u32 RTSRateFBLmt:4; + u32 CTS2Self:1; + u32 RTSEn:1; + u32 RaBRSRID:3; + u32 TXHT:1; + u32 TxShort:1; + u32 TxBw:1; + u32 TXSC:2; + u32 STBC:2; + u32 RD:1; + u32 RTSHT:1; + u32 RTSShort:1; + u32 RTSBW:1; + u32 RTSSC:2; + u32 RTSSTBC:2; + u32 UserRate:1; + + u32 PktID:9; + u32 TxRate:6; + u32 DISFB:1; + u32 DataRateFBLmt:5; + u32 TxAGC:11; + + u32 IPChkSum:16; + u32 TCPChkSum:16; + + u32 TxBufferSize:16; + u32 IPHdrOffset:8; + u32 Rsvd3:7; + u32 TCPEn:1; + + u32 TxBuffAddr; + + u32 NextDescAddress; + + u32 Reserve_Pass_92S_PCIE_MM_Limit[6]; + +} tx_desc, *ptx_desc; + + +typedef struct _tx_desc_cmd_8192se{ + u32 PktSize:16; + u32 Offset:8; + u32 Rsvd0:2; + u32 FirstSeg:1; + u32 LastSeg:1; + u32 LINIP:1; + u32 Rsvd1:2; + u32 OWN:1; + + u32 Rsvd2; + u32 Rsvd3; + u32 Rsvd4; + u32 Rsvd5; + u32 Rsvd6; + u32 Rsvd7; + + u32 TxBufferSize:16; + u32 Rsvd8:16; + + u32 TxBufferAddr; + + u32 NextTxDescAddress; + + u32 Reserve_Pass_92S_PCIE_MM_Limit[6]; + +}tx_desc_cmd, *ptx_desc_cmd; + + +typedef struct _tx_status_desc_8192se{ + + u32 PktSize:16; + u32 Offset:8; + u32 Type:2; + u32 LastSeg:1; + u32 FirstSeg:1; + u32 LINIP:1; + u32 AMSDU:1; + u32 GF:1; + u32 OWN:1; + + u32 MacID:5; + u32 MoreData:1; + u32 MoreFrag:1; + u32 PIFS:1; + u32 QueueSel:5; + u32 AckPolicy:2; + u32 NoACM:1; + u32 NonQos:1; + u32 KeyID:2; + u32 OUI:1; + u32 PktType:1; + u32 EnDescID:1; + u32 SecType:2; + u32 HTC:1; + u32 WDS:1; + u32 PktOffset:5; + u32 HWPC:1; + + u32 DataRetryLmt:6; + u32 RetryLmtEn:1; + u32 TSFL:5; + u32 RTSRC:6; + u32 DATARC:6; + u32 Rsvd1:5; + u32 AggEn:1; + u32 BK:1; + u32 OwnMAC:1; + + u32 NextHeadPage:8; + u32 TailPage:8; + u32 Seq:12; + u32 Frag:4; + + u32 RTSRate:6; + u32 DisRTSFB:1; + u32 RTSRateFBLmt:4; + u32 CTS2Self:1; + u32 RTSEn:1; + u32 RaBRSRID:3; + u32 TXHT:1; + u32 TxShort:1; + u32 TxBw:1; + u32 TXSC:2; + u32 STBC:2; + u32 RD:1; + u32 RTSHT:1; + u32 RTSShort:1; + u32 RTSBW:1; + u32 RTSSC:2; + u32 RTSSTBC:2; + u32 UserRate:1; + + u32 PktID:9; + u32 TxRate:6; + u32 DISFB:1; + u32 DataRateFBLmt:5; + u32 TxAGC:11; + + u32 IPChkSum:16; + u32 TCPChkSum:16; + + u32 TxBufferSize:16; + u32 IPHdrOffset:8; + u32 Rsvd2:7; + u32 TCPEn:1; + + u32 TxBufferAddr; + + u32 NextDescAddress; + + u32 Reserve_Pass_92S_PCIE_MM_Limit[6]; + +}tx_status_desc, *ptx_status_desc; + + +typedef struct _rx_desc_8192se{ + u32 Length:14; + u32 CRC32:1; + u32 ICVError:1; + u32 DrvInfoSize:4; + u32 Security:3; + u32 Qos:1; + u32 Shift:2; + u32 PHYStatus:1; + u32 SWDec:1; + u32 LastSeg:1; + u32 FirstSeg:1; + u32 EOR:1; + u32 OWN:1; + + u32 MACID:5; + u32 TID:4; + u32 HwRsvd:5; + u32 PAGGR:1; + u32 FAGGR:1; + u32 A1_FIT:4; + u32 A2_FIT:4; + u32 PAM:1; + u32 PWR:1; + u32 MoreData:1; + u32 MoreFrag:1; + u32 Type:2; + u32 MC:1; + u32 BC:1; + + u32 Seq:12; + u32 Frag:4; + u32 NextPktLen:14; + u32 NextIND:1; + u32 Rsvd:1; + + u32 RxMCS:6; + u32 RxHT:1; + u32 AMSDU:1; + u32 SPLCP:1; + u32 BandWidth:1; + u32 HTC:1; + u32 TCPChkRpt:1; + u32 IPChkRpt:1; + u32 TCPChkValID:1; + u32 HwPCErr:1; + u32 HwPCInd:1; + u32 IV0:16; + + u32 IV1; + + u32 TSFL; + + u32 BufferAddress; + + u32 NextRxDescAddress; + +#if 0 + u32 BA_SSN:12; + u32 BA_VLD:1; + u32 RSVD:19; +#endif + +} rx_desc, *prx_desc; + + + +typedef struct _rx_desc_status_8192se{ + u32 Length:14; + u32 CRC32:1; + u32 ICVError:1; + u32 DrvInfoSize:4; + u32 Security:3; + u32 Qos:1; + u32 Shift:2; + u32 PHYStatus:1; + u32 SWDec:1; + u32 LastSeg:1; + u32 FirstSeg:1; + u32 EOR:1; + u32 OWN:1; + + u32 MACID:5; + u32 TID:4; + u32 HwRsvd:5; + u32 PAGGR:1; + u32 FAGGR:1; + u32 A1_FIT:4; + u32 A2_FIT:4; + u32 PAM:1; + u32 PWR:1; + u32 MoreData:1; + u32 MoreFrag:1; + u32 Type:2; + u32 MC:1; + u32 BC:1; + + u32 Seq:12; + u32 Frag:4; + u32 NextPktLen:14; + u32 NextIND:1; + u32 Rsvd:1; + + u32 RxMCS:6; + u32 RxHT:1; + u32 AMSDU:1; + u32 SPLCP:1; + u32 BW:1; + u32 HTC:1; + u32 TCPChkRpt:1; + u32 IPChkRpt:1; + u32 TCPChkValID:1; + u32 HwPCErr:1; + u32 HwPCInd:1; + u32 IV0:16; + + u32 IV1; + + u32 TSFL; + + + u32 BufferAddress; + + u32 NextRxDescAddress; + +#if 0 + u32 BA_SSN:12; + u32 BA_VLD:1; + u32 RSVD:19; +#endif +}rx_desc_status, *prx_desc_status; + +typedef enum _HAL_FW_C2H_CMD_ID +{ + HAL_FW_C2H_CMD_Read_MACREG = 0, + HAL_FW_C2H_CMD_Read_BBREG = 1, + HAL_FW_C2H_CMD_Read_RFREG = 2, + HAL_FW_C2H_CMD_Read_EEPROM = 3, + HAL_FW_C2H_CMD_Read_EFUSE = 4, + HAL_FW_C2H_CMD_Read_CAM = 5, + HAL_FW_C2H_CMD_Get_BasicRate = 6, + HAL_FW_C2H_CMD_Get_DataRate = 7, + HAL_FW_C2H_CMD_Survey = 8 , + HAL_FW_C2H_CMD_SurveyDone = 9, + HAL_FW_C2H_CMD_JoinBss = 10, + HAL_FW_C2H_CMD_AddSTA = 11, + HAL_FW_C2H_CMD_DelSTA = 12, + HAL_FW_C2H_CMD_AtimDone = 13, + HAL_FW_C2H_CMD_TX_Report = 14, + HAL_FW_C2H_CMD_CCX_Report = 15, + HAL_FW_C2H_CMD_DTM_Report = 16, + HAL_FW_C2H_CMD_TX_Rate_Statistics = 17, + HAL_FW_C2H_CMD_C2HLBK = 18, + HAL_FW_C2H_CMD_C2HDBG = 19, + HAL_FW_C2H_CMD_C2HFEEDBACK = 20, + HAL_FW_C2H_CMD_BT_State = 25, + HAL_FW_C2H_CMD_BT_Service = 26, + HAL_FW_C2H_CMD_MAX +}HAL_FW_C2H_CMD_ID; + +#define HAL_FW_C2H_CMD_C2HFEEDBACK_CCX_PER_PKT_RPT 0x04 +#define HAL_FW_C2H_CMD_C2HFEEDBACK_DTM_TX_STATISTICS_RPT 0x05 +#endif diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_dev.c b/ubuntu/rtl8192se/rtl8192s/r8192S_dev.c new file mode 100644 index 000000000000..b9d797611113 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_dev.c @@ -0,0 +1,5256 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#include "../rtl_core.h" +#include "../rtl_dm.h" +#include "../rtl_wx.h" +#include "r8192S_phy.h" +#include "r8192S_phyreg.h" +#include "r8192S_rtl6052.h" +#include "r8192S_Efuse.h" + +#ifdef _RTL8192_EXT_PATCH_ +#include "../../../mshclass/msh_class.h" +#include "../rtl_mesh.h" +#endif + +extern int WDCAPARA_ADD[]; + +void rtl8192se_start_beacon(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct rtllib_network *net = &priv->rtllib->current_network; + u16 BcnTimeCfg = 0; + u16 BcnCW = 6; + u16 BcnIFS = 0xf; + + DMESG("Enabling beacon TX"); + rtl8192_irq_disable(dev); + + write_nic_word(dev, ATIMWND, 2); + + write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); +#ifdef _RTL8192_EXT_PATCH_ + PHY_SetBeaconHwReg(dev, net->beacon_interval); +#endif +#ifdef RTL8192SE + write_nic_word(dev, BCN_DRV_EARLY_INT, 10<<4); +#else + write_nic_word(dev, BCN_DRV_EARLY_INT, 10); +#endif + write_nic_word(dev, BCN_DMATIME, 256); + + write_nic_byte(dev, BCN_ERR_THRESH, 100); + + BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT; + BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; + write_nic_word(dev, BCN_TCFG, BcnTimeCfg); + rtl8192_irq_enable(dev); +} + +void rtl8192se_update_msr(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 msr; + LED_CTL_MODE LedAction = LED_CTL_NO_LINK; + msr = read_nic_byte(dev, MSR); + msr &= ~ MSR_LINK_MASK; + + switch (priv->rtllib->iw_mode) { + case IW_MODE_INFRA: + if (priv->rtllib->state == RTLLIB_LINKED) + msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); + else + msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + LedAction = LED_CTL_LINK; + break; + case IW_MODE_ADHOC: + if (priv->rtllib->state == RTLLIB_LINKED) + msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); + else + msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + break; + case IW_MODE_MASTER: + if (priv->rtllib->state == RTLLIB_LINKED) + msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); + else + msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + break; +#ifdef _RTL8192_EXT_PATCH_ + case IW_MODE_MESH: + printk("%s: only_mesh=%d state=%d\n", __FUNCTION__, + priv->rtllib->only_mesh, priv->rtllib->mesh_state); + if (priv->rtllib->only_mesh) { + if (priv->rtllib->mesh_state == RTLLIB_MESH_LINKED) + msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT); + else + msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); + } else { + if (priv->rtllib->mesh_state == RTLLIB_MESH_LINKED) { + msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); + if (priv->rtllib->state == RTLLIB_LINKED) + msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); + } else { + msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + } + } + break; +#endif + default: + break; + } + + write_nic_byte(dev, MSR, msr); + if(priv->rtllib->LedControlHandler) + priv->rtllib->LedControlHandler(dev, LedAction); +} + +static void rtl8192se_config_hw_for_load_fail(struct net_device* dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u16 i; + u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00}; + u8 rf_path, index; + u32 tmp1111 = 0; + u32 tmp2222 = 0; + + RT_TRACE(COMP_INIT, "====> rtl8192se_config_hw_for_load_fail\n"); + + for(;tmp2222<0xff;tmp2222+=4) + { + tmp1111= read_nic_dword(dev, tmp2222); + } + + write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); + mdelay(10); + write_nic_byte(dev, PMC_FSM, 0x02); + + priv->eeprom_vid= 0; + priv->eeprom_did= 0; + priv->eeprom_ChannelPlan= 0; + priv->eeprom_CustomerID= 0; + + get_random_bytes(&sMacAddr[5], 1); + for(i = 0; i < 6; i++) + dev->dev_addr[i] = sMacAddr[i]; + + + priv->rf_type= RTL819X_DEFAULT_RF_TYPE; + priv->rf_chip = RF_6052; + +#if (EEPROM_OLD_FORMAT_SUPPORT == 1) + for(i=0; i<14; i++) + { + priv->EEPROMTxPowerLevelCCK[i] = (u8)(EEPROM_Default_TxPower & 0xff); + RT_TRACE(COMP_INIT, "CCK 2.4G Tx Pwr Index %d = 0x%02x\n", + i, priv->EEPROMTxPowerLevelCCK[i]); + } + + for(i=0; i<14; i++) + { + priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff); + RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Pwr Index %d = 0x%02x\n", + i, priv->EEPROMTxPowerLevelOFDM24G[i]); + } + + for(i=0; i<14; i++) + { + priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i]; + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK[i]; + } + for(i=0; i<6; i++) + { + priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr; + } + +#else + for (rf_path = 0; rf_path < 2; rf_path++) + { + for (i = 0; i < 3; i++) + { + priv->RfCckChnlAreaTxPwr[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] = + EEPROM_Default_TxPowerLevel; + } + } + + for (rf_path = 0; rf_path < 2; rf_path++) + { + for(i=0; i<14; i++) + { + if (i < 3) + index = 0; +#ifdef _RTL8192_EXT_PATCH_ + else if (i < 9) +#else + else if (i < 8) +#endif + index = 1; + else + index = 2; + + priv->RfTxPwrLevelCck[rf_path][i] = + priv->RfCckChnlAreaTxPwr[rf_path][index] = + priv->RfTxPwrLevelOfdm1T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr1T[rf_path][index] = + priv->RfTxPwrLevelOfdm2T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr2T[rf_path][index] = + (u8)(EEPROM_Default_TxPower & 0xff); + + if (rf_path == 0) + { + priv->TxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff); + priv->TxPowerLevelCCK[i] = (u8)(EEPROM_Default_TxPower & 0xff); + } + } + + } + + RT_TRACE(COMP_INIT, "All TxPwr = 0x%x\n", EEPROM_Default_TxPower); + + for(i=0; i<14; i++) + { + priv->TxPwrHt20Diff[RF90_PATH_A][i] = DEFAULT_HT20_TXPWR_DIFF; + priv->TxPwrHt20Diff[RF90_PATH_B][i] = DEFAULT_HT20_TXPWR_DIFF; + + priv->TxPwrLegacyHtDiff[0][i] = EEPROM_Default_LegacyHTTxPowerDiff; + priv->TxPwrLegacyHtDiff[1][i] = EEPROM_Default_LegacyHTTxPowerDiff; + } + + priv->TxPwrSafetyFlag = 0; +#endif + + priv->EEPROMTxPowerDiff = EEPROM_Default_LegacyHTTxPowerDiff; + priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff; + RT_TRACE(COMP_INIT, "TxPowerDiff = %#x\n", priv->EEPROMTxPowerDiff); + +#ifndef _RTL8192_EXT_PATCH_ + for (rf_path = 0; rf_path < 2; rf_path++) + { + for (i = 0; i < 3; i++) + { + priv->EEPROMPwrGroup[rf_path][i] = 0; + } + } + + for (rf_path = 0; rf_path < 2; rf_path++) + { + for(i=0; i<14; i++) + { + if (i < 3) + index = 0; + else if (i < 8) + index = 1; + else + index = 2; + priv->PwrGroupHT20[rf_path][i] = (priv->EEPROMPwrGroup[rf_path][index]&0xf); + priv->PwrGroupHT40[rf_path][i] = ((priv->EEPROMPwrGroup[rf_path][index]&0xf0)>>4); + } + } + priv->EEPROMRegulatory = 0; + +#endif + + priv->EEPROMTSSI_A = EEPROM_Default_TSSI; + priv->EEPROMTSSI_B = EEPROM_Default_TSSI; + + for(i=0; i<6; i++) + { + priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr; + } + + + priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; + priv->ThermalMeter[0] = (priv->EEPROMThermalMeter&0x1f); + priv->TSSI_13dBm = priv->EEPROMThermalMeter *100; + + priv->BluetoothCoexist = EEPROM_Default_BlueToothCoexist; + priv->EEPROMBluetoothType = EEPROM_Default_BlueToothType; + priv->EEPROMBluetoothAntNum = EEPROM_Default_BlueToothAntNum; + priv->EEPROMBluetoothAntIsolation = EEPROM_Default_BlueToothAntIso; + + priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap; + priv->CrystalCap = priv->EEPROMCrystalCap; + + priv->eeprom_ChannelPlan = 0; + priv->eeprom_version = 1; + priv->bTXPowerDataReadFromEEPORM = false; + + priv->rf_type = RTL819X_DEFAULT_RF_TYPE; + priv->rf_chip = RF_6052; + priv->eeprom_CustomerID = 0; + RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID); + + + priv->EEPROMBoardType = EEPROM_Default_BoardType; + RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType); + +#ifdef _RTL8192_EXT_PATCH_ + priv->LedStrategy = SW_LED_MODE0; +#else + priv->LedStrategy = SW_LED_MODE7; +#endif + + + RT_TRACE(COMP_INIT,"<==== rtl8192se_config_hw_for_load_fail\n"); +} + +static void rtl8192se_get_IC_Inferiority(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 Efuse_ID; + + priv->IC_Class = IC_INFERIORITY_A; + if((priv->epromtype == EEPROM_BOOT_EFUSE) && !priv->AutoloadFailFlag) + { + Efuse_ID = EFUSE_Read1Byte(dev, EFUSE_IC_ID_OFFSET); + + if(Efuse_ID == 0xfe) + { + priv->IC_Class = IC_INFERIORITY_B; + + } + } +} + +#ifdef _RTL8192_EXT_PATCH_ +void HalCustomizedBehavior8192S(struct net_device* dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + switch(priv->CustomerID) + { + case RT_CID_DEFAULT: + priv->LedStrategy = SW_LED_MODE7; + if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8171 && + priv->eeprom_svid == 0x1A3B && priv->eeprom_smid == 0x1A07) + { + priv->RegWirelessMode = WIRELESS_MODE_G; + } + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8172 && + priv->eeprom_svid == 0x1A3B && priv->eeprom_smid == 0x1A04) + { + priv->RegWirelessMode = WIRELESS_MODE_G; + } + break; + + case RT_CID_TOSHIBA: + priv->rtllib->current_network.channel = 10; + priv->LedStrategy = SW_LED_MODE7; + if(priv->eeprom_smid >= 0x7000 && priv->eeprom_smid < 0x8000) + priv->RegWirelessMode = WIRELESS_MODE_G; + break; + + case RT_CID_CCX: + priv->DMFlag |= (HAL_DM_DIG_DISABLE | HAL_DM_HIPWR_DISABLE); + break; + + case RT_CID_819x_Lenovo: + priv->LedStrategy = SW_LED_MODE7; + break; + + case RT_CID_819x_QMI: + priv->LedStrategy = SW_LED_MODE8; + break; + + case RT_CID_819x_MSI: + priv->LedStrategy = SW_LED_MODE9; + break; + + case RT_CID_WHQL: + break; + + default: + RT_TRACE(COMP_INIT,"Unkown hardware Type \n"); + break; + } +} +#else +void +HalCustomizedBehavior8192S(struct net_device* dev) +{ + struct r8192_priv* priv = rtllib_priv(dev); + priv->rtllib->bForcedShowRateStill = false; + switch(priv->CustomerID) + { + case RT_CID_DEFAULT: + priv->LedStrategy = SW_LED_MODE7; + if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8171 && + priv->eeprom_svid == 0x1A3B && priv->eeprom_smid == 0x1A07) + { + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + priv->rtllib->bForcedBgMode = true; + priv->rtllib->bForcedShowRateStill = true; + } + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8172 && + priv->eeprom_svid == 0x1A3B && priv->eeprom_smid == 0x1A04) + { + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + priv->rtllib->bForcedBgMode = true; + priv->rtllib->bForcedShowRateStill = true; + } + else if(priv->eeprom_svid == 0x1A3B && (priv->eeprom_smid == 0x1104 || + priv->eeprom_smid == 0x1107)) + { + priv->rtllib->bForcedShowRateStill = true; + } + else if(priv->eeprom_vid == 0x10ec && priv->eeprom_did == 0x8171 && + priv->eeprom_svid == 0x10ec && priv->eeprom_smid == 0x7171){ + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + priv->rtllib->bForcedBgMode = true; + }else if(priv->eeprom_vid == 0x10ec && priv->eeprom_did == 0x8174 && + priv->eeprom_svid == 0x10ec && priv->eeprom_smid == 0x7174){ + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + }else if(priv->eeprom_vid == 0x10ec && priv->eeprom_did == 0x8174 && + priv->eeprom_svid == 0x10ec && priv->eeprom_smid == 0x7150){ + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + }else if(priv->eeprom_vid == 0x10ec && priv->eeprom_did == 0x8172 && + priv->eeprom_svid == 0x10ec && priv->eeprom_smid == 0x7172){ + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + }else if(priv->eeprom_vid == 0x10ec && priv->eeprom_did == 0x8172 && + priv->eeprom_svid == 0x10ec && priv->eeprom_smid == 0x7186){ + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + } + break; + + break; + + case RT_CID_819x_Acer: + priv->LedStrategy = SW_LED_MODE7; + break; + + case RT_CID_TOSHIBA: + priv->rtllib->current_network.channel = 10; + priv->LedStrategy = SW_LED_MODE7; + priv->EEPROMRegulatory = 1; + if(priv->eeprom_smid >= 0x7000 && priv->eeprom_smid < 0x8000){ + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + priv->rtllib->bForcedBgMode = true; + } + break; + case RT_CID_CCX: + priv->DMFlag |= (HAL_DM_DIG_DISABLE | HAL_DM_HIPWR_DISABLE); + break; + + case RT_CID_819x_Lenovo: + priv->LedStrategy = SW_LED_MODE7; + if(priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0xE025){ + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + } + break; + + case RT_CID_819x_QMI: + priv->LedStrategy = SW_LED_MODE8; + if(priv->eeprom_svid == 0x1462 && priv->eeprom_smid == 0x897A){ + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->RegWirelessMode = WIRELESS_MODE_G; + priv->rtllib->mode = WIRELESS_MODE_G; + } + break; + + case RT_CID_819x_MSI: + priv->LedStrategy = SW_LED_MODE9; + break; + + case RT_CID_819x_HP: + priv->LedStrategy = SW_LED_MODE7; + priv->bLedOpenDrain = true; + + case RT_CID_WHQL: + ; + break; + + default: + RT_TRACE(COMP_INIT,"Unkown hardware Type \n"); + break; + } +} +#endif + +static void rtl8192se_read_eeprom_info(struct net_device* dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u16 i,usValue; + u16 EEPROMId; +#if (EEPROM_OLD_FORMAT_SUPPORT == 1) + u8 tmpBuffer[30]; +#endif + u8 tempval; + u8 hwinfo[HWSET_MAX_SIZE_92S]; + u8 rf_path, index; + + RT_TRACE(COMP_INIT, "====> rtl8192se_read_eeprom_info\n"); + + if (priv->epromtype== EEPROM_93C46) + { + write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); + mdelay(10); + write_nic_byte(dev, PMC_FSM, 0x02); + + RT_TRACE(COMP_INIT, "EEPROM\n"); + for(i = 0; i < HWSET_MAX_SIZE_92S; i += 2) + { + usValue = eprom_read(dev, (u16) (i>>1)); + *((u16*)(&hwinfo[i])) = usValue; + } + } + else if (priv->epromtype == EEPROM_BOOT_EFUSE) + { + RT_TRACE(COMP_INIT, "EFUSE\n"); + + EFUSE_ShadowMapUpdate(dev); + + memcpy( hwinfo, &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S); + } + + + EEPROMId = *((u16 *)&hwinfo[0]); + if( EEPROMId != RTL8190_EEPROM_ID ) + { + RT_TRACE(COMP_ERR, "EEPROM ID(%#x) is invalid!!\n", EEPROMId); + priv->AutoloadFailFlag=true; + } + else + { + RT_TRACE(COMP_EPROM, "Autoload OK\n"); + priv->AutoloadFailFlag=false; + } + + if (priv->AutoloadFailFlag == true) + { + rtl8192se_config_hw_for_load_fail(dev); + return; + } + + rtl8192se_get_IC_Inferiority(dev); + + priv->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; + priv->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; + priv->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; + priv->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; + priv->eeprom_version = *(u16 *)&hwinfo[EEPROM_Version]; + + RT_TRACE(COMP_EPROM, "EEPROMId = 0x%4x\n", EEPROMId); + RT_TRACE(COMP_EPROM, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); + RT_TRACE(COMP_EPROM, "EEPROM DID = 0x%4x\n", priv->eeprom_did); + RT_TRACE(COMP_EPROM, "EEPROM SVID = 0x%4x\n", priv->eeprom_svid); + RT_TRACE(COMP_EPROM, "EEPROM SMID = 0x%4x\n", priv->eeprom_smid); + + priv->EEPROMOptional = *(u8 *)&hwinfo[EEPROM_Optional]; + priv->ShowRateMode = 2; + priv->rtllib->bForcedShowRxRate = false; + + if(priv->ShowRateMode == 0) { + if((priv->EEPROMOptional & BIT3) == 0x08/*0000_1000*/) { + priv->rtllib->bForcedShowRxRate = true; + } + } else if(priv->ShowRateMode == 2){ + priv->rtllib->bForcedShowRxRate = true; + } + + for(i = 0; i < 6; i += 2) + { + usValue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR+i]; + *((u16*)(&dev->dev_addr[i])) = usValue; + } + for (i=0;i<6;i++) + write_nic_byte(dev, MACIDR0+i, dev->dev_addr[i]); + + RT_TRACE(COMP_EPROM, "ReadAdapterInfo8192S(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5]); + +#if (EEPROM_OLD_FORMAT_SUPPORT == 1) + for(i = 0; i < EEPROM_TX_PWR_INDEX_RANGE; i += 2) + { + usValue = *(u16 *)&hwinfo[EEPROM_TxPowerBase+i]; + *((u16 *)(&tmpBuffer[i])) = usValue; + } + for(i=0; i<14; i++) + { + priv->EEPROMTxPowerLevelCCK[i] = (u8)tmpBuffer[i]; + priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)tmpBuffer[i+14]; + } + + + for(i=0; i<14; i++) + { + priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i]; + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK[i]; + + RT_TRACE(COMP_EPROM, "CH%d CCK Tx PWR IDX = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK[i]); + RT_TRACE(COMP_EPROM, "CH%d OFDM Tx PWR IDX = 0x%02x\n", i, priv->EEPROMTxPowerLevelOFDM24G[i]); + } + + for(i = 0; i < 6; i += 2) + { + usValue = *(u16 *)&hwinfo[EEPROM_HT2T_CH1_A+i]; + *((u16*)(&priv->EEPROMHT2T_TxPwr[i])) = usValue; + } + for(i=0; i<6; i++) + { + RT_TRACE(COMP_EPROM, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n", i, priv->EEPROMHT2T_TxPwr[i]); + } + +#else + + for (rf_path = 0; rf_path < 2; rf_path++) + { + for (i = 0; i < 3; i++) + { + priv->RfCckChnlAreaTxPwr[rf_path][i] = + hwinfo[EEPROM_TxPowerBase+rf_path*3+i]; + + priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] = + hwinfo[EEPROM_TxPowerBase+6+rf_path*3+i]; + + priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] = + hwinfo[EEPROM_TxPowerBase+12+rf_path*3+i]; + } + } + + for (rf_path = 0; rf_path < 2; rf_path++) + { + for (i = 0; i < 3; i++) + { + RT_TRACE(COMP_EPROM,"CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, + priv->RfCckChnlAreaTxPwr[rf_path][i]); + RT_TRACE(COMP_EPROM, "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, + priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]); + RT_TRACE(COMP_EPROM,"OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, + priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]); + } + + for(i=0; i<14; i++) + { + if (i < 3) + index = 0; +#ifdef _RTL8192_EXT_PATCH_ + else if (i < 9) +#else + else if (i < 8) +#endif + index = 1; + else + index = 2; + + priv->RfTxPwrLevelCck[rf_path][i] = + priv->RfCckChnlAreaTxPwr[rf_path][index]; + priv->RfTxPwrLevelOfdm1T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr1T[rf_path][index]; + priv->RfTxPwrLevelOfdm2T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr2T[rf_path][index]; + + if (rf_path == 0) + { + priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ; + priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i]; + } + } + + for(i=0; i<14; i++) + { + RT_TRACE(COMP_EPROM, "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n", + rf_path, i, priv->RfTxPwrLevelCck[rf_path][i], + priv->RfTxPwrLevelOfdm1T[rf_path][i] , + priv->RfTxPwrLevelOfdm2T[rf_path][i] ); + } + } + +#ifndef _RTL8192_EXT_PATCH_ + for (rf_path = 0; rf_path < 2; rf_path++) + { + for (i = 0; i < 3; i++) + { + priv->EEPROMPwrGroup[rf_path][i] = hwinfo[EEPROM_TxPWRGroup+rf_path*3+i]; + } + } + + for (rf_path = 0; rf_path < 2; rf_path++) + { + for(i=0; i<14; i++) + { + if (i < 3) + index = 0; + else if (i < 8) + index = 1; + else + index = 2; + priv->PwrGroupHT20[rf_path][i] = (priv->EEPROMPwrGroup[rf_path][index]&0xf); + priv->PwrGroupHT40[rf_path][i] = ((priv->EEPROMPwrGroup[rf_path][index]&0xf0)>>4); + RT_TRACE(COMP_INIT, "RF-%d PwrGroupHT20[%d] = 0x%x\n", rf_path, i, priv->PwrGroupHT20[rf_path][i]); + RT_TRACE(COMP_INIT, "RF-%d PwrGroupHT40[%d] = 0x%x\n", rf_path, i, priv->PwrGroupHT40[rf_path][i]); + } + } +#endif + + for(i=0; i<14; i++) + { + if (i < 3) + index = 0; +#ifdef _RTL8192_EXT_PATCH_ + else if (i < 9) +#else + else if (i < 8) +#endif + index = 1; + else + index = 2; + + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF+index])&0xff; + priv->TxPwrHt20Diff[RF90_PATH_A][i] = (tempval&0xF); + priv->TxPwrHt20Diff[RF90_PATH_B][i] = ((tempval>>4)&0xF); + + if (i < 3) + index = 0; +#ifdef _RTL8192_EXT_PATCH_ + else if (i < 9) +#else + else if (i < 8) +#endif + index = 0x11; + else + index = 1; + + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+index])&0xff; + priv->TxPwrLegacyHtDiff[RF90_PATH_A][i] = (tempval&0xF); + priv->TxPwrLegacyHtDiff[RF90_PATH_B][i] = ((tempval>>4)&0xF); + + tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]); + priv->TxPwrSafetyFlag = (tempval&0x01); + } + +#ifndef _RTL8192_EXT_PATCH_ + priv->EEPROMRegulatory = 0; + if(priv->eeprom_version >= 2) + { + if(priv->eeprom_version >= 4) + priv->EEPROMRegulatory = (hwinfo[EEPROM_Regulatory]&0x7); + else + priv->EEPROMRegulatory = (hwinfo[EEPROM_Regulatory]&0x1); + } + RT_TRACE(COMP_INIT, "EEPROMRegulatory = 0x%x\n", priv->EEPROMRegulatory); +#endif + for(i=0; i<14; i++) + RT_TRACE(COMP_EPROM, "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_A][i]); + for(i=0; i<14; i++) + RT_TRACE(COMP_EPROM, "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_A][i]); + for(i=0; i<14; i++) + RT_TRACE(COMP_EPROM, "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_B][i]); + for(i=0; i<14; i++) + RT_TRACE(COMP_EPROM, "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_B][i]); +#endif + RT_TRACE(COMP_EPROM, "TxPwrSafetyFlag = %d\n", priv->TxPwrSafetyFlag); + + tempval = (*(u8 *)&hwinfo[EEPROM_RFInd_PowerDiff])&0xff; + priv->EEPROMTxPowerDiff = tempval; +#ifdef _RTL8192_EXT_PATCH_ + priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff; +#else + priv->LegacyHTTxPowerDiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][0]; +#endif + + RT_TRACE(COMP_EPROM, "TxPowerDiff = %#x\n", priv->EEPROMTxPowerDiff); + + usValue = *(u16 *)&hwinfo[EEPROM_TSSI_A]; + priv->EEPROMTSSI_A = (u8)((usValue&0xff00)>>8); + usValue = *(u8 *)&hwinfo[EEPROM_TSSI_B]; + priv->EEPROMTSSI_B = (u8)(usValue&0xff); + RT_TRACE(COMP_EPROM, "TSSI_A = %#x, TSSI_B = %#x\n", + priv->EEPROMTSSI_A, priv->EEPROMTSSI_B); + + tempval = *(u8 *)&hwinfo[EEPROM_ThermalMeter]; + priv->EEPROMThermalMeter = tempval; + RT_TRACE(COMP_EPROM, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter); + priv->ThermalMeter[0] =(priv->EEPROMThermalMeter&0x1f); + priv->TSSI_13dBm = priv->EEPROMThermalMeter *100; + + tempval = *(u8 *)&hwinfo[EEPROM_BLUETOOTH_COEXIST]; + priv->EEPROMBluetoothCoexist = ((tempval&0x2)>>1); + priv->BluetoothCoexist = priv->EEPROMBluetoothCoexist; + tempval = hwinfo[EEPROM_BLUETOOTH_TYPE]; + priv->EEPROMBluetoothType = ((tempval&0xe)>>1); + priv->EEPROMBluetoothAntNum = (tempval&0x1); + priv->EEPROMBluetoothAntIsolation = ((tempval&0x10)>>4); + RT_TRACE(COMP_EPROM, "BlueTooth Coexistance = %#x\n", priv->BluetoothCoexist); + +#ifdef MERGE_TO_DO + BT_VAR_INIT(Adapter); + + tempval = hwinfo[EEPROM_WoWLAN]; + priv->EEPROMSupportWoWLAN = ((tempval&0x4)>>2); + if (priv->EEPROMSupportWoWLAN) + priv->bHwSupportRemoteWakeUp = true; + else + priv->bHwSupportRemoteWakeUp = false; +#endif +#ifdef RTL8192S_WAPI_SUPPORT + tempval = *(u8 *)&hwinfo[EEPROM_WAPI_SUPPORT]; + priv->EEPROMWapiSupport = ((tempval&0x10)>>4); + priv->EEPROMWapiSupport = 1; + + priv->WapiSupport = priv->EEPROMWapiSupport; + priv->rtllib->WapiSupport = priv->WapiSupport; + RT_TRACE(COMP_EPROM, "WAPI Support = %#x\n", priv->WapiSupport); +#endif + + tempval = (*(u8 *)&hwinfo[EEPROM_CrystalCap])>>4; + priv->EEPROMCrystalCap =tempval; + RT_TRACE(COMP_EPROM, "CrystalCap = %#x\n", priv->EEPROMCrystalCap); + priv->CrystalCap = priv->EEPROMCrystalCap; + + priv->eeprom_ChannelPlan = *(u8 *)&hwinfo[EEPROM_ChannelPlan]; +#ifdef _RTL8192_EXT_PATCH_ + priv->eeprom_version = *(u16 *)&hwinfo[EEPROM_Version]; +#endif + priv->bTXPowerDataReadFromEEPORM = true; + RT_TRACE(COMP_EPROM, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan); + + tempval = *(u8*)&hwinfo[EEPROM_BoardType]; + if (tempval == 0) + priv->rf_type= RF_2T2R; + else if (tempval == 1) + priv->rf_type = RF_1T2R; + else if (tempval == 2) + priv->rf_type = RF_1T2R; + else if (tempval == 3) + priv->rf_type = RF_1T1R; + + priv->rtllib->RF_Type = priv->rf_type; + priv->rtllib->b1x1RecvCombine = false; + if (priv->rf_type == RF_1T2R) + { + tempval = read_nic_byte(dev, 0x07); + if (!(tempval & BIT0)) + { + priv->rtllib->b1x1RecvCombine = true; + RT_TRACE(COMP_INIT, "RF_TYPE=1T2R but only 1SS\n"); + } + } + priv->rtllib->b1SSSupport = priv->rtllib->b1x1RecvCombine; + + priv->rf_chip = RF_6052; + + priv->eeprom_CustomerID = *(u8 *)&hwinfo[EEPROM_CustomID]; + + RT_TRACE(COMP_EPROM, "EEPROM Customer ID: 0x%2x, rf_chip:%x\n", priv->eeprom_CustomerID, priv->rf_chip); + + priv->rtllib->b_customer_lenovo_id = false; + + switch(priv->eeprom_CustomerID) + { + case EEPROM_CID_DEFAULT: + if(priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0xE020){ + priv->CustomerID = RT_CID_819x_Lenovo; + priv->rtllib->b_customer_lenovo_id = true; + } + else if(priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0xE025) + priv->CustomerID = RT_CID_819x_Lenovo; + else if(priv->eeprom_svid == 0x1A32 && priv->eeprom_smid == 0x4308) + priv->CustomerID = RT_CID_819x_QMI; + else if(priv->eeprom_svid == 0x1A32 && priv->eeprom_smid == 0x0311) + priv->CustomerID = RT_CID_819x_QMI; + else if(priv->eeprom_svid == 0x1462 && priv->eeprom_smid == 0x6897) + priv->CustomerID = RT_CID_819x_MSI; + else if(priv->eeprom_svid == 0x1462 && priv->eeprom_smid == 0x3821) + priv->CustomerID = RT_CID_819x_MSI; + else if(priv->eeprom_svid == 0x1462 && priv->eeprom_smid == 0x897A) + priv->CustomerID = RT_CID_819x_MSI; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8171 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0x8156) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8171 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0x8157) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8172 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0xE021) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8172 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0xE022) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8172 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0x8158) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8172 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0x8159) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8174 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0x8186) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8174 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0x8187) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8174 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0x8156) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8174 && + priv->eeprom_svid == 0x10EC && priv->eeprom_smid == 0x8157) + priv->CustomerID = RT_CID_819x_Acer; + else if( priv->eeprom_vid == 0x10EC && priv->eeprom_did == 0x8171 && + priv->eeprom_svid == 0x103C && priv->eeprom_smid == 0x1467) + priv->CustomerID = RT_CID_819x_HP; + else + priv->CustomerID = RT_CID_DEFAULT; + break; + + case EEPROM_CID_TOSHIBA: + priv->CustomerID = RT_CID_TOSHIBA; + break; + + case EEPROM_CID_QMI: + priv->CustomerID = RT_CID_819x_QMI; + break; + + case EEPROM_CID_WHQL: +#ifdef TO_DO_LIST + priv->bInHctTest = true; + priv->bSupportTurboMode = false; + priv->bAutoTurboBy8186 = false; + priv->PowerSaveControl.bInactivePs = false; + priv->PowerSaveControl.bIPSModeBackup = false; + priv->PowerSaveControl.bLeisurePs = false; + priv->keepAliveLevel = 0; + priv->bUnloadDriverwhenS3S4 = false; +#endif + break; + + default: + priv->CustomerID = RT_CID_DEFAULT; + break; + + } + +#ifdef _RTL8192_EXT_PATCH_ + HalCustomizedBehavior8192S(dev); +#endif + +#if defined (RTL8192S_WAPI_SUPPORT) + if (priv->rtllib->WapiSupport) + { + WapiInit(priv->rtllib); + } +#endif + RT_TRACE(COMP_INIT, "<==== rtl8192se_read_eeprom_info\n"); +} + +void rtl8192se_get_eeprom_size(struct net_device* dev) +{ + struct r8192_priv* priv = rtllib_priv(dev); + u8 curCR = 0; + curCR = read_nic_byte(dev, EPROM_CMD); + PHY_RFShadowRefresh(dev); + if (curCR & BIT4){ + RT_TRACE(COMP_EPROM, "Boot from EEPROM\n"); + priv->epromtype = EEPROM_93C46; + } + else{ + RT_TRACE(COMP_EPROM, "Boot from EFUSE\n"); + priv->epromtype = EEPROM_BOOT_EFUSE; + } + if (curCR & BIT5){ + RT_TRACE(COMP_EPROM,"Autoload OK\n"); + priv->AutoloadFailFlag=false; + rtl8192se_read_eeprom_info(dev); + } + else{ + RT_TRACE(COMP_INIT, "AutoLoad Fail reported from CR9346!!\n"); + priv->AutoloadFailFlag=true; + rtl8192se_config_hw_for_load_fail(dev); + + if (priv->epromtype == EEPROM_BOOT_EFUSE) + { +#if (RTL92SE_FPGA_VERIFY == 0) + EFUSE_ShadowMapUpdate(dev); +#endif + } + } +#ifdef TO_DO_LIST + if(Adapter->bInHctTest) + { + pMgntInfo->PowerSaveControl.bInactivePs = false; + pMgntInfo->PowerSaveControl.bIPSModeBackup = false; + pMgntInfo->PowerSaveControl.bLeisurePs = false; + pMgntInfo->keepAliveLevel = 0; + } + + switch(pHalData->eeprom_CustomerID) + { + case EEPROM_CID_DEFAULT: + pMgntInfo->CustomerID = RT_CID_DEFAULT; + break; + case EEPROM_CID_TOSHIBA: + pMgntInfo->CustomerID = RT_CID_TOSHIBA; + break; + default: + break; + } + +#ifdef _RTL8192_EXT_PATCH_ + if(pHalData->eeprom_svid == 0x10EC && pHalData->eeprom_smid == 0xE020) +#else + if(pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0xE020) +#endif + pMgntInfo->CustomerID = RT_CID_819x_Lenovo; +#endif +#ifdef ENABLE_DOT11D + priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13; + + if(priv->ChannelPlan == COUNTRY_CODE_GLOBAL_DOMAIN) { + GET_DOT11D_INFO(priv->rtllib)->bEnabled = 1; + RT_TRACE(COMP_INIT, "%s: Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n", __FUNCTION__); + } +#endif + + RT_TRACE(COMP_INIT, "RegChannelPlan(%d) EEPROMChannelPlan(%d)", \ + priv->RegChannelPlan, priv->eeprom_ChannelPlan); + RT_TRACE(COMP_INIT, "ChannelPlan = %d\n" , priv->ChannelPlan); +#ifndef _RTL8192_EXT_PATCH_ + HalCustomizedBehavior8192S(dev); +#endif +} + +#if (RTL92SE_FPGA_VERIFY == 1) +static void MacConfigBeforeFwDownload(struct net_device* dev) +{ + struct r8192_priv* priv = rtllib_priv(dev); + u8 i; + u8 tmpU1b; + u16 tmpU2b; + u32 addr; + + RT_TRACE(COMP_INIT, "Set some register before enable NIC\r\n"); + + tmpU1b = read_nic_byte(dev, 0x562); + tmpU1b |= 0x08; + write_nic_byte(dev, 0x562, tmpU1b); + tmpU1b &= ~(BIT3); + write_nic_byte(dev, 0x562, tmpU1b); + + tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1); + tmpU1b &= 0x73; + write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b); + + tmpU1b = read_nic_byte(dev, SYS_CLKR); + tmpU1b &= 0xfa; + write_nic_byte(dev, SYS_CLKR, tmpU1b); + + RT_TRACE(COMP_INIT, "Delay 1000ms before reset NIC. I dont know how long should we delay!!!!!\r\n"); + ssleep(1); + + write_nic_byte(dev, SYS_CLKR, SYS_CLKSEL_80M); + + tmpU1b = read_nic_byte(dev, SPS1_CTRL); + write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_LDEN)); + + tmpU1b = read_nic_byte(dev, AFE_MISC); + write_nic_byte(dev, AFE_MISC, (tmpU1b|AFE_BGEN)); + + tmpU1b = read_nic_byte(dev, LDOA15_CTRL); + write_nic_byte(dev, LDOA15_CTRL, (tmpU1b|LDA15_EN)); + + tmpU1b = read_nic_byte(dev, SPS1_CTRL); + write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_SWEN)); + + tmpU1b = read_nic_byte(dev, AFE_MISC); + write_nic_byte(dev, AFE_MISC, (tmpU1b|AFE_MBEN)); + + tmpU2b = read_nic_word(dev, SYS_ISO_CTRL); + write_nic_word(dev, SYS_ISO_CTRL, (tmpU2b|ISO_PWC_DV2RP)); + + tmpU2b = read_nic_word(dev, SYS_ISO_CTRL); + write_nic_word(dev, SYS_ISO_CTRL, (tmpU2b &(~ISO_PWC_RV2RP))); + + tmpU2b = read_nic_word(dev, AFE_XTAL_CTRL); + write_nic_word(dev, AFE_XTAL_CTRL, (tmpU2b &(~XTAL_GATE_AFE))); + + tmpU1b = read_nic_byte(dev, AFE_PLL_CTRL); + write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|APLL_EN)); + + write_nic_byte(dev, SYS_ISO_CTRL, 0xEE); + + tmpU2b = read_nic_word(dev, SYS_CLKR); + write_nic_word(dev, SYS_CLKR, (tmpU2b|SYS_MAC_CLK_EN)); + + tmpU2b = read_nic_word(dev, SYS_FUNC_EN); + write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|FEN_DCORE|FEN_MREGEN)); + + tmpU2b = read_nic_word(dev, SYS_CLKR); + write_nic_word(dev, SYS_CLKR, ((tmpU2b|SYS_FWHW_SEL)&(~SYS_SWHW_SEL))); + + write_nic_byte(dev, RF_CTRL, 0); + write_nic_byte(dev, RF_CTRL, 7); + + write_nic_word(dev, CMDR, 0x37FC); + +#if 1 + write_nic_byte(dev, 0x6, 0x30); + write_nic_byte(dev, 0x49, 0xf0); + + write_nic_byte(dev, 0x4b, 0x81); + + write_nic_byte(dev, 0xb5, 0x21); + + write_nic_byte(dev, 0xdc, 0xff); + write_nic_byte(dev, 0xdd, 0xff); + write_nic_byte(dev, 0xde, 0xff); + write_nic_byte(dev, 0xdf, 0xff); + + write_nic_byte(dev, 0x11a, 0x00); + write_nic_byte(dev, 0x11b, 0x00); + + for (i = 0; i < 32; i++) + write_nic_byte(dev, INIMCS_SEL+i, 0x1b); + + write_nic_byte(dev, 0x236, 0xff); + + write_nic_byte(dev, 0x503, 0x22); + + if(priv->bIntelBridgeExist) { + write_nic_byte(dev, 0x560, 0x40); +#ifndef _RTL8192_EXT_PATCH_ + } else { + write_nic_byte(dev, 0x560, 0x00); +#endif + } + + write_nic_byte(dev, DBG_PORT, 0x91); +#endif + +#ifdef CONFIG_RX_CMD + write_nic_dword(dev, RCDA, priv->rx_ring_dma[RX_CMD_QUEUE]); +#endif + write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]); + rtl8192_tx_enable(dev); + + RT_TRACE(COMP_INIT, "<---MacConfig8192SE()\n"); + +} /* MacConfigBeforeFwDownload */ +#else +void gen_RefreshLedState(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + PLED_8190 pLed0 = &(priv->SwLed0); + + if(priv->bfirst_init) + { + RT_TRACE(COMP_INIT, "gen_RefreshLedState first init\n"); + return; + } + + if(priv->rtllib->RfOffReason == RF_CHANGE_BY_IPS ) + { + SwLedOn(dev, pLed0); + } + else + { + SwLedOff(dev, pLed0); + } + +} +static void MacConfigBeforeFwDownload(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 i; + u8 tmpU1b; + u16 tmpU2b; + u8 PollingCnt = 20; + + RT_TRACE(COMP_INIT, "--->MacConfigBeforeFwDownload()\n"); + + if(priv->bfirst_init) + { + tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1); + tmpU1b &= 0xFE; + write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b); + udelay(1); + write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b|BIT0); + } + + tmpU1b = read_nic_byte(dev, (SYS_CLKR + 1)); + if(tmpU1b & BIT7) + { + tmpU1b &= ~(BIT6 | BIT7); + if(!HalSetSysClk8192SE(dev, tmpU1b)) + return; + } + +#ifdef MERGE_TO_DO + if( (pHalData->bt_coexist.BluetoothCoexist) && + (pHalData->bt_coexist.BT_CoexistType == BT_CSR) ) + { + write_nic_byte(dev, AFE_PLL_CTRL, 0x0); + udelay(50); + write_nic_byte(dev, LDOA15_CTRL, 0x34); + udelay(50); + } + else +#endif + { + write_nic_byte(dev, AFE_PLL_CTRL, 0x0); + udelay(50); + write_nic_byte(dev, LDOA15_CTRL, 0x34); + udelay(50); + } + + + write_nic_byte(dev, RPWM, 0x0); + + tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1); + tmpU1b &= 0x73; + write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b); + mdelay(1); + + write_nic_byte(dev, CMDR, 0); + write_nic_byte(dev, TCR, 0); + +#if (DEMO_BOARD_SUPPORT == 0) + tmpU1b = read_nic_byte(dev, SPS1_CTRL); + tmpU1b &= 0xfc; + write_nic_byte(dev, SPS1_CTRL, tmpU1b); +#endif + + tmpU1b = read_nic_byte(dev, 0x562); + tmpU1b |= 0x08; + write_nic_byte(dev, 0x562, tmpU1b); + tmpU1b &= ~(BIT3); + write_nic_byte(dev, 0x562, tmpU1b); + + + + + + RT_TRACE(COMP_INIT, "Enable AFE clock source\r\n"); + tmpU1b = read_nic_byte(dev, AFE_XTAL_CTRL); + write_nic_byte(dev, AFE_XTAL_CTRL, (tmpU1b|0x01)); + udelay(2000); + tmpU1b = read_nic_byte(dev, AFE_XTAL_CTRL+1); + write_nic_byte(dev, AFE_XTAL_CTRL+1, (tmpU1b&0xfb)); + + + RT_TRACE(COMP_INIT, "Enable AFE Macro Block's Bandgap\r\n"); + tmpU1b = read_nic_byte(dev, AFE_MISC); + write_nic_byte(dev, AFE_MISC, (tmpU1b|BIT0)); + mdelay(1); + + RT_TRACE(COMP_INIT, "Enable AFE Mbias\r\n"); + tmpU1b = read_nic_byte(dev, AFE_MISC); + write_nic_byte(dev, AFE_MISC, (tmpU1b|0x02)); + mdelay(1); + + tmpU1b = read_nic_byte(dev, LDOA15_CTRL); + write_nic_byte(dev, LDOA15_CTRL, (tmpU1b|BIT0)); + + + + tmpU2b = read_nic_word(dev, SYS_ISO_CTRL); + write_nic_word(dev, SYS_ISO_CTRL, (tmpU2b|BIT11)); + + + tmpU2b = read_nic_word(dev, SYS_FUNC_EN); +#ifdef _RTL8192_EXT_PATCH_ + write_nic_word(dev, SYS_FUNC_EN, tmpU2b |= BIT13); +#else + write_nic_word(dev, SYS_FUNC_EN, (tmpU2b |BIT13)); +#endif + + + write_nic_byte(dev, SYS_ISO_CTRL+1, 0x68); + + udelay(200); + tmpU1b = read_nic_byte(dev, AFE_PLL_CTRL); + write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|BIT0|BIT4)); + +#if 1 + udelay(100); + write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|BIT0|BIT4|BIT6)); + udelay(10); + write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|BIT0|BIT4)); + udelay(10); +#endif + tmpU1b = read_nic_byte(dev, AFE_PLL_CTRL+1); + write_nic_byte(dev, AFE_PLL_CTRL+1, (tmpU1b|BIT0)); + mdelay(1); + + write_nic_byte(dev, SYS_ISO_CTRL, 0xA6); + + tmpU2b = read_nic_word(dev, SYS_CLKR); + write_nic_word(dev, SYS_CLKR, (tmpU2b|BIT12|BIT11)); + + tmpU2b = read_nic_word(dev, SYS_FUNC_EN); + write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|BIT11)); + + tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1); + write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b&~(BIT7)); + + write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|BIT11|BIT15)); + + tmpU2b = read_nic_word(dev, SYS_CLKR); + write_nic_word(dev, SYS_CLKR, (tmpU2b&(~BIT2))); + + tmpU1b = read_nic_byte(dev, (SYS_CLKR + 1)); + tmpU1b = ((tmpU1b | BIT7) & (~BIT6)); + if(!HalSetSysClk8192SE(dev, tmpU1b)) + return; + +#if 0 + tmpU2b = read_nic_word(dev, SYS_CLKR); + write_nic_word(dev, SYS_CLKR, ((tmpU2b|BIT15)&(~BIT14))); +#endif + + write_nic_word(dev, CMDR, 0x07FC); + +#if 1 + write_nic_byte(dev, 0x6, 0x30); + write_nic_byte(dev, 0x49, 0xf0); + + write_nic_byte(dev, 0x4b, 0x81); + + write_nic_byte(dev, 0xb5, 0x21); + + write_nic_byte(dev, 0xdc, 0xff); + write_nic_byte(dev, 0xdd, 0xff); + write_nic_byte(dev, 0xde, 0xff); + write_nic_byte(dev, 0xdf, 0xff); + + write_nic_byte(dev, 0x11a, 0x00); + write_nic_byte(dev, 0x11b, 0x00); + + for (i = 0; i < 32; i++) + write_nic_byte(dev, INIMCS_SEL+i, 0x1b); + + write_nic_byte(dev, 0x236, 0xff); + + write_nic_byte(dev, 0x503, 0x22); + if (priv->pci_bridge_vendor & (PCI_BRIDGE_VENDOR_INTEL | PCI_BRIDGE_VENDOR_SIS)) { + write_nic_byte(dev, 0x560, 0x40); + } else { + write_nic_byte(dev, 0x560, 0x00); + } + + write_nic_byte(dev, DBG_PORT, 0x91); +#endif + + write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]); +#ifdef CONFIG_RX_CMD + write_nic_dword(dev, RCDA, priv->rx_ring_dma[RX_CMD_QUEUE]); +#endif + rtl8192_tx_enable(dev); + + write_nic_word(dev, CMDR, 0x37FC); + do { + tmpU1b = read_nic_byte(dev, TCR); + if((tmpU1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE) + break; + + udelay(5); + } while(PollingCnt--); + + if(PollingCnt <= 0 ) + { + RT_TRACE(COMP_ERR, "MacConfigBeforeFwDownloadASIC(): Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", tmpU1b); + tmpU1b = read_nic_byte(dev, CMDR); + write_nic_byte(dev, CMDR, tmpU1b&(~TXDMA_EN)); + udelay(2); + write_nic_byte(dev, CMDR, tmpU1b|TXDMA_EN); + } + + gen_RefreshLedState(dev); + + RT_TRACE(COMP_INIT, "<---MacConfigBeforeFwDownload()\n"); + +} /* MacConfigBeforeFwDownload */ +#endif + +static void MacConfigAfterFwDownload(struct net_device* dev) +{ + u8 i; + u16 tmpU2b; + struct r8192_priv* priv = rtllib_priv(dev); + + +#ifdef _RTL8192_EXT_PATCH_ + write_nic_word(dev, CMDR, + BBRSTn|BB_GLB_RSTn|SCHEDULE_EN|MACRXEN|MACTXEN|DDMA_EN|FW2HW_EN| + RXDMA_EN|TXDMA_EN|HCI_RXDMA_EN|HCI_TXDMA_EN); +#else + write_nic_byte(dev, CMDR, + (u8)(BBRSTn|BB_GLB_RSTn|SCHEDULE_EN|MACRXEN|MACTXEN|DDMA_EN|FW2HW_EN| + RXDMA_EN|TXDMA_EN|HCI_RXDMA_EN|HCI_TXDMA_EN)); +#endif + write_nic_dword(dev, TCR, + read_nic_dword(dev, TCR)|TXDMAPRE2FULL); + write_nic_dword(dev, RCR, priv->ReceiveConfig); + +#if 0 + for (i=0;i<6;i++) + write_nic_byte(dev, MACIDR0+i, dev->dev_addr[i]); +#endif + write_nic_word(dev, SIFS_CCK, 0x0a0a); + write_nic_word(dev, SIFS_OFDM, 0x1010); + write_nic_byte(dev, ACK_TIMEOUT, 0x40); + + write_nic_word(dev, BCN_INTERVAL, 100); + write_nic_word(dev, ATIMWND, 2); +#ifdef _ENABLE_SW_BEACON + write_nic_word(dev, BCN_DRV_EARLY_INT, BIT15); +#endif + +#if 0 + write_nic_dword(dev, RQPN1, + NUM_OF_PAGE_IN_FW_QUEUE_BK<<0 | NUM_OF_PAGE_IN_FW_QUEUE_BE<<8 |\ + NUM_OF_PAGE_IN_FW_QUEUE_VI<<16 | NUM_OF_PAGE_IN_FW_QUEUE_VO<<24); + write_nic_dword(dev, RQPN2, + NUM_OF_PAGE_IN_FW_QUEUE_HCCA << 0 | NUM_OF_PAGE_IN_FW_QUEUE_CMD << 8|\ + NUM_OF_PAGE_IN_FW_QUEUE_MGNT << 16 |NUM_OF_PAGE_IN_FW_QUEUE_HIGH << 24); + write_nic_dword(dev, RQPN3, + NUM_OF_PAGE_IN_FW_QUEUE_BCN<<0 | NUM_OF_PAGE_IN_FW_QUEUE_PUB<<8); + write_nic_byte(dev, LD_RQPN, BIT7); +#endif + + + + + write_nic_byte(dev, RXDMA, + read_nic_byte(dev, RXDMA)|BIT6); + + if (priv->card_8192_version== VERSION_8192S_ACUT) + write_nic_byte(dev, RRSR, 0xf0); +#ifdef _RTL8192_EXT_PATCH_ +#endif + write_nic_byte(dev, RRSR+1, 0x01); + write_nic_byte(dev, RRSR+2, 0x00); + + for (i = 0; i < 8; i++) + { + + if (priv->card_8192_version == VERSION_8192S_ACUT) + write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0); + else if (priv->card_8192_version == VERSION_8192S_BCUT) + write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0); + } + + write_nic_byte(dev, AGGLEN_LMT_H, 0x0f); + write_nic_word(dev, AGGLEN_LMT_L, 0x7442); + write_nic_word(dev, AGGLEN_LMT_L+2, 0xddd7); + write_nic_word(dev, AGGLEN_LMT_L+4, 0xd772); + write_nic_word(dev, AGGLEN_LMT_L+6, 0xfffd); + + write_nic_dword(dev, DARFRC, 0x04010000); + write_nic_dword(dev, DARFRC+4, 0x09070605); + write_nic_dword(dev, RARFRC, 0x04010000); + write_nic_dword(dev, RARFRC+4, 0x09070605); + + + + write_nic_word(dev, SG_RATE, 0xFFFF); + + + write_nic_word(dev, NAV_PROT_LEN, 0x0080); + write_nic_byte(dev, CFEND_TH, 0xFF); + write_nic_byte(dev, AMPDU_MIN_SPACE, 0x07); + write_nic_byte(dev, TXOP_STALL_CTRL, 0x00); + + + /*write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) | \ + (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) | \ + (1<<MULRW_SHIFT)));*/ + + write_nic_byte(dev, RXDRVINFO_SZ, 4); + + tmpU2b= read_nic_byte(dev, SYS_FUNC_EN); + write_nic_byte(dev, SYS_FUNC_EN, tmpU2b | BIT13); + tmpU2b= read_nic_byte(dev, SYS_ISO_CTRL); + write_nic_byte(dev, SYS_ISO_CTRL, tmpU2b & (~BIT8)); + + if (priv->epromtype == EEPROM_BOOT_EFUSE) + { + u8 tempval; + + tempval = read_nic_byte(dev, SYS_ISO_CTRL+1); + tempval &= 0xFE; + write_nic_byte(dev, SYS_ISO_CTRL+1, tempval); + + + + write_nic_byte(dev, EFUSE_CTRL+3, 0x72); + RT_TRACE(COMP_INIT, "EFUSE CONFIG OK\n"); + } + RT_TRACE(COMP_INIT, "MacConfigAfterFwDownload OK\n"); + +} /* MacConfigAfterFwDownload */ + +static void rtl8192se_HalDetectPwrDownMode(struct net_device*dev) +{ + u8 tmpvalue; + struct r8192_priv *priv = rtllib_priv(dev); + EFUSE_ShadowRead(dev, 1, 0x78, (u32 *)&tmpvalue); + + if (tmpvalue & BIT0) { + priv->pwrdown = true; + } else { + priv->pwrdown = false; + } +} + +void HwConfigureRTL8192SE(struct net_device *dev) +{ + + struct r8192_priv* priv = rtllib_priv(dev); + + u8 regBwOpMode = 0; + u32 regRATR = 0, regRRSR = 0; + u8 regTmp = 0; + + + switch(priv->rtllib->mode) + { + case WIRELESS_MODE_B: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK; + regRRSR = RATE_ALL_CCK; + break; + case WIRELESS_MODE_A: + regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ; + regRATR = RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_G: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_AUTO: + case WIRELESS_MODE_N_24G: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_N_5G: + regBwOpMode = BW_OPMODE_5G; + regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_OFDM_AG; + break; + default: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + } + + regTmp = read_nic_byte(dev, INIRTSMCS_SEL); +#if (RTL8192SU_DISABLE_CCK_RATE == 1) + regRRSR = ((regRRSR & 0x000ffff0)<<8) | regTmp; +#else + regRRSR = ((regRRSR & 0x000fffff)<<8) | regTmp; +#endif + write_nic_dword(dev, INIRTSMCS_SEL, regRRSR); + + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + priv->rtllib->SetHwRegHandler(dev, HW_VAR_RETRY_LIMIT, (u8*)(&priv->ShortRetryLimit)); + + write_nic_byte(dev, MLT, 0x8f); + + + +#if 1 + switch(priv->rf_type) + { + case RF_1T2R: + case RF_1T1R: + RT_TRACE(COMP_INIT, "Initializeadapter: RF_Type%s\n", priv->rf_type==RF_1T1R? "(1T1R)":"(1T2R)"); + priv->rtllib->MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3); + break; + case RF_2T2R: + case RF_2T2R_GREEN: + RT_TRACE(COMP_INIT, "Initializeadapter:RF_Type(2T2R)\n"); + priv->rtllib->MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3); + break; + } + write_nic_byte(dev, AMPDU_MIN_SPACE, priv->rtllib->MinSpaceCfg); +#else + priv->rtllib->MinSpaceCfg = 0x90; + SetHwReg8192SE(dev, HW_VAR_AMPDU_MIN_SPACE, (u8*)(&priv->rtllib->MinSpaceCfg)); +#endif +} + +void +RF_RECOVERY(struct net_device*dev ,u8 Start, u8 End) +{ + u8 offset; + u8 counter; + + + for(offset = Start; offset<End; offset++) + { + PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)0, offset,true); + + if(PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)0, offset)) + { + PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)0, offset, true); + + for (counter = 0; counter < 10; counter++) + { + RT_TRACE(COMP_INIT, "PHY_RFShadowCompare OKCNT=%d offset=%0x\n", counter, offset); + PHY_RFShadowRecorver( dev, (RF90_RADIO_PATH_E)0, offset); + if (offset == 0x18) + { + if (!PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)0, offset)) + { + RT_TRACE(COMP_INIT, "PHY_RFShadowCompare OKCNT=%d\n", counter); + PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)0, offset, false); + break; + } + } + else + { + PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)0, offset, false); + break; + } + } +} + } + +} + +bool rtl8192se_adapter_start(struct net_device* dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool rtStatus = true; + u8 tmpU1b; + u8 eRFPath; + u8 fw_download_times = 1; + u8 i=0; + RT_TRACE(COMP_INIT, "rtl8192se_adapter_start()\n"); + priv->being_init_adapter = true; +#ifdef CONFIG_ASPM_OR_D3 + RT_DISABLE_ASPM(dev); +#endif +start: + rtl8192_pci_resetdescring(dev); + MacConfigBeforeFwDownload(dev); + + priv->card_8192_version = priv->rtllib->VersionID + = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF); + + RT_TRACE(COMP_INIT, "NIC version : %s\n", ((read_nic_dword(dev, PMC_FSM)>>15)&0x1)?"C-cut":"B-cut"); + + rtStatus = FirmwareDownload92S((struct net_device*)dev); + if(rtStatus != true) + { + if(fw_download_times <= 10){ + RT_TRACE(COMP_INIT, "rtl8192se_adapter_start(): Download Firmware failed %d times, Download again!!\n",fw_download_times); + fw_download_times = fw_download_times + 1; + goto start; + }else{ + RT_TRACE(COMP_INIT, "rtl8192se_adapter_start(): Download Firmware failed 10, end!!\n"); + goto end; + } + } + + MacConfigAfterFwDownload(dev); + + priv->FwCmdIOMap = read_nic_word(dev, LBUS_MON_ADDR); + priv->FwCmdIOParam = read_nic_dword(dev, LBUS_ADDR_MASK); + + +#if (RTL8192S_DISABLE_FW_DM == 1) + write_nic_dword(dev, WFM5, FW_DM_DISABLE); + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_TXANT_SWITCH_DISABLE); + ChkFwCmdIoDone(dev); +#endif + +#if (HAL_MAC_ENABLE == 1) + RT_TRACE(COMP_INIT, "MAC Config Start!\n"); + if (PHY_MACConfig8192S(dev) != true) + { + RT_TRACE(COMP_ERR, "MAC Config failed\n"); + return rtStatus; + } + RT_TRACE(COMP_INIT, "MAC Config Finished!\n"); +#endif + + write_nic_dword(dev, CMDR, 0x37FC); + +#if (HAL_BB_ENABLE == 1) + RT_TRACE(COMP_INIT, "BB Config Start!\n"); + if (PHY_BBConfig8192S(dev) != true) + { + RT_TRACE(COMP_INIT, "BB Config failed\n"); + return rtStatus; + } + RT_TRACE(COMP_INIT, "BB Config Finished!\n"); +#endif + + + priv->Rf_Mode = RF_OP_By_SW_3wire; +#if (HAL_RF_ENABLE == 1) + RT_TRACE(COMP_INIT, "RF Config started!\n"); + +#if (RTL92SE_FPGA_VERIFY == 0) + write_nic_byte(dev, AFE_XTAL_CTRL+1, 0xDB); + if(priv->card_8192_version== VERSION_8192S_ACUT) + write_nic_byte(dev, SPS1_CTRL+3, 0x07); + else + write_nic_byte(dev, RF_CTRL, 0x07); +#endif + if(PHY_RFConfig8192S(dev) != true) + { + RT_TRACE(COMP_ERR, "RF Config failed\n"); + return rtStatus; + } + RT_TRACE(COMP_INIT, "RF Config Finished!\n"); +#endif + + + priv->RfRegChnlVal[0] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask); + priv->RfRegChnlVal[1] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask); + + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); + + HwConfigureRTL8192SE(dev); + + if(priv->ResetProgress == RESET_TYPE_NORESET) + rtl8192_SetWirelessMode(dev, priv->rtllib->mode); + CamResetAllEntry(dev); + { + u8 SECR_value = 0x0; + SECR_value |= SCR_TxEncEnable; + SECR_value |= SCR_RxDecEnable; + SECR_value |= SCR_NoSKMC; + write_nic_byte(dev, SECR, SECR_value); + } + + { + int i; + for (i=0; i<4; i++) + write_nic_dword(dev, WDCAPARA_ADD[i], 0x5e4322); + } + { + PHY_GetHWRegOriginalValue(dev); +#ifndef CONFIG_MP + rtl8192_phy_setTxPower(dev, priv->chan); +#endif + } + + rtl8192se_HalDetectPwrDownMode(dev); +#if 1 + if(priv->RegRfOff == true) + { + RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8190(): Turn off RF for RegRfOff ----------\n"); + MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW); + + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); + + } + else if(priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) + { + RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8190(): Turn off RF for RfOffReason(%d) ----------\n", priv->rtllib->RfOffReason); + MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason); + } + else + { + if(priv->bHwRadioOff == false){ + priv->rtllib->eRFPowerState = eRfOn; + priv->rtllib->RfOffReason = 0; + if(priv->rtllib->LedControlHandler) + priv->rtllib->LedControlHandler(dev, LED_CTL_POWER_ON); + } + } +#endif + + + + { + int i; + for (i=0;i<6;i++) + write_nic_byte(dev, MACIDR0+i, dev->dev_addr[i]); + } + + tmpU1b = read_nic_byte(dev, MAC_PINMUX_CFG); + write_nic_byte(dev, MAC_PINMUX_CFG, tmpU1b&(~BIT3)); + + if(priv->CustomerID == RT_CID_CCX) + { + RT_TRACE(COMP_INIT ,"InitializeAdapter8192SE(): Set FW Cmd FW_TX_FEEDBACK_CCX_ENABLE\n"); + write_nic_dword(dev, WFM5, FW_TX_FEEDBACK_CCX_ENABLE); + ChkFwCmdIoDone(dev); + + write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_DIG_HALT); + ChkFwCmdIoDone(dev); + + write_nic_byte(dev, 0xC50, 0x1C); + write_nic_byte(dev, 0xC58, 0x1C); + } + + if(priv->pFirmware->FirmwareVersion >= 0x49){ + u8 tmp_byte = 0; + + tmp_byte = read_nic_byte(dev, FW_RSVD_PG_CRTL) & (~BIT4); + tmp_byte = tmp_byte | BIT5; + write_nic_byte(dev, FW_RSVD_PG_CRTL, tmp_byte); + + write_nic_dword(dev, TXDESC_MSK, 0xFFFFCFFF); + } + + if(priv->pFirmware->FirmwareVersion >= 0x35) + { + priv->rtllib->SetFwCmdHandler(dev, FW_CMD_RA_INIT); + } + else if(priv->pFirmware->FirmwareVersion >= 0x34) + { + write_nic_dword(dev, WFM5, FW_RA_INIT); + ChkFwCmdIoDone(dev); + } + else + { + write_nic_dword(dev, WFM5, FW_RA_RESET); + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_RA_ACTIVE); + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_RA_REFRESH); + ChkFwCmdIoDone(dev); + } + + + + PHY_SwitchEphyParameter(dev); + RF_RECOVERY(dev, 0x25, 0x29); + + priv->SilentResetRxSlotIndex = 0; + for( i=0; i < MAX_SILENT_RESET_RX_SLOT_NUM; i++ ) + { + priv->SilentResetRxStuckEvent[i] = 0; + } + + if(priv->BluetoothCoexist) + { + printk("Write reg 0x%x = 1 for Bluetooth Co-existance\n", SYSF_CFG); + write_nic_byte(dev, SYSF_CFG, 0x1); + } + + priv->bIgnoreSilentReset = true; + +#ifdef CONFIG_FW_PARSEBEACON + if (!(priv->rtllib->softmac_features & IEEE_SOFTMAC_SCAN)){ + write_nic_dword(dev, RXFILTERMAP, 0x0100); + } +#endif + rtl8192_irq_enable(dev); +end: + priv->being_init_adapter = false; + return rtStatus; + + +} + +void rtl8192se_net_update(struct net_device *dev) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_network *net = &priv->rtllib->current_network; + u16 rate_config = 0; + u32 regTmp = 0; + u8 rateIndex = 0; + u8 RetryLimit = 0x30; + u16 cap = net->capability; + + priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE; + + { + rtl8192_config_rate(dev, &rate_config); + if (priv->card_8192_version== VERSION_8192S_ACUT) + priv->basic_rate = rate_config = rate_config & 0x150; + else if (priv->card_8192_version == VERSION_8192S_BCUT) + priv->basic_rate= rate_config = rate_config & 0x15f; + +#if 1 + if(priv->rtllib->pHTInfo->IOTPeer == HT_IOT_PEER_CISCO && ((rate_config &0x150)==0)) + { + rate_config |=0x010; + } + if(priv->rtllib->pHTInfo->IOTPeer & HT_IOT_ACT_WA_IOT_Broadcom) + { + rate_config &= 0x1f0; + printk("HW_VAR_BASIC_RATE, HT_IOT_ACT_WA_IOT_Broadcom, BrateCfg = 0x%x\n", rate_config); + } + + write_nic_byte(dev, RRSR, rate_config&0xff); + write_nic_byte(dev, RRSR+1, (rate_config>>8)&0xff); + + while(rate_config > 0x1) + { + rate_config = (rate_config>> 1); + rateIndex++; + } + write_nic_byte(dev, INIRTSMCS_SEL, rateIndex); + + regTmp = (priv->nCur40MhzPrimeSC) << 5; + if (priv->short_preamble) + regTmp |= 0x80; + write_nic_byte(dev, RRSR+2, regTmp); +#endif + } + + write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]); + write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]); + + if (priv->rtllib->iw_mode == IW_MODE_ADHOC){ + RetryLimit = HAL_RETRY_LIMIT_AP_ADHOC; + } else { + RetryLimit = (priv->CustomerID == RT_CID_CCX) ? 7 : HAL_RETRY_LIMIT_INFRA; + } + priv->rtllib->SetHwRegHandler(dev, HW_VAR_RETRY_LIMIT, (u8*)(&RetryLimit)); + + if (priv->rtllib->iw_mode == IW_MODE_ADHOC){ + priv->rtllib->SetHwRegHandler( dev, HW_VAR_BEACON_INTERVAL, (u8*)(&net->beacon_interval)); + } + + rtl8192_update_cap(dev, cap); +} + +#ifdef _RTL8192_EXT_PATCH_ +void rtl8192se_mesh_net_update(struct net_device *dev) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_network *net = &priv->rtllib->current_mesh_network; + u16 rate_config = 0; + u32 regTmp = 0; + u8 rateIndex = 0; + u8 retrylimit = 0x7; + u16 cap = net->capability; + /* At the peer mesh mode, the peer MP shall recognize the short preamble */ + priv->short_preamble = 1; + + if (priv->card_8192_version== VERSION_8192S_ACUT) + priv->basic_rate = rate_config = 0x150; + else if (priv->card_8192_version == VERSION_8192S_BCUT) + priv->basic_rate= rate_config = 0x15f; + + write_nic_byte(dev, RRSR, rate_config&0xff); + write_nic_byte(dev, RRSR+1, (rate_config>>8)&0xff); + + while(rate_config > 0x1) + { + rate_config = (rate_config>> 1); + rateIndex++; + } + write_nic_byte(dev, INIRTSMCS_SEL, rateIndex); + + regTmp = (priv->nCur40MhzPrimeSC) << 5; + if (priv->short_preamble) + regTmp |= 0x80; + write_nic_byte(dev, RRSR+2, regTmp); + + + write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); + PHY_SetBeaconHwReg( dev, net->beacon_interval); + rtl8192_update_cap(dev, cap); + + priv->ShortRetryLimit = + priv->LongRetryLimit = retrylimit; + + write_nic_word(dev,RETRY_LIMIT, \ + retrylimit << RETRY_LIMIT_SHORT_SHIFT | \ + retrylimit << RETRY_LIMIT_LONG_SHIFT); +} +#endif + +void rtl8192se_link_change(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device* ieee = priv->rtllib; + u32 reg = 0; + priv->rtllib->GetHwRegHandler(dev, HW_VAR_RCR, (u8*)(®)); + +#ifdef _RTL8192_EXT_PATCH_ + printk("===>%s():ieee->iw_mode is %d\n",__FUNCTION__,ieee->iw_mode); + if (ieee->state == RTLLIB_LINKED) { + if(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) + ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_DISABLE); + else + ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_ENABLE); + rtl8192se_net_update(dev); + if(ieee->bUseRAMask){ + ieee->UpdateHalRAMaskHandler( + dev, + false, + 0, + NULL, + ieee->mode, + 0); + priv->rssi_level = 0; + } + else{ + rtl8192se_update_ratr_table(dev,ieee->dot11HTOperationalRateSet,NULL); + } + reg |= RCR_CBSSID; + } else if ((ieee->mesh_state == RTLLIB_MESH_LINKED) && ieee->only_mesh) { + rtl8192se_mesh_net_update(dev); + reg &= ~RCR_CBSSID; + } else{ + reg &= ~RCR_CBSSID; + } + priv->rtllib->SetHwRegHandler( dev, HW_VAR_RCR, (u8*)(®) ); +#else + if (ieee->state == RTLLIB_LINKED) { +#ifdef CONFIG_FW_PARSEBEACON + if (!(priv->rtllib->softmac_features & IEEE_SOFTMAC_SCAN)){ + write_nic_dword(dev, RXFILTERMAP, 0x0000); + } +#endif + + if(priv->DM_Type == DM_Type_ByFW) { + if(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) + ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_DISABLE); + else + ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_ENABLE); + } + + rtl8192se_net_update(dev); + rtl8192se_update_ratr_table(dev,ieee->dot11HTOperationalRateSet,NULL); + reg |= RCR_CBSSID; + } else { +#ifdef CONFIG_FW_PARSEBEACON + if (!(priv->rtllib->softmac_features & IEEE_SOFTMAC_SCAN)){ + write_nic_dword(dev, RXFILTERMAP, 0x0100); + } +#endif + + reg &= ~RCR_CBSSID; + } + priv->rtllib->SetHwRegHandler( dev, HW_VAR_RCR, (u8*)(®) ); +#endif + + rtl8192se_update_msr(dev); + { + u32 temp = read_nic_dword(dev, TCR); + write_nic_dword(dev, TCR, temp&(~BIT8)); + write_nic_dword(dev, TCR, temp|BIT8); + } + +} + +u8 MRateToHwRate8192SE(struct net_device*dev, u8 rate) +{ + u8 ret = DESC92S_RATE1M; + u16 max_sg_rate; + static u16 multibss_sg_old = 0x1234; + u16 multibss_sg; + + switch(rate) + { + case MGN_1M: ret = DESC92S_RATE1M; break; + case MGN_2M: ret = DESC92S_RATE2M; break; + case MGN_5_5M: ret = DESC92S_RATE5_5M; break; + case MGN_11M: ret = DESC92S_RATE11M; break; + case MGN_6M: ret = DESC92S_RATE6M; break; + case MGN_9M: ret = DESC92S_RATE9M; break; + case MGN_12M: ret = DESC92S_RATE12M; break; + case MGN_18M: ret = DESC92S_RATE18M; break; + case MGN_24M: ret = DESC92S_RATE24M; break; + case MGN_36M: ret = DESC92S_RATE36M; break; + case MGN_48M: ret = DESC92S_RATE48M; break; + case MGN_54M: ret = DESC92S_RATE54M; break; + + case MGN_MCS0: ret = DESC92S_RATEMCS0; break; + case MGN_MCS1: ret = DESC92S_RATEMCS1; break; + case MGN_MCS2: ret = DESC92S_RATEMCS2; break; + case MGN_MCS3: ret = DESC92S_RATEMCS3; break; + case MGN_MCS4: ret = DESC92S_RATEMCS4; break; + case MGN_MCS5: ret = DESC92S_RATEMCS5; break; + case MGN_MCS6: ret = DESC92S_RATEMCS6; break; + case MGN_MCS7: ret = DESC92S_RATEMCS7; break; + case MGN_MCS8: ret = DESC92S_RATEMCS8; break; + case MGN_MCS9: ret = DESC92S_RATEMCS9; break; + case MGN_MCS10: ret = DESC92S_RATEMCS10; break; + case MGN_MCS11: ret = DESC92S_RATEMCS11; break; + case MGN_MCS12: ret = DESC92S_RATEMCS12; break; + case MGN_MCS13: ret = DESC92S_RATEMCS13; break; + case MGN_MCS14: ret = DESC92S_RATEMCS14; break; + case MGN_MCS15: ret = DESC92S_RATEMCS15; break; + + case MGN_MCS0_SG: + case MGN_MCS1_SG: + case MGN_MCS2_SG: + case MGN_MCS3_SG: + case MGN_MCS4_SG: + case MGN_MCS5_SG: + case MGN_MCS6_SG: + case MGN_MCS7_SG: + case MGN_MCS8_SG: + case MGN_MCS9_SG: + case MGN_MCS10_SG: + case MGN_MCS11_SG: + case MGN_MCS12_SG: + case MGN_MCS13_SG: + case MGN_MCS14_SG: + case MGN_MCS15_SG: + ret = DESC92S_RATEMCS15_SG; + max_sg_rate = rate&0xf; + multibss_sg = max_sg_rate | (max_sg_rate<<4) | (max_sg_rate<<8) | (max_sg_rate<<12); + if (multibss_sg_old != multibss_sg) + { + write_nic_dword(dev, SG_RATE, multibss_sg); + multibss_sg_old = multibss_sg; + } + break; + + + case (0x80|0x20): ret = DESC92S_RATEMCS32; break; + + default: ret = DESC92S_RATEMCS15; break; + + } + + return ret; +} + +u8 rtl8192se_MapHwQueueToFirmwareQueue(u8 QueueID, u8 priority) +{ + u8 QueueSelect = 0x0; + + switch(QueueID) { +#if defined RTL8192E || defined RTL8190P + case BE_QUEUE: + QueueSelect = QSLT_BE; + break; + + case BK_QUEUE: + QueueSelect = QSLT_BK; + break; + + case VO_QUEUE: + QueueSelect = QSLT_VO; + break; + + case VI_QUEUE: + QueueSelect = QSLT_VI; + break; + case MGNT_QUEUE: + QueueSelect = QSLT_MGNT; + break; + case BEACON_QUEUE: + QueueSelect = QSLT_BEACON; + break; + case TXCMD_QUEUE: + QueueSelect = QSLT_CMD; + break; + case HIGH_QUEUE: + QueueSelect = QSLT_HIGH; + break; +#elif defined RTL8192SE + case BE_QUEUE: + QueueSelect = priority; + break; + case BK_QUEUE: + QueueSelect = priority; + break; + case VO_QUEUE: + QueueSelect = priority; + break; + case VI_QUEUE: + QueueSelect = priority; + break; + case MGNT_QUEUE: + QueueSelect = QSLT_BE; + break; + case BEACON_QUEUE: + QueueSelect = QSLT_BEACON; + break; + case TXCMD_QUEUE: + QueueSelect = QSLT_CMD; + break; + case HIGH_QUEUE: + QueueSelect = QSLT_HIGH; + break; +#endif + default: + RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection: %d \n", QueueID); + break; + } + return QueueSelect; +} + + +void rtl8192se_tx_fill_desc(struct net_device* dev, tx_desc * pDesc, cb_desc * cb_desc, struct sk_buff* skb) +{ + u8 *pSeq; + u16 Temp; + struct r8192_priv* priv = rtllib_priv(dev); + + struct rtllib_hdr_1addr * header = NULL; + + dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE); + + u16 fc=0, stype=0; + header = (struct rtllib_hdr_1addr *)(((u8*)skb->data)); + fc = header->frame_ctl; + stype = WLAN_FC_GET_STYPE(fc); + memset((void*)pDesc, 0, 32); + + { + +#ifdef _RTL8192_EXT_PATCH_ + if(priv->rtllib->bUseRAMask){ + if(cb_desc->macId < 32) + { + pDesc->MacID = cb_desc->macId; + pDesc->Rsvd_MacID = cb_desc->macId; + } + } +#endif + pDesc->TXHT = (cb_desc->data_rate&0x80)?1:0; + +#if (RTL92SE_FPGA_VERIFY == 0) + if (priv->card_8192_version== VERSION_8192S_ACUT) + { + if (cb_desc->data_rate== MGN_1M || cb_desc->data_rate == MGN_2M || + cb_desc->data_rate == MGN_5_5M || cb_desc->data_rate == MGN_11M) + { + cb_desc->data_rate = MGN_12M; + } + } +#endif + pDesc->TxRate = MRateToHwRate8192SE(dev,cb_desc->data_rate); + pDesc->TxShort = QueryIsShort(((cb_desc->data_rate&0x80)?1:0), MRateToHwRate8192SE(dev,cb_desc->data_rate), cb_desc); + + if(cb_desc->bAMPDUEnable) + { + pDesc->AggEn = 1; + } + else + { + pDesc->AggEn = 0; + } + + { + pSeq = (u8 *)(skb->data+22); + Temp = pSeq[0]; + Temp <<= 12; + Temp |= (*(u16 *)pSeq)>>4; + pDesc->Seq = Temp; + } + + pDesc->RTSEn = (cb_desc->bRTSEnable && cb_desc->bCTSEnable==false)?1:0; + pDesc->CTS2Self = (cb_desc->bCTSEnable)?1:0; + pDesc->RTSSTBC = (cb_desc->bRTSSTBC)?1:0; + pDesc->RTSHT = (cb_desc->rts_rate&0x80)?1:0; + +#if (RTL92SE_FPGA_VERIFY == 0) + if (priv->card_8192_version== VERSION_8192S_ACUT) + { + if (cb_desc->rts_rate == MGN_1M || cb_desc->rts_rate == MGN_2M || + cb_desc->rts_rate == MGN_5_5M || cb_desc->rts_rate == MGN_11M) + { + cb_desc->rts_rate = MGN_12M; + } + } +#endif + pDesc->RTSRate = MRateToHwRate8192SE(dev,cb_desc->rts_rate); + pDesc->RTSRate = MRateToHwRate8192SE(dev,MGN_24M); + pDesc->RTSBW = 0; + pDesc->RTSSC = cb_desc->RTSSC; + pDesc->RTSShort = (pDesc->RTSHT==0)?(cb_desc->bRTSUseShortPreamble?1:0):(cb_desc->bRTSUseShortGI?1:0); + if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + if(cb_desc->bPacketBW) + { + pDesc->TxBw = 1; + pDesc->TXSC = 0; + } + else + { + pDesc->TxBw = 0; + pDesc->TXSC = priv->nCur40MhzPrimeSC; + } + } + else + { + pDesc->TxBw = 0; + pDesc->TXSC = 0; + } + + pDesc->LINIP = 0; + pDesc->Offset = 32; + pDesc->PktSize = (u16)skb->len; + + pDesc->RaBRSRID = cb_desc->RATRIndex; +#if 0 +printk("*************TXDESC:\n"); +printk("\tTxRate: %d\n", pDesc->TxRate); +printk("\tAMPDUEn: %d\n", pDesc->AggEn); +printk("\tTxBw: %d\n", pDesc->TxBw); +printk("\tTXSC: %d\n", pDesc->TXSC); +printk("\tPktSize: %d\n", pDesc->PktSize); +printk("\tRatrIdx: %d\n", pDesc->RaBRSRID); +#endif + if (cb_desc->bHwSec) { + static u8 tmp =0; + if (!tmp) { + tmp = 1; + } +#ifdef _RTL8192_EXT_PATCH_ + if(cb_desc->mesh_pkt == 0) +#endif + { + switch (priv->rtllib->pairwise_key_type) { + case KEY_TYPE_WEP40: + case KEY_TYPE_WEP104: + pDesc->SecType = 0x1; + break; + case KEY_TYPE_TKIP: + pDesc->SecType = 0x2; + break; + case KEY_TYPE_CCMP: + pDesc->SecType = 0x3; + break; + case KEY_TYPE_NA: + pDesc->SecType = 0x0; + break; + } + } +#ifdef _RTL8192_EXT_PATCH_ + else if(cb_desc->mesh_pkt == 1) + { + switch (priv->rtllib->mesh_pairwise_key_type) { + case KEY_TYPE_WEP40: + case KEY_TYPE_WEP104: + pDesc->SecType = 0x1; + break; + case KEY_TYPE_TKIP: + pDesc->SecType = 0x2; + break; + case KEY_TYPE_CCMP: + pDesc->SecType = 0x3; + break; + case KEY_TYPE_NA: + pDesc->SecType = 0x0; + break; + } + } +#endif + } + + pDesc->PktID = 0x0; + pDesc->QueueSel = rtl8192se_MapHwQueueToFirmwareQueue(cb_desc->queue_index, cb_desc->priority); + + pDesc->DataRateFBLmt = 0x1F; + pDesc->DISFB = cb_desc->bTxDisableRateFallBack; + pDesc->UserRate = cb_desc->bTxUseDriverAssingedRate; + + if (pDesc->UserRate == true && pDesc->TXHT == true) + RF_ChangeTxPath(dev, cb_desc->data_rate); + + } + + + pDesc->FirstSeg = 1; + pDesc->LastSeg = 1; + + pDesc->TxBufferSize= (u16)skb->len; + + pDesc->TxBuffAddr = cpu_to_le32(mapping); + +} + +void rtl8192se_tx_fill_cmd_desc(struct net_device* dev, tx_desc_cmd * entry, cb_desc * cb_desc, struct sk_buff* skb) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if(cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) { + + dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE); + + memset((void*)entry, 0, 32); + + entry->LINIP = cb_desc->bLastIniPkt; + + entry->FirstSeg = 1; + entry->LastSeg = 1; + + entry->TxBufferSize= (u16)(skb->len); + entry->TxBufferAddr = cpu_to_le32(mapping); + entry->PktSize = (u16)(skb->len); + + { + entry->OWN = 1; + } + } else { + + u8* pDesc = (u8*)entry; + + dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE); + + CLEAR_PCI_TX_DESC_CONTENT(pDesc, sizeof(tx_desc_cmd)); + + SET_TX_DESC_FIRST_SEG(pDesc, 1); + SET_TX_DESC_LAST_SEG(pDesc, 1); + + SET_TX_DESC_OFFSET(pDesc, 0x20); + + SET_TX_DESC_PKT_SIZE(pDesc, (u16)(skb->len)); + SET_TX_DESC_QUEUE_SEL(pDesc, 0x13); + + + SET_BITS_TO_LE_4BYTE(skb->data, 24, 7, priv->H2CTxCmdSeq); + + SET_TX_DESC_TX_BUFFER_SIZE(pDesc, (u16)(skb->len)); + SET_TX_DESC_TX_BUFFER_ADDRESS(pDesc, cpu_to_le32(mapping)); + + SET_TX_DESC_OWN(pDesc, 1); + + RT_TRACE(COMP_CMD, "TxFillCmdDesc8192SE(): H2C Tx Cmd Content ----->\n"); + } +} + +u8 HwRateToMRate92S(bool bIsHT, u8 rate) +{ + u8 ret_rate = 0x02; + + if (!bIsHT) { + switch (rate) { + case DESC92S_RATE1M: + ret_rate = MGN_1M; + break; + case DESC92S_RATE2M: + ret_rate = MGN_2M; + break; + case DESC92S_RATE5_5M: + ret_rate = MGN_5_5M; + break; + case DESC92S_RATE11M: + ret_rate = MGN_11M; + break; + case DESC92S_RATE6M: + ret_rate = MGN_6M; + break; + case DESC92S_RATE9M: + ret_rate = MGN_9M; + break; + case DESC92S_RATE12M: + ret_rate = MGN_12M; + break; + case DESC92S_RATE18M: + ret_rate = MGN_18M; + break; + case DESC92S_RATE24M: + ret_rate = MGN_24M; + break; + case DESC92S_RATE36M: + ret_rate = MGN_36M; + break; + case DESC92S_RATE48M: + ret_rate = MGN_48M; + break; + case DESC92S_RATE54M: + ret_rate = MGN_54M; + break; + default: + ret_rate = 0xff; + break; + } + } else { + switch (rate) { + case DESC92S_RATEMCS0: + ret_rate = MGN_MCS0; + break; + case DESC92S_RATEMCS1: + ret_rate = MGN_MCS1; + break; + case DESC92S_RATEMCS2: + ret_rate = MGN_MCS2; + break; + case DESC92S_RATEMCS3: + ret_rate = MGN_MCS3; + break; + case DESC92S_RATEMCS4: + ret_rate = MGN_MCS4; + break; + case DESC92S_RATEMCS5: + ret_rate = MGN_MCS5; + break; + case DESC92S_RATEMCS6: + ret_rate = MGN_MCS6; + break; + case DESC92S_RATEMCS7: + ret_rate = MGN_MCS7; + break; + case DESC92S_RATEMCS8: + ret_rate = MGN_MCS8; + break; + case DESC92S_RATEMCS9: + ret_rate = MGN_MCS9; + break; + case DESC92S_RATEMCS10: + ret_rate = MGN_MCS10; + break; + case DESC92S_RATEMCS11: + ret_rate = MGN_MCS11; + break; + case DESC92S_RATEMCS12: + ret_rate = MGN_MCS12; + break; + case DESC92S_RATEMCS13: + ret_rate = MGN_MCS13; + break; + case DESC92S_RATEMCS14: + ret_rate = MGN_MCS14; + break; + case DESC92S_RATEMCS15: + ret_rate = MGN_MCS15; + break; + case DESC92S_RATEMCS32: + ret_rate = (0x80|0x20); + break; + default: + ret_rate = 0xff; + break; + } + + } + return ret_rate; +} + +long +rtl8192se_signal_scale_mapping(struct r8192_priv * priv, + long currsig + ) +{ + long retsig; + +#if defined RTL8192SE || defined RTL8192CE + if(priv->CustomerID == RT_CID_819x_Lenovo) + { + return currsig; + } + else if(priv->CustomerID == RT_CID_819x_Netcore) + { + if(currsig >= 31 && currsig <= 100) + { + retsig = 100; + } + else if(currsig >= 21 && currsig <= 30) + { + retsig = 90 + ((currsig - 20) / 1); + } + else if(currsig >= 11 && currsig <= 20) + { + retsig = 80 + ((currsig - 10) / 1); + } + else if(currsig >= 7 && currsig <= 10) + { + retsig = 69 + (currsig - 7); + } + else if(currsig == 6) + { + retsig = 54; + } + else if(currsig == 5) + { + retsig = 45; + } + else if(currsig == 4) + { + retsig = 36; + } + else if(currsig == 3) + { + retsig = 27; + } + else if(currsig == 2) + { + retsig = 18; + } + else if(currsig == 1) + { + retsig = 9; + } + else + { + retsig = currsig; + } + return retsig; + } +#endif + + if(currsig >= 61 && currsig <= 100) + { + retsig = 90 + ((currsig - 60) / 4); + } + else if(currsig >= 41 && currsig <= 60) + { + retsig = 78 + ((currsig - 40) / 2); + } + else if(currsig >= 31 && currsig <= 40) + { + retsig = 66 + (currsig - 30); + } + else if(currsig >= 21 && currsig <= 30) + { + retsig = 54 + (currsig - 20); + } + else if(currsig >= 5 && currsig <= 20) + { + retsig = 42 + (((currsig - 5) * 2) / 3); + } + else if(currsig == 4) + { + retsig = 36; + } + else if(currsig == 3) + { + retsig = 27; + } + else if(currsig == 2) + { + retsig = 18; + } + else if(currsig == 1) + { + retsig = 9; + } + else + { + retsig = currsig; + } + + return retsig; +} + + +#define rx_hal_is_cck_rate(_pdesc)\ + (_pdesc->RxMCS == DESC92S_RATE1M ||\ + _pdesc->RxMCS == DESC92S_RATE2M ||\ + _pdesc->RxMCS == DESC92S_RATE5_5M ||\ + _pdesc->RxMCS == DESC92S_RATE11M) +#ifdef _RTL8192_EXT_PATCH_ +void rtl8192se_query_rxphystatus( + struct r8192_priv * priv, + struct rtllib_rx_stats * pstats, + prx_desc pdesc, + prx_fwinfo pDrvInfo, + bool bpacket_match_bssid, + bool bpacket_toself, + bool bPacketBeacon + ) +{ + bool is_cck_rate; + phy_sts_cck_8192s_t* cck_buf; + u8 rx_pwr_all=0, rx_pwr[4], rf_rx_num=0, EVM, PWDB_ALL; + u8 i, max_spatial_stream; + u32 rssi, total_rssi = 0; + u8 cck_highpwr = 0; + is_cck_rate = rx_hal_is_cck_rate(pdesc); + + pstats->bPacketMatchBSSID = bpacket_match_bssid; + pstats->bPacketToSelf = bpacket_toself; + pstats->bIsCCK = is_cck_rate; + pstats->bPacketBeacon = bPacketBeacon; + + pstats->RxMIMOSignalQuality[0] = -1; + pstats->RxMIMOSignalQuality[1] = -1; + + if (is_cck_rate){ + u8 report; + + cck_buf = (phy_sts_cck_8192s_t*)pDrvInfo; + + if(priv->rtllib->eRFPowerState == eRfOn) + cck_highpwr = (u8)priv->bCckHighPower; + else + cck_highpwr = false; + if (!cck_highpwr){ + report = cck_buf->cck_agc_rpt & 0xc0; + report = report >> 6; + switch(report){ + case 0x3: + rx_pwr_all = -40 - (cck_buf->cck_agc_rpt&0x3e); + break; + case 0x2: + rx_pwr_all = -20 - (cck_buf->cck_agc_rpt&0x3e); + break; + case 0x1: + rx_pwr_all = -2 - (cck_buf->cck_agc_rpt&0x3e); + break; + case 0x0: + rx_pwr_all = 14 - (cck_buf->cck_agc_rpt&0x3e); + break; + } + } + else{ + report = pDrvInfo->cfosho[0] & 0x60; + report = report >> 5; + switch(report){ + case 0x3: + rx_pwr_all = -40 - ((cck_buf->cck_agc_rpt & 0x1f)<<1); + break; + case 0x2: + rx_pwr_all = -20 - ((cck_buf->cck_agc_rpt & 0x1f)<<1); + break; + case 0x1: + rx_pwr_all = -2 - ((cck_buf->cck_agc_rpt & 0x1f)<<1); + break; + case 0x0: + rx_pwr_all = 14 - ((cck_buf->cck_agc_rpt & 0x1f)<<1); + break; + } + } + + PWDB_ALL= rtl819x_query_rxpwrpercentage(rx_pwr_all); + { + PWDB_ALL+=6; + if(PWDB_ALL > 100) + PWDB_ALL = 100; + if(PWDB_ALL > 34 && PWDB_ALL <= 42) + PWDB_ALL -= 2; + else if(PWDB_ALL > 26 && PWDB_ALL <= 34) + PWDB_ALL -= 6; + else if(PWDB_ALL > 14 && PWDB_ALL <= 26) + PWDB_ALL -= 8; + else if(PWDB_ALL > 4 && PWDB_ALL <= 14) + PWDB_ALL -= 4; + } + pstats->RxPWDBAll = PWDB_ALL; + pstats->RecvSignalPower = rx_pwr_all; + + if (bpacket_match_bssid){ + u8 sq; + if(priv->CustomerID == RT_CID_819x_Lenovo) + { + if(PWDB_ALL >= 50) + sq = 100; + else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + sq = 80; + else if(PWDB_ALL >= 22 && PWDB_ALL < 35) + sq = 60; + else if(PWDB_ALL >= 18 && PWDB_ALL < 22) + sq = 40; + else + sq = 20; + } + else + { + if (pstats->RxPWDBAll > 40) + sq = 100; + else{ + sq = cck_buf->sq_rpt; + if (sq > 64) + sq = 0; + else if(sq < 20) + sq = 100; + else + sq = ((64-sq)*100)/44; + } + } + pstats->SignalQuality = sq; + pstats->RxMIMOSignalQuality[0] = sq; + pstats->RxMIMOSignalQuality[1] = -1; + } + } + else{ + priv->brfpath_rxenable[0] = priv->brfpath_rxenable[1] = true; + + for (i=RF90_PATH_A; i<RF90_PATH_MAX; i++){ + if (priv->brfpath_rxenable[i]) + rf_rx_num ++; + + rx_pwr[i] = ((pDrvInfo->gain_trsw[i]&0x3f)*2) - 110; + rssi = rtl819x_query_rxpwrpercentage(rx_pwr[i]); + total_rssi += rssi; + + priv->stats.rxSNRdB[i] = (long)(pDrvInfo->rxsnr[i]/2); + + if (bpacket_match_bssid){ + pstats->RxMIMOSignalStrength[i] = (u8)rssi; + if(priv->CustomerID == RT_CID_819x_Lenovo) + { + u8 SQ; + + if(i == 0) + { + if(rssi >= 50) + SQ = 100; + else if(rssi >= 35 && rssi < 50) + SQ = 80; + else if(rssi >= 22 && rssi < 35) + SQ = 60; + else if(rssi >= 18 && rssi < 22) + SQ = 40; + else + SQ = 20; + pstats->SignalQuality = SQ; + } + } + } + } + rx_pwr_all = ((pDrvInfo->pwdb_all >> 1) & 0x7f) - 106; + PWDB_ALL = rtl819x_query_rxpwrpercentage(rx_pwr_all); + + pstats->RxPWDBAll = PWDB_ALL; + pstats->RxPower = rx_pwr_all; + pstats->RecvSignalPower = rx_pwr_all; + + if(priv->CustomerID != RT_CID_819x_Lenovo){ + if (pdesc->RxHT && pdesc->RxMCS >= DESC92S_RATEMCS8 && pdesc->RxMCS <= DESC92S_RATEMCS15) + max_spatial_stream = 2; + else + max_spatial_stream = 1; + + for(i=0; i<max_spatial_stream; i++){ + EVM = rtl819x_evm_dbtopercentage(pDrvInfo->rxevm[i]); + + if (bpacket_match_bssid) + { + if (i==0) + pstats->SignalQuality = (u8)(EVM & 0xff); + pstats->RxMIMOSignalQuality[i] = (u8)(EVM&0xff); + } + } + } +#if 1 + if (pdesc->BandWidth) + priv->stats.received_bwtype[1+pDrvInfo->rxsc]++; + else + priv->stats.received_bwtype[0]++; +#endif + } + + if (is_cck_rate){ + pstats->SignalStrength = (u8)(rtl8192se_signal_scale_mapping(priv,PWDB_ALL)); + } + else { + if (rf_rx_num != 0) + pstats->SignalStrength = (u8)(rtl8192se_signal_scale_mapping(priv,total_rssi/=rf_rx_num)); + } +} +#else +void rtl8192se_query_rxphystatus( + struct r8192_priv * priv, + struct rtllib_rx_stats * pstats, + prx_desc pdesc, + prx_fwinfo pDrvInfo, + struct rtllib_rx_stats * precord_stats, + bool bpacket_match_bssid, + bool bpacket_toself, + bool bPacketBeacon, + bool bToSelfBA + ) +{ + bool is_cck_rate; + phy_sts_cck_8192s_t* cck_buf; + s8 rx_pwr_all=0, rx_pwr[4]; + u8 rf_rx_num=0, EVM, PWDB_ALL; + u8 i, max_spatial_stream; + u32 rssi, total_rssi = 0; + + is_cck_rate = rx_hal_is_cck_rate(pdesc); + + memset(precord_stats, 0, sizeof(struct rtllib_rx_stats)); + pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid; + pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself; + pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate; + pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon; + pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA; + pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate; + + pstats->RxMIMOSignalQuality[0] = -1; + pstats->RxMIMOSignalQuality[1] = -1; + precord_stats->RxMIMOSignalQuality[0] = -1; + precord_stats->RxMIMOSignalQuality[1] = -1; + + if (is_cck_rate){ + u8 report, cck_highpwr; + + cck_buf = (phy_sts_cck_8192s_t*)pDrvInfo; + + if(!priv->bInPowerSaveMode) + cck_highpwr = (u8)rtl8192_QueryBBReg(priv->rtllib->dev, rFPGA0_XA_HSSIParameter2, BIT9); + else + cck_highpwr = false; + if (!cck_highpwr){ + report = cck_buf->cck_agc_rpt & 0xc0; + report = report >> 6; + switch(report){ + case 0x3: + rx_pwr_all = -35 - (cck_buf->cck_agc_rpt&0x3e); + break; + case 0x2: + rx_pwr_all = -23 - (cck_buf->cck_agc_rpt&0x3e); + break; + case 0x1: + rx_pwr_all = -11 - (cck_buf->cck_agc_rpt&0x3e); + break; + case 0x0: + rx_pwr_all = 8 - (cck_buf->cck_agc_rpt&0x3e); + break; + } + } + else{ + report = pDrvInfo->cfosho[0] & 0x60; + report = report >> 5; + switch(report){ + case 0x3: + rx_pwr_all = -35 - ((cck_buf->cck_agc_rpt & 0x1f)<<1); + break; + case 0x2: + rx_pwr_all = -23 - ((cck_buf->cck_agc_rpt & 0x1f)<<1); + break; + case 0x1: + rx_pwr_all = -11 - ((cck_buf->cck_agc_rpt & 0x1f)<<1); + break; + case 0x0: + rx_pwr_all = -8 - ((cck_buf->cck_agc_rpt & 0x1f)<<1); + break; + } + } + + PWDB_ALL= rtl819x_query_rxpwrpercentage(rx_pwr_all); + pstats->RxPWDBAll = precord_stats->RxPWDBAll = PWDB_ALL; + pstats->RecvSignalPower = rx_pwr_all; + + if (bpacket_match_bssid){ + u8 sq; + if (pstats->RxPWDBAll > 40) + sq = 100; + else{ + sq = cck_buf->sq_rpt; + if (sq > 64) + sq = 0; + else if(sq < 20) + sq = 100; + else + sq = ((64-sq)*100)/44; + } + pstats->SignalQuality = precord_stats->SignalQuality = sq; + pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq; + pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1; + } + } + else{ + priv->brfpath_rxenable[0] = priv->brfpath_rxenable[1] = true; + + for (i=RF90_PATH_A; i<RF90_PATH_MAX; i++){ + if (priv->brfpath_rxenable[i]) + rf_rx_num ++; + + rx_pwr[i] = ((pDrvInfo->gain_trsw[i]&0x3f)*2) - 110; + rssi = rtl819x_query_rxpwrpercentage(rx_pwr[i]); + total_rssi += rssi; + + priv->stats.rxSNRdB[i] = (long)(pDrvInfo->rxsnr[i]/2); + + if (bpacket_match_bssid){ + pstats->RxMIMOSignalStrength[i] = (u8)rssi; + precord_stats->RxMIMOSignalStrength [i] = (u8)rssi; + } + } + + rx_pwr_all = ((pDrvInfo->pwdb_all >> 1) & 0x7f) - 0x106; + PWDB_ALL = rtl819x_query_rxpwrpercentage(rx_pwr_all); + + pstats->RxPWDBAll = precord_stats->RxPWDBAll = PWDB_ALL; + pstats->RxPower = precord_stats->RxPower = rx_pwr_all; + pstats->RecvSignalPower = precord_stats->RecvSignalPower = rx_pwr_all; + + if (pdesc->RxHT && pdesc->RxMCS >= DESC92S_RATEMCS8 && pdesc->RxMCS <= DESC92S_RATEMCS15) + max_spatial_stream = 2; + else + max_spatial_stream = 1; + + for(i=0; i<max_spatial_stream; i++){ + EVM = rtl819x_evm_dbtopercentage(pDrvInfo->rxevm[i]); + + if (bpacket_match_bssid) + { + if (i==0) + pstats->SignalQuality = + precord_stats->SignalQuality = (u8)(EVM&0xff); + pstats->RxMIMOSignalQuality[i] = + precord_stats->RxMIMOSignalQuality[i] = (u8)(EVM&0xff); + } + } +#if 0 + if (pdesc->BW) + priv->stats.received_bwtype[1+pDrvInfo->rxsc]++; + else + priv->stats.received_bwtype[0]++; +#endif + } + + if (is_cck_rate) + pstats->SignalStrength = + precord_stats->SignalStrength = (u8)(rtl8192se_signal_scale_mapping(priv,PWDB_ALL)); + else + if (rf_rx_num != 0) + pstats->SignalStrength = + precord_stats->SignalStrength = (u8)(rtl8192se_signal_scale_mapping(priv,total_rssi/=rf_rx_num)); + +} +#endif + +#ifdef _RTL8192_EXT_PATCH_ +void rtl819x_update_rxsignalstatistics8192S( + struct r8192_priv * priv, + struct rtllib_rx_stats * pstats + ) +{ + int weighting = 0; + + + if(priv->stats.recv_signal_power == 0) + priv->stats.recv_signal_power = pstats->RecvSignalPower; + + if(pstats->RecvSignalPower > priv->stats.recv_signal_power) + weighting = 5; + else if(pstats->RecvSignalPower < priv->stats.recv_signal_power) + weighting = (-5); + priv->stats.recv_signal_power = (priv->stats.recv_signal_power * 5 + pstats->RecvSignalPower + weighting) / 6; + +} + +void Process_UI_RSSI_8192S(struct r8192_priv * priv,struct rtllib_rx_stats * pstats) +{ + u8 rfPath; + u32 last_rssi, tmpVal; + + if(pstats->bPacketToSelf || pstats->bPacketBeacon) + { + priv->stats.RssiCalculateCnt++; + if(priv->stats.ui_rssi.TotalNum++ >= PHY_RSSI_SLID_WIN_MAX) + { + priv->stats.ui_rssi.TotalNum = PHY_RSSI_SLID_WIN_MAX; + last_rssi = priv->stats.ui_rssi.elements[priv->stats.ui_rssi.index]; + priv->stats.ui_rssi.TotalVal -= last_rssi; + } + priv->stats.ui_rssi.TotalVal += pstats->SignalStrength; + + priv->stats.ui_rssi.elements[priv->stats.ui_rssi.index++] = pstats->SignalStrength; + if(priv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX) + priv->stats.ui_rssi.index = 0; + + tmpVal = priv->stats.ui_rssi.TotalVal/priv->stats.ui_rssi.TotalNum; + priv->stats.signal_strength = rtl819x_translate_todbm(priv, (u8)tmpVal); + + } + + if(!pstats->bIsCCK && pstats->bPacketToSelf) + { + for (rfPath = RF90_PATH_A; rfPath < priv->NumTotalRFPath; rfPath++) + { + if (!rtl8192_phy_CheckIsLegalRFPath(priv->rtllib->dev, rfPath)) + continue; + RT_TRACE(COMP_DBG, "pstats->RxMIMOSignalStrength[%d] = %d \n", rfPath, pstats->RxMIMOSignalStrength[rfPath] ); + + if(priv->stats.rx_rssi_percentage[rfPath] == 0) + { + priv->stats.rx_rssi_percentage[rfPath] = pstats->RxMIMOSignalStrength[rfPath]; + } + + if(pstats->RxMIMOSignalStrength[rfPath] > priv->stats.rx_rssi_percentage[rfPath]) + { + priv->stats.rx_rssi_percentage[rfPath] = + ( (priv->stats.rx_rssi_percentage[rfPath]*(Rx_Smooth_Factor-1)) + + (pstats->RxMIMOSignalStrength[rfPath])) /(Rx_Smooth_Factor); + priv->stats.rx_rssi_percentage[rfPath] = priv->stats.rx_rssi_percentage[rfPath] + 1; + } + else + { + priv->stats.rx_rssi_percentage[rfPath] = + ( (priv->stats.rx_rssi_percentage[rfPath]*(Rx_Smooth_Factor-1)) + + (pstats->RxMIMOSignalStrength[rfPath])) /(Rx_Smooth_Factor); + } + RT_TRACE(COMP_DBG, "priv->stats.rx_rssi_percentage[%d] = %d \n",rfPath, priv->stats.rx_rssi_percentage[rfPath] ); + } + } + +} + +void Process_PWDB_8192S(struct r8192_priv * priv,struct rtllib_rx_stats * pstats,struct rtllib_network* pnet) +{ + long UndecoratedSmoothedPWDB=0; + + if(pnet){ + if(priv->mshobj->ext_patch_get_peermp_rssi_param) + UndecoratedSmoothedPWDB = priv->mshobj->ext_patch_get_peermp_rssi_param(pnet); + } + else + UndecoratedSmoothedPWDB = priv->undecorated_smoothed_pwdb; + + if(pstats->bPacketToSelf || pstats->bPacketBeacon) + { + if(UndecoratedSmoothedPWDB < 0) + { + UndecoratedSmoothedPWDB = pstats->RxPWDBAll; + } + + if(pstats->RxPWDBAll > (u32)UndecoratedSmoothedPWDB) + { + UndecoratedSmoothedPWDB = + ( ((UndecoratedSmoothedPWDB)*(Rx_Smooth_Factor-1)) + + (pstats->RxPWDBAll)) /(Rx_Smooth_Factor); + UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB + 1; + } + else + { + UndecoratedSmoothedPWDB = + ( ((UndecoratedSmoothedPWDB)*(Rx_Smooth_Factor-1)) + + (pstats->RxPWDBAll)) /(Rx_Smooth_Factor); + } + if(pnet) + { + if(priv->mshobj->ext_patch_set_peermp_rssi_param) + priv->mshobj->ext_patch_set_peermp_rssi_param(pnet,UndecoratedSmoothedPWDB); + } + else + { + priv->undecorated_smoothed_pwdb = UndecoratedSmoothedPWDB; + } + rtl819x_update_rxsignalstatistics8192S(priv, pstats); + } +} + +void Process_UiLinkQuality8192S(struct r8192_priv * priv,struct rtllib_rx_stats * pstats) +{ + u32 last_evm=0, nSpatialStream, tmpVal; + + if(pstats->SignalQuality != 0) + { + if (pstats->bPacketToSelf || pstats->bPacketBeacon) + { + if(priv->stats.ui_link_quality.TotalNum++ >= PHY_LINKQUALITY_SLID_WIN_MAX) + { + priv->stats.ui_link_quality.TotalNum = PHY_LINKQUALITY_SLID_WIN_MAX; + last_evm = priv->stats.ui_link_quality.elements[priv->stats.ui_link_quality.index]; + priv->stats.ui_link_quality.TotalVal -= last_evm; + } + priv->stats.ui_link_quality.TotalVal += pstats->SignalQuality; + + priv->stats.ui_link_quality.elements[priv->stats.ui_link_quality.index++] = pstats->SignalQuality; + if(priv->stats.ui_link_quality.index >= PHY_LINKQUALITY_SLID_WIN_MAX) + priv->stats.ui_link_quality.index = 0; + + + tmpVal = priv->stats.ui_link_quality.TotalVal/priv->stats.ui_link_quality.TotalNum; + priv->stats.signal_quality = tmpVal; + priv->stats.last_signal_strength_inpercent = tmpVal; + + for(nSpatialStream = 0; nSpatialStream<2 ; nSpatialStream++) + { + if(pstats->RxMIMOSignalQuality[nSpatialStream] != -1) + { + if(priv->stats.rx_evm_percentage[nSpatialStream] == 0) + { + priv->stats.rx_evm_percentage[nSpatialStream] = pstats->RxMIMOSignalQuality[nSpatialStream]; + } + priv->stats.rx_evm_percentage[nSpatialStream] = + ( (priv->stats.rx_evm_percentage[nSpatialStream]*(Rx_Smooth_Factor-1)) + + (pstats->RxMIMOSignalQuality[nSpatialStream]* 1)) /(Rx_Smooth_Factor); + } + } + } + } + else + ; + +} +#endif + + +#ifdef _RTL8192_EXT_PATCH_ +void rtl8192se_process_phyinfo(struct r8192_priv * priv, u8* buffer,struct rtllib_rx_stats * pcurrent_stats,struct rtllib_network * pnet) +#else +void rtl8192se_process_phyinfo(struct r8192_priv * priv, u8* buffer,struct rtllib_rx_stats * pprevious_stats, struct rtllib_rx_stats * pcurrent_stats) +#endif +{ +#ifdef _RTL8192_EXT_PATCH_ + if(!pcurrent_stats->bPacketMatchBSSID) + return; + Process_UI_RSSI_8192S(priv, pcurrent_stats); + Process_PWDB_8192S(priv, pcurrent_stats, pnet); + Process_UiLinkQuality8192S(priv, pcurrent_stats); +#else + bool bcheck = false; + u8 rfpath; + u32 nspatial_stream, tmp_val; + static u32 slide_rssi_index=0, slide_rssi_statistics=0; + static u32 slide_evm_index=0, slide_evm_statistics=0; + static u32 last_rssi=0, last_evm=0; + static u32 slide_beacon_adc_pwdb_index=0, slide_beacon_adc_pwdb_statistics=0; + static u32 last_beacon_adc_pwdb=0; + + struct rtllib_hdr_3addr *hdr; + u16 sc ; + unsigned int frag,seq; + hdr = (struct rtllib_hdr_3addr *)buffer; + sc = le16_to_cpu(hdr->seq_ctl); + frag = WLAN_GET_SEQ_FRAG(sc); + seq = WLAN_GET_SEQ_SEQ(sc); + pcurrent_stats->Seq_Num = seq; + if(!pprevious_stats->bIsAMPDU) + { + bcheck = true; + }else + { +#if 0 + if( !pcurrent_stats->bIsAMPDU || pcurrent_stats->bFirstMPDU) + bcheck = true; +#endif + } + + if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) + { + slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX; + last_rssi = priv->stats.slide_signal_strength[slide_rssi_index]; + priv->stats.slide_rssi_total -= last_rssi; + } + priv->stats.slide_rssi_total += pprevious_stats->SignalStrength; + + priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength; + if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX) + slide_rssi_index = 0; + + tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics; + priv->stats.signal_strength = rtl819x_translate_todbm(priv, (u8)tmp_val); + pcurrent_stats->rssi = priv->stats.signal_strength; + if(!pprevious_stats->bPacketMatchBSSID) + { + if(!pprevious_stats->bToSelfBA) + return; + } + + if(!bcheck) + return; + + rtl819x_process_cck_rxpathsel(priv,pprevious_stats); + + priv->stats.num_process_phyinfo++; +#if 0 + if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) + { + slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX; + last_rssi = priv->stats.slide_signal_strength[slide_rssi_index]; + priv->stats.slide_rssi_total -= last_rssi; + } + priv->stats.slide_rssi_total += pprevious_stats->SignalStrength; + + priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength; + if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX) + slide_rssi_index = 0; + + tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics; + priv->stats.signal_strength = rtl819x_translate_todbm(priv, (u8)tmp_val); + +#endif + if(!pprevious_stats->bIsCCK && pprevious_stats->bPacketToSelf) + { + for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) + { + if (!rtl8192_phy_CheckIsLegalRFPath(priv->rtllib->dev, rfpath)) + continue; + RT_TRACE(COMP_DBG,"Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d \n" ,pprevious_stats->RxMIMOSignalStrength[rfpath] ); + if(priv->stats.rx_rssi_percentage[rfpath] == 0) + { + priv->stats.rx_rssi_percentage[rfpath] = pprevious_stats->RxMIMOSignalStrength[rfpath]; + } + if(pprevious_stats->RxMIMOSignalStrength[rfpath] > priv->stats.rx_rssi_percentage[rfpath]) + { + priv->stats.rx_rssi_percentage[rfpath] = + ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) + + (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor); + priv->stats.rx_rssi_percentage[rfpath] = priv->stats.rx_rssi_percentage[rfpath] + 1; + } + else + { + priv->stats.rx_rssi_percentage[rfpath] = + ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) + + (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor); + } + RT_TRACE(COMP_DBG,"Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d \n" ,priv->stats.rx_rssi_percentage[rfpath] ); + } + } + + + if(pprevious_stats->bPacketBeacon) + { + if(slide_beacon_adc_pwdb_statistics++ >= PHY_Beacon_RSSI_SLID_WIN_MAX) + { + slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX; + last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index]; + priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb; + } + priv->stats.Slide_Beacon_Total += pprevious_stats->RxPWDBAll; + priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = pprevious_stats->RxPWDBAll; + slide_beacon_adc_pwdb_index++; + if(slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX) + slide_beacon_adc_pwdb_index = 0; + pprevious_stats->RxPWDBAll = priv->stats.Slide_Beacon_Total/slide_beacon_adc_pwdb_statistics; + if(pprevious_stats->RxPWDBAll >= 3) + pprevious_stats->RxPWDBAll -= 3; + } + + RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n", + pprevious_stats->bIsCCK? "CCK": "OFDM", + pprevious_stats->RxPWDBAll); + + if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA) + { + if(priv->undecorated_smoothed_pwdb < 0) + { + priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll; + } +#if 1 + if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) + { + priv->undecorated_smoothed_pwdb = + ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) + + (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor); + priv->undecorated_smoothed_pwdb = priv->undecorated_smoothed_pwdb + 1; + } + else + { + priv->undecorated_smoothed_pwdb = + ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) + + (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor); + } +#else + if(pPreviousRfd->Status.RxPWDBAll > (u32)pHalData->UndecoratedSmoothedPWDB) + { + pHalData->UndecoratedSmoothedPWDB = + ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6; + pHalData->UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB + 1; + } + else + { + pHalData->UndecoratedSmoothedPWDB = + ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6; + } +#endif + rtl819x_update_rxsignalstatistics8190pci(priv,pprevious_stats); + } + + if(pprevious_stats->SignalQuality == 0) + { + } + else + { + if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA){ + if(slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX){ + slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX; + last_evm = priv->stats.slide_evm[slide_evm_index]; + priv->stats.slide_evm_total -= last_evm; + } + + priv->stats.slide_evm_total += pprevious_stats->SignalQuality; + + priv->stats.slide_evm[slide_evm_index++] = pprevious_stats->SignalQuality; + if(slide_evm_index >= PHY_RSSI_SLID_WIN_MAX) + slide_evm_index = 0; + + tmp_val = priv->stats.slide_evm_total/slide_evm_statistics; + priv->stats.signal_quality = tmp_val; + priv->stats.last_signal_strength_inpercent = tmp_val; + } + + if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA) + { + for(nspatial_stream = 0; nspatial_stream<2 ; nspatial_stream++) + { + if(pprevious_stats->RxMIMOSignalQuality[nspatial_stream] != -1) + { + if(priv->stats.rx_evm_percentage[nspatial_stream] == 0) + { + priv->stats.rx_evm_percentage[nspatial_stream] = pprevious_stats->RxMIMOSignalQuality[nspatial_stream]; + } + priv->stats.rx_evm_percentage[nspatial_stream] = + ( (priv->stats.rx_evm_percentage[nspatial_stream]* (Rx_Smooth_Factor-1)) + + (pprevious_stats->RxMIMOSignalQuality[nspatial_stream]* 1)) / (Rx_Smooth_Factor); + } + } + } + } +#endif + +} + + + +void rtl8192se_TranslateRxSignalStuff(struct net_device *dev, + struct sk_buff *skb, + struct rtllib_rx_stats * pstats, + prx_desc pdesc, + prx_fwinfo pdrvinfo) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + bool bpacket_match_bssid, bpacket_toself; + bool bPacketBeacon=false; + struct rtllib_hdr_3addr *hdr; +#ifdef _RTL8192_EXT_PATCH_ + struct rtllib_network* pnet=NULL; +#else + bool bToSelfBA=false; + static struct rtllib_rx_stats previous_stats; +#endif + u16 fc,type; + + + u8* tmp_buf; + u8 *praddr; +#ifdef _RTL8192_EXT_PATCH_ + u8 *psaddr; +#endif + + tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift; + + hdr = (struct rtllib_hdr_3addr *)tmp_buf; + fc = le16_to_cpu(hdr->frame_ctl); + type = WLAN_FC_GET_TYPE(fc); + praddr = hdr->addr1; + +#ifdef _RTL8192_EXT_PATCH_ + psaddr = hdr->addr2; + if((priv->rtllib->iw_mode == IW_MODE_MESH) && (priv->mshobj->ext_patch_get_mpinfo)) + pnet = priv->mshobj->ext_patch_get_mpinfo(dev,psaddr); +#endif +#ifdef _RTL8192_EXT_PATCH_ + bpacket_match_bssid = ((RTLLIB_FTYPE_CTL != type) && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV)); + if(pnet){ + bpacket_match_bssid = bpacket_match_bssid; + } + else{ + bpacket_match_bssid = bpacket_match_bssid && + (!compare_ether_addr(priv->rtllib->current_network.bssid, + (fc & RTLLIB_FCTL_TODS)? hdr->addr1 : + (fc & RTLLIB_FCTL_FROMDS )? hdr->addr2 : hdr->addr3)); + } +#else + bpacket_match_bssid = ((RTLLIB_FTYPE_CTL != type) && + (!compare_ether_addr(priv->rtllib->current_network.bssid, + (fc & RTLLIB_FCTL_TODS)? hdr->addr1 : + (fc & RTLLIB_FCTL_FROMDS )? hdr->addr2 : hdr->addr3)) + && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV)); +#endif + bpacket_toself = bpacket_match_bssid & (!compare_ether_addr(praddr, priv->rtllib->dev->dev_addr)); + if(WLAN_FC_GET_FRAMETYPE(fc)== RTLLIB_STYPE_BEACON) + { + bPacketBeacon = true; + } +#ifndef _RTL8192_EXT_PATCH_ + if(WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BLOCKACK) + { + if ((!compare_ether_addr(praddr,dev->dev_addr))) + bToSelfBA = true; + } + +#endif + if(bpacket_match_bssid) + { + priv->stats.numpacket_matchbssid++; + } + if(bpacket_toself){ + priv->stats.numpacket_toself++; + } +#ifdef _RTL8192_EXT_PATCH_ + rtl8192se_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, bpacket_match_bssid, + bpacket_toself ,bPacketBeacon); + rtl8192se_process_phyinfo(priv, tmp_buf,pstats,pnet); + +#else + rtl8192se_process_phyinfo(priv, tmp_buf,&previous_stats, pstats); + rtl8192se_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, &previous_stats, bpacket_match_bssid, + bpacket_toself ,bPacketBeacon, bToSelfBA); + rtl8192x_record_rxdesc_forlateruse(pstats, &previous_stats); +#endif + +} + +void rtl8192se_UpdateReceivedRateHistogramStatistics( + struct net_device *dev, + struct rtllib_rx_stats* pstats + ) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u32 rcvType=1; + u32 rateIndex; + u32 preamble_guardinterval; + + #if 0 + if (pRfd->queue_id == CMPK_RX_QUEUE_ID) + return; + #endif + if(pstats->bCRC) + rcvType = 2; + else if(pstats->bICV) + rcvType = 3; + + if(pstats->bShortPreamble) + preamble_guardinterval = 1; + else + preamble_guardinterval = 0; + + switch(pstats->rate) + { + case MGN_1M: rateIndex = 0; break; + case MGN_2M: rateIndex = 1; break; + case MGN_5_5M: rateIndex = 2; break; + case MGN_11M: rateIndex = 3; break; + case MGN_6M: rateIndex = 4; break; + case MGN_9M: rateIndex = 5; break; + case MGN_12M: rateIndex = 6; break; + case MGN_18M: rateIndex = 7; break; + case MGN_24M: rateIndex = 8; break; + case MGN_36M: rateIndex = 9; break; + case MGN_48M: rateIndex = 10; break; + case MGN_54M: rateIndex = 11; break; + case MGN_MCS0: rateIndex = 12; break; + case MGN_MCS1: rateIndex = 13; break; + case MGN_MCS2: rateIndex = 14; break; + case MGN_MCS3: rateIndex = 15; break; + case MGN_MCS4: rateIndex = 16; break; + case MGN_MCS5: rateIndex = 17; break; + case MGN_MCS6: rateIndex = 18; break; + case MGN_MCS7: rateIndex = 19; break; + case MGN_MCS8: rateIndex = 20; break; + case MGN_MCS9: rateIndex = 21; break; + case MGN_MCS10: rateIndex = 22; break; + case MGN_MCS11: rateIndex = 23; break; + case MGN_MCS12: rateIndex = 24; break; + case MGN_MCS13: rateIndex = 25; break; + case MGN_MCS14: rateIndex = 26; break; + case MGN_MCS15: rateIndex = 27; break; + default: rateIndex = 28; break; + } + priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++; + priv->stats.received_rate_histogram[0][rateIndex]++; + priv->stats.received_rate_histogram[rcvType][rateIndex]++; +} + +bool rtl8192se_rx_query_status_desc(struct net_device* dev, struct rtllib_rx_stats* stats, rx_desc *pdesc, struct sk_buff* skb) +{ + struct r8192_priv* priv = rtllib_priv(dev); + struct rtllib_device* ieee = priv->rtllib; + u32 PHYStatus = pdesc->PHYStatus; + rx_fwinfo* pDrvInfo; + stats->Length = (u16)pdesc->Length; + stats->RxDrvInfoSize = (u8)pdesc->DrvInfoSize*8; + stats->RxBufShift = (u8)((pdesc->Shift)&0x03); + stats->bICV = (u16)pdesc->ICVError; + stats->bCRC = (u16)pdesc->CRC32; + stats->bHwError = (u16)(pdesc->CRC32|pdesc->ICVError); + stats->Decrypted = !pdesc->SWDec; + stats->rate = (u8)pdesc->RxMCS; + stats->bShortPreamble= (u16)pdesc->SPLCP; + stats->bIsAMPDU = (bool)(pdesc->PAGGR==1); + stats->bFirstMPDU = (bool)((pdesc->PAGGR==1) && (pdesc->FAGGR==1)); + stats->TimeStampLow = pdesc->TSFL; + stats->RxIs40MHzPacket= (bool)pdesc->BandWidth; + if(IS_UNDER_11N_AES_MODE(ieee)) + { + if(stats->bICV && !stats->bCRC) + { + stats->bICV = false; + stats->bHwError = false; + } + } + + + if(stats->Length > 0x2000 || stats->Length < 24) + { + RT_TRACE(COMP_ERR, "Err RX pkt len = 0x%x\n", stats->Length); + stats->bHwError |= 1; + } + rtl8192se_UpdateReceivedRateHistogramStatistics(dev, stats); + + if(!stats->bHwError) + stats->rate = HwRateToMRate92S((bool)(pdesc->RxHT), (u8)(pdesc->RxMCS)); + else + { + stats->rate = MGN_1M; + return false; + } + + rtl819x_UpdateRxPktTimeStamp(dev, stats); + + if((stats->RxBufShift + stats->RxDrvInfoSize) > 0) + stats->bShift = 1; + + if (PHYStatus == true) + { + pDrvInfo = (rx_fwinfo*)(skb->data + stats->RxBufShift); + + rtl8192se_TranslateRxSignalStuff(dev, skb, stats, pdesc, pDrvInfo); + + } + return true; +} + +void rtl8192se_halt_adapter(struct net_device *dev, bool bReset) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int i; + u8 wait = 30; + + RT_TRACE(COMP_INIT, "==> rtl8192se_halt_adapter()\n"); + +#if 1 + while (wait-- >= 10 && priv->PwrDomainProtect == true) + { + if (priv->PwrDomainProtect == true) + { + RT_TRACE(COMP_INIT, "Delay 20ms to wait PwrDomainProtect\n"); + mdelay(20); + } + else + break; + } + + if (wait == 9) + RT_TRACE(COMP_INIT, "PwrDomainProtect FAIL\n"); +#endif + + priv->rtllib->state = RTLLIB_NOLINK; + rtl8192se_update_msr(dev); +#if 1 + PHY_SetRtl8192seRfHalt(dev); +#endif + udelay(100); + +#if 0 + udelay(20); + if (!bReset) { + mdelay(20); + } +#endif + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_purge(&priv->rtllib->skb_waitQ [i]); + } + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_purge(&priv->rtllib->skb_aggQ [i]); + } +#ifdef _RTL8192_EXT_PATCH_ + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_purge(&priv->rtllib->skb_meshaggQ [i]); + } +#endif + + skb_queue_purge(&priv->skb_queue); + RT_TRACE(COMP_INIT, "<== HaltAdapter8192SE()\n"); + return; +} + +u8 GetFreeRATRIndex8192SE (struct net_device* dev) +{ + struct r8192_priv* priv = rtllib_priv(dev); + u8 bitmap = priv->RATRTableBitmap; + u8 ratr_index = 0; + for( ;ratr_index<7; ratr_index++) + { + if((bitmap & BIT0) == 0) + { + priv->RATRTableBitmap |= BIT0<<ratr_index; + return ratr_index; + } + bitmap = bitmap >>1; + } + return ratr_index; +} + +void rtl8192se_update_ratr_table(struct net_device* dev,u8* pMcsRate,struct sta_info* pEntry) +{ + struct r8192_priv* priv = rtllib_priv(dev); + struct rtllib_device* ieee = priv->rtllib; + u32 ratr_value = 0; + u8 ratr_index = 0; + u8 bNMode = 0; + u16 shortGI_rate = 0; + u32 tmp_ratr_value = 0; + u8 MimoPs; + WIRELESS_MODE WirelessMode; + u8 bCurTxBW40MHz, bCurShortGI40MHz, bCurShortGI20MHz; + + if(ieee->iw_mode == IW_MODE_ADHOC){ + + if(pEntry == NULL){ + printk("Doesn't have match Entry\n"); + return; + } + + if(pEntry->ratr_index != 8) + ratr_index = pEntry->ratr_index; + else + ratr_index = GetFreeRATRIndex8192SE(dev); + + if(ratr_index == 7){ + RT_TRACE(COMP_RATE, "Ratrtable are full"); + return; + } + MimoPs = pEntry->htinfo.MimoPs; + + if((ieee->mode == WIRELESS_MODE_G) && (pEntry->wireless_mode == WIRELESS_MODE_N_24G)) + WirelessMode = ieee->mode; + else + WirelessMode = pEntry->wireless_mode; + + bCurTxBW40MHz = pEntry->htinfo.bCurTxBW40MHz; + bCurShortGI40MHz = pEntry->htinfo.bCurShortGI40MHz; + bCurShortGI20MHz = pEntry->htinfo.bCurShortGI20MHz; + pEntry->ratr_index = ratr_index; + } + else + { + ratr_index = 0; + WirelessMode = ieee->mode; + MimoPs = ieee->pHTInfo->PeerMimoPs; + bCurTxBW40MHz = ieee->pHTInfo->bCurTxBW40MHz; + bCurShortGI40MHz = ieee->pHTInfo->bCurShortGI40MHz; + bCurShortGI20MHz = ieee->pHTInfo->bCurShortGI20MHz; + } + + rtl8192_config_rate(dev, (u16*)(&ratr_value)); + ratr_value |= (*(u16*)(pMcsRate)) << 12; + switch (WirelessMode) + { + case IEEE_A: + ratr_value &= 0x00000FF0; + break; + case IEEE_B: + ratr_value &= 0x0000000D; + break; + case IEEE_G: + case IEEE_G|IEEE_B: + ratr_value &= 0x00000FF5; + break; + case IEEE_N_24G: + case IEEE_N_5G: + bNMode = 1; + if (MimoPs == 0) + ratr_value &= 0x0007F005; + else{ + if (priv->rf_type == RF_1T2R ||priv->rf_type == RF_1T1R || (ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_2SS)){ + if ((bCurTxBW40MHz) && !(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_40_MHZ)) + ratr_value &= 0x000FF015; + else + ratr_value &= 0x000ff005; + }else{ + if ((bCurTxBW40MHz) && !(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_40_MHZ)) + ratr_value &= 0x0f0ff015; + else + ratr_value &= 0x0f0ff005; + } + } + break; + default: + printk("====>%s(), mode is not correct:%x\n", __FUNCTION__,WirelessMode); + break; + } + if (priv->card_8192_version>= VERSION_8192S_BCUT) + ratr_value &= 0x0FFFFFFF; + else if (priv->card_8192_version == VERSION_8192S_ACUT) + ratr_value &= 0x0FFFFFF0; + + if (((ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI)==0) && + bNMode && ((bCurTxBW40MHz && bCurShortGI40MHz) || + (!bCurTxBW40MHz && bCurShortGI20MHz))) + { + ratr_value |= 0x10000000; + tmp_ratr_value = (ratr_value>>12); + for(shortGI_rate=15; shortGI_rate>0; shortGI_rate--) + { + if((1<<shortGI_rate) & tmp_ratr_value) + break; + } + shortGI_rate = (shortGI_rate<<12)|(shortGI_rate<<8)|\ + (shortGI_rate<<4)|(shortGI_rate); + write_nic_byte(dev, SG_RATE, shortGI_rate); + } + + if(ieee->pHTInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) + { + ratr_value &= 0xfffffff0; + printk("UpdateHalRATRTable8192SE(), for HT_IOT_ACT_WA_IOT_Broadcom, ratr_value = 0x%x\n", ratr_value); + } + + write_nic_dword(dev, ARFR0+ratr_index*4, ratr_value); + if (ratr_value & 0xfffff000){ + rtl8192se_set_fw_cmd(dev, FW_CMD_RA_REFRESH_N); + } + else{ + rtl8192se_set_fw_cmd(dev, FW_CMD_RA_REFRESH_BG); + } +} + +int r8192se_resume_firm(struct net_device *dev) +{ + write_nic_byte(dev, 0x42, 0xFF); + write_nic_word(dev, 0x40, 0x77FC); + write_nic_word(dev, 0x40, 0x57FC); + write_nic_word(dev, 0x40, 0x37FC); + write_nic_word(dev, 0x40, 0x77FC); + + udelay(100); + + write_nic_word(dev, 0x40, 0x57FC); + write_nic_word(dev, 0x40, 0x37FC); + write_nic_byte(dev, 0x42, 0x00); + + return 0; +} +void PHY_SetRtl8192seRfHalt(struct net_device* dev) +{ + struct r8192_priv* priv = rtllib_priv(dev); + PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl)); + u8 u1bTmp; + + if(priv->rtllib->RfOffReason == RF_CHANGE_BY_IPS && priv->LedStrategy == SW_LED_MODE8) + { + SET_RTL8192SE_RF_SLEEP(dev); + return; + } + +#ifdef LOW_DOWN_POWER + if(0) +#else + if(priv->bDriverIsGoingToUnload) +#endif + write_nic_byte(dev,0x560,0x0); + + RT_TRACE(COMP_PS, "PHY_SetRtl8192seRfHalt save BB/RF\n"); + u1bTmp = read_nic_byte(dev, LDOV12D_CTRL); + u1bTmp |= BIT0; + write_nic_byte(dev, LDOV12D_CTRL, u1bTmp); + write_nic_byte(dev, SPS1_CTRL, 0x0); + write_nic_byte(dev, TXPAUSE, 0xFF); + write_nic_word(dev, CMDR, 0x57FC); + udelay(100); + write_nic_word(dev, CMDR, 0x77FC); + write_nic_byte(dev, PHY_CCA, 0x0); + udelay(10); + write_nic_word(dev, CMDR, 0x37FC); + udelay(10); + write_nic_word(dev, CMDR, 0x77FC); + udelay(10); + write_nic_word(dev, CMDR, 0x57FC); + write_nic_word(dev, CMDR, 0x0000); + + +#ifdef LOW_DOWN_POWER + if(0) +#else + if(priv->bDriverIsGoingToUnload) +#endif + { + u1bTmp = read_nic_byte(dev, (SYS_FUNC_EN+ 1)); + u1bTmp &= ~(BIT0); + write_nic_byte(dev, SYS_FUNC_EN+1, u1bTmp); + } + + + u1bTmp = read_nic_byte(dev, (SYS_CLKR + 1)); + + if (u1bTmp & BIT7) { + u1bTmp &= ~(BIT6 | BIT7); + if(!HalSetSysClk8192SE(dev, u1bTmp)) { + printk("Switch ctrl path fail\n"); + return; + } + } + +#ifdef LOW_DOWN_POWER + if((priv->rtllib->RfOffReason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW)) && + !priv->bDriverIsGoingToUnload) +#else + if(priv->rtllib->RfOffReason==RF_CHANGE_BY_IPS && !priv->bDriverIsGoingToUnload) +#endif + { + write_nic_byte(dev, 0x03, 0xF9); + } else + { + write_nic_byte(dev, 0x03, 0xF9); + } + write_nic_byte(dev, SYS_CLKR+1, 0x70); + write_nic_byte(dev, AFE_PLL_CTRL+1, 0x68); + write_nic_byte(dev, AFE_PLL_CTRL, 0x00); + write_nic_byte(dev, LDOA15_CTRL, 0x34); + write_nic_byte(dev, AFE_XTAL_CTRL, 0x0E); + RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); +} + + +/* +* Description: +* Set RateAdaptive Mask +* /param Adapter Pionter to Adapter entity +* /param bMulticast TURE if broadcast or multicast, used for softAP basic rate +* /param macId macID to set +* /param wirelessMode wireless mode of associated AP/client +* /return void +* +*/ +#ifdef _RTL8192_EXT_PATCH_ +void UpdateHalRAMask8192SE( + struct net_device* dev, + bool bMulticast, + u8 macId, + u8* MacAddr, + u8 wirelessMode, + u8 rssi_level) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + PRT_HIGH_THROUGHPUT pHTInfo =ieee->pHTInfo; + u32 ratr_bitmap, RateSet; + u8 shortGI_rate = 0; + u32 tmp_ratr_value = 0; + u32 mask=0, band = 0; + u8 bShortGI = 0; + + rtl8192_config_rate(dev, (u16*)(&RateSet)); + RateSet |= (*((u16*)(ieee->dot11HTOperationalRateSet))) << 12; + ratr_bitmap = RateSet; + + switch (wirelessMode) + { + case WIRELESS_MODE_B: + { + band |= WIRELESS_11B; + ratr_bitmap &= 0x0000000d; + } + break; + + case WIRELESS_MODE_G: + { + band |= (WIRELESS_11G | WIRELESS_11B); + if(rssi_level == 1) + ratr_bitmap &= 0x00000f00; + else if(rssi_level == 2) + ratr_bitmap &= 0x00000ff0; + else + ratr_bitmap &= 0x00000ff5; + } + break; + + case WIRELESS_MODE_A: + { + band |= BIT2; + ratr_bitmap &= 0x00000ff0; + } + break; + + case WIRELESS_MODE_N_24G: + case WIRELESS_MODE_N_5G: + { + band |= (WIRELESS_11N| WIRELESS_11G| WIRELESS_11B); + if(macId == 0) + { + if(ieee->pHTInfo->PeerMimoPs == MIMO_PS_STATIC) + { + if(rssi_level == 1) + ratr_bitmap &= 0x00070000; + else if(rssi_level == 2) + ratr_bitmap &= 0x0007f000; + else + ratr_bitmap &= 0x0007f005; + } + else + { + if ( priv->rf_type == RF_1T2R || + priv->rf_type == RF_1T1R ) + { + if (pHTInfo->bCurTxBW40MHz) + { + if(rssi_level == 1) + ratr_bitmap &= 0x000f0000; + else if(rssi_level == 2) + ratr_bitmap &= 0x000ff000; + else + ratr_bitmap &= 0x000ff015; + } + else + { + if(rssi_level == 1) + ratr_bitmap &= 0x000f0000; + else if(rssi_level == 2) + ratr_bitmap &= 0x000ff000; + else + ratr_bitmap &= 0x000ff005; + } + } + else + { + if (pHTInfo->bCurTxBW40MHz) + { + if(rssi_level == 1) + ratr_bitmap &= 0x0f0f0000; + else if(rssi_level == 2) + ratr_bitmap &= 0x0f0ff000; + else + ratr_bitmap &= 0x0f0ff015; + } + else + { + if(rssi_level == 1) + ratr_bitmap &= 0x0f0f0000; + else if(rssi_level == 2) + ratr_bitmap &= 0x0f0ff000; + else + ratr_bitmap &= 0x0f0ff005; + } + } + } + + if( (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) || + (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz) ) + { + bShortGI = true; + + tmp_ratr_value = (ratr_bitmap>>12); + for(shortGI_rate=15; shortGI_rate>0; shortGI_rate--) + { + if((1<<shortGI_rate) & tmp_ratr_value) + break; + } + shortGI_rate = (shortGI_rate<<12)|(shortGI_rate<<8)|(shortGI_rate<<4)|(shortGI_rate); + write_nic_byte(dev, SG_RATE, shortGI_rate); + } + } + else if(macId == 1) + { + if ( priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R ) + { + if (pHTInfo->bCurBW40MHz) + { + ratr_bitmap &= 0x000ff015; + } + else + { + ratr_bitmap &= 0x000ff005; + } + } + else + { + if (pHTInfo->bCurBW40MHz) + { + ratr_bitmap &= 0x0f0ff015; + } + else + { + ratr_bitmap &= 0x0f0ff005; + } + } + } + else + { + if(ieee->iw_mode == IW_MODE_MESH) + { + if(ieee->ext_patch_rtllib_update_ratr_mask) + ieee->ext_patch_rtllib_update_ratr_mask(dev,MacAddr,rssi_level,&ratr_bitmap,&bShortGI); + } + } + } + break; + + default: + { + band |= (WIRELESS_11N| WIRELESS_11G| WIRELESS_11B); + if(priv->rf_type == RF_1T2R) + { + ratr_bitmap &= 0x000ff0ff; + } + else + { + ratr_bitmap &= 0x0f0ff0ff; + } + } + } + + if (priv->card_8192_version >= VERSION_8192S_BCUT) + ratr_bitmap &= 0x0FFFFFFF; + else if (priv->card_8192_version == VERSION_8192S_ACUT) + ratr_bitmap &= 0x0FFFFFF0; + + if(bShortGI) + ratr_bitmap |= 0x10000000; + + if(macId == 0) + { + if(pHTInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) + { + ratr_bitmap &= 0xfffffff0; + RT_TRACE(COMP_RATE, "UpdateHalRATRTable8192SE(), for HT_IOT_ACT_WA_IOT_Broadcom, ratr_value = 0x%x\n", ratr_bitmap); + } + if(pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI) + { + ratr_bitmap &=0x0fffffff; + } + } + mask |= (bMulticast ? 1 : 0)<<9 | (macId & 0x1f)<<4 | (band & 0xf); + + RT_TRACE(COMP_RATE, "UpdateHalRAMask92SE(): mask = %x, bitmap = %x\n", mask, ratr_bitmap); + write_nic_dword(dev, 0x2c4, ratr_bitmap); + write_nic_dword(dev, WFM5, (FW_RA_UPDATE_MASK | (mask << 8))); + +} +#else +void +UpdateHalRAMask8192SE( + struct net_device* dev, + bool bMulticast, + u8 macId, + u8* MacAddr, + u8* pEntry, + u8 rssi_level) + +{ + struct r8192_priv* priv = rtllib_priv(dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->rtllib->pHTInfo; + WIRELESS_MODE WirelessMode = WIRELESS_MODE_G; + u32 ratr_bitmap, RateSet; + u8 shortGI_rate = 0, MimoPs = 0, ratr_index = 8; + u32 tmp_ratr_value = 0; + u32 mask=0, band = 0; + bool bShortGI = false, bCurTxBW40MHz = 0; + struct rtllib_device* ieee = priv->rtllib; + u8* pMcsRate = ieee->dot11HTOperationalRateSet; + + if(macId == 0) + { + MimoPs = pHTInfo->PeerMimoPs; + WirelessMode = priv->rtllib->mode; + bCurTxBW40MHz = pHTInfo->bCurTxBW40MHz; + } + else if (macId == 1) + { + WirelessMode = WIRELESS_MODE_B; + } + else + { +#ifdef DO_DO_LIST + if(pEntry == NULL) + { + printk("Doesn't have match Entry\n"); + return; + } + + MimoPs = pEntry->HTInfo.MimoPs; + + if(IS_WIRELESS_MODE_G(Adapter) && (pEntry->WirelessMode == WIRELESS_MODE_N_24G)) + WirelessMode = pMgntInfo->dot11CurrentWirelessMode; + else + WirelessMode = pEntry->WirelessMode; + + bCurTxBW40MHz = pEntry->HTInfo.bBw40MHz; +#endif + } + rtl8192_config_rate(dev, (u16*)&RateSet); + RateSet |= (*(u16*)(pMcsRate)) << 12; + ratr_bitmap = RateSet; + switch (WirelessMode) + { + case WIRELESS_MODE_B: + { + band |= WIRELESS_11B; + ratr_index = RATR_INX_WIRELESS_B; + ratr_bitmap &= 0x0000000d; + } + break; + + case WIRELESS_MODE_G: + case (WIRELESS_MODE_G |WIRELESS_MODE_B): + { + band |= (WIRELESS_11G | WIRELESS_11B); + ratr_index = RATR_INX_WIRELESS_GB; + + if(rssi_level == 1) + ratr_bitmap &= 0x00000f00; + else if(rssi_level == 2) + ratr_bitmap &= 0x00000ff0; + else + ratr_bitmap &= 0x00000ff5; + } + break; + + case WIRELESS_MODE_A: + { + band |= WIRELESS_11A; + ratr_index = RATR_INX_WIRELESS_A; + ratr_bitmap &= 0x00000ff0; + } + break; + + case WIRELESS_MODE_N_24G: + case WIRELESS_MODE_N_5G: + { + band |= (WIRELESS_11N| WIRELESS_11G| WIRELESS_11B); + ratr_index = RATR_INX_WIRELESS_NGB; + + if(MimoPs == MIMO_PS_STATIC) + { + if(rssi_level == 1) + ratr_bitmap &= 0x00070000; + else if(rssi_level == 2) + ratr_bitmap &= 0x0007f000; + else + ratr_bitmap &= 0x0007f005; + } + else + { + if ( priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R ) + { + if (bCurTxBW40MHz) + { + if(rssi_level == 1) + ratr_bitmap &= 0x000f0000; + else if(rssi_level == 2) + ratr_bitmap &= 0x000ff000; + else + ratr_bitmap &= 0x000ff015; + } + else + { + if(rssi_level == 1) + ratr_bitmap &= 0x000f0000; + else if(rssi_level == 2) + ratr_bitmap &= 0x000ff000; + else + ratr_bitmap &= 0x000ff005; + } + } + else + { + if (bCurTxBW40MHz) + { + if(rssi_level == 1) + ratr_bitmap &= 0x0f0f0000; + else if(rssi_level == 2) + ratr_bitmap &= 0x0f0ff000; + else + ratr_bitmap &= 0x0f0ff015; + } + else + { + if(rssi_level == 1) + ratr_bitmap &= 0x0f0f0000; + else if(rssi_level == 2) + ratr_bitmap &= 0x0f0ff000; + else + ratr_bitmap &= 0x0f0ff005; + } + } + } + if( (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) || + (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz) ) + { + if(macId == 0) + bShortGI = true; + else + bShortGI = false; + } + } + break; + + default: + band |= (WIRELESS_11N| WIRELESS_11G| WIRELESS_11B); + ratr_index = RATR_INX_WIRELESS_NGB; + + if(priv->rf_type == RF_1T2R) + ratr_bitmap &= 0x000ff0ff; + else + ratr_bitmap &= 0x0f0ff0ff; + break; + } + + if (priv->card_8192_version >= VERSION_8192S_BCUT) + ratr_bitmap &= 0x0FFFFFFF; + else if (priv->card_8192_version == VERSION_8192S_ACUT) + ratr_bitmap &= 0x0FFFFFF0; + + if(bShortGI) + { + ratr_bitmap |= 0x10000000; + tmp_ratr_value = (ratr_bitmap>>12); + for(shortGI_rate=15; shortGI_rate>0; shortGI_rate--) + { + if((1<<shortGI_rate) & tmp_ratr_value) + break; + } + shortGI_rate = (shortGI_rate<<12)|(shortGI_rate<<8)|(shortGI_rate<<4)|(shortGI_rate); + write_nic_byte(dev, SG_RATE, shortGI_rate); + } + + if(macId == 0) { + if(priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) + ratr_bitmap &= 0xfffffff0; + if(priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI) + ratr_bitmap &=0x0fffffff; + } + + + mask |= (bMulticast ? 1 : 0)<<9 | (macId & 0x1f)<<4 | (band & 0xf); + + RT_TRACE(COMP_RATE, "UpdateHalRAMask92SE(): mask = %x, bitmap = %x ratr_index = %x\n", mask, ratr_bitmap, ratr_index); + write_nic_dword(dev, 0x2c4, ratr_bitmap); + write_nic_dword(dev, WFM5, (FW_RA_UPDATE_MASK | (mask << 8))); + +} +#endif + +u8 HalSetSysClk8192SE( struct net_device *dev, u8 Data) +{ +#if 0 + write_nic_byte(dev, (SYS_CLKR + 1), Data); + udelay(200);; + return 1; +#else + { + u8 WaitCount = 100; + bool bResult = false; + +#ifdef TO_DO_LIST + RT_DISABLE_FUNC(Adapter, DF_IO_BIT); + + do + { + if(pDevice->IOCount == 0) + break; + delay_us(10); + }while(WaitCount -- > 0); + + if(WaitCount == 0) + { + RT_ENABLE_FUNC(Adapter, DF_IO_BIT); + RT_TRACE(COMP_POWER, DBG_WARNING, ("HalSetSysClk8192SE(): Wait too long! Skip ....\n")); + return false; + } + #endif + write_nic_byte(dev,SYS_CLKR + 1,Data); + + udelay(400); + + + { + u8 TmpValue; + TmpValue=read_nic_byte(dev,SYS_CLKR + 1); + bResult = ((TmpValue&BIT7)== (Data & BIT7)); + if((Data &(BIT6|BIT7)) == false) + { + WaitCount = 100; + TmpValue = 0; + while(1) + { + WaitCount--; + TmpValue=read_nic_byte(dev, SYS_CLKR + 1); + if((TmpValue &BIT6)) + break; + printk("wait for BIT6 return value %x\n",TmpValue); + if(WaitCount==0) + break; + udelay(10); + } + if(WaitCount == 0) + bResult = false; + else + bResult = true; + } + } +#ifdef TO_DO_LIST + RT_ENABLE_FUNC(Adapter, DF_IO_BIT); +#endif + RT_TRACE(COMP_PS,"HalSetSysClk8192SE():Value = %02X, return: %d\n", Data, bResult); + return bResult; + } +#endif +} + +static u8 LegacyRateSet[12] = {0x02 , 0x04 , 0x0b , 0x16 , 0x0c , 0x12 , 0x18 , 0x24 , 0x30 , 0x48 , 0x60 , 0x6c}; +void GetHwReg8192SE(struct net_device *dev,u8 variable,u8* val) +{ + struct r8192_priv* priv = rtllib_priv(dev); + switch(variable) + { + case HW_VAR_INIT_TX_RATE: + { + u8 RateIdx = read_nic_byte(dev, TX_RATE_REG); + if(RateIdx < 76) + *((u8*)(val)) = (RateIdx<12)?(LegacyRateSet[RateIdx]):((RateIdx-12)|0x80); + else + *((u8*)(val)) = 0; + } + break; + + case HW_VAR_RCR: + *((u32*)(val)) = priv->ReceiveConfig; + break; + + default: + break; + } +} + +void SetHwReg8192SE(struct net_device *dev,u8 variable,u8* val) +{ + struct r8192_priv* priv = rtllib_priv(dev); + switch(variable) + { + case HW_VAR_AMPDU_MIN_SPACE: + { + u8 MinSpacingToSet; + u8 SecMinSpace; + + MinSpacingToSet = *((u8*)val); + if(MinSpacingToSet <= 7) + { + if((priv->rtllib->current_network.capability & WLAN_CAPABILITY_PRIVACY) == 0) + SecMinSpace = 0; + else if (priv->rtllib->rtllib_ap_sec_type && + (priv->rtllib->rtllib_ap_sec_type(priv->rtllib) + & (SEC_ALG_WEP|SEC_ALG_TKIP))) + SecMinSpace = 7; + else + SecMinSpace = 1; + + if(MinSpacingToSet < SecMinSpace) + MinSpacingToSet = SecMinSpace; + priv->rtllib->MinSpaceCfg = ((priv->rtllib->MinSpaceCfg&0xf8) |MinSpacingToSet); + RT_TRACE(COMP_MLME, "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", priv->rtllib->MinSpaceCfg); + write_nic_byte(dev, AMPDU_MIN_SPACE, priv->rtllib->MinSpaceCfg); + } + } + break; + case HW_VAR_SHORTGI_DENSITY: + { + u8 DensityToSet; + + DensityToSet = *((u8*)val); + priv->rtllib->MinSpaceCfg|= (DensityToSet<<3); + RT_TRACE(COMP_MLME, "Set HW_VAR_SHORTGI_DENSITY: %#x\n", priv->rtllib->MinSpaceCfg); + write_nic_byte(dev, AMPDU_MIN_SPACE, priv->rtllib->MinSpaceCfg); + break; + } + case HW_VAR_AMPDU_FACTOR: + { + u8 FactorToSet; + u8 RegToSet; + u8 FactorLevel[18] = {2, 4, 4, 7, 7, 13, 13, 13, 2, 7, 7, 13, 13, 15, 15, 15, 15, 0}; + u8 index = 0; + + FactorToSet = *((u8*)val); + if(FactorToSet <= 3) + { + FactorToSet = (1<<(FactorToSet + 2)); + if(FactorToSet>0xf) + FactorToSet = 0xf; + + for(index=0; index<17; index++) + { + if(FactorLevel[index] > FactorToSet) + FactorLevel[index] = FactorToSet; + } + + for(index=0; index<8; index++) + { + RegToSet = ((FactorLevel[index*2]) | (FactorLevel[index*2+1]<<4)); + write_nic_byte(dev, AGGLEN_LMT_L+index, RegToSet); + } + RegToSet = ((FactorLevel[16]) | (FactorLevel[17]<<4)); + write_nic_byte(dev, AGGLEN_LMT_H, RegToSet); + + RT_TRACE(COMP_MLME, "Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet); + } + } + break; + case HW_VAR_BASIC_RATE: + { + u16 BrateCfg = 0; + u8 RateIndex = 0; + + + rtl8192_config_rate(dev, &BrateCfg); + + if (priv->card_8192_version == VERSION_8192S_ACUT) + priv->basic_rate = BrateCfg = BrateCfg & 0x150; + else if (priv->card_8192_version == VERSION_8192S_BCUT) + priv->basic_rate = BrateCfg = BrateCfg & 0x15f; + + if(priv->rtllib->pHTInfo->IOTPeer == HT_IOT_PEER_CISCO && ((BrateCfg &0x150)==0)) + { + BrateCfg |=0x010; + } + if(priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) + { + BrateCfg &= 0x1f0; + printk("HW_VAR_BASIC_RATE, HT_IOT_ACT_WA_IOT_Broadcom, BrateCfg = 0x%x\n", BrateCfg); + } + write_nic_byte(dev, RRSR, BrateCfg&0xff); + write_nic_byte(dev, RRSR+1, (BrateCfg>>8)&0xff); + + while(BrateCfg > 0x1) + { + BrateCfg = (BrateCfg >> 1); + RateIndex++; + } + write_nic_byte(dev, INIRTSMCS_SEL, RateIndex); + } + break; + case HW_VAR_RETRY_LIMIT: + { + u8 RetryLimit = ((u8*)(val))[0]; + + priv->ShortRetryLimit = RetryLimit; + priv->LongRetryLimit = RetryLimit; + + write_nic_word(dev, RETRY_LIMIT, + RetryLimit << RETRY_LIMIT_SHORT_SHIFT | \ + RetryLimit << RETRY_LIMIT_LONG_SHIFT); + } + break; + case HW_VAR_BEACON_INTERVAL: + { + write_nic_word(dev, BCN_INTERVAL, *((u16*)val)); + PHY_SetBeaconHwReg(dev, *((u16*)val)); + } + break; + + case HW_VAR_BSSID: + write_nic_dword(dev, BSSIDR, ((u32*)(val))[0]); + write_nic_word(dev, BSSIDR+4, ((u16*)(val+4))[0]); + break; + + case HW_VAR_MEDIA_STATUS: + { + RT_OP_MODE OpMode = *((RT_OP_MODE *)(val)); + LED_CTL_MODE LedAction = LED_CTL_NO_LINK; + u8 btMsr = read_nic_byte(dev, MSR); + + btMsr &= 0xfc; + switch(OpMode) + { + case RT_OP_MODE_INFRASTRUCTURE: + btMsr |= MSR_INFRA; + LedAction = LED_CTL_LINK; + break; + + case RT_OP_MODE_IBSS: + btMsr |= MSR_ADHOC; + break; + + case RT_OP_MODE_AP: + btMsr |= MSR_AP; + LedAction = LED_CTL_LINK; + break; + + default: + btMsr |= MSR_NOLINK; + break; + } + + write_nic_byte(dev, MSR, btMsr); + + { + u32 temp = read_nic_dword(dev, TCR); + write_nic_dword(dev, TCR, temp&(~BIT8)); + write_nic_dword(dev, TCR, temp|BIT8); + } + priv->rtllib->LedControlHandler(dev, LedAction); + } + break; + + case HW_VAR_RCR: + { + write_nic_dword(dev, RCR,((u32*)(val))[0]); + priv->ReceiveConfig = ((u32*)(val))[0]; + } + break; + + case HW_VAR_CECHK_BSSID: + { + u32 RegRCR, Type; + + Type = ((u8*)(val))[0]; + priv->rtllib->GetHwRegHandler(dev, HW_VAR_RCR, (u8*)(&RegRCR)); + +#if (RTL92SE_FPGA_VERIFY == 1) + RegRCR &= (~RCR_CBSSID); +#else +#if 1 + if (Type == true) + RegRCR |= (RCR_CBSSID); + else if (Type == false) + RegRCR &= (~RCR_CBSSID); +#endif + priv->rtllib->SetHwRegHandler( dev, HW_VAR_RCR, (u8*)(&RegRCR) ); +#endif + } + break; + + case HW_VAR_SLOT_TIME: + { + + priv->slot_time = val[0]; + write_nic_byte(dev, SLOT_TIME, val[0]); + +#ifdef MERGE_TO_DO + if(priv->rtllib->current_network.qos_data.supported !=0) + { + for(eACI = 0; eACI < AC_MAX; eACI++) + { + priv->rtllib->SetHwRegHandler(dev, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, eACI) ); + } + } + else + { + u8 u1bAIFS = aSifsTime + (2 * priv->slot_time); + + write_nic_byte(dev, REG_EDCA_VO_PARAM, u1bAIFS); + write_nic_byte(dev, REG_EDCA_VI_PARAM, u1bAIFS); + write_nic_byte(dev, REG_EDCA_BE_PARAM, u1bAIFS); + write_nic_byte(dev, REG_EDCA_BK_PARAM, u1bAIFS); + } +#endif + } + break; + + case HW_VAR_ACK_PREAMBLE: + { + u8 regTmp; + priv->short_preamble = (bool)(*(u8*)val ); + regTmp = (priv->nCur40MhzPrimeSC)<<5; + if(priv->short_preamble) + regTmp |= 0x80; + + write_nic_byte(dev, RRSR+2, regTmp); + } + break; + + default: + break; + } +} + +void SetBeaconRelatedRegisters8192SE(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + struct rtllib_network *net = &priv->rtllib->current_network; + u16 BcnTimeCfg = 0; + u16 BcnCW = 6, BcnIFS = 0xf; + u16 AtimWindow = 2; + int OpMode = priv->rtllib->iw_mode; + u16 BcnInterval = net->beacon_interval; + write_nic_word(dev, ATIMWND, AtimWindow); + + write_nic_word(dev, BCN_INTERVAL, BcnInterval); + PHY_SetBeaconHwReg( dev, BcnInterval); + + write_nic_word(dev, BCN_DRV_EARLY_INT, 10<<4); + + write_nic_word(dev, BCN_DMATIME, 256); + + write_nic_byte(dev, BCN_ERR_THRESH, 100); + + + switch(OpMode) + { + case IW_MODE_ADHOC: + BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT); + break; + default: + printk("Invalid Operation Mode!!\n"); + break; + } + + BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; + + + { + u8 u1Temp = (u8)(BcnInterval); + write_nic_dword(dev, WFM5, 0xF1000000 |((u16)( u1Temp) << 8)); + ChkFwCmdIoDone(dev); + } +} + +void UpdateHalRATRTableIndex(struct net_device *dev) +{ + struct r8192_priv* priv = rtllib_priv(dev); + struct rtllib_device* ieee = priv->rtllib; + u8 bitmap = 0; + int i; + + for (i = 0; i < PEER_MAX_ASSOC; i++) { + if (NULL != ieee->peer_assoc_list[i]) { + bitmap |= BIT0 << ieee->peer_assoc_list[i]->ratr_index; + } + } + + priv->RATRTableBitmap = bitmap; + return; +} + +bool rtl8192se_check_ht_cap(struct net_device* dev, struct sta_info *sta, + struct rtllib_network* net) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + PHT_CAPABILITY_ELE pHTCapIE = NULL; + PHT_INFORMATION_ELE pPeerHTInfo = NULL; + u8 ExtChlOffset=0; + u8 *pMcsFilter = NULL; + u16 nMaxAMSDUSize = 0; + static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; + static u8 EWC11NHTInfo[] = {0x00, 0x90, 0x4c, 0x34}; + + if ((ieee->mode != WIRELESS_MODE_N_24G) && + (ieee->mode != WIRELESS_MODE_N_5G)) { + printk("%s():i am G mode ,do not need to check Cap IE\n", + __FUNCTION__); + if (net->mode == IEEE_N_5G) + sta->wireless_mode = IEEE_A; + else if (net->mode == IEEE_N_24G) { + if (net->rates_ex_len > 0) + sta->wireless_mode = IEEE_G; + else + sta->wireless_mode = IEEE_B; + } else + sta->wireless_mode = net->mode; + return false; + } + if ((ieee->mode ==WIRELESS_MODE_N_24G) + && ieee->pHTInfo->bRegSuppCCK== false) { + if(net->mode == IEEE_B){ + sta->wireless_mode = net->mode; + printk("%s(): peer is B MODE return\n", __FUNCTION__); + return false; + } + } + if(net->bssht.bdHTCapLen != 0) + { + sta->htinfo.bEnableHT = true; + sta->htinfo.bCurRxReorderEnable = ieee->pHTInfo->bRegRxReorderEnable; + if(net->mode == IEEE_A) + sta->wireless_mode = IEEE_N_5G; + else + sta->wireless_mode = IEEE_N_24G; + } else { + printk("%s(): have no HTCap IE, mode is %d\n",__FUNCTION__,net->mode); + sta->wireless_mode = net->mode; + sta->htinfo.bEnableHT = false; + return true; + } + + if (!memcmp(net->bssht.bdHTCapBuf ,EWC11NHTCap, sizeof(EWC11NHTCap))) + pHTCapIE = (PHT_CAPABILITY_ELE)(&(net->bssht.bdHTCapBuf[4])); + else + pHTCapIE = (PHT_CAPABILITY_ELE)(net->bssht.bdHTCapBuf); + + if (!memcmp(net->bssht.bdHTInfoBuf, EWC11NHTInfo, sizeof(EWC11NHTInfo))) + pPeerHTInfo = (PHT_INFORMATION_ELE)(&net->bssht.bdHTInfoBuf[4]); + else + pPeerHTInfo = (PHT_INFORMATION_ELE)(net->bssht.bdHTInfoBuf); + + ExtChlOffset=((ieee->pHTInfo->bRegBW40MHz == false)?HT_EXTCHNL_OFFSET_NO_EXT: + (ieee->current_network.channel<=6)? + HT_EXTCHNL_OFFSET_UPPER:HT_EXTCHNL_OFFSET_LOWER); + printk("******** STA wireless mode %d\n", sta->wireless_mode); + + if (ieee->pHTInfo->bRegSuppCCK) + sta->htinfo.bSupportCck = (pHTCapIE->DssCCk==1)?true:false; + else { + if(pHTCapIE->DssCCk==1) + return false; + } + + sta->htinfo.MimoPs= pHTCapIE->MimoPwrSave; + + printk("******** PEER MP MimoPs %d\n", sta->htinfo.MimoPs); + if(ieee->pHTInfo->bRegBW40MHz) + sta->htinfo.bBw40MHz= (pHTCapIE->ChlWidth==1)?true:false; + else + sta->htinfo.bBw40MHz = false; + + if((pPeerHTInfo->ExtChlOffset) != ExtChlOffset) + sta->htinfo.bBw40MHz = false; + + ieee->Peer_bCurBW40M = sta->htinfo.bBw40MHz; + printk("******** PEER MP bCurBW40M %d\n", sta->htinfo.bBw40MHz); + if(ieee->pHTInfo->bRegBW40MHz == true) + sta->htinfo.bCurTxBW40MHz = sta->htinfo.bBw40MHz; + + printk("******** PEER MP bCurTxBW40MHz %d\n", sta->htinfo.bCurTxBW40MHz); + sta->htinfo.bCurShortGI20MHz= + ((ieee->pHTInfo->bRegShortGI20MHz)?((pHTCapIE->ShortGI20Mhz==1)?true:false):false); + sta->htinfo.bCurShortGI40MHz= + ((ieee->pHTInfo->bRegShortGI40MHz)?((pHTCapIE->ShortGI40Mhz==1)?true:false):false); + + printk("******** PEER MP bCurShortGI20MHz %d, bCurShortGI40MHz %d\n",sta->htinfo.bCurShortGI20MHz,sta->htinfo.bCurShortGI40MHz); + nMaxAMSDUSize = (pHTCapIE->MaxAMSDUSize==0)?3839:7935; + if(ieee->pHTInfo->nAMSDU_MaxSize >= nMaxAMSDUSize) + sta->htinfo.AMSDU_MaxSize = nMaxAMSDUSize; + else + sta->htinfo.AMSDU_MaxSize = ieee->pHTInfo->nAMSDU_MaxSize; + + printk("****************AMSDU_MaxSize=%d\n",sta->htinfo.AMSDU_MaxSize); + + if(ieee->pHTInfo->AMPDU_Factor >= pHTCapIE->MaxRxAMPDUFactor) + sta->htinfo.AMPDU_Factor = pHTCapIE->MaxRxAMPDUFactor; + else + sta->htinfo.AMPDU_Factor = ieee->pHTInfo->AMPDU_Factor; + + if(ieee->pHTInfo->MPDU_Density >= pHTCapIE->MPDUDensity) + sta->htinfo.MPDU_Density = pHTCapIE->MPDUDensity; + else + sta->htinfo.MPDU_Density = ieee->pHTInfo->MPDU_Density; + + HTFilterMCSRate(ieee, pHTCapIE->MCS, sta->htinfo.McsRateSet); + if(sta->htinfo.MimoPs == 0) + pMcsFilter = MCS_FILTER_1SS; + else + pMcsFilter = MCS_FILTER_ALL; + + sta->htinfo.HTHighestOperaRate = HTGetHighestMCSRate(ieee, sta->htinfo.McsRateSet, pMcsFilter); + printk("******** PEER MP HTHighestOperaRate %x\n",sta->htinfo.HTHighestOperaRate); + + return true; + +} + +#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20) +void rtl8192se_check_tsf_wq(struct work_struct * work) +{ + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct rtllib_device *ieee = container_of(dwork, struct rtllib_device, check_tsf_wq); + struct net_device *dev = ieee->dev; +#else +void rtl8192se_check_tsf_wq(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; +#endif + u32 CurrTsfHigh,CurrTsfLow; + u32 TargetTsfHigh,TargetTsfLow; + + CurrTsfHigh = read_nic_dword(dev, TSFR+4); + CurrTsfLow = (u32)(ieee->CurrTsf & 0xffff); + TargetTsfHigh = (u32)(ieee->TargetTsf >> 32); + TargetTsfLow = (u32)(ieee->TargetTsf & 0xffff); + + printk("Current TSF Low = %x, Hight = %x\n",CurrTsfLow,CurrTsfHigh); + printk("Target TSF Low = %x, Hight = %x\n",TargetTsfLow,TargetTsfHigh); + + ieee->CurrTsf |= (u64)CurrTsfHigh << 32; + + if(ieee->CurrTsf < ieee->TargetTsf) + { + down(&ieee->wx_sem); + + rtllib_stop_protocol(ieee,true); + + ieee->ssid_set = 1; + + rtllib_start_protocol(ieee); + + up(&ieee->wx_sem); + } +} + +#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20) +void rtl8192se_update_peer_ratr_table_wq(struct work_struct * work) +{ + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct rtllib_device *ieee = container_of(dwork, struct rtllib_device, update_assoc_sta_info_wq); + struct net_device *dev = ieee->dev; + struct r8192_priv *priv = rtllib_priv(dev); +#else +void rtl8192se_update_peer_ratr_table_wq(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; +#endif + int idx = 0; + for(idx=0; idx<PEER_MAX_ASSOC; idx++) + { + if(NULL != priv->rtllib->peer_assoc_list[idx]) + { + u8 * addr = priv->rtllib->peer_assoc_list[idx]->macaddr; + printk("%s: STA:%x:%x:%x:%x:%x:%x\n",__FUNCTION__,addr[0],addr[1],addr[2],addr[3],addr[4],addr[5]); + rtl8192se_update_ratr_table(dev,priv->rtllib->peer_assoc_list[idx]->htinfo.McsRateSet,priv->rtllib->peer_assoc_list[idx]); + } + } + UpdateHalRATRTableIndex(dev); + + if(ieee->Peer_bCurBW40M) + HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20_40, (ieee->current_network.channel<=6)?HT_EXTCHNL_OFFSET_UPPER:HT_EXTCHNL_OFFSET_LOWER); + else + HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, (ieee->current_network.channel<=6)?HT_EXTCHNL_OFFSET_UPPER:HT_EXTCHNL_OFFSET_LOWER); +} + +bool +rtl8192se_RxCommandPacketHandle( + struct net_device *dev, + struct sk_buff* skb, + rx_desc *pdesc) +{ + u8* pRxCmdHeader; + u8* pCmdContent; + u16 total_length, offset; + u16 RxCmdLen; + u8 RxCmdElementID, RxCmdSeq; + bool RxCmdContinue; + +#if 0 + if ((pRfd->queue_id != CMPK_RX_QUEUE_ID) || (pRfd == NULL)) + { + return 0; + } +#endif + + +#if 0 + if(pdesc->MACID == 0x1e) + { + return 0; + } +#endif + + total_length = pdesc->Length; + pRxCmdHeader = skb->data; + offset = 0; + + do + { + RxCmdLen = (u16)GET_C2H_CMD_CMD_LEN(pRxCmdHeader + offset); + RxCmdElementID = (u8)GET_C2H_CMD_ELEMENT_ID(pRxCmdHeader + offset); + RxCmdSeq = (u8)GET_C2H_CMD_CMD_SEQ(pRxCmdHeader + offset); + RxCmdContinue = (bool)GET_C2H_CMD_CONTINUE(pRxCmdHeader + offset); + pCmdContent = (u8*)GET_C2H_CMD_CONTENT(pRxCmdHeader + offset); + + if((offset + C2H_RX_CMD_HDR_LEN + RxCmdLen) > total_length) + { + printk("Wrong C2H Cmd length!\n"); + break; + } + + RT_TRACE(COMP_CMD, "RxCmdLen = 0x%x, RxCmdElementID = 0x%x, RxCmdSeq = 0x%x, RxCmdContinue = 0x%x\n", + RxCmdLen, RxCmdElementID, RxCmdSeq, RxCmdContinue); + RT_TRACE(COMP_CMD, "Rx CMD Packet Hex Data :%x\n", total_length); + RT_TRACE(COMP_CMD, "Rx CMD Content Hex Data :%x:%x\n", *pCmdContent, RxCmdLen); + + switch(RxCmdElementID) + { + case HAL_FW_C2H_CMD_C2HFEEDBACK: + { + switch(GET_C2H_CMD_FEEDBACK_ELEMENT_ID(pCmdContent)) + { + case HAL_FW_C2H_CMD_C2HFEEDBACK_CCX_PER_PKT_RPT: + { + RT_TRACE(COMP_CMD, "HAL_FW_C2H_CMD_C2HFEEDBACK_CCX_PER_PKT_RPT FW_DBG CMD Hex:%x\n", total_length); + } + break; + + case HAL_FW_C2H_CMD_C2HFEEDBACK_DTM_TX_STATISTICS_RPT: + break; + + default: + break; + } + } + break; + + case HAL_FW_C2H_CMD_C2HDBG: + RT_TRACE(COMP_CMD, "rtl8192se_RxCommandPacketHandle(): %x:%x<*** FW_DBG CMD String ***>\n", *pCmdContent, RxCmdLen); + break; + + case HAL_FW_C2H_CMD_BT_State: + { + } + break; + case HAL_FW_C2H_CMD_BT_Service: + { + } + break; + case HAL_FW_C2H_CMD_SurveyDone: + { + rtl8192se_rx_surveydone_cmd(dev); + } + break; + default: + RT_TRACE(COMP_CMD, "rtl8192se_RxCommandPacketHandle(): Receive unhandled C2H CMD (%d)\n", RxCmdElementID); + break; + } + + offset += (C2H_RX_CMD_HDR_LEN + N_BYTE_ALIGMENT(RxCmdLen, 8)); + + if(!RxCmdContinue || ((offset + C2H_RX_CMD_HDR_LEN) > total_length)) + { + break; + } + }while(true); + RT_TRACE(COMP_RECV, "RxCommandPacketHandle8190Pci(): It is a command packet\n"); + + return 1; +} + +void +rtl8192se_InitializeVariables(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + if (priv->rf_type == RF_1T1R) + strcpy(priv->nick, "rtl8191SEVA1"); + else if (priv->rf_type == RF_1T2R) + strcpy(priv->nick, "rtl8191SEVA2"); + else + strcpy(priv->nick, "rtl8192SE"); + + priv->rtllib->tx_headroom = 0; + + priv->ShortRetryLimit = 0x30; + priv->LongRetryLimit = 0x30; + + priv->EarlyRxThreshold = 7; + priv->pwrGroupCnt = 0; + + priv->bIgnoreSilentReset = false; + priv->enable_gpio0 = 0; + + priv->TransmitConfig = 0; + + priv->ReceiveConfig = + RCR_APPFCS | RCR_APWRMGT | /*RCR_ADD3 |*/ + RCR_AMF | RCR_ADF | RCR_APP_MIC | RCR_APP_ICV | + RCR_AICV | RCR_ACRC32 | + RCR_AB | RCR_AM | + RCR_APM | + /*RCR_AAP |*/ + RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | + (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) ; + +#if 0 + priv->irq_mask[0] = + (IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK | \ + IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | \ + IMR_BDOK | IMR_RXCMDOK | /*IMR_TIMEOUT0 |*/ IMR_RDU | IMR_RXFOVW/* | \ + IMR_BcnInt| IMR_TXFOVW | IMR_TBDOK | IMR_TBDER*/); +#else + priv->irq_mask[0] = + (IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK | \ + IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | \ + IMR_BDOK | IMR_RXCMDOK | /*IMR_TIMEOUT0 |*/ IMR_RDU | IMR_RXFOVW | \ + IMR_BcnInt/*| IMR_TXFOVW*/ /*| IMR_TBDOK | IMR_TBDER*/); +#endif + priv->irq_mask[1] = 0;/* IMR_TBDOK | IMR_TBDER*/ + + + priv->MidHighPwrTHR_L1 = 0x3B; + priv->MidHighPwrTHR_L2 = 0x40; + priv->PwrDomainProtect = false; + + if (!(priv->rtllib->softmac_features & IEEE_SOFTMAC_SCAN)){ + if (!priv->scan_cmd) { + priv->scan_cmd = kmalloc(sizeof(H2C_SITESURVEY_PARA) + + RTL_MAX_SCAN_SIZE, GFP_KERNEL); + } + } +} + +void rtl8192se_EnableInterrupt(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + priv->irq_enabled = 1; + +#ifdef RTL8192CE + write_nic_dword(dev, REG_HIMR, priv->irq_mask[0]&0xFFFFFFFF); +#else + write_nic_dword(dev,INTA_MASK, priv->irq_mask[0]); +#endif + +#ifdef RTL8192SE + write_nic_dword(dev,INTA_MASK+4, priv->irq_mask[1]&0x3F); +#endif + +} + +void rtl8192se_DisableInterrupt(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + +#ifdef RTL8192CE + write_nic_dword(dev, REG_HIMR, IMR8190_DISABLED); +#else + write_nic_dword(dev,INTA_MASK,0); +#endif + +#ifdef RTL8192SE + write_nic_dword(dev,INTA_MASK + 4,0); +#endif + priv->irq_enabled = 0; +} + +void rtl8192se_ClearInterrupt(struct net_device *dev) +{ + u32 tmp = 0; +#ifdef RTL8192CE + tmp = read_nic_dword(dev, REG_HISR); + write_nic_dword(dev, REG_HISR, tmp); +#else + tmp = read_nic_dword(dev, ISR); + write_nic_dword(dev, ISR, tmp); +#endif + +#ifdef RTL8192SE + tmp = read_nic_dword(dev, ISR+4); + write_nic_dword(dev, ISR+4, tmp); +#endif +} + +void rtl8192se_enable_rx(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + write_nic_dword(dev, RDQDA,priv->rx_ring_dma[RX_MPDU_QUEUE]); +#ifdef CONFIG_RX_CMD + write_nic_dword(dev, RCDA, priv->rx_ring_dma[RX_CMD_QUEUE]); +#endif +} + +u32 TX_DESC_BASE[] = {TBKDA, TBEDA, TVIDA, TVODA, TBDA, TCDA, TMDA, THPDA, HDA}; +void rtl8192se_enable_tx(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u32 i; + + for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) + write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma); +} + + +void rtl8192se_beacon_disable(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u32 reg; + +#ifdef RTL8192CE + reg = read_nic_dword(priv->rtllib->dev,REG_HIMR); + + reg &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); + write_nic_dword(priv->rtllib->dev, REG_HIMR, reg); +#else + reg = read_nic_dword(priv->rtllib->dev,INTA_MASK); + + reg &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); + write_nic_dword(priv->rtllib->dev, INTA_MASK, reg); +#endif +} + +void rtl8192se_interrupt_recognized(struct net_device *dev, u32 *p_inta, u32 *p_intb) +{ +#ifdef RTL8192SE + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + *p_inta = read_nic_dword(dev, ISR) & priv->irq_mask[0]; +#else + *p_inta = read_nic_dword(dev, ISR) ; +#endif + write_nic_dword(dev,ISR,*p_inta); +#ifdef RTL8192SE + *p_intb = read_nic_dword(dev, ISR+4); + write_nic_dword(dev, ISR+4, *p_intb); +#endif +} + +bool rtl8192se_HalRxCheckStuck(struct net_device *dev) +{ + + struct r8192_priv *priv = rtllib_priv(dev); + u16 RegRxCounter = (u16)(priv->InterruptLog.nIMR_ROK&0xffff); + bool bStuck = false; + u32 SlotIndex = 0, TotalRxStuckCount = 0; + u8 i; + u8 SilentResetRxSoltNum = 4; + + + SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum; + + if(priv->RxCounter==RegRxCounter) + { + priv->SilentResetRxStuckEvent[SlotIndex] = 1; + + for( i = 0; i < SilentResetRxSoltNum ; i++ ) + TotalRxStuckCount += priv->SilentResetRxStuckEvent[i]; + + if(TotalRxStuckCount == SilentResetRxSoltNum) + { + bStuck = true; + for( i = 0; i < SilentResetRxSoltNum ; i++ ) + TotalRxStuckCount += priv->SilentResetRxStuckEvent[i]; + } + + + } else { + priv->SilentResetRxStuckEvent[SlotIndex] = 0; + } + + priv->RxCounter = RegRxCounter; + + return bStuck; +} + +bool rtl8192se_HalTxCheckStuck(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool bStuck = false; +#if defined(RTL8192E) || defined(RTL8190P) + u16 RegTxCounter = read_nic_word(dev, 0x128); +#elif defined (RTL8192SE) || defined (RTL8192CE) + u16 RegTxCounter = read_nic_word(dev, 0x366); +#else + u16 RegTxCounter = priv->TxCounter + 1; + WARN_ON(1); +#endif + + RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n", + __FUNCTION__,RegTxCounter,priv->TxCounter); + + if(priv->TxCounter == RegTxCounter) + bStuck = true; + + priv->TxCounter = RegTxCounter; + + return bStuck; +} diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_dev.h b/ubuntu/rtl8192se/rtl8192s/r8192S_dev.h new file mode 100644 index 000000000000..c0aec6853545 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_dev.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef _RTL8192SE_H +#define _RTL8192SE_H + +#include "r8192S_def.h" + +bool rtl8192se_HalTxCheckStuck(struct net_device *dev); +bool rtl8192se_HalRxCheckStuck(struct net_device *dev); +void rtl8192se_interrupt_recognized(struct net_device *dev, u32 *p_inta, u32 *p_intb); +void rtl8192se_enable_rx(struct net_device *dev); +void rtl8192se_enable_tx(struct net_device *dev); +void rtl8192se_EnableInterrupt(struct net_device *dev); +void rtl8192se_DisableInterrupt(struct net_device *dev); +void rtl8192se_ClearInterrupt(struct net_device *dev); +void rtl8192se_InitializeVariables(struct net_device *dev); +void rtl8192se_start_beacon(struct net_device *dev); +u8 MRateToHwRate8192SE(struct net_device*dev, u8 rate); +void rtl8192se_get_eeprom_size(struct net_device* dev); +bool rtl8192se_adapter_start(struct net_device* dev); +void rtl8192se_link_change(struct net_device *dev); +void rtl8192se_tx_fill_desc(struct net_device *dev, tx_desc *pDesc, cb_desc *cb_desc, struct sk_buff *skb); +void rtl8192se_tx_fill_cmd_desc(struct net_device *dev, tx_desc_cmd *entry, cb_desc *cb_desc, + struct sk_buff *skb); +bool rtl8192se_rx_query_status_desc(struct net_device* dev, struct rtllib_rx_stats* stats, + rx_desc *pdesc, struct sk_buff* skb); +void rtl8192se_halt_adapter(struct net_device *dev, bool bReset); +void rtl8192se_update_ratr_table(struct net_device* dev,u8* pMcsRate,struct sta_info* pEntry); +int r8192se_resume_firm(struct net_device *dev); +void PHY_SetRtl8192seRfHalt(struct net_device* dev); +#ifndef _RTL8192_EXT_PATCH_ +void UpdateHalRAMask8192SE(struct net_device* dev,bool bMulticast, u8 macId, u8* MacAddr, u8* pEntry, u8 rssi_level); +#else +void UpdateHalRAMask8192SE(struct net_device* dev, bool bMulticast, u8 macId, u8* MacAddr, u8 wirelessMode, u8 rssi_level); +#endif +u8 HalSetSysClk8192SE(struct net_device *dev, u8 Data); +bool rtl8192se_RxCommandPacketHandle(struct net_device *dev, struct sk_buff* skb,rx_desc *pdesc); +bool rtl8192se_check_ht_cap(struct net_device* dev, struct sta_info *sta, + struct rtllib_network* net); +u8 rtl8192se_MapHwQueueToFirmwareQueue(u8 QueueID, u8 priority); +#endif + diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_firmware.c b/ubuntu/rtl8192se/rtl8192s/r8192S_firmware.c new file mode 100644 index 000000000000..78877d8b8f08 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_firmware.c @@ -0,0 +1,856 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#if defined(RTL8192SE)
+#include "../rtl_core.h"
+#include "../rtl_endianfree.h"
+#include "r8192S_hwimg.h"
+#include "r8192S_dev.h"
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) && defined(USE_FW_SOURCE_IMG_FILE)
+#include <linux/firmware.h>
+#endif
+#define byte(x,n) ( (x >> (8 * n)) & 0xff )
+
+static void fw_SetRQPN(struct net_device *dev)
+{
+
+ write_nic_dword(dev, RQPN, 0xffffffff);
+ write_nic_dword(dev, RQPN+4, 0xffffffff);
+ write_nic_byte(dev, RQPN+8, 0xff);
+ write_nic_byte(dev, RQPN+0xB, 0x80);
+
+
+} /* fw_SetRQPN */
+
+bool FirmwareDownloadCode(struct net_device *dev, u8 * code_virtual_address,u32 buffer_len)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool rt_status = true;
+ u16 frag_threshold = MAX_FIRMWARE_CODE_SIZE; + u16 frag_length, frag_offset = 0;
+ struct sk_buff *skb;
+ unsigned char *seg_ptr;
+ cb_desc *tcb_desc;
+ u8 bLastIniPkt = 0;
+ u16 ExtraDescOffset = 0;
+
+#ifdef RTL8192SE
+ fw_SetRQPN(dev); +#endif
+
+ RT_TRACE(COMP_FIRMWARE, "--->FirmwareDownloadCode()\n" );
+
+ if(buffer_len >= MAX_FIRMWARE_CODE_SIZE)
+ {
+ RT_TRACE(COMP_ERR, "Size over FIRMWARE_CODE_SIZE! \n");
+ goto cmdsend_downloadcode_fail;
+ }
+
+ ExtraDescOffset = 0;
+
+ do {
+ if((buffer_len-frag_offset) > frag_threshold)
+ {
+ frag_length = frag_threshold + ExtraDescOffset;
+ }
+ else
+ {
+ frag_length = (u16)(buffer_len - frag_offset + ExtraDescOffset);
+ bLastIniPkt = 1;
+ }
+
+ skb = dev_alloc_skb(frag_length);
+ memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
+
+ tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
+ tcb_desc->queue_index = TXCMD_QUEUE;
+ tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT;
+ tcb_desc->bLastIniPkt = bLastIniPkt;
+
+ skb_reserve(skb, ExtraDescOffset);
+ seg_ptr = (u8 *)skb_put(skb, (u32)(frag_length-ExtraDescOffset));
+ memcpy(seg_ptr, code_virtual_address+frag_offset, (u32)(frag_length-ExtraDescOffset));
+
+ tcb_desc->txbuf_size= frag_length;
+
+ if(!priv->rtllib->check_nic_enough_desc(dev,tcb_desc->queue_index)||
+ (!skb_queue_empty(&priv->rtllib->skb_waitQ[tcb_desc->queue_index]))||\
+ (priv->rtllib->queue_stop) )
+ {
+ RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n");
+ skb_queue_tail(&priv->rtllib->skb_waitQ[tcb_desc->queue_index], skb);
+ }
+ else
+ {
+ priv->rtllib->softmac_hard_start_xmit(skb,dev);
+ }
+
+ frag_offset += (frag_length - ExtraDescOffset);
+
+ }while(frag_offset < buffer_len);
+ write_nic_byte(dev, TPPoll, TPPoll_CQ);
+ return rt_status ;
+
+
+cmdsend_downloadcode_fail:
+ rt_status = false;
+ RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n");
+ return rt_status;
+
+}
+
+
+
+bool
+FirmwareEnableCPU(struct net_device *dev)
+{
+
+ bool rtStatus = true;
+ u8 tmpU1b, CPUStatus = 0;
+ u16 tmpU2b;
+ u32 iCheckTime = 200;
+
+ RT_TRACE(COMP_FIRMWARE, "-->FirmwareEnableCPU()\n" );
+
+ fw_SetRQPN(dev); +
+ tmpU1b = read_nic_byte(dev, SYS_CLKR);
+ write_nic_byte(dev, SYS_CLKR, (tmpU1b|SYS_CPU_CLKSEL)); +
+ tmpU2b = read_nic_word(dev, SYS_FUNC_EN);
+ write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|FEN_CPUEN));
+
+ do
+ {
+ CPUStatus = read_nic_byte(dev, TCR);
+ if(CPUStatus& IMEM_RDY)
+ {
+ RT_TRACE(COMP_FIRMWARE, "IMEM Ready after CPU has refilled.\n");
+ break;
+ }
+
+ udelay(100);
+ }while(iCheckTime--);
+
+ if(!(CPUStatus & IMEM_RDY))
+ return false;
+
+ RT_TRACE(COMP_FIRMWARE, "<--FirmwareEnableCPU(): rtStatus(%#x)\n", rtStatus);
+ return rtStatus;
+}
+
+FIRMWARE_8192S_STATUS
+FirmwareGetNextStatus(FIRMWARE_8192S_STATUS FWCurrentStatus)
+{
+ FIRMWARE_8192S_STATUS NextFWStatus = 0;
+
+ switch(FWCurrentStatus)
+ {
+ case FW_STATUS_INIT:
+ NextFWStatus = FW_STATUS_LOAD_IMEM;
+ break;
+
+ case FW_STATUS_LOAD_IMEM:
+ NextFWStatus = FW_STATUS_LOAD_EMEM;
+ break;
+
+ case FW_STATUS_LOAD_EMEM:
+ NextFWStatus = FW_STATUS_LOAD_DMEM;
+ break;
+
+ case FW_STATUS_LOAD_DMEM:
+ NextFWStatus = FW_STATUS_READY;
+ break;
+
+ default:
+ RT_TRACE(COMP_ERR,"Invalid FW Status(%#x)!!\n", FWCurrentStatus);
+ break;
+ }
+ return NextFWStatus;
+}
+
+bool FirmwareCheckReady(struct net_device *dev, u8 LoadFWStatus)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool rtStatus = true;
+ rt_firmware *pFirmware = priv->pFirmware;
+ short PollingCnt = 1000;
+ u8 CPUStatus = 0;
+ u32 tmpU4b;
+
+ RT_TRACE(COMP_FIRMWARE, "--->%s(): LoadStaus(%d),", __FUNCTION__, LoadFWStatus);
+
+ pFirmware->FWStatus = (FIRMWARE_8192S_STATUS)LoadFWStatus;
+
+ switch (LoadFWStatus) {
+ case FW_STATUS_LOAD_IMEM:
+ do { + CPUStatus = read_nic_byte(dev, TCR);
+ if(CPUStatus& IMEM_CODE_DONE)
+ break;
+ udelay(5);
+ } while (PollingCnt--);
+ if (!(CPUStatus & IMEM_CHK_RPT) || (PollingCnt <= 0)) {
+ RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_IMEM FAIL CPU, Status=%x\r\n", CPUStatus);
+ goto status_check_fail;
+ }
+ break;
+
+ case FW_STATUS_LOAD_EMEM:
+ do { + CPUStatus = read_nic_byte(dev, TCR);
+ if(CPUStatus& EMEM_CODE_DONE)
+ break;
+ udelay(5);
+ } while(PollingCnt--);
+ if (!(CPUStatus & EMEM_CHK_RPT) || (PollingCnt <= 0)) {
+ RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_EMEM FAIL CPU, Status=%x\r\n", CPUStatus);
+ goto status_check_fail;
+ }
+
+ rtStatus = FirmwareEnableCPU(dev);
+ if (rtStatus != true) {
+ RT_TRACE(COMP_ERR, "Enable CPU fail ! \n" );
+ goto status_check_fail;
+ }
+ break;
+
+ case FW_STATUS_LOAD_DMEM:
+ do { + CPUStatus = read_nic_byte(dev, TCR);
+ if (CPUStatus& DMEM_CODE_DONE)
+ break;
+ udelay(5);
+ } while(PollingCnt--);
+
+ if (!(CPUStatus & DMEM_CODE_DONE) || (PollingCnt <= 0)) {
+ RT_TRACE(COMP_ERR, "Polling DMEM code done fail ! CPUStatus(%#x)\n", CPUStatus);
+ goto status_check_fail;
+ }
+
+ RT_TRACE(COMP_FIRMWARE, "DMEM code download success, CPUStatus(%#x)\n", CPUStatus);
+ PollingCnt = 2000; + do { + CPUStatus = read_nic_byte(dev, TCR);
+ if(CPUStatus & FWRDY)
+ break;
+ udelay(40);
+ } while(PollingCnt--);
+
+ RT_TRACE(COMP_FIRMWARE, "Polling Load Firmware ready, CPUStatus(%x)\n", CPUStatus);
+ if (((CPUStatus & LOAD_FW_READY) != LOAD_FW_READY) || (PollingCnt <= 0)) {
+ RT_TRACE(COMP_ERR, "Polling Load Firmware ready fail ! CPUStatus(%x)\n", CPUStatus);
+ goto status_check_fail;
+ }
+
+#ifdef RTL8192SE
+#endif
+
+ tmpU4b = read_nic_dword(dev,TCR);
+ write_nic_dword(dev, TCR, (tmpU4b&(~TCR_ICV)));
+
+ tmpU4b = read_nic_dword(dev, RCR);
+ write_nic_dword(dev, RCR,
+ (tmpU4b|RCR_APPFCS|RCR_APP_ICV|RCR_APP_MIC));
+
+ RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current RCR settings(%#x)\n", tmpU4b);
+
+#if 0
+ priv->TransmitConfig = read_nic_dword_E(dev, TCR);
+ RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current TCR settings(%#x)\n", priv->TransmitConfig);
+#endif
+
+ write_nic_byte(dev, LBKMD_SEL, LBK_NORMAL);
+ break;
+ default :
+ RT_TRACE(COMP_FIRMWARE, "Unknown status check!\n");
+ rtStatus = false;
+ break;
+ }
+
+status_check_fail:
+ RT_TRACE(COMP_FIRMWARE, "<---%s: LoadFWStatus(%d), rtStatus(%x)\n", __FUNCTION__,
+ LoadFWStatus, rtStatus);
+ return rtStatus;
+}
+u8 FirmwareHeaderMapRfType(struct net_device *dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ switch(priv->rf_type)
+ {
+ case RF_1T1R: return 0x11;
+ case RF_1T2R: return 0x12;
+ case RF_2T2R: return 0x22;
+ case RF_2T2R_GREEN: return 0x92;
+ default:
+ RT_TRACE(COMP_INIT, "Unknown RF type(%x)\n",priv->rf_type);
+ break;
+ }
+ return 0x22;
+}
+
+
+void FirmwareHeaderPriveUpdate(struct net_device *dev, PRT_8192S_FIRMWARE_PRIV pFwPriv)
+{
+ pFwPriv->rf_config = FirmwareHeaderMapRfType(dev);
+}
+
+
+
+bool FirmwareDownload92S(struct net_device *dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool rtStatus = true;
+ u8 *pucMappedFile = NULL;
+ u32 ulFileLength = 0;
+ u8 FwHdrSize = RT_8192S_FIRMWARE_HDR_SIZE;
+ rt_firmware *pFirmware = priv->pFirmware;
+ u8 FwStatus = FW_STATUS_INIT;
+ PRT_8192S_FIRMWARE_HDR pFwHdr = NULL;
+ PRT_8192S_FIRMWARE_PRIV pFwPriv = NULL;
+
+ pFirmware->FWStatus = FW_STATUS_INIT;
+
+ RT_TRACE(COMP_FIRMWARE, " --->FirmwareDownload92S()\n");
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) && defined(USE_FW_SOURCE_IMG_FILE)
+ priv->firmware_source = FW_SOURCE_IMG_FILE;
+#else
+ priv->firmware_source = FW_SOURCE_HEADER_FILE;
+#endif
+
+ switch( priv->firmware_source )
+ {
+ case FW_SOURCE_IMG_FILE:
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) && defined(USE_FW_SOURCE_IMG_FILE)
+ if(pFirmware->szFwTmpBufferLen == 0)
+ {
+#ifdef _RTL8192_EXT_PATCH_
+ const char *pFwImageFileName[1] = {"RTL8191SE_MESH/rtl8192sfw.bin"};
+#else
+ const char *pFwImageFileName[1] = {"RTL8192SE/rtl8192sfw.bin"};
+#endif
+ const struct firmware *fw_entry = NULL;
+ u32 ulInitStep = 0;
+ int rc = 0;
+ u32 file_length = 0;
+ rc = request_firmware(&fw_entry, pFwImageFileName[ulInitStep],&priv->pdev->dev); + if(rc < 0 ) {
+ RT_TRACE(COMP_ERR, "request firmware fail!\n");
+ goto DownloadFirmware_Fail;
+ }
+
+ if(fw_entry->size > sizeof(pFirmware->szFwTmpBuffer)) {
+ RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n");
+ release_firmware(fw_entry);
+ goto DownloadFirmware_Fail;
+ }
+
+ memcpy(pFirmware->szFwTmpBuffer,fw_entry->data,fw_entry->size);
+ pFirmware->szFwTmpBufferLen = fw_entry->size;
+ release_firmware(fw_entry);
+
+ pucMappedFile = pFirmware->szFwTmpBuffer;
+ file_length = pFirmware->szFwTmpBufferLen;
+
+ pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
+ pFwHdr = pFirmware->pFwHeader;
+ RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \
+ pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \
+ pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE);
+ pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0);
+ if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM)))
+ {
+ RT_TRACE(COMP_ERR, "%s: memory for data image is less than IMEM required\n",\
+ __FUNCTION__);
+ goto DownloadFirmware_Fail;
+ } else {
+ pucMappedFile+=FwHdrSize;
+
+ memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
+ pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
+ }
+
+ if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM))
+ {
+ RT_TRACE(COMP_ERR, "%s: memory for data image is less than EMEM required\n",\
+ __FUNCTION__);
+ goto DownloadFirmware_Fail;
+ }
+ else
+ {
+ pucMappedFile += pFirmware->FwIMEMLen;
+
+ memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE); + pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
+ }
+ }
+#endif
+ break;
+
+ case FW_SOURCE_HEADER_FILE:
+#if 1
+#define Rtl819XFwImageArray Rtl8192SEFwImgArray
+ pucMappedFile = Rtl819XFwImageArray;
+ ulFileLength = ImgArrayLength;
+
+ RT_TRACE(COMP_INIT,"Fw download from header.\n");
+ pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
+ pFwHdr = pFirmware->pFwHeader;
+ RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \
+ pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \
+ pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE);
+ pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0);
+
+ if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM)))
+ {
+ printk("FirmwareDownload92S(): memory for data image is less than IMEM required\n");
+ goto DownloadFirmware_Fail;
+ }
+ else
+ {
+ pucMappedFile+=FwHdrSize;
+
+ memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
+ pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
+ }
+
+ if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM))
+ {
+ printk(" FirmwareDownload92S(): memory for data image is less than EMEM required\n");
+ goto DownloadFirmware_Fail;
+ } else {
+ pucMappedFile+= pFirmware->FwIMEMLen;
+
+ memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);
+ pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
+ }
+#endif
+ break;
+ default:
+ break;
+ }
+
+ FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
+ while(FwStatus!= FW_STATUS_READY)
+ {
+ switch(FwStatus)
+ {
+ case FW_STATUS_LOAD_IMEM:
+ pucMappedFile = pFirmware->FwIMEM;
+ ulFileLength = pFirmware->FwIMEMLen;
+ break;
+
+ case FW_STATUS_LOAD_EMEM:
+ pucMappedFile = pFirmware->FwEMEM;
+ ulFileLength = pFirmware->FwEMEMLen;
+ break;
+
+ case FW_STATUS_LOAD_DMEM:
+ pFwHdr = pFirmware->pFwHeader;
+ pFwPriv = (PRT_8192S_FIRMWARE_PRIV)&pFwHdr->FWPriv;
+ FirmwareHeaderPriveUpdate(dev, pFwPriv);
+ pucMappedFile = (u8*)(pFirmware->pFwHeader)+RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
+ ulFileLength = FwHdrSize-RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
+ break;
+
+ default:
+ RT_TRACE(COMP_ERR, "Unexpected Download step!!\n");
+ goto DownloadFirmware_Fail;
+ break;
+ }
+
+ rtStatus = FirmwareDownloadCode(dev, pucMappedFile, ulFileLength);
+
+ if(rtStatus != true)
+ {
+ RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n" );
+ goto DownloadFirmware_Fail;
+ }
+
+ rtStatus = FirmwareCheckReady(dev, FwStatus);
+
+ if(rtStatus != true)
+ {
+ RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n");
+ goto DownloadFirmware_Fail;
+ }
+
+ FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
+ }
+
+ RT_TRACE(COMP_FIRMWARE, "Firmware Download Success!!\n");
+ return rtStatus;
+
+ DownloadFirmware_Fail:
+ RT_TRACE(COMP_ERR, "Firmware Download Fail!!%x\n",read_nic_word(dev, TCR));
+ rtStatus = false;
+ return rtStatus;
+}
+void rtl8192se_dump_skb_data(struct sk_buff *skb)
+{
+ u8 i = 0;
+ u8 *arry = skb->data;
+
+ printk("\nSCAN_CMD/PROBE_REQ==============>\n");
+ for(i = 0; i < skb->len; i ++){
+ if((i % 4 == 0)&&(i != 0))
+ printk("\n");
+ printk("%2.2x ", arry[i]);
+ }
+ printk("\nSCAN_CMD/PROBE_REQ<==============\n");
+}
+
+void rtl8192se_dump_cmd_para(u8*SiteSurveyPara)
+{
+ u8 i = 0;
+ u8 desc_size = sizeof(tx_desc_fw);
+ u8 para_size = 8+desc_size;
+ u8 *arry = SiteSurveyPara;
+
+ printk("\nSCAN_CMD_PARA==============>\n");
+ for(i = 0; i < para_size; i ++){
+ if((i % 4 == 0)&&(i != 0))
+ printk("\n");
+ printk("%2.2x ", arry[i]);
+ }
+ printk("\nSCAN_CMD_PARA<==============\n");
+}
+#if 1 +RT_STATUS
+CmdSendPacket(
+ struct net_device *dev,
+ cb_desc *pTcb,
+ struct sk_buff *skb,
+ u32 BufferLen,
+ u32 PacketType,
+ bool bLastInitPacket + )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ RT_STATUS rtStatus = RT_STATUS_SUCCESS;
+
+ pTcb->queue_index = TXCMD_QUEUE;
+ pTcb->bCmdOrInit = PacketType; + pTcb->bLastIniPkt = bLastInitPacket;
+ pTcb->txbuf_size = BufferLen;
+
+
+ if(!priv->rtllib->check_nic_enough_desc(dev,pTcb->queue_index)||
+ (!skb_queue_empty(&priv->rtllib->skb_waitQ[pTcb->queue_index]))||\
+ (priv->rtllib->queue_stop) ) {
+ RT_TRACE(COMP_CMD,"=========================> tx full!\n");
+ skb_queue_tail(&priv->rtllib->skb_waitQ[pTcb->queue_index], skb);
+ } else {
+ priv->rtllib->softmac_hard_start_xmit(skb,dev);
+ }
+
+ return rtStatus;
+}
+
+u32
+FillH2CCmd(
+ struct sk_buff *skb,
+ u32 H2CBufferLen,
+ u32 CmdNum,
+ u32* pElementID,
+ u32* pCmdLen,
+ u8** pCmbBuffer,
+ u8* CmdStartSeq
+ )
+{
+ u8 i = 0;
+ u32 TotalLen = 0, Len = 0, TxDescLen = 0;
+ u32 preContinueOffset = 0;
+
+ u8* pH2CBuffer;
+
+ do
+ {
+ Len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pCmdLen[i], 8);
+
+ if(H2CBufferLen < TotalLen + Len + TxDescLen)
+ break;
+
+ pH2CBuffer = (u8 *) skb_put(skb, (u32)Len);
+ memset((pH2CBuffer + TotalLen + TxDescLen),0,Len);
+
+ SET_BITS_TO_LE_4BYTE((pH2CBuffer + TotalLen + TxDescLen), 0, 16, pCmdLen[i]);
+
+ SET_BITS_TO_LE_4BYTE((pH2CBuffer + TotalLen + TxDescLen), 16, 8, pElementID[i]);
+
+ *CmdStartSeq = *CmdStartSeq % 0x80;
+ SET_BITS_TO_LE_4BYTE((pH2CBuffer + TotalLen + TxDescLen), 24, 7, *CmdStartSeq);
+ ++ *CmdStartSeq;
+
+ memcpy((pH2CBuffer + TotalLen + TxDescLen + H2C_TX_CMD_HDR_LEN), pCmbBuffer[i], pCmdLen[i]);
+
+ if(i < CmdNum - 1) + SET_BITS_TO_LE_4BYTE((pH2CBuffer + preContinueOffset), 31, 1, 1);
+
+ preContinueOffset = TotalLen;
+
+ TotalLen += Len;
+ }while(++ i < CmdNum);
+
+ return TotalLen;
+}
+
+u32
+GetH2CCmdLen(
+ u32 H2CBufferLen,
+ u32 CmdNum,
+ u32* pCmdLen
+ )
+{
+ u8 i = 0;
+ u32 TotalLen = 0, Len = 0, TxDescLen = 0;
+
+ do
+ {
+ Len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pCmdLen[i], 8);
+
+ if(H2CBufferLen < TotalLen + Len + TxDescLen)
+ break;
+
+ TotalLen += Len;
+ }while(++ i < CmdNum);
+
+ return TotalLen + TxDescLen;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function: FirmwareSetH2CCmd()
+ *
+ * Overview: Set FW H2C command (Decide ElementID, cmd content length, and get FW buffer)
+ *
+ * Input: H2CCmd: H2C command type.
+ * pCmdBuffer: Pointer of the H2C command content.
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS
+ *
+ * Revised History:
+ * When Who Remark
+ * 2009/1/12 tynli Create the version 0.
+ *
+ *---------------------------------------------------------------------------*/
+RT_STATUS
+FirmwareSetH2CCmd(
+ struct net_device *dev,
+ u8 H2CCmd,
+ u8* pCmdBuffer
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u32 ElementID;
+ u32 Cmd_Len;
+ cb_desc *pTcb;
+ struct sk_buff *skb;
+ u32 Len;
+
+ RT_STATUS rtStatus;
+
+ switch(H2CCmd){
+ case FW_H2C_SETPWRMODE:
+ {
+ ElementID = H2C_SetPwrMode_CMD ;
+ Cmd_Len = sizeof(H2C_SETPWRMODE_PARM);
+ }
+ break;
+ case FW_H2C_JOINBSSRPT:
+ {
+ ElementID = H2C_JoinbssRpt_CMD;
+ Cmd_Len = sizeof(H2C_JOINBSSRPT_PARM);
+ }
+ break;
+ case FW_H2C_WoWLAN_UPDATE_GTK:
+ {
+ ElementID = H2C_WoWLAN_UPDATE_GTK_CMD;
+ Cmd_Len = sizeof(H2C_WPA_TWO_WAY_PARA);
+ }
+ break;
+ case FW_H2C_WoWLAN_UPDATE_IV:
+ {
+ ElementID = H2C_WoWLAN_UPDATE_IV_CMD;
+ Cmd_Len = sizeof(unsigned long long);
+ }
+ break;
+
+ case FW_H2C_WoWLAN_OFFLOAD:
+ {
+ ElementID = H2C_WoWLAN_FW_OFFLOAD;
+ Cmd_Len = sizeof(u8);
+ }
+ break;
+ case FW_H2C_SITESURVEY:
+ {
+ ElementID = H2C_SiteSurvey_CMD;
+ Cmd_Len = sizeof(H2C_SITESURVEY_PARA) + ((PH2C_SITESURVEY_PARA)pCmdBuffer)->probe_req_len - sizeof(tx_desc_fw);
+ }
+ break;
+ default:
+ break;
+ }
+
+ RT_TRACE(COMP_CMD, "FirmwareSetH2CCmd() HW_VAR_SET_TX_CMD: ElementID = %d, %d+%d=Cmd_Len = %d\n", ElementID, sizeof(H2C_SITESURVEY_PARA),((PH2C_SITESURVEY_PARA)pCmdBuffer)->probe_req_len, Cmd_Len);
+
+ {
+ Len = GetH2CCmdLen(MAX_TRANSMIT_BUFFER_SIZE, 1, &Cmd_Len);
+
+ RT_TRACE(COMP_CMD, "---------->%s(), cmdlen:%d,len:%d\n", __func__,Cmd_Len,Len);
+ skb = dev_alloc_skb(Len);
+ memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev));
+
+ pTcb = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE);
+
+ FillH2CCmd(skb, MAX_TRANSMIT_BUFFER_SIZE, 1, &ElementID, &Cmd_Len, &pCmdBuffer, &priv->H2CTxCmdSeq);
+
+
+ rtStatus = CmdSendPacket(dev, pTcb, skb, Len, DESC_PACKET_TYPE_NORMAL, false);
+
+ }
+
+ write_nic_byte(dev, TPPoll, BIT0<<(TXCMD_QUEUE)); +
+ return RT_STATUS_SUCCESS;
+}
+
+
+void
+rtl8192se_set_scan_cmd(struct net_device *dev, u32 start_flag)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ H2C_SITESURVEY_PARA *SiteSurveyPara;
+
+ if (!priv->scan_cmd) {
+ priv->scan_cmd = kmalloc(sizeof(H2C_SITESURVEY_PARA) +
+ RTL_MAX_SCAN_SIZE, GFP_KERNEL);
+ if (!priv->scan_cmd) {
+ printk("----------->%s() Error!!!\n", __func__);
+ return;
+ }
+ }
+
+ SiteSurveyPara = priv->scan_cmd;
+ memset(SiteSurveyPara, 0, sizeof(struct _H2C_SITESURVEY_PARA) + RTL_MAX_SCAN_SIZE);
+
+ if(start_flag){
+ struct sk_buff *skb = rtllib_probe_req(priv->rtllib);
+ cb_desc *tcb_desc = (cb_desc *)(skb->cb + 8);
+
+
+ tcb_desc->queue_index = MGNT_QUEUE;
+ tcb_desc->data_rate = MgntQuery_MgntFrameTxRate(priv->rtllib);
+ tcb_desc->RATRIndex = 7;
+ tcb_desc->bTxDisableRateFallBack = 1;
+ tcb_desc->bTxUseDriverAssingedRate = 1;
+
+
+ SiteSurveyPara->start_flag = start_flag;
+ SiteSurveyPara->probe_req_len = skb->len + sizeof(tx_desc_fw);
+
+ SiteSurveyPara->desc.MacID = 0;
+ SiteSurveyPara->desc.TXHT = (tcb_desc->data_rate&0x80)?1:0;
+ SiteSurveyPara->desc.TxRate = MRateToHwRate8192SE(dev,tcb_desc->data_rate);
+ SiteSurveyPara->desc.TxShort = QueryIsShort(((tcb_desc->data_rate&0x80)?1:0), MRateToHwRate8192SE(dev,tcb_desc->data_rate), tcb_desc);
+
+ SiteSurveyPara->desc.AggEn = 0;
+ SiteSurveyPara->desc.Seq = 0; + SiteSurveyPara->desc.RTSEn = (tcb_desc->bRTSEnable && tcb_desc->bCTSEnable==false)?1:0;
+ SiteSurveyPara->desc.CTS2Self = (tcb_desc->bCTSEnable)?1:0;
+ SiteSurveyPara->desc.RTSSTBC = (tcb_desc->bRTSSTBC)?1:0;
+ SiteSurveyPara->desc.RTSHT = (tcb_desc->rts_rate&0x80)?1:0;
+ SiteSurveyPara->desc.RTSRate = MRateToHwRate8192SE(dev,tcb_desc->rts_rate);
+ SiteSurveyPara->desc.RTSRate = MRateToHwRate8192SE(dev,MGN_24M);
+ SiteSurveyPara->desc.RTSBW = 0;
+ SiteSurveyPara->desc.RTSSC = tcb_desc->RTSSC;
+ SiteSurveyPara->desc.RTSShort = (SiteSurveyPara->desc.RTSHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):(tcb_desc->bRTSUseShortGI?1:0);
+
+ if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40){
+ if(tcb_desc->bPacketBW) {
+ SiteSurveyPara->desc.TxBw = 1;
+ SiteSurveyPara->desc.TXSC = 0;
+ } else {
+ SiteSurveyPara->desc.TxBw = 0;
+ SiteSurveyPara->desc.TXSC = priv->nCur40MhzPrimeSC;
+ }
+ } else {
+ SiteSurveyPara->desc.TxBw = 0;
+ SiteSurveyPara->desc.TXSC = 0;
+ }
+
+ SiteSurveyPara->desc.LINIP = 0; + SiteSurveyPara->desc.Offset = 32; + SiteSurveyPara->desc.PktSize = (u16)skb->len;
+
+ SiteSurveyPara->desc.RaBRSRID = tcb_desc->RATRIndex;
+
+ SiteSurveyPara->desc.PktID = 0x0;
+ SiteSurveyPara->desc.QueueSel = rtl8192se_MapHwQueueToFirmwareQueue(tcb_desc->queue_index, tcb_desc->priority);
+
+ SiteSurveyPara->desc.DataRateFBLmt= 0x1F; + SiteSurveyPara->desc.DISFB = tcb_desc->bTxDisableRateFallBack;
+ SiteSurveyPara->desc.UserRate = tcb_desc->bTxUseDriverAssingedRate;
+
+
+ SiteSurveyPara->desc.FirstSeg = 1; + SiteSurveyPara->desc.LastSeg = 1; +
+ SiteSurveyPara->desc.TxBufferSize = (u16)skb->len;
+
+ SiteSurveyPara->desc.OWN = 1;
+
+
+ memcpy(&SiteSurveyPara->probe_req[0], skb->data, (u16)skb->len);
+
+ dev_kfree_skb_any(skb);
+ } else {
+ SiteSurveyPara->start_flag = start_flag;
+ SiteSurveyPara->probe_req_len = 0;
+ }
+
+ FirmwareSetH2CCmd( dev ,FW_H2C_SITESURVEY, (u8*)SiteSurveyPara);
+}
+
+int rtl8192se_send_scan_cmd(struct net_device *dev, bool start)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ if(start){
+ priv->rtllib->scan_watch_dog =0;
+#if 0
+ queue_delayed_work_rsl(priv->priv_wq,&priv->hw_scan_simu_wq,0);
+#else
+ rtl8192se_set_scan_cmd(dev, start);
+#endif
+ } else {
+#if 0
+ rtl8192se_rx_surveydone_cmd(dev);
+#else
+ rtl8192se_set_scan_cmd(dev, start);
+#endif
+ }
+ return true;
+}
+#endif
+
+#endif
diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_firmware.h b/ubuntu/rtl8192se/rtl8192s/r8192S_firmware.h new file mode 100644 index 000000000000..7784db18b851 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_firmware.h @@ -0,0 +1,419 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef __INC_FIRMWARE_H +#define __INC_FIRMWARE_H + +#include "r8192S_def.h" + +#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 +#define RTL8190_CPU_START_OFFSET 0x80 +#define MAX_FIRMWARE_CODE_SIZE 0xFF00 + +#define H2C_TX_CMD_HDR_LEN 8 + +#define RTL8192S_FW_PKT_FRAG_SIZE 0x4000 + +#ifdef RTL8192SE +#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8 +#else +#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN) +#endif + +typedef enum _DESC_PACKET_TYPE{ + DESC_PACKET_TYPE_INIT = 0, + DESC_PACKET_TYPE_NORMAL = 1, +}DESC_PACKET_TYPE; + + +#ifdef RTL8192S +typedef enum _firmware_init_step{ + FW_INIT_STEP0_IMEM = 0, + FW_INIT_STEP1_MAIN = 1, + FW_INIT_STEP2_DATA = 2, +}firmware_init_step_e; +#else +typedef enum _firmware_init_step{ + FW_INIT_STEP0_BOOT = 0, + FW_INIT_STEP1_MAIN = 1, + FW_INIT_STEP2_DATA = 2, +}firmware_init_step_e; +#endif + +typedef enum _firmware_source{ + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, +}firmware_source_e, *pfirmware_source_e; + +typedef enum _opt_rst_type{ + OPT_SYSTEM_RESET = 0, + OPT_FIRMWARE_RESET = 1, +}opt_rst_type_e; + +typedef enum _FIRMWARE_STATUS{ + FW_STATUS_0_INIT = 0, + FW_STATUS_1_MOVE_BOOT_CODE = 1, + FW_STATUS_2_MOVE_MAIN_CODE = 2, + FW_STATUS_3_TURNON_CPU = 3, + FW_STATUS_4_MOVE_DATA_CODE = 4, + FW_STATUS_5_READY = 5, +}FIRMWARE_STATUS; + +typedef enum _H2C_CMD{ + FW_H2C_SETPWRMODE = 0, + FW_H2C_JOINBSSRPT = 1, + FW_H2C_WoWLAN_UPDATE_GTK = 2, + FW_H2C_WoWLAN_UPDATE_IV = 3, + FW_H2C_WoWLAN_OFFLOAD = 4, + FW_H2C_SITESURVEY=5, +}H2C_CMD; + + typedef struct _H2C_SETPWRMODE_PARM { + u8 mode; + u8 flag_low_traffic_en; + u8 flag_lpnav_en; + u8 flag_rf_low_snr_en; + u8 flag_dps_en; + u8 bcn_rx_en; + u8 bcn_pass_cnt; + u8 bcn_to; // beacon TO (ms). ¡§=0¡¨ no limit. + u16 bcn_itv; + u8 app_itv; + u8 awake_bcn_itvl; + u8 smart_ps; + u8 bcn_pass_period; + }H2C_SETPWRMODE_PARM, *PH2C_SETPWRMODE_PARM; + +typedef struct _H2C_JOINBSSRPT_PARM { + u8 OpMode; + u8 Ps_Qos_Info; + u8 Bssid[6]; + u16 BcnItv; + u16 Aid; +}H2C_JOINBSSRPT_PARM, *PH2C_JOINBSSRPT_PARM; + +typedef struct _H2C_WPA_PTK { + u8 kck[16]; /* EAPOL-Key Key Confirmation Key (KCK) */ + u8 kek[16]; /* EAPOL-Key Key Encryption Key (KEK) */ + u8 tk1[16]; /* Temporal Key 1 (TK1) */ + union { + u8 tk2[16]; + struct { + u8 tx_mic_key[8]; + u8 rx_mic_key[8]; + }Athu; + }U; +}H2C_WPA_PTK; + +typedef struct _H2C_WPA_TWO_WAY_PARA{ + u8 pairwise_en_alg; + u8 group_en_alg; + H2C_WPA_PTK wpa_ptk_value; +}H2C_WPA_TWO_WAY_PARA, *PH2C_WPA_TWO_WAY_PARA; + +typedef struct _tx_desc_8192se_fw{ + + u32 PktSize:16; + u32 Offset:8; + u32 Type:2; + u32 LastSeg:1; + u32 FirstSeg:1; + u32 LINIP:1; + u32 AMSDU:1; + u32 GF:1; + u32 OWN:1; + + u32 MacID:5; + u32 MoreData:1; + u32 MoreFrag:1; + u32 PIFS:1; + u32 QueueSel:5; + u32 AckPolicy:2; + u32 NoACM:1; + u32 NonQos:1; + u32 KeyID:2; + u32 OUI:1; + u32 PktType:1; + u32 EnDescID:1; + u32 SecType:2; + u32 HTC:1; + u32 WDS:1; + u32 PktOffset:5; + u32 HWPC:1; + + u32 DataRetryLmt:6; + u32 RetryLmtEn:1; + u32 TSFL:5; + u32 RTSRC:6; + u32 DATARC:6; + + u32 Rsvd1:5; + u32 AggEn:1; + u32 BK:1; + u32 OwnMAC:1; + + u32 NextHeadPage:8; + u32 TailPage:8; + u32 Seq:12; + u32 Frag:4; + + u32 RTSRate:6; + u32 DisRTSFB:1; + u32 RTSRateFBLmt:4; + u32 CTS2Self:1; + u32 RTSEn:1; + u32 RaBRSRID:3; + u32 TXHT:1; + u32 TxShort:1; + u32 TxBw:1; + u32 TXSC:2; + u32 STBC:2; + u32 RD:1; + u32 RTSHT:1; + u32 RTSShort:1; + u32 RTSBW:1; + u32 RTSSC:2; + u32 RTSSTBC:2; + u32 UserRate:1; + + u32 PktID:9; + u32 TxRate:6; + u32 DISFB:1; + u32 DataRateFBLmt:5; + u32 TxAGC:11; + + u32 IPChkSum:16; + u32 TCPChkSum:16; + + u32 TxBufferSize:16; + u32 IPHdrOffset:8; + u32 Rsvd3:7; + u32 TCPEn:1; +} tx_desc_fw, *ptx_desc_fw; + +typedef struct _H2C_SITESURVEY_PARA { + u32 start_flag; + u32 probe_req_len; + tx_desc_fw desc; + u8 probe_req[0]; +}H2C_SITESURVEY_PARA, *PH2C_SITESURVEY_PARA; + + typedef enum _FIRMWARE_H2C_CMD{ + H2C_Read_MACREG_CMD , /*0*/ + H2C_Write_MACREG_CMD , + H2C_ReadBB_CMD , + H2C_WriteBB_CMD , + H2C_ReadRF_CMD , + H2C_WriteRF_CMD , /*5*/ + H2C_Read_EEPROM_CMD , + H2C_Write_EEPROM_CMD , + H2C_Read_EFUSE_CMD , + H2C_Write_EFUSE_CMD , + H2C_Read_CAM_CMD , /*10*/ + H2C_Write_CAM_CMD , + H2C_setBCNITV_CMD, + H2C_setMBIDCFG_CMD, + H2C_JoinBss_CMD , + H2C_DisConnect_CMD, /*15*/ + H2C_CreateBss_CMD , + H2C_SetOpMode_CMD, + H2C_SiteSurvey_CMD, + H2C_SetAuth_CMD, + H2C_SetKey_CMD , /*20*/ + H2C_SetStaKey_CMD , + H2C_SetAssocSta_CMD, + H2C_DelAssocSta_CMD , + H2C_SetStaPwrState_CMD , + H2C_SetBasicRate_CMD , /*25*/ + H2C_GetBasicRate_CMD , + H2C_SetDataRate_CMD , + H2C_GetDataRate_CMD , + H2C_SetPhyInfo_CMD , + H2C_GetPhyInfo_CMD , /*30*/ + H2C_SetPhy_CMD , + H2C_GetPhy_CMD , + H2C_readRssi_CMD , + H2C_readGain_CMD , + H2C_SetAtim_CMD , /*35*/ + H2C_SetPwrMode_CMD , + H2C_JoinbssRpt_CMD, + H2C_SetRaTable_CMD , + H2C_GetRaTable_CMD , + H2C_GetCCXReport_CMD, /*40*/ + H2C_GetDTMReport_CMD, + H2C_GetTXRateStatistics_CMD, + H2C_SetUsbSuspend_CMD, + H2C_SetH2cLbk_CMD , + H2C_tmp1 , /*45*/ + H2C_WoWLAN_UPDATE_GTK_CMD , + H2C_WoWLAN_FW_OFFLOAD , + H2C_tmp2 , + H2C_tmp3 , + H2C_WoWLAN_UPDATE_IV_CMD , /*50*/ + H2C_tmp4, + MAX_H2CCMD /*52*/ +}FIRMWARE_H2C_CMD; + + +typedef struct _RT_8192S_FIRMWARE_PRIV { + + u8 signature_0; + u8 signature_1; + u8 hci_sel; + u8 chip_version; + u8 customer_ID_0; + u8 customer_ID_1; + u8 rf_config; + u8 usb_ep_num; + + u8 regulatory_class_0; + u8 regulatory_class_1; + u8 regulatory_class_2; + u8 regulatory_class_3; + u8 rfintfs; + u8 def_nettype; + u8 rsvd010; + u8 rsvd011; + + + u8 lbk_mode; + u8 mp_mode; + u8 rsvd020; + u8 rsvd021; + u8 rsvd022; + u8 rsvd023; + u8 rsvd024; + u8 rsvd025; + + u8 qos_en; + u8 bw_40MHz_en; + u8 AMSDU2AMPDU_en; + u8 AMPDU_en; + u8 rate_control_offload; + u8 aggregation_offload; + u8 rsvd030; + u8 rsvd031; + + + unsigned char beacon_offload; + unsigned char MLME_offload; + unsigned char hwpc_offload; + unsigned char tcp_checksum_offload; + unsigned char tcp_offload; + unsigned char ps_control_offload; + unsigned char WWLAN_offload; + unsigned char rsvd040; + + u8 tcp_tx_frame_len_L; + u8 tcp_tx_frame_len_H; + u8 tcp_rx_frame_len_L; + u8 tcp_rx_frame_len_H; + u8 rsvd050; + u8 rsvd051; + u8 rsvd052; + u8 rsvd053; +}RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV; + +typedef struct _RT_8192S_FIRMWARE_HDR { + + u16 Signature; + u16 Version; + u32 DMEMSize; + + + u32 IMG_IMEM_SIZE; + u32 IMG_SRAM_SIZE; + + u32 FW_PRIV_SIZE; + u32 Rsvd0; + + u32 Rsvd1; + u32 Rsvd2; + + RT_8192S_FIRMWARE_PRIV FWPriv; + +}RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR; + +#define RT_8192S_FIRMWARE_HDR_SIZE 80 +#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32 + +typedef enum _FIRMWARE_8192S_STATUS{ + FW_STATUS_INIT = 0, + FW_STATUS_LOAD_IMEM = 1, + FW_STATUS_LOAD_EMEM = 2, + FW_STATUS_LOAD_DMEM = 3, + FW_STATUS_READY = 4, +}FIRMWARE_8192S_STATUS; + +typedef struct _rt_firmware{ + firmware_source_e eFWSource; + PRT_8192S_FIRMWARE_HDR pFwHeader; + FIRMWARE_8192S_STATUS FWStatus; + u16 FirmwareVersion; + u8 FwIMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE]; + u8 FwEMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE]; + u32 FwIMEMLen; + u32 FwEMEMLen; + u8 szFwTmpBuffer[164000]; + u32 szFwTmpBufferLen; + u16 CmdPacketFragThresold; +}rt_firmware, *prt_firmware; + +#define FW_DIG_ENABLE_CTL BIT0 +#define FW_HIGH_PWR_ENABLE_CTL BIT1 +#define FW_SS_CTL BIT2 +#define FW_RA_INIT_CTL BIT3 +#define FW_RA_BG_CTL BIT4 +#define FW_RA_N_CTL BIT5 +#define FW_PWR_TRK_CTL BIT6 +#define FW_IQK_CTL BIT7 +#define FW_FA_CTL BIT8 +#define FW_DRIVER_CTRL_DM_CTL BIT9 +#define FW_PAPE_CTL_BY_SW_HW BIT10 +#define FW_DISABLE_ALL_DM 0 + +#define FW_PWR_TRK_PARAM_CLR 0x0000ffff +#define FW_RA_PARAM_CLR 0xffff0000 + +#define FW_CMD_IO_CLR(priv, _Bit) \ + udelay(1000); \ + priv->FwCmdIOMap &= (~_Bit); + +#define FW_CMD_IO_UPDATE(priv, _val) \ + priv->FwCmdIOMap = _val; + +#define FW_CMD_IO_SET(priv, _val) \ + write_nic_word(priv->rtllib->dev, LBUS_MON_ADDR, (u16)_val); \ + FW_CMD_IO_UPDATE(priv, _val);\ + +#define FW_CMD_PARA_SET(priv, _val) \ + write_nic_dword(priv->rtllib->dev, LBUS_ADDR_MASK, _val); \ + priv->FwCmdIOParam = _val; + +#define FW_CMD_IO_QUERY(priv) (u16)(priv->FwCmdIOMap) +#define FW_CMD_IO_PARA_QUERY(priv) ((u32)(priv->FwCmdIOParam)) + +bool FirmwareEnableCPU(struct net_device *dev); +bool FirmwareCheckReady(struct net_device *dev, u8 LoadFWStatus); + +bool FirmwareDownload92S(struct net_device *dev); +int rtl8192se_send_scan_cmd(struct net_device *dev, bool start); + +void rtl8192se_dump_skb_data(struct sk_buff *skb); +#endif + diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_hw.h b/ubuntu/rtl8192se/rtl8192s/r8192S_hw.h new file mode 100644 index 000000000000..31be6fa135af --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_hw.h @@ -0,0 +1,1070 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#ifndef __INC_HAL8192SREG_H
+#define __INC_HAL8192SREG_H
+
+
+#if 0
+typedef enum _RT_RF_TYPE_DEF
+{
+ RF_1T2R = 0,
+ RF_2T4R,
+ RF_2T2R,
+ RF_1T1R,
+ RF_2T2R_GREEN,
+ RF_819X_MAX_TYPE
+}RT_RF_TYPE_DEF;
+#endif
+
+#define SYS_ISO_CTRL 0x0000 +#define SYS_FUNC_EN 0x0002 +#define PMC_FSM 0x0004 +#define SYS_CLKR 0x0008 +#define EPROM_CMD 0x000A +#define EE_VPD 0x000C +#define AFE_MISC 0x0010 +#define SPS0_CTRL 0x0011 +#define SPS1_CTRL 0x0018 +#define RF_CTRL 0x001F +#define LDOA15_CTRL 0x0020 +#define LDOV12D_CTRL 0x0021 +#define LDOHCI12_CTRL 0x0022 +#define LDO_USB_SDIO 0x0023 +#define LPLDO_CTRL 0x0024 +#define AFE_XTAL_CTRL 0x0026 +#define AFE_PLL_CTRL 0x0028 +#define EFUSE_CTRL 0x0030 +#define EFUSE_TEST 0x0034 +#define PWR_DATA 0x0038 +#define DBG_PORT 0x003A +#define DPS_TIMER 0x003C +#define RCLK_MON 0x003E +
+#define CMDR 0x0040 +#define TXPAUSE 0x0042 +#define LBKMD_SEL 0x0043 +#define TCR 0x0044 +#define RCR 0x0048 +#define MSR 0x004C +#define SYSF_CFG 0x004D +#define RX_PKY_LIMIT 0x004E +#define MBIDCTRL 0x004F +
+#define MACIDR 0x0050 +#define MACIDR0 0x0050 +#define MACIDR4 0x0054 +#define BSSIDR 0x0058 +#define HWVID 0x005E +#define MAR 0x0060 +#define MBIDCAMCONTENT 0x0068 +#define MBIDCAMCFG 0x0070 +#define BUILDTIME 0x0074 +#define BUILDUSER 0x0078 +
+#define IDR0 MACIDR0
+#define IDR4 MACIDR4
+
+#define TSFR 0x0080 +#define SLOT_TIME 0x0089 +#define USTIME 0x008A +#define SIFS_CCK 0x008C +#define SIFS_OFDM 0x008E +#define PIFS_TIME 0x0090 +#define ACK_TIMEOUT 0x0091 +#define EIFSTR 0x0092 +#define BCN_INTERVAL 0x0094 +#define ATIMWND 0x0096 +#define BCN_DRV_EARLY_INT 0x0098 +#define BCN_DMATIME 0x009A +#define BCN_ERR_THRESH 0x009C +#define MLT 0x009D +#define RSVD_MAC_TUNE_US 0x009E +
+#define RQPN 0x00A0
+#define RQPN1 0x00A0 +#define RQPN2 0x00A1 +#define RQPN3 0x00A2 +#define RQPN4 0x00A3 +#define RQPN5 0x00A4 +#define RQPN6 0x00A5 +#define RQPN7 0x00A6 +#define RQPN8 0x00A7 +#define RQPN9 0x00A8 +#define RQPN10 0x00A9 +#define LD_RQPN 0x00AB +#define RXFF_BNDY 0x00AC +#define RXRPT_BNDY 0x00B0 +#define TXPKTBUF_PGBNDY 0x00B4 +#define PBP 0x00B5 +#define RXDRVINFO_SZ 0x00B6 +#define TXFF_STATUS 0x00B7 +#define RXFF_STATUS 0x00B8 +#define TXFF_EMPTY_TH 0x00B9 +#define SDIO_RX_BLKSZ 0x00BC +#define RXDMA 0x00BD +#define RXPKT_NUM 0x00BE +#define C2HCMD_UDT_SIZE 0x00C0 +#define C2HCMD_UDT_ADDR 0x00C2 +#define FIFOPAGE1 0x00C4 +#define FIFOPAGE2 0x00C8 +#define FIFOPAGE3 0x00CC +#define FIFOPAGE4 0x00D0 +#define FIFOPAGE5 0x00D4 +#define FW_RSVD_PG_CRTL 0x00D8 +#define RXDMA_AGG_PG_TH 0x00D9 +#define TXDESC_MSK 0x00DC +#define TXRPTFF_RDPTR 0x00E0 +#define TXRPTFF_WTPTR 0x00E4 +#define C2HFF_RDPTR 0x00E8 +#define C2HFF_WTPTR 0x00EC +#define RXFF0_RDPTR 0x00F0 +#define RXFF0_WTPTR 0x00F4 +#define RXFF1_RDPTR 0x00F8 +#define RXFF1_WTPTR 0x00FC +#define RXRPT0_RDPTR 0x0100 +#define RXRPT0_WTPTR 0x0104 +#define RXRPT1_RDPTR 0x0108 +#define RXRPT1_WTPTR 0x010C +#define RX0_UDT_SIZE 0x0110 +#define RX1PKTNUM 0x0114 +#define RXFILTERMAP 0x0116 +#define RXFILTERMAP_GP1 0x0118 +#define RXFILTERMAP_GP2 0x011A +#define RXFILTERMAP_GP3 0x011C +#define BCNQ_CTRL 0x0120 +#define MGTQ_CTRL 0x0124 +#define HIQ_CTRL 0x0128 +#define VOTID7_CTRL 0x012c +#define VOTID6_CTRL 0x0130 +#define VITID5_CTRL 0x0134 +#define VITID4_CTRL 0x0138 +#define BETID3_CTRL 0x013c +#define BETID0_CTRL 0x0140 +#define BKTID2_CTRL 0x0144 +#define BKTID1_CTRL 0x0148 +#define CMDQ_CTRL 0x014c +#define TXPKT_NUM_CTRL 0x0150 +#define TXQ_PGADD 0x0152 +#define TXFF_PG_NUM 0x0154 +#define TRXDMA_STATUS 0x0156 +
+#define INIMCS_SEL 0x0160 +#define TX_RATE_REG INIMCS_SEL +#define INIRTSMCS_SEL 0x0180 +#define RRSR 0x0181 +#define ARFR0 0x0184 +#define ARFR1 0x0188 +#define ARFR2 0x018C +#define ARFR3 0x0190 +#define ARFR4 0x0194 +#define ARFR5 0x0198 +#define ARFR6 0x019C +#define ARFR7 0x01A0 +#define AGGLEN_LMT_H 0x01A7 +#define AGGLEN_LMT_L 0x01A8 +#define DARFRC 0x01B0 +#define RARFRC 0x01B8 +#define MCS_TXAGC 0x01C0
+#define CCK_TXAGC 0x01C8
+
+#define EDCAPARA_VO 0x01D0 +#define EDCAPARA_VI 0x01D4 +#define EDCAPARA_BE 0x01D8 +#define EDCAPARA_BK 0x01DC +#define BCNTCFG 0x01E0 +#define CWRR 0x01E2 +#define ACMAVG 0x01E4 +#define AcmHwCtrl 0x01E7
+#define VO_ADMTM 0x01E8 +#define VI_ADMTM 0x01EC
+#define BE_ADMTM 0x01F0
+#define RETRY_LIMIT 0x01F4 +#define SG_RATE 0x01F6 +
+#define NAV_CTRL 0x0200
+#define BW_OPMODE 0x0203
+#define BACAMCMD 0x0204
+#define BACAMCONTENT 0x0208 +
+#define LBDLY 0x0210 +#define FWDLY 0x0211 +#define HWPC_RX_CTRL 0x0218 +#define MQIR 0x0220 +#define MAIR 0x0222 +#define MSIR 0x0224 +#define CLM_RESULT 0x0227 +#define NHM_RPI_CNT 0x0228 +#define RXERR_RPT 0x0230 +#define NAV_PROT_LEN 0x0234 +#define CFEND_TH 0x0236 +#define AMPDU_MIN_SPACE 0x0237 +#define TXOP_STALL_CTRL 0x0238
+
+#define RWCAM 0x0240 +#define WCAMI 0x0244 +#define RCAMO 0x0248 +#define CAMDBG 0x024C
+#define SECR 0x0250 +
+#define WOW_CTRL 0x0260 +#define PSSTATUS 0x0261 +#define PSSWITCH 0x0262 +#define MIMOPS_WAIT_PERIOD 0x0263
+#define LPNAV_CTRL 0x0264
+#define WFM0 0x0270 +#define WFM1 0x0280 +#define WFM2 0x0290 +#define WFM3 0x02A0 +#define WFM4 0x02B0 +#define WFM5 0x02C0 +#define WFCRC 0x02D0 +#define FW_RPT_REG 0x02c4
+
+#define PSTIME 0x02E0 +#define TIMER0 0x02E4 +#define TIMER1 0x02E8 +#define GPIO_CTRL 0x02EC +#define GPIO_IN 0x02EC +#define GPIO_OUT 0x02ED +#define GPIO_IO_SEL 0x02EE +#define GPIO_MOD 0x02EF +#define GPIO_INTCTRL 0x02F0 +#define MAC_PINMUX_CFG 0x02F1 +#define LEDCFG 0x02F2 +#define PHY_REG 0x02F3 +#define PHY_REG_DATA 0x02F4 +#define EFUSE_CLK 0x02F8 +
+#define INTA_MASK 0x0300 +#define ISR 0x0308 +
+#define DBG_PORT_SWITCH 0x003A
+#define BIST 0x0310 +#define DBS 0x0314 +#define CPUINST 0x0318 +#define CPUCAUSE 0x031C +#define LBUS_ERR_ADDR 0x0320 +#define LBUS_ERR_CMD 0x0324 +#define LBUS_ERR_DATA_L 0x0328 +#define LBUS_ERR_DATA_H 0x032C +#define LX_EXCEPTION_ADDR 0x0330 +#define WDG_CTRL 0x0334 +#define INTMTU 0x0338 +#define INTM 0x033A +#define FDLOCKTURN0 0x033C +#define FDLOCKTURN1 0x033D +#define TRXPKTBUF_DBG_DATA 0x0340 +#define TRXPKTBUF_DBG_CTRL 0x0348 +#define DPLL 0x034A +#define CBUS_ERR_ADDR 0x0350 +#define CBUS_ERR_CMD 0x0354 +#define CBUS_ERR_DATA_L 0x0358 +#define CBUS_ERR_DATA_H 0x035C +#define USB_SIE_INTF_ADDR 0x0360 +#define USB_SIE_INTF_WD 0x0361 +#define USB_SIE_INTF_RD 0x0362 +#define USB_SIE_INTF_CTRL 0x0363 +#define LBUS_MON_ADDR 0x0364 +#define LBUS_ADDR_MASK 0x0368 +
+
+#define TPPoll 0x0500 +#define PM_CTRL 0x0502 +#define PCIF 0x0503 +
+#define THPDA 0x0514 +#define TMDA 0x0518 +#define TCDA 0x051C +#define HDA 0x0520 +#define TVODA 0x0524 +#define TVIDA 0x0528 +#define TBEDA 0x052C +#define TBKDA 0x0530 +#define TBDA 0x0534 +#define RCDA 0x0538 +#define RDQDA 0x053C +#define DBI_WDATA 0x0540 +#define DBI_RDATA 0x0544 +#define DBI_CTRL 0x0548 +#define MDIO_DATA 0x0550 +#define MDIO_CTRL 0x0554 +#define PCI_RPWM 0x0561 +#define PCI_CPWM 0x0563 +
+
+#define PHY_CCA 0x803 +
+
+#define USB_RX_AGG_TIMEOUT 0xFE5B
+
+#define FW_OFFLOAD_EN BIT7
+
+#define MAX_MSS_DENSITY_2T 0x13
+#define MAX_MSS_DENSITY_1T 0x0A
+
+#define RXDMA_AGG_EN BIT7
+
+#define RXDMA_AGG_TIMEOUT_DISABLE 0x00
+#define RXDMA_AGG_TIMEOUT_17MS 0x01
+#define RXDMA_AGG_TIMEOUT_17_2_MS 0x02
+#define RXDMA_AGG_TIMEOUT_17_4_MS 0x04
+#define RXDMA_AGG_TIMEOUT_17_10_MS 0x0A
+
+#define InvalidBBRFValue 0x12345678
+
+#define USB_RPWM 0xFE58
+
+#ifdef RTL8192SE
+#define RPWM PCI_RPWM
+#endif
+#ifdef RTL8192SU
+#define RPWM USB_RPWM
+#endif
+
+#if 1 +#define AFR 0x010 +#define BCN_TCFG 0x062 +#define RATR0 0x320 +#endif
+#define UnusedRegister 0x0320
+#define PSR UnusedRegister +#define DCAM UnusedRegister +#define BBAddr UnusedRegister +#define PhyDataR UnusedRegister +#define UFWP UnusedRegister
+
+
+
+#define ISO_MD2PP BIT0 +#define ISO_PA2PCIE BIT3 +#define ISO_PLL2MD BIT4 +#define ISO_PWC_DV2RP BIT11 +#define ISO_PWC_RV2RP BIT12 +
+#define FEN_MREGEN BIT15 +#define FEN_DCORE BIT11 +#define FEN_CPUEN BIT10 +
+#define PAD_HWPD_IDN BIT22 +
+#define SYS_CLKSEL_80M BIT0 +#define SYS_PS_CLKSEL BIT1 +#define SYS_CPU_CLKSEL BIT2 +#define SYS_MAC_CLK_EN BIT11 +#define SYS_SWHW_SEL BIT14 +#define SYS_FWHW_SEL BIT15 +
+
+#define CmdEEPROM_En BIT5 +#define CmdEERPOMSEL BIT4 +#define Cmd9346CR_9356SEL BIT4
+#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
+#define AutoLoadEFUSE CmdEEPROM_En
+#define EPROM_CMD_OPERATING_MODE_SHIFT 6
+#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
+#define EPROM_CMD_CONFIG 0x3
+#define EPROM_CMD_NORMAL 0
+#define EPROM_CMD_LOAD 1
+#define EPROM_CMD_PROGRAM 2
+#define EPROM_CS_SHIFT 3
+#define EPROM_CK_SHIFT 2
+#define EPROM_W_SHIFT 1
+#define EPROM_R_SHIFT 0
+
+#define AFE_MBEN BIT1 +#define AFE_BGEN BIT0 +
+#define SPS1_SWEN BIT1 +#define SPS1_LDEN BIT0 +
+#define RF_EN BIT0 +#define RF_RSTB BIT1 +#define RF_SDMRSTB BIT2 +
+#define LDA15_EN BIT0 +
+#define LDV12_EN BIT0 +#define LDV12_SDBY BIT1 +
+#define XTAL_GATE_AFE BIT10
+
+#define APLL_EN BIT0 +
+#define AFR_CardBEn BIT0
+#define AFR_CLKRUN_SEL BIT1
+#define AFR_FuncRegEn BIT2
+
+#define APSDOFF_STATUS BIT15 +#define APSDOFF BIT14 +#define BBRSTn BIT13 +#define BB_GLB_RSTn BIT12 +#define SCHEDULE_EN BIT10 +#define MACRXEN BIT9 +#define MACTXEN BIT8 +#define DDMA_EN BIT7 +#define FW2HW_EN BIT6 +#define RXDMA_EN BIT5 +#define TXDMA_EN BIT4 +#define HCI_RXDMA_EN BIT3 +#define HCI_TXDMA_EN BIT2 +
+#define StopHCCA BIT6
+#define StopHigh BIT5
+#define StopMgt BIT4
+#define StopVO BIT3
+#define StopVI BIT2
+#define StopBE BIT1
+#define StopBK BIT0
+
+#define LBK_NORMAL 0x00
+#define LBK_MAC_LB (BIT0|BIT1|BIT3)
+#define LBK_MAC_DLB (BIT0|BIT1)
+#define LBK_DMA_LB (BIT0|BIT1|BIT2)
+
+#define TCP_OFDL_EN BIT25 +#define HWPC_TX_EN BIT24 +#define TXDMAPRE2FULL BIT23 +#define DISCW BIT20 +#define TCRICV BIT19 +#define CfendForm BIT17 +#define TCRCRC BIT16 +#define FAKE_IMEM_EN BIT15 +#define TSFRST BIT9 +#define TSFEN BIT8 +#define FWALLRDY (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7)
+#define FWRDY BIT7
+#define BASECHG BIT6
+#define IMEM BIT5
+#define DMEM_CODE_DONE BIT4
+#define EXT_IMEM_CHK_RPT BIT3
+#define EXT_IMEM_CODE_DONE BIT2
+#define IMEM_CHK_RPT BIT1
+#define IMEM_CODE_DONE BIT0
+#define IMEM_CODE_DONE BIT0
+#define IMEM_CHK_RPT BIT1
+#define EMEM_CODE_DONE BIT2
+#define EMEM_CHK_RPT BIT3
+#define DMEM_CODE_DONE BIT4
+#define IMEM_RDY BIT5
+#define BASECHG BIT6
+#define FWRDY BIT7
+#define LOAD_FW_READY (IMEM_CODE_DONE|IMEM_CHK_RPT|EMEM_CODE_DONE|\
+ EMEM_CHK_RPT|DMEM_CODE_DONE|IMEM_RDY|BASECHG|\
+ FWRDY)
+#define TCR_TSFEN BIT8 +#define TCR_TSFRST BIT9 +#define TCR_FAKE_IMEM_EN BIT15
+#define TCR_CRC BIT16
+#define TCR_ICV BIT19 +#define TCR_DISCW BIT20 +#define TCR_HWPC_TX_EN BIT24
+#define TCR_TCP_OFDL_EN BIT25
+#define TXDMA_INIT_VALUE (IMEM_CHK_RPT|EXT_IMEM_CHK_RPT)
+
+#define RCR_APPFCS BIT31 +#define RCR_DIS_ENC_2BYTE BIT30 +#define RCR_DIS_AES_2BYTE BIT29 +#define RCR_HTC_LOC_CTRL BIT28 +#define RCR_ENMBID BIT27 +#define RCR_RX_TCPOFDL_EN BIT26 +#define RCR_APP_PHYST_RXFF BIT25 +#define RCR_APP_PHYST_STAFF BIT24 +#define RCR_CBSSID BIT23 +#define RCR_APWRMGT BIT22 +#define RCR_ADD3 BIT21 +#define RCR_AMF BIT20 +#define RCR_ACF BIT19 +#define RCR_ADF BIT18 +#define RCR_APP_MIC BIT17 +#define RCR_APP_ICV BIT16 +#define RCR_RXFTH BIT13 +#define RCR_AICV BIT12 +#define RCR_RXDESC_LK_EN BIT11 +#define RCR_APP_BA_SSN BIT6 +#define RCR_ACRC32 BIT5 +#define RCR_RXSHFT_EN BIT4 +#define RCR_AB BIT3 +#define RCR_AM BIT2 +#define RCR_APM BIT1 +#define RCR_AAP BIT0 +#define RCR_MXDMA_OFFSET 8
+#define RCR_FIFO_OFFSET 13
+
+/*
+Network Type
+00: No link
+01: Link in ad hoc network
+10: Link in infrastructure network
+11: AP mode
+Default: 00b.
+*/
+#define MSR_LINK_MASK ((1<<0)|(1<<1))
+#define MSR_LINK_MANAGED 2
+#define MSR_LINK_NONE 0
+#define MSR_LINK_SHIFT 0
+#define MSR_LINK_ADHOC 1
+#define MSR_LINK_MASTER 3
+#if 1
+#define MSR_NOLINK 0x00
+#define MSR_ADHOC 0x01
+#define MSR_INFRA 0x02
+#define MSR_AP 0x03
+#endif
+#define ENUART BIT7
+#define ENJTAG BIT3
+#define BTMODE (BIT2|BIT1)
+#define ENBT BIT0
+
+#define ENMBID BIT7
+#define BCNUM (BIT6|BIT5|BIT4)
+
+
+#define USTIME_EDCA 0xFF00
+#define USTIME_TSF 0x00FF
+
+#define SIFS_TRX 0xFF00
+#define SIFS_CTX 0x00FF
+
+#define ENSWBCN BIT15
+#define DRVERLY_TU 0x0FF0
+#define DRVERLY_US 0x000F
+#define BCN_TCFG_CW_SHIFT 8
+#define BCN_TCFG_IFS 0
+
+
+#define RRSR_RSC_OFFSET 21
+#define RRSR_SHORT_OFFSET 23
+#define RRSR_RSC_BW_40M 0x600000
+#define RRSR_RSC_UPSUBCHNL 0x400000
+#define RRSR_RSC_LOWSUBCHNL 0x200000
+#define RRSR_SHORT 0x800000
+#define RRSR_1M BIT0
+#define RRSR_2M BIT1
+#define RRSR_5_5M BIT2
+#define RRSR_11M BIT3
+#define RRSR_6M BIT4
+#define RRSR_9M BIT5
+#define RRSR_12M BIT6
+#define RRSR_18M BIT7
+#define RRSR_24M BIT8
+#define RRSR_36M BIT9
+#define RRSR_48M BIT10
+#define RRSR_54M BIT11
+#define RRSR_MCS0 BIT12
+#define RRSR_MCS1 BIT13
+#define RRSR_MCS2 BIT14
+#define RRSR_MCS3 BIT15
+#define RRSR_MCS4 BIT16
+#define RRSR_MCS5 BIT17
+#define RRSR_MCS6 BIT18
+#define RRSR_MCS7 BIT19
+#define BRSR_AckShortPmb BIT23
+
+#define RATR_1M 0x00000001
+#define RATR_2M 0x00000002
+#define RATR_55M 0x00000004
+#define RATR_11M 0x00000008
+#define RATR_6M 0x00000010
+#define RATR_9M 0x00000020
+#define RATR_12M 0x00000040
+#define RATR_18M 0x00000080
+#define RATR_24M 0x00000100
+#define RATR_36M 0x00000200
+#define RATR_48M 0x00000400
+#define RATR_54M 0x00000800
+#define RATR_MCS0 0x00001000
+#define RATR_MCS1 0x00002000
+#define RATR_MCS2 0x00004000
+#define RATR_MCS3 0x00008000
+#define RATR_MCS4 0x00010000
+#define RATR_MCS5 0x00020000
+#define RATR_MCS6 0x00040000
+#define RATR_MCS7 0x00080000
+#define RATR_MCS8 0x00100000
+#define RATR_MCS9 0x00200000
+#define RATR_MCS10 0x00400000
+#define RATR_MCS11 0x00800000
+#define RATR_MCS12 0x01000000
+#define RATR_MCS13 0x02000000
+#define RATR_MCS14 0x04000000
+#define RATR_MCS15 0x08000000
+#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
+#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
+ RATR_36M|RATR_48M|RATR_54M
+#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
+ RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
+#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\
+ RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
+
+#define AC_PARAM_TXOP_LIMIT_OFFSET 16
+#define AC_PARAM_ECW_MAX_OFFSET 12
+#define AC_PARAM_ECW_MIN_OFFSET 8
+#define AC_PARAM_AIFS_OFFSET 0
+
+#define AcmHw_HwEn BIT0
+#define AcmHw_BeqEn BIT1
+#define AcmHw_ViqEn BIT2
+#define AcmHw_VoqEn BIT3
+#define AcmHw_BeqStatus BIT4
+#define AcmHw_ViqStatus BIT5
+#define AcmHw_VoqStatus BIT6
+
+#define RETRY_LIMIT_SHORT_SHIFT 8
+#define RETRY_LIMIT_LONG_SHIFT 0
+
+#define NAV_UPPER_EN BIT16
+#define NAV_UPPER 0xFF00
+#define NAV_RTSRST 0xFF
+#define BW_OPMODE_20MHZ BIT2
+#define BW_OPMODE_5G BIT1
+#define BW_OPMODE_11J BIT0
+
+#define RXERR_RPT_RST BIT27 +#define RXERR_OFDM_PPDU 0
+#define RXERR_OFDM_FALSE_ALARM 1
+#define RXERR_OFDM_MPDU_OK 2
+#define RXERR_OFDM_MPDU_FAIL 3
+#define RXERR_CCK_PPDU 4
+#define RXERR_CCK_FALSE_ALARM 5
+#define RXERR_CCK_MPDU_OK 6
+#define RXERR_CCK_MPDU_FAIL 7
+#define RXERR_HT_PPDU 8
+#define RXERR_HT_FALSE_ALARM 9
+#define RXERR_HT_MPDU_TOTAL 10
+#define RXERR_HT_MPDU_OK 11
+#define RXERR_HT_MPDU_FAIL 12
+#define RXERR_RX_FULL_DROP 15
+
+
+#define CAM_CM_SecCAMPolling BIT31 +#define CAM_CM_SecCAMClr BIT30 +#define CAM_CM_SecCAMWE BIT16 +#define CAM_ADDR 0xFF +
+#define Dbg_CAM_TXSecCAMInfo BIT31 +#define Dbg_CAM_SecKeyFound BIT30 +
+
+#define SCR_TxUseDK BIT0 +#define SCR_RxUseDK BIT1 +#define SCR_TxEncEnable BIT2 +#define SCR_RxDecEnable BIT3 +#define SCR_SKByA2 BIT4 +#define SCR_NoSKMC BIT5 +#define CAM_VALID BIT15
+#define CAM_NOTVALID 0x0000
+#define CAM_USEDK BIT5
+
+#define CAM_NONE 0x0
+#define CAM_WEP40 0x01
+#define CAM_TKIP 0x02
+#define CAM_AES 0x04
+#define CAM_WEP104 0x05
+
+#define TOTAL_CAM_ENTRY 32
+#define HALF_CAM_ENTRY 16
+
+#define CAM_CONFIG_USEDK true
+#define CAM_CONFIG_NO_USEDK false
+
+#define CAM_WRITE BIT16
+#define CAM_READ 0x00000000
+#define CAM_POLLINIG BIT31
+
+#define SCR_UseDK 0x01
+#define SCR_TxSecEnable 0x02
+#define SCR_RxSecEnable 0x04
+
+#define WOW_PMEN BIT0 +#define WOW_WOMEN BIT1 +#define WOW_MAGIC BIT2 +#define WOW_UWF BIT3 +
+#define GPIOMUX_EN BIT3 +#define GPIOSEL_GPIO 0 +#define GPIOSEL_PHYDBG 1 +#define GPIOSEL_BT 2 +#define GPIOSEL_WLANDBG 3 +#define GPIOSEL_GPIO_MASK ~(BIT0|BIT1)
+
+#define HST_RDBUSY BIT0
+#define CPU_WTBUSY BIT1
+
+#define IMR8190_DISABLED 0x0
+#define IMR_CPUERR BIT5 +#define IMR_ATIMEND BIT4 +#define IMR_TBDOK BIT3 +#define IMR_TBDER BIT2 +#define IMR_BCNDMAINT8 BIT1 +#define IMR_BCNDMAINT7 BIT0 +#define IMR_BCNDMAINT6 BIT31 +#define IMR_BCNDMAINT5 BIT30 +#define IMR_BCNDMAINT4 BIT29 +#define IMR_BCNDMAINT3 BIT28 +#define IMR_BCNDMAINT2 BIT27 +#define IMR_BCNDMAINT1 BIT26 +#define IMR_BCNDOK8 BIT25 +#define IMR_BCNDOK7 BIT24 +#define IMR_BCNDOK6 BIT23 +#define IMR_BCNDOK5 BIT22 +#define IMR_BCNDOK4 BIT21 +#define IMR_BCNDOK3 BIT20 +#define IMR_BCNDOK2 BIT19 +#define IMR_BCNDOK1 BIT18 +#define IMR_TIMEOUT2 BIT17 +#define IMR_TIMEOUT1 BIT16 +#define IMR_TXFOVW BIT15 +#define IMR_PSTIMEOUT BIT14 +#define IMR_BcnInt BIT13 +#define IMR_RXFOVW BIT12 +#define IMR_RDU BIT11 +#define IMR_RXCMDOK BIT10 +#define IMR_BDOK BIT9 +#define IMR_HIGHDOK BIT8 +#define IMR_COMDOK BIT7 +#define IMR_MGNTDOK BIT6 +#define IMR_HCCADOK BIT5 +#define IMR_BKDOK BIT4 +#define IMR_BEDOK BIT3 +#define IMR_VIDOK BIT2 +#define IMR_VODOK BIT1 +#define IMR_ROK BIT0 +
+
+#define TPPoll_BKQ BIT0 +#define TPPoll_BEQ BIT1 +#define TPPoll_VIQ BIT2 +#define TPPoll_VOQ BIT3 +#define TPPoll_BQ BIT4 +#define TPPoll_CQ BIT5 +#define TPPoll_MQ BIT6 +#define TPPoll_HQ BIT7 +#define TPPoll_HCCAQ BIT8 +#define TPPoll_StopBK BIT9 +#define TPPoll_StopBE BIT10 +#define TPPoll_StopVI BIT11 +#define TPPoll_StopVO BIT12 +#define TPPoll_StopMgt BIT13 +#define TPPoll_StopHigh BIT14 +#define TPPoll_StopHCCA BIT15 +#define TPPoll_SHIFT 8 +
+#define MXDMA2_16bytes 0x000
+#define MXDMA2_32bytes 0x001
+#define MXDMA2_64bytes 0x010
+#define MXDMA2_128bytes 0x011
+#define MXDMA2_256bytes 0x100
+#define MXDMA2_512bytes 0x101
+#define MXDMA2_1024bytes 0x110
+#define MXDMA2_NoLimit 0x7
+
+#define MULRW_SHIFT 3
+#define MXDMA2_RX_SHIFT 4
+#define MXDMA2_TX_SHIFT 0
+
+#define CCX_CMD_CLM_ENABLE BIT0 +#define CCX_CMD_NHM_ENABLE BIT1 +#define CCX_CMD_FUNCTION_ENABLE BIT8
+#define CCX_CMD_IGNORE_CCA BIT9
+#define CCX_CMD_IGNORE_TXON BIT10
+#define CCX_CLM_RESULT_READY BIT16
+#define CCX_NHM_RESULT_READY BIT16
+#define CCX_CMD_RESET 0x0
+
+
+#define HWSET_MAX_SIZE_92S 128
+
+
+
+#ifdef RTL8192SE
+#define RTL8190_EEPROM_ID 0x8129 +#define EEPROM_HPON 0x02 +#define EEPROM_CLK 0x06 +#define EEPROM_TESTR 0x08 +
+#define EEPROM_VID 0x0A +#define EEPROM_DID 0x0C +#define EEPROM_SVID 0x0E +#define EEPROM_SMID 0x10 +
+#define EEPROM_MAC_ADDR 0x12 +#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 +
+#define EEPROM_PwDiff 0x54 +
+#define EEPROM_TxPowerBase 0x50 +#define EEPROM_TX_PWR_INDEX_RANGE 28 +
+#define EEPROM_TX_PWR_HT20_DIFF 0x62 +#define DEFAULT_HT20_TXPWR_DIFF 2 +#define EEPROM_TX_PWR_OFDM_DIFF 0x65 +
+#define EEPROM_TxPWRGroup 0x67 +#define EEPROM_Regulatory 0x6D +
+#define TX_PWR_SAFETY_CHK 0x6D +#define EEPROM_TxPwIndex_CCK_24G 0x5D +#define EEPROM_TxPwIndex_OFDM_24G 0x6B +#define EEPROM_HT2T_CH1_A 0x6c +#define EEPROM_HT2T_CH7_A 0x6d +#define EEPROM_HT2T_CH13_A 0x6e +#define EEPROM_HT2T_CH1_B 0x6f +#define EEPROM_HT2T_CH7_B 0x70 +#define EEPROM_HT2T_CH13_B 0x71 +#define EEPROM_TSSI_A 0x74 +#define EEPROM_TSSI_B 0x75 +#define EEPROM_RFInd_PowerDiff 0x76
+#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
+#define EEPROM_ThermalMeter 0x77 +#define EEPROM_BLUETOOTH_COEXIST 0x78 +#define EEPROM_BLUETOOTH_TYPE 0x4f +
+#define EEPROM_Optional 0x78 +#ifdef RTL8192S_WAPI_SUPPORT
+#define EEPROM_WAPI_SUPPORT 0x78
+#endif
+#define EEPROM_WoWLAN 0x78 +
+#define EEPROM_CrystalCap 0x79 +#define EEPROM_ChannelPlan 0x7B +#define EEPROM_Version 0x7C +#define EEPROM_CustomID 0x7A
+#define EEPROM_BoardType 0x7E
+
+#define EEPROM_Default_TSSI 0x0
+#define EEPROM_Default_TxPowerDiff 0x0
+#define EEPROM_Default_CrystalCap 0x5
+#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_TxPower 0x1010
+#define EEPROM_Default_HT2T_TxPwr 0x10
+
+#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
+#define EEPROM_Default_ThermalMeter 0x12
+#define EEPROM_Default_BlueToothCoexist 0x0
+#define EEPROM_Default_BlueToothAntNum 0x0
+#define EEPROM_Default_BlueToothAntIso 0x0
+#define EEPROM_Default_BlueToothType 0x0
+#define EEPROM_Default_AntTxPowerDiff 0x0
+#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
+#define EEPROM_Default_TxPowerLevel 0x22
+
+#define EEPROM_CHANNEL_PLAN_FCC 0x0
+#define EEPROM_CHANNEL_PLAN_IC 0x1
+#define EEPROM_CHANNEL_PLAN_ETSI 0x2
+#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
+#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
+#define EEPROM_CHANNEL_PLAN_MKK 0x5
+#define EEPROM_CHANNEL_PLAN_MKK1 0x6
+#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
+#define EEPROM_CHANNEL_PLAN_TELEC 0x8
+#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
+#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
+#define EEPROM_CHANNEL_PLAN_NCC 0xB
+#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
+
+
+#define EEPROM_CID_DEFAULT 0x0
+#define EEPROM_CID_TOSHIBA 0x4
+#define EEPROM_CID_CCX 0x10 +#define EEPROM_CID_QMI 0x0D
+#define EEPROM_CID_WHQL 0xFE +
+#else +#define RTL8190_EEPROM_ID 0x8129
+#define EEPROM_HPON 0x02 +#define EEPROM_VID 0x08 +#define EEPROM_PID 0x0A +#define EEPROM_USB_OPTIONAL 0x0C +#define EEPROM_USB_PHY_PARA1 0x0D +#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 +#define EEPROM_Version 0x50
+#define EEPROM_ChannelPlan 0x51 +#define EEPROM_CustomID 0x52
+#define EEPROM_SubCustomID 0x53 +
+#if (EEPROM_OLD_FORMAT_SUPPORT ==1)
+#define EEPROM_PwDiff 0x54 +#define EEPROM_ThermalMeter 0x55 +#define EEPROM_Reserved 0x56 +#define EEPROM_CrystalCap 0x57 +#define EEPROM_TxPowerBase 0x58 +#define EEPROM_TxPwIndex_CCK_24G 0x59 +#define EEPROM_TxPwIndex_OFDM_24G 0x67 +#define EEPROM_TSSI_A 0x75 +#define EEPROM_TSSI_B 0x76 +#define EEPROM_TxPwTkMode 0x77 +#define EEPROM_HT2T_CH1_A 0x78 +#define EEPROM_HT2T_CH7_A 0x79 +#define EEPROM_HT2T_CH13_A 0x7a +#define EEPROM_HT2T_CH1_B 0x7b +#define EEPROM_HT2T_CH7_B 0x7c +#define EEPROM_HT2T_CH13_B 0x7d +#define EEPROM_BoardType 0x7e +#else
+#define EEPROM_BoardType 0x54 +#define EEPROM_TxPwIndex 0x55 +#define EEPROM_PwDiff 0x67 +#define EEPROM_ThermalMeter 0x68 +#define EEPROM_CrystalCap 0x69 +#define EEPROM_TxPowerBase 0x6a +#define EEPROM_TSSI_A 0x6b +#define EEPROM_TSSI_B 0x6c +#define EEPROM_TxPwTkMode 0x6d +
+#define EEPROM_TX_PWR_HT20_DIFF 0x6e +#define DEFAULT_HT20_TXPWR_DIFF 2 +#define EEPROM_TX_PWR_OFDM_DIFF 0x71 +#define TX_PWR_SAFETY_CHK 0x79 +#endif
+#define EEPROM_USB_Default_OPTIONAL_FUNC 0x8
+#define EEPROM_USB_Default_PHY_PARAM 0x0
+#define EEPROM_Default_TSSI 0x0
+#define EEPROM_Default_TxPwrTkMode 0x0
+#define EEPROM_Default_TxPowerDiff 0x0
+#define EEPROM_Default_TxPowerBase 0x0
+#define EEPROM_Default_ThermalMeter 0x7
+#define EEPROM_Default_PwDiff 0x4
+#define EEPROM_Default_CrystalCap 0x5
+#define EEPROM_Default_TxPower 0x1010
+#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_HT2T_TxPwr 0x10
+#define EEPROM_USB_SN BIT0
+#define EEPROM_USB_REMOTE_WAKEUP BIT1
+#define EEPROM_USB_DEVICE_PWR BIT2
+#define EEPROM_EP_NUMBER (BIT3|BIT4)
+
+
+#define EEPROM_CHANNEL_PLAN_FCC 0x0
+#define EEPROM_CHANNEL_PLAN_IC 0x1
+#define EEPROM_CHANNEL_PLAN_ETSI 0x2
+#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
+#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
+#define EEPROM_CHANNEL_PLAN_MKK 0x5
+#define EEPROM_CHANNEL_PLAN_MKK1 0x6
+#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
+#define EEPROM_CHANNEL_PLAN_TELEC 0x8
+#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
+#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
+#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
+
+#define EEPROM_CID_DEFAULT 0x0
+#define EEPROM_CID_ALPHA 0x1
+#define EEPROM_CID_TOSHIBA 0x4
+#define EEPROM_CID_WHQL 0xFE +#endif
+
+
+#define FW_DIG_DISABLE 0xfd00cc00
+#define FW_DIG_ENABLE 0xfd000000
+#define FW_DIG_HALT 0xfd000001
+#define FW_DIG_RESUME 0xfd000002
+#define FW_HIGH_PWR_DISABLE 0xfd000008
+#define FW_HIGH_PWR_ENABLE 0xfd000009
+#define FW_ADD_A2_ENTRY 0xfd000016
+#define FW_TXPWR_TRACK_ENABLE 0xfd000017
+#define FW_TXPWR_TRACK_DISABLE 0xfd000018
+#define FW_TXPWR_TRACK_THERMAL 0xfd000019
+#define FW_TXANT_SWITCH_ENABLE 0xfd000023
+#define FW_TXANT_SWITCH_DISABLE 0xfd000024
+#define FW_RA_INIT 0xfd000026 +#define FW_CTRL_DM_BY_DRIVER 0Xfd00002a +#define FW_RA_IOT_BG_COMB 0xfd000030 +#define FW_RA_IOT_N_COMB 0xfd000031 +#define FW_RA_REFRESH 0xfd0000a0
+#define FW_RA_UPDATE_MASK 0xfd0000a2
+#define FW_RA_DISABLE 0xfd0000a4 +#define FW_RA_ACTIVE 0xfd0000a6
+#define FW_RA_DISABLE_RSSI_MASK 0xfd0000ac +#define FW_RA_ENABLE_RSSI_MASK 0xfd0000ad +#define FW_RA_RESET 0xfd0000af
+#define FW_DM_DISABLE 0xfd00aa00
+#define FW_IQK_ENABLE 0xf0000020
+#define FW_IQK_SUCCESS 0x0000dddd
+#define FW_IQK_FAIL 0x0000ffff
+#define FW_OP_FAILURE 0xffffffff
+#define FW_TX_FEEDBACK_NONE 0xfb000000 +#define FW_TX_FEEDBACK_DTM_ENABLE (FW_TX_FEEDBACK_NONE | 0x1) +#define FW_TX_FEEDBACK_CCX_ENABLE (FW_TX_FEEDBACK_NONE | 0x2) +#define FW_BB_RESET_ENABLE 0xff00000d
+#define FW_BB_RESET_DISABLE 0xff00000e
+#define FW_LPS_ENTER 0xfe000010
+#define FW_LPS_LEAVE 0xfe000011
+#define FW_INDIRECT_READ 0xf2000000
+#define FW_INDIRECT_WRITE 0xf2000001
+#define FW_CHAN_SET 0xf3000001 +
+
+
+
+
+
+
+#define RFPC 0x5F +#define RCR_9356SEL BIT6
+#define TCR_LRL_OFFSET 0
+#define TCR_SRL_OFFSET 8
+#define TCR_MXDMA_OFFSET 21
+#define TCR_SAT BIT24 +#define RCR_MXDMA_OFFSET 8
+#define RCR_FIFO_OFFSET 13
+#define RCR_OnlyErlPkt BIT31 +#define CWR 0xDC +#define RetryCTR 0xDE +
+
+#define LED1Cfg UnusedRegister +#define LED0Cfg UnusedRegister +#define GPI UnusedRegister +#define BRSR UnusedRegister +#define CPU_GEN UnusedRegister +#define SIFS UnusedRegister +
+#define CPU_GEN_SYSTEM_RESET 0x00000001
+
+
+
+
+#define CCX_COMMAND_REG 0x890
+#define CLM_PERIOD_REG 0x894
+#define NHM_PERIOD_REG 0x896
+#define NHM_THRESHOLD0 0x898 +#define NHM_THRESHOLD1 0x899 +#define NHM_THRESHOLD2 0x89A +#define NHM_THRESHOLD3 0x89B +#define NHM_THRESHOLD4 0x89C +#define NHM_THRESHOLD5 0x89D +#define NHM_THRESHOLD6 0x89E +#define CLM_RESULT_REG 0x8D0
+#define NHM_RESULT_REG 0x8D4
+#define NHM_RPI_COUNTER0 0x8D8
+#define NHM_RPI_COUNTER1 0x8D9
+#define NHM_RPI_COUNTER2 0x8DA
+#define NHM_RPI_COUNTER3 0x8DB
+#define NHM_RPI_COUNTER4 0x8DC
+#define NHM_RPI_COUNTER5 0x8DD
+#define NHM_RPI_COUNTER6 0x8DE
+#define NHM_RPI_COUNTER7 0x8DF
+
+
+#define HAL_8192S_HW_GPIO_OFF_BIT BIT3
+#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
+#define HAL_8192S_HW_GPIO_WPS_BIT BIT4
+
+#endif +
diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg.c b/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg.c new file mode 100644 index 000000000000..c7bab9992769 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg.c @@ -0,0 +1,6398 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+/*Created on 2009/11/17, 16:15*/
+
+#ifdef RTL8192SE
+#include "r8192S_hwimg.h"
+
+u8 Rtl8192SEFwImgArray[ImgArrayLength] = {
+0x92,0x81,0x4a,0x70,0x30,0x00,0x00,0x00,0x08,0xa4,0x00,0x00,0x88,0xb5,0x00,0x00,
+0x30,0x00,0x00,0x00,0x00,0xb4,0x00,0x00,0x4a,0x00,0x00,0x00,0x11,0x17,0x13,0x29,
+0x92,0x81,0x01,0x01,0x00,0x00,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x01,0x01,0x01,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x7f,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1f,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x25,0xb0,0x1a,0x3c,0x80,0x03,0x5a,0x37,0x00,0x80,0x1b,0x3c,0x80,0x00,0x7b,0x37,
+0x00,0x00,0x5b,0xaf,0x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x37,0x00,0x80,0x1b,0x3c,
+0x80,0x00,0x7b,0x37,0x00,0x00,0x5b,0xaf,0x01,0x80,0x1a,0x3c,0x10,0x9d,0x5a,0x27,
+0x08,0x00,0x40,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x04,0x00,0xa1,0xaf,0x08,0x00,0xa2,0xaf,0x0c,0x00,0xa3,0xaf,0x10,0x00,0xa4,0xaf,
+0x14,0x00,0xa5,0xaf,0x18,0x00,0xa6,0xaf,0x1c,0x00,0xa7,0xaf,0x20,0x00,0xa8,0xaf,
+0x24,0x00,0xa9,0xaf,0x28,0x00,0xaa,0xaf,0x2c,0x00,0xab,0xaf,0x30,0x00,0xac,0xaf,
+0x34,0x00,0xad,0xaf,0x38,0x00,0xae,0xaf,0x3c,0x00,0xaf,0xaf,0x12,0x40,0x00,0x00,
+0x10,0x48,0x00,0x00,0x00,0x70,0x0a,0x40,0x40,0x00,0xb0,0xaf,0x44,0x00,0xb1,0xaf,
+0x48,0x00,0xb2,0xaf,0x4c,0x00,0xb3,0xaf,0x50,0x00,0xb4,0xaf,0x54,0x00,0xb5,0xaf,
+0x58,0x00,0xb6,0xaf,0x5c,0x00,0xb7,0xaf,0x60,0x00,0xb8,0xaf,0x64,0x00,0xb9,0xaf,
+0x68,0x00,0xbc,0xaf,0x6c,0x00,0xbd,0xaf,0x70,0x00,0xbe,0xaf,0x74,0x00,0xbf,0xaf,
+0x78,0x00,0xa8,0xaf,0x7c,0x00,0xa9,0xaf,0x80,0x00,0xaa,0xaf,0xda,0x26,0x00,0x08,
+0x21,0x20,0xa0,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xff,0xff,0x88,0x30,0x80,0x28,0x08,0x00,0x2a,0xb0,0x0a,0x3c,0x21,0x38,0xaa,0x00,
+0x0c,0x00,0xe6,0x8c,0x02,0x80,0x03,0x3c,0xcc,0x3f,0x63,0x24,0x25,0xb0,0x02,0x3c,
+0xb0,0x03,0x42,0x34,0x21,0x28,0xa3,0x00,0xff,0x00,0xc4,0x30,0xff,0x00,0x09,0x24,
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+0x5b,0x00,0xc0,0x16,0x56,0x00,0x80,0x15,0x51,0x00,0x40,0x14,0x4c,0x00,0x00,0x13,
+0x48,0x00,0x00,0x12,0x44,0x00,0x00,0x11,0x40,0x00,0x00,0x10,0x36,0x35,0x2e,0x25,
+0x1c,0x12,0x09,0x04,0x33,0x32,0x2b,0x23,0x1a,0x11,0x08,0x04,0x30,0x2f,0x29,0x21,
+0x19,0x10,0x08,0x03,0x2d,0x2d,0x27,0x1f,0x18,0x0f,0x08,0x03,0x2b,0x2a,0x25,0x1e,
+0x16,0x0e,0x07,0x03,0x28,0x28,0x22,0x1c,0x15,0x0d,0x07,0x03,0x26,0x25,0x21,0x1b,
+0x14,0x0d,0x06,0x03,0x24,0x23,0x1f,0x19,0x13,0x0c,0x06,0x03,0x22,0x21,0x1d,0x18,
+0x11,0x0b,0x06,0x02,0x20,0x20,0x1b,0x16,0x11,0x08,0x05,0x02,0x1f,0x1e,0x1a,0x15,
+0x10,0x0a,0x05,0x02,0x1d,0x1c,0x18,0x14,0x0f,0x0a,0x05,0x02,0x1b,0x1a,0x17,0x13,
+0x0e,0x09,0x04,0x02,0x1a,0x19,0x16,0x12,0x0d,0x09,0x04,0x02,0x18,0x17,0x15,0x11,
+0x0c,0x08,0x04,0x02,0x17,0x16,0x13,0x10,0x0c,0x08,0x04,0x02,0x16,0x15,0x12,0x0f,
+0x0b,0x07,0x04,0x01,0x14,0x14,0x11,0x0e,0x0b,0x07,0x03,0x02,0x13,0x13,0x10,0x0d,
+0x0a,0x06,0x03,0x01,0x12,0x12,0x0f,0x0c,0x09,0x06,0x03,0x01,0x11,0x11,0x0f,0x0c,
+0x09,0x06,0x03,0x01,0x10,0x10,0x0e,0x0b,0x08,0x05,0x03,0x01,0x0f,0x0f,0x0d,0x0b,
+0x08,0x05,0x03,0x01,0x0e,0x0e,0x0c,0x0a,0x08,0x05,0x02,0x01,0x0d,0x0d,0x0c,0x0a,
+0x07,0x05,0x02,0x01,0x0d,0x0c,0x0b,0x09,0x07,0x04,0x02,0x01,0x0c,0x0c,0x0a,0x09,
+0x06,0x04,0x02,0x01,0x0b,0x0b,0x0a,0x08,0x06,0x04,0x02,0x01,0x0b,0x0a,0x09,0x08,
+0x06,0x04,0x02,0x01,0x0a,0x0a,0x09,0x07,0x05,0x03,0x02,0x01,0x0a,0x09,0x08,0x07,
+0x05,0x03,0x02,0x01,0x09,0x09,0x08,0x06,0x05,0x03,0x01,0x01,0x09,0x08,0x07,0x06,
+0x04,0x03,0x01,0x01,0x36,0x35,0x2e,0x1b,0x00,0x00,0x00,0x00,0x33,0x32,0x2b,0x19,
+0x00,0x00,0x00,0x00,0x30,0x2f,0x29,0x18,0x00,0x00,0x00,0x00,0x2d,0x2d,0x17,0x17,
+0x00,0x00,0x00,0x00,0x2b,0x2a,0x25,0x15,0x00,0x00,0x00,0x00,0x28,0x28,0x24,0x14,
+0x00,0x00,0x00,0x00,0x26,0x25,0x21,0x13,0x00,0x00,0x00,0x00,0x24,0x23,0x1f,0x12,
+0x00,0x00,0x00,0x00,0x22,0x21,0x1d,0x11,0x00,0x00,0x00,0x00,0x20,0x20,0x1b,0x10,
+0x00,0x00,0x00,0x00,0x1f,0x1e,0x1a,0x0f,0x00,0x00,0x00,0x00,0x1d,0x1c,0x18,0x0e,
+0x00,0x00,0x00,0x00,0x1b,0x1a,0x17,0x0e,0x00,0x00,0x00,0x00,0x1a,0x19,0x16,0x0d,
+0x00,0x00,0x00,0x00,0x18,0x17,0x15,0x0c,0x00,0x00,0x00,0x00,0x17,0x16,0x13,0x0b,
+0x00,0x00,0x00,0x00,0x16,0x15,0x12,0x0b,0x00,0x00,0x00,0x00,0x14,0x14,0x11,0x0a,
+0x00,0x00,0x00,0x00,0x13,0x13,0x10,0x0a,0x00,0x00,0x00,0x00,0x12,0x12,0x0f,0x09,
+0x00,0x00,0x00,0x00,0x11,0x11,0x0f,0x09,0x00,0x00,0x00,0x00,0x10,0x10,0x0e,0x08,
+0x00,0x00,0x00,0x00,0x0f,0x0f,0x0d,0x08,0x00,0x00,0x00,0x00,0x0e,0x0e,0x0c,0x07,
+0x00,0x00,0x00,0x00,0x0d,0x0d,0x0c,0x07,0x00,0x00,0x00,0x00,0x0d,0x0c,0x0b,0x06,
+0x00,0x00,0x00,0x00,0x0c,0x0c,0x0a,0x06,0x00,0x00,0x00,0x00,0x0b,0x0b,0x0a,0x06,
+0x00,0x00,0x00,0x00,0x0b,0x0a,0x09,0x05,0x00,0x00,0x00,0x00,0x0a,0x0a,0x09,0x05,
+0x00,0x00,0x00,0x00,0x0a,0x09,0x08,0x05,0x00,0x00,0x00,0x00,0x09,0x09,0x08,0x05,
+0x00,0x00,0x00,0x00,0x09,0x08,0x07,0x04,0x00,0x00,0x00,0x00,0x06,0x00,0x2a,0xb0,
+0x05,0x00,0x2a,0xb0,0x34,0x7b,0x00,0x80,0xbc,0x7b,0x00,0x80,0x60,0x7b,0x00,0x80,
+0xbc,0x7b,0x00,0x80,0xbc,0x7b,0x00,0x80,0xbc,0x7b,0x00,0x80,0xbc,0x7b,0x00,0x80,
+0x08,0x7b,0x00,0x80,0x00,0x01,0x02,0x02,0x03,0x03,0x03,0x03,0x04,0x04,0x04,0x04,
+0x04,0x04,0x04,0x04,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,
+0x05,0x05,0x05,0x05,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,
+0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,
+0x06,0x06,0x06,0x06,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,
+0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,
+0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,
+0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,
+0x07,0x07,0x07,0x07,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x28,0x28,0x28,0x28,0x28,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0xa0,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
+0x04,0x04,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x41,0x41,0x41,0x41,0x41,0x41,0x01,
+0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+0x01,0x01,0x01,0x10,0x10,0x10,0x10,0x10,0x10,0x42,0x42,0x42,0x42,0x42,0x42,0x02,
+0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,
+0x02,0x02,0x02,0x10,0x10,0x10,0x10,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x10,
+0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,
+0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x10,
+0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x00,0x36,0xc2,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x45,0xc4,0xf0,0x00,0x45,0xc4,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x45,0xb5,0x60,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x02,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0xc7,0x00,0xb8,0xff,0xff,0xff,0xff,
+};
+
+u8 Rtl8192SEFwMainArray[MainArrayLength] = {
+0x0, };
+
+u8 Rtl8192SEFwDataArray[DataArrayLength] = {
+0x0, };
+
+u32 Rtl8192SEPHY_REG_2T2RArray[PHY_REG_2T2RArrayLength] = {
+0x01c,0x07000000,
+0x800,0x00040000,
+0x804,0x00008003,
+0x808,0x0000fc00,
+0x80c,0x0000000a,
+0x810,0x10005088,
+0x814,0x020c3d10,
+0x818,0x00200185,
+0x81c,0x00000000,
+0x820,0x01000000,
+0x824,0x00390004,
+0x828,0x01000000,
+0x82c,0x00390004,
+0x830,0x00000004,
+0x834,0x00690200,
+0x838,0x00000004,
+0x83c,0x00690200,
+0x840,0x00010000,
+0x844,0x00010000,
+0x848,0x00000000,
+0x84c,0x00000000,
+0x850,0x00000000,
+0x854,0x00000000,
+0x858,0x48484848,
+0x85c,0x65a965a9,
+0x860,0x0f7f0130,
+0x864,0x0f7f0130,
+0x868,0x0f7f0130,
+0x86c,0x0f7f0130,
+0x870,0x03000700,
+0x874,0x03000300,
+0x878,0x00020002,
+0x87c,0x004f0201,
+0x880,0xa8300ac1,
+0x884,0x00000058,
+0x888,0x00000008,
+0x88c,0x00000004,
+0x890,0x00000000,
+0x894,0xfffffffe,
+0x898,0x40302010,
+0x89c,0x00706050,
+0x8b0,0x00000000,
+0x8e0,0x00000000,
+0x8e4,0x00000000,
+0xe00,0x30333333,
+0xe04,0x2a2d2e2f,
+0xe08,0x00003232,
+0xe10,0x30333333,
+0xe14,0x2a2d2e2f,
+0xe18,0x30333333,
+0xe1c,0x2a2d2e2f,
+0xe30,0x01007c00,
+0xe34,0x01004800,
+0xe38,0x1000dc1f,
+0xe3c,0x10008c1f,
+0xe40,0x021400a0,
+0xe44,0x281600a0,
+0xe48,0xf8000001,
+0xe4c,0x00002910,
+0xe50,0x01007c00,
+0xe54,0x01004800,
+0xe58,0x1000dc1f,
+0xe5c,0x10008c1f,
+0xe60,0x021400a0,
+0xe64,0x281600a0,
+0xe6c,0x00002910,
+0xe70,0x31ed92fb,
+0xe74,0x361536fb,
+0xe78,0x361536fb,
+0xe7c,0x361536fb,
+0xe80,0x361536fb,
+0xe84,0x000d92fb,
+0xe88,0x000d92fb,
+0xe8c,0x31ed92fb,
+0xed0,0x31ed92fb,
+0xed4,0x31ed92fb,
+0xed8,0x000d92fb,
+0xedc,0x000d92fb,
+0xee0,0x000d92fb,
+0xee4,0x015e5448,
+0xee8,0x21555448,
+0x900,0x00000000,
+0x904,0x00000023,
+0x908,0x00000000,
+0x90c,0x01121313,
+0xa00,0x00d047c8,
+0xa04,0x80ff0008,
+0xa08,0x88cd8300,
+0xa0c,0x2e62120f,
+0xa10,0x9500bb78,
+0xa14,0x11144028,
+0xa18,0x00881117,
+0xa1c,0x89140f00,
+0xa20,0x1a1b0000,
+0xa24,0x090e1317,
+0xa28,0x00000204,
+0xa2c,0x10d30000,
+0xc00,0x40071d40,
+0xc04,0x00a05633,
+0xc08,0x000000e4,
+0xc0c,0x6c6c6c6c,
+0xc10,0x08800000,
+0xc14,0x40000100,
+0xc18,0x08000000,
+0xc1c,0x40000100,
+0xc20,0x08000000,
+0xc24,0x40000100,
+0xc28,0x08000000,
+0xc2c,0x40000100,
+0xc30,0x6de9ac44,
+0xc34,0x469652cf,
+0xc38,0x49795994,
+0xc3c,0x0a979764,
+0xc40,0x1f7c403f,
+0xc44,0x000100b7,
+0xc48,0xec020000,
+0xc4c,0x007f037f,
+0xc50,0x69543420,
+0xc54,0x433c0094,
+0xc58,0x69543420,
+0xc5c,0x433c0094,
+0xc60,0x69543420,
+0xc64,0x433c0094,
+0xc68,0x69543420,
+0xc6c,0x433c0094,
+0xc70,0x2c7f000d,
+0xc74,0x0186175b,
+0xc78,0x0000001f,
+0xc7c,0x00b91612,
+0xc80,0x40000100,
+0xc84,0x20f60000,
+0xc88,0x20000080,
+0xc8c,0x20200000,
+0xc90,0x40000100,
+0xc94,0x00000000,
+0xc98,0x40000100,
+0xc9c,0x00000000,
+0xca0,0x00492492,
+0xca4,0x00000000,
+0xca8,0x00000000,
+0xcac,0x00000000,
+0xcb0,0x00000000,
+0xcb4,0x00000000,
+0xcb8,0x00000000,
+0xcbc,0x28000000,
+0xcc0,0x00000000,
+0xcc4,0x00000000,
+0xcc8,0x00000000,
+0xccc,0x00000000,
+0xcd0,0x00000000,
+0xcd4,0x00000000,
+0xcd8,0x64b22427,
+0xcdc,0x00766932,
+0xce0,0x00222222,
+0xce4,0x00000000,
+0xce8,0x37644302,
+0xcec,0x2f97d40c,
+0xd00,0x00000750,
+0xd04,0x00000403,
+0xd08,0x0000907f,
+0xd0c,0x00000001,
+0xd10,0xa0633333,
+0xd14,0x33333c63,
+0xd18,0x6a8f5b6b,
+0xd1c,0x00000000,
+0xd20,0x00000000,
+0xd24,0x00000000,
+0xd28,0x00000000,
+0xd2c,0xcc979975,
+0xd30,0x00000000,
+0xd34,0x00000000,
+0xd38,0x00000000,
+0xd3c,0x00027293,
+0xd40,0x00000000,
+0xd44,0x00000000,
+0xd48,0x00000000,
+0xd50,0x6437140a,
+0xd54,0x024dbd02,
+0xd58,0x00000000,
+0xd5c,0x30032064,
+0xd60,0x4653de68,
+0xd64,0x00518a3c,
+0xd68,0x00002101,
+0xf14,0x00000003,
+0xf4c,0x00000000,
+0xf00,0x00000300,
+};
+
+u32 Rtl8192SEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
+0x0, };
+
+u32 Rtl8192SEPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength] = {
+0x844,0xffffffff,0x00010000,
+0x804,0x0000000f,0x00000001,
+0x824,0x00f0000f,0x00300004,
+0x82c,0x00f0000f,0x00100002,
+0x870,0x04000000,0x00000001,
+0x864,0x00000400,0x00000000,
+0x878,0x000f000f,0x00000002,
+0xe74,0x0f000000,0x00000002,
+0xe78,0x0f000000,0x00000002,
+0xe7c,0x0f000000,0x00000002,
+0xe80,0x0f000000,0x00000002,
+0x90c,0x000000ff,0x00000011,
+0xc04,0x000000ff,0x00000011,
+0xd04,0x0000000f,0x00000001,
+0x1f4,0xffff0000,0x00007777,
+0x234,0xf8000000,0x0000000a,
+};
+
+u32 Rtl8192SEPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength] = {
+0x804,0x0000000f,0x00000003,
+0x824,0x00f0000f,0x00300004,
+0x82c,0x00f0000f,0x00300002,
+0x870,0x04000000,0x00000001,
+0x864,0x00000400,0x00000000,
+0x878,0x000f000f,0x00000002,
+0xe74,0x0f000000,0x00000002,
+0xe78,0x0f000000,0x00000002,
+0xe7c,0x0f000000,0x00000002,
+0xe80,0x0f000000,0x00000002,
+0x90c,0x000000ff,0x00000011,
+0xc04,0x000000ff,0x00000033,
+0xd04,0x0000000f,0x00000003,
+0x1f4,0xffff0000,0x00007777,
+0x234,0xf8000000,0x0000000a,
+};
+
+u32 Rtl8192SEPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength] = {
+0x804,0x0000000f,0x00000003,
+0x824,0x00f0000f,0x00300004,
+0x82c,0x00f0000f,0x00300004,
+0x870,0x04000000,0x00000001,
+0x864,0x00000400,0x00000001,
+0x878,0x000f000f,0x00020002,
+0xe74,0x0f000000,0x00000006,
+0xe78,0x0f000000,0x00000006,
+0xe7c,0x0f000000,0x00000006,
+0xe80,0x0f000000,0x00000006,
+0x90c,0x000000ff,0x00000033,
+0xc04,0x000000ff,0x00000033,
+0xd04,0x0000000f,0x00000003,
+0x1f4,0xffff0000,0x0000ffff,
+0x234,0xf8000000,0x00000013,
+};
+
+u32 Rtl8192SEPHY_REG_Array_PG[PHY_REG_Array_PGLength] = {
+0xe00,0xffffffff,0x06090909,
+0xe04,0xffffffff,0x00030406,
+0xe08,0x0000ff00,0x00000000,
+0xe10,0xffffffff,0x0a0c0d0e,
+0xe14,0xffffffff,0x03040508,
+0xe18,0xffffffff,0x0a0c0d0e,
+0xe1c,0xffffffff,0x03040508,
+0xe00,0xffffffff,0x04040404,
+0xe04,0xffffffff,0x00020204,
+0xe08,0x0000ff00,0x00000000,
+0xe10,0xffffffff,0x02040404,
+0xe14,0xffffffff,0x00000002,
+0xe18,0xffffffff,0x02040404,
+0xe1c,0xffffffff,0x00000002,
+0xe00,0xffffffff,0x04040404,
+0xe04,0xffffffff,0x00020204,
+0xe08,0x0000ff00,0x00000000,
+0xe10,0xffffffff,0x02040404,
+0xe14,0xffffffff,0x00000002,
+0xe18,0xffffffff,0x02040404,
+0xe1c,0xffffffff,0x00000002,
+0xe00,0xffffffff,0x02020202,
+0xe04,0xffffffff,0x00020202,
+0xe08,0x0000ff00,0x00000000,
+0xe10,0xffffffff,0x02020202,
+0xe14,0xffffffff,0x00000002,
+0xe18,0xffffffff,0x02020202,
+0xe1c,0xffffffff,0x00000002,
+};
+
+u32 Rtl8192SERadioA_1T_Array[RadioA_1T_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00030250,
+0x002,0x00010000,
+0x010,0x0008000f,
+0x011,0x000231fc,
+0x010,0x000c000f,
+0x011,0x0003f9f8,
+0x010,0x0002000f,
+0x011,0x00020101,
+0x014,0x0001093e,
+0x014,0x0009093e,
+0x015,0x0000f8f4,
+0x017,0x000f6500,
+0x01a,0x00013056,
+0x01b,0x00060000,
+0x01c,0x00000300,
+0x01e,0x00031059,
+0x021,0x00054000,
+0x022,0x0000083c,
+0x023,0x00001558,
+0x024,0x00000060,
+0x025,0x00022583,
+0x026,0x0000f200,
+0x027,0x000eacf1,
+0x028,0x0009bd54,
+0x029,0x00004582,
+0x02a,0x00000001,
+0x02b,0x00021334,
+0x02a,0x00000000,
+0x02b,0x0000000a,
+0x02a,0x00000001,
+0x02b,0x00000808,
+0x02b,0x00053333,
+0x02c,0x0000000c,
+0x02a,0x00000002,
+0x02b,0x00000808,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000003,
+0x02b,0x00000808,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000004,
+0x02b,0x00000808,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000005,
+0x02b,0x00000709,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x00000006,
+0x02b,0x00000709,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000007,
+0x02b,0x00000709,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000008,
+0x02b,0x00000709,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000009,
+0x02b,0x0000060a,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000a,
+0x02b,0x0000060a,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x0000000b,
+0x02b,0x0000060a,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x0000000c,
+0x02b,0x0000060a,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x0000000d,
+0x02b,0x0000050b,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000e,
+0x02b,0x0000050b,
+0x02b,0x00066623,
+0x02c,0x0000001a,
+0x02a,0x000e4000,
+0x030,0x00020000,
+0x031,0x000b9631,
+0x032,0x0000130d,
+0x033,0x00000187,
+0x013,0x00019e6c,
+0x013,0x00015e94,
+0x000,0x00010159,
+0x018,0x0000f401,
+0x0fe,0x00000000,
+0x01e,0x0003105b,
+0x0fe,0x00000000,
+0x000,0x00030159,
+0x010,0x0004000f,
+0x011,0x000203f9,
+};
+
+u32 Rtl8192SERadioB_Array[RadioB_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00001041,
+0x002,0x00011000,
+0x005,0x00080fc0,
+0x007,0x000fc803,
+0x013,0x00017cb0,
+0x013,0x00011cc0,
+0x013,0x0000dc60,
+0x013,0x00008c60,
+0x013,0x00004450,
+0x013,0x00000020,
+};
+
+u32 Rtl8192SERadioA_to1T_Array[RadioA_to1T_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00030250,
+0x002,0x00010000,
+0x010,0x0008000f,
+0x011,0x000231fc,
+0x010,0x000c000f,
+0x011,0x0003f9f8,
+0x014,0x0001093e,
+0x014,0x0009093e,
+0x015,0x000198f4,
+0x017,0x000f6500,
+0x01a,0x00013056,
+0x01b,0x00060000,
+0x01c,0x00000300,
+0x01e,0x00031059,
+0x021,0x00054000,
+0x022,0x0000083c,
+0x023,0x00001558,
+0x024,0x00000060,
+0x025,0x00022583,
+0x026,0x0000f200,
+0x027,0x000eacf1,
+0x028,0x000dbd54,
+0x029,0x00004582,
+0x02a,0x00000001,
+0x02b,0x00021334,
+0x02a,0x00000000,
+0x02b,0x0000000a,
+0x02a,0x00000001,
+0x02b,0x00000808,
+0x02b,0x00053333,
+0x02c,0x0000000c,
+0x02a,0x00000002,
+0x02b,0x00000808,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000003,
+0x02b,0x00000808,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000004,
+0x02b,0x00000808,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000005,
+0x02b,0x00000709,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x00000006,
+0x02b,0x00000709,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000007,
+0x02b,0x00000709,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000008,
+0x02b,0x00000709,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000009,
+0x02b,0x0000060a,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000a,
+0x02b,0x0000060a,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x0000000b,
+0x02b,0x0000060a,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x0000000c,
+0x02b,0x0000060a,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x0000000d,
+0x02b,0x0000050b,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000e,
+0x02b,0x0000050b,
+0x02b,0x00066623,
+0x02c,0x0000001a,
+0x02a,0x000e4000,
+0x030,0x00020000,
+0x031,0x000b9631,
+0x033,0x00000187,
+0x013,0x00019e6c,
+0x013,0x00015e94,
+0x000,0x00010159,
+0x018,0x0000f401,
+0x0fe,0x00000000,
+0x01e,0x0003105b,
+0x0fe,0x00000000,
+0x000,0x00030159,
+0x010,0x0004000f,
+0x011,0x000203f9,
+};
+
+u32 Rtl8192SERadioA_to2T_Array[RadioA_to2T_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00030250,
+0x002,0x00010000,
+0x010,0x0008000f,
+0x011,0x000231fc,
+0x010,0x000c000f,
+0x011,0x0003f9f8,
+0x014,0x0001093e,
+0x014,0x0009093e,
+0x015,0x000198f4,
+0x017,0x000f6500,
+0x01a,0x00013056,
+0x01b,0x00060000,
+0x01c,0x00000300,
+0x01e,0x00031059,
+0x021,0x00054000,
+0x022,0x0000083c,
+0x023,0x00001558,
+0x024,0x00000060,
+0x025,0x00022583,
+0x026,0x0000f200,
+0x027,0x000eacf1,
+0x028,0x000dbd54,
+0x029,0x00004582,
+0x02a,0x00000001,
+0x02b,0x00021334,
+0x02a,0x00000000,
+0x02b,0x0000000a,
+0x02a,0x00000001,
+0x02b,0x00000808,
+0x02b,0x00053333,
+0x02c,0x0000000c,
+0x02a,0x00000002,
+0x02b,0x00000808,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000003,
+0x02b,0x00000808,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000004,
+0x02b,0x00000808,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000005,
+0x02b,0x00000709,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x00000006,
+0x02b,0x00000709,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000007,
+0x02b,0x00000709,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000008,
+0x02b,0x00000709,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000009,
+0x02b,0x0000060a,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000a,
+0x02b,0x0000060a,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x0000000b,
+0x02b,0x0000060a,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x0000000c,
+0x02b,0x0000060a,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x0000000d,
+0x02b,0x0000050b,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000e,
+0x02b,0x0000050b,
+0x02b,0x00066623,
+0x02c,0x0000001a,
+0x02a,0x000e4000,
+0x030,0x00020000,
+0x031,0x000b9631,
+0x033,0x00000187,
+0x013,0x00019e6c,
+0x013,0x00015e94,
+0x000,0x00010159,
+0x018,0x0000f401,
+0x0fe,0x00000000,
+0x01e,0x0003105b,
+0x0fe,0x00000000,
+0x000,0x00030159,
+0x010,0x0004000f,
+0x011,0x000203f9,
+};
+
+u32 Rtl8192SERadioB_GM_Array[RadioB_GM_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00001041,
+0x002,0x00011000,
+0x005,0x00080fc0,
+0x007,0x000fc803,
+};
+
+u32 Rtl8192SEMAC_2T_Array[MAC_2T_ArrayLength] = {
+0x020,0x00000035,
+0x048,0x0000000e,
+0x049,0x000000f0,
+0x04a,0x00000077,
+0x04b,0x00000083,
+0x0b5,0x00000021,
+0x0dc,0x000000ff,
+0x0dd,0x000000ff,
+0x0de,0x000000ff,
+0x0df,0x000000ff,
+0x116,0x00000000,
+0x117,0x00000000,
+0x118,0x00000000,
+0x119,0x00000000,
+0x11a,0x00000000,
+0x11b,0x00000000,
+0x11c,0x00000000,
+0x11d,0x00000000,
+0x160,0x0000000b,
+0x161,0x0000000b,
+0x162,0x0000000b,
+0x163,0x0000000b,
+0x164,0x0000000b,
+0x165,0x0000000b,
+0x166,0x0000000b,
+0x167,0x0000000b,
+0x168,0x0000000b,
+0x169,0x0000000b,
+0x16a,0x0000000b,
+0x16b,0x0000000b,
+0x16c,0x0000000b,
+0x16d,0x0000000b,
+0x16e,0x0000000b,
+0x16f,0x0000000b,
+0x170,0x0000000b,
+0x171,0x0000000b,
+0x172,0x0000000b,
+0x173,0x0000000b,
+0x174,0x0000000b,
+0x175,0x0000000b,
+0x176,0x0000000b,
+0x177,0x0000000b,
+0x178,0x0000000b,
+0x179,0x0000000b,
+0x17a,0x0000000b,
+0x17b,0x0000000b,
+0x17c,0x0000000b,
+0x17d,0x0000000b,
+0x17e,0x0000000b,
+0x17f,0x0000000b,
+0x236,0x0000000c,
+0x503,0x00000022,
+0x560,0x00000000,
+};
+
+u32 Rtl8192SEMACPHY_Array_PG[MACPHY_Array_PGLength] = {
+0x0, };
+
+u32 Rtl8192SEAGCTAB_Array[AGCTAB_ArrayLength] = {
+0xc78,0x7f000001,
+0xc78,0x7f010001,
+0xc78,0x7e020001,
+0xc78,0x7d030001,
+0xc78,0x7c040001,
+0xc78,0x7b050001,
+0xc78,0x7a060001,
+0xc78,0x79070001,
+0xc78,0x78080001,
+0xc78,0x77090001,
+0xc78,0x760a0001,
+0xc78,0x750b0001,
+0xc78,0x740c0001,
+0xc78,0x730d0001,
+0xc78,0x720e0001,
+0xc78,0x710f0001,
+0xc78,0x70100001,
+0xc78,0x6f110001,
+0xc78,0x6f120001,
+0xc78,0x6e130001,
+0xc78,0x6d140001,
+0xc78,0x6d150001,
+0xc78,0x6c160001,
+0xc78,0x6b170001,
+0xc78,0x6a180001,
+0xc78,0x6a190001,
+0xc78,0x691a0001,
+0xc78,0x681b0001,
+0xc78,0x671c0001,
+0xc78,0x661d0001,
+0xc78,0x651e0001,
+0xc78,0x641f0001,
+0xc78,0x63200001,
+0xc78,0x4c210001,
+0xc78,0x4b220001,
+0xc78,0x4a230001,
+0xc78,0x49240001,
+0xc78,0x48250001,
+0xc78,0x47260001,
+0xc78,0x46270001,
+0xc78,0x45280001,
+0xc78,0x44290001,
+0xc78,0x2c2a0001,
+0xc78,0x2b2b0001,
+0xc78,0x2a2c0001,
+0xc78,0x292d0001,
+0xc78,0x282e0001,
+0xc78,0x272f0001,
+0xc78,0x26300001,
+0xc78,0x25310001,
+0xc78,0x24320001,
+0xc78,0x23330001,
+0xc78,0x22340001,
+0xc78,0x09350001,
+0xc78,0x08360001,
+0xc78,0x07370001,
+0xc78,0x06380001,
+0xc78,0x05390001,
+0xc78,0x043a0001,
+0xc78,0x033b0001,
+0xc78,0x023c0001,
+0xc78,0x013d0001,
+0xc78,0x003e0001,
+0xc78,0x003f0001,
+0xc78,0x7f400001,
+0xc78,0x7f410001,
+0xc78,0x7e420001,
+0xc78,0x7d430001,
+0xc78,0x7c440001,
+0xc78,0x7b450001,
+0xc78,0x7a460001,
+0xc78,0x79470001,
+0xc78,0x78480001,
+0xc78,0x77490001,
+0xc78,0x764a0001,
+0xc78,0x754b0001,
+0xc78,0x744c0001,
+0xc78,0x734d0001,
+0xc78,0x724e0001,
+0xc78,0x714f0001,
+0xc78,0x70500001,
+0xc78,0x6f510001,
+0xc78,0x6f520001,
+0xc78,0x6e530001,
+0xc78,0x6d540001,
+0xc78,0x6d550001,
+0xc78,0x6c560001,
+0xc78,0x6b570001,
+0xc78,0x6a580001,
+0xc78,0x6a590001,
+0xc78,0x695a0001,
+0xc78,0x685b0001,
+0xc78,0x675c0001,
+0xc78,0x665d0001,
+0xc78,0x655e0001,
+0xc78,0x645f0001,
+0xc78,0x63600001,
+0xc78,0x4c610001,
+0xc78,0x4b620001,
+0xc78,0x4a630001,
+0xc78,0x49640001,
+0xc78,0x48650001,
+0xc78,0x47660001,
+0xc78,0x46670001,
+0xc78,0x45680001,
+0xc78,0x44690001,
+0xc78,0x2c6a0001,
+0xc78,0x2b6b0001,
+0xc78,0x2a6c0001,
+0xc78,0x296d0001,
+0xc78,0x286e0001,
+0xc78,0x276f0001,
+0xc78,0x26700001,
+0xc78,0x25710001,
+0xc78,0x24720001,
+0xc78,0x23730001,
+0xc78,0x22740001,
+0xc78,0x09750001,
+0xc78,0x08760001,
+0xc78,0x07770001,
+0xc78,0x06780001,
+0xc78,0x05790001,
+0xc78,0x047a0001,
+0xc78,0x037b0001,
+0xc78,0x027c0001,
+0xc78,0x017d0001,
+0xc78,0x007e0001,
+0xc78,0x007f0001,
+0xc78,0x3000001e,
+0xc78,0x3001001e,
+0xc78,0x3002001e,
+0xc78,0x3003001e,
+0xc78,0x3004001e,
+0xc78,0x3405001e,
+0xc78,0x3806001e,
+0xc78,0x3e07001e,
+0xc78,0x3e08001e,
+0xc78,0x4409001e,
+0xc78,0x460a001e,
+0xc78,0x480b001e,
+0xc78,0x480c001e,
+0xc78,0x4e0d001e,
+0xc78,0x560e001e,
+0xc78,0x5a0f001e,
+0xc78,0x5e10001e,
+0xc78,0x6211001e,
+0xc78,0x6c12001e,
+0xc78,0x7213001e,
+0xc78,0x7214001e,
+0xc78,0x7215001e,
+0xc78,0x7216001e,
+0xc78,0x7217001e,
+0xc78,0x7218001e,
+0xc78,0x7219001e,
+0xc78,0x721a001e,
+0xc78,0x721b001e,
+0xc78,0x721c001e,
+0xc78,0x721d001e,
+0xc78,0x721e001e,
+0xc78,0x721f001e,
+};
+
+#endif
diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg.h b/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg.h new file mode 100644 index 000000000000..fef006c15213 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg.h @@ -0,0 +1,60 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#ifndef __INC_HAL8192SE_FW_IMG_H
+#define __INC_HAL8192SE_FW_IMG_H
+
+/*Created on 2009/11/17, 16:15*/
+
+#include <linux/types.h>
+#define ImgArrayLength 88592
+extern u8 Rtl8192SEFwImgArray[ImgArrayLength];
+#define MainArrayLength 1
+extern u8 Rtl8192SEFwMainArray[MainArrayLength];
+#define DataArrayLength 1
+extern u8 Rtl8192SEFwDataArray[DataArrayLength];
+#define PHY_REG_2T2RArrayLength 372
+extern u32 Rtl8192SEPHY_REG_2T2RArray[PHY_REG_2T2RArrayLength];
+#define PHY_REG_1T2RArrayLength 1
+extern u32 Rtl8192SEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength];
+#define PHY_ChangeTo_1T1RArrayLength 48
+extern u32 Rtl8192SEPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength];
+#define PHY_ChangeTo_1T2RArrayLength 45
+extern u32 Rtl8192SEPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength];
+#define PHY_ChangeTo_2T2RArrayLength 45
+extern u32 Rtl8192SEPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength];
+#define PHY_REG_Array_PGLength 84
+extern u32 Rtl8192SEPHY_REG_Array_PG[PHY_REG_Array_PGLength];
+#define RadioA_1T_ArrayLength 202
+extern u32 Rtl8192SERadioA_1T_Array[RadioA_1T_ArrayLength];
+#define RadioB_ArrayLength 22
+extern u32 Rtl8192SERadioB_Array[RadioB_ArrayLength];
+#define RadioA_to1T_ArrayLength 196
+extern u32 Rtl8192SERadioA_to1T_Array[RadioA_to1T_ArrayLength];
+#define RadioA_to2T_ArrayLength 196
+extern u32 Rtl8192SERadioA_to2T_Array[RadioA_to2T_ArrayLength];
+#define RadioB_GM_ArrayLength 10
+extern u32 Rtl8192SERadioB_GM_Array[RadioB_GM_ArrayLength];
+#define MAC_2T_ArrayLength 106
+extern u32 Rtl8192SEMAC_2T_Array[MAC_2T_ArrayLength];
+#define MACPHY_Array_PGLength 1
+extern u32 Rtl8192SEMACPHY_Array_PG[MACPHY_Array_PGLength];
+#define AGCTAB_ArrayLength 320
+extern u32 Rtl8192SEAGCTAB_Array[AGCTAB_ArrayLength];
+
+#endif diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg492.c b/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg492.c new file mode 100644 index 000000000000..e41d3b975bee --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg492.c @@ -0,0 +1,5610 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+/*Created on 2009/ 7/23, 5: 4*/
+
+#ifdef RTL8192SE
+#include "r8192S_hwimg.h"
+
+u8 Rtl8192SEFwImgArray[ImgArrayLength] = {
+0x92,0x81,0x31,0x70,0x30,0x00,0x00,0x00,0x08,0x84,0x00,0x00,0x48,0xa4,0x00,0x00,
+0x30,0x00,0x00,0x00,0xc0,0xa2,0x00,0x00,0x31,0x00,0x02,0x00,0x07,0x20,0x16,0x06,
+0x92,0x81,0x01,0x01,0x00,0x00,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x01,0x01,0x01,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x7f,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1f,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x25,0xb0,0x1a,0x3c,0x80,0x03,0x5a,0x37,0x00,0x80,0x1b,0x3c,0x80,0x00,0x7b,0x37,
+0x00,0x00,0x5b,0xaf,0x25,0xb0,0x1a,0x3c,0x18,0x03,0x5a,0x37,0x00,0x80,0x1b,0x3c,
+0x80,0x00,0x7b,0x37,0x00,0x00,0x5b,0xaf,0x00,0x80,0x1a,0x3c,0x44,0x7c,0x5a,0x27,
+0x08,0x00,0x40,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x04,0x00,0xa1,0xaf,0x08,0x00,0xa2,0xaf,0x0c,0x00,0xa3,0xaf,0x10,0x00,0xa4,0xaf,
+0x14,0x00,0xa5,0xaf,0x18,0x00,0xa6,0xaf,0x1c,0x00,0xa7,0xaf,0x20,0x00,0xa8,0xaf,
+0x24,0x00,0xa9,0xaf,0x28,0x00,0xaa,0xaf,0x2c,0x00,0xab,0xaf,0x30,0x00,0xac,0xaf,
+0x34,0x00,0xad,0xaf,0x38,0x00,0xae,0xaf,0x3c,0x00,0xaf,0xaf,0x12,0x40,0x00,0x00,
+0x10,0x48,0x00,0x00,0x00,0x70,0x0a,0x40,0x40,0x00,0xb0,0xaf,0x44,0x00,0xb1,0xaf,
+0x48,0x00,0xb2,0xaf,0x4c,0x00,0xb3,0xaf,0x50,0x00,0xb4,0xaf,0x54,0x00,0xb5,0xaf,
+0x58,0x00,0xb6,0xaf,0x5c,0x00,0xb7,0xaf,0x60,0x00,0xb8,0xaf,0x64,0x00,0xb9,0xaf,
+0x68,0x00,0xbc,0xaf,0x6c,0x00,0xbd,0xaf,0x70,0x00,0xbe,0xaf,0x74,0x00,0xbf,0xaf,
+0x78,0x00,0xa8,0xaf,0x7c,0x00,0xa9,0xaf,0x80,0x00,0xaa,0xaf,0xac,0x1e,0x00,0x08,
+0x21,0x20,0xa0,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x25,0xb0,0x06,0x3c,0x00,0x80,0x02,0x3c,0xe8,0xff,0xbd,0x27,0x18,0x03,0xc3,0x34,
+0x00,0x03,0x42,0x24,0x14,0x00,0xbf,0xaf,0x10,0x00,0xb0,0xaf,0x00,0x00,0x62,0xac,
+0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x00,0x60,0x81,0x40,0x42,0xb0,0x03,0x3c,
+0x03,0x00,0x63,0x34,0x00,0x00,0x62,0x90,0x02,0x80,0x0a,0x3c,0x02,0x80,0x10,0x3c,
+0xff,0x00,0x42,0x30,0x00,0x46,0x02,0x00,0x10,0x00,0x42,0x30,0x13,0x00,0x40,0x10,
+0x03,0x46,0x08,0x00,0x24,0x7e,0x42,0x8d,0x68,0x15,0x05,0x26,0xe0,0x63,0xa4,0x94,
+0x01,0x00,0x47,0x24,0x10,0x00,0x02,0x24,0xb0,0x03,0xc9,0x34,0x00,0x00,0x62,0xa0,
+0x07,0x00,0x80,0x10,0x1c,0x03,0xc6,0x34,0xe4,0x63,0xa2,0x94,0xe0,0x63,0xa0,0xa4,
+0xe4,0x63,0xa0,0xa4,0x00,0x00,0x04,0x24,0x00,0x00,0xc2,0xac,0x00,0x00,0x20,0xad,
+0x01,0x00,0x82,0x24,0x24,0x7e,0x47,0xad,0xe0,0x63,0xa2,0xa4,0x12,0x00,0x00,0x05,
+0x42,0xb0,0x02,0x3c,0x00,0x60,0x01,0x40,0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,
+0x00,0x60,0x81,0x40,0x68,0x15,0x04,0x26,0x0c,0x4b,0x83,0x94,0x08,0x4b,0x85,0x94,
+0x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,0x80,0x00,0x63,0x30,0x41,0xb0,0x02,0x3c,
+0x25,0x18,0x65,0x00,0x08,0x00,0x42,0x34,0x18,0x00,0xbd,0x27,0x00,0x00,0x43,0xa4,
+0x08,0x00,0xe0,0x03,0x08,0x4b,0x83,0xa4,0x80,0xff,0x03,0x24,0x03,0x00,0x42,0x34,
+0x00,0x00,0x43,0xa0,0x64,0x10,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x60,0x01,0x40,
+0x01,0x00,0x21,0x34,0x01,0x00,0x21,0x38,0x00,0x60,0x81,0x40,0x68,0x15,0x04,0x26,
+0x0c,0x4b,0x83,0x94,0x08,0x4b,0x85,0x94,0x14,0x00,0xbf,0x8f,0x10,0x00,0xb0,0x8f,
+0x80,0x00,0x63,0x30,0x41,0xb0,0x02,0x3c,0x25,0x18,0x65,0x00,0x08,0x00,0x42,0x34,
+0x18,0x00,0xbd,0x27,0x00,0x00,0x43,0xa4,0x08,0x00,0xe0,0x03,0x08,0x4b,0x83,0xa4,
+0xff,0x00,0x84,0x30,0x0b,0x00,0x82,0x2c,0xff,0xff,0xe7,0x30,0x10,0x00,0xa8,0x93,
+0x19,0x00,0x40,0x10,0x21,0x18,0x00,0x00,0x02,0x80,0x03,0x3c,0x80,0x10,0x04,0x00,
+0x58,0x9f,0x63,0x24,0x21,0x10,0x43,0x00,0x00,0x00,0x44,0x8c,0x00,0x00,0x00,0x00,
+0x08,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x43,0xb0,0x02,0x3c,0x78,0x00,0x44,0x34,
+0x07,0x00,0xe2,0x30,0x00,0x00,0x85,0xac,0x04,0x00,0x86,0xac,0x04,0x00,0x40,0x18,
+0x00,0x00,0x00,0x00,0xf8,0xff,0xe2,0x30,0x08,0x00,0x42,0x24,0xff,0xff,0x47,0x30,
+0x21,0x10,0xe8,0x00,0x00,0x80,0x03,0x3c,0x08,0x00,0x82,0xac,0x25,0x10,0x43,0x00,
+0x08,0x00,0x82,0xac,0x01,0x00,0x03,0x24,0x08,0x00,0xe0,0x03,0x21,0x10,0x60,0x00,
+0x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,0x6c,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,
+0x20,0x01,0x00,0x08,0x60,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,
+0x54,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,0x48,0x00,0x44,0x34,
+0x43,0xb0,0x02,0x3c,0x20,0x01,0x00,0x08,0x3c,0x00,0x44,0x34,0x43,0xb0,0x02,0x3c,
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+0x40,0x06,0x00,0x00,0x40,0x06,0x00,0x00,0xd0,0x07,0x00,0x00,0xd0,0x07,0x00,0x00,
+0x2c,0x05,0x00,0x80,0x20,0x05,0x00,0x80,0x14,0x05,0x00,0x80,0x08,0x05,0x00,0x80,
+0xfc,0x04,0x00,0x80,0xf0,0x04,0x00,0x80,0xe4,0x04,0x00,0x80,0xd8,0x04,0x00,0x80,
+0xcc,0x04,0x00,0x80,0xc0,0x04,0x00,0x80,0x78,0x04,0x00,0x80,0x70,0x3b,0x01,0x80,
+0x48,0x3b,0x01,0x80,0x24,0x3b,0x01,0x80,0x14,0x3c,0x01,0x80,0xf0,0x3b,0x01,0x80,
+0xcc,0x3b,0x01,0x80,0xa8,0x3b,0x01,0x80,0x30,0x41,0x00,0x80,0x3c,0x41,0x00,0x80,
+0x48,0x41,0x00,0x80,0x54,0x41,0x00,0x80,0x30,0x41,0x00,0x80,0x30,0x41,0x00,0x80,
+0x30,0x41,0x00,0x80,0x30,0x41,0x00,0x80,0x60,0x41,0x00,0x80,0x6c,0x41,0x00,0x80,
+0x78,0x41,0x00,0x80,0x84,0x41,0x00,0x80,0x68,0x15,0x02,0x80,0x68,0x15,0x02,0x80,
+0x84,0x0e,0x25,0xb0,0x88,0x0e,0x25,0xb0,0x8c,0x0e,0x25,0xb0,0xd0,0x0e,0x25,0xb0,
+0xd8,0x0e,0x25,0xb0,0x20,0x08,0x25,0xb0,0xfe,0x01,0x80,0x7f,0xe2,0x01,0x80,0x78,
+0xc7,0x01,0xc0,0x71,0xae,0x01,0x80,0x6b,0x95,0x01,0x40,0x65,0x7f,0x01,0xc0,0x5f,
+0x69,0x01,0x40,0x5a,0x55,0x01,0x40,0x55,0x42,0x01,0x80,0x50,0x30,0x01,0x00,0x4c,
+0x1f,0x01,0xc0,0x47,0x0f,0x01,0xc0,0x43,0x00,0x01,0x00,0x40,0xf2,0x00,0x80,0x3c,
+0xe4,0x00,0x00,0x39,0xd7,0x00,0xc0,0x35,0xcb,0x00,0xc0,0x32,0xc0,0x00,0x00,0x30,
+0xb5,0x00,0x40,0x2d,0xab,0x00,0xc0,0x2a,0xa2,0x00,0x80,0x28,0x98,0x00,0x00,0x26,
+0x90,0x00,0x00,0x24,0x88,0x00,0x00,0x22,0x80,0x00,0x00,0x20,0x79,0x00,0x40,0x1e,
+0x72,0x00,0x80,0x1c,0x6c,0x00,0x00,0x1b,0x66,0x00,0x80,0x19,0x60,0x00,0x00,0x18,
+0x5b,0x00,0xc0,0x16,0x56,0x00,0x80,0x15,0x51,0x00,0x40,0x14,0x4c,0x00,0x00,0x13,
+0x48,0x00,0x00,0x12,0x44,0x00,0x00,0x11,0x40,0x00,0x00,0x10,0x36,0x35,0x2e,0x25,
+0x1c,0x12,0x09,0x04,0x33,0x32,0x2b,0x23,0x1a,0x11,0x08,0x04,0x30,0x2f,0x29,0x21,
+0x19,0x10,0x08,0x03,0x2d,0x2d,0x27,0x1f,0x18,0x0f,0x08,0x03,0x2b,0x2a,0x25,0x1e,
+0x16,0x0e,0x07,0x03,0x28,0x28,0x22,0x1c,0x15,0x0d,0x07,0x03,0x26,0x25,0x21,0x1b,
+0x14,0x0d,0x06,0x03,0x24,0x23,0x1f,0x19,0x13,0x0c,0x06,0x03,0x22,0x21,0x1d,0x18,
+0x11,0x0b,0x06,0x02,0x20,0x20,0x1b,0x16,0x11,0x08,0x05,0x02,0x1f,0x1e,0x1a,0x15,
+0x10,0x0a,0x05,0x02,0x1d,0x1c,0x18,0x14,0x0f,0x0a,0x05,0x02,0x1b,0x1a,0x17,0x13,
+0x0e,0x09,0x04,0x02,0x1a,0x19,0x16,0x12,0x0d,0x09,0x04,0x02,0x18,0x17,0x15,0x11,
+0x0c,0x08,0x04,0x02,0x17,0x16,0x13,0x10,0x0c,0x08,0x04,0x02,0x16,0x15,0x12,0x0f,
+0x0b,0x07,0x04,0x01,0x14,0x14,0x11,0x0e,0x0b,0x07,0x03,0x02,0x13,0x13,0x10,0x0d,
+0x0a,0x06,0x03,0x01,0x12,0x12,0x0f,0x0c,0x09,0x06,0x03,0x01,0x11,0x11,0x0f,0x0c,
+0x09,0x06,0x03,0x01,0x10,0x10,0x0e,0x0b,0x08,0x05,0x03,0x01,0x0f,0x0f,0x0d,0x0b,
+0x08,0x05,0x03,0x01,0x0e,0x0e,0x0c,0x0a,0x08,0x05,0x02,0x01,0x0d,0x0d,0x0c,0x0a,
+0x07,0x05,0x02,0x01,0x0d,0x0c,0x0b,0x09,0x07,0x04,0x02,0x01,0x0c,0x0c,0x0a,0x09,
+0x06,0x04,0x02,0x01,0x0b,0x0b,0x0a,0x08,0x06,0x04,0x02,0x01,0x0b,0x0a,0x09,0x08,
+0x06,0x04,0x02,0x01,0x0a,0x0a,0x09,0x07,0x05,0x03,0x02,0x01,0x0a,0x09,0x08,0x07,
+0x05,0x03,0x02,0x01,0x09,0x09,0x08,0x06,0x05,0x03,0x01,0x01,0x09,0x08,0x07,0x06,
+0x04,0x03,0x01,0x01,0x36,0x35,0x2e,0x1b,0x00,0x00,0x00,0x00,0x33,0x32,0x2b,0x19,
+0x00,0x00,0x00,0x00,0x30,0x2f,0x29,0x18,0x00,0x00,0x00,0x00,0x2d,0x2d,0x17,0x17,
+0x00,0x00,0x00,0x00,0x2b,0x2a,0x25,0x15,0x00,0x00,0x00,0x00,0x28,0x28,0x24,0x14,
+0x00,0x00,0x00,0x00,0x26,0x25,0x21,0x13,0x00,0x00,0x00,0x00,0x24,0x23,0x1f,0x12,
+0x00,0x00,0x00,0x00,0x22,0x21,0x1d,0x11,0x00,0x00,0x00,0x00,0x20,0x20,0x1b,0x10,
+0x00,0x00,0x00,0x00,0x1f,0x1e,0x1a,0x0f,0x00,0x00,0x00,0x00,0x1d,0x1c,0x18,0x0e,
+0x00,0x00,0x00,0x00,0x1b,0x1a,0x17,0x0e,0x00,0x00,0x00,0x00,0x1a,0x19,0x16,0x0d,
+0x00,0x00,0x00,0x00,0x18,0x17,0x15,0x0c,0x00,0x00,0x00,0x00,0x17,0x16,0x13,0x0b,
+0x00,0x00,0x00,0x00,0x16,0x15,0x12,0x0b,0x00,0x00,0x00,0x00,0x14,0x14,0x11,0x0a,
+0x00,0x00,0x00,0x00,0x13,0x13,0x10,0x0a,0x00,0x00,0x00,0x00,0x12,0x12,0x0f,0x09,
+0x00,0x00,0x00,0x00,0x11,0x11,0x0f,0x09,0x00,0x00,0x00,0x00,0x10,0x10,0x0e,0x08,
+0x00,0x00,0x00,0x00,0x0f,0x0f,0x0d,0x08,0x00,0x00,0x00,0x00,0x0e,0x0e,0x0c,0x07,
+0x00,0x00,0x00,0x00,0x0d,0x0d,0x0c,0x07,0x00,0x00,0x00,0x00,0x0d,0x0c,0x0b,0x06,
+0x00,0x00,0x00,0x00,0x0c,0x0c,0x0a,0x06,0x00,0x00,0x00,0x00,0x0b,0x0b,0x0a,0x06,
+0x00,0x00,0x00,0x00,0x0b,0x0a,0x09,0x05,0x00,0x00,0x00,0x00,0x0a,0x0a,0x09,0x05,
+0x00,0x00,0x00,0x00,0x0a,0x09,0x08,0x05,0x00,0x00,0x00,0x00,0x09,0x09,0x08,0x05,
+0x00,0x00,0x00,0x00,0x09,0x08,0x07,0x04,0x00,0x00,0x00,0x00,0x06,0x00,0x2a,0xb0,
+0x05,0x00,0x2a,0xb0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x28,0x28,0x28,0x28,0x28,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
+0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0xa0,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,
+0x04,0x04,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x41,0x41,0x41,0x41,0x41,0x41,0x01,
+0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+0x01,0x01,0x01,0x10,0x10,0x10,0x10,0x10,0x10,0x42,0x42,0x42,0x42,0x42,0x42,0x02,
+0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,
+0x02,0x02,0x02,0x10,0x10,0x10,0x10,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x10,
+0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,
+0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x10,
+0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x00,0xa5,0x76,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x26,0x72,0xb0,0x00,0x26,0x72,0xb0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x26,0x65,0x60,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x02,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x5a,0x00,0xb8,0xff,0xff,0xff,0xff,
+};
+
+u8 Rtl8192SEFwMainArray[MainArrayLength] = {
+0x0, };
+
+u8 Rtl8192SEFwDataArray[DataArrayLength] = {
+0x0, };
+
+u32 Rtl8192SEPHY_REG_2T2RArray[PHY_REG_2T2RArrayLength] = {
+0x01c,0x07000000,
+0x800,0x00040000,
+0x804,0x00008003,
+0x808,0x0000fc00,
+0x80c,0x0000000a,
+0x810,0x10005088,
+0x814,0x020c3d10,
+0x818,0x00200185,
+0x81c,0x00000000,
+0x820,0x01000000,
+0x824,0x00390004,
+0x828,0x01000000,
+0x82c,0x00390004,
+0x830,0x00000004,
+0x834,0x00690200,
+0x838,0x00000004,
+0x83c,0x00690200,
+0x840,0x00010000,
+0x844,0x00010000,
+0x848,0x00000000,
+0x84c,0x00000000,
+0x850,0x00000000,
+0x854,0x00000000,
+0x858,0x48484848,
+0x85c,0x65a965a9,
+0x860,0x0f7f0130,
+0x864,0x0f7f0130,
+0x868,0x0f7f0130,
+0x86c,0x0f7f0130,
+0x870,0x03000700,
+0x874,0x03000300,
+0x878,0x00020002,
+0x87c,0x004f0201,
+0x880,0xa8300ac1,
+0x884,0x00000058,
+0x888,0x00000008,
+0x88c,0x00000004,
+0x890,0x00000000,
+0x894,0xfffffffe,
+0x898,0x40302010,
+0x89c,0x00706050,
+0x8b0,0x00000000,
+0x8e0,0x00000000,
+0x8e4,0x00000000,
+0xe00,0x30333333,
+0xe04,0x2a2d2e2f,
+0xe08,0x00003232,
+0xe10,0x30333333,
+0xe14,0x2a2d2e2f,
+0xe18,0x30333333,
+0xe1c,0x2a2d2e2f,
+0xe30,0x01007c00,
+0xe34,0x01004800,
+0xe38,0x1000dc1f,
+0xe3c,0x10008c1f,
+0xe40,0x021400a0,
+0xe44,0x281600a0,
+0xe48,0xf8000001,
+0xe4c,0x00002910,
+0xe50,0x01007c00,
+0xe54,0x01004800,
+0xe58,0x1000dc1f,
+0xe5c,0x10008c1f,
+0xe60,0x021400a0,
+0xe64,0x281600a0,
+0xe6c,0x00002910,
+0xe70,0x31ed92fb,
+0xe74,0x361536fb,
+0xe78,0x361536fb,
+0xe7c,0x361536fb,
+0xe80,0x361536fb,
+0xe84,0x000d92fb,
+0xe88,0x000d92fb,
+0xe8c,0x31ed92fb,
+0xed0,0x31ed92fb,
+0xed4,0x31ed92fb,
+0xed8,0x000d92fb,
+0xedc,0x000d92fb,
+0xee0,0x000d92fb,
+0xee4,0x015e5448,
+0xee8,0x21555448,
+0x900,0x00000000,
+0x904,0x00000023,
+0x908,0x00000000,
+0x90c,0x01121313,
+0xa00,0x00d047c8,
+0xa04,0x80ff0008,
+0xa08,0x8ccd8300,
+0xa0c,0x2e62120f,
+0xa10,0x9500bb78,
+0xa14,0x11144028,
+0xa18,0x00881117,
+0xa1c,0x89140f00,
+0xa20,0x1a1b0000,
+0xa24,0x090e1317,
+0xa28,0x00000204,
+0xa2c,0x10d30000,
+0xc00,0x40071d40,
+0xc04,0x00a05633,
+0xc08,0x000000e4,
+0xc0c,0x6c6c6c6c,
+0xc10,0x08800000,
+0xc14,0x40000100,
+0xc18,0x08000000,
+0xc1c,0x40000100,
+0xc20,0x08000000,
+0xc24,0x40000100,
+0xc28,0x08000000,
+0xc2c,0x40000100,
+0xc30,0x6de9ac44,
+0xc34,0x469652cf,
+0xc38,0x49795994,
+0xc3c,0x0a979764,
+0xc40,0x1f7c403f,
+0xc44,0x000100b7,
+0xc48,0xec020000,
+0xc4c,0x007f037f,
+0xc50,0x69543420,
+0xc54,0x433c0094,
+0xc58,0x69543420,
+0xc5c,0x433c0094,
+0xc60,0x69543420,
+0xc64,0x433c0094,
+0xc68,0x69543420,
+0xc6c,0x433c0094,
+0xc70,0x2c7f000d,
+0xc74,0x0186155b,
+0xc78,0x0000001f,
+0xc7c,0x00b91612,
+0xc80,0x40000100,
+0xc84,0x20f60000,
+0xc88,0x20000080,
+0xc8c,0x20200000,
+0xc90,0x40000100,
+0xc94,0x00000000,
+0xc98,0x40000100,
+0xc9c,0x00000000,
+0xca0,0x00492492,
+0xca4,0x00000000,
+0xca8,0x00000000,
+0xcac,0x00000000,
+0xcb0,0x00000000,
+0xcb4,0x00000000,
+0xcb8,0x00000000,
+0xcbc,0x28000000,
+0xcc0,0x00000000,
+0xcc4,0x00000000,
+0xcc8,0x00000000,
+0xccc,0x00000000,
+0xcd0,0x00000000,
+0xcd4,0x00000000,
+0xcd8,0x64b22427,
+0xcdc,0x00766932,
+0xce0,0x00222222,
+0xce4,0x00000000,
+0xce8,0x37644302,
+0xcec,0x2f97d40c,
+0xd00,0x00000750,
+0xd04,0x00000403,
+0xd08,0x0000907f,
+0xd0c,0x00000001,
+0xd10,0xa0633333,
+0xd14,0x33333c63,
+0xd18,0x6a8f5b6b,
+0xd1c,0x00000000,
+0xd20,0x00000000,
+0xd24,0x00000000,
+0xd28,0x00000000,
+0xd2c,0xcc979975,
+0xd30,0x00000000,
+0xd34,0x00000000,
+0xd38,0x00000000,
+0xd3c,0x00027293,
+0xd40,0x00000000,
+0xd44,0x00000000,
+0xd48,0x00000000,
+0xd50,0x6437140a,
+0xd54,0x024dbd02,
+0xd58,0x00000000,
+0xd5c,0x30032064,
+0xd60,0x4653de68,
+0xd64,0x00518a3c,
+0xd68,0x00002101,
+0xf14,0x00000003,
+0xf4c,0x00000000,
+0xf00,0x00000300,
+};
+
+u32 Rtl8192SEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
+0x0, };
+
+u32 Rtl8192SEPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength] = {
+0x844,0xffffffff,0x00010000,
+0x804,0x0000000f,0x00000001,
+0x824,0x00f0000f,0x00300004,
+0x82c,0x00f0000f,0x00100002,
+0x870,0x04000000,0x00000001,
+0x864,0x00000400,0x00000000,
+0x878,0x000f000f,0x00000002,
+0xe74,0x0f000000,0x00000002,
+0xe78,0x0f000000,0x00000002,
+0xe7c,0x0f000000,0x00000002,
+0xe80,0x0f000000,0x00000002,
+0x90c,0x000000ff,0x00000011,
+0xc04,0x000000ff,0x00000011,
+0xd04,0x0000000f,0x00000001,
+0x1f4,0xffff0000,0x00007777,
+0x234,0xf8000000,0x0000000a,
+};
+
+u32 Rtl8192SEPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength] = {
+0x804,0x0000000f,0x00000003,
+0x824,0x00f0000f,0x00300004,
+0x82c,0x00f0000f,0x00300002,
+0x870,0x04000000,0x00000001,
+0x864,0x00000400,0x00000000,
+0x878,0x000f000f,0x00000002,
+0xe74,0x0f000000,0x00000002,
+0xe78,0x0f000000,0x00000002,
+0xe7c,0x0f000000,0x00000002,
+0xe80,0x0f000000,0x00000002,
+0x90c,0x000000ff,0x00000011,
+0xc04,0x000000ff,0x00000033,
+0xd04,0x0000000f,0x00000003,
+0x1f4,0xffff0000,0x00007777,
+0x234,0xf8000000,0x0000000a,
+};
+
+u32 Rtl8192SEPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength] = {
+0x804,0x0000000f,0x00000003,
+0x824,0x00f0000f,0x00300004,
+0x82c,0x00f0000f,0x00300004,
+0x870,0x04000000,0x00000001,
+0x864,0x00000400,0x00000001,
+0x878,0x000f000f,0x00020002,
+0xe74,0x0f000000,0x00000006,
+0xe78,0x0f000000,0x00000006,
+0xe7c,0x0f000000,0x00000006,
+0xe80,0x0f000000,0x00000006,
+0x90c,0x000000ff,0x00000033,
+0xc04,0x000000ff,0x00000033,
+0xd04,0x0000000f,0x00000003,
+0x1f4,0xffff0000,0x0000ffff,
+0x234,0xf8000000,0x00000013,
+};
+
+u32 Rtl8192SEPHY_REG_Array_PG[PHY_REG_Array_PGLength] = {
+0xe00,0xffffffff,0x06090909,
+0xe04,0xffffffff,0x00030406,
+0xe08,0x0000ff00,0x00000000,
+0xe10,0xffffffff,0x0a0c0d0e,
+0xe14,0xffffffff,0x04070809,
+0xe18,0xffffffff,0x0a0c0d0e,
+0xe1c,0xffffffff,0x04070809,
+0xe00,0xffffffff,0x04040404,
+0xe04,0xffffffff,0x00020204,
+0xe08,0x0000ff00,0x00000000,
+0xe10,0xffffffff,0x02040404,
+0xe14,0xffffffff,0x00000002,
+0xe18,0xffffffff,0x02040404,
+0xe1c,0xffffffff,0x00000002,
+0xe00,0xffffffff,0x04040404,
+0xe04,0xffffffff,0x00020204,
+0xe08,0x0000ff00,0x00000000,
+0xe10,0xffffffff,0x02040404,
+0xe14,0xffffffff,0x00000002,
+0xe18,0xffffffff,0x02040404,
+0xe1c,0xffffffff,0x00000002,
+0xe00,0xffffffff,0x02020202,
+0xe04,0xffffffff,0x00020202,
+0xe08,0x0000ff00,0x00000000,
+0xe10,0xffffffff,0x02020202,
+0xe14,0xffffffff,0x00000002,
+0xe18,0xffffffff,0x02020202,
+0xe1c,0xffffffff,0x00000002,
+};
+
+u32 Rtl8192SERadioA_1T_Array[RadioA_1T_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00030250,
+0x002,0x00010000,
+0x010,0x0008000f,
+0x011,0x000231fc,
+0x010,0x000c000f,
+0x011,0x0003f9f8,
+0x010,0x0002000f,
+0x011,0x00020101,
+0x014,0x0001093e,
+0x014,0x0009093e,
+0x015,0x0000f8f4,
+0x017,0x000f6500,
+0x01a,0x00013056,
+0x01b,0x00060000,
+0x01c,0x00000300,
+0x01e,0x00031059,
+0x021,0x00054000,
+0x022,0x0000083c,
+0x023,0x00001558,
+0x024,0x00000060,
+0x025,0x00022583,
+0x026,0x0000f200,
+0x027,0x000eacf1,
+0x028,0x0009bd54,
+0x029,0x00004582,
+0x02a,0x00000001,
+0x02b,0x00021334,
+0x02a,0x00000000,
+0x02b,0x0000000a,
+0x02a,0x00000001,
+0x02b,0x00000808,
+0x02b,0x00053333,
+0x02c,0x0000000c,
+0x02a,0x00000002,
+0x02b,0x00000808,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000003,
+0x02b,0x00000808,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000004,
+0x02b,0x00000808,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000005,
+0x02b,0x00000709,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x00000006,
+0x02b,0x00000709,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000007,
+0x02b,0x00000709,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000008,
+0x02b,0x00000709,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000009,
+0x02b,0x0000060a,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000a,
+0x02b,0x0000060a,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x0000000b,
+0x02b,0x0000060a,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x0000000c,
+0x02b,0x0000060a,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x0000000d,
+0x02b,0x0000050b,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000e,
+0x02b,0x0000050b,
+0x02b,0x00066623,
+0x02c,0x0000001a,
+0x02a,0x000e4000,
+0x030,0x00020000,
+0x031,0x000b9631,
+0x032,0x0000130d,
+0x033,0x00000187,
+0x013,0x00019e6c,
+0x013,0x00015e94,
+0x000,0x00010159,
+0x018,0x0000f401,
+0x0fe,0x00000000,
+0x01e,0x0003105b,
+0x0fe,0x00000000,
+0x000,0x00030159,
+0x010,0x0004000f,
+0x011,0x000203f9,
+};
+
+u32 Rtl8192SERadioB_Array[RadioB_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00001041,
+0x002,0x00011000,
+0x005,0x00080fc0,
+0x007,0x000fc803,
+0x013,0x00017cb0,
+0x013,0x00011cc0,
+0x013,0x0000dc60,
+0x013,0x00008c60,
+0x013,0x00004450,
+0x013,0x00000020,
+};
+
+u32 Rtl8192SERadioA_to1T_Array[RadioA_to1T_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00030250,
+0x002,0x00010000,
+0x010,0x0008000f,
+0x011,0x000231fc,
+0x010,0x000c000f,
+0x011,0x0003f9f8,
+0x014,0x0001093e,
+0x014,0x0009093e,
+0x015,0x000198f4,
+0x017,0x000f6500,
+0x01a,0x00013056,
+0x01b,0x00060000,
+0x01c,0x00000300,
+0x01e,0x00031059,
+0x021,0x00054000,
+0x022,0x0000083c,
+0x023,0x00001558,
+0x024,0x00000060,
+0x025,0x00022583,
+0x026,0x0000f200,
+0x027,0x000eacf1,
+0x028,0x000dbd54,
+0x029,0x00004582,
+0x02a,0x00000001,
+0x02b,0x00021334,
+0x02a,0x00000000,
+0x02b,0x0000000a,
+0x02a,0x00000001,
+0x02b,0x00000808,
+0x02b,0x00053333,
+0x02c,0x0000000c,
+0x02a,0x00000002,
+0x02b,0x00000808,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000003,
+0x02b,0x00000808,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000004,
+0x02b,0x00000808,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000005,
+0x02b,0x00000709,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x00000006,
+0x02b,0x00000709,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000007,
+0x02b,0x00000709,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000008,
+0x02b,0x00000709,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000009,
+0x02b,0x0000060a,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000a,
+0x02b,0x0000060a,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x0000000b,
+0x02b,0x0000060a,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x0000000c,
+0x02b,0x0000060a,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x0000000d,
+0x02b,0x0000050b,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000e,
+0x02b,0x0000050b,
+0x02b,0x00066623,
+0x02c,0x0000001a,
+0x02a,0x000e4000,
+0x030,0x00020000,
+0x031,0x000b9631,
+0x033,0x00000187,
+0x013,0x00019e6c,
+0x013,0x00015e94,
+0x000,0x00010159,
+0x018,0x0000f401,
+0x0fe,0x00000000,
+0x01e,0x0003105b,
+0x0fe,0x00000000,
+0x000,0x00030159,
+0x010,0x0004000f,
+0x011,0x000203f9,
+};
+
+u32 Rtl8192SERadioA_to2T_Array[RadioA_to2T_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00030250,
+0x002,0x00010000,
+0x010,0x0008000f,
+0x011,0x000231fc,
+0x010,0x000c000f,
+0x011,0x0003f9f8,
+0x014,0x0001093e,
+0x014,0x0009093e,
+0x015,0x000198f4,
+0x017,0x000f6500,
+0x01a,0x00013056,
+0x01b,0x00060000,
+0x01c,0x00000300,
+0x01e,0x00031059,
+0x021,0x00054000,
+0x022,0x0000083c,
+0x023,0x00001558,
+0x024,0x00000060,
+0x025,0x00022583,
+0x026,0x0000f200,
+0x027,0x000eacf1,
+0x028,0x000dbd54,
+0x029,0x00004582,
+0x02a,0x00000001,
+0x02b,0x00021334,
+0x02a,0x00000000,
+0x02b,0x0000000a,
+0x02a,0x00000001,
+0x02b,0x00000808,
+0x02b,0x00053333,
+0x02c,0x0000000c,
+0x02a,0x00000002,
+0x02b,0x00000808,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000003,
+0x02b,0x00000808,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000004,
+0x02b,0x00000808,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000005,
+0x02b,0x00000709,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x00000006,
+0x02b,0x00000709,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x00000007,
+0x02b,0x00000709,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x00000008,
+0x02b,0x00000709,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x00000009,
+0x02b,0x0000060a,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000a,
+0x02b,0x0000060a,
+0x02b,0x0005b333,
+0x02c,0x0000000d,
+0x02a,0x0000000b,
+0x02b,0x0000060a,
+0x02b,0x00063333,
+0x02c,0x0000000d,
+0x02a,0x0000000c,
+0x02b,0x0000060a,
+0x02b,0x0006b333,
+0x02c,0x0000000d,
+0x02a,0x0000000d,
+0x02b,0x0000050b,
+0x02b,0x00053333,
+0x02c,0x0000000d,
+0x02a,0x0000000e,
+0x02b,0x0000050b,
+0x02b,0x00066623,
+0x02c,0x0000001a,
+0x02a,0x000e4000,
+0x030,0x00020000,
+0x031,0x000b9631,
+0x033,0x00000187,
+0x013,0x00019e6c,
+0x013,0x00015e94,
+0x000,0x00010159,
+0x018,0x0000f401,
+0x0fe,0x00000000,
+0x01e,0x0003105b,
+0x0fe,0x00000000,
+0x000,0x00030159,
+0x010,0x0004000f,
+0x011,0x000203f9,
+};
+
+u32 Rtl8192SERadioB_GM_Array[RadioB_GM_ArrayLength] = {
+0x000,0x00030159,
+0x001,0x00001041,
+0x002,0x00011000,
+0x005,0x00080fc0,
+0x007,0x000fc803,
+};
+
+u32 Rtl8192SEMAC_2T_Array[MAC_2T_ArrayLength] = {
+0x020,0x00000035,
+0x048,0x0000000e,
+0x049,0x000000f0,
+0x04a,0x00000077,
+0x04b,0x00000083,
+0x0b5,0x00000021,
+0x0dc,0x000000ff,
+0x0dd,0x000000ff,
+0x0de,0x000000ff,
+0x0df,0x000000ff,
+0x116,0x00000000,
+0x117,0x00000000,
+0x118,0x00000000,
+0x119,0x00000000,
+0x11a,0x00000000,
+0x11b,0x00000000,
+0x11c,0x00000000,
+0x11d,0x00000000,
+0x160,0x0000000b,
+0x161,0x0000000b,
+0x162,0x0000000b,
+0x163,0x0000000b,
+0x164,0x0000000b,
+0x165,0x0000000b,
+0x166,0x0000000b,
+0x167,0x0000000b,
+0x168,0x0000000b,
+0x169,0x0000000b,
+0x16a,0x0000000b,
+0x16b,0x0000000b,
+0x16c,0x0000000b,
+0x16d,0x0000000b,
+0x16e,0x0000000b,
+0x16f,0x0000000b,
+0x170,0x0000000b,
+0x171,0x0000000b,
+0x172,0x0000000b,
+0x173,0x0000000b,
+0x174,0x0000000b,
+0x175,0x0000000b,
+0x176,0x0000000b,
+0x177,0x0000000b,
+0x178,0x0000000b,
+0x179,0x0000000b,
+0x17a,0x0000000b,
+0x17b,0x0000000b,
+0x17c,0x0000000b,
+0x17d,0x0000000b,
+0x17e,0x0000000b,
+0x17f,0x0000000b,
+0x236,0x0000000c,
+0x503,0x00000022,
+0x560,0x00000000,
+};
+
+u32 Rtl8192SEMACPHY_Array_PG[MACPHY_Array_PGLength] = {
+0x0, };
+
+u32 Rtl8192SEAGCTAB_Array[AGCTAB_ArrayLength] = {
+0xc78,0x7f000001,
+0xc78,0x7f010001,
+0xc78,0x7e020001,
+0xc78,0x7d030001,
+0xc78,0x7c040001,
+0xc78,0x7b050001,
+0xc78,0x7a060001,
+0xc78,0x79070001,
+0xc78,0x78080001,
+0xc78,0x77090001,
+0xc78,0x760a0001,
+0xc78,0x750b0001,
+0xc78,0x740c0001,
+0xc78,0x730d0001,
+0xc78,0x720e0001,
+0xc78,0x710f0001,
+0xc78,0x70100001,
+0xc78,0x6f110001,
+0xc78,0x6f120001,
+0xc78,0x6e130001,
+0xc78,0x6d140001,
+0xc78,0x6d150001,
+0xc78,0x6c160001,
+0xc78,0x6b170001,
+0xc78,0x6a180001,
+0xc78,0x6a190001,
+0xc78,0x691a0001,
+0xc78,0x681b0001,
+0xc78,0x671c0001,
+0xc78,0x661d0001,
+0xc78,0x651e0001,
+0xc78,0x641f0001,
+0xc78,0x63200001,
+0xc78,0x4c210001,
+0xc78,0x4b220001,
+0xc78,0x4a230001,
+0xc78,0x49240001,
+0xc78,0x48250001,
+0xc78,0x47260001,
+0xc78,0x46270001,
+0xc78,0x45280001,
+0xc78,0x44290001,
+0xc78,0x2c2a0001,
+0xc78,0x2b2b0001,
+0xc78,0x2a2c0001,
+0xc78,0x292d0001,
+0xc78,0x282e0001,
+0xc78,0x272f0001,
+0xc78,0x26300001,
+0xc78,0x25310001,
+0xc78,0x24320001,
+0xc78,0x23330001,
+0xc78,0x22340001,
+0xc78,0x09350001,
+0xc78,0x08360001,
+0xc78,0x07370001,
+0xc78,0x06380001,
+0xc78,0x05390001,
+0xc78,0x043a0001,
+0xc78,0x033b0001,
+0xc78,0x023c0001,
+0xc78,0x013d0001,
+0xc78,0x003e0001,
+0xc78,0x003f0001,
+0xc78,0x7f400001,
+0xc78,0x7f410001,
+0xc78,0x7e420001,
+0xc78,0x7d430001,
+0xc78,0x7c440001,
+0xc78,0x7b450001,
+0xc78,0x7a460001,
+0xc78,0x79470001,
+0xc78,0x78480001,
+0xc78,0x77490001,
+0xc78,0x764a0001,
+0xc78,0x754b0001,
+0xc78,0x744c0001,
+0xc78,0x734d0001,
+0xc78,0x724e0001,
+0xc78,0x714f0001,
+0xc78,0x70500001,
+0xc78,0x6f510001,
+0xc78,0x6f520001,
+0xc78,0x6e530001,
+0xc78,0x6d540001,
+0xc78,0x6d550001,
+0xc78,0x6c560001,
+0xc78,0x6b570001,
+0xc78,0x6a580001,
+0xc78,0x6a590001,
+0xc78,0x695a0001,
+0xc78,0x685b0001,
+0xc78,0x675c0001,
+0xc78,0x665d0001,
+0xc78,0x655e0001,
+0xc78,0x645f0001,
+0xc78,0x63600001,
+0xc78,0x4c610001,
+0xc78,0x4b620001,
+0xc78,0x4a630001,
+0xc78,0x49640001,
+0xc78,0x48650001,
+0xc78,0x47660001,
+0xc78,0x46670001,
+0xc78,0x45680001,
+0xc78,0x44690001,
+0xc78,0x2c6a0001,
+0xc78,0x2b6b0001,
+0xc78,0x2a6c0001,
+0xc78,0x296d0001,
+0xc78,0x286e0001,
+0xc78,0x276f0001,
+0xc78,0x26700001,
+0xc78,0x25710001,
+0xc78,0x24720001,
+0xc78,0x23730001,
+0xc78,0x22740001,
+0xc78,0x09750001,
+0xc78,0x08760001,
+0xc78,0x07770001,
+0xc78,0x06780001,
+0xc78,0x05790001,
+0xc78,0x047a0001,
+0xc78,0x037b0001,
+0xc78,0x027c0001,
+0xc78,0x017d0001,
+0xc78,0x007e0001,
+0xc78,0x007f0001,
+0xc78,0x3000001e,
+0xc78,0x3001001e,
+0xc78,0x3002001e,
+0xc78,0x3003001e,
+0xc78,0x3004001e,
+0xc78,0x3405001e,
+0xc78,0x3806001e,
+0xc78,0x3e07001e,
+0xc78,0x3e08001e,
+0xc78,0x4409001e,
+0xc78,0x460a001e,
+0xc78,0x480b001e,
+0xc78,0x480c001e,
+0xc78,0x4e0d001e,
+0xc78,0x560e001e,
+0xc78,0x5a0f001e,
+0xc78,0x5e10001e,
+0xc78,0x6211001e,
+0xc78,0x6c12001e,
+0xc78,0x7213001e,
+0xc78,0x7214001e,
+0xc78,0x7215001e,
+0xc78,0x7216001e,
+0xc78,0x7217001e,
+0xc78,0x7218001e,
+0xc78,0x7219001e,
+0xc78,0x721a001e,
+0xc78,0x721b001e,
+0xc78,0x721c001e,
+0xc78,0x721d001e,
+0xc78,0x721e001e,
+0xc78,0x721f001e,
+};
+
+#endif
diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg492.h b/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg492.h new file mode 100644 index 000000000000..b8f541b9cdb4 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_hwimg492.h @@ -0,0 +1,60 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#ifndef __INC_HAL8192SE_FW_IMG_H
+#define __INC_HAL8192SE_FW_IMG_H
+
+/*Created on 2009/ 7/23, 5: 4*/
+
+#include <linux/types.h>
+#define ImgArrayLength 75984
+extern u8 Rtl8192SEFwImgArray[ImgArrayLength];
+#define MainArrayLength 1
+extern u8 Rtl8192SEFwMainArray[MainArrayLength];
+#define DataArrayLength 1
+extern u8 Rtl8192SEFwDataArray[DataArrayLength];
+#define PHY_REG_2T2RArrayLength 372
+extern u32 Rtl8192SEPHY_REG_2T2RArray[PHY_REG_2T2RArrayLength];
+#define PHY_REG_1T2RArrayLength 1
+extern u32 Rtl8192SEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength];
+#define PHY_ChangeTo_1T1RArrayLength 48
+extern u32 Rtl8192SEPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength];
+#define PHY_ChangeTo_1T2RArrayLength 45
+extern u32 Rtl8192SEPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength];
+#define PHY_ChangeTo_2T2RArrayLength 45
+extern u32 Rtl8192SEPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength];
+#define PHY_REG_Array_PGLength 84
+extern u32 Rtl8192SEPHY_REG_Array_PG[PHY_REG_Array_PGLength];
+#define RadioA_1T_ArrayLength 202
+extern u32 Rtl8192SERadioA_1T_Array[RadioA_1T_ArrayLength];
+#define RadioB_ArrayLength 22
+extern u32 Rtl8192SERadioB_Array[RadioB_ArrayLength];
+#define RadioA_to1T_ArrayLength 196
+extern u32 Rtl8192SERadioA_to1T_Array[RadioA_to1T_ArrayLength];
+#define RadioA_to2T_ArrayLength 196
+extern u32 Rtl8192SERadioA_to2T_Array[RadioA_to2T_ArrayLength];
+#define RadioB_GM_ArrayLength 10
+extern u32 Rtl8192SERadioB_GM_Array[RadioB_GM_ArrayLength];
+#define MAC_2T_ArrayLength 106
+extern u32 Rtl8192SEMAC_2T_Array[MAC_2T_ArrayLength];
+#define MACPHY_Array_PGLength 1
+extern u32 Rtl8192SEMACPHY_Array_PG[MACPHY_Array_PGLength];
+#define AGCTAB_ArrayLength 320
+extern u32 Rtl8192SEAGCTAB_Array[AGCTAB_ArrayLength];
+
+#endif diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_led.c b/ubuntu/rtl8192se/rtl8192s/r8192S_led.c new file mode 100644 index 000000000000..7403a8c68ffe --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_led.c @@ -0,0 +1,1361 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#include "../rtl_core.h"
+#ifdef RTL8192SE
+#define LED_BLINK_NORMAL_INTERVAL 100
+#define LED_BLINK_SLOWLY_INTERVAL 200
+
+#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100
+#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000
+
+#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000
+#define LED_BLINK_NORMAL_INTERVAL_PORNET 100
+
+
+#define LED_CM2_BLINK_ON_INTERVAL 250
+#define LED_CM2_BLINK_OFF_INTERVAL 4750
+
+#define LED_CM8_BLINK_OFF_INTERVAL 3750 +
+#define LED_RunTop_BLINK_INTERVAL 300
+
+#define LED_CM3_BLINK_INTERVAL 1500
+
+
+
+static void BlinkTimerCallback(unsigned long data);
+
+
+void InitLed8190Pci(struct net_device *dev, PLED_8190 pLed,LED_PIN_8190 LedPin)
+{
+ pLed->dev = dev;
+ pLed->LedPin = LedPin;
+
+ pLed->CurrLedState = LED_OFF;
+ pLed->bLedOn = false;
+ pLed->bLedBlinkInProgress = false;
+ pLed->BlinkTimes = 0;
+ pLed->BlinkingLedState = LED_OFF;
+
+ setup_timer(&pLed->BlinkTimer,
+ BlinkTimerCallback,
+ (unsigned long) pLed);
+}
+
+void DeInitLed8190Pci(PLED_8190 pLed)
+{
+ del_timer_sync(&(pLed->BlinkTimer));
+ pLed->bLedBlinkInProgress = false;
+}
+
+void SwLedOn( struct net_device *dev , PLED_8190 pLed)
+{
+ u8 LedCfg;
+
+ LedCfg = read_nic_byte(dev, LEDCFG);
+
+ switch(pLed->LedPin)
+ {
+ case LED_PIN_GPIO0:
+ break;
+
+ case LED_PIN_LED0:
+ write_nic_byte(dev, LEDCFG, LedCfg&0xf0); + break;
+
+ case LED_PIN_LED1:
+ write_nic_byte(dev, LEDCFG, LedCfg&0x0f); + break;
+
+ default:
+ break;
+ }
+
+ pLed->bLedOn = true;
+}
+
+void SwLedOff(struct net_device *dev, PLED_8190 pLed)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 LedCfg;
+
+ LedCfg = read_nic_byte(dev, LEDCFG);
+
+ switch(pLed->LedPin)
+ {
+ case LED_PIN_GPIO0:
+ break;
+
+ case LED_PIN_LED0:
+ LedCfg &= 0xf0; +
+ if(priv->bLedOpenDrain == true) + write_nic_byte(dev, LEDCFG, (LedCfg|BIT1));
+ else
+ write_nic_byte(dev, LEDCFG, (LedCfg|BIT3));
+ break;
+
+ case LED_PIN_LED1:
+ LedCfg &= 0x0f; + write_nic_byte(dev, LEDCFG, (LedCfg|BIT7));
+ break;
+
+ default:
+ break;
+ }
+
+ pLed->bLedOn = false;
+}
+
+
+void InitSwLeds(struct net_device *dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ InitLed8190Pci(
+ dev,
+ &(priv->SwLed0),
+ LED_PIN_LED0);
+
+ InitLed8190Pci(
+ dev,
+ &(priv->SwLed1),
+ LED_PIN_LED1);
+}
+
+
+void DeInitSwLeds(struct net_device *dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ DeInitLed8190Pci( &(priv->SwLed0) );
+ DeInitLed8190Pci( &(priv->SwLed1) );
+}
+
+void HwLedBlink(struct net_device *dev, PLED_8190 pLed)
+{
+
+
+ switch(pLed->LedPin)
+ {
+ case LED_PIN_GPIO0:
+ break;
+
+ case LED_PIN_LED0:
+ break;
+
+ case LED_PIN_LED1:
+ break;
+
+ default:
+ break;
+ }
+
+ pLed->bLedOn = true;
+}
+
+
+
+void SwLedBlink(PLED_8190 pLed)
+{
+ struct net_device *dev = (struct net_device *)pLed->dev;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool bStopBlinking = false;
+
+ if( pLed->BlinkingLedState == LED_ON )
+ {
+ SwLedOn(dev, pLed);
+ RT_TRACE(COMP_LED, "Blinktimes (%d): turn on\n", pLed->BlinkTimes);
+ }
+ else
+ {
+ SwLedOff(dev, pLed);
+ RT_TRACE(COMP_LED, "Blinktimes (%d): turn off\n", pLed->BlinkTimes);
+ }
+
+ pLed->BlinkTimes--;
+ switch(pLed->CurrLedState)
+ {
+ case LED_BLINK_NORMAL:
+ case LED_BLINK_TXRX:
+ case LED_BLINK_RUNTOP:
+ if(pLed->BlinkTimes == 0)
+ {
+ bStopBlinking = true;
+ }
+ break;
+
+ case LED_SCAN_BLINK:
+ if( (priv->rtllib->state == RTLLIB_LINKED) && + (!rtllib_act_scanning(priv->rtllib,true))&& + (pLed->BlinkTimes % 2 == 0)) + {
+ bStopBlinking = true;
+ }
+ break;
+
+ case LED_NO_LINK_BLINK:
+ case LED_BLINK_StartToBlink:
+ if( (priv->rtllib->state == RTLLIB_LINKED) && (priv->rtllib->iw_mode == IW_MODE_INFRA))
+ {
+ bStopBlinking = true;
+ }
+ else if((priv->rtllib->state == RTLLIB_LINKED) && (priv->rtllib->iw_mode == IW_MODE_ADHOC))
+ {
+ bStopBlinking = true;
+ }
+ else if(pLed->BlinkTimes == 0)
+ {
+ bStopBlinking = true;
+ }
+ break;
+
+ case LED_BLINK_CAMEO:
+ if((priv->rtllib->state == RTLLIB_LINKED) && (priv->rtllib->iw_mode == IW_MODE_INFRA))
+ {
+ bStopBlinking = true;
+ }
+ else if((priv->rtllib->state == RTLLIB_LINKED) && (priv->rtllib->iw_mode == IW_MODE_ADHOC) )
+ {
+ bStopBlinking = true;
+ }
+ break;
+
+ default:
+ bStopBlinking = true;
+ break;
+ }
+
+ if(bStopBlinking)
+ {
+ if( priv->rtllib->eRFPowerState != eRfOn )
+ {
+ SwLedOff(dev, pLed);
+ }
+ else if(pLed->CurrLedState == LED_BLINK_TXRX)
+ {
+ SwLedOff(dev, pLed);
+ }
+ else if(pLed->CurrLedState == LED_BLINK_RUNTOP)
+ {
+ SwLedOff(dev, pLed);
+ }
+ else if( (priv->rtllib->state == RTLLIB_LINKED) && (pLed->bLedOn == false))
+ {
+ SwLedOn(dev, pLed);
+ }
+ else if( (priv->rtllib->state != RTLLIB_LINKED) && pLed->bLedOn == true)
+ {
+ SwLedOff(dev, pLed);
+ }
+
+ pLed->BlinkTimes = 0;
+ pLed->bLedBlinkInProgress = false;
+ }
+ else
+ {
+ if( pLed->BlinkingLedState == LED_ON )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+
+ switch( pLed->CurrLedState )
+ {
+ case LED_BLINK_NORMAL:
+ case LED_BLINK_TXRX:
+ case LED_BLINK_StartToBlink:
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL));
+ break;
+
+ case LED_BLINK_SLOWLY:
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL));
+ break;
+
+ case LED_SCAN_BLINK:
+ case LED_NO_LINK_BLINK:
+ if( pLed->bLedOn )
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_ON_INTERVAL));
+ else
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_OFF_INTERVAL));
+ break;
+
+ case LED_BLINK_RUNTOP:
+ mod_timer(&(pLed->BlinkTimer),jiffies + MSECS(LED_RunTop_BLINK_INTERVAL));
+ break;
+
+ case LED_BLINK_CAMEO:
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_PORNET));
+ break;
+
+ default:
+ RT_TRACE(COMP_ERR, "SwLedCm2Blink(): unexpected state!\n");
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL));
+ break;
+ }
+ }
+}
+
+void SwLedBlink5(PLED_8190 pLed)
+{
+ struct net_device *dev = (struct net_device *)pLed->dev;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool bStopBlinking = false;
+
+ if( pLed->BlinkingLedState == LED_ON )
+ {
+ SwLedOn(dev, pLed);
+ RT_TRACE(COMP_LED, "Blinktimes (%d): turn on\n", pLed->BlinkTimes);
+ }
+ else
+ {
+ SwLedOff(dev, pLed);
+ RT_TRACE(COMP_LED, "Blinktimes (%d): turn off\n", pLed->BlinkTimes);
+ }
+
+ switch(pLed->CurrLedState)
+ {
+ case LED_OFF:
+ SwLedOff(dev, pLed);
+ break;
+
+ case LED_BLINK_SLOWLY:
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_NETTRONIX));
+ break;
+
+ case LED_BLINK_NORMAL:
+ pLed->BlinkTimes--;
+ if( pLed->BlinkTimes == 0 )
+ {
+ bStopBlinking = true;
+ }
+ if(bStopBlinking)
+ {
+ if( priv->rtllib->eRFPowerState != eRfOn )
+ {
+ SwLedOff(dev, pLed);
+ }
+ else
+ {
+ pLed->bLedSlowBlinkInProgress = true;
+ pLed->CurrLedState = LED_BLINK_SLOWLY;
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_NETTRONIX));
+ }
+ pLed->BlinkTimes = 0;
+ pLed->bLedBlinkInProgress = false;
+ }
+ else
+ {
+ if( priv->rtllib->eRFPowerState != eRfOn )
+ {
+ SwLedOff(dev, pLed);
+ }
+ else
+ {
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL_NETTRONIX));
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+}
+
+
+void SwLedBlink6(PLED_8190 pLed)
+{
+ struct net_device *dev = (struct net_device *)pLed->dev;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool bStopBlinking = false;
+
+ if( pLed->BlinkingLedState == LED_ON )
+ {
+ SwLedOn(dev, pLed);
+ RT_TRACE(COMP_LED, "Blinktimes (%d): turn on\n", pLed->BlinkTimes);
+ }
+ else
+ {
+ SwLedOff(dev, pLed);
+ RT_TRACE(COMP_LED, "Blinktimes (%d): turn off\n", pLed->BlinkTimes);
+ }
+
+ switch(pLed->CurrLedState)
+ {
+ case LED_OFF:
+ SwLedOff(dev, pLed);
+ break;
+
+ case LED_BLINK_SLOWLY:
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_PORNET));
+ break;
+
+ case LED_BLINK_NORMAL:
+ pLed->BlinkTimes--;
+ if( pLed->BlinkTimes == 0 )
+ {
+ bStopBlinking = true;
+ }
+ if(bStopBlinking)
+ {
+ if( priv->rtllib->eRFPowerState != eRfOn )
+ {
+ SwLedOff(dev, pLed);
+ }
+ else
+ {
+ pLed->bLedSlowBlinkInProgress = true;
+ pLed->CurrLedState = LED_BLINK_SLOWLY;
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_PORNET));
+ }
+ pLed->BlinkTimes = 0;
+ pLed->bLedBlinkInProgress = false;
+ }
+ else
+ {
+ if( priv->rtllib->eRFPowerState != eRfOn )
+ {
+ SwLedOff(dev, pLed);
+ }
+ else
+ {
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL_PORNET));
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+}
+
+void SwLedBlink7( PLED_8190 pLed)
+{
+ struct net_device *dev = (struct net_device *)pLed->dev;
+
+ SwLedOn(dev, pLed);
+ RT_TRACE(COMP_LED, "Blinktimes (%d): turn on\n", pLed->BlinkTimes);
+}
+
+void BlinkTimerCallback(unsigned long data)
+{
+ PLED_8190 pLed = (PLED_8190)data;
+ struct net_device *dev = (struct net_device *)pLed->dev;
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ switch(priv->LedStrategy)
+ {
+ case SW_LED_MODE1:
+ break;
+ case SW_LED_MODE2:
+ break;
+ case SW_LED_MODE3:
+ break;
+ case SW_LED_MODE5:
+ break;
+ case SW_LED_MODE6:
+ break;
+
+ case SW_LED_MODE7:
+ SwLedBlink7(pLed);
+ break;
+
+ default:
+ break;
+ }
+}
+
+void SwLedControlMode0(struct net_device *dev,LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed0 = &(priv->SwLed0);
+ PLED_8190 pLed1 = &(priv->SwLed1);
+
+ switch(LedAction)
+ {
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ break;
+
+ case LED_CTL_LINK:
+ pLed0->CurrLedState = LED_ON;
+ SwLedOn(dev, pLed0);
+
+ pLed1->CurrLedState = LED_BLINK_NORMAL;
+ HwLedBlink(dev, pLed1);
+ break;
+
+ case LED_CTL_POWER_ON:
+ pLed0->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed0);
+
+ pLed1->CurrLedState = LED_BLINK_NORMAL;
+ HwLedBlink(dev, pLed1);
+
+ break;
+
+ case LED_CTL_POWER_OFF:
+ pLed0->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed0);
+
+ pLed1->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed1);
+ break;
+
+ case LED_CTL_SITE_SURVEY:
+ break;
+
+ case LED_CTL_NO_LINK:
+ pLed0->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed0);
+
+ pLed1->CurrLedState = LED_BLINK_NORMAL;
+ HwLedBlink(dev, pLed1);
+ break;
+
+ default:
+ break;
+ }
+
+ RT_TRACE(COMP_LED, "Led0 %d Led1 %d\n", pLed0->CurrLedState, pLed1->CurrLedState);
+}
+
+
+void SwLedControlMode1(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed = &(priv->SwLed1);
+
+ switch(LedAction)
+ {
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ if( pLed->bLedBlinkInProgress == false )
+ {
+ pLed->bLedBlinkInProgress = true;
+
+ pLed->CurrLedState = LED_BLINK_NORMAL;
+ pLed->BlinkTimes = 2;
+
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL));
+ }
+ break;
+
+ case LED_CTL_SITE_SURVEY:
+ if( pLed->bLedBlinkInProgress == false )
+ {
+ pLed->bLedBlinkInProgress = true;
+
+ if(priv->rtllib->state == RTLLIB_LINKED)
+ {
+ pLed->CurrLedState = LED_SCAN_BLINK;
+ pLed->BlinkTimes = 4;
+ }
+ else
+ {
+ pLed->CurrLedState = LED_NO_LINK_BLINK;
+ pLed->BlinkTimes = 24;
+ }
+
+ if( pLed->bLedOn )
+ {
+ pLed->BlinkingLedState = LED_OFF;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_ON_INTERVAL));
+ }
+ else
+ {
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_OFF_INTERVAL));
+ }
+ }
+ else
+ {
+ if(pLed->CurrLedState != LED_NO_LINK_BLINK)
+ {
+ if(priv->rtllib->state == RTLLIB_LINKED)
+ {
+ pLed->CurrLedState = LED_SCAN_BLINK;
+ }
+ else
+ {
+ pLed->CurrLedState = LED_NO_LINK_BLINK;
+ }
+ }
+ }
+ break;
+
+ case LED_CTL_NO_LINK:
+ if( pLed->bLedBlinkInProgress == false )
+ {
+ pLed->bLedBlinkInProgress = true;
+
+ pLed->CurrLedState = LED_NO_LINK_BLINK;
+ pLed->BlinkTimes = 24;
+
+ if( pLed->bLedOn )
+ {
+ pLed->BlinkingLedState = LED_OFF;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_ON_INTERVAL));
+ }
+ else
+ {
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_OFF_INTERVAL));
+ }
+ }
+ else
+ {
+ pLed->CurrLedState = LED_NO_LINK_BLINK;
+ }
+ break;
+
+ case LED_CTL_LINK:
+ pLed->CurrLedState = LED_ON;
+ if( pLed->bLedBlinkInProgress == false )
+ {
+ SwLedOn(dev, pLed);
+ }
+ break;
+
+ case LED_CTL_POWER_OFF:
+ pLed->CurrLedState = LED_OFF;
+ if(pLed->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed->BlinkTimer));
+ pLed->bLedBlinkInProgress = false;
+ }
+ SwLedOff(dev, pLed);
+ break;
+
+ default:
+ break;
+ }
+
+ RT_TRACE(COMP_LED, "Led %d \n", pLed->CurrLedState);
+}
+
+void SwLedControlMode2(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed0 = &(priv->SwLed0);
+ PLED_8190 pLed1 = &(priv->SwLed1);
+
+ switch(LedAction)
+ {
+ case LED_CTL_POWER_ON:
+ pLed0->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed0);
+
+ pLed1->CurrLedState = LED_BLINK_CAMEO;
+ if( pLed1->bLedBlinkInProgress == false )
+ {
+ pLed1->bLedBlinkInProgress = true;
+
+ pLed1->BlinkTimes = 6;
+
+ if( pLed1->bLedOn )
+ pLed1->BlinkingLedState = LED_OFF;
+ else
+ pLed1->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed1->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_PORNET));
+ }
+ break;
+
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ if( pLed0->bLedBlinkInProgress == false )
+ {
+ pLed0->bLedBlinkInProgress = true;
+
+ pLed0->CurrLedState = LED_BLINK_TXRX;
+ pLed0->BlinkTimes = 2;
+
+ if( pLed0->bLedOn )
+ pLed0->BlinkingLedState = LED_OFF;
+ else
+ pLed0->BlinkingLedState = LED_ON;
+
+ mod_timer(&(pLed0->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL));
+ }
+ break;
+
+ case LED_CTL_NO_LINK:
+ pLed1->CurrLedState = LED_BLINK_CAMEO;
+ if( pLed1->bLedBlinkInProgress == false )
+ {
+ pLed1->bLedBlinkInProgress = true;
+
+ pLed1->BlinkTimes = 6;
+
+ if( pLed1->bLedOn )
+ pLed1->BlinkingLedState = LED_OFF;
+ else
+ pLed1->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed1->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_PORNET));
+ }
+ break;
+
+ case LED_CTL_LINK:
+ pLed1->CurrLedState = LED_ON;
+ if( pLed1->bLedBlinkInProgress == false )
+ {
+ SwLedOn(dev, pLed1);
+ }
+ break;
+
+ case LED_CTL_POWER_OFF:
+ pLed0->CurrLedState = LED_OFF;
+ pLed1->CurrLedState = LED_OFF;
+ if(pLed0->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedBlinkInProgress = false;
+ }
+ if(pLed1->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed1->BlinkTimer));
+ pLed1->bLedBlinkInProgress = false;
+ }
+ SwLedOff(dev, pLed0);
+ SwLedOff(dev, pLed1);
+ break;
+
+ default:
+ break;
+ }
+
+ RT_TRACE(COMP_LED, "Led0 %d, Led1 %d \n", pLed0->CurrLedState, pLed1->CurrLedState);
+}
+
+
+
+void SwLedControlMode3(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed0 = &(priv->SwLed0);
+ PLED_8190 pLed1 = &(priv->SwLed1);
+
+ switch(LedAction)
+ {
+ case LED_CTL_POWER_ON:
+ pLed0->CurrLedState = LED_ON;
+ SwLedOn(dev, pLed0);
+ pLed1->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed1);
+ break;
+
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ if( pLed1->bLedBlinkInProgress == false )
+ {
+ pLed1->bLedBlinkInProgress = true;
+
+ pLed1->CurrLedState = LED_BLINK_RUNTOP;
+ pLed1->BlinkTimes = 2;
+
+ if( pLed1->bLedOn )
+ pLed1->BlinkingLedState = LED_OFF;
+ else
+ pLed1->BlinkingLedState = LED_ON;
+
+ mod_timer(&(pLed1->BlinkTimer), jiffies + MSECS(LED_RunTop_BLINK_INTERVAL));
+ }
+ break;
+
+ case LED_CTL_POWER_OFF:
+ pLed0->CurrLedState = LED_OFF;
+ pLed1->CurrLedState = LED_OFF;
+ if(pLed0->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedBlinkInProgress = false;
+ }
+ if(pLed1->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed1->BlinkTimer));
+ pLed1->bLedBlinkInProgress = false;
+ }
+ SwLedOff(dev, pLed0);
+ SwLedOff(dev, pLed1);
+ break;
+
+ default:
+ break;
+ }
+
+ RT_TRACE(COMP_LED, "Led0 %d, Led1 %d \n", pLed0->CurrLedState, pLed1->CurrLedState);
+}
+
+
+void SwLedControlMode4(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed0 = &(priv->SwLed0);
+ PLED_8190 pLed1 = &(priv->SwLed1);
+
+ switch(LedAction)
+ {
+ case LED_CTL_POWER_ON:
+ pLed1->CurrLedState = LED_ON;
+ SwLedOn(dev, pLed1);
+ pLed0->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed0);
+ break;
+
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ if( pLed0->bLedBlinkInProgress == false )
+ {
+ pLed0->bLedBlinkInProgress = true;
+
+ pLed0->CurrLedState = LED_BLINK_RUNTOP;
+ pLed0->BlinkTimes = 2;
+
+ if( pLed0->bLedOn )
+ pLed0->BlinkingLedState = LED_OFF;
+ else
+ pLed0->BlinkingLedState = LED_ON;
+
+ mod_timer(&(pLed0->BlinkTimer), jiffies + MSECS(LED_RunTop_BLINK_INTERVAL));
+ }
+ break;
+
+ case LED_CTL_POWER_OFF:
+ pLed0->CurrLedState = LED_OFF;
+ pLed1->CurrLedState = LED_OFF;
+ if(pLed0->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedBlinkInProgress = false;
+ }
+ if(pLed1->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed1->BlinkTimer));
+ pLed1->bLedBlinkInProgress = false;
+ }
+ SwLedOff(dev, pLed0);
+ SwLedOff(dev, pLed1);
+ break;
+
+ default:
+ break;
+ }
+
+ RT_TRACE(COMP_LED, "Led0 %d, Led1 %d \n", pLed0->CurrLedState, pLed1->CurrLedState);
+}
+
+void SwLedControlMode5(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed0 = &(priv->SwLed0);
+ PLED_8190 pLed1 = &(priv->SwLed1);
+ switch(LedAction)
+ {
+ case LED_CTL_POWER_ON:
+ case LED_CTL_START_TO_LINK:
+ case LED_CTL_NO_LINK:
+ pLed1->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed1);
+
+
+ if( pLed0->bLedSlowBlinkInProgress == false )
+ {
+ pLed0->bLedSlowBlinkInProgress = true;
+ pLed0->CurrLedState = LED_BLINK_SLOWLY;
+ if( pLed0->bLedOn )
+ pLed0->BlinkingLedState = LED_OFF;
+ else
+ pLed0->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed0->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_NETTRONIX));
+ }
+
+ break;
+
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ pLed1->CurrLedState = LED_ON;
+ SwLedOn(dev, pLed1);
+
+ if( pLed0->bLedBlinkInProgress == false )
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedSlowBlinkInProgress = false;
+ pLed0->bLedBlinkInProgress = true;
+ pLed0->CurrLedState = LED_BLINK_NORMAL;
+ pLed0->BlinkTimes = 2;
+
+ if( pLed0->bLedOn )
+ pLed0->BlinkingLedState = LED_OFF;
+ else
+ pLed0->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed0->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL_NETTRONIX));
+ }
+ break;
+
+ case LED_CTL_LINK:
+ pLed1->CurrLedState = LED_ON;
+ SwLedOn(dev, pLed1);
+
+ if( pLed0->bLedSlowBlinkInProgress == false )
+ {
+ pLed0->bLedSlowBlinkInProgress = true;
+ pLed0->CurrLedState = LED_BLINK_SLOWLY;
+ if( pLed0->bLedOn )
+ pLed0->BlinkingLedState = LED_OFF;
+ else
+ pLed0->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed0->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_NETTRONIX));
+ }
+ break;
+
+
+ case LED_CTL_POWER_OFF:
+ pLed0->CurrLedState = LED_OFF;
+ pLed1->CurrLedState = LED_OFF;
+ if( pLed0->bLedSlowBlinkInProgress == true )
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedSlowBlinkInProgress = false;
+ }
+ if(pLed0->bLedBlinkInProgress == true)
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedBlinkInProgress = false;
+ }
+ SwLedOff(dev, pLed0);
+ SwLedOff(dev, pLed1);
+ break;
+
+ default:
+ break;
+ }
+
+
+}
+
+void SwLedControlMode6(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed0 = &(priv->SwLed0);
+ PLED_8190 pLed1 = &(priv->SwLed1);
+
+
+ switch(LedAction)
+ {
+ case LED_CTL_POWER_ON:
+ case LED_CTL_START_TO_LINK:
+ case LED_CTL_NO_LINK:
+ case LED_CTL_LINK:
+ case LED_CTL_SITE_SURVEY:
+ pLed1->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed1);
+
+ if( pLed0->bLedSlowBlinkInProgress == false )
+ {
+ pLed0->bLedSlowBlinkInProgress = true;
+ pLed0->CurrLedState = LED_BLINK_SLOWLY;
+ if( pLed0->bLedOn )
+ pLed0->BlinkingLedState = LED_OFF;
+ else
+ pLed0->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed0->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL_PORNET));
+ }
+ break;
+
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ pLed1->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed1);
+ if( pLed0->bLedBlinkInProgress == false )
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedSlowBlinkInProgress = false;
+ pLed0->bLedBlinkInProgress = true;
+ pLed0->CurrLedState = LED_BLINK_NORMAL;
+ pLed0->BlinkTimes = 2;
+ if( pLed0->bLedOn )
+ pLed0->BlinkingLedState = LED_OFF;
+ else
+ pLed0->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed0->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL_PORNET));
+ }
+ break;
+
+ case LED_CTL_POWER_OFF:
+ pLed1->CurrLedState = LED_OFF;
+ SwLedOff(dev, pLed1);
+
+ pLed0->CurrLedState = LED_OFF;
+ if( pLed0->bLedSlowBlinkInProgress == true )
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedSlowBlinkInProgress = false;
+ }
+ if(pLed0->bLedBlinkInProgress == true)
+ {
+ del_timer_sync(&(pLed0->BlinkTimer));
+ pLed0->bLedBlinkInProgress = false;
+ }
+ SwLedOff(dev, pLed0);
+ break;
+
+ default:
+ break;
+
+ }
+}
+
+
+void SwLedControlMode7(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed0 = &(priv->SwLed0);
+
+ switch(LedAction)
+ {
+ case LED_CTL_POWER_ON:
+ case LED_CTL_LINK:
+ case LED_CTL_NO_LINK:
+ SwLedOn(dev, pLed0);
+ break;
+
+ case LED_CTL_POWER_OFF:
+ SwLedOff(dev, pLed0);
+ break;
+
+ default:
+ break;
+
+ }
+}
+
+void
+SwLedControlMode8(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed = &(priv->SwLed0);
+
+ switch(LedAction)
+ {
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ if( pLed->bLedBlinkInProgress == false && priv->rtllib->state == RTLLIB_LINKED)
+ {
+ pLed->bLedBlinkInProgress = true;
+
+ pLed->CurrLedState = LED_BLINK_NORMAL;
+ pLed->BlinkTimes = 2;
+
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL));
+ }
+ break;
+
+ case LED_CTL_SITE_SURVEY:
+ if( pLed->bLedBlinkInProgress == false )
+ {
+ pLed->bLedBlinkInProgress = true;
+ pLed->CurrLedState = LED_SCAN_BLINK;
+ pLed->BlinkTimes = 2;
+
+ if( pLed->bLedOn )
+ {
+ pLed->BlinkingLedState = LED_OFF;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_ON_INTERVAL));
+ }
+ else
+ {
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM8_BLINK_OFF_INTERVAL));
+ }
+ }
+ else if(pLed->CurrLedState != LED_SCAN_BLINK)
+ {
+ del_timer_sync(&(pLed->BlinkTimer));
+ pLed->CurrLedState = LED_SCAN_BLINK;
+ pLed->BlinkTimes = 2;
+
+ if( pLed->bLedOn )
+ {
+ pLed->BlinkingLedState = LED_OFF;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_ON_INTERVAL));
+ }
+ else
+ {
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM8_BLINK_OFF_INTERVAL));
+ }
+ }
+ break;
+
+ case LED_CTL_POWER_ON:
+ case LED_CTL_NO_LINK:
+ if( pLed->bLedBlinkInProgress == false )
+ {
+ pLed->bLedBlinkInProgress = true;
+
+ pLed->CurrLedState = LED_NO_LINK_BLINK;
+ pLed->BlinkTimes = 24;
+
+ if( pLed->bLedOn )
+ {
+ pLed->BlinkingLedState = LED_OFF;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_ON_INTERVAL));
+ }
+ else
+ {
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM8_BLINK_OFF_INTERVAL));
+ }
+ }
+ else if(pLed->CurrLedState != LED_SCAN_BLINK && pLed->CurrLedState != LED_NO_LINK_BLINK)
+ {
+ pLed->CurrLedState = LED_NO_LINK_BLINK;
+ pLed->BlinkTimes = 24;
+
+ if( pLed->bLedOn )
+ {
+ pLed->BlinkingLedState = LED_OFF;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM2_BLINK_ON_INTERVAL));
+ }
+ else
+ {
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_CM8_BLINK_OFF_INTERVAL));
+ }
+ }
+ break;
+
+ case LED_CTL_LINK:
+ pLed->CurrLedState = LED_ON;
+ if(pLed->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed->BlinkTimer));
+ pLed->bLedBlinkInProgress = false;
+ }
+ SwLedOn(dev, pLed);
+ break;
+
+ case LED_CTL_POWER_OFF:
+ pLed->CurrLedState = LED_OFF;
+ if(pLed->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed->BlinkTimer));
+ pLed->bLedBlinkInProgress = false;
+ }
+ SwLedOff(dev, pLed);
+ break;
+
+ default:
+ break;
+ }
+}
+
+void
+SwLedControlMode9(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PLED_8190 pLed = &(priv->SwLed0);
+
+ switch(LedAction)
+ {
+ case LED_CTL_TX:
+ case LED_CTL_RX:
+ if( pLed->bLedBlinkInProgress == false )
+ {
+ pLed->bLedBlinkInProgress = true;
+
+ pLed->CurrLedState = LED_BLINK_NORMAL;
+ pLed->BlinkTimes = 2;
+
+ if( pLed->bLedOn )
+ pLed->BlinkingLedState = LED_OFF;
+ else
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_NORMAL_INTERVAL));
+ }
+ break;
+
+ case LED_CTL_SITE_SURVEY:
+ if(priv->rtllib->LinkDetectInfo.bBusyTraffic && priv->rtllib->state == RTLLIB_LINKED)
+ ;
+ else
+ {
+ if( pLed->bLedBlinkInProgress == true )
+ del_timer_sync(&(pLed->BlinkTimer));
+ else
+ pLed->bLedBlinkInProgress = true;
+
+ pLed->CurrLedState = LED_SCAN_BLINK;
+ pLed->BlinkTimes = 24;
+
+ if( pLed->bLedOn )
+ {
+ pLed->BlinkingLedState = LED_OFF;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL));
+ }
+ else
+ {
+ pLed->BlinkingLedState = LED_ON;
+ mod_timer(&(pLed->BlinkTimer), jiffies + MSECS(LED_BLINK_SLOWLY_INTERVAL));
+ }
+ }
+ break;
+
+ case LED_CTL_POWER_ON:
+ case LED_CTL_NO_LINK:
+ case LED_CTL_LINK:
+ if( pLed->bLedBlinkInProgress == false )
+ {
+ pLed->CurrLedState = LED_ON;
+ SwLedOn(dev, pLed);
+ }
+ break;
+
+ case LED_CTL_POWER_OFF:
+ pLed->CurrLedState = LED_OFF;
+ if(pLed->bLedBlinkInProgress)
+ {
+ del_timer_sync(&(pLed->BlinkTimer));
+ pLed->bLedBlinkInProgress = false;
+ }
+ SwLedOff(dev, pLed);
+ break;
+
+ default:
+ break;
+ }
+
+ RT_TRACE(COMP_LED, "LED9 CurrLedState %d\n", pLed->CurrLedState);
+
+}
+
+
+
+void LedControl8192SE(struct net_device *dev, LED_CTL_MODE LedAction)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+
+#ifdef _RTL8192_EXT_PATCH_
+ if((!priv->up)&& (!priv->mesh_up))
+#else
+ if(!priv->up)
+#endif
+ return;
+
+#ifdef TO_DO_LIST
+ if(Adapter->bInHctTest)
+ return;
+#endif
+
+ if( priv->rtllib->eRFPowerState != eRfOn &&
+ (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX ||
+ LedAction == LED_CTL_SITE_SURVEY ||
+ LedAction == LED_CTL_LINK ||
+ LedAction == LED_CTL_NO_LINK||
+ LedAction == LED_CTL_START_TO_LINK ||
+ LedAction == LED_CTL_POWER_ON) )
+ {
+ return;
+ }
+
+ RT_TRACE(COMP_LED, "LedAction %d, \n", LedAction);
+
+ switch(priv->LedStrategy)
+ {
+ case SW_LED_MODE0:
+ break;
+ case SW_LED_MODE1:
+ break;
+ case SW_LED_MODE2:
+ break;
+ case SW_LED_MODE3:
+ break;
+ case SW_LED_MODE4:
+ break;
+ case SW_LED_MODE5:
+ break;
+
+ case SW_LED_MODE6:
+ break;
+
+ case SW_LED_MODE7:
+ SwLedControlMode7(dev, LedAction);
+ break;
+ case SW_LED_MODE8:
+ SwLedControlMode8(dev, LedAction);
+ break;
+
+ case SW_LED_MODE9:
+ SwLedControlMode9(dev, LedAction);
+ break;
+
+ default:
+ break;
+ }
+}
+
+#ifdef TO_DO_LIST
+#ifdef NDIS50_MINIPORT
+void LedBlinkTimerStallCheck(struct net_device *dev)
+{
+}
+
+
+void DoLedTimerStallCheck(PLED_8190 pLed)
+{
+}
+#endif +#endif
+#endif
diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_led.h b/ubuntu/rtl8192se/rtl8192s/r8192S_led.h new file mode 100644 index 000000000000..9467187863f5 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_led.h @@ -0,0 +1,84 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#ifndef __INC_HAL8192SELED_H
+#define __INC_HAL8192SELED_H
+
+
+
+typedef enum _LED_STATE_8190{
+ LED_UNKNOWN = 0,
+ LED_ON = 1,
+ LED_OFF = 2,
+ LED_BLINK_NORMAL = 3,
+ LED_BLINK_SLOWLY = 4,
+ LED_POWER_ON_BLINK = 5,
+ LED_SCAN_BLINK = 6, + LED_NO_LINK_BLINK = 7, + LED_BLINK_StartToBlink = 8,
+ LED_BLINK_TXRX = 9,
+ LED_BLINK_RUNTOP = 10, + LED_BLINK_CAMEO = 11,
+}LED_STATE_8190;
+
+typedef enum _LED_PIN_8190{
+ LED_PIN_GPIO0,
+ LED_PIN_LED0,
+ LED_PIN_LED1
+}LED_PIN_8190;
+
+typedef struct _LED_8190{
+ void * dev;
+
+ LED_PIN_8190 LedPin; +
+ LED_STATE_8190 CurrLedState; + bool bLedOn; +
+ bool bLedBlinkInProgress; +
+ bool bLedSlowBlinkInProgress; + u32 BlinkTimes; + LED_STATE_8190 BlinkingLedState; +
+ struct timer_list BlinkTimer; +} LED_8190, *PLED_8190;
+
+
+
+
+typedef enum _LED_STRATEGY_8190{
+ SW_LED_MODE0, + SW_LED_MODE1, + SW_LED_MODE2, + SW_LED_MODE3, + SW_LED_MODE4, + SW_LED_MODE5, + SW_LED_MODE6, + SW_LED_MODE7, + SW_LED_MODE8, + SW_LED_MODE9, + HW_LED, +}LED_STRATEGY_8190, *PLED_STRATEGY_8190;
+
+
+void InitSwLeds(struct net_device *dev);
+void DeInitSwLeds(struct net_device *dev);
+void LedControl8192SE(struct net_device *dev, LED_CTL_MODE LedAction);
+
+#endif /*__INC_HAL8190PCILED_H*/
diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_mp.c b/ubuntu/rtl8192se/rtl8192s/r8192S_mp.c new file mode 100644 index 000000000000..8bd53961a77f --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_mp.c @@ -0,0 +1,1256 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#ifdef CONFIG_MP +#include "../rtl_core.h" +#include "r8192S_phy.h" +#include "r8192S_phyreg.h" +#include "r8192S_mp.h" + +void rtl8192_init_mp(struct net_device* dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + priv->chan_forced = false; + + priv->bSingleCarrier = false; + priv->RegBoard = 0; + priv->bCckContTx = false; + priv->bOfdmContTx = false; + priv->bStartContTx = false; + priv->RegPaModel = 0; + priv->btMpCckTxPower = 0; + priv->btMpOfdmTxPower = 0; +} + +static bool r8192_MgntIsRateValidForWirelessMode(u8 rate, u8 wirelessmode) +{ + bool bReturn = false; + + switch(wirelessmode) + { + case WIRELESS_MODE_A: + case WIRELESS_MODE_N_5G: + if((rate >= 12) && (rate <= 108) && (rate != 22) && (rate != 44)) + { + bReturn = true; + } + break; + + case WIRELESS_MODE_B: + if( ((rate <= 22) && (rate != 12) && (rate != 18)) || + (rate == 44) ) + { + bReturn = true; + } + break; + + case WIRELESS_MODE_G: + case WIRELESS_MODE_G | WIRELESS_MODE_B: + case WIRELESS_MODE_N_24G: + if((rate >= 2) && (rate <= 108)) + { + bReturn = true; + } + break; + + case WIRELESS_MODE_AUTO: + printk("MgntIsRateValidForWirelessMode(): wirelessmode should not be WIRELESS_MODE_AUTO\n"); + break; + + default: + printk("MgntIsRateValidForWirelessMode(): Unknown wirelessmode: %d\n", wirelessmode); + break; + } + + if(!bReturn) + { + if(wirelessmode&(WIRELESS_MODE_N_24G|WIRELESS_MODE_N_5G)) + { + if((rate>=0x80) && (rate<=MGN_MCS15_SG)) + bReturn = true; + } + } + return bReturn; +} + +inline u8 r8192_is_wireless_b_mode(u16 rate) +{ + if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) ) + return 1; + else return 0; +} + +static void r8192_XmitOnePacket(struct net_device* dev) +{ + struct r8192_priv* priv = rtllib_priv(dev); + struct rtllib_device* ieee = priv->rtllib; + struct sk_buff* skb = rtllib_get_beacon(ieee); + + if (unlikely(!skb)){ + printk("========>error alloc skb\n"); + return; + } + + priv->rtllib->softmac_data_hard_start_xmit(skb, dev, ieee->rate); +} + +int r8192_wx_mp_set_chan(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + int ret = -1; + u8 channel; + + down(&priv->wx_sem); + + channel = *extra; + + rtllib_stop_scan(ieee); + + printk("####RTL819X MP####set channel[1-11] %d\n",channel); + + if((channel > 11) || (channel < 1)) { + up(&priv->wx_sem); + return ret; + } + + priv->rtllib->current_network.channel = channel; + priv->MptChannelToSw = channel; + + priv->chan_forced = false; + MPT_ProSwChannel(dev); + priv->chan_forced = true; + + ret = 0; + up(&priv->wx_sem); + + return ret; + +} + +int r8192_wx_mp_set_txrate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device* ieee = priv->rtllib; + int ret = -1; + u32 data_rate_index = 0; + + down(&priv->wx_sem); + + data_rate_index = *extra; + + printk("####RTL819X MP####set tx rate index %d\n",data_rate_index); + + priv->MptRateIndex = data_rate_index; + + if((data_rate_index > 27) || (data_rate_index < 0)) { + up(&priv->wx_sem); + return ret; + } else if(data_rate_index <= 3) { + ieee->mode = WIRELESS_MODE_B; + } else if (data_rate_index <= 11) { + ieee->mode = WIRELESS_MODE_G; + } else { + ieee->mode = WIRELESS_MODE_N_24G; + } + + MPT_ProSetDataRate819x(dev); + + printk("####RTL819X MP####set tx rate %d\n",ieee->rate); + + ret = 0; + up(&priv->wx_sem); + + return ret; +} + +int r8192_wx_mp_set_txpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int ret = -1; + u8 power_index = 0; + + down(&priv->wx_sem); + + power_index = *extra; + + printk("####RTL819X MP####set tx power index %d\n",power_index); + + if((power_index > 0x3F) || (power_index < 0x00)) { + up(&priv->wx_sem); + return ret; + } + + mpt_ProSetTxPower(dev, power_index); + + ret = 0; + up(&priv->wx_sem); + + return ret; + +} + +int r8192_wx_mp_set_bw(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int ret = -1; + u8 bw_index = 0; + + down(&priv->wx_sem); + + bw_index = *extra; + + printk("####RTL819X MP####set bandwith index %d [0: 20MHz 1: 40MHz]\n",bw_index); + + priv->MptBandWidth = bw_index; + +#if 0 + if((bw_index > 1) || (bw_index < 0)) { + up(&priv->wx_sem); + return ret; + } else if(bw_index == 1) { + HTSetConnectBwMode(priv->rtllib, HT_CHANNEL_WIDTH_20_40, + (priv->rtllib->current_network.channel<=6)?HT_EXTCHNL_OFFSET_UPPER:HT_EXTCHNL_OFFSET_LOWER); + } else { + HTSetConnectBwMode(priv->rtllib, HT_CHANNEL_WIDTH_20, + (priv->rtllib->current_network.channel<=6)?HT_EXTCHNL_OFFSET_UPPER:HT_EXTCHNL_OFFSET_LOWER); + } +#else + MPT_ProSetBandWidth819x(dev); +#endif + + ret = 0; + up(&priv->wx_sem); + + return ret; + +} + + + +int r8192_wx_mp_set_txstart(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + int ret = -1; + u8 start_flag = 0; + + down(&priv->wx_sem); + + start_flag = *extra; + + if(start_flag == 1) { + if (priv->bCckContTx || priv->bOfdmContTx) { + printk("####RTL819X MP####continious Tx is undergoing, please close it first\n"); + ret = -EBUSY; + up(&priv->wx_sem); + return ret; + } + + if(r8192_is_wireless_b_mode(ieee->rate)) { + printk("####RTL819X MP####start cck continious TX, rate:%d\n", ieee->rate); + mpt_StartCckContTx(dev, true); + r8192_XmitOnePacket(dev); + } else { + printk("####RTL819X MP####start ofdm continious TX, rate:%d\n", ieee->rate); + mpt_StartOfdmContTx(dev); + r8192_XmitOnePacket(dev); + } + } else if(start_flag == 2) { + bool bCckContTx = priv->bCckContTx; + bool bOfdmContTx = priv->bOfdmContTx; + + if(bCckContTx && !bOfdmContTx) { + printk("####RTL819X MP####stop cck continious TX\n"); + mpt_StopCckCoNtTx(dev); + } else if (!bCckContTx && bOfdmContTx) { + printk("####RTL819X MP####stop ofdm continious TX\n"); + mpt_StopOfdmContTx(dev); + } else if(!bCckContTx && !bOfdmContTx) { + ; + } else { + printk("####RTL819X MP#### Unexpected case! bCckContTx: %d , bOfdmContTx: %d\n", + bCckContTx, bOfdmContTx); +} + } else { + ret = -1; + up(&priv->wx_sem); + return ret; + } + + + ret = 0; + up(&priv->wx_sem); + + return ret; + +} + +int r8192_wx_mp_set_singlecarrier(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + struct rtllib_device *ieee = priv->rtllib; + int ret = -1; + u8 start_flag = 0; + + if((ieee->rate > 108) || (ieee->rate < 12)) + printk("####RTL819X MP#### we did not do singlecarrier when rate not in [6M-54M] tmp, see StartTesting_SingleCarrierTx to get more\n"); + + down(&priv->wx_sem); + + start_flag = *extra; + + if(start_flag == 1){ + if (priv->bCckContTx || priv->bOfdmContTx || priv->bSingleCarrier){ + printk("####RTL819X MP#### single carrier continious Tx is undergoing, please close it first\n"); + ret = -EBUSY; + up(&priv->wx_sem); + return ret; + } + + printk("####RTL819X MP####start single carrier cck continious TX\n"); + mpt_StartOfdmContTx(dev); + r8192_XmitOnePacket(dev); + + } else if(start_flag == 2) { + if (priv->bCckContTx) { + printk("####RTL819X MP####stop single cck continious TX\n"); + mpt_StopCckCoNtTx(dev); + } + if (priv->bOfdmContTx) { + printk("####RTL819X MP####stop single ofdm continious TX\n"); + mpt_StopOfdmContTx(dev); + } + if (priv->bSingleCarrier) { + printk("####RTL819X MP####stop single carrier mode\n"); + MPT_ProSetSingleCarrier(dev, false); + } + } else { + ret = -1; + up(&priv->wx_sem); + + return ret; + } + + ret = 0; + up(&priv->wx_sem); + + return ret; + +} +int r8192_wx_mp_write_rf(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 ulIoType, INulRegOffset, INulRegValue; + u32 *info_buf = (u32*)(&wrqu->freq.m); + u32 ulRegOffset = info_buf[0]; + u32 ulRegValue = info_buf[1]; + u32 RF_PATH = info_buf[2]; + + down(&priv->wx_sem); + printk("####RTL819X MP####%s :ulRegOffset %x, ulRegValue %x, RF_PATH:%x\n", + __func__, ulRegOffset, ulRegValue, RF_PATH); + + ulIoType = MPT_WRITE_RF; + INulRegOffset = ulRegOffset & bRFRegOffsetMask; + INulRegValue = ulRegValue & bRFRegOffsetMask; + + + priv->MptIoOffset = INulRegOffset; + priv->MptIoValue = INulRegValue; + priv->MptRfPath = RF_PATH; + priv->MptActType = ulIoType; + + mpt_Pro819xIoCallback(dev); + + up(&priv->wx_sem); + return 0; + +} + +int r8192_wx_mp_write_mac(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 *info_buf = (u32*)(&wrqu->freq.m); + u32 ulRegOffset = info_buf[0]; + u32 ulRegValue = info_buf[1]; + u32 ulRegDataWidth = info_buf[2]; + u32 ulIoType = 0; + + down(&priv->wx_sem); + + printk("####RTL819X MP####%s :ulRegOffset %x, ulRegValue %x, ulRegDataWidth:%x\n", + __func__, ulRegOffset, ulRegValue, ulRegDataWidth); + + switch(ulRegDataWidth) + { + case 1: + ulIoType = MPT_WRITE_MAC_1BYTE; + break; + + case 2: + ulIoType = MPT_WRITE_MAC_2BYTE; + break; + case 4: + ulIoType = MPT_WRITE_MAC_4BYTE; + break; + default: + printk("####RTL819X MP####%s :error ulRegDataWidth:%x\n", __func__, ulRegDataWidth); + break; + } + + if(ulIoType != 0){ + priv->MptIoOffset = ulRegOffset; + priv->MptIoValue = ulRegValue; + priv->MptActType = ulIoType; + mpt_Pro819xIoCallback(dev); + } + + up(&priv->wx_sem); + + return 0; + +} + +/*----------------------------------------------------------------------------- + * Function: mpt_StartCckContTx() + * + * Overview: Start CCK Continuous Tx. + * + * Input: PADAPTER pAdapter + * BOOLEAN bScrambleOn + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/16/2007 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +void mpt_StartCckContTx(struct net_device *dev,bool bScrambleOn) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u32 cckrate; + + if(!rtl8192_QueryBBReg(dev, rFPGA0_RFMOD, bCCKEn)) + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, bEnable); + + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMContinueTx, bDisable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleTone, bDisable); + switch(priv->rtllib->rate) + { + case 2: + cckrate = 0; + break; + case 4: + cckrate = 1; + break; + case 11: + cckrate = 2; + break; + case 22: + cckrate = 3; + break; + default: + cckrate = 0; + break; + } + rtl8192_setBBreg(dev, rCCK0_System, bCCKTxRate, cckrate); + + rtl8192_setBBreg(dev, rCCK0_System, bCCKBBMode, 0x2); + rtl8192_setBBreg(dev, rCCK0_System, bCCKScramble, 0x1); + + priv->bCckContTx = true; + priv->bOfdmContTx = false; + +} /* mpt_StartCckContTx */ + +/*----------------------------------------------------------------------------- + * Function: mpt_StartOfdmContTx() + * + * Overview: Start OFDM Continuous Tx. + * + * Input: PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/16/2007 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +void mpt_StartOfdmContTx(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + if(!rtl8192_QueryBBReg(dev, rFPGA0_RFMOD, bOFDMEn)) + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, bEnable); + + rtl8192_setBBreg(dev, rCCK0_System, bCCKBBMode, bDisable); + + rtl8192_setBBreg(dev, rCCK0_System, bCCKScramble, bEnable); + + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMContinueTx, bEnable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleTone, bDisable); + + priv->bCckContTx = false; + priv->bOfdmContTx = true; + +} /* mpt_StartOfdmContTx */ + +/*----------------------------------------------------------------------------- + * Function: mpt_StopCckCoNtTx() + * + * Overview: Stop CCK Continuous Tx. + * + * Input: PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/16/2007 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +void mpt_StopCckCoNtTx(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + priv->bCckContTx = false; + priv->bOfdmContTx = false; + + rtl8192_setBBreg(dev, rCCK0_System, bCCKBBMode, 0x0); + rtl8192_setBBreg(dev, rCCK0_System, bCCKScramble, 0x1); + + rtl8192_setBBreg(dev, rPMAC_Reset, bBBResetB, 0x0); + rtl8192_setBBreg(dev, rPMAC_Reset, bBBResetB, 0x1); + +} /* mpt_StopCckCoNtTx */ + +/*----------------------------------------------------------------------------- + * Function: mpt_StopOfdmContTx() + * + * Overview: Stop 818xB OFDM Continuous Tx. + * + * Input: PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/16/2007 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +void mpt_StopOfdmContTx(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + priv->bCckContTx = false; + priv->bOfdmContTx = false; + + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMContinueTx, bDisable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleTone, bDisable); + mdelay(10); + rtl8192_setBBreg(dev, rPMAC_Reset, bBBResetB, 0x0); + rtl8192_setBBreg(dev, rPMAC_Reset, bBBResetB, 0x1); + +} /* mpt_StopOfdmContTx */ + +/*----------------------------------------------------------------------------- + * Function: mpt_SwitchRfSetting92S + * + * Overview: Change RF Setting when we siwthc channel/rate/BW for 92S series MP. + * + * Input: IN PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series. + * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. + * + *---------------------------------------------------------------------------*/ + void mpt_SwitchRfSetting92S(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u8 ChannelToSw = priv->MptChannelToSw; + u32 ulRateIdx = priv->MptRateIndex; + u32 ulbandwidth = priv->MptBandWidth; + + if (ulbandwidth == BAND_20MHZ_MODE) + { + if (ChannelToSw == 1) + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)0, RF_IPA, 0xFFFFF, 0x0A8F4); + } + else if (ChannelToSw == 11) + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)0, RF_IPA, 0xFFFFF, 0x0F8F5); + } + else + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)0, RF_IPA, 0xFFFFF, 0x0F8F4); + } + } + else + { + if (ChannelToSw == 3) + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)0, RF_IPA, 0xFFFFF, 0x0A8F4); + } + else if (ChannelToSw == 9 || ChannelToSw == 10 || ChannelToSw == 11) + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)0, RF_IPA, 0xFFFFF, 0x0F8F5); + } + else + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)0, RF_IPA, 0xFFFFF, 0x0F8F4); + } + } + + + if (ulRateIdx < MPT_RATE_6M) + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)0, RF_SYN_G2, 0xFFFFF, 0x04440); + else + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)0, RF_SYN_G2, 0xFFFFF, 0x0F200); +} + +/*----------------------------------------------------------------------------- + * Function: mpt_ProSetTxPower() + * + * Overview: Change Tx Power of current channel for + * OID_RT_PRO_SET_TX_POWER_CONTROL. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/16/2007 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +bool mpt_ProSetTxPower( struct net_device *dev, u32 ulTxPower) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u8 CurrChannel = priv->rtllib->current_network.channel; + bool bResult = true; + + CurrChannel = priv->MptChannelToSw; + + if(CurrChannel > 11 || CurrChannel < 1) + { + printk("mpt_ProSetTxPower(): CurrentChannel:%d is not valid\n", CurrChannel); + return false; + } + + if(ulTxPower > MAX_TX_PWR_INDEX_N_MODE) + { + printk("mpt_ProSetTxPower(): TxPWR:%d is invalid\n", ulTxPower); + return false; + } + + if( priv->MptRateIndex >= MPT_RATE_1M && + priv->MptRateIndex <= MPT_RATE_11M ) + { + priv->TxPowerLevelCCK[CurrChannel-1] = (u8)ulTxPower; + + priv->RfTxPwrLevelCck[0][CurrChannel-1] = (u8)ulTxPower; + } + else if(priv->MptRateIndex >= MPT_RATE_6M && + priv->MptRateIndex <= MPT_RATE_MCS15 ) + { + priv->TxPowerLevelOFDM24G[CurrChannel-1] = (u8)ulTxPower; + + priv->RfTxPwrLevelOfdm1T[0][CurrChannel-1] = (u8)ulTxPower; + priv->RfTxPwrLevelOfdm2T[0][CurrChannel-1] = (u8)ulTxPower; + } + + rtl8192_phy_setTxPower(dev,CurrChannel); + + return bResult; + +} /* mpt_ProSetTxPower */ + +/*----------------------------------------------------------------------------- + * Function: mpt_ProSetTxAGCOffset() + * + * Overview: Change Tx AGC Offset + * OID_RT_PRO_SET_TX_AGC_OFFSET. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 08/09/2007 Cosa Create Version 0. + * + *---------------------------------------------------------------------------*/ +bool mpt_ProSetTxAGCOffset(struct net_device *dev, u32 ulTxAGCOffset) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + bool bResult = true; + u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D; + + TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); + TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); + TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); + + if( TxAGCOffset_B > TxAGC_Offset_neg1 || + TxAGCOffset_C > TxAGC_Offset_neg1 || + TxAGCOffset_D > TxAGC_Offset_neg1 ) + { + printk("mpt_ProSetTxAGCOffset(): TxAGCOffset:%d is invalid\n", ulTxAGCOffset); + return false; + } + + priv->AntennaTxPwDiff[0] = TxAGCOffset_B; + priv->AntennaTxPwDiff[1] = TxAGCOffset_C; + priv->AntennaTxPwDiff[2] = TxAGCOffset_D; + + MPT_ProSetTxAGCOffset(dev); + + return bResult; + +} /* mpt_ProSetTxPower */ + +/*----------------------------------------------------------------------------- + * Function: mpt_ProSetTxAGCOffset() + * + * Overview: Change Tx AGC Offset + * OID_RT_PRO_SET_TX_AGC_OFFSET. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 08/09/2007 Cosa Create Version 0. + * + *---------------------------------------------------------------------------*/ +bool mpt_ProSetRxFilter(struct net_device *dev, u32 RCRMode) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + if(RCRMode == 1) + { + priv->MptRCR &= ~(RCR_AAP|RCR_AM|RCR_AB); + priv->MptRCR |= RCR_APM; + write_nic_dword(dev, RCR, priv->MptRCR); + } + else + { + priv->MptRCR |= (RCR_AAP|RCR_APM|RCR_AM|RCR_AB); + write_nic_dword(dev, RCR, priv->MptRCR); + } + + return 1; +} /* mpt_ProSetTxPower */ + +/*----------------------------------------------------------------------------- + * Function: mpt_ProSetModulation() + * + * Overview: Switch wireless mode for OID_RT_PRO_SET_MODULATION. + * + * Input: PADAPTER pAdapter + * ULONG ulWirelessMode + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/16/2007 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +bool mpt_ProSetModulation(struct net_device *dev, u32 ulWirelessMode) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + WIRELESS_MODE WirelessMode; + bool bResult = false; + + switch(ulWirelessMode) + { + case WIRELESS_MODE_A: + WirelessMode = WIRELESS_MODE_A; + break; + + case WIRELESS_MODE_B: + WirelessMode = WIRELESS_MODE_B; + break; + + case WIRELESS_MODE_G: + case WIRELESS_MODE_G |WIRELESS_MODE_B: + WirelessMode = WIRELESS_MODE_G; + break; + + case WIRELESS_MODE_N_24G: + WirelessMode = WIRELESS_MODE_N_24G; + break; + + case WIRELESS_MODE_N_5G: + WirelessMode = WIRELESS_MODE_N_5G; + break; + + case WIRELESS_MODE_AUTO: + default: + bResult = false; + return bResult; + break; + } + + priv->rtllib->mode = WirelessMode; + priv->RegWirelessMode = WirelessMode; + rtl8192_SetWirelessMode(dev, priv->rtllib->mode); + HTUseDefaultSetting(priv->rtllib); + + + if (IS_HARDWARE_TYPE_8192SE(dev)) + { + mpt_SwitchRfSetting92S(dev); + } + + bResult = true; + + return bResult; + +} + +/*----------------------------------------------------------------------------- + * Function: mpt_Pro819xIoCallback() + * + * Overview: Callback function of a workitem for IO. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/16/2007 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +void mpt_Pro819xIoCallback(struct net_device *dev) +{ + + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u32 MptActType = priv->MptActType; + + printk("####RTL819X MP####%s :ulRegOffset %x, ulRegValue %x, MptActType:%x, MptRfPath:%x\n", + __func__, priv->MptIoOffset, priv->MptIoValue, MptActType, priv->MptRfPath); + + switch(MptActType) + { + case MPT_WRITE_MAC_1BYTE: + write_nic_byte(dev, priv->MptIoOffset, (u8)(priv->MptIoValue)); + break; + + case MPT_WRITE_MAC_2BYTE: + write_nic_word(dev, priv->MptIoOffset, (u16)(priv->MptIoValue)); + break; + + case MPT_WRITE_MAC_4BYTE: + write_nic_dword(dev, priv->MptIoOffset, (u32)(priv->MptIoValue)); + break; + + case MPT_WRITE_RF: + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)priv->MptRfPath, + priv->MptIoOffset, bRFRegOffsetMask, priv->MptIoValue); + break; + + default: + break; + } +} + +void MPT_ProSetSingleCarrier(struct net_device *dev, bool ulMode) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + + if(ulMode == 1) { + priv->bSingleCarrier = true; + } else { + priv->bSingleCarrier = false; + } + + if(priv->bSingleCarrier) + { + if(!rtl8192_QueryBBReg(dev, rFPGA0_RFMOD, bOFDMEn)) + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, bEnable); + + rtl8192_setBBreg(dev, rCCK0_System, bCCKBBMode, bDisable); + + rtl8192_setBBreg(dev, rCCK0_System, bCCKScramble, bEnable); + + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMContinueTx, bDisable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleTone, bDisable); + } + else + { + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMContinueTx, bDisable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); + rtl8192_setBBreg(dev, rOFDM1_LSTF, bOFDMSingleTone, bDisable); + mdelay(10); + rtl8192_setBBreg(dev, rPMAC_Reset, bBBResetB, 0x0); + rtl8192_setBBreg(dev, rPMAC_Reset, bBBResetB, 0x1); + } +} + +/*----------------------------------------------------------------------------- + * Function: MPT_ProSetBandWidth819x() + * + * Overview: None + * + * Input: PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/03/2007 Cosa Create Version 0. + * + *---------------------------------------------------------------------------*/ +void MPT_ProSetBandWidth819x(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->rtllib->pHTInfo; + u32 ulbandwidth = priv->MptBandWidth; + + printk("##################MPT_ProSetBandWidth819x() is start. \n"); + /* 2007/06/07 MH Call normal driver API and set 40MHZ mode. */ + if (ulbandwidth == BAND_20MHZ_MODE) { + /* 20 MHZ sub-carrier mode --> dont care. */ + pHTInfo->bCurBW40MHz = false; + pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_EXT; + priv->rtllib->SetBWModeHandler(dev, HT_CHANNEL_WIDTH_20, pHTInfo->CurSTAExtChnlOffset); + } else if (ulbandwidth == BAND_40MHZ_DUPLICATE_MODE) { + /* Sub-Carrier mode is defined in MAC data sheet chapter 12.3. */ + /* 40MHX sub-carrier mode --> duplicate. */ + pHTInfo->bCurBW40MHz = true; + pHTInfo->bCurTxBW40MHz = true; + pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_DEF; + + priv->rtllib->SetBWModeHandler(dev, HT_CHANNEL_WIDTH_20_40, pHTInfo->CurSTAExtChnlOffset); + } else if (ulbandwidth == BAND_40MHZ_LOWER_MODE) { + /* 40MHX sub-carrier mode --> lower mode */ + pHTInfo->bCurBW40MHz = true; + pHTInfo->bCurTxBW40MHz = true; + pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_LOWER; + + /* Extention channel is lower. Current channel must > 3. */ + /*if (pMgntInfo->dot11CurrentChannelNumber < 3) + DbgPrint("Illegal Current_Chl=%d\r\n", pMgntInfo->dot11CurrentChannelNumber); + else + pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, pMgntInfo->dot11CurrentChannelNumber-2);*/ + + priv->rtllib->SetBWModeHandler(dev, HT_CHANNEL_WIDTH_20_40, pHTInfo->CurSTAExtChnlOffset); + } else if (ulbandwidth == BAND_40MHZ_UPPER_MODE) { + /* 40MHX sub-carrier mode --> upper mode */ + pHTInfo->bCurBW40MHz = true; + pHTInfo->bCurTxBW40MHz = true; + pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_UPPER; + + /* Extention channel is upper. Current channel must < 12. */ + /*if (pMgntInfo->dot11CurrentChannelNumber > 12) + DbgPrint("Illegal Current_Chl=%d", pMgntInfo->dot11CurrentChannelNumber); + else + pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, pMgntInfo->dot11CurrentChannelNumber+2);*/ + + priv->rtllib->SetBWModeHandler(dev, HT_CHANNEL_WIDTH_20_40, pHTInfo->CurSTAExtChnlOffset); + } else if (ulbandwidth == BAND_40MHZ_DONTCARE_MODE) { + /* 40MHX sub-carrier mode --> dont care mode */ + pHTInfo->bCurBW40MHz = true; + pHTInfo->bCurTxBW40MHz = true; + pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_LOWER; + + priv->rtllib->SetBWModeHandler(dev, HT_CHANNEL_WIDTH_20_40, pHTInfo->CurSTAExtChnlOffset); + } else { + printk("##################MPT_ProSetBandWidth819x() error BW. \n"); + return; + } + +{ + mpt_SwitchRfSetting92S(dev); + return; + } + + printk("##################MPT_ProSetBandWidth819x() is finished. \n"); +} + +/*----------------------------------------------------------------------------- + * Function: MPT_ProSwChannel() + * + * Overview: Callback function of a work item to switch channel for + * OID_RT_PRO_SET_CHANNEL_DIRECT_CALL + * + * Input: PVOID Context + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/16/2007 MHC Create Version 0. + * 06/07/2007 MHC Normal driver change switch channel handler. + * 09/03/2008 MHC RF channel register for 92S. + * 01/08/2008 MHC For MP verification for 92S,weneed to change setting according + * to SD3 Willis's document. + * + *---------------------------------------------------------------------------*/ +void MPT_ProSwChannel(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u8 ChannelToSw = priv->MptChannelToSw; + u8 eRFPath; + + priv->rtllib->current_network.channel = ChannelToSw; + priv->MptChannelToSw = ChannelToSw; + + if (IS_HARDWARE_TYPE_8192SE(dev)) + { + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rRfChannel, 0x3FF, ChannelToSw); + } + + if (IS_HARDWARE_TYPE_8192SE(dev)) + { + mpt_SwitchRfSetting92S(dev); + } + } + +#ifdef MP_DEVELOP_READY + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + if (IS_HARDWARE_TYPE_8192SE(dev)) + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rRfChannel, 0x3FF, ChannelToSw); + + udelay(100); + } + + + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + if (IS_HARDWARE_TYPE_8192SE(dev)) + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rRfChannel, 0x3FF, ChannelToSw); + + udelay(100); + } +#endif + + /* 2007/06/07 MH Normal driver change sw channel handler. It does not + support SwChnlByDelayHandler ans replace with SwChnlByTimerHandler. */ + priv->rtllib->set_chan(dev, ChannelToSw); + +#if 0 + if(pHalData->CurrentChannel == 14 && !pHalData->bCCKinCH14){ + pHalData->bCCKinCH14 = true; + MPT_CCKTxPowerAdjust(pAdapter,pHalData->bCCKinCH14); + } + else if(pHalData->CurrentChannel != 14 && pHalData->bCCKinCH14){ + pHalData->bCCKinCH14 = false; + MPT_CCKTxPowerAdjust(pAdapter,pHalData->bCCKinCH14); + } +#endif +} /* MPT_ProSwChannel */ + +/*----------------------------------------------------------------------------- + * Function: MPT_ProSetDataRate819x() + * + * Overview: None + * + * Input: PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/03/2007 Cosa Create Version 0. + * + *---------------------------------------------------------------------------*/ +void MPT_ProSetDataRate819x(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u8 DataRate = 0xFF; + u32 ulRateIdx = priv->MptRateIndex; + + + printk("################MPT_ProSetDataRate819x():Rate=%d\n", ulRateIdx); + switch(ulRateIdx) + { + /* CCK rate. */ + case MPT_RATE_1M: DataRate = 2; break; + case MPT_RATE_2M: DataRate = 4; break; + case MPT_RATE_55M: DataRate = 11; break; + case MPT_RATE_11M: DataRate = 22; break; + + /* OFDM rate. */ + case MPT_RATE_6M: DataRate = 12; break; + case MPT_RATE_9M: DataRate = 18; break; + case MPT_RATE_12M: DataRate = 24; break; + case MPT_RATE_18M: DataRate = 36; break; + case MPT_RATE_24M: DataRate = 48; break; + case MPT_RATE_36M: DataRate = 72; break; + case MPT_RATE_48M: DataRate = 96; break; + case MPT_RATE_54M: DataRate = 108; break; + + /* HT rate. */ + case MPT_RATE_MCS0: DataRate = 0x80; break; + case MPT_RATE_MCS1: DataRate = 0x81; break; + case MPT_RATE_MCS2: DataRate = 0x82; break; + case MPT_RATE_MCS3: DataRate = 0x83; break; + case MPT_RATE_MCS4: DataRate = 0x84; break; + case MPT_RATE_MCS5: DataRate = 0x85; break; + case MPT_RATE_MCS6: DataRate = 0x86; break; + case MPT_RATE_MCS7: DataRate = 0x87; break; + case MPT_RATE_MCS8: DataRate = 0x88; break; + case MPT_RATE_MCS9: DataRate = 0x89; break; + case MPT_RATE_MCS10: DataRate = 0x8A; break; + case MPT_RATE_MCS11: DataRate = 0x8B; break; + case MPT_RATE_MCS12: DataRate = 0x8C; break; + case MPT_RATE_MCS13: DataRate = 0x8D; break; + case MPT_RATE_MCS14: DataRate = 0x8E; break; + case MPT_RATE_MCS15: DataRate = 0x8F; break; + case MPT_RATE_LAST: + break; + + default: + break; + } + + { + mpt_SwitchRfSetting92S(dev); + } + +#ifdef MP_DEVELOP_READY + if (IS_HARDWARE_TYPE_8192SE(dev)) + { + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + if (ulbandwidth == BAND_20MHZ_MODE) + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rRfChannel, (BIT11|BIT10), 0x01); + else + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rRfChannel, (BIT11|BIT10), 0x00); + + delay_us(100); + } + } +#endif + + + if(!r8192_MgntIsRateValidForWirelessMode(DataRate, priv->rtllib->mode) && DataRate != 0 ) + { + printk("[MPT]: unknow wmode=%d", priv->rtllib->mode); + } + if (DataRate != 0xFF) + { + printk("[MPT]: Force rate=0x%02x", DataRate); + priv->rtllib->rate = (int)DataRate; + } + +} + +/*----------------------------------------------------------------------------- + * Function: MPT_ProSetTxAGCOffset() + * + * Overview: Set Tx power level for + * OID_RT_PRO_SET_TX_AGC_OFFSET + * + * Input: PVOID Context + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 08/09/2007 Cosa Create Version 0. + * + *---------------------------------------------------------------------------*/ +void MPT_ProSetTxAGCOffset(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); + u32 u4RegValue, TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D; + + TxAGCOffset_B = priv->AntennaTxPwDiff[0]; + TxAGCOffset_C = priv->AntennaTxPwDiff[1]; + TxAGCOffset_D = priv->AntennaTxPwDiff[2]; + + + u4RegValue = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); + rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); + printk("##################MPT_ProSetTxAGCOffset() is finished \n"); +} + +#endif + diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_mp.h b/ubuntu/rtl8192se/rtl8192s/r8192S_mp.h new file mode 100644 index 000000000000..29be7e9d56a4 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_mp.h @@ -0,0 +1,185 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#ifndef __INC_HAL8192S_MP_H +#define __INC_HAL8192S_MP_H + +/*--------------------------Define Parameters-------------------------------*/ + +#define MPT_NOOP 0 +#define MPT_READ_MAC_1BYTE 1 +#define MPT_READ_MAC_2BYTE 2 +#define MPT_READ_MAC_4BYTE 3 +#define MPT_WRITE_MAC_1BYTE 4 +#define MPT_WRITE_MAC_2BYTE 5 +#define MPT_WRITE_MAC_4BYTE 6 +#define MPT_READ_BB_CCK 7 +#define MPT_WRITE_BB_CCK 8 +#define MPT_READ_BB_OFDM 9 +#define MPT_WRITE_BB_OFDM 10 +#define MPT_READ_RF 11 +#define MPT_WRITE_RF 12 +#define MPT_READ_EEPROM_1BYTE 13 +#define MPT_WRITE_EEPROM_1BYTE 14 +#define MPT_READ_EEPROM_2BYTE 15 +#define MPT_WRITE_EEPROM_2BYTE 16 +#define MPT_SET_CSTHRESHOLD 21 +#define MPT_SET_INITGAIN 22 +#define MPT_SWITCH_BAND 23 +#define MPT_SWITCH_CHANNEL 24 +#define MPT_SET_DATARATE 25 +#define MPT_SWITCH_ANTENNA 26 +#define MPT_SET_TX_POWER 27 +#define MPT_SET_CONT_TX 28 +#define MPT_SET_SINGLE_CARRIER 29 +#define MPT_SET_CARRIER_SUPPRESSION 30 + +#define MPT_SET_ANTENNA_GAIN_OFFSET 40 +#define MPT_SET_CRYSTAL_CAP 41 +#define MPT_TRIGGER_RF_THERMAL_METER 42 +#define MPT_SET_SINGLE_TONE 43 +#define MPT_READ_RF_THERMAL_METER 44 +#define MPT_SWITCH_BAND_WIDTH 45 +#define MPT_QUERY_TSSI_VALUE 46 +#define MPT_SET_TX_POWER_ADJUST 47 +#define MPT_DO_TX_POWER_TRACK 48 +#define MPT_QUERY_NIC_TYPE 49 +#define MPT_QUERY_WPS_PUSHED 50 +#define MPT_SET_LED_CONTROL 51 +#define MPT_TX_POWER_TRACK_CONTROL 52 + +#define MPT_WRITE_EFUSE_1BYTE 53 +#define MPT_READ_EFUSE_1BYTE 54 +#define MPT_READ_EFUSE_2BYTE 55 +#define MPT_READ_EFUSE_4BYTE 56 +#define MPT_UPDATE_EFUSE 57 +#define MPT_UPDATE_EFUSE_UTILIZE 58 +#define MPT_UPDATE_AUTOLOAD_STS 59 + +#define MAX_TX_PWR_INDEX_N_MODE 64 +/*--------------------------Define Parameters-------------------------------*/ + +/*------------------------------Define structure----------------------------*/ +/* MP set force data rate base on the definition. */ +typedef enum _MPT_RATE_INDEX{ + /* CCK rate. */ + MPT_RATE_1M = 1, + MPT_RATE_2M, + MPT_RATE_55M, + MPT_RATE_11M, + + /* OFDM rate. */ + MPT_RATE_6M, + MPT_RATE_9M, + MPT_RATE_12M, + MPT_RATE_18M, + MPT_RATE_24M, + MPT_RATE_36M, + MPT_RATE_48M, + MPT_RATE_54M, + + /* HT rate. */ + MPT_RATE_MCS0, + MPT_RATE_MCS1, + MPT_RATE_MCS2, + MPT_RATE_MCS3, + MPT_RATE_MCS4, + MPT_RATE_MCS5, + MPT_RATE_MCS6, + MPT_RATE_MCS7, + MPT_RATE_MCS8, + MPT_RATE_MCS9, + MPT_RATE_MCS10, + MPT_RATE_MCS11, + MPT_RATE_MCS12, + MPT_RATE_MCS13, + MPT_RATE_MCS14, + MPT_RATE_MCS15, + MPT_RATE_LAST + +}MPT_RATE_E, *PMPT_RATE_E; + +typedef enum _MPT_Bandwidth_Switch_Mode{ + BAND_20MHZ_MODE = 0, + BAND_40MHZ_DUPLICATE_MODE = 1, + BAND_40MHZ_LOWER_MODE = 2, + BAND_40MHZ_UPPER_MODE = 3, + BAND_40MHZ_DONTCARE_MODE = 4 +}MPT_BANDWIDTH_MODE_E, *PMPT_BANDWIDTH_MODE_E; + +typedef enum _TxAGC_Offset{ + TxAGC_Offset_0 = 0x00, + TxAGC_Offset_1, + TxAGC_Offset_2, + TxAGC_Offset_3, + TxAGC_Offset_4, + TxAGC_Offset_5, + TxAGC_Offset_6, + TxAGC_Offset_7, + TxAGC_Offset_neg8, + TxAGC_Offset_neg7, + TxAGC_Offset_neg6, + TxAGC_Offset_neg5, + TxAGC_Offset_neg4, + TxAGC_Offset_neg3, + TxAGC_Offset_neg2, + TxAGC_Offset_neg1 +} TxAGC_Offset; +/*------------------------------Define structure----------------------------*/ +void rtl8192_init_mp(struct net_device* dev); +int r8192_wx_mp_set_chan(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int r8192_wx_mp_set_txrate(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int r8192_wx_mp_set_txpower(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int r8192_wx_mp_set_bw(struct net_device *dev,struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int r8192_wx_mp_set_txstart(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int r8192_wx_mp_set_singlecarrier(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int r8192_wx_mp_write_rf(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int r8192_wx_mp_write_mac(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +void mpt_StartCckContTx(struct net_device *dev,bool bScrambleOn); +void mpt_StartOfdmContTx(struct net_device *dev); +void mpt_StopCckCoNtTx(struct net_device *dev); +void mpt_StopOfdmContTx(struct net_device *dev); +void mpt_SwitchRfSetting92S(struct net_device *dev); +bool mpt_ProSetTxPower( struct net_device *dev, u32 ulTxPower); +bool mpt_ProSetTxAGCOffset(struct net_device *dev, u32 ulTxAGCOffset); +bool mpt_ProSetRxFilter(struct net_device *dev, u32 RCRMode); +bool mpt_ProSetRxFilter(struct net_device *dev, u32 RCRMode); +bool mpt_ProSetModulation(struct net_device *dev, u32 ulWirelessMode); +void mpt_Pro819xIoCallback(struct net_device *dev); +void MPT_ProSetSingleCarrier(struct net_device *dev, bool ulMode); +void MPT_ProSetBandWidth819x(struct net_device *dev); +void MPT_ProSwChannel(struct net_device *dev); +void MPT_ProSetDataRate819x(struct net_device *dev); +void MPT_ProSetTxAGCOffset(struct net_device *dev); +#endif diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_phy.c b/ubuntu/rtl8192se/rtl8192s/r8192S_phy.c new file mode 100644 index 000000000000..fbec7a96ff88 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_phy.c @@ -0,0 +1,3527 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#ifdef RTL8192SE
+
+#include "../rtl_core.h"
+#include "../rtl_dm.h"
+#include "r8192S_phy.h"
+#include "r8192S_phyreg.h"
+#include "r8192S_rtl6052.h"
+#include "r8192S_hwimg.h"
+
+#ifdef ENABLE_DOT11D
+#include "../rtllib/dot11d.h"
+#endif
+
+/*---------------------------Define Local Constant---------------------------*/
+#define MAX_PRECMD_CNT 16
+#define MAX_RFDEPENDCMD_CNT 16
+#define MAX_POSTCMD_CNT 16
+
+#define MAX_DOZE_WAITING_TIMES_9x 64
+
+#define PHY_STOP_SWITCH_CLKREQ 0
+/*---------------------------Define Local Constant---------------------------*/
+
+/*------------------------Define global variable-----------------------------*/
+
+#define Rtl819XMAC_Array Rtl8192SEMAC_2T_Array
+#define Rtl819XAGCTAB_Array Rtl8192SEAGCTAB_Array
+#define Rtl819XPHY_REG_Array Rtl8192SEPHY_REG_2T2RArray
+#define Rtl819XPHY_REG_to1T1R_Array Rtl8192SEPHY_ChangeTo_1T1RArray
+#define Rtl819XPHY_REG_to1T2R_Array Rtl8192SEPHY_ChangeTo_1T2RArray
+#define Rtl819XPHY_REG_to2T2R_Array Rtl8192SEPHY_ChangeTo_2T2RArray
+#define Rtl819XPHY_REG_Array_PG Rtl8192SEPHY_REG_Array_PG
+#define Rtl819XRadioA_Array Rtl8192SERadioA_1T_Array
+#define Rtl819XRadioB_Array Rtl8192SERadioB_Array
+#define Rtl819XRadioB_GM_Array Rtl8192SERadioB_GM_Array
+#define Rtl819XRadioA_to1T_Array Rtl8192SERadioA_to1T_Array
+#define Rtl819XRadioA_to2T_Array Rtl8192SERadioA_to2T_Array
+
+/*------------------------Define local variable------------------------------*/
+#if 0
+static u32 RF_CHANNEL_TABLE_ZEBRA[]={
+ 0,
+ 0x085c, + 0x08dc, + 0x095c, + 0x09dc, + 0x0a5c, + 0x0adc, + 0x0b5c, + 0x0bdc, + 0x0c5c, + 0x0cdc, + 0x0d5c, + 0x0ddc, + 0x0e5c, + 0x0f72, +};
+#endif
+
+/*------------------------Define local variable------------------------------*/
+
+
+/*--------------------Define export function prototype-----------------------*/
+/*--------------------Define export function prototype-----------------------*/
+
+
+/*---------------------Define local function prototype-----------------------*/
+
+static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
+static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
+
+static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
+static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
+static u32 phy_CalculateBitShift(u32 BitMask);
+static bool phy_BB8190_Config_HardCode(struct net_device* dev);
+static bool phy_BB8192S_Config_ParaFile(struct net_device* dev);
+
+static bool phy_ConfigMACWithHeaderFile(struct net_device* dev);
+
+static bool phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
+
+static bool phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
+
+static bool phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev,u8 ConfigType);
+
+static void phy_InitBBRFRegisterDefinition(struct net_device* dev);
+static bool phy_SetSwChnlCmdArray( SwChnlCmd* CmdTable,
+ u32 CmdTableIdx,
+ u32 CmdTableSz,
+ SwChnlCmdID CmdID,
+ u32 Para1,
+ u32 Para2,
+ u32 msDelay );
+
+static bool phy_SwChnlStepByStep(
+ struct net_device* dev,
+ u8 channel,
+ u8 *stage,
+ u8 *step,
+ u32 *delay
+ );
+
+static void phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
+
+static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
+static bool phy_SetRFPowerState8192SE(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
+static void phy_CheckEphySwitchReady( struct net_device* dev);
+
+static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx);
+void rtl8192_SetFwCmdIOCallback(struct net_device* dev);
+
+
+/*---------------------Define local function prototype-----------------------*/
+
+
+/*----------------------------Function Body----------------------------------*/
+u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
+{
+
+ u32 ReturnValue = 0, OriginalValue, BitShift;
+
+#if (DISABLE_BB_RF == 1)
+ return 0;
+#endif
+
+ RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
+
+ OriginalValue = read_nic_dword(dev, RegAddr);
+
+ BitShift = phy_CalculateBitShift(BitMask);
+ ReturnValue = (OriginalValue & BitMask) >> BitShift;
+
+ RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
+ return (ReturnValue);
+}
+
+void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
+{
+ u32 OriginalValue, BitShift, NewValue;
+
+#if (DISABLE_BB_RF == 1)
+ return;
+#endif
+
+
+ {
+ if(BitMask!= bMaskDWord)
+ { + OriginalValue = read_nic_dword(dev, RegAddr);
+ BitShift = phy_CalculateBitShift(BitMask);
+ NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
+ write_nic_dword(dev, RegAddr, NewValue);
+ }else
+ write_nic_dword(dev, RegAddr, Data);
+ }
+
+ return;
+}
+
+
+u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
+{
+ u32 Original_Value, Readback_Value, BitShift; + struct r8192_priv *priv = rtllib_priv(dev);
+ unsigned long flags;
+
+#if (DISABLE_BB_RF == 1)
+ return 0;
+#endif
+
+ RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
+
+ if (!((priv->rf_pathmap >> eRFPath) & 0x1))
+ return 0;
+
+ if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
+ return 0;
+
+ spin_lock_irqsave(&priv->rf_lock, flags);
+ if (priv->Rf_Mode == RF_OP_By_FW)
+ {
+ Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
+ }
+ else
+ {
+ Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
+ }
+
+ BitShift = phy_CalculateBitShift(BitMask);
+ Readback_Value = (Original_Value & BitMask) >> BitShift;
+ spin_unlock_irqrestore(&priv->rf_lock, flags);
+
+
+ return (Readback_Value);
+}
+
+
+void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
+{
+
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u32 Original_Value, BitShift, New_Value; + unsigned long flags;
+#if (DISABLE_BB_RF == 1)
+ return;
+#endif
+
+ RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
+ RegAddr, BitMask, Data, eRFPath);
+
+ if (!((priv->rf_pathmap >> eRFPath) & 0x1))
+ return ;
+ if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
+ {
+ return;
+ }
+
+ spin_lock_irqsave(&priv->rf_lock, flags);
+ if (priv->Rf_Mode == RF_OP_By_FW)
+ {
+ if (BitMask != bRFRegOffsetMask) + {
+ Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
+ BitShift = phy_CalculateBitShift(BitMask);
+ New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
+
+ phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
+ }
+ else
+ phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
+ }
+ else
+ {
+ if (BitMask != bRFRegOffsetMask) + {
+ Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
+ BitShift = phy_CalculateBitShift(BitMask);
+ New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
+
+ phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
+ }
+ else
+ phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
+
+ }
+ spin_unlock_irqrestore(&priv->rf_lock, flags);
+ RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
+ RegAddr, BitMask, Data, eRFPath);
+
+}
+
+static u32
+phy_FwRFSerialRead(
+ struct net_device* dev,
+ RF90_RADIO_PATH_E eRFPath,
+ u32 Offset )
+{
+ u32 retValue = 0;
+#if 0
+ u32 Data = 0;
+ u8 time = 0;
+ Data |= ((Offset&0xFF)<<12);
+ Data |= ((eRFPath&0x3)<<20);
+ Data |= 0x80000000;
+ while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
+ {
+ if (time++ < 100)
+ {
+ delay_us(10);
+ }
+ else
+ break;
+ }
+ PlatformIOWrite4Byte(dev, QPNR, Data);
+ while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
+ {
+ if (time++ < 100)
+ {
+ delay_us(10);
+ }
+ else
+ return (0);
+ }
+ retValue = PlatformIORead4Byte(dev, RF_DATA);
+#endif
+ return (retValue);
+
+} /* phy_FwRFSerialRead */
+
+static void
+phy_FwRFSerialWrite(
+ struct net_device* dev,
+ RF90_RADIO_PATH_E eRFPath,
+ u32 Offset,
+ u32 Data )
+{
+#if 0
+ u8 time = 0;
+ DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
+
+ Data |= ((Offset&0xFF)<<12);
+ Data |= ((eRFPath&0x3)<<20);
+ Data |= 0x400000;
+ Data |= 0x80000000;
+
+ while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
+ {
+ if (time++ < 100)
+ {
+ delay_us(10);
+ }
+ else
+ break;
+ }
+ PlatformIOWrite4Byte(dev, QPNR, Data);
+#endif
+} /* phy_FwRFSerialWrite */
+
+#if (RTL92SE_FPGA_VERIFY == 1)
+static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
+{
+
+ u32 retValue = 0;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
+ u32 NewOffset;
+
+ Offset &= 0x3f;
+
+ if( priv->rf_chip == RF_8256 ||
+ priv->rf_chip == RF_8225 ||
+ priv->rf_chip == RF_6052)
+ {
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); +
+ if(Offset>=31)
+ {
+ priv->RFReadPageCnt[2]++; + priv->RfReg0Value[eRFPath] |= 0x140;
+
+ rtl8192_setBBreg(dev,
+ pPhyReg->rf3wireOffset,
+ bMaskDWord,
+ (priv->RfReg0Value[eRFPath] << 16) );
+
+ NewOffset = Offset - 30;
+
+ }else if(Offset>=16)
+ {
+ priv->RFReadPageCnt[1]++; + priv->RfReg0Value[eRFPath] |= 0x100;
+ priv->RfReg0Value[eRFPath] &= (~0x40);
+
+ rtl8192_setBBreg(dev,
+ pPhyReg->rf3wireOffset,
+ bMaskDWord,
+ (priv->RfReg0Value[eRFPath] << 16) );
+
+ NewOffset = Offset - 15;
+ }
+ else
+ {
+ priv->RFReadPageCnt[0]++; + NewOffset = Offset;
+ }
+ }
+ else
+ NewOffset = Offset;
+
+#if (RTL92SE_FPGA_VERIFY == 1)
+ {
+ u32 temp1, temp2;
+
+ temp1 = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0xffffffff);
+ temp2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, 0xffffffff);
+ temp2 = temp2 & (~bLSSIReadAddress) | (NewOffset<<24) | bLSSIReadEdge;
+
+ rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, 0xffffffff, temp1&(~bLSSIReadEdge));
+ msleep(1);
+ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, 0xffffffff, temp2);
+ msleep(1);
+ rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, 0xffffffff, temp1|bLSSIReadEdge);
+ msleep(1);
+
+ }
+#else
+ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
+
+ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
+ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
+#endif
+
+ mdelay(1);
+
+ retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
+
+ if( priv->rf_chip == RF_8256 ||
+ priv->rf_chip == RF_8225 ||
+ priv->rf_chip == RF_6052)
+ {
+ if (Offset >= 0x10)
+ {
+ priv->RfReg0Value[eRFPath] &= 0xebf;
+
+ rtl8192_setBBreg(
+ dev,
+ pPhyReg->rf3wireOffset,
+ bMaskDWord,
+ (priv->RfReg0Value[eRFPath] << 16) );
+ }
+
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf); + }
+
+ return retValue;
+}
+
+
+static void
+phy_RFSerialWrite(
+ struct net_device* dev,
+ RF90_RADIO_PATH_E eRFPath,
+ u32 Offset,
+ u32 Data
+ )
+{
+ u32 DataAndAddr = 0;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
+ u32 NewOffset;
+
+ Offset &= 0x3f;
+
+ PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
+
+ if( priv->rf_chip == RF_8256 ||
+ priv->rf_chip == RF_8225 ||
+ priv->rf_chip == RF_6052)
+ {
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); +
+ if(Offset>=31)
+ {
+ priv->RFWritePageCnt[2]++; + priv->RfReg0Value[eRFPath] |= 0x140;
+
+ rtl8192_setBBreg(dev,
+ pPhyReg->rf3wireOffset,
+ bMaskDWord,
+ (priv->RfReg0Value[eRFPath] << 16) );
+
+ NewOffset = Offset - 30;
+
+ }else if(Offset>=16)
+ {
+ priv->RFWritePageCnt[1]++; + priv->RfReg0Value[eRFPath] |= 0x100;
+ priv->RfReg0Value[eRFPath] &= (~0x40);
+
+
+ rtl8192_setBBreg(dev,
+ pPhyReg->rf3wireOffset,
+ bMaskDWord,
+ (priv->RfReg0Value[eRFPath] << 16) );
+
+ NewOffset = Offset - 15;
+ }
+ else
+ {
+ priv->RFWritePageCnt[0]++; + NewOffset = Offset;
+ }
+ }
+ else
+ NewOffset = Offset;
+
+ DataAndAddr = (Data<<16) | (NewOffset&0x3f);
+
+ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
+
+
+ if(Offset==0x0)
+ priv->RfReg0Value[eRFPath] = Data;
+
+ if( priv->rf_chip == RF_8256 ||
+ priv->rf_chip == RF_8225 ||
+ priv->rf_chip == RF_6052)
+ {
+ if (Offset >= 0x10)
+ {
+ if(Offset != 0)
+ {
+ priv->RfReg0Value[eRFPath] &= 0xebf;
+ rtl8192_setBBreg(
+ dev,
+ pPhyReg->rf3wireOffset,
+ bMaskDWord,
+ (priv->RfReg0Value[eRFPath] << 16) );
+ }
+ }
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf); + }
+
+}
+#else
+static u32
+phy_RFSerialRead(
+ struct net_device* dev,
+ RF90_RADIO_PATH_E eRFPath,
+ u32 Offset
+ )
+{
+
+ u32 retValue = 0;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
+ u32 NewOffset;
+ u32 tmplong,tmplong2;
+ u8 RfPiEnable=0;
+#if 0
+ if(priv->rf_chip == RF_8225 && Offset > 0x24) + return retValue;
+ if(priv->rf_chip == RF_8256 && Offset > 0x2D) + return retValue;
+#endif
+ Offset &= 0x3f;
+
+ NewOffset = Offset;
+
+ tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
+ if(eRFPath == RF90_PATH_A)
+ tmplong2 = tmplong;
+ else
+ tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
+ tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; +
+ rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
+ udelay(1000);
+
+ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
+ udelay(1000);
+
+ rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
+
+ if(eRFPath == RF90_PATH_A)
+ RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
+ else if(eRFPath == RF90_PATH_B)
+ RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
+
+ if(RfPiEnable)
+ { + retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
+ }
+ else
+ { + retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
+ }
+
+ retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
+
+ return retValue;
+
+}
+
+static void
+phy_RFSerialWrite(
+ struct net_device* dev,
+ RF90_RADIO_PATH_E eRFPath,
+ u32 Offset,
+ u32 Data
+ )
+{
+ u32 DataAndAddr = 0;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
+ u32 NewOffset;
+
+#if 0
+ if(priv->rf_chip == RF_8225 && Offset > 0x24) + return;
+ if(priv->rf_chip == RF_8256 && Offset > 0x2D) + return;
+#endif
+
+ Offset &= 0x3f;
+
+ PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
+
+ NewOffset = Offset;
+
+ DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; +
+ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
+
+}
+
+#endif
+
+static u32 phy_CalculateBitShift(u32 BitMask)
+{
+ u32 i;
+
+ for(i=0; i<=31; i++)
+ {
+ if ( ((BitMask>>i) & 0x1 ) == 1)
+ break;
+ }
+
+ return (i);
+}
+
+
+extern bool PHY_MACConfig8192S(struct net_device* dev)
+{
+ bool rtStatus = true;
+
+#if RTL8190_Download_Firmware_From_Header
+ rtStatus = phy_ConfigMACWithHeaderFile(dev);
+#else
+
+ RT_TRACE(COMP_INIT, "Read MACREG.txt\n");
+#endif
+ return (rtStatus == true) ? 1:0;
+
+}
+
+extern bool
+PHY_BBConfig8192S(struct net_device* dev)
+{
+ bool rtStatus = true;
+ u8 PathMap = 0, index = 0, rf_num = 0;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 bRegHwParaFile = 1;
+
+ phy_InitBBRFRegisterDefinition(dev);
+
+ switch(bRegHwParaFile)
+ {
+ case 0:
+ phy_BB8190_Config_HardCode(dev);
+ break;
+
+ case 1:
+ rtStatus = phy_BB8192S_Config_ParaFile(dev);
+ break;
+
+ case 2:
+ phy_BB8190_Config_HardCode(dev);
+ phy_BB8192S_Config_ParaFile(dev);
+ break;
+
+ default:
+ phy_BB8190_Config_HardCode(dev);
+ break;
+ }
+
+ PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
+ rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
+ priv->rf_pathmap = PathMap;
+ for(index = 0; index<4; index++)
+ {
+ if((PathMap>>index)&0x1)
+ rf_num++;
+ }
+
+ if((priv->rf_type==RF_1T1R && rf_num!=1) ||
+ (priv->rf_type==RF_1T2R && rf_num!=2) ||
+ (priv->rf_type==RF_2T2R && rf_num!=2) ||
+ (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
+ (priv->rf_type==RF_2T4R && rf_num!=4))
+ {
+ RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
+ }
+ return rtStatus;
+}
+
+extern bool
+PHY_RFConfig8192S(struct net_device* dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool rtStatus = true;
+
+
+ if (IS_HARDWARE_TYPE_8192SE(dev))
+ priv->rf_chip = RF_6052;
+
+ switch(priv->rf_chip)
+ {
+ case RF_8225:
+ case RF_6052:
+ rtStatus = PHY_RF6052_Config(dev);
+ break;
+
+ case RF_8256:
+ break;
+
+ case RF_8258:
+ break;
+
+ case RF_PSEUDO_11N:
+ break;
+ default:
+ break;
+ }
+
+ return rtStatus;
+}
+
+
+static bool
+phy_BB8190_Config_HardCode(struct net_device* dev)
+{
+ return true;
+}
+
+
+static bool
+phy_BB8192S_Config_ParaFile(struct net_device* dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool rtStatus = true;
+
+ RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
+
+#if RTL8190_Download_Firmware_From_Header
+ if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
+ priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
+ {
+ rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
+ if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
+ { + rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
+ }
+ }else
+ rtStatus = false;
+#else
+ RT_TRACE(COMP_INIT, "RF_Type == %d\n", priv->rf_type);
+ if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
+ priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
+ {
+ rtStatus = phy_ConfigBBWithParaFile(dev, (char* )&szBBRegFile);
+ if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
+ { + if(priv->rf_type == RF_1T1R)
+ rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T1RFile);
+ else if(priv->rf_type == RF_1T2R)
+ rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T2RFile);
+ }
+
+ }else
+ rtStatus = false;
+#endif
+
+ if(rtStatus != true){
+ RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
+ goto phy_BB8190_Config_ParaFile_Fail;
+ }
+
+ if (priv->AutoloadFailFlag == false)
+ {
+ priv->pwrGroupCnt = 0;
+
+#if RTL8190_Download_Firmware_From_Header
+ rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
+#else
+ rtStatus = phy_ConfigBBWithPgParaFile(dev, (char* )&szBBRegPgFile);
+#endif
+ }
+ if(rtStatus != true){
+ RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
+ goto phy_BB8190_Config_ParaFile_Fail;
+ }
+
+#if RTL8190_Download_Firmware_From_Header
+ rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
+#else
+ RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile AGC_TAB.txt\n");
+ rtStatus = phy_ConfigBBWithParaFile(dev, (char* )&szAGCTableFile);
+#endif
+
+ if(rtStatus != true){
+ printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
+ goto phy_BB8190_Config_ParaFile_Fail;
+ }
+
+
+#if 0 + if(pHalData->VersionID > VERSION_8190_BD)
+ {
+ u4RegValue = ( pHalData->AntennaTxPwDiff[2]<<8 |
+ pHalData->AntennaTxPwDiff[1]<<4 |
+ pHalData->AntennaTxPwDiff[0]);
+
+ PHY_SetBBReg(dev, rFPGA0_TxGainStage,
+ (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
+
+ u4RegValue = pHalData->CrystalCap;
+ PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
+
+ }
+#endif
+
+ priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
+
+
+phy_BB8190_Config_ParaFile_Fail:
+ return rtStatus;
+}
+
+static bool
+phy_ConfigMACWithHeaderFile(struct net_device* dev)
+{
+ u32 i = 0;
+ u32 ArrayLength = 0;
+ u32* ptrArray;
+
+ /*if(dev->bInHctTest)
+ {
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
+ ArrayLength = MACPHY_ArrayLengthDTM;
+ ptrArray = Rtl819XMACPHY_ArrayDTM;
+ }
+ else if(pHalData->bTXPowerDataReadFromEEPORM)
+ {
+
+ }else*/
+ { + RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
+ ArrayLength = MAC_2T_ArrayLength;
+ ptrArray = Rtl819XMAC_Array;
+ }
+
+ /*for(i = 0 ;i < ArrayLength;i=i+3){
+ RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
+ if(ptrArray[i] == 0x318)
+ {
+ ptrArray[i+2] = 0x00000800;
+ }
+ PHY_SetBBReg(dev, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
+ }*/
+ for(i = 0 ;i < ArrayLength;i=i+2){ + write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
+ }
+ return true;
+}
+
+
+static bool
+phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
+{
+ int i;
+ u32* Rtl819XPHY_REGArray_Table;
+ u32* Rtl819XAGCTAB_Array_Table;
+ u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
+ /*if(dev->bInHctTest)
+ {
+
+ AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
+ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
+
+ if(pHalData->RF_Type == RF_2T4R)
+ {
+ PHY_REGArrayLen = PHY_REGArrayLengthDTM;
+ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
+ }
+ else if (pHalData->RF_Type == RF_1T2R)
+ {
+ PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
+ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
+ }
+
+ }
+ else
+ */
+ AGCTAB_ArrayLen = AGCTAB_ArrayLength;
+ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
+ PHY_REGArrayLen = PHY_REG_2T2RArrayLength; + Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
+
+ if(ConfigType == BaseBand_Config_PHY_REG)
+ {
+ for(i=0;i<PHY_REGArrayLen;i=i+2)
+ {
+ if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
+ mdelay(50);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
+ mdelay(5);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
+ mdelay(1);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
+ udelay(50);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
+ udelay(5);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
+ udelay(1);
+#ifdef ECS_T20_INIT_DELAY
+ udelay(1);
+#endif
+ rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
+
+ }
+ }
+ else if(ConfigType == BaseBand_Config_AGC_TAB){
+ for(i=0;i<AGCTAB_ArrayLen;i=i+2)
+ {
+ rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
+#ifdef ECS_T20_INIT_DELAY
+ udelay(1);
+#endif
+ }
+ }
+ return true;
+}
+
+
+static bool
+phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
+{
+ int i;
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u32* Rtl819XPHY_REGArraytoXTXR_Table;
+ u16 PHY_REGArraytoXTXRLen;
+
+ if(priv->rf_type == RF_1T1R)
+ {
+ Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
+ PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
+ }
+ else if(priv->rf_type == RF_1T2R)
+ {
+ Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
+ PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
+ }
+ else
+ {
+ return false;
+ }
+
+ if(ConfigType == BaseBand_Config_PHY_REG)
+ {
+ for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
+ {
+ if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
+ mdelay(50);
+ else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
+ mdelay(5);
+ else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
+ mdelay(1);
+ else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
+ udelay(50);
+ else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
+ udelay(5);
+ else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
+ udelay(1);
+ rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
+ }
+ }
+ else {
+ RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
+ }
+ return true;
+}
+
+void
+storePwrIndexDiffRateOffset(
+ struct net_device* dev,
+ u32 RegAddr,
+ u32 BitMask,
+ u32 Data
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ if(RegAddr == rTxAGC_Rate18_06)
+ {
+ priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][0] = Data;
+ }
+ if(RegAddr == rTxAGC_Rate54_24)
+ {
+ priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][1] = Data;
+ }
+ if(RegAddr == rTxAGC_CCK_Mcs32)
+ {
+ priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][6] = Data;
+ }
+ if(RegAddr == rTxAGC_Mcs03_Mcs00)
+ {
+ priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][2] = Data;
+ }
+ if(RegAddr == rTxAGC_Mcs07_Mcs04)
+ {
+ priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][3] = Data;
+ }
+ if(RegAddr == rTxAGC_Mcs11_Mcs08)
+ {
+ priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][4] = Data;
+ }
+ if(RegAddr == rTxAGC_Mcs15_Mcs12)
+ {
+ priv->MCSTxPowerLevelOriginalOffset[priv->pwrGroupCnt][5] = Data;
+ priv->pwrGroupCnt++;
+ }
+}
+
+static bool
+phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
+{
+ int i;
+ u32* Rtl819XPHY_REGArray_Table_PG;
+ u16 PHY_REGArrayPGLen;
+
+ PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
+ Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
+
+ if(ConfigType == BaseBand_Config_PHY_REG)
+ {
+ for(i=0;i<PHY_REGArrayPGLen;i=i+3)
+ {
+ if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
+ mdelay(50);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
+ mdelay(5);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
+ mdelay(1);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
+ udelay(50);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
+ udelay(5);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
+ udelay(1);
+ storePwrIndexDiffRateOffset(dev, Rtl819XPHY_REGArray_Table_PG[i],
+ Rtl819XPHY_REGArray_Table_PG[i+1],
+ Rtl819XPHY_REGArray_Table_PG[i+2]);
+ rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
+ }
+ }
+ else{
+ RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
+ }
+ return true;
+
+} /* phy_ConfigBBWithPgHeaderFile */
+
+RT_STATUS rtl8192_phy_configRFPABiascurrent(struct net_device *dev, RF90_RADIO_PATH_E eRFPath)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ RT_STATUS rtStatus = RT_STATUS_SUCCESS;
+ u32 tmpval=0;
+
+ if(priv->IC_Class != IC_INFERIORITY_A)
+ {
+ tmpval = rtl8192_phy_QueryRFReg(dev, eRFPath, RF_IPA, 0xf);
+ rtl8192_phy_SetRFReg(dev, eRFPath, RF_IPA, 0xf, tmpval+1);
+ }
+
+ return rtStatus;
+}
+
+u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ int i;
+ bool rtStatus = true;
+ u32 *Rtl819XRadioA_Array_Table;
+ u32 *Rtl819XRadioB_Array_Table;
+ u16 RadioA_ArrayLen,RadioB_ArrayLen;
+
+ RadioA_ArrayLen = RadioA_1T_ArrayLength;
+ Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
+
+ if(priv->rf_type == RF_2T2R_GREEN)
+ {
+ Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
+ RadioB_ArrayLen = RadioB_GM_ArrayLength;
+ }
+ else
+ {
+ Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
+ RadioB_ArrayLen = RadioB_ArrayLength;
+ }
+
+
+ RT_TRACE(COMP_INIT, "PHY_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath);
+ rtStatus = true;
+
+ switch(eRFPath){
+ case RF90_PATH_A:
+ for(i = 0;i<RadioA_ArrayLen; i=i+2)
+ {
+ if(Rtl819XRadioA_Array_Table[i] == 0xfe)
+ { + mdelay(50);
+ }
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
+ mdelay(5);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
+ mdelay(1);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
+ udelay(50);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
+ udelay(5);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
+ udelay(1);
+ else {
+ rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i],
+ bMask20Bits, Rtl819XRadioA_Array_Table[i+1]);
+ }
+ }
+ rtl8192_phy_configRFPABiascurrent(dev, eRFPath);
+ break;
+ case RF90_PATH_B:
+ for(i = 0;i<RadioB_ArrayLen; i=i+2){
+ if(Rtl819XRadioB_Array_Table[i] == 0xfe)
+ { + mdelay(50);
+ }
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
+ mdelay(5);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
+ mdelay(1);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
+ udelay(50);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
+ udelay(5);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
+ udelay(1);
+ else
+ {
+ rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bMask20Bits, Rtl819XRadioB_Array_Table[i+1]);
+ }
+#ifdef ECS_T20_INIT_DELAY
+ udelay(1);
+#endif
+ }
+ break;
+ case RF90_PATH_C:
+ break;
+ case RF90_PATH_D:
+ break;
+ default:
+ break;
+ }
+ return rtStatus;
+
+}
+
+bool rtl8192_phy_checkBBAndRF(
+ struct net_device* dev,
+ HW90_BLOCK_E CheckBlock,
+ RF90_RADIO_PATH_E eRFPath
+ )
+{
+ bool rtStatus = true;
+ u32 i, CheckTimes = 4,ulRegRead = 0;
+ u32 WriteAddr[4];
+ u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
+
+ WriteAddr[HW90_BLOCK_MAC] = 0x100;
+ WriteAddr[HW90_BLOCK_PHY0] = 0x900;
+ WriteAddr[HW90_BLOCK_PHY1] = 0x800;
+ WriteAddr[HW90_BLOCK_RF] = 0x3;
+
+ for(i=0 ; i < CheckTimes ; i++)
+ {
+
+ switch(CheckBlock)
+ {
+ case HW90_BLOCK_MAC:
+ RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
+ break;
+
+ case HW90_BLOCK_PHY0:
+ case HW90_BLOCK_PHY1:
+ write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
+ ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
+ break;
+
+ case HW90_BLOCK_RF:
+ WriteData[i] &= 0xfff;
+ rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask20Bits, WriteData[i]);
+ mdelay(10);
+ ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
+ mdelay(10);
+ break;
+
+ default:
+ rtStatus = false;
+ break;
+ }
+
+
+ if(ulRegRead != WriteData[i])
+ {
+ RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
+ rtStatus = false;
+ break;
+ }
+ }
+
+ return rtStatus;
+}
+
+#ifdef TO_DO_LIST
+void
+PHY_SetRFPowerState8192SUsb(
+ struct net_device* dev,
+ RF_POWER_STATE RFPowerState
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool WaitShutDown = false;
+ u32 DWordContent;
+ u8 eRFPath;
+ BB_REGISTER_DEFINITION_T *pPhyReg;
+
+ if(priv->SetRFPowerStateInProgress == true)
+ return;
+
+ priv->SetRFPowerStateInProgress = true;
+
+
+ if(RFPowerState==RF_SHUT_DOWN)
+ {
+ RFPowerState=RF_OFF;
+ WaitShutDown=true;
+ }
+
+
+ priv->RFPowerState = RFPowerState;
+ switch( priv->rf_chip )
+ {
+ case RF_8225:
+ case RF_6052:
+ switch( RFPowerState )
+ {
+ case RF_ON:
+ break;
+
+ case RF_SLEEP:
+ break;
+
+ case RF_OFF:
+ break;
+ }
+ break;
+
+ case RF_8256:
+ switch( RFPowerState )
+ {
+ case RF_ON:
+ break;
+
+ case RF_SLEEP:
+ break;
+
+ case RF_OFF:
+ for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
+ {
+ if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
+ continue;
+
+ pPhyReg = &priv->PHYRegDef[eRFPath];
+ rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
+ rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
+ }
+ break;
+ }
+ break;
+
+ case RF_8258:
+ break;
+ } +
+ priv->SetRFPowerStateInProgress = false;
+}
+#endif
+
+void PHY_GetHWRegOriginalValue(struct net_device* dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+#if 0 + priv->MCSTxPowerLevelOriginalOffset[0] =
+ rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
+ priv->MCSTxPowerLevelOriginalOffset[1] =
+ rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
+ priv->MCSTxPowerLevelOriginalOffset[2] =
+ rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
+ priv->MCSTxPowerLevelOriginalOffset[3] =
+ rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
+ priv->MCSTxPowerLevelOriginalOffset[4] =
+ rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
+ priv->MCSTxPowerLevelOriginalOffset[5] =
+ rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
+
+ priv->CCKTxPowerLevelOriginalOffset=
+ rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
+ RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
+ priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
+ priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
+ priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
+#endif
+
+ priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
+ priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
+ priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
+ priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
+ RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
+ priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
+ priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
+
+ priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
+ priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
+ RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
+ rOFDM0_RxDetector3, priv->framesync);
+
+}
+
+
+
+static void phy_InitBBRFRegisterDefinition( struct net_device* dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; + priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; + priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; + priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; +
+ priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; + priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; + priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; + priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; +
+ priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; +
+ priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; + priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; +
+ priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; + priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
+ priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
+ priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
+
+ priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; + priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
+ priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
+ priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
+
+ priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; + priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; + priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; + priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; +
+ priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; + priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; + priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; + priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; +
+ priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; + priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; + priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; + priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; +
+ priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; + priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
+ priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
+ priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
+
+ priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
+ priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
+ priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
+ priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
+
+ priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
+ priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
+ priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
+ priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
+
+ priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
+ priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
+ priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
+ priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
+
+ priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
+ priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
+ priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
+ priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
+
+ priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
+ priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
+ priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
+ priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
+
+ priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
+ priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
+ priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
+ priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
+
+ priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
+ priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
+ priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
+ priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
+
+ priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
+ priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
+
+}
+
+
+bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ bool bResult = false;
+
+ RT_TRACE((COMP_PS | COMP_RF), "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
+
+ if(eRFPowerState == priv->rtllib->eRFPowerState)
+ {
+ ; + return bResult;
+ }
+
+ bResult = phy_SetRFPowerState8192SE(dev, eRFPowerState);
+
+ RT_TRACE((COMP_PS | COMP_RF), "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
+
+ return bResult;
+}
+
+static bool phy_SetRFPowerState8192SE(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
+ bool bResult = true;
+ u8 i, QueueID;
+ struct rtl8192_tx_ring *ring = NULL;
+ priv->SetRFPowerStateInProgress = true;
+
+ switch(priv->rf_chip )
+ {
+ default: + switch( eRFPowerState )
+ {
+ case eRfOn:
+ RT_TRACE(COMP_PS,"========>%s():eRfOn\n", __func__);
+ {
+ if((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
+ { + bool rtstatus = true;
+ u32 InitializeCount = 0;
+ do
+ {
+ InitializeCount++;
+ rtstatus = NicIFEnableNIC(dev);
+ }while( (rtstatus != true) &&(InitializeCount < 10) );
+ if(rtstatus != true)
+ {
+ RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__FUNCTION__);
+ priv->SetRFPowerStateInProgress = false;
+ return false;
+ }
+ RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
+ }
+ else
+ { + write_nic_word(dev, CMDR, 0x37FC);
+ write_nic_byte(dev, TXPAUSE, 0x00);
+ write_nic_byte(dev, PHY_CCA, 0x3);
+ }
+
+#if 1
+ if(priv->rtllib->state == RTLLIB_LINKED)
+ {
+ LedControl8192SE(dev, LED_CTL_LINK);
+ }
+ else
+ {
+ LedControl8192SE(dev, LED_CTL_NO_LINK);
+ }
+#endif
+ }
+ break;
+ case eRfOff:
+ RT_TRACE(COMP_PS,"========>%s():eRfOff\n", __func__);
+ {
+ for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
+ {
+ ring = &priv->tx_ring[QueueID];
+ if(skb_queue_len(&ring->queue) == 0)
+ {
+ QueueID++;
+ continue;
+ }
+ #ifdef TO_DO_LIST
+ #if( DEV_BUS_TYPE==PCI_INTERFACE)
+ else if(IsLowPowerState(Adapter))
+ {
+ RT_TRACE(COMP_PS, DBG_LOUD,
+ ("eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID));
+ break;
+ }
+ #endif
+ #endif
+ else
+ {
+ RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
+ udelay(10);
+ i++;
+ }
+
+ if(i >= MAX_DOZE_WAITING_TIMES_9x)
+ {
+ RT_TRACE(COMP_PS, "\n\n\n %s(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", __FUNCTION__,MAX_DOZE_WAITING_TIMES_9x, QueueID);
+ break;
+ }
+ }
+
+ if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
+ { + NicIFDisableNIC(dev);
+ RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
+ if(priv->pwrdown && priv->rtllib->RfOffReason>= RF_CHANGE_BY_HW)
+ write_nic_byte(dev,0x03,0x31);
+ }
+ else if(!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
+ { + SET_RTL8192SE_RF_SLEEP(dev);
+
+#if 1
+ if(priv->rtllib->RfOffReason == RF_CHANGE_BY_IPS )
+ {
+ LedControl8192SE(dev,LED_CTL_NO_LINK);
+ }
+ else
+ {
+ LedControl8192SE(dev, LED_CTL_POWER_OFF);
+ }
+#endif
+ }
+ }
+ break;
+
+ case eRfSleep:
+ RT_TRACE(COMP_PS,"========>%s():eRfSleep\n", __func__);
+ {
+ if(priv->rtllib->eRFPowerState == eRfOff)
+ break;
+
+ for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
+ {
+ ring = &priv->tx_ring[QueueID];
+ if(skb_queue_len(&ring->queue) == 0)
+ {
+ QueueID++;
+ continue;
+ }
+ #ifdef TO_DO_LIST
+ #if( DEV_BUS_TYPE==PCI_INTERFACE)
+ else if(IsLowPowerState(Adapter))
+ {
+ RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID);
+ break;
+ }
+ #endif
+ #endif
+ else
+ {
+ RT_TRACE(COMP_PS, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
+ udelay(10);
+ i++;
+ }
+
+ if(i >= MAX_DOZE_WAITING_TIMES_9x)
+ {
+ RT_TRACE(COMP_PS, "\n\n\n %s(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", __FUNCTION__,MAX_DOZE_WAITING_TIMES_9x, QueueID);
+ break;
+ }
+ }
+
+ SET_RTL8192SE_RF_SLEEP(dev);
+ }
+ break;
+
+ default:
+ bResult = false;
+ RT_TRACE(COMP_ERR, "phy_SetRFPowerState8192S(): unknow state to set: 0x%X!!!\n", eRFPowerState);
+ break;
+ }
+ break;
+ }
+
+ if(bResult)
+ {
+ priv->rtllib->eRFPowerState = eRFPowerState;
+ }
+
+ priv->SetRFPowerStateInProgress = false;
+
+ return bResult;
+}
+
+
+void
+PHY_SwitchEphyParameter(struct net_device* dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ write_nic_dword(dev, 0x540, 0x73c11);
+ write_nic_dword(dev, 0x548, 0x2407c);
+
+ write_nic_word(dev, 0x550, 0x1000);
+ write_nic_byte(dev, 0x554, 0x20);
+ phy_CheckEphySwitchReady(dev);
+
+ write_nic_word(dev, 0x550, 0xa0eb);
+ write_nic_byte(dev, 0x554, 0x3e);
+ phy_CheckEphySwitchReady(dev);
+
+ write_nic_word(dev, 0x550, 0xff80);
+ write_nic_byte(dev, 0x554, 0x39);
+ phy_CheckEphySwitchReady(dev);
+
+ if (priv->pci_bridge_vendor & (PCI_BRIDGE_VENDOR_INTEL | PCI_BRIDGE_VENDOR_SIS))
+ write_nic_byte(dev, 0x560, 0x40);
+ else
+ write_nic_byte(dev, 0x560, 0x00);
+
+} +
+
+ void
+PHY_GetTxPowerLevel8192S(
+ struct net_device* dev,
+ long* powerlevel
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 TxPwrLevel = 0;
+ long TxPwrDbm;
+
+ TxPwrLevel = priv->CurrentCckTxPwrIdx;
+ TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
+
+ TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
+
+ if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
+ TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
+ TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
+
+ if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
+ TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
+ *powerlevel = TxPwrDbm;
+}
+
+#if 1
+void getTxPowerIndex(
+ struct net_device* dev,
+ u8 channel,
+ u8* cckPowerLevel,
+ u8* ofdmPowerLevel
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 index = (channel -1);
+ cckPowerLevel[0] = priv->RfTxPwrLevelCck[0][index]; + cckPowerLevel[1] = priv->RfTxPwrLevelCck[1][index]; +
+ if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
+ {
+ ofdmPowerLevel[0] = priv->RfTxPwrLevelOfdm1T[0][index];
+ ofdmPowerLevel[1] = priv->RfTxPwrLevelOfdm1T[1][index];
+ }
+ else if (priv->rf_type == RF_2T2R)
+ {
+ ofdmPowerLevel[0] = priv->RfTxPwrLevelOfdm2T[0][index];
+ ofdmPowerLevel[1] = priv->RfTxPwrLevelOfdm2T[1][index];
+ }
+ RT_TRACE(COMP_POWER,"Channel-%d, set tx power index !!\n", channel);
+}
+
+void ccxPowerIndexCheck(
+ struct net_device* dev,
+ u8 channel,
+ u8* cckPowerLevel,
+ u8* ofdmPowerLevel
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+#ifdef TODO + if( priv->rtllib->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
+ channel == priv->rtllib->current_network.channel)
+ {
+ u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
+ u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
+ u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
+
+ RT_TRACE(COMP_TXAGC,
+ "CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
+ priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx);
+ RT_TRACE(COMP_TXAGC,
+ "EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
+ channel, cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);
+
+ if(cckPowerLevel[0] > CckCellPwrIdx)
+ cckPowerLevel[0] = CckCellPwrIdx;
+ if(ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
+ {
+ if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
+ {
+ ofdmPowerLevel[0] = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
+ }
+ else
+ {
+ ofdmPowerLevel[0] = 0;
+ }
+ }
+
+ RT_TRACE(COMP_TXAGC,
+ "Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
+ cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);
+ }
+
+#endif
+ priv->CurrentCckTxPwrIdx = cckPowerLevel[0];
+ priv->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
+
+ RT_TRACE(COMP_TXAGC,
+ "PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
+ cckPowerLevel[0], ofdmPowerLevel[0] + priv->LegacyHTTxPowerDiff, ofdmPowerLevel[0]);
+
+}
+/*-----------------------------------------------------------------------------
+ * Function: SetTxPowerLevel8190()
+ *
+ * Overview: This function is export to "HalCommon" moudule
+ * We must consider RF path later!!!!!!!
+ *
+ * Input: PADAPTER Adapter
+ * u1Byte channel
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ * 2008/11/04 MHC We remove EEPROM_93C56.
+ * We need to move CCX relative code to independet file.
+ * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
+ *
+ *---------------------------------------------------------------------------*/
+void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 cckPowerLevel[2], ofdmPowerLevel[2]; +
+ if(priv->bTXPowerDataReadFromEEPORM == false)
+ return;
+ getTxPowerIndex(dev, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
+ RT_TRACE(COMP_POWER, "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
+ channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1]);
+
+ ccxPowerIndexCheck(dev, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
+
+ switch(priv->rf_chip)
+ {
+ case RF_8225:
+ break;
+
+ case RF_8256:
+ ; + break;
+
+ case RF_6052:
+ PHY_RF6052SetCckTxPower(dev, cckPowerLevel[0]);
+ PHY_RF6052SetOFDMTxPower(dev, &ofdmPowerLevel[0], channel);
+ break;
+
+ case RF_8258:
+ break;
+ default:
+ break;
+ }
+}
+#else
+void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
+ s8 ant_pwr_diff = 0;
+ u32 u4RegValue;
+ u8 index = (channel -1);
+ u8 pwrdiff[2] = {0};
+ u8 ht20pwr[2] = {0}, ht40pwr[2] = {0};
+ u8 rfpath = 0, rfpathnum = 2;
+
+ if(priv->bTXPowerDataReadFromEEPORM == false)
+ return;
+
+
+ powerlevel = priv->RfTxPwrLevelCck[0][index];
+
+ if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
+ {
+ powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
+
+
+ rfpathnum = 1;
+ ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
+ }
+ else if (priv->rf_type == RF_2T2R)
+ {
+ powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
+ ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] -
+ priv->RfTxPwrLevelOfdm2T[0][index];
+
+ RT_TRACE(COMP_POWER, "CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
+ channel, priv->RfTxPwrLevelOfdm2T[0][index],
+ priv->RfTxPwrLevelOfdm2T[1][index],
+ priv->RfTxPwrLevelOfdm2T[0][index],
+ priv->RfTxPwrLevelOfdm2T[1][index]);
+
+ ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
+ ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
+ }
+ RT_TRACE(COMP_POWER, "Channel-%d, set tx power index\n", channel);
+
+ if (priv->eeprom_version >= 2) + {
+ if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
+ {
+ for (rfpath = 0; rfpath < rfpathnum; rfpath++)
+ {
+ pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
+
+ if (pwrdiff[rfpath] < 8) + {
+ ht20pwr[rfpath] += pwrdiff[rfpath];
+ }
+ else + {
+ ht20pwr[rfpath] -= (16-pwrdiff[rfpath]);
+ }
+ }
+
+ if (priv->rf_type == RF_2T2R)
+ ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
+
+ RT_TRACE(COMP_POWER, "HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
+ pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]);
+ }
+ }
+
+ if(ant_pwr_diff > 7)
+ ant_pwr_diff = 7;
+ if(ant_pwr_diff < -8)
+ ant_pwr_diff = -8;
+
+ RT_TRACE(COMP_POWER, "CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
+ powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff);
+
+ ant_pwr_diff &= 0xf;
+
+ priv->AntennaTxPwDiff[2] = 0; + priv->AntennaTxPwDiff[1] = 0; + priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); + RT_TRACE(COMP_POWER, "pHalData->AntennaTxPwDiff[0]/[1]/[2] = 0x%x/0x%x/0x%x\n",
+ priv->AntennaTxPwDiff[0], priv->AntennaTxPwDiff[1], priv->AntennaTxPwDiff[2]);
+ u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
+ priv->AntennaTxPwDiff[1]<<4 |
+ priv->AntennaTxPwDiff[0] );
+ RT_TRACE(COMP_POWER, "BCD-Diff=0x%x\n", u4RegValue);
+
+ rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
+
+#ifdef TODO + if( priv->rtllib->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
+ channel == priv->rtllib->current_network.channel)
+ {
+ u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
+ u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
+ u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
+
+ RT_TRACE(COMP_TXAGC,
+ ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
+ priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
+ RT_TRACE(COMP_TXAGC,
+ ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
+ channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
+
+ if(powerlevel > CckCellPwrIdx)
+ powerlevel = CckCellPwrIdx;
+ if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
+ {
+ if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
+ {
+ powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
+ }
+ else
+ {
+ powerlevelOFDM24G = 0;
+ }
+ }
+
+ RT_TRACE(COMP_TXAGC,
+ ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
+ powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
+ }
+#endif
+ priv->CurrentCckTxPwrIdx = powerlevel;
+ priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
+
+ RT_TRACE(COMP_POWER, "PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
+ powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G);
+
+ switch(priv->rf_chip)
+ {
+ case RF_8225:
+ break;
+
+ case RF_8256:
+ break;
+
+ case RF_6052:
+ PHY_RF6052SetCckTxPower(dev, powerlevel);
+ PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G, channel);
+ break;
+
+ case RF_8258:
+ break;
+ default:
+ break;
+ }
+
+}
+#endif
+
+bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 idx;
+ u8 rf_path;
+
+ u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
+ u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
+
+ if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
+ OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
+ else
+ OfdmTxPwrIdx = 0;
+
+ RT_TRACE(COMP_POWER, "PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx);
+
+ for(idx = 0; idx < 14; idx++)
+ {
+ priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
+ priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
+ priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
+ priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
+ priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
+ priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
+ for (rf_path = 0; rf_path < 2; rf_path++)
+ {
+ priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
+ priv->RfTxPwrLevelOfdm1T[rf_path][idx] =
+ priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
+ }
+ }
+
+ rtl8192_phy_setTxPower(dev, priv->chan);
+
+ return true;
+}
+
+extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u32 NewBeaconNum;
+
+ if(priv->pFirmware->FirmwareVersion >= 0x33) + {
+ write_nic_dword(dev,WFM5,0xF1000000|(BeaconInterval<<8));
+ }
+ else
+ {
+ NewBeaconNum = BeaconInterval *32 - 64;
+ write_nic_dword(dev, WFM3+4, NewBeaconNum);
+ write_nic_dword(dev, WFM3, 0xB026007C);
+}
+}
+
+static u8 phy_DbmToTxPwrIdx(
+ struct net_device* dev,
+ WIRELESS_MODE WirelessMode,
+ long PowerInDbm
+ )
+{
+ u8 TxPwrIdx = 0;
+ long Offset = 0;
+
+
+ switch(WirelessMode)
+ {
+ case WIRELESS_MODE_B:
+ Offset = -7;
+ break;
+
+ case WIRELESS_MODE_G:
+ Offset = -8;
+ break;
+
+ case WIRELESS_MODE_N_24G:
+ default:
+ Offset = -8;
+ break;
+ }
+
+ if((PowerInDbm - Offset) > 0)
+ {
+ TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
+ }
+ else
+ {
+ TxPwrIdx = 0;
+ }
+
+ if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
+ TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
+
+ return TxPwrIdx;
+}
+
+static long phy_TxPwrIdxToDbm(
+ struct net_device* dev,
+ WIRELESS_MODE WirelessMode,
+ u8 TxPwrIdx
+ )
+{
+ long Offset = 0;
+ long PwrOutDbm = 0;
+
+ switch(WirelessMode)
+ {
+ case WIRELESS_MODE_B:
+ Offset = -7;
+ break;
+
+ case WIRELESS_MODE_G:
+ case WIRELESS_MODE_N_24G:
+ Offset = -8;
+ break;
+ default:
+ Offset = -8;
+ break;
+ }
+
+ PwrOutDbm = TxPwrIdx / 2 + Offset; +
+ return PwrOutDbm;
+}
+
+#ifdef TO_DO_LIST
+extern void
+PHY_ScanOperationBackup8192S(
+ struct net_device* dev,
+ u8 Operation
+ )
+{
+#if(RTL8192S_DISABLE_FW_DM == 0)
+
+ if(!Adapter->bDriverStopped)
+ {
+ switch(Operation)
+ {
+ case SCAN_OPT_BACKUP:
+ Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
+ break;
+
+ case SCAN_OPT_RESTORE:
+ Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
+ break;
+
+ default:
+ RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
+ break;
+ }
+ }
+#endif
+}
+#endif
+void PHY_SetBWModeCallback8192S(struct net_device *dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u8 regBwOpMode, regRRSR_RSC;
+
+
+
+ RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8192s() Switch to %s bandwidth\n", \
+ priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
+
+ if(priv->rf_chip == RF_PSEUDO_11N)
+ {
+ priv->SetBWModeInProgress= false;
+ return;
+ }
+#ifdef _RTL8192_EXT_PATCH_
+ if((!priv->up) && (!priv->mesh_up))
+#else
+ if(!priv->up)
+#endif
+ {
+ priv->SwChnlInProgress = priv->SetBWModeInProgress = false;
+ return;
+ }
+
+ regBwOpMode = read_nic_byte(dev, BW_OPMODE);
+ regRRSR_RSC = read_nic_byte(dev, RRSR+2);
+
+ switch(priv->CurrentChannelBW)
+ {
+ case HT_CHANNEL_WIDTH_20:
+ regBwOpMode |= BW_OPMODE_20MHZ;
+ write_nic_byte(dev, BW_OPMODE, regBwOpMode);
+ break;
+
+ case HT_CHANNEL_WIDTH_20_40:
+ regBwOpMode &= ~BW_OPMODE_20MHZ;
+ write_nic_byte(dev, BW_OPMODE, regBwOpMode);
+
+ break;
+
+ default:
+ RT_TRACE(COMP_DBG, "SetBWModeCallback8192s():\
+ unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
+ break;
+ }
+
+ switch(priv->CurrentChannelBW)
+ {
+ case HT_CHANNEL_WIDTH_20:
+ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
+ rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
+
+ if(priv->card_8192_version >= VERSION_8192S_BCUT)
+ write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
+ break;
+
+ case HT_CHANNEL_WIDTH_20_40:
+ rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
+ rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
+
+
+ rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
+ rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
+
+ if(priv->card_8192_version >= VERSION_8192S_BCUT)
+ write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
+ break;
+
+ default:
+ RT_TRACE(COMP_DBG, "SetBWModeCallback8192s(): unknown Bandwidth: %#X\n"\
+ ,priv->CurrentChannelBW);
+ break;
+
+ }
+
+
+ switch( priv->rf_chip )
+ {
+ case RF_8225:
+ break;
+
+ case RF_8256:
+ break;
+
+ case RF_8258:
+ break;
+
+ case RF_PSEUDO_11N:
+ break;
+
+ case RF_6052:
+ PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
+ break;
+ default:
+ printk("Unknown rf_chip: %d\n", priv->rf_chip);
+ break;
+ }
+
+ priv->SetBWModeInProgress= false;
+
+ RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8192s() \n" );
+}
+
+
+void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+
+
+
+
+ if(priv->SetBWModeInProgress)
+ return;
+
+ priv->SetBWModeInProgress= true;
+
+ priv->CurrentChannelBW = Bandwidth;
+
+ if(Offset==HT_EXTCHNL_OFFSET_LOWER)
+ priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
+ else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
+ priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
+ else
+ priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+#if 0
+ if(!priv->bDriverStopped)
+ {
+#ifdef USE_WORKITEM
+ PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem)); +#else
+ PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0); +#endif
+ }
+#endif
+#ifdef _RTL8192_EXT_PATCH_
+ if(priv->up || priv->mesh_up)
+#else
+ if (priv->up)
+#endif
+ {
+ PHY_SetBWModeCallback8192S(dev);
+ } else {
+ priv->SetBWModeInProgress= false;
+ }
+}
+
+void PHY_SwChnlCallback8192S(struct net_device *dev)
+{
+
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u32 delay;
+
+ RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
+
+#ifdef _RTL8192_EXT_PATCH_
+ if((!priv->up) && (!priv->mesh_up))
+#else
+ if(!priv->up)
+#endif
+ {
+ printk("%s: driver is not up\n", __FUNCTION__);
+ priv->SwChnlInProgress = priv->SetBWModeInProgress = false;
+ return;
+ }
+ if(priv->rf_chip == RF_PSEUDO_11N)
+ {
+ printk("%s: rt chip is RF_PSEUDO_11N\n", __FUNCTION__);
+ priv->SwChnlInProgress=false;
+ return; + }
+
+ do{
+ if(!priv->SwChnlInProgress)
+ break;
+
+ if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
+ {
+ if(delay>0)
+ {
+ mdelay(delay);
+ }
+ else
+ continue;
+ }
+ else
+ {
+ priv->SwChnlInProgress=false;
+ break;
+ }
+ }while(true);
+}
+
+u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+#ifdef _RTL8192_EXT_PATCH_
+ if((!priv->up) && (!priv->mesh_up))
+#else
+ if(!priv->up)
+#endif
+ {
+ printk("%s: driver is not up.\n",__FUNCTION__);
+ priv->SwChnlInProgress = priv->SetBWModeInProgress = false;
+ return false;
+ }
+ if(priv->SwChnlInProgress){
+ printk("%s: SwChnl is in progress\n",__FUNCTION__);
+ return false;
+ }
+
+ if(priv->SetBWModeInProgress){
+ printk("%s: Set BWMode is in progress\n",__FUNCTION__);
+ return false;
+ }
+ if (0)
+ {
+ u8 path;
+ for(path=0; path<2; path++){
+ printk("============>to set channel:%x\n", rtl8192_phy_QueryRFReg(dev, path, 0x18, 0x3ff));
+ udelay(10);
+ }
+ }
+ switch(priv->rtllib->mode)
+ {
+ case WIRELESS_MODE_A:
+ case WIRELESS_MODE_N_5G:
+ if (channel<=14){
+ RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
+ return false;
+ }
+ break;
+
+ case WIRELESS_MODE_B:
+ if (channel>14){
+ RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
+ return false;
+ }
+ break;
+
+ case WIRELESS_MODE_G:
+ case WIRELESS_MODE_N_24G:
+ if (channel>14){
+ RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
+ return false;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ priv->SwChnlInProgress = true;
+ if( channel == 0)
+ channel = 1;
+
+ priv->chan=channel;
+
+ priv->SwChnlStage=0;
+ priv->SwChnlStep=0;
+
+#if 0
+ if(!dev->bDriverStopped)
+ {
+#ifdef USE_WORKITEM
+ PlatformScheduleWorkItem(&(priv->SwChnlWorkItem)); +#else
+ PlatformSetTimer(dev, &(priv->SwChnlTimer), 0); +#endif
+ }
+#endif
+
+#ifdef _RTL8192_EXT_PATCH_
+ if(priv->up || priv->mesh_up)
+#else
+ if(priv->up)
+#endif
+ {
+ PHY_SwChnlCallback8192S(dev);
+ } else {
+ priv->SwChnlInProgress = false;
+ }
+ return true;
+}
+
+
+void PHY_SwChnlPhy8192S( + struct net_device* dev,
+ u8 channel
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+
+ RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
+
+#ifdef TO_DO_LIST
+ if(RT_CANNOT_IO(dev))
+ return;
+#endif
+
+ if(priv->SwChnlInProgress)
+ return;
+
+ if(priv->rf_chip == RF_PSEUDO_11N)
+ {
+ priv->SwChnlInProgress=false;
+ return;
+ }
+
+ priv->SwChnlInProgress = true;
+ if( channel == 0)
+ channel = 1;
+
+ priv->chan=channel;
+
+ priv->SwChnlStage = 0;
+ priv->SwChnlStep = 0;
+
+ phy_FinishSwChnlNow(dev,channel);
+
+ priv->SwChnlInProgress = false;
+}
+
+static bool
+phy_SwChnlStepByStep(
+ struct net_device* dev,
+ u8 channel,
+ u8 *stage,
+ u8 *step,
+ u32 *delay
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
+ u32 PreCommonCmdCnt;
+ SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
+ u32 PostCommonCmdCnt;
+ SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
+ u32 RfDependCmdCnt;
+ SwChnlCmd *CurrentCmd = NULL;
+ u8 eRFPath;
+ u16 u2Channel = 0;
+
+ RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
+ if (!IsLegalChannel(priv->rtllib, channel))
+ {
+ RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
+ return true; + }
+
+
+ PreCommonCmdCnt = 0;
+ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
+ CmdID_SetTxPowerLevel, 0, 0, 0);
+ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
+ CmdID_End, 0, 0, 0);
+
+ PostCommonCmdCnt = 0;
+
+ phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
+ CmdID_End, 0, 0, 0);
+
+ RfDependCmdCnt = 0;
+ switch( priv->rf_chip )
+ {
+ case RF_8225:
+ if (channel < 1 || channel > 14)
+ RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_RF_WriteReg, rRfChannel, channel, 10);
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_End, 0, 0, 0);
+ break;
+
+ case RF_8256:
+ if (channel < 1 || channel > 14)
+ RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_RF_WriteReg, rRfChannel, channel, 10);
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_End, 0, 0, 0);
+ break;
+
+ case RF_6052:
+ if (channel < 1 || channel > 14)
+ RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
+
+ u2Channel = channel;
+
+ switch(priv->CurrentChannelBW)
+ {
+ case HT_CHANNEL_WIDTH_20:
+ u2Channel |= BIT10;
+ break;
+
+ case HT_CHANNEL_WIDTH_20_40:
+ u2Channel &= ~BIT10;
+ break;
+ default:
+ u2Channel |= BIT10; + break;
+ }
+ u2Channel |= BIT12|BIT13|BIT14;
+
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_RF_WriteReg, RF_CHNLBW, u2Channel, 10);
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_End, 0, 0, 0);
+ break;
+
+ case RF_8258:
+ break;
+
+ default:
+ return false;
+ break;
+ }
+
+
+ do{
+ switch(*stage)
+ {
+ case 0:
+ CurrentCmd=&PreCommonCmd[*step];
+ break;
+ case 1:
+ CurrentCmd=&RfDependCmd[*step];
+ break;
+ case 2:
+ CurrentCmd=&PostCommonCmd[*step];
+ break;
+ }
+
+ if(CurrentCmd->CmdID==CmdID_End)
+ {
+ if((*stage)==2)
+ {
+ return true;
+ }
+ else
+ {
+ (*stage)++;
+ (*step)=0;
+ continue;
+ }
+ }
+
+ switch(CurrentCmd->CmdID)
+ {
+ case CmdID_SetTxPowerLevel:
+#ifndef CONFIG_MP
+ rtl8192_phy_setTxPower(dev,channel);
+#endif
+ break;
+ case CmdID_WritePortUlong:
+ write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
+ break;
+ case CmdID_WritePortUshort:
+ write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
+ break;
+ case CmdID_WritePortUchar:
+ write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
+ break;
+ case CmdID_RF_WriteReg: + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
+ {
+ if (IS_HARDWARE_TYPE_8192SE(dev)) {
+#ifdef CONFIG_FW_SETCHAN
+ u32 rf_bw = ((priv->RfRegChnlVal[eRFPath] & 0xfffffc00) | (CurrentCmd->Para2 & 0xFF00));
+#endif
+ priv->RfRegChnlVal[eRFPath] = ((priv->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
+
+#ifdef CONFIG_FW_SETCHAN
+ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, rf_bw);
+#else
+ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, priv->RfRegChnlVal[eRFPath]);
+#endif
+ } else {
+ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ break;
+ }while(true);
+
+ (*delay)=CurrentCmd->msDelay;
+ (*step)++;
+ RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
+ return false;
+}
+
+static bool
+phy_SetSwChnlCmdArray(
+ SwChnlCmd* CmdTable,
+ u32 CmdTableIdx,
+ u32 CmdTableSz,
+ SwChnlCmdID CmdID,
+ u32 Para1,
+ u32 Para2,
+ u32 msDelay
+ )
+{
+ SwChnlCmd* pCmd;
+
+ if(CmdTable == NULL)
+ {
+ return false;
+ }
+ if(CmdTableIdx >= CmdTableSz)
+ {
+ return false;
+ }
+
+ pCmd = CmdTable + CmdTableIdx;
+ pCmd->CmdID = CmdID;
+ pCmd->Para1 = Para1;
+ pCmd->Para2 = Para2;
+ pCmd->msDelay = msDelay;
+
+ return true;
+}
+
+static void
+phy_FinishSwChnlNow( + struct net_device* dev,
+ u8 channel
+ )
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u32 delay;
+
+ while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
+ {
+ if(delay>0)
+ mdelay(delay);
+#ifdef _RTL8192_EXT_PATCH_
+ if((!priv->up) && (!priv->mesh_up))
+#else
+ if(!priv->up)
+#endif
+ break;
+ }
+}
+
+#ifdef TO_DO_LIST
+extern VOID
+PHY_SetMonitorMode8192S(
+ IN PADAPTER pAdapter,
+ IN BOOLEAN bEnableMonitorMode
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ BOOLEAN bFilterOutNonAssociatedBSSID = false;
+
+ if(bEnableMonitorMode)
+ {
+ bFilterOutNonAssociatedBSSID = false;
+ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
+
+ pHalData->bInMonitorMode = true;
+ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, true, true);
+ pAdapter->HalFunc.SetHwRegHandler(pAdapter, HW_VAR_CECHK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
+ }
+ else
+ {
+ bFilterOutNonAssociatedBSSID = true;
+ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
+
+ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, false, true);
+ pHalData->bInMonitorMode = false;
+ pAdapter->HalFunc.SetHwRegHandler(pAdapter, HW_VAR_CECHK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
+ }
+}
+#endif
+
+
+u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
+{
+ bool rtValue = true;
+
+#if 0
+ if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
+ {
+ rtValue = false;
+ }
+ if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
+ {
+
+ }
+#endif
+ return rtValue;
+
+} /* PHY_CheckIsLegalRfPath8192S */
+
+
+
+void
+PHY_IQCalibrate( struct net_device* dev)
+{
+ u32 i, reg;
+ u32 old_value;
+ long X, Y, TX0[4];
+ u32 TXA[4];
+
+
+ for (i = 0; i < 10; i++)
+ {
+ rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
+ udelay(2000);
+ rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
+
+
+ reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
+
+ if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
+ {
+ old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
+
+ X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
+ TXA[RF90_PATH_A] = (X * old_value)/0x100;
+ reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
+ reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
+ rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
+ udelay(5);
+
+ Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
+ TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
+ reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
+ reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
+ rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
+ reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
+ reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
+ rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
+ udelay(5);
+
+ reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
+ X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
+ reg = (reg & 0xFFFFFC00) |X;
+ rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
+ Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
+ reg = (reg & 0xFFFF03FF) |Y<<10;
+ rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
+ udelay(5);
+ old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
+
+ X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
+ reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
+ TXA[RF90_PATH_A] = (X * old_value) / 0x100;
+ reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
+ rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
+ udelay(5);
+
+ Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
+ TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
+ reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
+ reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
+ rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
+ reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
+ reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
+ rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
+ udelay(5);
+
+ reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
+ X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
+ reg = (reg & 0xFFFFFC00) |X;
+ rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
+
+ Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
+ reg = (reg & 0xFFFF03FF) |Y<<10;
+ rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
+ udelay(5);
+
+ RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
+ break;
+ }
+
+ }
+
+
+
+
+}
+
+extern void PHY_IQCalibrateBcut(struct net_device* dev)
+{
+ u32 i, reg;
+ u32 old_value;
+ long X, Y, TX0[4];
+ u32 TXA[4];
+ u32 calibrate_set[13] = {0};
+ u32 load_value[13];
+ u8 RfPiEnable=0;
+
+ /*
+ 0xee0[31:0]=0x3fed92fb;
+ 0xedc[31:0] =0x3fed92fb;
+ 0xe70[31:0] =0x3fed92fb;
+ 0xe74[31:0] =0x3fed92fb;
+ 0xe78[31:0] =0x3fed92fb;
+ 0xe7c[31:0]= 0x3fed92fb;
+ 0xe80[31:0]= 0x3fed92fb;
+ 0xe84[31:0]= 0x3fed92fb;
+ 0xe88[31:0]= 0x3fed92fb;
+ 0xe8c[31:0]= 0x3fed92fb;
+ 0xed0[31:0]= 0x3fed92fb;
+ 0xed4[31:0]= 0x3fed92fb;
+ 0xed8[31:0]= 0x3fed92fb;
+ */
+ calibrate_set [0] = 0xee0;
+ calibrate_set [1] = 0xedc;
+ calibrate_set [2] = 0xe70;
+ calibrate_set [3] = 0xe74;
+ calibrate_set [4] = 0xe78;
+ calibrate_set [5] = 0xe7c;
+ calibrate_set [6] = 0xe80;
+ calibrate_set [7] = 0xe84;
+ calibrate_set [8] = 0xe88;
+ calibrate_set [9] = 0xe8c;
+ calibrate_set [10] = 0xed0;
+ calibrate_set [11] = 0xed4;
+ calibrate_set [12] = 0xed8;
+ for (i = 0; i < 13; i++)
+ {
+ load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
+ rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
+
+ }
+
+ RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
+ for (i = 0; i < 10; i++)
+ {
+ RT_TRACE(COMP_INIT, "IQK -%d\n", i);
+ if (!RfPiEnable) + {
+ rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
+ rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
+ }
+
+ rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
+ udelay(5);
+
+ udelay(2000);
+
+ rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
+
+ udelay(2000);
+
+ rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
+ udelay(5);
+ rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
+
+ if (!RfPiEnable) + {
+ rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
+ rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
+ }
+
+
+ reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
+
+ if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
+ {
+ old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
+
+ X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
+ TXA[RF90_PATH_A] = (X * old_value)/0x100;
+ reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
+ reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
+ rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
+ udelay(5);
+
+ Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
+ TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
+ reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
+ reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
+ rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
+ reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
+ reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
+ rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
+ udelay(5);
+
+ reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
+ X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
+ reg = (reg & 0xFFFFFC00) |X;
+ rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
+ Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
+ reg = (reg & 0xFFFF03FF) |Y<<10;
+ rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
+ udelay(5);
+ old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
+
+ X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
+ reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
+ TXA[RF90_PATH_A] = (X * old_value) / 0x100;
+ reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
+ rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
+ udelay(5);
+
+ Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
+ TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
+ reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
+ reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
+ rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
+ reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
+ reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
+ rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
+ udelay(5);
+
+ reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
+ X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
+ reg = (reg & 0xFFFFFC00) |X;
+ rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
+
+ Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
+ reg = (reg & 0xFFFF03FF) |Y<<10;
+ rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
+ udelay(5);
+
+ RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
+ break;
+ }
+
+ }
+
+ for (i = 0; i < 13; i++)
+ rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
+
+
+
+
+
+} +
+#define HalGetFirmwareVerison(priv) (priv->pFirmware->FirmwareVersion )
+bool rtl8192se_set_fw_cmd(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u32 FwParam = FW_CMD_IO_PARA_QUERY(priv);
+ u16 FwCmdMap = FW_CMD_IO_QUERY(priv);
+ bool bPostProcessing = false;
+
+ RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%#x), SetFwCmdInProgress(%d)\n", FwCmdIO, priv->SetFwCmdInProgress);
+
+
+
+
+
+ RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%#x), SetFwCmdInProgress(%d)\n",
+ FwCmdIO, priv->SetFwCmdInProgress);
+
+ do{
+
+ if(HalGetFirmwareVerison(priv) >= 0x35)
+ {
+ switch(FwCmdIO)
+ {
+ case FW_CMD_RA_REFRESH_N:
+ FwCmdIO = FW_CMD_RA_REFRESH_N_COMB;
+ break;
+ case FW_CMD_RA_REFRESH_BG:
+ FwCmdIO = FW_CMD_RA_REFRESH_BG_COMB;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ if((FwCmdIO == FW_CMD_IQK_ENABLE) ||
+ (FwCmdIO == FW_CMD_RA_REFRESH_N) ||
+ (FwCmdIO == FW_CMD_RA_REFRESH_BG))
+ {
+ bPostProcessing = true;
+ break;
+ }
+ }
+
+ if(HalGetFirmwareVerison(priv) >= 0x3E)
+ {
+ if(FwCmdIO == FW_CMD_CTRL_DM_BY_DRIVER)
+ FwCmdIO = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
+ }
+
+
+ switch(FwCmdIO)
+ {
+
+ case FW_CMD_RA_INIT:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] RA init!!\n");
+ FwCmdMap |= FW_RA_INIT_CTL;
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ FW_CMD_IO_CLR(priv, FW_RA_INIT_CTL); + break;
+
+ case FW_CMD_DIG_DISABLE:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG disable!!\n");
+ FwCmdMap &= ~FW_DIG_ENABLE_CTL;
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ break;
+
+ case FW_CMD_DIG_ENABLE:
+ case FW_CMD_DIG_RESUME:
+ if(!(priv->DMFlag & HAL_DM_DIG_DISABLE))
+ {
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG enable or resume!!\n");
+ FwCmdMap |= (FW_DIG_ENABLE_CTL|FW_SS_CTL);
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ }
+ break;
+
+ case FW_CMD_DIG_HALT:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG halt!!\n");
+ FwCmdMap &= ~(FW_DIG_ENABLE_CTL|FW_SS_CTL);
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ break;
+
+ case FW_CMD_TXPWR_TRACK_THERMAL:
+ {
+ u8 ThermalVal = 0;
+ FwCmdMap |= FW_PWR_TRK_CTL;
+ FwParam &= FW_PWR_TRK_PARAM_CLR; + ThermalVal = priv->ThermalValue;
+ FwParam |= ((ThermalVal<<24) |(priv->ThermalMeter[0]<<16));
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);
+ FW_CMD_PARA_SET(priv, FwParam);
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ FW_CMD_IO_CLR(priv, FW_PWR_TRK_CTL); + }
+ break;
+
+ case FW_CMD_RA_REFRESH_N_COMB:
+ FwCmdMap |= FW_RA_N_CTL;
+ FwCmdMap &= ~(FW_RA_BG_CTL |FW_RA_INIT_CTL); + FwParam &= FW_RA_PARAM_CLR; + if(!(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL))
+ FwParam |= ((priv->rtllib->pHTInfo->IOTRaFunc)&0xf);
+ FwParam |= ((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<4);
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);
+ FW_CMD_PARA_SET(priv, FwParam);
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ FW_CMD_IO_CLR(priv, FW_RA_N_CTL); + break;
+
+ case FW_CMD_RA_REFRESH_BG_COMB:
+ FwCmdMap |= FW_RA_BG_CTL;
+ FwCmdMap &= ~(FW_RA_N_CTL|FW_RA_INIT_CTL); + FwParam &= FW_RA_PARAM_CLR; + if(!(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL))
+ FwParam |= ((priv->rtllib->pHTInfo->IOTRaFunc)&0xf);
+ FwParam |= ((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<4);
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set RA/IOT Comb in BG mode!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);
+ FW_CMD_PARA_SET(priv, FwParam);
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ FW_CMD_IO_CLR(priv, FW_RA_BG_CTL); + break;
+
+ case FW_CMD_IQK_ENABLE:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] IQK enable.\n");
+ FwCmdMap |= FW_IQK_CTL;
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ FW_CMD_IO_CLR(priv, FW_IQK_CTL); + break;
+
+ case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
+ RT_TRACE(COMP_CMD, "[FW CMD][New Version] Inform FW driver control some DM!! FwCmdMap(%#x), FwParam(%#x)\n", FwCmdMap, FwParam);
+ FwCmdMap |= FW_DRIVER_CTRL_DM_CTL;
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ break;
+
+ case FW_CMD_RESUME_DM_BY_SCAN:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Resume DM after scan.\n");
+ FwCmdMap |= (FW_DIG_ENABLE_CTL|FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);
+
+ if(priv->DMFlag & HAL_DM_DIG_DISABLE || !dm_digtable.dig_enable_flag)
+ FwCmdMap &= ~FW_DIG_ENABLE_CTL;
+
+ if((priv->DMFlag & HAL_DM_HIPWR_DISABLE) ||
+ (priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) ||
+ (priv->rtllib->bdynamic_txpower_enable == true))
+ FwCmdMap &= ~FW_HIGH_PWR_ENABLE_CTL;
+
+ if( (dm_digtable.Dig_Ext_Port_Stage == DIG_EXT_PORT_STAGE_0) ||
+ (dm_digtable.Dig_Ext_Port_Stage == DIG_EXT_PORT_STAGE_1))
+ FwCmdMap &= ~FW_DIG_ENABLE_CTL;
+
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ bPostProcessing = true;
+ break;
+
+ case FW_CMD_PAUSE_DM_BY_SCAN:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Pause DM before scan.\n");
+ FwCmdMap &= ~(FW_DIG_ENABLE_CTL|FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ bPostProcessing = true;
+ break;
+
+ case FW_CMD_HIGH_PWR_DISABLE:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set HighPwr disable!!\n");
+ FwCmdMap &= ~FW_HIGH_PWR_ENABLE_CTL;
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ bPostProcessing = true;
+ break;
+
+ case FW_CMD_HIGH_PWR_ENABLE:
+ if(((priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0) &&
+ !(priv->DMFlag & HAL_DM_HIPWR_DISABLE) &&
+ (priv->rtllib->bdynamic_txpower_enable != true))
+ {
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set HighPwr enable!!\n");
+ FwCmdMap |= (FW_HIGH_PWR_ENABLE_CTL|FW_SS_CTL);
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ bPostProcessing = true;
+ }
+ break;
+
+ case FW_CMD_DIG_MODE_FA:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG Mode to FA.\n");
+ FwCmdMap |= FW_FA_CTL;
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ break;
+
+ case FW_CMD_DIG_MODE_SS:
+ RT_TRACE(COMP_CMD, "[FW CMD] [New Version] Set DIG Mode to SS.\n");
+ FwCmdMap &= ~FW_FA_CTL;
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ break;
+
+ case FW_CMD_PAPE_CONTROL:
+ RT_TRACE(COMP_CMD, "[FW CMD] Set PAPE Control \n");
+#ifdef MERGE_TO_DO
+ if(pHalData->bt_coexist.BT_PapeCtrl)
+ {
+ RTPRINT(FBT, BT_TRACE, ("BT set PAPE Control to SW/HW dynamically. \n"));
+ FwCmdMap |= FW_PAPE_CTL_BY_SW_HW;
+ }
+ else
+#endif
+ {
+ printk("BT set PAPE Control to SW\n");
+ FwCmdMap &= ~FW_PAPE_CTL_BY_SW_HW;
+ }
+ FW_CMD_IO_SET(priv, FwCmdMap);
+ break;
+
+ default:
+ bPostProcessing = true; + break;
+ }
+ }while(false);
+
+ RT_TRACE(COMP_CMD, "[FW CMD] Current FwCmdMap(%#x)\n", priv->FwCmdIOMap);
+ RT_TRACE(COMP_CMD, "[FW CMD] Current FwCmdIOParam(%#x)\n", priv->FwCmdIOParam);
+
+ if(bPostProcessing && !priv->SetFwCmdInProgress)
+ {
+ priv->SetFwCmdInProgress = true;
+ priv->CurrentFwCmdIO = FwCmdIO; + }
+ else
+ {
+ return false;
+ }
+
+#if 0
+#ifdef USE_WORKITEM
+ PlatformScheduleWorkItem(&(pHalData->FwCmdIOWorkItem));
+#else
+ PlatformSetTimer(Adapter, &(pHalData->SetFwCmdIOTimer), 0);
+#endif
+#endif
+ rtl8192_SetFwCmdIOCallback(dev);
+ return true;
+}
+void ChkFwCmdIoDone(struct net_device* dev)
+{
+ u16 PollingCnt = 10000;
+ u32 tmpValue;
+
+ do
+ { +
+ udelay(10); +
+ tmpValue = read_nic_dword(dev, WFM5);
+ if(tmpValue == 0)
+ {
+ RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
+ break;
+ }
+ else
+ {
+ RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
+ }
+ }while( --PollingCnt );
+
+ if(PollingCnt == 0)
+ {
+ RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
+ }
+}
+void rtl8192_SetFwCmdIOCallback(struct net_device* dev)
+{
+ struct r8192_priv *priv = rtllib_priv(dev);
+ u32 input,CurrentAID = 0;
+
+#ifdef _RTL8192_EXT_PATCH_
+ if((!priv->up) && (!priv->mesh_up))
+#else
+ if(!priv->up)
+#endif
+ {
+ RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
+ return;
+ }
+
+ RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
+
+ if(HalGetFirmwareVerison(priv) >= 0x34)
+ {
+ switch(priv->CurrentFwCmdIO)
+ {
+ case FW_CMD_RA_REFRESH_N:
+ priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_N_COMB;
+ break;
+ case FW_CMD_RA_REFRESH_BG:
+ priv->CurrentFwCmdIO = FW_CMD_RA_REFRESH_BG_COMB;
+ break;
+ default:
+ break;
+ }
+ }
+
+ switch(priv->CurrentFwCmdIO)
+ {
+
+ case FW_CMD_RA_RESET:
+ RT_TRACE(COMP_CMD, "[FW CMD] Set RA Reset!!\n");
+ write_nic_dword(dev, WFM5, FW_RA_RESET);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ case FW_CMD_RA_ACTIVE:
+ RT_TRACE(COMP_CMD, "[FW CMD] Set RA Active!!\n");
+ write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ case FW_CMD_RA_REFRESH_N:
+ RT_TRACE(COMP_CMD, "[FW CMD] Set RA n refresh!!\n");
+ if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
+ input = FW_RA_REFRESH;
+ else
+ input = FW_RA_REFRESH | (priv->rtllib->pHTInfo->IOTRaFunc << 8);
+ write_nic_dword(dev, WFM5, input);
+ ChkFwCmdIoDone(dev);
+ write_nic_dword(dev, WFM5, FW_RA_ENABLE_RSSI_MASK);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ case FW_CMD_RA_REFRESH_BG:
+ RT_TRACE(COMP_CMD, "[FW CMD] Set RA BG refresh!!\n");
+ write_nic_dword(dev, WFM5, FW_RA_REFRESH);
+ ChkFwCmdIoDone(dev);
+ write_nic_dword(dev, WFM5, FW_RA_DISABLE_RSSI_MASK);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ case FW_CMD_RA_REFRESH_N_COMB:
+ RT_TRACE(COMP_CMD, "[FW CMD] Set RA n Combo refresh!!\n");
+ if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
+ input = FW_RA_IOT_N_COMB;
+ else
+ input = FW_RA_IOT_N_COMB | (((priv->rtllib->pHTInfo->IOTRaFunc)&0x0f) << 8);
+ input = input |((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<12);
+ RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in n mode!! input(%#x)\n", input);
+ write_nic_dword(dev, WFM5, input);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ case FW_CMD_RA_REFRESH_BG_COMB:
+ RT_TRACE(COMP_CMD, "[FW CMD] Set RA B/G Combo refresh!!\n");
+ if(priv->rtllib->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
+ input = FW_RA_IOT_BG_COMB;
+ else
+ input = FW_RA_IOT_BG_COMB | (((priv->rtllib->pHTInfo->IOTRaFunc)&0x0f) << 8);
+ input = input |((priv->rtllib->pHTInfo->IOTPeer & 0xf) <<12);
+ RT_TRACE(COMP_CMD, "[FW CMD] Set RA/IOT Comb in B/G mode!! input(%#x)\n", input);
+ write_nic_dword(dev, WFM5, input);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ case FW_CMD_IQK_ENABLE:
+ RT_TRACE(COMP_CMD, "[FW CMD] IQK Enable!!\n");
+ write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ case FW_CMD_PAUSE_DM_BY_SCAN:
+ RT_TRACE(COMP_CMD, "[FW CMD] Pause DM by Scan!!\n");
+ rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
+ rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
+ rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
+ break;
+
+ case FW_CMD_RESUME_DM_BY_SCAN:
+ RT_TRACE(COMP_CMD, "[FW CMD] Resume DM by Scan!!\n");
+ rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
+ rtl8192_phy_setTxPower(dev, priv->rtllib->current_network.channel);
+ break;
+
+ case FW_CMD_HIGH_PWR_DISABLE:
+ RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Disable!!\n");
+ if(priv->DMFlag & HAL_DM_HIPWR_DISABLE)
+ break;
+ rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
+ rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
+ rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
+ break;
+
+ case FW_CMD_HIGH_PWR_ENABLE:
+ RT_TRACE(COMP_CMD, "[FW CMD] High Pwr Enable!!\n");
+ if((priv->DMFlag & HAL_DM_HIPWR_DISABLE) ||
+ (priv->rtllib->bdynamic_txpower_enable == true))
+ break;
+ rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
+ break;
+
+ case FW_CMD_LPS_ENTER:
+ RT_TRACE(COMP_CMD, "[FW CMD] Enter LPS mode!!\n");
+ CurrentAID = priv->rtllib->assoc_id;
+ write_nic_dword(dev, WFM5, (FW_LPS_ENTER| ((CurrentAID|0xc000)<<8)) );
+ ChkFwCmdIoDone(dev);
+ priv->rtllib->pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_EDCA_TURBO;
+ break;
+
+ case FW_CMD_LPS_LEAVE:
+ RT_TRACE(COMP_CMD, "[FW CMD] Leave LPS mode!!\n");
+ write_nic_dword(dev, WFM5, FW_LPS_LEAVE );
+ ChkFwCmdIoDone(dev);
+ priv->rtllib->pHTInfo->IOTAction &= (~HT_IOT_ACT_DISABLE_EDCA_TURBO);
+ break;
+
+ case FW_CMD_ADD_A2_ENTRY:
+ RT_TRACE(COMP_CMD, "[FW CMD] ADD A2 entry!!\n");
+ write_nic_dword(dev, WFM5, FW_ADD_A2_ENTRY);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ case FW_CMD_CTRL_DM_BY_DRIVER:
+ RT_TRACE(COMP_CMD, "[FW CMD] Inform fw driver will do some dm at driver\n");
+ write_nic_dword(dev, WFM5, FW_CTRL_DM_BY_DRIVER);
+ ChkFwCmdIoDone(dev);
+ break;
+ case FW_CMD_CHAN_SET:
+ input = FW_CHAN_SET | (((priv->chan)&0xff) << 8);
+ RT_TRACE(COMP_CMD, "[FW CMD] Inform fw to set channel to %x!!, input(%#x):\n", priv->chan,input);
+ write_nic_dword(dev, WFM5, input);
+ ChkFwCmdIoDone(dev);
+ break;
+
+ default:
+ break;
+ }
+
+
+ ChkFwCmdIoDone(dev);
+
+
+ priv->SetFwCmdInProgress = false; + RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
+}
+
+static void
+phy_CheckEphySwitchReady(struct net_device* dev)
+{
+ u32 delay = 100; + u8 regu1;
+
+ regu1 = read_nic_byte(dev, 0x554);
+ while ((regu1 & BIT5) && (delay > 0))
+ {
+ regu1 = read_nic_byte(dev, 0x554);
+ delay--;
+ udelay(50);
+ }
+ RT_TRACE(COMP_INIT, "regu1=%02x delay = %d\n", regu1, delay);
+
+} +
+#ifdef TO_DO_LIST
+void
+HW_RadioGpioChk92SE(
+ IN PADAPTER pAdapter
+ )
+{
+ PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
+ u1Byte u1Tmp = 0;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ RT_RF_POWER_STATE eRfPowerStateToSet;
+ BOOLEAN bActuallySet = false;
+
+#if 0
+ if (!RT_IN_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3) &&
+ pMgntInfo->RfOffReason != RF_CHANGE_BY_HW)
+ {
+ return;
+ }
+
+ PlatformSwitchClkReq(pAdapter, 0x00);
+
+ if (RT_IN_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3))
+ {
+ RT_LEAVE_D3(pAdapter, false);
+ RT_CLEAR_PS_LEVEL(pAdapter, RT_RF_OFF_LEVL_PCI_D3);
+ Power_DomainInit92SE(pAdapter);
+ }
+
+ PlatformEFIOWrite1Byte(pAdapter, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
+
+ u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IO_SEL);
+ u1Tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
+ PlatformEFIOWrite1Byte(pAdapter, GPIO_IO_SEL, u1Tmp);
+
+ RT_TRACE(COMP_CMD, DBG_LOUD,
+ ("HW_RadioGpioChk92SE HW_RadioGpioChk92SE=%02x\n", HW_RadioGpioChk92SE));
+
+ u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IN);
+
+ eRfPowerStateToSet = (u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? eRfOn : eRfOff;
+
+ if( (pHalData->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))
+ {
+ RT_TRACE(COMP_RF, DBG_LOUD, ("HW_RadioGpioChk92SE - HW Radio ON\n"));
+ pHalData->bHwRadioOff = false;
+ bActuallySet = true;
+ }
+ else if ( (pHalData->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))
+ {
+ RT_TRACE(COMP_RF, DBG_LOUD, ("HW_RadioGpioChk92SE - HW Radio OFF\n"));
+ pHalData->bHwRadioOff = true;
+ bActuallySet = true;
+ }
+
+ if(bActuallySet)
+ {
+ pHalData->bHwRfOffAction = 1;
+ MgntActSet_RF_State(pAdapter, eRfPowerStateToSet, RF_CHANGE_BY_HW);
+ DrvIFIndicateCurrentPhyStatus(pAdapter);
+
+
+ {
+ PMP_ADAPTER pDevice = &(pAdapter->NdisAdapter);
+ if(pDevice->RegHwSwRfOffD3 == 1 || pDevice->RegHwSwRfOffD3 == 2) + (eRfPowerStateToSet == eRfOff) ? RT_ENABLE_ASPM(pAdapter) : RT_DISABLE_ASPM(pAdapter);
+ }
+ }
+ RT_TRACE(COMP_RF, DBG_TRACE, ("HW_RadioGpioChk92SE() <--------- \n"));
+#endif
+}/* HW_RadioGpioChk92SE */
+#endif
+#endif diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_phy.h b/ubuntu/rtl8192se/rtl8192s/r8192S_phy.h new file mode 100644 index 000000000000..acd9cabeceb1 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_phy.h @@ -0,0 +1,202 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+/* Check to see if the file has been included already. */
+#ifndef _R8192S_PHY_H
+#define _R8192S_PHY_H
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT 5
+#define MAX_STALL_TIME 50 +#define AntennaDiversityValue 0x80 +#define MAX_TXPWR_IDX_NMODE_92S 63
+#define Reset_Cnt_Limit 3
+
+
+#define MAX_PRECMD_CNT 16
+#define MAX_RFDEPENDCMD_CNT 16
+#define MAX_POSTCMD_CNT 16
+#ifdef RTL8192SE
+#define SET_RTL8192SE_RF_SLEEP(dev) \
+{ \
+ u8 u1bTmp; \
+ u1bTmp = read_nic_byte (dev, LDOV12D_CTRL); \
+ u1bTmp |= BIT0; \
+ write_nic_byte(dev, LDOV12D_CTRL, u1bTmp); \
+ write_nic_byte(dev, SPS1_CTRL, 0x0); \
+ write_nic_byte(dev, TXPAUSE, 0xFF); \
+ write_nic_word(dev, CMDR, 0x57FC); \
+ udelay(100); \
+ write_nic_word(dev, CMDR, 0x77FC); \
+ write_nic_byte(dev, PHY_CCA, 0x0); \
+ udelay(10); \
+ write_nic_word(dev, CMDR, 0x37FC); \
+ udelay(10); \
+ write_nic_word(dev, CMDR, 0x77FC); \
+ udelay(10); \
+ write_nic_word(dev, CMDR, 0x57FC); \
+}
+
+
+#endif
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+typedef enum _SwChnlCmdID{
+ CmdID_End,
+ CmdID_SetTxPowerLevel,
+ CmdID_BBRegWrite10,
+ CmdID_WritePortUlong,
+ CmdID_WritePortUshort,
+ CmdID_WritePortUchar,
+ CmdID_RF_WriteReg,
+}SwChnlCmdID;
+
+
+typedef struct _SwChnlCmd{
+ SwChnlCmdID CmdID;
+ u32 Para1;
+ u32 Para2;
+ u32 msDelay;
+}__attribute__ ((packed)) SwChnlCmd;
+
+extern u32 rtl819XMACPHY_Array_PG[];
+extern u32 rtl819XPHY_REG_1T2RArray[];
+extern u32 rtl819XAGCTAB_Array[];
+extern u32 rtl819XRadioA_Array[];
+extern u32 rtl819XRadioB_Array[];
+extern u32 rtl819XRadioC_Array[];
+extern u32 rtl819XRadioD_Array[];
+
+typedef enum _HW90_BLOCK{
+ HW90_BLOCK_MAC = 0,
+ HW90_BLOCK_PHY0 = 1,
+ HW90_BLOCK_PHY1 = 2,
+ HW90_BLOCK_RF = 3,
+ HW90_BLOCK_MAXIMUM = 4, +}HW90_BLOCK_E, *PHW90_BLOCK_E;
+
+typedef enum _RF90_RADIO_PATH{
+ RF90_PATH_A = 0, + RF90_PATH_B = 1, + RF90_PATH_C = 2, + RF90_PATH_D = 3, +#ifndef _RTL8192_EXT_PATCH_
+ RF90_PATH_MAX = 4, +#endif
+}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
+#ifdef _RTL8192_EXT_PATCH_
+#define RF90_PATH_MAX 2
+#endif
+
+#define bMaskByte0 0xff
+#define bMaskByte1 0xff00
+#define bMaskByte2 0xff0000
+#define bMaskByte3 0xff000000
+#define bMaskHWord 0xffff0000
+#define bMaskLWord 0x0000ffff
+#define bMaskDWord 0xffffffff
+
+typedef enum _BaseBand_Config_Type{
+ BaseBand_Config_PHY_REG = 0, + BaseBand_Config_AGC_TAB = 1, +}BaseBand_Config_Type, *PBaseBand_Config_Type;
+
+typedef enum _VERSION_8190{
+ VERSION_8190_BD=0x3,
+ VERSION_8190_BE
+}VERSION_8190,*PVERSION_8190;
+
+
+typedef enum _VERSION_8192S{
+ VERSION_8192S_ACUT,
+ VERSION_8192S_BCUT,
+ VERSION_8192S_CCUT
+}VERSION_8192S,*PVERSION_8192S;
+
+typedef enum _PHY_Rate_Tx_Power_Offset_Area{
+ RA_OFFSET_LEGACY_OFDM1,
+ RA_OFFSET_LEGACY_OFDM2,
+ RA_OFFSET_HT_OFDM1,
+ RA_OFFSET_HT_OFDM2,
+ RA_OFFSET_HT_OFDM3,
+ RA_OFFSET_HT_OFDM4,
+ RA_OFFSET_HT_CCK,
+}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
+
+typedef enum _RATR_TABLE_MODE_8192S{
+ RATR_INX_WIRELESS_NGB = 0,
+ RATR_INX_WIRELESS_NG = 1,
+ RATR_INX_WIRELESS_NB = 2,
+ RATR_INX_WIRELESS_N = 3,
+ RATR_INX_WIRELESS_GB = 4,
+ RATR_INX_WIRELESS_G = 5,
+ RATR_INX_WIRELESS_B = 6,
+ RATR_INX_WIRELESS_MC = 7,
+ RATR_INX_WIRELESS_A = 8,
+}RATR_TABLE_MODE_8192S, *PRATR_TABLE_MODE_8192S;
+
+/*------------------------------Define structure----------------------------*/
+
+
+/*------------------------Export global variable----------------------------*/
+/*------------------------Export global variable----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+
+extern u32 rtl8192_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask);
+extern void rtl8192_setBBreg(struct net_device* dev,u32 RegAddr, u32 BitMask,u32 Data);
+extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
+extern void rtl8192_phy_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr,u32 BitMask,u32 Data);
+
+bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
+
+
+extern bool PHY_MACConfig8192S(struct net_device* dev);
+extern bool PHY_BBConfig8192S(struct net_device* dev);
+extern bool PHY_RFConfig8192S(struct net_device* dev);
+
+extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath);
+extern void rtl8192_SetBWMode(struct net_device* dev,HT_CHANNEL_WIDTH ChnlWidth,HT_EXTCHNL_OFFSET Offset );
+extern u8 rtl8192_phy_SwChnl(struct net_device* dev,u8 channel);
+extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev,u32 eRFPath );
+extern void rtl8192_BBConfig(struct net_device* dev);
+extern void PHY_IQCalibrateBcut(struct net_device* dev);
+extern void PHY_IQCalibrate(struct net_device* dev);
+extern void PHY_GetHWRegOriginalValue(struct net_device* dev);
+
+extern void InitialGainOperateWorkItemCallBack(void *data);
+void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
+
+/*--------------------------Exported Function prototype---------------------*/
+bool rtl8192se_set_fw_cmd(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO);
+extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval);
+void ChkFwCmdIoDone(struct net_device* dev);
+void PHY_SwitchEphyParameter(struct net_device* dev);
+bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState);
+
+#endif +
diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_phyreg.h b/ubuntu/rtl8192se/rtl8192s/r8192S_phyreg.h new file mode 100644 index 000000000000..28e82f23ebb2 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_phyreg.h @@ -0,0 +1,954 @@ +/******************************************************************************
+ * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+******************************************************************************/
+#ifndef __INC_HAL8192SPHYREG_H
+#define __INC_HAL8192SPHYREG_H
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+
+
+#define rPMAC_Reset 0x100
+#define rPMAC_TxStart 0x104
+#define rPMAC_TxLegacySIG 0x108
+#define rPMAC_TxHTSIG1 0x10c
+#define rPMAC_TxHTSIG2 0x110
+#define rPMAC_PHYDebug 0x114
+#define rPMAC_TxPacketNum 0x118
+#define rPMAC_TxIdle 0x11c
+#define rPMAC_TxMACHeader0 0x120
+#define rPMAC_TxMACHeader1 0x124
+#define rPMAC_TxMACHeader2 0x128
+#define rPMAC_TxMACHeader3 0x12c
+#define rPMAC_TxMACHeader4 0x130
+#define rPMAC_TxMACHeader5 0x134
+#define rPMAC_TxDataType 0x138
+#define rPMAC_TxRandomSeed 0x13c
+#define rPMAC_CCKPLCPPreamble 0x140
+#define rPMAC_CCKPLCPHeader 0x144
+#define rPMAC_CCKCRC16 0x148
+#define rPMAC_OFDMRxCRC32OK 0x170
+#define rPMAC_OFDMRxCRC32Er 0x174
+#define rPMAC_OFDMRxParityEr 0x178
+#define rPMAC_OFDMRxCRC8Er 0x17c
+#define rPMAC_CCKCRxRC16Er 0x180
+#define rPMAC_CCKCRxRC32Er 0x184
+#define rPMAC_CCKCRxRC32OK 0x188
+#define rPMAC_TxStatus 0x18c
+
+#define RF_BB_CMD_ADDR 0x02c0 +#define RF_BB_CMD_DATA 0x02c4 +
+#define rFPGA0_RFMOD 0x800 +
+#define rFPGA0_TxInfo 0x804 +#define rFPGA0_PSDFunction 0x808
+
+#define rFPGA0_TxGainStage 0x80c +
+#define rFPGA0_RFTiming1 0x810 +#define rFPGA0_RFTiming2 0x814
+
+#define rFPGA0_XA_HSSIParameter1 0x820 +#define rFPGA0_XA_HSSIParameter2 0x824
+#define rFPGA0_XB_HSSIParameter1 0x828
+#define rFPGA0_XB_HSSIParameter2 0x82c
+#define rFPGA0_XC_HSSIParameter1 0x830
+#define rFPGA0_XC_HSSIParameter2 0x834
+#define rFPGA0_XD_HSSIParameter1 0x838
+#define rFPGA0_XD_HSSIParameter2 0x83c
+#define rFPGA0_XA_LSSIParameter 0x840
+#define rFPGA0_XB_LSSIParameter 0x844
+#define rFPGA0_XC_LSSIParameter 0x848
+#define rFPGA0_XD_LSSIParameter 0x84c
+
+#define rFPGA0_RFWakeUpParameter 0x850 +#define rFPGA0_RFSleepUpParameter 0x854
+
+#define rFPGA0_XAB_SwitchControl 0x858 +#define rFPGA0_XCD_SwitchControl 0x85c
+
+#define rFPGA0_XA_RFInterfaceOE 0x860 +#define rFPGA0_XB_RFInterfaceOE 0x864
+#define rFPGA0_XC_RFInterfaceOE 0x868
+#define rFPGA0_XD_RFInterfaceOE 0x86c
+
+#define rFPGA0_XAB_RFInterfaceSW 0x870 +#define rFPGA0_XCD_RFInterfaceSW 0x874
+
+#define rFPGA0_XAB_RFParameter 0x878 +#define rFPGA0_XCD_RFParameter 0x87c
+
+#define rFPGA0_AnalogParameter1 0x880 +#define rFPGA0_AnalogParameter2 0x884
+#define rFPGA0_AnalogParameter3 0x888 +#define rFPGA0_AnalogParameter4 0x88c
+
+#define rFPGA0_XA_LSSIReadBack 0x8a0 +#define rFPGA0_XB_LSSIReadBack 0x8a4
+#define rFPGA0_XC_LSSIReadBack 0x8a8
+#define rFPGA0_XD_LSSIReadBack 0x8ac
+
+#define rFPGA0_PSDReport 0x8b4 +#define TransceiverA_HSPI_Readback 0x8b8 +#define TransceiverB_HSPI_Readback 0x8bc +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 +
+#define rFPGA1_RFMOD 0x900 +
+#define rFPGA1_TxBlock 0x904 +#define rFPGA1_DebugSelect 0x908 +#define rFPGA1_TxInfo 0x90c +
+#define rCCK0_System 0xa00
+
+#define rCCK0_AFESetting 0xa04 +#define rCCK0_CCA 0xa08 +
+#define rCCK0_RxAGC1 0xa0c +#define rCCK0_RxAGC2 0xa10 +
+#define rCCK0_RxHP 0xa14
+
+#define rCCK0_DSPParameter1 0xa18 +#define rCCK0_DSPParameter2 0xa1c +
+#define rCCK0_TxFilter1 0xa20
+#define rCCK0_TxFilter2 0xa24
+#define rCCK0_DebugPort 0xa28 +#define rCCK0_FalseAlarmReport 0xa2c +#define rCCK0_TRSSIReport 0xa50
+#define rCCK0_RxReport 0xa54 +#define rCCK0_FACounterLower 0xa5c +#define rCCK0_FACounterUpper 0xa58 +
+#define rOFDM0_LSTF 0xc00
+
+#define rOFDM0_TRxPathEnable 0xc04
+#define rOFDM0_TRMuxPar 0xc08
+#define rOFDM0_TRSWIsolation 0xc0c
+
+#define rOFDM0_XARxAFE 0xc10 +#define rOFDM0_XARxIQImbalance 0xc14 +#define rOFDM0_XBRxAFE 0xc18
+#define rOFDM0_XBRxIQImbalance 0xc1c
+#define rOFDM0_XCRxAFE 0xc20
+#define rOFDM0_XCRxIQImbalance 0xc24
+#define rOFDM0_XDRxAFE 0xc28
+#define rOFDM0_XDRxIQImbalance 0xc2c
+
+#define rOFDM0_RxDetector1 0xc30 +#define rOFDM0_RxDetector2 0xc34 +#define rOFDM0_RxDetector3 0xc38 +#define rOFDM0_RxDetector4 0xc3c +
+#define rOFDM0_RxDSP 0xc40 +#define rOFDM0_CFOandDAGC 0xc44 +#define rOFDM0_CCADropThreshold 0xc48 +#define rOFDM0_ECCAThreshold 0xc4c +
+#define rOFDM0_XAAGCCore1 0xc50 +#define rOFDM0_XAAGCCore2 0xc54
+#define rOFDM0_XBAGCCore1 0xc58
+#define rOFDM0_XBAGCCore2 0xc5c
+#define rOFDM0_XCAGCCore1 0xc60
+#define rOFDM0_XCAGCCore2 0xc64
+#define rOFDM0_XDAGCCore1 0xc68
+#define rOFDM0_XDAGCCore2 0xc6c
+
+#define rOFDM0_AGCParameter1 0xc70
+#define rOFDM0_AGCParameter2 0xc74
+#define rOFDM0_AGCRSSITable 0xc78
+#define rOFDM0_HTSTFAGC 0xc7c
+
+#define rOFDM0_XATxIQImbalance 0xc80 +#define rOFDM0_XATxAFE 0xc84
+#define rOFDM0_XBTxIQImbalance 0xc88
+#define rOFDM0_XBTxAFE 0xc8c
+#define rOFDM0_XCTxIQImbalance 0xc90
+#define rOFDM0_XCTxAFE 0xc94
+#define rOFDM0_XDTxIQImbalance 0xc98
+#define rOFDM0_XDTxAFE 0xc9c
+
+#define rOFDM0_RxHPParameter 0xce0
+#define rOFDM0_TxPseudoNoiseWgt 0xce4
+#define rOFDM0_FrameSync 0xcf0
+#define rOFDM0_DFSReport 0xcf4
+#define rOFDM0_TxCoeff1 0xca4
+#define rOFDM0_TxCoeff2 0xca8
+#define rOFDM0_TxCoeff3 0xcac
+#define rOFDM0_TxCoeff4 0xcb0
+#define rOFDM0_TxCoeff5 0xcb4
+#define rOFDM0_TxCoeff6 0xcb8
+
+
+#define rOFDM1_LSTF 0xd00
+#define rOFDM1_TRxPathEnable 0xd04
+
+#define rOFDM1_CFO 0xd08 +#define rOFDM1_CSI1 0xd10
+#define rOFDM1_SBD 0xd14
+#define rOFDM1_CSI2 0xd18
+#define rOFDM1_CFOTracking 0xd2c
+#define rOFDM1_TRxMesaure1 0xd34
+#define rOFDM1_IntfDet 0xd3c
+#define rOFDM1_PseudoNoiseStateAB 0xd50
+#define rOFDM1_PseudoNoiseStateCD 0xd54
+#define rOFDM1_RxPseudoNoiseWgt 0xd58
+
+#define rOFDM_PHYCounter1 0xda0 +#define rOFDM_PHYCounter2 0xda4 +#define rOFDM_PHYCounter3 0xda8 +
+#define rOFDM_ShortCFOAB 0xdac +#define rOFDM_ShortCFOCD 0xdb0
+#define rOFDM_LongCFOAB 0xdb4
+#define rOFDM_LongCFOCD 0xdb8
+#define rOFDM_TailCFOAB 0xdbc
+#define rOFDM_TailCFOCD 0xdc0
+#define rOFDM_PWMeasure1 0xdc4
+#define rOFDM_PWMeasure2 0xdc8
+#define rOFDM_BWReport 0xdcc
+#define rOFDM_AGCReport 0xdd0
+#define rOFDM_RxSNR 0xdd4
+#define rOFDM_RxEVMCSI 0xdd8
+#define rOFDM_SIGReport 0xddc
+
+
+#define rTxAGC_Rate18_06 0xe00
+#define rTxAGC_Rate54_24 0xe04
+#define rTxAGC_CCK_Mcs32 0xe08
+#define rTxAGC_Mcs03_Mcs00 0xe10
+#define rTxAGC_Mcs07_Mcs04 0xe14
+#define rTxAGC_Mcs11_Mcs08 0xe18
+#define rTxAGC_Mcs15_Mcs12 0xe1c
+
+#define rZebra1_HSSIEnable 0x0 +#define rZebra1_TRxEnable1 0x1
+#define rZebra1_TRxEnable2 0x2
+#define rZebra1_AGC 0x4
+#define rZebra1_ChargePump 0x5
+#define rZebra1_Channel 0x7 +
+#define rZebra1_TxGain 0x8 +#define rZebra1_TxLPF 0x9
+#define rZebra1_RxLPF 0xb
+#define rZebra1_RxHPFCorner 0xc
+
+#define rGlobalCtrl 0 +#define rRTL8256_TxLPF 19
+#define rRTL8256_RxLPF 11
+
+#define rRTL8258_TxLPF 0x11 +#define rRTL8258_RxLPF 0x13
+#define rRTL8258_RSSILPF 0xa
+
+#define RF_AC 0x00 +
+#define RF_IQADJ_G1 0x01 +#define RF_IQADJ_G2 0x02 +#define RF_POW_TRSW 0x05 +
+#define RF_GAIN_RX 0x06 +#define RF_GAIN_TX 0x07 +
+#define RF_TXM_IDAC 0x08 +#define RF_BS_IQGEN 0x0F +
+#define RF_MODE1 0x10 +#define RF_MODE2 0x11 +
+#define RF_RX_AGC_HP 0x12 +#define RF_TX_AGC 0x13 +#define RF_BIAS 0x14 +#define RF_IPA 0x15 +#define RF_POW_ABILITY 0x17 +#define RF_MODE_AG 0x18 +#define rRfChannel 0x18 +#define RF_CHNLBW 0x18 +#define RF_TOP 0x19 +
+#define RF_RX_G1 0x1A +#define RF_RX_G2 0x1B +
+#define RF_RX_BB2 0x1C +#define RF_RX_BB1 0x1D +
+#define RF_RCK1 0x1E +#define RF_RCK2 0x1F +
+#define RF_TX_G1 0x20 +#define RF_TX_G2 0x21 +#define RF_TX_G3 0x22 +
+#define RF_TX_BB1 0x23 +
+#define RF_T_METER 0x24 +
+#define RF_SYN_G1 0x25 +#define RF_SYN_G2 0x26 +#define RF_SYN_G3 0x27 +#define RF_SYN_G4 0x28 +#define RF_SYN_G5 0x29 +#define RF_SYN_G6 0x2A +#define RF_SYN_G7 0x2B +#define RF_SYN_G8 0x2C +
+#define RF_RCK_OS 0x30 +
+#define RF_TXPA_G1 0x31 +#define RF_TXPA_G2 0x32 +#define RF_TXPA_G3 0x33 +
+#define bBBResetB 0x100 +#define bGlobalResetB 0x200
+#define bOFDMTxStart 0x4
+#define bCCKTxStart 0x8
+#define bCRC32Debug 0x100
+#define bPMACLoopback 0x10
+#define bTxLSIG 0xffffff
+#define bOFDMTxRate 0xf
+#define bOFDMTxReserved 0x10
+#define bOFDMTxLength 0x1ffe0
+#define bOFDMTxParity 0x20000
+#define bTxHTSIG1 0xffffff
+#define bTxHTMCSRate 0x7f
+#define bTxHTBW 0x80
+#define bTxHTLength 0xffff00
+#define bTxHTSIG2 0xffffff
+#define bTxHTSmoothing 0x1
+#define bTxHTSounding 0x2
+#define bTxHTReserved 0x4
+#define bTxHTAggreation 0x8
+#define bTxHTSTBC 0x30
+#define bTxHTAdvanceCoding 0x40
+#define bTxHTShortGI 0x80
+#define bTxHTNumberHT_LTF 0x300
+#define bTxHTCRC8 0x3fc00
+#define bCounterReset 0x10000
+#define bNumOfOFDMTx 0xffff
+#define bNumOfCCKTx 0xffff0000
+#define bTxIdleInterval 0xffff
+#define bOFDMService 0xffff0000
+#define bTxMACHeader 0xffffffff
+#define bTxDataInit 0xff
+#define bTxHTMode 0x100
+#define bTxDataType 0x30000
+#define bTxRandomSeed 0xffffffff
+#define bCCKTxPreamble 0x1
+#define bCCKTxSFD 0xffff0000
+#define bCCKTxSIG 0xff
+#define bCCKTxService 0xff00
+#define bCCKLengthExt 0x8000
+#define bCCKTxLength 0xffff0000
+#define bCCKTxCRC16 0xffff
+#define bCCKTxStatus 0x1
+#define bOFDMTxStatus 0x2
+
+#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
+
+#define bRFMOD 0x1 +#define bJapanMode 0x2
+#define bCCKTxSC 0x30
+#define bCCKEn 0x1000000
+#define bOFDMEn 0x2000000
+
+#define bOFDMRxADCPhase 0x10000 +#define bOFDMTxDACPhase 0x40000
+#define bXATxAGC 0x3f
+
+#define bXBTxAGC 0xf00 +#define bXCTxAGC 0xf000
+#define bXDTxAGC 0xf0000
+
+#define bPAStart 0xf0000000 +#define bTRStart 0x00f00000
+#define bRFStart 0x0000f000
+#define bBBStart 0x000000f0
+#define bBBCCKStart 0x0000000f
+#define bPAEnd 0xf +#define bTREnd 0x0f000000
+#define bRFEnd 0x000f0000
+#define bCCAMask 0x000000f0 +#define bR2RCCAMask 0x00000f00
+#define bHSSI_R2TDelay 0xf8000000
+#define bHSSI_T2RDelay 0xf80000
+#define bContTxHSSI 0x400 +#define bIGFromCCK 0x200
+#define bAGCAddress 0x3f
+#define bRxHPTx 0x7000
+#define bRxHPT2R 0x38000
+#define bRxHPCCKIni 0xc0000
+#define bAGCTxCode 0xc00000
+#define bAGCRxCode 0x300000
+
+#define b3WireDataLength 0x800 +#define b3WireAddressLength 0x400
+
+#define b3WireRFPowerDown 0x1 +#define b5GPAPEPolarity 0x40000000
+#define b2GPAPEPolarity 0x80000000
+#define bRFSW_TxDefaultAnt 0x3
+#define bRFSW_TxOptionAnt 0x30
+#define bRFSW_RxDefaultAnt 0x300
+#define bRFSW_RxOptionAnt 0x3000
+#define bRFSI_3WireData 0x1
+#define bRFSI_3WireClock 0x2
+#define bRFSI_3WireLoad 0x4
+#define bRFSI_3WireRW 0x8
+#define bRFSI_3Wire 0xf
+
+#define bRFSI_RFENV 0x10 +
+#define bRFSI_TRSW 0x20 +#define bRFSI_TRSWB 0x40
+#define bRFSI_ANTSW 0x100
+#define bRFSI_ANTSWB 0x200
+#define bRFSI_PAPE 0x400
+#define bRFSI_PAPE5G 0x800
+#define bBandSelect 0x1
+#define bHTSIG2_GI 0x80
+#define bHTSIG2_Smoothing 0x01
+#define bHTSIG2_Sounding 0x02
+#define bHTSIG2_Aggreaton 0x08
+#define bHTSIG2_STBC 0x30
+#define bHTSIG2_AdvCoding 0x40
+#define bHTSIG2_NumOfHTLTF 0x300
+#define bHTSIG2_CRC8 0x3fc
+#define bHTSIG1_MCS 0x7f
+#define bHTSIG1_BandWidth 0x80
+#define bHTSIG1_HTLength 0xffff
+#define bLSIG_Rate 0xf
+#define bLSIG_Reserved 0x10
+#define bLSIG_Length 0x1fffe
+#define bLSIG_Parity 0x20
+#define bCCKRxPhase 0x4
+#if (RTL92SE_FPGA_VERIFY == 1)
+#define bLSSIReadAddress 0x3f000000 +#else
+#define bLSSIReadAddress 0x7f800000 +#endif
+#define bLSSIReadEdge 0x80000000 +#if (RTL92SE_FPGA_VERIFY == 1)
+#define bLSSIReadBackData 0xfff +#else
+#define bLSSIReadBackData 0xfffff +#endif
+#define bLSSIReadOKFlag 0x1000 +#define bCCKSampleRate 0x8 +#define bRegulator0Standby 0x1
+#define bRegulatorPLLStandby 0x2
+#define bRegulator1Standby 0x4
+#define bPLLPowerUp 0x8
+#define bDPLLPowerUp 0x10
+#define bDA10PowerUp 0x20
+#define bAD7PowerUp 0x200
+#define bDA6PowerUp 0x2000
+#define bXtalPowerUp 0x4000
+#define b40MDClkPowerUP 0x8000
+#define bDA6DebugMode 0x20000
+#define bDA6Swing 0x380000
+
+#define bADClkPhase 0x4000000 +
+#define b80MClkDelay 0x18000000 +#define bAFEWatchDogEnable 0x20000000
+
+#define bXtalCap01 0xc0000000 +#define bXtalCap23 0x3
+#define bXtalCap92x 0x0f000000
+#define bXtalCap 0x0f000000
+
+#define bIntDifClkEnable 0x400 +#define bExtSigClkEnable 0x800
+#define bBandgapMbiasPowerUp 0x10000
+#define bAD11SHGain 0xc0000
+#define bAD11InputRange 0x700000
+#define bAD11OPCurrent 0x3800000
+#define bIPathLoopback 0x4000000
+#define bQPathLoopback 0x8000000
+#define bAFELoopback 0x10000000
+#define bDA10Swing 0x7e0
+#define bDA10Reverse 0x800
+#define bDAClkSource 0x1000
+#define bAD7InputRange 0x6000
+#define bAD7Gain 0x38000
+#define bAD7OutputCMMode 0x40000
+#define bAD7InputCMMode 0x380000
+#define bAD7Current 0xc00000
+#define bRegulatorAdjust 0x7000000
+#define bAD11PowerUpAtTx 0x1
+#define bDA10PSAtTx 0x10
+#define bAD11PowerUpAtRx 0x100
+#define bDA10PSAtRx 0x1000
+#define bCCKRxAGCFormat 0x200
+#define bPSDFFTSamplepPoint 0xc000
+#define bPSDAverageNum 0x3000
+#define bIQPathControl 0xc00
+#define bPSDFreq 0x3ff
+#define bPSDAntennaPath 0x30
+#define bPSDIQSwitch 0x40
+#define bPSDRxTrigger 0x400000
+#define bPSDTxTrigger 0x80000000
+#define bPSDSineToneScale 0x7f000000
+#define bPSDReport 0xffff
+
+#define bOFDMTxSC 0x30000000 +#define bCCKTxOn 0x1
+#define bOFDMTxOn 0x2
+#define bDebugPage 0xfff +#define bDebugItem 0xff +#define bAntL 0x10
+#define bAntNonHT 0x100
+#define bAntHT1 0x1000
+#define bAntHT2 0x10000
+#define bAntHT1S1 0x100000
+#define bAntNonHTS1 0x1000000
+
+#define bCCKBBMode 0x3 +#define bCCKTxPowerSaving 0x80
+#define bCCKRxPowerSaving 0x40
+
+#define bCCKSideBand 0x10 +
+#define bCCKScramble 0x8 +#define bCCKAntDiversity 0x8000
+#define bCCKCarrierRecovery 0x4000
+#define bCCKTxRate 0x3000
+#define bCCKDCCancel 0x0800
+#define bCCKISICancel 0x0400
+#define bCCKMatchFilter 0x0200
+#define bCCKEqualizer 0x0100
+#define bCCKPreambleDetect 0x800000
+#define bCCKFastFalseCCA 0x400000
+#define bCCKChEstStart 0x300000
+#define bCCKCCACount 0x080000
+#define bCCKcs_lim 0x070000
+#define bCCKBistMode 0x80000000
+#define bCCKCCAMask 0x40000000
+#define bCCKTxDACPhase 0x4
+#define bCCKRxADCPhase 0x20000000 +#define bCCKr_cp_mode0 0x0100
+#define bCCKTxDCOffset 0xf0
+#define bCCKRxDCOffset 0xf
+#define bCCKCCAMode 0xc000
+#define bCCKFalseCS_lim 0x3f00
+#define bCCKCS_ratio 0xc00000
+#define bCCKCorgBit_sel 0x300000
+#define bCCKPD_lim 0x0f0000
+#define bCCKNewCCA 0x80000000
+#define bCCKRxHPofIG 0x8000
+#define bCCKRxIG 0x7f00
+#define bCCKLNAPolarity 0x800000
+#define bCCKRx1stGain 0x7f0000
+#define bCCKRFExtend 0x20000000 +#define bCCKRxAGCSatLevel 0x1f000000
+#define bCCKRxAGCSatCount 0xe0
+#define bCCKRxRFSettle 0x1f +#define bCCKFixedRxAGC 0x8000
+#define bCCKAntennaPolarity 0x2000
+#define bCCKTxFilterType 0x0c00
+#define bCCKRxAGCReportType 0x0300
+#define bCCKRxDAGCEn 0x80000000
+#define bCCKRxDAGCPeriod 0x20000000
+#define bCCKRxDAGCSatLevel 0x1f000000
+#define bCCKTimingRecovery 0x800000
+#define bCCKTxC0 0x3f0000
+#define bCCKTxC1 0x3f000000
+#define bCCKTxC2 0x3f
+#define bCCKTxC3 0x3f00
+#define bCCKTxC4 0x3f0000
+#define bCCKTxC5 0x3f000000
+#define bCCKTxC6 0x3f
+#define bCCKTxC7 0x3f00
+#define bCCKDebugPort 0xff0000
+#define bCCKDACDebug 0x0f000000
+#define bCCKFalseAlarmEnable 0x8000
+#define bCCKFalseAlarmRead 0x4000
+#define bCCKTRSSI 0x7f
+#define bCCKRxAGCReport 0xfe
+#define bCCKRxReport_AntSel 0x80000000
+#define bCCKRxReport_MFOff 0x40000000
+#define bCCKRxRxReport_SQLoss 0x20000000
+#define bCCKRxReport_Pktloss 0x10000000
+#define bCCKRxReport_Lockedbit 0x08000000
+#define bCCKRxReport_RateError 0x04000000
+#define bCCKRxReport_RxRate 0x03000000
+#define bCCKRxFACounterLower 0xff
+#define bCCKRxFACounterUpper 0xff000000
+#define bCCKRxHPAGCStart 0xe000
+#define bCCKRxHPAGCFinal 0x1c00
+#define bCCKRxFalseAlarmEnable 0x8000
+#define bCCKFACounterFreeze 0x4000
+#define bCCKTxPathSel 0x10000000
+#define bCCKDefaultRxPath 0xc000000
+#define bCCKOptionRxPath 0x3000000
+
+#define bNumOfSTF 0x3 +#define bShift_L 0xc0
+#define bGI_TH 0xc
+#define bRxPathA 0x1
+#define bRxPathB 0x2
+#define bRxPathC 0x4
+#define bRxPathD 0x8
+#define bTxPathA 0x1
+#define bTxPathB 0x2
+#define bTxPathC 0x4
+#define bTxPathD 0x8
+#define bTRSSIFreq 0x200
+#define bADCBackoff 0x3000
+#define bDFIRBackoff 0xc000
+#define bTRSSILatchPhase 0x10000
+#define bRxIDCOffset 0xff
+#define bRxQDCOffset 0xff00
+#define bRxDFIRMode 0x1800000
+#define bRxDCNFType 0xe000000
+#define bRXIQImb_A 0x3ff
+#define bRXIQImb_B 0xfc00
+#define bRXIQImb_C 0x3f0000
+#define bRXIQImb_D 0xffc00000
+#define bDC_dc_Notch 0x60000
+#define bRxNBINotch 0x1f000000
+#define bPD_TH 0xf
+#define bPD_TH_Opt2 0xc000
+#define bPWED_TH 0x700
+#define bIfMF_Win_L 0x800
+#define bPD_Option 0x1000
+#define bMF_Win_L 0xe000
+#define bBW_Search_L 0x30000
+#define bwin_enh_L 0xc0000
+#define bBW_TH 0x700000
+#define bED_TH2 0x3800000
+#define bBW_option 0x4000000
+#define bRatio_TH 0x18000000
+#define bWindow_L 0xe0000000
+#define bSBD_Option 0x1
+#define bFrame_TH 0x1c
+#define bFS_Option 0x60
+#define bDC_Slope_check 0x80
+#define bFGuard_Counter_DC_L 0xe00
+#define bFrame_Weight_Short 0x7000
+#define bSub_Tune 0xe00000
+#define bFrame_DC_Length 0xe000000
+#define bSBD_start_offset 0x30000000
+#define bFrame_TH_2 0x7
+#define bFrame_GI2_TH 0x38
+#define bGI2_Sync_en 0x40
+#define bSarch_Short_Early 0x300
+#define bSarch_Short_Late 0xc00
+#define bSarch_GI2_Late 0x70000
+#define bCFOAntSum 0x1
+#define bCFOAcc 0x2
+#define bCFOStartOffset 0xc
+#define bCFOLookBack 0x70
+#define bCFOSumWeight 0x80
+#define bDAGCEnable 0x10000
+#define bTXIQImb_A 0x3ff
+#define bTXIQImb_B 0xfc00
+#define bTXIQImb_C 0x3f0000
+#define bTXIQImb_D 0xffc00000
+#define bTxIDCOffset 0xff
+#define bTxQDCOffset 0xff00
+#define bTxDFIRMode 0x10000
+#define bTxPesudoNoiseOn 0x4000000
+#define bTxPesudoNoise_A 0xff
+#define bTxPesudoNoise_B 0xff00
+#define bTxPesudoNoise_C 0xff0000
+#define bTxPesudoNoise_D 0xff000000
+#define bCCADropOption 0x20000
+#define bCCADropThres 0xfff00000
+#define bEDCCA_H 0xf
+#define bEDCCA_L 0xf0
+#define bLambda_ED 0x300
+#define bRxInitialGain 0x7f
+#define bRxAntDivEn 0x80
+#define bRxAGCAddressForLNA 0x7f00
+#define bRxHighPowerFlow 0x8000
+#define bRxAGCFreezeThres 0xc0000
+#define bRxFreezeStep_AGC1 0x300000
+#define bRxFreezeStep_AGC2 0xc00000
+#define bRxFreezeStep_AGC3 0x3000000
+#define bRxFreezeStep_AGC0 0xc000000
+#define bRxRssi_Cmp_En 0x10000000
+#define bRxQuickAGCEn 0x20000000
+#define bRxAGCFreezeThresMode 0x40000000
+#define bRxOverFlowCheckType 0x80000000
+#define bRxAGCShift 0x7f
+#define bTRSW_Tri_Only 0x80
+#define bPowerThres 0x300
+#define bRxAGCEn 0x1
+#define bRxAGCTogetherEn 0x2
+#define bRxAGCMin 0x4
+#define bRxHP_Ini 0x7
+#define bRxHP_TRLNA 0x70
+#define bRxHP_RSSI 0x700
+#define bRxHP_BBP1 0x7000
+#define bRxHP_BBP2 0x70000
+#define bRxHP_BBP3 0x700000
+#define bRSSI_H 0x7f0000 +#define bRSSI_Gen 0x7f000000 +#define bRxSettle_TRSW 0x7
+#define bRxSettle_LNA 0x38
+#define bRxSettle_RSSI 0x1c0
+#define bRxSettle_BBP 0xe00
+#define bRxSettle_RxHP 0x7000
+#define bRxSettle_AntSW_RSSI 0x38000
+#define bRxSettle_AntSW 0xc0000
+#define bRxProcessTime_DAGC 0x300000
+#define bRxSettle_HSSI 0x400000
+#define bRxProcessTime_BBPPW 0x800000
+#define bRxAntennaPowerShift 0x3000000
+#define bRSSITableSelect 0xc000000
+#define bRxHP_Final 0x7000000
+#define bRxHTSettle_BBP 0x7
+#define bRxHTSettle_HSSI 0x8
+#define bRxHTSettle_RxHP 0x70
+#define bRxHTSettle_BBPPW 0x80
+#define bRxHTSettle_Idle 0x300
+#define bRxHTSettle_Reserved 0x1c00
+#define bRxHTRxHPEn 0x8000
+#define bRxHTAGCFreezeThres 0x30000
+#define bRxHTAGCTogetherEn 0x40000
+#define bRxHTAGCMin 0x80000
+#define bRxHTAGCEn 0x100000
+#define bRxHTDAGCEn 0x200000
+#define bRxHTRxHP_BBP 0x1c00000
+#define bRxHTRxHP_Final 0xe0000000
+#define bRxPWRatioTH 0x3
+#define bRxPWRatioEn 0x4
+#define bRxMFHold 0x3800
+#define bRxPD_Delay_TH1 0x38
+#define bRxPD_Delay_TH2 0x1c0
+#define bRxPD_DC_COUNT_MAX 0x600
+#define bRxPD_Delay_TH 0x8000
+#define bRxProcess_Delay 0xf0000
+#define bRxSearchrange_GI2_Early 0x700000
+#define bRxFrame_Guard_Counter_L 0x3800000
+#define bRxSGI_Guard_L 0xc000000
+#define bRxSGI_Search_L 0x30000000
+#define bRxSGI_TH 0xc0000000
+#define bDFSCnt0 0xff
+#define bDFSCnt1 0xff00
+#define bDFSFlag 0xf0000
+#define bMFWeightSum 0x300000
+#define bMinIdxTH 0x7f000000
+#define bDAFormat 0x40000
+#define bTxChEmuEnable 0x01000000
+#define bTRSWIsolation_A 0x7f
+#define bTRSWIsolation_B 0x7f00
+#define bTRSWIsolation_C 0x7f0000
+#define bTRSWIsolation_D 0x7f000000
+#define bExtLNAGain 0x7c00
+
+#define bSTBCEn 0x4 +#define bAntennaMapping 0x10
+#define bNss 0x20
+#define bCFOAntSumD 0x200
+#define bPHYCounterReset 0x8000000
+#define bCFOReportGet 0x4000000
+#define bOFDMContinueTx 0x10000000
+#define bOFDMSingleCarrier 0x20000000
+#define bOFDMSingleTone 0x40000000
+#define bHTDetect 0x100
+#define bCFOEn 0x10000
+#define bCFOValue 0xfff00000
+#define bSigTone_Re 0x3f
+#define bSigTone_Im 0x7f00
+#define bCounter_CCA 0xffff
+#define bCounter_ParityFail 0xffff0000
+#define bCounter_RateIllegal 0xffff
+#define bCounter_CRC8Fail 0xffff0000
+#define bCounter_MCSNoSupport 0xffff
+#define bCounter_FastSync 0xffff
+#define bShortCFO 0xfff
+#define bShortCFOTLength 12 +#define bShortCFOFLength 11 +#define bLongCFO 0x7ff
+#define bLongCFOTLength 11
+#define bLongCFOFLength 11
+#define bTailCFO 0x1fff
+#define bTailCFOTLength 13
+#define bTailCFOFLength 12
+#define bmax_en_pwdB 0xffff
+#define bCC_power_dB 0xffff0000
+#define bnoise_pwdB 0xffff
+#define bPowerMeasTLength 10
+#define bPowerMeasFLength 3
+#define bRx_HT_BW 0x1
+#define bRxSC 0x6
+#define bRx_HT 0x8
+#define bNB_intf_det_on 0x1
+#define bIntf_win_len_cfg 0x30
+#define bNB_Intf_TH_cfg 0x1c0
+#define bRFGain 0x3f
+#define bTableSel 0x40
+#define bTRSW 0x80
+#define bRxSNR_A 0xff
+#define bRxSNR_B 0xff00
+#define bRxSNR_C 0xff0000
+#define bRxSNR_D 0xff000000
+#define bSNREVMTLength 8
+#define bSNREVMFLength 1
+#define bCSI1st 0xff
+#define bCSI2nd 0xff00
+#define bRxEVM1st 0xff0000
+#define bRxEVM2nd 0xff000000
+#define bSIGEVM 0xff
+#define bPWDB 0xff00
+#define bSGIEN 0x10000
+
+#define bSFactorQAM1 0xf +#define bSFactorQAM2 0xf0
+#define bSFactorQAM3 0xf00
+#define bSFactorQAM4 0xf000
+#define bSFactorQAM5 0xf0000
+#define bSFactorQAM6 0xf0000
+#define bSFactorQAM7 0xf00000
+#define bSFactorQAM8 0xf000000
+#define bSFactorQAM9 0xf0000000
+#define bCSIScheme 0x100000
+
+#define bNoiseLvlTopSet 0x3 +#define bChSmooth 0x4
+#define bChSmoothCfg1 0x38
+#define bChSmoothCfg2 0x1c0
+#define bChSmoothCfg3 0xe00
+#define bChSmoothCfg4 0x7000
+#define bMRCMode 0x800000
+#define bTHEVMCfg 0x7000000
+
+#define bLoopFitType 0x1 +#define bUpdCFO 0x40
+#define bUpdCFOOffData 0x80
+#define bAdvUpdCFO 0x100
+#define bAdvTimeCtrl 0x800
+#define bUpdClko 0x1000
+#define bFC 0x6000
+#define bTrackingMode 0x8000
+#define bPhCmpEnable 0x10000
+#define bUpdClkoLTF 0x20000
+#define bComChCFO 0x40000
+#define bCSIEstiMode 0x80000
+#define bAdvUpdEqz 0x100000
+#define bUChCfg 0x7000000
+#define bUpdEqz 0x8000000
+
+#define bTxAGCRate18_06 0x7f7f7f7f +#define bTxAGCRate54_24 0x7f7f7f7f
+#define bTxAGCRateMCS32 0x7f
+#define bTxAGCRateCCK 0x7f00
+#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
+#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
+#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
+#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
+
+#define bRxPesudoNoiseOn 0x20000000 +#define bRxPesudoNoise_A 0xff
+#define bRxPesudoNoise_B 0xff00
+#define bRxPesudoNoise_C 0xff0000
+#define bRxPesudoNoise_D 0xff000000
+#define bPesudoNoiseState_A 0xffff
+#define bPesudoNoiseState_B 0xffff0000
+#define bPesudoNoiseState_C 0xffff
+#define bPesudoNoiseState_D 0xffff0000
+
+#define bZebra1_HSSIEnable 0x8 +#define bZebra1_TRxControl 0xc00
+#define bZebra1_TRxGainSetting 0x07f
+#define bZebra1_RxCorner 0xc00
+#define bZebra1_TxChargePump 0x38
+#define bZebra1_RxChargePump 0x7
+#define bZebra1_ChannelNum 0xf80
+#define bZebra1_TxLPFBW 0x400
+#define bZebra1_RxLPFBW 0x600
+
+#define bRTL8256RegModeCtrl1 0x100 +#define bRTL8256RegModeCtrl0 0x40
+#define bRTL8256_TxLPFBW 0x18
+#define bRTL8256_RxLPFBW 0x600
+
+#define bRTL8258_TxLPFBW 0xc +#define bRTL8258_RxLPFBW 0xc00
+#define bRTL8258_RSSILPFBW 0xc0
+
+
+
+#define bByte0 0x1 +#define bByte1 0x2
+#define bByte2 0x4
+#define bByte3 0x8
+#define bWord0 0x3
+#define bWord1 0xc
+#define bDWord 0xf
+
+#define bMaskByte0 0xff +#define bMaskByte1 0xff00
+#define bMaskByte2 0xff0000
+#define bMaskByte3 0xff000000
+#define bMaskHWord 0xffff0000
+#define bMaskLWord 0x0000ffff
+#define bMaskDWord 0xffffffff
+
+#if (RTL92SE_FPGA_VERIFY == 1)
+#define bMask12Bits 0xfff +#define bMask20Bits 0xfff +#define bRFRegOffsetMask 0xfff
+#else
+#define bMask12Bits 0xfffff +#define bMask20Bits 0xfffff +#define bRFRegOffsetMask 0xfffff
+#endif
+#define bEnable 0x1 +#define bDisable 0x0
+
+#define LeftAntenna 0x0 +#define RightAntenna 0x1
+
+#define tCheckTxStatus 500 +#define tUpdateRxCounter 100 +
+#define rateCCK 0 +#define rateOFDM 1
+#define rateHT 2
+
+#define bPMAC_End 0x1ff +#define bFPGAPHY0_End 0x8ff
+#define bFPGAPHY1_End 0x9ff
+#define bCCKPHY0_End 0xaff
+#define bOFDMPHY0_End 0xcff
+#define bOFDMPHY1_End 0xdff
+
+
+#define bPMACControl 0x0 +#define bWMACControl 0x1
+#define bWNICControl 0x2
+
+#define PathA 0x0 +#define PathB 0x1
+#define PathC 0x2
+#define PathD 0x3
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+#endif +
+
diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_rtl6052.c b/ubuntu/rtl8192se/rtl8192s/r8192S_rtl6052.c new file mode 100644 index 000000000000..15ab5eb09214 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_rtl6052.c @@ -0,0 +1,974 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + +#ifdef RTL8192SE +#include "../rtl_core.h" +#include "../rtl_dm.h" +#include "r8192S_phyreg.h" +#include "r8192S_phy.h" +#include "r8192S_rtl6052.h" + +/*---------------------------Define Local Constant---------------------------*/ +typedef struct RF_Shadow_Compare_Map { + u32 Value; + u8 Compare; + u8 ErrorOrNot; + u8 Recorver; + u8 Driver_Write; +}RF_SHADOW_T; +/*---------------------------Define Local Constant---------------------------*/ + + +/*------------------------Define global variable-----------------------------*/ +/*------------------------Define global variable-----------------------------*/ + + + + +/*---------------------Define local function prototype-----------------------*/ +void phy_RF6052_Config_HardCode(struct net_device* dev); + +bool phy_RF6052_Config_ParaFile(struct net_device* dev); +/*---------------------Define local function prototype-----------------------*/ + +/*------------------------Define function prototype--------------------------*/ +extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate); + +/*------------------------Define function prototype--------------------------*/ + +/*------------------------Define local variable------------------------------*/ +static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; +/*------------------------Define local variable------------------------------*/ + +/*------------------------Define function prototype--------------------------*/ +extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate) +{ +#if 0 + static u1Byte RF_Path_Type = 2; + static u4Byte tx_gain_tbl1[6] + = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100}; + static u4Byte tx_gain_tbl2[6] + = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030}; + u1Byte i; + + if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7) + { + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G2, bMask20Bits, 0x0f000); + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G3, bMask20Bits, 0xeacf1); + + for (i = 0; i < 6; i++) + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]); + + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G2, bMask20Bits, 0x01e39); + } + else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8) + { + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G2, bMask20Bits, 0x04440); + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G3, bMask20Bits, 0xea4f1); + + for (i = 0; i < 6; i++) + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]); + + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G2, bMask20Bits, 0x01e19); + } +#endif + +} /* RF_ChangeTxPath */ + + +void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) +{ + u8 eRFPath; + struct r8192_priv *priv = rtllib_priv(dev); + + + if (IS_HARDWARE_TYPE_8192SE(dev)) + { +#if (RTL92SE_FPGA_VERIFY == 0) + switch(Bandwidth) + { + case HT_CHANNEL_WIDTH_20: +#if 1 + priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]); +#else + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01); +#endif + break; + case HT_CHANNEL_WIDTH_20_40: +#if 1 + priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff)); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]); +#else + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00); +#endif + break; + default: + RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth); + break; + } +#endif + } + else + { + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + switch(Bandwidth) + { + case HT_CHANNEL_WIDTH_20: + break; + case HT_CHANNEL_WIDTH_20_40: + break; + default: + RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); + break; + + } + } + } +} + + +extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 TxAGC=0; + bool dontIncCCKOrTurboScanOff=false; + + if (((priv->eeprom_version >= 2) && (priv->TxPwrSafetyFlag == 1)) || + ((priv->eeprom_version >= 2) && (priv->EEPROMRegulatory != 0))) { + dontIncCCKOrTurboScanOff = true; + } + + if(rtllib_act_scanning(priv->rtllib,true) == true){ + TxAGC = 0x3f; + + if(dontIncCCKOrTurboScanOff ) + TxAGC = powerlevel; + } else { + TxAGC = powerlevel; + + if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) + TxAGC = 0x10; + else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) + TxAGC = 0x0; + } + + if(TxAGC > RF6052_MAX_TX_PWR) + TxAGC = RF6052_MAX_TX_PWR; + + rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); + +} /* PHY_RF6052SetCckTxPower */ + + +#if 0 +extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel, u8 Channel) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 writeVal, powerBase0, powerBase1; + u8 index = 0; + u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; + u8 rfa_pwr[4]; + u8 rfa_lower_bound = 0, rfa_upper_bound = 0; + u8 i; + u8 rf_pwr_diff = 0, chnlGroup = 0; + u8 Legacy_pwrdiff=0, HT20_pwrdiff=0; + + if (priv->eeprom_version < 2) + powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); + else if (priv->eeprom_version >= 2) + { + Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; + powerBase0 = powerlevel + Legacy_pwrdiff; + RT_TRACE(COMP_POWER, " [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff); + RT_TRACE(COMP_POWER, " [OFDM power base index = 0x%x]\n", powerBase0); + } + powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; + + if(priv->eeprom_version >= 2) + { + + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + { + HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1]; + + if (HT20_pwrdiff < 8) + powerlevel += HT20_pwrdiff; + else + powerlevel -= (16-HT20_pwrdiff); + + RT_TRACE(COMP_POWER, " [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff); + RT_TRACE(COMP_POWER, " [MCS power base index = 0x%x]\n", powerlevel); + } + } + powerBase1 = powerlevel; + powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; + + RT_TRACE(COMP_POWER, " [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1); + + for(index=0; index<6; index++) + { + + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + writeVal = ((index<2)?powerBase0:powerBase1); + } + else + { + if(priv->pwrGroupCnt == 0) + chnlGroup = 0; + if(priv->pwrGroupCnt >= 3) + { + if(Channel <= 3) + chnlGroup = 0; + else if(Channel >= 4 && Channel <= 9) + chnlGroup = 1; + else if(Channel >= 10) + chnlGroup = 2; + if(priv->pwrGroupCnt == 4) + chnlGroup ++; + } + else + chnlGroup = 0; + writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + + ((index<2)?powerBase0:powerBase1); + } + RT_TRACE(COMP_POWER, "Reg 0x%x, chnlGroup = %d, Original=%x writeVal=%x\n", + RegOffset[index], chnlGroup, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index], + writeVal); + + if (priv->rf_type == RF_2T2R) + { + rf_pwr_diff = priv->AntennaTxPwDiff[0]; + RT_TRACE(COMP_POWER, "2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff); + + if (rf_pwr_diff >= 8) + { + rfa_lower_bound = 0x10-rf_pwr_diff; + RT_TRACE(COMP_POWER, "rfa_lower_bound= %d\n", rfa_lower_bound); + } + else if (rf_pwr_diff >= 0) + { + rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; + RT_TRACE(COMP_POWER, "rfa_upper_bound= %d\n", rfa_upper_bound); + } + } + + for (i= 0; i <4; i++) + { + rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); + if (rfa_pwr[i] > RF6052_MAX_TX_PWR) + rfa_pwr[i] = RF6052_MAX_TX_PWR; + + if (priv->rf_type == RF_2T2R) + { + if (rf_pwr_diff >= 8) + { + if (rfa_pwr[i] <rfa_lower_bound) + { + RT_TRACE(COMP_POWER, "Underflow"); + rfa_pwr[i] = rfa_lower_bound; + } + } + else if (rf_pwr_diff >= 1) + { + if (rfa_pwr[i] > rfa_upper_bound) + { + RT_TRACE(COMP_POWER, "Overflow"); + rfa_pwr[i] = rfa_upper_bound; + } + } + RT_TRACE(COMP_POWER, "rfa_pwr[%d]=%x\n", i, rfa_pwr[i]); + } + + } + +#if 1 + writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; + RT_TRACE(COMP_POWER, "WritePower=%08x\n", writeVal); +#else + if(priv->bDynamicTxHighPower == true) + { + if(index > 1) + { + writeVal = 0x03030303; + } + else + { + writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; + } + RT_TRACE(COMP_POWER, "HighPower=%08x\n", writeVal); + } + else + { + writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; + RT_TRACE(COMP_POWER, "NormalPower=%08x\n", writeVal); + } +#endif + rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); + } + +} /* PHY_RF6052SetOFDMTxPower */ +#endif + +void getPowerBase( + struct net_device* dev, + u8* pPowerLevel, + u8 Channel, + u32* OfdmBase, + u32* MCSBase, + u8* pFinalPowerIndex + ) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u32 powerBase0, powerBase1; + u8 Legacy_pwrdiff=0, HT20_pwrdiff=0; + u8 i, powerlevel[4]; + + for(i=0; i<2; i++) + powerlevel[i] = pPowerLevel[i]; + if (priv->eeprom_version < 2) + powerBase0 = powerlevel[0] + (priv->LegacyHTTxPowerDiff & 0xf); + else if (priv->eeprom_version >= 2) + { + Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; + powerBase0 = powerlevel[0] + Legacy_pwrdiff; + } + powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; + *OfdmBase = powerBase0; + RT_TRACE(COMP_POWER, " [OFDM power base index = 0x%x]\n", powerBase0); + + if(priv->eeprom_version >= 2) + { + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + { + for(i=0; i<2; i++) + { + HT20_pwrdiff = priv->TxPwrHt20Diff[i][Channel-1]; + if (HT20_pwrdiff < 8) + powerlevel[i] += HT20_pwrdiff; + else + powerlevel[i] -= (16-HT20_pwrdiff); + } + } + } + powerBase1 = powerlevel[0]; + powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; + *MCSBase = powerBase1; + + RT_TRACE(COMP_POWER, " [MCS power base index = 0x%x]\n", powerBase1); + + pFinalPowerIndex[0] = powerlevel[0]; + pFinalPowerIndex[1] = powerlevel[1]; + switch(priv->EEPROMRegulatory) + { + case 3: + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + pFinalPowerIndex[0] += priv->PwrGroupHT40[RF90_PATH_A][Channel-1]; + pFinalPowerIndex[1] += priv->PwrGroupHT40[RF90_PATH_B][Channel-1]; + } + else + { + pFinalPowerIndex[0] += priv->PwrGroupHT20[RF90_PATH_A][Channel-1]; + pFinalPowerIndex[1] += priv->PwrGroupHT20[RF90_PATH_B][Channel-1]; + } + break; + default: + break; + } + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + RT_TRACE(COMP_POWER, "40MHz finalPowerIndex (A / B) = 0x%x / 0x%x\n", + pFinalPowerIndex[0], pFinalPowerIndex[1]); + } + else + { + RT_TRACE(COMP_POWER, "20MHz finalPowerIndex (A / B) = 0x%x / 0x%x\n", + pFinalPowerIndex[0], pFinalPowerIndex[1]); + } +} + +void getTxPowerWriteValByRegulatory( + struct net_device* dev, + u8 Channel, + u8 index, + u32 powerBase0, + u32 powerBase1, + u32* pOutWriteVal + ) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u8 i, chnlGroup, pwr_diff_limit[4]; + u32 writeVal, customer_limit; + + switch(priv->EEPROMRegulatory) + { + case 0: + chnlGroup = 0; + RT_TRACE(COMP_POWER,"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", + chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index]); + writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + + ((index<2)?powerBase0:powerBase1); + RT_TRACE(COMP_POWER,"RTK better performance, writeVal = 0x%x\n", writeVal); + break; + case 1: + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + writeVal = ((index<2)?powerBase0:powerBase1); + RT_TRACE(COMP_POWER,"Realtek regulatory, 40MHz, writeVal = 0x%x\n", writeVal); + } + else + { + if(priv->pwrGroupCnt == 1) + chnlGroup = 0; + if(priv->pwrGroupCnt >= 3) + { + if(Channel <= 3) + chnlGroup = 0; + else if(Channel >= 4 && Channel <= 8) + chnlGroup = 1; + else if(Channel > 8) + chnlGroup = 2; + if(priv->pwrGroupCnt == 4) + chnlGroup++; + } + RT_TRACE(COMP_POWER,"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", + chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index]); + writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + + ((index<2)?powerBase0:powerBase1); + RT_TRACE(COMP_POWER,"Realtek regulatory, 20MHz, writeVal = 0x%x\n", writeVal); + } + break; + case 2: + writeVal = ((index<2)?powerBase0:powerBase1); + RT_TRACE(COMP_POWER,"Better regulatory, writeVal = 0x%x\n", writeVal); + break; + case 3: + chnlGroup = 0; + RT_TRACE(COMP_POWER,"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", + chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index]); + + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + RT_TRACE(COMP_POWER,"customer's limit, 40MHz = 0x%x\n", + priv->PwrGroupHT40[RF90_PATH_A][Channel-1]); + } + else + { + RT_TRACE(COMP_POWER,"customer's limit, 20MHz = 0x%x\n", + priv->PwrGroupHT20[RF90_PATH_A][Channel-1]); + } + for (i=0; i<4; i++) + { + pwr_diff_limit[i] = (u8)((priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index]&(0x7f<<(i*8)))>>(i*8)); + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + if(pwr_diff_limit[i] > priv->PwrGroupHT40[RF90_PATH_A][Channel-1]) + { + pwr_diff_limit[i] = priv->PwrGroupHT40[RF90_PATH_A][Channel-1]; + } + } + else + { + if(pwr_diff_limit[i] > priv->PwrGroupHT20[RF90_PATH_A][Channel-1]) + { + pwr_diff_limit[i] = priv->PwrGroupHT20[RF90_PATH_A][Channel-1]; + } + } + } + customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) | + (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]); + RT_TRACE(COMP_POWER,"Customer's limit = 0x%x\n", customer_limit); + + writeVal = customer_limit + ((index<2)?powerBase0:powerBase1); + RT_TRACE(COMP_POWER,"Customer, writeVal = 0x%x\n", writeVal); + break; + default: + chnlGroup = 0; + writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + + ((index<2)?powerBase0:powerBase1); + RT_TRACE(COMP_POWER,"RTK better performance, writeVal = 0x%x\n", writeVal); + break; + } + + if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) + writeVal = 0x10101010; + else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) + writeVal = 0x0; + + *pOutWriteVal = writeVal; + +} + +void setAntennaDiff( + struct net_device* dev, + u8* pFinalPowerIndex + ) +{ + struct r8192_priv *priv = rtllib_priv(dev); + char ant_pwr_diff=0; + u32 u4RegValue=0; + + if (priv->rf_type == RF_2T2R) + { + ant_pwr_diff = pFinalPowerIndex[1] - pFinalPowerIndex[0]; + + if(ant_pwr_diff > 7) + ant_pwr_diff = 7; + if(ant_pwr_diff < -8) + ant_pwr_diff = -8; + RT_TRACE(COMP_POWER,"Antenna Diff from RF-B to RF-A = %d (0x%x)\n", + ant_pwr_diff, ant_pwr_diff&0xf); + ant_pwr_diff &= 0xf; + } + priv->AntennaTxPwDiff[2] = 0; + priv->AntennaTxPwDiff[1] = 0; + priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); + + u4RegValue = (priv->AntennaTxPwDiff[2]<<8 | + priv->AntennaTxPwDiff[1]<<4 | + priv->AntennaTxPwDiff[0] ); + + rtl8192_setBBreg(dev, rFPGA0_TxGainStage, + (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); + + RT_TRACE(COMP_POWER,"Write BCD-Diff(0x%x) = 0x%x\n", + rFPGA0_TxGainStage, u4RegValue); +} + +void writeOFDMPowerReg( + struct net_device* dev, + u8 index, + u32 Value + ) +{ + struct r8192_priv *priv = rtllib_priv(dev); + u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; + u8 i, rfa_pwr[4]; + u8 rfa_lower_bound = 0, rfa_upper_bound = 0, rf_pwr_diff = 0; + u32 writeVal=Value; + if (priv->rf_type == RF_2T2R) + { + rf_pwr_diff = priv->AntennaTxPwDiff[0]; + + if (rf_pwr_diff >= 8) + { + rfa_lower_bound = 0x10-rf_pwr_diff; + RT_TRACE(COMP_POWER,"rfa_lower_bound= %d\n", rfa_lower_bound); + } + else if (rf_pwr_diff >= 0) + { + rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; + RT_TRACE(COMP_POWER,"rfa_upper_bound= %d\n", rfa_upper_bound); + } + } + + for (i=0; i<4; i++) + { + rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); + if (rfa_pwr[i] > RF6052_MAX_TX_PWR) + rfa_pwr[i] = RF6052_MAX_TX_PWR; + + if (priv->rf_type == RF_2T2R) + { + if (rf_pwr_diff >= 8) + { + if (rfa_pwr[i] <rfa_lower_bound) + { + RT_TRACE(COMP_POWER,"Underflow"); + rfa_pwr[i] = rfa_lower_bound; + } + } + else if (rf_pwr_diff >= 1) + { + if (rfa_pwr[i] > rfa_upper_bound) + { + RT_TRACE(COMP_POWER,"Overflow"); + rfa_pwr[i] = rfa_upper_bound; + } + } + RT_TRACE(COMP_POWER,"rfa_pwr[%d]=%x\n", i, rfa_pwr[i]); + } + + } + + writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; + + rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); + RT_TRACE(COMP_POWER,"Set 0x%x = %08x\n",RegOffset[index], writeVal); +} + +/*----------------------------------------------------------------------------- + * Function: PHY_RF6052SetOFDMTxPower + * + * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for + * different channel and read original value in TX power register area from + * 0xe00. We increase offset and original value to be correct tx pwr. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/05/2008 MHC Simulate 8192 series method. + * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to + * A/B pwr difference or legacy/HT pwr diff. + * 2. We concern with path B legacy/HT OFDM difference. + * 01/22/2009 MHC Support new EPRO format from SD3. + * + *---------------------------------------------------------------------------*/ +extern void +PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8* pPowerLevel, u8 Channel) +{ + u32 writeVal, powerBase0, powerBase1; + u8 index = 0; + u8 finalPowerIndex[4]; + + getPowerBase(dev, pPowerLevel, Channel, &powerBase0, &powerBase1, &finalPowerIndex[0]); + setAntennaDiff(dev, &finalPowerIndex[0] ); + + for(index=0; index<6; index++) + { + getTxPowerWriteValByRegulatory(dev, Channel, index, + powerBase0, powerBase1, &writeVal); + + writeOFDMPowerReg(dev, index, writeVal); + } +} + +bool PHY_RF6052_Config(struct net_device* dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + bool rtStatus = true; + u8 bRegHwParaFile = 1; + + if(priv->rf_type == RF_1T1R) + priv->NumTotalRFPath = 1; + else + priv->NumTotalRFPath = 2; + + switch(bRegHwParaFile) + { + case 0: + phy_RF6052_Config_HardCode(dev); + break; + + case 1: + rtStatus = phy_RF6052_Config_ParaFile(dev); + break; + + case 2: + phy_RF6052_Config_HardCode(dev); + phy_RF6052_Config_ParaFile(dev); + break; + + default: + phy_RF6052_Config_HardCode(dev); + break; + } + return rtStatus; + +} + +void phy_RF6052_Config_HardCode(struct net_device* dev) +{ + + + +} + +bool phy_RF6052_Config_ParaFile(struct net_device* dev) +{ + u32 u4RegValue = 0; + u8 eRFPath; + bool rtStatus = true; + struct r8192_priv *priv = rtllib_priv(dev); + BB_REGISTER_DEFINITION_T *pPhyReg; + + + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + + pPhyReg = &priv->PHYRegDef[eRFPath]; + + switch(eRFPath) + { + case RF90_PATH_A: + case RF90_PATH_C: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); + break; + case RF90_PATH_B : + case RF90_PATH_D: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); + break; + } + + rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); + + rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); + + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); + + + switch(eRFPath) + { + case RF90_PATH_A: +#if RTL8190_Download_Firmware_From_Header + rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); +#else + rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath); +#endif + break; + case RF90_PATH_B: +#if RTL8190_Download_Firmware_From_Header + rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); +#else + if(priv->rf_type == RF_2T2R_GREEN) + rtStatus = PHY_ConfigRFWithParaFile(dev, (char *)&szRadioBGMFile, (RF90_RADIO_PATH_E)eRFPath); + else + rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath); +#endif + break; + case RF90_PATH_C: + break; + case RF90_PATH_D: + break; + } + + switch(eRFPath) + { + case RF90_PATH_A: + case RF90_PATH_C: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); + break; + case RF90_PATH_B : + case RF90_PATH_D: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); + break; + } + + if(rtStatus != true){ + printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath); + goto phy_RF6052_Config_ParaFile_Fail; + } + + } + + RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n"); + return rtStatus; + +phy_RF6052_Config_ParaFile_Fail: + return rtStatus; +} + + +extern u32 PHY_RFShadowRead( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset) +{ + return RF_Shadow[eRFPath][Offset].Value; + +} /* PHY_RFShadowRead */ + + +extern void PHY_RFShadowWrite( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u32 Data) +{ + RF_Shadow[eRFPath][Offset].Value = (Data & bMask20Bits); + RF_Shadow[eRFPath][Offset].Driver_Write = true; + +} /* PHY_RFShadowWrite */ + + +extern bool PHY_RFShadowCompare( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset) +{ + u32 reg; + + if (RF_Shadow[eRFPath][Offset].Compare == true) + { + reg = rtl8192_phy_QueryRFReg(dev, eRFPath, Offset, bMask20Bits); + if (RF_Shadow[eRFPath][Offset].Value != reg) + { + RF_Shadow[eRFPath][Offset].ErrorOrNot = true; + RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02xErr = %05x", eRFPath, Offset, reg); + } + else + { + RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02x Err = %05x return false\n", eRFPath, Offset, reg); + RF_Shadow[eRFPath][Offset].ErrorOrNot = false; + } + return RF_Shadow[eRFPath][Offset].ErrorOrNot; + } + return false; +} /* PHY_RFShadowCompare */ + +extern void PHY_RFShadowRecorver( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset) +{ + if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true) + { + if (RF_Shadow[eRFPath][Offset].Recorver == true) + { + rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bMask20Bits, RF_Shadow[eRFPath][Offset].Value); + RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x", + eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value); + } + } + +} /* PHY_RFShadowRecorver */ + + +extern void PHY_RFShadowCompareAll(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)eRFPath, Offset); + } + } + +} /* PHY_RFShadowCompareAll */ + + +extern void PHY_RFShadowRecorverAll(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + PHY_RFShadowRecorver(dev, (RF90_RADIO_PATH_E)eRFPath, Offset); + } + } + +} /* PHY_RFShadowRecorverAll */ + + +extern void PHY_RFShadowCompareFlagSet( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u8 Type) +{ + RF_Shadow[eRFPath][Offset].Compare = Type; + +} /* PHY_RFShadowCompareFlagSet */ + + +extern void PHY_RFShadowRecorverFlagSet( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u8 Type) +{ + RF_Shadow[eRFPath][Offset].Recorver= Type; + +} /* PHY_RFShadowRecorverFlagSet */ + + +extern void PHY_RFShadowCompareFlagSetAll(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + if (Offset != 0x26 && Offset != 0x27) + PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, false); + else + PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, true); + } + } + +} /* PHY_RFShadowCompareFlagSetAll */ + + +extern void PHY_RFShadowRecorverFlagSetAll(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + if (Offset != 0x26 && Offset != 0x27) + PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, false); + else + PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, true); + } + } + +} /* PHY_RFShadowCompareFlagSetAll */ + + + +extern void PHY_RFShadowRefresh(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + RF_Shadow[eRFPath][Offset].Value = 0; + RF_Shadow[eRFPath][Offset].Compare = false; + RF_Shadow[eRFPath][Offset].Recorver = false; + RF_Shadow[eRFPath][Offset].ErrorOrNot = false; + RF_Shadow[eRFPath][Offset].Driver_Write = false; + } + } + +} /* PHY_RFShadowRead */ + +/* End of HalRf6052.c */ + +#endif diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_rtl6052.h b/ubuntu/rtl8192se/rtl8192s/r8192S_rtl6052.h new file mode 100644 index 000000000000..78614bae5cfe --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_rtl6052.h @@ -0,0 +1,116 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ + + +/*--------------------------Define Parameters-------------------------------*/ + +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG 0x3F +#define RF6052_MAX_PATH 4 +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +#if 1 +extern void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); +extern void PHY_SetRF8225Bandwidth( struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); +extern bool PHY_RF8225_Config(struct net_device* dev ); +extern void phy_RF8225_Config_HardCode(struct net_device* dev); +extern bool phy_RF8225_Config_ParaFile(struct net_device* dev); +extern void PHY_SetRF8225CckTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF8225OfdmTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF0222DOfdmTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF0222DCckTxPower(struct net_device* dev ,u8 powerlevel); + +extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); +extern void PHY_RF8256_Config(struct net_device* dev); +extern void phy_RF8256_Config_ParaFile(struct net_device* dev); +extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel); +extern void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel); +#endif + +extern void RF_ChangeTxPath(struct net_device * dev, u16 DataRate); +extern void PHY_RF6052SetBandwidth(struct net_device * dev,HT_CHANNEL_WIDTH Bandwidth); +extern void PHY_RF6052SetCckTxPower(struct net_device * dev, u8 powerlevel); +extern void PHY_RF6052SetOFDMTxPower(struct net_device * dev, u8* pPowerLevel, u8 Channel); +extern bool PHY_RF6052_Config(struct net_device * dev); +extern void PHY_RFShadowRefresh( struct net_device * dev); +extern void PHY_RFShadowWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); + +extern bool +PHY_RFShadowCompare( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset); +extern void +PHY_RFShadowRecorver( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset); +extern void +PHY_RFShadowCompareFlagSet( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u8 Type); +extern void +PHY_RFShadowRecorverFlagSet( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u8 Type); +#if 0 +extern u32 +PHY_RFShadowRead( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset); +extern void +PHY_RFShadowCompareAll( + struct net_device * dev); +extern void +PHY_RFShadowRecorverAll( + struct net_device * dev); +extern void +PHY_RFShadowCompareFlagSetAll( + struct net_device * dev); +extern void +PHY_RFShadowRecorverFlagSetAll( + struct net_device * dev); +extern void +PHY_RFShadowRefresh( + struct net_device * dev); +#endif +/*--------------------------Exported Function prototype---------------------*/ + + +/* End of HalRf.h */ diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_scan.c b/ubuntu/rtl8192se/rtl8192s/r8192S_scan.c new file mode 100644 index 000000000000..5b0f44b54486 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_scan.c @@ -0,0 +1,414 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#include "../rtl_core.h" + +#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ) + +void rtl8192se_hw_scan_simu(void *data) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + struct r8192_priv *priv = container_of_dwork_rsl(data,struct r8192_priv,hw_scan_simu_wq); + struct net_device *dev = priv->rtllib->dev; +#else + struct net_device *dev = (struct net_device *)data; + struct r8192_priv *priv = rtllib_priv(dev); +#endif + + rtllib_update_active_chan_map(priv->rtllib); + + priv->rtllib->current_network.channel = (priv->rtllib->current_network.channel + 1) % 12; + if (priv->rtllib->scan_watch_dog++ > 12) + { + goto out; /* no good chans */ + } + + if ((!test_bit(STATUS_SCANNING, &priv->rtllib->status)) || + (test_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status))){ + goto out; + } + + if(priv->rtllib->current_network.channel != 0){ + priv->rtllib->set_chan(dev,priv->rtllib->current_network.channel); +#ifdef _RTL8192_EXT_PATCH_ + rtllib_send_probe_requests(priv->rtllib, 1); +#else + rtllib_send_probe_requests(priv->rtllib); +#endif + } + + queue_delayed_work_rsl(priv->priv_wq, &priv->hw_scan_simu_wq, MSECS(RTLLIB_SOFTMAC_SCAN_TIME)); + + return; +out: + priv->rtllib->scan_watch_dog =0; + rtl8192se_rx_surveydone_cmd(dev); + + if(priv->rtllib->state == RTLLIB_LINKED_SCANNING){ + priv->rtllib->current_network.channel = priv->rtllib->hwscan_ch_bk; + printk("%s():back to linked chan:%d\n", __func__,priv->rtllib->current_network.channel); + priv->rtllib->set_chan(dev,priv->rtllib->current_network.channel); + } +} + +void rtl8192se_before_hw_scan(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + HT_EXTCHNL_OFFSET chan_offset=0; + HT_CHANNEL_WIDTH bandwidth=0; + struct rtllib_device *ieee = priv->rtllib; + + if(priv->rtllib->state != RTLLIB_LINKED) + return; + + +#ifdef ENABLE_LPS + if (ieee->LeisurePSLeave) { + ieee->LeisurePSLeave(ieee->dev); + } + /* notify AP to be in PS mode */ + rtllib_sta_ps_send_null_frame(ieee, 1); + rtllib_sta_ps_send_null_frame(ieee, 1); +#endif + + netif_carrier_off(ieee->dev); + if (ieee->data_hard_stop) + ieee->data_hard_stop(ieee->dev); + rtllib_stop_send_beacons(ieee); + ieee->state = RTLLIB_LINKED_SCANNING; + ieee->link_change(ieee->dev); + /* wait for ps packet to be kicked out successfully */ + //msleep(50); + mdelay(50); + +#if(RTL8192S_DISABLE_FW_DM == 0) + if (ieee->SetFwCmdHandler) { + ieee->SetFwCmdHandler(ieee->dev, FW_CMD_PAUSE_DM_BY_SCAN); + } +#endif + + if (ieee->pHTInfo->bCurrentHTSupport && ieee->pHTInfo->bEnableHT && ieee->pHTInfo->bCurBW40MHz) { + priv->hwscan_bw_40 = 1; + priv->rtllib->chan_offset_bk = chan_offset = ieee->pHTInfo->CurSTAExtChnlOffset; + priv->rtllib->bandwidth_bk = bandwidth = (HT_CHANNEL_WIDTH)ieee->pHTInfo->bCurBW40MHz; + printk("-------------->%s():before scan force BW to 20M:%d, %d\n", __func__,chan_offset, bandwidth); + ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + } +} +void rtl8192se_after_hw_scan(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + HT_EXTCHNL_OFFSET chan_offset = priv->rtllib->chan_offset_bk; + HT_CHANNEL_WIDTH bandwidth = priv->rtllib->bandwidth_bk; + struct rtllib_device *ieee = priv->rtllib; + + if(priv->rtllib->state != RTLLIB_LINKED_SCANNING){ + goto out; + } + + if (ieee->LinkDetectInfo.NumRecvBcnInPeriod == 0 || + ieee->LinkDetectInfo.NumRecvDataInPeriod == 0 ) { + ieee->LinkDetectInfo.NumRecvBcnInPeriod = 1; + ieee->LinkDetectInfo.NumRecvDataInPeriod= 1; + } + + if (priv->hwscan_bw_40) { + priv->hwscan_bw_40 = 0; + printk("-------------->%s():after scan back BW to 40M:%d, %d\n", __func__, chan_offset, bandwidth); +#if 1 + if (chan_offset == HT_EXTCHNL_OFFSET_UPPER){ + ieee->set_chan(ieee->dev, priv->rtllib->hwscan_ch_bk + 2); + }else if (chan_offset == HT_EXTCHNL_OFFSET_LOWER){ + ieee->set_chan(ieee->dev, priv->rtllib->hwscan_ch_bk - 2); + }else{ + priv->rtllib->current_network.channel = priv->rtllib->hwscan_ch_bk; + ieee->set_chan(ieee->dev, priv->rtllib->hwscan_ch_bk); + } +#endif + ieee->SetBWModeHandler(ieee->dev, bandwidth, chan_offset); + } else { + ieee->set_chan(ieee->dev, priv->rtllib->hwscan_ch_bk); + } + +#if(RTL8192S_DISABLE_FW_DM == 0) + if (ieee->SetFwCmdHandler) { + ieee->SetFwCmdHandler(ieee->dev, FW_CMD_RESUME_DM_BY_SCAN); + } +#endif + ieee->state = RTLLIB_LINKED; + ieee->link_change(ieee->dev); + +#ifdef ENABLE_LPS + /* Notify AP that I wake up again */ + rtllib_sta_ps_send_null_frame(ieee, 0); +#endif + + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + + if(ieee->iw_mode == IW_MODE_ADHOC || ieee->iw_mode == IW_MODE_MASTER) + rtllib_start_send_beacons(ieee); + + netif_carrier_on(ieee->dev); + +out: + return; +} +/* Service HAL_FW_C2H_CMD_SurveyDone (0x9) */ +void rtl8192se_rx_surveydone_cmd(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + + + + cancel_delayed_work(&priv->check_hw_scan_wq); + + /* If a request to abort was given, or the scan did not succeed + * then we reset the scan state machine and terminate, + * re-queuing another scan if one has been requested */ + if (test_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status)) { + RT_TRACE(COMP_ERR, "Aborted scan completed.\n"); + clear_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status); + } + + rtl8192se_after_hw_scan(dev); + +#ifdef CONFIG_FW_PARSEBEACON + if(priv->rtllib->state < RTLLIB_LINKED) + write_nic_dword(dev, RXFILTERMAP, 0x0100); +#endif + + mdelay(1); + + clear_bit(STATUS_SCANNING, &priv->rtllib->status); + + { + union iwreq_data wrqu; + memset(&wrqu, 0, sizeof(wrqu)); + wireless_send_event(priv->rtllib->dev,SIOCGIWSCAN,&wrqu,NULL); + } + + if(priv->rtllib->hwscan_sem_up == 0){ + up(&priv->wx_sem); + priv->rtllib->hwscan_sem_up = 1; + } + + + return; +} + + +void rtl8192se_check_hw_scan(void *data) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + struct r8192_priv *priv = container_of_dwork_rsl(data,struct r8192_priv,check_hw_scan_wq); + struct net_device *dev = priv->rtllib->dev; +#else + struct net_device *dev = (struct net_device *)data; + struct r8192_priv *priv = rtllib_priv(dev); +#endif + unsigned long flags; + + + spin_lock_irqsave(&priv->fw_scan_lock,flags); + printk("----------->%s()\n", __func__); + + if (test_bit(STATUS_SCANNING, &priv->rtllib->status) || + test_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status)) { + printk("FW Scan long time without stop, stop hw scan\n"); + rtl8192se_send_scan_abort(dev); + } + + + if(priv->rtllib->hwscan_sem_up == 0){ + up(&priv->wx_sem); + priv->rtllib->hwscan_sem_up = 1; + } + + printk("<-----------%s()\n", __func__); + spin_unlock_irqrestore(&priv->fw_scan_lock,flags); +} + +void rtl8192se_start_hw_scan(void *data) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + struct r8192_priv *priv = container_of_dwork_rsl(data,struct r8192_priv,start_hw_scan_wq); + struct net_device *dev = priv->rtllib->dev; +#else + struct net_device *dev = (struct net_device *)data; + struct r8192_priv *priv = rtllib_priv(dev); +#endif + bool start_flag =true; + unsigned long flags; + + down(&priv->wx_sem); + priv->rtllib->hwscan_sem_up = 0; + + spin_lock_irqsave(&priv->fw_scan_lock,flags); + + + cancel_delayed_work(&priv->check_hw_scan_wq); + + /* Make sure the scan wasn't canceled before this queued work + * was given the chance to run... */ + if (!test_bit(STATUS_SCANNING, &priv->rtllib->status)){ + RT_TRACE(COMP_ERR,"not in scanning. Ignoring second request.\n"); + goto done; + } + + if (test_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status)) { + RT_TRACE(COMP_ERR, "Scan request while abort pending. Queuing.\n"); + goto done; + } + + +#ifdef CONFIG_FW_PARSEBEACON + if(priv->rtllib->state < RTLLIB_LINKED) + write_nic_dword(dev, RXFILTERMAP, 0x0000); +#endif + + rtl8192se_before_hw_scan(dev); + rtl8192se_send_scan_cmd(dev,start_flag); + + queue_delayed_work_rsl(priv->priv_wq,&priv->check_hw_scan_wq,MSECS(7000)); + + + spin_unlock_irqrestore(&priv->fw_scan_lock,flags); + + return; + + done: + up(&priv->wx_sem); + priv->rtllib->hwscan_sem_up = 1; + /* Cannot perform scan. Make sure we clear scanning + * bits from status so next scan request can be performed. + * If we don't clear scanning status bit here all next scan + * will fail + */ + clear_bit(STATUS_SCANNING, &priv->rtllib->status); + + /* inform mac80211 scan aborted */ + + //printk("<-------------%s() failed\n", __func__); + spin_unlock_irqrestore(&priv->fw_scan_lock,flags); + + return; +} + +void rtl8192se_hw_scan_initiate(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&priv->fw_scan_lock,flags); + + + if (test_bit(STATUS_SCANNING, &priv->rtllib->status)) { + printk("Scan already in progress.\n"); + goto done; + } + + if (test_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status)) { + printk("Scan request while abort pending\n"); + goto done; + } + + + set_bit(STATUS_SCANNING, &priv->rtllib->status); + + queue_delayed_work_rsl(priv->priv_wq,&priv->start_hw_scan_wq,0); + +done: + spin_unlock_irqrestore(&priv->fw_scan_lock,flags); + + return; +} + +void rtl8192se_send_scan_abort(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + int ret = true; + bool start_flag =false; + + + /* If there isn't a scan actively going on in the hardware + * then we are in between scan bands and not actually + * actively scanning, so don't send the abort command */ + if (!test_bit(STATUS_SCANNING, &priv->rtllib->status)) { + goto done; + } + + ret = rtl8192se_send_scan_cmd(dev, start_flag); + mdelay(1); + +#ifdef CONFIG_FW_PARSEBEACON + if(priv->rtllib->state < RTLLIB_LINKED) + write_nic_dword(dev, RXFILTERMAP, 0x0100); +#endif + + if (ret) { + goto done; + } + + +done: + clear_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status); + clear_bit(STATUS_SCANNING, &priv->rtllib->status); + + return; +} + +/** + * rtl8192se_cancel_hw_scan - Cancel any currently executing HW scan + * + * NOTE: priv->mutex is not required before calling this function + */ +void rtl8192se_cancel_hw_scan(struct net_device *dev) +{ + struct r8192_priv *priv = rtllib_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&priv->fw_scan_lock,flags); + + if (test_bit(STATUS_SCANNING, &priv->rtllib->status)) { + if (!test_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status)) { + printk("-------------->%s()scan abort start...\n", __func__); + cancel_delayed_work(&priv->check_hw_scan_wq); + + set_bit(STATUS_SCAN_ABORTING, &priv->rtllib->status); + rtl8192se_send_scan_abort(dev); + } else { + printk("-------------->%s()Scan abort already in progress.\n", __func__); + } + } + + if(priv->rtllib->hwscan_sem_up == 0){ + up(&priv->wx_sem); + priv->rtllib->hwscan_sem_up = 1; + } + + spin_unlock_irqrestore(&priv->fw_scan_lock,flags); + return; +} + diff --git a/ubuntu/rtl8192se/rtl8192s/r8192S_scan.h b/ubuntu/rtl8192se/rtl8192s/r8192S_scan.h new file mode 100644 index 000000000000..35ddc1ca9fe6 --- /dev/null +++ b/ubuntu/rtl8192se/rtl8192s/r8192S_scan.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * + * Based on the r8180 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> +******************************************************************************/ +#ifndef _RTL8192SE_SCAN +#define _RTL8192SE_SCAN + +void rtl8192se_hw_scan_simu(void *data); +void rtl8192se_rx_surveydone_cmd(struct net_device *dev); +void rtl8192se_check_hw_scan(void *data); +void rtl8192se_start_hw_scan(void *data); +void rtl8192se_abort_hw_scan(struct net_device *dev); +void rtl8192se_hw_scan_initiate(struct net_device *dev); +void rtl8192se_send_scan_abort(struct net_device *dev); +void rtl8192se_cancel_hw_scan(struct net_device *dev); + +#endif + |