348 files changed, 126090 insertions, 2162 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f6179f41566d..5dec03f1e5ae 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1371,6 +1371,25 @@ config UACCESS_WITH_MEMCPY
 	  However, if the CPU data cache is using a write-allocate mode,
 	  this option is unlikely to provide any performance gain.
 
+config UNOFFICIAL_USER_DMA_API
+	bool "Enable unofficial user DMA API (READ HELP TEXT)"
+	depends on EXPERIMENTAL
+	help
+	  This option enables the exposure of the kernel's three DMA cache
+	  coherence functions to userspace via three ARM private syscalls.
+
+	  This API is not officially supported; it is a stop gap measure
+	  to allow developers to achieve their goals.  It doesn't take
+	  account of any DMA restrictions which may be in the system, and
+	  makes no attempt to work around those.
+
+	  The user is entirely responsible for coordinating the use of this
+	  API with DMA activity and CPU snooping activity.  Improper use
+	  of this API can result in random data corruption, especially if
+	  the memory contains DMA scatterlists.
+
+	  Use of this API will taint the kernel.
+
 endmenu
 
 menu "Boot options"
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 1b6cd52f5451..c0c76eaf3ed3 100644..100755
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.34
-# Wed Jul  7 13:16:21 2010
+# Sat Jul 10 05:15:05 2010
 #
 CONFIG_ARM=y
 CONFIG_HAVE_PWM=y
@@ -249,7 +249,10 @@ CONFIG_ARCH_OMAP4=y
 # CONFIG_OMAP_RESET_CLOCKS is not set
 # CONFIG_OMAP_MUX is not set
 CONFIG_OMAP_MCBSP=y
-# CONFIG_OMAP_MBOX_FWK is not set
+CONFIG_OMAP_MBOX_FWK=y
+CONFIG_OMAP_REMOTE_PROC=y
+CONFIG_OMAP_RPROC_MEMPOOL_SIZE=0x600000
+CONFIG_OMAP_IOMMU=y
 # CONFIG_OMAP_MPU_TIMER is not set
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_32K_TIMER_HZ=128
@@ -260,6 +263,8 @@ CONFIG_OMAP_PM_NOOP=y
 #
 # OMAP Board Type
 #
+# CONFIG_WIFI_CONTROL_FUNC is not set
+# CONFIG_TIWLAN_SDIO is not set
 # CONFIG_OMAP4_ES1 is not set
 CONFIG_MACH_OMAP_4430SDP=y
 # CONFIG_ERRATA_OMAP4_AXI2OCP is not set
@@ -352,6 +357,7 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 # CONFIG_UACCESS_WITH_MEMCPY is not set
+CONFIG_UNOFFICIAL_USER_DMA_API=y
 
 #
 # Boot options
@@ -465,7 +471,24 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+# CONFIG_BT_BNEP is not set
+# CONFIG_BT_HIDP is not set
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=y
+# CONFIG_BT_HCIUART_H4 is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
 # CONFIG_AF_RXRPC is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
@@ -484,7 +507,9 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
@@ -528,6 +553,13 @@ CONFIG_BMP085=y
 # CONFIG_EEPROM_MAX6875 is not set
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+CONFIG_TI_ST=m
+CONFIG_TI_ST_BT=m
+CONFIG_TI_ST_FM=m
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -657,7 +689,7 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_CM109 is not set
 # CONFIG_INPUT_TWL4030_PWRBUTTON is not set
 # CONFIG_INPUT_TWL4030_VIBRA is not set
-# CONFIG_INPUT_UINPUT is not set
+CONFIG_INPUT_UINPUT=y
 # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
 CONFIG_INPUT_SFH7741=y
 CONFIG_INPUT_CMA3000_I2C=y
@@ -943,27 +975,204 @@ CONFIG_REGULATOR_TWL4030=y
 # CONFIG_REGULATOR_LP3971 is not set
 # CONFIG_REGULATOR_TPS65023 is not set
 # CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_MEDIA_SUPPORT is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_IR_CORE=y
+CONFIG_VIDEO_IR=y
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_SG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=y
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_VIDEO_OMAP2_VOUT=y
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_DAB is not set
+CONFIG_DMM_OMAP=y
+CONFIG_TILER_OMAP=y
 
 #
 # Graphics support
 #
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_OMAP2_VRAM=y
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_VRAM_SIZE=4
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set
+CONFIG_OMAP2_DSS_DPI=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+# CONFIG_OMAP2_DSS_VENC is not set
+CONFIG_OMAP2_DSS_HDMI=y
+CONFIG_OMAP2_DSS_DSI=y
+# CONFIG_OMAP2_DSS_USE_DSI_PLL is not set
+CONFIG_OMAP2_DSS_FAKE_VSYNC=y
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
+CONFIG_FB_OMAP2=y
+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
+CONFIG_FB_OMAP2_NUM_FBS=2
+
+#
+# OMAP2/3 Display Device Drivers
+#
+# CONFIG_PANEL_GENERIC is not set
+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set
+CONFIG_PANEL_PICO_DLP=y
+CONFIG_PANEL_TAAL=y
+# CONFIG_PANEL_TOPPOLY_TDO35S is not set
+# CONFIG_PANEL_TPO_TD043MTEA1 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+# CONFIG_BACKLIGHT_PWM is not set
 
 #
 # Display device support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_OMAP_MCPDM=y
+CONFIG_SND_OMAP_SOC_ABE=y
+CONFIG_SND_OMAP_SOC_SDP4430=y
+CONFIG_SND_OMAP_SOC_HDMI=y
+# CONFIG_SND_OMAP_VOICE_TEST is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_ABE_TWL6040=y
+# CONFIG_SOUND_PRIME is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
@@ -1198,6 +1407,16 @@ CONFIG_SENSORS_HMC5843=y
 # CONFIG_RAMZSWAP is not set
 # CONFIG_BATMAN_ADV is not set
 # CONFIG_STRIP is not set
+# CONFIG_FB_SM7XX is not set
+CONFIG_Sys_Link=y
+CONFIG_SYSLINK_PROC=y
+CONFIG_SYSLINK_PROC4430=y
+CONFIG_DUCATI_BASEIMAGE_PHYS_ADDR=0x9CF00000
+CONFIG_SYSLINK_DUCATI_PM=y
+CONFIG_MPU_SYSLINK_PLATFORM=y
+CONFIG_MPU_SYSLINK_IPC=y
+CONFIG_SYSLINK_USE_SYSMGR=y
+CONFIG_OMAP_IOMMU_DEBUG_MODULE=y
 
 #
 # File systems
@@ -1557,7 +1776,7 @@ CONFIG_CRYPTO_HW=y
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=y
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
diff --git a/arch/arm/configs/omap_4430simulator_defconfig b/arch/arm/configs/omap_4430simulator_defconfig
new file mode 100644
index 000000000000..6274bb1c53e0
--- /dev/null
+++ b/arch/arm/configs/omap_4430simulator_defconfig
@@ -0,0 +1,1017 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc9
+# Thu Oct  1 15:58:54 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+# CONFIG_ARCH_OMAP3 is not set
+CONFIG_ARCH_OMAP4=y
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MCBSP=y
+CONFIG_OMAP_MBOX_FWK=y
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+
+#
+# OMAP Board Type
+#
+CONFIG_MACH_OMAP_4430SDP=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_ERRATA_484863=y
+
+CONFIG_ARM_GIC=y
+# CONFIG_OMAP_L2_EVENT_DEBUG is not set
+CONFIG_OMAP4_SUDO_ROMCODE=y
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=2
+# CONFIG_LOCAL_TIMERS is not set
+# CONFIG_HOTPLUG_CPU is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480 loglevel=1"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_OMAP=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_SPI=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+CONFIG_I2C_OMAP=y
+CONFIG_SPI_OMAP24XX=y
+CONFIG_SPI_MASTER=y
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MEDIA_SUPPORT is not set
+CONFIG_TWL6030_CORE=y
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=m
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_OMAP=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 44xx high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
+# CONFIG_USB_MUSB_OTG is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_USB_MUSB_DEBUG=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_TWL=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_TWL=y
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index d3730f0f4b50..9792a717174a 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -198,6 +198,21 @@
  *	DMA Cache Coherency
  *	===================
  *
+ *	dma_inv_range(start, end)
+ *
+ *		Invalidate (discard) the specified virtual address range.
+ *		May not write back any entries.  If 'start' or 'end'
+ *		are not cache line aligned, those lines must be written
+ *		back.
+ *		- start  - virtual start address
+ *		- end    - virtual end address
+ *
+ *	dma_clean_range(start, end)
+ *
+ *		Clean (write back) the specified virtual address range.
+ *		- start  - virtual start address
+ *		- end    - virtual end address
+ *
  *	dma_flush_range(start, end)
  *
  *		Clean and invalidate the specified virtual address range.
@@ -217,6 +232,8 @@ struct cpu_cache_fns {
 	void (*dma_map_area)(const void *, size_t, int);
 	void (*dma_unmap_area)(const void *, size_t, int);
 
+	void (*dma_inv_range)(const void *, const void *);
+	void (*dma_clean_range)(const void *, const void *);
 	void (*dma_flush_range)(const void *, const void *);
 };
 
@@ -242,6 +259,8 @@ extern struct cpu_cache_fns cpu_cache;
  */
 #define dmac_map_area			cpu_cache.dma_map_area
 #define dmac_unmap_area		cpu_cache.dma_unmap_area
+#define dmac_inv_range			cpu_cache.dma_inv_range
+#define dmac_clean_range		cpu_cache.dma_clean_range
 #define dmac_flush_range		cpu_cache.dma_flush_range
 
 #else
@@ -268,10 +287,14 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
  */
 #define dmac_map_area			__glue(_CACHE,_dma_map_area)
 #define dmac_unmap_area		__glue(_CACHE,_dma_unmap_area)
+#define dmac_inv_range			__glue(_CACHE,_dma_inv_range)
+#define dmac_clean_range		__glue(_CACHE,_dma_clean_range)
 #define dmac_flush_range		__glue(_CACHE,_dma_flush_range)
 
 extern void dmac_map_area(const void *, size_t, int);
 extern void dmac_unmap_area(const void *, size_t, int);
+extern void dmac_inv_range(const void *, const void *);
+extern void dmac_clean_range(const void *, const void *);
 extern void dmac_flush_range(const void *, const void *);
 
 #endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index c980156f3263..ea6123b8fcc3 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -79,6 +79,9 @@ extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
 
 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
+extern void __iomem * __arm_multi_strided_ioremap(int, unsigned long *,
+        size_t *,unsigned long *, unsigned long *, unsigned int);
+
 extern void __iounmap(volatile void __iomem *addr);
 
 /*
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index dd2bf53000fe..f4e4726985fc 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -407,7 +407,17 @@
  * *NOTE*: This is a ghost syscall private to the kernel.  Only the
  * __kuser_cmpxchg code in entry-armv.S should be aware of its
  * existence.  Don't ever use this from user code.
+=======
+ * These are temporary interfaces; they are a stop gap until we get
+ * a proper solution to DMA.  These won't always work for every
+ * device.  Only use these IF you *really* know what you're doing.
+ * Don't be surprised if they go away in later kernels.
+>>>>>>> ARM: UNOFFICIAL_USER_DMA_API:arch/arm/include/asm/unistd.h
  */
+#define __ARM_NR_temp_dma_inv_range	(__ARM_NR_BASE+0x0007fd)
+#define __ARM_NR_temp_dma_clean_range	(__ARM_NR_BASE+0x0007fe)
+#define __ARM_NR_temp_dma_flush_range	(__ARM_NR_BASE+0x0007ff)
+
 #ifdef __KERNEL__
 #define __ARM_NR_cmpxchg		(__ARM_NR_BASE+0x00fff0)
 #endif
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 056b2a9f1be8..0330a4058e1d 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -437,7 +437,7 @@ static int bad_syscall(int n, struct pt_regs *regs)
 	return regs->ARM_r0;
 }
 
-static inline void
+static void
 do_cache_op(unsigned long start, unsigned long end, int flags)
 {
 	struct mm_struct *mm = current->active_mm;
@@ -532,6 +532,22 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 #endif
 		return 0;
 
+#ifdef CONFIG_UNOFFICIAL_USER_DMA_API
+	/*
+	 * These are temporary interfaces; they are a stop gap until we get
+	 * a proper solution to DMA.  These won't always work for every
+	 * device.  Only use these IF you *really* know what you're doing.
+	 * Don't be surprised if they go away in later kernels.
+	 */
+	case NR(temp_dma_inv_range):
+	case NR(temp_dma_clean_range):
+	case NR(temp_dma_flush_range):
+	{
+		extern int temp_user_dma_op(unsigned long, unsigned long, int);
+		return temp_user_dma_op(regs->ARM_r0, regs->ARM_r1, no & 3);
+	}
+#endif
+
 #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
 	/*
 	 * Atomically store r1 in *r2 if *r2 is equal to r0 for user space.
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2ae09b48df84..c54cae27444b 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -79,6 +79,32 @@ config MACH_OMAP3EVM
 	depends on ARCH_OMAP3
 	select OMAP_PACKAGE_CBB
 
+config WIFI_CONTROL_FUNC
+        bool "Enable WiFi control function abstraction"
+        depends on MACH_OMAP_4430SDP
+        select WIRELESS_EXT
+        select WEXT_CORE
+        select WEXT_PROC
+        select WEXT_PRIV
+        default Y
+        help
+           Enables Power/Reset/Carddetect function abstraction
+config TIWLAN_SDIO
+        bool "TI WLAN Enhanced SDIO Contoller support"
+        depends on MMC_OMAP || MMC_OMAP_MODULE || MMC_OMAP_HS || MMC_OMAP_HS_MODULE
+        help
+           Say Y here if you want to be able to use TI's WLAN device using the
+           SDIO interface. If unsure, say N.
+config TIWLAN_MMC_CONTROLLER
+        int "MMC Controller number that TI WLAN chip is connected to"
+        range 1 5
+        depends on TIWLAN_SDIO
+        default "5"
+        help
+          Choose the number of the MMC controller that TI WLAN chip is
+          connected to. TI WLAN has SDIO host controller that will control
+          this MMC port.
+
 config MACH_OMAP3517EVM
 	bool "OMAP3517/ AM3517 EVM board"
 	depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 13825a2ff2e9..0ab62c2082a2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -106,11 +106,20 @@ obj-$(CONFIG_OMAP3_EMU)			+= emu.o
 obj-$(CONFIG_OMAP_MBOX_FWK)		+= mailbox_mach.o
 mailbox_mach-objs			:= mailbox.o
 
-iommu-y					+= iommu2.o
-iommu-$(CONFIG_ARCH_OMAP3)		+= omap3-iommu.o
-
+ifeq ($(CONFIG_OMAP_REMOTE_PROC),y)
+obj-$(CONFIG_ARCH_OMAP2)		+= remoteproc24xx.o
+obj-$(CONFIG_ARCH_OMAP3)		+= remoteproc3xxx.o
+obj-$(CONFIG_ARCH_OMAP4)		+= remoteproc44xx.o
+endif
+iommu-y					+= iommu2.o omap-iommu.o
 obj-$(CONFIG_OMAP_IOMMU)		+= $(iommu-y)
 
+ifeq ($(CONFIG_OMAP_REMOTE_PROC),y)
+obj-$(CONFIG_ARCH_OMAP2)		+= remoteproc24xx.o
+obj-$(CONFIG_ARCH_OMAP3)		+= remoteproc3xxx.o
+obj-$(CONFIG_ARCH_OMAP4)		+= remoteproc44xx.o
+endif
+
 i2c-omap-$(CONFIG_I2C_OMAP)		:= i2c.o
 obj-y					+= $(i2c-omap-m) $(i2c-omap-y)
 
@@ -159,6 +168,7 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)	+= board-omap3touchbook.o \
 					   hsmmc.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)		+= board-4430sdp.o \
 					   hsmmc.o
+obj-$(CONFIG_TIWLAN_SDIO)               += board-4430sdp-wifi.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o
 
diff --git a/arch/arm/mach-omap2/board-4430sdp-wifi.c b/arch/arm/mach-omap2/board-4430sdp-wifi.c
new file mode 100644
index 000000000000..b13e9fc3767a
--- /dev/null
+++ b/arch/arm/mach-omap2/board-4430sdp-wifi.c
@@ -0,0 +1,138 @@
+/*
+ * Board support file for containing WiFi specific details for OMAP4430 SDP.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Author: Pradeep Gurumath <pradeepgurumath@ti.com>
+ *
+ * Based on mach-omap2/board-3430sdp.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* linux/arch/arm/mach-omap2/board-4430sdp-wifi.c
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/err.h>
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <plat/wifi_tiwlan.h>
+
+#define SDP4430_WIFI_PMENA_GPIO	 54
+#define SDP4430_WIFI_IRQ_GPIO	 53
+
+static int sdp4430_wifi_cd;		/* WIFI virtual 'card detect' status */
+static void (*wifi_status_cb)(int card_present, void *dev_id);
+static void *wifi_status_cb_devid;
+
+int omap_wifi_status_register(void (*callback)(int card_present,
+						void *dev_id), void *dev_id)
+{
+	if (wifi_status_cb)
+		return -EAGAIN;
+	wifi_status_cb = callback;
+
+	wifi_status_cb_devid = dev_id;
+
+	return 0;
+}
+
+int omap_wifi_status(int irq)
+{
+	return sdp4430_wifi_cd;
+}
+
+int sdp4430_wifi_set_carddetect(int val)
+{
+	printk(KERN_WARNING"%s: %d\n", __func__, val);
+	sdp4430_wifi_cd = val;
+	if (wifi_status_cb)
+		wifi_status_cb(val, wifi_status_cb_devid);
+	else
+		printk(KERN_WARNING "%s: Nobody to notify\n", __func__);
+	return 0;
+}
+#ifndef CONFIG_WIFI_CONTROL_FUNC
+EXPORT_SYMBOL(sdp4430_wifi_set_carddetect);
+#endif
+
+static int sdp4430_wifi_power_state;
+
+int sdp4430_wifi_power(int on)
+{
+	printk(KERN_WARNING"%s: %d\n", __func__, on);
+	gpio_set_value(SDP4430_WIFI_PMENA_GPIO, on);
+	sdp4430_wifi_power_state = on;
+	return 0;
+}
+#ifndef CONFIG_WIFI_CONTROL_FUNC
+EXPORT_SYMBOL(sdp4430_wifi_power);
+#endif
+
+static int sdp4430_wifi_reset_state;
+int sdp4430_wifi_reset(int on)
+{
+	printk(KERN_WARNING"%s: %d\n", __func__, on);
+	sdp4430_wifi_reset_state = on;
+	return 0;
+}
+#ifndef CONFIG_WIFI_CONTROL_FUNC
+EXPORT_SYMBOL(sdp4430_wifi_reset);
+#endif
+
+struct wifi_platform_data sdp4430_wifi_control = {
+	.set_power	= sdp4430_wifi_power,
+	.set_reset	= sdp4430_wifi_reset,
+	.set_carddetect	= sdp4430_wifi_set_carddetect,
+};
+
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+static struct resource sdp4430_wifi_resources[] = {
+	[0] = {
+		.name		= "device_wifi_irq",
+		.start		= OMAP_GPIO_IRQ(SDP4430_WIFI_IRQ_GPIO),
+		.end		= OMAP_GPIO_IRQ(SDP4430_WIFI_IRQ_GPIO),
+		.flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+	},
+};
+
+static struct platform_device sdp4430_wifi_device = {
+	.name           = "device_wifi",
+	.id             = 1,
+	.num_resources  = ARRAY_SIZE(sdp4430_wifi_resources),
+	.resource       = sdp4430_wifi_resources,
+	.dev            = {
+		.platform_data = &sdp4430_wifi_control,
+	},
+};
+#endif
+
+static int __init sdp4430_wifi_init(void)
+{
+	int ret;
+
+	printk(KERN_WARNING"%s: start\n", __func__);
+	ret = gpio_request(SDP4430_WIFI_IRQ_GPIO, "wifi_irq");
+	if (ret < 0) {
+		printk(KERN_ERR "%s: can't reserve GPIO: %d\n", __func__,
+			SDP4430_WIFI_IRQ_GPIO);
+		goto out;
+	}
+	gpio_direction_input(SDP4430_WIFI_IRQ_GPIO);
+#ifdef CONFIG_WIFI_CONTROL_FUNC
+	ret = platform_device_register(&sdp4430_wifi_device);
+#endif
+out:
+	return ret;
+}
+
+device_initcall(sdp4430_wifi_init);
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index c6f319c03096..916773dc0e6f 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -38,6 +38,8 @@
 #include <plat/common.h>
 #include <plat/control.h>
 #include <plat/timer-gp.h>
+#include <plat/display.h>
+#include <linux/delay.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 #include <plat/omap_hwmod.h>
@@ -361,8 +363,6 @@ error1:
 	return status;
 }
 
-/* Begin Synaptic Touchscreen TM-01217 */
-
 static char *tm12xx_idev_names[] = {
 	"Synaptic TM12XX TouchPoint 1",
 	"Synaptic TM12XX TouchPoint 2",
@@ -396,20 +396,245 @@ static struct tm12xx_ts_platform_data tm12xx_platform_data[] = {
 		.swap_xy = 1,
 	},
 };
+/* Begin Synaptic Touchscreen TM-01217 */
+static int sdp4430_taal_enable(struct omap_dss_device *dssdev)
+{
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD) {
+		gpio_request(102, "dsi1_en_gpio");	/* DSI1_GPIO_102*/
+		gpio_direction_output(102, 0);
+		mdelay(500);
+		gpio_set_value(102, 1);
+		mdelay(500);
+		gpio_set_value(102, 0);
+		mdelay(500);
+		gpio_set_value(102, 1);
+
+		twl_i2c_write_u8(TWL_MODULE_PWM, 0xFF, 0x03);
+		twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, 0x04);
+		twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x30, 0x92);
+
+		gpio_request(27, "dsi1_bl_gpio");	/*DSI1_GPIO_27*/
+		gpio_direction_output(27, 1);
+		mdelay(120);
+		gpio_set_value(27, 0);
+		mdelay(120);
+		gpio_set_value(27, 1);
+	} else {
+		gpio_request(104, "dsi2_en_gpio");	/* DSI2_GPIO_104 */
+		gpio_direction_output(104, 0);
+		mdelay(500);
+		gpio_set_value(104, 1);
+		mdelay(500);
+		gpio_set_value(104, 0);
+		mdelay(500);
+		gpio_set_value(104, 1);
+
+		twl_i2c_write_u8(TWL_MODULE_PWM, 0xFF, 0x03);
+		twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, 0x04);
+		twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x30, 0x92);
+
+		gpio_request(59, "dsi2_bl_gpio");	/* DSI2_GPIO_59 */
+		gpio_direction_output(59, 1);
+		mdelay(120);
+		gpio_set_value(59, 0);
+		mdelay(120);
+		gpio_set_value(59, 1);
+	}
+	return 0;
+}
 
-/* End Synaptic Touchscreen TM-01217 */
+static void sdp4430_taal_disable(struct omap_dss_device *dssdev)
+{
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD) {
+		gpio_set_value(102, 1);	/*DSI1_GPIO_102*/
+		gpio_set_value(27, 0);	/*DSI1_GPIO_27*/
+	} else {
+		gpio_set_value(104, 1);	/* DSI2_GPIO_104 */
+		gpio_set_value(59, 0);	/* DSI2_GPIO_59 */
+	}
+}
 
-static struct platform_device sdp4430_lcd_device = {
-	.name		= "sdp4430_lcd",
-	.id		= -1,
+static struct omap_dss_device sdp4430_lcd_device = {
+	.name			= "lcd",
+	.driver_name		= "taal",
+	.type			= OMAP_DISPLAY_TYPE_DSI,
+	.reset_gpio		= 102,
+	.phy.dsi		= {
+		.clk_lane	= 1,
+		.clk_pol	= 0,
+		.data1_lane	= 2,
+		.data1_pol	= 0,
+		.data2_lane	= 3,
+		.data2_pol	= 0,
+		.ext_te		= true,
+		.ext_te_gpio	= 101,
+		.div		= {
+			.lck_div	= 1,
+			.pck_div	= 6,
+			.regm		= 200,
+			.regn		= 19,
+			.regm3		= 4,
+			.regm4		= 5,
+			.lp_clk_div	= 6,
+		},
+	},
+	.platform_enable	=	sdp4430_taal_enable,
+	.platform_disable	=	sdp4430_taal_disable,
+	.channel			=	OMAP_DSS_CHANNEL_LCD,
 };
 
-static struct platform_device *sdp4430_devices[] __initdata = {
+static struct omap_dss_device sdp4430_lcd2_device = {
+	.name			= "2lcd",
+	.driver_name		= "taal2",
+	.type			= OMAP_DISPLAY_TYPE_DSI,
+	.reset_gpio		= 102,
+	.phy.dsi		= {
+		.clk_lane	= 1,
+		.clk_pol	= 0,
+		.data1_lane	= 2,
+		.data1_pol	= 0,
+		.data2_lane	= 3,
+		.data2_pol	= 0,
+		.ext_te		= true,
+		.ext_te_gpio	= 103,
+		.div		= {
+			.lck_div	= 1,
+			.pck_div	= 6,
+			.regm		= 200,
+			.regn		= 19,
+			.regm3		= 4,
+			.regm4		= 5,
+			.lp_clk_div	= 6,
+		},
+	},
+	.platform_enable	=	sdp4430_taal_enable,
+	.platform_disable	=	sdp4430_taal_disable,
+	.channel			=	OMAP_DSS_CHANNEL_LCD2,
+ };
+
+static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
+{
+	gpio_request(HDMI_GPIO_60 , "hdmi_gpio_60");
+	gpio_request(HDMI_GPIO_41 , "hdmi_gpio_41");
+	gpio_direction_output(HDMI_GPIO_60, 0);
+	gpio_direction_output(HDMI_GPIO_41, 0);
+	gpio_set_value(HDMI_GPIO_60, 1);
+	gpio_set_value(HDMI_GPIO_41, 1);
+	gpio_set_value(HDMI_GPIO_60, 0);
+	gpio_set_value(HDMI_GPIO_41, 0);
+	gpio_set_value(HDMI_GPIO_60, 1);
+	gpio_set_value(HDMI_GPIO_41, 1);
+	return 0;
+}
+
+static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev)
+{
+	gpio_set_value(HDMI_GPIO_60, 1);
+	gpio_set_value(HDMI_GPIO_41, 1);
+
+}
+
+static __attribute__ ((unused)) void __init sdp4430_hdmi_init(void)
+{
+	return;
+}
+
+static struct omap_dss_device sdp4430_hdmi_device = {
+	.name = "hdmi",
+	.driver_name = "hdmi_panel",
+	.type = OMAP_DISPLAY_TYPE_HDMI,
+	.phy.dpi.data_lines = 24,
+	.platform_enable = sdp4430_panel_enable_hdmi,
+	.platform_disable = sdp4430_panel_disable_hdmi,
+};
+
+static int sdp4430_panel_enable_pico_DLP(struct omap_dss_device *dssdev)
+{
+	int i = 0;
+	gpio_request(DLP_4430_GPIO_59, "DLP DISPLAY SEL");
+	gpio_direction_output(DLP_4430_GPIO_59, 0);
+	gpio_request(DLP_4430_GPIO_45, "DLP PARK");
+	gpio_direction_output(DLP_4430_GPIO_45, 0);
+	gpio_request(DLP_4430_GPIO_40, "DLP PHY RESET");
+	gpio_direction_output(DLP_4430_GPIO_40, 0);
+	gpio_request(DLP_4430_GPIO_44, "DLP READY RESET");
+	gpio_direction_input(DLP_4430_GPIO_44);
+	mdelay(500);
+
+	gpio_set_value(DLP_4430_GPIO_59, 1);
+	gpio_set_value(DLP_4430_GPIO_45, 1);
+	mdelay(1000);
+
+	gpio_set_value(DLP_4430_GPIO_40, 1);
+	mdelay(1000);
+
+	/*FIXME with the MLO gpio changes , gpio read is not retuning correct value even though 		it is  set in hardware so the check is comment till the problem is fixed */
+	/*while(i == 0){
+	i=gpio_get_value(DLP_4430_GPIO_44);
+	printk("wait for ready bit %d\n",i);
+	}*/
+	printk("%d ready bit ", i);
+	mdelay(2000);
+	return 0;
+}
+
+static void sdp4430_panel_disable_pico_DLP(struct omap_dss_device *dssdev)
+{
+	gpio_set_value(DLP_4430_GPIO_40, 0);
+	gpio_set_value(DLP_4430_GPIO_45, 0);
+
+}
+
+static struct omap_dss_device sdp4430_picoDLP_device = {
+	.name			            = "pico_DLP",
+	.driver_name		        = "picoDLP_panel",
+	.type			            = OMAP_DISPLAY_TYPE_DPI,
+	.phy.dpi.data_lines	        = 24,
+	.platform_enable	        = sdp4430_panel_enable_pico_DLP,
+	.platform_disable	        = sdp4430_panel_disable_pico_DLP,
+	.channel			= OMAP_DSS_CHANNEL_LCD2,
+};
+
+/* wl128x BT, FM, GPS connectivity chip */
+static int gpios[] = {55, -1, -1};
+static struct platform_device wl128x_device = {
+	.name           = "kim",
+	.id             = -1,
+	.dev.platform_data = &gpios,
+};
+
+static struct omap_dss_device *sdp4430_dss_devices[] = {
 	&sdp4430_lcd_device,
+	&sdp4430_lcd2_device,
+#ifdef CONFIG_OMAP2_DSS_HDMI
+	&sdp4430_hdmi_device,
+#endif
+#ifdef CONFIG_PANEL_PICO_DLP
+	&sdp4430_picoDLP_device,
+#endif
+};
+
+static struct omap_dss_board_info sdp4430_dss_data = {
+	.num_devices	=	ARRAY_SIZE(sdp4430_dss_devices),
+	.devices	=	sdp4430_dss_devices,
+	.default_device	=	&sdp4430_lcd_device,
+};
+
+static struct platform_device sdp4430_dss_device = {
+	.name	=	"omapdss",
+	.id	=	-1,
+	.dev	= {
+		.platform_data = &sdp4430_dss_data,
+	},
+};
+
+static struct platform_device *sdp4430_devices[] __initdata = {
+	&sdp4430_dss_device,
 	&sdp4430_keypad_device,
 	&sdp4430_proximity_device,
 	&sdp4430_leds_gpio,
 	&sdp4430_leds_pwm,
+	&wl128x_device,
 };
 
 static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -534,6 +759,13 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 	for (c = controllers; c->mmc; c++)
 		omap4_twl6030_hsmmc_set_late_init(c->dev);
 
+#ifdef CONFIG_TIWLAN_SDIO
+	/* The controller that is connected to the 128x device
+	should hould have the card detect gpio disabled. This is
+	achieved by initializing it with a negative value */
+	c[CONFIG_TIWLAN_MMC_CONTROLLER - 1].gpio_cd = -EINVAL;
+#endif
+
 	return 0;
 }
 
@@ -680,6 +912,17 @@ static struct twl4030_bci_platform_data sdp4430_bci_data = {
 	.low_bat_voltagemV		= 3300,
 };
 
+static struct twl4030_codec_data twl6040_codec = {
+#ifdef CONFIG_OMAP4_AUDIO_PWRON
+	.audpwron_gpio  = 127,
+#else
+	/* provide GPIO number above the valid value
+	 * to mean there is no GPIO connected. */
+	.audpwron_gpio  = 1024,
+	.naudint_irq    = OMAP44XX_IRQ_SYS_2N,
+#endif
+};
+
 static struct twl4030_platform_data sdp4430_twldata = {
 	.irq_base	= TWL6030_IRQ_BASE,
 	.irq_end	= TWL6030_IRQ_END,
@@ -697,6 +940,9 @@ static struct twl4030_platform_data sdp4430_twldata = {
 	.vaux3		= &sdp4430_vaux3,
 	.madc           = &sdp4430_gpadc_data,
 	.bci            = &sdp4430_bci_data,
+
+	/* children */
+	.codec		= &twl6040_codec,
 };
 
 static struct bq2415x_platform_data sdp4430_bqdata = {
@@ -716,6 +962,12 @@ static struct cma3000_platform_data cma3000_platform_data = {
 	.irqflags = IRQF_TRIGGER_HIGH,
 };
 
+static struct pico_platform_data picodlp_platform_data[] = {
+	[0] = { /* DLP Controller */
+		.gpio_intr = 40,
+	},
+};
+
 static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = {
 	{
 		I2C_BOARD_INFO("twl6030", 0x48),
@@ -734,6 +986,10 @@ static struct i2c_board_info __initdata sdp4430_i2c_2_boardinfo[] = {
 		I2C_BOARD_INFO("tm12xx_ts_primary", 0x4b),
 		.platform_data = &tm12xx_platform_data[0],
 	},
+    {
+		I2C_BOARD_INFO("picoDLP_i2c_driver", 0x1b),
+		.platform_data = &picodlp_platform_data[0],
+	},
 };
 
 static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
@@ -827,6 +1083,38 @@ fail1:
 	gpio_free(OMAP4_SFH7741_SENSOR_OUTPUT_GPIO);
 }
 
+#ifdef CONFIG_TIWLAN_SDIO
+static void pad_config(unsigned long pad_addr, u32 andmask, u32 ormask)
+{
+	int val;
+	u32 *addr;
+
+	addr = (u32 *) ioremap(pad_addr, 4);
+	if (!addr) {
+		printk(KERN_ERR"OMAP_pad_config: ioremap failed with addr %lx\n",
+			pad_addr);
+	return;
+	}
+
+	val =  __raw_readl(addr);
+	val &= andmask;
+	val |= ormask;
+	__raw_writel(val, addr);
+
+	iounmap(addr);
+}
+
+void wlan_1283_config()
+{
+	pad_config(0x4A100078, 0xFFECFFFF, 0x00030000);
+	pad_config(0x4A10007C, 0xFFFFFFEF, 0x0000000B);
+	if (gpio_request(54, NULL) != 0)
+		printk(KERN_ERR "GPIO 54 request failed\n");
+	gpio_direction_output(54, 0);
+	return ;
+}
+#endif
+
 static void omap_cma3000accl_init(void)
 {
 	if (gpio_request(OMAP4_CMA3000ACCL_GPIO, "Accelerometer") < 0) {
@@ -836,14 +1124,28 @@ static void omap_cma3000accl_init(void)
 	gpio_direction_input(OMAP4_CMA3000ACCL_GPIO);
 }
 
+static void __init omap4_display_init(void)
+{
+	void __iomem *phymux_base = NULL;
+	unsigned int dsimux = 0xFFFFFFFF;
+	phymux_base = ioremap(0x4A100000, 0x1000);
+	/* Turning on DSI PHY Mux*/
+	__raw_writel(dsimux, phymux_base+0x618);
+	dsimux = __raw_readl(phymux_base+0x618);
+}
+
 static void __init omap_4430sdp_init(void)
 {
 	int status;
 
 	omap4_i2c_init();
+	omap4_display_init();
 	platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
 	omap_serial_init();
 	omap4_twl6030_hsmmc_init(mmc);
+#ifdef CONFIG_TIWLAN_SDIO
+	wlan_1283_config();
+#endif
 	/* OMAP4 SDP uses internal transceiver so register nop transceiver */
 	usb_nop_xceiv_register();
 	usb_musb_init(&musb_board_data);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7f862ac1b8de..40440913e7c0 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -733,6 +733,58 @@ static inline void omap_hdq_init(void)
 static inline void omap_hdq_init(void) {}
 #endif
 
+/*---------------------------------------------------------------------------*/
+
+#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
+	defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
+#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
+#ifdef CONFIG_ARCH_OMAP4
+static struct resource omap_vout_resource[4 - CONFIG_FB_OMAP2_NUM_FBS] = {
+#else
+static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
+#endif
+};
+#else
+#ifdef CONFIG_ARCH_OMAP4
+static struct resource omap_vout_resource[3] = {
+#else
+static struct resource omap_vout_resource[2] = {
+#endif
+};
+#endif
+
+static struct platform_device omap_vout_device = {
+	.name		= "omap_vout",
+	.num_resources	= ARRAY_SIZE(omap_vout_resource),
+	.resource	= &omap_vout_resource[0],
+	.id		= -1,
+};
+static void omap_init_vout(void)
+{
+	if (platform_device_register(&omap_vout_device) < 0)
+		printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
+}
+
+static struct resource sdp4430_wb_resource[1] = {
+};
+
+static struct platform_device sdp4430_wb_device = {
+	.name		= "omap_wb",
+	.num_resources	= ARRAY_SIZE(sdp4430_wb_resource),
+	.resource	= &sdp4430_wb_resource[0],
+	.id		= -1,
+};
+
+static void omap_init_wb(void)
+{
+		(void) platform_device_register(&sdp4430_wb_device);
+}
+
+#else
+static inline void omap_init_vout(void) {}
+static void omap_init_wb(void) {}
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 static int __init omap2_init_devices(void)
@@ -747,6 +799,9 @@ static int __init omap2_init_devices(void)
 	omap_hdq_init();
 	omap_init_sti();
 	omap_init_sha1_md5();
+	omap_init_vout();
+	if (cpu_is_omap44xx())
+		omap_init_wb();
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 6a6dd3e7a772..215bb3fadabb 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -19,6 +19,11 @@
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 
+#ifdef CONFIG_TIWLAN_SDIO
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/sdio_func.h>
+#endif
+
 #include "hsmmc.h"
 
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
@@ -197,6 +202,30 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot,
 
 static struct omap_mmc_platform_data *hsmmc_data[OMAP44XX_NR_MMC] __initdata;
 
+#ifdef CONFIG_TIWLAN_SDIO
+static struct sdio_embedded_func wifi_func_array[] = {
+        {
+                .f_class        = SDIO_CLASS_BT_A,
+                .f_maxblksize   = 512,
+        },
+        {
+                .f_class        = SDIO_CLASS_WLAN,
+                .f_maxblksize   = 512,
+        },
+};
+
+static struct embedded_sdio_data omap_wifi_emb_data = {
+        .cis    = {
+                .vendor         = SDIO_VENDOR_ID_TI,
+                .device         = SDIO_DEVICE_ID_TI_WL12xx,
+                .blksize        = 512,
+                .max_dtr        = 24000000,
+        },
+        .funcs  = wifi_func_array,
+	.quirks = MMC_QUIRK_VDD_165_195 | MMC_QUIRK_LENIENT_FUNC0,
+};
+#endif
+
 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
 	struct omap2_hsmmc_info *c;
@@ -254,6 +283,16 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 		else
 			snprintf(hc->name, ARRAY_SIZE(hc->name),
 				"mmc%islot%i", c->mmc, 1);
+
+#ifdef CONFIG_TIWLAN_SDIO
+                if (c->mmc == CONFIG_TIWLAN_MMC_CONTROLLER) {
+                        mmc->slots[0].embedded_sdio = &omap_wifi_emb_data;
+                        mmc->slots[0].register_status_notify =
+                                &omap_wifi_status_register;
+                        mmc->slots[0].card_detect = &omap_wifi_status;
+                }
+#endif
+
 		mmc->slots[0].name = hc->name;
 		mmc->nr_slots = 1;
 		mmc->slots[0].wires = c->wires;
@@ -327,6 +366,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 			/* TODO Update required */
 			mmc->slots[0].before_set_reg = NULL;
 			mmc->slots[0].after_set_reg = NULL;
+#ifdef CONFIG_TIWLAN_SDIO
+                        mmc->slots[0].ocr_mask  = MMC_VDD_165_195;
+#endif
 			break;
 		default:
 			pr_err("MMC%d configuration not supported!\n", c->mmc);
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index 36f0ba8d89e2..abaaa753dc53 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -25,6 +25,12 @@ struct omap2_hsmmc_info {
 	void (*remux)(struct device *dev, int slot, int power_on);
 };
 
+#ifdef CONFIG_TIWLAN_SDIO
+int omap_wifi_status_register(void (*callback)(int card_present,
+        void *dev_id), void *dev_id);
+int omap_wifi_status(int irq);
+#endif
+
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
 void omap2_hsmmc_init(struct omap2_hsmmc_info *);
diff --git a/arch/arm/mach-omap2/include/mach/dmm.h b/arch/arm/mach-omap2/include/mach/dmm.h
new file mode 100644
index 000000000000..700f08aefbc4
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/dmm.h
@@ -0,0 +1,126 @@
+/*
+ * dmm.h
+ *
+ * DMM driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef DMM_H
+#define DMM_H
+
+#define DMM_BASE 0x4E000000
+#define DMM_SIZE 0x800
+
+#define DMM_REVISION          0x000
+#define DMM_HWINFO            0x004
+#define DMM_LISA_HWINFO       0x008
+#define DMM_DMM_SYSCONFIG     0x010
+#define DMM_LISA_LOCK         0x01C
+#define DMM_LISA_MAP__0       0x040
+#define DMM_LISA_MAP__1       0x044
+#define DMM_TILER_HWINFO      0x208
+#define DMM_TILER_OR__0       0x220
+#define DMM_TILER_OR__1       0x224
+#define DMM_PAT_HWINFO        0x408
+#define DMM_PAT_GEOMETRY      0x40C
+#define DMM_PAT_CONFIG        0x410
+#define DMM_PAT_VIEW__0       0x420
+#define DMM_PAT_VIEW__1       0x424
+#define DMM_PAT_VIEW_MAP__0   0x440
+#define DMM_PAT_VIEW_MAP_BASE 0x460
+#define DMM_PAT_IRQ_EOI       0x478
+#define DMM_PAT_IRQSTATUS_RAW 0x480
+#define DMM_PAT_IRQSTATUS     0x490
+#define DMM_PAT_IRQENABLE_SET 0x4A0
+#define DMM_PAT_IRQENABLE_CLR 0x4B0
+#define DMM_PAT_STATUS__0     0x4C0
+#define DMM_PAT_STATUS__1     0x4C4
+#define DMM_PAT_STATUS__2     0x4C8
+#define DMM_PAT_STATUS__3     0x4CC
+#define DMM_PAT_DESCR__0      0x500
+#define DMM_PAT_AREA__0       0x504
+#define DMM_PAT_CTRL__0       0x508
+#define DMM_PAT_DATA__0       0x50C
+#define DMM_PEG_HWINFO        0x608
+#define DMM_PEG_PRIO          0x620
+#define DMM_PEG_PRIO_PAT      0x640
+
+/**
+ * PAT refill programming mode.
+ */
+enum pat_mode {
+	MANUAL,
+	AUTO
+};
+
+/**
+ * Area definition for DMM physical address translator.
+ */
+struct pat_area {
+	s32 x0:8;
+	s32 y0:8;
+	s32 x1:8;
+	s32 y1:8;
+};
+
+/**
+ * DMM physical address translator control.
+ */
+struct pat_ctrl {
+	s32 start:4;
+	s32 dir:4;
+	s32 lut_id:8;
+	s32 sync:12;
+	s32 ini:4;
+};
+
+/**
+ * PAT descriptor.
+ */
+struct pat {
+	struct pat *next;
+	struct pat_area area;
+	struct pat_ctrl ctrl;
+	u32 data;
+};
+
+/**
+ * DMM device data
+ */
+struct dmm {
+	void __iomem *base;
+};
+
+/**
+ * Create and initialize the physical address translator.
+ * @param id    PAT id
+ * @return pointer to device data
+ */
+struct dmm *dmm_pat_init(u32 id);
+
+/**
+ * Program the physical address translator.
+ * @param dmm   Device data
+ * @param desc  PAT descriptor
+ * @param mode  programming mode
+ * @return an error status.
+ */
+s32 dmm_pat_refill(struct dmm *dmm, struct pat *desc, enum pat_mode mode);
+
+/**
+ * Clean up the physical address translator.
+ * @param dmm    Device data
+ * @return an error status.
+ */
+void dmm_pat_release(struct dmm *dmm);
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/tiler.h b/arch/arm/mach-omap2/include/mach/tiler.h
new file mode 100644
index 000000000000..ba3b779d6223
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/tiler.h
@@ -0,0 +1,216 @@
+/*
+ * tiler.h
+ *
+ * TILER driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef TILER_H
+#define TILER_H
+
+#define TILER_PAGE 0x1000
+#define TILER_WIDTH    256
+#define TILER_HEIGHT   128
+#define TILER_BLOCK_WIDTH  64
+#define TILER_BLOCK_HEIGHT 64
+#define TILER_LENGTH (TILER_WIDTH * TILER_HEIGHT * TILER_PAGE)
+
+#define TILER_MAX_NUM_BLOCKS 16
+
+#define TILIOC_GBUF  _IOWR('z', 100, u32)
+#define TILIOC_FBUF  _IOWR('z', 101, u32)
+#define TILIOC_GSSP  _IOWR('z', 102, u32)
+#define TILIOC_MBUF  _IOWR('z', 103, u32)
+#define TILIOC_UMBUF _IOWR('z', 104, u32)
+#define TILIOC_QBUF  _IOWR('z', 105, u32)
+#define TILIOC_RBUF  _IOWR('z', 106, u32)
+#define TILIOC_URBUF _IOWR('z', 107, u32)
+#define TILIOC_QUERY_BLK _IOWR('z', 108, u32)
+
+enum tiler_fmt {
+	TILFMT_MIN     = -1,
+	TILFMT_INVALID = -1,
+	TILFMT_NONE    = 0,
+	TILFMT_8BIT    = 1,
+	TILFMT_16BIT   = 2,
+	TILFMT_32BIT   = 3,
+	TILFMT_PAGE    = 4,
+	TILFMT_MAX     = 4
+};
+
+struct area {
+	u16 width;
+	u16 height;
+};
+
+struct tiler_block_info {
+	enum tiler_fmt fmt;
+	union {
+		struct area area;
+		u32 len;
+	} dim;
+	u32 stride;
+	void *ptr;
+	u32 ssptr;
+};
+
+struct tiler_buf_info {
+	s32 num_blocks;
+	struct tiler_block_info blocks[TILER_MAX_NUM_BLOCKS];
+	s32 offset;
+};
+
+struct tiler_view_orient {
+	u8 rotate_90;
+	u8 x_invert;
+	u8 y_invert;
+};
+
+/* utility functions */
+static inline u32 tilfmt_bpp(enum tiler_fmt fmt)
+{
+	return  fmt == TILFMT_8BIT ? 1 :
+		fmt == TILFMT_16BIT ? 2 :
+		fmt == TILFMT_32BIT ? 4 : 0;
+}
+
+/**
+ * Reserves a 1D or 2D TILER block area and memory for the
+ * current process with group ID 0.
+ *
+ * @param fmt 		TILER bit mode
+ * @param width 	block width
+ * @param height 	block height (must be 1 for 1D)
+ * @param sys_addr 	pointer where system space (L3) address
+ *  			will be stored.
+ *
+ * @return error status
+ */
+s32 tiler_alloc(enum tiler_fmt fmt, u32 width, u32 height, u32 *sys_addr);
+
+/**
+ * Reserves a 1D or 2D TILER block area and memory with extended
+ * arguments.
+ *
+ * @param fmt 		TILER bit mode
+ * @param width 	block width
+ * @param height 	block height (must be 1 for 1D)
+ * @param align 	block alignment (default: PAGE_SIZE)
+ * @param offs 		block offset
+ * @param gid 		group ID
+ * @param pid 		process ID
+ * @param sys_addr 	pointer where system space (L3) address
+ *  			will be stored.
+ *
+ * @return error status
+ */
+s32 tiler_allocx(enum tiler_fmt fmt, u32 width, u32 height,
+			u32 align, u32 offs, u32 gid, pid_t pid, u32 *sys_addr);
+
+/**
+ * Maps an existing buffer to a 1D or 2D TILER area for the
+ * current process with group ID 0.
+ *
+ * Currently, only 1D area mapping is supported.
+ *
+ * @param fmt 		TILER bit mode
+ * @param width 	block width
+ * @param height 	block height (must be 1 for 1D)
+ * @param sys_addr 	pointer where system space (L3) address
+ *  			will be stored.
+ * @param usr_addr	user space address of existing buffer.
+ *
+ * @return error status
+ */
+s32 tiler_map(enum tiler_fmt fmt, u32 width, u32 height, u32 *sys_addr,
+								u32 usr_addr);
+
+/**
+ * Maps an existing buffer to a 1D or 2D TILER area with
+ * extended arguments.
+ *
+ * Currently, only 1D area mapping is supported.
+ *
+ * NOTE: alignment is always PAGE_SIZE and offset is 0
+ *
+ * @param fmt 		TILER bit mode
+ * @param width 	block width
+ * @param height 	block height (must be 1 for 1D)
+ * @param gid 		group ID
+ * @param pid 		process ID
+ * @param sys_addr 	pointer where system space (L3) address
+ *  			will be stored.
+ * @param usr_addr	user space address of existing buffer.
+ *
+ * @return error status
+ */
+s32 tiler_mapx(enum tiler_fmt fmt, u32 width, u32 height,
+			u32 gid, pid_t pid, u32 *sys_addr, u32 usr_addr);
+
+/**
+ * Free TILER memory.
+ *
+ * @param sys_addr system space (L3) address.
+ *
+ * @return an error status.
+ */
+s32 tiler_free(u32 sys_addr);
+
+/**
+ * Reserves tiler area for n identical set of blocks (buffer)
+ * for the current process.  Use this method to get optimal
+ * placement of multiple related tiler blocks; however, it may
+ * not reserve area if tiler_alloc is equally efficient.
+ *
+ * @param n 	number of identical set of blocks
+ * @param b	information on the set of blocks (ptr, ssptr and
+ *  		stride fields are ignored)
+ *
+ * @return error status
+ */
+s32 tiler_reserve(u32 n, struct tiler_buf_info *b);
+
+/**
+ * Reserves tiler area for n identical set of blocks (buffer) fo
+ * a given process. Use this method to get optimal placement of
+ * multiple related tiler blocks; however, it may not reserve
+ * area if tiler_alloc is equally efficient.
+ *
+ * @param n 	number of identical set of blocks
+ * @param b	information on the set of blocks (ptr, ssptr and
+ *  		stride fields are ignored)
+ * @param pid   process ID
+ *
+ * @return error status
+ */
+s32 tiler_reservex(u32 n, struct tiler_buf_info *b, pid_t pid);
+
+u32 tiler_reorient_addr(u32 tsptr, struct tiler_view_orient orient);
+
+u32 tiler_get_natural_addr(void *sys_ptr);
+
+u32 tiler_reorient_topleft(u32 tsptr, struct tiler_view_orient orient,
+				u32 width, u32 height);
+
+u32 tiler_stride(u32 tsptr);
+
+void tiler_rotate_view(struct tiler_view_orient *orient, u32 rotation);
+
+void tiler_alloc_packed(s32 *count, enum tiler_fmt fmt, u32 width, u32 height,
+			void **sysptr, void **allocptr, s32 aligned);
+
+void tiler_alloc_packed_nv12(s32 *count, u32 width, u32 height, void **y_sysptr,
+				void **uv_sysptr, void **y_allocptr,
+				void **uv_allocptr, s32 aligned);
+
+#endif
+
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 4f63dc6859a4..3cfe1c4b5f11 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -44,9 +44,13 @@
 #define MMU_IRQ_EMUMISS		(1 << 2)
 #define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
 #define MMU_IRQ_TLBMISS		(1 << 0)
-#define MMU_IRQ_MASK	\
-	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
-	 MMU_IRQ_TRANSLATIONFAULT)
+
+#define __MMU_IRQ_FAULT		\
+	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
+#define MMU_IRQ_MASK		\
+	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
+#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
+#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
 
 /* MMU_CNTL */
 #define MMU_CNTL_SHIFT		1
@@ -61,6 +65,25 @@
 	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
 	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
 
+
+static void omap2_iommu_set_twl(struct iommu *obj, bool on)
+{
+	u32 l = iommu_read_reg(obj, MMU_CNTL);
+
+	if (on)
+		iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
+	else
+		iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
+
+	l &= ~MMU_CNTL_MASK;
+	if (on)
+		l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
+	else
+		l |= (MMU_CNTL_MMU_EN);
+
+	iommu_write_reg(obj, l, MMU_CNTL);
+}
+
 static int omap2_iommu_enable(struct iommu *obj)
 {
 	u32 l, pa;
@@ -96,13 +119,9 @@ static int omap2_iommu_enable(struct iommu *obj)
 	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
 	iommu_write_reg(obj, l, MMU_SYSCONFIG);
 
-	iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
 	iommu_write_reg(obj, pa, MMU_TTB);
 
-	l = iommu_read_reg(obj, MMU_CNTL);
-	l &= ~MMU_CNTL_MASK;
-	l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
-	iommu_write_reg(obj, l, MMU_CNTL);
+	omap2_iommu_set_twl(obj, true);
 
 	return 0;
 }
@@ -147,6 +166,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 	printk("\n");
 
 	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
+	omap2_iommu_disable(obj);
 	return stat;
 }
 
@@ -184,7 +204,7 @@ static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
 	if (!cr)
 		return ERR_PTR(-ENOMEM);
 
-	cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz;
+	cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
 	cr->ram = e->pa | e->endian | e->elsz | e->mixed;
 
 	return cr;
@@ -212,7 +232,8 @@ static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
 	char *p = buf;
 
 	/* FIXME: Need more detail analysis of cam/ram */
-	p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);
+	p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
+					(cr->cam & MMU_CAM_P) ? 1 : 0);
 
 	return p - buf;
 }
@@ -298,6 +319,7 @@ static const struct iommu_functions omap2_iommu_ops = {
 
 	.enable		= omap2_iommu_enable,
 	.disable	= omap2_iommu_disable,
+	.set_twl	= omap2_iommu_set_twl,
 	.fault_isr	= omap2_iommu_fault_isr,
 
 	.tlb_read_cr	= omap2_tlb_read_cr,
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 318f3638653c..afc95aa5b519 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -94,13 +94,15 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
 	u32 l;
 	unsigned long timeout;
 
-	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
-	if (IS_ERR(mbox_ick_handle)) {
-		printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
-			PTR_ERR(mbox_ick_handle));
-		return PTR_ERR(mbox_ick_handle);
+	if (!cpu_is_omap44xx()) {
+		mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
+		if (IS_ERR(mbox_ick_handle)) {
+			printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
+				PTR_ERR(mbox_ick_handle));
+			return PTR_ERR(mbox_ick_handle);
+		}
+		clk_enable(mbox_ick_handle);
 	}
-	clk_enable(mbox_ick_handle);
 
 	if (cpu_is_omap44xx()) {
 		mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
@@ -146,9 +148,11 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
 
 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
 {
-	clk_disable(mbox_ick_handle);
-	clk_put(mbox_ick_handle);
-	mbox_ick_handle = NULL;
+	if (!cpu_is_omap44xx()) {
+		clk_disable(mbox_ick_handle);
+		clk_put(mbox_ick_handle);
+		mbox_ick_handle = NULL;
+	}
 }
 
 /* Mailbox FIFO handle functions */
@@ -486,5 +490,6 @@ module_exit(omap2_mbox_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
-MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
+MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
+MODULE_AUTHOR("Paul Mundt");
 MODULE_ALIAS("platform:"DRV_NAME);
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 1fbbdda76717..9cf02a71653a 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -195,7 +195,6 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
 		.phys_base      = OMAP44XX_MCBSP1_BASE,
 		.dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
 		.dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
-		.rx_irq         = OMAP44XX_IRQ_MCBSP1,
 		.tx_irq         = OMAP44XX_IRQ_MCBSP1,
 		.ops            = &omap2_mcbsp_ops,
 	},
@@ -203,7 +202,6 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
 		.phys_base      = OMAP44XX_MCBSP2_BASE,
 		.dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
 		.dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
-		.rx_irq         = OMAP44XX_IRQ_MCBSP2,
 		.tx_irq         = OMAP44XX_IRQ_MCBSP2,
 		.ops            = &omap2_mcbsp_ops,
 	},
@@ -211,7 +209,6 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
 		.phys_base      = OMAP44XX_MCBSP3_BASE,
 		.dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
 		.dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
-		.rx_irq         = OMAP44XX_IRQ_MCBSP3,
 		.tx_irq         = OMAP44XX_IRQ_MCBSP3,
 		.ops            = &omap2_mcbsp_ops,
 	},
@@ -219,7 +216,6 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
 		.phys_base      = OMAP44XX_MCBSP4_BASE,
 		.dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
 		.dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
-		.rx_irq         = OMAP44XX_IRQ_MCBSP4,
 		.tx_irq         = OMAP44XX_IRQ_MCBSP4,
 		.ops            = &omap2_mcbsp_ops,
 	},
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
new file mode 100644
index 000000000000..f6015702f8ee
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -0,0 +1,168 @@
+/*
+ * omap iommu: omap device registration
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+
+#include <plat/iommu.h>
+#include <plat/irqs.h>
+
+struct iommu_device {
+	resource_size_t base;
+	int irq;
+	struct iommu_platform_data pdata;
+	struct resource res[2];
+};
+static struct iommu_device *devices;
+static int num_iommu_devices;
+
+#ifdef CONFIG_ARCH_OMAP3
+static struct iommu_device omap3_devices[] = {
+	{
+		.base = 0x480bd400,
+		.irq = 24,
+		.pdata = {
+			.name = "isp",
+			.nr_tlb_entries = 8,
+			.clk_name = "cam_ick",
+		},
+	},
+#if defined(CONFIG_MPU_BRIDGE_IOMMU)
+	{
+		.base = 0x5d000000,
+		.irq = 28,
+		.pdata = {
+			.name = "iva2",
+			.nr_tlb_entries = 32,
+			.clk_name = "iva2_ck",
+		},
+	},
+#endif
+};
+#define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices)
+static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
+#else
+#define omap3_devices		NULL
+#define NR_OMAP3_IOMMU_DEVICES	0
+#define omap3_iommu_pdev	NULL
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+static struct iommu_device omap4_devices[] = {
+	{
+		.base = OMAP4_MMU1_BASE,
+		.irq = OMAP44XX_IRQ_DUCATI_MMU,
+		.pdata = {
+			.name = "ducati",
+			.nr_tlb_entries = 32,
+			.clk_name = "ipu_ick",
+		},
+	},
+#if defined(CONFIG_MPU_TESLA_IOMMU)
+	{
+		.base = OMAP4_MMU2_BASE,
+		.irq = INT_44XX_DSP_MMU,
+		.pdata = {
+			.name = "tesla",
+			.nr_tlb_entries = 32,
+			.clk_name = "iva_ick",
+		},
+	},
+#endif
+};
+#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
+static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
+#else
+#define omap4_devices		NULL
+#define NR_OMAP4_IOMMU_DEVICES	0
+#define omap4_iommu_pdev	NULL
+#endif
+
+static struct platform_device **omap_iommu_pdev;
+
+int iommu_get_plat_data_size()
+{
+	return num_iommu_devices;
+}
+EXPORT_SYMBOL(iommu_get_plat_data_size);
+
+struct iommu_device *iommu_get_device_data(void)
+{
+	return devices;
+}
+
+static int __init omap_iommu_init(void)
+{
+	int i, err;
+	struct resource res[] = {
+		{ .flags = IORESOURCE_MEM },
+		{ .flags = IORESOURCE_IRQ },
+	};
+
+	if (cpu_is_omap34xx()) {
+		devices = omap3_devices;
+		omap_iommu_pdev = omap3_iommu_pdev;
+		num_iommu_devices = NR_OMAP3_IOMMU_DEVICES;
+	} else if (cpu_is_omap44xx()) {
+		devices = omap4_devices;
+		omap_iommu_pdev = omap4_iommu_pdev;
+		num_iommu_devices = NR_OMAP4_IOMMU_DEVICES;
+	} else
+		return -ENODEV;
+
+	for (i = 0; i < num_iommu_devices; i++) {
+		struct platform_device *pdev;
+		const struct iommu_device *d = &devices[i];
+
+		pdev = platform_device_alloc("omap-iommu", i);
+		if (!pdev) {
+			err = -ENOMEM;
+			goto err_out;
+		}
+
+		res[0].start = d->base;
+		res[0].end = d->base + MMU_REG_SIZE - 1;
+		res[1].start = res[1].end = d->irq;
+
+		err = platform_device_add_resources(pdev, res,
+						    ARRAY_SIZE(res));
+		if (err)
+			goto err_out;
+		err = platform_device_add_data(pdev, &d->pdata,
+					       sizeof(d->pdata));
+		if (err)
+			goto err_out;
+		err = platform_device_add(pdev);
+		if (err)
+			goto err_out;
+		omap_iommu_pdev[i] = pdev;
+	}
+	return 0;
+
+err_out:
+	while (i--)
+		platform_device_put(omap_iommu_pdev[i]);
+	return err;
+}
+module_init(omap_iommu_init);
+
+static void __exit omap_iommu_exit(void)
+{
+	int i;
+
+	for (i = 0; i < num_iommu_devices; i++)
+		platform_device_unregister(omap_iommu_pdev[i]);
+}
+module_exit(omap_iommu_exit);
+
+MODULE_AUTHOR("Hiroshi DOYU");
+MODULE_DESCRIPTION("omap iommu: omap device registration");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c
deleted file mode 100644
index fbbcb5c83367..000000000000
--- a/arch/arm/mach-omap2/omap3-iommu.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * omap iommu: omap3 device registration
- *
- * Copyright (C) 2008-2009 Nokia Corporation
- *
- * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-
-#include <plat/iommu.h>
-
-struct iommu_device {
-	resource_size_t base;
-	int irq;
-	struct iommu_platform_data pdata;
-	struct resource res[2];
-};
-
-static struct iommu_device devices[] = {
-	{
-		.base = 0x480bd400,
-		.irq = 24,
-		.pdata = {
-			.name = "isp",
-			.nr_tlb_entries = 8,
-			.clk_name = "cam_ick",
-		},
-	},
-#if defined(CONFIG_MPU_BRIDGE_IOMMU)
-	{
-		.base = 0x5d000000,
-		.irq = 28,
-		.pdata = {
-			.name = "iva2",
-			.nr_tlb_entries = 32,
-			.clk_name = "iva2_ck",
-		},
-	},
-#endif
-};
-#define NR_IOMMU_DEVICES ARRAY_SIZE(devices)
-
-static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES];
-
-static int __init omap3_iommu_init(void)
-{
-	int i, err;
-	struct resource res[] = {
-		{ .flags = IORESOURCE_MEM },
-		{ .flags = IORESOURCE_IRQ },
-	};
-
-	for (i = 0; i < NR_IOMMU_DEVICES; i++) {
-		struct platform_device *pdev;
-		const struct iommu_device *d = &devices[i];
-
-		pdev = platform_device_alloc("omap-iommu", i);
-		if (!pdev) {
-			err = -ENOMEM;
-			goto err_out;
-		}
-
-		res[0].start = d->base;
-		res[0].end = d->base + MMU_REG_SIZE - 1;
-		res[1].start = res[1].end = d->irq;
-
-		err = platform_device_add_resources(pdev, res,
-						    ARRAY_SIZE(res));
-		if (err)
-			goto err_out;
-		err = platform_device_add_data(pdev, &d->pdata,
-					       sizeof(d->pdata));
-		if (err)
-			goto err_out;
-		err = platform_device_add(pdev);
-		if (err)
-			goto err_out;
-		omap3_iommu_pdev[i] = pdev;
-	}
-	return 0;
-
-err_out:
-	while (i--)
-		platform_device_put(omap3_iommu_pdev[i]);
-	return err;
-}
-module_init(omap3_iommu_init);
-
-static void __exit omap3_iommu_exit(void)
-{
-	int i;
-
-	for (i = 0; i < NR_IOMMU_DEVICES; i++)
-		platform_device_unregister(omap3_iommu_pdev[i]);
-}
-module_exit(omap3_iommu_exit);
-
-MODULE_AUTHOR("Hiroshi DOYU");
-MODULE_DESCRIPTION("omap iommu: omap3 device registration");
-MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/remoteproc44xx.c b/arch/arm/mach-omap2/remoteproc44xx.c
new file mode 100644
index 000000000000..5972e2c02c37
--- /dev/null
+++ b/arch/arm/mach-omap2/remoteproc44xx.c
@@ -0,0 +1,236 @@
+/*
+ * Remote Processor machine-specific module for OMAP3
+ *
+ * Copyright (C) 2010 Texas Instruments Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <plat/remoteproc.h>
+#include <mach/irqs.h>
+#include <plat/omap_device.h>
+
+#include "cm.h"
+#include "prm.h"
+
+#define RM_M3_RST1ST				0x1
+#define RM_M3_RST2ST				0x2
+#define RM_M3_RST3ST				0x4
+#define RM_M3_REL_RST1_MASK			0x2
+#define RM_M3_REL_RST2_MASK			0x0
+#define RM_M3_AST_RST1_MASK			0x3
+#define RM_M3_AST_RST2_MASK			0x2
+
+#define M3_CLK_MOD_MODE_HW_AUTO			0x1
+#define M3_CLKTRCTRL_SW_WKUP			0x2
+#define M3_CLKTRCTRL_SW_SLEEP			0x1
+#define M3_CLKACTIVITY_MPU_M3_CLK		0x100
+
+static inline int proc44x_sysm3_start(struct omap_rproc *rproc)
+{
+	u32 reg;
+	int counter = 10;
+	struct device *dev = rproc->dev;
+
+	/* Module is managed automatically by HW */
+	cm_write_mod_reg(M3_CLK_MOD_MODE_HW_AUTO, OMAP4430_CM2_CORE_MOD,
+					OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET);
+
+	/* Enable the M3 clock */
+	cm_write_mod_reg(M3_CLKTRCTRL_SW_WKUP, OMAP4430_CM2_CORE_MOD,
+					OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET);
+	do {
+		reg = cm_read_mod_reg(OMAP4430_CM2_CORE_MOD,
+					OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET);
+		if (reg & M3_CLKACTIVITY_MPU_M3_CLK) {
+			dev_info(dev, "M3 clock enabled:"
+			"OMAP4430_CM_DUCATI_CLKSTCTRL = 0x%x\n", reg);
+			break;
+		}
+		msleep(1);
+	} while (--counter);
+	if (counter == 0) {
+		dev_info(dev, "FAILED TO ENABLE DUCATI M3 CLOCK !%x\n", reg);
+		return -EFAULT;
+	}
+
+	/* De-assert RST1, and clear the Reset status */
+	dev_info(dev, "De-assert RST1\n");
+	prm_write_mod_reg(RM_M3_REL_RST1_MASK, OMAP4430_PRM_CORE_MOD,
+				OMAP4_RM_DUCATI_RSTCTRL_OFFSET);
+	while (!(prm_read_mod_reg(OMAP4430_PRM_CORE_MOD,
+		OMAP4_RM_DUCATI_RSTST_OFFSET) & RM_M3_RST1ST))
+		;
+	dev_info(dev, "RST1 released!");
+
+	prm_write_mod_reg(RM_M3_RST1ST, OMAP4430_PRM_CORE_MOD,
+				OMAP4_RM_DUCATI_RSTST_OFFSET);
+
+	return 0;
+}
+
+static inline int proc44x_appm3_start(struct omap_rproc *rproc)
+{
+	struct device *dev = rproc->dev;
+
+	/* De-assert RST2, and clear the Reset status */
+	dev_info(dev, "De-assert RST2\n");
+	prm_write_mod_reg(RM_M3_REL_RST2_MASK, OMAP4430_PRM_CORE_MOD,
+				OMAP4_RM_DUCATI_RSTCTRL_OFFSET);
+
+	while (!(prm_read_mod_reg(OMAP4430_PRM_CORE_MOD,
+		OMAP4_RM_DUCATI_RSTST_OFFSET) & RM_M3_RST2ST))
+		;
+	dev_info(dev, "RST2 released!");
+
+	prm_write_mod_reg(RM_M3_RST2ST, OMAP4430_PRM_CORE_MOD,
+				OMAP4_RM_DUCATI_RSTST_OFFSET);
+
+	return 0;
+}
+
+static inline int proc44x_sysm3_stop(struct omap_rproc *rproc)
+{
+	struct device *dev = rproc->dev;
+	u32 reg;
+
+	reg = prm_read_mod_reg(OMAP4430_PRM_CORE_MOD,
+					OMAP4_RM_DUCATI_RSTCTRL_OFFSET);
+
+	dev_info(dev, "assert RST1 reg = 0x%x\n", reg);
+	prm_write_mod_reg((reg | RM_M3_AST_RST1_MASK), OMAP4430_PRM_CORE_MOD,
+				OMAP4_RM_DUCATI_RSTCTRL_OFFSET);
+	return 0;
+}
+
+static inline int proc44x_appm3_stop(struct omap_rproc *rproc)
+{
+	struct device *dev = rproc->dev;
+	u32 reg;
+
+	reg = prm_read_mod_reg(OMAP4430_PRM_CORE_MOD,
+					OMAP4_RM_DUCATI_RSTCTRL_OFFSET);
+
+	dev_info(dev, "assert RST2 reg = 0x%x\n", reg);
+	prm_write_mod_reg((reg | RM_M3_AST_RST2_MASK), OMAP4430_PRM_CORE_MOD,
+				OMAP4_RM_DUCATI_RSTCTRL_OFFSET);
+	return 0;
+}
+
+static inline int omap4_rproc_get_state(struct omap_rproc *rproc)
+{
+	return rproc->state;
+}
+
+static struct omap_rproc_ops omap4_ducati0_ops = {
+	.start = proc44x_sysm3_start,
+	.stop = proc44x_sysm3_stop,
+	.get_state = omap4_rproc_get_state,
+};
+
+static struct omap_rproc_ops omap4_ducati1_ops = {
+	.start = proc44x_appm3_start,
+	.stop = proc44x_appm3_stop,
+	.get_state = omap4_rproc_get_state,
+};
+
+static struct omap_rproc_ops omap4_tesla_ops = {
+	.start = NULL,
+	.stop = NULL,
+};
+
+static struct omap_rproc_platform_data omap4_rproc_data[] = {
+	{
+		.name = "tesla",
+		.ops = &omap4_tesla_ops,
+		.oh_name = "tesla_hwmod",
+	},
+	{
+		.name = "ducati-proc0",
+		.ops = &omap4_ducati0_ops,
+		.oh_name = "ducati_hwmod0",
+	},
+	{
+		.name = "ducati-proc1",
+		.ops = &omap4_ducati1_ops,
+		.oh_name = "ducati_hwmod1",
+	},
+};
+
+struct omap_rproc_platform_data *remoteproc_get_plat_data(void)
+{
+	return omap4_rproc_data;
+}
+
+int remoteproc_get_plat_data_size(void)
+{
+	return ARRAY_SIZE(omap4_rproc_data);
+}
+EXPORT_SYMBOL(remoteproc_get_plat_data_size);
+
+
+#define NR_RPROC_DEVICES ARRAY_SIZE(omap4_rproc_data)
+
+static struct platform_device *omap4_rproc_pdev[NR_RPROC_DEVICES];
+
+static int __init omap4_rproc_init(void)
+{
+	int i, err;
+
+	for (i = 0; i < NR_RPROC_DEVICES; i++) {
+		struct platform_device *pdev;
+
+		pdev = platform_device_alloc("omap-remoteproc", i);
+		if (!pdev) {
+			err = -ENOMEM;
+			goto err_out;
+		}
+
+		err = platform_device_add_data(pdev, &omap4_rproc_data[i],
+					       sizeof(omap4_rproc_data[0]));
+		err = platform_device_add(pdev);
+		if (err)
+			goto err_out;
+		omap4_rproc_pdev[i] = pdev;
+	}
+	return 0;
+
+err_out:
+	while (i--)
+		platform_device_put(omap4_rproc_pdev[i]);
+	return err;
+}
+module_init(omap4_rproc_init);
+
+static void __exit omap4_rproc_exit(void)
+{
+	int i;
+
+	for (i = 0; i < NR_RPROC_DEVICES; i++)
+		platform_device_unregister(omap4_rproc_pdev[i]);
+}
+module_exit(omap4_rproc_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("OMAP4 Remote Processor module");
+MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");
+MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>");
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index 7148e53e6078..8ebffdd6fcff 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -157,7 +157,7 @@ ENTRY(fa_flush_kern_dcache_area)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-fa_dma_inv_range:
+ENTRY(fa_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c14, 1		@ clean & invalidate D entry
@@ -180,7 +180,7 @@ fa_dma_inv_range:
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-fa_dma_clean_range:
+ENTRY(fa_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
@@ -241,5 +241,7 @@ ENTRY(fa_cache_fns)
 	.long	fa_flush_kern_dcache_area
 	.long	fa_dma_map_area
 	.long	fa_dma_unmap_area
+	.long	fa_dma_inv_range
+	.long	fa_dma_clean_range
 	.long	fa_dma_flush_range
 	.size	fa_cache_fns, . - fa_cache_fns
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index c2ff3c599fee..6df52dc014be 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -84,6 +84,20 @@ ENTRY(v3_flush_kern_dcache_area)
 	/* FALLTHROUGH */
 
 /*
+ *	dma_inv_range(start, end)
+ *
+ *	Invalidate (discard) the specified virtual address range.
+ *	May not write back any entries.  If 'start' or 'end'
+ *	are not cache line aligned, those lines must be written
+ *	back.
+ *
+ *	- start  - virtual start address
+ *	- end	 - virtual end address
+ */
+ENTRY(v3_dma_inv_range)
+	/* FALLTHROUGH */
+
+/*
  *	dma_flush_range(start, end)
  *
  *	Clean and invalidate the specified virtual address range.
@@ -94,6 +108,17 @@ ENTRY(v3_flush_kern_dcache_area)
 ENTRY(v3_dma_flush_range)
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c0, 0		@ flush ID cache
+	/* FALLTHROUGH */
+
+/*
+ *	dma_clean_range(start, end)
+ *
+ *	Clean (write back) the specified virtual address range.
+ *
+ *	- start  - virtual start address
+ *	- end	 - virtual end address
+ */
+ENTRY(v3_dma_clean_range)
 	mov	pc, lr
 
 /*
@@ -104,7 +129,7 @@ ENTRY(v3_dma_flush_range)
  */
 ENTRY(v3_dma_unmap_area)
 	teq	r2, #DMA_TO_DEVICE
-	bne	v3_dma_flush_range
+	bne	v3_dma_inv_range
 	/* FALLTHROUGH */
 
 /*
@@ -130,5 +155,7 @@ ENTRY(v3_cache_fns)
 	.long	v3_flush_kern_dcache_area
 	.long	v3_dma_map_area
 	.long	v3_dma_unmap_area
+	.long	v3_dma_inv_range
+	.long	v3_dma_clean_range
 	.long	v3_dma_flush_range
 	.size	v3_cache_fns, . - v3_cache_fns
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 4810f7e3e813..df3b423713b9 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -94,6 +94,20 @@ ENTRY(v4_flush_kern_dcache_area)
 	/* FALLTHROUGH */
 
 /*
+ *	dma_inv_range(start, end)
+ *
+ *	Invalidate (discard) the specified virtual address range.
+ *	May not write back any entries.  If 'start' or 'end'
+ *	are not cache line aligned, those lines must be written
+ *	back.
+ *
+ *	- start  - virtual start address
+ *	- end	 - virtual end address
+ */
+ENTRY(v4_dma_inv_range)
+	/* FALLTHROUGH */
+
+/*
  *	dma_flush_range(start, end)
  *
  *	Clean and invalidate the specified virtual address range.
@@ -106,6 +120,17 @@ ENTRY(v4_dma_flush_range)
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
 #endif
+	/* FALLTHROUGH */
+
+/*
+ *	dma_clean_range(start, end)
+ *
+ *	Clean (write back) the specified virtual address range.
+ *
+ *	- start  - virtual start address
+ *	- end	 - virtual end address
+ */
+ENTRY(v4_dma_clean_range)
 	mov	pc, lr
 
 /*
@@ -116,7 +141,7 @@ ENTRY(v4_dma_flush_range)
  */
 ENTRY(v4_dma_unmap_area)
 	teq	r2, #DMA_TO_DEVICE
-	bne	v4_dma_flush_range
+	bne	v4_dma_inv_range
 	/* FALLTHROUGH */
 
 /*
@@ -142,5 +167,7 @@ ENTRY(v4_cache_fns)
 	.long	v4_flush_kern_dcache_area
 	.long	v4_dma_map_area
 	.long	v4_dma_unmap_area
+	.long	v4_dma_inv_range
+	.long	v4_dma_clean_range
 	.long	v4_dma_flush_range
 	.size	v4_cache_fns, . - v4_cache_fns
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index df8368afa102..32e7a7448496 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -173,7 +173,7 @@ ENTRY(v4wb_coherent_user_range)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-v4wb_dma_inv_range:
+ENTRY(v4wb_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -194,7 +194,7 @@ v4wb_dma_inv_range:
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-v4wb_dma_clean_range:
+ENTRY(v4wb_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
@@ -252,5 +252,7 @@ ENTRY(v4wb_cache_fns)
 	.long	v4wb_flush_kern_dcache_area
 	.long	v4wb_dma_map_area
 	.long	v4wb_dma_unmap_area
+	.long	v4wb_dma_inv_range
+	.long	v4wb_dma_clean_range
 	.long	v4wb_dma_flush_range
 	.size	v4wb_cache_fns, . - v4wb_cache_fns
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 45c70312f43b..3d8dad5b2650 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -142,12 +142,23 @@ ENTRY(v4wt_flush_kern_dcache_area)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-v4wt_dma_inv_range:
+ENTRY(v4wt_dma_inv_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
 	add	r0, r0, #CACHE_DLINESIZE
 	cmp	r0, r1
 	blo	1b
+	/* FALLTHROUGH */
+
+/*
+ *	dma_clean_range(start, end)
+ *
+ *	Clean the specified virtual address range.
+ *
+ *	- start  - virtual start address
+ *	- end	 - virtual end address
+ */
+ENTRY(v4wt_dma_clean_range)
 	mov	pc, lr
 
 /*
@@ -196,5 +207,7 @@ ENTRY(v4wt_cache_fns)
 	.long	v4wt_flush_kern_dcache_area
 	.long	v4wt_dma_map_area
 	.long	v4wt_dma_unmap_area
+	.long	v4wt_dma_inv_range
+	.long	v4wt_dma_clean_range
 	.long	v4wt_dma_flush_range
 	.size	v4wt_cache_fns, . - v4wt_cache_fns
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index e46ecd847138..c58392d4ff5a 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -195,7 +195,7 @@ ENTRY(v6_flush_kern_dcache_area)
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v6_dma_inv_range:
+ENTRY(v6_dma_inv_range)
 	tst	r0, #D_CACHE_LINE_SIZE - 1
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
@@ -231,7 +231,7 @@ v6_dma_inv_range:
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v6_dma_clean_range:
+ENTRY(v6_dma_clean_range)
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
 #ifdef CONFIG_SMP
@@ -310,5 +310,7 @@ ENTRY(v6_cache_fns)
 	.long	v6_flush_kern_dcache_area
 	.long	v6_dma_map_area
 	.long	v6_dma_unmap_area
+	.long	v6_dma_inv_range
+	.long	v6_dma_clean_range
 	.long	v6_dma_flush_range
 	.size	v6_cache_fns, . - v6_cache_fns
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157e116e..884ac48a2010 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -224,7 +224,7 @@ ENDPROC(v7_flush_kern_dcache_area)
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v7_dma_inv_range:
+ENTRY(v7_dma_inv_range)
 	dcache_line_size r2, r3
 	sub	r3, r2, #1
 	tst	r0, r3
@@ -248,7 +248,7 @@ ENDPROC(v7_dma_inv_range)
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v7_dma_clean_range:
+ENTRY(v7_dma_clean_range)
 	dcache_line_size r2, r3
 	sub	r3, r2, #1
 	bic	r0, r0, r3
@@ -317,5 +317,7 @@ ENTRY(v7_cache_fns)
 	.long	v7_flush_kern_dcache_area
 	.long	v7_dma_map_area
 	.long	v7_dma_unmap_area
+	.long	v7_dma_inv_range
+	.long	v7_dma_clean_range
 	.long	v7_dma_flush_range
 	.size	v7_cache_fns, . - v7_cache_fns
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index bb9b6124a0d5..20a3e7fea2c4 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -622,3 +622,86 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 	}
 }
 EXPORT_SYMBOL(dma_sync_sg_for_device);
+
+#ifdef CONFIG_UNOFFICIAL_USER_DMA_API
+int temp_user_dma_op(unsigned long start, unsigned long end, int op)
+{
+	struct mm_struct *mm = current->active_mm;
+	void (*inner_op)(const void *, const void *);
+	void (*outer_op)(unsigned long, unsigned long);
+
+	if (!test_taint(TAINT_USER)) {
+		printk(KERN_WARNING "%s: using unofficial user DMA API, kernel tainted.\n",
+			current->comm);
+		add_taint(TAINT_USER);
+	}
+
+	switch (op) {
+	case 1:
+		inner_op = dmac_inv_range;
+		outer_op = outer_inv_range;
+		break;
+	case 2:
+		inner_op = dmac_clean_range;
+		outer_op = outer_clean_range;
+		break;
+	case 3:
+		inner_op = dmac_flush_range;
+		outer_op = outer_flush_range;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (end < start)
+		return -EINVAL;
+
+	down_read(&mm->mmap_sem);
+	do {
+		struct vm_area_struct *vma = find_vma(mm, start);
+
+		if (!vma || start < vma->vm_start ||
+		    vma->vm_flags & (VM_IO | VM_PFNMAP)) {
+			up_read(&mm->mmap_sem);
+			return -EFAULT;
+		}
+
+		do {
+			unsigned long e = (start | ~PAGE_MASK) + 1;
+			struct page *page;
+
+			if (e > end)
+				e = end;
+
+			page = follow_page(vma, start, FOLL_GET);
+			if (IS_ERR(page)) {
+				up_read(&mm->mmap_sem);
+				return PTR_ERR(page);
+			}
+
+			if (page) {
+				unsigned long phys;
+
+				/*
+				 * This flushes the userspace address - which
+				 * is not what this API was intended to do.
+				 * Things may go astray as a result.
+				 */
+				inner_op((void *)start, (void *)e);
+
+				/*
+				 * Now handle the L2 cache.
+				 */
+				phys = page_to_phys(page) + (start & ~PAGE_MASK);
+				outer_op(phys, phys + e - start);
+
+				put_page(page);
+			}
+			start = e;
+		} while (start < end && start < vma->vm_end);
+	} while (start < end);
+	up_read(&mm->mmap_sem);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 28c8b950ef04..d5a38801cc08 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -349,6 +349,109 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
+#define MAX_SECTIONS 4
+void __iomem *
+__arm_multi_strided_ioremap(int sections,
+			    unsigned long *phys_addr, size_t *phys_size,
+			    unsigned long *phys_stride,
+			    unsigned long *virt_stride,
+			    unsigned int mtype)
+{
+	unsigned long pfns[MAX_SECTIONS];
+	const struct mem_type *type;
+	unsigned long total_size = 0, j;
+	int err = 0, i;
+	unsigned long addr, addr_i, pstride, vstride;
+	struct vm_struct * area;
+
+	if (sections > MAX_SECTIONS)
+		return NULL;
+
+	for (i = 0; i < sections; i++) {
+		/* both physical and virtual strides must be both specified
+		   or neither specified */
+		pstride = ((phys_stride && phys_stride[i]) ?
+			   phys_stride[i] : phys_size[i]);
+		vstride = ((virt_stride && virt_stride[i]) ?
+			   virt_stride[i] : phys_size[i]);
+
+		if (!pstride ^ !vstride)
+			return NULL;
+
+		/*
+		* Don't allow wraparound or zero size.  Also, sections
+		* must end/begin on page boundary, and strides be page
+		* aligned
+		*
+		* For now, size must be multiple of physical stride.  This
+		* may be relaxed to contain only full virtual strides.  (E.g.
+		* not have to contain the waste after the last virtual block.)
+		*
+		*/
+		if (((phys_addr[i] | phys_size[i] |
+		      vstride | pstride) & ~PAGE_MASK) ||
+		    !phys_size[i] ||
+		    vstride > pstride ||
+		    (pstride && (phys_size[i] % pstride)) ||
+		    (phys_addr[i] + phys_size[i] - 1 < phys_addr[i]))
+			return NULL;
+
+		pfns[i] = __phys_to_pfn(phys_addr[i]);
+
+		/*
+		 * High mappings must be supersection aligned
+		 */
+		if (pfns[i] >= 0x100000 &&
+		    (__pfn_to_phys(pfns[i]) & ~SUPERSECTION_MASK))
+			return NULL;
+
+		total_size += phys_size[i] / pstride * vstride;
+	}
+
+	type = get_mem_type(mtype);
+	if (!type)
+		return NULL;
+
+	area = get_vm_area(total_size, VM_IOREMAP);
+	if (!area)
+		return NULL;
+	addr = addr_i = (unsigned long)area->addr;
+
+	for (i = 0; i < sections && !err; i++) {
+		printk(KERN_ERR "mapping %lx to %lx (%x)\n", __pfn_to_phys(pfns[i]), addr_i, phys_size[i]);
+		pstride = ((phys_stride && phys_stride[i]) ?
+			   phys_stride[i] : phys_size[i]);
+		vstride = ((virt_stride && virt_stride[i]) ?
+			   virt_stride[i] : phys_size[i]);
+		for (j = 0; j < phys_size[i]; j += pstride) {
+	#ifndef CONFIG_SMP
+			if (DOMAIN_IO == 0 &&
+			    (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) ||
+			       cpu_is_xsc3()) && pfns[i] >= 0x100000 &&
+			       !((__pfn_to_phys(pfns[i]) | vstride | addr_i) & ~SUPERSECTION_MASK)) {
+				area->flags |= VM_ARM_SECTION_MAPPING;
+				err = remap_area_supersections(addr_i, pfns[i], size[i], type);
+			} else if (!((__pfn_to_phys(pfns[i]) | vstride | addr_i) & ~PMD_MASK)) {
+				area->flags |= VM_ARM_SECTION_MAPPING;
+				err = remap_area_sections(addr_i, pfns[i], vstride, type);
+			} else
+	#endif
+				err = remap_area_pages(addr_i, pfns[i], vstride, type);
+			pfns[i] += __phys_to_pfn(pstride);
+			addr_i += vstride;
+		}
+	}
+
+	if (err) {
+		vunmap((void *)addr);
+		return NULL;
+	}
+
+	flush_cache_vmap(addr, addr + total_size);
+	return (void __iomem *) addr;
+}
+EXPORT_SYMBOL(__arm_multi_strided_ioremap);
+
 void __iounmap(volatile void __iomem *io_addr)
 {
 	void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 72507c630ceb..c85f5eb42634 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -265,7 +265,7 @@ ENTRY(arm1020_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm1020_dma_inv_range:
+ENTRY(arm1020_dma_inv_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	tst	r0, #CACHE_DLINESIZE - 1
@@ -295,7 +295,7 @@ arm1020_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm1020_dma_clean_range:
+ENTRY(arm1020_dma_clean_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CACHE_DLINESIZE - 1
@@ -363,6 +363,8 @@ ENTRY(arm1020_cache_fns)
 	.long	arm1020_flush_kern_dcache_area
 	.long	arm1020_dma_map_area
 	.long	arm1020_dma_unmap_area
+	.long	arm1020_dma_inv_range
+	.long	arm1020_dma_clean_range
 	.long	arm1020_dma_flush_range
 
 	.align	5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index d27829805609..5a3cf7620a2c 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -258,7 +258,7 @@ ENTRY(arm1020e_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm1020e_dma_inv_range:
+ENTRY(arm1020e_dma_inv_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	tst	r0, #CACHE_DLINESIZE - 1
@@ -284,7 +284,7 @@ arm1020e_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm1020e_dma_clean_range:
+ENTRY(arm1020e_dma_clean_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CACHE_DLINESIZE - 1
@@ -349,6 +349,8 @@ ENTRY(arm1020e_cache_fns)
 	.long	arm1020e_flush_kern_dcache_area
 	.long	arm1020e_dma_map_area
 	.long	arm1020e_dma_unmap_area
+	.long	arm1020e_dma_inv_range
+	.long	arm1020e_dma_clean_range
 	.long	arm1020e_dma_flush_range
 
 	.align	5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index ce13e4a827de..fec8f5878438 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -247,7 +247,7 @@ ENTRY(arm1022_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm1022_dma_inv_range:
+ENTRY(arm1022_dma_inv_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	tst	r0, #CACHE_DLINESIZE - 1
@@ -273,7 +273,7 @@ arm1022_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm1022_dma_clean_range:
+ENTRY(arm1022_dma_clean_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CACHE_DLINESIZE - 1
@@ -338,6 +338,8 @@ ENTRY(arm1022_cache_fns)
 	.long	arm1022_flush_kern_dcache_area
 	.long	arm1022_dma_map_area
 	.long	arm1022_dma_unmap_area
+	.long	arm1022_dma_inv_range
+	.long	arm1022_dma_clean_range
 	.long	arm1022_dma_flush_range
 
 	.align	5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 636672a29c6d..9ece6f666497 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -241,7 +241,7 @@ ENTRY(arm1026_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm1026_dma_inv_range:
+ENTRY(arm1026_dma_inv_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	tst	r0, #CACHE_DLINESIZE - 1
@@ -267,7 +267,7 @@ arm1026_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm1026_dma_clean_range:
+ENTRY(arm1026_dma_clean_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CACHE_DLINESIZE - 1
@@ -332,6 +332,8 @@ ENTRY(arm1026_cache_fns)
 	.long	arm1026_flush_kern_dcache_area
 	.long	arm1026_dma_map_area
 	.long	arm1026_dma_unmap_area
+	.long	arm1026_dma_inv_range
+	.long	arm1026_dma_clean_range
 	.long	arm1026_dma_flush_range
 
 	.align	5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 8be81992645d..6f6ab2747da6 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -239,7 +239,7 @@ ENTRY(arm920_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm920_dma_inv_range:
+ENTRY(arm920_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -262,7 +262,7 @@ arm920_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm920_dma_clean_range:
+ENTRY(arm920_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
@@ -321,6 +321,8 @@ ENTRY(arm920_cache_fns)
 	.long	arm920_flush_kern_dcache_area
 	.long	arm920_dma_map_area
 	.long	arm920_dma_unmap_area
+	.long	arm920_dma_inv_range
+	.long	arm920_dma_clean_range
 	.long	arm920_dma_flush_range
 
 #endif
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index c0ff8e4b1074..4e4396b121ca 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -241,7 +241,7 @@ ENTRY(arm922_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm922_dma_inv_range:
+ENTRY(arm922_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -264,7 +264,7 @@ arm922_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm922_dma_clean_range:
+ENTRY(arm922_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
@@ -323,6 +323,8 @@ ENTRY(arm922_cache_fns)
 	.long	arm922_flush_kern_dcache_area
 	.long	arm922_dma_map_area
 	.long	arm922_dma_unmap_area
+	.long	arm922_dma_inv_range
+	.long	arm922_dma_clean_range
 	.long	arm922_dma_flush_range
 
 #endif
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 3c6cffe400f6..7c01c5d1108c 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -283,7 +283,7 @@ ENTRY(arm925_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm925_dma_inv_range:
+ENTRY(arm925_dma_inv_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -308,7 +308,7 @@ arm925_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm925_dma_clean_range:
+ENTRY(arm925_dma_clean_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -374,6 +374,8 @@ ENTRY(arm925_cache_fns)
 	.long	arm925_flush_kern_dcache_area
 	.long	arm925_dma_map_area
 	.long	arm925_dma_unmap_area
+	.long	arm925_dma_inv_range
+	.long	arm925_dma_clean_range
 	.long	arm925_dma_flush_range
 
 ENTRY(cpu_arm925_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 75b707c9cce1..72a01a4b80ab 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -246,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm926_dma_inv_range:
+ENTRY(arm926_dma_inv_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -271,7 +271,7 @@ arm926_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm926_dma_clean_range:
+ENTRY(arm926_dma_clean_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -337,6 +337,8 @@ ENTRY(arm926_cache_fns)
 	.long	arm926_flush_kern_dcache_area
 	.long	arm926_dma_map_area
 	.long	arm926_dma_unmap_area
+	.long	arm926_dma_inv_range
+	.long	arm926_dma_clean_range
 	.long	arm926_dma_flush_range
 
 ENTRY(cpu_arm926_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 1af1657819eb..6bb58fca7270 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -171,7 +171,7 @@ ENTRY(arm940_flush_kern_dcache_area)
  *	- start	- virtual start address
  *	- end	- virtual end address
  */
-arm940_dma_inv_range:
+ENTRY(arm940_dma_inv_range)
 	mov	ip, #0
 	mov	r1, #(CACHE_DSEGMENTS - 1) << 4	@ 4 segments
 1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -192,7 +192,7 @@ arm940_dma_inv_range:
  *	- start	- virtual start address
  *	- end	- virtual end address
  */
-arm940_dma_clean_range:
+ENTRY(arm940_dma_clean_range)
 ENTRY(cpu_arm940_dcache_clean_area)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -266,6 +266,8 @@ ENTRY(arm940_cache_fns)
 	.long	arm940_flush_kern_dcache_area
 	.long	arm940_dma_map_area
 	.long	arm940_dma_unmap_area
+	.long	arm940_dma_inv_range
+	.long	arm940_dma_clean_range
 	.long	arm940_dma_flush_range
 
 	__INIT
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 1664b6aaff79..ac0f9ba719d7 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -215,7 +215,7 @@ ENTRY(arm946_flush_kern_dcache_area)
  *	- end	- virtual end address
  * (same as arm926)
  */
-arm946_dma_inv_range:
+ENTRY(arm946_dma_inv_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -240,7 +240,7 @@ arm946_dma_inv_range:
  *
  * (same as arm926)
  */
-arm946_dma_clean_range:
+ENTRY(arm946_dma_clean_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -308,6 +308,8 @@ ENTRY(arm946_cache_fns)
 	.long	arm946_flush_kern_dcache_area
 	.long	arm946_dma_map_area
 	.long	arm946_dma_unmap_area
+	.long	arm946_dma_inv_range
+	.long	arm946_dma_clean_range
 	.long	arm946_dma_flush_range
 
 
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 53e632343849..97e1d784f152 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -274,7 +274,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area)
  * (same as v4wb)
  */
 	.align	5
-feroceon_dma_inv_range:
+ENTRY(feroceon_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -288,7 +288,7 @@ feroceon_dma_inv_range:
 	mov	pc, lr
 
 	.align	5
-feroceon_range_dma_inv_range:
+ENTRY(feroceon_range_dma_inv_range)
 	mrs	r2, cpsr
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -314,7 +314,7 @@ feroceon_range_dma_inv_range:
  * (same as v4wb)
  */
 	.align	5
-feroceon_dma_clean_range:
+ENTRY(feroceon_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
@@ -324,7 +324,7 @@ feroceon_dma_clean_range:
 	mov	pc, lr
 
 	.align	5
-feroceon_range_dma_clean_range:
+ENTRY(feroceon_range_dma_clean_range)
 	mrs	r2, cpsr
 	cmp	r1, r0
 	subne	r1, r1, #1			@ top address is inclusive
@@ -414,6 +414,8 @@ ENTRY(feroceon_cache_fns)
 	.long	feroceon_flush_kern_dcache_area
 	.long	feroceon_dma_map_area
 	.long	feroceon_dma_unmap_area
+	.long	feroceon_dma_inv_range
+	.long	feroceon_dma_clean_range
 	.long	feroceon_dma_flush_range
 
 ENTRY(feroceon_range_cache_fns)
@@ -425,6 +427,8 @@ ENTRY(feroceon_range_cache_fns)
 	.long	feroceon_range_flush_kern_dcache_area
 	.long	feroceon_range_dma_map_area
 	.long	feroceon_dma_unmap_area
+	.long	feroceon_range_dma_inv_range
+	.long	feroceon_range_dma_clean_range
 	.long	feroceon_range_dma_flush_range
 
 	.align	5
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index caa31154e7db..55b7fbec6548 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -218,7 +218,7 @@ ENTRY(mohawk_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-mohawk_dma_inv_range:
+ENTRY(mohawk_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
 	tst	r1, #CACHE_DLINESIZE - 1
@@ -241,7 +241,7 @@ mohawk_dma_inv_range:
  *
  * (same as v4wb)
  */
-mohawk_dma_clean_range:
+ENTRY(mohawk_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
@@ -301,6 +301,8 @@ ENTRY(mohawk_cache_fns)
 	.long	mohawk_flush_kern_dcache_area
 	.long	mohawk_dma_map_area
 	.long	mohawk_dma_unmap_area
+	.long	mohawk_dma_inv_range
+	.long	mohawk_dma_clean_range
 	.long	mohawk_dma_flush_range
 
 ENTRY(cpu_mohawk_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index e5797f1c1db7..32231a0e917e 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -257,7 +257,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-xsc3_dma_inv_range:
+ENTRY(xsc3_dma_inv_range)
 	tst	r0, #CACHELINESIZE - 1
 	bic	r0, r0, #CACHELINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean L1 D line
@@ -278,7 +278,7 @@ xsc3_dma_inv_range:
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-xsc3_dma_clean_range:
+ENTRY(xsc3_dma_clean_range)
 	bic	r0, r0, #CACHELINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
 	add	r0, r0, #CACHELINESIZE
@@ -337,6 +337,8 @@ ENTRY(xsc3_cache_fns)
 	.long	xsc3_flush_kern_dcache_area
 	.long	xsc3_dma_map_area
 	.long	xsc3_dma_unmap_area
+	.long	xsc3_dma_inv_range
+	.long	xsc3_dma_clean_range
 	.long	xsc3_dma_flush_range
 
 ENTRY(cpu_xsc3_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 63037e2162f2..a7999f94bf27 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -315,7 +315,7 @@ ENTRY(xscale_flush_kern_dcache_area)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-xscale_dma_inv_range:
+ENTRY(xscale_dma_inv_range)
 	tst	r0, #CACHELINESIZE - 1
 	bic	r0, r0, #CACHELINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -336,7 +336,7 @@ xscale_dma_inv_range:
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-xscale_dma_clean_range:
+ENTRY(xscale_dma_clean_range)
 	bic	r0, r0, #CACHELINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHELINESIZE
@@ -409,6 +409,8 @@ ENTRY(xscale_cache_fns)
 	.long	xscale_flush_kern_dcache_area
 	.long	xscale_dma_map_area
 	.long	xscale_dma_unmap_area
+	.long	xscale_dma_inv_range
+	.long	xscale_dma_clean_range
 	.long	xscale_dma_flush_range
 
 /*
@@ -434,6 +436,8 @@ ENTRY(xscale_80200_A0_A1_cache_fns)
 	.long	xscale_dma_a0_map_area
 	.long	xscale_dma_unmap_area
 	.long	xscale_dma_flush_range
+	.long	xscale_dma_clean_range
+	.long	xscale_dma_flush_range
 
 ENTRY(cpu_xscale_dcache_clean_area)
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 33256d8a9003..a5a473a88050 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -147,6 +147,21 @@ config OMAP_MBOX_FWK
 	  Say Y here if you want to use OMAP Mailbox framework support for
 	  DSP, IVA1.0 and IVA2 in OMAP1/2/3.
 
+config OMAP_REMOTE_PROC
+	bool "Remote Processor framework support"
+	depends on ARCH_OMAP
+	help
+	  Say Y here if you want to use OMAP Remote Processor framework
+	  support for DSP, IVA, Tesla and Ducati (OMAP2/3/4).
+
+config OMAP_RPROC_MEMPOOL_SIZE
+	hex "Physical memory pool size for remote processor (in bytes)"
+	depends on OMAP_REMOTE_PROC
+	default 0x600000
+	help
+	  Allocate specified size of memory at booting time to avoid allocation
+	  failure under heavy memory fragmentation after some use time.
+
 config OMAP_IOMMU
 	tristate
 
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 87e5124fe556..34c6b46f5fb4 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
-	 usb.o fb.o io.o timer-32k-sync.o
+	 usb.o fb.o io.o hdmi_lib.o timer-32k-sync.o
 obj-m :=
 obj-n :=
 obj-  :=
@@ -36,5 +36,6 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
 
 # OMAP mailbox framework
 obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
+obj-$(CONFIG_OMAP_REMOTE_PROC) += remoteproc.o
 
 obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 701e4ea4d0e9..104eaecc2278 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -336,6 +336,7 @@ struct clk *omap_clk_get_by_name(const char *name)
 
 	return ret;
 }
+EXPORT_SYMBOL(omap_clk_get_by_name);
 
 /*
  * Low level helpers
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 1dc7a3986e5b..a8446b4ae152 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -15,6 +15,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -28,8 +30,11 @@
 #include <mach/gpio.h>
 #include <plat/menelaus.h>
 #include <plat/mcbsp.h>
+#include <plat/mcpdm.h>
 #include <plat/dsp_common.h>
 #include <plat/omap44xx.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
 
 #if	defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 
@@ -194,34 +199,41 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
-		defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
+#if defined(CONFIG_OMAP_MCPDM) || defined(CONFIG_OMAP_MCPDM_MODULE)
 
-static struct resource mcpdm_resources[] = {
+static struct omap_device_pm_latency omap_mcpdm_latency[] = {
 	{
-		.name		= "mcpdm_mem",
-		.start		= OMAP44XX_MCPDM_BASE,
-		.end		= OMAP44XX_MCPDM_BASE + SZ_4K,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.name		= "mcpdm_irq",
-		.start		= OMAP44XX_IRQ_MCPDM,
-		.end		= OMAP44XX_IRQ_MCPDM,
-		.flags		= IORESOURCE_IRQ,
+		.deactivate_func = omap_device_idle_hwmods,
+		.activate_func = omap_device_enable_hwmods,
+		.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
 	},
 };
 
-static struct platform_device omap_mcpdm_device = {
-	.name		= "omap-mcpdm",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(mcpdm_resources),
-	.resource	= mcpdm_resources,
-};
-
 static void omap_init_mcpdm(void)
 {
-	(void) platform_device_register(&omap_mcpdm_device);
+	struct omap_hwmod *oh;
+	struct omap_device *od;
+	struct omap_mcpdm_platform_data *pdata;
+
+	oh = omap_hwmod_lookup("mcpdm");
+	if (!oh)
+		printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+
+	pdata = kzalloc(sizeof(struct omap_mcpdm_platform_data), GFP_KERNEL);
+	if (!pdata)
+		printk(KERN_ERR "Could not allocate platform data\n");
+
+	pdata->device_enable = omap_device_enable;
+	pdata->device_idle = omap_device_idle;
+	pdata->device_shutdown = omap_device_shutdown;
+
+	od = omap_device_build("omap-mcpdm", -1, oh, pdata,
+				sizeof(struct omap_mcpdm_platform_data),
+				omap_mcpdm_latency,
+				ARRAY_SIZE(omap_mcpdm_latency), 0);
+
+	if (od <= 0)
+		printk(KERN_ERR "Could not build omap_device for omap-mcpdm\n");
 }
 #else
 static inline void omap_init_mcpdm(void) {}
@@ -229,6 +241,45 @@ static inline void omap_init_mcpdm(void) {}
 
 /*-------------------------------------------------------------------------*/
 
+#if defined(SND_SOC_ABE_TWL6040)
+
+static struct omap_device_pm_latency omap_aess_latency[] = {
+	{
+		.deactivate_func = omap_device_idle_hwmods,
+		.activate_func = omap_device_enable_hwmods,
+		.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+	},
+};
+
+static void omap_init_aess(void)
+{
+	struct omap_hwmod *oh;
+	struct omap_device *od;
+	struct twl6040_code_data *pdata;
+
+	oh = omap_hwmod_lookup("aess");
+	if (!oh)
+		printk (KERN_ERR "Could not look up aess hw_mod\n");
+
+
+	pdata->device_enable = omap_device_enable;
+	pdata->device_idle = omap_device_idle;
+	pdata->device_shutdown = omap_device_shutdown;
+
+	od = omap_device_build("omap-aess", -1, oh, pdata,
+				sizeof(struct omap_aess_platform_data),
+				omap_aess_latency,
+				ARRAY_SIZE(omap_aess_latency), 0);
+
+	if (od <= 0)
+		printk(KERN_ERR "Could not build omap_device for omap-aess\n");
+}
+#else
+static inline void omap_init_aess(void) {}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
 #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
 
 #ifdef CONFIG_ARCH_OMAP2
diff --git a/arch/arm/plat-omap/hdmi_lib.c b/arch/arm/plat-omap/hdmi_lib.c
new file mode 100644
index 000000000000..efc409a35534
--- /dev/null
+++ b/arch/arm/plat-omap/hdmi_lib.c
@@ -0,0 +1,1482 @@
+/*
+ * hdmi_lib.c
+ *
+ * HDMI library support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2010 Texas Instruments
+ * Author: Yong Zhi <y-zhi@ti.com>
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/* Rev history:
+ * Yong Zhi <y-zhi@ti.com>	changed SiVal macros
+ * 				added PLL/PHY code
+ *				added EDID code
+ * 				moved PLL/PHY code to hdmi panel driver
+ * 				cleanup 2/08/10
+ * MythriPk <mythripk@ti.com>	Apr 2010 Modified to read extended EDID partition
+ *				and handle checksum with and without extension
+ *				May 2010 Added support for Hot Plug Detect.
+ *
+ */
+
+#define DSS_SUBSYS_NAME "HDMI"
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+#include <plat/hdmi_lib.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+
+/* HDMI PHY */
+#define HDMI_TXPHY_TX_CTRL						0x0ul
+#define HDMI_TXPHY_DIGITAL_CTRL					0x4ul
+#define HDMI_TXPHY_POWER_CTRL					0x8ul
+
+/* HDMI Wrapper */
+#define HDMI_WP_REVISION						0x0ul
+#define HDMI_WP_SYSCONFIG						0x10ul
+#define HDMI_WP_IRQSTATUS_RAW					0x24ul
+#define HDMI_WP_IRQSTATUS						0x28ul
+#define HDMI_WP_PWR_CTRL						0x40ul
+#define HDMI_WP_IRQENABLE_SET					0x2Cul
+#define HDMI_WP_VIDEO_CFG						0x50ul
+#define HDMI_WP_VIDEO_SIZE						0x60ul
+#define HDMI_WP_VIDEO_TIMING_H					0x68ul
+#define HDMI_WP_VIDEO_TIMING_V					0x6Cul
+#define HDMI_WP_WP_CLK								0x70ul
+
+/* HDMI IP Core System */
+#define HDMI_CORE_SYS__VND_IDL					0x0ul
+#define HDMI_CORE_SYS__DEV_IDL					0x8ul
+#define HDMI_CORE_SYS__DEV_IDH					0xCul
+#define HDMI_CORE_SYS__DEV_REV					0x10ul
+#define HDMI_CORE_SYS__SRST						0x14ul
+#define HDMI_CORE_CTRL1							0x20ul
+#define HDMI_CORE_SYS__SYS_STAT					0x24ul
+#define HDMI_CORE_SYS__VID_ACEN					0x124ul
+#define HDMI_CORE_SYS__VID_MODE					0x128ul
+#define HDMI_CORE_SYS__INTR_STATE				0x1C0ul
+#define HDMI_CORE_SYS__INTR1					0x1C4ul
+#define HDMI_CORE_SYS__INTR2					0x1C8ul
+#define HDMI_CORE_SYS__INTR3					0x1CCul
+#define HDMI_CORE_SYS__INTR4					0x1D0ul
+#define HDMI_CORE_SYS__UMASK1					0x1D4ul
+#define HDMI_CORE_SYS__TMDS_CTRL				0x208ul
+#define HDMI_CORE_CTRL1_VEN__FOLLOWVSYNC		0x1ul
+#define HDMI_CORE_CTRL1_HEN__FOLLOWHSYNC		0x1ul
+#define HDMI_CORE_CTRL1_BSEL__24BITBUS			0x1ul
+#define HDMI_CORE_CTRL1_EDGE__RISINGEDGE		0x1ul
+
+#define HDMI_CORE_SYS__DE_DLY				0xC8ul
+#define HDMI_CORE_SYS__DE_CTRL				0xCCul
+#define HDMI_CORE_SYS__DE_TOP				0xD0ul
+#define HDMI_CORE_SYS__DE_CNTL				0xD8ul
+#define HDMI_CORE_SYS__DE_CNTH				0xDCul
+#define HDMI_CORE_SYS__DE_LINL				0xE0ul
+#define HDMI_CORE_SYS__DE_LINH__1			0xE4ul
+
+/* HDMI IP Core Audio Video */
+#define HDMI_CORE_AV_HDMI_CTRL				0xBCul
+#define HDMI_CORE_AV_DPD					0xF4ul
+#define HDMI_CORE_AV_PB_CTRL1				0xF8ul
+#define HDMI_CORE_AV_PB_CTRL2				0xFCul
+#define HDMI_CORE_AV_AVI_TYPE				0x100ul
+#define HDMI_CORE_AV_AVI_VERS				0x104ul
+#define HDMI_CORE_AV_AVI_LEN				0x108ul
+#define HDMI_CORE_AV_AVI_CHSUM				0x10Cul
+#define HDMI_CORE_AV_AVI_DBYTE				0x110ul
+#define HDMI_CORE_AV_AVI_DBYTE__ELSIZE		0x4ul
+
+/* HDMI DDC E-DID */
+#define HDMI_CORE_DDC_CMD				0x3CCul
+#define HDMI_CORE_DDC_STATUS			0x3C8ul
+#define HDMI_CORE_DDC_ADDR				0x3B4ul
+#define HDMI_CORE_DDC_OFFSET			0x3BCul
+#define HDMI_CORE_DDC_COUNT1			0x3C0ul
+#define HDMI_CORE_DDC_COUNT2			0x3C4ul
+#define HDMI_CORE_DDC_DATA				0x3D0ul
+#define HDMI_CORE_DDC_SEGM				0x3B8ul
+
+#define HDMI_WP_AUDIO_CFG                         0x80ul
+#define HDMI_WP_AUDIO_CFG2                        0x84ul
+#define HDMI_WP_AUDIO_CTRL                        0x88ul
+#define HDMI_WP_AUDIO_DATA                        0x8Cul
+
+#define HDMI_CORE_AV__AVI_DBYTE                0x110ul
+#define HDMI_CORE_AV__AVI_DBYTE__ELSIZE        0x4ul
+#define HDMI_IP_CORE_AV__AVI_DBYTE__NELEMS        15
+#define HDMI_CORE_AV__SPD_DBYTE                0x190ul
+#define HDMI_CORE_AV__SPD_DBYTE__ELSIZE        0x4ul
+#define HDMI_CORE_AV__SPD_DBYTE__NELEMS        27
+#define HDMI_CORE_AV__AUDIO_DBYTE              0x210ul
+#define HDMI_CORE_AV__AUDIO_DBYTE__ELSIZE      0x4ul
+#define HDMI_CORE_AV__AUDIO_DBYTE__NELEMS      10
+#define HDMI_CORE_AV__MPEG_DBYTE               0x290ul
+#define HDMI_CORE_AV__MPEG_DBYTE__ELSIZE       0x4ul
+#define HDMI_CORE_AV__MPEG_DBYTE__NELEMS       27
+#define HDMI_CORE_AV__GEN_DBYTE                0x300ul
+#define HDMI_CORE_AV__GEN_DBYTE__ELSIZE        0x4ul
+#define HDMI_CORE_AV__GEN_DBYTE__NELEMS        31
+#define HDMI_CORE_AV__GEN2_DBYTE               0x380ul
+#define HDMI_CORE_AV__GEN2_DBYTE__ELSIZE       0x4ul
+#define HDMI_CORE_AV__GEN2_DBYTE__NELEMS       31
+#define HDMI_CORE_AV__ACR_CTRL                 0x4ul
+#define HDMI_CORE_AV__FREQ_SVAL                0x8ul
+#define HDMI_CORE_AV__N_SVAL1                  0xCul
+#define HDMI_CORE_AV__N_SVAL2                  0x10ul
+#define HDMI_CORE_AV__N_SVAL3                  0x14ul
+#define HDMI_CORE_AV__CTS_SVAL1                0x18ul
+#define HDMI_CORE_AV__CTS_SVAL2                0x1Cul
+#define HDMI_CORE_AV__CTS_SVAL3                0x20ul
+#define HDMI_CORE_AV__CTS_HVAL1                0x24ul
+#define HDMI_CORE_AV__CTS_HVAL2                0x28ul
+#define HDMI_CORE_AV__CTS_HVAL3                0x2Cul
+#define HDMI_CORE_AV__AUD_MODE                 0x50ul
+#define HDMI_CORE_AV__SPDIF_CTRL               0x54ul
+#define HDMI_CORE_AV__HW_SPDIF_FS              0x60ul
+#define HDMI_CORE_AV__SWAP_I2S                 0x64ul
+#define HDMI_CORE_AV__SPDIF_ERTH               0x6Cul
+#define HDMI_CORE_AV__I2S_IN_MAP               0x70ul
+#define HDMI_CORE_AV__I2S_IN_CTRL              0x74ul
+#define HDMI_CORE_AV__I2S_CHST0                0x78ul
+#define HDMI_CORE_AV__I2S_CHST1                0x7Cul
+#define HDMI_CORE_AV__I2S_CHST2                0x80ul
+#define HDMI_CORE_AV__I2S_CHST4                0x84ul
+#define HDMI_CORE_AV__I2S_CHST5                0x88ul
+#define HDMI_CORE_AV__ASRC                     0x8Cul
+#define HDMI_CORE_AV__I2S_IN_LEN               0x90ul
+#define HDMI_CORE_AV__HDMI_CTRL                0xBCul
+#define HDMI_CORE_AV__AUDO_TXSTAT              0xC0ul
+#define HDMI_CORE_AV__AUD_PAR_BUSCLK_1         0xCCul
+#define HDMI_CORE_AV__AUD_PAR_BUSCLK_2         0xD0ul
+#define HDMI_CORE_AV__AUD_PAR_BUSCLK_3         0xD4ul
+#define HDMI_CORE_AV__TEST_TXCTRL              0xF0ul
+#define HDMI_CORE_AV__DPD                      0xF4ul
+#define HDMI_CORE_AV__PB_CTRL1                 0xF8ul
+#define HDMI_CORE_AV__PB_CTRL2                 0xFCul
+#define HDMI_CORE_AV__AVI_TYPE                 0x100ul
+#define HDMI_CORE_AV__AVI_VERS                 0x104ul
+#define HDMI_CORE_AV__AVI_LEN                  0x108ul
+#define HDMI_CORE_AV__AVI_CHSUM                0x10Cul
+#define HDMI_CORE_AV__SPD_TYPE                 0x180ul
+#define HDMI_CORE_AV__SPD_VERS                 0x184ul
+#define HDMI_CORE_AV__SPD_LEN                  0x188ul
+#define HDMI_CORE_AV__SPD_CHSUM                0x18Cul
+#define HDMI_CORE_AV__AUDIO_TYPE               0x200ul
+#define HDMI_CORE_AV__AUDIO_VERS               0x204ul
+#define HDMI_CORE_AV__AUDIO_LEN                0x208ul
+#define HDMI_CORE_AV__AUDIO_CHSUM              0x20Cul
+#define HDMI_CORE_AV__MPEG_TYPE                0x280ul
+#define HDMI_CORE_AV__MPEG_VERS                0x284ul
+#define HDMI_CORE_AV__MPEG_LEN                 0x288ul
+#define HDMI_CORE_AV__MPEG_CHSUM               0x28Cul
+#define HDMI_CORE_AV__CP_BYTE1                 0x37Cul
+#define HDMI_CORE_AV__CEC_ADDR_ID              0x3FCul
+
+
+static struct {
+	void __iomem *base_core;     /*0*/
+	void __iomem *base_core_av;  /*1*/
+	void __iomem *base_wp;       /*2*/
+	struct mutex hdmi_lock;
+} hdmi;
+
+int count = 0, count_hpd = 0;
+
+static inline void hdmi_write_reg(u32 base, u16 idx, u32 val)
+{
+	void __iomem *b;
+
+	switch (base) {
+	case HDMI_CORE_SYS:
+	  b = hdmi.base_core;
+	  break;
+	case HDMI_CORE_AV:
+	  b = hdmi.base_core_av;
+	  break;
+	case HDMI_WP:
+	  b = hdmi.base_wp;
+	  break;
+	default:
+	  BUG();
+	}
+	__raw_writel(val, b + idx);
+	/* DBG("write = 0x%x idx =0x%x\r\n", val, idx); */
+}
+
+static inline u32 hdmi_read_reg(u32 base, u16 idx)
+{
+	void __iomem *b;
+	u32 l;
+
+	switch (base) {
+	case HDMI_CORE_SYS:
+	 b = hdmi.base_core;
+	 break;
+	case HDMI_CORE_AV:
+	 b = hdmi.base_core_av;
+	 break;
+	case HDMI_WP:
+	 b = hdmi.base_wp;
+	 break;
+	default:
+	 BUG();
+	}
+	l = __raw_readl(b + idx);
+
+	/* DBG("addr = 0x%p rd = 0x%x idx = 0x%x\r\n", (b+idx), l, idx); */
+	return l;
+}
+
+#define FLD_MASK(start, end)	(((1 << (start - end + 1)) - 1) << (end))
+#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end))
+#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
+#define FLD_MOD(orig, val, start, end) \
+	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
+
+#define REG_FLD_MOD(base, idx, val, start, end) \
+	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx), val, start, end))
+
+#define RD_REG_32(COMP, REG)            hdmi_read_reg(COMP, REG)
+#define WR_REG_32(COMP, REG, VAL)       hdmi_write_reg(COMP, REG, (u32)(VAL))
+
+u8 edid_backup[256];
+
+
+int hdmi_get_image_format(void)
+{
+	int offset = 0x4, i, current_byte, length, flag = 0, j = 0;
+	if (edid_backup[0x7e] != 0x00) {
+		printk(KERN_INFO"Extension block present");
+		offset = edid_backup[(0x80) + 2];
+		if (offset != 0x4) {
+			i = 0x80 + 4;
+			while (i < (0x80 + offset)) {
+				current_byte = edid_backup[i];
+				if ((current_byte >> 5) == 0x2) {
+					length = current_byte & 0x1F;
+					for (j = 1 ; j < length ; j++) {
+						current_byte = edid_backup[i+j];
+						printk(KERN_INFO"Image format supported is %d", current_byte & 0x7F);
+
+					}
+				flag = 1;
+				break;
+
+				} else {
+					length = (current_byte & 0x1F) + 1;
+					i += length;
+				}
+			}
+		}
+
+	} else if (edid_backup[0x7e] != 0x00 && flag == 0) {
+		printk(KERN_INFO "Video Information Data Not found");
+	} else {
+		printk(KERN_INFO "TV does not have Extension Block");
+	}
+	return 0 ;
+}
+EXPORT_SYMBOL(hdmi_get_image_format);
+
+int hdmi_get_audio_format(void)
+{
+	int offset = 0x4, i, current_byte, length, flag = 0, j = 0;
+	if (edid_backup[0x7e] != 0x00) {
+		printk(KERN_INFO"Extension block present");
+		offset = edid_backup[(0x80) + 2];
+		if (offset != 0x4) {
+			i = 0x80 + 4;
+			while (i < (0x80 + offset)) {
+				current_byte = edid_backup[i];
+				if ((current_byte >> 5) == 1) {
+					current_byte = edid_backup[i];
+					length = current_byte & 0x1F;
+					for (j = 1 ; j < length ; j++) {
+						if (j%3 == 1) {
+						current_byte = edid_backup[i+j];
+						printk(KERN_INFO"Audio format supported is %d", current_byte & 0x78);
+printk(KERN_INFO"Number of channels supported %d", (current_byte & 0x07) + 1);
+						}
+
+					}
+				flag = 1;
+				break;
+				} else {
+					length = (current_byte & 0x1F) + 1;
+					i += length;
+				}
+			}
+		}
+
+	} else if (edid_backup[0x7e] != 0x00 && flag == 0) {
+		printk(KERN_INFO "Audio Information Data Not found");
+	} else {
+		printk(KERN_INFO "TV does not have Extension Block");
+	}
+	return 0;
+}
+EXPORT_SYMBOL(hdmi_get_audio_format);
+
+int hdmi_get_audio_video_latency(void)
+{
+	printk("This is yet to be implemented");
+	return 0;
+}
+EXPORT_SYMBOL(hdmi_get_audio_video_latency);
+
+int hdmi_get_pixel_append_position(void)
+{
+	printk("This is yet to be implemented");
+	return 0;
+}
+EXPORT_SYMBOL(hdmi_get_pixel_append_position);
+
+int hdmi_core_ddc_edid(u8 *pEDID)
+{
+	u32 i, j, l;
+	char checksum = 0;
+	u32 sts = HDMI_CORE_DDC_STATUS;
+	u32 ins = HDMI_CORE_SYS;
+
+	/* Turn on CLK for DDC */
+	REG_FLD_MOD(HDMI_CORE_AV, HDMI_CORE_AV_DPD, 0x7, 2, 0);
+
+	/* Wait */
+	mdelay(10);
+
+	/* Clk SCL Devices */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
+
+	/* HDMI_CORE_DDC_STATUS__IN_PROG */
+	while (FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1)
+
+	/* Clear FIFO */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
+
+	/* HDMI_CORE_DDC_STATUS__IN_PROG */
+	while (FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1)
+
+	/* Load Slave Address Register */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
+
+	/* Load Offset Address Register */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_OFFSET, 0x0, 7, 0);
+	/* Load Byte Count */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_COUNT1, 0x100, 7, 0);
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_COUNT2, 0x100>>8, 1, 0);
+	/* Set DDC_CMD */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
+
+	/* Yong: do not optimize this part of the code, seems
+	DDC bus needs some time to get stabilized
+	*/
+	l = hdmi_read_reg(ins, sts);
+
+	/* HDMI_CORE_DDC_STATUS__BUS_LOW */
+	if (FLD_GET(l, 6, 6) == 1) {
+		printk("I2C Bus Low?\n\r");
+		return -1;
+	}
+	/* HDMI_CORE_DDC_STATUS__NO_ACK */
+	if (FLD_GET(l, 5, 5) == 1) {
+		printk("I2C No Ack\n\r");
+		return -1;
+	}
+
+	j = 100;
+	while (j--) {
+		l = hdmi_read_reg(ins, sts);
+		/* progress */
+		if (FLD_GET(l, 4, 4) == 1) {
+			/* HACK: Load Slave Address Register again */
+			REG_FLD_MOD(ins, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
+			REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
+			break;
+		}
+		mdelay(20);
+	}
+
+	i = 0;
+	while (((FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1)
+			| (FLD_GET(hdmi_read_reg(ins, sts), 2, 2) == 0)) && i < 256) {
+		if (FLD_GET(hdmi_read_reg(ins,
+			sts), 2, 2) == 0) {
+			/* FIFO not empty */
+			pEDID[i++] = FLD_GET(hdmi_read_reg(ins, HDMI_CORE_DDC_DATA), 7, 0);
+		}
+	}
+
+	if (pEDID[0x14] == 0x80) {/* Digital Display */
+		if (pEDID[0x7e] == 0x00) {/* No Extention Block */
+			for (j = 0; j < 128; j++)
+			checksum += pEDID[j];
+			DBG("No extension 128 bit checksum\n");
+		} else {
+			for (j = 0; j < 256; j++)
+			checksum += pEDID[j];
+			DBG("Extension present 256 bit checksum\n");
+			/* HDMI_CORE_DDC_READ_EXTBLOCK(); */
+		}
+	} else {
+		DBG("Analog Display\n");
+	}
+
+	DBG("EDID Content %d\n", i);
+	for (i = 0 ; i < 256 ; i++)
+		edid_backup[i] = pEDID[i];
+
+#ifdef DEBUG_EDID
+	DBG("Header:\n");
+	for (i = 0x00; i < 0x08; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Vendor & Product:\n");
+	for (i = 0x08; i < 0x12; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("EDID Structure:\n");
+	for (i = 0x12; i < 0x14; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Basic Display Parameter:\n");
+	for (i = 0x14; i < 0x19; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Color Characteristics:\n");
+	for (i = 0x19; i < 0x23; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Established timings:\n");
+	for (i = 0x23; i < 0x26; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Standart timings:\n");
+	for (i = 0x26; i < 0x36; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Detailed timing1:\n");
+	for (i = 0x36; i < 0x48; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Detailed timing2:\n");
+	for (i = 0x48; i < 0x5a; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Detailed timing3:\n");
+	for (i = 0x5a; i < 0x6c; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Detailed timing4:\n");
+	for (i = 0x6c; i < 0x7e; i++)
+		DBG("%02x\n", pEDID[i]);
+#endif
+	if (checksum != 0) {
+		printk("E-EDID checksum failed!!");
+		return -1;
+	}
+	return 0;
+}
+
+static void hdmi_core_init(struct hdmi_core_video_config_t *v_cfg,
+	struct hdmi_core_audio_config *audio_cfg,
+	struct hdmi_core_infoframe_avi *avi,
+	struct hdmi_core_packet_enable_repeat *r_p)
+{
+	DBG("Enter HDMI_Core_GlobalInitVars()\n");
+
+	/*video core*/
+	v_cfg->CoreInputBusWide = HDMI_INPUT_8BIT;
+	v_cfg->CoreOutputDitherTruncation = HDMI_OUTPUTTRUNCATION_8BIT;
+	v_cfg->CoreDeepColorPacketED = HDMI_DEEPCOLORPACKECTDISABLE;
+	v_cfg->CorePacketMode = HDMI_PACKETMODERESERVEDVALUE;
+	v_cfg->CoreHdmiDvi = HDMI_DVI;
+	v_cfg->CoreTclkSelClkMult = FPLL10IDCK;
+
+	/*audio core*/
+	audio_cfg->fs = FS_44100;
+	audio_cfg->n = 0;
+	audio_cfg->cts = 0;
+	audio_cfg->layout = LAYOUT_2CH; /*2channel audio*/
+	audio_cfg->aud_par_busclk = 0;
+	audio_cfg->cts_mode = CTS_MODE_HW;
+
+	/*info frame*/
+	avi->db1y_rgb_yuv422_yuv444 = 0;
+	avi->db1a_active_format_off_on = 0;
+	avi->db1b_no_vert_hori_verthori = 0;
+	avi->db1s_0_1_2 = 0;
+	avi->db2c_no_itu601_itu709_extented = 0;
+	avi->db2m_no_43_169 = 0;
+	avi->db2r_same_43_169_149 = 0;
+	avi->db3itc_no_yes = 0;
+	avi->db3ec_xvyuv601_xvyuv709 = 0;
+	avi->db3q_default_lr_fr = 0;
+	avi->db3sc_no_hori_vert_horivert = 0;
+	avi->db4vic_videocode = 0;
+	avi->db5pr_no_2_3_4_5_6_7_8_9_10 = 0;
+	avi->db6_7_lineendoftop = 0 ;
+	avi->db8_9_linestartofbottom = 0;
+	avi->db10_11_pixelendofleft = 0;
+	avi->db12_13_pixelstartofright = 0;
+
+	/*packet enable and repeat*/
+	r_p->AudioPacketED = 0;
+	r_p->AudioPacketRepeat = 0;
+	r_p->AVIInfoFrameED = 0;
+	r_p->AVIInfoFrameRepeat = 0;
+	r_p->GeneralcontrolPacketED = 0;
+	r_p->GeneralcontrolPacketRepeat = 0;
+	r_p->GenericPacketED = 0;
+	r_p->GenericPacketRepeat = 0;
+}
+
+static void hdmi_core_powerdown_disable(void)
+{
+	DBG("Enter DSS_HDMI_CORE_POWER_DOWN_DISABLE()\n");
+	REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_CTRL1, 0x0, 0, 0);
+}
+
+/* todo: power off the core */
+static __attribute__ ((unused)) void hdmi_core_powerdown_enable(void)
+{
+	REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_CTRL1, 0x1, 0, 0);
+}
+
+static void hdmi_core_swreset_release(void)
+{
+	DBG("Enter DSS_HDMI_CORE_SW_RESET_RELEASE()\n");
+	REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_SYS__SRST, 0x0, 0, 0);
+}
+
+static void hdmi_core_swreset_assert(void)
+{
+	DBG("Enter DSS_HDMI_CORE_SW_RESET_ASSERT ()\n");
+	REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_SYS__SRST, 0x1, 0, 0);
+}
+
+/* DSS_HDMI_CORE_VIDEO_CONFIG */
+static int hdmi_core_video_config(
+	struct hdmi_core_video_config_t *cfg)
+{
+	u32 name = HDMI_CORE_SYS;
+	u32 av_name = HDMI_CORE_AV;
+	u32 r = 0;
+
+	/*sys_ctrl1 default configuration not tunable*/
+	u32 ven;
+	u32 hen;
+	u32 bsel;
+	u32 edge;
+
+	/*sys_ctrl1 default configuration not tunable*/
+	ven = HDMI_CORE_CTRL1_VEN__FOLLOWVSYNC;
+	hen = HDMI_CORE_CTRL1_HEN__FOLLOWHSYNC;
+	bsel = HDMI_CORE_CTRL1_BSEL__24BITBUS;
+	edge = HDMI_CORE_CTRL1_EDGE__RISINGEDGE;
+
+	/*sys_ctrl1 default configuration not tunable*/
+	r = hdmi_read_reg(name, HDMI_CORE_CTRL1);
+	r = FLD_MOD(r, ven, 5, 5);
+	r = FLD_MOD(r, hen, 4, 4);
+	r = FLD_MOD(r, bsel, 2, 2);
+	r = FLD_MOD(r, edge, 1, 1);
+	hdmi_write_reg(name, HDMI_CORE_CTRL1, r);
+
+	REG_FLD_MOD(name, HDMI_CORE_SYS__VID_ACEN, cfg->CoreInputBusWide, 7, 6);
+
+	/*Vid_Mode */
+	r = hdmi_read_reg(name, HDMI_CORE_SYS__VID_MODE);
+	/*dither truncation configuration*/
+	if (cfg->CoreOutputDitherTruncation >
+				HDMI_OUTPUTTRUNCATION_12BIT) {
+		r = FLD_MOD(r, cfg->CoreOutputDitherTruncation - 3, 7, 6);
+		r = FLD_MOD(r, 1, 5, 5);
+	} else {
+		r = FLD_MOD(r, cfg->CoreOutputDitherTruncation, 7, 6);
+		r = FLD_MOD(r, 0, 5, 5);
+	}
+	hdmi_write_reg(name, HDMI_CORE_SYS__VID_MODE, r);
+
+	/*HDMI_Ctrl*/
+	r = hdmi_read_reg(av_name, HDMI_CORE_AV_HDMI_CTRL);
+	r = FLD_MOD(r, cfg->CoreDeepColorPacketED, 6, 6);
+	r = FLD_MOD(r, cfg->CorePacketMode, 5, 3);
+	r = FLD_MOD(r, cfg->CoreHdmiDvi, 0, 0);
+	hdmi_write_reg(av_name, HDMI_CORE_AV_HDMI_CTRL, r);
+
+	/*TMDS_CTRL*/
+	REG_FLD_MOD(name, HDMI_CORE_SYS__TMDS_CTRL,
+		cfg->CoreTclkSelClkMult, 6, 5);
+
+	return 0;
+}
+
+static int hdmi_core_audio_mode_enable(u32  instanceName)
+{
+	REG_FLD_MOD(instanceName, HDMI_CORE_AV__AUD_MODE, 1, 0, 0);
+	return 0;
+}
+
+static int hdmi_core_audio_config(u32 name,
+		struct hdmi_core_audio_config *audio_cfg)
+{
+	int ret = 0;
+	u32 SD3_EN, SD2_EN, SD1_EN, SD0_EN;
+	u8 DBYTE1, DBYTE2, DBYTE4, CHSUM;
+	u8 size1;
+	u16 size0;
+
+	/*CTS_MODE*/
+	WR_REG_32(name, HDMI_CORE_AV__ACR_CTRL,
+		((0x0 << 2) | /* MCLK_EN (0: Mclk is not used)*/
+		(0x1 << 1) | /* CTS Request Enable (1:Packet Enable, 0:Disable) */
+		(audio_cfg->cts_mode << 0))); /* CTS Source Select  (1:SW, 0:HW)*/
+
+	REG_FLD_MOD(name, HDMI_CORE_AV__FREQ_SVAL, 0, 2, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL1, audio_cfg->n, 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL2, (audio_cfg->n >> 8), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL3, (audio_cfg->n >> 16), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL1, (audio_cfg->cts), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL2, (audio_cfg->cts >> 8), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL3, (audio_cfg->cts >> 16), 7, 0);
+
+	/*number of channel*/
+	REG_FLD_MOD(name, HDMI_CORE_AV__HDMI_CTRL, audio_cfg->layout, 2, 1);
+	REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_1,
+				audio_cfg->aud_par_busclk, 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_2,
+				(audio_cfg->aud_par_busclk >> 8), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_3,
+				(audio_cfg->aud_par_busclk >> 16), 7, 0);
+	/* FS_OVERRIDE = 1 because // input is used*/
+	WR_REG_32(name, HDMI_CORE_AV__SPDIF_CTRL, 0x1);
+	 /* refer to table209 p192 in func core spec*/
+	WR_REG_32(name, HDMI_CORE_AV__I2S_CHST4, audio_cfg->fs);
+
+	/* audio config is mainly due to wrapper hardware connection
+	   and so are fixe (hardware) I2S deserializer is by-pass
+	   so I2S configuration is not needed (I2S don't care).
+	   Wrapper are directly connected at the I2S deserialiser
+	   output level so some register call I2S... need to be
+	   programm to configure this parallel bus, there configuration
+	   is also fixe and due to the hardware connection (I2S hardware)
+	*/
+	WR_REG_32(name, HDMI_CORE_AV__I2S_IN_CTRL,
+		(0 << 7) | /* HBRA_ON */
+		(1 << 6) | /* SCK_EDGE Sample clock is rising */
+		(0 << 5) | /* CBIT_ORDER */
+		(0 << 4) | /* VBit, 0x0=PCM, 0x1=compressed */
+		(0 << 3) | /* I2S_WS, 0xdon't care */
+		(0 << 2) | /* I2S_JUST, 0=left-justified 1=right-justified */
+		(0 << 1) | /* I2S_DIR, 0xdon't care */
+		(0)); /* I2S_SHIFT, 0x0 don't care*/
+
+	WR_REG_32(name, HDMI_CORE_AV__I2S_CHST5, /* mode only */
+		(0 << 4) | /* FS_ORIG */
+		(1 << 1) | /* I2S lenght 16bits (refer doc) */
+		(0));/* Audio sample lenght */
+
+	WR_REG_32(name, HDMI_CORE_AV__I2S_IN_LEN, /* mode only */
+		(0xb)); /* In lenght b=>24bits     i2s hardware */
+
+	/*channel enable depend of the layout*/
+	if (audio_cfg->layout == LAYOUT_2CH) {
+		SD3_EN = 0x0;
+		SD2_EN = 0x0;
+		SD1_EN = 0x0;
+		SD0_EN = 0x1;
+	}
+	if (audio_cfg->layout == LAYOUT_8CH) {
+		SD3_EN = 0x1;
+		SD2_EN = 0x1;
+		SD1_EN = 0x1;
+		SD0_EN = 0x1;
+	}
+
+	WR_REG_32(name, HDMI_CORE_AV__AUD_MODE,
+		(SD3_EN << 7) | /* SD3_EN */
+		(SD2_EN << 6) | /* SD2_EN */
+		(SD1_EN << 5) | /* SD1_EN */
+		(SD0_EN << 4) | /* SD0_EN */
+		(0 << 3) | /* DSD_EN */
+		(1 << 2) | /* AUD_PAR_EN*/
+		(0 << 1) | /* SPDIF_EN*/
+		(0)); /* AUD_EN*/
+
+	/* Audio info frame setting refer to CEA-861-d spec p75 */
+	/*0x10 because only PCM is supported / -1 because 1 is for 2 channel*/
+	DBYTE1 = 0x10 + (audio_cfg->if_channel_number - 1);
+	DBYTE2 = (audio_cfg->if_fs << 2) + audio_cfg->if_sample_size;
+	/*channel location according to CEA spec*/
+	DBYTE4 = audio_cfg->if_audio_channel_location;
+
+	CHSUM = 0x100-0x84-0x01-0x0A-DBYTE1-DBYTE2-DBYTE4;
+
+	WR_REG_32(name, HDMI_CORE_AV__AUDIO_TYPE, 0x084);
+	WR_REG_32(name, HDMI_CORE_AV__AUDIO_VERS, 0x001);
+	WR_REG_32(name, HDMI_CORE_AV__AUDIO_LEN, 0x00A);
+	WR_REG_32(name, HDMI_CORE_AV__AUDIO_CHSUM, CHSUM); /*don't care on VMP*/
+
+	size0 = HDMI_CORE_AV__AUDIO_DBYTE;
+	size1 = HDMI_CORE_AV__AUDIO_DBYTE__ELSIZE;
+	hdmi_write_reg(name, (size0 + 0 * size1), DBYTE1);
+	hdmi_write_reg(name, (size0 + 1 * size1), DBYTE2);
+	hdmi_write_reg(name, (size0 + 2 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 3 * size1), DBYTE4);
+	hdmi_write_reg(name, (size0 + 4 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 5 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 6 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 7 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 8 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 9 * size1), 0x000);
+
+	return ret;
+}
+
+static int hdmi_core_audio_infoframe_avi(u32 name,
+	struct hdmi_core_infoframe_avi info_avi)
+{
+	u16 offset;
+	int dbyte, dbyte_size;
+	u32 val;
+
+	dbyte = HDMI_CORE_AV_AVI_DBYTE;
+	dbyte_size = HDMI_CORE_AV_AVI_DBYTE__ELSIZE;
+	/*info frame video*/
+	hdmi_write_reg(name, HDMI_CORE_AV_AVI_TYPE, 0x082);
+	hdmi_write_reg(name, HDMI_CORE_AV_AVI_VERS, 0x002);
+	hdmi_write_reg(name, HDMI_CORE_AV_AVI_LEN, 0x00D);
+
+	offset = dbyte + (0 * dbyte_size);
+	val = (info_avi.db1y_rgb_yuv422_yuv444 << 5) |
+		(info_avi.db1a_active_format_off_on << 4) |
+		(info_avi.db1b_no_vert_hori_verthori << 2) |
+		(info_avi.db1s_0_1_2);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (1 * dbyte_size);
+	val = (info_avi.db2c_no_itu601_itu709_extented << 6) |
+		(info_avi.db2m_no_43_169 << 4) |
+		(info_avi.db2r_same_43_169_149);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (2 * dbyte_size);
+	val = (info_avi.db3itc_no_yes << 7) |
+		(info_avi.db3ec_xvyuv601_xvyuv709 << 4) |
+		(info_avi.db3q_default_lr_fr << 2) |
+		(info_avi.db3sc_no_hori_vert_horivert);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (3 * dbyte_size);
+	hdmi_write_reg(name, offset, info_avi.db4vic_videocode);
+
+	offset = dbyte + (4 * dbyte_size);
+	val = info_avi.db5pr_no_2_3_4_5_6_7_8_9_10;
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (5 * dbyte_size);
+	val = info_avi.db6_7_lineendoftop & 0x00FF;
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (6 * dbyte_size);
+	val = ((info_avi.db6_7_lineendoftop >> 8) & 0x00FF);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (7 * dbyte_size);
+	val = info_avi.db8_9_linestartofbottom & 0x00FF;
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (8 * dbyte_size);
+	val = ((info_avi.db8_9_linestartofbottom >> 8) & 0x00FF);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (9 * dbyte_size);
+	val = info_avi.db10_11_pixelendofleft & 0x00FF;
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (10 * dbyte_size);
+	val = ((info_avi.db10_11_pixelendofleft >> 8) & 0x00FF);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (11 * dbyte_size);
+	val = info_avi.db12_13_pixelstartofright & 0x00FF;
+	hdmi_write_reg(name, offset , val);
+
+	offset = dbyte + (12 * dbyte_size);
+	val = ((info_avi.db12_13_pixelstartofright >> 8) & 0x00FF);
+	hdmi_write_reg(name, offset, val);
+
+	return 0;
+}
+
+static int hdmi_core_av_packet_config(u32 name,
+	struct hdmi_core_packet_enable_repeat r_p)
+{
+	/*enable/repeat the infoframe*/
+	hdmi_write_reg(name, HDMI_CORE_AV_PB_CTRL1,
+		(r_p.AudioPacketED << 5)|
+		(r_p.AudioPacketRepeat << 4)|
+		(r_p.AVIInfoFrameED << 1)|
+		(r_p.AVIInfoFrameRepeat));
+
+	/*enable/repeat the packet*/
+	hdmi_write_reg(name, HDMI_CORE_AV_PB_CTRL2,
+		(r_p.GeneralcontrolPacketED << 3)|
+		(r_p.GeneralcontrolPacketRepeat << 2)|
+		(r_p.GenericPacketED << 1)|
+		(r_p.GenericPacketRepeat));
+	return 0;
+}
+
+static void hdmi_w1_init(struct hdmi_video_timing *t_p,
+	struct hdmi_video_format *f_p,
+	struct hdmi_video_interface *i_p,
+	struct hdmi_irq_vector *pIrqVectorEnable,
+	struct hdmi_audio_format *audio_fmt,
+	struct hdmi_audio_dma *audio_dma)
+{
+	DBG("Enter HDMI_W1_GlobalInitVars()\n");
+
+	t_p->horizontalBackPorch = 0;
+	t_p->horizontalFrontPorch = 0;
+	t_p->horizontalSyncPulse = 0;
+	t_p->verticalBackPorch = 0;
+	t_p->verticalFrontPorch = 0;
+	t_p->verticalSyncPulse = 0;
+
+	f_p->packingMode = HDMI_PACK_10b_RGB_YUV444;
+	f_p->linePerPanel = 0;
+	f_p->pixelPerLine = 0;
+
+	i_p->vSyncPolarity = 0;
+	i_p->hSyncPolarity = 0;
+
+	i_p->interlacing = 0;
+	i_p->timingMode = 0; /* HDMI_TIMING_SLAVE */
+
+	pIrqVectorEnable->pllRecal = 0;
+	pIrqVectorEnable->pllUnlock = 0;
+	pIrqVectorEnable->pllLock = 0;
+	pIrqVectorEnable->phyDisconnect = 1;
+	pIrqVectorEnable->phyConnect = 1;
+	pIrqVectorEnable->phyShort5v = 0;
+	pIrqVectorEnable->videoEndFrame = 0;
+	pIrqVectorEnable->videoVsync = 0;
+	pIrqVectorEnable->fifoSampleRequest = 0;
+	pIrqVectorEnable->fifoOverflow = 0;
+	pIrqVectorEnable->fifoUnderflow = 0;
+	pIrqVectorEnable->ocpTimeOut = 0;
+	pIrqVectorEnable->core = 1;
+
+	audio_fmt->stereo_channel_enable = HDMI_STEREO_ONECHANNELS;
+	audio_fmt->audio_channel_location = HDMI_CEA_CODE_03;
+	audio_fmt->iec = HDMI_AUDIO_FORMAT_LPCM;
+	audio_fmt->justify = HDMI_AUDIO_JUSTIFY_LEFT;
+	audio_fmt->left_before = HDMI_SAMPLE_LEFT_FIRST;
+	audio_fmt->sample_number = HDMI_ONEWORD_ONE_SAMPLE;
+	audio_fmt->sample_size = HDMI_SAMPLE_24BITS;
+
+	audio_dma->dma_transfer = 0x10;
+	audio_dma->block_size = 0xC0;
+	audio_dma->dma_or_irq = HDMI_THRESHOLD_DMA;
+	audio_dma->threshold_value = 0x10;
+	audio_dma->block_start_end = HDMI_BLOCK_STARTEND_ON;
+
+}
+
+
+static void hdmi_w1_irq_enable(struct hdmi_irq_vector *pIrqVectorEnable)
+{
+	u32 r = 0;
+
+	r = ((pIrqVectorEnable->pllRecal << 31) |
+		(pIrqVectorEnable->pllUnlock << 30) |
+		(pIrqVectorEnable->pllLock << 29) |
+		(pIrqVectorEnable->phyDisconnect << 26) |
+		(pIrqVectorEnable->phyConnect << 25) |
+		(pIrqVectorEnable->phyShort5v << 24) |
+		(pIrqVectorEnable->videoEndFrame << 17) |
+		(pIrqVectorEnable->videoVsync << 16) |
+		(pIrqVectorEnable->fifoSampleRequest << 10) |
+		(pIrqVectorEnable->fifoOverflow << 9) |
+		(pIrqVectorEnable->fifoUnderflow << 8) |
+		(pIrqVectorEnable->ocpTimeOut << 4) |
+		(pIrqVectorEnable->core << 0));
+
+	hdmi_write_reg(HDMI_WP, HDMI_WP_IRQENABLE_SET, r);
+}
+
+static inline int hdmi_w1_wait_for_bit_change(const u32 ins,
+	u32 idx, int b2, int b1, int val)
+{
+	int t = 0;
+	while (val != FLD_GET(hdmi_read_reg(ins, idx), b2, b1)) {
+		udelay(1);
+		if (t++ > 1000)
+			return !val;
+	}
+	return val;
+}
+
+/* todo: add timeout value */
+int hdmi_w1_set_wait_srest(void)
+{
+	/* reset W1 */
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_SYSCONFIG, 0x1, 0, 0);
+
+	/* wait till SOFTRESET == 0 */
+	while (FLD_GET(hdmi_read_reg(HDMI_WP, HDMI_WP_SYSCONFIG), 0, 0))
+		;
+
+	return 0;
+}
+
+/* PHY_PWR_CMD */
+int hdmi_w1_set_wait_phy_pwr(HDMI_PhyPwr_t val)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_PWR_CTRL, val, 7, 6);
+
+	if (hdmi_w1_wait_for_bit_change(HDMI_WP,
+		HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
+		ERR("Failed to set PHY power mode to %d\n", val);
+		return -ENODEV;
+	}
+	return 0;
+}
+
+/* PLL_PWR_CMD */
+int hdmi_w1_set_wait_pll_pwr(HDMI_PllPwr_t val)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_PWR_CTRL, val, 3, 2);
+
+	/* wait till PHY_PWR_STATUS=ON */
+	if (hdmi_w1_wait_for_bit_change(HDMI_WP,
+		HDMI_WP_PWR_CTRL, 1, 0, val) != val) {
+		ERR("Failed to set PHY_PWR_STATUS to ON\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+void hdmi_w1_video_stop(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, 0, 31, 31);
+}
+
+void hdmi_w1_video_start(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, (u32)0x1, 31, 31);
+}
+
+static void hdmi_w1_video_init_format(struct hdmi_video_format *f_p,
+	struct hdmi_video_timing *t_p, struct hdmi_config *param)
+{
+	DBG("Enter HDMI_W1_ConfigVideoResolutionTiming()\n");
+
+	f_p->linePerPanel = param->lpp;
+	f_p->pixelPerLine = param->ppl;
+
+	t_p->horizontalBackPorch = param->hbp;
+	t_p->horizontalFrontPorch = param->hfp;
+	t_p->horizontalSyncPulse = param->hsw;
+	t_p->verticalBackPorch = param->vbp;
+	t_p->verticalFrontPorch = param->vfp;
+	t_p->verticalSyncPulse = param->vsw;
+}
+
+static void hdmi_w1_video_config_format(
+	struct hdmi_video_format *f_p)
+{
+	u32 l = 0;
+
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, f_p->packingMode, 10, 8);
+
+	l |= FLD_VAL(f_p->linePerPanel, 31, 16);
+	l |= FLD_VAL(f_p->pixelPerLine, 15, 0);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE, l);
+}
+
+static void hdmi_w1_video_config_interface(
+	struct hdmi_video_interface *i_p)
+{
+	u32 r;
+	DBG("Enter HDMI_W1_ConfigVideoInterface()\n");
+
+	r = hdmi_read_reg(HDMI_WP, HDMI_WP_VIDEO_CFG);
+	r = FLD_MOD(r, i_p->vSyncPolarity, 7, 7);
+	r = FLD_MOD(r, i_p->hSyncPolarity, 6, 6);
+	r = FLD_MOD(r, i_p->interlacing, 3, 3);
+	r = FLD_MOD(r, i_p->timingMode, 1, 0);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_CFG, r);
+}
+
+static void hdmi_w1_video_config_timing(
+	struct hdmi_video_timing *t_p)
+{
+	u32 timing_h = 0;
+	u32 timing_v = 0;
+
+	DBG("Enter HDMI_W1_ConfigVideoTiming ()\n");
+
+	timing_h |= FLD_VAL(t_p->horizontalBackPorch, 31, 20);
+	timing_h |= FLD_VAL(t_p->horizontalFrontPorch, 19, 8);
+	timing_h |= FLD_VAL(t_p->horizontalSyncPulse, 7, 0);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_TIMING_H, timing_h);
+
+	timing_v |= FLD_VAL(t_p->verticalBackPorch, 31, 20);
+	timing_v |= FLD_VAL(t_p->verticalFrontPorch, 19, 8);
+	timing_v |= FLD_VAL(t_p->verticalSyncPulse, 7, 0);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_TIMING_V, timing_v);
+}
+
+static int hdmi_w1_audio_config_format(u32 name,
+			struct hdmi_audio_format *audio_fmt)
+{
+	int ret = 0;
+	u32 value = 0;
+
+	value = hdmi_read_reg(name, HDMI_WP_AUDIO_CFG);
+	value &= 0xfffffff7;
+	value |= ((audio_fmt->justify) << 3);;
+	value &= 0xfffffffb;
+	value |= ((audio_fmt->left_before) << 2);
+	value &= 0xfffffffd;
+	value |= ((audio_fmt->sample_number) << 1);
+	value &= 0xfffffffe;
+	value |= ((audio_fmt->sample_size));
+	value &= 0xf8ffffff;
+	value |= ((audio_fmt->stereo_channel_enable) << 24);
+	value &= 0xff00ffff;
+	value |= ((audio_fmt->audio_channel_location) << 16);
+	value &= 0xffffffef;
+	value |= ((audio_fmt->iec) << 4);
+	/* Wakeup */
+	value = 0x1030022;
+	hdmi_write_reg(name, HDMI_WP_AUDIO_CFG, value);
+	DBG("HDMI_WP_AUDIO_CFG = 0x%x \n", value);
+
+	return ret;
+}
+
+static int hdmi_w1_audio_config_dma(u32 name, struct hdmi_audio_dma *audio_dma)
+
+{
+	int ret = 0;
+	u32 value = 0;
+
+	value = hdmi_read_reg(name, HDMI_WP_AUDIO_CFG2);
+	value &= 0xffffff00;
+	value |= (audio_dma->block_size);
+	value &= 0xffff00ff;
+	value |= ((audio_dma->dma_transfer) << 8);
+	/*  Wakeup */
+	value = 0x20C0;
+	hdmi_write_reg(name, HDMI_WP_AUDIO_CFG2, value);
+	DBG("HDMI_WP_AUDIO_CFG2 = 0x%x \n", value);
+
+	value = hdmi_read_reg(name, HDMI_WP_AUDIO_CTRL);
+	value &= 0xfffffdff;
+	value |= ((audio_dma->dma_or_irq)<<9);
+	value &= 0xfffffe00;
+	value |= (audio_dma->threshold_value);
+	/*  Wakeup */
+	value = 0x020;
+	hdmi_write_reg(name, HDMI_WP_AUDIO_CTRL, value);
+	DBG("HDMI_WP_AUDIO_CTRL = 0x%x \n", value);
+
+	return ret;
+}
+
+static void hdmi_w1_audio_enable(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 1, 31, 31);
+}
+
+static __attribute__ ((unused))__attribute__ ((unused)) void hdmi_w1_audio_disable(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 0, 31, 31);
+}
+
+static void hdmi_w1_audio_start(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 1, 30, 30);
+}
+
+static void hdmi_w1_audio_stop(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 0, 30, 30);
+}
+
+static int hdmi_w1_audio_config(void)
+{
+	int ret;
+
+	struct hdmi_audio_format audio_fmt;
+	struct hdmi_audio_dma audio_dma;
+
+	audio_fmt.justify = HDMI_AUDIO_JUSTIFY_LEFT;
+	audio_fmt.sample_number = HDMI_ONEWORD_ONE_SAMPLE;
+	audio_fmt.sample_size = HDMI_SAMPLE_24BITS;
+	audio_fmt.stereo_channel_enable = HDMI_STEREO_ONECHANNELS;
+	audio_fmt.audio_channel_location = 0x03;
+
+	ret = hdmi_w1_audio_config_format(HDMI_WP, &audio_fmt);
+
+	audio_dma.dma_transfer = 0x20;
+	audio_dma.threshold_value = 0x60;
+	audio_dma.dma_or_irq = HDMI_THRESHOLD_DMA;
+
+	ret = hdmi_w1_audio_config_dma(HDMI_WP, &audio_dma);
+
+	return ret;
+}
+
+int hdmi_lib_enable(struct hdmi_config *cfg)
+{
+	u32 r, val;
+
+	u32 av_name = HDMI_CORE_AV;
+
+	/*HDMI*/
+	struct hdmi_video_timing VideoTimingParam;
+	struct hdmi_video_format VideoFormatParam;
+	struct hdmi_video_interface VideoInterfaceParam;
+	struct hdmi_irq_vector IrqHdmiVectorEnable;
+	struct hdmi_audio_format audio_fmt;
+	struct hdmi_audio_dma audio_dma;
+
+	/*HDMI core*/
+	struct hdmi_core_infoframe_avi avi_param;
+	struct hdmi_core_video_config_t v_core_cfg;
+	struct hdmi_core_audio_config audio_cfg;
+	struct hdmi_core_packet_enable_repeat repeat_param;
+
+	hdmi_w1_init(&VideoTimingParam, &VideoFormatParam,
+		&VideoInterfaceParam, &IrqHdmiVectorEnable,
+		&audio_fmt, &audio_dma);
+
+	hdmi_core_init(&v_core_cfg,
+		&audio_cfg,
+		&avi_param,
+		&repeat_param);
+
+	/* Enable PLL Lock and UnLock intrerrupts */
+	IrqHdmiVectorEnable.pllUnlock = 1;
+	IrqHdmiVectorEnable.pllLock = 1;
+
+	/***************** init DSS register **********************/
+	hdmi_w1_irq_enable(&IrqHdmiVectorEnable);
+
+	hdmi_w1_video_init_format(&VideoFormatParam,
+			&VideoTimingParam, cfg);
+
+	hdmi_w1_video_config_timing(&VideoTimingParam);
+
+	/*video config*/
+	VideoFormatParam.packingMode = HDMI_PACK_24b_RGB_YUV444_YUV422;
+
+	hdmi_w1_video_config_format(&VideoFormatParam);
+
+	/* FIXME */
+	VideoInterfaceParam.vSyncPolarity = cfg->v_pol;
+	VideoInterfaceParam.hSyncPolarity = cfg->h_pol;
+	VideoInterfaceParam.interlacing = cfg->interlace;
+	VideoInterfaceParam.timingMode = 1 ; /* HDMI_TIMING_MASTER_24BIT */
+
+	hdmi_w1_video_config_interface(&VideoInterfaceParam);
+
+#if 0
+	/* hnagalla */
+	val = hdmi_read_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE);
+
+	val &= 0x0FFFFFFF;
+	val |= ((0x1f) << 27); /* wakeup */
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE, val);
+
+	hdmi_w1_audio_config();
+#endif
+
+	/****************************** CORE *******************************/
+	/************* configure core video part ********************************/
+	/*set software reset in the core*/
+	hdmi_core_swreset_assert();
+
+	/*power down off*/
+	hdmi_core_powerdown_disable();
+
+	v_core_cfg.CorePacketMode = HDMI_PACKETMODE24BITPERPIXEL;
+	v_core_cfg.CoreHdmiDvi = HDMI_HDMI;
+
+	/* hnagalla */
+	audio_cfg.fs = 0x02;
+	audio_cfg.if_fs = 0x00;
+	audio_cfg.n = 6144;
+	audio_cfg.cts = 74250;
+
+	/* audio channel */
+	audio_cfg.if_sample_size = 0x0;
+	audio_cfg.layout = 0;
+	audio_cfg.if_channel_number = 2;
+	audio_cfg.if_audio_channel_location = 0x00;
+
+	/* TODO: Is this configuration correct? */
+	audio_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
+	audio_cfg.cts_mode = 0;
+
+	r = hdmi_core_video_config(&v_core_cfg);
+
+	/* hnagalla */
+	hdmi_core_audio_config(av_name, &audio_cfg);
+	hdmi_core_audio_mode_enable(av_name);
+
+	/*release software reset in the core*/
+	hdmi_core_swreset_release();
+
+	/*configure packet*/
+	/*info frame video see doc CEA861-D page 65*/
+	avi_param.db1y_rgb_yuv422_yuv444 = INFOFRAME_AVI_DB1Y_RGB;
+	avi_param.db1a_active_format_off_on =
+		INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
+	avi_param.db1b_no_vert_hori_verthori = INFOFRAME_AVI_DB1B_NO;
+	avi_param.db1s_0_1_2 = INFOFRAME_AVI_DB1S_0;
+	avi_param.db2c_no_itu601_itu709_extented = INFOFRAME_AVI_DB2C_NO;
+	avi_param.db2m_no_43_169 = INFOFRAME_AVI_DB2M_NO;
+	avi_param.db2r_same_43_169_149 = INFOFRAME_AVI_DB2R_SAME;
+	avi_param.db3itc_no_yes = INFOFRAME_AVI_DB3ITC_NO;
+	avi_param.db3ec_xvyuv601_xvyuv709 = INFOFRAME_AVI_DB3EC_XVYUV601;
+	avi_param.db3q_default_lr_fr = INFOFRAME_AVI_DB3Q_DEFAULT;
+	avi_param.db3sc_no_hori_vert_horivert = INFOFRAME_AVI_DB3SC_NO;
+	avi_param.db4vic_videocode = cfg->video_format;
+	avi_param.db5pr_no_2_3_4_5_6_7_8_9_10 = INFOFRAME_AVI_DB5PR_NO;
+	avi_param.db6_7_lineendoftop = 0;
+	avi_param.db8_9_linestartofbottom = 0;
+	avi_param.db10_11_pixelendofleft = 0;
+	avi_param.db12_13_pixelstartofright = 0;
+
+	r = hdmi_core_audio_infoframe_avi(av_name, avi_param);
+
+	/*enable/repeat the infoframe*/
+	repeat_param.AVIInfoFrameED = PACKETENABLE;
+	repeat_param.AVIInfoFrameRepeat = PACKETREPEATON;
+	/* wakeup */
+	repeat_param.AudioPacketED = PACKETENABLE;
+	repeat_param.AudioPacketRepeat = PACKETREPEATON;
+	r = hdmi_core_av_packet_config(av_name, repeat_param);
+
+	REG_FLD_MOD(av_name, HDMI_CORE_AV__HDMI_CTRL, cfg->hdmi_dvi, 0, 0);
+	return r;
+}
+
+int hdmi_lib_init(void){
+	u32 rev;
+
+	hdmi.base_wp = ioremap(HDMI_WP, (HDMI_HDCP - HDMI_WP));
+
+	if (!hdmi.base_wp) {
+		ERR("can't ioremap WP\n");
+		return -ENOMEM;
+	}
+
+	hdmi.base_core = hdmi.base_wp + 0x400;
+	hdmi.base_core_av = hdmi.base_wp + 0x900;
+
+	rev = hdmi_read_reg(HDMI_WP, HDMI_WP_REVISION);
+
+	printk(KERN_INFO "OMAP HDMI W1 rev %d.%d\n",
+		FLD_GET(rev, 10, 8), FLD_GET(rev, 5, 0));
+
+	return 0;
+}
+
+void hdmi_lib_exit(void){
+	iounmap(hdmi.base_wp);
+}
+
+void dump_regs(void){
+	DBG("W1 VIDEO_CFG = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x50ul));
+	DBG("Core CTRL1 = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x420ul));
+	DBG("Core VID_MODE = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x528ul));
+	DBG("Core AV_CTRL = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x9bcul));
+	DBG("Core VID_ACEN = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x524ul));
+	DBG("Core PB_CTR2 packet buf = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x9fcul));
+}
+
+int hdmi_set_irqs(void)
+{
+	u32 r = 0 , hpd = 0;
+	struct hdmi_irq_vector pIrqVectorEnable;
+
+	pIrqVectorEnable.pllRecal = 0;
+	pIrqVectorEnable.phyShort5v = 0;
+	pIrqVectorEnable.videoEndFrame = 0;
+	pIrqVectorEnable.videoVsync = 0;
+	pIrqVectorEnable.fifoSampleRequest = 0;
+	pIrqVectorEnable.fifoOverflow = 0;
+	pIrqVectorEnable.fifoUnderflow = 0;
+	pIrqVectorEnable.ocpTimeOut = 0;
+	pIrqVectorEnable.pllUnlock = 1;
+	pIrqVectorEnable.pllLock = 1;
+	pIrqVectorEnable.phyDisconnect = 1;
+	pIrqVectorEnable.phyConnect = 1;
+	pIrqVectorEnable.core = 1;
+
+	hdmi_w1_irq_enable(&pIrqVectorEnable);
+
+	r = hdmi_read_reg(HDMI_WP, HDMI_WP_IRQENABLE_SET);
+	DBG("Irqenable %x \n", r);
+	hpd = hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__UMASK1);
+	DBG("%x hpd\n", hpd);
+	return 0;
+}
+
+/* Interrupt handler*/
+void HDMI_W1_HPD_handler(int *r)
+{
+	u32 val, intr, set;
+	mdelay(30);
+	val = hdmi_read_reg(HDMI_WP, HDMI_WP_IRQSTATUS);
+	DBG("%x hdmi_wp_irqstatus\n", val);
+	mdelay(30);
+	set = 0;
+	set = hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__SYS_STAT);
+	DBG("%x hdmi_core_sys_sys_stat\n", set);
+	mdelay(30);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_IRQSTATUS, val);
+	/* flush posted write */
+	hdmi_read_reg(HDMI_WP, HDMI_WP_IRQSTATUS);
+	mdelay(30);
+	*r = 0;
+	if ((count == 0) && ((val & 0x02000000) == 0x02000000) &&
+		((set & 0x00000002) != 0x00000002)) {
+		*r = 2;
+		DBG("First interrupt physical attach but not HPD");
+		count_hpd = 0;
+	}
+	count++;
+	hdmi_set_irqs();
+	DBG("%d count and count_hpd %d", count, count_hpd);
+	if ((set & 0x00000002) == 0x00000002) {
+		if (count_hpd == 0) {
+			*r = 4;
+			count_hpd++;
+			goto end;
+		} else
+			*r = 1;
+		DBG("HPD is set you can read edid");
+	}
+	if (((val & 0x04000000) == 0x04000000) && ((set & 0x00000002) != 0x00000002)) {
+		*r = 3;
+		count = 0;
+		count_hpd = 0;
+	}
+	intr =  hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__INTR1);
+	DBG("%x hdmi_core_sys_sys_intr\n", intr);
+	end: /*Do nothing*/;
+}
+
+
+/* wrapper functions to be used until L24.5 release*/
+int HDMI_CORE_DDC_READEDID(u32 name, u8 *p)
+{
+	int r = hdmi_core_ddc_edid(p);
+	return r;
+}
+
+int HDMI_W1_StopVideoFrame(u32 name)
+{
+	DBG("Enter HDMI_W1_StopVideoFrame()\n");
+	hdmi_w1_video_stop();
+	return 0;
+}
+
+int HDMI_W1_StartVideoFrame(u32 name)
+{
+	DBG("Enter HDMI_W1_StartVideoFrame  ()\n");
+	hdmi_w1_video_start();
+	return 0;
+}
+
+/* PHY_PWR_CMD */
+int HDMI_W1_SetWaitPhyPwrState(u32 name,
+	HDMI_PhyPwr_t param)
+{
+	int r = hdmi_w1_set_wait_phy_pwr(param);
+	return r;
+}
+
+/* PLL_PWR_CMD */
+int HDMI_W1_SetWaitPllPwrState(u32 name,
+		HDMI_PllPwr_t param)
+{
+	int r = hdmi_w1_set_wait_pll_pwr(param);
+	return r;
+}
+
+int HDMI_W1_SetWaitSoftReset(void)
+{
+	/* reset W1 */
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_SYSCONFIG, 0x1, 0, 0);
+
+	/* wait till SOFTRESET == 0 */
+	while (FLD_GET(hdmi_read_reg(HDMI_WP, HDMI_WP_SYSCONFIG), 0, 0))
+		;
+
+	return 0;
+}
+
+int hdmi_w1_wrapper_enable(u32 instanceName)
+{
+	printk(KERN_INFO "Wrapper Enabled...\n");
+	hdmi_w1_audio_enable();
+	return 0;
+}
+
+int hdmi_w1_wrapper_disable(u32 instanceName)
+{
+	hdmi_w1_audio_enable();
+	printk(KERN_INFO "Wrapper disabled...\n");
+	return 0;
+}
+
+int hdmi_w1_stop_audio_transfer(u32 instanceName)
+{
+	hdmi_w1_audio_stop();
+	return 0;
+}
+
+int hdmi_w1_start_audio_transfer(u32 instanceName)
+{
+	hdmi_w1_audio_start();
+	printk(KERN_INFO "Start audio transfer...\n");
+	return 0;
+}
+
+int DSS_HDMI_CONFIG(HDMI_Timing_t timings, u32 video_format,
+	u32 mode)
+{
+	int err;
+	struct hdmi_config data;
+
+	data.ppl = timings.pixelPerLine;
+	data.lpp = timings.linePerPanel;
+	data.pixel_clock = timings.pplclk;
+
+	data.hsw = timings.horizontalSyncPulse;
+	data.hfp = timings.horizontalFrontPorch;
+	data.hbp = timings.horizontalBackPorch;
+	data.vsw = timings.verticalSyncPulse;
+	data.vfp = timings.verticalFrontPorch;
+	data.vbp = timings.verticalBackPorch;
+
+	data.h_pol = 1;
+	data.v_pol = 1;
+	data.hdmi_dvi = mode;
+	data.video_format = video_format;
+
+	err = hdmi_lib_enable(&data);
+	return err;
+}
+
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 1c529ce9dc11..c5a54458d72a 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -42,6 +42,17 @@
 #define DISPC_IRQ_SYNC_LOST		(1 << 14)
 #define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
 #define DISPC_IRQ_WAKEUP		(1 << 16)
+#define DISPC_IRQ_SYNC_LOST_2  (1 << 17)
+#define DISPC_IRQ_VSYNC2               (1 << 18)
+#define DISPC_IRQ_VID3_END_WIN         (1 << 19)
+#define DISPC_IRQ_VID3_FIFO_UNDERFLOW  (1 << 20)
+					/* VID3_BUF_UNDERFLOW*/
+#define DISPC_IRQ_ACBIAS_COUNT_STAT2   (1 << 21)
+#define DISPC_IRQ_FRAMEDONE2           (1 << 22)
+#define DISPC_IRQ_FRAMEDONE_WB         (1 << 23)
+#define DISPC_IRQ_FRAMEDONE_DIG                (1 << 24) /* FRAMEDONE_TV*/
+#define DISPC_IRQ_WB_BUF_OVERFLOW      (1 << 25)
+
 
 struct omap_dss_device;
 struct omap_overlay_manager;
@@ -53,17 +64,21 @@ enum omap_display_type {
 	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
 	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
 	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
+	OMAP_DISPLAY_TYPE_HDMI		= 1 << 5,
 };
 
 enum omap_plane {
 	OMAP_DSS_GFX	= 0,
 	OMAP_DSS_VIDEO1	= 1,
-	OMAP_DSS_VIDEO2	= 2
+	OMAP_DSS_VIDEO2	= 2,
+	OMAP_DSS_VIDEO3 = 3,
+	OMAP_DSS_WB = 4
 };
 
 enum omap_channel {
 	OMAP_DSS_CHANNEL_LCD	= 0,
 	OMAP_DSS_CHANNEL_DIGIT	= 1,
+	OMAP_DSS_CHANNEL_LCD2   = 2,
 };
 
 enum omap_color_mode {
@@ -81,6 +96,13 @@ enum omap_color_mode {
 	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
 	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
 	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
+	OMAP_DSS_COLOR_NV12     = 1 << 14, /* NV12 format: YUV 4:2:0 */
+	OMAP_DSS_COLOR_RGBA12   = 1 << 15, /* RGBA12 - 4444 */
+	OMAP_DSS_COLOR_XRGB12   = 1 << 16, /* xRGB12, 16-bit container */
+	OMAP_DSS_COLOR_ARGB16_1555      = 1 << 17, /* ARGB16-1555 */
+	OMAP_DSS_COLOR_RGBX24_32_ALGN   = 1 << 18, /* 32-msb aligned 24bit */
+	OMAP_DSS_COLOR_XRGB15   = 1 << 19, /* xRGB15: 1555*/
+
 
 	OMAP_DSS_COLOR_GFX_OMAP2 =
 		OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
@@ -102,16 +124,26 @@ enum omap_color_mode {
 		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 
 	OMAP_DSS_COLOR_VID1_OMAP3 =
+		OMAP_DSS_COLOR_NV12 | OMAP_DSS_COLOR_RGBA12 |
+		OMAP_DSS_COLOR_XRGB12 | OMAP_DSS_COLOR_ARGB16_1555 |
+		OMAP_DSS_COLOR_RGBX24_32_ALGN | OMAP_DSS_COLOR_XRGB15 |
 		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
 		OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
-		OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
+		OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY |
+		OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBA32 |
+		OMAP_DSS_COLOR_RGBX32,
 
 	OMAP_DSS_COLOR_VID2_OMAP3 =
+		OMAP_DSS_COLOR_NV12 | OMAP_DSS_COLOR_RGBA12 |
+		OMAP_DSS_COLOR_XRGB12 | OMAP_DSS_COLOR_ARGB16_1555 |
+		OMAP_DSS_COLOR_RGBX24_32_ALGN | OMAP_DSS_COLOR_XRGB15 |
 		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 		OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
 		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
+
+	OMAP_DSS_COLOR_VID3_OMAP3 = OMAP_DSS_COLOR_VID2_OMAP3,
 };
 
 enum omap_lcd_display_type {
@@ -173,11 +205,13 @@ enum omap_dss_display_state {
 enum omap_dss_overlay_managers {
 	OMAP_DSS_OVL_MGR_LCD,
 	OMAP_DSS_OVL_MGR_TV,
+	OMAP_DSS_OVL_MGR_LCD2,
 };
 
 enum omap_dss_rotation_type {
 	OMAP_DSS_ROT_DMA = 0,
 	OMAP_DSS_ROT_VRFB = 1,
+	OMAP_DSS_ROT_TILER = 2,
 };
 
 /* clockwise rotation angle */
@@ -197,6 +231,34 @@ enum omap_overlay_manager_caps {
 	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
 };
 
+enum omap_overlay_zorder {
+	OMAP_DSS_OVL_ZORDER_0	= 0x0,
+	OMAP_DSS_OVL_ZORDER_1	= 0x1,
+	OMAP_DSS_OVL_ZORDER_2	= 0x2,
+	OMAP_DSS_OVL_ZORDER_3	= 0x3,
+};
+
+/* write back*/
+enum omap_writeback_source {
+	OMAP_WB_LCD_1_MANAGER		= 0,
+	OMAP_WB_LCD_2_MANAGER		= 1,
+	OMAP_WB_TV_MANAGER		= 2,
+	OMAP_WB_OVERLAY0			= 3,
+	OMAP_WB_OVERLAY1			= 4,
+	OMAP_WB_OVERLAY2			= 5,
+	OMAP_WB_OVERLAY3 			= 6
+};
+
+enum omap_writeback_capturemode {
+	OMAP_WB_CAPTURE_ALL = 0x0,
+	OMAP_WB_CAPTURE_1 = 0x1,
+	OMAP_WB_CAPTURE_1_OF_2 = 0x2,
+	OMAP_WB_CAPTURE_1_OF_3 = 0x3,
+	OMAP_WB_CAPTURE_1_OF_4 = 0x4,
+	OMAP_WB_CAPTURE_1_OF_5 = 0x5,
+	OMAP_WB_CAPTURE_1_OF_6 = 0x6,
+	OMAP_WB_CAPTURE_1_OF_7 = 0x7
+};
 /* RFBI */
 
 struct rfbi_timings {
@@ -230,20 +292,42 @@ int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 			     int hs_pol_inv, int vs_pol_inv, int extif_div);
 
 /* DSI */
-void dsi_bus_lock(void);
-void dsi_bus_unlock(void);
-int dsi_vc_dcs_write(int channel, u8 *data, int len);
-int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
-int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
-int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
-int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
-int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
-int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data);
-int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
-int dsi_vc_send_null(int channel);
-int dsi_vc_send_bta_sync(int channel);
+enum omap_dsi_index {
+	DSI1 = 0,
+	DSI2 = 1,
+};
+void dsi_bus_lock(enum omap_dsi_index ix);
+void dsi_bus_unlock(enum omap_dsi_index ix);
+int dsi_vc_dcs_write(enum omap_dsi_index ix, int channel,
+		u8 *data, int len);
+int dsi_vc_dcs_write_0(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd);
+int dsi_vc_dcs_write_1(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd, u8 param);
+int dsi_vc_dcs_write_nosync(enum omap_dsi_index ix, int channel,
+		u8 *data, int len);
+int dsi_vc_dcs_read(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd, u8 *buf, int buflen);
+int dsi_vc_dcs_read_1(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd, u8 *data);
+int dsi_vc_dcs_read_2(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd, u16 *data);
+int dsi_vc_set_max_rx_packet_size(enum omap_dsi_index ix,
+		int channel, u16 len);
+int dsi_vc_send_null(enum omap_dsi_index ix, int channel);
+int dsi_vc_send_bta_sync(enum omap_dsi_index ix, int channel);
 
 /* Board specific data */
+#define PWM2ON		0x03
+#define PWM2OFF		0x04
+#define TOGGLE3		0x92
+#define HDMI_GPIO_60 60
+#define HDMI_GPIO_41 41
+#define DLP_4430_GPIO_40	40
+#define DLP_4430_GPIO_44	44
+#define DLP_4430_GPIO_45	45
+#define DLP_4430_GPIO_59	59
+
 struct omap_dss_board_info {
 	int (*get_last_off_on_transaction_id)(struct device *dev);
 	int num_devices;
@@ -299,6 +383,8 @@ struct omap_overlay_info {
 	u16 out_width;	/* if 0, out_width == width */
 	u16 out_height;	/* if 0, out_height == height */
 	u8 global_alpha;
+	enum omap_overlay_zorder zorder;
+	u32 p_uv_addr; /* relevant for NV12 format only */
 };
 
 struct omap_overlay {
@@ -377,6 +463,43 @@ struct omap_overlay_manager {
 	int (*disable)(struct omap_overlay_manager *mgr);
 };
 
+enum omap_writeback_source_type {
+	OMAP_WB_SOURCE_OVERLAY	= 0,
+	OMAP_WB_SOURCE_MANAGER	= 1
+};
+
+
+struct omap_writeback_info {
+		bool					enabled;
+		bool					info_dirty;
+		enum omap_writeback_source		source;
+		enum omap_writeback_source_type 	source_type;
+		unsigned long				width;
+		unsigned long				height;
+		enum omap_color_mode			dss_mode;
+		enum omap_writeback_capturemode 	capturemode;
+		unsigned long				paddr;
+		/* NV12 support*/
+		unsigned long				puv_addr;
+
+};
+
+struct omap_writeback {
+	struct kobject kobj;
+	struct list_head list;
+	bool								enabled;
+	bool								info_dirty;
+	bool								first_time;
+	/* mutex to control access to wb data */
+	struct mutex lock;
+	struct omap_writeback_info info;
+	bool (*check_wb)(struct omap_writeback *wb);
+
+	int (*set_wb_info)(struct omap_writeback *wb, struct omap_writeback_info *info);
+	void (*get_wb_info)(struct omap_writeback *wb, struct omap_writeback_info *info);
+
+};
+
 struct omap_dss_device {
 	struct device dev;
 
@@ -460,8 +583,10 @@ struct omap_dss_device {
 	enum omap_display_caps caps;
 
 	struct omap_overlay_manager *manager;
+	struct omap_writeback *wb_manager;
 
 	enum omap_dss_display_state state;
+	enum omap_channel channel;
 
 	/* platform specific  */
 	int (*platform_enable)(struct omap_dss_device *dssdev);
@@ -494,6 +619,7 @@ struct omap_dss_driver {
 	int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 	int (*get_te)(struct omap_dss_device *dssdev);
 
+	int (*wait_for_te)(struct omap_dss_device *dssdev);
 	u8 (*get_rotate)(struct omap_dss_device *dssdev);
 	int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 
@@ -517,6 +643,15 @@ struct omap_dss_driver {
 
 	int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 	u32 (*get_wss)(struct omap_dss_device *dssdev);
+
+/*HDMI specific */
+	void (*get_edid)(struct omap_dss_device *dssdev);
+	void (*set_custom_edid_timing_code)(struct omap_dss_device *dssdev, int mode, int code);
+	int (*hpd_enable)(struct omap_dss_device *dssdev);
+};
+
+struct pico_platform_data {
+	u8 gpio_intr;
 };
 
 int omap_dss_register_driver(struct omap_dss_driver *);
@@ -540,11 +675,13 @@ struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 
 int omap_dss_get_num_overlays(void);
 struct omap_overlay *omap_dss_get_overlay(int num);
+struct omap_writeback *omap_dss_get_wb(int num);
 
 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
 		u16 *xres, u16 *yres);
 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
-
+bool dispc_go_busy(enum omap_channel channel);
+void dispc_go(enum omap_channel channel);
 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
@@ -556,7 +693,8 @@ int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
 
-void omapdss_dsi_vc_enable_hs(int channel, bool enable);
+void omapdss_dsi_vc_enable_hs(enum omap_dsi_index ix, int channel,
+	bool enable);
 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
 
 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
diff --git a/arch/arm/plat-omap/include/plat/hdmi_lib.h b/arch/arm/plat-omap/include/plat/hdmi_lib.h
new file mode 100644
index 000000000000..bf45e025dc98
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/hdmi_lib.h
@@ -0,0 +1,428 @@
+ /*
+ * hdmi_lib.h
+ *
+ * HDMI driver definition for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _HDMI_H_
+#define _HDMI_H_
+
+#include <linux/string.h>
+
+#define HDMI_WP				0x58006000
+#define HDMI_CORE_SYS		0x58006400
+#define HDMI_CORE_AV		0x58006900
+#define HDMI_HDCP			0x58007000
+
+#define HDMI_WP_AUDIO_DATA		0x8Cul
+
+#define DBG(format, ...) \
+		printk(KERN_DEBUG "hdmi: " format, ## __VA_ARGS__)
+#define ERR(format, ...) \
+	printk(KERN_ERR "hdmi error: " format, ## __VA_ARGS__)
+
+#define BITS_32(in_NbBits) \
+		((((u32)1 << in_NbBits) - 1) | ((u32)1 << in_NbBits))
+
+#define BITFIELD(in_UpBit, in_LowBit) \
+		(BITS_32(in_UpBit) & ~((BITS_32(in_LowBit)) >> 1))
+
+struct hdmi_irq_vector {
+	u8	pllRecal;
+	u8	pllUnlock;
+	u8	pllLock;
+	u8	phyDisconnect;
+	u8	phyConnect;
+	u8	phyShort5v;
+	u8	videoEndFrame;
+	u8	videoVsync;
+	u8	fifoSampleRequest;
+	u8	fifoOverflow;
+	u8	fifoUnderflow;
+	u8	ocpTimeOut;
+	u8	core;
+};
+
+typedef enum HDMI_PhyPwr_label {
+	HDMI_PHYPWRCMD_OFF = 0,
+	HDMI_PHYPWRCMD_LDOON = 1,
+	HDMI_PHYPWRCMD_TXON = 2
+} HDMI_PhyPwr_t, *pHDMI_PhyPwr_t;
+
+typedef enum HDMI_PllPwr_label {
+	HDMI_PLLPWRCMD_ALLOFF = 0,
+	HDMI_PLLPWRCMD_PLLONLY = 1,
+	HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
+	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
+} HDMI_PllPwr_t, *pHDMI_PllPwr_t;
+
+enum hdmi_core_inputbus_width {
+	HDMI_INPUT_8BIT = 0,
+	HDMI_INPUT_10BIT = 1,
+	HDMI_INPUT_12BIT = 2
+};
+
+enum hdmi_core_dither_trunc {
+	HDMI_OUTPUTTRUNCATION_8BIT = 0,
+	HDMI_OUTPUTTRUNCATION_10BIT = 1,
+	HDMI_OUTPUTTRUNCATION_12BIT = 2,
+	HDMI_OUTPUTDITHER_8BIT = 3,
+	HDMI_OUTPUTDITHER_10BIT = 4,
+	HDMI_OUTPUTDITHER_12BIT = 5
+};
+
+enum hdmi_core_deepcolor_ed {
+	HDMI_DEEPCOLORPACKECTDISABLE = 0,
+	HDMI_DEEPCOLORPACKECTENABLE = 1
+};
+
+enum hdmi_core_packet_mode {
+	HDMI_PACKETMODERESERVEDVALUE = 0,
+	HDMI_PACKETMODE24BITPERPIXEL = 4,
+	HDMI_PACKETMODE30BITPERPIXEL = 5,
+	HDMI_PACKETMODE36BITPERPIXEL = 6,
+	HDMI_PACKETMODE48BITPERPIXEL = 7
+};
+
+enum hdmi_core_hdmi_dvi {
+	HDMI_DVI	= 0,
+	HDMI_HDMI	= 1
+};
+
+enum hdmi_core_tclkselclkmult {
+	FPLL05IDCK  = 0,
+	FPLL10IDCK  = 1,
+	FPLL20IDCK  = 2,
+	FPLL40IDCK  = 3
+};
+
+struct hdmi_core_video_config_t {
+	enum hdmi_core_inputbus_width	CoreInputBusWide;
+	enum hdmi_core_dither_trunc 	CoreOutputDitherTruncation;
+	enum hdmi_core_deepcolor_ed		CoreDeepColorPacketED;
+	enum hdmi_core_packet_mode		CorePacketMode;
+	enum hdmi_core_hdmi_dvi			CoreHdmiDvi;
+	enum hdmi_core_tclkselclkmult	CoreTclkSelClkMult;
+};
+
+enum hdmi_core_fs {
+	FS_32000 = 0,
+	FS_44100 = 1
+};
+
+enum hdmi_core_layout {
+	LAYOUT_2CH = 0,
+	LAYOUT_8CH = 1
+};
+
+enum hdmi_core_cts_mode {
+	CTS_MODE_HW = 0,
+	CTS_MODE_SW = 1
+};
+
+enum hdmi_core_packet_ctrl {
+	PACKETENABLE = 1,
+	PACKETDISABLE = 0,
+	PACKETREPEATON = 1,
+	PACKETREPEATOFF = 0
+};
+
+/* INFOFRAME_AVI_ definations */
+enum hdmi_core_infoframe {
+	INFOFRAME_AVI_DB1Y_RGB = 0,
+	INFOFRAME_AVI_DB1Y_YUV422 = 1,
+	INFOFRAME_AVI_DB1Y_YUV444 = 2,
+	INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
+	INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
+	INFOFRAME_AVI_DB1B_NO = 0,
+	INFOFRAME_AVI_DB1B_VERT = 1,
+	INFOFRAME_AVI_DB1B_HORI = 2,
+	INFOFRAME_AVI_DB1B_VERTHORI = 3,
+	INFOFRAME_AVI_DB1S_0 = 0,
+	INFOFRAME_AVI_DB1S_1 = 1,
+	INFOFRAME_AVI_DB1S_2 = 2,
+	INFOFRAME_AVI_DB2C_NO = 0,
+	INFOFRAME_AVI_DB2C_ITU601 = 1,
+	INFOFRAME_AVI_DB2C_ITU709 = 2,
+	INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
+	INFOFRAME_AVI_DB2M_NO = 0,
+	INFOFRAME_AVI_DB2M_43 = 1,
+	INFOFRAME_AVI_DB2M_169 = 2,
+	INFOFRAME_AVI_DB2R_SAME = 8,
+	INFOFRAME_AVI_DB2R_43 = 9,
+	INFOFRAME_AVI_DB2R_169 = 10,
+	INFOFRAME_AVI_DB2R_149 = 11,
+	INFOFRAME_AVI_DB3ITC_NO = 0,
+	INFOFRAME_AVI_DB3ITC_YES = 1,
+	INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
+	INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
+	INFOFRAME_AVI_DB3Q_DEFAULT = 0,
+	INFOFRAME_AVI_DB3Q_LR = 1,
+	INFOFRAME_AVI_DB3Q_FR = 2,
+	INFOFRAME_AVI_DB3SC_NO = 0,
+	INFOFRAME_AVI_DB3SC_HORI = 1,
+	INFOFRAME_AVI_DB3SC_VERT = 2,
+	INFOFRAME_AVI_DB3SC_HORIVERT = 3,
+	INFOFRAME_AVI_DB5PR_NO = 0,
+	INFOFRAME_AVI_DB5PR_2 = 1,
+	INFOFRAME_AVI_DB5PR_3 = 2,
+	INFOFRAME_AVI_DB5PR_4 = 3,
+	INFOFRAME_AVI_DB5PR_5 = 4,
+	INFOFRAME_AVI_DB5PR_6 = 5,
+	INFOFRAME_AVI_DB5PR_7 = 6,
+	INFOFRAME_AVI_DB5PR_8 = 7,
+	INFOFRAME_AVI_DB5PR_9 = 8,
+	INFOFRAME_AVI_DB5PR_10 = 9
+};
+
+struct hdmi_core_infoframe_avi {
+	u8		db1y_rgb_yuv422_yuv444;
+	u8		db1a_active_format_off_on;
+	u8		db1b_no_vert_hori_verthori;
+	u8		db1s_0_1_2;
+	u8		db2c_no_itu601_itu709_extented;
+	u8		db2m_no_43_169;
+	u8		db2r_same_43_169_149;
+	u8		db3itc_no_yes;
+	u8		db3ec_xvyuv601_xvyuv709;
+	u8		db3q_default_lr_fr;
+	u8		db3sc_no_hori_vert_horivert;
+	u8		db4vic_videocode;
+	u8		db5pr_no_2_3_4_5_6_7_8_9_10;
+	u16		db6_7_lineendoftop;
+	u16		db8_9_linestartofbottom;
+	u16		db10_11_pixelendofleft;
+	u16		db12_13_pixelstartofright;
+};
+
+struct hdmi_core_packet_enable_repeat {
+	u32		AudioPacketED;
+	u32		AudioPacketRepeat;
+	u32		AVIInfoFrameED;
+	u32		AVIInfoFrameRepeat;
+	u32		GeneralcontrolPacketED;
+	u32		GeneralcontrolPacketRepeat;
+	u32		GenericPacketED;
+	u32		GenericPacketRepeat;
+};
+
+enum hdmi_stereo_channel {
+	HDMI_STEREO_NOCHANNEL = 0,
+	HDMI_STEREO_ONECHANNELS = 1,
+	HDMI_STEREO_TWOCHANNELS = 2,
+	HDMI_STEREO_THREECHANNELS = 3,
+	HDMI_STEREO_FOURCHANNELS = 4
+};
+
+enum hdmi_cea_code {
+	HDMI_CEA_CODE_00 = 0x0,
+	HDMI_CEA_CODE_01 = 0x1,
+	HDMI_CEA_CODE_02 = 0x2,
+	HDMI_CEA_CODE_03 = 0x3,
+	HDMI_CEA_CODE_04 = 0x4,
+	HDMI_CEA_CODE_05 = 0x5,
+	HDMI_CEA_CODE_06 = 0x6,
+	HDMI_CEA_CODE_07 = 0x7,
+	HDMI_CEA_CODE_08 = 0x8,
+	HDMI_CEA_CODE_09 = 0x9,
+	HDMI_CEA_CODE_0A = 0xA,
+	HDMI_CEA_CODE_0B = 0xB,
+	HDMI_CEA_CODE_0C = 0xC,
+	HDMI_CEA_CODE_0D = 0xD,
+	HDMI_CEA_CODE_0E = 0xE,
+	HDMI_CEA_CODE_0F = 0xF,
+	HDMI_CEA_CODE_10 = 0x10,
+	HDMI_CEA_CODE_11 = 0x11,
+	HDMI_CEA_CODE_12 = 0x12,
+	HDMI_CEA_CODE_13 = 0x13,
+	HDMI_CEA_CODE_14 = 0x14,
+	HDMI_CEA_CODE_15 = 0x15,
+	HDMI_CEA_CODE_16 = 0x16,
+	HDMI_CEA_CODE_17 = 0x17,
+	HDMI_CEA_CODE_18 = 0x18,
+	HDMI_CEA_CODE_19 = 0x19,
+	HDMI_CEA_CODE_1A = 0x1A,
+	HDMI_CEA_CODE_1B = 0x1B,
+	HDMI_CEA_CODE_1C = 0x1C,
+	HDMI_CEA_CODE_1D = 0x1D,
+	HDMI_CEA_CODE_1E = 0x1E,
+	HDMI_CEA_CODE_1F = 0x1F,
+	HDMI_CEA_CODE_20 = 0x20,
+	HDMI_CEA_CODE_21 = 0x21,
+	HDMI_CEA_CODE_22 = 0x22,
+	HDMI_CEA_CODE_23 = 0x23,
+	HDMI_CEA_CODE_24 = 0x24,
+	HDMI_CEA_CODE_25 = 0x25,
+	HDMI_CEA_CODE_26 = 0x26
+};
+
+enum hdmi_iec_format {
+	HDMI_AUDIO_FORMAT_LPCM = 0,
+	HDMI_AUDIO_FORMAT_IEC = 1
+};
+
+enum hdmi_audio_justify {
+	HDMI_AUDIO_JUSTIFY_LEFT = 0,
+	HDMI_AUDIO_JUSTIFY_RIGHT = 1
+};
+
+enum hdmi_sample_order {
+	HDMI_SAMPLE_RIGHT_FIRST = 0,
+	HDMI_SAMPLE_LEFT_FIRST = 1
+};
+
+enum hdmi_sample_perword {
+	HDMI_ONEWORD_ONE_SAMPLE = 0,
+	HDMI_ONEWORD_TWO_SAMPLES = 1
+};
+
+enum hdmi_sample_size {
+	HDMI_SAMPLE_16BITS = 0,
+	HDMI_SAMPLE_24BITS = 1
+};
+
+struct hdmi_audio_format {
+	enum hdmi_stereo_channel	stereo_channel_enable;
+	enum hdmi_cea_code		audio_channel_location;
+	enum hdmi_iec_format		iec;
+	enum hdmi_audio_justify		justify;
+	enum hdmi_sample_order		left_before;
+	enum hdmi_sample_perword	sample_number;
+	enum hdmi_sample_size		sample_size;
+};
+
+enum hdmi_dma_irq {
+	HDMI_THRESHOLD_DMA = 0,
+	HDMI_THRESHOLD_IRQ = 1
+};
+
+enum hdmi_block_start_end {
+	HDMI_BLOCK_STARTEND_ON = 0,
+	HDMI_BLOCK_STARTEND_OFF = 1
+};
+
+struct hdmi_audio_dma {
+	u8				dma_transfer;
+	u8				block_size;
+	enum hdmi_dma_irq		dma_or_irq;
+	u16				threshold_value;
+	enum hdmi_block_start_end	block_start_end;
+};
+
+enum hdmi_packing_mode {
+	HDMI_PACK_10b_RGB_YUV444 = 0,
+	HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
+	HDMI_PACK_20b_YUV422 = 2,
+	HDMI_PACK_ALREADYPACKED = 7
+};
+
+struct hdmi_video_format {
+	enum hdmi_packing_mode	packingMode;
+	u32	linePerPanel;
+	u32	pixelPerLine;
+};
+
+struct hdmi_video_interface {
+	int	vSyncPolarity;
+	int	hSyncPolarity;
+	int	interlacing;
+	int	timingMode;
+};
+
+struct hdmi_video_timing {
+	u32	horizontalBackPorch;
+	u32	horizontalFrontPorch;
+	u32	horizontalSyncPulse;
+	u32	verticalBackPorch;
+	u32	verticalFrontPorch;
+	u32	verticalSyncPulse;
+};
+
+typedef struct HDMI_Timing_label {
+	u32	pixelPerLine;
+	u32	linePerPanel;
+	u32	horizontalBackPorch;
+	u32	horizontalFrontPorch;
+	u32	horizontalSyncPulse;
+	u32	verticalBackPorch;
+	u32	verticalFrontPorch;
+	u32	verticalSyncPulse;
+	u32	pplclk;
+} HDMI_Timing_t, *pHDMI_Timing_t;
+
+struct hdmi_config {
+	u16 ppl;	/* pixel per line */
+	u16 lpp;	/* line per panel */
+	u32 pixel_clock;
+	u16 hsw;	/* Horizontal synchronization pulse width */
+	u16 hfp;	/* Horizontal front porch */
+	u16 hbp;	/* Horizontal back porch */
+	u16 vsw;	/* Vertical synchronization pulse width */
+	u16 vfp;	/* Vertical front porch */
+	u16 vbp;	/* Vertical back porch */
+	u16 interlace;
+	u16 h_pol;
+	u16 v_pol;
+	u16 hdmi_dvi;
+	u16 video_format;
+};
+
+enum hdmi_core_if_fs {
+	IF_FS_NO     = 0x0,
+	IF_FS_32000  = 0x1,
+	IF_FS_44100  = 0x2,
+	IF_FS_48000  = 0x3,
+	IF_FS_88200  = 0x4,
+	IF_FS_96000  = 0x5,
+	IF_FS_176400 = 0x6,
+	IF_FS_192000 = 0x7
+};
+
+enum hdmi_core_if_sample_size{
+	IF_NO_PER_SAMPLE = 0x0,
+	IF_16BIT_PER_SAMPLE = 0x1,
+	IF_20BIT_PER_SAMPLE = 0x2,
+	IF_24BIT_PER_SAMPLE = 0x3
+};
+
+struct hdmi_core_audio_config {
+	enum hdmi_core_fs		fs; /* 0=32KHz - 1=44.1KHz */
+	u32				n;
+	u32				cts;
+	u32				aud_par_busclk;
+	enum hdmi_core_layout		layout; /* 0: 2Ch - 1: 8Ch */
+	enum hdmi_core_cts_mode		cts_mode; /* 0: HW  - 1: SW*/
+	enum hdmi_core_if_fs		if_fs;
+	u32				if_channel_number;
+	enum hdmi_core_if_sample_size	if_sample_size;
+	enum hdmi_cea_code		if_audio_channel_location;
+ };
+
+/* Function prototype */
+int HDMI_W1_StopVideoFrame(u32);
+int HDMI_W1_StartVideoFrame(u32);
+int HDMI_W1_SetWaitPhyPwrState(u32 name, HDMI_PhyPwr_t param);
+int HDMI_W1_SetWaitPllPwrState(u32 name, HDMI_PllPwr_t param);
+int HDMI_W1_SetWaitSoftReset(void);
+int hdmi_w1_wrapper_disable(u32);
+int hdmi_w1_wrapper_enable(u32);
+int hdmi_w1_stop_audio_transfer(u32);
+int hdmi_w1_start_audio_transfer(u32);
+int HDMI_CORE_DDC_READEDID(u32 Core, u8 *data);
+int DSS_HDMI_CONFIG(HDMI_Timing_t timings, u32 video_format, u32 mode);
+void HDMI_W1_HPD_handler(int *r);
+int hdmi_lib_init(void);
+void hdmi_lib_exit(void);
+
+#endif
+
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 128b549c2796..55e24a4127cf 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -205,6 +205,7 @@
 #define L4_PER_44XX_VIRT	(L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_PER_44XX_SIZE	SZ_4M
 
+#define L4_ABE_44XX_BASE	0x49000000
 #define L4_ABE_44XX_PHYS	L4_ABE_44XX_BASE
 						/* 0x49000000 --> 0xfb000000 */
 #define L4_ABE_44XX_VIRT	(L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 0752af9d099e..a45a0b1c348f 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -13,6 +13,9 @@
 #ifndef __MACH_IOMMU_H
 #define __MACH_IOMMU_H
 
+#include <linux/device.h>
+#include <linux/cdev.h>
+
 struct iotlb_entry {
 	u32 da;
 	u32 pa;
@@ -50,6 +53,8 @@ struct iommu {
 	int (*isr)(struct iommu *obj);
 
 	void *ctx; /* iommu context: registres saved area */
+	struct cdev cdev;
+	int minor;
 };
 
 struct cr_regs {
@@ -80,6 +85,7 @@ struct iommu_functions {
 
 	int (*enable)(struct iommu *obj);
 	void (*disable)(struct iommu *obj);
+	void (*set_twl)(struct iommu *obj, bool on);
 	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
 
 	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
@@ -104,6 +110,11 @@ struct iommu_platform_data {
 	const int nr_tlb_entries;
 };
 
+#define IOMMU_IOC_MAGIC		'I'
+
+#define IOMMU_IOCSETTLBENT	_IO(IOMMU_IOC_MAGIC, 0)
+
+
 #if defined(CONFIG_ARCH_OMAP1)
 #error "iommu for this processor not implemented yet"
 #else
@@ -143,6 +154,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
 extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
 
 extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iommu_set_twl(struct iommu *obj, bool on);
 extern void flush_iotlb_page(struct iommu *obj, u32 da);
 extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);
@@ -165,4 +177,5 @@ extern int foreach_iommu_device(void *data,
 extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
 extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
 
+extern int iommu_get_plat_data_size(void);
 #endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index 729166b76a7c..0486d64c24f7 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -7,6 +7,7 @@
 #include <linux/workqueue.h>
 #include <linux/blkdev.h>
 #include <linux/interrupt.h>
+#include <linux/kfifo.h>
 
 typedef u32 mbox_msg_t;
 struct omap_mbox;
@@ -19,6 +20,8 @@ typedef int __bitwise omap_mbox_type_t;
 #define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
 #define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
 
+#define MBOX_KFIFO_SIZE        (256)
+
 struct omap_mbox_ops {
 	omap_mbox_type_t	type;
 	int		(*startup)(struct omap_mbox *mbox);
@@ -42,7 +45,7 @@ struct omap_mbox_ops {
 
 struct omap_mbox_queue {
 	spinlock_t		lock;
-	struct request_queue	*queue;
+	struct kfifo            fifo;
 	struct work_struct	work;
 	struct tasklet_struct	tasklet;
 	int	(*callback)(void *);
diff --git a/arch/arm/plat-omap/include/plat/mcpdm.h b/arch/arm/plat-omap/include/plat/mcpdm.h
new file mode 100644
index 000000000000..3c7c783c36e1
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/mcpdm.h
@@ -0,0 +1 @@
+#include "../../../../../sound/soc/omap/mcpdm.h"
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index f5a08367cd0c..ac33cc848097 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -20,6 +20,10 @@
 #include <plat/board.h>
 #include <plat/omap_hwmod.h>
 
+#ifdef CONFIG_TIWLAN_SDIO
+#include <linux/mmc/card.h>
+#endif
+
 #define OMAP15XX_NR_MMC		1
 #define OMAP16XX_NR_MMC		2
 #define OMAP1_MMC_SIZE		0x080
@@ -50,6 +54,13 @@
 #define MMC_SUPPORT_18V_3V		(1 << 0)
 #define MMC_SUPPORT_3V			(1 << 1)
 
+#ifdef CONFIG_TIWLAN_SDIO
+struct embedded_sdio_data {
+struct sdio_cis cis;
+struct sdio_embedded_func *funcs;
+unsigned int quirks;
+};
+#endif
 
 struct mmc_dev_attr {
 	u8 flags;
@@ -151,6 +162,13 @@ struct omap_mmc_platform_data {
 
 		unsigned int ban_openended:1;
 
+#ifdef CONFIG_TIWLAN_SDIO
+                struct embedded_sdio_data *embedded_sdio;
+                int (*register_status_notify)
+                        (void (*callback)(int card_present, void *dev_id),
+                        void *dev_id);
+#endif
+
 	} slots[OMAP_MMC_MAX_SLOTS];
 };
 
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index 76832d387ea6..8b3f12ff5cbc 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -49,5 +49,8 @@
 #define OMAP44XX_MAILBOX_BASE		(L4_44XX_BASE + 0xF4000)
 #define OMAP44XX_HSUSB_OTG_BASE		(L4_44XX_BASE + 0xAB000)
 
+#define OMAP4_MMU1_BASE			0x55082000
+#define OMAP4_MMU2_BASE			0x4A066000
+
 #endif /* __ASM_ARCH_OMAP44XX_H */
 
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
new file mode 100644
index 000000000000..351553d18fc4
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/remoteproc.h
@@ -0,0 +1,75 @@
+/*
+ * OMAP Remote Processor driver
+ *
+ * Copyright (C) 2010 Texas Instruments Inc.
+ *
+ * Written by Ohad Ben-Cohen <ohad@wizery.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef REMOTEPROC_H
+#define REMOTEPROC_H
+
+#include <linux/ioctl.h>
+#include <linux/cdev.h>
+
+#define RPROC_IOC_MAGIC		'P'
+
+#define RPROC_IOCMONITOR	_IO(RPROC_IOC_MAGIC, 0)
+#define RPROC_IOCSTART		_IO(RPROC_IOC_MAGIC, 1)
+#define RPROC_IOCSTOP		_IO(RPROC_IOC_MAGIC, 2)
+#define RPROC_IOCGETSTATE	_IOR(RPROC_IOC_MAGIC, 3, int)
+
+#define RPROC_IOC_MAXNR		(3)
+
+struct omap_rproc;
+
+struct omap_rproc_ops {
+	int (*startup)(struct omap_rproc *rproc);
+	int (*shutdown)(struct omap_rproc *rproc);
+	int (*start)(struct omap_rproc *rproc);
+	int (*stop)(struct omap_rproc *rproc);
+	int (*get_state)(struct omap_rproc *rproc);
+};
+
+struct omap_rproc_clk_t {
+	void *clk_handle;
+	const char *dev_id;
+	const char *con_id;
+};
+
+struct omap_rproc_platform_data {
+	struct omap_rproc_ops *ops;
+	char *name;
+	char *oh_name;
+};
+
+struct omap_rproc {
+	struct device *dev;
+	struct cdev cdev;
+	atomic_t count;
+	int state;
+	int minor;
+};
+
+extern struct omap_rproc_platform_data *remoteproc_get_plat_data(void);
+extern int remoteproc_get_plat_data_size(void);
+
+struct omap_rproc *rproc_get(const char *name);
+void rproc_put(struct omap_rproc *obj);
+
+#endif /* REMOTEPROC_H */
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h
index d8a03ced3b10..3792bdea2f6d 100644
--- a/arch/arm/plat-omap/include/plat/vrfb.h
+++ b/arch/arm/plat-omap/include/plat/vrfb.h
@@ -35,6 +35,7 @@ struct vrfb {
 	bool yuv_mode;
 };
 
+#ifdef CONFIG_OMAP2_VRFB
 extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
 extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
 extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
@@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
 extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
 extern void omap_vrfb_restore_context(void);
 
+#else
+static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
+static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
+static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
+		u8 bytespp) {}
+static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
+		{ return 0; }
+static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
+		{ return 0; }
+static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+		u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
+static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
+		{ return 0; }
+static inline void omap_vrfb_restore_context(void) {}
+#endif
 #endif /* __VRFB_H */
diff --git a/arch/arm/plat-omap/include/plat/wifi_tiwlan.h b/arch/arm/plat-omap/include/plat/wifi_tiwlan.h
new file mode 100644
index 000000000000..b0332b04ddc9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/wifi_tiwlan.h
@@ -0,0 +1,23 @@
+/* mach/wifi_tiwlan.h
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef _LINUX_WIFI_TIWLAN_H_
+#define _LINUX_WIFI_TIWLAN_H_
+
+struct wifi_platform_data {
+	int (*set_power)(int val);
+	int (*set_reset)(int val);
+	int (*set_carddetect)(int val);
+	void *(*mem_prealloc)(int section, unsigned long size);
+};
+
+#endif
diff --git a/arch/arm/plat-omap/include/syslink/GlobalTypes.h b/arch/arm/plat-omap/include/syslink/GlobalTypes.h
new file mode 100644
index 000000000000..6cd959cde952
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/GlobalTypes.h
@@ -0,0 +1,154 @@
+/*
+ * GlobalTypes.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef __GLOBALTYPES_H
+#define __GLOBALTYPES_H
+
+#define  REG volatile
+
+/*
+ * Definition: RET_CODE_BASE
+ *
+ * DESCRIPTION:  Base value for return code offsets
+ *
+ *
+ */
+#define RET_CODE_BASE        0
+
+/*
+ * TYPE: ReturnCode_t
+ *
+ * DESCRIPTION:  Return codes to be returned by all library functions
+ *
+ *
+ */
+enum ReturnCode_label {
+RET_OK = 0,
+RET_FAIL = -1,
+RET_BAD_NULL_PARAM = -2,
+RET_PARAM_OUT_OF_RANGE = -3,
+RET_INVALID_ID = -4,
+RET_EMPTY = -5,
+RET_FULL = -6,
+RET_TIMEOUT = -7,
+RET_INVALID_OPERATION = -8,
+/* Add new error codes at end of above list */
+RET_NUM_RET_CODES     /* this should ALWAYS be LAST entry */
+};
+
+
+
+/*
+ * MACRO: RD_MEM_32_VOLATILE, WR_MEM_32_VOLATILE
+ *
+ * DESCRIPTION:  32 bit register access macros
+ *
+ *
+ */
+#define RD_MEM_32_VOLATILE(addr) \
+((unsigned long)(*((REG unsigned long *)(addr))))
+
+#define WR_MEM_32_VOLATILE(addr, data) \
+(*((REG unsigned long *)(addr)) = (unsigned long)(data))
+
+
+
+
+#ifdef CHECK_INPUT_PARAMS
+/*
+ * MACRO: CHECK_INPUT_PARAMS
+ *
+ * DESCRIPTION:  Checks an input code and returns a specified value if code is
+ *               invalid value, also writes spy value if error found.
+ *
+ * NOTE:         Can be disabled to save HW cycles.
+ *
+ *
+ */
+#define CHECK_INPUT_PARAM(actualValue, invalidValue,  \
+returnCodeIfMismatch, spyCodeIfMisMatch) do {\
+	if ((invalidValue) == (actualValue)) {\
+		RES_Set((spyCodeIfMisMatch));\
+		return returnCodeIfMismatch; \
+	} \
+} while (0)
+
+/*
+ * MACRO: CHECK_INPUT_RANGE
+ *
+ * DESCRIPTION:  Checks an input value and returns a specified value if not in
+ *               specified range, also writes spy value if error found.
+ *
+* NOTE:         Can be disabled to save HW cycles.
+ *
+ *
+ */
+#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue, \
+returnCodeIfMismatch, spyCodeIfMisMatch) do {\
+	if (((actualValue) < (minValidValue)) || \
+		((actualValue) > (maxValidValue))) {\
+		RES_Set((spyCodeIfMisMatch));\
+		return returnCodeIfMismatch; \
+	} \
+} while (0)
+
+/*
+ * MACRO: CHECK_INPUT_RANGE_MIN0
+ *
+ * DESCRIPTION:  Checks an input value and returns a
+ * specified value if not in
+ * specified range, also writes spy value if error found.
+ * The minimum
+ * value is 0.
+ *
+ * NOTE:         Can be disabled to save HW cycles.
+ *
+ *
+ */
+#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue, \
+returnCodeIfMismatch, spyCodeIfMisMatch) do {\
+	if ((actualValue) > (maxValidValue)) {\
+		RES_Set((spyCodeIfMisMatch));\
+		return returnCodeIfMismatch; \
+	} \
+} while (0)
+
+#else
+
+#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\
+spyCodeIfMisMatch)
+
+#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue, \
+returnCodeIfMismatch)
+
+#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue, \
+returnCodeIfMismatch, spyCodeIfMisMatch)
+
+#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue , \
+maxValidValue, returnCodeIfMismatch)
+
+#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue, \
+returnCodeIfMismatch, spyCodeIfMisMatch)
+
+#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, \
+maxValidValue, returnCodeIfMismatch)
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif	/* __GLOBALTYPES_H */
diff --git a/arch/arm/plat-omap/include/syslink/MBXAccInt.h b/arch/arm/plat-omap/include/syslink/MBXAccInt.h
new file mode 100644
index 000000000000..84e333d0d5da
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/MBXAccInt.h
@@ -0,0 +1,550 @@
+/*
+ * MBXAccInt.h
+ *
+ * Notify mailbox driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef _MLB_ACC_INT_H
+#define _MLB_ACC_INT_H
+
+
+/*
+ * EXPORTED DEFINITIONS
+ *
+ */
+
+
+#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET (unsigned long)(0x0040)
+#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP   (unsigned long)(0x0004)
+#define MLB_MAILBOX_MESSAGE___REGSET_0_15_BANKS  (unsigned long)(16)
+
+/* Register offset address definitions relative
+to register set MAILBOX_MESSAGE___REGSET_0_15 */
+
+#define MLB_MAILBOX_MESSAGE___0_15_OFFSET (unsigned long)(0x0)
+
+
+/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15
+address offset, bank address increment and number of banks */
+
+#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET (unsigned long)(0x0080)
+#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP   (unsigned long)(0x0004)
+#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_BANKS (unsigned long)(16)
+
+/* Register offset address definitions relative to
+register set MAILBOX_FIFOSTATUS___REGSET_0_15 */
+
+#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET  (unsigned long)(0x0)
+
+
+/* Register set MAILBOX_MSGSTATUS___REGSET_0_15
+address offset, bank address increment and number of banks */
+
+#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET (unsigned long)(0x00c0)
+#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP   (unsigned long)(0x0004)
+#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_BANKS  (unsigned long)(16)
+
+/* Register offset address definitions relative to
+register set MAILBOX_MSGSTATUS___REGSET_0_15 */
+
+#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET  (unsigned long)(0x0)
+
+
+/*Register set MAILBOX_IRQSTATUS___REGSET_0_3 address
+offset, bank address increment and number of banks */
+
+#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET (unsigned long)(0x0100)
+#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP (unsigned long)(0x0008)
+#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_BANKS (unsigned long)(4)
+
+#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET  (unsigned long)(0x0104)
+#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP    (unsigned long)(0x0010)
+#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_BANKS   (unsigned long)(4)
+
+/* Register offset address definitions relative to
+register set MAILBOX_IRQSTATUS___REGSET_0_3 */
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET (unsigned long)(0x0)
+
+
+/* Register set MAILBOX_IRQENABLE___REGSET_0_3
+address offset, bank address increment and number of banks */
+
+#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET (unsigned long)(0x0104)
+#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP (unsigned long)(0x0008)
+#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_BANKS (unsigned long)(4)
+
+#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET  (unsigned long)(0x0108)
+#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP    (unsigned long)(0x0010)
+#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_BANKS   (unsigned long)(4)
+
+#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_OFFSET   (unsigned long)(0x010C)
+#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_STEP     (unsigned long)(0x0010)
+#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_BANKS    (unsigned long)(4)
+
+/* Register offset address definitions relative to register
+set MAILBOX_IRQENABLE___REGSET_0_3 */
+
+#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET (unsigned long)(0x0)
+
+
+/* Register offset address definitions */
+
+#define MLB_MAILBOX_REVISION_OFFSET  (unsigned long)(0x0)
+#define MLB_MAILBOX_SYSCONFIG_OFFSET (unsigned long)(0x10)
+#define MLB_MAILBOX_SYSSTATUS_OFFSET (unsigned long)(0x14)
+
+
+/* Bitfield mask and offset declarations */
+
+#define MLB_MAILBOX_REVISION_Rev_MASK  (unsigned long)(0xff)
+#define MLB_MAILBOX_REVISION_Rev_OFFSET  (unsigned long)(0)
+
+#define MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK  (unsigned long)(0x100)
+#define MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET (unsigned long)(8)
+
+#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK  (unsigned long)(0x18)
+#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET (unsigned long)(3)
+
+#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK   (unsigned long)(0x2)
+#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET (unsigned long)(1)
+
+#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK    (unsigned long)(0x1)
+#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET  (unsigned long)(0)
+
+#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK   (unsigned long)(0x1)
+#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET (unsigned long)(0)
+
+#define MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK  \
+(unsigned long)(0xffffffff)
+
+#define MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET (unsigned long)(0)
+
+#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK  (unsigned long)(0x1)
+#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET (unsigned long)(0)
+
+#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK   (unsigned long)(0x7f)
+#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET (unsigned long)(0)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK \
+(unsigned long)(0x80000000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET \
+(unsigned long)(31)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK  \
+(unsigned long)(0x40000000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET \
+(unsigned long)(30)
+
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK \
+(unsigned long)(0x20000000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET \
+(unsigned long)(29)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK  \
+(unsigned long)(0x10000000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET \
+(unsigned long)(28)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK  \
+(unsigned long)(0x8000000)
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET \
+(unsigned long)(27)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK   \
+(unsigned long)(0x4000000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET  \
+(unsigned long)(26)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK   \
+(unsigned long)(0x2000000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET \
+(unsigned long)(25)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK \
+(unsigned long)(0x1000000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET \
+(unsigned long)(24)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK  \
+(unsigned long)(0x800000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET \
+(unsigned long)(23)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK    \
+(unsigned long)(0x400000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET  \
+(unsigned long)(22)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK    \
+(unsigned long)(0x200000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET  \
+(unsigned long)(21)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK \
+(unsigned long)(0x100000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET \
+(unsigned long)(20)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK \
+(unsigned long)(0x80000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET \
+(unsigned long)(19)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK \
+(unsigned long)(0x40000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET \
+(unsigned long)(18)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK \
+(unsigned long)(0x20000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET \
+(unsigned long)(17)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK  \
+(unsigned long)(0x10000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET  \
+(unsigned long)(16)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK   \
+(unsigned long)(0x8000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET  \
+(unsigned long)(15)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK     \
+(unsigned long)(0x4000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET \
+(unsigned long)(14)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK  \
+(unsigned long)(0x2000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET \
+(unsigned long)(13)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK \
+(unsigned long)(0x1000)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET \
+(unsigned long)(12)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK  \
+(unsigned long)(0x800)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET \
+(unsigned long)(11)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK   \
+(unsigned long)(0x400)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET \
+(unsigned long)(10)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK  \
+(unsigned long)(0x200)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET  \
+(unsigned long)(9)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK \
+(unsigned long)(0x100)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET \
+(unsigned long)(8)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK  \
+(unsigned long)(0x80)
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET \
+(unsigned long)(7)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK  \
+(unsigned long)(0x40)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET \
+(unsigned long)(6)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK  \
+(unsigned long)(0x20)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET  \
+(unsigned long)(5)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK \
+(unsigned long)(0x10)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET \
+(unsigned long)(4)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK  \
+(unsigned long)(0x8)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET  \
+(unsigned long)(3)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK  \
+(unsigned long)(0x4)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET \
+(unsigned long)(2)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK  \
+(unsigned long)(0x2)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET \
+(unsigned long)(1)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK    \
+(unsigned long)(0x1)
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET  \
+(unsigned long)(0)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK  \
+(unsigned long)(0x80000000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET  \
+(unsigned long)(31)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK \
+(unsigned long)(0x40000000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET \
+(unsigned long)(30)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK \
+(unsigned long)(0x20000000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET \
+(unsigned long)(29)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK \
+(unsigned long)(0x10000000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET \
+(unsigned long)(28)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK \
+(unsigned long)(0x8000000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET \
+(unsigned long)(27)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK \
+(unsigned long)(0x4000000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET \
+(unsigned long)(26)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK  \
+(unsigned long)(0x2000000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET \
+(unsigned long)(25)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK  \
+(unsigned long)(0x1000000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET \
+(unsigned long)(24)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK  \
+(unsigned long)(0x800000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET \
+(unsigned long)(23)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK \
+(unsigned long)(0x400000)
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET \
+(unsigned long)(22)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK \
+(unsigned long)(0x200000)
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET \
+(unsigned long)(21)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK  \
+(unsigned long)(0x100000)
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET \
+(unsigned long)(20)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK  \
+(unsigned long)(0x80000)
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET \
+(unsigned long)(19)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK \
+(unsigned long)(0x40000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET \
+(unsigned long)(18)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK \
+(unsigned long)(0x20000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET \
+(unsigned long)(17)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK \
+(unsigned long)(0x10000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET \
+(unsigned long)(16)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK \
+(unsigned long)(0x8000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET \
+(unsigned long)(15)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK \
+(unsigned long)(0x4000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET \
+(unsigned long)(14)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK \
+(unsigned long)(0x2000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET \
+(unsigned long)(13)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK \
+(unsigned long)(0x1000)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET \
+(unsigned long)(12)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK \
+(unsigned long)(0x800)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET \
+(unsigned long)(11)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK \
+(unsigned long)(0x400)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET \
+(unsigned long)(10)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK  \
+(unsigned long)(0x200)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET  \
+(unsigned long)(9)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK   \
+(unsigned long)(0x100)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET  \
+(unsigned long)(8)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK  \
+(unsigned long)(0x80)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET \
+(unsigned long)(7)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK  \
+(unsigned long)(0x40)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET  \
+(unsigned long)(6)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK  \
+(unsigned long)(0x20)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET \
+(unsigned long)(5)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK  \
+(unsigned long)(0x10)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET \
+(unsigned long)(4)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK \
+(unsigned long)(0x8)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET \
+(unsigned long)(3)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK \
+(unsigned long)(0x4)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET \
+(unsigned long)(2)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK \
+(unsigned long)(0x2)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET \
+(unsigned long)(1)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK \
+(unsigned long)(0x1)
+
+#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET \
+(unsigned long)(0)
+
+
+/*
+ * EXPORTED TYPES
+ *
+ */
+
+/* The following type definitions
+represent the enumerated values for each bitfield */
+
+enum MLBMAILBOX_SYSCONFIGSIdleModeE {
+	MLBMAILBOX_SYSCONFIGSIdleModeb00 = 0x0000,
+	MLBMAILBOX_SYSCONFIGSIdleModeb01 = 0x0001,
+	MLBMAILBOX_SYSCONFIGSIdleModeb10 = 0x0002,
+	MLBMAILBOX_SYSCONFIGSIdleModeb11 = 0x0003
+};
+
+enum MLBMAILBOX_SYSCONFIGSoftResetE {
+	MLBMAILBOX_SYSCONFIGSoftResetb0 = 0x0000,
+	MLBMAILBOX_SYSCONFIGSoftResetb1 = 0x0001
+};
+
+enum MLBMAILBOX_SYSCONFIGAutoIdleE {
+	MLBMAILBOX_SYSCONFIGAutoIdleb0 = 0x0000,
+	MLBMAILBOX_SYSCONFIGAutoIdleb1 = 0x0001
+};
+
+enum MLBMAILBOX_SYSSTATUSResetDoneE {
+	MLBMAILBOX_SYSSTATUSResetDonerstongoing = 0x0000,
+	MLBMAILBOX_SYSSTATUSResetDonerstcomp = 0x0001
+};
+
+#endif /* _MLB_ACC_INT_H */
diff --git a/arch/arm/plat-omap/include/syslink/MBXRegAcM.h b/arch/arm/plat-omap/include/syslink/MBXRegAcM.h
new file mode 100644
index 000000000000..1c6732ecc9a2
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/MBXRegAcM.h
@@ -0,0 +1,3027 @@
+/*
+ * MBXRegAcM.h
+ *
+ * Notify mailbox driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _MBX_REG_ACM_H
+#define _MBX_REG_ACM_H
+
+
+#include <syslink/GlobalTypes.h>
+#include <syslink/MBXAccInt.h>
+
+
+/*
+ * EXPORTED DEFINITIONS
+ *
+ */
+
+#if defined(USE_LEVEL_1_MACROS)
+
+#define MLBMAILBOX_REVISIONReadRegister32(base_address)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+MLB_MAILBOX_REVISION_OFFSET))
+
+
+
+#define MLBMAILBOX_REVISIONRevRead32(base_address)\
+((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+ \
+(MLB_MAILBOX_REVISION_OFFSET)))) &\
+MLB_MAILBOX_REVISION_Rev_MASK) >>\
+MLB_MAILBOX_REVISION_Rev_OFFSET))
+
+
+
+#define MLBMAILBOX_REVISIONRevGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_REVISION_Rev_MASK) \
+>> MLB_MAILBOX_REVISION_Rev_OFFSET))
+
+
+
+#define MLBMAILBOX_SYSCONFIGReadRegister32(base_address)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+MLB_MAILBOX_SYSCONFIG_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGWriteRegister32(base_address, value)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register unsigned long newValue = ((unsigned long)(value));\
+	WR_MEM_32_VOLATILE(((unsigned long)(base_address))+ \
+	offset, newValue);\
+} while (0)
+
+
+#define MLBMAILBOX_SYSCONFIGClockActivityRead32(base_address)\
+((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGClockActivityGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK) \
+>> MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(base_address)\
+((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb0032(base_address)\
+((MLBMAILBOX_SYSCONFIGSIdleModeb00 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)))
+
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb0132(base_address)\
+((MLBMAILBOX_SYSCONFIGSIdleModeb01 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)))
+
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb1032(base_address)\
+((MLBMAILBOX_SYSCONFIGSIdleModeb10 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb1132(base_address)\
+((MLBMAILBOX_SYSCONFIGSIdleModeb11 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >> \
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeIsb0032(var)\
+((MLBMAILBOX_SYSCONFIGSIdleModeb00  ==  \
+(MLBMAILBOX_SYSCONFIGSIdleModeE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeIsb0132(var)\
+((MLBMAILBOX_SYSCONFIGSIdleModeb01 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeIsb1032(var)\
+((MLBMAILBOX_SYSCONFIGSIdleModeb10 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeIsb1132(var)\
+((MLBMAILBOX_SYSCONFIGSIdleModeb11 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(base_address, value)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+ \
+	offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb0032(base_address)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	const unsigned long newValue = \
+	(unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb00 <<\
+	MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb0132(base_address)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	const unsigned long newValue = \
+	(unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb01 <<\
+	MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb1032(base_address)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	const unsigned long newValue = \
+	(unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb10 <<\
+	MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb1132(base_address)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	const unsigned long newValue = \
+	(unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb11 <<\
+	MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeSet32(var, value)\
+(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK)) |\
+((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET) &\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK)))
+
+#define MLBMAILBOX_SYSCONFIGSoftResetRead32(base_address)\
+((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))
+
+#define MLBMAILBOX_SYSCONFIGSoftResetReadIsb032(base_address)\
+((MLBMAILBOX_SYSCONFIGSoftResetb0  ==  (MLBMAILBOX_SYSCONFIGSoftResetE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSoftResetReadIsb132(base_address)\
+((MLBMAILBOX_SYSCONFIGSoftResetb1 == (MLBMAILBOX_SYSCONFIGSoftResetE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSoftResetGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >> \
+MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))
+
+#define MLBMAILBOX_SYSCONFIGSoftResetIsb032(var)\
+((MLBMAILBOX_SYSCONFIGSoftResetb0  ==  (MLBMAILBOX_SYSCONFIGSoftResetE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSoftResetIsb132(var)\
+((MLBMAILBOX_SYSCONFIGSoftResetb1 == (MLBMAILBOX_SYSCONFIGSoftResetE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(base_address, value)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGSoftResetWriteb032(base_address)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	const unsigned long newValue = \
+	(unsigned long)MLBMAILBOX_SYSCONFIGSoftResetb0 <<\
+	MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGSoftResetWriteb132(base_address)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	const unsigned long newValue = \
+	(unsigned long)MLBMAILBOX_SYSCONFIGSoftResetb1 <<\
+	MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGSoftResetSet32(var, value)\
+(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK)) |\
+((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET) &\
+MLB_MAILBOX_SYSCONFIG_SoftReset_MASK)))
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(base_address)\
+((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleReadIsb032(base_address)\
+((MLBMAILBOX_SYSCONFIGAutoIdleb0 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleReadIsb132(base_address)\
+((MLBMAILBOX_SYSCONFIGAutoIdleb1 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >> MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleIsb032(var)\
+((MLBMAILBOX_SYSCONFIGAutoIdleb0 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleIsb132(var)\
+((MLBMAILBOX_SYSCONFIGAutoIdleb1 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)))
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(base_address, value)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleWriteb032(base_address)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	const unsigned long newValue = \
+	(unsigned long)MLBMAILBOX_SYSCONFIGAutoIdleb0 <<\
+	MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleWriteb132(base_address)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	const unsigned long newValue = \
+	(unsigned long)MLBMAILBOX_SYSCONFIGAutoIdleb1 <<\
+	MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\
+} while (0)
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleSet32(var, value)\
+(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK)) |\
+((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET) &\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK)))
+
+#define MLBMAILBOX_SYSSTATUSReadRegister32(base_address)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+MLB_MAILBOX_SYSSTATUS_OFFSET))
+
+#define MLBMAILBOX_SYSSTATUSResetDoneRead32(base_address)\
+((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\
+MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
+MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))
+
+#define MLBMAILBOX_SYSSTATUSResetDoneReadisrstongoing32(base_address)\
+((MLBMAILBOX_SYSSTATUSResetDonerstongoing == (MLBMAILBOX_SYSSTATUSResetDoneE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\
+MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
+MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)))
+
+#define MLBMAILBOX_SYSSTATUSResetDoneReadisrstcomp32(base_address)\
+((MLBMAILBOX_SYSSTATUSResetDonerstcomp == (MLBMAILBOX_SYSSTATUSResetDoneE)\
+(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\
+(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\
+MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
+MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)))
+
+#define MLBMAILBOX_SYSSTATUSResetDoneGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >> \
+MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))
+
+#define MLBMAILBOX_SYSSTATUSResetDoneisrstongoing32(var)\
+((MLBMAILBOX_SYSSTATUSResetDonerstongoing  == (MLBMAILBOX_SYSSTATUSResetDoneE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
+MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)))
+
+#define MLBMAILBOX_SYSSTATUSResetDoneisrstcomp32(var)\
+((MLBMAILBOX_SYSSTATUSResetDonerstcomp == (MLBMAILBOX_SYSSTATUSResetDoneE)\
+((((unsigned long)(var)) & MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
+MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)))
+
+#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(base_address, bank)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_MESSAGE___0_15_OFFSET+((bank)*\
+MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP))))
+
+#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(base_address, bank, value)\
+do {\
+	const unsigned long offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
+	MLB_MAILBOX_MESSAGE___0_15_OFFSET +\
+	((bank) * MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmRead32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_MESSAGE___0_15_OFFSET+((bank)*\
+MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) &\
+MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK) >>\
+MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET))
+
+#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK) >> \
+MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET))
+
+#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmWrite32\
+(base_address, bank, value) do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
+	MLB_MAILBOX_MESSAGE___0_15_OFFSET +\
+	((bank) * MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK);\
+	newValue <<= MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET;\
+	newValue &= MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmSet32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET) &\
+MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK)))
+
+#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(base_address, bank)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+((bank)*\
+MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP))))
+
+#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+((bank)*\
+MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\
+MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\
+MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET))
+
+#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >> \
+MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET))
+
+#define MLBMAILBOX_MSGSTATUS___0_15ReadRegister32(base_address, bank)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+((bank)*\
+MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP))))
+
+#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+((bank)*\
+MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\
+MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\
+MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET))
+
+#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmGet32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) \
+>> MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET))
+
+#if defined(OMAP44XX) || defined(VPOM4430_1_06)
+
+#define MLBMAILBOX_IRQSTATUS_CLR___0_3ReadRegister32(base_address, bank)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP))))
+
+#else
+
+#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(base_address, bank)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP))))
+
+#endif
+
+#if defined(OMAP44XX) || defined(VPOM4430_1_06)
+
+#define MLBMAILBOX_IRQSTATUS_CLR___0_3WriteRegister32\
+(base_address, bank, value) do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * \
+	MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	WR_MEM_32_VOLATILE(((unsigned long)(base_address))+ \
+	offset, newValue);\
+} while (0)
+
+#else
+
+#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\
+} while (0)
+
+#endif
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\
+((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\
+((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Write32\
+(base_address, bank, value)\
+do {\
+	onst unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\
++(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)\
+*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK) \
+>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\
+((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = RD_\
+	MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK)))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK) >>\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK) >> \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET))
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK);\
+	newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET) &\
+MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK)))
+
+#if defined(OMAP44XX) || defined(VPOM4430_1_06)
+
+#define MLBMAILBOX_IRQENABLE_SET___0_3ReadRegister32(base_address, bank)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP))))
+
+#else
+
+#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(base_address, bank)\
+(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP))))
+
+#endif
+
+#if defined(OMAP44XX) || defined(VPOM4430_1_06)
+
+#define MLBMAILBOX_IRQENABLE_SET___0_3WriteRegister32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * \
+	MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE_CLR___0_3WriteRegister32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * \
+	MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_STEP);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\
+} while (0)
+
+#else
+
+#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\
+} while (0)
+
+#endif
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = \
+	((unsigned long)(value));\
+	data &= \
+	~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK);\
+	newValue <<= \
+	MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET;\
+	newValue \
+	&= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\
+((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = \
+	((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Set32\
+(var, value)\
+(((((unsigned long)(var)) &\
+~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\
++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Set32(var, value)\
+(((((unsigned long)(var)) & \
+~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Get32(var)\
+((unsigned long)((((unsigned long)(var)) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Read32(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\
++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\
++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Get32\
+(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\
++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)\
+*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Get32\
+(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\
++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)\
+*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Get32(var)\
+((unsigned long)((((unsigned long)(var)) \
+& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Set32\
+(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK)) |\
+((((unsigned long)(value)) << \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Read32\
+(base_address, bank) do {\
+	((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+	(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+	MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK) >>\
+	MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET))\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK) >> \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Set32(var, value)\
+(((((unsigned long)(var)) &\
+~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK)))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Read32\
+(base_address, bank)\
+((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\
+MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK) >>\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Get32(var)\
+((unsigned long)((((unsigned long)(var)) & \
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK) \
+>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET))
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Write32\
+(base_address, bank, value)\
+do {\
+	const unsigned long offset = \
+	MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register unsigned long data = \
+	RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\
+	register unsigned long newValue = ((unsigned long)(value));\
+	data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK);\
+	newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET;\
+	newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\
+} while (0)
+
+#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Set32(var, value)\
+(((((unsigned long)(var)) \
+& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK)) |\
+((((unsigned long)(value)) \
+<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET) &\
+MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK)))
+
+#endif    /* USE_LEVEL_1_MACROS */
+
+
+#endif /* _MBX_REG_ACM_H */
diff --git a/arch/arm/plat-omap/include/syslink/MLBAccInt.h b/arch/arm/plat-omap/include/syslink/MLBAccInt.h
new file mode 100644
index 000000000000..6cd469709005
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/MLBAccInt.h
@@ -0,0 +1,132 @@
+/*
+ * MLBAccInt.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef _MLB_ACC_INT_H
+#define _MLB_ACC_INT_H
+
+/* Mappings of level 1 EASI function numbers to function names */
+
+#define EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32   (MLB_BASE_EASIL1 + 3)
+#define EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32  (MLB_BASE_EASIL1 + 4)
+#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32   (MLB_BASE_EASIL1 + 7)
+#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32  (MLB_BASE_EASIL1 + 17)
+#define EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32 (MLB_BASE_EASIL1 + 29)
+#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32 \
+						(MLB_BASE_EASIL1 + 33)
+#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32   (MLB_BASE_EASIL1 + 39)
+#define EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32  (MLB_BASE_EASIL1 + 44)
+#define EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32 \
+						(MLB_BASE_EASIL1 + 50)
+#define EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32  \
+						(MLB_BASE_EASIL1 + 51)
+#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32  \
+						(MLB_BASE_EASIL1 + 56)
+#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32 \
+						(MLB_BASE_EASIL1 + 57)
+#define EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32  \
+						(MLB_BASE_EASIL1 + 60)
+#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32  \
+						(MLB_BASE_EASIL1 + 62)
+#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32 \
+						(MLB_BASE_EASIL1 + 63)
+#define EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32    \
+						(MLB_BASE_EASIL1 + 192)
+#define EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32   \
+						(MLB_BASE_EASIL1 + 193)
+
+/* Register set MAILBOX_MESSAGE___REGSET_0_15 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET    (u32)(0x0040)
+#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP   (u32)(0x0004)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_MESSAGE___REGSET_0_15 */
+
+#define MLB_MAILBOX_MESSAGE___0_15_OFFSET   (u32)(0x0)
+
+
+/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET  (u32)(0x0080)
+#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP   (u32)(0x0004)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_FIFOSTATUS___REGSET_0_15 */
+
+#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET    (u32)(0x0)
+
+
+/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET  (u32)(0x00c0)
+#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP    (u32)(0x0004)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_MSGSTATUS___REGSET_0_15 */
+
+#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET    (u32)(0x0)
+
+
+/* Register set MAILBOX_IRQSTATUS___REGSET_0_3 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET        (u32)(0x0100)
+#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP          (u32)(0x0008)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_IRQSTATUS___REGSET_0_3 */
+
+#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET        (u32)(0x0)
+
+
+/* Register set MAILBOX_IRQENABLE___REGSET_0_3 address offset, bank address
+ * increment and number of banks */
+
+#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET     (u32)(0x0104)
+#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP     (u32)(0x0008)
+
+/* Register offset address definitions relative to register set
+ * MAILBOX_IRQENABLE___REGSET_0_3 */
+
+#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET          (u32)(0x0)
+
+
+/* Register offset address definitions */
+
+#define MLB_MAILBOX_SYSCONFIG_OFFSET            (u32)(0x10)
+#define MLB_MAILBOX_SYSSTATUS_OFFSET            (u32)(0x14)
+
+
+/* Bitfield mask and offset declarations */
+
+#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK        (u32)(0x18)
+#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET      (u32)(3)
+#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK        (u32)(0x2)
+#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET      (u32)(1)
+#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK          (u32)(0x1)
+#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET        (u32)(0)
+#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK         (u32)(0x1)
+#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET         (u32)(0)
+#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK   (u32)(0x1)
+#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET  (u32)(0)
+#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK    (u32)(0x7f)
+#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET    (u32)(0)
+
+#endif /* _MLB_ACC_INT_H */
diff --git a/arch/arm/plat-omap/include/syslink/MLBRegAcM.h b/arch/arm/plat-omap/include/syslink/MLBRegAcM.h
new file mode 100644
index 000000000000..5ef9cf32aef2
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/MLBRegAcM.h
@@ -0,0 +1,206 @@
+/*
+ * MLBRegAcM.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _MLB_REG_ACM_H
+#define _MLB_REG_ACM_H
+
+#include <syslink/GlobalTypes.h>
+#include <syslink/EasiGlobal.h>
+#include <syslink/MLBAccInt.h>
+
+#if defined(USE_LEVEL_1_MACROS)
+
+#define MLBMAILBOX_SYSCONFIGReadRegister32(base_address)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+ \
+MLB_MAILBOX_SYSCONFIG_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGWriteRegister32(base_address, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\
+	WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\
+} while (0)
+
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(base_address)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32),\
+(((RD_MEM_32_VOLATILE((((u32)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(base_address, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(((u32)(base_address)) +\
+				offset);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\
+} while (0)
+
+
+#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(base_address, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register u32 data =\
+	RD_MEM_32_VOLATILE(((u32)(base_address))+offset);\
+	register u32 newValue = ((u32)(value));\
+	printk(KERN_ALERT "In SYSCONFIG MACOR line %i    file %s",  \
+	__LINE__, __FILE__);\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32);\
+	printk(KERN_ALERT "******************BEFORE DATA WRITE");\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\
+	printk(KERN_ALERT "line %i    file %s", __LINE__, __FILE__);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\
+	newValue |= data;\
+	printk(KERN_ALERT "line %i    file %s", __LINE__, __FILE__);\
+	WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\
+	printk(KERN_ALERT "line %i    file %s", __LINE__, __FILE__);\
+} while (0)
+
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(base_address)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32),\
+(((RD_MEM_32_VOLATILE((((u32)(base_address))+\
+(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
+MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))
+
+
+#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(base_address, value)\
+{\
+	const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
+	register u32 data =\
+	RD_MEM_32_VOLATILE(((u32)(base_address))+offset);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32);\
+	data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\
+	newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\
+	newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\
+}
+
+
+#define MLBMAILBOX_SYSSTATUSResetDoneRead32(base_address)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32),\
+(((RD_MEM_32_VOLATILE((((u32)(base_address))+\
+(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\
+MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
+MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))
+
+
+#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_MESSAGE___0_15_OFFSET+(\
+(bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP))))
+
+
+#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(base_address, bank, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
+	MLB_MAILBOX_MESSAGE___0_15_OFFSET +\
+	((bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32);\
+	WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\
+} while (0)
+
+
+#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(\
+EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
+((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP))))
+
+
+#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(\
+EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32),\
+(((RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
+((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\
+MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\
+MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET))
+
+
+#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(\
+EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32),\
+(((RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\
+MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+\
+((bank)*MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\
+MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\
+MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET))
+
+
+#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\
+((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP))))
+
+
+#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(base_address, bank, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
+	((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32);\
+	WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\
+} while (0)
+
+
+#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(base_address, bank)\
+(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32),\
+RD_MEM_32_VOLATILE(((u32)(base_address))+\
+(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\
+((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP))))
+
+
+#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(base_address, bank, value)\
+do {\
+	const u32 offset = MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
+	MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
+	((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
+	register u32 newValue = ((u32)(value));\
+	_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32);\
+	WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\
+} while (0)
+
+
+#endif	/* USE_LEVEL_1_MACROS */
+
+#endif /* _MLB_REG_ACM_H */
diff --git a/arch/arm/plat-omap/include/syslink/MMUAccInt.h b/arch/arm/plat-omap/include/syslink/MMUAccInt.h
new file mode 100644
index 000000000000..2aa0fa2436ae
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/MMUAccInt.h
@@ -0,0 +1,180 @@
+/*
+ * MMUAccInt.h
+ *
+ * Syslink ducati driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _MMU_ACC_INT_H
+#define _MMU_ACC_INT_H
+
+
+/* Register offset address definitions */
+
+#define MMU_MMU_REVISION_OFFSET 0x0
+#define MMU_MMU_SYSCONFIG_OFFSET 0x10
+#define MMU_MMU_SYSSTATUS_OFFSET 014
+#define MMU_MMU_IRQSTATUS_OFFSET 0x18
+#define MMU_MMU_IRQENABLE_OFFSET 0x1c
+#define MMU_MMU_WALKING_ST_OFFSET 0x40
+#define MMU_MMU_CNTL_OFFSET     0x44
+#define MMU_MMU_FAULT_AD_OFFSET 0x48
+#define MMU_MMU_TTB_OFFSET      0x4c
+#define MMU_MMU_LOCK_OFFSET     0x50
+#define MMU_MMU_LD_TLB_OFFSET   0x54
+#define MMU_MMU_CAM_OFFSET      0x58
+#define MMU_MMU_RAM_OFFSET      0x5c
+#define MMU_MMU_GFLUSH_OFFSET   0x60
+#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64
+#define MMU_MMU_READ_CAM_OFFSET	0x68
+#define MMU_MMU_READ_RAM_OFFSET	0x6c
+#define MMU_MMU_EMU_FAULT_AD_OFFSET	0x70
+#define MMU_MMU_FAULT_PC_OFFSET  0x80
+#define MMU_MMU_FAULT_STATUS_OFFSET  0x84
+
+/* Bitfield mask and offset declarations */
+
+#define MMU_MMU_REVISION_Rev_MASK	0xff
+#define MMU_MMU_REVISION_Rev_OFFSET	0
+
+#define MMU_MMU_SYSCONFIG_ClockActivity_MASK	0x300
+#define MMU_MMU_SYSCONFIG_ClockActivity_OFFSET	8
+
+#define MMU_MMU_SYSCONFIG_IdleMode_MASK	0x18
+#define MMU_MMU_SYSCONFIG_IdleMode_OFFSET	3
+
+#define MMU_MMU_SYSCONFIG_SoftReset_MASK	0x2
+#define MMU_MMU_SYSCONFIG_SoftReset_OFFSET	1
+
+#define MMU_MMU_SYSCONFIG_AutoIdle_MASK	0x1
+#define MMU_MMU_SYSCONFIG_AutoIdle_OFFSET	0
+
+#define MMU_MMU_SYSSTATUS_ResetDone_MASK	0x1
+#define MMU_MMU_SYSSTATUS_ResetDone_OFFSET	0
+
+#define MMU_MMU_IRQSTATUS_MultiHitFault_MASK	0x10
+#define MMU_MMU_IRQSTATUS_MultiHitFault_OFFSET	4
+
+#define MMU_MMU_IRQSTATUS_TableWalkFault_MASK	0x8
+#define MMU_MMU_IRQSTATUS_TableWalkFault_OFFSET	3
+
+#define MMU_MMU_IRQSTATUS_EMUMiss_MASK	0x4
+#define MMU_MMU_IRQSTATUS_EMUMiss_OFFSET	2
+
+#define MMU_MMU_IRQSTATUS_TranslationFault_MASK	0x2
+#define MMU_MMU_IRQSTATUS_TranslationFault_OFFSET	1
+
+#define MMU_MMU_IRQSTATUS_TLBMiss_MASK	0x1
+#define MMU_MMU_IRQSTATUS_TLBMiss_OFFSET	0
+
+#define MMU_MMU_IRQENABLE_MultiHitFault_MASK	0x10
+#define MMU_MMU_IRQENABLE_MultiHitFault_OFFSET	4
+
+#define MMU_MMU_IRQENABLE_TableWalkFault_MASK	0x8
+#define MMU_MMU_IRQENABLE_TableWalkFault_OFFSET	3
+
+#define MMU_MMU_IRQENABLE_EMUMiss_MASK	0x4
+#define MMU_MMU_IRQENABLE_EMUMiss_OFFSET	2
+
+#define MMU_MMU_IRQENABLE_TranslationFault_MASK	0x2
+#define MMU_MMU_IRQENABLE_TranslationFault_OFFSET	1
+
+#define MMU_MMU_IRQENABLE_TLBMiss_MASK	0x1
+#define MMU_MMU_IRQENABLE_TLBMiss_OFFSET	0
+
+#define MMU_MMU_WALKING_ST_TWLRunning_MASK	0x1
+#define MMU_MMU_WALKING_ST_TWLRunning_OFFSET	0
+
+#define MMU_MMU_CNTL_EmuTLBUpdate_MASK	0x8
+#define MMU_MMU_CNTL_EmuTLBUpdate_OFFSET	3
+
+#define MMU_MMU_CNTL_TWLEnable_MASK	0x4
+#define MMU_MMU_CNTL_TWLEnable_OFFSET	2
+
+#define MMU_MMU_CNTL_MMUEnable_MASK	0x2
+#define MMU_MMU_CNTL_MMUEnable_OFFSET	1
+
+#define MMU_MMU_FAULT_AD_FaultAddress_MASK	0xffffffff
+#define MMU_MMU_FAULT_AD_FaultAddress_OFFSET	0
+
+#define MMU_MMU_TTB_TTBAddress_MASK	0xffffff00
+#define MMU_MMU_TTB_TTBAddress_OFFSET	8
+
+#define MMU_MMU_LOCK_BaseValue_MASK	0xfc00
+#define MMU_MMU_LOCK_BaseValue_OFFSET	10
+
+#define MMU_MMU_LOCK_CurrentVictim_MASK	0x3f0
+#define MMU_MMU_LOCK_CurrentVictim_OFFSET	4
+
+#define MMU_MMU_LD_TLB_LdTLBItem_MASK	0x1
+#define MMU_MMU_LD_TLB_LdTLBItem_OFFSET	0
+
+#define MMU_MMU_CAM_VATag_MASK	0xfffff000
+#define MMU_MMU_CAM_VATag_OFFSET	12
+
+#define MMU_MMU_CAM_P_MASK	0x8
+#define MMU_MMU_CAM_P_OFFSET	3
+
+#define MMU_MMU_CAM_V_MASK	0x4
+#define MMU_MMU_CAM_V_OFFSET	2
+
+#define MMU_MMU_CAM_PageSize_MASK	0x3
+#define MMU_MMU_CAM_PageSize_OFFSET	0
+
+#define MMU_MMU_RAM_PhysicalAddress_MASK	0xfffff000
+#define MMU_MMU_RAM_PhysicalAddress_OFFSET	12
+
+#define MMU_MMU_RAM_Endianness_MASK	0x200
+#define MMU_MMU_RAM_Endianness_OFFSET	9
+
+#define MMU_MMU_RAM_ElementSize_MASK	0x180
+#define MMU_MMU_RAM_ElementSize_OFFSET	7
+
+#define MMU_MMU_RAM_Mixed_MASK	0x40
+#define MMU_MMU_RAM_Mixed_OFFSET	6
+
+#define MMU_MMU_GFLUSH_GlobalFlush_MASK	0x1
+#define MMU_MMU_GFLUSH_GlobalFlush_OFFSET	0
+
+#define MMU_MMU_FLUSH_ENTRY_FlushEntry_MASK	0x1
+#define MMU_MMU_FLUSH_ENTRY_FlushEntry_OFFSET	0
+
+#define MMU_MMU_READ_CAM_VATag_MASK	0xfffff000
+#define MMU_MMU_READ_CAM_VATag_OFFSET	12
+
+#define MMU_MMU_READ_CAM_P_MASK	0x8
+#define MMU_MMU_READ_CAM_P_OFFSET	3
+
+#define MMU_MMU_READ_CAM_V_MASK	0x4
+#define MMU_MMU_READ_CAM_V_OFFSET	2
+
+#define MMU_MMU_READ_CAM_PageSize_MASK	0x3
+#define MMU_MMU_READ_CAM_PageSize_OFFSET	0
+
+#define MMU_MMU_READ_RAM_PhysicalAddress_MASK	0xfffff000
+#define MMU_MMU_READ_RAM_PhysicalAddress_OFFSET	12
+
+#define MMU_MMU_READ_RAM_Endianness_MASK	0x200
+#define MMU_MMU_READ_RAM_Endianness_OFFSET	9
+
+#define MMU_MMU_READ_RAM_ElementSize_MASK	0x180
+#define MMU_MMU_READ_RAM_ElementSize_OFFSET	7
+
+#define MMU_MMU_READ_RAM_Mixed_MASK	0x40
+#define MMU_MMU_READ_RAM_Mixed_OFFSET	6
+
+#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_MASK	0xffffffff
+#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_OFFSET	0
+
+#endif /* _MMU_ACC_INT_H */
+/* EOF */
+
diff --git a/arch/arm/plat-omap/include/syslink/MMURegAcM.h b/arch/arm/plat-omap/include/syslink/MMURegAcM.h
new file mode 100644
index 000000000000..c4944110789e
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/MMURegAcM.h
@@ -0,0 +1,434 @@
+/*
+ * MMURegAcM.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _MMU_REG_ACM_H
+#define _MMU_REG_ACM_H
+
+
+
+#include "GlobalTypes.h"
+#include "MMUAccInt.h"
+
+
+/*
+* EXPORTED DEFINITIONS
+*
+*/
+
+#if defined(USE_LEVEL_1_MACROS)
+
+
+#define MMUMMU_SYSCONFIGReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_SYSCONFIG_OFFSET))
+
+
+#define MMUMMU_SYSCONFIGWriteRegister32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+#define MMUMMU_SYSCONFIGClockActivityGet32(var)\
+	((u32)(((var) & MMU_MMU_SYSCONFIG_ClockActivity_MASK)\
+	>> MMU_MMU_SYSCONFIG_ClockActivity_OFFSET))
+
+#define mmu_sisconf_auto_idle_set32(var, value)\
+	((((var) & ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK)) |\
+	(((value) << MMU_MMU_SYSCONFIG_AutoIdle_OFFSET) &\
+	MMU_MMU_SYSCONFIG_AutoIdle_MASK)))
+
+#define MMUMMU_IRQSTATUSReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_IRQSTATUS_OFFSET))
+
+
+#define MMUMMU_IRQSTATUSWriteRegister32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+
+#define MMUMMU_IRQENABLEReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_IRQENABLE_OFFSET))
+
+
+#define MMUMMU_IRQENABLEWriteRegister32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+#define MMUMMU_IRQENABLETableWalkFaultSet32(var, value)\
+	((((var) & ~(MMU_MMU_IRQENABLE_TableWalkFault_MASK)) |\
+	(((value) << MMU_MMU_IRQENABLE_TableWalkFault_OFFSET) &\
+	MMU_MMU_IRQENABLE_TableWalkFault_MASK)))
+
+#define MMUMMU_IRQENABLETranslationFaultRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\
+	MMU_MMU_IRQENABLE_TranslationFault_MASK) >>\
+	MMU_MMU_IRQENABLE_TranslationFault_OFFSET))
+
+
+
+#define MMUMMU_IRQENABLETranslationFaultSet32(var, value)\
+	((((var) & ~(MMU_MMU_IRQENABLE_TranslationFault_MASK)) |\
+	(((value) << MMU_MMU_IRQENABLE_TranslationFault_OFFSET) &\
+	MMU_MMU_IRQENABLE_TranslationFault_MASK)))
+
+
+#define MMUMMU_IRQENABLETLBMissRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\
+	MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
+	MMU_MMU_IRQENABLE_TLBMiss_OFFSET))
+
+
+#define MMUMMU_IRQENABLETLBMissReadIsTrMissIntM32(base_address)\
+	((MMUMMU_IRQENABLETLBMissTrMissIntM == (MMUMMU_IRQENABLETLBMissE)\
+	(((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\
+	MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
+	MMU_MMU_IRQENABLE_TLBMiss_OFFSET)))
+
+
+#define MMUMMU_IRQENABLETLBMissReadIsTrMissGInt32(base_address)\
+	((MMUMMU_IRQENABLETLBMissTrMissGInt == (MMUMMU_IRQENABLETLBMissE)\
+	(((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\
+	MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
+	MMU_MMU_IRQENABLE_TLBMiss_OFFSET)))
+
+
+#define MMUMMU_IRQENABLETLBMissGet32(var)\
+	((u32)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK)\
+	>> MMU_MMU_IRQENABLE_TLBMiss_OFFSET))
+
+
+#define MMUMMU_IRQENABLETLBMissIsTrMissIntM32(var)\
+	((MMUMMU_IRQENABLETLBMissTrMissIntM == \
+	(MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
+	MMU_MMU_IRQENABLE_TLBMiss_OFFSET)))
+
+#define MMUMMU_IRQENABLETLBMissIsTrMissGInt32(var)\
+	((MMUMMU_IRQENABLETLBMissTrMissGInt ==\
+	(MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\
+	MMU_MMU_IRQENABLE_TLBMiss_OFFSET)))
+
+#define MMUMMU_IRQENABLETLBMissWrite32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\
+	register u32 newValue = (value);\
+	data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\
+	newValue <<= MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\
+	newValue &= MMU_MMU_IRQENABLE_TLBMiss_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE(base_address+offset, newValue);\
+}
+
+
+#define MMUMMU_IRQENABLETLBMissWriteTrMissIntM32(base_address)\
+{\
+	const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
+	const u32 newValue = (u32)MMUMMU_IRQENABLETLBMissTrMissIntM <<\
+	MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\
+	data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\
+		data |= newValue;\
+	WR_MEM_32_VOLATILE(base_address+offset, data);\
+}
+
+
+#define MMUMMU_IRQENABLETLBMissWriteTrMissGInt32(base_address)\
+{\
+	const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
+	const u32 newValue = (u32)MMUMMU_IRQENABLETLBMissTrMissGInt <<\
+	MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\
+	data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE(base_address+offset, data);\
+}
+
+
+#define MMUMMU_IRQENABLETLBMissSet32(var, value)\
+	((((var) & ~(MMU_MMU_IRQENABLE_TLBMiss_MASK)) |\
+	(((value) << MMU_MMU_IRQENABLE_TLBMiss_OFFSET) &\
+	MMU_MMU_IRQENABLE_TLBMiss_MASK)))
+
+
+#define MMUMMU_WALKING_STTWLRunningRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_WALKING_ST_OFFSET)))) &\
+	MMU_MMU_WALKING_ST_TWLRunning_MASK) >>\
+	MMU_MMU_WALKING_ST_TWLRunning_OFFSET))
+
+
+
+#define MMUMMU_CNTLTWLEnableRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_CNTL_OFFSET)))) &\
+	MMU_MMU_CNTL_TWLEnable_MASK) >>\
+	MMU_MMU_CNTL_TWLEnable_OFFSET))
+
+
+#define MMUMMU_CNTLTWLEnableWrite32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_CNTL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\
+	register u32 newValue = (value);\
+	data &= ~(MMU_MMU_CNTL_TWLEnable_MASK);\
+	newValue <<= MMU_MMU_CNTL_TWLEnable_OFFSET;\
+	newValue &= MMU_MMU_CNTL_TWLEnable_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE(base_address+offset, newValue);\
+}
+
+
+#define MMUMMU_CNTLMMUEnableWrite32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_CNTL_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\
+	register u32 newValue = (value);\
+	data &= ~(MMU_MMU_CNTL_MMUEnable_MASK);\
+	newValue <<= MMU_MMU_CNTL_MMUEnable_OFFSET;\
+	newValue &= MMU_MMU_CNTL_MMUEnable_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE(base_address+offset, newValue);\
+}
+
+
+#define MMUMMU_FAULT_ADReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FAULT_AD_OFFSET))
+
+
+#define MMUMMU_FAULT_ADFaultAddressRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_FAULT_AD_OFFSET)))) &\
+	MMU_MMU_FAULT_AD_FaultAddress_MASK) >>\
+	MMU_MMU_FAULT_AD_FaultAddress_OFFSET))
+
+#define MMUMMU_FAULT_ADFaultAddressGet32(var)\
+	((u32)(((var) & MMU_MMU_FAULT_AD_FaultAddress_MASK)\
+	>> MMU_MMU_FAULT_AD_FaultAddress_OFFSET))
+
+
+#define MMUMMU_TTBReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_TTB_OFFSET))
+
+#define MMUMMU_TTBWriteRegister32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_TTB_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+#define MMUMMU_TTBTTBAddressRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_TTB_OFFSET)))) &\
+	MMU_MMU_TTB_TTBAddress_MASK) >>\
+	MMU_MMU_TTB_TTBAddress_OFFSET))
+
+#define MMUMMU_TTBTTBAddressGet32(var)\
+	((u32)(((var) & MMU_MMU_TTB_TTBAddress_MASK)\
+	>> MMU_MMU_TTB_TTBAddress_OFFSET))
+
+
+#define MMUMMU_TTBTTBAddressWrite32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_TTB_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\
+	register u32 newValue = (value);\
+	data &= ~(MMU_MMU_TTB_TTBAddress_MASK);\
+	newValue <<= MMU_MMU_TTB_TTBAddress_OFFSET;\
+	newValue &= MMU_MMU_TTB_TTBAddress_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE(base_address+offset, newValue);\
+}
+
+#define MMUMMU_TTBTTBAddressSet32(var, value)\
+	((((var) & ~(MMU_MMU_TTB_TTBAddress_MASK)) |\
+	(((value) << MMU_MMU_TTB_TTBAddress_OFFSET) &\
+	MMU_MMU_TTB_TTBAddress_MASK)))
+
+
+#define mmu_lckread_reg_32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_LOCK_OFFSET))
+
+#define mmu_lck_write_reg32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_LOCK_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+
+#define MMUMMU_LOCKBaseValueRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
+	MMU_MMU_LOCK_BaseValue_MASK) >>\
+	MMU_MMU_LOCK_BaseValue_OFFSET))
+#define MMUMMU_LOCKBaseValueGet32(var)\
+	((u32)(((var) & MMU_MMU_LOCK_BaseValue_MASK)\
+	>> MMU_MMU_LOCK_BaseValue_OFFSET))
+
+
+#define MMUMMU_LOCKBaseValueWrite32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_LOCK_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\
+	register u32 newValue = (value);\
+	data &= ~(MMU_MMU_LOCK_BaseValue_MASK);\
+	newValue <<= MMU_MMU_LOCK_BaseValue_OFFSET;\
+	newValue &= MMU_MMU_LOCK_BaseValue_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE(base_address+offset, newValue);\
+}
+
+
+#define MMUMMU_LOCKBaseValueSet32(var, value)\
+	((((var) & ~(MMU_MMU_LOCK_BaseValue_MASK)) |\
+	(((value) << MMU_MMU_LOCK_BaseValue_OFFSET) &\
+	MMU_MMU_LOCK_BaseValue_MASK)))
+
+#define MMUMMU_LOCKCurrentVictimRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
+	MMU_MMU_LOCK_CurrentVictim_MASK) >>\
+	MMU_MMU_LOCK_CurrentVictim_OFFSET))
+
+
+#define MMUMMU_LOCKCurrentVictimGet32(var)\
+	((u32)(((var) & MMU_MMU_LOCK_CurrentVictim_MASK)\
+	>> MMU_MMU_LOCK_CurrentVictim_OFFSET))
+
+
+#define mmu_lck_crnt_vctmwite32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_LOCK_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\
+	register u32 newValue = (value);\
+	data &= ~(MMU_MMU_LOCK_CurrentVictim_MASK);\
+	newValue <<= MMU_MMU_LOCK_CurrentVictim_OFFSET;\
+	newValue &= MMU_MMU_LOCK_CurrentVictim_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE(base_address+offset, newValue);\
+}
+
+
+#define MMUMMU_LOCKCurrentVictimSet32(var, value)\
+	((((var) & ~(MMU_MMU_LOCK_CurrentVictim_MASK)) |\
+	(((value) << MMU_MMU_LOCK_CurrentVictim_OFFSET) &\
+	MMU_MMU_LOCK_CurrentVictim_MASK)))
+
+
+#define MMUMMU_LD_TLBReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_LD_TLB_OFFSET))
+
+#define mmu_ld_tlbwrt_reg32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+#define MMUMMU_LD_TLBLdTLBItemRead32(base_address)\
+	((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LD_TLB_OFFSET)))) &\
+	MMU_MMU_LD_TLB_LdTLBItem_MASK) >>\
+	MMU_MMU_LD_TLB_LdTLBItem_OFFSET))
+
+
+#define MMUMMU_CAMReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_READ_CAM_OFFSET))
+
+
+#define MMUMMU_CAMWriteRegister32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_CAM_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+#define MMUMMU_RAMReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_READ_RAM_OFFSET))
+
+
+#define MMUMMU_RAMWriteRegister32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_RAM_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+#define MMUMMU_GFLUSHGlobalFlushWrite32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\
+	register u32 newValue = (value);\
+	data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\
+	newValue <<= MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\
+	newValue &= MMU_MMU_GFLUSH_GlobalFlush_MASK;\
+	newValue |= data;\
+	WR_MEM_32_VOLATILE(base_address+offset, newValue);\
+}
+
+#define MMUMMU_GFLUSHGlobalFlushWritenft_w32(base_address)\
+{\
+		const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
+	const u32 newValue = (u32)MMUMMU_GFLUSHGlobalFlushnft_w <<\
+	MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\
+	data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE(base_address+offset, data);\
+}
+
+#define MMUMMU_GFLUSHGlobalFlushWriteflush_w32(base_address)\
+{\
+	const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
+	const u32 newValue = (u32)MMUMMU_GFLUSHGlobalFlushflush_w <<\
+	MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\
+	register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\
+	data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\
+	data |= newValue;\
+	WR_MEM_32_VOLATILE(base_address+offset, data);\
+}
+
+
+#define MMUMMU_GFLUSHGlobalFlushSet32(var, value)\
+	((((var) & ~(MMU_MMU_GFLUSH_GlobalFlush_MASK)) |\
+	(((value) << MMU_MMU_GFLUSH_GlobalFlush_OFFSET) &\
+	MMU_MMU_GFLUSH_GlobalFlush_MASK)))
+
+#define MMUMMU_FLUSH_ENTRYReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FLUSH_ENTRY_OFFSET))
+
+
+#define MMUMMU_FLUSH_ENTRYWriteRegister32(base_address, value)\
+{\
+	const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
+	register u32 newValue = (value);\
+	WR_MEM_32_VOLATILE((base_address)+offset, newValue);\
+}
+
+#define MMUMMU_FAULT_PCReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FAULT_PC_OFFSET))
+
+#define MMUMMU_FAULT_STATUSReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FAULT_STATUS_OFFSET))
+
+#define MMUMMU_FAULT_EMUAddressReadRegister32(base_address)\
+	(RD_MEM_32_VOLATILE((base_address)+MMU_MMU_EMU_FAULT_AD_OFFSET))
+
+#endif	/* USE_LEVEL_1_MACROS */
+
+#endif /* _MMU_REG_ACM_H */
+/* EOF */
+
diff --git a/arch/arm/plat-omap/include/syslink/_listmp.h b/arch/arm/plat-omap/include/syslink/_listmp.h
new file mode 100644
index 000000000000..282d2c8c10e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/_listmp.h
@@ -0,0 +1,68 @@
+/*
+ *  _listmp.h
+ *
+ *  Internal definitions for shared memory doubly linked list.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef __LISTMP_H_
+#define __LISTMP_H_
+
+/* Standard headers */
+#include <linux/types.h>
+#include <linux/list.h>
+
+#include <listmp.h>
+#include <sharedregion.h>
+
+/* Unique module ID. */
+#define LISTMP_MODULEID		(0xa413)
+
+/* Created tag */
+#define LISTMP_CREATED		0x12181964
+
+
+/* Structure defining shared memory attributes for the ListMP module. */
+struct listmp_attrs {
+	u32 status;
+	u32 *gatemp_addr;
+	struct listmp_elem head;
+};
+
+/* Structure defining config parameters for the ListMP module. */
+struct listmp_config {
+	uint max_runtime_entries;
+	/* Maximum number of ListMP's that can be dynamically created and
+	added to the NameServer. */
+	uint max_name_len; /* Maximum length of name */
+};
+
+
+/* Structure defining processor related information for the ListMP module. */
+struct listmp_proc_attrs {
+	bool creator; /* Creator or opener */
+	u16 proc_id; /* Processor Identifier */
+	u32 open_count; /* How many times it is opened on a processor */
+};
+
+
+/* Function to get the configuration */
+void listmp_get_config(struct listmp_config *cfg_params);
+
+/* Function to setup the listmp module */
+int listmp_setup(const struct listmp_config *config);
+
+/* Function to destroy the listmp module */
+int listmp_destroy(void);
+
+#endif /* __LISTMP_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/_notify.h b/arch/arm/plat-omap/include/syslink/_notify.h
new file mode 100644
index 000000000000..9f9d88914160
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/_notify.h
@@ -0,0 +1,83 @@
+/*
+ *  _notify.h
+ *
+ *  The MessageQ module supports the structured sending and receiving of
+ *  variable length messages. This module can be used for homogeneous or
+ *  heterogeneous multi-processor messaging.
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#if !defined(__NOTIFY_H_)
+#define __NOTIFY_H_
+
+
+/* Module headers */
+#include <syslink/notify.h>
+
+
+/* Module ID for notify. */
+#define NOTIFY_MODULEID		((u16) 0x5F84)
+
+/* Mask to check for event ID. */
+#define NOTIFY_EVENT_MASK	((u16) 0xFFFF)
+
+#define ISRESERVED(event_id, reserved_event)	\
+			(((event_id & NOTIFY_EVENT_MASK) >= reserved_event) || \
+			((event_id >> 16) == NOTIFY_SYSTEMKEY))
+
+/* This structure defines attributes for initialization of the notify module. */
+struct notify_config {
+	u32 num_events;
+	/* Number of events to be supported */
+	u32 send_event_poll_count;
+	/* Poll for specified amount before send_event times out */
+	u32 num_lines;
+	/* Max. number of interrupt lines between a single pair of processors */
+	u32 reserved_events;
+	/* Number of reserved events to be supported */
+};
+
+/* This structure defines the configuration structure for initialization
+ * of the notify object. */
+struct notify_params {
+	u32 reserved; /* Reserved field */
+};
+
+
+/* Function to get the default configuration for the notify module. */
+void notify_get_config(struct notify_config *cfg);
+
+/* Function to setup the notify module */
+int notify_setup(struct notify_config *cfg);
+
+/* Function to destroy the notify module */
+int notify_destroy(void);
+
+/* Function to create an instance of notify driver */
+struct notify_object *notify_create(void *driver_handle, u16 remote_proc_id,
+			u16 line_id, const struct notify_params *params);
+
+/* Function to delete an instance of notify driver */
+int notify_delete(struct notify_object **handle_ptr);
+
+/* Function to call device specific the notify module setup */
+int notify_attach(u16 proc_id, void *shared_addr);
+
+/* Function to destroy the device specific notify module */
+int notify_detach(u16 proc_id);
+
+/* Function registered as callback with the notify driver */
+void notify_exec(struct notify_object *obj, u32 event_id, u32 payload);
+
+
+#endif /* !defined(__NOTIFY_H_) */
diff --git a/arch/arm/plat-omap/include/syslink/_sysmgr.h b/arch/arm/plat-omap/include/syslink/_sysmgr.h
new file mode 100644
index 000000000000..58fbdd378155
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/_sysmgr.h
@@ -0,0 +1,50 @@
+/*
+ *  _sysmgr.h
+ *
+ *  Defines for system manager functions
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef __SYSMGR_H_
+#define __SYSMGR_H_
+
+/* Structure to retrieve the scalability proc info from the slave */
+struct sysmgr_proc_config {
+	u32 proc_id;
+	u32 use_notify;
+	u32 use_messageq;
+	u32 use_heapbuf;
+	u32 use_frameq;
+	u32 use_ringio;
+	u32 use_listmp;
+	u32 use_nameserver;
+	u32 boot_mode;
+};
+
+/* Function to set the boot load page address for a slave */
+void sysmgr_set_boot_load_page(u16 proc_id, u32 boot_load_page);
+
+/* Function to get configuration values for a host object(component/instance) */
+u32 sysmgr_get_object_config(u16 proc_id, void *config, u32 cmd_id, u32 size);
+
+/* Function to put configuration values for a slave object(component/instance)*/
+u32 sysmgr_put_object_config(u16 proc_id, void *config, u32 cmd_id, u32 size);
+
+/* Function to wait for scalability handshake value. */
+void sysmgr_wait_for_scalability_info(u16 proc_id);
+
+/* Function to wait for slave to complete setup */
+void sysmgr_wait_for_slave_setup(u16 proc_id);
+
+
+#endif /* ifndef __SYSMGR_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/atomic_linux.h b/arch/arm/plat-omap/include/syslink/atomic_linux.h
new file mode 100644
index 000000000000..76fd8a1b9dc5
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/atomic_linux.h
@@ -0,0 +1,105 @@
+/*
+*  atomic_linux.h
+*
+*  Atomic operations functions
+*
+*  Copyright (C) 2008-2009 Texas Instruments, Inc.
+*
+*  This package is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License version 2 as
+*  published by the Free Software Foundation.
+*
+*  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+*  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+*  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+*  PURPOSE.
+*/
+
+#ifndef _ATOMIC_LINUX_H
+#define _ATOMIC_LINUX_H
+
+#include <linux/types.h>
+#include <generated/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/atomic.h>
+
+/*
+ * ======== atomic_cmpmask_and_set ========
+ *  Purpose:
+ *  This will compare a mask and set if not equal
+ */
+static inline void atomic_cmpmask_and_set(atomic_t *v, u32 mask, u32 val)
+{
+	s32	ret;
+	unsigned long flags;
+	atomic_t *atm = v;
+
+	raw_local_irq_save(flags);
+	ret = atm->counter;
+	if (likely(((ret & mask) != mask)))
+		atm->counter = val;
+	raw_local_irq_restore(flags);
+}
+
+/*
+ * ======== atomic_cmpmask_and_set ========
+ *  Purpose:
+ *  This will compare a mask and then check current value less than
+ *  provided value.
+ */
+static inline bool atomic_cmpmask_and_lt(atomic_t *v, u32 mask, u32 val)
+{
+	bool ret = true;
+	atomic_t *atm = v;
+	s32 cur;
+	unsigned long flags;
+
+	raw_local_irq_save(flags);
+	cur = atm->counter;
+	/* Compare mask, if matches then compare val */
+	if (likely(((cur & mask) == mask))) {
+		if (likely(cur >= val))
+			ret = false;
+	}
+	raw_local_irq_restore(flags);
+
+	/* retval = true  if mask matches and current value is less than given
+	*  value */
+	/* retval = false either mask doesnot matches or current value is not
+	*  less than given value */
+	return ret;
+}
+
+
+/*
+ * ======== atomic_cmpmask_and_set ========
+ *  Purpose:
+ *  This will compare a mask and then check current value greater than
+ *  provided value.
+ */
+static inline bool atomic_cmpmask_and_gt(atomic_t *v, u32 mask, u32 val)
+{
+	bool ret = false;
+	atomic_t *atm = v;
+	s32	cur;
+	unsigned long flags;
+
+	raw_local_irq_save(flags);
+	cur = atm->counter;
+	/* Compare mask, if matches then compare val */
+	if (likely(((cur & mask) == mask))) {
+		if (likely(cur > val))
+			ret = true;
+	}
+
+	raw_local_irq_restore(flags);
+	/* retval = true  if mask matches and current value is less than given
+	 *  value */
+	/* etval =false either mask doesnot matches or current value is not
+	 *  greater than given value */
+	return ret;
+}
+
+#endif /* if !defined(_ATOMIC_LINUX_H) */
+
diff --git a/arch/arm/plat-omap/include/syslink/drv_notify.h b/arch/arm/plat-omap/include/syslink/drv_notify.h
new file mode 100644
index 000000000000..2f386170e311
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/drv_notify.h
@@ -0,0 +1,43 @@
+/*
+ * drv_notify.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#if !defined _DRV_NOTIFY_H_
+#define _DRV_NOTIFY_H_
+
+
+/* Module includes */
+#include <syslink/notify_driverdefs.h>
+#include <syslink/_notify.h>
+
+
+/* read function for of Notify driver.*/
+int notify_drv_read(struct file *filp, char *dst, size_t size,
+				loff_t *offset);
+
+/* Linux driver function to map memory regions to user space. */
+int notify_drv_mmap(struct file *filp, struct vm_area_struct *vma);
+
+/* ioctl function for of Linux Notify driver.*/
+int notify_drv_ioctl(struct inode *inode, struct file *filp, u32 cmd,
+						unsigned long args);
+
+void _notify_drv_setup(void);
+
+void _notify_drv_destroy(void);
+
+
+#endif  /* !defined (_DRV_NOTIFY_H_) */
diff --git a/arch/arm/plat-omap/include/syslink/ducatienabler.h b/arch/arm/plat-omap/include/syslink/ducatienabler.h
new file mode 100644
index 000000000000..f2f8023ce8b4
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/ducatienabler.h
@@ -0,0 +1,291 @@
+/*
+ * ducatienabler.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef _DDUCATIMMU_ENABLER_H_
+#define _DDUCATIMMU_ENABLER_H_
+
+#include <linux/types.h>
+#include <linux/mm.h>
+
+#include <syslink/hw_defs.h>
+#include <syslink/hw_mmu.h>
+
+
+#define PAGE_SIZE_4KB				0x1000
+#define PAGE_SIZE_64KB				0x10000
+#define PAGE_SIZE_1MB				0x100000
+#define PAGE_SIZE_16MB				0x1000000
+
+/* Define the Peripheral PAs and their Ducati VAs. */
+#define L4_PERIPHERAL_MBOX			0x4A0F4000
+#define DUCATI_PERIPHERAL_MBOX			0xAA0F4000
+
+#define L4_PERIPHERAL_I2C1			0x48070000
+#define DUCATI_PERIPHERAL_I2C1			0xA8070000
+#define L4_PERIPHERAL_I2C2			0x48072000
+#define DUCATI_PERIPHERAL_I2C2			0xA8072000
+#define L4_PERIPHERAL_I2C3			0x48060000
+#define DUCATI_PERIPHERAL_I2C3			0xA8060000
+
+#define L4_PERIPHERAL_DMA			0x4A056000
+#define DUCATI_PERIPHERAL_DMA			0xAA056000
+
+#define L4_PERIPHERAL_GPIO1			0x4A310000
+#define DUCATI_PERIPHERAL_GPIO1			0xAA310000
+#define L4_PERIPHERAL_GPIO2			0x48055000
+#define DUCATI_PERIPHERAL_GPIO2			0xA8055000
+#define L4_PERIPHERAL_GPIO3			0x48057000
+#define DUCATI_PERIPHERAL_GPIO3			0xA8057000
+
+#define L4_PERIPHERAL_GPTIMER3			0x48034000
+#define DUCATI_PERIPHERAL_GPTIMER3		0xA8034000
+#define L4_PERIPHERAL_GPTIMER4			0x48036000
+#define DUCATI_PERIPHERAL_GPTIMER4		0xA8036000
+#define L4_PERIPHERAL_GPTIMER9			0x48040000
+#define DUCATI_PERIPHERAL_GPTIMER9		0xA8040000
+#define L4_PERIPHERAL_GPTIMER11			0x48088000
+#define DUCATI_PERIPHERAL_GPTIMER11		0xA8088000
+
+#define L4_PERIPHERAL_UART1			0x4806A000
+#define DUCATI_PERIPHERAL_UART1			0xA806A000
+#define L4_PERIPHERAL_UART2			0x4806C000
+#define DUCATI_PERIPHERAL_UART2			0xA806C000
+#define L4_PERIPHERAL_UART3			0x48020000
+#define DUCATI_PERIPHERAL_UART3			0xA8020000
+#define L4_PERIPHERAL_UART4			0x4806E000
+#define DUCATI_PERIPHERAL_UART4			0xA806E000
+
+
+#define L3_TILER_VIEW0_ADDR			0x60000000
+#define DUCATIVA_TILER_VIEW0_ADDR		0x60000000
+#define DUCATIVA_TILER_VIEW0_LEN		0x20000000
+
+
+
+#if 0  /* Original definitions for OMAP4430. */
+/* Define the various Ducati Memory Regions. */
+/* The first 4K page of BOOTVECS is programmed as a TLB entry. The remaining */
+/* three pages are not used and are mapped to minimize number of PTEs */
+#define DUCATI_BOOTVECS_ADDR			0x1000
+#define DUCATI_BOOTVECS_LEN			0x3000
+
+#define DUCATI_EXTMEM_SYSM3_ADDR		0x4000
+#define DUCATI_EXTMEM_SYSM3_LEN			0x1FC000
+
+#define DUCATI_EXTMEM_APPM3_ADDR		0x10000000
+#define DUCATI_EXTMEM_APPM3_LEN			0x200000
+
+#define DUCATI_PRIVATE_SYSM3_DATA_ADDR		0x84000000
+#define DUCATI_PRIVATE_SYSM3_DATA_LEN		0x200000
+
+#define DUCATI_PRIVATE_APPM3_DATA_ADDR		0x8A000000
+#define DUCATI_PRIVATE_APPM3_DATA_LEN		0x200000
+
+#define DUCATI_SHARED_M3_DATA_ADDR		0x90000000
+#define DUCATI_SHARED_M3_DATA_LEN		0x100000
+
+#define DUCATI_SHARED_IPC_ADDR			0x98000000
+#define DUCATI_SHARED_IPC_LEN			0x100000
+
+#define DUCATI_SW_DMM_ADDR			0x80000000
+#define DUCATI_SW_DMM_LEN			0x400000
+#endif
+
+/* OMAP4430 SDC definitions */
+#define L4_PERIPHERAL_L4CFG			0x4A000000
+#define DUCATI_PERIPHERAL_L4CFG			0xAA000000
+
+#define L4_PERIPHERAL_L4PER			0x48000000
+#define DUCATI_PERIPHERAL_L4PER			0xA8000000
+
+#define L3_IVAHD_CONFIG				0x5A000000
+#define DUCATI_IVAHD_CONFIG			0xBA000000
+
+#define L3_IVAHD_SL2				0x5B000000
+#define DUCATI_IVAHD_SL2			0xBB000000
+
+#define L3_TILER_MODE0_1_ADDR			0x60000000
+#define DUCATI_TILER_MODE0_1_ADDR		0x60000000
+#define DUCATI_TILER_MODE0_1_LEN		0x10000000
+
+#define L3_TILER_MODE3_ADDR			0x78000000
+#define DUCATI_TILER_MODE3_ADDR			0x78000000
+#define DUCATI_TILER_MODE3_LEN			0x8000000
+
+#define DUCATI_BOOTVECS_UNUSED_ADDR		0x1000
+#define DUCATI_BOOTVECS_UNUSED_LEN		0x3000
+
+#define DUCATI_MEM_CODE_SYSM3_ADDR		0x4000
+#define DUCATI_MEM_CODE_SYSM3_LEN		0x1FC000
+
+#define DUCATI_MEM_CODE_APPM3_ADDR		0x800000
+#define DUCATI_MEM_CODE_APPM3_LEN		0x200000
+
+#define DUCATI_MEM_CONST_SYSM3_ADDR		0x80000000
+#define DUCATI_MEM_CONST_SYSM3_LEN		0x100000
+
+#define DUCATI_MEM_CONST_APPM3_ADDR		0x80100000
+#define DUCATI_MEM_CONST_APPM3_LEN		0x100000
+
+#define DUCATI_MEM_HEAP_SYSM3_ADDR		0x80200000
+#define DUCATI_MEM_HEAP_SYSM3_LEN		0x100000
+
+#define DUCATI_MEM_HEAP_APPM3_ADDR		0x80300000
+#define DUCATI_MEM_HEAP_APPM3_LEN		0x1000000
+
+#define DUCATI_MEM_MPU_DUCATI_SHMEM_ADDR	0x81300000
+#define DUCATI_MEM_MPU_DUCATI_SHMEM_LEN		0xC00000
+
+#define DUCATI_MEM_IPC_SHMEM_ADDR		0x81F00000
+#define DUCATI_MEM_IPC_SHMEM_LEN		0x100000
+
+#define DUCATI_MEM_IPC_HEAP0_ADDR		0xA0000000
+#define DUCATI_MEM_IPC_HEAP0_LEN		0x55000
+
+#define DUCATI_MEM_IPC_HEAP1_ADDR		0xA0055000
+#define DUCATI_MEM_IPC_HEAP1_LEN		0x55000
+
+#define DUCATI_MEM_IPC_HEAP2_ADDR		0xA00AA000
+#define DUCATI_MEM_IPC_HEAP2_LEN		0x56000
+
+
+/* Types of mapping attributes */
+
+/* MPU address is virtual and needs to be translated to physical addr */
+#define DSP_MAPVIRTUALADDR			0x00000000
+#define DSP_MAPPHYSICALADDR			0x00000001
+
+/* Mapped data is big endian */
+#define DSP_MAPBIGENDIAN			0x00000002
+#define DSP_MAPLITTLEENDIAN			0x00000000
+
+/* Element size is based on DSP r/w access size */
+#define DSP_MAPMIXEDELEMSIZE			0x00000004
+
+/*
+ * Element size for MMU mapping (8, 16, 32, or 64 bit)
+ * Ignored if DSP_MAPMIXEDELEMSIZE enabled
+ */
+#define DSP_MAPELEMSIZE8			0x00000008
+#define DSP_MAPELEMSIZE16			0x00000010
+#define DSP_MAPELEMSIZE32			0x00000020
+#define DSP_MAPELEMSIZE64			0x00000040
+
+#define DSP_MAPVMALLOCADDR			0x00000080
+#define DSP_MAPTILERADDR			0x00000100
+
+
+#define PG_MASK(pg_size) (~((pg_size)-1))
+#define PG_ALIGN_LOW(addr, pg_size) ((addr) & PG_MASK(pg_size))
+#define PG_ALIGN_HIGH(addr, pg_size) (((addr)+(pg_size)-1) & PG_MASK(pg_size))
+
+
+struct mmu_entry {
+	u32 ul_phy_addr ;
+	u32 ul_virt_addr ;
+	u32 ul_size ;
+};
+
+struct memory_entry {
+	u32 ul_virt_addr;
+	u32 ul_size;
+};
+
+#if 0 /* Original definitions for OMAP4430. */
+static const struct mmu_entry l4_map[] = {
+	/*  Mailbox 4KB*/
+	{L4_PERIPHERAL_MBOX, DUCATI_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB},
+	/* I2C 4KB each */
+	{L4_PERIPHERAL_I2C1, DUCATI_PERIPHERAL_I2C1, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_I2C2, DUCATI_PERIPHERAL_I2C2, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_I2C3, DUCATI_PERIPHERAL_I2C3, HW_PAGE_SIZE_4KB},
+	/* DMA 4KB */
+	{L4_PERIPHERAL_DMA, DUCATI_PERIPHERAL_DMA, HW_PAGE_SIZE_4KB},
+	/* GPIO Banks 4KB each */
+	{L4_PERIPHERAL_GPIO1, DUCATI_PERIPHERAL_GPIO1, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPIO2, DUCATI_PERIPHERAL_GPIO2, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPIO3, DUCATI_PERIPHERAL_GPIO3, HW_PAGE_SIZE_4KB},
+	/* GPTimers 4KB each */
+	{L4_PERIPHERAL_GPTIMER3, DUCATI_PERIPHERAL_GPTIMER3, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPTIMER4, DUCATI_PERIPHERAL_GPTIMER4, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPTIMER9, DUCATI_PERIPHERAL_GPTIMER9, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_GPTIMER11, DUCATI_PERIPHERAL_GPTIMER11,
+							HW_PAGE_SIZE_4KB},
+	/* UARTs 4KB each */
+	{L4_PERIPHERAL_UART1, DUCATI_PERIPHERAL_UART1, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_UART2, DUCATI_PERIPHERAL_UART2, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_UART3, DUCATI_PERIPHERAL_UART3, HW_PAGE_SIZE_4KB},
+	{L4_PERIPHERAL_UART4, DUCATI_PERIPHERAL_UART4,
+							HW_PAGE_SIZE_4KB},
+};
+
+static const struct  memory_entry l3_memory_regions[] = {
+	/*  BootVecs regions */
+	{0, (PAGE_SIZE_1MB * 2)},
+	/*  EXTMEM_CORE1: 0x10000000 to 0x100FFFFF */
+	{DUCATI_EXTMEM_APPM3_ADDR, DUCATI_EXTMEM_APPM3_LEN},
+	/*  PRIVATE_SYSM3_DATA*/
+	{DUCATI_PRIVATE_SYSM3_DATA_ADDR, DUCATI_PRIVATE_SYSM3_DATA_LEN},
+	/*  PRIVATE_APPM3_DATA*/
+	{DUCATI_PRIVATE_APPM3_DATA_ADDR, DUCATI_PRIVATE_APPM3_DATA_LEN},
+	/*  SHARED_M3_DATA*/
+	{DUCATI_SHARED_M3_DATA_ADDR, DUCATI_SHARED_M3_DATA_LEN},
+	/*  IPC*/
+	{DUCATI_SHARED_IPC_ADDR, DUCATI_SHARED_IPC_LEN},
+	/*  DMM*/
+	{DUCATI_SW_DMM_ADDR, DUCATI_SW_DMM_LEN},
+};
+#endif
+
+/* OMAP4430 SDC definitions */
+static const struct mmu_entry l4_map[] = {
+	/* TILER 8-bit and 16-bit modes */
+	{L3_TILER_MODE0_1_ADDR, DUCATI_TILER_MODE0_1_ADDR,
+		(HW_PAGE_SIZE_16MB * 16)},
+	/* TILER: Pages-mode */
+	{L3_TILER_MODE3_ADDR, DUCATI_TILER_MODE3_ADDR,
+		(HW_PAGE_SIZE_16MB * 8)},
+	/*  L4_CFG: Covers all modules in L4_CFG 16MB*/
+	{L4_PERIPHERAL_L4CFG, DUCATI_PERIPHERAL_L4CFG, HW_PAGE_SIZE_16MB},
+	/*  L4_PER: Covers all modules in L4_PER 16MB*/
+	{L4_PERIPHERAL_L4PER, DUCATI_PERIPHERAL_L4PER, HW_PAGE_SIZE_16MB},
+	/* IVA_HD Config: Covers all modules in IVA_HD Config space 16MB */
+	{L3_IVAHD_CONFIG, DUCATI_IVAHD_CONFIG, HW_PAGE_SIZE_16MB},
+	/* IVA_HD SL2: Covers all memory in IVA_HD SL2 space 16MB */
+	{L3_IVAHD_SL2, DUCATI_IVAHD_SL2, HW_PAGE_SIZE_16MB},
+};
+
+static const struct  memory_entry l3_memory_regions[] = {
+	/*  MEM_IPC_HEAP0, MEM_IPC_HEAP1, MEM_IPC_HEAP2 */
+	{DUCATI_MEM_IPC_HEAP0_ADDR, PAGE_SIZE_1MB},
+	/*  MEM_INTVECS_SYSM3, MEM_INTVECS_APPM3, MEM_CODE_SYSM3,
+		MEM_CODE_APPM3 */
+	{0, PAGE_SIZE_16MB},
+	/*  MEM_CONST_SYSM3, MEM_CONST_APPM3, MEM_HEAP_SYSM3, MEM_HEAP_APPM3,
+		MEM_MPU_DUCATI_SHMEM, MEM_IPC_SHMEM */
+	{DUCATI_MEM_CONST_SYSM3_ADDR, (PAGE_SIZE_16MB * 2)},
+};
+
+
+void dbg_print_ptes(bool ashow_inv_entries, bool ashow_repeat_entries);
+int ducati_setup(void);
+void ducati_destroy(void);
+u32 get_ducati_virt_mem(void);
+void unmap_ducati_virt_mem(u32 shm_virt_addr);
+int ducati_mem_map(u32 va, u32 da, u32 num_bytes, u32 map_attr);
+int ducati_mem_unmap(u32 da, u32 num_bytes);
+u32 user_va2pa(struct mm_struct *mm, u32 address);
+inline u32 ducati_mem_virtToPhys(u32 da);
+#endif /* _DDUCATIMMU_ENABLER_H_*/
diff --git a/arch/arm/plat-omap/include/syslink/gate.h b/arch/arm/plat-omap/include/syslink/gate.h
new file mode 100644
index 000000000000..1041f752f46c
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/gate.h
@@ -0,0 +1,76 @@
+/*
+ *  gate.h
+ *
+ *  Critical section support.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+/** ============================================================================
+ *  Gates are used by clients to protect concurrent access to critical
+ *  data structures.  Critical data structures are those that must be
+ *  updated by at most one thread at a time.  All code that needs access
+ *  to a critical data structure "enters" a gate (that's associated with the
+ *  data structure) prior to accessing the data, modifies the data structure,
+ *  then "leaves" the gate.
+ *
+ *  A gate is responsible for ensuring that at most one thread at a time
+ *  can enter and execute "inside" the gate.  There are several
+ *  implementations of gates, with different system executation times and
+ *  latency tradoffs.  In addition, some gates must not be entered by certain
+ *  thread types; e.g., a gate that is implemented via a "blocking" semaphore
+ *  must not be called by an interrupt service routine (ISR).
+ *
+ *  A module can be declared "gated" by adding the `@Gated` attribute to the
+ *  module's XDC spec file.  A "gated" module is assigned a module-level gate
+ *  at the configuration time, and that gate is then used to protect critical
+ *  sections in the module's target code. A module-level gate is an instance of
+ *  a module implementing `{@link IGateProvider}` interface. However, gated
+ *  modules do not access their module-level gates directly. They use this
+ *  module to access transparently their module-level gate.
+ *
+ *  Application code that is not a part of any module also has a
+ *  module-level gate, configured through the module `{@link Main}`.
+ *
+ *  Each gated module can optionally create gates on an adhoc basis at
+ *  runtime using the same gate module that was used to create the module
+ *  level gate.
+ *
+ *  Gates that work by disabling all preemption while inside a gate can be
+ *  used to protect data structures accessed by ISRs and other
+ *  threads.  But, if the time required to update the data structure is not
+ *  a small constant, this type of gate may violate a system's real-time
+ *  requirements.
+ *
+ *  Gates have two orthogonal attributes: "blocking" and "preemptible".
+ *  In general, gates that are "blocking" can not be use by code that is
+ *  called by ISRs and gates that are not "preemptible" should only be used to
+ *  to protect data manipulated by code that has small constant execution
+ *  time.
+ *  ============================================================================
+ */
+
+
+#ifndef GATE_H_0xAF6F
+#define GATE_H_0xAF6F
+
+#include <igateprovider.h>
+
+extern struct igateprovider_object *gate_system_handle;
+
+/* Function to enter a Gate */
+int *gate_enter_system(void);
+
+/* Function to leave a Gate */
+void gate_leave_system(int *key);
+
+
+#endif /* GATE_H_0xAF6F */
diff --git a/arch/arm/plat-omap/include/syslink/gate_remote.h b/arch/arm/plat-omap/include/syslink/gate_remote.h
new file mode 100644
index 000000000000..e8115d59535a
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/gate_remote.h
@@ -0,0 +1,34 @@
+/*
+ *  gate_remote.h
+ *
+ *  This includes the functions to handle remote gates
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _NAMESERVER_REMOTE_H_
+#define _GATE_REMOTE_H_
+
+#include <linux/types.h>
+
+/*
+ *  This function is used to enter in to a remote gate
+ */
+int gate_remote_enter(void *ghandle, u32 key);
+
+/*
+ *  This function is used to leave from a remote gate
+ */
+int gate_remote_leave(void *ghandle, u32 key);
+
+#endif /* _GATE_REMOTE_H_ */
+
diff --git a/arch/arm/plat-omap/include/syslink/gatehwspinlock.h b/arch/arm/plat-omap/include/syslink/gatehwspinlock.h
new file mode 100644
index 000000000000..afcfcbde7d45
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/gatehwspinlock.h
@@ -0,0 +1,158 @@
+/*
+ *  gatehwspinlock.h
+ *
+ *  Defines for gatehwspinlock.
+ *
+ *  Copyright(C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+#ifndef GATEHWSPINLOCK_H_
+#define GATEHWSPINLOCK_H_
+
+/* Module headers */
+#include <multiproc.h>
+#include <gatemp.h>
+#include <igatempsupport.h>
+#include <sharedregion.h>
+
+/* Unique module ID. */
+#define GATEHWSPINLOCK_MODULEID			(0xF416)
+
+/* =============================================================================
+ * Module Success and Failure codes
+ * =============================================================================
+ */
+/* Argument passed to a function is invalid. */
+#define GATEHWSPINLOCK_E_INVALIDARG       -1
+
+/* Memory allocation failed. */
+#define GATEHWSPINLOCK_E_MEMORY           -2
+
+/* the name is already registered or not. */
+#define GATEHWSPINLOCK_E_BUSY             -3
+
+/* Generic failure. */
+#define GATEHWSPINLOCK_E_FAIL             -4
+
+/* name not found in the nameserver. */
+#define GATEHWSPINLOCK_E_NOTFOUND         -5
+
+/* Module is not initialized. */
+#define GATEHWSPINLOCK_E_INVALIDSTATE     -6
+
+/* Instance is not created on this processor. */
+#define GATEHWSPINLOCK_E_NOTONWER         -7
+
+/* Remote opener of the instance has not closed the instance. */
+#define GATEHWSPINLOCK_E_REMOTEACTIVE     -8
+
+/* Indicates that the instance is in use. */
+#define GATEHWSPINLOCK_E_INUSE            -9
+
+/* Failure in OS call. */
+#define GATEHWSPINLOCK_E_OSFAILURE        -10
+
+/* Version mismatch error. */
+#define GATEHWSPINLOCK_E_VERSION          -11
+
+/* Operation successful. */
+#define GATEHWSPINLOCK_S_SUCCESS            0
+
+/* The GATEHWSPINLOCK module has already been setup in this process. */
+#define GATEHWSPINLOCK_S_ALREADYSETUP     1
+
+
+/* =============================================================================
+ * Macros
+ * =============================================================================
+ */
+
+/* Q_BLOCKING */
+#define GATEHWSEM_Q_BLOCKING   (1)
+
+/* Q_PREEMPTING */
+#define GATEHWSEM_Q_PREEMPTING (2)
+
+
+/* =============================================================================
+ * Enums & Structures
+ * =============================================================================
+ */
+
+/* Structure defining config parameters for the gatehwspinlock module. */
+struct gatehwspinlock_config {
+	enum gatemp_local_protect default_protection;
+	/* Default module-wide local context protection level. The level of
+	 * protection specified here determines which local gate is created
+	 * per gatehwspinlock instance for local protection during create.
+	 * The instance configuration parameter may be used to override this
+	 * module setting per instance.  The configuration used here should
+	 * reflect both the context in which enter and leave are to be called,
+	 * as well as the maximum level protection needed locally.
+	 */
+	u32 base_addr;
+	/* Device-specific base address for HW Semaphore subsystem in HOST OS
+	 * address space, this is updated in Ipc module */
+	u32 num_locks;
+	/* Device-specific number of semphores in the HW Semaphore subsystem */
+};
+
+/* Structure defining config parameters for the gatehwspinlock instances. */
+struct gatehwspinlock_params {
+	IGATEMPSUPPORT_SUPERPARAMS;
+};
+
+
+/* Inherit everything from IGateMPSupport */
+IGATEMPSUPPORT_INHERIT(gatehwspinlock);
+
+
+/* =============================================================================
+ * APIs
+ * =============================================================================
+ */
+/* Function to get the default configuration for the gatehwspinlock module. */
+void gatehwspinlock_get_config(struct gatehwspinlock_config *config);
+
+/* Function to setup the gatehwspinlock module. */
+int gatehwspinlock_setup(const struct gatehwspinlock_config *config);
+
+/* Function to destroy the gatehwspinlock module */
+int gatehwspinlock_destroy(void);
+
+/* Get the default parameters for the gatehwspinlock instance. */
+void gatehwspinlock_params_init(struct gatehwspinlock_params *params);
+
+/* Function to create an instance of gatehwspinlock */
+void *gatehwspinlock_create(enum igatempsupport_local_protect local_protect,
+				const struct gatehwspinlock_params *params);
+
+/* Function to delete an instance of gatehwspinlock */
+int gatehwspinlock_delete(void **handle_ptr);
+
+/* Function to enter the gatehwspinlock instance */
+int *gatehwspinlock_enter(void *handle);
+
+/* Function to leave the gatehwspinlock instance */
+void gatehwspinlock_leave(void *handle, int *key);
+
+/* Function to return the shared memory requirement for a single instance */
+u32 gatehwspinlock_shared_mem_req(const struct gatehwspinlock_params *params);
+
+/* Function to return the number of instances configured in the module. */
+u32 gatehwspinlock_get_num_instances(void);
+
+/* Function to initialize the locks module. */
+void gatehwspinlock_locks_init(void);
+
+#endif /* ifndef GATEHWSPINLOCK_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/gatemp.h b/arch/arm/plat-omap/include/syslink/gatemp.h
new file mode 100644
index 000000000000..ea0af5b692fa
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/gatemp.h
@@ -0,0 +1,237 @@
+/*
+ *  gatemp.h
+ *
+ *  gatemp wrapper defines
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _GATEMP_H_
+#define _GATEMP_H_
+
+#include <sharedregion.h>
+
+/* Unique module ID. */
+#define GATEMP_MODULEID		(0xAF70)
+
+/* The resource is still in use */
+#define GateMP_S_BUSY		2
+
+/* The module has been already setup */
+#define GateMP_S_ALREADYSETUP	1
+
+/* Operation is successful. */
+#define GateMP_S_SUCCESS	0
+
+/* Generic failure. */
+#define GateMP_E_FAIL		-1
+
+/* The specified entity already exists. */
+#define GateMP_E_ALREADYEXISTS	-4
+
+/* Unable to find the specified entity. */
+#define GateMP_E_NOTFOUND	-5
+
+/* Operation timed out. */
+#define GateMP_E_TIMEOUT	-6
+
+/* Module is not initialized. */
+#define GateMP_E_INVALIDSTATE	-7
+
+/* A failure occurred in an OS-specific call */
+#define GateMP_E_OSFAILURE	-8
+
+/* Specified resource is not available */
+#define GateMP_E_RESOURCE	-9
+
+/* Operation was interrupted. Please restart the operation */
+#define GateMP_E_RESTART	-10
+
+/* Gate is local gate not remote */
+#define GateMP_E_LOCALGATE	-11
+
+
+/*
+ * A set of local context protection levels
+ *
+ *  Each member corresponds to a specific local processor gates used for
+ *  local protection.
+ *
+ *  In linux user mode, the following are the mapping for the constants
+ *   - INTERRUPT -> [N/A]
+ *   - TASKLET   -> [N/A]
+ *   - THREAD    -> GateMutex
+ *   - PROCESS   -> GateMutex
+ *
+ *  In linux kernel mode, the following are the mapping for the constants
+ *   - INTERRUPT -> [Interrupts disabled]
+ *   - TASKLET   -> GateMutex
+ *   - THREAD    -> GateMutex
+ *   - PROCESS   -> GateMutex
+ *
+ *  For SYS/BIOS users, the following are the mappings for the constants
+ *   - INTERRUPT -> GateHwi: disables interrupts
+ *   - TASKLET   -> GateSwi: disables Swi's (software interrupts)
+ *   - THREAD    -> GateMutexPri: based on Semaphores
+ *   - PROCESS   -> GateMutexPri: based on Semaphores
+ */
+enum gatemp_local_protect {
+	GATEMP_LOCALPROTECT_NONE = 0,
+	/* Use no local protection */
+
+	GATEMP_LOCALPROTECT_INTERRUPT = 1,
+	/* Use the INTERRUPT local protection level */
+
+	GATEMP_LOCALPROTECT_TASKLET = 2,
+	/* Use the TASKLET local protection level */
+
+	GATEMP_LOCALPROTECT_THREAD = 3,
+	/* Use the THREAD local protection level */
+
+	GATEMP_LOCALPROTECT_PROCESS = 4
+	/* Use the PROCESS local protection level */
+};
+
+/*
+ * Type of remote Gate
+ *
+ *  Each member corresponds to a specific type of remote gate.
+ *  Each enum value corresponds to the following remote protection levels:
+ *   - NONE      -> No remote protection (the gatemp instance will
+ *                  exclusively offer local protection configured in
+ *                  #GateMP_Params::local_protect
+ *   - SYSTEM    -> Use the SYSTEM remote protection level (default for
+ *                  remote protection
+ *   - CUSTOM1   -> Use the CUSTOM1 remote protection level
+ *   - CUSTOM2   -> Use the CUSTOM2 remote protection level
+ */
+enum gatemp_remote_protect {
+	GATEMP_REMOTEPROTECT_NONE = 0,
+	/* No remote protection (the gatemp instance will exclusively
+	 * offer local protection configured in #GateMP_Params::local_protect)
+	 */
+
+	GATEMP_REMOTEPROTECT_SYSTEM = 1,
+	/* Use the SYSTEM remote protection level (default remote protection) */
+
+	GATEMP_REMOTEPROTECT_CUSTOM1 = 2,
+	/* Use the CUSTOM1 remote protection level */
+
+	GATEMP_REMOTEPROTECT_CUSTOM2 = 3
+	/* Use the CUSTOM2 remote protection level */
+};
+
+/* Structure defining parameters for the gatemp module. */
+struct gatemp_params {
+	char *name;
+	/* Name of this instance.
+	 * The name (if not NULL) must be unique among all GateMP
+	 * instances in the entire system.  When creating a new
+	 * heap, it is necessary to supply an instance name.
+	 */
+
+	u32 region_id;
+	/* Shared region ID
+	 * The index corresponding to the shared region from which shared memory
+	 * will be allocated.
+	 * If not specified, the default of '0' will be used.
+	 */
+
+	void *shared_addr;
+	/* Physical address of the shared memory
+	 * This value can be left as 'null' unless it is required to place the
+	 * heap at a specific location in shared memory.  If sharedAddr is null,
+	 * then shared memory for a new instance will be allocated from the
+	 * heap belonging to the region identified by #GateMP_Params::region_id.
+	 */
+
+	enum gatemp_local_protect local_protect;
+	/* Local protection level.
+	 * The default value is #GATEMP_LOCALPROTECT_THREAD */
+
+	enum gatemp_remote_protect remote_protect;
+	/* Remote protection level
+	 * The default value is #GATEMP_REMOTEPROTECT_SYSTEM */
+};
+
+/* Structure defining config parameters for the gatemp module. */
+struct gatemp_config {
+	u32 num_resources;
+	/* Maximum number of resources */
+	enum gatemp_local_protect default_protection;
+	u32 max_name_len;
+	u32 max_runtime_entries;
+};
+
+
+/* Close an opened gate */
+int gatemp_close(void **handle_ptr);
+
+/* Create a gatemp instance */
+void *gatemp_create(const struct gatemp_params *params);
+
+/* Delete a created gatemp instance */
+int gatemp_delete(void **handle_ptr);
+
+/* Get the default remote gate */
+void *gatemp_get_default_remote(void);
+
+/* Open a created gatemp by name */
+int gatemp_open(char *name, void **handle_ptr);
+
+/* Open a created gatemp by address */
+int gatemp_open_by_addr(void *shared_addr, void **handle_ptr);
+
+/* Initialize a gatemp parameters struct */
+void gatemp_params_init(struct gatemp_params *params);
+
+/* Amount of shared memory required for creation of each instance */
+uint gatemp_shared_mem_req(const struct gatemp_params *params);
+
+/* Enter the gatemp */
+int *gatemp_enter(void *handle);
+
+/* Leave the gatemp */
+void gatemp_leave(void *handle, int *key);
+
+/* Get the default configuration for the gatemp module. */
+void gatemp_get_config(struct gatemp_config *cfg_params);
+
+/* Setup the gatemp module. */
+s32 gatemp_setup(const struct gatemp_config *cfg);
+
+/* Function to destroy the gatemp module. */
+s32 gatemp_destroy(void);
+
+/* Function to attach gatemp to a remote processor */
+int gatemp_attach(u16 remote_proc_id, void *shared_addr);
+
+/* Function to detach gatemp from a remote processor */
+int gatemp_detach(u16 remote_proc_id, void *shared_addr);
+
+/* Function to start gatemp */
+int gatemp_start(void *shared_addr);
+
+/* Function to start gatemp */
+int gatemp_stop(void);
+
+/* Function to create local gatemp */
+void *gatemp_create_local(enum gatemp_local_protect local_protect);
+
+/* Function to return size required in shared region 0 */
+uint gatemp_get_region0_reserved_size(void);
+
+/* Function to get the shared address of a gatemp object */
+u32 *gatemp_get_shared_addr(void *obj);
+
+
+#endif /* _GATEMP_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/gatemp_ioctl.h b/arch/arm/plat-omap/include/syslink/gatemp_ioctl.h
new file mode 100644
index 000000000000..203f6b1a4961
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/gatemp_ioctl.h
@@ -0,0 +1,177 @@
+/*
+ *  gatemp_ioctl.h
+ *
+ *  Definitions of gatemp ioctl types and structures.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _GATEMP_IOCTL_H_
+#define _GATEMP_IOCTL_H_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#include <ipc_ioctl.h>
+#include <gatemp.h>
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+#define GATEMP_IOC_MAGIC		IPC_IOC_MAGIC
+/*  IOCTL command ID definitions for GateMP */
+enum CMD_GATEMP {
+	GATEMP_GETCONFIG = GATEMP_BASE_CMD,
+	GATEMP_SETUP,
+	GATEMP_DESTROY,
+	GATEMP_PARAMS_INIT,
+	GATEMP_CREATE,
+	GATEMP_DELETE,
+	GATEMP_OPEN,
+	GATEMP_CLOSE,
+	GATEMP_ENTER,
+	GATEMP_LEAVE,
+	GATEMP_SHAREDMEMREQ,
+	GATEMP_OPENBYADDR,
+	GATEMP_GETDEFAULTREMOTE
+};
+
+/*
+ *  IOCTL command IDs for GateMP
+ */
+/* Command for gatemp_get_config */
+#define CMD_GATEMP_GETCONFIG		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_GETCONFIG,		\
+					struct gatemp_cmd_args)
+/* Command for gatemp_setup */
+#define CMD_GATEMP_SETUP		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_SETUP,			\
+					struct gatemp_cmd_args)
+/* Command for gatemp_destroy */
+#define CMD_GATEMP_DESTROY		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_DESTROY,			\
+					struct gatemp_cmd_args)
+/* Command for gatemp_params_init */
+#define CMD_GATEMP_PARAMS_INIT		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_PARAMS_INIT,		\
+					struct gatemp_cmd_args)
+/* Command for gatemp_create */
+#define CMD_GATEMP_CREATE		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_CREATE,			\
+					struct gatemp_cmd_args)
+/* Command for gatemp_delete */
+#define CMD_GATEMP_DELETE		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_DELETE,			\
+					struct gatemp_cmd_args)
+/* Command for gatemp_open */
+#define CMD_GATEMP_OPEN			_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_OPEN,			\
+					struct gatemp_cmd_args)
+/* Command for gatemp_close */
+#define CMD_GATEMP_CLOSE		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_CLOSE,			\
+					struct gatemp_cmd_args)
+/* Command for gatemp_enter */
+#define CMD_GATEMP_ENTER		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_ENTER,			\
+					struct gatemp_cmd_args)
+/* Command for gatemp_leave */
+#define CMD_GATEMP_LEAVE		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_LEAVE,			\
+					struct gatemp_cmd_args)
+/* Command for gatemp_shared_mem_req */
+#define CMD_GATEMP_SHAREDMEMREQ		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_SHAREDMEMREQ,		\
+					struct gatemp_cmd_args)
+/* Command for gatemp_open_by_addr */
+#define CMD_GATEMP_OPENBYADDR		_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_OPENBYADDR,		\
+					struct gatemp_cmd_args)
+/* Command for gatemp_get_default_remote */
+#define CMD_GATEMP_GETDEFAULTREMOTE	_IOWR(GATEMP_IOC_MAGIC,		\
+					GATEMP_GETDEFAULTREMOTE,	\
+					struct gatemp_cmd_args)
+
+/* Command arguments for GateMP */
+struct gatemp_cmd_args {
+	union {
+		struct {
+			struct gatemp_params *params;
+		} params_init;
+
+		struct {
+			struct gatemp_config *config;
+		} get_config;
+
+		struct {
+			struct gatemp_config *config;
+		} setup;
+
+		struct {
+			void *handle;
+			struct gatemp_params *params;
+			u32 name_len;
+			u32 *shared_addr_srptr;
+		} create;
+
+		struct {
+			void *handle;
+		} delete_instance;
+
+		struct {
+			void *handle;
+			char *name;
+			u32 name_len;
+			u32 *shared_addr_srptr;
+		} open;
+
+		struct {
+			void *handle;
+			u32 *shared_addr_srptr;
+		} open_by_addr;
+
+		struct {
+			void *handle;
+		} close;
+
+		struct {
+			void *handle;
+			int *flags;
+		} enter;
+
+		struct {
+			void *handle;
+			int *flags;
+		} leave;
+
+		struct {
+			struct gatemp_params *params;
+			u32 ret_val;
+		} shared_mem_req;
+
+		struct {
+			void *handle;
+		} get_default_remote;
+	} args;
+
+	s32 api_status;
+};
+
+
+/*
+ * ioctl interface function for gatemp
+ */
+int gatemp_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args);
+
+#endif /* _GATEMP_IOCTL_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/gatempdefs.h b/arch/arm/plat-omap/include/syslink/gatempdefs.h
new file mode 100644
index 000000000000..d12d8f84414c
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/gatempdefs.h
@@ -0,0 +1,116 @@
+/*
+ *  gatemp.h
+ *
+ *  Definitions of gatemp support proxies
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _GATEMPDEFS_H_
+#define _GATEMPDEFS_H_
+
+
+/* Utilities headers */
+#include <gatepeterson.h>
+#include <gatehwspinlock.h>
+/* Enable once ported - GateMPSupportNull may not be needed
+#include <_GateMPSupportNull.h>
+#include <GateMPSupportNull.h>
+*/
+
+#if 1 /* Enable when SpinLock is available */
+#define gatemp_remote_system_proxy_params_init	gatehwspinlock_params_init
+#define gatemp_remote_custom1_proxy_params_init	gatepeterson_params_init
+#define gatemp_remote_custom2_proxy_params_init	gatepeterson_params_init
+#define gatemp_remote_system_proxy_create	gatehwspinlock_create
+#define gatemp_remote_custom1_proxy_create	gatepeterson_create
+#define gatemp_remote_custom2_proxy_create	gatepeterson_create
+#define gatemp_remote_system_proxy_delete	gatehwspinlock_delete
+#define gatemp_remote_custom1_proxy_delete	gatepeterson_delete
+#define gatemp_remote_custom2_proxy_delete	gatepeterson_delete
+#define gatemp_remote_system_proxy_params	struct gatehwspinlock_params
+#define gatemp_remote_custom1_proxy_params	struct gatepeterson_params
+#define gatemp_remote_custom2_proxy_params	struct gatepeterson_params
+#define gatemp_remote_system_proxy_shared_mem_req	\
+						gatehwspinlock_shared_mem_req
+#define gatemp_remote_custom1_proxy_shared_mem_req	\
+						gatepeterson_shared_mem_req
+#define gatemp_remote_custom2_proxy_shared_mem_req	\
+						gatepeterson_shared_mem_req
+#define gatemp_remote_system_proxy_get_num_instances	\
+						gatehwspinlock_get_num_instances
+#define gatemp_remote_custom1_proxy_get_num_instances	\
+						gatepeterson_get_num_instances
+#define gatemp_remote_custom2_proxy_get_num_instances	\
+						gatepeterson_get_num_instances
+#define gatemp_remote_system_proxy_locks_init	gatehwspinlock_locks_init
+#define gatemp_remote_custom1_proxy_locks_init	gatepeterson_locks_init
+#define gatemp_remote_custom2_proxy_locks_init	gatepeterson_locks_init
+#define gatemp_remote_system_proxy_handle	void *
+#define gatemp_remote_custom1_proxy_handle	void *
+#define gatemp_remote_custom2_proxy_handle	void *
+#define gatemp_remote_system_proxy_open_by_addr	gatehwspinlock_open_by_addr
+#define gatemp_remote_custom1_proxy_open_by_addr	\
+						gatepeterson_open_by_addr
+#define gatemp_remote_custom2_proxy_open_by_addr	\
+						gatepeterson_open_by_addr
+#define gatemp_remote_system_proxy_enter	gatehwspinlock_enter
+#define gatemp_remote_system_proxy_leave	gatehwspinlock_leave
+#define gatemp_remote_custom1_proxy_enter	gatepeterson_enter
+#define gatemp_remote_custom1_proxy_leave	gatepeterson_leave
+#define gatemp_remote_custom2_proxy_enter	gatepeterson_enter
+#define gatemp_remote_custom2_proxy_leave	gatepeterson_leave
+#else
+#define gatemp_remote_system_proxy_params_init	gatepeterson_params_init
+#define gatemp_remote_custom1_proxy_params_init	gatepeterson_params_init
+#define gatemp_remote_custom2_proxy_params_init	gatepeterson_params_init
+#define gatemp_remote_system_proxy_create	gatepeterson_create
+#define gatemp_remote_custom1_proxy_create	gatepeterson_create
+#define gatemp_remote_custom2_proxy_create	gatepeterson_create
+#define gatemp_remote_system_proxy_delete	gatepeterson_delete
+#define gatemp_remote_custom1_proxy_delete	gatepeterson_delete
+#define gatemp_remote_custom2_proxy_delete	gatepeterson_delete
+#define gatemp_remote_system_proxy_params	struct gatepeterson_params
+#define gatemp_remote_custom1_proxy_params	struct gatepeterson_params
+#define gatemp_remote_custom2_proxy_params	struct gatepeterson_params
+#define gatemp_remote_system_proxy_shared_mem_req	\
+						gatepeterson_shared_mem_req
+#define gatemp_remote_custom1_proxy_shared_mem_req	\
+						gatepeterson_shared_mem_req
+#define gatemp_remote_custom2_proxy_shared_mem_req	\
+						gatepeterson_shared_mem_req
+#define gatemp_remote_system_proxy_get_num_instances	\
+						gatepeterson_get_num_instances
+#define gatemp_remote_custom1_proxy_get_num_instances	\
+						gatepeterson_get_num_instances
+#define gatemp_remote_custom2_proxy_get_num_instances	\
+						gatepeterson_get_num_instances
+#define gatemp_remote_system_proxy_locks_init	gatepeterson_locks_init
+#define gatemp_remote_custom1_proxy_locks_init	gatepeterson_locks_init
+#define gatemp_remote_custom2_proxy_locks_init	gatepeterson_locks_init
+#define gatemp_remote_system_proxy_handle	void *
+#define gatemp_remote_custom1_proxy_handle	void *
+#define gatemp_remote_custom2_proxy_handle	void *
+#define gatemp_remote_system_proxy_open_by_addr	gatepeterson_open_by_addr
+#define gatemp_remote_custom1_proxy_open_by_addr	\
+						gatepeterson_open_by_addr
+#define gatemp_remote_custom2_proxy_open_by_addr	\
+						gatepeterson_open_by_addr
+#define gatemp_remote_system_proxy_enter	gatepeterson_enter
+#define gatemp_remote_system_proxy_leave	gatepeterson_leave
+#define gatemp_remote_custom1_proxy_enter	gatepeterson_enter
+#define gatemp_remote_custom1_proxy_leave	gatepeterson_leave
+#define gatemp_remote_custom2_proxy_enter	gatepeterson_enter
+#define gatemp_remote_custom2_proxy_leave	gatepeterson_leave
+#endif
+
+#endif /* _GATEMPDEFS_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/gatepeterson.h b/arch/arm/plat-omap/include/syslink/gatepeterson.h
new file mode 100644
index 000000000000..461ebe06f193
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/gatepeterson.h
@@ -0,0 +1,140 @@
+/*
+ *  gatepeterson.h
+ *
+ *  The Gate Peterson Algorithm for mutual exclusion of shared memory.
+ *  Current implementation works for 2 processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _GATEPETERSON_H_
+#define _GATEPETERSON_H_
+
+#include <linux/types.h>
+
+#include <igatempsupport.h>
+
+/*
+ *  GATEPETERSON_MODULEID
+ *  Unique module ID
+ */
+#define GATEPETERSON_MODULEID       (0xF415)
+
+/*
+ *  A set of context protection levels that each correspond to
+ *  single processor gates used for local protection
+ */
+enum gatepeterson_protect {
+	GATEPETERSON_PROTECT_DEFAULT	= 0,
+	GATEPETERSON_PROTECT_NONE	= 1,
+	GATEPETERSON_PROTECT_INTERRUPT	= 2,
+	GATEPETERSON_PROTECT_TASKLET	= 3,
+	GATEPETERSON_PROTECT_THREAD	= 4,
+	GATEPETERSON_PROTECT_PROCESS	= 5,
+	GATEPETERSON_PROTECT_END_VALUE	= 6
+};
+
+/*
+ *  Structure defining config parameters for the Gate Peterson
+ *  module
+ */
+struct gatepeterson_config {
+	enum gatepeterson_protect default_protection;
+	/*!< Default module-wide local context protection level. The level of
+	* protection specified here determines which local gate is created per
+	* GatePeterson instance for local protection during create. The instance
+	* configuration parameter may be usedto override this module setting per
+	* instance.  The configuration used here should reflect both the context
+	* in which enter and leave are to be called,as well as the maximum level
+	* of protection needed locally.
+	*/
+	u32 num_instances;
+	/*!< Maximum number of instances supported by the GatePeterson module */
+
+};
+
+/*
+ *  Structure defining config parameters for the Gate Peterson
+ *  instances
+ */
+struct gatepeterson_params {
+	IGATEMPSUPPORT_SUPERPARAMS;
+};
+
+/*
+ *  Function to initialize the parameter structure
+ */
+void gatepeterson_get_config(struct gatepeterson_config *config);
+
+/*
+ *  Function to initialize GP module
+ */
+int gatepeterson_setup(const struct gatepeterson_config *config);
+
+/*
+ *  Function to destroy the GP module
+ */
+int gatepeterson_destroy(void);
+
+/*
+ *  Function to initialize the parameter structure
+ */
+void gatepeterson_params_init(struct gatepeterson_params *params);
+
+/*
+ *  Function to create an instance of GatePeterson
+ */
+void *gatepeterson_create(enum igatempsupport_local_protect local_protect,
+				const struct gatepeterson_params *params);
+
+/*
+ *  Function to delete an instance of GatePeterson
+ */
+int gatepeterson_delete(void **gphandle);
+
+/*
+ *  Function to open a previously created instance by address
+ */
+int gatepeterson_open_by_addr(enum igatempsupport_local_protect local_protect,
+				void *shared_addr, void **gphandle);
+
+/*
+ *  Function to close a previously opened instance
+ */
+int gatepeterson_close(void **gphandle);
+
+/*
+ * Function to enter the gate peterson
+ */
+int *gatepeterson_enter(void *gphandle);
+
+/*
+ *Function to leave the gate peterson
+ */
+void gatepeterson_leave(void *gphandle, int *key);
+
+/*
+ * Function to return the shared memory requirement
+ */
+u32 gatepeterson_shared_mem_req(const struct gatepeterson_params *params);
+
+/*
+ * Function to return the number of instances configured in the module.
+ */
+u32 gatepeterson_get_num_instances(void);
+
+/*
+ * Function to initialize the locks module.
+ */
+void gatepeterson_locks_init(void);
+
+#endif /* _GATEPETERSON_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/gt.h b/arch/arm/plat-omap/include/syslink/gt.h
new file mode 100644
index 000000000000..95e3feb18e7b
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/gt.h
@@ -0,0 +1,320 @@
+
+/*
+ * gt.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ *  ======== gt.h ========
+ *  Purpose:
+ *	There are two definitions that affect which portions of trace
+ *	are acutally compiled into the client: GT_TRACE and GT_ASSERT. If
+ *	GT_TRACE is set to 0 then all trace statements (except for assertions)
+ *	will be compiled out of the client. If GT_ASSERT is set to 0 then
+ *	assertions will be compiled out of the client. GT_ASSERT can not be
+ *	set to 0 unless GT_TRACE is also set to 0 (i.e. GT_TRACE == 1 implies
+ *	GT_ASSERT == 1).
+ *
+ *! Revision History
+ *! ================
+ *! 02-Feb-2000 rr:	Renamed this file to gtce.h. GT CLASS and trace
+ *!			definitions are WinCE Specific.
+ *! 03-Jan-1997	ge	Replaced "GT_" prefix to GT_Config structure members
+ *!			to eliminate preprocessor confusion with other macros.
+ */
+#include <linux/types.h>
+#ifndef GT_
+#define GT_
+
+#ifndef GT_TRACE
+#define GT_TRACE 0	/* 0 = "trace compiled out"; 1 = "trace active" */
+#endif
+
+/* #include <syslink/host_os.h> */
+
+typedef s32(*Fxn)();	/* generic function type */
+
+
+#if !defined(GT_ASSERT) || GT_TRACE
+#define GT_ASSERT 1
+#endif
+
+struct GT_Config {
+	Fxn PRINTFXN;
+	Fxn PIDFXN;
+	Fxn TIDFXN;
+	Fxn ERRORFXN;
+};
+
+extern struct GT_Config *GT;
+
+struct gt_mask {
+	char *modName;
+	u8 *flags;
+} ;
+
+/*
+ *  New GT Class defenitions.
+ *
+ *  The following are the explanations and how it could be used in the code
+ *
+ *  -   GT_ENTER	On Entry to Functions
+ *
+ *  -   GT_1CLASS	Display level of debugging status- Object/Automatic
+ *			variables
+ *  -   GT_2CLASS	---- do ----
+ *
+ *  -   GT_3CLASS	 ---- do ---- + It can be used(recommended) for debug
+ *			status in the ISR, IST
+ *  -   GT_4CLASS	---- do ----
+ *
+ *  -   GT_5CLASS	Display entry for module init/exit functions
+ *
+ *  -   GT_6CLASS	Warn whenever SERVICES function fails
+ *
+ *  -   GT_7CLASS	Warn failure of Critical failures
+ *
+ */
+
+#define GT_ENTER	((u8)0x01)
+#define GT_1CLASS	((u8)0x02)
+#define GT_2CLASS	((u8)0x04)
+#define GT_3CLASS	((u8)0x08)
+#define GT_4CLASS	((u8)0x10)
+#define GT_5CLASS	((u8)0x20)
+#define GT_6CLASS	((u8)0x40)
+#define GT_7CLASS	((u8)0x80)
+#define GT_LEAVE	((u8)0x02)
+
+#ifdef _LINT_
+
+/* LINTLIBRARY */
+
+/*
+ *  ======== GT_assert ========
+ */
+/* ARGSUSED */
+void GT_assert(struct gt_mask mask, s32 expr)
+{
+}
+
+/*
+ *  ======== GT_config ========
+ */
+/* ARGSUSED */
+void GT_config(struct GT_Config config)
+{
+}
+
+/*
+ *  ======== GT_create ========
+ */
+/* ARGSUSED */
+void GT_create(struct gt_mask *mask, char *modName)
+{
+}
+
+/*
+ *  ======== GT_curline ========
+ *  Purpose:
+ *	Returns the current source code line number. Is useful for performing
+ *	branch testing using trace.  For example,
+ *
+ *	gt_1trace(curTrace, GT_1CLASS,
+ *	  "in module XX_mod, executing line %u\n", GT_curline());
+ */
+/* ARGSUSED */
+u16 GT_curline(void)
+{
+	return (u16)NULL;
+}
+
+/*
+ *  ======== GT_exit ========
+ */
+/* ARGSUSED */
+void GT_exit(void)
+{
+}
+
+/*
+ *  ======== GT_init ========
+ */
+/* ARGSUSED */
+void GT_init(void)
+{
+}
+
+/*
+ *  ======== GT_query ========
+ */
+/* ARGSUSED */
+bool GT_query(struct gt_mask mask, u8 class)
+{
+	return false;
+}
+
+/*
+ *  ======== GT_set ========
+ *  sets trace mask according to settings
+ */
+
+/* ARGSUSED */
+void GT_set(char *settings)
+{
+}
+
+/*
+ *  ======== GT_setprintf ========
+ *  sets printf function
+ */
+
+/* ARGSUSED */
+void GT_setprintf(Fxn fxn)
+{
+}
+
+/* ARGSUSED */
+void gt_0trace(struct gt_mask mask, u8 class, char *format)
+{
+}
+
+/* ARGSUSED */
+void gt_1trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void gt_2trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void gt_3trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void gt_4trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void gt_5trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+/* ARGSUSED */
+void GT_6trace(struct gt_mask mask, u8 class, char *format, ...)
+{
+}
+
+#else
+
+#define	GT_BOUND	26	/* 26 letters in alphabet */
+
+extern void _GT_create(struct gt_mask *mask, char *modName);
+
+#define GT_exit()
+
+extern void GT_init(void);
+extern void _GT_set(char *str);
+extern s32 _GT_trace(struct gt_mask *mask, char *format, ...);
+
+#if GT_ASSERT == 0
+
+#define GT_assert(mask, expr)
+#define GT_config(config)
+#define GT_configInit(config)
+#define GT_seterror(fxn)
+
+#else
+
+extern struct GT_Config _GT_params;
+
+#define GT_assert(mask, expr) \
+	(!(expr) ? \
+		printk(KERN_ALERT "assertion violation: %s, line %d\n", \
+				__FILE__, __LINE__), NULL : NULL)
+
+#define GT_config(config)		(_GT_params = *(config))
+#define GT_configInit(config)		(*(config) = _GT_params)
+#define GT_seterror(fxn)		(_GT_params.ERRORFXN = (Fxn)(fxn))
+
+#endif
+
+#if GT_TRACE == 0
+
+#define GT_curline()			((u16)__LINE__)
+#define GT_create(mask, modName)
+#define GT_exit()
+#define GT_init()
+#define GT_set(settings)
+#define GT_setprintf(fxn)
+
+#define GT_query(mask, class)		false
+
+#define gt_0trace(mask, class, format)
+#define gt_1trace(mask, class, format, arg1)
+#define gt_2trace(mask, class, format, arg1, arg2)
+#define gt_3trace(mask, class, format, arg1, arg2, arg3)
+#define gt_4trace(mask, class, format, arg1, arg2, arg3, arg4)
+#define gt_5trace(mask, class, format, arg1, arg2, arg3, arg4, arg5)
+#define GT_6trace(mask, class, format, arg1, arg2, arg3, arg4, arg5, arg6)
+
+#else				/* GT_TRACE == 1 */
+
+#define GT_create(mask, modName)	_GT_create((mask), (modName))
+#define GT_curline()			((u16)__LINE__)
+#define GT_set(settings)		_GT_set(settings)
+#define GT_setprintf(fxn)		(_GT_params.PRINTFXN = (Fxn)(fxn))
+
+#define GT_query(mask, class) ((*(mask).flags & (class)))
+
+#define gt_0trace(mask, class, format) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format)) : 0)
+
+#define gt_1trace(mask, class, format, arg1) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1)) : 0)
+
+#define gt_2trace(mask, class, format, arg1, arg2) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2)) : 0)
+
+#define gt_3trace(mask, class, format, arg1, arg2, arg3) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2), (arg3)) : 0)
+
+#define gt_4trace(mask, class, format, arg1, arg2, arg3, arg4) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4)) : 0)
+
+#define gt_5trace(mask, class, format, arg1, arg2, arg3, arg4, arg5) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4), (arg5)) \
+	 : 0)
+
+#define GT_6trace(mask, class, format, arg1, arg2, arg3, arg4, arg5, arg6) \
+	((*(mask).flags & (class)) ? \
+	_GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4), (arg5), \
+	(arg6)) : 0)
+
+#endif				/* GT_TRACE */
+
+#endif				/* _LINT_ */
+
+#endif				/* GTCE_ */
diff --git a/arch/arm/plat-omap/include/syslink/heap.h b/arch/arm/plat-omap/include/syslink/heap.h
new file mode 100644
index 000000000000..1d3e9fb237de
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/heap.h
@@ -0,0 +1,97 @@
+/*
+ *  heap.h
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _HEAP_H_
+#define _HEAP_H_
+
+#include <linux/types.h>
+
+/*
+ *  Structure defining memory related statistics
+ */
+struct memory_stats{
+	u32 total_size; /* Total memory size */
+	u32 total_free_size; /* Total free memory size */
+	u32 largest_free_size; /* Largest free memory size */
+};
+
+/*!
+ *  ======== extendedstats ========
+ *  Stats structure for the get_extended_stats API.
+ *
+ *  max_allocated_blocks: The maximum number of blocks allocated
+ *  from this heap at any single point in time during the lifetime of this
+ *  heap instance.
+ *
+ *  num_allocated_blocks: The total number of blocks currently
+ *  allocated in this Heap instance.
+ */
+struct heap_extended_stats {
+	u32 max_allocated_blocks;
+	u32 num_allocated_blocks;
+};
+
+/*
+ *  Structure defining config parameters for the heapbuf module
+ */
+struct heap_config {
+	u32 max_name_len; /* Maximum length of name */
+	bool track_max_allocs; /* Track the max number of allocated blocks */
+};
+
+/*
+ *  Structure for the handle for the heap
+ */
+struct heap_object {
+	void* (*alloc) (void *handle, u32 size, u32 align);
+	int (*free) (void *handle, void *block, u32 size);
+	void (*get_stats) (void *handle, struct memory_stats *stats);
+	void (*get_extended_stats) (void *handle,
+					struct heap_extended_stats *stats);
+	bool (*is_blocking) (void *handle);
+	void *obj;
+};
+
+/*
+ *  Allocate a block
+ */
+void *sl_heap_alloc(void *handle, u32 size, u32 align);
+
+/*
+ *  Frees the block to this Heap
+ */
+int sl_heap_free(void *handle, void *block, u32 size);
+
+/*
+ * Get heap statistics
+ */
+void sl_heap_get_stats(void *handle, struct memory_stats *stats);
+
+/*
+ * Get heap extended statistics
+ */
+void sl_heap_get_extended_stats(void *hphandle,
+				struct heap_extended_stats *stats);
+
+/*
+ * Indicates whether a heap will block on free or alloc
+ */
+bool sl_heap_is_blocking(void *hphandle);
+
+#endif /* _HEAP_H_ */
+
diff --git a/arch/arm/plat-omap/include/syslink/heapbufmp.h b/arch/arm/plat-omap/include/syslink/heapbufmp.h
new file mode 100644
index 000000000000..56699f3bc968
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/heapbufmp.h
@@ -0,0 +1,253 @@
+/*
+ *  heapbufmp.h
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _HEAPBUFMP_H_
+#define _HEAPBUFMP_H_
+
+#include <linux/types.h>
+#include <heap.h>
+#include <listmp.h>
+
+/*!
+ *  @def	LISTMP_MODULEID
+ *  @brief  Unique module ID.
+ */
+#define HEAPBUFMP_MODULEID	(0x4cd5)
+
+/*
+ *  Creation of Heap Buf succesful.
+*/
+#define HEAPBUFMP_CREATED            (0x05251995)
+
+/*
+ *  Version.
+ */
+#define HEAPBUFMP_VERSION            (1)
+
+/* =============================================================================
+ *  All success and failure codes for the module
+ * =============================================================================
+ */
+
+/*!
+ *  @def    HEAPBUFMP_S_BUSY
+ *  @brief  The resource is still in use
+ */
+#define HEAPBUFMP_S_BUSY               2
+
+/*!
+ *  @def    HEAPBUFMP_S_ALREADYSETUP
+ *  @brief  The module has been already setup
+ */
+#define HEAPBUFMP_S_ALREADYSETUP       1
+
+/*!
+ *  @def    HEAPBUFMP_S_SUCCESS
+ *  @brief  Operation is successful.
+ */
+#define HEAPBUFMP_S_SUCCESS            0
+
+/*!
+ *  @def    HEAPBUFMP_E_FAIL
+ *  @brief  Generic failure.
+ */
+#define HEAPBUFMP_E_FAIL              -1
+
+/*!
+ *  @def    HEAPBUFMP_E_INVALIDARG
+ *  @brief  Argument passed to function is invalid.
+ */
+#define HEAPBUFMP_E_INVALIDARG          -2
+
+/*!
+ *  @def    HEAPBUFMP_E_MEMORY
+ *  @brief  Operation resulted in memory failure.
+ */
+#define HEAPBUFMP_E_MEMORY              -3
+
+/*!
+ *  @def    HEAPBUFMP_E_ALREADYEXISTS
+ *  @brief  The specified entity already exists.
+ */
+#define HEAPBUFMP_E_ALREADYEXISTS       -4
+
+/*!
+ *  @def    HEAPBUFMP_E_NOTFOUND
+ *  @brief  Unable to find the specified entity.
+ */
+#define HEAPBUFMP_E_NOTFOUND            -5
+
+/*!
+ *  @def    HEAPBUFMP_E_TIMEOUT
+ *  @brief  Operation timed out.
+ */
+#define HEAPBUFMP_E_TIMEOUT             -6
+
+/*!
+ *  @def    HEAPBUFMP_E_INVALIDSTATE
+ *  @brief  Module is not initialized.
+ */
+#define HEAPBUFMP_E_INVALIDSTATE        -7
+
+/*!
+ *  @def    HEAPBUFMP_E_OSFAILURE
+ *  @brief  A failure occurred in an OS-specific call  */
+#define HEAPBUFMP_E_OSFAILURE           -8
+
+/*!
+ *  @def    HEAPBUFMP_E_RESOURCE
+ *  @brief  Specified resource is not available  */
+#define HEAPBUFMP_E_RESOURCE            -9
+
+/*!
+ *  @def    HEAPBUFMP_E_RESTART
+ *  @brief  Operation was interrupted. Please restart the operation  */
+#define HEAPBUFMP_E_RESTART             -10
+
+
+/* =============================================================================
+ * Macros
+ * =============================================================================
+ */
+
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+
+/*
+ *  Structure defining config parameters for the HeapBuf module.
+ */
+struct heapbufmp_config {
+	u32 max_name_len; /* Maximum length of name */
+	u32 max_runtime_entries; /* Maximum number of heapbufmp instances */
+				/* that can be created */
+	bool track_allocs; 	/* Track the maximum number of allocated */
+				/* blocks */
+};
+
+/*
+ *  Structure defining parameters for the HeapBuf module
+ */
+struct heapbufmp_params {
+	char *name; /* Name of this instance */
+	u16 region_id; /* Shared region ID */
+	void *shared_addr; /* Physical address of the shared memory */
+	u32 block_size; /* Size (in MAUs) of each block */
+	u32 num_blocks; /* Number of fixed-size blocks */
+	u32 align; /* Alignment (in MAUs, power of 2) of each block */
+	bool exact; /* Only allocate on exact match of rquested size */
+	void *gate; /* GateMP used for critical region management of */
+		    /* the shared memory */
+};
+
+/*
+ *  Stats structure for the getExtendedStats API.
+ */
+struct heapbufmp_extended_stats {
+	u32 max_allocated_blocks;
+	/* maximum number of blocks allocated from this heap instance */
+	u32 num_allocated_blocks;
+	/* total number of blocks currently allocated from this heap instance*/
+};
+
+/* =============================================================================
+ *  APIs
+ * =============================================================================
+ */
+
+/*
+ *  Function to get default configuration for the heapbufmp module
+ */
+int heapbufmp_get_config(struct heapbufmp_config *cfgparams);
+
+/*
+ *  Function to setup the heapbufmp module
+ */
+int heapbufmp_setup(const struct heapbufmp_config *cfg);
+
+/*
+ *  Function to destroy the heapbufmp module
+ */
+int heapbufmp_destroy(void);
+
+/* Initialize this config-params structure with supplier-specified
+ *  defaults before instance creation
+ */
+void heapbufmp_params_init(struct heapbufmp_params *params);
+
+/*
+ *  Creates a new instance of heapbufmp module
+ */
+void *heapbufmp_create(const struct heapbufmp_params *params);
+
+/*
+ * Deletes a instance of heapbufmp module
+ */
+int heapbufmp_delete(void **handle_ptr);
+
+/*
+ *  Opens a created instance of heapbufmp module by name
+ */
+int heapbufmp_open(char *name, void **handle_ptr);
+
+/*
+ *  Opens a created instance of heapbufmp module by address
+ */
+int heapbufmp_open_by_addr(void *shared_addr, void **handle_ptr);
+
+/*
+ *  Closes previously opened/created instance of heapbufmp module
+ */
+int heapbufmp_close(void **handle_ptr);
+
+/*
+ *  Returns the amount of shared memory required for creation
+ *  of each instance
+ */
+int heapbufmp_shared_mem_req(const struct heapbufmp_params *params);
+
+/*
+ *  Allocate a block
+ */
+void *heapbufmp_alloc(void *hphandle, u32 size, u32 align);
+
+/*
+ *  Frees the block to this heapbufmp
+ */
+int heapbufmp_free(void *hphandle, void *block, u32 size);
+
+/*
+ *  Get memory statistics
+ */
+void heapbufmp_get_stats(void *hphandle, struct memory_stats *stats);
+
+/*
+ *  Indicate whether the heap may block during an alloc or free call
+ */
+bool heapbufmp_isblocking(void *handle);
+
+/*
+ *  Get extended statistics
+ */
+void heapbufmp_get_extended_stats(void *hphandle,
+				struct heapbufmp_extended_stats *stats);
+
+
+#endif /* _HEAPBUFMP_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/heapbufmp_ioctl.h b/arch/arm/plat-omap/include/syslink/heapbufmp_ioctl.h
new file mode 100644
index 000000000000..5c801487fc11
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/heapbufmp_ioctl.h
@@ -0,0 +1,232 @@
+/*
+ *  heapbufmp_ioctl.h
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _HEAPBUFMP_IOCTL_
+#define _HEAPBUFMP_IOCTL_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#include <ipc_ioctl.h>
+#include <heapbufmp.h>
+
+
+enum CMD_HEAPBUF {
+	HEAPBUFMP_GETCONFIG = HEAPBUFMP_BASE_CMD,
+	HEAPBUFMP_SETUP,
+	HEAPBUFMP_DESTROY,
+	HEAPBUFMP_PARAMS_INIT,
+	HEAPBUFMP_CREATE,
+	HEAPBUFMP_DELETE,
+	HEAPBUFMP_OPEN,
+	HEAPBUFMP_OPENBYADDR,
+	HEAPBUFMP_CLOSE,
+	HEAPBUFMP_ALLOC,
+	HEAPBUFMP_FREE,
+	HEAPBUFMP_SHAREDMEMREQ,
+	HEAPBUFMP_GETSTATS,
+	HEAPBUFMP_GETEXTENDEDSTATS
+};
+
+/*
+ *  Command for heapbufmp_get_config
+ */
+#define CMD_HEAPBUFMP_GETCONFIG		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_GETCONFIG, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_setup
+ */
+#define CMD_HEAPBUFMP_SETUP		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_SETUP, \
+					struct heapbufmp_cmd_args)
+/*
+ *  Command for heapbufmp_destroy
+ */
+#define CMD_HEAPBUFMP_DESTROY 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_DESTROY, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_prams_init
+ */
+#define CMD_HEAPBUFMP_PARAMS_INIT 	_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_PARAMS_INIT, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_create
+ */
+#define CMD_HEAPBUFMP_CREATE 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_CREATE, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_delete
+ */
+#define CMD_HEAPBUFMP_DELETE 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_DELETE, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_open
+ */
+#define CMD_HEAPBUFMP_OPEN 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_OPEN, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_open_by_addr
+ */
+#define CMD_HEAPBUFMP_OPENBYADDR	_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_OPENBYADDR, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_close
+ */
+#define CMD_HEAPBUFMP_CLOSE 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_CLOSE, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_alloc
+ */
+#define CMD_HEAPBUFMP_ALLOC 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_ALLOC, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_free
+ */
+#define CMD_HEAPBUFMP_FREE		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_FREE, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_shared_mem_req
+ */
+#define CMD_HEAPBUFMP_SHAREDMEMREQ	_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_SHAREDMEMREQ, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_get_stats
+ */
+#define CMD_HEAPBUFMP_GETSTATS		_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_GETSTATS, \
+					struct heapbufmp_cmd_args)
+
+/*
+ *  Command for heapbufmp_get_extended_stats
+ */
+#define CMD_HEAPBUFMP_GETEXTENDEDSTATS	_IOWR(IPC_IOC_MAGIC, \
+					HEAPBUFMP_GETEXTENDEDSTATS, \
+					struct heapbufmp_cmd_args)
+
+
+/*
+ *  Command arguments for heapbuf
+ */
+union heapbufmp_arg {
+	struct {
+		struct heapbufmp_params *params;
+	} params_init;
+
+	struct  {
+		struct heapbufmp_config *config;
+	} get_config;
+
+	struct {
+		struct heapbufmp_config *config;
+	} setup;
+
+	struct {
+		void *handle;
+		struct heapbufmp_params *params;
+		u32 name_len;
+		u32 *shared_addr_srptr;
+		void *knl_gate;
+	} create;
+
+	struct {
+		void *handle;
+	} delete;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+	} open;
+
+	struct {
+		void *handle;
+		u32 *shared_addr_srptr;
+	} open_by_addr;
+
+	struct {
+		void *handle;
+	} close;
+
+	struct {
+		void *handle;
+		u32 size;
+		u32 align;
+		u32 *block_srptr;
+	} alloc;
+
+	struct {
+		void *handle;
+		u32 *block_srptr;
+		u32 size;
+	} free;
+
+	struct {
+		void *handle;
+		struct memory_stats *stats;
+	} get_stats;
+
+	struct {
+		void *handle;
+		struct heapbufmp_extended_stats *stats;
+	} get_extended_stats;
+
+	struct {
+		void *handle;
+		struct heapbufmp_params *params;
+		u32 *shared_addr_srptr;
+		u32 bytes;
+	} shared_mem_req;
+};
+
+/*
+ *  Command arguments for heapbuf
+ */
+struct heapbufmp_cmd_args{
+	union heapbufmp_arg args;
+	s32 api_status;
+};
+
+/*
+ *  This ioctl interface for heapbuf module
+ */
+int heapbufmp_ioctl(struct inode *pinode, struct file *filp,
+			unsigned int cmd, unsigned long  args);
+
+#endif /* _HEAPBUFMP_IOCTL_ */
diff --git a/arch/arm/plat-omap/include/syslink/heapmemmp.h b/arch/arm/plat-omap/include/syslink/heapmemmp.h
new file mode 100644
index 000000000000..bfce85be4b5b
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/heapmemmp.h
@@ -0,0 +1,252 @@
+/*
+ *  heapmemmp.h
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _HEAPMEMMP_H_
+#define _HEAPMEMMP_H_
+
+#include <linux/types.h>
+#include <heap.h>
+#include <listmp.h>
+
+/*!
+ *  @def	LISTMP_MODULEID
+ *  @brief  Unique module ID.
+ */
+#define HEAPMEMMP_MODULEID	(0x4cd7)
+
+/*
+ *  Creation of Heap Buf succesful.
+*/
+#define HEAPMEMMP_CREATED            (0x07041776)
+
+/*
+ *  Version.
+ */
+#define HEAPMEMMP_VERSION            (1)
+
+/* =============================================================================
+ *  All success and failure codes for the module
+ * =============================================================================
+ */
+
+/*!
+ *  @def    HEAPMEMMP_S_BUSY
+ *  @brief  The resource is still in use
+ */
+#define HEAPMEMMP_S_BUSY               2
+
+/*!
+ *  @def    HEAPMEMMP_S_ALREADYSETUP
+ *  @brief  The module has been already setup
+ */
+#define HEAPMEMMP_S_ALREADYSETUP       1
+
+/*!
+ *  @def    HEAPMEMMP_S_SUCCESS
+ *  @brief  Operation is successful.
+ */
+#define HEAPMEMMP_S_SUCCESS            0
+
+/*!
+ *  @def    HEAPMEMMP_E_FAIL
+ *  @brief  Generic failure.
+ */
+#define HEAPMEMMP_E_FAIL              -1
+
+/*!
+ *  @def    HEAPMEMMP_E_INVALIDARG
+ *  @brief  Argument passed to function is invalid.
+ */
+#define HEAPMEMMP_E_INVALIDARG          -2
+
+/*!
+ *  @def    HEAPMEMMP_E_MEMORY
+ *  @brief  Operation resulted in memory failure.
+ */
+#define HEAPMEMMP_E_MEMORY              -3
+
+/*!
+ *  @def    HEAPMEMMP_E_ALREADYEXISTS
+ *  @brief  The specified entity already exists.
+ */
+#define HEAPMEMMP_E_ALREADYEXISTS       -4
+
+/*!
+ *  @def    HEAPMEMMP_E_NOTFOUND
+ *  @brief  Unable to find the specified entity.
+ */
+#define HEAPMEMMP_E_NOTFOUND            -5
+
+/*!
+ *  @def    HEAPMEMMP_E_TIMEOUT
+ *  @brief  Operation timed out.
+ */
+#define HEAPMEMMP_E_TIMEOUT             -6
+
+/*!
+ *  @def    HEAPMEMMP_E_INVALIDSTATE
+ *  @brief  Module is not initialized.
+ */
+#define HEAPMEMMP_E_INVALIDSTATE        -7
+
+/*!
+ *  @def    HEAPMEMMP_E_OSFAILURE
+ *  @brief  A failure occurred in an OS-specific call  */
+#define HEAPMEMMP_E_OSFAILURE           -8
+
+/*!
+ *  @def    HEAPMEMMP_E_RESOURCE
+ *  @brief  Specified resource is not available  */
+#define HEAPMEMMP_E_RESOURCE            -9
+
+/*!
+ *  @def    HEAPMEMMP_E_RESTART
+ *  @brief  Operation was interrupted. Please restart the operation  */
+#define HEAPMEMMP_E_RESTART             -10
+
+
+/* =============================================================================
+ * Macros
+ * =============================================================================
+ */
+
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+
+/*
+ *  Structure defining config parameters for the HeapBuf module.
+ */
+struct heapmemmp_config {
+	u32 max_name_len; /* Maximum length of name */
+	u32 max_runtime_entries; /* Maximum number of heapmemmp instances */
+				/* that can be created */
+};
+
+/*
+ *  Structure defining parameters for the HeapBuf module
+ */
+struct heapmemmp_params {
+	char *name; /* Name of this instance */
+	u16 region_id; /* Shared region ID */
+	void *shared_addr; /* Physical address of the shared memory */
+	u32 shared_buf_size; /* Size of shared buffer */
+	void *gate; /* GateMP used for critical region management of the */
+			/* shared memory */
+};
+
+/*
+ *  Stats structure for the getExtendedStats API.
+ */
+struct heapmemmp_extended_stats {
+	void *buf;
+	/* Local address of the shared buffer */
+
+	u32 size;
+	/* Size of the shared buffer */
+};
+
+/* =============================================================================
+ *  APIs
+ * =============================================================================
+ */
+
+/*
+ *  Function to get default configuration for the heapmemmp module
+ */
+int heapmemmp_get_config(struct heapmemmp_config *cfgparams);
+
+/*
+ *  Function to setup the heapmemmp module
+ */
+int heapmemmp_setup(const struct heapmemmp_config *cfg);
+
+/*
+ *  Function to destroy the heapmemmp module
+ */
+int heapmemmp_destroy(void);
+
+/* Initialize this config-params structure with supplier-specified
+ *  defaults before instance creation
+ */
+void heapmemmp_params_init(struct heapmemmp_params *params);
+
+/*
+ *  Creates a new instance of heapmemmp module
+ */
+void *heapmemmp_create(const struct heapmemmp_params *params);
+
+/*
+ * Deletes a instance of heapmemmp module
+ */
+int heapmemmp_delete(void **handle_ptr);
+
+/*
+ *  Opens a created instance of heapmemmp module by name
+ */
+int heapmemmp_open(char *name, void **handle_ptr);
+
+/*
+ *  Opens a created instance of heapmemmp module by address
+ */
+int heapmemmp_open_by_addr(void *shared_addr, void **handle_ptr);
+
+/*
+ *  Closes previously opened/created instance of heapmemmp module
+ */
+int heapmemmp_close(void **handle_ptr);
+
+/*
+ *  Returns the amount of shared memory required for creation
+ *  of each instance
+ */
+int heapmemmp_shared_mem_req(const struct heapmemmp_params *params);
+
+/*
+ *  Allocate a block
+ */
+void *heapmemmp_alloc(void *hphandle, u32 size, u32 align);
+
+/*
+ *  Frees the block to this heapmemmp
+ */
+int heapmemmp_free(void *hphandle, void *block, u32 size);
+
+/*
+ *  Get memory statistics
+ */
+void heapmemmp_get_stats(void *hphandle, struct memory_stats *stats);
+
+/*
+ *  Indicate whether the heap may block during an alloc or free call
+ */
+bool heapmemmp_isblocking(void *handle);
+
+/*
+ *  Get extended statistics
+ */
+void heapmemmp_get_extended_stats(void *hphandle,
+				       struct heapmemmp_extended_stats *stats);
+/*
+ *  Restore an instance to it's original created state.
+ */
+void heapmemmp_restore(void *handle);
+
+#endif /* _HEAPMEMMP_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/heapmemmp_ioctl.h b/arch/arm/plat-omap/include/syslink/heapmemmp_ioctl.h
new file mode 100644
index 000000000000..f95dad36c45b
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/heapmemmp_ioctl.h
@@ -0,0 +1,243 @@
+/*
+ *  heapmemmp_ioctl.h
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _HEAPMEMMP_IOCTL_
+#define _HEAPMEMMP_IOCTL_
+
+#include <linux/types.h>
+
+#include <ipc_ioctl.h>
+#include <heapmemmp.h>
+
+
+enum CMD_HEAPMEM {
+	HEAPMEMMP_GETCONFIG = HEAPMEMMP_BASE_CMD,
+	HEAPMEMMP_SETUP,
+	HEAPMEMMP_DESTROY,
+	HEAPMEMMP_PARAMS_INIT,
+	HEAPMEMMP_CREATE,
+	HEAPMEMMP_DELETE,
+	HEAPMEMMP_OPEN,
+	HEAPMEMMP_OPENBYADDR,
+	HEAPMEMMP_CLOSE,
+	HEAPMEMMP_ALLOC,
+	HEAPMEMMP_FREE,
+	HEAPMEMMP_SHAREDMEMREQ,
+	HEAPMEMMP_GETSTATS,
+	HEAPMEMMP_GETEXTENDEDSTATS,
+	HEAPMEMMP_RESTORE
+};
+
+/*
+ *  Command for heapmemmp_get_config
+ */
+#define CMD_HEAPMEMMP_GETCONFIG		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_GETCONFIG,\
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_setup
+ */
+#define CMD_HEAPMEMMP_SETUP		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_SETUP, \
+					struct heapmemmp_cmd_args)
+/*
+ *  Command for heapmemmp_destroy
+ */
+#define CMD_HEAPMEMMP_DESTROY 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_DESTROY, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_prams_init
+ */
+#define CMD_HEAPMEMMP_PARAMS_INIT 	_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_PARAMS_INIT, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_create
+ */
+#define CMD_HEAPMEMMP_CREATE 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_CREATE, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_delete
+ */
+#define CMD_HEAPMEMMP_DELETE 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_DELETE, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_open
+ */
+#define CMD_HEAPMEMMP_OPEN 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_OPEN, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_open_by_addr
+ */
+#define CMD_HEAPMEMMP_OPENBYADDR	_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_OPENBYADDR, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_close
+ */
+#define CMD_HEAPMEMMP_CLOSE 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_CLOSE, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_alloc
+ */
+#define CMD_HEAPMEMMP_ALLOC 		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_ALLOC, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_free
+ */
+#define CMD_HEAPMEMMP_FREE		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_FREE, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_shared_mem_req
+ */
+#define CMD_HEAPMEMMP_SHAREDMEMREQ	_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_SHAREDMEMREQ, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_get_stats
+ */
+#define CMD_HEAPMEMMP_GETSTATS		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_GETSTATS, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_get_extended_stats
+ */
+#define CMD_HEAPMEMMP_GETEXTENDEDSTATS	_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_GETEXTENDEDSTATS, \
+					struct heapmemmp_cmd_args)
+
+/*
+ *  Command for heapmemmp_restore
+ */
+#define CMD_HEAPMEMMP_RESTORE		_IOWR(IPC_IOC_MAGIC, \
+					HEAPMEMMP_RESTORE, \
+					struct heapmemmp_cmd_args)
+
+
+/*
+ *  Command arguments for heapmem
+ */
+union heapmemmp_arg {
+	struct {
+		struct heapmemmp_params *params;
+	} params_init;
+
+	struct  {
+		struct heapmemmp_config *config;
+	} get_config;
+
+	struct {
+		struct heapmemmp_config *config;
+	} setup;
+
+	struct {
+		void *handle;
+		struct heapmemmp_params *params;
+		u32 name_len;
+		u32 *shared_addr_srptr;
+		u32 *shared_buf_srptr;
+		void *knl_gate;
+	} create;
+
+	struct {
+		void *handle;
+	} delete;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+	} open;
+
+	struct {
+		void *handle;
+		u32 *shared_addr_srptr;
+	} open_by_addr;
+
+	struct {
+		void *handle;
+	} close;
+
+	struct {
+		void *handle;
+		u32 size;
+		u32 align;
+		u32 *block_srptr;
+	} alloc;
+
+	struct {
+		void *handle;
+		u32 *block_srptr;
+		u32 size;
+	} free;
+
+	struct {
+		void *handle;
+		struct memory_stats *stats;
+	} get_stats;
+
+	struct {
+		void *handle;
+	} restore;
+
+	struct {
+		void *handle;
+		struct heapmemmp_extended_stats *stats;
+	} get_extended_stats;
+
+	struct {
+		struct heapmemmp_params *params;
+		u32 *shared_addr_srptr;
+		u32 bytes;
+	} shared_mem_req;
+};
+
+/*
+ *  Command arguments for heapmem
+ */
+struct heapmemmp_cmd_args{
+	union heapmemmp_arg args;
+	s32 api_status;
+};
+
+/*
+ *  This ioctl interface for heapmem module
+ */
+int heapmemmp_ioctl(struct inode *pinode, struct file *filp,
+			unsigned int cmd, unsigned long  args);
+
+#endif /* _HEAPMEMMP_IOCTL_ */
diff --git a/arch/arm/plat-omap/include/syslink/host_os.h b/arch/arm/plat-omap/include/syslink/host_os.h
new file mode 100644
index 000000000000..2e2164f314fa
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/host_os.h
@@ -0,0 +1,72 @@
+
+/*
+ * host_os.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ *  ======== windows.h ========
+ *
+ *! Revision History
+ *! ================
+ *! 08-Mar-2004 sb Added cacheflush.h to support Dynamic Memory Mapping feature
+ *! 16-Feb-2004 sb Added headers required for consistent_alloc
+ */
+
+#ifndef _HOST_OS_H_
+#define _HOST_OS_H_
+
+#include <generated/autoconf.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <linux/semaphore.h>
+#include <linux/uaccess.h>
+#include <asm/irq.h>
+#include <linux/io.h>
+#include <linux/syscalls.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/stddef.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/file.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/ctype.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/vmalloc.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/pagemap.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+
+/*  ----------------------------------- Macros */
+
+#define SEEK_SET        0	/* Seek from beginning of file.  */
+#define SEEK_CUR        1	/* Seek from current position.  */
+#define SEEK_END        2	/* Seek from end of file.  */
+
+/* TODO -- Remove, once BP defines them */
+#define INT_MAIL_MPU_IRQ        26
+#define INT_DSP_MMU_IRQ        28
+
+#endif
diff --git a/arch/arm/plat-omap/include/syslink/hw_defs.h b/arch/arm/plat-omap/include/syslink/hw_defs.h
new file mode 100644
index 000000000000..440dbb14445e
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/hw_defs.h
@@ -0,0 +1,63 @@
+/*
+ * hw_defs.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef __HW_DEFS_H
+#define __HW_DEFS_H
+
+#include <syslink/GlobalTypes.h>
+
+/* Page size */
+#define HW_PAGE_SIZE_4KB   0x1000
+#define HW_PAGE_SIZE_64KB  0x10000
+#define HW_PAGE_SIZE_1MB   0x100000
+#define HW_PAGE_SIZE_16MB  0x1000000
+
+/* hw_status:  return type for HW API */
+typedef long hw_status;
+
+/* hw_set_clear_t:  Enumerated Type used to set and clear any bit */
+enum hw_set_clear_t {
+	HW_CLEAR,
+	HW_SET
+} ;
+
+/* hw_endianism_t:  Enumerated Type used to specify the endianism
+ *		Do NOT change these values. They are used as bit fields. */
+enum hw_endianism_t {
+	HW_LITTLE_ENDIAN,
+	HW_BIG_ENDIAN
+
+} ;
+
+/* hw_elemnt_siz_t:  Enumerated Type used to specify the element size
+ *		Do NOT change these values. They are used as bit fields. */
+enum hw_elemnt_siz_t {
+	HW_ELEM_SIZE_8BIT,
+	HW_ELEM_SIZE_16BIT,
+	HW_ELEM_SIZE_32BIT,
+	HW_ELEM_SIZE_64BIT
+
+} ;
+
+/* HW_IdleMode_t:  Enumerated Type used to specify Idle modes */
+enum HW_IdleMode_t {
+	HW_FORCE_IDLE,
+	HW_NO_IDLE,
+	HW_SMART_IDLE
+} ;
+
+#endif  /* __HW_DEFS_H */
diff --git a/arch/arm/plat-omap/include/syslink/hw_mbox.h b/arch/arm/plat-omap/include/syslink/hw_mbox.h
new file mode 100644
index 000000000000..f50ef782e66f
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/hw_mbox.h
@@ -0,0 +1,447 @@
+/*
+ * hw_mbox.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef __MBOX_H
+#define __MBOX_H
+
+#include <syslink/hw_defs.h>
+
+
+#define HW_MBOX_INT_NEW_MSG    0x1
+#define HW_MBOX_INT_NOT_FULL   0x2
+#define HW_MBOX_INT_ALL        0x3
+
+/*
+ * DEFINITION:   HW_MBOX_MAX_NUM_MESSAGES
+ *
+ * DESCRIPTION:  Maximum number of messages that mailbox can hald at a time.
+ *
+ *
+ */
+
+#define HW_MBOX_MAX_NUM_MESSAGES   4
+
+
+	/* width in bits of MBOX Id */
+#define HW_MBOX_ID_WIDTH           2
+
+
+/*
+ * TYPE:         enum hw_mbox_id_t
+ *
+ * DESCRIPTION:  Enumerated Type used to specify Mail Box Sub Module Id Number
+ *
+ *
+ */
+	enum hw_mbox_id_t {
+		HW_MBOX_ID_0,
+		HW_MBOX_ID_1,
+		HW_MBOX_ID_2,
+		HW_MBOX_ID_3,
+		HW_MBOX_ID_4,
+		HW_MBOX_ID_5
+	};
+
+/*
+ * TYPE:         enum hw_mbox_userid_t
+ *
+ * DESCRIPTION:  Enumerated Type used to specify Mail box User Id
+ *
+ *
+ */
+	enum hw_mbox_userid_t {
+		HW_MBOX_U0_ARM11,
+		HW_MBOX_U1_UMA,
+		HW_MBOX_U2_IVA,
+		HW_MBOX_U3_ARM11
+	};
+
+#if defined(OMAP3430)
+/*
+* TYPE:         mailbox_context
+*
+* DESCRIPTION:  Mailbox context settings
+*
+*
+*/
+struct mailbox_context {
+	unsigned long sysconfig;
+	unsigned long irqEnable0;
+	unsigned long irqEnable1;
+};
+#endif/* defined(OMAP3430)*/
+
+/*
+* FUNCTION      : hw_mbox_msg_read
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   Description : Base Address of instance of Mailbox module
+*
+*   Identifier  : mail_box_id
+*   Type        : const enum hw_mbox_id_t
+*   Description : Mail Box Sub module Id to read
+*
+* OUTPUTS:
+*
+*   Identifier  : p_read_value
+*   Type        : unsigned long *const
+*   Description : Value read from MailBox
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*   RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*   RET_INVALID_ID      Invalid Id used
+*   RET_EMPTY           Mailbox empty
+*
+* PURPOSE:
+*     : this function reads a unsigned long from the sub module message
+*     box Specified. if there are no messages in the mailbox
+*    then and error is returned.
+*
+*/
+extern long hw_mbox_msg_read(
+		const unsigned long base_address,
+		const enum hw_mbox_id_t mail_box_id,
+		unsigned long *const p_read_value
+	);
+
+/*
+* FUNCTION      : hw_mbox_msg_write
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   Description : Base Address of instance of Mailbox module
+*
+*   Identifier  : mail_box_id
+*   Type        : const enum hw_mbox_id_t
+*   Description : Mail Box Sub module Id to write
+*
+*   Identifier  : write_value
+*   Type        : const unsigned long
+*   Description : Value to write to MailBox
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*   RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*   RET_INVALID_ID      Invalid Id used
+*
+* PURPOSE:: this function writes a unsigned long from the sub module message
+*           box Specified.
+*
+*
+*/
+extern long hw_mbox_msg_write(
+		const unsigned long base_address,
+		const enum hw_mbox_id_t mail_box_id,
+		const unsigned long write_value
+	);
+
+/*
+* FUNCTION      : hw_mbox_is_full
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   Description : Base Address of instance of Mailbox module
+*
+*   Identifier  : mail_box_id
+*   Type        : const enum hw_mbox_id_t
+*   Description : Mail Box Sub module Id to check
+*
+* OUTPUTS:
+*
+*   Identifier  : p_is_full
+*   Type        : unsigned long *const
+*   Description : false means mail box not Full
+*                 true means mailbox full.
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*   RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*   RET_INVALID_ID      Invalid Id used
+*
+* PURPOSE:      : this function reads the full status register for mailbox.
+*
+*
+*/
+extern long hw_mbox_is_full(
+		const unsigned long base_address,
+		const enum hw_mbox_id_t mail_box_id,
+		unsigned long *const p_is_full
+	);
+
+/* -----------------------------------------------------------------
+* FUNCTION      : hw_mbox_nomsg_get
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   Description : Base Address of instance of Mailbox module
+*
+*   Identifier  : mail_box_id
+*   Type        : const enum hw_mbox_id_t
+*   Description : Mail Box Sub module Id to get num messages
+*
+* OUTPUTS:
+*
+*   Identifier  : p_num_msg
+*   Type        : unsigned long *const
+*   Description : Number of messages in mailbox
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*   RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*   RET_INVALID_ID      Inavlid ID input at parameter
+*
+* PURPOSE:
+*    : this function gets number of messages in a specified mailbox.
+*
+*
+*/
+extern long hw_mbox_nomsg_get(
+		const unsigned long base_address,
+		const enum hw_mbox_id_t mail_box_id,
+		unsigned long *const p_num_msg
+	);
+
+/*
+* FUNCTION      : hw_mbox_event_enable
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*
+*   Identifier  : mail_box_id
+*   Type        : const enum hw_mbox_id_t
+*   Description : Mail Box Sub module Id to enable
+*
+*   Identifier  : user_id
+*   Type        : const enum hw_mbox_userid_t
+*   Description : Mail box User Id to enable
+*
+*   Identifier  : enableIrq
+*   Type        : const unsigned long
+*   Description : Irq value to enable
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*    RET_BAD_NULL_PARAM  A Pointer Paramater was set to NULL
+*    RET_INVALID_ID      Invalid Id used
+*
+* PURPOSE:      : this function enables the specified IRQ.
+*
+*
+*/
+extern long hw_mbox_event_enable(
+		const unsigned long base_address,
+		const enum hw_mbox_id_t mail_box_id,
+		const enum hw_mbox_userid_t user_id,
+		const unsigned long events
+	);
+
+/*
+* FUNCTION      : hw_mbox_event_disable
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*  RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*
+*   Identifier  : mail_box_id
+*   Type        : const enum hw_mbox_id_t
+*   Description : Mail Box Sub module Id to disable
+*
+*   Identifier  : user_id
+*   Type        : const enum hw_mbox_userid_t
+*   Description : Mail box User Id to disable
+*
+*   Identifier  : enableIrq
+*   Type        : const unsigned long
+*   Description : Irq value to disable
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*                 RET_BAD_NULL_PARAM  A Pointer Paramater was set to NULL
+*                 RET_INVALID_ID      Invalid Id used
+*
+* PURPOSE:      : this function disables the specified IRQ.
+*
+*
+*/
+extern long hw_mbox_event_disable(
+		const unsigned long base_address,
+		const enum hw_mbox_id_t mail_box_id,
+		const enum hw_mbox_userid_t user_id,
+		const unsigned long events
+	);
+
+/*
+* FUNCTION      : hw_mbox_event_status
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   Description : Base Address of instance of Mailbox module
+*
+*   Identifier  : mail_box_id
+*   Type        : const enum hw_mbox_id_t
+*   Description : Mail Box Sub module Id to clear
+*
+*   Identifier  : user_id
+*   Type        : const enum hw_mbox_userid_t
+*   Description : Mail box User Id to clear
+*
+* OUTPUTS:
+*
+*   Identifier  : pIrqStatus
+*   Type        : pMBOX_Int_t *const
+*   Description : The value in IRQ status register
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*   RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*   RET_INVALID_ID      Invalid Id used
+*
+* PURPOSE:      : this function gets the status of the specified IRQ.
+*
+*
+*/
+extern long hw_mbox_event_status(
+		const unsigned long base_address,
+		const enum hw_mbox_id_t mail_box_id,
+		const enum hw_mbox_userid_t user_id,
+		unsigned long *const p_eventStatus
+	);
+
+/*
+* FUNCTION      : hw_mbox_event_ack
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   Description : Base Address of instance of Mailbox module
+*
+*   Identifier  : mail_box_id
+*   Type        : const enum hw_mbox_id_t
+*   Description : Mail Box Sub module Id to set
+*
+*   Identifier  : user_id
+*   Type        : const enum hw_mbox_userid_t
+*   Description : Mail box User Id to set
+*
+*   Identifier  : irqStatus
+*   Type        : const unsigned long
+*   Description : The value to write IRQ status
+*
+* OUTPUTS:
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*                 RET_BAD_NULL_PARAM  Address Paramater was set to 0
+*                 RET_INVALID_ID      Invalid Id used
+*
+* PURPOSE:      : this function sets the status of the specified IRQ.
+*
+*
+*/
+extern long hw_mbox_event_ack(
+		const unsigned long base_address,
+		const enum hw_mbox_id_t mail_box_id,
+		const enum hw_mbox_userid_t user_id,
+		const unsigned long event
+	);
+
+#if defined(OMAP3430)
+/* ---------------------------------------------------------------
+* FUNCTION      : hw_mbox_save_settings
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   Description : Base Address of instance of Mailbox module
+*
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*   RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*   RET_INVALID_ID      Invalid Id used
+*    RET_EMPTY           Mailbox empty
+*
+* PURPOSE:      : this function saves the context of mailbox
+*
+* ----------------------------------------------------------------
+*/
+extern long hw_mbox_save_settings(unsigned long baseAddres);
+
+/*
+* FUNCTION      : hw_mbox_restore_settings
+*
+* INPUTS:
+*
+*   Identifier  : base_address
+*   Type        : const unsigned long
+*   Description : Base Address of instance of Mailbox module
+*
+*
+* RETURNS:
+*
+*   Type        : ReturnCode_t
+*   Description : RET_OK              No errors occured
+*   RET_BAD_NULL_PARAM  Address/pointer Paramater was set to 0/NULL
+*   RET_INVALID_ID      Invalid Id used
+*   RET_EMPTY           Mailbox empty
+*
+* PURPOSE:      : this function restores the context of mailbox
+*
+*
+*/
+extern long hw_mbox_restore_settings(unsigned long baseAddres);
+#endif/* defined(OMAP3430)*/
+
+#endif  /* __MBOX_H */
+
diff --git a/arch/arm/plat-omap/include/syslink/hw_mmu.h b/arch/arm/plat-omap/include/syslink/hw_mmu.h
new file mode 100644
index 000000000000..3463fe1e4086
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/hw_mmu.h
@@ -0,0 +1,171 @@
+/*
+ * hw_mbox.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef __HW_MMU_H
+#define __HW_MMU_H
+
+#include <linux/types.h>
+
+/* Bitmasks for interrupt sources */
+#define HW_MMU_TRANSLATION_FAULT   0x2
+#define HW_MMU_ALL_INTERRUPTS      0x1F
+
+#define HW_MMU_COARSE_PAGE_SIZE 0x400
+
+/* hw_mmu_mixed_size_t:  Enumerated Type used to specify whether to follow
+			CPU/TLB Element size */
+enum hw_mmu_mixed_size_t {
+	HW_MMU_TLBES,
+	HW_MMU_CPUES
+
+} ;
+
+/* hw_mmu_map_attrs_t:  Struct containing MMU mapping attributes */
+struct hw_mmu_map_attrs_t {
+	enum hw_endianism_t     endianism;
+	enum hw_elemnt_siz_t   element_size;
+	enum hw_mmu_mixed_size_t  mixedSize;
+} ;
+
+extern hw_status hw_mmu_enable(const u32 base_address);
+
+extern hw_status hw_mmu_disable(const u32 base_address);
+
+extern hw_status hw_mmu_numlocked_set(const u32 base_address,
+				      u32 num_lcked_entries);
+
+extern hw_status hw_mmu_victim_numset(const u32 base_address,
+				      u32 vctm_entry_num);
+
+/* For MMU faults */
+extern hw_status hw_mmu_eventack(const u32 base_address,
+				 u32 irq_mask);
+
+extern hw_status hw_mmu_event_disable(const u32 base_address,
+				      u32 irq_mask);
+
+extern hw_status hw_mmu_event_enable(const u32 base_address,
+				     u32 irq_mask);
+
+extern hw_status hw_mmu_event_status(const u32 base_address,
+				     u32 *irq_mask);
+
+extern hw_status hw_mmu_flt_adr_rd(const u32 base_address,
+				   u32 *addr);
+
+/* Set the TT base address */
+extern hw_status hw_mmu_ttbset(const u32 base_address,
+			       u32 ttb_phys_addr);
+
+extern hw_status hw_mmu_twl_enable(const u32 base_address);
+
+extern hw_status hw_mmu_twl_disable(const u32 base_address);
+
+extern hw_status hw_mmu_tlb_flush(const u32 base_address,
+				  u32 virtual_addr,
+				  u32 page_size);
+
+extern hw_status hw_mmu_tlb_flushAll(const u32 base_address);
+
+extern hw_status hw_mmu_tlb_add(const u32     base_address,
+				u32	   physical_addr,
+				u32	   virtual_addr,
+				u32	   page_size,
+				u32	    entryNum,
+				struct hw_mmu_map_attrs_t *map_attrs,
+				enum hw_set_clear_t    preserve_bit,
+				enum hw_set_clear_t    valid_bit);
+
+
+/* For PTEs */
+extern hw_status hw_mmu_pte_set(const u32     pg_tbl_va,
+				u32	   physical_addr,
+				u32	   virtual_addr,
+				u32	   page_size,
+				struct hw_mmu_map_attrs_t *map_attrs);
+
+extern hw_status hw_mmu_pte_clear(const u32   pg_tbl_va,
+				  u32	 pg_size,
+				  u32	 virtual_addr);
+
+static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va)
+{
+	u32 pte_addr;
+	u32 VA_31_to_20;
+
+	VA_31_to_20  = va >> (20 - 2); /* Left-shift by 2 here itself */
+	VA_31_to_20 &= 0xFFFFFFFCUL;
+	pte_addr = l1_base + VA_31_to_20;
+
+	return pte_addr;
+}
+
+static inline u32 hw_mmu_pte_addr_l2(u32 l2_base, u32 va)
+{
+	u32 pte_addr;
+
+	pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC);
+
+	return pte_addr;
+}
+
+static inline u32 hw_mmu_pte_coarsel1(u32 pte_val)
+{
+	u32 pteCoarse;
+
+	pteCoarse = pte_val & 0xFFFFFC00;
+
+	return pteCoarse;
+}
+
+static inline u32 hw_mmu_pte_sizel1(u32 pte_val)
+{
+	u32 pte_size = 0;
+
+	if ((pte_val & 0x3) == 0x1) {
+		/* Points to L2 PT */
+		pte_size = HW_MMU_COARSE_PAGE_SIZE;
+	}
+
+	if ((pte_val & 0x3) == 0x2) {
+		if (pte_val & (1 << 18))
+			pte_size = HW_PAGE_SIZE_16MB;
+		else
+			pte_size = HW_PAGE_SIZE_1MB;
+	}
+
+	return pte_size;
+}
+
+static inline u32 hw_mmu_pte_sizel2(u32 pte_val)
+{
+	u32 pte_size = 0;
+
+	if (pte_val & 0x2)
+		pte_size = HW_PAGE_SIZE_4KB;
+	else if (pte_val & 0x1)
+		pte_size = HW_PAGE_SIZE_64KB;
+
+	return pte_size;
+}
+extern hw_status hw_mmu_tlb_dump(u32 base_address, bool shw_inv_entries);
+
+extern u32 hw_mmu_pte_phyaddr(u32 pte_val, u32 pte_size);
+
+extern u32 hw_mmu_fault_dump(const u32 base_address);
+
+#endif  /* __HW_MMU_H */
diff --git a/arch/arm/plat-omap/include/syslink/hw_ocp.h b/arch/arm/plat-omap/include/syslink/hw_ocp.h
new file mode 100644
index 000000000000..7277bbfcde33
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/hw_ocp.h
@@ -0,0 +1,60 @@
+/*
+ * hw_ocp.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+#ifndef __HW_OCP_H
+#define __HW_OCP_H
+
+#include <syslink/GlobalTypes.h>
+#include <syslink/hw_ocp.h>
+#include <syslink/hw_defs.h>
+#include <syslink/MBXRegAcM.h>
+#include <syslink/MBXAccInt.h>
+
+
+/*
+* TYPE:         HW_IdleMode_t
+*
+* DESCRIPTION:  Enumerated Type for idle modes in OCP SYSCONFIG register
+*
+*
+*/
+enum hal_ocp_idlemode_t {
+	HW_OCP_FORCE_IDLE,
+	HW_OCP_NO_IDLE,
+	HW_OCP_SMART_IDLE
+};
+
+extern long hw_ocp_soft_reset(const unsigned long base_address);
+
+extern long hw_ocp_soft_reset_isdone(const unsigned long base_address,
+					     unsigned long *reset_is_done);
+
+extern long hw_ocp_idle_modeset(const unsigned long base_address,
+					enum hal_ocp_idlemode_t idle_mode);
+
+extern long hw_ocp_idlemode_get(const unsigned long base_address,
+					enum hal_ocp_idlemode_t *idle_mode);
+
+extern long hw_ocp_autoidle_set(const unsigned long base_address,
+					enum hw_set_clear_t auto_idle);
+
+extern long hw_ocp_autoidle_get(const unsigned long base_address,
+					enum hw_set_clear_t *auto_idle);
+
+#endif  /* __HW_OCP_H */
+
diff --git a/arch/arm/plat-omap/include/syslink/igatempsupport.h b/arch/arm/plat-omap/include/syslink/igatempsupport.h
new file mode 100644
index 000000000000..0f350d123ad1
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/igatempsupport.h
@@ -0,0 +1,74 @@
+/*
+ *  igatempsupport.h
+ *
+ *  Interface implemented by all multiprocessor gates.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ *
+ */
+
+#ifndef _IGATEMPSUPPORT_H_
+#define _IGATEMPSUPPORT_H_
+
+
+/* Invalid Igate */
+#define IGATEMPSUPPORT_NULL		(void *)0xFFFFFFFF
+
+/* Gates with this "quality" may cause the calling thread to block;
+ *  i.e., suspend execution until another thread leaves the gate. */
+#define IGATEMPSUPPORT_Q_BLOCKING	1
+
+/* Gates with this "quality" allow other threads to preempt the thread
+ *  that has already entered the gate. */
+#define IGATEMPSUPPORT_Q_PREEMPTING	2
+
+/* Object embedded in other Gate modules. (Inheritance) */
+#define IGATEMPSUPPORT_SUPERPARAMS		\
+	u32 resource_id;			\
+	bool open_flag;				\
+	u16 region_id;				\
+	void *shared_addr			\
+
+/* All other GateMP modules inherit this. */
+#define IGATEMPSUPPORT_INHERIT(X)		\
+enum X##_local_protect {			\
+	X##_LOCALPROTECT_NONE = 0,		\
+	X##_LOCALPROTECT_INTERRUPT = 1,		\
+	X##_LOCALPROTECT_TASKLET = 2,		\
+	X##_LOCALPROTECT_THREAD = 3,		\
+	X##_LOCALPROTECT_PROCESS = 4		\
+};
+
+/* Paramter initializer. */
+#define IGATEMPSUPPORT_PARAMSINTIALIZER(x)	\
+	(x)->resource_id = 0;			\
+	(x)->open_flag = true;			\
+	(x)->region_id = 0;			\
+	(x)->shared_addr = NULL
+
+enum igatempsupport_local_protect {
+	IGATEMPSUPPORT_LOCALPROTECT_NONE = 0,
+	IGATEMPSUPPORT_LOCALPROTECT_INTERRUPT = 1,
+	IGATEMPSUPPORT_LOCALPROTECT_TASKLET = 2,
+	IGATEMPSUPPORT_LOCALPROTECT_THREAD = 3,
+	IGATEMPSUPPORT_LOCALPROTECT_PROCESS = 4
+};
+
+struct igatempsupport_params {
+	u32 resource_id;
+	bool open_flag;
+	u16 region_id;
+	void *shared_addr;
+};
+
+
+#endif /* ifndef __IGATEMPSUPPORT_H__ */
diff --git a/arch/arm/plat-omap/include/syslink/igateprovider.h b/arch/arm/plat-omap/include/syslink/igateprovider.h
new file mode 100644
index 000000000000..6c10591cca97
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/igateprovider.h
@@ -0,0 +1,121 @@
+/*
+ *  igateprovider.h
+ *
+ *   Interface implemented by all gate providers.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ *
+ */
+/** ============================================================================
+ *  Gates are used serialize access to data structures that are used by more
+ *  than one thread.
+ *
+ *  Gates are responsible for ensuring that only one out of multiple threads
+ *  can access a data structure at a time.  There
+ *  are important scheduling latency and performance considerations that
+ *  affect the "type" of gate used to protect each data structure.  For
+ *  example, the best way to protect a shared counter is to simply disable
+ *  all interrupts before the update and restore the interrupt state after
+ *  the update; disabling all interrupts prevents all thread switching, so
+ *  the update is guaranteed to be "atomic".  Although highly efficient, this
+ *  method of creating atomic sections causes serious system latencies when
+ *  the time required to update the data structure can't be bounded.
+ *
+ *  For example, a memory manager's list of free blocks can grow indefinitely
+ *  long during periods of high fragmentation.  Searching such a list with
+ *  interrupts disabled would cause system latencies to also become unbounded.
+ *  In this case, the best solution is to provide a gate that suspends the
+ *  execution of  threads that try to enter a gate that has already been
+ *  entered; i.e., the gate "blocks" the thread until the thread
+ *  already in the gate leaves.  The time required to enter and leave the
+ *  gate is greater than simply enabling and restoring interrupts, but since
+ *  the time spent within the gate is relatively large, the overhead caused by
+ *  entering and leaving gates will not become a significant percentage of
+ *  overall system time.  More importantly, threads that do not need to
+ *  access the shared data structure are completely unaffected by threads
+ *  that do access it.
+ *  ============================================================================
+ */
+
+
+#ifndef _IGATEPROVIDER_H_
+#define _IGATEPROVIDER_H_
+
+
+/* Invalid Igate */
+#define IGATEPROVIDER_NULL	(struct igateprovider_object *)0xFFFFFFFF
+
+/* Gates with this "quality" may cause the calling thread to block;
+ *  i.e., suspend execution until another thread leaves the gate. */
+#define IGateProvider_Q_BLOCKING	1
+
+/* Gates with this "quality" allow other threads to preempt the thread
+ * that has already entered the gate. */
+#define IGateProvider_Q_PREEMPTING	2
+
+/* Object embedded in other Gate modules. (Inheritance) */
+#define IGATEPROVIDER_SUPEROBJECT	\
+	int *(*enter)(void *);		\
+	void (*leave)(void *, int *)
+
+#define IGATEPROVIDER_OBJECTINITIALIZER(x, y)	\
+	((struct igateprovider_object *)(x))->enter = y##_enter; \
+	((struct igateprovider_object *)(x))->leave = y##_leave;
+
+
+/* Structure for generic gate instance */
+struct igateprovider_object {
+	IGATEPROVIDER_SUPEROBJECT;
+};
+
+
+/*
+ * Enter this gate
+ *
+ * Each gate provider can implement mutual exclusion using different
+ * algorithms; e.g., disabling all scheduling, disabling the scheduling
+ * of all threads below a specified "priority level", suspending the
+ * caller when the gate has been entered by another thread and
+ * re-enabling it when the the other thread leaves the gate.  However,
+ * in all cases, after this method returns that caller has exclusive
+ * access to the data protected by this gate.
+ *
+ * A thread may reenter a gate without blocking or failing.
+ */
+static inline int *igateprovider_enter(struct igateprovider_object *handle)
+{
+	int *key = 0;
+
+	if (handle != IGATEPROVIDER_NULL)
+		key = (handle->enter)((void *)handle);
+	return key;
+}
+
+
+/*
+ * Leave this gate
+ *
+ * This method is only called by threads that have previously entered
+ * this gate via `{@link #enter}`.  After this method returns, the
+ * caller must not access the data structure protected by this gate
+ * (unless the caller has entered the gate more than once and other
+ * calls to `leave` remain to balance the number of previous
+ * calls to `enter`).
+ */
+static inline void igateprovider_leave(struct igateprovider_object *handle,
+						int *key)
+{
+	if (handle != IGATEPROVIDER_NULL)
+		(handle->leave)((void *)handle, key);
+}
+
+#endif /* ifndef _IGATEPROVIDER_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/iobject.h b/arch/arm/plat-omap/include/syslink/iobject.h
new file mode 100644
index 000000000000..4d0c1e6c7e03
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/iobject.h
@@ -0,0 +1,176 @@
+/*
+ *  iobject.h
+ *
+ *  Interface to provide object creation facilities.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+#ifndef _IOBJECT_H_
+#define _IOBJECT_H_
+
+/* ObjType */
+enum ipc_obj_type {
+	IPC_OBJTYPE_CREATESTATIC = 0x1,
+	IPC_OBJTYPE_CREATESTATIC_REGION = 0x2,
+	IPC_OBJTYPE_CREATEDYNAMIC = 0x4,
+	IPC_OBJTYPE_CREATEDYNAMIC_REGION = 0x8,
+	IPC_OBJTYPE_OPENDYNAMIC = 0x10,
+	IPC_OBJTYPE_LOCAL = 0x20
+};
+
+
+/* Object embedded in other module's object */
+#define IOBJECT_SUPEROBJECT		\
+	void *next;			\
+	int status;
+
+/* Generic macro to define a create/delete function for a module */
+#define IOBJECT_CREATE0(MNAME) \
+static struct MNAME##_object *MNAME##_first_object;\
+\
+\
+void *MNAME##_create(const struct MNAME##_params *params)\
+{ \
+	int *key;\
+	struct MNAME##_object *obj = (struct MNAME##_object *)\
+					kmalloc(sizeof(struct MNAME##_object),\
+					GFP_KERNEL);\
+	if (!obj)\
+		return NULL;\
+	memset(obj, 0, sizeof(struct MNAME##_object));\
+	obj->status = MNAME##_instance_init(obj, params);\
+	if (obj->status == 0) { \
+		key = gate_enter_system();\
+		if (MNAME##_first_object == NULL) { \
+			MNAME##_first_object = obj;\
+			obj->next = NULL;\
+		} else { \
+			obj->next = MNAME##_first_object;\
+			MNAME##_first_object = obj;\
+		} \
+		gate_leave_system(key);\
+	} else { \
+		kfree(obj);\
+		obj = NULL;\
+	} \
+	return obj;\
+} \
+\
+\
+int MNAME##_delete(void **handle)\
+{ \
+	int *key;\
+	struct MNAME##_object *temp;\
+	struct MNAME##_object *obj;\
+	\
+	if (handle == NULL) \
+		return -EINVAL;\
+	if (*handle == NULL) \
+		return -EINVAL;\
+	obj = (struct MNAME##_object *)(*handle);\
+	key = gate_enter_system();\
+	if (obj == MNAME##_first_object) \
+		MNAME##_first_object = obj->next;\
+	else { \
+		temp = MNAME##_first_object;\
+		while (temp) { \
+			if (temp->next == obj) { \
+				temp->next = obj->next;\
+				break;\
+			} else { \
+				temp = temp->next;\
+			} \
+		} \
+		if (temp == NULL) { \
+			gate_leave_system(key);\
+			return -EINVAL;\
+		} \
+	} \
+	gate_leave_system(key);\
+	MNAME##_instance_finalize(obj, obj->status);\
+	kfree(obj);\
+	*handle = NULL;\
+	return 0;\
+}
+
+#define IOBJECT_CREATE1(MNAME, ARG) \
+static struct MNAME##_object *MNAME##_first_object;\
+\
+\
+void *MNAME##_create(ARG arg, const struct MNAME##_params *params)\
+{ \
+	int *key;\
+	struct MNAME##_object *obj = (struct MNAME##_object *) \
+					kmalloc(sizeof(struct MNAME##_object),\
+					GFP_KERNEL);\
+	if (!obj) \
+		return NULL;\
+	memset(obj, 0, sizeof(struct MNAME##_object));\
+	obj->status = MNAME##_instance_init(obj, arg, params);\
+	if (obj->status == 0) { \
+		key = gate_enter_system();\
+		if (MNAME##_first_object == NULL) { \
+			MNAME##_first_object = obj;\
+			obj->next = NULL;\
+		} else { \
+			obj->next = MNAME##_first_object;\
+			MNAME##_first_object = obj;\
+		} \
+		gate_leave_system(key);\
+	} else { \
+		kfree(obj);\
+		obj = NULL;\
+	} \
+	return obj;\
+} \
+\
+\
+int MNAME##_delete(void **handle)\
+{ \
+	int *key;\
+	struct MNAME##_object *temp;\
+	struct MNAME##_object *obj;\
+	\
+	if (handle == NULL) \
+		return -EINVAL;\
+	if (*handle == NULL) \
+		return -EINVAL;\
+	obj = (struct MNAME##_object *)(*handle);\
+	key = gate_enter_system();\
+	if (obj == MNAME##_first_object) \
+		MNAME##_first_object = obj->next;\
+	else { \
+		temp = MNAME##_first_object;\
+		while (temp) { \
+			if (temp->next == obj) { \
+				temp->next = obj->next;\
+				break;\
+			} else { \
+				temp = temp->next;\
+			} \
+		} \
+		if (temp == NULL) { \
+			gate_leave_system(key);\
+			return -EINVAL;\
+		} \
+	} \
+	gate_leave_system(key);\
+	MNAME##_instance_finalize(obj, obj->status);\
+	kfree(obj);\
+	*handle = NULL;\
+	return 0;\
+}
+
+
+#endif /* ifndef _IOBJECT_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/ipc.h b/arch/arm/plat-omap/include/syslink/ipc.h
new file mode 100644
index 000000000000..ddd3faeeee11
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/ipc.h
@@ -0,0 +1,167 @@
+/*
+ *  sysmgr.h
+ *
+ *  Defines for System manager.
+ *
+ *  Copyright(C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _IPC_H_
+#define _IPC_H_
+
+
+/* Module headers */
+#include <multiproc.h>
+#include <gatepeterson.h>
+#include <sharedregion.h>
+#include <notify.h>
+#include <notify_ducatidriver.h>
+#include <heap.h>
+#include <heapbufmp.h>
+#include <heapmemmp.h>
+
+
+
+/* Unique module ID. */
+#define IPC_MODULEID			(0xF086)
+
+
+/* =============================================================================
+ * Module Success and Failure codes
+ * =============================================================================
+ */
+/* The resource is still in use */
+#define IPC_S_BUSY		2
+
+/* The module has been already setup */
+#define IPC_S_ALREADYSETUP	1
+
+/* Operation is successful. */
+#define IPC_S_SUCCESS		0
+
+/* Generic failure. */
+#define IPC_E_FAIL		-1
+
+/* Argument passed to function is invalid. */
+#define IPC_E_INVALIDARG	-2
+
+/* Operation resulted in memory failure. */
+#define IPC_E_MEMORY		-3
+
+/* The specified entity already exists. */
+#define IPC_E_ALREADYEXISTS	-4
+
+/* Unable to find the specified entity. */
+#define IPC_E_NOTFOUND		-5
+
+/* Operation timed out. */
+#define IPC_E_TIMEOUT		-6
+
+/* Module is not initialized. */
+#define IPC_E_INVALIDSTATE	-7
+
+/* A failure occurred in an OS-specific call */
+#define IPC_E_OSFAILURE		-8
+
+/* Specified resource is not available */
+#define IPC_E_RESOURCE		-9
+
+/* Operation was interrupted. Please restart the operation */
+#define IPC_E_RESTART		-10
+
+
+/* =============================================================================
+ * Macros
+ * =============================================================================
+ */
+/* IPC_CONTROLCMD_LOADCALLBACK */
+#define IPC_CONTROLCMD_LOADCALLBACK	(0xBABE0000)
+
+/* IPC_CONTROLCMD_STARTCALLBACK */
+#define IPC_CONTROLCMD_STARTCALLBACK	(0xBABE0001)
+
+/* IPC_CONTROLCMD_STOPCALLBACK */
+#define IPC_CONTROLCMD_STOPCALLBACK	(0xBABE0002)
+
+
+/* =============================================================================
+ * Enums & Structures
+ * =============================================================================
+ */
+/* the different options for processor synchronization */
+enum ipc_proc_sync {
+	IPC_PROCSYNC_NONE,          /* don't do any processor sync            */
+	IPC_PROCSYNC_PAIR,          /* sync pair of processors in ipc_attach  */
+	IPC_PROCSYNC_ALL            /* sync all processors, done in ipc_start */
+};
+
+/* ipc configuration structure. */
+struct ipc_config {
+	enum ipc_proc_sync proc_sync;
+	/* the different options for processor synchronization */
+};
+
+/* ipc configuration structure. */
+struct ipc_params {
+	bool setup_messageq;
+	bool setup_notify;
+	bool setup_ipu_pm;
+	bool slave;
+	enum ipc_proc_sync proc_sync;
+};
+
+
+/* =============================================================================
+ * APIs
+ * =============================================================================
+ */
+/* Attach to remote processor */
+int ipc_attach(u16 remote_proc_id);
+
+/* Detach from the remote processor */
+int ipc_detach(u16 remote_proc_id);
+
+/* Reads the config entry from the config area. */
+int ipc_read_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size);
+
+/* Reserves memory, creates default gatemp and heapmemmp */
+int ipc_start(void);
+
+/* Writes the config entry to the config area. */
+int ipc_write_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size);
+
+/* Returns default configuration values for ipc. */
+void ipc_get_config(struct ipc_config *cfg_params);
+
+/* Sets up ipc for this processor. */
+int ipc_setup(const struct ipc_config *cfg_params);
+
+/* Destroys ipc for this processor. */
+int ipc_destroy(void);
+
+/* Creates a ipc. */
+int ipc_create(u16 proc_id, struct ipc_params *params);
+
+/* Function to control a Ipc instance for a slave */
+int ipc_control(u16 proc_id, u32 cmd_id, void *arg);
+
+/* Function to read configuration information from ipc module */
+int ipc_read_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size);
+
+/* Function to write configuration information to ipc module */
+int ipc_write_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size);
+
+/* Clears memory, deletes  default gatemp and heapmemmp */
+int ipc_stop(void);
+
+
+#endif /* ifndef _IPC_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/ipc_ioctl.h b/arch/arm/plat-omap/include/syslink/ipc_ioctl.h
new file mode 100644
index 000000000000..6c16a3d22e12
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/ipc_ioctl.h
@@ -0,0 +1,92 @@
+/*
+ *  ipc_ioctl.h
+ *
+ *  Base file for all TI OMAP IPC ioctl's.
+ *  Linux-OMAP IPC has allocated base 0xEE with a range of 0x00-0xFF.
+ *  (need to get  the real one from open source maintainers)
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _IPC_IOCTL_H
+#define _IPC_IOCTL_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+
+#define IPC_IOC_MAGIC		0xE0
+#define IPC_IOC_BASE		2
+
+enum ipc_command_count {
+	MULTIPROC_CMD_NOS = 4,
+	NAMESERVER_CMD_NOS = 15,
+	HEAPBUFMP_CMD_NOS = 14,
+	SHAREDREGION_CMD_NOS = 13,
+	GATEMP_CMD_NOS = 13,
+	LISTMP_CMD_NOS = 19,
+	MESSAGEQ_CMD_NOS = 18,
+	IPC_CMD_NOS = 5,
+	SYSMEMMGR_CMD_NOS = 6,
+	HEAPMEMMP_CMD_NOS = 15,
+	NOTIFY_CMD_NOS = 18
+};
+
+enum ipc_command_ranges {
+	MULTIPROC_BASE_CMD = IPC_IOC_BASE,
+	MULTIPROC_END_CMD = (MULTIPROC_BASE_CMD + \
+				MULTIPROC_CMD_NOS - 1),
+
+	NAMESERVER_BASE_CMD = 10,
+	NAMESERVER_END_CMD = (NAMESERVER_BASE_CMD + \
+				NAMESERVER_CMD_NOS - 1),
+
+	HEAPBUFMP_BASE_CMD = 30,
+	HEAPBUFMP_END_CMD = (HEAPBUFMP_BASE_CMD + \
+				HEAPBUFMP_CMD_NOS - 1),
+
+	SHAREDREGION_BASE_CMD = 50,
+	SHAREDREGION_END_CMD = (SHAREDREGION_BASE_CMD + \
+				SHAREDREGION_CMD_NOS - 1),
+
+	GATEMP_BASE_CMD = 70,
+	GATEMP_END_CMD = (GATEMP_BASE_CMD + \
+				GATEMP_CMD_NOS - 1),
+
+	LISTMP_BASE_CMD = 90,
+	LISTMP_END_CMD = (LISTMP_BASE_CMD + \
+				LISTMP_CMD_NOS - 1),
+
+	MESSAGEQ_BASE_CMD = 110,
+	MESSAGEQ_END_CMD = (MESSAGEQ_BASE_CMD + \
+				MESSAGEQ_CMD_NOS - 1),
+
+	IPC_BASE_CMD = 130,
+	IPC_END_CMD = (IPC_BASE_CMD + \
+				IPC_CMD_NOS - 1),
+
+	SYSMEMMGR_BASE_CMD = 140,
+	SYSMEMMGR_END_CMD = (SYSMEMMGR_BASE_CMD + \
+				SYSMEMMGR_CMD_NOS - 1),
+
+	HEAPMEMMP_BASE_CMD = 150,
+	HEAPMEMMP_END_CMD = (HEAPMEMMP_BASE_CMD + \
+				HEAPMEMMP_CMD_NOS - 1),
+
+	NOTIFY_BASE_CMD = 170,
+	NOTIFY_END_CMD = (NOTIFY_BASE_CMD + \
+				NOTIFY_CMD_NOS - 1)
+};
+
+int ipc_ioc_router(u32 cmd, ulong arg);
+
+#endif /* _IPC_IOCTL_H */
diff --git a/arch/arm/plat-omap/include/syslink/listmp.h b/arch/arm/plat-omap/include/syslink/listmp.h
new file mode 100644
index 000000000000..31d2429e851f
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/listmp.h
@@ -0,0 +1,146 @@
+/*
+ *  listmp.h
+ *
+ *  The listmp module defines the shared memory doubly linked list.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _LISTMP_H_
+#define _LISTMP_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/list.h>
+/*#include <heap.h>*/
+
+/* =============================================================================
+ *  All success and failure codes for the module
+ * =============================================================================
+ */
+/* The resource is still in use */
+#define LISTMP_S_BUSY		2
+
+/* The module has already been setup */
+#define LISTMP_S_ALREADYSETUP	1
+
+/* Operation is successful. */
+#define LISTMP_SUCCESS		0
+
+/* Generic failure. */
+#define LISTMP_E_FAIL		-1
+
+/* Argument passed to a function is invalid. */
+#define LISTMP_E_INVALIDARG	-2
+
+/* Memory allocation failed. */
+#define LISTMP_E_MEMORY		-3
+
+/* The specified entity already exists. */
+#define LISTMP_E_ALREADYEXISTS	-4
+
+/* Unable to find the specified entity. */
+#define LISTMP_E_NOTFOUND	-5
+
+/* Operation timed out. */
+#define LISTMP_E_TIMEOUT	-6
+
+/* Module is not initialized. */
+#define LISTMP_E_INVALIDSTATE	-7
+
+/* A failure occurred in an OS-specific call */
+#define LISTMP_E_OSFAILURE	-8
+
+/* Specified resource is not available */
+#define LISTMP_E_RESOURCE	-9
+
+/* Operation was interrupted. Please restart the operation */
+#define LISTMP_E_RESTART	-10
+
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+#define VOLATILE volatile
+
+/* Structure defining list element for the ListMP. */
+struct listmp_elem {
+	VOLATILE struct listmp_elem *next;
+	VOLATILE struct listmp_elem *prev;
+};
+
+/* Structure defining config parameters for the ListMP instances. */
+struct listmp_params {
+	/* gatemp instance for critical management of shared memory */
+	void *gatemp_handle;
+	void *shared_addr;  /* physical address of the shared memory */
+	char *name; /* name of the instance */
+	u16 region_id; /* sharedregion id */
+};
+
+
+/* Function initializes listmp parameters */
+void listmp_params_init(struct listmp_params *params);
+
+/* Function to create an instance of ListMP */
+void *listmp_create(const struct listmp_params *params);
+
+/* Function to delete an instance of ListMP */
+int listmp_delete(void **listmp_handle_ptr);
+
+/* Function to open a previously created instance */
+int listmp_open(char *name, void **listmp_handle_ptr);
+
+/* Function to open a previously created instance */
+int listmp_open_by_addr(void *shared_addr, void **listmp_handle_ptr);
+
+/* Function to close a previously opened instance */
+int listmp_close(void **listmp_handle);
+
+/* Function to check if list is empty */
+bool listmp_empty(void *listmp_handle);
+
+/* Retrieves the GateMP handle associated with the ListMP instance. */
+void *listmp_get_gate(void *listmp_handle);
+
+/* Function to get head element from list */
+void *listmp_get_head(void *listmp_handle);
+
+/* Function to get tail element from list */
+void *listmp_get_tail(void *listmp_handle);
+
+/* Function to insert element into list */
+int listmp_insert(void *listmp_handle, struct listmp_elem *new_elem,
+			struct listmp_elem *cur_elem);
+
+/* Function to traverse to next element in list */
+void *listmp_next(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to traverse to prev element in list */
+void *listmp_prev(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to put head element into list */
+int listmp_put_head(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to put tail element into list */
+int listmp_put_tail(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to traverse to remove element from list */
+int listmp_remove(void *listmp_handle, struct listmp_elem *elem);
+
+/* Function to get shared memory requirement for the module */
+uint listmp_shared_mem_req(const struct listmp_params *params);
+
+#endif /* _LISTMP_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/listmp_ioctl.h b/arch/arm/plat-omap/include/syslink/listmp_ioctl.h
new file mode 100644
index 000000000000..bb0825efcef3
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/listmp_ioctl.h
@@ -0,0 +1,268 @@
+/*
+ *  listmp_ioctl.h
+ *
+ *  Definitions of listmp driver types and structures.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _LISTMP_IOCTL_H_
+#define _LISTMP_IOCTL_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Syslink headers */
+#include <ipc_ioctl.h>
+#include <listmp.h>
+#include <sharedregion.h>
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+/* Base command ID for listmp */
+#define LISTMP_IOC_MAGIC		IPC_IOC_MAGIC
+enum listmp_drv_cmd {
+	LISTMP_GETCONFIG = LISTMP_BASE_CMD,
+	LISTMP_SETUP,
+	LISTMP_DESTROY,
+	LISTMP_PARAMS_INIT,
+	LISTMP_CREATE,
+	LISTMP_DELETE,
+	LISTMP_OPEN,
+	LISTMP_CLOSE,
+	LISTMP_ISEMPTY,
+	LISTMP_GETHEAD,
+	LISTMP_GETTAIL,
+	LISTMP_PUTHEAD,
+	LISTMP_PUTTAIL,
+	LISTMP_INSERT,
+	LISTMP_REMOVE,
+	LISTMP_NEXT,
+	LISTMP_PREV,
+	LISTMP_SHAREDMEMREQ,
+	LISTMP_OPENBYADDR
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL command IDs for listmp
+ *  ----------------------------------------------------------------------------
+ */
+/* Command for listmp_get_config */
+#define CMD_LISTMP_GETCONFIG		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_GETCONFIG,		\
+					struct listmp_cmd_args)
+
+/* Command for listmp_setup */
+#define CMD_LISTMP_SETUP		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_SETUP,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_destroy */
+#define CMD_LISTMP_DESTROY		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_DESTROY,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_params_init */
+#define CMD_LISTMP_PARAMS_INIT		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_PARAMS_INIT,		\
+					struct listmp_cmd_args)
+
+/* Command for listmp_create */
+#define CMD_LISTMP_CREATE		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_CREATE,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_delete */
+#define CMD_LISTMP_DELETE		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_DELETE,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_open */
+#define CMD_LISTMP_OPEN			_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_OPEN,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_close */
+#define CMD_LISTMP_CLOSE		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_CLOSE,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_is_empty */
+#define CMD_LISTMP_ISEMPTY		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_ISEMPTY,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_get_head */
+#define CMD_LISTMP_GETHEAD		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_GETHEAD,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_get_tail */
+#define CMD_LISTMP_GETTAIL		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_GETTAIL,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_put_head */
+#define CMD_LISTMP_PUTHEAD		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_PUTHEAD,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_put_tail */
+#define CMD_LISTMP_PUTTAIL		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_PUTTAIL,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_insert */
+#define CMD_LISTMP_INSERT		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_INSERT,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_remove */
+#define CMD_LISTMP_REMOVE		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_REMOVE,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_next */
+#define CMD_LISTMP_NEXT			_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_NEXT,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_prev */
+#define CMD_LISTMP_PREV			_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_PREV,			\
+					struct listmp_cmd_args)
+
+/* Command for listmp_shared_mem_req */
+#define CMD_LISTMP_SHAREDMEMREQ		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_SHAREDMEMREQ,		\
+					struct listmp_cmd_args)
+
+/* Command for listmp_open_by_addr */
+#define CMD_LISTMP_OPENBYADDR		_IOWR(LISTMP_IOC_MAGIC,		\
+					LISTMP_OPENBYADDR,		\
+					struct listmp_cmd_args)
+
+/* Command arguments for listmp */
+struct listmp_cmd_args {
+	union {
+		struct {
+			struct listmp_params *params;
+		} params_init;
+
+		struct {
+			struct listmp_config *config;
+		} get_config;
+
+		struct {
+			struct listmp_config *config;
+		} setup;
+
+		struct {
+			void *listmp_handle;
+			struct listmp_params *params;
+			u32 name_len;
+			u32 shared_addr_srptr;
+			void *knl_gate;
+		} create;
+
+		struct {
+			void *listmp_handle;
+		} delete_instance;
+
+		struct {
+			void *listmp_handle;
+			u32 name_len;
+			char *name;
+		} open;
+
+		struct {
+			void *listmp_handle;
+			u32 shared_addr_srptr;
+		} open_by_addr;
+
+
+		struct {
+			void *listmp_handle;
+		} close;
+
+		struct {
+			void *listmp_handle;
+			bool is_empty;
+		} is_empty;
+
+		struct {
+			void *listmp_handle;
+			u32 *elem_srptr;
+		} get_head;
+
+		struct {
+			void *listmp_handle;
+			u32 *elem_srptr;
+		} get_tail;
+
+		struct {
+			void *listmp_handle;
+			u32 *elem_srptr;
+		} put_head;
+
+		struct {
+			void *listmp_handle;
+			u32 *elem_srptr;
+		} put_tail;
+
+		struct {
+			void *listmp_handle;
+			u32 *new_elem_srptr;
+			u32 *cur_elem_srptr;
+		} insert;
+
+		struct {
+			void *listmp_handle;
+			u32 *elem_srptr;
+		} remove;
+
+		struct {
+			void *listmp_handle;
+			u32 *elem_srptr;
+			u32 *next_elem_srptr;
+		} next;
+
+		struct {
+			void *listmp_handle;
+			u32 *elem_srptr;
+			u32 *prev_elem_srptr;
+		} prev;
+
+		struct {
+			struct listmp_params *params;
+			u32 bytes;
+			void *knl_gate;
+			u32 *shared_addr_srptr;
+			u32 name_len;
+			void *listmp_handle;
+		} shared_mem_req;
+	} args;
+
+	int api_status;
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL functions for listmp module
+ *  ----------------------------------------------------------------------------
+ */
+/* ioctl interface function for listmp */
+int listmp_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args);
+
+#endif /* _LISTMP_IOCTL_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/messageq.h b/arch/arm/plat-omap/include/syslink/messageq.h
new file mode 100644
index 000000000000..d0d59970a49b
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/messageq.h
@@ -0,0 +1,440 @@
+/*
+ *  messageq.h
+ *
+ *  The MessageQ module supports the structured sending and receiving of
+ *  variable length messages. This module can be used for homogeneous or
+ *  heterogeneous multi-processor messaging.
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _MESSAGEQ_H_
+#define _MESSAGEQ_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/list.h>
+
+/* Syslink headers */
+#include <listmp.h>
+
+/*!
+ *  @def	MESSAGEQ_MODULEID
+ *  @brief	Unique module ID.
+ */
+#define MESSAGEQ_MODULEID			(0xded2)
+
+
+/* =============================================================================
+ *  All success and failure codes for the module
+ * =============================================================================
+ */
+
+/*!
+ *  @def    MESSAGEQ_S_BUSY
+ *  @brief  The resource is still in use
+ */
+#define MESSAGEQ_S_BUSY				2
+
+/*!
+ *  @def    MESSAGEQ_S_ALREADYSETUP
+ *  @brief  The module has been already setup
+ */
+#define MESSAGEQ_S_ALREADYSETUP			1
+
+/*!
+ *  @def    MESSAGEQ_S_SUCCESS
+ *  @brief  Operation is successful.
+ */
+#define MESSAGEQ_S_SUCCESS			0
+
+/*!
+ *  @def    MESSAGEQ_E_FAIL
+ *  @brief  Operation is not successful.
+ */
+#define MESSAGEQ_E_FAIL				-1
+
+/*!
+ *  @def    MESSAGEQ_E_INVALIDARG
+ *  @brief  There is an invalid argument.
+ */
+#define MESSAGEQ_E_INVALIDARG			-2
+
+/*!
+ *  @def    MESSAGEQ_E_MEMORY
+ *  @brief  Operation resulted in memory failure.
+ */
+#define MESSAGEQ_E_MEMORY			-3
+
+/*!
+ *  @def    MESSAGEQ_E_ALREADYEXISTS
+ *  @brief  The specified entity already exists.
+ */
+#define MESSAGEQ_E_ALREADYEXISTS		-4
+
+/*!
+ *  @def    MESSAGEQ_E_NOTFOUND
+ *  @brief  Unable to find the specified entity.
+ */
+#define MESSAGEQ_E_NOTFOUND			-5
+
+/*!
+ *  @def    MESSAGEQ_E_TIMEOUT
+ *  @brief  Operation timed out.
+ */
+#define MESSAGEQ_E_TIMEOUT			-6
+
+/*!
+ *  @def    MESSAGEQ_E_INVALIDSTATE
+ *  @brief  Module is not initialized.
+ */
+#define MESSAGEQ_E_INVALIDSTATE			-7
+
+/*!
+ *  @def    MESSAGEQ_E_OSFAILURE
+ *  @brief  A failure occurred in an OS-specific call
+ */
+#define MESSAGEQ_E_OSFAILURE			-8
+
+/*!
+ *  @def    MESSAGEQ_E_RESOURCE
+ *  @brief  Specified resource is not available
+ */
+#define MESSAGEQ_E_RESOURCE			-9
+
+/*!
+ *  @def    MESSAGEQ_E_RESTART
+ *  @brief  Operation was interrupted. Please restart the operation
+ */
+#define MESSAGEQ_E_RESTART			-10
+
+/*!
+ *  @def    MESSAGEQ_E_INVALIDMSG
+ *  @brief  Operation is successful.
+ */
+#define MESSAGEQ_E_INVALIDMSG			-11
+
+/*!
+ *  @def    MESSAGEQ_E_NOTOWNER
+ *  @brief  Not the owner
+ */
+#define MESSAGEQ_E_NOTOWNER			-12
+
+/*!
+ *  @def    MESSAGEQ_E_REMOTEACTIVE
+ *  @brief  Operation is successful.
+ */
+#define MESSAGEQ_E_REMOTEACTIVE			-13
+
+/*!
+ *  @def    MESSAGEQ_E_INVALIDHEAPID
+ *  @brief  Operation is successful.
+ */
+#define MESSAGEQ_E_INVALIDHEAPID		-14
+
+/*!
+ *  @def    MESSAGEQ_E_INVALIDPROCID
+ *  @brief  Operation is successful.
+ */
+#define MESSAGEQ_E_INVALIDPROCID		-15
+
+/*!
+ *  @def    MESSAGEQ_E_MAXREACHED
+ *  @brief  Operation is successful.
+ */
+#define MESSAGEQ_E_MAXREACHED			-16
+
+/*!
+ *  @def    MESSAGEQ_E_UNREGISTEREDHEAPID
+ *  @brief  Operation is successful.
+ */
+#define MESSAGEQ_E_UNREGISTEREDHEAPID		-17
+
+/*!
+ *  @def    MESSAGEQ_E_CANNOTFREESTATICMSG
+ *  @brief  Operation is successful.
+ */
+#define MESSAGEQ_E_CANNOTFREESTATICMSG		-18
+
+
+/* =============================================================================
+ * Macros and types
+ * =============================================================================
+ */
+/*!
+ *	@brief	Mask to extract version setting
+ */
+#define MESSAGEQ_HEADERVERSION			0x2000u
+
+/*! Mask to extract Trace setting */
+#define MESSAGEQ_TRACEMASK			(uint) 0x1000
+
+/*! Shift for Trace setting */
+#define MESSAGEQ_TRACESHIFT			(uint) 12
+
+/*!
+ *	@brief	Mask to extract priority setting
+ */
+#define MESSAGEQ_PRIORITYMASK			0x3u
+
+/*!
+ *  Used as the timeout value to specify wait forever
+ */
+#define MESSAGEQ_FOREVER			(~((u32) 0))
+
+/*!
+ *  Invalid message id
+ */
+#define MESSAGEQ_INVALIDMSGID			0xFFFF
+
+/*!
+ * Invalid message queue
+ */
+#define MESSAGEQ_INVALIDMESSAGEQ		0xFFFF
+
+/*!
+ * Indicates that if maximum number of message queues are already created,
+ * should allow growth to create additional Message Queue.
+ */
+#define MESSAGEQ_ALLOWGROWTH			(~((u32) 0))
+
+/*!
+ * Number of types of priority queues for each transport
+ */
+#define MESSAGEQ_NUM_PRIORITY_QUEUES		2
+
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+/*!
+ * Message priority
+ */
+enum messageq_priority {
+	MESSAGEQ_NORMALPRI = 0,
+	/*!< Normal priority message */
+	MESSAGEQ_HIGHPRI = 1,
+	/*!< High priority message */
+	MESSAGEQ_RESERVEDPRI = 2,
+	/*!< Reserved value for message priority */
+	MESSAGEQ_URGENTPRI = 3
+	/*!< Urgent priority message */
+};
+
+/*! Structure which defines the first field in every message */
+struct msgheader {
+	u32 reserved0;
+	/*!< Reserved field */
+	u32 reserved1;
+	/*!< Reserved field */
+	u32 msg_size;
+	/*!< Size of the message (including header) */
+	u16 flags;
+	/*!< Flags */
+	u16 msg_id;
+	/*!< Maximum length for Message queue names */
+	u16 dst_id;
+	/*!< Maximum length for Message queue names */
+	u16 dst_proc;
+	/*!< Maximum length for Message queue names */
+	u16 reply_id;
+	/*!< Maximum length for Message queue names */
+	u16 reply_proc;
+	/*!< Maximum length for Message queue names */
+	u16 src_proc;
+	/*!< Maximum length for Message queue names */
+	u16 heap_id;
+	/*!< Maximum length for Message queue names */
+	u16 seq_num;
+	/*!< sequence number */
+	u32 reserved;
+	/*!< Reserved field */
+};
+
+/*! Structure which defines the first field in every message */
+#define messageq_msg	struct msgheader *
+/*typedef struct msgheader *messageq_msg;*/
+
+
+/*!
+ *  @brief	Structure defining config parameters for the MessageQ Buf module.
+ */
+struct messageq_config {
+	bool trace_flag;
+	/*!< Trace Flag
+	*  This flag allows the configuration of the default module trace
+	*  settings.
+	*/
+
+	u16 num_heaps;
+	/*!< Number of heapIds in the system
+	*  This allows MessageQ to pre-allocate the heaps table.
+	*  The heaps table is used when registering heaps.
+	*  The default is 1 since generally all systems need at least one heap.
+	*  There is no default heap, so unless the system is only using
+	*  staticMsgInit, the application must register a heap.
+	*/
+
+	u32 max_runtime_entries;
+	/*!
+	*  Maximum number of MessageQs that can be dynamically created
+	*/
+
+	u32 max_name_len;
+	/*!< Maximum length for Message queue names */
+};
+
+struct messageq_params {
+	void *synchronizer;
+	/*!< Synchronizer instance used to signal IO completion
+	*
+	* The synchronizer is used in the #MessageQ_put and #MessageQ_get calls.
+	* The synchronizer signal is called as part of the #MessageQ_put call.
+	* The synchronizer waits in the #MessageQ_get if there are no messages
+	* present.
+	*/
+};
+
+/* =============================================================================
+ *  APIs
+ * =============================================================================
+ */
+/* Functions to get the configuration for messageq setup */
+void messageq_get_config(struct messageq_config *cfg);
+
+/* Function to setup the MessageQ module. */
+int messageq_setup(const struct messageq_config *cfg);
+
+/* Function to destroy the MessageQ module. */
+int messageq_destroy(void);
+
+/* Returns the amount of shared memory used by one transport instance.
+ *
+ *  The MessageQ module itself does not use any shared memory but the
+ *  underlying transport may use some shared memory.
+ */
+uint messageq_shared_mem_req(void *shared_addr);
+
+/* Calls the SetupProxy function to setup the MessageQ transports. */
+int messageq_attach(u16 remote_proc_id, void *shared_addr);
+
+/* Calls the SetupProxy function to detach the MessageQ transports. */
+int messageq_detach(u16 remote_proc_id);
+
+/* Initialize this config-params structure with supplier-specified
+ * defaults before instance creation.
+ */
+void messageq_params_init(struct messageq_params *params);
+
+/* Create a message queue */
+void *messageq_create(char *name, const struct messageq_params *params);
+
+/* Deletes a instance of MessageQ module. */
+int messageq_delete(void **messageq_handleptr);
+
+/* Open a message queue */
+int messageq_open(char *name, u32 *queue_id);
+
+/* Close an opened message queue handle */
+int messageq_close(u32 *queue_id);
+
+/* Allocates a message from the heap */
+messageq_msg messageq_alloc(u16 heapId, u32 size);
+
+/* Frees a message back to the heap */
+int messageq_free(messageq_msg msg);
+
+/* Initializes a message not obtained from MessageQ_alloc */
+void messageq_static_msg_init(messageq_msg msg, u32 size);
+
+/* Place a message onto a message queue */
+int messageq_put(u32 queueId, messageq_msg msg);
+
+/* Gets a message for a message queue and blocks if the queue is empty */
+int messageq_get(void *messageq_handle, messageq_msg *msg, u32 timeout);
+
+/* Register a heap with MessageQ */
+int messageq_register_heap(void *heap_handle, u16 heap_id);
+
+/* Unregister a heap with MessageQ */
+int messageq_unregister_heap(u16 heapId);
+
+/* Returns the number of messages in a message queue */
+int messageq_count(void *messageq_handle);
+
+/* Get the proc Id of the message. */
+u16 messageq_get_proc_id(void *messageq_handle);
+
+/* Get the queue Id of the message. */
+u32 messageq_get_queue_id(void *messageq_handle);
+
+/* Set the destination queue of the message. */
+void messageq_set_reply_queue(void *messageq_handle, messageq_msg msg);
+
+/* Set the tracing of a message */
+void messageq_set_msg_trace(messageq_msg msg, bool trace_flag);
+
+/*
+ *  Functions to set Message properties
+ */
+/*!
+ *  @brief   Returns the MessageQ_Queue handle of the destination
+ *           message queue for the specified message.
+ */
+u32 messageq_get_dst_queue(messageq_msg msg);
+
+/*!
+ *  @brief   Returns the message ID of the specified message.
+ */
+u16 messageq_get_msg_id(messageq_msg msg);
+
+/*!
+ *  @brief   Returns the size of the specified message.
+ */
+u32 messageq_get_msg_size(messageq_msg msg);
+
+/*!
+ *  @brief	Gets the message priority of a message
+ */
+u32 messageq_get_msg_pri(messageq_msg msg);
+
+/*!
+ *  @brief   Returns the MessageQ_Queue handle of the destination
+ *           message queue for the specified message.
+ */
+u32 messageq_get_reply_queue(messageq_msg msg);
+
+/*!
+ *  @brief   Sets the message ID in the specified message.
+ */
+void messageq_set_msg_id(messageq_msg msg, u16 msg_id);
+/*!
+ *  @brief   Sets the message priority in the specified message.
+ */
+void messageq_set_msg_pri(messageq_msg msg, u32 priority);
+
+/* =============================================================================
+ *  APIs called internally by MessageQ transports
+ * =============================================================================
+ */
+/* Register a transport with MessageQ */
+int messageq_register_transport(void *imessageq_transport_handle,
+					u16 proc_id, u32 priority);
+
+/* Unregister a transport with MessageQ */
+void messageq_unregister_transport(u16 proc_id, u32 priority);
+
+
+#endif /* _MESSAGEQ_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/messageq_ioctl.h b/arch/arm/plat-omap/include/syslink/messageq_ioctl.h
new file mode 100644
index 000000000000..34da7e1f3a5b
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/messageq_ioctl.h
@@ -0,0 +1,255 @@
+/*
+ *  messageq_ioctl.h
+ *
+ *  Definitions of messageq driver types and structures.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _MESSAGEQ_IOCTL_H_
+#define _MESSAGEQ_IOCTL_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Syslink headers */
+#include <ipc_ioctl.h>
+#include <messageq.h>
+#include <heap.h>
+#include <sharedregion.h>
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+#define MESSAGEQ_IOC_MAGIC		IPC_IOC_MAGIC
+enum messageq_drv_cmd {
+	MESSAGEQ_GETCONFIG = MESSAGEQ_BASE_CMD,
+	MESSAGEQ_SETUP,
+	MESSAGEQ_DESTROY,
+	MESSAGEQ_PARAMS_INIT,
+	MESSAGEQ_CREATE,
+	MESSAGEQ_DELETE,
+	MESSAGEQ_OPEN,
+	MESSAGEQ_CLOSE,
+	MESSAGEQ_COUNT,
+	MESSAGEQ_ALLOC,
+	MESSAGEQ_FREE,
+	MESSAGEQ_PUT,
+	MESSAGEQ_REGISTERHEAP,
+	MESSAGEQ_UNREGISTERHEAP,
+	MESSAGEQ_ATTACH,
+	MESSAGEQ_DETACH,
+	MESSAGEQ_GET,
+	MESSAGEQ_SHAREDMEMREQ
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL command IDs for messageq
+ *  ----------------------------------------------------------------------------
+ */
+/* Base command ID for messageq */
+#define MESSAGEQ_BASE_CMD			0x0
+
+/* Command for messageq_get_config */
+#define CMD_MESSAGEQ_GETCONFIG \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_GETCONFIG, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_setup */
+#define CMD_MESSAGEQ_SETUP \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_SETUP, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_destroy */
+#define CMD_MESSAGEQ_DESTROY \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_DESTROY, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_params_init */
+#define CMD_MESSAGEQ_PARAMS_INIT \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_PARAMS_INIT, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_create */
+#define CMD_MESSAGEQ_CREATE \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_CREATE, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_delete */
+#define CMD_MESSAGEQ_DELETE \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_DELETE, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_open */
+#define CMD_MESSAGEQ_OPEN \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_OPEN, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_close */
+#define CMD_MESSAGEQ_CLOSE \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_CLOSE, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_count */
+#define CMD_MESSAGEQ_COUNT \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_COUNT, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_alloc */
+#define CMD_MESSAGEQ_ALLOC \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_ALLOC, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_free */
+#define CMD_MESSAGEQ_FREE \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_FREE, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_put */
+#define CMD_MESSAGEQ_PUT \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_PUT, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_register_heap */
+#define CMD_MESSAGEQ_REGISTERHEAP \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_REGISTERHEAP, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_unregister_heap */
+#define CMD_MESSAGEQ_UNREGISTERHEAP \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_UNREGISTERHEAP, \
+			struct messageq_cmd_args)
+
+
+/* Command for messageq_attach */
+#define CMD_MESSAGEQ_ATTACH \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_ATTACH, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_detach */
+#define CMD_MESSAGEQ_DETACH \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_DETACH, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_get */
+#define CMD_MESSAGEQ_GET \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_GET, \
+			struct messageq_cmd_args)
+
+/* Command for messageq_sharedmem_req */
+#define CMD_MESSAGEQ_SHAREDMEMREQ \
+			_IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_SHAREDMEMREQ, \
+			struct messageq_cmd_args)
+
+/* Command arguments for messageq */
+struct messageq_cmd_args {
+	union {
+		struct {
+			void *messageq_handle;
+			struct messageq_params *params;
+		} params_init;
+
+		struct {
+			struct messageq_config *config;
+		} get_config;
+
+		struct {
+			struct messageq_config *config;
+		} setup;
+
+		struct {
+			void *messageq_handle;
+			char *name;
+			struct messageq_params *params;
+			u32 name_len;
+			u32 queue_id;
+		} create;
+
+		struct {
+			void *messageq_handle;
+		} delete_messageq;
+
+		struct {
+			char *name;
+			u32 queue_id;
+			u32 name_len;
+		} open;
+
+		struct {
+			u32 queue_id;
+		} close;
+
+		struct {
+			void *messageq_handle;
+			u32 timeout;
+			u32 *msg_srptr;
+		} get;
+
+		struct {
+			void *messageq_handle;
+			int count;
+		} count;
+
+		struct {
+			u16 heap_id;
+			u32 size;
+			u32 *msg_srptr;
+		} alloc;
+
+		struct {
+			u32 *msg_srptr;
+		} free;
+
+		struct {
+			u32 queue_id;
+			u32 *msg_srptr;
+		} put;
+
+		struct {
+			void *heap_handle;
+			u16 heap_id;
+		} register_heap;
+
+		struct {
+			u16 heap_id;
+		} unregister_heap;
+
+		struct {
+			u32 *shared_addr_srptr;
+			uint mem_req;
+		} shared_mem_req;
+
+		struct {
+			u16 remote_proc_id;
+			u32 *shared_addr_srptr;
+		} attach;
+
+		struct {
+			u16 remote_proc_id;
+		} detach;
+	} args;
+
+	int api_status;
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL functions for messageq module
+ *  ----------------------------------------------------------------------------
+ */
+/*
+ *  ioctl interface function for messageq
+ */
+int messageq_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args);
+
+#endif /* _MESSAGEQ_IOCTL_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/multiproc.h b/arch/arm/plat-omap/include/syslink/multiproc.h
new file mode 100644
index 000000000000..4d14e8c193c6
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/multiproc.h
@@ -0,0 +1,89 @@
+/*
+* multiproc.h
+*
+* Many multi-processor modules have the concept of processor id. multiproc
+* centeralizes the processor id management.
+*
+* Copyright (C) 2008-2009 Texas Instruments, Inc.
+*
+* This package is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE.
+*/
+
+#ifndef _MULTIPROC_H_
+#define _MULTIPROC_H_
+
+#include <linux/types.h>
+
+
+#define VOLATILE volatile
+
+/*
+ *  Unique module ID
+ */
+#define MULTIPROC_MODULEID		(u16)0xB522
+
+/* Macro to define invalid processor id */
+#define MULTIPROC_INVALIDID		((u16)0xFFFF)
+
+/*
+ *  Maximum number of processors in the system
+ *  OMAP4 has 4 processors in single core.
+ */
+#define MULTIPROC_MAXPROCESSORS 4
+
+/*
+ *  Max name length for a processor name
+ */
+#define MULTIPROC_MAXNAMELENGTH 32
+
+/*
+ *  Configuration structure for multiproc module
+ */
+struct multiproc_config {
+	s32 num_processors; /* Number of procs for particular system */
+	char name_list[MULTIPROC_MAXPROCESSORS][MULTIPROC_MAXNAMELENGTH];
+	/* Name List for processors in the system */
+	u16 id; /* Local Proc ID. This needs to be set before calling any
+			other APIs */
+};
+
+/* =============================================================================
+ *  APIs
+ * =============================================================================
+ */
+
+/* Function to get the default configuration for the multiproc module. */
+void multiproc_get_config(struct multiproc_config *cfg);
+
+/* Function to setup the multiproc Module */
+s32 multiproc_setup(struct multiproc_config *cfg);
+
+/* Function to destroy the multiproc module */
+s32 multiproc_destroy(void);
+
+/* Function to set local processor Id */
+int multiproc_set_local_id(u16 proc_id);
+
+/* Function to get processor id from processor name. */
+u16  multiproc_get_id(const char *proc_name);
+
+/* Function to get name from processor id. */
+char *multiproc_get_name(u16 proc_id);
+
+/* Function to get number of processors in the system. */
+u16 multiproc_get_num_processors(void);
+
+/* Return Id of current processor */
+u16 multiproc_self(void);
+
+/* Determines the offset for any two processors. */
+u32 multiproc_get_slot(u16 remote_proc_id);
+
+#endif	/* _MULTIPROC_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h b/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h
new file mode 100644
index 000000000000..0c9780136b02
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h
@@ -0,0 +1,94 @@
+/*
+*  multiproc_ioctl.h
+*
+*  This provides the ioctl interface for multiproc module
+*
+*  Copyright (C) 2008-2009 Texas Instruments, Inc.
+*
+*  This package is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License version 2 as
+*  published by the Free Software Foundation.
+*
+*  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+*  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+*  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+*  PURPOSE.
+*/
+
+#ifndef _MULTIPROC_IOCTL_H_
+#define _MULTIPROC_IOCTL_H_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#include <ipc_ioctl.h>
+#include <multiproc.h>
+
+enum CMD_MULTIPROC {
+	MULTIPROC_SETUP = MULTIPROC_BASE_CMD,
+	MULTIPROC_DESTROY,
+	MULTIPROC_GETCONFIG,
+	MULTIPROC_SETLOCALID
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL command IDs for MultiProc
+ *  ----------------------------------------------------------------------------
+ */
+
+/*
+ *  Command for multiproc_setup
+ */
+#define CMD_MULTIPROC_SETUP	_IOWR(IPC_IOC_MAGIC, MULTIPROC_SETUP,          \
+				struct multiproc_cmd_args)
+
+/*
+ *  Command for multiproc_destroy
+ */
+#define CMD_MULTIPROC_DESTROY	_IOWR(IPC_IOC_MAGIC, MULTIPROC_DESTROY,        \
+				struct multiproc_cmd_args)
+
+/*
+ *  Command for multiproc_get_config
+ */
+#define CMD_MULTIPROC_GETCONFIG _IOWR(IPC_IOC_MAGIC, MULTIPROC_GETCONFIG,      \
+				struct multiproc_cmd_args)
+
+/*
+ *  Command for multiproc_set_local_id
+ */
+#define CMD_MULTIPROC_SETLOCALID _IOWR(IPC_IOC_MAGIC, MULTIPROC_SETLOCALID,    \
+				struct multiproc_cmd_args)
+
+/*
+ *  Command arguments for multiproc
+ */
+union multiproc_arg {
+	struct {
+		struct multiproc_config *config;
+	} get_config;
+
+	struct {
+		struct multiproc_config *config;
+	} setup;
+
+	struct {
+		u16 id;
+	} set_local_id;
+};
+
+/*
+ *  Command arguments for multiproc
+ */
+struct multiproc_cmd_args {
+	union multiproc_arg args;
+	s32 api_status;
+};
+
+/*
+ *  This ioctl interface for multiproc module
+ */
+int multiproc_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args);
+
+#endif	/* _MULTIPROC_IOCTL_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/nameserver.h b/arch/arm/plat-omap/include/syslink/nameserver.h
new file mode 100644
index 000000000000..3aeee242bc39
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/nameserver.h
@@ -0,0 +1,157 @@
+/*
+ *  nameserver.h
+ *
+ *  The nameserver module manages local name/value pairs that
+ *  enables an application and other modules to store and retrieve
+ *  values based on a name.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _NAMESERVER_H_
+#define _NAMESERVER_H_
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+/*
+ *  NAMESERVER_MODULEID
+ *  Unique module ID
+ */
+#define NAMESERVER_MODULEID      (0xF414)
+
+struct nameserver_config {
+	u32 reserved;
+};
+
+/*
+ *  Instance config-params object.
+ */
+struct nameserver_params {
+	u32 max_runtime_entries;
+	void *table_heap; /* Table is placed into a section on dyn creates */
+	bool check_existing; /* Prevents duplicate entry add in to the table */
+	u32 max_value_len; /* Length, in MAUs, of the value field */
+	u16 max_name_len; /* Length, in MAUs, of name field */
+};
+
+
+/*
+ *  Function to get the default configuration for the nameserver module
+ */
+void nameserver_get_config(struct nameserver_config *cfg);
+
+/*
+ *  Function to setup the nameserver module
+ */
+int nameserver_setup(void);
+
+/*
+ *  Function to destroy the nameserver module
+ */
+int nameserver_destroy(void);
+
+/*
+ *  Function to construct a name server.
+ */
+void nameserver_construct(void *object, const char *name,
+				const struct nameserver_params *params);
+
+/*
+ *  Function to destruct a name server
+ */
+void nameserver_destruct(void *object);
+
+/*
+ *  Function to register a remote driver
+ */
+int nameserver_register_remote_driver(void *handle, u16 proc_id);
+
+/*
+ *  Function to unregister a remote driver
+ */
+int nameserver_unregister_remote_driver(u16 proc_id);
+
+/*
+ *  Determines if a remote driver is registered for the specified id.
+ */
+bool nameserver_is_registered(u16 proc_id);
+
+/*
+ *  Function to initialize the parameter structure
+ */
+void nameserver_params_init(struct nameserver_params *params);
+
+/*
+ *  Function to create a name server
+ */
+void *nameserver_create(const char *name,
+			const struct nameserver_params *params);
+
+/*
+ *  Function to delete a name server
+ */
+int nameserver_delete(void **handle);
+
+/*
+ *  Function to handle for  a name
+ */
+void *nameserver_get_handle(const char *name);
+
+/*
+ *  Function to add a variable length value into the local table
+ */
+void *nameserver_add(void *handle, const char *name, void *buf, u32 len);
+
+/*
+ *  Function to add a 32 bit value into the local table
+ */
+void *nameserver_add_uint32(void *handle, const char *name, u32 value);
+
+/*
+ *  Function to retrieve the value portion of a name/value pair
+ */
+int nameserver_get(void *handle, const char *name, void *buf, u32 *len,
+			u16 procId[]);
+
+/*
+ *  Function to retrieve a 32-bit value of a name/value pair
+ */
+int nameserver_get_uint32(void *handle, const char *name, void *buf,
+				u16 procId[]);
+
+/*
+ *  Function to get the value portion of a name/value pair from local table
+ */
+int nameserver_get_local(void *handle, const char *name, void *buf, u32 *len);
+
+/*
+ *  Function to retrieve a 32-bit value from the local name/value table
+ */
+int nameserver_get_local_uint32(void *handle, const char *name, void *buf);
+
+/*
+ *  Function to match the name
+ */
+int nameserver_match(void *handle, const char *name, u32 *value);
+
+/*
+ *  Function to removes a value/pair
+ */
+int nameserver_remove(void *handle, const char *name);
+
+/*
+ *  Function to remove an entry from the table
+ */
+int nameserver_remove_entry(void *handle, void *entry);
+
+#endif /* _NAMESERVER_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h b/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h
new file mode 100644
index 000000000000..4909aa3fa3cb
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h
@@ -0,0 +1,261 @@
+/*
+*  nameserver_ioctl.h
+*
+*  This provides the ioctl interface for nameserver module
+*
+*  Copyright (C) 2008-2009 Texas Instruments, Inc.
+*
+*  This package is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License version 2 as
+*  published by the Free Software Foundation.
+*
+*  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+*  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+*  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+*  PURPOSE.
+*/
+
+#ifndef _NAMESERVER_IOCTL_H_
+#define _NAMESERVER_IOCTL_H_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#include <ipc_ioctl.h>
+#include <nameserver.h>
+
+enum CMD_NAMESERVER {
+	NAMESERVER_SETUP = NAMESERVER_BASE_CMD,
+	NAMESERVER_DESTROY,
+	NAMESERVER_PARAMS_INIT,
+	NAMESERVER_CREATE,
+	NAMESERVER_DELETE,
+	NAMESERVER_ADD,
+	NAMESERVER_ADDUINT32,
+	NAMESERVER_GET,
+	NAMESERVER_GETLOCAL,
+	NAMESERVER_MATCH,
+	NAMESERVER_REMOVE,
+	NAMESERVER_REMOVEENTRY,
+	NAMESERVER_GETHANDLE,
+	NAMESERVER_ISREGISTERED,
+	NAMESERVER_GETCONFIG
+};
+
+/*
+ *  IOCTL command IDs for nameserver
+ *
+ */
+/*
+ *  Command for nameserver_setup
+ */
+#define CMD_NAMESERVER_SETUP		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_SETUP, 		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_destroy
+ */
+#define CMD_NAMESERVER_DESTROY		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_DESTROY,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_params_init
+ */
+#define CMD_NAMESERVER_PARAMS_INIT	_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_PARAMS_INIT,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_create
+ */
+#define CMD_NAMESERVER_CREATE		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_CREATE,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_delete
+ */
+#define CMD_NAMESERVER_DELETE		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_DELETE,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_add
+ */
+#define CMD_NAMESERVER_ADD		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_ADD,			\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_addu32
+ */
+#define CMD_NAMESERVER_ADDUINT32	_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_ADDUINT32,		\
+					struct nameserver_cmd_args)
+/*
+ *  Command for nameserver_get
+ */
+#define CMD_NAMESERVER_GET		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_GET,			\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_get_local
+ */
+#define CMD_NAMESERVER_GETLOCAL		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_GETLOCAL,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_match
+ */
+#define CMD_NAMESERVER_MATCH		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_MATCH,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_remove
+ */
+#define CMD_NAMESERVER_REMOVE		_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_REMOVE,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_remove_entry
+ */
+#define CMD_NAMESERVER_REMOVEENTRY 	_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_REMOVEENTRY,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for nameserver_get_handle
+ */
+#define CMD_NAMESERVER_GETHANDLE	_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_GETHANDLE,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for NameServer_isRegistered
+ */
+#define CMD_NAMESERVER_ISREGISTERED	_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_ISREGISTERED,	\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command for NameServer_getConfig
+ */
+#define CMD_NAMESERVER_GETCONFIG	_IOWR(IPC_IOC_MAGIC,		\
+					NAMESERVER_GETCONFIG,		\
+					struct nameserver_cmd_args)
+
+/*
+ *  Command arguments for nameserver
+ */
+union nameserver_arg {
+	struct {
+		struct nameserver_config *config;
+	} get_config;
+
+	struct {
+		struct nameserver_config *config;
+	} setup;
+
+	struct {
+		struct nameserver_params *params;
+	} params_init;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+		struct nameserver_params *params;
+	} create;
+
+	struct {
+		void *handle;
+	} delete_instance;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+		void *buf;
+		s32 len;
+		void *entry;
+		void *node;
+	} add;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+		u32 value;
+		void *entry;
+	} addu32;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+		void *value;
+		u32 len;
+		u16 *proc_id;
+		u32 proc_len;
+	} get;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+		void *value;
+		u32 len;
+	} get_local;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+		u32 value;
+		u32 count;
+	} match;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+	} remove;
+
+	struct {
+		void *handle;
+		void *entry;
+	} remove_entry;
+
+	struct {
+		void *handle;
+		char *name;
+		u32 name_len;
+	} get_handle;
+
+	struct {
+		u16 proc_id;
+		bool check;
+	} is_registered;
+};
+
+/*
+ *  Command arguments for nameserver
+ */
+struct nameserver_cmd_args {
+	union nameserver_arg args;
+	s32 api_status;
+};
+
+/*
+ *  This ioctl interface for nameserver module
+ */
+int nameserver_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args);
+
+#endif	/* _NAMESERVER_IOCTL_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/nameserver_remote.h b/arch/arm/plat-omap/include/syslink/nameserver_remote.h
new file mode 100644
index 000000000000..bc0921b08e06
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/nameserver_remote.h
@@ -0,0 +1,39 @@
+/*
+ *  nameserver_remote.h
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _NAMESERVER_REMOTE_H_
+#define _NAMESERVER_REMOTE_H_
+
+#include <linux/types.h>
+
+/*
+ *  Structure defining object for the nameserver remote driver
+ */
+struct nameserver_remote_object {
+	int (*get)(const struct nameserver_remote_object *obj,
+		const char *instance_name, const char *name,
+		void *value, u32 *value_len, void *reserved);
+		/* Function to get data from remote nameserver */
+	void *obj; /* Implementation specific object */
+};
+
+/*
+ *  Function get data from remote name server
+ */
+int nameserver_remote_get(const struct nameserver_remote_object *handle,
+			const char *instance_name, const char *name,
+			void *value, u32 *value_len, void *reserved);
+
+#endif /* _NAMESERVER_REMOTE_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h b/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h
new file mode 100644
index 000000000000..cb9b6218930d
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h
@@ -0,0 +1,90 @@
+/*
+ *  nameserver_remotenotify.h
+ *
+ *  The nameserver_remotenotify module provides functionality to get name
+ *  value pair from a remote nameserver.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _NAMESERVER_REMOTENOTIFY_H_
+#define _NAMESERVER_REMOTENOTIFY_H_
+
+#include <linux/types.h>
+
+/*
+ *  NAMESERVERREMOTENOTIFY_MODULEID
+ *  Unique module ID
+ */
+#define NAMESERVERREMOTENOTIFY_MODULEID      (0x08FD)
+
+/*
+ *  Module configuration structure
+ */
+struct nameserver_remotenotify_config {
+	u32 notify_event_id;
+	/* Notify event number */
+};
+
+/*
+  * Module configuration structure
+ */
+struct nameserver_remotenotify_params {
+	void *shared_addr; /* Address of the shared memory */
+	void *gatemp; /* Handle to the gatemp used for protecting the
+			nameserver_remotenotify instance. Using the default
+			value of NULL will result in the default gatemp being
+			used for context protection */
+};
+
+/* Function to get the default configuration for the nameserver_remotenotify
+ * module */
+void nameserver_remotenotify_get_config(
+				struct nameserver_remotenotify_config *cfg);
+
+/* Function to setup the nameserver_remotenotify module */
+int nameserver_remotenotify_setup(struct nameserver_remotenotify_config *cfg);
+
+/* Function to destroy the nameserver_remotenotify module */
+int nameserver_remotenotify_destroy(void);
+
+/* Function to get the current configuration values */
+void nameserver_remotenotify_params_init(
+				struct nameserver_remotenotify_params *params);
+
+/* Function to create the nameserver_remotenotify object */
+void *nameserver_remotenotify_create(u16 remote_proc_id,
+			const struct nameserver_remotenotify_params *params);
+
+/* Function to delete the nameserver_remotenotify object */
+int nameserver_remotenotify_delete(void **handle);
+
+/* Function to get a name/value from remote nameserver */
+int nameserver_remotenotify_get(void *handle,
+				const char *instance_name, const char *name,
+				void *value, u32 *value_len, void *reserved);
+
+/* Get the shared memory requirements for the nameserver_remotenotify */
+uint nameserver_remotenotify_shared_mem_req(
+			const struct nameserver_remotenotify_params *params);
+
+/* Create all the NameServerRemoteNotify drivers. */
+int nameserver_remotenotify_start(void *shared_addr);
+
+/* Attaches to remote processor */
+int nameserver_remotenotify_attach(u16 remote_proc_id, void *shared_addr);
+
+/* Detaches from remote processor */
+int nameserver_remotenotify_detach(u16 remote_proc_id);
+
+
+#endif /* _NAMESERVER_REMOTENOTIFY_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/notify.h b/arch/arm/plat-omap/include/syslink/notify.h
new file mode 100644
index 000000000000..0f9a399e5ceb
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notify.h
@@ -0,0 +1,146 @@
+/*
+ * notify.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#if !defined(_NOTIFY_H_)
+#define _NOTIFY_H_
+
+/* The resource is still in use */
+#define NOTIFY_S_BUSY			2
+
+/* Module already set up */
+#define NOTIFY_S_ALREADYSETUP		1
+
+/* Operation is successful. */
+#define NOTIFY_S_SUCCESS		0
+
+/* Generic failure */
+#define NOTIFY_E_FAIL			-1
+
+/* Argument passed to function is invalid.. */
+#define NOTIFY_E_INVALIDARG		-2
+
+/* Operation resulted in memory failure. */
+#define NOTIFY_E_MEMORY			-3
+
+/* The specified entity already exists. */
+#define NOTIFY_E_ALREADYEXISTS		-4
+
+/* Unable to find the specified entity. */
+#define NOTIFY_E_NOTFOUND		-5
+
+/* Operation timed out. */
+#define NOTIFY_E_TIMEOUT		-6
+
+/* Module is not initialized. */
+#define NOTIFY_E_INVALIDSTATE		-7
+
+/* A failure occurred in an OS-specific call */
+#define NOTIFY_E_OSFAILURE		-8
+
+/* The module has been already setup */
+#define NOTIFY_E_ALREADYSETUP		-9
+
+/* Specified resource is not available */
+#define NOTIFY_E_RESOURCE		-10
+
+/* Operation was interrupted. Please restart the operation */
+#define NOTIFY_E_RESTART		-11
+
+/* The resource is still in use */
+#define NOTIFY_E_BUSY			-12
+
+/* Driver corresponding to the specified eventId is not registered */
+#define NOTIFY_E_DRIVERNOTREGISTERED	-13
+
+/* Event not registered */
+#define NOTIFY_E_EVTNOTREGISTERED	-14
+
+/* Event is disabled */
+#define NOTIFY_E_EVTDISABLED		-15
+
+/* Remote notification is not initialized */
+#define NOTIFY_E_NOTINITIALIZED		-16
+
+/* Trying to illegally use a reserved event */
+#define NOTIFY_E_EVTRESERVED		-17
+
+/* Macro to make a correct module magic number with refCount */
+#define NOTIFY_MAKE_MAGICSTAMP(x) ((NOTIFY_MODULEID << 12u) | (x))
+
+#define REG volatile
+
+/* Maximum number of events supported by the Notify module */
+#define NOTIFY_MAXEVENTS		(u16)32
+
+/* Maximum number of IPC interrupt lines per processor. */
+#define NOTIFY_MAX_INTLINES		4u
+
+/* This key must be provided as the upper 16 bits of the eventNo when
+ * registering for an event, if any reserved event numbers are to be
+ * used. */
+#define NOTIFY_SYSTEMKEY		0xC1D2
+
+
+typedef void (*notify_fn_notify_cbck)(u16 proc_id, u16 line_id, u32 event_id,
+					uint *arg, u32 payload);
+
+extern struct notify_module_object notify_state;
+
+
+/* Function to disable Notify module */
+u32 notify_disable(u16 procId, u16 line_id);
+
+/* Function to disable particular event */
+void notify_disable_event(u16 proc_id, u16 line_id, u32 event_id);
+
+/* Function to enable particular event */
+void notify_enable_event(u16 proc_id, u16 line_id, u32 event_id);
+
+/* Function to find out whether notification via interrupt line has been
+ * registered. */
+bool notify_is_registered(u16 proc_id, u16 line_id);
+
+/* Returns the amount of shared memory used by one Notify instance. */
+uint notify_shared_mem_req(u16 proc_id, void *shared_addr);
+
+/* Function to register an event */
+int notify_register_event(u16 proc_id, u16 line_id, u32 event_id,
+			notify_fn_notify_cbck notify_callback_fxn,
+			void *cbck_arg);
+
+/* Function to register an event */
+int notify_register_event_single(u16 proc_id, u16 line_id, u32 event_id,
+			notify_fn_notify_cbck notify_callback_fxn,
+			void *cbck_arg);
+
+/* Function to restore Notify module state */
+void notify_restore(u16 proc_id, u16 line_id, u32 key);
+
+/* Function to send an event to other processor */
+int notify_send_event(u16 proc_id, u16 line_id, u32 event_id, u32 payload,
+			bool wait_clear);
+
+/* Function to unregister an event */
+int notify_unregister_event(u16 proc_id, u16 line_id, u32 event_id,
+			notify_fn_notify_cbck notify_callback_fxn,
+			void *cbck_arg);
+
+/* Function to unregister an event */
+int notify_unregister_event_single(u16 proc_id, u16 line_id, u32 event_id);
+
+
+#endif /* !defined(_NOTIFY_H_) */
diff --git a/arch/arm/plat-omap/include/syslink/notify_dispatcher.h b/arch/arm/plat-omap/include/syslink/notify_dispatcher.h
new file mode 100644
index 000000000000..efd87315815e
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notify_dispatcher.h
@@ -0,0 +1,158 @@
+/*
+ * notify_dispatcher.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef __TMBX_H__
+#define __TMBX_H__
+
+
+#include <syslink/notifydefs.h>
+#include <linux/interrupt.h>
+
+#include <syslink/notifyerr.h>
+
+#define MAX_MBOX_MODULES 2
+#define MAX_MBOX_ISRS 32
+#define KErrNone 0
+#define KErrNotSupported 1
+#define KErrNotReady 2
+#define KErrArgument 2
+
+typedef void (*isr_call_back)(void *);
+
+struct mbox_config {
+	unsigned long int mbox_linear_addr;
+	unsigned long int mbox_modules;
+	signed long int interrupt_lines[MAX_MBOX_MODULES];
+	signed long int mailboxes[MAX_MBOX_MODULES];
+};
+
+struct mbox_isrs {
+	signed long int isrNo[MAX_MBOX_MODULES];
+	/* TODO: Remove this - seems to be unused.*/
+	isr_call_back isrs[MAX_MBOX_MODULES][MAX_MBOX_ISRS];
+	void *isr_params[MAX_MBOX_MODULES][MAX_MBOX_ISRS];
+};
+
+extern const unsigned long *linear_address;
+
+irqreturn_t notify_mailbx0_user0_isr(int temp, void *anArg, struct pt_regs *p);
+
+/*
+ *func    ntfy_disp_bind_interrupt
+ *
+ * desc    Bind an ISR to the HW interrupt line coming into the processor
+ */
+int ntfy_disp_bind_interrupt(int interrupt_no,
+			isr_call_back hw_isr,
+			void *isr_arg);
+
+
+/*
+ * desc    Print the mailbox registers and other useful debug information
+ *
+ */
+void ntfy_disp_debug(void);
+
+
+/*
+ * func    ntfy_disp_deinit
+ * desc    Uninitialize the Mailbox Manager module
+ */
+int ntfy_disp_deinit(void);
+
+
+/*
+ * desc    Return the pointer to the Mailbox Manager's configuration object
+ */
+struct mbox_config *ntfy_disp_get_config(void);
+
+
+/*
+ * desc    Initialize the Mailbox Manager module
+ */
+int ntfy_disp_init(void);
+
+
+/*
+ * desc    Disable a particular IRQ bit on a Mailbox IRQ Enable Register
+ */
+int ntfy_disp_interrupt_disable(unsigned long int mbox_module_no,
+				int a_irq_bit);
+
+
+/*
+ * desc    Enable a particular IRQ bit on a Mailbox IRQ Enable Register
+ */
+int ntfy_disp_interrupt_enable(unsigned long int mbox_module_no,
+				int a_irq_bit);
+
+
+/*
+ * desc    Read a message on a Mailbox FIFO queue
+ */
+int ntfy_disp_read(unsigned long int mbox_module_no,
+				int a_mbox_no,
+				int *messages,
+				int *num_messages,
+				short int read_all);
+
+
+/*
+ * func    ntfy_disp_register
+ * desc    Register a ISR callback associated with a particular IRQ bit on a
+ * Mailbox IRQ Enable Register
+ */
+int ntfy_disp_register(unsigned long int mbox_module_no,
+			int a_irq_bit,
+			isr_call_back isr_cbck_fn,
+			void *isrCallbackArgs);
+
+
+/*
+ * func    ntfy_disp_send
+ * desc    Send a message on a Mailbox FIFO queue
+ */
+int ntfy_disp_send(unsigned long int mbox_module_no,
+			int a_mbox_no,
+			int message);
+
+
+/*
+ * func    ntfy_disp_unbind_interrupt
+ * desc    Remove the ISR to the HW interrupt line coming into the processor
+ */
+int ntfy_disp_unbind_interrupt(int interrupt_no);
+
+
+/*
+ * func    ntfy_disp_unregister
+ *  desc    Unregister a ISR callback associated with a particular IRQ bit on a
+ * Mailbox IRQ Enable Register
+ */
+int ntfy_disp_unregister(unsigned long int mbox_module_no,
+			int a_irq_bit);
+
+/*
+ * func    notify_mailbx0_user0_isr
+ * desc    mail ISR
+ *
+ */
+
+irqreturn_t notify_mailbx0_user0_isr(int temp, void *anArg, struct pt_regs *p);
+
+
+#endif
diff --git a/arch/arm/plat-omap/include/syslink/notify_driver.h b/arch/arm/plat-omap/include/syslink/notify_driver.h
new file mode 100644
index 000000000000..95c586b77626
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notify_driver.h
@@ -0,0 +1,45 @@
+/*
+ * notify_driver.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#if !defined _NOTIFY_DRIVER_H_
+#define _NOTIFY_DRIVER_H_
+
+
+/* Module includes */
+#include <syslink/notify_driverdefs.h>
+#include <syslink/_notify.h>
+
+
+/* Function to register notify driver */
+int notify_register_driver(u16 remote_proc_id,
+			u16 line_id,
+			struct notify_driver_fxn_table *fxn_table,
+			struct notify_driver_object **driver_handle);
+
+/* Function to unregister notify driver */
+int notify_unregister_driver(struct notify_driver_object *drv_handle);
+
+/* Function to set the driver handle */
+int notify_set_driver_handle(u16 remote_proc_id, u16 line_id,
+				struct notify_object *handle);
+
+/* Function to find the driver in the list of drivers */
+struct notify_driver_object *notify_get_driver_handle(u16 remote_proc_id,
+							u16 line_id);
+
+
+#endif  /* !defined (_NOTIFY_DRIVER_H_) */
diff --git a/arch/arm/plat-omap/include/syslink/notify_driverdefs.h b/arch/arm/plat-omap/include/syslink/notify_driverdefs.h
new file mode 100644
index 000000000000..56f6b282caf7
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notify_driverdefs.h
@@ -0,0 +1,137 @@
+/*
+ * notify_driverdefs.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#if !defined(_NOTIFY_DRIVERDEFS_H_)
+#define _NOTIFY_DRIVERDEFS_H_
+
+
+/* Module headers */
+#include <syslink/multiproc.h>
+#include <syslink/notify.h>
+#include <syslink/_notify.h>
+
+
+/* Enumerations to indicate types of Driver initialization status */
+enum notify_driver_init_status {
+	NOTIFY_DRIVERINITSTATUS_NOTDONE = 0,
+	/* Driver initialization is not done. */
+	NOTIFY_DRIVERINITSTATUS_DONE = 1,
+	/* Driver initialization is complete. */
+	NOTIFY_DRIVERINITSTATUS_INPROGRESS = 2,
+	/* Driver initialization is in progress. */
+	NOTIFY_DRIVERINITSTATUS_ENDVALUE = 3
+	/* End delimiter indicating start of invalid values for this enum */
+};
+
+struct notify_driver_object;
+
+/* This structure defines the function table interface for the Notify
+ * driver.
+ * This function table interface must be implemented by each Notify
+ * driver and registered with the Notify module. */
+struct notify_driver_fxn_table {
+	int (*register_event)(struct notify_driver_object *handle,
+								u32 event_id);
+	/* interface function register_event */
+	int (*unregister_event)(struct notify_driver_object *handle,
+								u32 event_id);
+	/* interface function unregister_event */
+	int (*send_event)(struct notify_driver_object *handle, u32 event_id,
+						u32 payload, bool wait_clear);
+	/* interface function send_event */
+	u32 (*disable)(struct notify_driver_object *handle);
+	/* interface function disable */
+	void (*enable)(struct notify_driver_object *handle);
+	/* interface function enable */
+	void (*disable_event)(struct notify_driver_object *handle,
+								u32 event_id);
+	/* interface function disable_event */
+	void (*enable_event)(struct notify_driver_object *handle, u32 event_id);
+	/* interface function enable_event */
+};
+
+/* This structure defines the Notify driver object and handle used
+ * internally to contain all information required for the Notify driver
+ * This object contains all information for the Notify module to be
+ * able to identify and interact with the Notify driver. */
+struct notify_driver_object {
+	enum notify_driver_init_status is_init;
+	struct notify_driver_fxn_table fxn_table;
+	struct notify_object *notify_handle;
+};
+
+#if 0
+/*
+ *This structure defines information for all processors supported by
+ *the Notify driver.
+ *An instance of this object is provided for each processor handled by
+ *the Notify driver, when registering itself with the Notify module.
+ *
+ */
+struct notify_driver_proc_info {
+	u32 max_events;
+	u32 reserved_events;
+	bool event_priority;
+	u32 payload_size;
+	u16 proc_id;
+};
+
+/*
+ * This structure defines the structure for specifying Notify driver
+ * attributes to the Notify module.
+ * This structure provides information about the Notify driver to the
+ * Notify module. The information is used by the Notify module mainly
+ * for parameter validation. It may also be used by the Notify module
+ * to take appropriate action if required, based on the characteristics
+ * of the Notify driver.
+ */
+struct notify_driver_attrs {
+	u32 numProc;
+	struct notify_driver_proc_info
+				proc_info[MULTIPROC_MAXPROCESSORS];
+};
+
+union notify_drv_procevents{
+	struct {
+		struct notify_shmdrv_attrs  attrs;
+		struct notify_shmdrv_ctrl *ctrl_ptr;
+	} shm_events;
+
+	struct {
+		/*Attributes */
+		unsigned long int  num_events;
+		unsigned long int  send_event_pollcount;
+		/*Control Paramters */
+		unsigned long int send_init_status ;
+		struct notify_shmdrv_eventreg_mask  reg_mask ;
+	} non_shm_events;
+};
+
+struct notify_drv_eventlist {
+	unsigned long int event_handler_count;
+	struct list_head listeners;
+};
+
+struct notify_drv_proc_module {
+	unsigned long int proc_id;
+	struct notify_drv_eventlist *event_list;
+	struct notify_shmdrv_eventreg *reg_chart;
+	union notify_drv_procevents events_obj;
+};
+#endif
+
+#endif /* !defined(_NOTIFY_DRIVERDEFS_H_) */
diff --git a/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h b/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h
new file mode 100644
index 000000000000..aa805ffbb3cb
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h
@@ -0,0 +1,141 @@
+/*
+ * notify_ducatidriver.h
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef NOTIFY_DUCATIDRIVER_H_
+#define NOTIFY_DUCATIDRIVER_H_
+
+
+
+/* Notify*/
+#include <syslink/notify.h>
+#include <syslink/notify_driverdefs.h>
+
+/* Module ID for NotifyDriverShm. */
+#define NOTIFY_DUCATIDRIVER_MODULEID	((u16) 0xb9d4)
+
+#define VOLATILE volatile
+
+extern u32 get_ducati_virt_mem();
+extern void unmap_ducati_virt_mem(u32 shm_virt_addr);
+
+
+/* module configuration structure */
+struct notify_ducatidrv_config {
+	u32 reserved;
+};
+
+/* This structure defines the configuration structure for
+ * initialization of the Notify driver. */
+struct notify_ducatidrv_params {
+	void *shared_addr;
+	/* Address in shared memory where this instance will be placed */
+	bool cache_enabled;
+	/* Whether cache operations will be performed */
+	u32 cache_line_size;
+	/* The cache line size of the shared memory */
+	u32 remote_proc_id;
+	/* Processor Id of remote processor required for communication */
+	u32 line_id;
+	/* Line ID for the interrupt */
+	u32 local_int_id;
+	/* Local interrupt ID for interrupt line for incoming interrupts */
+	u32 remote_int_id;
+	/* Remote interrupt ID for interrupt line for outgoing interrupts */
+};
+
+/* Defines the structure of event entry within the event chart.
+ * Each entry contains occured event-specific information.
+ * Used to flag a remote event and determine if a local event has been
+ * flagged. This struct is placed in shared memory. */
+struct notify_ducatidrv_event_entry {
+	VOLATILE u32 flag;
+	/* Flag indicating whether event is set */
+	VOLATILE u32 payload;
+	/* Payload associated with event */
+	VOLATILE u32 reserved;
+	/* Reserved field */
+	/* Padding for cache line alignment */
+};
+
+/* Defines the NotifyDriverShm control structure, which contains all
+ * information for one processor. This structure is shared between the
+ * two processors. */
+struct notify_ducatidrv_proc_ctrl {
+	VOLATILE u32 recv_init_status;
+	/* Initialization status for receiving events */
+	VOLATILE u32 send_init_status;
+	/* Initialization status for sending events */
+	VOLATILE u32 event_reg_mask;
+	/* Event Registered mask */
+	VOLATILE u32 event_enable_mask;
+	/* Event Enabled mask */
+};
+
+
+/* Function to get the default configuration for the notify_ducati driver
+ * module. */
+void notify_ducatidrv_get_config(struct notify_ducatidrv_config *cfg);
+
+/* Function to setup the notify ducati driver with the given configuration*/
+int notify_ducatidrv_setup(struct notify_ducatidrv_config *cfg);
+
+/* Function to destroy the notify ducati driver */
+int notify_ducatidrv_destroy(void);
+
+/*Function to initialize the given parameters  */
+void notify_ducatidrv_params_init(struct notify_ducatidrv_params *params);
+
+/* Function to create the ducati driver handle and performs initialization. */
+struct notify_ducatidrv_object *notify_ducatidrv_create(
+				const struct notify_ducatidrv_params *params);
+
+/* Function to delete the ducati driver handle and performs de initialization.*/
+int notify_ducatidrv_delete(struct notify_ducatidrv_object **handle);
+
+/* Get the shared memory requirements for the notify ducati driver. */
+uint notify_ducatidrv_shared_mem_req(
+				const struct notify_ducatidrv_params *params);
+
+
+/* Register a callback for an event with the Notify driver. */
+int notify_ducatidrv_register_event(struct notify_driver_object *handle,
+					u32 event_id);
+
+/* Unregister a callback for an event with the Notify driver. */
+int notify_ducatidrv_unregister_event(struct notify_driver_object *handle,
+					u32 event_id);
+
+/* Send a notification event to the registered users for this
+ notification on the specified processor. */
+int notify_ducatidrv_send_event(struct notify_driver_object *handle,
+				u32 event_id, u32 payload, bool wait_clear);
+
+/* Disable all events for this Notify driver. */
+int notify_ducatidrv_disable(struct notify_driver_object *handle);
+
+/* Restore the Notify driver to the state before the last disable was called. */
+void notify_ducatidrv_enable(struct notify_driver_object *handle);
+
+/* Disable a specific event for this Notify driver. */
+void notify_ducatidrv_disable_event(struct notify_driver_object *handle,
+					u32 event_id);
+
+/* Enable a specific event for this Notify driver. */
+void notify_ducatidrv_enable_event(struct notify_driver_object *handle,
+					u32 event_id);
+
+
+#endif  /* !defined  NOTIFY_SHMDRIVER_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/notify_ioctl.h b/arch/arm/plat-omap/include/syslink/notify_ioctl.h
new file mode 100644
index 000000000000..9d1dcadd4ba3
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notify_ioctl.h
@@ -0,0 +1,278 @@
+/*
+ * notify_driverdefs.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#if !defined(_NOTIFY_IOCTL_H_)
+#define _NOTIFY_IOCTL_H_
+
+/* Linux headers */
+#include <linux/ioctl.h>
+
+/* Utilities headers */
+#include <syslink/host_os.h>
+
+/* Module headers */
+#include <ipc_ioctl.h>
+#include <syslink/notify.h>
+#include <syslink/notify_ducatidriver.h>
+#include <syslink/notifydefs.h>
+
+
+enum CMD_NOTIFY {
+	NOTIFY_GETCONFIG = NOTIFY_BASE_CMD,
+	NOTIFY_SETUP,
+	NOTIFY_DESTROY,
+	NOTIFY_REGISTEREVENT,
+	NOTIFY_UNREGISTEREVENT,
+	NOTIFY_SENDEVENT,
+	NOTIFY_DISABLE,
+	NOTIFY_RESTORE,
+	NOTIFY_DISABLEEVENT,
+	NOTIFY_ENABLEEVENT,
+	NOTIFY_ATTACH,
+	NOTIFY_DETACH,
+	NOTIFY_THREADATTACH,
+	NOTIFY_THREADDETACH,
+	NOTIFY_ISREGISTERED,
+	NOTIFY_SHAREDMEMREQ,
+	NOTIFY_REGISTEREVENTSINGLE,
+	NOTIFY_UNREGISTEREVENTSINGLE
+};
+
+/* Command for notify_get_config */
+#define CMD_NOTIFY_GETCONFIG		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_GETCONFIG,		\
+					struct notify_cmd_args_get_config)
+
+/* Command for notify_setup */
+#define CMD_NOTIFY_SETUP		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_SETUP,			\
+					struct notify_cmd_args_setup)
+
+/* Command for notify_destroy */
+#define CMD_NOTIFY_DESTROY		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_DESTROY,			\
+					struct notify_cmd_args_destroy)
+
+/* Command for notify_register_event */
+#define CMD_NOTIFY_REGISTEREVENT	_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_REGISTEREVENT,		\
+					struct notify_cmd_args_register_event)
+
+/* Command for notify_unregister_event */
+#define CMD_NOTIFY_UNREGISTEREVENT	_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_UNREGISTEREVENT,		\
+					struct notify_cmd_args_unregister_event)
+
+/* Command for notify_send_event */
+#define CMD_NOTIFY_SENDEVENT		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_SENDEVENT,		\
+					struct notify_cmd_args_send_event)
+/* Command for notify_disable */
+#define CMD_NOTIFY_DISABLE		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_DISABLE,		\
+					struct notify_cmd_args_disable)
+
+/* Command for notify_restore */
+#define CMD_NOTIFY_RESTORE		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_RESTORE,		\
+					struct notify_cmd_args_restore)
+
+/* Command for notify_disable_event */
+#define CMD_NOTIFY_DISABLEEVENT		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_DISABLEEVENT,		\
+					struct notify_cmd_args_disable_event)
+
+/* Command for notify_enable_event */
+#define CMD_NOTIFY_ENABLEEVENT		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_ENABLEEVENT,		\
+					struct notify_cmd_args_enable_event)
+
+/* Command for notify_attach */
+#define CMD_NOTIFY_ATTACH		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_ATTACH,			\
+					struct notify_cmd_args_attach)
+
+/* Command for notify_detach */
+#define CMD_NOTIFY_DETACH		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_DETACH,			\
+					struct notify_cmd_args_detach)
+
+/* Command for notify_thread_attach */
+#define CMD_NOTIFY_THREADATTACH		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_THREADATTACH,		\
+					struct notify_cmd_args)
+
+/* Command for notify_thread_detach */
+#define CMD_NOTIFY_THREADDETACH		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_THREADDETACH,		\
+					struct notify_cmd_args)
+
+/* Command for notify_is_registered */
+#define CMD_NOTIFY_ISREGISTERED		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_ISREGISTERED,		\
+					struct notify_cmd_args_is_registered)
+
+/* Command for notify_shared_mem_req */
+#define CMD_NOTIFY_SHAREDMEMREQ		_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_SHAREDMEMREQ,		\
+					struct notify_cmd_args_shared_mem_req)
+/* Command for notify_register_event_single */
+#define CMD_NOTIFY_REGISTEREVENTSINGLE	_IOWR(IPC_IOC_MAGIC,		\
+					NOTIFY_REGISTEREVENTSINGLE,	\
+					struct notify_cmd_args_register_event)
+
+/* Command for notify_unregister_event_single */
+#define CMD_NOTIFY_UNREGISTEREVENTSINGLE	_IOWR(IPC_IOC_MAGIC,	\
+					NOTIFY_UNREGISTEREVENTSINGLE,	\
+					struct notify_cmd_args_unregister_event)
+
+
+/*Structure of Event Packet read from notify kernel-side..*/
+struct notify_drv_event_packet {
+	struct list_head element;
+	u32 pid;
+	u32 proc_id;
+	u32 event_id;
+	u16 line_id;
+	u32 data;
+	notify_fn_notify_cbck func;
+	void *param;
+	bool is_exit;
+};
+
+/* Common arguments for all ioctl commands */
+struct notify_cmd_args {
+	int api_status;
+};
+
+/* Command arguments for notify_get_config */
+struct notify_cmd_args_get_config {
+	struct notify_cmd_args common_args;
+	struct notify_config *cfg;
+};
+
+/* Command arguments for notify_setup */
+struct notify_cmd_args_setup {
+	struct notify_cmd_args common_args;
+	struct notify_config *cfg;
+};
+
+/* Command arguments for notify_destroy */
+struct notify_cmd_args_destroy {
+	struct notify_cmd_args common_args;
+};
+
+/* Command arguments for notify_attach */
+struct notify_cmd_args_attach {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	void *shared_addr;
+};
+
+/* Command arguments for notify_detach */
+struct notify_cmd_args_detach {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+};
+
+/* Command arguments for notify_cmd_args_shared_mem_req */
+struct notify_cmd_args_shared_mem_req {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	void *shared_addr;
+	uint shared_mem_size;
+};
+
+/* Command arguments for notify_cmd_args_is_registered */
+struct notify_cmd_args_is_registered {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	u16 line_id;
+	bool is_registered;
+};
+
+/* Command arguments for notify_register_event */
+struct notify_cmd_args_register_event {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	u16 line_id;
+	u32 event_id;
+	notify_fn_notify_cbck fn_notify_cbck;
+	uint *cbck_arg;
+	u32 pid;
+};
+
+/* Command arguments for notify_unregister_event */
+struct notify_cmd_args_unregister_event {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	u16 line_id;
+	u32 event_id;
+	notify_fn_notify_cbck fn_notify_cbck;
+	uint *cbck_arg;
+	u32 pid;
+};
+
+/* Command arguments for notify_send_event */
+struct notify_cmd_args_send_event {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	u16 line_id;
+	u32 event_id;
+	u32 payload;
+	bool wait_clear;
+};
+
+/* Command arguments for notify_disable */
+struct notify_cmd_args_disable {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	u16 line_id;
+	u32 flags;
+};
+
+/* Command arguments for notify_restore */
+struct notify_cmd_args_restore {
+	struct notify_cmd_args common_args;
+	u32 key;
+	u16 proc_id;
+	u16 line_id;
+};
+
+/* Command arguments for notify_disable_event */
+struct notify_cmd_args_disable_event {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	u16 line_id;
+	u32 event_id;
+};
+
+/* Command arguments for notify_enable_event */
+struct notify_cmd_args_enable_event {
+	struct notify_cmd_args common_args;
+	u16 proc_id;
+	u16 line_id;
+	u32 event_id;
+};
+
+/* Command arguments for notify_exit */
+struct notify_cmd_args_exit {
+	struct notify_cmd_args common_args;
+};
+
+
+#endif /* !defined(_NOTIFY_IOCTL_H_) */
diff --git a/arch/arm/plat-omap/include/syslink/notify_setup_proxy.h b/arch/arm/plat-omap/include/syslink/notify_setup_proxy.h
new file mode 100644
index 000000000000..383b3150a7d7
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notify_setup_proxy.h
@@ -0,0 +1,53 @@
+/*
+ * notify_setup_proxy.h
+ *
+ * Proxy to connect notify setup to device specific implementation
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#if !defined(_NOTIFYSETUPPROXY_H_0x5f84)
+#define _NOTIFYSETUPPROXY_H_0x5f84
+
+#if defined(CONFIG_ARCH_OMAP4)
+/* Function that will be called in Notify_attach */
+extern int notify_setup_omap4_attach(u16 proc_id, void *shared_addr);
+#define notify_setup_proxy_attach(proc_id, shared_addr)		\
+			notify_setup_omap4_attach(proc_id, shared_addr)
+
+/* Function that will be called in notify_stop */
+extern int notify_setup_omap4_detach(u16 proc_id);
+#define notify_setup_proxy_detach notify_setup_omap4_detach
+
+/* Shared Memory Required for notify setup */
+extern uint notify_setup_omap4_shared_mem_req(u16 proc_id, void *shared_addr);
+#define notify_setup_proxy_shared_mem_req(proc_id, shared_addr)	\
+			notify_setup_omap4_shared_mem_req(proc_id, shared_addr)
+
+/* Is interrupt line available? */
+extern bool notify_setup_omap4_int_line_available(u16 remote_proc_id);
+#define notify_setup_proxy_int_line_available(remote_proc_id)	\
+	notify_setup_omap4_int_line_available(remote_proc_id)
+#else
+/* Function that will be called in Notify_attach */
+#define notify_setup_proxy_attach(proc_id, shared_addr)
+
+/* Function that will be called in notify_stop */
+#define notify_setup_proxy_detach
+
+/* Shared Memory Required for notify setup */
+#define notify_setup_proxy_shared_mem_req(proc_id, shared_addr)
+
+/* Is interrupt line available? */
+#define notify_setup_proxy_int_line_available(remote_proc_id)
+#endif /* if defined (SYSLINK_PLATFORM_OMAPL1XX) */
+
+#endif  /* !defined(_NOTIFYSETUPPROXY_H_0x5f84) */
diff --git a/arch/arm/plat-omap/include/syslink/notifydefs.h b/arch/arm/plat-omap/include/syslink/notifydefs.h
new file mode 100644
index 000000000000..b0df5d536168
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notifydefs.h
@@ -0,0 +1,92 @@
+/*
+ * notifydefs.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#if !defined(_NOTIFYDEFS_H_)
+#define _NOTIFYDEFS_H_
+
+/* Linux headers */
+#include <linux/list.h>
+
+/* Osal And Utils  headers */
+#include <syslink/atomic_linux.h>
+
+/* Module headers */
+#include <syslink/notify.h>
+#include <syslink/_notify.h>
+#include <syslink/notify_driverdefs.h>
+
+
+/*Macro to make a correct module magic number with ref Count */
+#define NOTIFY_MAKE_MAGICSTAMP(x)	((NOTIFY_MODULEID << 12u) | (x))
+
+/* Maximum number of Notify drivers supported. */
+#define NOTIFY_MAX_DRIVERS		4u
+
+/* Mask to check for system key. */
+#define NOTIFY_SYSTEMKEY_MASK		((u16)0xFFFF0000)
+
+
+/* Defines the Event callback information instance */
+struct notify_event_callback {
+	notify_fn_notify_cbck fn_notify_cbck;
+	/* Callback function pointer */
+	uint *cbck_arg;
+	/* Argument associated with callback function */
+};
+
+/* Defines the Notify state object, which contains all the module
+ * specific information. */
+struct notify_module_object {
+	atomic_t ref_count;
+	/* Reference count */
+	struct notify_config cfg;
+	/* Notify configuration structure */
+	struct notify_config def_cfg;
+	/* Default module configuration */
+	struct mutex *gate_handle;
+	/* Handle of gate to be used for local thread safety */
+	struct notify_driver_object
+		drivers[NOTIFY_MAX_DRIVERS][NOTIFY_MAX_INTLINES];
+	/* Array of configured drivers. */
+	u32 local_enable_mask;
+	/* This is used for local/loopback events. Default to enabled (-1) */
+	bool start_complete;
+	/* TRUE if start() was called */
+	bool is_setup;
+	/* Indicates whether the Notify module is setup. */
+	struct notify_object *local_notify_handle;
+	/* Handle to Notify object for local notifications. */
+};
+
+/* Defines the Notify instance object. */
+struct notify_object {
+	uint nesting;
+	/* Disable/restore nesting */
+	void *driver_handle;
+	/* Handle to device specific driver */
+	u16 remote_proc_id;
+	/* Remote MultiProc id */
+	u16 line_id;
+	/* Interrupt line id */
+	struct notify_event_callback callbacks[NOTIFY_MAXEVENTS];
+	/* List of event callbacks registered */
+	struct list_head event_list[NOTIFY_MAXEVENTS];
+	/* List of event listeners registered */
+};
+
+
+#endif  /* !defined (_NOTIFYDEFS_H_) */
diff --git a/arch/arm/plat-omap/include/syslink/notifyerr.h b/arch/arm/plat-omap/include/syslink/notifyerr.h
new file mode 100644
index 000000000000..9bbaa238fa3a
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/notifyerr.h
@@ -0,0 +1,198 @@
+/*
+ * notifyerr.h
+ *
+ * Notify driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#if !defined NOTIFYERR_H
+#define NOTIFYERR_H
+
+
+/*
+ *  name   NOTIFY_SUCCEEDED
+ *
+ *  desc   Check if the provided status code indicates a success code.
+ *
+ *  arg    status
+ *              Status code to be checked
+ *
+ *  ret    TRUE
+ *              If status code indicates success
+ *          FALSE
+ *              If status code indicates failure
+ *
+ *  enter  None.
+ *
+ *  leave  None.
+ *
+ *  see    NOTIFY_FAILED
+ *
+ */
+#define NOTIFY_SUCCEEDED(status)\
+(((signed long int) (status) >= (NOTIFY_SBASE)) \
+&& ((signed long int) (status) <= (NOTIFY_SLAST)))
+
+
+/*
+ *  @name   NOTIFY_FAILED
+ *
+ *  @desc   Check if the provided status code indicates a failure code.
+ *
+ *  @arg    status
+ *              Status code to be checked
+ *
+ *  @ret    TRUE
+ *              If status code indicates failure
+ *          FALSE
+ *              If status code indicates success
+ *
+ *  @enter  None.
+ *
+ *  @leave  None.
+ *
+ *  @see    NOTIFY_FAILED
+ *
+ */
+#define NOTIFY_FAILED(status)      (!NOTIFY_SUCCEEDED(status))
+
+
+
+/*
+ *  name   NOTIFY_SBASE, NOTIFY_SLAST
+ *
+ *   desc   Defines the base and range for the success codes used by the
+ *          Notify module
+ *
+ */
+#define NOTIFY_SBASE               (signed long int)0x00002000l
+#define NOTIFY_SLAST               (signed long int)0x000020FFl
+
+/*
+ *  name   NOTIFY_EBASE, NOTIFY_ELAST
+ *
+ *  desc   Defines the base and range for the failure codes used by the
+ *          Notify module
+ *
+ */
+#define NOTIFY_EBASE               (signed long int)0x80002000l
+#define NOTIFY_ELAST               (signed long int)0x800020FFl
+
+
+/*
+ *  SUCCESS Codes
+ *
+ */
+
+/* Generic success code for Notify module */
+#define NOTIFY_SOK                (NOTIFY_SBASE + 0x01l)
+
+/* Indicates that the Notify module (or driver) has already been initialized
+ * by another client, and this process has now successfully acquired the right
+ * to use the Notify module.
+ */
+#define NOTIFY_SALREADYINIT       (NOTIFY_SBASE + 0x02l)
+
+/* Indicates that the Notify module (or driver) is now being finalized, since
+  * the calling client is the last one finalizing the module, and all open
+ * handles to it have been closed.
+ */
+#define NOTIFY_SEXIT              (NOTIFY_SBASE + 0x03l)
+
+
+/*
+ *  FAILURE Codes
+ *
+ */
+
+/* Generic failure code for Notify module */
+#define NOTIFY_EFAIL              (NOTIFY_EBASE + 0x01l)
+
+/* This failure code indicates that an operation has timed out. */
+#define NOTIFY_ETIMEOUT           (NOTIFY_EBASE + 0x02l)
+
+/* This failure code indicates a configuration error */
+#define NOTIFY_ECONFIG            (NOTIFY_EBASE + 0x03l)
+
+/* This failure code indicates that the Notify module has already been
+ * initialized from the calling client (process).
+ */
+#define NOTIFY_EALREADYINIT       (NOTIFY_EBASE + 0x04l)
+
+/* This failure code indicates that the specified entity was not found
+ * The interpretation of this error code depends on the function from which it
+ * was returned.
+ */
+#define NOTIFY_ENOTFOUND          (NOTIFY_EBASE + 0x05l)
+
+/* This failure code indicates that the specified feature is not supported
+ * The interpretation of this error code depends on the function from which it
+ * was returned.
+ */
+#define NOTIFY_ENOTSUPPORTED      (NOTIFY_EBASE + 0x06l)
+
+/* This failure code indicates that the specified event number is 
+ * not supported
+ */
+#define NOTIFY_EINVALIDEVENT      (NOTIFY_EBASE + 0x07l)
+
+/* This failure code indicates that the specified pointer is invalid */
+#define NOTIFY_EPOINTER           (NOTIFY_EBASE + 0x08l)
+
+/* This failure code indicates that a provided parameter was outside its valid
+ * range.
+ * The interpretation of this error code depends on the function from which it
+ * was returned.
+ */
+#define NOTIFY_ERANGE             (NOTIFY_EBASE + 0x09l)
+
+/* This failure code indicates that the specified handle is invalid */
+#define NOTIFY_EHANDLE            (NOTIFY_EBASE + 0x0Al)
+
+/* This failure code indicates that an invalid argument was specified */
+#define NOTIFY_EINVALIDARG        (NOTIFY_EBASE + 0x0Bl)
+
+/* This failure code indicates a memory related failure */
+#define NOTIFY_EMEMORY            (NOTIFY_EBASE + 0x0Cl)
+
+/* This failure code indicates that the Notify module has not been initialized*/
+#define NOTIFY_EINIT              (NOTIFY_EBASE + 0x0Dl)
+
+/* This failure code indicates that a resource was not available.
+ * The interpretation of this error code depends on the function from which it
+ * was returned.
+ */
+#define NOTIFY_ERESOURCE          (NOTIFY_EBASE + 0x0El)
+
+/* This failure code indicates that there was an attempt to register for a
+ * reserved event.
+ */
+#define NOTIFY_ERESERVEDEVENT     (NOTIFY_EBASE + 0x0Fl)
+
+/* This failure code indicates that the specified entity already exists.
+ * The interpretation of this error code depends on the function from which it
+ * was returned.
+ */
+#define NOTIFY_EALREADYEXISTS     (NOTIFY_EBASE + 0x10l)
+
+/* This failure code indicates that the Notify driver has not been fully
+ * initialized
+ */
+#define NOTIFY_EDRIVERINIT        (NOTIFY_EBASE + 0x11l)
+
+/* This failure code indicates that the other side is not ready to receive
+ * notifications.
+ */
+#define NOTIFY_ENOTREADY          (NOTIFY_EBASE + 0x12l)
+
+#endif /* !defined (NOTIFYERR_H) */
diff --git a/arch/arm/plat-omap/include/syslink/platform.h b/arch/arm/plat-omap/include/syslink/platform.h
new file mode 100644
index 000000000000..9dbae5cf1521
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/platform.h
@@ -0,0 +1,44 @@
+/*
+ *  platform.h
+ *
+ *  Defines the platform functions to be used by SysMgr module.
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _PLATFORM_H_
+#define _PLATFORM_H_
+
+#define PLATFORM_S_SUCCESS       0
+#define PLATFORM_E_FAIL         -1
+#define PLATFORM_E_INVALIDARG   -2
+
+/* =============================================================================
+ * APIs
+ * =============================================================================
+ */
+/* Function to setup the platform */
+s32 platform_setup(void);
+
+/* Function to destroy the platform */
+s32 platform_destroy(void);
+
+/* Function called when slave is loaded with executable */
+int platform_load_callback(u16 proc_id, void *arg);
+
+/* Function called when slave is in started state*/
+int platform_start_callback(u16 proc_id, void *arg);
+
+/* Function called when slave is stopped state */
+int platform_stop_callback(u16 proc_id, void *arg);
+
+#endif /* ifndef _PLATFORM_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/platform_mem.h b/arch/arm/plat-omap/include/syslink/platform_mem.h
new file mode 100644
index 000000000000..874a1153fc21
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/platform_mem.h
@@ -0,0 +1,137 @@
+/*
+ *  platform_mem.c
+ *
+ * Target memory management interface implementation.
+ *
+ *  This abstracts the Memory management interface in the kernel
+ *  code. Allocation, Freeing-up, copy and address translate are
+ *  supported for the kernel memory management.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _PLATFORM_MEM_H_
+#define _PLATFORM_MEM_H_
+
+#include <linux/types.h>
+
+/*
+ *  MEMORYOS_MODULEID
+ *  Module ID for platform mem module
+ */
+#define PLATFORM_MEM_MODULEID				 (u16) 0x97D2
+
+/*
+ *  Enumerates the types of caching for memory regions
+ */
+enum platform_mem_cache_flags {
+	PLATFORM_MEM_CACHE_FLAGS_DEFAULT  = 0x00000000,
+	/* Default flags - Cached */
+	PLATFORM_MEM_CACHE_FLAGS_CACHED   = 0x00010000,
+	/* Cached memory */
+	PLATFORM_MEM_CACHE_FLAGS_UNCACHED = 0x00020000,
+	/* Uncached memory */
+	PLATFORM_MEM_CACHE_FLAGS_END_VALUE = 0x00030000
+	/* End delimiter indicating start of invalid values for this enum */
+};
+
+/*
+ *  Enumerates the types of memory allocation
+ */
+enum platform_mem_mtype_flags{
+	PLATFORM_MEM_MTYPE_FLAGS_DEFAULT  = 0x00000000,
+	/* Default flags - virtually contiguous */
+	PLATFORM_MEM_MTYPE_FLAGS_PHYSICAL = 0x00000001,
+	/* Physically contiguous */
+	PLATFORM_MEM_MTYPE_FLAGS_DMA	  = 0x00000002,
+	/* Physically contiguous */
+	PLATFORM_MEM_MTYPE_FLAGS_END_VALUE = 0x00000003
+	/* End delimiter indicating start of invalid values for this enum */
+};
+
+/*
+ *  Enumerates the types of translation
+ */
+enum memory_xlt_flags{
+	PLATFORM_MEM_XLT_FLAGS_VIRT2PHYS = 0x00000000,
+	/* Virtual to physical */
+	PLATFORM_MEM_XLT_FLAGS_PHYS2VIRT = 0x00000001,
+	/* Virtual to physical */
+	PLATFORM_MEM_XLT_FLAGS_END_VALUE  = 0x00000002
+	/* End delimiter indicating start of invalid values for this enum */
+};
+
+/*
+ *  Structure containing information required for mapping a
+ *  memory region.
+ */
+struct platform_mem_map_info {
+	u32 src;
+	/* Address to be mapped. */
+	u32 size;
+	/*  Size of memory region to be mapped. */
+	u32 dst;
+	/* Mapped address. */
+	bool	 is_cached;
+	/* Whether the mapping is to a cached area or uncached area. */
+	void *drv_handle;
+	/* Handle to the driver that is implementing the mmap call. Ignored for
+	Kernel-side version. */
+};
+
+/*
+ * Structure containing information required for unmapping a
+ * memory region.
+ */
+struct platform_mem_unmap_info {
+	u32  addr;
+	/* Address to be unmapped.*/
+	u32  size;
+	/* Size of memory region to be unmapped.*/
+	bool	is_cached;
+	/* Whether the mapping is to a cached area or uncached area.  */
+};
+
+/*
+ *  Structure containing information required for mapping a
+ *		   memory region.
+ */
+#define memory_map_info   struct platform_mem_map_info
+
+/*
+ * Structure containing information required for unmapping a
+ * memory region.
+ */
+#define memory_unmap_info struct platform_mem_unmap_info
+
+
+/* =============================================================================
+ *  APIs
+ * =============================================================================
+ */
+/* Initialize the platform mem module. */
+int platform_mem_setup(void);
+
+/* Finalize the platform mem module. */
+int  platform_mem_destroy(void);
+
+/* Maps a memory area into virtual space. */
+int  platform_mem_map(memory_map_info *map_info);
+
+/* Unmaps a memory area into virtual space. */
+int  platform_mem_unmap(memory_unmap_info *unmap_info);
+
+/* Translate API */
+void *platform_mem_translate(void *srcAddr, enum memory_xlt_flags flags);
+
+#endif /* ifndef _PLATFORM_MEM_H_ */
+
diff --git a/arch/arm/plat-omap/include/syslink/procmgr.h b/arch/arm/plat-omap/include/syslink/procmgr.h
new file mode 100644
index 000000000000..4d113c9fa90d
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/procmgr.h
@@ -0,0 +1,280 @@
+/*
+ * procmgr.h
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef SYSLINK_PROC_MGR_H
+#define SYSLINK_PROC_MGR_H
+
+#include <linux/types.h>
+#include <syslink/multiproc.h>
+
+
+
+#define PROCMGR_MODULEID		0xf2ba
+
+/*
+ * Maximum name length for ProcMgr module strings.
+ */
+#define PROCMGR_MAX_STRLEN		32
+
+/*
+ * Maximum number of memory regions supported by ProcMgr module.
+ */
+#define PROCMGR_MAX_MEMORY_REGIONS	32
+
+/*
+ *	IS_VALID_PROCID
+ *   Checks if the Processor ID is valid
+ */
+#define IS_VALID_PROCID(id)		(id < MULTIPROC_MAXPROCESSORS)
+
+
+/*
+ *   Enumerations to indicate Processor states.
+ */
+enum proc_mgr_state {
+	PROC_MGR_STATE_UNKNOWN = 0,
+	/* Unknown Processor state (e.g. at startup or error). */
+	PROC_MGR_STATE_POWERED = 1,
+	/* Indicates the Processor is powered up. */
+	PROC_MGR_STATE_RESET = 2,
+	/* Indicates the Processor is reset. */
+	PROC_MGR_STATE_LOADED = 3,
+	/* Indicates the Processor is loaded. */
+	PROC_MGR_STATE_RUNNNING = 4,
+	/* Indicates the Processor is running. */
+	PROC_MGR_STATE_UNAVAILABLE = 5,
+	/* Indicates the Processor is unavailable to the physical transport. */
+	PROC_MGR_STATE_ENDVALUE = 6
+	/* End delimiter indicating start of invalid values for this enum */
+};
+
+/*
+ *   Enumerations to indicate different types of slave boot modes.
+ */
+enum proc_mgr_boot_mode {
+	PROC_MGR_BOOTMODE_BOOT = 0,
+	/* ProcMgr is responsible for loading the slave and its reset control */
+	PROC_MGR_BOOTMODE_NOLOAD = 1,
+	/* ProcMgr is not responsible for loading the slave. It is responsible
+		 for reset control of the slave. */
+	PROC_MGR_BOOTMODE_NOBOOT = 2,
+	/* ProcMgr is not responsible for loading or reset control of the slave.
+	 The slave either self-boots, or this is done by some entity outside of
+	 the ProcMgr module. */
+	PROC_MGR_BOOTMODE_ENDVALUE = 3
+	/* End delimiter indicating start of invalid values for this enum */
+} ;
+
+/*
+ *   Enumerations to indicate address types used for translation
+ */
+enum proc_mgr_addr_type{
+	PROC_MGR_ADDRTYPE_MASTERKNLVIRT = 0,
+	/* Kernel Virtual address on master processor */
+	PROC_MGR_ADDRTYPE_MASTERUSRVIRT = 1,
+	/* User Virtual address on master processor */
+	PROC_MGR_ADDRTYPE_SLAVEVIRT = 2,
+	/* Virtual address on slave processor */
+	PROC_MGR_ADDRTYPE_ENDVALUE = 3
+	/* End delimiter indicating start of invalid values for this enum */
+};
+
+/*
+ *   Enumerations to indicate types of address mapping
+ */
+enum proc_mgr_map_type {
+	PROC_MGR_MAPTYPE_VIRT = 0,
+	/* Map/unmap to virtual address space (kernel/user) */
+	PROC_MGR_MAPTYPE_SLAVE = 1,
+	/* Map/unmap to slave address space */
+	PROC_MGR_MAPTYPE_ENDVALUE = 2
+	/* End delimiter indicating start of invalid values for this enum */
+};
+
+/*
+ * Module configuration structure.
+ */
+struct proc_mgr_config {
+	void *gate_handle;
+} ;
+
+/*
+ *   Configuration parameters specific to the slave ProcMgr instance.
+ */
+struct proc_mgr_params {
+	void *proc_handle;
+	/* void * to the Processor object associated with this ProcMgr. */
+	void *loader_handle;
+    /*!< Handle to the Loader object associated with this ProcMgr. */
+	void *pwr_handle;
+    /*!< Handle to the PwrMgr object associated with this ProcMgr. */
+};
+
+/*
+ *   Configuration parameters specific to the slave ProcMgr instance.
+ */
+struct proc_mgr_attach_params {
+	enum proc_mgr_boot_mode boot_mode;
+	/* Boot mode for the slave processor. */
+} ;
+
+/*
+ *   Configuration parameters to be provided while starting the slave
+ *  processor.
+ */
+struct proc_mgr_start_params {
+	u32 proc_id;
+};
+
+/*
+ *   Configuration parameters to be provided while stopping the slave
+ *  processor.
+ */
+struct proc_mgr_stop_params {
+	u32 proc_id;
+};
+
+/*
+ *   This structure defines information about memory regions mapped by
+ *  the ProcMgr module.
+ */
+struct  proc_mgr_addr_info {
+/*	bool is_init;  */
+	unsigned short is_init;
+	/* Is this memory region initialized? */
+	u32 addr[PROC_MGR_ADDRTYPE_ENDVALUE];
+	/* Addresses for each type of address space */
+	u32 size;
+	/* Size of the memory region in bytes */
+};
+
+/*
+ *   Characteristics of the slave processor
+ */
+struct proc_mgr_proc_info {
+	enum proc_mgr_boot_mode	boot_mode;
+	/* Boot mode of the processor. */
+	u16 num_mem_entries;
+	/* Number of valid memory entries */
+	struct proc_mgr_addr_info mem_entries[PROCMGR_MAX_MEMORY_REGIONS];
+	/* Configuration of memory regions */
+};
+
+
+/*
+ * Function pointer type that is passed to the proc_mgr_registerNotify function
+*/
+typedef int (*proc_mgr_callback_fxn)(u16 proc_id, void *handle,
+		enum proc_mgr_state from_state, enum proc_mgr_state to_state);
+
+/* Function to get the default configuration for the ProcMgr module. */
+void proc_mgr_get_config(struct proc_mgr_config *cfg);
+
+/* Function to setup the ProcMgr module. */
+int proc_mgr_setup(struct proc_mgr_config *cfg);
+
+/* Function to destroy the ProcMgr module. */
+int proc_mgr_destroy(void);
+
+/* Function to initialize the parameters for the ProcMgr instance. */
+void proc_mgr_params_init(void *handle, struct proc_mgr_params *params);
+
+/* Function to create a ProcMgr object for a specific slave processor. */
+void *proc_mgr_create(u16 proc_id, const struct proc_mgr_params *params);
+
+/* Function to delete a ProcMgr object for a specific slave processor. */
+int proc_mgr_delete(void **handle_ptr);
+
+/* Function to open a handle to an existing ProcMgr object handling the
+ * proc_id.
+ */
+int proc_mgr_open(void **handle, u16 proc_id);
+
+/* Function to close this handle to the ProcMgr instance. */
+int proc_mgr_close(void *handle);
+
+/* Function to initialize the parameters for the ProcMgr attach function. */
+void proc_mgr_get_attach_params(void *handle,
+		struct proc_mgr_attach_params *params);
+
+/* Function to attach the client to the specified slave and also initialize the
+ * slave(if required).
+ */
+int proc_mgr_attach(void *handle, struct proc_mgr_attach_params *params);
+
+/* Function to detach the client from the specified slave and also finalze the
+ * slave(if required).
+ */
+int proc_mgr_detach(void *handle);
+
+/* Function to initialize the parameters for the ProcMgr start function. */
+void proc_mgr_get_start_params(void *handle,
+				struct proc_mgr_start_params *params);
+
+/* Function to starts execution of the loaded code on the slave from the
+ * starting point specified in the slave executable loaded earlier by call to
+ * proc_mgr_load().
+ */
+int proc_mgr_start(void *handle, u32 entry_point,
+				struct proc_mgr_start_params *params);
+
+/* Function to stop execution of the slave Processor. */
+int proc_mgr_stop(void *handle, struct proc_mgr_stop_params *params);
+
+/* Function to get the current state of the slave Processor as maintained on
+ * the master Processor state machine.
+ */
+enum proc_mgr_state proc_mgr_get_state(void *handle);
+
+/* Function to read from the slave Processor's memory space. */
+int proc_mgr_read(void *handle, u32 proc_addr, u32 *num_bytes,
+		  void *buffer);
+
+/* Function to read from the slave Processor's memory space. */
+int proc_mgr_write(void *handle, u32 proc_addr, u32 *num_bytes, void *buffer);
+
+/* Function that provides a hook for performing device dependent operations on
+ * the slave Processor.
+ */
+int proc_mgr_control(void *handle, int cmd, void *arg);
+
+int proc_mgr_translate_addr(void *handle, void **dst_addr,
+		enum proc_mgr_addr_type dst_addr_type, void *src_addr,
+		enum proc_mgr_addr_type src_addr_type);
+
+/* Function that maps the specified slave address to master address space. */
+int proc_mgr_map(void *handle, u32 proc_addr, u32 size,
+	u32 *mappedAddr, u32 *mapped_size, u32 map_attribs);
+
+/* Function that unmaps the specified slave address to master address space. */
+int proc_mgr_unmap(void *handle, u32 mapped_addr);
+
+/* Function that registers for notification when the slave processor
+ * transitions to any of the states specified.
+ */
+int proc_mgr_register_notify(void *handle, proc_mgr_callback_fxn fxn,
+				void *args, enum proc_mgr_state state[]);
+
+/* Function that returns information about the characteristics of the slave
+ * processor.
+ */
+int proc_mgr_get_proc_info(void *handle, struct proc_mgr_proc_info *proc_info);
+
+/* Function that returns virtual to physical translations
+ */
+int proc_mgr_virt_to_phys(void *handle, u32 da, u32 *mapped_entries,
+						u32 num_of_entries);
+
+#endif
diff --git a/arch/arm/plat-omap/include/syslink/sharedregion.h b/arch/arm/plat-omap/include/syslink/sharedregion.h
new file mode 100644
index 000000000000..ca644e7ebcdc
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/sharedregion.h
@@ -0,0 +1,244 @@
+/*
+ *  sharedregion.h
+ *
+ *  The SharedRegion module is designed to be used in a
+ *  multi-processor environment where there are memory regions
+ *  that are shared and accessed across different processors
+ *
+ *  Copyright (C) 2008-2010 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _SHAREDREGION_H_
+#define _SHAREDREGION_H_
+
+#include <linux/types.h>
+#include <heapmemmp.h>
+
+/*
+ *  SHAREDREGION_MODULEID
+ *  Module ID for Shared region manager
+ */
+#define SHAREDREGION_MODULEID		(0x5D8A)
+
+/*
+ *  Name of the reserved nameserver used for application
+ */
+#define SHAREDREGION_NAMESERVER		"SHAREDREGION"
+
+/*
+ *  Name of the reserved nameserver used for application
+ */
+#define SHAREDREGION_INVALIDREGIONID	((u16)(~0))
+
+/*!
+ *  @def        SharedRegion_DEFAULTOWNERID
+ *  @brief      Default owner processor id
+ */
+#define SHAREDREGION_DEFAULTOWNERID	((u16)(~0))
+
+/*
+ *  Name of the reserved nameserver used for application
+ */
+#define SHAREDREGION_INVALIDSRPTR	((u32 *)(~0))
+
+
+struct sharedregion_entry {
+	/* The base address of the region */
+	void *base;
+	/* The length of the region */
+	uint len;
+	/* The MultiProc id of the owner of the region */
+	u16 owner_proc_id;
+	/* Whether the region is valid */
+	bool is_valid;
+	/* Whether to perform cache operations for the region */
+	bool cache_enable;
+	/* The cache line size of the region */
+	uint cache_line_size;
+	/* Whether a heap is created for the region */
+	bool create_heap;
+	/* The name of the region */
+	char *name;
+};
+
+/*
+ * Module configuration structure
+ */
+struct sharedregion_config {
+	uint cache_line_size;
+	/*
+	*  Worst-case cache line size
+	*
+	*  This is the default system cache line size for all modules.
+	*  When a module puts structures in shared memory, this value is
+	*  used to make sure items are aligned on a cache line boundary.
+	*  If no cacheLineSize is specified for a region, it will use this
+	*  value.
+	*/
+
+	u16 num_entries;
+	/*
+	*  The number of shared region table entries.
+	*
+	*  This value is used for calculating the number of bits for the offset.
+	*  Note: This value must be the same across all processors in the
+	*        system. Increasing this parameter will increase the footprint
+	*        and the time for translating a pointer to a SRPtr.
+	*/
+
+	bool translate;
+	/*
+	*  This configuration parameter should be set to 'true'
+	*  if and only if all shared memory regions are the same
+	*  for all processors. If 'true', it results in a fast
+	*  getPtr and getSRPtr.
+	*/
+};
+
+/*
+ *  Information stored on a per region basis
+ */
+struct sharedregion_region {
+	struct sharedregion_entry entry;
+	uint reserved_size;
+	struct heapmemmp_object *heap;
+};
+
+
+/*
+ *  Function to get the configuration
+ */
+int sharedregion_get_config(struct sharedregion_config *config);
+
+/*
+ *  Function to setup the SharedRegion module
+ */
+int sharedregion_setup(const struct sharedregion_config *config);
+
+/*
+ *  Function to destroy the SharedRegion module
+ */
+int sharedregion_destroy(void);
+
+/*
+ *  Creates a heap by owner of region for each SharedRegion.
+ *  Function is called by ipc_start(). Requires that SharedRegion 0
+ *  be valid before calling start().
+ */
+int sharedregion_start(void);
+
+/*
+ *  Function to stop Shared Region 0
+ */
+int sharedregion_stop(void);
+
+/*
+ *  Opens a heap, for non-owner processors, for each SharedRegion.
+ */
+int sharedregion_attach(u16 remote_proc_id);
+
+/*
+ *  Closes a heap, for non-owner processors, for each SharedRegion.
+ */
+int sharedregion_detach(u16 remote_proc_id);
+
+/*
+ *  Reserve shared region memory
+ */
+void *sharedregion_reserve_memory(u16 id, u32 size);
+
+/*
+ *  Reserve shared region memory
+ */
+void sharedregion_unreserve_memory(u16 id, u32 size);
+
+/*
+ *  Sets the entry at the specified region id(doesn't create heap)
+ */
+int _sharedregion_set_entry(u16 region_id, struct sharedregion_entry *entry);
+
+/*
+ *  Function to clear the reserved memory
+ */
+void sharedregion_clear_reserved_memory(void);
+
+/*
+ *  Return the region info
+ */
+void sharedregion_get_region_info(u16 i, struct sharedregion_region *region);
+
+/*
+ *  Clears the entry at the specified region id
+ */
+int sharedregion_clear_entry(u16 region_id);
+
+/*
+ *  Initializes the entry fields
+ */
+void sharedregion_entry_init(struct sharedregion_entry *entry);
+
+/*
+ *  Gets the cache line size for the specified region id
+ */
+uint sharedregion_get_cache_line_size(u16 region_id);
+
+/*
+ *  Gets the entry information for the specified region id
+ */
+int sharedregion_get_entry(u16 region_id, struct sharedregion_entry *entry);
+
+/*
+ *  Gets the heap associated with the specified region id
+ */
+void *sharedregion_get_heap(u16 region_id);
+
+/*
+ *  Gets the region id for the specified address
+ */
+u16 sharedregion_get_id(void *addr);
+
+/*
+ *  Gets the id of a region, given the name
+ */
+u16 sharedregion_get_id_by_name(char *name);
+
+/*
+ *  Gets the number of regions
+ */
+u16 sharedregion_get_num_regions(void);
+
+/*
+ *  Returns the address pointer associated with the shared region pointer
+ */
+void *sharedregion_get_ptr(u32 *srptr);
+
+/*
+ *  Returns the shared region pointer
+ */
+u32 *sharedregion_get_srptr(void *addr, u16 index);
+
+/*
+ *  whether cache enable was specified
+ */
+bool sharedregion_is_cache_enabled(u16 region_id);
+
+/*
+ *  Sets the entry at the specified region id
+ */
+int sharedregion_set_entry(u16 region_id, struct sharedregion_entry *entry);
+
+/*
+ *  Whether address translation is enabled
+ */
+bool sharedregion_translate_enabled(void);
+
+#endif /* _SHAREDREGION_H */
diff --git a/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h b/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h
new file mode 100644
index 000000000000..4d45df002046
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h
@@ -0,0 +1,189 @@
+/*
+ *  sharedregion_ioctl.h
+ *
+ *  The sharedregion module is designed to be used in a
+ *  multi-processor environment where there are memory regions
+ *  that are shared and accessed across different processors
+ *
+ *  Copyright (C) 2008-2010 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _SHAREDREGION_IOCTL_H
+#define _SHAREDREGION_IOCTL_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#include <ipc_ioctl.h>
+#include <sharedregion.h>
+
+enum CMD_SHAREDREGION {
+	SHAREDREGION_GETCONFIG = SHAREDREGION_BASE_CMD,
+	SHAREDREGION_SETUP,
+	SHAREDREGION_DESTROY,
+	SHAREDREGION_START,
+	SHAREDREGION_STOP,
+	SHAREDREGION_ATTACH,
+	SHAREDREGION_DETACH,
+	SHAREDREGION_GETHEAP,
+	SHAREDREGION_CLEARENTRY,
+	SHAREDREGION_SETENTRY,
+	SHAREDREGION_RESERVEMEMORY,
+	SHAREDREGION_CLEARRESERVEDMEMORY,
+	SHAREDREGION_GETREGIONINFO
+};
+
+/*
+ *  IOCTL command IDs for sharedregion
+ *
+ */
+
+/*
+ *  Command for sharedregion_get_config
+ */
+#define CMD_SHAREDREGION_GETCONFIG	_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_GETCONFIG,		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_setup
+ */
+#define CMD_SHAREDREGION_SETUP		_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_SETUP,		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_setup
+ */
+#define CMD_SHAREDREGION_DESTROY	_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_DESTROY, 		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_start
+ */
+#define CMD_SHAREDREGION_START		_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_START,		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_stop
+ */
+#define CMD_SHAREDREGION_STOP		_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_STOP,		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_attach
+ */
+#define CMD_SHAREDREGION_ATTACH		_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_ATTACH,		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_detach
+ */
+#define CMD_SHAREDREGION_DETACH		_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_DETACH,		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_get_heap
+ */
+#define CMD_SHAREDREGION_GETHEAP	_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_GETHEAP,		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_clear_entry
+ */
+#define CMD_SHAREDREGION_CLEARENTRY	_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_CLEARENTRY,	\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_set_entry
+ */
+#define CMD_SHAREDREGION_SETENTRY	_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_SETENTRY,		\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_reserve_memory
+ */
+#define CMD_SHAREDREGION_RESERVEMEMORY	_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_RESERVEMEMORY,	\
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_clear_reserved_memory
+ */
+#define CMD_SHAREDREGION_CLEARRESERVEDMEMORY				\
+					_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_CLEARRESERVEDMEMORY, \
+					struct sharedregion_cmd_args)
+/*
+ *  Command for sharedregion_get_region_info
+ */
+#define CMD_SHAREDREGION_GETREGIONINFO	_IOWR(IPC_IOC_MAGIC,		\
+					SHAREDREGION_GETREGIONINFO,	\
+					struct sharedregion_cmd_args)
+
+/*
+ *  Command arguments for sharedregion
+ */
+union sharedregion_arg {
+	struct {
+		struct sharedregion_config *config;
+	} get_config;
+
+	struct {
+		struct sharedregion_region *regions;
+		struct sharedregion_config *config;
+	} setup;
+
+	struct {
+		struct sharedregion_region *regions;
+	} get_region_info;
+
+	struct {
+		u16 remote_proc_id;
+	} attach;
+
+	struct {
+		u16 remote_proc_id;
+	} detach;
+
+	struct {
+		u16 id;
+		void *heap_handle;
+	} get_heap;
+
+	struct {
+		u16 id;
+		struct sharedregion_entry entry;
+	} set_entry;
+
+	struct {
+		u16 id;
+	} clear_entry;
+
+	struct {
+		u16 id;
+		u32 size;
+	} reserve_memory;
+};
+
+/*
+ *  Command arguments for sharedregion
+ */
+struct sharedregion_cmd_args {
+	union sharedregion_arg args;
+	s32 api_status;
+};
+
+/*
+ *  This ioctl interface for sharedregion module
+ */
+int sharedregion_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args);
+
+#endif /* _SHAREDREGION_IOCTL_H */
diff --git a/arch/arm/plat-omap/include/syslink/sysipc_ioctl.h b/arch/arm/plat-omap/include/syslink/sysipc_ioctl.h
new file mode 100644
index 000000000000..d5896c21c96d
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/sysipc_ioctl.h
@@ -0,0 +1,118 @@
+/*
+ *  sysipc_ioctl.h
+ *
+ *  Definitions of sysmgr driver types and structures..
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _SYSIPC_IOCTL_H_
+#define _SYSIPC_IOCTL_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Syslink headers */
+#include <ipc_ioctl.h>
+#include <ipc.h>
+
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+/*  ----------------------------------------------------------------------------
+ *  IOCTL command IDs for sysmgr
+ *  ----------------------------------------------------------------------------
+ */
+/* IOC Magic Number for sysmgr */
+#define SYSIPC_IOC_MAGIC		IPC_IOC_MAGIC
+
+/* IOCTL command numbers for ipc/sysipc */
+enum sysipc_drv_cmd {
+	IPC_SETUP = IPC_BASE_CMD,
+	IPC_DESTROY,
+	IPC_CONTROL,
+	IPC_READCONFIG,
+	IPC_WRITECONFIG
+ };
+
+/* Command for ipc_setup */
+#define CMD_IPC_SETUP \
+			_IOWR(SYSIPC_IOC_MAGIC, IPC_SETUP, \
+			struct sysipc_cmd_args)
+
+/* Command for ipc_destroy */
+#define CMD_IPC_DESTROY \
+			_IOWR(SYSIPC_IOC_MAGIC, IPC_DESTROY, \
+			struct sysipc_cmd_args)
+
+/* Command for load callback */
+#define CMD_IPC_CONTROL \
+			_IOWR(SYSIPC_IOC_MAGIC, IPC_CONTROL, \
+			struct sysipc_cmd_args)
+
+/* Command for ipc_read_config */
+#define CMD_IPC_READCONFIG \
+			_IOWR(SYSIPC_IOC_MAGIC, IPC_READCONFIG, \
+			struct sysipc_cmd_args)
+
+/* Command for ipc_write_config */
+#define CMD_IPC_WRITECONFIG \
+			_IOWR(SYSIPC_IOC_MAGIC, IPC_WRITECONFIG, \
+			struct sysipc_cmd_args)
+
+
+/*  ----------------------------------------------------------------------------
+ *  Command arguments for sysmgr
+ *  ----------------------------------------------------------------------------
+ */
+/* Command arguments for sysmgr */
+struct sysipc_cmd_args {
+	union {
+		struct {
+			u16 proc_id;
+			s32 cmd_id;
+			void *arg;
+		} control;
+
+		struct {
+			u16 remote_proc_id;
+			u32 tag;
+			void *cfg;
+			u32 size;
+		} read_config;
+
+		struct {
+			u16 remote_proc_id;
+			u32 tag;
+			void *cfg;
+			u32 size;
+		} write_config;
+
+		struct {
+			struct ipc_config *config;
+		} setup;
+	} args;
+
+	s32 api_status;
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL functions for sysmgr module
+ *  ----------------------------------------------------------------------------
+ */
+/* ioctl interface function for sysmgr */
+int sysipc_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args);
+
+#endif /* _SYSIPC_IOCTL_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/sysmemmgr.h b/arch/arm/plat-omap/include/syslink/sysmemmgr.h
new file mode 100644
index 000000000000..34c3b4182288
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/sysmemmgr.h
@@ -0,0 +1,179 @@
+/*
+ *  sysmemmgr.h
+ *
+ *  Manager for the Slave system memory. Slave system level memory is allocated
+ *  through this module.
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+#ifndef _SYSTEMMEMORYMANAGER_H_
+#define _SYSTEMMEMORYMANAGER_H_
+
+
+/*!
+ *  @def    SYSMEMMGR_MODULEID
+ *  @brief  Module identifier for System memory manager.
+ */
+#define SYSMEMMGR_MODULEID		(0xb53d)
+
+/*!
+ *  @def    SYSMEMMGR_STATUSCODEBASE
+ *  @brief  Error code base for system memory manager module.
+ */
+#define SYSMEMMGR_STATUSCODEBASE	(SYSMEMMGR_MODULEID << 12u)
+
+/*!
+ *  @def    SYSMEMMGR_MAKE_ERROR
+ *  @brief  Macro to make error code.
+ */
+#define SYSMEMMGR_MAKE_ERROR(x)		((int)(0x80000000 + \
+						(SYSMEMMGR_STATUSCODEBASE + \
+						(x))))
+
+/*!
+ *  @def    SYSMEMMGR_MAKE_SUCCESS
+ *  @brief  Macro to make success code.
+ */
+#define SYSMEMMGR_MAKE_SUCCESS(x)	(SYSMEMMGR_STATUSCODEBASE + (x))
+
+/*!
+ *  @def    SYSMEMMGR_E_CREATEALLOCATOR
+ *  @brief  Static allocator creation failed.
+ */
+#define SYSMEMMGR_E_CREATEALLOCATOR	SYSMEMMGR_MAKE_ERROR(1)
+
+/*!
+ *  @def    SYSMEMMGR_E_CREATELOCK
+ *  @brief  Mutex lock creation failed.
+ */
+#define SYSMEMMGR_E_CREATELOCK		SYSMEMMGR_MAKE_ERROR(2)
+
+/*!
+ *  @def    SYSMEMMGR_E_INVALIDSTATE
+ *  @brief  Module is not initialized.
+ */
+#define SYSMEMMGR_E_INVALIDSTATE	SYSMEMMGR_MAKE_ERROR(3)
+
+/*!
+ *  @def    SYSMEMMGR_E_INVALIDARG
+ *  @brief  Argument passed to a function is invalid.
+ */
+#define SYSMEMMGR_E_INVALIDARG		SYSMEMMGR_MAKE_ERROR(4)
+
+/*!
+ *  @def    SYSMEMMGR_E_BPAFREE
+ *  @brief  Freeing to buddy allocator failed.
+ */
+#define SYSMEMMGR_E_BPAFREE		SYSMEMMGR_MAKE_ERROR(5)
+
+/*!
+ *  @def    SYSMEMMGR_E_MEMORY
+ *  @brief  Memory allocation failed.
+ */
+#define SYSMEMMGR_E_MEMORY		SYSMEMMGR_MAKE_ERROR(6)
+
+/*!
+ *  @def    SYSMEMMGR_SUCCESS
+ *  @brief  Operation successful.
+ */
+#define SYSMEMMGR_SUCCESS		SYSMEMMGR_MAKE_SUCCESS(0)
+
+/*!
+ *  @def    SYSMEMMGR_S_ALREADYSETUP
+ *  @brief  Module already initialized.
+ */
+#define SYSMEMMGR_S_ALREADYSETUP	SYSMEMMGR_MAKE_SUCCESS(1)
+
+/*!
+ *  @def    SYSMEMMGR_S_DRVALREADYOPENED
+ *  @brief  Internal OS Driver is already opened.
+ */
+#define SYSMEMMGR_S_DRVALREADYOPENED	SYSMEMMGR_MAKE_SUCCESS(2)
+
+/*!
+ *  @brief  Configuration data structure of system memory manager.
+ */
+struct sysmemmgr_config {
+	u32 sizeof_valloc;
+	/* Total size for virtual memory allocation */
+	u32 sizeof_palloc;
+	/* Total size for physical memory allocation */
+	u32 static_phys_base_addr;
+	/* Physical address of static memory region */
+	u32 static_virt_base_addr;
+	/* Virtual  address of static memory region */
+	u32 static_mem_size;
+	/* size of static memory region */
+	u32 page_size;
+	/* Page size */
+	u32 event_no;
+	/* Event number to be used */
+};
+
+/*!
+ *  @brief  Flag used for allocating memory blocks.
+ */
+enum sysmemmgr_allocflag {
+	sysmemmgr_allocflag_uncached = 0u,
+	/* Flag used for allocating uncacheable block */
+	sysmemmgr_allocflag_cached = 1u,
+	/* Flag used for allocating cacheable block */
+	sysmemmgr_allocflag_physical = 2u,
+	/* Flag used for allocating physically contiguous block */
+	sysmemmgr_allocflag_virtual = 3u,
+	/* Flag used for allocating virtually contiguous block */
+	sysmemmgr_allocflag_dma = 4u
+	/* Flag used for allocating DMAable (physically contiguous) block */
+};
+
+/*!
+ *  @brief  Flag used for translating address.
+ */
+enum sysmemmgr_xltflag {
+	sysmemmgr_xltflag_kvirt2phys = 0x0001u,
+	/* Flag used for converting Kernel virtual address to physical
+	 *  address */
+	sysmemmgr_xltflag_kvirt2uvirt = 0x0002u,
+	/* Flag used for converting Kernel virtual address to user virtual
+	 *  address */
+	sysmemmgr_xltflag_uvirt2phys = 0x0003u,
+	/* Flag used for converting user virtual address to physical address */
+	sysmemmgr_xltflag_uvirt2kvirt = 0x0004u,
+	/* Flag used for converting user virtual address to Kernel virtual
+	 *  address */
+	sysmemmgr_xltflag_phys2kvirt = 0x0005u,
+	/* Flag used for converting physical address to user virtual address */
+	sysmemmgr_xltflag_phys2uvirt = 0x0006u
+	/* Flag used for converting physical address to Kernel virtual
+	 *  address */
+};
+
+
+/* Function prototypes */
+void sysmemmgr_get_config(struct sysmemmgr_config *config);
+
+int sysmemmgr_setup(struct sysmemmgr_config *params);
+
+int sysmemmgr_destroy(void);
+
+int sysmemmgr_attach(u16 slave_id);
+
+void *sysmemmgr_alloc(u32 size, enum sysmemmgr_allocflag flag);
+
+int sysmemmgr_free(void *blk, u32 size, enum sysmemmgr_allocflag flag);
+
+void *sysmemmgr_translate(void *srcAddr, enum sysmemmgr_xltflag flag);
+
+
+#endif /* _SYSTEMMEMORYMANAGER_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h b/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h
new file mode 100644
index 000000000000..4b0d99615560
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h
@@ -0,0 +1,130 @@
+/*
+ *  sysmemmgr_ioctl.h
+ *
+ *  Definitions of sysmemmgr driver types and structures..
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _SYSMEMMGR_IOCTL_H_
+#define _SYSMEMMGR_IOCTL_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Syslink headers */
+#include <ipc_ioctl.h>
+#include <sysmgr.h>
+
+
+/* =============================================================================
+ *  Macros and types
+ * =============================================================================
+ */
+/*  ----------------------------------------------------------------------------
+ *  IOCTL command IDs for sysmemmgr
+ *  ----------------------------------------------------------------------------
+ */
+/* IOC Magic Number for sysmemmgr */
+#define SYSMEMMGR_IOC_MAGIC		IPC_IOC_MAGIC
+
+/* IOCTL command numbers for sysmemmgr */
+enum sysmemmgr_drv_cmd {
+	SYSMEMMGR_GETCONFIG = SYSMEMMGR_BASE_CMD,
+	SYSMEMMGR_SETUP,
+	SYSMEMMGR_DESTROY,
+	SYSMEMMGR_ALLOC,
+	SYSMEMMGR_FREE,
+	SYSMEMMGR_TRANSLATE
+};
+
+/* Command for sysmemmgr_getConfig */
+#define CMD_SYSMEMMGR_GETCONFIG \
+			_IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_GETCONFIG, \
+			struct sysmemmgr_cmd_args)
+
+/* Command for sysmemmgr_setup */
+#define CMD_SYSMEMMGR_SETUP \
+			_IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_SETUP, \
+			struct sysmemmgr_cmd_args)
+
+/* Command for sysmemmgr_destroy */
+#define CMD_SYSMEMMGR_DESTROY \
+			_IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_DESTROY, \
+			struct sysmemmgr_cmd_args)
+
+/* Command for sysmemmgr_alloc */
+#define CMD_SYSMEMMGR_ALLOC \
+			_IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_ALLOC, \
+			struct sysmemmgr_cmd_args)
+
+/* Command for sysmemmgr_free */
+#define CMD_SYSMEMMGR_FREE \
+			_IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_FREE, \
+			struct sysmemmgr_cmd_args)
+
+/* Command for sysmemmgr_translate */
+#define CMD_SYSMEMMGR_TRANSLATE \
+			_IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_TRANSLATE, \
+			struct sysmemmgr_cmd_args)
+
+
+/*  ----------------------------------------------------------------------------
+ *  Command arguments for sysmemmgr
+ *  ----------------------------------------------------------------------------
+ */
+/* Command arguments for sysmemmgr */
+struct sysmemmgr_cmd_args {
+	union {
+		struct {
+			struct sysmemmgr_config *config;
+		} get_config;
+
+		struct {
+			struct sysmemmgr_config *config;
+		} setup;
+
+		struct {
+			u32 size;
+			void *buf;
+			void *phys;
+			void *kbuf;
+			enum sysmemmgr_allocflag flags;
+		} alloc;
+
+		struct {
+			u32 size;
+			void *buf;
+			void *phys;
+			void *kbuf;
+			enum sysmemmgr_allocflag flags;
+		} free;
+
+		struct {
+			void *buf;
+			void *ret_ptr;
+			enum sysmemmgr_xltflag flags;
+		} translate;
+	} args;
+
+	s32 api_status;
+};
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL functions for sysmemmgr module
+ *  ----------------------------------------------------------------------------
+ */
+/* ioctl interface function for sysmemmgr */
+int sysmemmgr_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args);
+
+#endif /* SYSMEMMGR_DRVDEFS_H_0xF414 */
diff --git a/arch/arm/plat-omap/include/syslink/sysmgr.h b/arch/arm/plat-omap/include/syslink/sysmgr.h
new file mode 100644
index 000000000000..19fab220b2c4
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/sysmgr.h
@@ -0,0 +1,182 @@
+/*
+ *  sysmgr.h
+ *
+ *  Defines for System manager.
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _SYSMGR_H_
+#define _SYSMGR_H_
+
+
+/* Module headers */
+#include <multiproc.h>
+#include <gatepeterson.h>
+#include <sharedregion.h>
+#include <listmp.h>
+#include <listmp_sharedmemory.h>
+#include <messageq.h>
+#include <messageq_transportshm.h>
+#include <notify.h>
+#include <notify_ducatidriver.h>
+#include <nameserver.h>
+#include <nameserver_remote.h>
+#include <nameserver_remotenotify.h>
+#include <procmgr.h>
+#include <heap.h>
+#include <heapbuf.h>
+#include <sysmemmgr.h>
+
+
+/*!
+ *  @def    SYSMGR_MODULEID
+ *  @brief  Unique module ID.
+ */
+#define SYSMGR_MODULEID			(0xF086)
+
+
+/* =============================================================================
+ * Module Success and Failure codes
+ * =============================================================================
+ */
+/*!
+ *  @def    SYSMGR_STATUSCODEBASE
+ *  @brief  Error code base for System manager.
+ */
+#define SYSMGR_STATUSCODEBASE		(SYSMGR_MODULEID << 12u)
+
+/*!
+ *  @def    SYSMGR_MAKE_FAILURE
+ *  @brief  Macro to make error code.
+ */
+#define SYSMGR_MAKE_FAILURE(x)			((s32)(0x80000000 + \
+						(SYSMGR_STATUSCODEBASE + \
+						(x))))
+
+/*!
+ *  @def    SYSMGR_MAKE_SUCCESS
+ *  @brief  Macro to make success code.
+ */
+#define SYSMGR_MAKE_SUCCESS(x)		(SYSMGR_STATUSCODEBASE + (x))
+
+/*!
+ *  @def    SYSMGR_E_INVALIDARG
+ *  @brief  Argument passed to a function is invalid.
+ */
+#define SYSMGR_E_INVALIDARG			SYSMGR_MAKE_FAILURE(1)
+
+/*!
+ *  @def    SYSMGR_E_MEMORY
+ *  @brief  Memory allocation failed.
+ */
+#define SYSMGR_E_MEMORY			SYSMGR_MAKE_FAILURE(2)
+
+/*!
+ *  @def    SYSMGR_E_FAIL
+ *  @brief  General failure.
+ */
+#define SYSMGR_E_FAIL				SYSMGR_MAKE_FAILURE(3)
+
+/*!
+ *  @def    SYSMGR_E_INVALIDSTATE
+ *  @brief  Module is in invalid state.
+ */
+#define SYSMGR_E_INVALIDSTATE			SYSMGR_MAKE_FAILURE(4)
+
+/*!
+ *  @def    SYSMGR_E_OSFAILURE
+ *  @brief  Failure in OS call.
+ */
+#define SYSMGR_E_OSFAILURE			SYSMGR_MAKE_FAILURE(5)
+
+/*!
+ *  @def    SYSMGR_S_ALREADYSETUP
+ *  @brief  Module is already initialized.
+ */
+#define SYSMGR_S_ALREADYSETUP			SYSMGR_MAKE_SUCCESS(1)
+
+/*!
+ *  @def    SYSMGR_CMD_SCALABILITY
+ *  @brief  Command ID for scalability info.
+ */
+#define SYSMGR_CMD_SCALABILITY			(0x00000000)
+
+/*!
+ *  @def    SYSMGR_CMD_SHAREDREGION_ENTRY_BASE
+ *  @brief  Base of command IDs for entries used by Shared region.
+ */
+#define SYSMGR_CMD_SHAREDREGION_ENTRY_START	(0x00000001)
+#define SYSMGR_CMD_SHAREDREGION_ENTRY_END		(0x00001000)
+
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+/*!
+ *  @brief  Structure defining config parameters for overall System.
+ */
+struct sysmgr_config {
+	struct sysmemmgr_config sysmemmgr_cfg;
+	/*!< System memory manager config parameter */
+
+	struct multiproc_config multiproc_cfg;
+	/*!< Multiproc config parameter */
+
+	struct gatepeterson_config gatepeterson_cfg;
+	/*!< Gatepeterson config parameter */
+
+	struct sharedregion_config sharedregion_cfg;
+	/*!< SharedRegion config parameter */
+
+	struct messageq_config messageq_cfg;
+	/*!< MessageQ config parameter */
+
+	struct notify_config notify_cfg;
+	/*!< Notify config parameter */
+
+	struct proc_mgr_config proc_mgr_cfg;
+	/*!< Processor manager config parameter */
+
+	struct heapbuf_config heapbuf_cfg;
+	/*!< Heap Buf config parameter */
+
+	struct listmp_config listmp_sharedmemory_cfg;
+	/*!< ListMPSharedMemory config parameter */
+
+	struct messageq_transportshm_config messageq_transportshm_cfg;
+	/*!< MessageQTransportShm config parameter */
+
+	struct notify_ducatidrv_config notify_ducatidrv_cfg;
+	/*!< NotifyDriverShm config parameter */
+
+	struct nameserver_remotenotify_config nameserver_remotenotify_cfg;
+	/*!< NameServerRemoteNotify config parameter */
+};
+
+
+/* =============================================================================
+ * APIs
+ * =============================================================================
+ */
+/* Function to initialize the parameter structure */
+void sysmgr_get_config(struct sysmgr_config *config);
+
+/* Function to initialize sysmgr module */
+s32 sysmgr_setup(const struct sysmgr_config *config);
+
+/* Function to Finalize sysmgr module */
+s32 sysmgr_destroy(void);
+
+
+#endif /* ifndef SYSMGR_H_0xF086 */
diff --git a/arch/arm/plat-omap/include/syslink/transportshm.h b/arch/arm/plat-omap/include/syslink/transportshm.h
new file mode 100644
index 000000000000..02a2b6a80c90
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/transportshm.h
@@ -0,0 +1,220 @@
+/*
+ *  transportshm.h
+ *
+ *  Shared memory based physical transport for
+ *  communication with the remote processor.
+ *
+ *  This file contains the declarations of types and APIs as part
+ *  of interface of the shared memory transport.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _TRANSPORTSHM_H_
+#define _TRANSPORTSHM_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/list.h>
+
+/* =============================================================================
+ *  All success and failure codes for the module
+ * =============================================================================
+ */
+/* Unique module ID. */
+#define TRANSPORTSHM_MODULEID		(0x0a7a)
+
+/* =============================================================================
+ *  All success and failure codes for the module
+ * =============================================================================
+ */
+/* Error code base for TransportShm. */
+#define TRANSPORTSHM_STATUSCODEBASE	(TRANSPORTSHM_MODULEID << 12)
+
+/* Macro to make error code. */
+#define TRANSPORTSHM_MAKE_FAILURE(x)	((int)  (0x80000000 \
+				+ (TRANSPORTSHM_STATUSCODEBASE \
+				+ (x))))
+
+/* Macro to make success code. */
+#define TRANSPORTSHM_MAKE_SUCCESS(x)	(TRANSPORTSHM_STATUSCODEBASE + (x))
+
+/* Argument passed to a function is invalid. */
+#define TRANSPORTSHM_E_INVALIDARG	TRANSPORTSHM_MAKE_FAILURE(1)
+
+/* Invalid shared address size */
+#define TRANSPORTSHM_E_INVALIDSIZE	TRANSPORTSHM_MAKE_FAILURE(2)
+
+/* Module is not initialized. */
+#define TRANSPORTSHM_E_INVALIDSTATE	TRANSPORTSHM_MAKE_FAILURE(3)
+
+/* Versions don't match */
+#define TRANSPORTSHM_E_BADVERSION	TRANSPORTSHM_MAKE_FAILURE(4)
+
+/* General Failure */
+#define TRANSPORTSHM_E_FAIL		TRANSPORTSHM_MAKE_FAILURE(5)
+
+/* Memory allocation failed */
+#define TRANSPORTSHM_E_MEMORY		TRANSPORTSHM_MAKE_FAILURE(6)
+
+/* Failure in OS call. */
+#define TRANSPORTSHM_E_OSFAILURE	TRANSPORTSHM_MAKE_FAILURE(7)
+
+/* Invalid handle specified. */
+#define TRANSPORTSHM_E_HANDLE		TRANSPORTSHM_MAKE_FAILURE(8)
+
+/* The specified operation is not supported. */
+#define TRANSPORTSHM_E_NOTSUPPORTED	TRANSPORTSHM_MAKE_FAILURE(9)
+
+/* Operation successful. */
+#define TRANSPORTSHM_SUCCESS		TRANSPORTSHM_MAKE_SUCCESS(0)
+
+/* The MESSAGETRANSPORTSHM module has already been setup in this process. */
+#define TRANSPORTSHM_S_ALREADYSETUP	TRANSPORTSHM_MAKE_SUCCESS(1)
+
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+
+/*
+ *    Structure defining the reason for error function being called
+ */
+enum transportshm_reason {
+	TRANSPORTSHM_REASON_FAILEDPUT,
+	/* Failed to send the message. */
+	TRANSPORTSHM_REASON_INTERNALERR,
+	/* An internal error occurred in the transport */
+	TRANSPORTSHM_REASON_PHYSICALERR,
+	/*  An error occurred in the physical link in the transport */
+	TRANSPORTSHM_REASON_FAILEDALLOC
+	/*  Failed to allocate a message. */
+};
+
+/*
+ *     transport error callback function.
+ *
+ *  First parameter: Why the error function is being called.
+ *
+ *  Second parameter: Handle of transport that had the error. NULL denotes
+ *  that it is a system error, not a specific transport.
+ *
+ *  Third parameter: Pointer to the message. This is only valid for
+ *  #TRANSPORTSHM_REASON_FAILEDPUT.
+ *
+ *  Fourth parameter: Transport specific information. Refer to individual
+ *  transports for more details.
+ */
+
+/*
+ *    Module configuration structure.
+ */
+struct transportshm_config {
+	void (*err_fxn)(enum transportshm_reason reason,
+				void *handle,
+				void *msg,
+				u32 info);
+	/* Asynchronous error function for the transport module */
+};
+
+/*
+ *    Structure defining config parameters for the transport
+ *  instances.
+ */
+struct transportshm_params {
+	u32 priority;
+	/*<  Priority of messages supported by this transport */
+	void *gate;
+	/*< Gate used for critical region management of the shared memory */
+	void *shared_addr;
+	/*<  Address of the shared memory. The creator must supply the shared
+	*    memory that this will use for maintain shared state information.
+	*/
+	u32 notify_event_id;
+	/*<  Notify event number to be used by the transport */
+};
+
+/*
+ *    Structure defining Transport status values
+ */
+enum transportshm_status {
+	transportshm_status_INIT,
+	/*< Transport Shm instance has not not completed
+	* initialization. */
+	transportshm_status_UP,
+	/*< Transport Shm instance is up and functional. */
+	transportshm_status_DOWN,
+	/*< Transport Shm instance is down and not functional. */
+	transportshm_status_RESETTING
+	/*< Transport Shm instance was up at one point and is in
+	* process of resetting.
+	*/
+};
+
+
+/* =============================================================================
+ *  APIs called by applications
+ * =============================================================================
+ */
+/* Function to get the default configuration for the TransportShm
+ * module. */
+void transportshm_get_config(struct transportshm_config *cfg);
+
+/* Function to setup the TransportShm module. */
+int transportshm_setup(const struct transportshm_config *cfg);
+
+/* Function to destroy the TransportShm module. */
+int transportshm_destroy(void);
+
+/* Get the default parameters for the NotifyShmDriver. */
+void transportshm_params_init(struct transportshm_params *params);
+
+/* Create an instance of the TransportShm. */
+void *transportshm_create(u16 proc_id,
+			const struct transportshm_params *params);
+
+/* Delete an instance of the TransportShm. */
+int transportshm_delete(void **handle_ptr);
+
+/* Open a created TransportShm instance by address */
+int transportshm_open_by_addr(void *shared_addr, void **handle_ptr);
+
+/* Close an opened instance */
+int transportshm_close(void **handle_ptr);
+
+/* Get the shared memory requirements for the TransportShm. */
+u32 transportshm_shared_mem_req(const struct transportshm_params *params);
+
+/* Set the asynchronous error function for the transport module */
+void transportshm_set_err_fxn(void (*err_fxn)(enum transportshm_reason reason,
+					      void *handle,
+					      void *msg,
+					      u32 info));
+
+
+/* =============================================================================
+ *  APIs called internally by TransportShm module.
+ * =============================================================================
+ */
+/* Put msg to remote list */
+int transportshm_put(void *handle, void *msg);
+
+/* Control Function */
+int transportshm_control(void *handle, u32 cmd, u32 *cmd_arg);
+
+/* Get current status of the TransportShm */
+enum transportshm_status transportshm_get_status(void *handle);
+
+#endif /* _TRANSPORTSHM_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/transportshm_setup.h b/arch/arm/plat-omap/include/syslink/transportshm_setup.h
new file mode 100644
index 000000000000..99345773dd8f
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/transportshm_setup.h
@@ -0,0 +1,47 @@
+/*
+ *  transportshm_setup.h
+ *
+ *  Shared Memory Transport setup layer
+ *
+ *  This file contains the declarations of types and APIs as part
+ *  of interface of the shared memory transport.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _TRANSPORTSHM_SETUP_H_
+#define _TRANSPORTSHM_SETUP_H_
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/list.h>
+
+/* =============================================================================
+ *  APIs called by applications
+ * =============================================================================
+ */
+
+/* Function that will be called in messageq_attach */
+int transportshm_setup_attach(u16 remote_proc_id, u32 *shared_addr);
+
+/* Function that will be called in messageq_detach */
+int transportshm_setup_detach(u16 remote_proc_id);
+
+/* Function that returns the amount of shared memory required */
+u32 transportshm_setup_shared_mem_req(u32 *shared_addr);
+
+/* Determines if a transport has been registered to a remote processor */
+bool transportshm_setup_is_registered(u16 remote_proc_id);
+
+#endif /* _TRANSPORTSHM_SETUP_H_ */
diff --git a/arch/arm/plat-omap/include/syslink/transportshm_setup_proxy.h b/arch/arm/plat-omap/include/syslink/transportshm_setup_proxy.h
new file mode 100644
index 000000000000..72eaf400a195
--- /dev/null
+++ b/arch/arm/plat-omap/include/syslink/transportshm_setup_proxy.h
@@ -0,0 +1,48 @@
+/*
+ *  transportshm_setup_proxy.h
+ *
+ *  Shared Memory Transport setup layer
+ *
+ *  This file contains the declarations of types and APIs as part
+ *  of interface of the shared memory transport.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#ifndef _TRANSPORTSHM_SETUP_PROXY_H_
+#define _TRANSPORTSHM_SETUP_PROXY_H_
+
+/* Module headers */
+#include <transportshm_setup.h>
+
+/* =============================================================================
+ *  APIs
+ * =============================================================================
+ */
+/* function that will be called in messageq_attach */
+#define messageq_setup_transport_proxy_attach(remote_proc_id, shared_addr) \
+				transportshm_setup_attach(remote_proc_id, \
+								shared_addr)
+
+/* function that will be called in messageq_detach */
+#define messageq_setup_transport_proxy_detach(remote_proc_id) \
+				transportshm_setup_detach(remote_proc_id)
+
+/* Shared memory req function */
+#define messageq_setup_transport_proxy_shared_mem_req(shared_addr) \
+				transportshm_setup_shared_mem_req(shared_addr)
+
+/* is_registered function */
+#define messageq_setup_transport_proxy_is_registered(remote_proc_id) \
+				transportshm_setup_is_registered(remote_proc_id)
+
+#endif /* _TRANSPORTSHM_SETUP_PROXY_H_ */
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 0e137663349c..bd196a383332 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -25,6 +25,24 @@
 
 #include "iopgtable.h"
 
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/file.h>
+#include <linux/poll.h>
+
+
+#define for_each_iotlb_cr(obj, n, __i, cr)				\
+	for (__i = 0;							\
+	     (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);	\
+	     __i++)
+#define OMAP_IOMMU_NAME "omap-iommu"
+
+static atomic_t		num_of_iommus;
+static struct class	*omap_iommu_class;
+static dev_t		omap_iommu_dev;
+
+
 /* accommodate the difference between omap1 and omap2/3 */
 static const struct iommu_functions *arch_iommu;
 
@@ -98,12 +116,7 @@ static int iommu_enable(struct iommu *obj)
 
 	if (!obj)
 		return -EINVAL;
-
-	clk_enable(obj->clk);
-
 	err = arch_iommu->enable(obj);
-
-	clk_disable(obj->clk);
 	return err;
 }
 
@@ -111,12 +124,7 @@ static void iommu_disable(struct iommu *obj)
 {
 	if (!obj)
 		return;
-
-	clk_enable(obj->clk);
-
 	arch_iommu->disable(obj);
-
-	clk_disable(obj->clk);
 }
 
 /*
@@ -171,16 +179,12 @@ static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
 
 	l->base = MMU_LOCK_BASE(val);
 	l->vict = MMU_LOCK_VICT(val);
-
-	BUG_ON(l->base != 0); /* Currently no preservation is used */
 }
 
 static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l)
 {
 	u32 val;
 
-	BUG_ON(l->base != 0); /* Currently no preservation is used */
-
 	val = (l->base << MMU_LOCK_BASE_SHIFT);
 	val |= (l->vict << MMU_LOCK_VICT_SHIFT);
 
@@ -214,6 +218,20 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
 	return arch_iommu->dump_cr(obj, cr, buf);
 }
 
+/* only used for iotlb iteration in for-loop */
+static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n)
+{
+	struct cr_regs cr;
+	struct iotlb_lock l;
+
+	iotlb_lock_get(obj, &l);
+	l.vict = n;
+	iotlb_lock_set(obj, &l);
+	iotlb_read_cr(obj, &cr);
+
+	return cr;
+}
+
 /**
  * load_iotlb_entry - Set an iommu tlb entry
  * @obj:	target iommu
@@ -221,7 +239,6 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
  **/
 int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
 {
-	int i;
 	int err = 0;
 	struct iotlb_lock l;
 	struct cr_regs *cr;
@@ -229,40 +246,46 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
 	if (!obj || !obj->nr_tlb_entries || !e)
 		return -EINVAL;
 
-	clk_enable(obj->clk);
-
-	for (i = 0; i < obj->nr_tlb_entries; i++) {
+	iotlb_lock_get(obj, &l);
+	if (l.base == obj->nr_tlb_entries) {
+		dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
+		err = -EBUSY;
+		goto out;
+	}
+	if (!e->prsvd) {
+		int i;
 		struct cr_regs tmp;
 
+		for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
+			if (!iotlb_cr_valid(&tmp))
+				break;
+
+		if (i == obj->nr_tlb_entries) {
+			dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
+			err = -EBUSY;
+			goto out;
+		}
+
 		iotlb_lock_get(obj, &l);
-		l.vict = i;
+	} else {
+		l.vict = l.base;
 		iotlb_lock_set(obj, &l);
-		iotlb_read_cr(obj, &tmp);
-		if (!iotlb_cr_valid(&tmp))
-			break;
-	}
-
-	if (i == obj->nr_tlb_entries) {
-		dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
-		err = -EBUSY;
-		goto out;
 	}
 
 	cr = iotlb_alloc_cr(obj, e);
-	if (IS_ERR(cr)) {
-		clk_disable(obj->clk);
+	if (IS_ERR(cr))
 		return PTR_ERR(cr);
-	}
 
 	iotlb_load_cr(obj, cr);
 	kfree(cr);
 
+	if (e->prsvd)
+		l.base++;
 	/* increment victim for next tlb load */
 	if (++l.vict == obj->nr_tlb_entries)
-		l.vict = 0;
+		l.vict = l.base;
 	iotlb_lock_set(obj, &l);
 out:
-	clk_disable(obj->clk);
 	return err;
 }
 EXPORT_SYMBOL_GPL(load_iotlb_entry);
@@ -276,20 +299,13 @@ EXPORT_SYMBOL_GPL(load_iotlb_entry);
  **/
 void flush_iotlb_page(struct iommu *obj, u32 da)
 {
-	struct iotlb_lock l;
 	int i;
+	struct cr_regs cr;
 
-	clk_enable(obj->clk);
-
-	for (i = 0; i < obj->nr_tlb_entries; i++) {
-		struct cr_regs cr;
+	for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
 		u32 start;
 		size_t bytes;
 
-		iotlb_lock_get(obj, &l);
-		l.vict = i;
-		iotlb_lock_set(obj, &l);
-		iotlb_read_cr(obj, &cr);
 		if (!iotlb_cr_valid(&cr))
 			continue;
 
@@ -299,12 +315,9 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
 		if ((start <= da) && (da < start + bytes)) {
 			dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
 				__func__, start, da, bytes);
-			iotlb_load_cr(obj, &cr);
 			iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
 		}
 	}
-	clk_disable(obj->clk);
-
 	if (i == obj->nr_tlb_entries)
 		dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
 }
@@ -338,18 +351,28 @@ void flush_iotlb_all(struct iommu *obj)
 {
 	struct iotlb_lock l;
 
-	clk_enable(obj->clk);
-
 	l.base = 0;
 	l.vict = 0;
 	iotlb_lock_set(obj, &l);
-
 	iommu_write_reg(obj, 1, MMU_GFLUSH);
-
-	clk_disable(obj->clk);
 }
 EXPORT_SYMBOL_GPL(flush_iotlb_all);
 
+/**
+ * iommu_set_twl - enable/disable table walking logic
+ * @obj:	target iommu
+ * @on:		enable/disable
+ *
+ * Function used to enable/disable TWL. If one wants to work
+ * exclusively with locked TLB entries and receive notifications
+ * for TLB miss then call this function to disable TWL.
+ */
+void iommu_set_twl(struct iommu *obj, bool on)
+{
+	arch_iommu->set_twl(obj, on);
+}
+EXPORT_SYMBOL_GPL(iommu_set_twl);
+
 #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
 
 ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
@@ -357,12 +380,7 @@ ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
 	if (!obj || !buf)
 		return -EINVAL;
 
-	clk_enable(obj->clk);
-
 	bytes = arch_iommu->dump_ctx(obj, buf, bytes);
-
-	clk_disable(obj->clk);
-
 	return bytes;
 }
 EXPORT_SYMBOL_GPL(iommu_dump_ctx);
@@ -370,29 +388,18 @@ EXPORT_SYMBOL_GPL(iommu_dump_ctx);
 static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
 {
 	int i;
-	struct iotlb_lock saved, l;
+	struct iotlb_lock saved;
+	struct cr_regs tmp;
 	struct cr_regs *p = crs;
 
-	clk_enable(obj->clk);
-
 	iotlb_lock_get(obj, &saved);
-	memcpy(&l, &saved, sizeof(saved));
-
-	for (i = 0; i < num; i++) {
-		struct cr_regs tmp;
-
-		iotlb_lock_get(obj, &l);
-		l.vict = i;
-		iotlb_lock_set(obj, &l);
-		iotlb_read_cr(obj, &tmp);
+	for_each_iotlb_cr(obj, num, i, tmp) {
 		if (!iotlb_cr_valid(&tmp))
 			continue;
-
 		*p++ = tmp;
 	}
-	iotlb_lock_set(obj, &saved);
-	clk_disable(obj->clk);
 
+	iotlb_lock_set(obj, &saved);
 	return  p - crs;
 }
 
@@ -745,10 +752,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
 
 	if (!err)
 		return IRQ_HANDLED;
-
-	clk_enable(obj->clk);
 	stat = iommu_report_fault(obj, &da);
-	clk_disable(obj->clk);
 	if (!stat)
 		return IRQ_HANDLED;
 
@@ -787,28 +791,23 @@ struct iommu *iommu_get(const char *name)
 	int err = -ENOMEM;
 	struct device *dev;
 	struct iommu *obj;
-
 	dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
 				 device_match_by_alias);
 	if (!dev)
 		return ERR_PTR(-ENODEV);
-
 	obj = to_iommu(dev);
 
 	mutex_lock(&obj->iommu_lock);
-
 	if (obj->refcount++ == 0) {
 		err = iommu_enable(obj);
 		if (err)
 			goto err_enable;
 		flush_iotlb_all(obj);
 	}
-
 	if (!try_module_get(obj->owner))
 		goto err_module;
 
 	mutex_unlock(&obj->iommu_lock);
-
 	dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
 	return obj;
 
@@ -844,6 +843,86 @@ void iommu_put(struct iommu *obj)
 }
 EXPORT_SYMBOL_GPL(iommu_put);
 
+struct omap_iommu_dev {
+	struct device *dev;
+	struct cdev cdev;
+	atomic_t count;
+	int state;
+	int minor;
+};
+
+static int omap_iommu_open(struct inode *inode, struct file *filp)
+{
+	int ret = 0;
+	struct iommu *obj;
+
+	obj = container_of(inode->i_cdev, struct iommu, cdev);
+	if (!obj->dev)
+		return -EINVAL;
+
+	filp->private_data = obj;
+	iommu_get(obj->name);
+
+	return ret;
+}
+
+static int omap_iommu_release(struct inode *inode, struct file *filp)
+{
+	struct iommu *obj;
+	obj = container_of(inode->i_cdev, struct iommu, cdev);
+	if (!obj->dev)
+		return -EINVAL;
+	iommu_put(obj);
+	return 0;
+}
+
+static int omap_iommu_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args)
+
+{
+	struct iommu *obj;
+	int ret = 0;
+
+	obj = filp->private_data;
+	if (!obj)
+		return -EINVAL;
+
+	if (_IOC_TYPE(cmd) != IOMMU_IOC_MAGIC)
+		return -ENOTTY;
+
+	switch (cmd) {
+	case IOMMU_IOCSETTLBENT:
+	{
+		struct iotlb_entry e;
+		int size;
+		/* FIXME: Re-visit the following check */
+		/*if (!capable(CAP_SYS_ADMIN))
+		  return -EPERM;*/
+		size = copy_from_user(&e, (void __user *)args,
+					sizeof(struct iotlb_entry));
+		if (size) {
+			ret = -EINVAL;
+			goto err_user_buf;
+		}
+		load_iotlb_entry(obj, &e);
+		break;
+	}
+	default:
+		return -ENOTTY;
+	}
+err_user_buf:
+	return ret;
+}
+
+
+static const struct file_operations omap_iommu_fops = {
+	.owner		=	THIS_MODULE,
+	.open		=	omap_iommu_open,
+	.release	=	omap_iommu_release,
+	.ioctl		=	omap_iommu_ioctl,
+};
+
+
 /*
  *	OMAP Device MMU(IOMMU) detection
  */
@@ -855,6 +934,9 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
 	struct iommu *obj;
 	struct resource *res;
 	struct iommu_platform_data *pdata = pdev->dev.platform_data;
+	int major, minor;
+	struct device *tmpdev;
+	int ret = 0;
 
 	if (pdev->num_resources != 2)
 		return -EINVAL;
@@ -918,8 +1000,42 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
 	BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE));
 
 	dev_info(&pdev->dev, "%s registered\n", obj->name);
+
+	major = MAJOR(omap_iommu_dev);
+	minor = atomic_read(&num_of_iommus);
+	atomic_inc(&num_of_iommus);
+
+	obj->minor = minor;
+
+	cdev_init(&obj->cdev, &omap_iommu_fops);
+	obj->cdev.owner = THIS_MODULE;
+	ret = cdev_add(&obj->cdev, MKDEV(major, minor), 1);
+	if (ret) {
+		dev_err(&pdev->dev, "%s: cdev_add failed: %d\n", __func__, ret);
+		goto err_cdev;
+	}
+
+	tmpdev = device_create(omap_iommu_class, NULL,
+				MKDEV(major, minor),
+				NULL,
+				OMAP_IOMMU_NAME "%d", minor);
+	if (IS_ERR(tmpdev)) {
+		ret = PTR_ERR(tmpdev);
+		pr_err("%s: device_create failed: %d\n", __func__, ret);
+		goto clean_cdev;
+	}
+
+	pr_info("%s initialized %s, major: %d, base-minor: %d\n",
+			OMAP_IOMMU_NAME,
+			pdata->name,
+			MAJOR(omap_iommu_dev),
+			minor);
+
 	return 0;
 
+clean_cdev:
+	cdev_del(&obj->cdev);
+err_cdev:
 err_pgd:
 	free_irq(irq, obj);
 err_irq:
@@ -937,6 +1053,10 @@ static int __devexit omap_iommu_remove(struct platform_device *pdev)
 	int irq;
 	struct resource *res;
 	struct iommu *obj = platform_get_drvdata(pdev);
+	int major = MAJOR(omap_iommu_dev);
+
+	device_destroy(omap_iommu_class, MKDEV(major, obj->minor));
+	cdev_del(&obj->cdev);
 
 	platform_set_drvdata(pdev, NULL);
 
@@ -968,11 +1088,13 @@ static void iopte_cachep_ctor(void *iopte)
 	clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
 }
 
+
 static int __init omap_iommu_init(void)
 {
 	struct kmem_cache *p;
 	const unsigned long flags = SLAB_HWCACHE_ALIGN;
 	size_t align = 1 << 10; /* L2 pagetable alignement */
+	int ret, num;
 
 	p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
 			      iopte_cachep_ctor);
@@ -980,7 +1102,28 @@ static int __init omap_iommu_init(void)
 		return -ENOMEM;
 	iopte_cachep = p;
 
+	num = iommu_get_plat_data_size();
+	ret = alloc_chrdev_region(&omap_iommu_dev, 0, num, OMAP_IOMMU_NAME);
+
+	if (ret) {
+		pr_err("%s: alloc_chrdev_region failed: %d\n", __func__, ret);
+		goto out;
+	}
+
+	omap_iommu_class = class_create(THIS_MODULE, OMAP_IOMMU_NAME);
+	if (IS_ERR(omap_iommu_class)) {
+		ret = PTR_ERR(omap_iommu_class);
+		pr_err("%s: class_create failed: %d\n", __func__, ret);
+		goto unreg_region;
+	}
+	atomic_set(&num_of_iommus, 0);
+
 	return platform_driver_register(&omap_iommu_driver);
+
+unreg_region:
+	unregister_chrdev_region(omap_iommu_dev, num);
+out:
+	return ret;
 }
 module_init(omap_iommu_init);
 
@@ -989,6 +1132,9 @@ static void __exit omap_iommu_exit(void)
 	kmem_cache_destroy(iopte_cachep);
 
 	platform_driver_unregister(&omap_iommu_driver);
+
+	if (omap_iommu_class)
+		class_destroy(omap_iommu_class);
 }
 module_exit(omap_iommu_exit);
 
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 08a2df766289..b06d3de49a80 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -26,12 +26,14 @@
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/kfifo.h>
 
 #include <plat/mailbox.h>
 
 static struct workqueue_struct *mboxd;
 static struct omap_mbox *mboxes;
-static DEFINE_RWLOCK(mboxes_lock);
+static DEFINE_SPINLOCK(mboxes_lock);
+static bool rq_full;
 
 static int mbox_configured;
 
@@ -67,61 +69,69 @@ static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
 /*
  * message sender
  */
-static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
+static int __mbox_poll_for_space(struct omap_mbox *mbox)
 {
 	int ret = 0, i = 1000;
 
 	while (mbox_fifo_full(mbox)) {
-		if (mbox->ops->type == OMAP_MBOX_TYPE2)
-			return -1;
 		if (--i == 0)
 			return -1;
 		udelay(1);
+		printk(KERN_ERR "Mailbox FIFO full %d\n", i);
 	}
-	mbox_fifo_write(mbox, msg);
 	return ret;
 }
 
 
 int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
 {
+	struct omap_mbox_queue *mq = mbox->txq;
+	int ret = 0, len;
 
-	struct request *rq;
-	struct request_queue *q = mbox->txq->queue;
+	spin_lock_bh(&mq->lock);
+	if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
+		ret = -ENOMEM;
+		goto out;
+	}
 
-	rq = blk_get_request(q, WRITE, GFP_ATOMIC);
-	if (unlikely(!rq))
-		return -ENOMEM;
+	len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+	if (unlikely(len != sizeof(msg))) {
+		pr_err("%s: kfifo_in anomaly\n", __func__);
+		ret = -ENOMEM;
+	}
 
-	blk_insert_request(q, rq, 0, (void *) msg);
 	tasklet_schedule(&mbox->txq->tasklet);
 
-	return 0;
+out:
+	spin_unlock_bh(&mq->lock);
+	return ret;
 }
 EXPORT_SYMBOL(omap_mbox_msg_send);
 
 static void mbox_tx_tasklet(unsigned long tx_data)
 {
-	int ret;
-	struct request *rq;
 	struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
-	struct request_queue *q = mbox->txq->queue;
+	struct omap_mbox_queue *mq = mbox->txq;
+	mbox_msg_t msg;
+	int ret;
 
-	while (1) {
+	spin_lock(&mq->lock);
+	while (kfifo_len(&mq->fifo)) {
+		if (__mbox_poll_for_space(mbox)) {
+			omap_mbox_enable_irq(mbox, IRQ_TX);
+			break;
+		}
 
-		rq = blk_fetch_request(q);
+		ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
+								sizeof(msg));
+		if (unlikely(ret != sizeof(msg)))
+			pr_err("%s: kfifo_out anomaly\n", __func__);
+
+		mbox_fifo_write(mbox, msg);
 
-		if (!rq)
-			break;
 
-		ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special);
-		if (ret) {
-			omap_mbox_enable_irq(mbox, IRQ_TX);
-			blk_requeue_request(q, rq);
-			return;
-		}
-		blk_end_request_all(rq, 0);
 	}
+	spin_unlock(&mq->lock);
 }
 
 /*
@@ -131,36 +141,22 @@ static void mbox_rx_work(struct work_struct *work)
 {
 	struct omap_mbox_queue *mq =
 			container_of(work, struct omap_mbox_queue, work);
-	struct omap_mbox *mbox = mq->queue->queuedata;
-	struct request_queue *q = mbox->rxq->queue;
-	struct request *rq;
 	mbox_msg_t msg;
-	unsigned long flags;
+	int len;
 
-	while (1) {
-		spin_lock_irqsave(q->queue_lock, flags);
-		rq = blk_fetch_request(q);
-		spin_unlock_irqrestore(q->queue_lock, flags);
-		if (!rq)
-			break;
+	while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
+		len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+		if (unlikely(len != sizeof(msg)))
+			pr_err("%s: kfifo_out anomaly detected\n", __func__);
 
-		msg = (mbox_msg_t)rq->special;
-		blk_end_request_all(rq, 0);
-		mbox->rxq->callback((void *)msg);
+		if (mq->callback)
+			mq->callback((void *)msg);
 	}
 }
 
 /*
  * Mailbox interrupt handler
  */
-static void mbox_txq_fn(struct request_queue *q)
-{
-}
-
-static void mbox_rxq_fn(struct request_queue *q)
-{
-}
-
 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
 {
 	omap_mbox_disable_irq(mbox, IRQ_TX);
@@ -170,19 +166,22 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox)
 
 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 {
-	struct request *rq;
+	struct omap_mbox_queue *mq = mbox->rxq;
 	mbox_msg_t msg;
-	struct request_queue *q = mbox->rxq->queue;
+	int len;
 
 	while (!mbox_fifo_empty(mbox)) {
-		rq = blk_get_request(q, WRITE, GFP_ATOMIC);
-		if (unlikely(!rq))
+		if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
+			omap_mbox_disable_irq(mbox, IRQ_RX);
+			rq_full = true;
 			goto nomem;
+		}
 
 		msg = mbox_fifo_read(mbox);
 
-
-		blk_insert_request(q, rq, 0, (void *)msg);
+		len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+		if (unlikely(len != sizeof(msg)))
+			pr_err("%s: kfifo_in anomaly detected\n", __func__);
 		if (mbox->ops->type == OMAP_MBOX_TYPE1)
 			break;
 	}
@@ -207,11 +206,9 @@ static irqreturn_t mbox_interrupt(int irq, void *p)
 }
 
 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
-					request_fn_proc *proc,
 					void (*work) (struct work_struct *),
 					void (*tasklet)(unsigned long))
 {
-	struct request_queue *q;
 	struct omap_mbox_queue *mq;
 
 	mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
@@ -220,11 +217,8 @@ static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
 
 	spin_lock_init(&mq->lock);
 
-	q = blk_init_queue(proc, &mq->lock);
-	if (!q)
+	if (kfifo_alloc(&mq->fifo, MBOX_KFIFO_SIZE, GFP_KERNEL))
 		goto error;
-	q->queuedata = mbox;
-	mq->queue = q;
 
 	if (work)
 		INIT_WORK(&mq->work, work);
@@ -239,7 +233,7 @@ error:
 
 static void mbox_queue_free(struct omap_mbox_queue *q)
 {
-	blk_cleanup_queue(q->queue);
+	kfifo_free(&q->fifo);
 	kfree(q);
 }
 
@@ -249,16 +243,16 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 	struct omap_mbox_queue *mq;
 
 	if (likely(mbox->ops->startup)) {
-		write_lock(&mboxes_lock);
+		spin_lock(&mboxes_lock);
 		if (!mbox_configured)
 			ret = mbox->ops->startup(mbox);
 
 		if (unlikely(ret)) {
-			write_unlock(&mboxes_lock);
+			spin_unlock(&mboxes_lock);
 			return ret;
 		}
 		mbox_configured++;
-		write_unlock(&mboxes_lock);
+		spin_unlock(&mboxes_lock);
 	}
 
 	ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
@@ -269,14 +263,14 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 		goto fail_request_irq;
 	}
 
-	mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet);
+	mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
 	if (!mq) {
 		ret = -ENOMEM;
 		goto fail_alloc_txq;
 	}
 	mbox->txq = mq;
 
-	mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL);
+	mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
 	if (!mq) {
 		ret = -ENOMEM;
 		goto fail_alloc_rxq;
@@ -290,7 +284,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
  fail_alloc_txq:
 	free_irq(mbox->irq, mbox);
  fail_request_irq:
-	if (unlikely(mbox->ops->shutdown))
+	if (likely(mbox->ops->shutdown))
 		mbox->ops->shutdown(mbox);
 
 	return ret;
@@ -303,13 +297,13 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 
 	free_irq(mbox->irq, mbox);
 
-	if (unlikely(mbox->ops->shutdown)) {
-		write_lock(&mboxes_lock);
+	if (likely(mbox->ops->shutdown)) {
+		spin_lock(&mboxes_lock);
 		if (mbox_configured > 0)
 			mbox_configured--;
 		if (!mbox_configured)
 			mbox->ops->shutdown(mbox);
-		write_unlock(&mboxes_lock);
+		spin_unlock(&mboxes_lock);
 	}
 }
 
@@ -330,14 +324,14 @@ struct omap_mbox *omap_mbox_get(const char *name)
 	struct omap_mbox *mbox;
 	int ret;
 
-	read_lock(&mboxes_lock);
+	spin_lock(&mboxes_lock);
 	mbox = *(find_mboxes(name));
 	if (mbox == NULL) {
-		read_unlock(&mboxes_lock);
+		spin_unlock(&mboxes_lock);
 		return ERR_PTR(-ENOENT);
 	}
 
-	read_unlock(&mboxes_lock);
+	spin_unlock(&mboxes_lock);
 
 	ret = omap_mbox_startup(mbox);
 	if (ret)
@@ -363,15 +357,15 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
 	if (mbox->next)
 		return -EBUSY;
 
-	write_lock(&mboxes_lock);
+	spin_lock(&mboxes_lock);
 	tmp = find_mboxes(mbox->name);
 	if (*tmp) {
 		ret = -EBUSY;
-		write_unlock(&mboxes_lock);
+		spin_unlock(&mboxes_lock);
 		goto err_find;
 	}
 	*tmp = mbox;
-	write_unlock(&mboxes_lock);
+	spin_unlock(&mboxes_lock);
 
 	return 0;
 
@@ -384,18 +378,18 @@ int omap_mbox_unregister(struct omap_mbox *mbox)
 {
 	struct omap_mbox **tmp;
 
-	write_lock(&mboxes_lock);
+	spin_lock(&mboxes_lock);
 	tmp = &mboxes;
 	while (*tmp) {
 		if (mbox == *tmp) {
 			*tmp = mbox->next;
 			mbox->next = NULL;
-			write_unlock(&mboxes_lock);
+			spin_unlock(&mboxes_lock);
 			return 0;
 		}
 		tmp = &(*tmp)->next;
 	}
-	write_unlock(&mboxes_lock);
+	spin_unlock(&mboxes_lock);
 
 	return -EINVAL;
 }
@@ -403,7 +397,7 @@ EXPORT_SYMBOL(omap_mbox_unregister);
 
 static int __init omap_mbox_init(void)
 {
-	mboxd = create_workqueue("mboxd");
+	mboxd = create_singlethread_workqueue("mboxd");
 	if (!mboxd)
 		return -ENOMEM;
 
@@ -419,4 +413,5 @@ module_exit(omap_mbox_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
-MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU");
+MODULE_AUTHOR("Toshihiro Kobayashi");
+MODULE_AUTHOR("Hiroshi DOYU");
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 2aa5337855ed..6c77d6f12188 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -491,7 +491,7 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 {
 	struct omap_mcbsp *mcbsp;
 
-	if (!cpu_is_omap34xx())
+	if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 		return;
 
 	if (!omap_mcbsp_check_valid_id(id)) {
@@ -513,7 +513,7 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 {
 	struct omap_mcbsp *mcbsp;
 
-	if (!cpu_is_omap34xx())
+	if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 		return;
 
 	if (!omap_mcbsp_check_valid_id(id)) {
@@ -589,7 +589,7 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 	 * Enable wakup behavior, smart idle and all wakeups
 	 * REVISIT: some wakeups may be unnecessary
 	 */
-	if (cpu_is_omap34xx()) {
+	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		u16 syscon;
 
 		syscon = MCBSP_READ(mcbsp, SYSCON);
@@ -612,7 +612,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 	/*
 	 * Disable wakup behavior, smart idle and all wakeups
 	 */
-	if (cpu_is_omap34xx()) {
+	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		u16 syscon;
 
 		syscon = MCBSP_READ(mcbsp, SYSCON);
@@ -726,14 +726,17 @@ int omap_mcbsp_request(unsigned int id)
 			goto err_clk_disable;
 		}
 
-		init_completion(&mcbsp->rx_irq_completion);
-		err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
+		if (mcbsp->rx_irq) {
+			init_completion(&mcbsp->rx_irq_completion);
+			err = request_irq(mcbsp->rx_irq,
+					omap_mcbsp_rx_irq_handler,
 					0, "McBSP", (void *)mcbsp);
-		if (err != 0) {
-			dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
-					"for McBSP%d\n", mcbsp->rx_irq,
-					mcbsp->id);
-			goto err_free_irq;
+			if (err != 0) {
+				dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
+						"for McBSP%d\n", mcbsp->rx_irq,
+						mcbsp->id);
+				goto err_free_irq;
+			}
 		}
 	}
 
@@ -783,7 +786,8 @@ void omap_mcbsp_free(unsigned int id)
 
 	if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 		/* Free IRQs */
-		free_irq(mcbsp->rx_irq, (void *)mcbsp);
+		if (mcbsp->rx_irq)
+			free_irq(mcbsp->rx_irq, (void *)mcbsp);
 		free_irq(mcbsp->tx_irq, (void *)mcbsp);
 	}
 
@@ -857,7 +861,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
 		MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 	}
 
-	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		/* Release the transmitter and receiver */
 		w = MCBSP_READ_CACHE(mcbsp, XCCR);
 		w &= ~(tx ? XDISABLE : 0);
@@ -887,7 +891,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 
 	/* Reset transmitter */
 	tx &= 1;
-	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		w = MCBSP_READ_CACHE(mcbsp, XCCR);
 		w |= (tx ? XDISABLE : 0);
 		MCBSP_WRITE(mcbsp, XCCR, w);
@@ -897,7 +901,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 
 	/* Reset receiver */
 	rx &= 1;
-	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		w = MCBSP_READ_CACHE(mcbsp, RCCR);
 		w |= (rx ? RDISABLE : 0);
 		MCBSP_WRITE(mcbsp, RCCR, w);
diff --git a/arch/arm/plat-omap/remoteproc.c b/arch/arm/plat-omap/remoteproc.c
new file mode 100644
index 000000000000..9056be5a8c6b
--- /dev/null
+++ b/arch/arm/plat-omap/remoteproc.c
@@ -0,0 +1,349 @@
+/*
+ * OMAP Remote Processor driver
+ *
+ * Copyright (C) 2010 Texas Instruments Inc.
+ *
+ * Written by Ohad Ben-Cohen <ohad@wizery.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/file.h>
+#include <linux/poll.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include <plat/remoteproc.h>
+
+#define OMAP_RPROC_NAME "omap-rproc"
+#define DRV_NAME "omap-remoteproc"
+
+static struct class *omap_rproc_class;
+static dev_t omap_rproc_dev;
+static atomic_t num_of_rprocs;
+static struct platform_driver omap_rproc_driver;
+
+static inline int rproc_start(struct omap_rproc *rproc)
+{
+	struct omap_rproc_platform_data *pdata;
+	if (!rproc->dev)
+		return -EINVAL;
+
+	pdata = rproc->dev->platform_data;
+	if (!pdata->ops)
+		return -EINVAL;
+
+	return pdata->ops->start(rproc);
+}
+
+static inline int rproc_stop(struct omap_rproc *rproc)
+{
+	struct omap_rproc_platform_data *pdata;
+	if (!rproc->dev)
+		return -EINVAL;
+
+	pdata = rproc->dev->platform_data;
+	if (!pdata->ops)
+		return -EINVAL;
+
+	return pdata->ops->stop(rproc);
+}
+
+static inline int rproc_get_state(struct omap_rproc *rproc)
+{
+	struct omap_rproc_platform_data *pdata;
+	if (!rproc->dev)
+		return -EINVAL;
+
+	pdata = rproc->dev->platform_data;
+	if (!pdata->ops)
+		return -EINVAL;
+
+	return pdata->ops->get_state(rproc);
+}
+static int omap_rproc_open(struct inode *inode, struct file *filp)
+{
+	int ret = 0;
+	struct omap_rproc *rproc;
+	struct omap_rproc_platform_data *pdata;
+
+	rproc = container_of(inode->i_cdev, struct omap_rproc, cdev);
+	if (!rproc->dev)
+		return -EINVAL;
+
+	pdata = rproc->dev->platform_data;
+
+	if (pdata->ops->startup) {
+		ret = pdata->ops->startup(rproc);
+		if (ret)
+			goto out;
+	}
+	filp->private_data = rproc;
+
+out:
+	return ret;
+}
+
+static int omap_rproc_release(struct inode *inode, struct file *filp)
+{
+	struct omap_rproc_platform_data *pdata;
+	struct omap_rproc *rproc = filp->private_data;
+	if (!rproc || !rproc->dev)
+		return -EINVAL;
+
+	pdata = rproc->dev->platform_data;
+
+	if (pdata->ops->shutdown)
+		pdata->ops->shutdown(rproc);
+
+	return 0;
+}
+
+static int omap_rproc_ioctl(struct inode *inode, struct file *filp,
+					unsigned int cmd, unsigned long arg)
+{
+	int rc = 0;
+	struct omap_rproc *rproc = filp->private_data;
+
+	if (!rproc)
+		return -EINVAL;
+
+	if (_IOC_TYPE(cmd) != RPROC_IOC_MAGIC)
+		return -ENOTTY;
+	if (_IOC_NR(cmd) > RPROC_IOC_MAXNR)
+		return -ENOTTY;
+	if (_IOC_DIR(cmd) & _IOC_READ) {
+		if (!access_ok(VERIFY_WRITE, (void __user *)arg,
+				       _IOC_SIZE(cmd)))
+			return -EFAULT;
+	} else if (_IOC_DIR(cmd) & _IOC_WRITE) {
+		if (!access_ok(VERIFY_READ, (void __user *)arg,
+				       _IOC_SIZE(cmd)))
+			return -EFAULT;
+	}
+
+	switch (cmd) {
+	case RPROC_IOCSTART:
+		/*FIXME: re-visit this check to perform
+			proper permission checks */
+		/*if (!capable(CAP_SYS_ADMIN))
+			return -EPERM;*/
+		rc = rproc_start(rproc);
+		break;
+	case RPROC_IOCSTOP:
+		/*FIXME: re-visit this check to perform
+			proper permission checks */
+		/*if (!capable(CAP_SYS_ADMIN))
+			return -EPERM;*/
+		rc = rproc_stop(rproc);
+		break;
+	case RPROC_IOCGETSTATE:
+		rc = rproc_get_state(rproc);
+		break;
+
+	default:
+		return -ENOTTY;
+	}
+
+	return rc;
+}
+
+static int omap_rproc_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+
+	vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot);
+	vma->vm_flags |= VM_RESERVED;
+
+	if (remap_pfn_range(vma,
+			 vma->vm_start,
+			 vma->vm_pgoff,
+			 vma->vm_end - vma->vm_start,
+			 vma->vm_page_prot)) {
+		return -EAGAIN;
+	}
+	return 0;
+}
+
+static const struct file_operations omap_rproc_fops = {
+	.open		=	omap_rproc_open,
+	.release	=	omap_rproc_release,
+	.ioctl		=	omap_rproc_ioctl,
+	.mmap		=	omap_rproc_mmap,
+	.owner		=	THIS_MODULE,
+};
+
+static int omap_rproc_probe(struct platform_device *pdev)
+{
+	int ret = 0, major, minor;
+	struct device *tmpdev;
+	struct device *dev = &pdev->dev;
+	struct omap_rproc_platform_data *pdata = dev->platform_data;
+	struct omap_rproc *rproc;
+
+	if (!pdata || !pdata->name || !pdata->oh_name || !pdata->ops)
+		return -EINVAL;
+
+	dev_info(dev, "%s: adding rproc %s\n", __func__, pdata->name);
+
+	rproc = kzalloc(sizeof(struct omap_rproc), GFP_KERNEL);
+	if (!rproc) {
+		dev_err(dev, "%s: kzalloc failed\n", __func__);
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	platform_set_drvdata(pdev, rproc);
+	major = MAJOR(omap_rproc_dev);
+	minor = atomic_read(&num_of_rprocs);
+	atomic_inc(&num_of_rprocs);
+
+	rproc->dev = dev;
+	rproc->minor = minor;
+
+	cdev_init(&rproc->cdev, &omap_rproc_fops);
+	rproc->cdev.owner = THIS_MODULE;
+	ret = cdev_add(&rproc->cdev, MKDEV(major, minor), 1);
+	if (ret) {
+		dev_err(dev, "%s: cdev_add failed: %d\n", __func__, ret);
+		goto free_rproc;
+	}
+
+	tmpdev = device_create(omap_rproc_class, NULL,
+				MKDEV(major, minor),
+				NULL,
+				OMAP_RPROC_NAME "%d", minor);
+	if (IS_ERR(tmpdev)) {
+		ret = PTR_ERR(tmpdev);
+		pr_err("%s: device_create failed: %d\n", __func__, ret);
+		goto clean_cdev;
+	}
+
+	pr_info("%s initialized %s, major: %d, base-minor: %d\n",
+			OMAP_RPROC_NAME,
+			pdata->name,
+			MAJOR(omap_rproc_dev),
+			minor);
+	return 0;
+
+clean_cdev:
+	cdev_del(&rproc->cdev);
+free_rproc:
+	kfree(rproc);
+out:
+	return ret;
+}
+
+static int omap_rproc_remove(struct platform_device *pdev)
+{
+	int major = MAJOR(omap_rproc_dev);
+	struct device *dev = &pdev->dev;
+	struct omap_rproc_platform_data *pdata = dev->platform_data;
+	struct omap_rproc *rproc = platform_get_drvdata(pdev);
+
+	if (!pdata || !rproc)
+		return -EINVAL;
+
+	dev_info(dev, "%s removing %s, major: %d, base-minor: %d\n",
+			OMAP_RPROC_NAME,
+			pdata->name,
+			major,
+			rproc->minor);
+
+	device_destroy(omap_rproc_class, MKDEV(major, rproc->minor));
+	cdev_del(&rproc->cdev);
+
+	return 0;
+}
+
+#ifndef CONFIG_PM
+#define omap_rproc_suspend		NULL
+#define omap_rproc_resume		NULL
+#define omap_rproc_runtime_suspend	NULL
+#define omap_rproc_runtime_resume	NULL
+#endif
+
+
+const static struct dev_pm_ops omap_rproc_dev_pm_ops = {
+	.suspend = omap_rproc_suspend,
+	.resume = omap_rproc_resume,
+	.runtime_suspend = omap_rproc_runtime_suspend,
+	.runtime_resume = omap_rproc_runtime_resume,
+};
+
+static struct platform_driver omap_rproc_driver = {
+	.probe = omap_rproc_probe,
+	.remove = omap_rproc_remove,
+	.driver = {
+		.name = DRV_NAME,
+		.owner = THIS_MODULE,
+		.pm = &omap_rproc_dev_pm_ops,
+	},
+};
+
+
+static int __init omap_rproc_init(void)
+{
+	int num = remoteproc_get_plat_data_size();
+	int ret;
+
+	ret = alloc_chrdev_region(&omap_rproc_dev, 0, num, OMAP_RPROC_NAME);
+	if (ret) {
+		pr_err("%s: alloc_chrdev_region failed: %d\n", __func__, ret);
+		goto out;
+	}
+
+	omap_rproc_class = class_create(THIS_MODULE, OMAP_RPROC_NAME);
+	if (IS_ERR(omap_rproc_class)) {
+		ret = PTR_ERR(omap_rproc_class);
+		pr_err("%s: class_create failed: %d\n", __func__, ret);
+		goto unreg_region;
+	}
+
+	atomic_set(&num_of_rprocs, 0);
+
+	ret = platform_driver_register(&omap_rproc_driver);
+	if (ret) {
+		pr_err("%s: platform_driver_register failed: %d\n",
+							__func__, ret);
+		goto out;
+	}
+	return 0;
+unreg_region:
+	unregister_chrdev_region(omap_rproc_dev, num);
+out:
+	return ret;
+}
+module_init(omap_rproc_init);
+
+static void __exit omap_rproc_exit(void)
+{
+	int num = remoteproc_get_plat_data_size();
+	pr_info("%s\n", __func__);
+	class_destroy(omap_rproc_class);
+	unregister_chrdev_region(omap_rproc_dev, num);
+}
+module_exit(omap_rproc_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("OMAP Remote Processor driver");
+MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");
+MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>");
diff --git a/drivers/Kconfig b/drivers/Kconfig
index a2b902f4d437..260a07c38af8 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -111,4 +111,7 @@ source "drivers/xen/Kconfig"
 source "drivers/staging/Kconfig"
 
 source "drivers/platform/Kconfig"
+
+source "drivers/dsp/syslink/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index f42a03029b7c..76c9d154d63d 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -113,3 +113,10 @@ obj-$(CONFIG_VLYNQ)		+= vlynq/
 obj-$(CONFIG_STAGING)		+= staging/
 obj-y				+= platform/
 obj-y				+= ieee802154/
+obj-$(CONFIG_DMM_OMAP)		+= media/
+obj-$(CONFIG_TILER_OMAP)		+= media/
+obj-$(CONFIG_SYSLINK_DUCATI_PM) += dsp/syslink/multicore_ipc/
+obj-$(CONFIG_MPU_SYSLINK_PLATFORM)   += dsp/syslink/multicore_ipc/
+obj-$(CONFIG_MPU_SYSLINK_IPC)   += dsp/syslink/multicore_ipc/
+obj-$(CONFIG_SYSLINK_PROC)      += dsp/syslink/procmgr/
+obj-$(CONFIG_SYSLINK_PROC4430)  += dsp/syslink/procmgr/proc4430/
diff --git a/drivers/dsp/syslink/Kconfig b/drivers/dsp/syslink/Kconfig
new file mode 100644
index 000000000000..08964039a4a3
--- /dev/null
+++ b/drivers/dsp/syslink/Kconfig
@@ -0,0 +1,67 @@
+
+
+menuconfig Sys_Link
+	bool "Sys_Link"
+	default y
+
+if Sys_Link
+
+config  SYSLINK_PROC
+        tristate "Syslink ProcMgr"
+        default y
+        select OMAP_IOMMU
+	help
+           Syslink Proc manager
+
+config  SYSLINK_PROC4430
+        tristate "Proc 4430"
+        depends on SYSLINK_PROC
+        default y
+        help
+           Ducati Proc implementation
+
+config  DUCATI_BASEIMAGE_PHYS_ADDR
+	hex "Physical Address where the Ducati is loaded"
+	depends on SYSLINK_PROC4430
+	default 0x9CF00000
+	help
+	  Specify the physical address where the Ducati image will be
+	  loaded.
+
+config  SYSLINK_DUCATI_PM
+        tristate "DUCATI POWER MANAGEMENT"
+        depends on SYSLINK_PROC && SYSLINK_PROC4430
+        default y
+        help
+           Ducati Power Management Implementation
+
+config MPU_SYSLINK_PLATFORM
+        tristate "Syslink Platform Module"
+        default y
+        help
+          Syslink Platform Module
+
+config MPU_SYSLINK_IPC
+        tristate "Syslink IPC Module"
+        depends on SYSLINK_PROC4430
+        default y
+        select OMAP_MBOX_FWK
+        select OMAP_REMOTE_PROC
+        help
+          Syslink IPC Module (includes Notify)
+
+config SYSLINK_USE_SYSMGR
+        bool "Enable SYS MGR setup"
+        depends on MPU_SYSLINK_IPC && SYSLINK_PROC
+        default y
+        help
+          This is the experimental option to enable SYS manager setup
+
+ config OMAP_IOMMU_DEBUG_MODULE
+        bool "IOMMU debugging"
+	default y
+endif
+
+
+
+
diff --git a/drivers/dsp/syslink/ipu_pm/ipu_pm.c b/drivers/dsp/syslink/ipu_pm/ipu_pm.c
new file mode 100644
index 000000000000..b36e4e721045
--- /dev/null
+++ b/drivers/dsp/syslink/ipu_pm/ipu_pm.c
@@ -0,0 +1,1463 @@
+/*
+ * ipu_pm.c
+ *
+ * IPU Power Management support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <generated/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/uaccess.h>
+#include <linux/platform_device.h>
+#include <syslink/notify.h>
+#include <syslink/notify_driver.h>
+#include <syslink/notifydefs.h>
+#include <syslink/notify_driverdefs.h>
+#include <syslink/notify_ducatidriver.h>
+
+/* Power Management headers */
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/dma.h>
+#include <plat/dmtimer.h>
+#include <plat/clock.h>
+#include <plat/i2c.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/semaphore.h>
+#include <linux/jiffies.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/i2c/twl.h>
+
+/* Module headers */
+#include "ipu_pm.h"
+
+/** ============================================================================
+ *  Macros and types
+ *  ============================================================================
+ */
+#define A9 3
+#define SYS_M3 2
+#define APP_M3 1
+#define TESLA 0
+
+#define LINE_ID 0
+#define NUM_SELF_PROC 2
+#define PM_VERSION 0x0100
+
+/* FIXME:Values needed for the regulator hack */
+#define VAUX3_CFG_STATE 0x8E
+#define VAUX3_CFG_VOLTAGE 0x8F
+#define VCXIO_CFG_TRANS 0x91
+#define VMMC_CFG_VOLTAGE 0x9B
+#define CAM_2_ENABLE 0xE1
+#define CAM_2_DISABLE 0xE0
+
+/** ============================================================================
+ *  Forward declarations of internal functions
+ *  ============================================================================
+ */
+
+/* Function to get sdma channels from PRCM */
+static inline int ipu_pm_get_sdma_chan(int proc_id, unsigned rcb_num);
+
+/* Function to get gptimers from PRCM */
+static inline int ipu_pm_get_gptimer(int proc_id, unsigned rcb_num);
+
+/* Function to get i2c buses from PRCM */
+static inline int ipu_pm_get_i2c_bus(int proc_id, unsigned rcb_num);
+
+/* Function to get gpios from PRCM */
+static inline int ipu_pm_get_gpio(int proc_id, unsigned rcb_num);
+
+/* Function to get regulators from PRCM */
+static inline int ipu_pm_get_regulator(int proc_id, unsigned rcb_num);
+
+/* Function to release sdma channels to PRCM */
+static inline int ipu_pm_rel_sdma_chan(int proc_id, unsigned rcb_num);
+
+/* Function to release gptimers to PRCM */
+static inline int ipu_pm_rel_gptimer(int proc_id, unsigned rcb_num);
+
+/* Function to release i2c buses to PRCM */
+static inline int ipu_pm_rel_i2c_bus(int proc_id, unsigned rcb_num);
+
+/* Function to release gpios from PRCM */
+static inline int ipu_pm_rel_gpio(int proc_id, unsigned rcb_num);
+
+/* Function to release regulators to PRCM */
+static inline int ipu_pm_rel_regulator(int proc_id, unsigned rcb_num);
+
+/* Function to get ipu pm object */
+static inline struct ipu_pm_object *ipu_pm_get_handle(int proc_id);
+
+/** ============================================================================
+ *  Globals
+ *  ============================================================================
+ */
+
+static union message_slicer pm_msg;
+
+static int pm_action_type;
+static int pm_resource_type;
+static int pm_gptimer_num;
+static int pm_gpio_num;
+static int pm_i2c_bus_num;
+static int pm_sdmachan_num;
+static int pm_sdmachan_dummy;
+static int ch, ch_aux;
+static int pm_regulator_num;
+static int return_val;
+static u32 GPTIMER_USE_MASK = 0xFFFF;
+
+static int ipu_timer_list[NUM_IPU_TIMERS] = {
+	GP_TIMER_3,
+	GP_TIMER_4,
+	GP_TIMER_9,
+	GP_TIMER_11};
+
+static struct ipu_pm_object *pm_handle_appm3;
+static struct ipu_pm_object *pm_handle_sysm3;
+
+static struct ipu_pm_module_object ipu_pm_state = {
+	.def_cfg.reserved = 1,
+	.gate_handle = NULL
+} ;
+
+static struct ipu_pm_params pm_params = {
+	.pm_gpio_counter = 0,
+	.pm_gptimer_counter = 0,
+	.pm_i2c_bus_counter = 0,
+	.pm_sdmachan_counter = 0,
+	.pm_regulator_counter = 0,
+	.shared_addr = NULL,
+	.timeout = 10000,
+	.pm_num_events = NUMBER_PM_EVENTS,
+	.pm_resource_event = PM_RESOURCE,
+	.pm_notification_event = PM_NOTIFICATION,
+	.proc_id = A9,
+	.remote_proc_id = -1,
+	.line_id = 0
+} ;
+
+/*
+  Function for PM resources Callback
+ *
+ */
+void ipu_pm_callback(u16 proc_id, u16 line_id, u32 event_id,
+					uint *arg, u32 payload)
+{
+	struct rcb_block *rcb_p;
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return;
+
+	/* Get the payload */
+	pm_msg.whole = payload;
+	/* Get pointer to the proper RCB */
+	rcb_p = (struct rcb_block *)
+		&handle->rcb_table->rcb[pm_msg.fields.rcb_num];
+
+	/* Get the type of resource and the actions required */
+	pm_action_type = rcb_p->msg_type;
+	pm_resource_type = rcb_p->sub_type;
+
+	/* Request the resource to PRCM */
+	switch (pm_resource_type) {
+	case SDMA:
+		if (pm_action_type == PM_REQUEST_RESOURCE) {
+			return_val =
+				ipu_pm_get_sdma_chan(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* Update payload with the failure msg */
+				pm_msg.fields.msg_type = PM_REQUEST_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		if (pm_action_type == PM_RELEASE_RESOURCE) {
+			return_val =
+				ipu_pm_rel_sdma_chan(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* Update payload with the failure msg */
+				pm_msg.fields.msg_type = PM_RELEASE_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		break;
+	case GP_TIMER:
+		if (pm_action_type == PM_REQUEST_RESOURCE) {
+			/* GP Timers 3,4,9 or 11 for Ducati M3 */
+			return_val = ipu_pm_get_gptimer(proc_id,
+							pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* Update the payload with the failure msg */
+				pm_msg.fields.msg_type = PM_REQUEST_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		if (pm_action_type == PM_RELEASE_RESOURCE) {
+			return_val =
+				ipu_pm_rel_gptimer(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* Update the payload with the failure msg */
+				pm_msg.fields.msg_type = PM_RELEASE_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		break;
+	case GP_IO:
+		if (pm_action_type == PM_REQUEST_RESOURCE) {
+			return_val =
+				ipu_pm_get_gpio(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* Update the payload with the failure msg */
+				pm_msg.fields.msg_type = PM_REQUEST_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		if (pm_action_type == PM_RELEASE_RESOURCE) {
+			return_val =
+				ipu_pm_rel_gpio(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* Update the payload with the failure msg */
+				pm_msg.fields.msg_type = PM_RELEASE_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		break;
+	case I2C:
+		if (pm_action_type == PM_REQUEST_RESOURCE) {
+			return_val =
+				ipu_pm_get_i2c_bus(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* i2c bus/clock for Ducati unavailable */
+				/* Update the payload with the failure msg */
+				pm_msg.fields.msg_type = PM_REQUEST_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		if (pm_action_type == PM_RELEASE_RESOURCE) {
+			return_val =
+				ipu_pm_rel_i2c_bus(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* i2c bus/clock for Ducati unavailable */
+				/* Update the payload with the failure msg */
+				pm_msg.fields.msg_type = PM_RELEASE_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		break;
+	case REGULATOR:
+		if (pm_action_type == PM_REQUEST_RESOURCE) {
+			return_val =
+				ipu_pm_get_regulator(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* Regulator unavailable */
+				/* Update the payload with the failure msg */
+				pm_msg.fields.msg_type = PM_REQUEST_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		if (pm_action_type == PM_RELEASE_RESOURCE) {
+			return_val =
+				ipu_pm_rel_regulator(proc_id,
+					pm_msg.fields.rcb_num);
+			if (return_val != PM_SUCCESS) {
+				/* Update the payload with the failure msg */
+				pm_msg.fields.msg_type = PM_RELEASE_FAIL;
+				pm_msg.fields.parm = return_val;
+				break;
+			}
+			break;
+		}
+		break;
+	case DUCATI:
+	case IVA_HD:
+	case ISS:
+	default:
+		printk(KERN_ERR "Unsupported resource\n");
+		/* Report error to Remote processor */
+		pm_msg.fields.msg_type = PM_FAILURE,
+		pm_msg.fields.parm = PM_UNSUPPORTED;
+		break;
+	}
+
+	/* Update the payload with the reply msg */
+	pm_msg.fields.reply_flag = true;
+
+	/* Update the payload before send */
+	payload = pm_msg.whole;
+
+	/* send the ACK to DUCATI*/
+	return_val = notify_send_event(
+				params->remote_proc_id,/*DUCATI_PROC*/
+				params->line_id,
+				params->pm_resource_event | \
+					(NOTIFY_SYSTEMKEY << 16),
+				payload,
+				true);
+	if (return_val < 0)
+		printk(KERN_ERR "ERROR SENDING PM EVENT\n");
+}
+EXPORT_SYMBOL(ipu_pm_callback);
+
+/*
+  Function for PM notifications Callback
+ *
+ */
+void ipu_pm_notify_callback(u16 proc_id, u16 line_id, u32 event_id,
+					uint *arg, u32 payload)
+{
+	/**
+	 * Post semaphore based in eventType (payload);
+	 * IPU has alreay finished the process for the
+	 * notification
+	 */
+	/* Get the payload */
+	struct ipu_pm_object *handle;
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return;
+
+	pm_msg.whole = payload;
+	switch (pm_msg.fields.msg_subtype) {
+	case PM_SUSPEND:
+		up(&handle->pm_event[PM_SUSPEND].sem_handle);
+		break;
+	case PM_RESUME:
+		up(&handle->pm_event[PM_RESUME].sem_handle);
+		break;
+	case PM_OTHER:
+		up(&handle->pm_event[PM_OTHER].sem_handle);
+		break;
+	}
+}
+EXPORT_SYMBOL(ipu_pm_notify_callback);
+
+/*
+  Function for send PM Notifications
+ *
+ */
+int ipu_pm_notifications(enum pm_event_type event_type)
+{
+	/**
+	 * Function called by linux driver
+	 * Recieves evenType: Suspend, Resume, others...
+	 * Send event to Ducati
+	 * Pend semaphore based in event_type (payload)
+	 * Return ACK to caller
+	 */
+
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	int pm_ack = 0;
+	int i;
+	int proc_id;
+
+	/*get the handle to proper ipu pm object */
+	for (i = 0; i < NUM_SELF_PROC; i++) {
+		proc_id = i + 1;
+		handle = ipu_pm_get_handle(proc_id);
+		if (handle == NULL)
+			continue;
+		params = handle->params;
+		if (params == NULL)
+			continue;
+		switch (event_type) {
+		case PM_SUSPEND:
+			pm_msg.fields.msg_type = PM_NOTIFICATIONS;
+			pm_msg.fields.msg_subtype = PM_SUSPEND;
+			pm_msg.fields.parm = PM_SUCCESS;
+			/* send the request to IPU*/
+			return_val = notify_send_event(
+					params->remote_proc_id,
+					params->line_id,
+					params->pm_notification_event | \
+						(NOTIFY_SYSTEMKEY << 16),
+					(unsigned int)pm_msg.whole,
+					true);
+			if (return_val < 0)
+				printk(KERN_ERR "ERROR SENDING PM EVENT\n");
+			/* wait until event from IPU (ipu_pm_notify_callback)*/
+			return_val = down_timeout
+					(&handle->pm_event[PM_SUSPEND]
+					.sem_handle,
+					msecs_to_jiffies(params->timeout));
+			if (WARN_ON((return_val < 0) ||
+					(pm_msg.fields.parm ==
+						PM_NOTIFICATIONS_FAIL))) {
+				printk(KERN_ERR "Error Suspend\n");
+				pm_ack = EBUSY;
+			}
+			break;
+		case PM_RESUME:
+			pm_msg.fields.msg_type = PM_NOTIFICATIONS;
+			pm_msg.fields.msg_subtype = PM_RESUME;
+			pm_msg.fields.parm = PM_SUCCESS;
+			/* send the request to IPU*/
+			return_val = notify_send_event(
+					params->remote_proc_id,
+					params->line_id,
+					params->pm_notification_event | \
+						(NOTIFY_SYSTEMKEY << 16),
+					(unsigned int)pm_msg.whole,
+					true);
+			if (return_val < 0)
+				printk(KERN_ERR "ERROR SENDING PM EVENT\n");
+			/* wait until event from IPU (ipu_pm_notify_callback)*/
+			return_val = down_timeout
+					(&handle->pm_event[PM_RESUME]
+					.sem_handle,
+					msecs_to_jiffies(params->timeout));
+			if (WARN_ON((return_val < 0) ||
+					(pm_msg.fields.parm ==
+						PM_NOTIFICATIONS_FAIL))) {
+				printk(KERN_ERR "Error Resume\n");
+				pm_ack = EBUSY;
+			}
+			break;
+		case PM_OTHER:
+			pm_msg.fields.msg_type = PM_NOTIFICATIONS;
+			pm_msg.fields.msg_subtype = PM_OTHER;
+			pm_msg.fields.parm = PM_SUCCESS;
+			/* send the request to IPU*/
+			return_val = notify_send_event(
+					params->remote_proc_id,
+					params->line_id,
+					params->pm_notification_event | \
+						(NOTIFY_SYSTEMKEY << 16),
+					(unsigned int)pm_msg.whole,
+					true);
+			if (return_val < 0)
+				printk(KERN_ERR "ERROR SENDING PM EVENT\n");
+			/* wait until event from IPU (ipu_pm_notify_callback)*/
+			return_val = down_timeout
+					(&handle->pm_event[PM_OTHER]
+					.sem_handle,
+					msecs_to_jiffies(params->timeout));
+			if (WARN_ON((return_val < 0) ||
+					(pm_msg.fields.parm ==
+						PM_NOTIFICATIONS_FAIL))) {
+				printk(KERN_ERR "Error Other\n");
+				pm_ack = EBUSY;
+			}
+			break;
+		}
+	}
+	return pm_ack;
+}
+EXPORT_SYMBOL(ipu_pm_notifications);
+
+/*
+  Function to get sdma channels from PRCM
+ *
+ */
+static inline int ipu_pm_get_sdma_chan(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+	/* Get number of channels from RCB */
+	pm_sdmachan_num = rcb_p->num_chan;
+	if (WARN_ON((pm_sdmachan_num <= 0) ||
+			(pm_sdmachan_num > SDMA_CHANNELS_MAX)))
+		return PM_INVAL_NUM_CHANNELS;
+
+	/* Request resource using PRCM API */
+	for (ch = 0; ch < pm_sdmachan_num; ch++) {
+		return_val = omap_request_dma(proc_id,
+			"ducati-ss",
+			NULL,
+			NULL,
+			&pm_sdmachan_dummy);
+		if (return_val == 0) {
+			params->pm_sdmachan_counter++;
+			rcb_p->channels[ch] = (unsigned char)pm_sdmachan_dummy;
+		} else
+			goto clean_sdma;
+	}
+	return PM_SUCCESS;
+clean_sdma:
+	/*failure, need to free the chanels*/
+	for (ch_aux = 0; ch_aux < ch; ch_aux++) {
+		pm_sdmachan_dummy = (int)rcb_p->channels[ch_aux];
+		omap_free_dma(pm_sdmachan_dummy);
+		params->pm_sdmachan_counter--;
+	}
+	return PM_INSUFFICIENT_CHANNELS;
+}
+
+/*
+  Function to get gptimers from PRCM
+ *
+ */
+static inline int ipu_pm_get_gptimer(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+	struct omap_dm_timer *p_gpt = NULL;
+	int pm_gp_num;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+	/* Request resource using PRCM API */
+	for (pm_gp_num = 0; pm_gp_num < NUM_IPU_TIMERS; pm_gp_num++) {
+		if (GPTIMER_USE_MASK & (1 << ipu_timer_list[pm_gp_num])) {
+			p_gpt = omap_dm_timer_request_specific
+				(ipu_timer_list[pm_gp_num]);
+		} else
+			continue;
+		if (p_gpt != NULL) {
+			/* Clear the bit in the usage mask */
+			GPTIMER_USE_MASK &= ~(1 << ipu_timer_list[pm_gp_num]);
+			break;
+		}
+	}
+	if (p_gpt == NULL)
+		return PM_NO_GPTIMER;
+	else {
+		/* Store the gptimer number and base address */
+		rcb_p->fill9 = ipu_timer_list[pm_gp_num];
+		rcb_p->mod_base_addr = (unsigned)p_gpt;
+		params->pm_gptimer_counter++;
+		return PM_SUCCESS;
+	}
+}
+
+/*
+  Function to get an i2c bus
+ *
+ */
+static inline int ipu_pm_get_i2c_bus(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+	struct clk *p_i2c_clk;
+	int i2c_clk_status;
+	char i2c_name[10];
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+
+	pm_i2c_bus_num = rcb_p->fill9;
+	if (WARN_ON((pm_i2c_bus_num < I2C_BUS_MIN) ||
+			(pm_i2c_bus_num > I2C_BUS_MAX)))
+		return PM_INVAL_NUM_I2C;
+
+	/* building the name for i2c_clk */
+	sprintf(i2c_name, "i2c%d_fck", pm_i2c_bus_num);
+
+	/* Request resource using PRCM API */
+	p_i2c_clk = omap_clk_get_by_name(i2c_name);
+	if (p_i2c_clk == 0)
+		return PM_NO_I2C;
+	i2c_clk_status = clk_enable(p_i2c_clk);
+	if (i2c_clk_status != 0)
+		return PM_NO_I2C;
+	rcb_p->mod_base_addr = (unsigned)p_i2c_clk;
+	params->pm_i2c_bus_counter++;
+
+	return PM_SUCCESS;
+}
+
+/*
+  Function to get gpio
+ *
+ */
+static inline int ipu_pm_get_gpio(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+
+	pm_gpio_num = rcb_p->fill9;
+	return_val = gpio_request(pm_gpio_num , "ducati-ss");
+	if (return_val != 0)
+		return PM_NO_GPIO;
+	params->pm_gpio_counter++;
+
+	return PM_SUCCESS;
+}
+
+/*
+  Function to get a regulator
+ *
+ */
+static inline int ipu_pm_get_regulator(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+	struct regulator *p_regulator = NULL;
+	u8 pm_reg_voltage_index;
+	s32 retval = 0;
+	/*
+	  There are 5 bits to set the voltage, to calculate the max_error
+	 *(steps / 2) and we add this value to the
+	 *value shared in rcb->data[0]->(minVoltage) to provide the nearest
+	 *value to the minVoltage.
+	 *Fixed_voltage -> minVoltage + max_error
+	 */
+	u32 fixed_voltage;
+	u32 max_error = (100000 / 2);
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+
+	pm_regulator_num = rcb_p->fill9;
+	if (WARN_ON((pm_regulator_num < REGULATOR_MIN) ||
+			(pm_regulator_num > REGULATOR_MAX)))
+		return PM_INVAL_REGULATOR;
+
+	/*
+	  FIXME:Only providing 1 regulator, if more are provided
+	 *	this check is not valid.
+	 */
+	if (WARN_ON(params->pm_regulator_counter > 0))
+		return PM_INVAL_REGULATOR;
+
+	/*
+	  Fix the voltage to give the nearest value to
+	 *the minimum by adding the maximum error.
+	 *rcb_p->data[0] contains the minimum voltage
+	 *rcb_p->data[1] contains the maximum voltage
+	 */
+	fixed_voltage = rcb_p->data[0] + max_error;
+	/* 5 bits to represent the voltage */
+	pm_reg_voltage_index = ((fixed_voltage - 1000000)/100000)+1;
+
+	/*
+	  FIXME:Disable/set_voltage regulator with a hack, once the
+	 *	regulator API are fully working this will be removed.
+	 *	This is only for Phoenix ES1.0
+	 */
+	pm_reg_voltage_index |= 0x80;
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x00, VMMC_CFG_VOLTAGE);
+	if (retval)
+		goto exit;
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x80, VCXIO_CFG_TRANS);
+	if (retval)
+		goto exit;
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID0, CAM_2_ENABLE,
+							VAUX3_CFG_STATE);
+	if (retval)
+		goto exit;
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID0, pm_reg_voltage_index,
+							VAUX3_CFG_VOLTAGE);
+	if (retval)
+		goto exit;
+
+	/*
+	  FIXME:The real value will be stored once the regulator API
+	 *	are fully working.
+	 */
+	rcb_p->mod_base_addr = (unsigned)p_regulator;
+	params->pm_regulator_counter++;
+
+	return PM_SUCCESS;
+exit:
+	return PM_INVAL_REGULATOR;
+}
+
+/*
+  Function to release sdma channels to PRCM
+ *
+ */
+static inline int ipu_pm_rel_sdma_chan(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+
+	/* Release resource using PRCM API */
+	pm_sdmachan_num = rcb_p->num_chan;
+	for (ch = 0; ch < pm_sdmachan_num; ch++) {
+		pm_sdmachan_dummy = (int)rcb_p->channels[ch];
+		omap_free_dma(pm_sdmachan_dummy);
+		params->pm_sdmachan_counter--;
+	}
+	return PM_SUCCESS;
+}
+
+/*
+  Function to release gptimer to PRCM
+ *
+ */
+static inline int ipu_pm_rel_gptimer(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+	struct omap_dm_timer *p_gpt;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+
+	p_gpt = (struct omap_dm_timer *)rcb_p->mod_base_addr;
+	pm_gptimer_num = rcb_p->fill9;
+
+	/* Set the usage mask for reuse */
+	GPTIMER_USE_MASK |= (1 << pm_gptimer_num);
+
+	/* Release resource using PRCM API */
+	if (p_gpt != NULL)
+		omap_dm_timer_free(p_gpt);
+	rcb_p->mod_base_addr = 0;
+	params->pm_gptimer_counter--;
+	return PM_SUCCESS;
+}
+
+/*
+  Function to release an i2c bus
+ *
+ */
+static inline int ipu_pm_rel_i2c_bus(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+	struct clk *p_i2c_clk;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+	p_i2c_clk = (struct clk *)rcb_p->mod_base_addr;
+
+	/* Release resource using PRCM API */
+	clk_disable(p_i2c_clk);
+	rcb_p->mod_base_addr = 0;
+	params->pm_i2c_bus_counter--;
+
+	return PM_SUCCESS;
+}
+
+/*
+  Function to release gpio
+ *
+ */
+static inline int ipu_pm_rel_gpio(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+
+	pm_gpio_num = rcb_p->fill9;
+	gpio_free(pm_gpio_num);
+	params->pm_gpio_counter--;
+
+	return PM_SUCCESS;
+}
+
+/*
+  Function to release a regulator
+ *
+ */
+static inline int ipu_pm_rel_regulator(int proc_id, unsigned rcb_num)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	struct rcb_block *rcb_p;
+	struct regulator *p_regulator = NULL;
+	s32 retval = 0;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(proc_id);
+	if (WARN_ON(unlikely(handle == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL)))
+		return PM_NOT_INSTANTIATED;
+
+	/* Get pointer to the proper RCB */
+	if (WARN_ON((rcb_num < RCB_MIN) || (rcb_num > RCB_MAX)))
+		return PM_INVAL_RCB_NUM;
+	rcb_p = (struct rcb_block *)&handle->rcb_table->rcb[rcb_num];
+	p_regulator = (struct regulator *)rcb_p->mod_base_addr;
+
+	/* Release resource using PRCM API */
+	/*
+	  FIXME:Disable/voltage the regulator with a hack, once the regulator
+	 *	API are fully working this will be removed.
+	 * Add a check for twl write
+	 */
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x00, VMMC_CFG_VOLTAGE);
+	if (retval)
+		goto exit;
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x80, VCXIO_CFG_TRANS);
+	if (retval)
+		goto exit;
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID0, 0x00, VAUX3_CFG_VOLTAGE);
+	if (retval)
+		goto exit;
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID0, CAM_2_DISABLE,
+							VAUX3_CFG_STATE);
+	if (retval)
+		goto exit;
+	retval = twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x40, VCXIO_CFG_TRANS);
+	if (retval)
+		goto exit;
+
+	rcb_p->mod_base_addr = 0;
+	params->pm_regulator_counter--;
+
+	return PM_SUCCESS;
+exit:
+	return PM_INVAL_REGULATOR;
+}
+
+/*
+  Function to set init parameters
+ *
+ */
+void ipu_pm_params_init(struct ipu_pm_params *params)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	memcpy(params, &(pm_params), sizeof(struct ipu_pm_params));
+	return;
+exit:
+	printk(KERN_ERR "ipu_pm_params_init failed status(0x%x)\n", retval);
+}
+EXPORT_SYMBOL(ipu_pm_params_init);
+
+/*
+  Function to calculate ipu_pm mem required
+ *
+ */
+int ipu_pm_mem_req(const struct ipu_pm_params *params)
+{
+	/* Memory required for ipu pm module */
+	/* FIXME: Maybe more than this is needed */
+	return sizeof(struct sms);
+}
+EXPORT_SYMBOL(ipu_pm_mem_req);
+
+/*
+  Function to register events
+  This function will register the events needed for ipu_pm
+  the events reserved for power management are 2 and 3
+  both sysm3 and appm3 will use the same events.
+ */
+int ipu_pm_init_transport(struct ipu_pm_object *handle)
+{
+	s32 status = 0;
+	struct ipu_pm_params *params;
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = -EINVAL;
+		goto pm_register_fail;
+	}
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL))) {
+		status = -EINVAL;
+		goto pm_register_fail;
+	}
+
+	status = notify_register_event(
+		params->remote_proc_id,
+		params->line_id,
+		params->pm_resource_event | \
+				(NOTIFY_SYSTEMKEY << 16),
+		(notify_fn_notify_cbck)ipu_pm_callback,
+		(void *)NULL);
+	if (status < 0)
+		goto pm_register_fail;
+
+	status = notify_register_event(
+		params->remote_proc_id,
+		params->line_id,
+		params->pm_notification_event | \
+				(NOTIFY_SYSTEMKEY << 16),
+		(notify_fn_notify_cbck)ipu_pm_notify_callback,
+		(void *)NULL);
+
+	if (status < 0) {
+		status = notify_unregister_event(
+		params->remote_proc_id,
+		params->line_id,
+		params->pm_resource_event | \
+				(NOTIFY_SYSTEMKEY << 16),
+		(notify_fn_notify_cbck)ipu_pm_callback,
+		(void *)NULL);
+		if (status < 0)
+			printk(KERN_ERR "ERROR UNREGISTERING PM EVENT\n");
+		goto pm_register_fail;
+	}
+	return status;
+
+pm_register_fail:
+	printk(KERN_ERR "pm register events failed status(0x%x)", status);
+	return status;
+}
+
+/*
+  Function to create ipu pm object
+ *
+ */
+struct ipu_pm_object *ipu_pm_create(const struct ipu_pm_params *params)
+{
+	int i;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (params->remote_proc_id == SYS_M3) {
+		pm_handle_sysm3 = kmalloc(sizeof(struct ipu_pm_object),
+						GFP_ATOMIC);
+
+		if (WARN_ON(unlikely(pm_handle_sysm3 == NULL))) {
+			retval = -EINVAL;
+			goto exit;
+		}
+
+		pm_handle_sysm3->rcb_table = (struct sms *)params->shared_addr;
+
+		pm_handle_sysm3->pm_event = kzalloc(sizeof(struct pm_event)
+					* params->pm_num_events, GFP_KERNEL);
+
+		if (WARN_ON(unlikely(pm_handle_sysm3->pm_event == NULL))) {
+			retval = -EINVAL;
+			kfree(pm_handle_sysm3);
+			goto exit;
+		}
+
+		/* Each event has it own sem */
+		for (i = 0; i < params->pm_num_events; i++) {
+			sema_init(&pm_handle_sysm3->pm_event[i].sem_handle, 0);
+			pm_handle_sysm3->pm_event[i].event_type = i;
+		}
+
+		pm_handle_sysm3->params = kzalloc(sizeof(struct ipu_pm_params)
+							, GFP_KERNEL);
+
+		if (WARN_ON(unlikely(pm_handle_sysm3->params == NULL))) {
+			retval = -EINVAL;
+			kfree(pm_handle_sysm3->pm_event);
+			kfree(pm_handle_sysm3);
+			goto exit;
+		}
+
+		memcpy(pm_handle_sysm3->params, params,
+			sizeof(struct ipu_pm_params));
+
+		/* Check the SW version on both sides */
+		if (WARN_ON(pm_handle_sysm3->rcb_table->pm_version !=
+						PM_VERSION))
+			printk(KERN_WARNING "Mismatch in PM version Host:0x%x "
+					"Remote:0x%x", PM_VERSION,
+					pm_handle_sysm3->rcb_table->pm_version);
+
+		return pm_handle_sysm3;
+	} else {/* remote_proc_id == APP_M3 */
+		pm_handle_appm3 = kmalloc(sizeof(struct ipu_pm_object),
+						GFP_ATOMIC);
+
+		if (WARN_ON(unlikely(pm_handle_appm3 == NULL))) {
+			retval = -EINVAL;
+			goto exit;
+		}
+
+		pm_handle_appm3->rcb_table = (struct sms *)params->shared_addr;
+
+		pm_handle_appm3->pm_event = kzalloc(sizeof(struct pm_event)
+					* params->pm_num_events, GFP_KERNEL);
+
+		if (WARN_ON(unlikely(pm_handle_appm3->pm_event == NULL))) {
+			retval = -EINVAL;
+			kfree(pm_handle_appm3);
+			goto exit;
+		}
+
+		/* Each event has it own sem */
+		for (i = 0; i < params->pm_num_events; i++) {
+			sema_init(&pm_handle_appm3->pm_event[i].sem_handle, 0);
+			pm_handle_appm3->pm_event[i].event_type = i;
+		}
+
+		pm_handle_appm3->params = kzalloc(sizeof(struct ipu_pm_params)
+						, GFP_KERNEL);
+
+		if (WARN_ON(unlikely(pm_handle_appm3->params == NULL))) {
+			retval = -EINVAL;
+			kfree(pm_handle_appm3->pm_event);
+			kfree(pm_handle_appm3);
+			goto exit;
+		}
+
+		memcpy(pm_handle_appm3->params, params,
+			sizeof(struct ipu_pm_params));
+
+		/* Check the SW version on both sides */
+		if (WARN_ON(pm_handle_appm3->rcb_table->pm_version !=
+						PM_VERSION))
+			printk(KERN_WARNING "Mismatch in PM version Host:0x%x "
+					"Remote:0x%x", PM_VERSION,
+					pm_handle_appm3->rcb_table->pm_version);
+
+		return pm_handle_appm3;
+	}
+
+exit:
+	printk(KERN_ERR "ipu_pm_create failed! "
+		"status = 0x%x\n", retval);
+	return NULL;
+}
+
+/*
+  Function to delete ipu pm object
+ *
+ */
+void ipu_pm_delete(struct ipu_pm_object *handle)
+{
+	s32 retval = 0;
+	struct ipu_pm_params *params;
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	/* Release the shared RCB */
+	handle->rcb_table = NULL;
+
+	kfree(handle->pm_event);
+	if (params->remote_proc_id == SYS_M3)
+		pm_handle_sysm3 = NULL;
+	else
+		pm_handle_appm3 = NULL;
+	kfree(handle->params);
+	kfree(handle);
+	return;
+exit:
+	printk(KERN_ERR "ipu_pm_delete is already NULL "
+		"status = 0x%x\n", retval);
+}
+
+/*
+  Function to get ipu pm object
+ *
+ */
+static inline struct ipu_pm_object *ipu_pm_get_handle(int proc_id)
+{
+	if (proc_id == SYS_M3)
+		return pm_handle_sysm3;
+	else if (proc_id == APP_M3)
+		return pm_handle_appm3;
+	else
+		return NULL;
+}
+
+/*
+  Get the default configuration for the ipu_pm module.
+  needed in ipu_pm_setup.
+ */
+void ipu_pm_get_config(struct ipu_pm_config *cfg)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(cfg == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (atomic_cmpmask_and_lt(&(ipu_pm_state.ref_count),
+			IPU_PM_MAKE_MAGICSTAMP(0),
+			IPU_PM_MAKE_MAGICSTAMP(1)) == true)
+		memcpy(cfg, &ipu_pm_state.def_cfg,
+			sizeof(struct ipu_pm_config));
+	else
+		memcpy(cfg, &ipu_pm_state.cfg, sizeof(struct ipu_pm_config));
+	return;
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "ipu_pm_get_config failed! status = 0x%x",
+			retval);
+	}
+	return;
+}
+EXPORT_SYMBOL(ipu_pm_get_config);
+
+/*
+  Function to setup ipu pm object
+  This function is called in platform_setup()
+  TODO
+  This function will load the default configuration for ipu_pm
+  in this function we can decide what is going to be controled
+  by ipu_pm (DVFS, NOTIFICATIONS, ...) this configuration can
+  can be changed on run-time.
+ */
+int ipu_pm_setup(struct ipu_pm_config *cfg)
+{
+	struct ipu_pm_config tmp_cfg;
+	s32 retval = 0;
+	struct mutex *lock = NULL;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of refCount variable.
+	*/
+	atomic_cmpmask_and_set(&ipu_pm_state.ref_count,
+				IPU_PM_MAKE_MAGICSTAMP(0),
+				IPU_PM_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&ipu_pm_state.ref_count)
+				!= IPU_PM_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	if (cfg == NULL) {
+		ipu_pm_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	/* Create a default gate handle for local module protection */
+	lock = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (lock == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+	mutex_init(lock);
+	ipu_pm_state.gate_handle = lock;
+
+	/* No proc attached yet */
+	pm_handle_appm3 = NULL;
+	pm_handle_sysm3 = NULL;
+
+	memcpy(&ipu_pm_state.cfg, cfg, sizeof(struct ipu_pm_config));
+	ipu_pm_state.is_setup = true;
+	return retval;
+
+exit:
+	printk(KERN_ERR "ipu_pm_setup failed! retval = 0x%x", retval);
+	return retval;
+}
+EXPORT_SYMBOL(ipu_pm_setup);
+
+/*
+  Function to attach ipu pm object
+  This function is called in ipc_attach()
+  TODO
+  This function will create the object based on the remoteproc id
+  and save the handle.
+  It is also recieving the shared address pointer to use in rcb
+ */
+int ipu_pm_attach(u16 remote_proc_id, void *shared_addr)
+{
+	struct ipu_pm_params params;
+	struct ipu_pm_object *handle;
+	s32 retval = 0;
+
+	ipu_pm_params_init(&params);
+	params.remote_proc_id = remote_proc_id;
+	params.shared_addr = (void *)shared_addr;
+	params.line_id = LINE_ID;
+	params.shared_addr_size = ipu_pm_mem_req(NULL);
+
+	handle = ipu_pm_create(&params);
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	retval = ipu_pm_init_transport(handle);
+
+	if (retval < 0)
+		goto exit;
+
+	return retval;
+exit:
+	printk(KERN_ERR "ipu_pm_attach failed! retval = 0x%x", retval);
+	return retval;
+}
+EXPORT_SYMBOL(ipu_pm_attach);
+
+/*
+  Function to deattach ipu pm object
+  This function is called in ipc_deattach()
+  TODO
+  This function will delete the object based on the remoteproc id
+  and save the handle.
+ */
+int ipu_pm_detach(u16 remote_proc_id)
+{
+	struct ipu_pm_object *handle;
+	struct ipu_pm_params *params;
+	s32 retval = 0;
+
+	/* get the handle to proper ipu pm object */
+	handle = ipu_pm_get_handle(remote_proc_id);
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	params = handle->params;
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	/* unregister the events used for ipu_pm */
+	retval = notify_unregister_event(
+		params->remote_proc_id,
+		params->line_id,
+		params->pm_resource_event | (NOTIFY_SYSTEMKEY << 16),
+		(notify_fn_notify_cbck)ipu_pm_callback,
+		(void *)NULL);
+	if (retval < 0) {
+		printk(KERN_ERR "ERROR UNREGISTERING PM EVENT\n");
+		goto exit;
+	}
+	retval = notify_unregister_event(
+		params->remote_proc_id,
+		params->line_id,
+		params->pm_notification_event | (NOTIFY_SYSTEMKEY << 16),
+		(notify_fn_notify_cbck)ipu_pm_notify_callback,
+		(void *)NULL);
+	if (retval < 0) {
+		printk(KERN_ERR "ERROR UNREGISTERING PM EVENT\n");
+		goto exit;
+	}
+
+	/* Deleting the handle based on remote_proc_id */
+	ipu_pm_delete(handle);
+	return retval;
+exit:
+	printk(KERN_ERR "ipu_pm_detach failed handle null retval 0x%x", retval);
+	return retval;
+}
+EXPORT_SYMBOL(ipu_pm_detach);
+
+/*
+  Function to destroy ipu_pm module
+  this function will destroy the shared region 1(?)
+  an all the other structs created to set the configuration
+ */
+int ipu_pm_destroy(void)
+{
+	s32 retval = 0;
+	struct mutex *lock = NULL;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&ipu_pm_state.ref_count,
+				IPU_PM_MAKE_MAGICSTAMP(0),
+				IPU_PM_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (!(atomic_dec_return(&ipu_pm_state.ref_count)
+					== IPU_PM_MAKE_MAGICSTAMP(0))) {
+		retval = 1;
+		goto exit;
+	}
+
+	if (WARN_ON(ipu_pm_state.gate_handle == NULL)) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(ipu_pm_state.gate_handle);
+	if (retval)
+		goto exit;
+
+	lock = ipu_pm_state.gate_handle;
+	ipu_pm_state.gate_handle = NULL;
+	mutex_unlock(lock);
+	kfree(lock);
+	return retval;
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "ipu_pm_destroy failed, retval: %x\n",
+			retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(ipu_pm_destroy);
diff --git a/drivers/dsp/syslink/ipu_pm/ipu_pm.h b/drivers/dsp/syslink/ipu_pm/ipu_pm.h
new file mode 100644
index 000000000000..6d1ab5d1c6ba
--- /dev/null
+++ b/drivers/dsp/syslink/ipu_pm/ipu_pm.h
@@ -0,0 +1,317 @@
+/*
+* ipu_pm.h
+*
+* Syslink IPU Power Managament support functions for TI OMAP processors.
+*
+* Copyright (C) 2009-2010 Texas Instruments, Inc.
+*
+* This package is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+*
+*  --------------------------------------------------------------------
+* | rcb_num                             |      |        |       |      |
+* | msg_type                            |      |        |       |      |
+* | sub_type                            |      |        |       |      |
+* | rqst_cpu                            |    1-|word    |       |      |
+* | extd_mem_flag                       |      |        |       |      |
+* | num_chan                            |      |        |       |      |
+* | fill9                               |      |        |       |      |
+* |-------------------------------------|    ------  4-words 4-words   |
+* | process_id                          |    1-word     |       |      |
+* |-------------------------------------|    ------     |       |      |
+* | sem_hnd                             |    1-word     |       |      |
+* |-------------------------------------|    ------     |       |      |
+* | mod_base_addr                       |    1-word     |       |      |
+* |-------------------------------------|    ------   -----   -----    |
+* | channels[0]  | data[0] | datax[0]   |      |        |       |      |
+* | channels[1]  |         |            |    1-word     |       |   RCB_SIZE
+* | channels[2]  |         |            |      |        |       |      =
+* | channels[3]  |         |            |      |        |       |    8WORDS
+* |--------------|---------|------------|    ------     |       |      |
+* | channels[4]  | data[0] | datax[1]   |      |        |       |      |
+* | channels[5]  |         |            |    1-word     |  RCB_SIZE-5  |
+* | channels[6]  |         |            |      |        |       |      |
+* | channels[7]  |         |            |      |     RCB_SIZE-4 |      |
+* |--------------|---------|------------|    ------     |       |      |
+* | channels[8]  | data[0] | datax[2]   |      |        |       |      |
+* | channels[9]  |         |            |    1-word     |       |      |
+* | channels[10] |         |            |      |        |       |      |
+* | channels[11] |         |            |      |        |       |      |
+* |--------------|---------|------------|    ------     |     -----    |
+* | channels[12] | data[0] |extd_mem_hnd|      |        |       |      |
+* | channels[13] |         |            |    1-word     |     1-word   |
+* | channels[14] |         |            |      |        |       |      |
+* | channels[15] |         |            |      |        |       |      |
+*  --------------------------------------------------------------------
+*
+*The Ducati Power Management sub-system uses a structure called RCB_struct or
+*just RCB to share information with the MPU about a particular resource involved
+*in the communication. The information stored in this structure is needed to get
+*attributes and other useful data about the resource.
+*The fisrt fields of the RCB resemble the Rcb message sent across the NotifyDver
+*It retains the rcb_num, msg_type and msg_subtype from the rcb message as its
+*first 3 fields. The rqst_cpu fields indicates which remote processor originates
+*the request/release petition. When a particular resource is requested, some of
+*its parameters should be specify.
+*For devices like Gptimer and GPIO, the most significant attribute its itemID.
+*This value should be placed in the "fill9" field of the Rcb sruct. This field
+*should be fill by the requester if asking for a particular resource or by the
+*receiver if the resource granted is other than the one asked.
+*
+*Other variables related with the resource are:
+*"sem_hnd" which storage the semaphore handle associated in the ducati side.
+*We are pending on this semaphore when asked for the resource and
+*posted when granted.
+*"mod_base_addr". It is the virtual base addres for the resource.
+*"process_id". It is the Task Id where the petition for the resource was called.
+*
+*The last 16 bytes of the structure could be interpreted in 3 different ways
+*according to the context.
+*1) For the case of the Rcb is for SDMA. The last 16 bytes correspond to a array
+*  of 16 channels[ ]. Each entry has the number of the SDMA channel granted.
+*  As many number of channels indicated in num_chan as many are meaningful
+*  in the channels[] array.
+*2) If the extd_mem_flag bit is NOT set the 16 last bytes are used as a data[]
+*  array. Each entry is 4bytes long so the maximum number of entries is 4.
+*3) If the extd_mem_flag bit is NOT set the 16 last bytes are used as an array
+*  datax[ ]  3 members Each entry  4bytes long  and one additional field of
+*  "extd_mem_hnd" which is a pointer to the continuation of this datax array
+*/
+
+#ifndef _IPU_PM_H_
+#define _IPU_PM_H_
+
+#include <linux/types.h>
+#include <linux/semaphore.h>
+
+/* Pm notify ducati driver */
+/* Suspend/resume/other... */
+#define NUMBER_PM_EVENTS 3
+
+#define RCB_SIZE 8
+
+#define DATA_MAX (RCB_SIZE - 4)
+#define DATAX_MAX (RCB_SIZE - 5)
+#define SDMA_CHANNELS_MAX 16
+#define I2C_BUS_MIN 1
+#define I2C_BUS_MAX 4
+#define REGULATOR_MIN 1
+#define REGULATOR_MAX 1
+
+#define GP_TIMER_3 3
+#define GP_TIMER_4 4
+#define GP_TIMER_9 9
+#define GP_TIMER_11 11
+#define NUM_IPU_TIMERS 4
+
+#define RCB_MIN 1
+#define RCB_MAX 33
+
+#define PM_RESOURCE 2
+#define PM_NOTIFICATION 3
+#define PM_SUCCESS 0
+#define PM_FAILURE -1
+#define PM_SHM_BASE_ADDR 0x9cff0000
+
+/*
+ *  IPU_PM_MODULEID
+ *  Unique module ID
+ */
+#define IPU_PM_MODULEID      (0x6A6A)
+
+/* Macro to make a correct module magic number with refCount */
+#define IPU_PM_MAKE_MAGICSTAMP(x) ((IPU_PM_MODULEID << 12u) | (x))
+
+enum pm_failure_codes{
+	PM_INSUFFICIENT_CHANNELS = 1,
+	PM_NO_GPTIMER,
+	PM_NO_GPIO,
+	PM_NO_I2C,
+	PM_NO_REGULATOR,
+	PM_REGULATOR_IN_USE,
+	PM_INVAL_RCB_NUM,
+	PM_INVAL_NUM_CHANNELS,
+	PM_INVAL_NUM_I2C,
+	PM_INVAL_REGULATOR,
+	PM_NOT_INSTANTIATED,
+	PM_UNSUPPORTED
+};
+
+enum pm_msgtype_codes{PM_NULLMSG,
+	PM_ACKNOWLEDGEMENT,
+	PM_REQUEST_RESOURCE,
+	PM_RELEASE_RESOURCE,
+	PM_REQUEST_FAIL,
+	PM_RELEASE_FAIL,
+	PM_REGULATOR_FAIL,
+	PM_NOTIFICATIONS,
+	PM_NOTIFICATIONS_FAIL,
+	PM_ENABLE_RESOURCE,
+	PM_WRITE_RESOURCE,
+	PM_READ_RESOURCE,
+	PM_DISABLE_RESOURCE
+};
+
+enum pm_regulator_action{PM_SET_VOLTAGE,
+	PM_SET_CURRENT,
+	PM_SET_MODE,
+	PM_GET_MODE,
+	PM_GET_CURRENT,
+	PM_GET_VOLTAGE
+};
+
+enum res_type{
+	DUCATI = 0,
+	IVA_HD,
+	ISS,
+	SDMA,
+	GP_TIMER,
+	GP_IO,
+	I2C,
+	REGULATOR
+};
+
+enum pm_event_type{PM_SUSPEND,
+	PM_RESUME,
+	PM_OTHER
+};
+
+struct rcb_message {
+	unsigned rcb_flag:1;
+	unsigned rcb_num:6;
+	unsigned reply_flag:1;
+	unsigned msg_type:4;
+	unsigned msg_subtype:4;
+	unsigned parm:16;
+};
+
+union message_slicer {
+	struct rcb_message fields;
+	int whole;
+};
+
+struct rcb_block {
+	unsigned rcb_num:6;
+	unsigned msg_type:4;
+	unsigned sub_type:4;
+	unsigned rqst_cpu:4;
+	unsigned extd_mem_flag:1;
+	unsigned num_chan:4;
+	unsigned fill9:9;
+
+	unsigned process_id;
+	unsigned *sem_hnd;
+	unsigned mod_base_addr;
+	union {
+		unsigned int data[DATA_MAX];
+		struct {
+			unsigned datax[DATAX_MAX];
+			unsigned extd_mem_hnd;
+		};
+		unsigned char channels[SDMA_CHANNELS_MAX];
+	};
+};
+
+struct sms {
+	unsigned rat;
+	unsigned pm_version;
+	struct rcb_block rcb[RCB_MAX];
+};
+
+struct pm_event {
+	enum pm_event_type event_type;
+	struct semaphore sem_handle;
+};
+
+struct ipu_pm_params {
+	int pm_gptimer_counter;
+	int pm_gpio_counter;
+	int pm_sdmachan_counter;
+	int pm_i2c_bus_counter;
+	int pm_regulator_counter;
+	int timeout;
+	void *shared_addr;
+	int shared_addr_size;
+	int pm_num_events;
+	int pm_resource_event;
+	int pm_notification_event;
+	int proc_id;
+	int remote_proc_id;
+	int line_id;
+	void *gate_mp;
+};
+
+/* This structure defines attributes for initialization of the ipu_pm module. */
+struct ipu_pm_config {
+	u32 reserved;
+};
+
+/* Defines the ipu_pm state object, which contains all the module
+ * specific information. */
+struct ipu_pm_module_object {
+	atomic_t ref_count;
+	/* Reference count */
+	struct ipu_pm_config cfg;
+	/* ipu_pm configuration structure */
+	struct ipu_pm_config def_cfg;
+	/* Default module configuration */
+	struct mutex *gate_handle;
+	/* Handle of gate to be used for local thread safety */
+	bool is_setup;
+	/* Indicates whether the ipu_pm module is setup. */
+};
+
+/* ipu_pm handle one for each proc SYSM3/APPM3 */
+struct ipu_pm_object {
+	struct sms *rcb_table;
+	struct pm_event *pm_event;
+	struct ipu_pm_params *params;
+};
+
+/* Function for PM resources Callback */
+void ipu_pm_callback(u16 proc_id, u16 line_id, u32 event_id,
+					uint *arg, u32 payload);
+
+/* Function for PM notifications Callback */
+void ipu_pm_notify_callback(u16 proc_id, u16 line_id, u32 event_id,
+					uint *arg, u32 payload);
+
+/* Function for send PM Notifications */
+int ipu_pm_notifications(enum pm_event_type event_type);
+
+/* Function to set init parameters */
+void ipu_pm_params_init(struct ipu_pm_params *params);
+
+/* Function to calculate ipu pm mem */
+int ipu_pm_mem_req(const struct ipu_pm_params *params);
+
+/* Function to config ipu_pm module */
+void ipu_pm_get_config(struct ipu_pm_config *cfg);
+
+/* Function to set up ipu_pm module */
+int ipu_pm_setup(struct ipu_pm_config *cfg);
+
+/* Function to create ipu pm object */
+struct ipu_pm_object *ipu_pm_create(const struct ipu_pm_params *params);
+
+/* Function to delete ipu pm object */
+void ipu_pm_delete(struct ipu_pm_object *handle);
+
+/* Function to destroy ipu_pm module */
+int ipu_pm_destroy(void);
+
+/* Function to attach ipu_pm module */
+int ipu_pm_attach(u16 remote_proc_id, void *shared_addr);
+
+/* Function to deattach ipu_pm module */
+int ipu_pm_detach(u16 remote_proc_id);
+
+/* Function to register the ipu_pm events */
+int ipu_pm_init_transport(struct ipu_pm_object *handle);
+
+#endif
diff --git a/drivers/dsp/syslink/multicore_ipc/Kbuild b/drivers/dsp/syslink/multicore_ipc/Kbuild
new file mode 100644
index 000000000000..faf06d8b35b4
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/Kbuild
@@ -0,0 +1,31 @@
+libsyslink_ipc = multiproc.o multiproc_ioctl.o nameserver.o \
+nameserver_ioctl.o nameserver_remote.o nameserver_remotenotify.o \
+listmp.o listmp_ioctl.o sharedregion.o sharedregion_ioctl.o \
+gate.o gatepeterson.o gatehwspinlock.o gatemp.o gatemp_ioctl.o \
+heap.o heapmemmp.o heapmemmp_ioctl.o heapbufmp.o heapbufmp_ioctl.o \
+messageq.o messageq_ioctl.o transportshm.o transportshm_setup.o \
+platform.o ipc.o sysipc_ioctl.o ipc_ioctl.o ipc_drv.o \
+../omap_notify/notify_driver.o ../omap_notify/notify.o \
+../omap_notify/drv_notify.o ../omap_notify/plat/omap4_notify_setup.o \
+../notify_ducatidriver/notify_ducati.o ../ipu_pm/ipu_pm.o
+
+libsyslink_platform = platform_mem.o
+
+obj-$(CONFIG_MPU_SYSLINK_IPC)        += syslink_ipc.o
+syslink_ipc-objs = $(libservices) $(libsyslink_ipc)
+
+obj-$(CONFIG_MPU_SYSLINK_PLATFORM)        += syslink_platform.o
+syslink_platform-objs = $(libservices) $(libsyslink_platform)
+
+ccflags-y += -Wno-strict-prototypes
+
+#Machine dependent
+ccflags-y += -D_TI_ -D_DB_TIOMAP -DTMS32060 \
+                -DTICFG_PROC_VER -DTICFG_EVM_TYPE -DCHNL_SMCLASS \
+                -DCHNL_MESSAGES -DUSE_LEVEL_1_MACROS  \
+                -DCONFIG_DISABLE_BRIDGE_PM -DDSP_TRACEBUF_DISABLED
+
+#Header files
+ccflags-y += -Iarch/arm/plat-omap/include
+ccflags-y += -Iarch/arm/plat-omap/include/syslink
+
diff --git a/drivers/dsp/syslink/multicore_ipc/gate.c b/drivers/dsp/syslink/multicore_ipc/gate.c
new file mode 100644
index 000000000000..713f22e7fcad
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/gate.c
@@ -0,0 +1,69 @@
+/*
+ *  gatemp.c
+ *
+ *  Gate wrapper implementation
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+/* Standard headers */
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+/* Module level headers */
+#include <igateprovider.h>
+#include <gate.h>
+
+
+/* Structure defining internal object for the Gate Peterson.*/
+struct gate_object {
+	IGATEPROVIDER_SUPEROBJECT; /* For inheritance from IGateProvider */
+};
+
+/* Function to enter a Gate */
+int *gate_enter_system(void)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	return (int *)flags;
+}
+
+/* Function to leave a gate */
+void gate_leave_system(int *key)
+{
+	local_irq_restore((unsigned long) key);
+}
+
+/* Match with IGateProvider */
+static inline int *_gate_enter_system(struct gate_object *obj)
+{
+	(void) obj;
+	return gate_enter_system();
+}
+
+/* Match with IGateProvider */
+static inline void _gate_leave_system(struct gate_object *obj, int *key)
+{
+	(void) obj;
+	gate_leave_system(key);
+}
+
+struct gate_object gate_system_object = {
+	.enter = (int *(*)(void *))_gate_enter_system,
+	.leave = (void (*)(void *, int *))_gate_leave_system,
+};
+
+struct igateprovider_object *gate_system_handle = \
+			(struct igateprovider_object *)&gate_system_object;
diff --git a/drivers/dsp/syslink/multicore_ipc/gate_remote.c b/drivers/dsp/syslink/multicore_ipc/gate_remote.c
new file mode 100644
index 000000000000..b5cf6871c8b9
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/gate_remote.c
@@ -0,0 +1,40 @@
+/*
+ *  gate_remote.c
+ *
+ *  This includes the functions to handle remote gates
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/types.h>
+
+/*
+ * ======== gate_remote_enter ========
+ *  Purpose:
+ *  This function is used to enter in to a remote gate
+ */
+int gate_remote_enter(void *ghandle)
+{
+	return 0;
+}
+
+/*
+ * ======== gate_remote_leave ========
+ *  Purpose:
+ *  This function is used to leave from a remote gate
+ */
+int gate_remote_leave(void *ghandle, u32 key)
+{
+	key = 0;
+	return 0;
+}
+
diff --git a/drivers/dsp/syslink/multicore_ipc/gatehwspinlock.c b/drivers/dsp/syslink/multicore_ipc/gatehwspinlock.c
new file mode 100644
index 000000000000..c97e57cb30f8
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/gatehwspinlock.c
@@ -0,0 +1,494 @@
+/*
+ *  gatehwspinlock.c
+ *
+ *  Hardware-based spinlock gate for mutual exclusion of shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <syslink/atomic_linux.h>
+#include <multiproc.h>
+#include <sharedregion.h>
+#include <gatemp.h>
+#include <igatempsupport.h>
+#include <igateprovider.h>
+#include <iobject.h>
+#include <gatehwspinlock.h>
+
+
+/* =============================================================================
+ * Macros
+ * =============================================================================
+ */
+
+/* Macro to make a correct module magic number with refCount */
+#define GATEHWSPINLOCK_MAKE_MAGICSTAMP(x) ((GATEHWSPINLOCK_MODULEID << 12u)  \
+					| (x))
+/*
+ *  structure for gatehwspinlock module state
+ */
+struct gatehwspinlock_module_object {
+	atomic_t ref_count; /* Reference count */
+	struct gatehwspinlock_config cfg;
+	struct gatehwspinlock_config default_cfg;
+	struct gatehwspinlock_params def_inst_params; /* default instance
+							paramters */
+	u32 *base_addr; /* Base address of lock registers */
+	u32 num_locks; /* Maximum number of locks */
+};
+
+/*
+ *  Structure defining object for the Gate Spinlock
+ */
+struct gatehwspinlock_object {
+	IGATEPROVIDER_SUPEROBJECT; /* For inheritance from IGateProvider */
+	IOBJECT_SUPEROBJECT;       /* For inheritance for IObject */
+	u32 lock_num;
+	u32 nested;
+	void *local_gate;
+};
+
+/*
+ *  Variable for holding state of the gatehwspinlock module
+ */
+struct gatehwspinlock_module_object gatehwspinlock_state = {
+	.default_cfg.default_protection	= \
+					gatehwspinlock_LOCALPROTECT_INTERRUPT,
+	.default_cfg.num_locks		= 32u,
+	.def_inst_params.shared_addr	= NULL,
+	.def_inst_params.resource_id	= 0x0,
+	.def_inst_params.region_id	= 0x0,
+	.num_locks			= 32u
+};
+
+static struct gatehwspinlock_module_object *gatehwspinlock_module =
+						&gatehwspinlock_state;
+
+/* =============================================================================
+ * Internal functions
+ * =============================================================================
+ */
+
+/* TODO: figure these out */
+#define gate_enter_system() 0
+#define gate_leave_system(key) {}
+
+/* =============================================================================
+ * APIS
+ * =============================================================================
+ */
+/*
+ * ======== gatehwspinlock_get_config ========
+ *  Purpose:
+ *  This will get the default configuration parameters for gatehwspinlock
+ *  module
+ */
+void gatehwspinlock_get_config(struct gatehwspinlock_config *config)
+{
+	int *key = 0;
+
+	if (WARN_ON(config == NULL))
+		goto exit;
+
+	key = gate_enter_system();
+	if (atomic_cmpmask_and_lt(&(gatehwspinlock_module->ref_count),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) == true)
+		memcpy(config, &gatehwspinlock_module->default_cfg,
+					sizeof(struct gatehwspinlock_config));
+	else
+		memcpy(config, &gatehwspinlock_module->cfg,
+					sizeof(struct gatehwspinlock_config));
+	gate_leave_system(key);
+
+exit:
+	return;
+}
+EXPORT_SYMBOL(gatehwspinlock_get_config);
+
+/*
+ * ======== gatehwspinlock_setup ========
+ *  Purpose:
+ *  This will setup the gatehwspinlock module
+ */
+int gatehwspinlock_setup(const struct gatehwspinlock_config *config)
+{
+	struct gatehwspinlock_config tmp_cfg;
+	int *key = 0;
+
+	key = gate_enter_system();
+
+	/* This sets the ref_count variable  not initialized, upper 16 bits is
+	* written with module _id to ensure correctness of ref_count variable
+	*/
+	atomic_cmpmask_and_set(&gatehwspinlock_module->ref_count,
+					GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+					GATEHWSPINLOCK_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&gatehwspinlock_module->ref_count)
+					!= GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) {
+		gate_leave_system(key);
+		return 1;
+	}
+
+	if (config == NULL) {
+		gatehwspinlock_get_config(&tmp_cfg);
+		config = &tmp_cfg;
+	}
+	gate_leave_system(key);
+
+	memcpy(&gatehwspinlock_module->cfg, config,
+					sizeof(struct gatehwspinlock_config));
+
+	gatehwspinlock_module->base_addr = (void *)config->base_addr;
+	gatehwspinlock_module->num_locks = config->num_locks;
+
+	return 0;
+
+}
+EXPORT_SYMBOL(gatehwspinlock_setup);
+
+/*
+ * ======== gatehwspinlock_destroy ========
+ *  Purpose:
+ *  This will destroy the gatehwspinlock module
+ */
+int gatehwspinlock_destroy(void)
+{
+	s32 retval = 0;
+	int *key = 0;
+
+	key = gate_enter_system();
+
+	if (atomic_cmpmask_and_lt(&(gatehwspinlock_module->ref_count),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (!(atomic_dec_return(&gatehwspinlock_module->ref_count)
+			== GATEHWSPINLOCK_MAKE_MAGICSTAMP(0))) {
+		gate_leave_system(key);
+		retval = 1;
+		goto exit;
+	}
+	gate_leave_system(key);
+
+	memset(&gatehwspinlock_module->cfg, 0,
+				sizeof(struct gatehwspinlock_config));
+	return 0;
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "gatehwspinlock_destroy failed status:%x\n",
+			retval);
+	}
+	return retval;
+
+}
+EXPORT_SYMBOL(gatehwspinlock_destroy);
+
+/*
+ * ======== gatehwspinlock_get_num_instances ========
+ *  Purpose:
+ *  Function to return the number of instances configured in the module.
+ */
+u32 gatehwspinlock_get_num_instances(void)
+{
+	return gatehwspinlock_module->num_locks;
+}
+EXPORT_SYMBOL(gatehwspinlock_get_num_instances);
+
+/*
+ * ======== gatepeterson_locks_init ========
+ *  Purpose:
+ *  Function to initialize the locks.
+ */
+void gatehwspinlock_locks_init(void)
+{
+	u32 i;
+
+	for (i = 0; i < gatehwspinlock_module->num_locks; i++)
+		gatehwspinlock_module->base_addr[i] = 0;
+}
+EXPORT_SYMBOL(gatehwspinlock_locks_init);
+
+/*
+ * ======== gatehwspinlock_params_init ========
+ *  Purpose:
+ *  This will  Initialize this config-params structure with
+ *  supplier-specified defaults before instance creation
+ */
+void gatehwspinlock_params_init(struct gatehwspinlock_params *params)
+{
+	int *key = 0;
+
+	key = gate_enter_system();
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(gatehwspinlock_module->ref_count),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) == true))
+		goto exit;
+	if (WARN_ON(params == NULL))
+		goto exit;
+
+	gate_leave_system(key);
+	memcpy(params, &(gatehwspinlock_module->def_inst_params),
+				sizeof(struct gatehwspinlock_params));
+	return;
+
+exit:
+	gate_leave_system(key);
+	return;
+}
+EXPORT_SYMBOL(gatehwspinlock_params_init);
+
+/*
+ * ======== gatehwspinlock_create ========
+ *  Purpose:
+ *  This will creates a new instance of gatehwspinlock module
+ */
+void *gatehwspinlock_create(enum igatempsupport_local_protect local_protect,
+				const struct gatehwspinlock_params *params)
+{
+	void *handle = NULL;
+	struct gatehwspinlock_object *obj = NULL;
+	s32 retval = 0;
+
+	if (atomic_cmpmask_and_lt(&(gatehwspinlock_module->ref_count),
+					GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(params == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(params->shared_addr == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = kzalloc(sizeof(struct gatehwspinlock_object), GFP_KERNEL);
+	if (obj == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+
+	IGATEPROVIDER_OBJECTINITIALIZER(obj, gatehwspinlock);
+
+	/* Create the local gate */
+	obj->local_gate = gatemp_create_local(local_protect);
+	if (obj->local_gate == NULL) {
+		retval = GATEHWSPINLOCK_E_FAIL;
+		goto exit;
+	}
+
+	obj->lock_num = params->resource_id;
+	obj->nested   = 0;
+
+	handle = obj;
+	return handle;
+
+exit:
+	printk(KERN_ERR "gatehwspinlock_create failed status: %x\n", retval);
+	return NULL;
+}
+EXPORT_SYMBOL(gatehwspinlock_create);
+
+/*
+ * ======== gatehwspinlock_delete ========
+ *  Purpose:
+ *  This will deletes an instance of gatehwspinlock module
+ */
+int gatehwspinlock_delete(void **gphandle)
+
+{
+	struct gatehwspinlock_object *obj = NULL;
+	s32 retval;
+
+	if (atomic_cmpmask_and_lt(&(gatehwspinlock_module->ref_count),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(gphandle == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(*gphandle == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct gatehwspinlock_object *)(*gphandle);
+
+	/* No need to delete the local gate, as it is gatemp module wide
+	 * local mutex. */
+
+	kfree(obj);
+	*gphandle = NULL;
+
+	return 0;
+
+exit:
+	printk(KERN_ERR "gatehwspinlock_delete failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(gatehwspinlock_delete);
+
+
+/*
+ * ======== gatehwspinlock_enter ========
+ *  Purpose:
+ *  This will enters the gatehwspinlock instance
+ */
+int *gatehwspinlock_enter(void *gphandle)
+{
+	struct gatehwspinlock_object *obj = NULL;
+	s32 retval = 0;
+	int *key = 0;
+	VOLATILE u32 *base_addr = (VOLATILE u32 *)
+					gatehwspinlock_module->base_addr;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(gatehwspinlock_module->ref_count),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(gphandle == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct gatehwspinlock_object *)gphandle;
+
+	/* Enter local gate */
+	/* Enter local gate */
+	if (obj->local_gate != NULL) {
+		retval = mutex_lock_interruptible(
+					(struct mutex *)obj->local_gate);
+		if (retval)
+			goto exit;
+	}
+
+	/* If the gate object has already been entered, return the nested
+	 * value */
+	obj->nested++;
+	if (obj->nested > 1)
+		return key;
+
+	/* Enter the spinlock */
+	while (1) {
+		if (base_addr[obj->lock_num] == 0)
+			break;
+	}
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "gatehwspinlock_enter failed! status = 0x%x",
+			retval);
+	return key;
+}
+EXPORT_SYMBOL(gatehwspinlock_enter);
+
+/*
+ * ======== gatehwspinlock_leave ========
+ *  Purpose:
+ *  This will leaves the gatehwspinlock instance
+ */
+void gatehwspinlock_leave(void *gphandle, int *key)
+{
+	struct gatehwspinlock_object *obj = NULL;
+	VOLATILE u32 *base_addr = (VOLATILE u32 *)
+					gatehwspinlock_module->base_addr;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(gatehwspinlock_module->ref_count),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(gphandle == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct gatehwspinlock_object *)gphandle;
+	obj->nested--;
+	/* Leave the spinlock if the leave() is not nested */
+	if (obj->nested == 0)
+		base_addr[obj->lock_num] = 0;
+	/* Leave local gate */
+	mutex_unlock(obj->local_gate);
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "gatehwspinlock_leave failed! status = 0x%x",
+			retval);
+	return;
+}
+EXPORT_SYMBOL(gatehwspinlock_leave);
+
+/*
+ *  ======== gatehwspinlock_get_resource_id ========
+ */
+u32 gatehwspinlock_get_resource_id(void *handle)
+{
+	struct gatehwspinlock_object *obj = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(gatehwspinlock_module->ref_count),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(0),
+				GATEHWSPINLOCK_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(handle == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct gatehwspinlock_object *)handle;
+
+	return obj->lock_num;
+
+exit:
+	printk(KERN_ERR "gatehwspinlock_get_resource_id failed status: %x\n",
+		retval);
+	return (u32)-1;
+}
+EXPORT_SYMBOL(gatehwspinlock_get_resource_id);
+
+/*
+ * ======== gatehwspinlock_shared_memreq ========
+ *  Purpose:
+ *  This will give the amount of shared memory required
+ *  for creation of each instance
+ */
+u32 gatehwspinlock_shared_mem_req(const struct gatehwspinlock_params *params)
+{
+	return 0;
+}
+EXPORT_SYMBOL(gatehwspinlock_shared_mem_req);
diff --git a/drivers/dsp/syslink/multicore_ipc/gatemp.c b/drivers/dsp/syslink/multicore_ipc/gatemp.c
new file mode 100644
index 000000000000..4c7244168bbd
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/gatemp.c
@@ -0,0 +1,1846 @@
+/*
+ *  gatemp.c
+ *
+ *  Gate wrapper implementation
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+#include <linux/semaphore.h>
+
+/* Syslink utilities headers */
+#include <syslink/atomic_linux.h>
+
+/* Syslink module headers */
+#include <multiproc.h>
+#include <igateprovider.h>
+#include <igatempsupport.h>
+#include <iobject.h>
+#include <gate.h>
+/*#include <memory.h>
+#include <bitops.h>
+#include <ti/syslink/utils/Cache.h>
+*/
+#include <nameserver.h>
+#include <sharedregion.h>
+
+/* Module level headers */
+#include <gatemp.h>
+#include <gatemp.h>
+#include <gatempdefs.h>
+
+
+/* -----------------------------------------------------------------------------
+ * Macros
+ * -----------------------------------------------------------------------------
+ */
+/* VERSION */
+#define GATEMP_VERSION			(1)
+
+/* CREATED */
+#define GATEMP_CREATED			(0x11202009)
+
+/* PROXYORDER_SYSTEM */
+#define GATEMP_PROXYORDER_SYSTEM	(0)
+
+/* PROXYORDER_CUSTOM1 */
+#define GATEMP_PROXYORDER_CUSTOM1	(1)
+
+/* PROXYORDER_CUSTOM2 */
+#define GATEMP_PROXYORDER_CUSTOM2	(2)
+
+/* PROXYORDER_NUM */
+#define GATEMP_PROXYORDER_NUM		(3)
+
+/* Macro to make a correct module magic number with refCount */
+#define GATEMP_MAKE_MAGICSTAMP(x)	\
+				((GATEMP_MODULEID << 12u) | (x))
+
+/* Helper macros */
+#define GETREMOTE(mask)		((enum gatemp_remote_protect)(mask >> 8))
+#define GETLOCAL(mask)		((enum gatemp_local_protect)(mask & 0xFF))
+#define SETMASK(remote_protect, local_protect) \
+				((u32)(remote_protect << 8 | local_protect))
+
+
+/* Name of the reserved NameServer used for GateMP. */
+#define GATEMP_NAMESERVER  "GateMP"
+
+#define ROUND_UP(a, b)	(((a) + ((b) - 1)) & (~((b) - 1)))
+
+#define Gate_enterSystem()	(int *)0
+
+#define Gate_leaveSystem(key)	(void)0
+
+/* -----------------------------------------------------------------------------
+ * Structs & Enums
+ * -----------------------------------------------------------------------------
+ */
+/* Attrs */
+struct gatemp_attrs {
+	u16 mask;
+	u16 creator_proc_id;
+	u32 arg;
+	u32 status;
+};
+
+/* Structure defining state of GateMP Module */
+struct gatemp_module_state {
+	void *name_server;
+	int num_remote_system;
+	int num_remote_custom1;
+	int num_remote_custom2;
+	u8 *remote_system_in_use_alloc;
+	u8 *remote_custom1_in_use_alloc;
+	u8 *remote_custom2_in_use_alloc;
+	void **remote_system_gates_alloc;
+	void **remote_custom1_gates_alloc;
+	void **remote_custom2_gates_alloc;
+	u8 *remote_system_in_use;
+	u8 *remote_custom1_in_use;
+	u8 *remote_custom2_in_use;
+	void **remote_system_gates;
+	void **remote_custom1_gates;
+	void **remote_custom2_gates;
+	struct igateprovider_object *gate_hwi;
+	struct mutex *gate_mutex;
+	struct igateprovider_object *gate_null;
+	struct gatemp_object *default_gate;
+	int proxy_map[GATEMP_PROXYORDER_NUM];
+	atomic_t ref_count;
+	struct gatemp_config cfg;
+	/* Current config values */
+	struct gatemp_config default_cfg;
+	/* default config values */
+	struct gatemp_params def_inst_params;
+	/* default instance paramters */
+	bool is_owner;
+	/* Indicates if this processor is the owner */
+	atomic_t attach_ref_count;
+	/* Attach/detach reference count */
+};
+
+/* Structure defining instance of GateMP Module */
+struct gatemp_object {
+	IGATEPROVIDER_SUPEROBJECT; /* For inheritance from IGateProvider */
+	IOBJECT_SUPEROBJECT; /* For inheritance for IObject */
+	enum gatemp_remote_protect remote_protect;
+	enum gatemp_local_protect local_protect;
+	void *ns_key;
+	int num_opens;
+	u16 creator_proc_id;
+	bool cache_enabled;
+	struct gatemp_attrs *attrs;
+	u16 region_id;
+	uint alloc_size;
+	void *proxy_attrs;
+	u32 resource_id;
+	void *gate_handle;
+	enum ipc_obj_type obj_type; /* from shared region? */
+};
+
+/* Reserved */
+struct gatemp_reserved {
+	u32  version;
+};
+
+/* Localgate */
+struct gatemp_local_gate {
+	struct igateprovider_object *local_gate;
+	int ref_count;
+};
+
+/*!
+ *  @brief  Structure defining parameters for the GateMP module.
+ */
+struct _gatemp_params {
+	char *name;
+	u32 region_id;
+	void *shared_addr;
+	enum gatemp_local_protect local_protect;
+	enum gatemp_remote_protect remote_protect;
+	u32 resource_id;
+	bool open_flag;
+};
+
+/* -----------------------------------------------------------------------------
+ * Forward declaration
+ * -----------------------------------------------------------------------------
+ */
+static void gatemp_set_region0_reserved(void *shared_addr);
+static void gatemp_clear_region0_reserved(void);
+static void gatemp_open_region0_reserved(void *shared_addr);
+static void gatemp_close_region0_reserved(void *shared_addr);
+static void gatemp_set_default_remote(void *handle);
+static uint gatemp_get_free_resource(u8 *in_use, int num);
+static struct gatemp_object *_gatemp_create(
+					const struct _gatemp_params *params);
+
+/* -----------------------------------------------------------------------------
+ * Globals
+ * -----------------------------------------------------------------------------
+ */
+static struct gatemp_module_state gatemp_state = {
+	.default_cfg.num_resources = 32,
+	.default_cfg.max_name_len = 32,
+	.default_cfg.default_protection = GATEMP_LOCALPROTECT_INTERRUPT,
+	.def_inst_params.shared_addr = 0x0,
+	.def_inst_params.region_id = 0x0,
+	.default_gate  = NULL
+};
+
+static struct gatemp_module_state *gatemp_module = &gatemp_state;
+static struct gatemp_object *gatemp_first_object;
+
+/* -----------------------------------------------------------------------------
+ * APIs
+ * -----------------------------------------------------------------------------
+ */
+
+void gatemp_get_config(struct gatemp_config *cfg)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(cfg == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (atomic_cmpmask_and_lt(&(gatemp_module->ref_count),
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(1)) == true) {
+		/* Setup has not yet been called */
+		memcpy((void *)cfg, &gatemp_module->default_cfg,
+			sizeof(struct gatemp_config));
+	} else {
+		memcpy((void *)cfg, &gatemp_module->cfg,
+			sizeof(struct gatemp_config));
+	}
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "gatemp_get_config failed! status = 0x%x",
+			retval);
+	return;
+}
+
+s32 gatemp_setup(const struct gatemp_config *cfg)
+{
+	s32 retval = 0;
+	struct gatemp_config tmp_cfg;
+	int i;
+	struct nameserver_params params;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of refCount variable.
+	*/
+	atomic_cmpmask_and_set(&gatemp_module->ref_count,
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&gatemp_module->ref_count)
+				!= GATEMP_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	if (cfg == NULL) {
+		gatemp_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	gatemp_module->default_gate = NULL;
+	for (i = 0; i < GATEMP_PROXYORDER_NUM; i++)
+		gatemp_module->proxy_map[i] = i;
+
+	if ((void *)gatemp_remote_custom1_proxy_create
+			== (void *)gatemp_remote_system_proxy_create) {
+		gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM1] =
+			gatemp_module->proxy_map[GATEMP_PROXYORDER_SYSTEM];
+	}
+
+	if ((void *) gatemp_remote_system_proxy_create
+			== (void *) gatemp_remote_custom2_proxy_create) {
+		gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM2] =
+			gatemp_module->proxy_map[GATEMP_PROXYORDER_SYSTEM];
+	} else if ((void *) gatemp_remote_custom2_proxy_create
+			== (void *) gatemp_remote_custom1_proxy_create) {
+		gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM2] =
+			gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM1];
+	}
+
+	/* Create MutexPri gate */
+	gatemp_module->gate_mutex = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (gatemp_module->gate_mutex == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+	mutex_init(gatemp_module->gate_mutex);
+
+	/* create Nameserver */
+	nameserver_params_init(&params);
+	params.max_runtime_entries = cfg->max_runtime_entries;
+	params.max_name_len = cfg->max_name_len;
+	params.max_value_len = 2 * sizeof(u32);
+	gatemp_module->name_server = nameserver_create(GATEMP_NAMESERVER,
+							&params);
+	if (gatemp_module->name_server == NULL) {
+		retval = -1;
+		goto error_nameserver;
+	}
+
+	/* Get the number of coonfigured instances from the plugged in
+	* Proxy gates */
+	gatemp_module->num_remote_system = \
+				gatemp_remote_system_proxy_get_num_instances();
+	gatemp_module->num_remote_custom1 = \
+				gatemp_remote_custom1_proxy_get_num_instances();
+	gatemp_module->num_remote_custom2 = \
+				gatemp_remote_custom2_proxy_get_num_instances();
+	gatemp_module->remote_system_in_use_alloc = \
+		kzalloc((sizeof(u8) * cfg->num_resources), GFP_KERNEL);
+	if (gatemp_module->remote_system_in_use_alloc == NULL) {
+		retval = -ENOMEM;
+		goto error_remote_system_fail;
+	}
+	gatemp_module->remote_system_in_use = \
+				gatemp_module->remote_system_in_use_alloc;
+
+	gatemp_module->remote_custom1_in_use_alloc = \
+		kzalloc((sizeof(u8) * cfg->num_resources), GFP_KERNEL);
+	if (gatemp_module->remote_custom1_in_use_alloc == NULL) {
+		retval = -ENOMEM;
+		goto error_remote_custom1_fail;
+	}
+	gatemp_module->remote_custom1_in_use = \
+				gatemp_module->remote_custom1_in_use_alloc;
+
+	gatemp_module->remote_custom2_in_use_alloc = \
+		kzalloc((sizeof(u8) * cfg->num_resources), GFP_KERNEL);
+	if (gatemp_module->remote_custom2_in_use_alloc == NULL) {
+		retval = -ENOMEM;
+		goto error_remote_custom2_fail;
+	}
+	gatemp_module->remote_custom2_in_use = \
+				gatemp_module->remote_custom2_in_use_alloc;
+
+	if (gatemp_module->num_remote_system) {
+		gatemp_module->remote_system_gates_alloc = kzalloc(
+			(sizeof(void *) * gatemp_module->num_remote_system),
+			GFP_KERNEL);
+		if (gatemp_module->remote_system_gates_alloc == NULL) {
+			retval = -ENOMEM;
+			goto error_remote_system_gates_fail;
+		}
+	} else
+		gatemp_module->remote_system_gates_alloc = NULL;
+	gatemp_module->remote_system_gates = \
+				gatemp_module->remote_system_gates_alloc;
+
+	if (gatemp_module->num_remote_custom1) {
+		gatemp_module->remote_custom1_gates_alloc = kzalloc(
+			(sizeof(void *) * gatemp_module->num_remote_custom1),
+			GFP_KERNEL);
+		if (gatemp_module->remote_custom1_gates_alloc == NULL) {
+			retval = -ENOMEM;
+			goto error_remote_custom1_gates_fail;
+		}
+	} else
+		gatemp_module->remote_custom1_gates_alloc = NULL;
+	gatemp_module->remote_custom1_gates = \
+				gatemp_module->remote_custom1_gates_alloc;
+
+	if (gatemp_module->num_remote_custom2) {
+		gatemp_module->remote_custom2_gates_alloc = kzalloc(
+			(sizeof(void *) * gatemp_module->num_remote_custom2),
+			GFP_KERNEL);
+		if (gatemp_module->remote_custom2_gates_alloc == NULL) {
+			retval = -ENOMEM;
+			goto error_remote_custom2_gates_fail;
+		}
+	} else
+		gatemp_module->remote_custom2_gates_alloc = NULL;
+	gatemp_module->remote_custom2_gates = \
+				gatemp_module->remote_custom2_gates_alloc;
+
+	/* Copy the cfg */
+	memcpy((void *) &gatemp_module->cfg, (void *) cfg,
+			sizeof(struct gatemp_config));
+	return 0;
+
+error_remote_custom2_gates_fail:
+	kfree(gatemp_module->remote_custom1_gates_alloc);
+	gatemp_module->remote_custom1_gates_alloc = NULL;
+	gatemp_module->remote_custom1_gates = NULL;
+error_remote_custom1_gates_fail:
+	kfree(gatemp_module->remote_system_gates_alloc);
+	gatemp_module->remote_system_gates_alloc = NULL;
+	gatemp_module->remote_system_gates = NULL;
+error_remote_system_gates_fail:
+	kfree(gatemp_module->remote_custom2_in_use_alloc);
+	gatemp_module->remote_custom2_in_use_alloc = NULL;
+	gatemp_module->remote_custom2_in_use = NULL;
+error_remote_custom2_fail:
+	kfree(gatemp_module->remote_custom1_in_use_alloc);
+	gatemp_module->remote_custom1_in_use_alloc = NULL;
+	gatemp_module->remote_custom1_in_use = NULL;
+error_remote_custom1_fail:
+	kfree(gatemp_module->remote_system_in_use_alloc);
+	gatemp_module->remote_system_in_use_alloc = NULL;
+	gatemp_module->remote_system_in_use = NULL;
+error_remote_system_fail:
+	if (gatemp_module->name_server)
+		nameserver_delete(&gatemp_module->name_server);
+error_nameserver:
+	kfree(gatemp_module->gate_mutex);
+	gatemp_module->gate_mutex = NULL;
+exit:
+	printk(KERN_ERR "gatemp_setup failed! status = 0x%x", retval);
+	return retval;
+}
+
+s32 gatemp_destroy(void)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(gatemp_module->ref_count),
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (!(atomic_dec_return(&gatemp_module->ref_count)
+			== GATEMP_MAKE_MAGICSTAMP(0))) {
+		retval = 1;
+		goto exit;
+	}
+
+	kfree(gatemp_module->gate_mutex);
+	gatemp_module->gate_mutex = NULL;
+
+	if (gatemp_module->name_server)
+		nameserver_delete(&gatemp_module->name_server);
+
+	kfree(gatemp_module->remote_system_in_use_alloc);
+	gatemp_module->remote_system_in_use_alloc = NULL;
+	gatemp_module->remote_system_in_use = NULL;
+
+	kfree(gatemp_module->remote_custom1_in_use_alloc);
+	gatemp_module->remote_custom1_in_use_alloc = NULL;
+	gatemp_module->remote_custom1_in_use = NULL;
+
+	kfree(gatemp_module->remote_custom2_in_use_alloc);
+	gatemp_module->remote_custom2_in_use_alloc = NULL;
+	gatemp_module->remote_custom2_in_use = NULL;
+
+	kfree(gatemp_module->remote_system_gates_alloc);
+	gatemp_module->remote_system_gates_alloc = NULL;
+	gatemp_module->remote_system_gates = NULL;
+
+	kfree(gatemp_module->remote_custom1_gates_alloc);
+	gatemp_module->remote_custom1_gates_alloc = NULL;
+	gatemp_module->remote_custom1_gates = NULL;
+
+	kfree(gatemp_module->remote_custom2_gates_alloc);
+	gatemp_module->remote_custom2_gates_alloc = NULL;
+	gatemp_module->remote_custom2_gates = NULL;
+
+	/* Clear cfg area */
+	memset((void *) &gatemp_module->cfg, 0, sizeof(struct gatemp_config));
+	gatemp_module->is_owner = false;
+	return 0;
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "gatemp_destroy failed! status = 0x%x", retval);
+	return retval;
+}
+
+static void _gatemp_get_shared_params(struct gatemp_params *sparams,
+					const struct _gatemp_params *params)
+{
+	sparams->name = params->name;
+	sparams->region_id = params->region_id;
+	sparams->shared_addr = params->shared_addr;
+	sparams->local_protect = \
+			(enum gatemp_local_protect) params->local_protect;
+	sparams->remote_protect = \
+			(enum gatemp_remote_protect) params->remote_protect;
+}
+
+void gatemp_params_init(struct gatemp_params *params)
+{
+	params->name = NULL;
+	params->region_id = 0;
+	params->shared_addr = NULL;
+	params->local_protect = GATEMP_LOCALPROTECT_INTERRUPT;
+	params->remote_protect = GATEMP_REMOTEPROTECT_SYSTEM;
+}
+
+int gatemp_instance_init(struct gatemp_object *obj,
+			 const struct _gatemp_params *params)
+{
+	int *key;
+	void *remote_handle;
+	gatemp_remote_system_proxy_params system_params;
+	gatemp_remote_custom1_proxy_params custom1_params;
+	gatemp_remote_custom2_proxy_params custom2_params;
+	u32 min_align;
+	u32 offset;
+	u32 *shared_shm_base;
+	struct gatemp_params sparams;
+	u32 ns_value[2];
+	uint cache_line_size = 0;
+	int retval = 0;
+	void *region_heap;
+
+	/* No parameter check since this function will be called internally */
+
+	/* Initialize resource_id to an invalid value */
+	obj->resource_id = (u32)-1;
+
+	/* Open GateMP instance */
+	if (params->open_flag == true) {
+		/* all open work done here except for remote gate_handle */
+		obj->local_protect = params->local_protect;
+		obj->remote_protect = params->remote_protect;
+		obj->ns_key = 0;
+		obj->num_opens = 1;
+		obj->creator_proc_id = MULTIPROC_INVALIDID;
+		obj->attrs = (struct gatemp_attrs *)params->shared_addr;
+		obj->region_id = sharedregion_get_id((void *)obj->attrs);
+		obj->cache_enabled = \
+				sharedregion_is_cache_enabled(obj->region_id);
+		obj->obj_type = IPC_OBJTYPE_OPENDYNAMIC;
+
+		/* Assert that the buffer is in a valid shared region */
+		if (obj->region_id == SHAREDREGION_INVALIDREGIONID)
+			retval = 1;
+
+		if (retval == 0) {
+			cache_line_size = sharedregion_get_cache_line_size(
+								obj->region_id);
+
+			obj->alloc_size = 0;
+
+			/*min_align = Memory_getMaxDefaultTypeAlign();*/
+			min_align = 4;
+			if (cache_line_size > min_align)
+				min_align = cache_line_size;
+
+			offset = ROUND_UP(sizeof(struct gatemp_attrs), \
+								min_align);
+			obj->proxy_attrs = (void *)((u32)obj->attrs + offset);
+		}
+		goto proxy_work;
+	}
+
+	/* Create GateMP instance */
+	obj->local_protect = params->local_protect;
+	obj->remote_protect = params->remote_protect;
+	obj->ns_key = 0;
+	obj->num_opens = 0;
+	obj->creator_proc_id = multiproc_self();
+
+	/* No Remote Protection needed, just create the local protection */
+	if (obj->remote_protect == GATEMP_REMOTEPROTECT_NONE) {
+		/* Creating a local gate (Attrs is in local memory) */
+		/* all work done here and return */
+		obj->gate_handle = gatemp_create_local(obj->local_protect);
+
+		if (params->shared_addr != NULL) {
+			obj->attrs = params->shared_addr;
+			obj->obj_type = IPC_OBJTYPE_CREATEDYNAMIC;
+			/* Need cache settings since attrs is in shared mem */
+			obj->region_id = \
+				sharedregion_get_id((void *)obj->attrs);
+			obj->cache_enabled = \
+				sharedregion_is_cache_enabled(obj->region_id);
+		} else {
+			obj->obj_type = IPC_OBJTYPE_LOCAL;
+			obj->cache_enabled = false; /* local */
+			obj->region_id = SHAREDREGION_INVALIDREGIONID;
+			/* Using default target alignment */
+			obj->attrs = kmalloc(sizeof(struct gatemp_attrs),
+						GFP_KERNEL);
+			if (obj->attrs == NULL)
+				return 2;
+		}
+
+		if (retval == 0) {
+			obj->attrs->arg = (u32)obj;
+			obj->attrs->mask = SETMASK(obj->remote_protect,
+							obj->local_protect);
+			obj->attrs->creator_proc_id = obj->creator_proc_id;
+			obj->attrs->status = GATEMP_CREATED;
+#if 0
+			if (obj->cache_enabled) {
+				/* Need to write back memory if cache is enabled
+				 * because cache will be invalidated during
+				 * open_by_addr */
+				Cache_wbInv(obj->attrs,
+						sizeof(struct gatemp_attrs),
+						Cache_Type_ALL, true);
+			}
+#endif
+			if (params->name != NULL) {
+				/*  Top 16 bits = procId of creator. Bottom 16
+				 * bits = '0' if local, '1' otherwise */
+				ns_value[0] = (u32)obj->attrs;
+				ns_value[1] = multiproc_self() << 16;
+				obj->ns_key = nameserver_add(
+						gatemp_module->name_server,
+						params->name, &ns_value,
+						2 * sizeof(u32));
+			}
+		}
+		goto proxy_work;
+	}
+
+	/* Create remote protection */
+	if (params->shared_addr == NULL) {
+		/* If sharedAddr = NULL we are creating dynamically from the
+		 * heap */
+		obj->obj_type = IPC_OBJTYPE_CREATEDYNAMIC_REGION;
+		obj->region_id = params->region_id;
+		_gatemp_get_shared_params(&sparams, params);
+		obj->alloc_size = gatemp_shared_mem_req(&sparams);
+		obj->cache_enabled = sharedregion_is_cache_enabled(
+								obj->region_id);
+
+		/* The region heap will do the alignment */
+		region_heap = sharedregion_get_heap(obj->region_id);
+		WARN_ON(region_heap == NULL);
+		obj->attrs = sl_heap_alloc(region_heap, obj->alloc_size, 0);
+		if (obj->attrs == NULL)
+			retval = 3;
+
+		if (retval == 0) {
+			cache_line_size = sharedregion_get_cache_line_size(
+								obj->region_id);
+			/*min_align = Memory_getMaxDefaultTypeAlign();*/
+			min_align = 4;
+
+			if (cache_line_size > min_align)
+				min_align = cache_line_size;
+
+			offset = ROUND_UP(sizeof(struct gatemp_attrs), \
+								min_align);
+			obj->proxy_attrs = (void *)((u32)obj->attrs + offset);
+		}
+	} else { /* creating using shared_addr */
+		obj->region_id = sharedregion_get_id(params->shared_addr);
+		/* Assert that the buffer is in a valid shared region */
+		if (obj->region_id == SHAREDREGION_INVALIDREGIONID)
+			retval = 4;
+
+		cache_line_size = sharedregion_get_cache_line_size(
+								obj->region_id);
+		/* Assert that shared_addr is cache aligned */
+		if ((retval == 0) && (((u32)params->shared_addr % \
+							cache_line_size) != 0))
+			retval = 5;
+
+		if (retval == 0) {
+			obj->obj_type = IPC_OBJTYPE_CREATEDYNAMIC;
+			obj->attrs = (struct gatemp_attrs *)params->shared_addr;
+			obj->cache_enabled = \
+				sharedregion_is_cache_enabled(obj->region_id);
+
+			/*min_align = Memory_getMaxDefaultTypeAlign();*/
+			min_align = 4;
+			if (cache_line_size > min_align)
+				min_align = cache_line_size;
+			offset = ROUND_UP(sizeof(struct gatemp_attrs), \
+								min_align);
+			obj->proxy_attrs = (void *)((u32)obj->attrs + offset);
+		}
+	}
+
+proxy_work:
+	/* Proxy work for open and create done here */
+	switch (obj->remote_protect) {
+	case GATEMP_REMOTEPROTECT_SYSTEM:
+		if (obj->obj_type != IPC_OBJTYPE_OPENDYNAMIC) {
+			/* Created Instance */
+			obj->resource_id = gatemp_get_free_resource(
+					gatemp_module->remote_system_in_use,
+					gatemp_module->num_remote_system);
+			if (obj->resource_id == -1)
+				retval = 6;
+		} else {
+			/* resource_id set by open call */
+			obj->resource_id = params->resource_id;
+		}
+
+		if (retval == 0) {
+			/* Create the proxy object */
+			gatemp_remote_system_proxy_params_init(&system_params);
+			system_params.resource_id = obj->resource_id;
+			system_params.open_flag = \
+				(obj->obj_type == IPC_OBJTYPE_OPENDYNAMIC);
+			system_params.shared_addr = obj->proxy_attrs;
+			system_params.region_id = obj->region_id;
+			remote_handle = gatemp_remote_system_proxy_create(
+					(enum igatempsupport_local_protect)
+					obj->local_protect,
+					&system_params);
+
+			if (remote_handle == NULL)
+				retval = 7;
+
+			if (retval == 0) {
+				/* Finish filling in the object */
+				obj->gate_handle = remote_handle;
+
+				/* Fill in the local array because it is
+				 * cooked */
+				key = Gate_enterSystem();
+				gatemp_module->remote_system_gates[
+					obj->resource_id] = (void *)obj;
+				Gate_leaveSystem(key);
+			}
+		}
+		break;
+
+	case GATEMP_REMOTEPROTECT_CUSTOM1:
+		if (obj->obj_type != IPC_OBJTYPE_OPENDYNAMIC) {
+			/* Created Instance */
+			obj->resource_id = gatemp_get_free_resource(
+					gatemp_module->remote_custom1_in_use,
+					gatemp_module->num_remote_custom1);
+			if (obj->resource_id == -1)
+				retval = 6;
+		} else {
+			/* resource_id set by open call */
+			obj->resource_id = params->resource_id;
+		}
+
+		if (retval == 0) {
+			/* Create the proxy object */
+			gatemp_remote_custom1_proxy_params_init(\
+							&custom1_params);
+			custom1_params.resource_id = obj->resource_id;
+			custom1_params.open_flag = \
+				(obj->obj_type == IPC_OBJTYPE_OPENDYNAMIC);
+			custom1_params.shared_addr = obj->proxy_attrs;
+			custom1_params.region_id = obj->region_id;
+			remote_handle = gatemp_remote_custom1_proxy_create(
+						(enum gatemp_local_protect)
+						obj->local_protect,
+						&custom1_params);
+			if (remote_handle == NULL)
+				retval = 7;
+
+			if (retval == 0) {
+				/* Finish filling in the object */
+				obj->gate_handle = remote_handle;
+
+				/* Fill in the local array because it is
+				 * cooked */
+				key = Gate_enterSystem();
+				gatemp_module->remote_custom1_gates[
+					obj->resource_id] = (void *)obj;
+				Gate_leaveSystem(key);
+			}
+		}
+		break;
+
+	case GATEMP_REMOTEPROTECT_CUSTOM2:
+		if (obj->obj_type != IPC_OBJTYPE_OPENDYNAMIC) {
+			/* Created Instance */
+			obj->resource_id = gatemp_get_free_resource(
+				gatemp_module->remote_custom2_in_use,
+				gatemp_module->num_remote_custom2);
+			if (obj->resource_id == -1)
+				retval = 6;
+		} else {
+			/* resource_id set by open call */
+			obj->resource_id = params->resource_id;
+		}
+
+		if (retval == 0) {
+			/* Create the proxy object */
+			gatemp_remote_custom2_proxy_params_init(\
+							&custom2_params);
+			custom2_params.resource_id = obj->resource_id;
+			custom2_params.open_flag = \
+				(obj->obj_type == IPC_OBJTYPE_OPENDYNAMIC);
+			custom2_params.shared_addr = obj->proxy_attrs;
+			custom2_params.region_id = obj->region_id;
+			remote_handle = gatemp_remote_custom2_proxy_create(
+						(enum gatemp_local_protect)
+						obj->local_protect,
+						&custom2_params);
+			if (remote_handle == NULL)
+				retval = 7;
+
+			if (retval == 0) {
+				/* Finish filling in the object */
+				obj->gate_handle = remote_handle;
+
+				/* Fill in the local array because it is
+				 * cooked */
+				key = Gate_enterSystem();
+				gatemp_module->remote_custom2_gates[
+					obj->resource_id] = (void *)obj;
+				Gate_leaveSystem(key);
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	/* Place Name/Attrs into NameServer table */
+	if ((obj->obj_type != IPC_OBJTYPE_OPENDYNAMIC) && (retval == 0)) {
+		/* Fill in the attrs */
+		obj->attrs->arg = obj->resource_id;
+		obj->attrs->mask = \
+			SETMASK(obj->remote_protect, obj->local_protect);
+		obj->attrs->creator_proc_id = obj->creator_proc_id;
+		obj->attrs->status = GATEMP_CREATED;
+#if 0
+		if (obj->cache_enabled) {
+			Cache_wbInv(obj->attrs, sizeof(struct gatemp_attrs),
+				Cache_Type_ALL, true);
+		}
+#endif
+
+		if (params->name != NULL) {
+			shared_shm_base = sharedregion_get_srptr(obj->attrs,
+								obj->region_id);
+			ns_value[0] = (u32)shared_shm_base;
+			/*  Top 16 bits = procId of creator, Bottom 16
+			 * bits = '0' if local, '1' otherwise */
+			ns_value[1] = multiproc_self() << 16 | 1;
+			obj->ns_key = nameserver_add(gatemp_module->name_server,
+						params->name, &ns_value,
+						2 * sizeof(u32));
+			if (obj->ns_key == NULL)
+				retval = 8;
+		}
+	}
+
+	if (retval != 0) {
+		printk(KERN_ERR "gatemp_instance_init failed! status = 0x%x",
+			retval);
+	}
+	return retval;
+}
+
+void gatemp_instance_finalize(struct gatemp_object *obj, int status)
+{
+	int *system_key = (int *)0;
+	gatemp_remote_system_proxy_handle system_handle;
+	gatemp_remote_custom1_proxy_handle custom1_handle;
+	gatemp_remote_custom2_proxy_handle custom2_handle;
+	int retval = 0;
+	void **remote_handles = NULL;
+	u8 *in_use_array = NULL;
+	u32 num_resources = 0;
+
+	/* No parameter check since this function will be called internally */
+
+	/* Cannot call when numOpen is non-zero. */
+	if (obj->num_opens != 0) {
+		retval = GateMP_E_INVALIDSTATE;
+		goto exit;
+	}
+
+	/* Remove from NameServer */
+	if (obj->ns_key != 0) {
+		nameserver_remove_entry(gatemp_module->name_server,
+			obj->ns_key);
+	}
+	/* Set the status to 0 */
+	if (obj->obj_type != IPC_OBJTYPE_OPENDYNAMIC) {
+		obj->attrs->status = 0;
+#if 0
+		if (obj->cache_enabled)
+			Cache_wbInv(obj->attrs, sizeof(struct gatemp_attrs),
+					Cache_Type_ALL, true);
+#endif
+	}
+
+	/* If ObjType_LOCAL, memory was allocated from the local system heap.
+	 * obj->attrs might be NULL if the Memory_alloc failed in Instance_init
+	 */
+	if (obj->remote_protect == GATEMP_REMOTEPROTECT_NONE)
+		kfree(obj->attrs);
+
+	/* Delete if a remote gate */
+	switch (obj->remote_protect) {
+		/* Delete proxy instance... need to downCast */
+	case GATEMP_REMOTEPROTECT_SYSTEM:
+		if (obj->gate_handle) {
+			system_handle = (gatemp_remote_system_proxy_handle)
+							(obj->gate_handle);
+			gatemp_remote_system_proxy_delete(&system_handle);
+		}
+		in_use_array = gatemp_module->remote_system_in_use;
+		remote_handles = gatemp_module->remote_system_gates;
+		num_resources = gatemp_module->num_remote_system;
+		break;
+	case GATEMP_REMOTEPROTECT_CUSTOM1:
+		if (obj->gate_handle) {
+			custom1_handle = (gatemp_remote_custom1_proxy_handle)
+							(obj->gate_handle);
+			gatemp_remote_custom1_proxy_delete(&custom1_handle);
+		}
+		in_use_array = gatemp_module->remote_custom1_in_use;
+		remote_handles = gatemp_module->remote_custom1_gates;
+		num_resources = gatemp_module->num_remote_custom1;
+		break;
+	case GATEMP_REMOTEPROTECT_CUSTOM2:
+		if (obj->gate_handle) {
+			custom2_handle = (gatemp_remote_custom2_proxy_handle)
+							(obj->gate_handle);
+			gatemp_remote_custom2_proxy_delete(&custom2_handle);
+		}
+		in_use_array = gatemp_module->remote_custom2_in_use;
+		remote_handles = gatemp_module->remote_custom2_gates;
+		num_resources = gatemp_module->num_remote_custom2;
+		break;
+	case GATEMP_REMOTEPROTECT_NONE:
+		/* Nothing else to finalize. Any alloc'ed memory has already
+		 * been freed */
+		return;
+	default:
+		/* Nothing to do */
+		break;
+	}
+
+	/* Clear the handle array entry in local memory */
+	if (obj->resource_id != (uint)-1)
+		remote_handles[obj->resource_id] = NULL;
+
+	if (obj->obj_type != IPC_OBJTYPE_OPENDYNAMIC &&
+		obj->resource_id != (uint)-1) {
+		/* Only enter default gate if not deleting default gate. */
+		if (obj != gatemp_module->default_gate)
+			system_key = gatemp_enter(gatemp_module->default_gate);
+		/* Clear the resource used flag in shared memory */
+		in_use_array[obj->resource_id] = false;
+#if 0
+		if (obj->cache_enabled) {
+			Cache_wbInv(in_use_array, num_resources, Cache_Type_ALL,
+					true);
+		}
+#endif
+		/* Only leave default gate if not deleting default gate. */
+		if (obj != gatemp_module->default_gate)
+			gatemp_leave(gatemp_module->default_gate, system_key);
+	}
+
+	if (obj->obj_type == IPC_OBJTYPE_CREATEDYNAMIC_REGION) {
+		if (obj->attrs) {
+			/* Free memory allocated from the region heap */
+			sl_heap_free(sharedregion_get_heap(obj->region_id),
+					obj->attrs, obj->alloc_size);
+		}
+	}
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "gatemp_instance_finalize failed! "
+			"status = 0x%x", retval);
+	}
+	return;
+}
+
+int *gatemp_enter(void *obj)
+{
+	int *key;
+	struct gatemp_object *gmp_handle = (struct gatemp_object *)obj;
+
+	key = igateprovider_enter(gmp_handle->gate_handle);
+
+	return key;
+}
+
+void gatemp_leave(void *obj, int *key)
+{
+	struct gatemp_object *gmp_handle = (struct gatemp_object *)obj;
+
+	igateprovider_leave(gmp_handle->gate_handle, key);
+}
+
+int gatemp_open(char *name, void **handle)
+{
+	u32 *shared_shm_base;
+	int retval;
+	u32 len;
+	void *shared_addr;
+	u32 ns_value[2];
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(gatemp_module->ref_count),
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	len = sizeof(ns_value);
+	/* Get the Attrs out of the NameServer instance.
+	 * Search all processors. */
+	retval = nameserver_get(gatemp_module->name_server, name, &ns_value,
+				&len, NULL);
+	if (retval < 0) {
+		*handle = NULL;
+		return GateMP_E_NOTFOUND;
+	}
+
+	/* The least significant bit of nsValue[1] == 0 means its a
+	 * local GateMP, otherwise its a remote GateMP. */
+	if (!(ns_value[1] & 0x1) && ((ns_value[1] >> 16) != multiproc_self())) {
+		*handle = NULL;
+		return -1;
+	}
+
+	if ((ns_value[1] & 0x1) == 0) {
+		/* Opening a local GateMP locally. The GateMP is created
+		* from a local heap so don't do SharedRegion Ptr conversion. */
+		shared_addr = (u32 *)ns_value[0];
+	} else {
+		/* Opening a remote GateMP. Need to do SR ptr conversion. */
+		shared_shm_base = (u32 *)ns_value[0];
+		shared_addr = sharedregion_get_ptr(shared_shm_base);
+	}
+
+	retval = gatemp_open_by_addr(shared_addr, handle);
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "gatemp_open failed! status = 0x%x", retval);
+	return retval;
+}
+
+int gatemp_open_by_addr(void *shared_addr, void **handle)
+{
+	int retval = 0;
+	int *key;
+	struct gatemp_object *obj = NULL;
+	struct _gatemp_params params;
+	struct gatemp_attrs *attrs;
+#if 0
+	u16 region_id;
+#endif
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(gatemp_module->ref_count),
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(shared_addr == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	attrs = (struct gatemp_attrs *)shared_addr;
+
+#if 0
+	/* get the region id and invalidate attrs is needed */
+	region_id = sharedregion_get_id(shared_addr);
+	if (region_id != SHAREDREGION_INVALIDREGIONID) {
+		if (sharedregion_is_cache_enabled(region_id))
+			Cache_inv(attrs, sizeof(struct gatemp_attrs),
+				Cache_Type_ALL, true);
+	}
+#endif
+
+	if (attrs->status != GATEMP_CREATED) {
+		retval = -1;
+		goto exit;
+	}
+
+	/* Local gate */
+	if (GETREMOTE(attrs->mask) == GATEMP_REMOTEPROTECT_NONE) {
+		if (attrs->creator_proc_id != multiproc_self())
+			retval = GateMP_E_LOCALGATE; /* TBD */
+		else {
+			key = Gate_enterSystem();
+			obj = (void *)attrs->arg;
+			*handle = obj;
+			obj->num_opens++;
+			Gate_leaveSystem(key);
+		}
+	} else {
+		/* Remote case */
+		switch (GETREMOTE(attrs->mask)) {
+		case GATEMP_REMOTEPROTECT_SYSTEM:
+			obj = (struct gatemp_object *)
+				gatemp_module->remote_system_gates[attrs->arg];
+			break;
+
+		case GATEMP_REMOTEPROTECT_CUSTOM1:
+			obj = (struct gatemp_object *)
+				gatemp_module->remote_custom1_gates[attrs->arg];
+			break;
+
+		case GATEMP_REMOTEPROTECT_CUSTOM2:
+			obj = (struct gatemp_object *)
+				gatemp_module->remote_custom2_gates[attrs->arg];
+			break;
+
+		default:
+			break;
+		}
+
+		/* If the object is NULL, then it must have been created on a
+		 * remote processor. Need to create a local object. This is
+		 * accomplished by setting the open_flag to true. */
+		if ((retval == 0) && (obj == NULL)) {
+			/* Create a GateMP object with the open_flag set to
+			 * true */
+			params.name = NULL;
+			params.open_flag = true;
+			params.shared_addr = shared_addr;
+			params.resource_id = attrs->arg;
+			params.local_protect = GETLOCAL(attrs->mask);
+			params.remote_protect = GETREMOTE(attrs->mask);
+
+			obj = _gatemp_create(&params);
+			if (obj == NULL)
+				retval = GateMP_E_FAIL;
+		} else {
+			obj->num_opens++;
+		}
+
+		/* Return the "opened" GateMP instance  */
+		*handle = obj;
+	}
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "gatemp_open_by_addr failed! status = 0x%x",
+			retval);
+	}
+	return retval;
+}
+
+int gatemp_close(void **handle)
+{
+	int *key;
+	struct gatemp_object *gate_handle = NULL;
+	int count;
+	int retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(gatemp_module->ref_count),
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((handle == NULL) || (*handle == NULL)))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	gate_handle = (struct gatemp_object *)(*handle);
+	/* Cannot call with the num_opens equal to zero. This is either
+	 * a created handle or been closed already. */
+	if (unlikely(gate_handle->num_opens == 0)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	key = Gate_enterSystem();
+	count = --gate_handle->num_opens;
+	Gate_leaveSystem(key);
+
+	/* If the gate is remote, call the close function */
+	if (gate_handle->remote_protect != GATEMP_REMOTEPROTECT_NONE) {
+		/* if the count is zero and the gate is opened, then this
+		 * object was created in the open (i.e. the create happened
+		 * on a remote processor.**/
+		if ((count == 0) && \
+			(gate_handle->obj_type == IPC_OBJTYPE_OPENDYNAMIC))
+			gatemp_delete((void **)&gate_handle);
+	}
+	*handle = NULL;
+	return 0;
+
+exit:
+	printk(KERN_ERR "gatemp_close failed! status = 0x%x", retval);
+	return retval;
+}
+
+u32 *gatemp_get_shared_addr(void *obj)
+{
+	u32 *sr_ptr;
+	struct gatemp_object *object = (struct gatemp_object *) obj;
+
+	sr_ptr = sharedregion_get_srptr(object->attrs, object->region_id);
+
+	return sr_ptr;
+}
+
+bool gatemp_query(int qual)
+{
+	return false;
+}
+
+void *gatemp_get_default_remote(void)
+{
+	return gatemp_module->default_gate;
+}
+
+enum gatemp_local_protect gatemp_get_local_protect(struct gatemp_object *obj)
+{
+	WARN_ON(obj == NULL);
+
+	return obj->local_protect;
+}
+
+enum gatemp_remote_protect gatemp_get_remote_protect(struct gatemp_object *obj)
+{
+	WARN_ON(obj == NULL);
+
+	return obj->remote_protect;
+}
+
+void *gatemp_create_local(enum gatemp_local_protect local_protect)
+{
+	void *gate_handle = NULL;
+
+	/* Create the local gate. */
+	switch (local_protect) {
+	case GATEMP_LOCALPROTECT_NONE:
+		/* Plug with the GateNull singleton */
+		gate_handle = NULL;
+		break;
+
+	case GATEMP_LOCALPROTECT_INTERRUPT:
+		/* Plug with the GateHwi singleton */
+		gate_handle = gate_system_handle;
+		break;
+
+	case GATEMP_LOCALPROTECT_TASKLET:
+		/* Plug with the GateSwi singleton */
+		gate_handle = gatemp_module->gate_mutex;
+		break;
+
+	case GATEMP_LOCALPROTECT_THREAD:
+	case GATEMP_LOCALPROTECT_PROCESS:
+		/* Plug with the GateMutexPri singleton */
+		gate_handle = gatemp_module->gate_mutex;
+		break;
+
+	default:
+		break;
+	}
+
+	return gate_handle;
+}
+
+uint gatemp_shared_mem_req(const struct gatemp_params *params)
+{
+	uint mem_req, min_align;
+	u16 region_id;
+	gatemp_remote_system_proxy_params system_params;
+	gatemp_remote_custom1_proxy_params custom1_params;
+	gatemp_remote_custom2_proxy_params custom2_params;
+
+	if (params->shared_addr)
+		region_id = sharedregion_get_id(params->shared_addr);
+	else
+		region_id = params->region_id;
+
+	/*min_align = Memory_getMaxDefaultTypeAlign();*/min_align = 4;
+	if (sharedregion_get_cache_line_size(region_id) > min_align)
+		min_align = sharedregion_get_cache_line_size(region_id);
+
+	mem_req = ROUND_UP(sizeof(struct gatemp_attrs), min_align);
+
+	/* add the amount of shared memory required by proxy */
+	if (params->remote_protect == GATEMP_REMOTEPROTECT_SYSTEM) {
+		gatemp_remote_system_proxy_params_init(&system_params);
+		system_params.region_id = region_id;
+		mem_req += gatemp_remote_system_proxy_shared_mem_req(
+							&system_params);
+	} else if (params->remote_protect == GATEMP_REMOTEPROTECT_CUSTOM1) {
+		gatemp_remote_custom1_proxy_params_init(&custom1_params);
+		custom1_params.region_id = region_id;
+		mem_req += gatemp_remote_custom1_proxy_shared_mem_req(
+							&custom1_params);
+	} else if (params->remote_protect == GATEMP_REMOTEPROTECT_CUSTOM2) {
+		gatemp_remote_custom2_proxy_params_init(&custom2_params);
+		custom2_params.region_id = region_id;
+		mem_req += gatemp_remote_custom2_proxy_shared_mem_req(
+							&custom2_params);
+	}
+
+	return mem_req;
+}
+
+uint gatemp_get_region0_reserved_size(void)
+{
+	uint reserved, min_align;
+
+	/*min_align = Memory_getMaxDefaultTypeAlign();*/min_align = 4;
+
+	if (sharedregion_get_cache_line_size(0) > min_align)
+		min_align = sharedregion_get_cache_line_size(0);
+
+	reserved = ROUND_UP(sizeof(struct gatemp_reserved), min_align);
+
+	reserved += ROUND_UP(gatemp_module->num_remote_system, min_align);
+
+	if (gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM1] ==
+			GATEMP_PROXYORDER_CUSTOM1) {
+		reserved += ROUND_UP(gatemp_module->num_remote_custom1,
+					min_align);
+	}
+
+	if (gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM2] ==
+			GATEMP_PROXYORDER_CUSTOM2) {
+		reserved += ROUND_UP(gatemp_module->num_remote_custom2,
+					min_align);
+	}
+
+	return reserved;
+}
+
+static void gatemp_set_region0_reserved(void *shared_addr)
+{
+	struct gatemp_reserved *reserve;
+	u32 min_align, offset;
+
+	/*min_align = Memory_getMaxDefaultTypeAlign();*/min_align = 4;
+	if (sharedregion_get_cache_line_size(0) > min_align)
+		min_align = sharedregion_get_cache_line_size(0);
+
+	/* setup struct gatemp_reserved fields */
+	reserve = (struct gatemp_reserved *)shared_addr;
+	reserve->version = GATEMP_VERSION;
+
+	if (sharedregion_is_cache_enabled(0)) {
+#if 0
+		Cache_wbInv(shared_addr, sizeof(struct gatemp_reserved),
+			Cache_Type_ALL, true);
+#endif
+	}
+
+	/* initialize the in-use array in shared memory for the system gates. */
+	offset = ROUND_UP(sizeof(struct gatemp_reserved), min_align);
+	gatemp_module->remote_system_in_use =
+					(void *)((u32)shared_addr + offset);
+	memset(gatemp_module->remote_system_in_use, 0,
+			gatemp_module->num_remote_system);
+
+	if (sharedregion_is_cache_enabled(0)) {
+#if 0
+		Cache_wbInv(gatemp_module->remote_system_in_use,
+				gatemp_module->num_remote_system,
+				Cache_Type_ALL, true);
+#endif
+	}
+
+	/* initialize the in-use array in shared memory for the custom1 gates.
+	 * Need to check if this proxy is the same as system */
+	offset = ROUND_UP(gatemp_module->num_remote_system, min_align);
+	if (gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM1] ==
+			GATEMP_PROXYORDER_CUSTOM1) {
+		if (gatemp_module->num_remote_custom1 != 0) {
+			gatemp_module->remote_custom1_in_use =
+				gatemp_module->remote_system_in_use + offset;
+		}
+
+		memset(gatemp_module->remote_custom1_in_use, 0,
+			gatemp_module->num_remote_custom1);
+
+		if (sharedregion_is_cache_enabled(0)) {
+#if 0
+			Cache_wbInv(gatemp_module->remote_custom1_in_use,
+					gatemp_module->num_remote_custom1,
+					Cache_Type_ALL, true);
+#endif
+		}
+	} else {
+		gatemp_module->remote_custom1_in_use = \
+					gatemp_module->remote_system_in_use;
+		gatemp_module->remote_custom1_gates = \
+					gatemp_module->remote_system_gates;
+	}
+
+	/*  initialize the in-use array in shared memory for the custom2 gates.
+	 *  Need to check if this proxy is the same as system or custom1 */
+	offset = ROUND_UP(gatemp_module->num_remote_custom1, min_align);
+	if (gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM2] ==
+			GATEMP_PROXYORDER_CUSTOM2) {
+		if (gatemp_module->num_remote_custom2 != 0) {
+			gatemp_module->remote_custom2_in_use =
+				gatemp_module->remote_custom1_in_use + offset;
+		}
+		memset(gatemp_module->remote_custom2_in_use, 0,
+			gatemp_module->num_remote_custom2);
+
+		if (sharedregion_is_cache_enabled(0)) {
+#if 0
+			Cache_wbInv(gatemp_module->remote_custom2_in_use,
+					gatemp_module->num_remote_custom2,
+					Cache_Type_ALL, true);
+#endif
+		}
+	} else if (gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM2] ==
+			GATEMP_PROXYORDER_CUSTOM1) {
+		gatemp_module->remote_custom2_in_use =
+				gatemp_module->remote_custom1_in_use;
+		gatemp_module->remote_custom2_gates =
+				gatemp_module->remote_custom1_gates;
+	} else {
+		gatemp_module->remote_custom2_in_use = \
+				gatemp_module->remote_system_in_use;
+		gatemp_module->remote_custom2_gates = \
+				gatemp_module->remote_system_gates;
+	}
+
+	return;
+}
+
+static void gatemp_clear_region0_reserved(void)
+{
+	printk(KERN_INFO "gatemp_clear_region0_reserved: either nothing to do "
+		"or not implemented");
+}
+
+static void gatemp_open_region0_reserved(void *shared_addr)
+{
+	struct gatemp_reserved *reserve;
+	u32 min_align, offset;
+
+	/*min_align = Memory_getMaxDefaultTypeAlign();*/min_align = 4;
+	if (sharedregion_get_cache_line_size(0) > min_align)
+		min_align = sharedregion_get_cache_line_size(0);
+
+
+	/* setup struct gatemp_reserved fields */
+	reserve = (struct gatemp_reserved *)shared_addr;
+
+	if (reserve->version != GATEMP_VERSION) {
+		/* TBD */
+		return;
+	}
+
+	offset = ROUND_UP(sizeof(struct gatemp_reserved), min_align);
+	gatemp_module->remote_system_in_use = \
+				(void *)((u32)shared_addr + offset);
+
+	/* initialize the in-use array in shared memory for the custom1 gates.
+	 *  Need to check if this proxy is the same as system */
+	offset = ROUND_UP(gatemp_module->num_remote_system, min_align);
+	if (gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM1] ==
+			GATEMP_PROXYORDER_CUSTOM1) {
+		if (gatemp_module->num_remote_custom1 != 0) {
+			gatemp_module->remote_custom1_in_use =
+				gatemp_module->remote_system_in_use + offset;
+		}
+	} else {
+		gatemp_module->remote_custom1_in_use = \
+				gatemp_module->remote_system_in_use;
+		gatemp_module->remote_custom1_gates = \
+				gatemp_module->remote_system_gates;
+	}
+
+	offset = ROUND_UP(gatemp_module->num_remote_custom1, min_align);
+	if (gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM2] ==
+			GATEMP_PROXYORDER_CUSTOM2) {
+		if (gatemp_module->num_remote_custom2 != 0) {
+			gatemp_module->remote_custom2_in_use =
+				gatemp_module->remote_custom1_in_use + offset;
+		}
+	} else if (gatemp_module->proxy_map[GATEMP_PROXYORDER_CUSTOM2] ==
+			GATEMP_PROXYORDER_CUSTOM1) {
+		gatemp_module->remote_custom2_in_use =
+				gatemp_module->remote_custom1_in_use;
+		gatemp_module->remote_custom2_gates =
+				gatemp_module->remote_custom1_gates;
+	} else {
+		gatemp_module->remote_custom2_in_use = \
+				gatemp_module->remote_system_in_use;
+		gatemp_module->remote_custom2_gates = \
+				gatemp_module->remote_system_gates;
+	}
+
+	return;
+}
+
+static void gatemp_close_region0_reserved(void *shared_addr)
+{
+	printk(KERN_INFO "gatemp_close_region0_reserved: either nothing to do "
+		"or not implemented");
+}
+
+static void gatemp_set_default_remote(void *handle)
+{
+	gatemp_module->default_gate = handle;
+}
+
+int gatemp_start(void *shared_addr)
+{
+	struct sharedregion_entry entry;
+	struct gatemp_params gatemp_params;
+	void *default_gate;
+	int retval = 0;
+
+	/* get region 0 information */
+	sharedregion_get_entry(0, &entry);
+
+	/* if entry owner proc is not specified return */
+	if (entry.owner_proc_id != SHAREDREGION_DEFAULTOWNERID) {
+		if (entry.owner_proc_id == multiproc_self()) {
+			/* Intialize the locks if ncessary.*/
+			gatemp_remote_system_proxy_locks_init();
+			gatemp_remote_custom1_proxy_locks_init();
+			gatemp_remote_custom2_proxy_locks_init();
+		}
+
+		/* Init params for default gate */
+		gatemp_params_init(&gatemp_params);
+		gatemp_params.shared_addr = (void *)((u32)shared_addr +
+					gatemp_get_region0_reserved_size());
+		gatemp_params.local_protect = GATEMP_LOCALPROTECT_TASKLET;
+
+		if (multiproc_get_num_processors() > 1) {
+			gatemp_params.remote_protect = \
+						GATEMP_REMOTEPROTECT_SYSTEM;
+		} else {
+			gatemp_params.remote_protect = \
+						GATEMP_REMOTEPROTECT_NONE;
+		}
+
+		if (entry.owner_proc_id == multiproc_self()) {
+			gatemp_module->is_owner = true;
+
+			/* if owner of the SharedRegion */
+			gatemp_set_region0_reserved(shared_addr);
+
+			/* create default GateMP */
+			default_gate = gatemp_create(&gatemp_params);
+
+			if (default_gate != NULL) {
+				/* set the default GateMP for creator */
+				gatemp_set_default_remote(default_gate);
+			} else {
+				retval = -1;
+			}
+		}
+	}
+
+	if (retval < 0)
+		printk(KERN_ERR "gatemp_start failed! status = 0x%x", retval);
+	return retval;
+}
+
+int gatemp_stop(void)
+{
+	int retval = 0;
+
+	/* if entry owner proc is not specified return */
+	if (gatemp_module->is_owner == true) {
+		/* if owner of the SharedRegion */
+		gatemp_clear_region0_reserved();
+
+		gatemp_delete((void **)&gatemp_module->default_gate);
+
+		/* set the default GateMP for creator */
+		gatemp_set_default_remote(NULL);
+	}
+
+	return retval;
+}
+
+
+/*
+ *************************************************************************
+ *      Internal functions
+ *************************************************************************
+ */
+uint gatemp_get_free_resource(u8 *in_use, int num)
+{
+	int *key = 0;
+	bool flag = false;
+	uint resource_id;
+	void *default_gate;
+
+	/* Need to look at shared memory. Enter default gate */
+	default_gate = gatemp_get_default_remote();
+
+	if (default_gate)
+		key = gatemp_enter(default_gate);
+
+#if 0
+	/* Invalidate cache before looking at the in-use flags */
+	if (sharedregion_is_cache_enabled(0))
+		Cache_inv(in_use, num * sizeof(u8), Cache_Type_ALL, true);
+#endif
+
+	/* Find a free resource id. Note: zero is reserved on the
+	 * system proxy for the default gate. */
+	for (resource_id = 0; resource_id < num; resource_id++) {
+		/* If not in-use, set the in_use to true to prevent other
+		 * creates from getting this one. */
+		if (in_use[resource_id] == false) {
+			flag = true;
+
+			/* Denote in shared memory that the resource is used */
+			in_use[resource_id] = true;
+			break;
+		}
+	}
+
+#if 0
+	/* Write-back if a in-use flag was changed */
+	if (flag == true && sharedregion_is_cache_enabled(0))
+		Cache_wbInv(in_use, num * sizeof(u8), Cache_Type_ALL, true);
+#endif
+
+	/* Done with the critical section */
+	if (default_gate)
+		gatemp_leave(default_gate, key);
+
+	if (flag == false)
+		resource_id = -1;
+
+	return resource_id;
+}
+
+void *gatemp_create(const struct gatemp_params *params)
+{
+	struct _gatemp_params _params;
+	struct gatemp_object *handle = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(gatemp_module->ref_count),
+			GATEMP_MAKE_MAGICSTAMP(0),
+			GATEMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params->shared_addr == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	memset(&_params, 0, sizeof(struct _gatemp_params));
+	memcpy(&_params, params, sizeof(struct gatemp_params));
+
+	handle = _gatemp_create(&_params);
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "gatemp_create failed! status = 0x%x", retval);
+	return (void *)handle;
+}
+
+static struct gatemp_object *_gatemp_create(const struct _gatemp_params *params)
+{
+	struct gatemp_object *obj = NULL;
+	s32 retval = 0;
+	int *key;
+
+	/* No parameter checking since internal function */
+
+	obj = kmalloc(sizeof(struct gatemp_object), GFP_KERNEL);
+	if (obj == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+
+	obj->status = gatemp_instance_init(obj, params);
+	if (obj->status != 0) {
+		retval = -1;
+		goto gatemp_init_fail;
+	}
+
+	key = Gate_enterSystem();
+	if (gatemp_first_object == NULL) {
+		gatemp_first_object = obj;
+		obj->next = NULL;
+	} else {
+		obj->next = gatemp_first_object;
+		gatemp_first_object = obj;
+	}
+	Gate_leaveSystem(key);
+	return (void *)obj;
+
+gatemp_init_fail:
+	kfree(obj);
+	obj = NULL;
+exit:
+	printk(KERN_ERR "_gatemp_create failed! status = 0x%x", retval);
+	return (void *)NULL;
+}
+
+int gatemp_delete(void **handle)
+{
+	int *key;
+	struct gatemp_object *temp;
+	bool found = false;
+	int retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(gatemp_module->ref_count),
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((handle == NULL) || (*handle == NULL)))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	key = Gate_enterSystem();
+	if ((struct gatemp_object *)*handle == gatemp_first_object) {
+		gatemp_first_object = ((struct gatemp_object *)(*handle))->next;
+		found = true;
+	} else {
+		temp = gatemp_first_object;
+		while (temp) {
+			if (temp->next == (struct gatemp_object *)(*handle)) {
+				temp->next = ((struct gatemp_object *)
+							(*handle))->next;
+				found = true;
+				break;
+			} else {
+				temp = temp->next;
+			}
+		}
+	}
+	Gate_leaveSystem(key);
+
+	if (found == false) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	gatemp_instance_finalize(*handle, ((struct gatemp_object *)
+							(*handle))->status);
+	kfree((*handle));
+	*handle = NULL;
+	return 0;
+
+exit:
+	printk(KERN_ERR "gatemp_delete failed! status = 0x%x", retval);
+	return retval;
+}
+
+int gatemp_attach(u16 remote_proc_id, void *shared_addr)
+{
+	int retval = 0;
+	void *gatemp_shared_addr;
+	struct sharedregion_entry entry;
+	void *default_gate;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(gatemp_module->ref_count),
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(shared_addr == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (atomic_inc_return(&gatemp_module->attach_ref_count) != 1)
+		return 1;
+
+	/* get region 0 information */
+	sharedregion_get_entry(0, &entry);
+
+	gatemp_shared_addr = (void *)((u32)shared_addr +
+					gatemp_get_region0_reserved_size());
+
+	if ((entry.owner_proc_id != multiproc_self()) &&
+		(entry.owner_proc_id != SHAREDREGION_DEFAULTOWNERID)) {
+		gatemp_module->is_owner = false;
+
+		/* if not the owner of the SharedRegion */
+		gatemp_open_region0_reserved(shared_addr);
+
+		/* open the gate by address */
+		retval = gatemp_open_by_addr(gatemp_shared_addr, &default_gate);
+		/* set the default GateMP for opener */
+		if (retval >= 0)
+			gatemp_set_default_remote(default_gate);
+	}
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "gatemp_attach failed! status = 0x%x", retval);
+	return retval;
+}
+
+int gatemp_detach(u16 remote_proc_id, void *shared_addr)
+{
+	int retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(gatemp_module->ref_count),
+				GATEMP_MAKE_MAGICSTAMP(0),
+				GATEMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(shared_addr == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (!(atomic_dec_return(&gatemp_module->attach_ref_count) == 0))
+		return 1;
+
+	/* if entry owner proc is not specified return */
+	if (gatemp_module->is_owner == false) {
+		gatemp_close_region0_reserved(shared_addr);
+
+		retval = gatemp_close((void **)&gatemp_module->default_gate);
+
+		/* set the default GateMP for opener */
+		gatemp_set_default_remote(NULL);
+	}
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "gatemp_detach failed! status = 0x%x", retval);
+	return retval;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/gatemp_ioctl.c b/drivers/dsp/syslink/multicore_ipc/gatemp_ioctl.c
new file mode 100644
index 000000000000..7270a76774b9
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/gatemp_ioctl.c
@@ -0,0 +1,356 @@
+/*
+ *  gatemp_ioctl.c
+ *
+ *  The Gate Peterson Algorithm for mutual exclusion of shared memory.
+ *  Current implementation works for 2 processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/uaccess.h>
+#include <linux/types.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+#include <gatemp.h>
+#include <gatemp_ioctl.h>
+#include <sharedregion.h>
+
+/* ioctl interface to gatemp_get_config function*/
+static int gatemp_ioctl_get_config(struct gatemp_cmd_args *cargs)
+{
+	struct gatemp_config config;
+	s32 status = 0;
+	s32 size;
+
+	gatemp_get_config(&config);
+	size = copy_to_user(cargs->args.get_config.config, &config,
+				sizeof(struct gatemp_config));
+	if (size)
+		status = -EFAULT;
+
+	cargs->api_status = 0;
+	return status;
+}
+
+/* ioctl interface to gatemp_setup function */
+static int gatemp_ioctl_setup(struct gatemp_cmd_args *cargs)
+{
+	struct gatemp_config config;
+	s32 status = 0;
+	s32 size;
+
+	size = copy_from_user(&config, cargs->args.setup.config,
+				sizeof(struct gatemp_config));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = gatemp_setup(&config);
+
+exit:
+	return status;
+}
+
+/* ioctl interface to gatemp_destroy function */
+static int gatemp_ioctl_destroy(struct gatemp_cmd_args *cargs)
+{
+	cargs->api_status = gatemp_destroy();
+	return 0;
+}
+
+/* ioctl interface to gatemp_params_init function */
+static int gatemp_ioctl_params_init(struct gatemp_cmd_args *cargs)
+{
+	struct gatemp_params params;
+	s32 status = 0;
+	s32 size;
+
+	gatemp_params_init(&params);
+	size = copy_to_user(cargs->args.params_init.params, &params,
+					sizeof(struct gatemp_params));
+	if (size)
+		status = -EFAULT;
+
+	cargs->api_status = 0;
+	return status;
+}
+
+/* ioctl interface to gatemp_create function */
+static int gatemp_ioctl_create(struct gatemp_cmd_args *cargs)
+{
+	struct gatemp_params params;
+	s32 status = 0;
+	s32 size;
+
+	cargs->api_status = -1;
+	size = copy_from_user(&params, cargs->args.create.params,
+					sizeof(struct gatemp_params));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	if (cargs->args.create.name_len > 0) {
+		params.name = kmalloc(cargs->args.create.name_len, GFP_KERNEL);
+		if (params.name == NULL) {
+			status = -ENOMEM;
+			goto exit;
+		}
+
+		params.name[cargs->args.create.name_len] = '\0';
+		size = copy_from_user(params.name,
+					cargs->args.create.params->name,
+					cargs->args.create.name_len);
+		if (size) {
+			status = -EFAULT;
+			goto name_from_usr_error;
+		}
+
+	}
+
+	params.shared_addr = sharedregion_get_ptr(
+				(u32 *)cargs->args.create.shared_addr_srptr);
+	cargs->args.create.handle = gatemp_create(&params);
+	if (cargs->args.create.handle != NULL)
+		cargs->api_status = 0;
+
+name_from_usr_error:
+	if (cargs->args.open.name_len > 0)
+		kfree(params.name);
+
+exit:
+	return status;
+}
+
+/* ioctl interface to gatemp_ioctl_delete function */
+static int gatemp_ioctl_delete(struct gatemp_cmd_args *cargs)
+
+{
+	cargs->api_status = gatemp_delete(&cargs->args.delete_instance.handle);
+	return 0;
+}
+
+/* ioctl interface to gatemp_open function */
+static int gatemp_ioctl_open(struct gatemp_cmd_args *cargs)
+{
+	struct gatemp_params params;
+	void *handle = NULL;
+	s32 status = 0;
+	s32 size;
+
+	gatemp_params_init(&params);
+	if (cargs->args.open.name_len > 0) {
+		params.name = kmalloc(cargs->args.open.name_len, GFP_KERNEL);
+		if (params.name == NULL) {
+			status = -ENOMEM;
+			goto exit;
+		}
+
+		params.name[cargs->args.open.name_len] = '\0';
+		size = copy_from_user(params.name,
+					cargs->args.open.name,
+					cargs->args.open.name_len);
+		if (size) {
+			status = -EFAULT;
+			goto name_from_usr_error;
+		}
+	}
+
+	cargs->api_status = gatemp_open(params.name, &handle);
+	cargs->args.open.handle = handle;
+
+name_from_usr_error:
+	if (cargs->args.open.name_len > 0)
+		kfree(params.name);
+
+exit:
+	return status;
+}
+
+/* ioctl interface to gatemp_close function */
+static int gatemp_ioctl_close(struct gatemp_cmd_args *cargs)
+{
+	cargs->api_status = gatemp_close(&cargs->args.close.handle);
+	return 0;
+}
+
+/* ioctl interface to gatemp_enter function */
+static int gatemp_ioctl_enter(struct gatemp_cmd_args *cargs)
+{
+	cargs->args.enter.flags = gatemp_enter(cargs->args.enter.handle);
+	cargs->api_status = 0;
+	return 0;
+}
+
+/* ioctl interface to gatemp_leave function */
+static int gatemp_ioctl_leave(struct gatemp_cmd_args *cargs)
+{
+	gatemp_leave(cargs->args.leave.handle, cargs->args.leave.flags);
+	cargs->api_status = 0;
+	return 0;
+}
+
+/* ioctl interface to gatemp_shared_mem_req function */
+static int gatemp_ioctl_shared_mem_req(struct gatemp_cmd_args *cargs)
+{
+	struct gatemp_params params;
+	s32 status = 0;
+	s32 size;
+
+	size = copy_from_user(&params, cargs->args.shared_mem_req.params,
+					sizeof(struct gatemp_params));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	cargs->args.shared_mem_req.ret_val =
+		gatemp_shared_mem_req(cargs->args.shared_mem_req.params);
+	cargs->api_status = 0;
+
+exit:
+	return status;
+}
+
+/* ioctl interface to gatemp_open_by_addr function */
+static int gatemp_ioctl_open_by_addr(struct gatemp_cmd_args *cargs)
+{
+	void *shared_addr;
+	void *handle = NULL;
+	s32 status = 0;
+
+	/* For open by name, the shared_add_srptr may be invalid */
+	if (cargs->args.open_by_addr.shared_addr_srptr != \
+					SHAREDREGION_INVALIDSRPTR) {
+		shared_addr = sharedregion_get_ptr((u32 *)cargs->args.
+						open_by_addr.shared_addr_srptr);
+	}
+	cargs->api_status = gatemp_open_by_addr(shared_addr, &handle);
+	cargs->args.open.handle = handle;
+
+	return status;
+}
+
+/* ioctl interface to gatemp_ioctl_get_default_remote function */
+static int gatemp_ioctl_get_default_remote(struct gatemp_cmd_args *cargs)
+{
+	void *handle = NULL;
+
+	handle = gatemp_get_default_remote();
+	cargs->args.get_default_remote.handle = handle;
+	cargs->api_status = 0;
+
+	return 0;
+}
+
+/* ioctl interface for gatemp module */
+int gatemp_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args)
+{
+	s32 status = 0;
+	s32 size = 0;
+	struct gatemp_cmd_args __user *uarg =
+				(struct gatemp_cmd_args __user *)args;
+	struct gatemp_cmd_args cargs;
+
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+
+	if (status) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg,
+					sizeof(struct gatemp_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_GATEMP_GETCONFIG:
+		status = gatemp_ioctl_get_config(&cargs);
+		break;
+
+	case CMD_GATEMP_SETUP:
+		status = gatemp_ioctl_setup(&cargs);
+		break;
+
+	case CMD_GATEMP_DESTROY:
+		status = gatemp_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_GATEMP_PARAMS_INIT:
+		status  = gatemp_ioctl_params_init(&cargs);
+		break;
+
+	case CMD_GATEMP_CREATE:
+		status = gatemp_ioctl_create(&cargs);
+		break;
+
+	case CMD_GATEMP_DELETE:
+		status = gatemp_ioctl_delete(&cargs);
+		break;
+
+	case CMD_GATEMP_OPEN:
+		status = gatemp_ioctl_open(&cargs);
+		break;
+
+	case CMD_GATEMP_CLOSE:
+		status = gatemp_ioctl_close(&cargs);
+		break;
+
+	case CMD_GATEMP_ENTER:
+		status = gatemp_ioctl_enter(&cargs);
+		break;
+
+	case CMD_GATEMP_LEAVE:
+		status = gatemp_ioctl_leave(&cargs);
+		break;
+
+	case CMD_GATEMP_SHAREDMEMREQ:
+		status = gatemp_ioctl_shared_mem_req(&cargs);
+		break;
+
+	case CMD_GATEMP_OPENBYADDR:
+		status = gatemp_ioctl_open_by_addr(&cargs);
+		break;
+
+	case CMD_GATEMP_GETDEFAULTREMOTE:
+		status = gatemp_ioctl_get_default_remote(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		status = -ENOTTY;
+		break;
+	}
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs, sizeof(struct gatemp_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+exit:
+	return status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/gatepeterson.c b/drivers/dsp/syslink/multicore_ipc/gatepeterson.c
new file mode 100644
index 000000000000..d49561759f75
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/gatepeterson.c
@@ -0,0 +1,1004 @@
+/*
+ *  gatepeterson.c
+ *
+ *  The Gate Peterson Algorithm for mutual exclusion of shared memory.
+ *  Current implementation works for 2 processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <syslink/atomic_linux.h>
+#include <multiproc.h>
+#include <sharedregion.h>
+#include <gatemp.h>
+#include <igatempsupport.h>
+#include <igateprovider.h>
+#include <iobject.h>
+#include <gatepeterson.h>
+
+
+/* IPC stubs */
+
+#define GATEPETERSON_BUSY		1
+#define GATEPETERSON_FREE		0
+#define GATEPETERSON_VERSION		1
+#define GATEPETERSON_CREATED		0x08201997 /* Stamp to indicate GP
+							was created here */
+
+/* Cache line size */
+#define GATEPETERSON_CACHESIZE		128
+
+/* Macro to make a correct module magic number with ref_count */
+#define GATEPETERSON_MAKE_MAGICSTAMP(x) ((GATEPETERSON_MODULEID << 12) | (x))
+
+/*
+ *  structure for gatepeterson module state
+ */
+struct gatepeterson_module_object {
+	atomic_t ref_count; /* Reference count */
+	struct list_head obj_list;
+	struct mutex *mod_lock; /* Lock for obj list */
+	struct gatepeterson_config cfg;
+	struct gatepeterson_config default_cfg;
+	struct gatepeterson_params def_inst_params; /* default instance
+							paramters */
+};
+
+/*
+ *  Structure defining attribute parameters for the Gate Peterson module
+ */
+struct gatepeterson_attrs {
+	VOLATILE u16 creator_proc_id;
+	VOLATILE  u16 opener_proc_id;
+};
+
+/*
+ *  Structure defining internal object for the Gate Peterson
+ */
+struct gatepeterson_object {
+	IGATEPROVIDER_SUPEROBJECT; /* For inheritance from IGateProvider */
+	IOBJECT_SUPEROBJECT;       /* For inheritance for IObject */
+	struct list_head elem;
+	VOLATILE struct gatepeterson_attrs *attrs; /* Instance attr */
+	VOLATILE u16 *flag[2]; /* Flags for processors */
+	VOLATILE u16 *turn; /* Indicates whoes turn it is now? */
+	u16 self_id; /* Self identifier */
+	u16 other_id; /* Other's identifier */
+	u32 nested; /* Counter to track nesting */
+	void *local_gate; /* Local lock handle */
+	enum igatempsupport_local_protect local_protect; /* Type of local
+						protection to be used */
+	struct gatepeterson_params params;
+	u32 ref_count; /* Local reference count */
+	u32 cache_line_size; /* Cache Line Size */
+	bool cache_enabled; /* Is cache enabled? */
+};
+
+
+/*
+ *  Variable for holding state of the gatepeterson module
+ */
+struct gatepeterson_module_object gatepeterson_state = {
+	.obj_list	 = LIST_HEAD_INIT(gatepeterson_state.obj_list),
+	.default_cfg.default_protection = GATEPETERSON_PROTECT_INTERRUPT,
+	.default_cfg.num_instances	= 16,
+	.def_inst_params.shared_addr	= 0x0,
+	.def_inst_params.resource_id	= 0x0,
+	.def_inst_params.region_id	= 0x0
+};
+
+static struct gatepeterson_module_object *gatepeterson_module =
+						&gatepeterson_state;
+
+/* =============================================================================
+ * Internal functions
+ * =============================================================================
+ */
+#if 0
+static void *_gatepeterson_create(enum igatempsupport_local_protect
+							local_protect,
+				const struct gatepeterson_params *params,
+				bool create_flag);
+#endif
+
+static void gatepeterson_post_init(struct gatepeterson_object *obj);
+
+#if 0
+static bool gatepeterson_inc_refcount(const struct gatepeterson_params *params,
+					void **handle);
+#endif
+
+/* TODO: figure these out */
+#define gate_enter_system() 0
+#define gate_leave_system(key) {}
+
+/* =============================================================================
+ * APIS
+ * =============================================================================
+ */
+/*
+ * ======== gatepeterson_get_config ========
+ *  Purpose:
+ *  This will get the default configuration parameters for gatepeterson
+ *  module
+ */
+void gatepeterson_get_config(struct gatepeterson_config *config)
+{
+	if (WARN_ON(config == NULL))
+		goto exit;
+
+	if (atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+				GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true)
+		memcpy(config, &gatepeterson_module->default_cfg,
+					sizeof(struct gatepeterson_config));
+	else
+		memcpy(config, &gatepeterson_module->cfg,
+					sizeof(struct gatepeterson_config));
+
+exit:
+	return;
+}
+EXPORT_SYMBOL(gatepeterson_get_config);
+
+/*
+ * ======== gatepeterson_setup ========
+ *  Purpose:
+ *  This will setup the gatepeterson module
+ */
+int gatepeterson_setup(const struct gatepeterson_config *config)
+{
+	struct gatepeterson_config tmp_cfg;
+	int *key = 0;
+	s32 retval = 0;
+
+	key = gate_enter_system();
+
+	/* This sets the ref_count variable  not initialized, upper 16 bits is
+	* written with module _id to ensure correctness of ref_count variable
+	*/
+	atomic_cmpmask_and_set(&gatepeterson_module->ref_count,
+					GATEPETERSON_MAKE_MAGICSTAMP(0),
+					GATEPETERSON_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&gatepeterson_module->ref_count)
+					!= GATEPETERSON_MAKE_MAGICSTAMP(1)) {
+		gate_leave_system(key);
+		return 1;
+	}
+
+	if (config == NULL) {
+		gatepeterson_get_config(&tmp_cfg);
+		config = &tmp_cfg;
+	}
+	gate_leave_system(key);
+
+	memcpy(&gatepeterson_module->cfg, config,
+					sizeof(struct gatepeterson_config));
+
+	gatepeterson_module->mod_lock = kmalloc(sizeof(struct mutex),
+								GFP_KERNEL);
+	if (gatepeterson_module->mod_lock == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+	mutex_init(gatepeterson_module->mod_lock);
+
+	/* Initialize object list */
+	INIT_LIST_HEAD(&gatepeterson_module->obj_list);
+
+	return 0;
+
+exit:
+	atomic_set(&gatepeterson_module->ref_count,
+				GATEPETERSON_MAKE_MAGICSTAMP(0));
+
+	printk(KERN_ERR	"gatepeterson_setup failed status: %x\n",
+			retval);
+	return retval;
+}
+EXPORT_SYMBOL(gatepeterson_setup);
+
+/*
+ * ======== gatepeterson_destroy ========
+ *  Purpose:
+ *  This will destroy the gatepeterson module
+ */
+int gatepeterson_destroy(void)
+{
+	struct gatepeterson_object *obj = NULL;
+	struct mutex *lock = NULL;
+	s32 retval = 0;
+	int *key = 0;
+
+	key = gate_enter_system();
+
+	if (atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+				GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (!(atomic_dec_return(&gatepeterson_module->ref_count)
+			== GATEPETERSON_MAKE_MAGICSTAMP(0))) {
+		gate_leave_system(key);
+		retval = 1;
+		goto exit;
+	}
+	atomic_set(&gatepeterson_module->ref_count,
+				GATEPETERSON_MAKE_MAGICSTAMP(1));
+	/* Check if any gatepeterson instances have not been
+	*  ideleted/closed so far, if there any, delete or close them
+	*/
+	list_for_each_entry(obj, &gatepeterson_module->obj_list, elem) {
+		gatepeterson_delete((void **)&obj);
+
+		if (list_empty(&gatepeterson_module->obj_list))
+			break;
+	}
+
+	/* Again reset ref_count. */
+	atomic_set(&gatepeterson_module->ref_count,
+				GATEPETERSON_MAKE_MAGICSTAMP(0));
+	gate_leave_system(key);
+
+	retval = mutex_lock_interruptible(gatepeterson_module->mod_lock);
+	if (retval != 0)
+		goto exit;
+
+	lock = gatepeterson_module->mod_lock;
+	gatepeterson_module->mod_lock = NULL;
+	memset(&gatepeterson_module->cfg, 0,
+			sizeof(struct gatepeterson_config));
+	mutex_unlock(lock);
+	kfree(lock);
+	return 0;
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "gatepeterson_destroy failed status:%x\n",
+			retval);
+	}
+	return retval;
+
+}
+EXPORT_SYMBOL(gatepeterson_destroy);
+
+/*
+ * ======== gatepeterson_get_num_instances ========
+ *  Purpose:
+ *  Function to return the number of instances configured in the module.
+ */
+u32 gatepeterson_get_num_instances(void)
+{
+	return gatepeterson_module->default_cfg.num_instances;
+}
+EXPORT_SYMBOL(gatepeterson_get_num_instances);
+
+/*
+ * ======== gatepeterson_locks_init ========
+ *  Purpose:
+ *  Function to initialize the locks.
+ */
+inline void gatepeterson_locks_init(void)
+{
+	/* Do nothing*/
+}
+
+/*
+ * ======== gatepeterson_params_init ========
+ *  Purpose:
+ *  This will  Initialize this config-params structure with
+ *  supplier-specified defaults before instance creation
+ */
+void gatepeterson_params_init(struct gatepeterson_params *params)
+{
+	int *key = 0;
+
+	key = gate_enter_system();
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+				GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true))
+		goto exit;
+
+	if (WARN_ON(params == NULL))
+		goto exit;
+
+	memcpy(params, &(gatepeterson_module->def_inst_params),
+				sizeof(struct gatepeterson_params));
+
+exit:
+	gate_leave_system(key);
+	return;
+}
+EXPORT_SYMBOL(gatepeterson_params_init);
+
+
+int gatepeterson_instance_init(struct gatepeterson_object *obj,
+		enum igatempsupport_local_protect local_protect,
+		const struct gatepeterson_params *params)
+{
+	s32 retval = 0;
+
+	IGATEPROVIDER_OBJECTINITIALIZER(obj, gatepeterson);
+
+	if (params->shared_addr == NULL) {
+		retval = 1;
+		goto exit;
+	}
+
+	/* Create the local gate */
+	obj->local_gate = gatemp_create_local(local_protect);
+	obj->cache_enabled  = sharedregion_is_cache_enabled(params->region_id);
+	obj->cache_line_size =
+		sharedregion_get_cache_line_size(params->region_id);
+
+	/* Settings for both the creator and opener */
+	if (obj->cache_line_size > sizeof(struct gatepeterson_attrs)) {
+		obj->attrs   = params->shared_addr;
+		obj->flag[0] = (u16 *)((u32)(obj->attrs) +
+							obj->cache_line_size);
+		obj->flag[1] = (u16 *)((u32)(obj->flag[0]) +
+							obj->cache_line_size);
+		obj->turn = (u16 *)((u32)(obj->flag[1]) +
+							obj->cache_line_size);
+	} else {
+		obj->attrs   = params->shared_addr;
+		obj->flag[0] = (u16 *)((u32)(obj->attrs) +
+					sizeof(struct gatepeterson_attrs));
+		obj->flag[1] = (u16 *)((u32)(obj->flag[0]) + sizeof(u16));
+		obj->turn	= (u16 *)((u32)(obj->flag[1]) + sizeof(u16));
+	}
+	obj->nested  = 0;
+
+	if (!params->open_flag) {
+		/* Creating. */
+		obj->self_id = 0;
+		obj->other_id = 1;
+		gatepeterson_post_init(obj);
+	} else {
+#if 0
+		Cache_inv((Ptr)obj->attrs, sizeof(struct gatepeterson_attrs),
+				Cache_Type_ALL, TRUE);
+#endif
+		if (obj->attrs->creator_proc_id == multiproc_self()) {
+			/* Opening locally */
+			obj->self_id	= 0;
+			obj->other_id	= 1;
+		} else {
+			/* Trying to open a gate remotely */
+			obj->self_id	= 1;
+			obj->other_id	= 0;
+			if (obj->attrs->opener_proc_id == MULTIPROC_INVALIDID) {
+				/* Opening remotely for the first time */
+				obj->attrs->opener_proc_id = multiproc_self();
+			} else if (obj->attrs->opener_proc_id !=
+							multiproc_self()) {
+				retval = -EACCES;
+				goto exit;
+			}
+#if 0
+			if (obj->cache_enabled) {
+				Cache_wbInv((Ptr)obj->attrs,
+					sizeof(struct gatepeterson_attrs),
+					Cache_Type_ALL, TRUE);
+			}
+#endif
+		}
+	}
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "gatemp_instance_init failed! status = 0x%x",
+			retval);
+	}
+	return retval;
+}
+
+void gatepeterson_instance_finalize(struct gatepeterson_object *obj, int status)
+{
+	switch (status) {
+	/* No break here. Fall through to the next. */
+	case 0:
+		{
+			/* Modify shared memory */
+			obj->attrs->opener_proc_id = MULTIPROC_INVALIDID;
+#if 0
+			Cache_wbInv((Ptr)obj->attrs, sizeof(GatePeterson_Attrs),
+				Cache_Type_ALL, TRUE);
+#endif
+		}
+		/* No break here. Fall through to the next. */
+
+	case 1:
+		{
+			/* Nothing to be done. */
+		}
+	}
+	return;
+}
+
+
+
+#if 0
+/*
+ * ======== gatepeterson_create ========
+ *  Purpose:
+ *  This will creates a new instance of gatepeterson module
+ */
+void *gatepeterson_create(enum igatempsupport_local_protect local_protect,
+				const struct gatepeterson_params *params)
+{
+	void *handle = NULL;
+	s32 retval = 0;
+
+	BUG_ON(params == NULL);
+	if (atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+					GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (WARN_ON(params->shared_addr == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	handle = _gatepeterson_create(local_protect, params, true);
+	return handle;
+
+exit:
+	return NULL;
+}
+EXPORT_SYMBOL(gatepeterson_create);
+
+/*
+ * ======== gatepeterson_delete ========
+ *  Purpose:
+ *  This will deletes an instance of gatepeterson module
+ */
+int gatepeterson_delete(void **gphandle)
+
+{
+	struct gatepeterson_object *obj = NULL;
+	s32 retval;
+
+	BUG_ON(gphandle == NULL);
+	BUG_ON(*gphandle == NULL);
+	if (atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+				GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	obj = (struct gatepeterson_object *)(*gphandle);
+	if (unlikely(obj == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (unlikely(obj->attrs == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	/* Check if we have created the GP or not */
+	if (WARN_ON(unlikely(obj->attrs->creator_proc_id !=
+						multiproc_get_id(NULL)))) {
+		retval = -EACCES;
+		goto exit;
+	}
+
+	if (obj->ref_count != 0) {
+		retval = -EBUSY;
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(gatepeterson_module->mod_lock);
+	if (retval)
+		goto exit;
+
+	list_del(&obj->elem); /* Remove the GP instance from the GP list */
+	mutex_unlock(gatepeterson_module->mod_lock);
+	/* Modify shared memory */
+	obj->attrs->opener_proc_id = MULTIPROC_INVALIDID;
+#if 0
+	Cache_wbInv((Ptr)obj->attrs, sizeof(struct gatepeterson_attrs),
+			Cache_Type_ALL, true);
+#endif
+
+	kfree(obj);
+	*gphandle = NULL;
+	return 0;
+
+exit:
+	printk(KERN_ERR "gatepeterson_delete failed status: %x\n",
+			retval);
+	return retval;
+}
+EXPORT_SYMBOL(gatepeterson_delete);
+
+#else
+
+/* Override the IObject interface to define create and delete APIs */
+IOBJECT_CREATE1(gatepeterson, enum igatempsupport_local_protect);
+
+#endif
+
+#if 0
+/*
+ * ======== gatepeterson_open ========
+ *  Purpose:
+ *  This will opens a created instance of gatepeterson
+ *  module by shared addr.
+ */
+int gatepeterson_open_by_addr(enum igatempsupport_local_protect local_protect,
+				void *shared_addr, void **handle_ptr)
+{
+	void *temp = NULL;
+	s32 retval = 0;
+	struct gatepeterson_params params;
+
+	BUG_ON(shared_addr == NULL);
+	BUG_ON(handle_ptr == NULL);
+	if (atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+				GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (shared_addr == NULL) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (handle_ptr == NULL) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (gatepeterson_inc_refcount(&params, &temp)) {
+		retval = -EBUSY;
+		goto exit; /* It's already opened from local processor */
+	}
+
+	gatepeterson_params_init(&params);
+	params.shared_addr = shared_addr;
+	params.region_id = sharedregion_get_id(shared_addr);
+
+	*handle_ptr = _gatepeterson_create(local_protect, &params, false);
+	return 0;
+
+exit:
+	printk(KERN_ERR "gatepeterson_open failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(gatepeterson_open_by_addr);
+
+/*
+ * ======== gatepeterson_close ========
+ *  Purpose:
+ *  This will closes previously opened/created instance
+ * of gatepeterson module
+ */
+int gatepeterson_close(void **gphandle)
+{
+	struct gatepeterson_object *obj = NULL;
+	struct gatepeterson_params *params = NULL;
+	s32 retval = 0;
+
+	BUG_ON(gphandle == NULL);
+	if (atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+				GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (WARN_ON(*gphandle == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct gatepeterson_object *) (*gphandle);
+	if (unlikely(obj == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	key = gatemp_enter(obj->local_gate);
+
+	if (obj->ref_count > 1) {
+		obj->ref_count--;
+		gatemp_leave(obj->local_gate, key);
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(gatepeterson_module->mod_lock);
+	if (retval)
+		goto error_handle;
+
+	list_del(&obj->elem);
+	mutex_unlock(gatepeterson_module->mod_lock);
+	params = &obj->params;
+
+	gatemp_leave(obj->local_gate, key);
+
+	gatemp_delete(obj->local_gate);
+
+	kfree(obj);
+	*gphandle = NULL;
+	return 0;
+
+error_handle:
+	gatemp_leave(obj->local_gate, key);
+
+exit:
+	printk(KERN_ERR "gatepeterson_close failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(gatepeterson_close);
+#endif
+
+/*
+ * ======== gatepeterson_enter ========
+ *  Purpose:
+ *  This will enters the gatepeterson instance
+ */
+int *gatepeterson_enter(void *gphandle)
+{
+	struct gatepeterson_object *obj = NULL;
+	s32 retval = 0;
+	int *key = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+				GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(gphandle == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct gatepeterson_object *) gphandle;
+
+	/* Enter local gate */
+	if (obj->local_gate != NULL) {
+		retval = mutex_lock_interruptible(obj->local_gate);
+		if (retval)
+			goto exit;
+	}
+
+	/* If the gate object has already been entered, return the key */
+	obj->nested++;
+	if (obj->nested > 1)
+		return key;
+
+	/* indicate, needs to use the resource. */
+	*((u32 *)obj->flag[obj->self_id]) = GATEPETERSON_BUSY ;
+#if 0
+	if (obj->cacheEnabled)
+		Cache_wbInv((Ptr)obj->flag[obj->selfId],
+			obj->cacheLineSize, Cache_Type_ALL, true);
+#endif
+	/* Give away the turn. */
+	*((u32 *)(obj->turn)) = obj->other_id;
+#if 0
+	if (obj->cacheEnabled) {
+		Cache_wbInv((Ptr)obj->turn, obj->cacheLineSize,
+						Cache_Type_ALL, true);
+		Cache_inv((Ptr)obj->flag[obj->otherId], obj->cacheLineSize,
+						Cache_Type_ALL, true);
+	}
+#endif
+
+	/* Wait while other processor is using the resource and has
+	 *  the turn
+	 */
+	while ((*((VOLATILE u32 *) obj->flag[obj->other_id])
+		== GATEPETERSON_BUSY) &&
+		(*((VOLATILE u32  *)obj->turn) == obj->other_id)) {
+		/* Empty body loop */
+		/* Except for cache stuff */
+#if 0
+		if (obj->cacheEnabled) {
+			Cache_inv((Ptr)obj->flag[obj->otherId], obj->
+					cacheLineSize, Cache_Type_ALL, true);
+			Cache_inv((Ptr)obj->turn, obj->
+					cacheLineSize, Cache_Type_ALL, true);
+		}
+		udelay(10);
+#endif
+	}
+
+	return key;
+
+exit:
+	return 0;
+}
+EXPORT_SYMBOL(gatepeterson_enter);
+
+/*
+ * ======== gatepeterson_leave ========
+ *  Purpose:
+ *  This will leaves the gatepeterson instance
+ */
+void gatepeterson_leave(void *gphandle, int *key)
+{
+	struct gatepeterson_object *obj	= NULL;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(gatepeterson_module->ref_count),
+				GATEPETERSON_MAKE_MAGICSTAMP(0),
+				GATEPETERSON_MAKE_MAGICSTAMP(1)) == true))
+		goto exit;
+
+	BUG_ON(gphandle == NULL);
+
+	obj = (struct gatepeterson_object *)gphandle;
+
+	/* Release the resource and leave system gate. */
+	obj->nested--;
+	if (obj->nested == 0) {
+		*((VOLATILE u32 *)obj->flag[obj->self_id]) = GATEPETERSON_FREE;
+#if 0
+		if (obj->cacheEnabled)
+			Cache_wbInv((Ptr)obj->flag[obj->selfId],
+			obj->cacheLineSize, Cache_Type_ALL, true);
+#endif
+	}
+	/* Leave local gate */
+	mutex_unlock(obj->local_gate);
+
+exit:
+	return;
+}
+EXPORT_SYMBOL(gatepeterson_leave);
+
+/*
+ * ======== gatepeterson_shared_mem_req ========
+ *  Purpose:
+ *  This will give the amount of shared memory required
+ *  for creation of each instance
+ */
+u32 gatepeterson_shared_mem_req(const struct gatepeterson_params *params)
+{
+	u32 mem_req = 0;
+
+	if (sharedregion_get_cache_line_size(params->region_id) >=
+			sizeof(struct gatepeterson_attrs))
+		/* 4 Because shared of shared memory usage */
+		mem_req = 4 * sharedregion_get_cache_line_size(params->
+								region_id);
+	else
+		mem_req = sizeof(struct gatepeterson_attrs) +
+						sizeof(u16) * 3;
+
+	return mem_req;
+}
+EXPORT_SYMBOL(gatepeterson_shared_mem_req);
+
+/*
+ *************************************************************************
+ *                       Internal functions
+ *************************************************************************
+ */
+#if 0
+/*
+ * ======== gatepeterson_create ========
+ *  Purpose:
+ *  Creates a new instance of gatepeterson module.
+ *  This is an internal function because both
+ *  gatepeterson_create and gatepeterson_open
+ *  call use the same functionality.
+ */
+static void *_gatepeterson_create(enum igatempsupport_local_protect
+		local_protect, const struct gatepeterson_params *params,
+							bool create_flag)
+{
+	int status = 0;
+	struct gatepeterson_object *handle = NULL;
+	struct gatepeterson_obj *obj = NULL;
+
+	handle = kmalloc(sizeof(struct gatepeterson_object), GFP_KERNEL);
+	if (handle == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	obj = kmalloc(sizeof(struct gatepeterson_obj), GFP_KERNEL);
+	if (obj == NULL) {
+		status = -ENOMEM;
+		goto obj_alloc_fail;
+	}
+
+	if (local_protect >= GATEPETERSON_PROTECT_END_VALUE) {
+		status = -EINVAL;
+		goto exit_with_cleanup;
+	}
+
+	handle->obj = obj;
+	handle->enter = &gatepeterson_enter;
+	handle->leave = &gatepeterson_leave;
+
+	/* Create the local gate */
+	obj->local_gate = gatemp_create_local(local_protect);
+	obj->cache_enabled  = sharedregion_is_cache_enabled(params->region_id);
+	obj->cache_line_size = sharedregion_get_cache_line_size(params->
+								region_id);
+
+	/* Settings for both the creator and opener */
+	if (obj->cache_line_size > sizeof(struct gatepeterson_attrs)) {
+		obj->attrs = params->shared_addr;
+		obj->flag[0] = (u16 *)((u32)(obj->attrs) + obj->
+							cache_line_size);
+		obj->flag[1] = (u16 *)((u32)(obj->flag[0]) + obj->
+							cache_line_size);
+		obj->turn = (u16 *)((u32)(obj->flag[1]) + obj->
+							cache_line_size);
+	} else {
+		obj->attrs   = params->shared_addr;
+		obj->flag[0] = (u16 *)((u32)(obj->attrs) +
+					sizeof(struct gatepeterson_attrs));
+		obj->flag[1] = (u16 *)((u32)(obj->flag[0]) + sizeof(u16));
+		obj->turn	= (u16 *)((u32)(obj->flag[1]) + sizeof(u16));
+	}
+	obj->nested  = 0;
+
+	if (params->open_flag == false) {
+		/* Creating. */
+		obj->self_id = 0;
+		obj->other_id = 1;
+		obj->ref_count = 0;
+		gatepeterson_post_init(obj);
+	} else {
+#if 0
+		Cache_inv((Ptr)obj->attrs, sizeof(struct gatepeterson_attrs),
+				Cache_Type_ALL, true);
+#endif
+		obj->ref_count = 1;
+		if (obj->attrs->creator_proc_id == multiproc_self()) {
+			/* Opening locally */
+			obj->self_id		 = 0;
+			obj->other_id		= 1;
+		} else {
+			/* Trying to open a gate remotely */
+			obj->self_id		 = 1;
+			obj->other_id		= 0;
+			if (obj->attrs->opener_proc_id == MULTIPROC_INVALIDID)
+				/* Opening remotely for the first time */
+				obj->attrs->opener_proc_id = multiproc_self();
+			else if (obj->attrs->opener_proc_id !=
+						multiproc_self()) {
+				status = -EFAULT;
+				goto exit_with_cleanup;
+			}
+#if 0
+		if (status >= 0) {
+			if (obj->cache_enabled) {
+				Cache_wbInv((Ptr)obj->attrs,
+					sizeof(struct gatepeterson_attrs),
+					Cache_Type_ALL, true);
+			}
+		}
+#endif
+		}
+	}
+
+	status = mutex_lock_interruptible(gatepeterson_module->mod_lock);
+	if (status)
+		goto mod_lock_fail;
+
+	list_add_tail(&obj->elem, &gatepeterson_module->obj_list);
+	mutex_unlock(gatepeterson_module->mod_lock);
+
+	return handle;
+mod_lock_fail:
+exit_with_cleanup:
+	gatemp_delete(&obj->local_gate);
+	kfree(obj);
+
+obj_alloc_fail:
+	kfree(handle);
+	handle = NULL;
+
+exit:
+	if (create_flag == true)
+		printk(KERN_ERR "_gatepeterson_create (create) failed "
+			"status: %x\n", status);
+	else
+		printk(KERN_ERR "_gatepeterson_create (open) failed "
+			"status: %x\n", status);
+
+	return NULL;
+}
+
+#endif
+
+/*
+ * ======== gatepeterson_post_init ========
+ *  Purpose:
+ *  Function to be called during
+ *  1. module startup to complete the initialization of all static instances
+ *  2. instance_init to complete the initialization of a dynamic instance
+ *
+ *  Main purpose is to set up shared memory
+ */
+static void gatepeterson_post_init(struct gatepeterson_object *obj)
+{
+	/* Set up shared memory */
+	*(obj->turn)       = 0;
+	*(obj->flag[0])    = 0;
+	*(obj->flag[1])    = 0;
+	obj->attrs->creator_proc_id = multiproc_self();
+	obj->attrs->opener_proc_id  = MULTIPROC_INVALIDID;
+#if 0
+	/*
+	* Write everything back to memory. This assumes that obj->attrs is
+	* equal to the shared memory base address
+	*/
+	if (obj->cacheEnabled) {
+		Cache_wbInv((Ptr)obj->attrs, sizeof(struct gatepeterson_attrs),
+			Cache_Type_ALL, false);
+		Cache_wbInv((Ptr)(obj->flag[0]), obj->cacheLineSize * 3,
+			Cache_Type_ALL, true);
+	}
+#endif
+}
+
+#if 0
+/*
+ * ======== gatepeterson_inc_refcount ========
+ *  Purpose:
+ *  This will increment the reference count while opening
+ *  a GP instance if it is already opened from local processor
+ */
+static bool gatepeterson_inc_refcount(const struct gatepeterson_params *params,
+					void **handle)
+{
+	struct gatepeterson_object *obj = NULL;
+	s32 retval  = 0;
+	bool done = false;
+
+	list_for_each_entry(obj, &gatepeterson_module->obj_list, elem) {
+		if (params->shared_addr != NULL) {
+			if (obj->params.shared_addr == params->shared_addr) {
+				retval = mutex_lock_interruptible(
+						gatepeterson_module->mod_lock);
+				if (retval)
+					break;
+
+				obj->ref_count++;
+				*handle = obj;
+				mutex_unlock(gatepeterson_module->mod_lock);
+				done = true;
+				break;
+			}
+		}
+	}
+
+	return done;
+}
+#endif
diff --git a/drivers/dsp/syslink/multicore_ipc/heap.c b/drivers/dsp/syslink/multicore_ipc/heap.c
new file mode 100644
index 000000000000..b87988a796f0
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/heap.c
@@ -0,0 +1,115 @@
+/*
+ *  heap.c
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+#include <linux/types.h>
+#include <linux/bug.h>
+
+
+#include <heap.h>
+
+
+/*
+ * ======== sl_heap_alloc ========
+ *  Purpose:
+ *  This will allocate a block of memory of specified
+ *  size
+ */
+void *sl_heap_alloc(void *hphandle, u32 size, u32 align)
+{
+	char *block = NULL;
+	struct heap_object *obj = NULL;
+
+	BUG_ON(hphandle == NULL);
+
+	obj = (struct heap_object *)hphandle;
+	BUG_ON(obj->alloc == NULL);
+	block = obj->alloc(hphandle, size, align);
+	return block;
+}
+
+/*
+ * ======== sl_heap_free ========
+ *  Purpose:
+ *  This will frees a block of memory allocated
+ *  rom heap
+ */
+int sl_heap_free(void *hphandle, void *block, u32 size)
+{
+	struct heap_object *obj = NULL;
+	s32 retval  = 0;
+
+	BUG_ON(hphandle == NULL);
+
+	obj = (struct heap_object *)hphandle;
+	BUG_ON(obj->free == NULL);
+	retval = obj->free(hphandle, block, size);
+	return retval;
+}
+
+/*
+ * ======== sl_heap_get_stats ========
+ *  Purpose:
+ *  This will get the heap memory statistics
+ */
+void sl_heap_get_stats(void *hphandle, struct memory_stats *stats)
+{
+	struct heap_object *obj = NULL;
+
+	BUG_ON(hphandle == NULL);
+	BUG_ON(stats == NULL);
+
+	obj = (struct heap_object *)hphandle;
+	BUG_ON(obj->get_stats == NULL);
+	obj->get_stats(hphandle, stats);
+}
+
+/*
+ * ======== sl_heap_get_extended_stats ========
+ *  Purpose:
+ *  This will get the heap memory extended statistics
+ */
+void sl_heap_get_extended_stats(void *hphandle,
+				struct heap_extended_stats *stats)
+{
+	struct heap_object *obj = NULL;
+
+	BUG_ON(hphandle == NULL);
+	BUG_ON(stats == NULL);
+
+	obj = (struct heap_object *)hphandle;
+	BUG_ON(obj->get_extended_stats == NULL);
+	obj->get_extended_stats(hphandle, stats);
+}
+
+
+/*
+ * ======== sl_heap_is_blocking ========
+ *  Purpose:
+ *  Indicates whether the heap may block during an alloc or free call
+ */
+bool sl_heap_is_blocking(void *hphandle)
+{
+	struct heap_object *obj = NULL;
+
+	BUG_ON(hphandle == NULL);
+
+	obj = (struct heap_object *)hphandle;
+	BUG_ON(obj->is_blocking == NULL);
+
+	return obj->is_blocking(hphandle);
+}
+
diff --git a/drivers/dsp/syslink/multicore_ipc/heapbufmp.c b/drivers/dsp/syslink/multicore_ipc/heapbufmp.c
new file mode 100644
index 000000000000..e625789950fc
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/heapbufmp.c
@@ -0,0 +1,1555 @@
+/*
+ *  heapbufmp.c
+ *
+ *  Heap module manages variable size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright(C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <atomic_linux.h>
+#include <multiproc.h>
+#include <nameserver.h>
+#include <sharedregion.h>
+#include <gatemp.h>
+#include <heapbufmp.h>
+
+/*
+ *  Name of the reserved nameserver used for heapbufmp.
+ */
+#define HEAPBUFMP_NAMESERVER			"HeapBufMP"
+/* brief Macro to make a correct module magic number with ref_count */
+#define HEAPBUFMP_MAKE_MAGICSTAMP(x)	((HEAPBUFMP_MODULEID << 12) | (x))
+/* Max heapbufmp name length */
+#define HEAPBUFMP_MAX_NAME_LEN			32
+/* Max number of runtime entries */
+#define HEAPBUFMP_MAX_RUNTIME_ENTRIES		32
+
+#define ROUND_UP(a, b)	(((a) + ((b) - 1)) & (~((b) - 1)))
+
+/*
+ *  Structure defining attribute parameters for the heapbufmp module
+ */
+struct heapbufmp_attrs {
+	VOLATILE u32 status; /* Module status */
+	VOLATILE u32 *gatemp_addr; /* gatemp shared address(shm safe) */
+	VOLATILE u32 *buf_ptr; /* Memory managed by instance */
+	VOLATILE u32 num_free_blocks; /* Number of free blocks */
+	VOLATILE u32 min_free_blocks; /* Min number of free blocks */
+	VOLATILE u32 block_size; /* True size of each block */
+	VOLATILE u32 align; /* Alignment of each block */
+	VOLATILE u32 num_blocks; /* Number of individual blocks */
+	VOLATILE u16 exact; /* For 'exact' allocation */
+};
+
+/*
+ *  Structure defining processor related information for the
+ *  heapbufmp module
+ */
+struct heapbufmp_proc_attrs {
+	bool creator; /* Creator or opener */
+	u16 proc_id; /* Processor identifier */
+	u32 open_count; /* open count in a processor */
+};
+
+/*
+ *  Structure for heapbufmp module state
+ */
+struct heapbufmp_module_object {
+	atomic_t ref_count; /* Reference count */
+	void *nameserver; /* Nameserver handle */
+	struct list_head obj_list; /* List holding created objects */
+	struct mutex *local_lock; /* lock for protecting obj_list */
+	struct heapbufmp_config cfg; /* Current config values */
+	struct heapbufmp_config default_cfg; /* Default config values */
+	struct heapbufmp_params default_inst_params; /* Default instance
+						creation parameters */
+};
+
+struct heapbufmp_module_object heapbufmp_state = {
+	.obj_list = LIST_HEAD_INIT(heapbufmp_state.obj_list),
+	.default_cfg.max_name_len = HEAPBUFMP_MAX_NAME_LEN,
+	.default_cfg.max_runtime_entries = HEAPBUFMP_MAX_RUNTIME_ENTRIES,
+	.default_cfg.track_allocs = false,
+	.default_inst_params.gate = NULL,
+	.default_inst_params.exact = false,
+	.default_inst_params.name = NULL,
+	.default_inst_params.align = 1u,
+	.default_inst_params.num_blocks = 0u,
+	.default_inst_params.block_size = 0u,
+	.default_inst_params.region_id = 0,
+	.default_inst_params.shared_addr = NULL,
+};
+
+/* Pointer to module state */
+static struct heapbufmp_module_object *heapbufmp_module = &heapbufmp_state;
+
+/*
+ *  Structure for the handle for the heapbufmp
+ */
+struct heapbufmp_obj {
+	struct list_head list_elem; /* Used for creating a linked list */
+	struct heapbufmp_attrs *attrs; /* The shared attributes structure */
+	void *gate; /* Lock used for critical region management */
+	void *ns_key; /* nameserver key required for remove */
+	bool cache_enabled; /* Whether to do cache calls */
+	u16 region_id; /* shared region index */
+	u32 alloc_size; /* Size of allocated shared memory */
+	char *buf; /* Pointer to allocated memory */
+	void *free_list; /* List of free buffers */
+	u32 block_size; /* Adjusted block_size */
+	u32 align; /* Adjusted alignment */
+	u32 num_blocks; /* Number of blocks in buffer */
+	bool exact; /* Exact match flag */
+	struct heapbufmp_proc_attrs owner; /* owner processor info */
+	void *top; /* Pointer to the top object */
+	struct heapbufmp_params params; /* The creation parameter structure */
+};
+
+#define heapbufmp_object heap_object
+
+/* =============================================================================
+ * Forward declarations of internal functions
+ * =============================================================================
+ */
+static int heapbufmp_post_init(struct heapbufmp_object *handle);
+
+/* =============================================================================
+ * APIs called directly by applications
+ * =============================================================================
+ */
+/*
+ * ======== heapbufmp_get_config ========
+ *  Purpose:
+ *  This will get default configuration for the
+ *  heapbufmp module
+ */
+int heapbufmp_get_config(struct heapbufmp_config *cfgparams)
+{
+	s32 retval = 0;
+
+	BUG_ON(cfgparams == NULL);
+
+	if (cfgparams == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true)
+		memcpy(cfgparams, &heapbufmp_module->default_cfg,
+					sizeof(struct heapbufmp_config));
+	else
+		memcpy(cfgparams, &heapbufmp_module->cfg,
+					sizeof(struct heapbufmp_config));
+	return 0;
+error:
+	printk(KERN_ERR "heapbufmp_get_config failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapbufmp_get_config);
+
+/*
+ * ======== heapbufmp_setup ========
+ *  Purpose:
+ *  This will setup the heapbufmp module
+ *
+ *  This function sets up the heapbufmp module. This function
+ *  must be called before any other instance-level APIs can be
+ *  invoked.
+ *  Module-level configuration needs to be provided to this
+ *  function. If the user wishes to change some specific config
+ *  parameters, then heapbufmp_getconfig can be called to get
+ *  the configuration filled with the default values. After this,
+ *  only the required configuration values can be changed. If the
+ *  user does not wish to make any change in the default parameters,
+ *  the application can simply call heapbufmp_setup with NULL
+ *  parameters. The default parameters would get automatically used.
+ */
+int heapbufmp_setup(const struct heapbufmp_config *cfg)
+{
+	struct nameserver_params params;
+	struct heapbufmp_config tmp_cfg;
+	s32 retval  = 0;
+
+	/* This sets the ref_count variable  not initialized, upper 16 bits is
+	 * written with module Id to ensure correctness of ref_count variable
+	 */
+	atomic_cmpmask_and_set(&heapbufmp_module->ref_count,
+					HEAPBUFMP_MAKE_MAGICSTAMP(0),
+					HEAPBUFMP_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&heapbufmp_module->ref_count)
+					!= HEAPBUFMP_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	if (cfg == NULL) {
+		heapbufmp_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	if (cfg->max_name_len == 0 ||
+		cfg->max_name_len > HEAPBUFMP_MAX_NAME_LEN) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* Initialize the parameters */
+	nameserver_params_init(&params);
+	params.max_value_len = sizeof(u32);
+	params.max_name_len = cfg->max_name_len;
+	params.max_runtime_entries = cfg->max_runtime_entries;
+
+	/* Create the nameserver for modules */
+	heapbufmp_module->nameserver =
+		nameserver_create(HEAPBUFMP_NAMESERVER, &params);
+	if (heapbufmp_module->nameserver == NULL) {
+		retval = -EFAULT;
+		goto error;
+	}
+
+	/* Construct the list object */
+	INIT_LIST_HEAD(&heapbufmp_module->obj_list);
+	/* Copy config info */
+	memcpy(&heapbufmp_module->cfg, cfg, sizeof(struct heapbufmp_config));
+	/* Create a lock for protecting list object */
+	heapbufmp_module->local_lock = kmalloc(sizeof(struct mutex),
+								GFP_KERNEL);
+	mutex_init(heapbufmp_module->local_lock);
+	if (heapbufmp_module->local_lock == NULL) {
+		retval = -ENOMEM;
+		heapbufmp_destroy();
+		goto error;
+	}
+
+	return 0;
+
+error:
+	printk(KERN_ERR "heapbufmp_setup failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapbufmp_setup);
+
+/*
+ * ======== heapbufmp_destroy ========
+ *  Purpose:
+ *  This will destroy the heapbufmp module
+ */
+int heapbufmp_destroy(void)
+{
+	s32 retval  = 0;
+	struct mutex *lock = NULL;
+	struct heapbufmp_obj *obj = NULL;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (atomic_dec_return(&heapbufmp_module->ref_count)
+				== HEAPBUFMP_MAKE_MAGICSTAMP(0)) {
+		/* Temporarily increment ref_count here. */
+		atomic_set(&heapbufmp_module->ref_count,
+					HEAPBUFMP_MAKE_MAGICSTAMP(1));
+
+		/*  Check if any heapbufmp instances have not been
+		 *  deleted/closed so far. if there any, delete or close them
+		 */
+		list_for_each_entry(obj, &heapbufmp_module->obj_list,
+								list_elem) {
+			if (obj->owner.proc_id == multiproc_get_id(NULL))
+				retval = heapbufmp_delete(&obj->top);
+			else
+				retval = heapbufmp_close(obj->top);
+
+			if (list_empty(&heapbufmp_module->obj_list))
+				break;
+
+			if (retval < 0)
+				goto error;
+		}
+
+		/* Again reset ref_count. */
+		atomic_set(&heapbufmp_module->ref_count,
+					HEAPBUFMP_MAKE_MAGICSTAMP(0));
+
+		if (likely(heapbufmp_module->nameserver != NULL)) {
+			retval = nameserver_delete(&heapbufmp_module->
+							nameserver);
+			if (unlikely(retval != 0))
+				goto error;
+		}
+
+		/* Delete the list lock */
+		lock = heapbufmp_module->local_lock;
+		retval = mutex_lock_interruptible(lock);
+		if (retval)
+			goto error;
+
+		heapbufmp_module->local_lock = NULL;
+		mutex_unlock(lock);
+		kfree(lock);
+		memset(&heapbufmp_module->cfg, 0,
+				sizeof(struct heapbufmp_config));
+	}
+
+	return 0;
+
+error:
+	printk(KERN_ERR "heapbufmp_destroy failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapbufmp_destroy);
+
+/*
+ * ======== heapbufmp_params_init ========
+ *  Purpose:
+ *  This will get the intialization prams for a heapbufmp
+ *  module instance
+ */
+void heapbufmp_params_init(struct heapbufmp_params *params)
+{
+	s32 retval  = 0;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	BUG_ON(params == NULL);
+
+	memcpy(params, &heapbufmp_module->default_inst_params,
+				sizeof(struct heapbufmp_params));
+
+	return;
+error:
+	printk(KERN_ERR "heapbufmp_params_init failed status: %x\n", retval);
+}
+EXPORT_SYMBOL(heapbufmp_params_init);
+
+/*
+ * ======== _heapbufmp_create ========
+ *  Purpose:
+ *  This will create a new instance of heapbufmp module
+ *  This is an internal function as both heapbufmp_create
+ *  and heapbufmp_open use the functionality
+ *
+ *  NOTE: The lock to protect the shared memory area
+ *  used by heapbufmp is provided by the consumer of
+ *  heapbufmp module
+ */
+int _heapbufmp_create(void **handle_ptr, const struct heapbufmp_params *params,
+				u32 create_flag)
+{
+	s32 retval  = 0;
+	struct heapbufmp_obj *obj = NULL;
+	struct heapbufmp_object *handle = NULL;
+	void *gate_handle = NULL;
+	void *local_addr = NULL;
+	u32 *shared_shm_base;
+	u32 min_align;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	/* No need for parameter checks, since this is an internal function. */
+
+	/* Initialize return parameter. */
+	*handle_ptr = NULL;
+
+	handle = kmalloc(sizeof(struct heapbufmp_object), GFP_KERNEL);
+	if (handle == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+
+	obj = kmalloc(sizeof(struct heapbufmp_obj), GFP_KERNEL);
+	if (obj == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+
+	handle->obj = (struct heapbufmp_obj *)obj;
+	handle->alloc = &heapbufmp_alloc;
+	handle->free = &heapbufmp_free;
+	handle->get_stats = &heapbufmp_get_stats;
+	handle->is_blocking = &heapbufmp_isblocking;
+
+	obj->ns_key	 = NULL;
+	obj->alloc_size = 0;
+
+	/* Put in local ilst */
+	retval = mutex_lock_interruptible(heapbufmp_module->local_lock);
+	if (retval < 0)
+		goto error;
+
+	INIT_LIST_HEAD(&obj->list_elem);
+	list_add(&heapbufmp_module->obj_list, &obj->list_elem);
+	mutex_unlock(heapbufmp_module->local_lock);
+
+	if (create_flag == false) {
+		obj->owner.creator = false;
+		obj->owner.open_count = 0;
+		obj->owner.proc_id = MULTIPROC_INVALIDID;
+		obj->top = handle;
+
+		obj->attrs = (struct heapbufmp_attrs *) params->shared_addr;
+
+		/* No need to Cache_inv- already done in openByAddr() */
+		obj->align          = obj->attrs->align;
+		obj->num_blocks     = obj->attrs->num_blocks;
+		obj->block_size     = obj->attrs->block_size;
+		obj->exact          = obj->attrs->exact;
+		obj->buf            = sharedregion_get_ptr((u32 *)obj->attrs->
+								buf_ptr);
+		obj->region_id      = sharedregion_get_id(obj->buf);
+
+		/* Set min_align */
+		min_align = 4; /* memory_get_max_default_type_align(); */
+		if (sharedregion_get_cache_line_size(obj->region_id) >
+								min_align)
+			min_align = sharedregion_get_cache_line_size(obj->
+								region_id);
+		obj->cache_enabled = sharedregion_is_cache_enabled(obj->
+								region_id);
+
+		local_addr = sharedregion_get_ptr((u32 *)obj->attrs->
+								gatemp_addr);
+		retval = gatemp_open_by_addr(local_addr, &gate_handle);
+
+		if (retval < 0) {
+			retval = -EFAULT;
+			goto error;
+		}
+		obj->gate = gate_handle;
+
+		/* Open the ListMP */
+		local_addr = (void *) ROUND_UP(((u32)obj->attrs
+					 + sizeof(struct heapbufmp_attrs)),
+					 min_align);
+		retval = listmp_open_by_addr(local_addr, &(obj->free_list));
+
+		if (retval < 0) {
+			retval = -EFAULT;
+			goto error;
+		}
+	} else {
+		obj->owner.creator = true;
+		obj->owner.open_count = 1;
+		obj->owner.proc_id = multiproc_self();
+		obj->top = handle;
+
+		/* Creating the gate */
+		if (params->gate != NULL)
+			obj->gate = params->gate;
+		else {
+			/* If no gate specified, get the default system gate */
+			obj->gate = gatemp_get_default_remote();
+		}
+
+		if (obj->gate == NULL) {
+			retval = -EFAULT;
+			goto error;
+		}
+
+		obj->exact      = params->exact;
+		obj->align      = params->align;
+		obj->num_blocks = params->num_blocks;
+
+		if (params->shared_addr == NULL) {
+			/* Creating using a shared region ID */
+			/* It is allowed to have NULL name for an anonymous, not
+			 * to be opened by name, heap.
+			 */
+			/* Will be allocated in post_init */
+			obj->attrs = NULL;
+			obj->region_id = params->region_id;
+		} else {
+			/* Creating using shared_addr */
+			obj->region_id = sharedregion_get_id(
+							params->shared_addr);
+
+			/* Assert that the buffer is in a valid shared
+			 * region
+			 */
+			if (obj->region_id == SHAREDREGION_INVALIDREGIONID) {
+				retval = -EFAULT;
+				goto error;
+			} else if (((u32) params->shared_addr
+					% sharedregion_get_cache_line_size(obj->
+					region_id) != 0)) {
+				retval = -EFAULT;
+				goto error;
+			}
+			obj->attrs = (struct heapbufmp_attrs *)
+							params->shared_addr;
+		}
+
+		obj->cache_enabled = sharedregion_is_cache_enabled(
+								obj->region_id);
+
+		/* Fix the alignment (alignment may be needed even if
+		 * cache is disabled)
+		 */
+		obj->align = 4; /* memory_get_max_default_type_align(); */
+		if (sharedregion_get_cache_line_size(obj->region_id) >
+								obj->align)
+			obj->align = sharedregion_get_cache_line_size(
+								obj->region_id);
+
+		/* Round the block_size up by the adjusted alignment */
+		obj->block_size = ROUND_UP(params->block_size, obj->align);
+
+		retval = heapbufmp_post_init(handle);
+		if (retval < 0) {
+			retval = -EFAULT;
+			goto error;
+		}
+
+		/* Populate the params member */
+		memcpy(&obj->params, params, sizeof(struct heapbufmp_params));
+		if (params->name != NULL) {
+			obj->params.name = kmalloc(strlen(params->name) + 1,
+							GFP_KERNEL);
+			if (obj->params.name == NULL) {
+				retval  = -ENOMEM;
+				goto error;
+			}
+			strncpy(obj->params.name, params->name,
+						strlen(params->name) + 1);
+		}
+
+		/* We will store a shared pointer in the NameServer */
+		shared_shm_base = sharedregion_get_srptr((void *)obj->attrs,
+							obj->region_id);
+		if (obj->params.name != NULL) {
+			obj->ns_key = nameserver_add_uint32(
+						heapbufmp_module->nameserver,
+						params->name,
+						(u32)shared_shm_base);
+			if (obj->ns_key == NULL) {
+				retval = -EFAULT;
+				goto error;
+			}
+		}
+	}
+
+	*handle_ptr = (void *)handle;
+	return retval;
+
+
+error:
+	/* Do whatever cleanup is required*/
+	if (create_flag == true)
+		heapbufmp_delete(handle_ptr);
+	else
+		heapbufmp_close(handle_ptr);
+
+	printk(KERN_ERR "_heapbufmp_create failed status: %x\n", retval);
+	return retval;
+}
+
+/*
+ * ======== heapbufmp_create ========
+ *  Purpose:
+ *  This will create a new instance of heapbufmp module
+ */
+void *heapbufmp_create(const struct heapbufmp_params *params)
+{
+	s32 retval = 0;
+	struct heapbufmp_object *handle = NULL;
+	struct heapbufmp_params sparams;
+
+	BUG_ON(params == NULL);
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (params == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (params->block_size == 0) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (params->num_blocks == 0) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	memcpy(&sparams, (void *)params, sizeof(struct heapbufmp_params));
+	retval = _heapbufmp_create((void **)&handle, &sparams, true);
+	if (retval < 0)
+		goto error;
+
+	return (void *)handle;
+
+error:
+	printk(KERN_ERR "heapbufmp_create failed status: %x\n", retval);
+	return (void *)handle;
+}
+EXPORT_SYMBOL(heapbufmp_create);
+
+/*
+ * ======== heapbufmp_delete ========
+ *  Purpose:
+ *  This will delete an instance of heapbufmp module
+ */
+int heapbufmp_delete(void **handle_ptr)
+{
+	int status = 0;
+	struct heapbufmp_object *handle = NULL;
+	struct heapbufmp_obj *obj = NULL;
+	struct heapbufmp_params *params = NULL;
+	struct heapbufmp_object *region_heap = NULL;
+	s32 retval = 0;
+	int *key;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(handle_ptr == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	handle = (struct heapbufmp_object *)(*handle_ptr);
+	if (WARN_ON(handle == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	obj = (struct heapbufmp_obj *)handle->obj;
+	if (obj != NULL) {
+		if (obj->owner.proc_id != multiproc_self()) {
+			status = -ENODEV;
+			goto error;
+		}
+
+		/* Take the local lock */
+		key = gatemp_enter(obj->gate);
+
+		if (obj->owner.open_count > 1) {
+			retval = -ENODEV;
+			goto device_busy_error;
+		}
+
+		retval = mutex_lock_interruptible(heapbufmp_module->local_lock);
+		if (retval < 0)
+			goto lock_error;
+
+		/* Remove frmo the local list */
+		list_del(&obj->list_elem);
+
+		mutex_unlock(heapbufmp_module->local_lock);
+
+		params = (struct heapbufmp_params *) &obj->params;
+
+		if (likely(params->name != NULL)) {
+			if (likely(obj->ns_key != NULL)) {
+				nameserver_remove_entry(heapbufmp_module->
+						nameserver, obj->ns_key);
+				obj->ns_key = NULL;
+			}
+			kfree(params->name);
+		}
+
+		/* Set status to 'not created' */
+		if (obj->attrs != NULL) {
+#if 0
+			obj->attrs->status = 0;
+			if (obj->cache_enabled) {
+				cache_wbinv(obj->attrs, sizeof(struct
+					heapbufmp_attrs), CACHE_TYPE_ALL,
+					true);
+			}
+#endif
+		}
+
+		/* Release the shared lock */
+		gatemp_leave(obj->gate, key);
+
+		if (obj->free_list != NULL)
+			/* Free the list */
+			listmp_delete(&obj->free_list);
+
+		/* If necessary, free shared memory  if memory is internally
+		 * allocated
+		 */
+		region_heap = sharedregion_get_heap(obj->region_id);
+
+		if ((region_heap != NULL) &&
+			(obj->params.shared_addr == NULL) &&
+			(obj->attrs != NULL)) {
+			sl_heap_free(region_heap, obj->attrs, obj->alloc_size);
+		}
+
+		kfree(obj);
+		kfree(handle);
+
+		*handle_ptr = NULL;
+	} else {	/* obj == NULL */
+		kfree(handle);
+		*handle_ptr = NULL;
+	}
+
+
+	return 0;
+
+lock_error:
+device_busy_error:
+	gatemp_leave(obj->gate, key);
+
+error:
+	printk(KERN_ERR "heapbufmp_delete failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapbufmp_delete);
+
+/*
+ * ======== heapbufmp_open  ========
+ *  Purpose:
+ *  This will opens a created instance of heapbufmp
+ *  module
+ */
+int heapbufmp_open(char *name, void **handle_ptr)
+{
+	s32 retval = 0;
+	u32 *shared_shm_base = SHAREDREGION_INVALIDSRPTR;
+	u32 *shared_addr = NULL;
+	struct heapbufmp_obj *obj = NULL;
+	bool done_flag = false;
+	struct list_head *elem = NULL;
+
+	BUG_ON(name  == NULL);
+	BUG_ON(handle_ptr == NULL);
+
+	if (unlikely(
+			atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (name == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (handle_ptr == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* First check in the local list */
+	list_for_each(elem, &heapbufmp_module->obj_list) {
+		obj = (struct heapbufmp_obj *)elem;
+		if (obj->params.name != NULL) {
+			if (strcmp(obj->params.name, name) == 0) {
+				retval = mutex_lock_interruptible(
+					heapbufmp_module->local_lock);
+				if (retval < 0)
+					goto error;
+				/* Check if we have created the heapbufmp or
+				 * not
+				 */
+				if (obj->owner.proc_id == multiproc_self())
+					obj->owner.open_count++;
+
+				*handle_ptr = (void *)obj->top;
+				mutex_unlock(heapbufmp_module->local_lock);
+				done_flag = true;
+				break;
+			}
+		}
+	}
+
+	if (likely(done_flag == false)) {
+		/* Find in name server */
+		retval = nameserver_get_uint32(heapbufmp_module->nameserver,
+					       name,
+					       &shared_shm_base,
+					       NULL);
+		if (unlikely(retval < 0))
+			goto error;
+
+		/*
+		 * Convert from shared region pointer to local address
+		 */
+		shared_addr = sharedregion_get_ptr(shared_shm_base);
+		if (unlikely(shared_addr == NULL)) {
+			retval = -EINVAL;
+			goto error;
+		}
+
+		retval = heapbufmp_open_by_addr(shared_addr, handle_ptr);
+
+		if (unlikely(retval < 0))
+			goto error;
+	}
+
+	return 0;
+
+error:
+	printk(KERN_ERR "heapbufmp_open failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapbufmp_open);
+
+/*
+ * ======== heapbufmp_close  ========
+ *  Purpose:
+ *  This will closes previously opened/created instance
+ *  of heapbufmp module
+ */
+int heapbufmp_close(void **handle_ptr)
+{
+	struct heapbufmp_object *handle = NULL;
+	struct heapbufmp_obj *obj = NULL;
+	s32 retval = 0;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(handle_ptr == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(*handle_ptr == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	handle = (struct heapbufmp_object *)(*handle_ptr);
+	obj = (struct heapbufmp_obj *)handle->obj;
+
+	if (obj != NULL) {
+		retval = mutex_lock_interruptible(heapbufmp_module->
+							local_lock);
+		if (retval)
+			goto error;
+
+		/* opening an instance created locally */
+		if (obj->owner.proc_id == multiproc_self())
+			obj->owner.open_count--;
+
+		/* Check if HeapMemMP is opened on same processor
+		 * and this is the last closure.
+		 */
+		if ((obj->owner.creator == false)
+				&& (obj->owner.open_count == 0)) {
+			list_del(&obj->list_elem);
+
+			if (obj->free_list != NULL)
+				/* Close the list */
+				listmp_close(&obj->free_list);
+
+			if (obj->gate != NULL)
+				/* Close the instance gate */
+				gatemp_close(&obj->gate);
+
+			/* Now free the handle */
+			kfree(obj);
+			obj = NULL;
+			kfree(handle);
+			*handle_ptr = NULL;
+		}
+
+		mutex_unlock(heapbufmp_module->local_lock);
+	} else {
+		kfree(handle);
+		*handle_ptr = NULL;
+	}
+	return 0;
+
+error:
+	printk(KERN_ERR "heapbufmp_close failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapbufmp_close);
+
+/*
+ * ======== heapbufmp_alloc  ========
+ *  Purpose:
+ *  This will allocs a block of memory
+ */
+void *heapbufmp_alloc(void *hphandle, u32 size, u32 align)
+{
+	char *block = NULL;
+	struct heapbufmp_object *handle = NULL;
+	struct heapbufmp_obj *obj = NULL;
+	int *key;
+	s32 retval = 0;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+	if (WARN_ON(hphandle == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(size == 0)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	handle = (struct heapbufmp_object *)(hphandle);
+	obj = (struct heapbufmp_obj *)handle->obj;
+	if (WARN_ON(obj == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(unlikely(size > obj->block_size))) {
+		retval  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(unlikely((obj->exact == true)
+			  && (size != obj->block_size)))) {
+		retval  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(unlikely(align > obj->align))) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	/*key = gatemp_enter(obj->gate); gate protection acquired in listmp */
+	block = listmp_get_head((struct listmp_object *) obj->free_list);
+	if (unlikely(block == NULL)) {
+		retval = -ENOMEM;
+		goto error;
+	}
+	key = gatemp_enter(obj->gate); /*gatemp call moved down */
+	if (unlikely(heapbufmp_module->cfg.track_allocs)) {
+#if 0
+		/* Make sure the attrs are not in cache */
+		if (unlikely(obj->cache_enabled)) {
+			Cache_inv((Ptr) obj->attrs,
+					   sizeof(heapbufmp_attrs),
+					   Cache_Type_ALL,
+					   true);
+		}
+#endif
+	}
+
+	obj->attrs->num_free_blocks--;
+
+	if (obj->attrs->num_free_blocks
+		< obj->attrs->min_free_blocks) {
+		/* save the new minimum */
+		obj->attrs->min_free_blocks = obj->attrs->num_free_blocks;
+	}
+#if 0
+	/* Make sure the attrs are written out to memory */
+	if (EXPECT_false(obj->cacheEnabled == true)) {
+		Cache_wbInv((Ptr) obj->attrs,
+					 sizeof(heapbufmp_attrs),
+					 Cache_Type_ALL,
+					 true);
+	}
+#endif
+	gatemp_leave(obj->gate, key);
+
+	if (block == NULL)
+		printk(KERN_ERR "heapbufmp_alloc returned NULL\n");
+
+	return block;
+error:
+	printk(KERN_ERR "heapbufmp_alloc failed status: %x\n", retval);
+	return NULL;
+}
+EXPORT_SYMBOL(heapbufmp_alloc);
+
+/*
+ * ======== heapbufmp_free  ========
+ *  Purpose:
+ *  This will free a block of memory
+ */
+int heapbufmp_free(void *hphandle, void *block, u32 size)
+{
+	struct heapbufmp_object *handle = NULL;
+	s32 retval = 0;
+	struct heapbufmp_obj *obj = NULL;
+	int *key;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+	if (WARN_ON(hphandle == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(block == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	handle = (struct heapbufmp_object *)(hphandle);
+	obj = (struct heapbufmp_obj *)handle->obj;
+	if (WARN_ON(obj == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	/* key = gatemp_enter(obj->gate); */
+	retval = listmp_put_tail(obj->free_list, block);
+	if (unlikely(retval < 0)) {
+		retval = -EFAULT;
+		goto error;
+	}
+	key = gatemp_enter(obj->gate); /*gatemp call moved down */
+	if (unlikely(heapbufmp_module->cfg.track_allocs)) {
+#if 0
+		/* Make sure the attrs are not in cache */
+		if (EXPECT_false(obj->cacheEnabled == true)) {
+			Cache_inv((Ptr) obj->attrs,
+					   sizeof(heapbufmp_attrs),
+					   Cache_Type_ALL,
+					   true);
+		}
+#endif
+
+		obj->attrs->num_free_blocks++;
+#if 0
+		/* Make sure the attrs are written out to memory */
+		if (EXPECT_false(obj->cacheEnabled == true)) {
+			Cache_wbInv((Ptr) obj->attrs,
+						 sizeof(heapbufmp_attrs),
+						 Cache_Type_ALL,
+						 true);
+		}
+#endif
+	}
+
+	gatemp_leave(obj->gate, key);
+
+	return 0;
+
+error:
+	printk(KERN_ERR "heapbufmp_free failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapbufmp_free);
+
+/*
+ * ======== heapbufmp_get_stats  ========
+ *  Purpose:
+ *  This will get memory statistics
+ */
+void heapbufmp_get_stats(void *hphandle, struct memory_stats *stats)
+{
+	struct heapbufmp_object *object = NULL;
+	struct heapbufmp_obj *obj = NULL;
+	int *key;
+	s32 retval = 0;
+	u32 block_size;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+	if (WARN_ON(hphandle == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(stats == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	object = (struct heapbufmp_object *)(hphandle);
+	obj = (struct heapbufmp_obj *)object->obj;
+	if (WARN_ON(obj == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	block_size = obj->attrs->block_size;
+
+	if (unlikely(heapbufmp_module->cfg.track_allocs)) {
+
+		key = gatemp_enter(obj->gate);
+#if 0
+		/* Make sure the attrs are not in cache */
+		if (EXPECT_false(obj->cacheEnabled == true)) {
+			Cache_inv((Ptr) obj->attrs,
+				   sizeof(heapbufmp_attrs),
+				   Cache_Type_ALL,
+				   true);
+		}
+#endif
+
+		stats->total_free_size = block_size * obj->attrs->
+							num_free_blocks;
+		stats->largest_free_size = (obj->attrs->num_free_blocks > 0) ?
+					block_size : 0; /* determined later */
+
+		gatemp_leave(obj->gate, key);
+	} else {
+		/* Tracking disabled */
+		stats->total_free_size = 0;
+		stats->largest_free_size = 0;
+	}
+	return;
+
+error:
+	if (retval < 0)
+		printk(KERN_ERR "heapbufmp_get_stats status: [0x%x]\n",
+								retval);
+}
+EXPORT_SYMBOL(heapbufmp_get_stats);
+
+/*
+ * ======== heapbufmp_isblocking  ========
+ *  Purpose:
+ *  Indicate whether the heap may block during an alloc or free call
+ */
+bool heapbufmp_isblocking(void *handle)
+{
+	bool isblocking = false;
+	s32 retval  = 0;
+
+	if (WARN_ON(handle == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	/* TBD: Figure out how to determine whether the gate is blocking */
+	isblocking = true;
+
+	/* retval true  Heap blocks during alloc/free calls */
+	/* retval false Heap does not block during alloc/free calls */
+	return isblocking;
+
+error:
+	printk(KERN_ERR "heapbufmp_isblocking status: %x\n", retval);
+	return isblocking;
+}
+EXPORT_SYMBOL(heapbufmp_isblocking);
+
+/*
+ * ======== heapbufmp_get_extended_stats  ========
+ *  Purpose:
+ *  This will get extended statistics
+ */
+void heapbufmp_get_extended_stats(void *hphandle,
+				struct heapbufmp_extended_stats *stats)
+{
+	s32 retval = 0;
+	struct heapbufmp_object *object = NULL;
+	struct heapbufmp_obj *obj = NULL;
+	int *key;
+
+	if (atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+				HEAPBUFMP_MAKE_MAGICSTAMP(0),
+				HEAPBUFMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+	if (WARN_ON(heapbufmp_module->nameserver == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(hphandle == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	object = (struct heapbufmp_object *)(hphandle);
+	obj = (struct heapbufmp_obj *)object->obj;
+	if (WARN_ON(obj == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+#if 0
+	/* Make sure the attrs are not in cache */
+	if (EXPECT_false(obj->cacheEnabled == true)) {
+		Cache_inv((Ptr) obj->attrs,
+				   sizeof(heapbufmp_attrs),
+				   Cache_Type_ALL,
+				   true);
+	}
+#endif
+	/*
+	 *  The maximum number of allocations for this HeapBufMP(for any given
+	 *  instance of time during its liftime) is computed as follows:
+	 *
+	 *  max_allocated_blocks = obj->num_blocks - obj->min_free_blocks
+	 *
+	 *  Note that max_allocated_blocks is *not* the maximum allocation
+	 *  count, but rather the maximum allocations seen at any snapshot of
+	 *  time in the HeapBufMP instance.
+	 */
+	key = gatemp_enter(obj->gate);
+	/* if nothing has been alloc'ed yet, return 0 */
+	if ((s32)(obj->attrs->min_free_blocks) == -1)
+		stats->max_allocated_blocks = 0;
+	else
+		stats->max_allocated_blocks =   obj->attrs->num_blocks
+						- obj->attrs->min_free_blocks;
+
+	/*
+	 * current # of alloc'ed blocks is computed
+	 * using curr # of free blocks
+	 */
+	stats->num_allocated_blocks = obj->attrs->num_blocks
+						- obj->attrs->num_free_blocks;
+
+	gatemp_leave(obj->gate, key);
+
+	return;
+
+error:
+	printk(KERN_ERR "heapbufmp_get_extended_stats status: %x\n",
+			retval);
+}
+EXPORT_SYMBOL(heapbufmp_get_extended_stats);
+
+/*
+ * ======== heapbufmp_shared_mem_req ========
+ *  Purpose:
+ *  This will get amount of shared memory required for
+ *  creation of each instance
+ */
+int heapbufmp_shared_mem_req(const struct heapbufmp_params *params)
+{
+	int mem_req = 0;
+	struct listmp_params listmp_params;
+	u32 buf_align = 0;
+	u32 block_size = 0;
+
+	s32 status = 0;
+	u32 region_id;
+	u32 min_align;
+
+	if (WARN_ON(params == NULL)) {
+		status = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(params->block_size == 0)) {
+		status = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(params->num_blocks == 0)) {
+		status = -EINVAL;
+		goto error;
+	}
+
+	if (params->shared_addr == NULL)
+		region_id = params->region_id;
+	else
+		region_id = sharedregion_get_id(params->shared_addr);
+
+	if (region_id == SHAREDREGION_INVALIDREGIONID)  {
+		status = -EFAULT;
+		goto error;
+	}
+
+	buf_align = params->align;
+
+	min_align = 4; /* memory_get_default_type_align() */
+	if (sharedregion_get_cache_line_size(region_id) > min_align)
+		min_align = sharedregion_get_cache_line_size(region_id);
+
+	if (buf_align < min_align)
+		buf_align = min_align;
+
+	/* Determine the actual block size */
+	block_size = ROUND_UP(params->block_size, buf_align);
+
+	/* Add size of HeapBufMP Attrs */
+	mem_req = ROUND_UP(sizeof(struct heapbufmp_attrs), min_align);
+
+	/*
+	 *  Add size of ListMP Attrs.  No need to init params since it's
+	 *  not used to create.
+	 */
+	listmp_params_init(&listmp_params);
+	listmp_params.region_id = region_id;
+	mem_req += listmp_shared_mem_req(&listmp_params);
+
+	/* Round by the buffer alignment */
+	mem_req = ROUND_UP(mem_req, buf_align);
+
+	/*
+	 *  Add the buffer size. No need to subsequently round because the
+	 *  product should be a multiple of cacheLineSize if cache alignment
+	 *  is enabled
+	 */
+	mem_req += (block_size * params->num_blocks);
+
+	return mem_req;
+error:
+	printk(KERN_ERR "heapbufmp_shared_mem_req status: %x\n",
+		status);
+	return mem_req;
+}
+EXPORT_SYMBOL(heapbufmp_shared_mem_req);
+
+
+/*
+ * ======== heapbufmp_open_by_addr ========
+ *  Purpose:
+ *  Open existing heapbufmp based on address
+ */
+int
+heapbufmp_open_by_addr(void *shared_addr, void **handle_ptr)
+{
+	s32 retval = 0;
+	bool done_flag = false;
+	struct heapbufmp_attrs *attrs = NULL;
+	u16 id = 0;
+	struct heapbufmp_params params;
+	struct heapbufmp_obj *obj = NULL;
+
+	if (unlikely(atomic_cmpmask_and_lt(&(heapbufmp_module->ref_count),
+					   HEAPBUFMP_MAKE_MAGICSTAMP(0),
+					   HEAPBUFMP_MAKE_MAGICSTAMP(1))
+					  == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+	if (unlikely(handle_ptr == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* First check in the local list */
+	list_for_each_entry(obj, &heapbufmp_module->obj_list, list_elem) {
+		if (obj->params.shared_addr == shared_addr) {
+			retval = mutex_lock_interruptible(heapbufmp_module->
+								local_lock);
+			if (retval < 0)
+				goto error;
+
+			if (obj->owner.proc_id == multiproc_self())
+				obj->owner.open_count++;
+
+			mutex_unlock(heapbufmp_module->local_lock);
+			*handle_ptr = obj->top;
+			done_flag = true;
+			break;
+		}
+	}
+
+	/* If not already existing locally, create object locally for open. */
+	if (unlikely(done_flag == false)) {
+		heapbufmp_params_init(&params);
+		params.shared_addr = shared_addr;
+		attrs = (struct heapbufmp_attrs *) shared_addr;
+		id = sharedregion_get_id(shared_addr);
+#if 0
+		if (unlikely(sharedregion_is_cache_enabled(id))) {
+			Cache_inv(attrs,
+					   sizeof(heapbufmp_attrs),
+					   Cache_Type_ALL,
+					   true);
+		}
+#endif
+		if (unlikely(attrs->status != HEAPBUFMP_CREATED)) {
+			*handle_ptr = NULL;
+			retval = -ENOENT;
+			goto error;
+		}
+
+		retval = _heapbufmp_create(handle_ptr, &params, false);
+
+		if (unlikely(retval < 0))
+			goto error;
+	}
+	return 0;
+
+error:
+	printk(KERN_ERR "heapbufmp_open_by_addr status: %x\n",
+		retval);
+
+	return retval;
+}
+
+
+/* =========================================================================
+ * Internal functions
+ * =========================================================================
+ */
+/*
+ *                          Shared memory Layout:
+ *
+ *          sharedAddr   -> ---------------------------
+ *                         |  heapbufmp_attrs        |
+ *                         | (min_align PADDING)     |
+ *                         |-------------------------|
+ *                         |  ListMP shared instance |
+ *                         | (bufAlign PADDING)     |
+ *                         |-------------------------|
+ *                         |  HeapBufMP BUFFER       |
+ *                         |-------------------------|
+ */
+
+
+/*
+ * ======== heapbufmp_post_init ========
+ *  Purpose:
+ *  Slice and dice the buffer up into the correct size blocks and
+ *  add to the freelist.
+ */
+int heapbufmp_post_init(struct heapbufmp_object *handle)
+{
+	s32 retval = 0;
+	char *buf = NULL;
+	struct heapbufmp_obj *obj = NULL;
+	struct heapbufmp_object *region_heap = NULL;
+	struct heapbufmp_params params;
+	struct listmp_params listmp_params;
+	u32 min_align;
+	u32 i;
+
+	obj = (struct heapbufmp_obj *)handle->obj;
+	if (WARN_ON(obj == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	min_align = 4; /* memory_get_default_type_align() */
+	if (sharedregion_get_cache_line_size(obj->region_id) > min_align)
+		min_align = sharedregion_get_cache_line_size(obj->region_id);
+
+	if (obj->attrs == NULL) {
+		heapbufmp_params_init(&params);
+		params.region_id = obj->region_id;
+		params.num_blocks    = obj->num_blocks;
+		params.align         = obj->align;
+		params.block_size    = obj->block_size;
+		obj->alloc_size = heapbufmp_shared_mem_req(&params);
+
+		region_heap = sharedregion_get_heap(obj->region_id);
+		if (region_heap == NULL) {
+			retval = -EFAULT;
+			goto error;
+		}
+
+		obj->attrs = sl_heap_alloc(region_heap, obj->alloc_size,
+						min_align);
+		if (obj->attrs == NULL) {
+			retval = -ENOMEM;
+			goto error;
+		}
+	}
+
+	/* Store the GateMP sharedAddr in the HeapBuf Attrs */
+	obj->attrs->gatemp_addr = gatemp_get_shared_addr(obj->gate);
+
+	/* Create the free_list */
+	listmp_params_init(&listmp_params);
+	listmp_params.shared_addr = (void *)ROUND_UP((u32)obj->attrs
+					+ sizeof(struct heapbufmp_attrs),
+						min_align);
+	listmp_params.gatemp_handle = obj->gate;
+	obj->free_list = listmp_create(&listmp_params);
+	if (obj->free_list == NULL) {
+		retval = -EFAULT;
+		goto error;
+	}
+
+	/* obj->buf will get alignment-adjusted in postInit */
+	obj->buf = (void *)((u32)listmp_params.shared_addr
+			+ listmp_shared_mem_req(&listmp_params));
+	buf = obj->buf = (char *)ROUND_UP((u32)obj->buf, obj->align);
+
+	obj->attrs->num_free_blocks	= obj->num_blocks;
+	obj->attrs->min_free_blocks	= (32)-1;
+	obj->attrs->block_size		= obj->block_size;
+	obj->attrs->align		= obj->align;
+	obj->attrs->num_blocks		= obj->num_blocks;
+	obj->attrs->exact		= obj->exact ? 1 : 0;
+
+	/* Put a SRPtr in attrs */
+	obj->attrs->buf_ptr = sharedregion_get_srptr(obj->buf,
+							obj->region_id);
+	BUG_ON(obj->attrs->buf_ptr == SHAREDREGION_INVALIDSRPTR);
+
+	/*
+	 * Split the buffer into blocks that are length "block_size" and
+	 * add into the free_list Queue.
+	 */
+	for (i = 0; i < obj->num_blocks; i++) {
+		/* Add the block to the free_list */
+		retval = listmp_put_tail(obj->free_list,
+					(struct listmp_elem *)buf);
+		if (retval < 0) {
+			retval = -EFAULT;
+			goto created_free_list_error;
+		}
+
+		buf = (char *)((u32)buf + obj->block_size);
+	}
+
+	/* Last thing, set the status */
+	obj->attrs->status = HEAPBUFMP_CREATED;
+#if 0
+	if (unlikely(obj->cacheEnabled)) {
+		Cache_wbInv((Ptr) obj->attrs,
+			     sizeof(heapbufmp_attrs),
+			     Cache_Type_ALL,
+			     true);
+	}
+#endif
+	return 0;
+
+created_free_list_error:
+	listmp_delete(&obj->free_list);
+
+error:
+	printk(KERN_ERR "heapmem_post_init status: %x\n", retval);
+	return retval;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/heapbufmp_ioctl.c b/drivers/dsp/syslink/multicore_ipc/heapbufmp_ioctl.c
new file mode 100644
index 000000000000..539c4eaa6a8b
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/heapbufmp_ioctl.c
@@ -0,0 +1,459 @@
+/*
+ *  heapbufmp_ioctl.c
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/uaccess.h>
+#include <linux/types.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+#include <sharedregion.h>
+#include <heap.h>
+#include <heapbufmp.h>
+#include <heapbufmp_ioctl.h>
+
+/*
+ * ======== heapbufmp_ioctl_alloc ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_alloc function
+ */
+static int heapbufmp_ioctl_alloc(struct heapbufmp_cmd_args *cargs)
+{
+	u32 *block_srptr = SHAREDREGION_INVALIDSRPTR;
+	void *block;
+	s32 index;
+	s32 status = 0;
+
+	block = heapbufmp_alloc(cargs->args.alloc.handle,
+				cargs->args.alloc.size,
+				cargs->args.alloc.align);
+	if (block != NULL) {
+		index = sharedregion_get_id(block);
+		block_srptr = sharedregion_get_srptr(block, index);
+	}
+	/* The error on above fn will be a null ptr. We are not
+	checking that condition here. We are passing whatever
+	we are getting from the heapbuf module. So IOCTL will succed,
+	but the actual fn might be failed inside heapbuf
+	*/
+	BUG_ON(index == SHAREDREGION_INVALIDREGIONID);
+	cargs->args.alloc.block_srptr = block_srptr;
+	BUG_ON(cargs->args.alloc.block_srptr == SHAREDREGION_INVALIDSRPTR);
+	cargs->api_status = 0;
+	return status;
+}
+
+/*
+ * ======== heapbufmp_ioctl_free ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_free function
+ */
+static int heapbufmp_ioctl_free(struct heapbufmp_cmd_args *cargs)
+{
+	char *block;
+
+	block = sharedregion_get_ptr(cargs->args.free.block_srptr);
+	BUG_ON(block == NULL);
+	cargs->api_status  = heapbufmp_free(cargs->args.free.handle, block,
+					cargs->args.free.size);
+	return 0;
+}
+
+/*
+ * ======== heapbufmp_ioctl_params_init ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_params_init function
+ */
+static int heapbufmp_ioctl_params_init(struct heapbufmp_cmd_args *cargs)
+{
+	struct heapbufmp_params params;
+	s32 status = 0;
+	u32 size;
+
+	heapbufmp_params_init(&params);
+	cargs->api_status = 0;
+	size = copy_to_user(cargs->args.params_init.params, &params,
+				sizeof(struct heapbufmp_params));
+	if (size)
+		status = -EFAULT;
+
+	return status;
+}
+
+/*
+ * ======== heapbufmp_ioctl_create ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_create function
+ */
+static int heapbufmp_ioctl_create(struct heapbufmp_cmd_args *cargs)
+{
+	struct heapbufmp_params params;
+	s32 status = 0;
+	u32 size;
+	void *handle = NULL;
+
+	size = copy_from_user(&params, cargs->args.create.params,
+				sizeof(struct heapbufmp_params));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	if (cargs->args.create.name_len > 0) {
+		params.name = kmalloc(cargs->args.create.name_len, GFP_KERNEL);
+		if (params.name == NULL) {
+			status = -ENOMEM;
+			goto exit;
+		}
+
+		params.name[cargs->args.create.name_len] = '\0';
+		size = copy_from_user(params.name,
+					cargs->args.create.params->name,
+					cargs->args.create.name_len);
+		if (size) {
+			status = -EFAULT;
+			goto name_from_usr_error;
+		}
+	}
+
+	params.shared_addr = sharedregion_get_ptr((u32 *)
+				cargs->args.create.shared_addr_srptr);
+	params.gate = cargs->args.create.knl_gate;
+	handle = heapbufmp_create(&params);
+	cargs->args.create.handle = handle;
+	cargs->api_status  = 0;
+
+name_from_usr_error:
+	if (cargs->args.create.name_len > 0)
+		kfree(params.name);
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== heapbufmp_ioctl_delete ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_delete function
+ */
+static int heapbufmp_ioctl_delete(struct heapbufmp_cmd_args *cargs)
+{
+	cargs->api_status = heapbufmp_delete(&cargs->args.delete.handle);
+	return 0;
+}
+
+/*
+ * ======== heapbufmp_ioctl_open ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_open function
+ */
+static int heapbufmp_ioctl_open(struct heapbufmp_cmd_args *cargs)
+{
+	s32 status = 0;
+	u32 size = 0;
+	void *handle = NULL;
+	char *name = NULL;
+
+	if (cargs->args.open.name_len > 0) {
+		name = kmalloc(cargs->args.open.name_len, GFP_KERNEL);
+		if (name == NULL) {
+			status = -ENOMEM;
+			goto exit;
+		}
+
+		size = copy_from_user(name, cargs->args.open.name,
+					cargs->args.open.name_len);
+		if (size) {
+			status = -EFAULT;
+			goto exit;
+		}
+	}
+
+	cargs->api_status = heapbufmp_open(cargs->args.open.name, &handle);
+	cargs->args.open.handle = handle;
+
+	if (cargs->args.open.name_len > 0)
+		kfree(name);
+exit:
+	return status;
+}
+
+/*
+ * ======== heapbufmp_ioctl_open_by_addr ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_open_by_addr function
+ */
+static int heapbufmp_ioctl_open_by_addr(struct heapbufmp_cmd_args *cargs)
+{
+	void *handle = NULL;
+	void *shared_addr;
+
+	shared_addr = sharedregion_get_ptr(cargs->args.
+				open_by_addr.shared_addr_srptr);
+	cargs->api_status = heapbufmp_open_by_addr(
+				shared_addr, &handle);
+	cargs->args.open_by_addr.handle = handle;
+
+	return 0;
+}
+
+
+/*
+ * ======== heapbufmp_ioctl_close ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_close function
+ */
+static int heapbufmp_ioctl_close(struct heapbufmp_cmd_args *cargs)
+{
+	cargs->api_status = heapbufmp_close(&cargs->args.close.handle);
+	return 0;
+}
+
+/*
+ * ======== heapbufmp_ioctl_shared_mem_req ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_shared_mem_req function
+ */
+static int heapbufmp_ioctl_shared_mem_req(struct heapbufmp_cmd_args *cargs)
+{
+	struct heapbufmp_params params;
+	s32 status = 0;
+	ulong size;
+
+	size = copy_from_user(&params, cargs->args.shared_mem_req.params,
+					sizeof(struct heapbufmp_params));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	cargs->args.shared_mem_req.bytes = heapbufmp_shared_mem_req(&params);
+	cargs->api_status = 0;
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== heapbufmp_ioctl_get_config ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_get_config function
+ */
+static int heapbufmp_ioctl_get_config(struct heapbufmp_cmd_args *cargs)
+{
+	struct heapbufmp_config config;
+	s32 status = 0;
+	ulong size;
+
+	cargs->api_status = heapbufmp_get_config(&config);
+	size = copy_to_user(cargs->args.get_config.config, &config,
+					sizeof(struct heapbufmp_config));
+	if (size)
+		status = -EFAULT;
+
+	return status;
+}
+
+/*
+ * ======== heapbufmp_ioctl_setup ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_setup function
+ */
+static int heapbufmp_ioctl_setup(struct heapbufmp_cmd_args *cargs)
+{
+	struct heapbufmp_config config;
+	s32 status = 0;
+	ulong size;
+
+	size = copy_from_user(&config, cargs->args.setup.config,
+					sizeof(struct heapbufmp_config));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = heapbufmp_setup(&config);
+
+exit:
+	return status;
+}
+/*
+ * ======== heapbufmp_ioctl_destroy ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_destroy function
+ */
+static int heapbufmp_ioctl_destroy(struct heapbufmp_cmd_args *cargs)
+{
+	cargs->api_status = heapbufmp_destroy();
+	return 0;
+}
+
+
+/*
+ * ======== heapbufmp_ioctl_get_stats ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_get_stats function
+ */
+static int heapbufmp_ioctl_get_stats(struct heapbufmp_cmd_args *cargs)
+{
+	struct memory_stats stats;
+	s32 status = 0;
+	ulong size;
+
+	heapbufmp_get_stats(cargs->args.get_stats.handle, &stats);
+	cargs->api_status = 0;
+
+	size = copy_to_user(cargs->args.get_stats.stats, &stats,
+					sizeof(struct memory_stats));
+	if (size)
+		status = -EFAULT;
+
+	return status;
+}
+
+/*
+ * ======== heapbufmp_ioctl_get_extended_stats ========
+ *  Purpose:
+ *  This ioctl interface to heapbufmp_get_extended_stats function
+ */
+static int heapbufmp_ioctl_get_extended_stats(struct heapbufmp_cmd_args *cargs)
+{
+	struct heapbufmp_extended_stats stats;
+	s32 status = 0;
+	ulong size;
+	heapbufmp_get_extended_stats(cargs->args.get_extended_stats.
+							handle, &stats);
+	cargs->api_status = 0;
+
+	size = copy_to_user(cargs->args.get_extended_stats.stats, &stats,
+				sizeof(struct heapbufmp_extended_stats));
+	if (size)
+		status = -EFAULT;
+
+	return status;
+}
+
+/*
+ * ======== heapbufmp_ioctl ========
+ *  Purpose:
+ *  This ioctl interface for heapbuf module
+ */
+int heapbufmp_ioctl(struct inode *pinode, struct file *filp,
+			unsigned int cmd, unsigned long  args)
+{
+	s32 status = 0;
+	s32 size = 0;
+	struct heapbufmp_cmd_args __user *uarg =
+				(struct heapbufmp_cmd_args __user *)args;
+	struct heapbufmp_cmd_args cargs;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+
+	if (status) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg,
+					sizeof(struct heapbufmp_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_HEAPBUFMP_ALLOC:
+		status = heapbufmp_ioctl_alloc(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_FREE:
+		status = heapbufmp_ioctl_free(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_PARAMS_INIT:
+		status = heapbufmp_ioctl_params_init(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_CREATE:
+		status = heapbufmp_ioctl_create(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_DELETE:
+		status  = heapbufmp_ioctl_delete(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_OPEN:
+		status  = heapbufmp_ioctl_open(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_OPENBYADDR:
+		status  = heapbufmp_ioctl_open_by_addr(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_CLOSE:
+		status = heapbufmp_ioctl_close(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_SHAREDMEMREQ:
+		status = heapbufmp_ioctl_shared_mem_req(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_GETCONFIG:
+		status = heapbufmp_ioctl_get_config(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_SETUP:
+		status = heapbufmp_ioctl_setup(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_DESTROY:
+		status = heapbufmp_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_GETSTATS:
+		status = heapbufmp_ioctl_get_stats(&cargs);
+		break;
+
+	case CMD_HEAPBUFMP_GETEXTENDEDSTATS:
+		status = heapbufmp_ioctl_get_extended_stats(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		status = -ENOTTY;
+		break;
+	}
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs,
+				sizeof(struct heapbufmp_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+exit:
+	return status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/heapmemmp.c b/drivers/dsp/syslink/multicore_ipc/heapmemmp.c
new file mode 100644
index 000000000000..c5e1b9e163cd
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/heapmemmp.c
@@ -0,0 +1,1669 @@
+/*
+ *  heapmemmp.c
+ *
+ *  Heap module manages variable size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <atomic_linux.h>
+#include <multiproc.h>
+#include <nameserver.h>
+#include <sharedregion.h>
+#include <gatemp.h>
+#include <heapmemmp.h>
+
+/*
+ *  Name of the reserved nameserver used for heapmemmp.
+ */
+#define HEAPMEMMP_NAMESERVER			"HeapMemMP"
+#define HEAPMEMMP_MAX_NAME_LEN			32
+#define HEAPMEMMP_MAX_RUNTIME_ENTRIES	32
+#define HEAPMEMMP_CACHESIZE				128
+/* brief Macro to make a correct module magic number with ref_count */
+#define HEAPMEMMP_MAKE_MAGICSTAMP(x)	((HEAPMEMMP_MODULEID << 12) | (x))
+
+#define ROUND_UP(a, b)	(((a) + ((b) - 1)) & (~((b) - 1)))
+
+/*
+ *  Structure defining processor related information for the
+ *  heapmemmp module
+ */
+struct heapmemmp_proc_attrs {
+	bool creator; /* Creator or opener */
+	u16 proc_id; /* Processor identifier */
+	u32 open_count; /* open count in a processor */
+};
+
+/*
+ * heapmemmp header structure
+ */
+struct heapmemmp_header {
+    u32 *next; /* SRPtr to next header */
+    u32 size; /* Size of this segment */
+} heapmemmp_header;
+
+/*
+ *  Structure defining attribute parameters for the heapmemmp module
+ */
+struct heapmemmp_attrs {
+	VOLATILE u32 status; /* Module status */
+	VOLATILE u32 *buf_ptr; /* Memory managed by instance */
+	VOLATILE struct heapmemmp_header head; /* header */
+	VOLATILE u32 *gatemp_addr; /* gatemp shared address (shm safe) */
+};
+
+/*
+ *  Structure for heapmemmp module state
+ */
+struct heapmemmp_module_object {
+	atomic_t ref_count; /* Reference count */
+	void *nameserver; /* Nameserver handle */
+	struct list_head obj_list; /* List holding created objects */
+	struct mutex *local_lock; /* lock for protecting obj_list */
+	struct heapmemmp_config cfg; /* Current config values */
+	struct heapmemmp_config default_cfg; /* Default config values */
+	struct heapmemmp_params default_inst_params; /* Default instance
+						creation parameters */
+};
+
+struct heapmemmp_module_object heapmemmp_state = {
+	.obj_list = LIST_HEAD_INIT(heapmemmp_state.obj_list),
+	.default_cfg.max_name_len = HEAPMEMMP_MAX_NAME_LEN,
+	.default_cfg.max_runtime_entries = HEAPMEMMP_MAX_RUNTIME_ENTRIES,
+	.default_inst_params.gate = NULL,
+	.default_inst_params.name = NULL,
+	.default_inst_params.region_id = 0,
+	.default_inst_params.shared_addr = NULL,
+	.default_inst_params.shared_buf_size = 0,
+};
+
+/* Pointer to module state */
+static struct heapmemmp_module_object *heapmemmp_module = &heapmemmp_state;
+
+/*
+ *  Structure for the handle for the heapmemmp
+ */
+struct heapmemmp_obj {
+	struct list_head list_elem; /* Used for creating a linked list */
+	struct heapmemmp_attrs *attrs; /* The shared attributes structure */
+	void *gate; /* Lock used for critical region management */
+	void *ns_key; /* nameserver key required for remove */
+	bool cache_enabled; /* Whether to do cache calls */
+	u16 region_id; /* shared region index */
+	u32 alloc_size; /* Size of allocated shared memory */
+	char *buf; /* Pointer to allocated memory */
+	u32 min_align; /* Minimum alignment required */
+	u32 buf_size; /* Buffer Size */
+	struct heapmemmp_proc_attrs owner; /* owner processor info */
+	void *top; /* Pointer to the top object */
+	struct heapmemmp_params params; /* The creation parameter structure */
+};
+
+#define heapmemmp_object heap_object
+
+/* =============================================================================
+ * Forward declarations of internal functions
+ * =============================================================================
+ */
+static int heapmemmp_post_init(struct heapmemmp_object *handle);
+
+/* =============================================================================
+ * APIs called directly by applications
+ * =============================================================================
+ */
+
+/*
+ *  This will get default configuration for the
+ *  heapmemmp module
+ */
+int heapmemmp_get_config(struct heapmemmp_config *cfgparams)
+{
+	s32 retval = 0;
+
+	BUG_ON(cfgparams == NULL);
+
+	if (cfgparams == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true)
+		memcpy(cfgparams, &heapmemmp_module->default_cfg,
+					sizeof(struct heapmemmp_config));
+	else
+		memcpy(cfgparams, &heapmemmp_module->cfg,
+					sizeof(struct heapmemmp_config));
+	return 0;
+error:
+	printk(KERN_ERR "heapmemmp_get_config failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapmemmp_get_config);
+
+/*
+ *  This will setup the heapmemmp module
+ *
+ *  This function sets up the heapmemmp module. This function
+ *  must be called before any other instance-level APIs can be
+ *  invoked.
+ *  Module-level configuration needs to be provided to this
+ *  function. If the user wishes to change some specific config
+ *  parameters, then heapmemmp_getconfig can be called to get
+ *  the configuration filled with the default values. After this,
+ *  only the required configuration values can be changed. If the
+ *  user does not wish to make any change in the default parameters,
+ *  the application can simply call heapmemmp_setup with NULL
+ *  parameters. The default parameters would get automatically used.
+ */
+int heapmemmp_setup(const struct heapmemmp_config *cfg)
+{
+	struct nameserver_params params;
+	struct heapmemmp_config tmp_cfg;
+	s32 retval  = 0;
+
+	/* This sets the ref_count variable  not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of ref_count variable
+	*/
+	atomic_cmpmask_and_set(&heapmemmp_module->ref_count,
+					HEAPMEMMP_MAKE_MAGICSTAMP(0),
+					HEAPMEMMP_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&heapmemmp_module->ref_count)
+					!= HEAPMEMMP_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	if (cfg == NULL) {
+		heapmemmp_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	if (cfg->max_name_len == 0 ||
+		cfg->max_name_len > HEAPMEMMP_MAX_NAME_LEN) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* Initialize the parameters */
+	nameserver_params_init(&params);
+	params.max_value_len = sizeof(u32);
+	params.max_name_len = cfg->max_name_len;
+
+	/* Create the nameserver for modules */
+	heapmemmp_module->nameserver  =
+		nameserver_create(HEAPMEMMP_NAMESERVER, &params);
+	if (heapmemmp_module->nameserver == NULL) {
+		retval = -EFAULT;
+		goto error;
+	}
+
+	/* Construct the list object */
+	INIT_LIST_HEAD(&heapmemmp_module->obj_list);
+	/* Copy config info */
+	memcpy(&heapmemmp_module->cfg, cfg, sizeof(struct heapmemmp_config));
+	/* Create a lock for protecting list object */
+	heapmemmp_module->local_lock = kmalloc(sizeof(struct mutex),
+								GFP_KERNEL);
+	mutex_init(heapmemmp_module->local_lock);
+	if (heapmemmp_module->local_lock == NULL) {
+		retval = -ENOMEM;
+		heapmemmp_destroy();
+		goto error;
+	}
+
+	return 0;
+
+error:
+	printk(KERN_ERR "heapmemmp_setup failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapmemmp_setup);
+
+/*
+ *  This will destroy the heapmemmp module
+ */
+int heapmemmp_destroy(void)
+{
+	s32 retval  = 0;
+	struct mutex *lock = NULL;
+	struct heapmemmp_obj *obj = NULL;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (atomic_dec_return(&heapmemmp_module->ref_count)
+				== HEAPMEMMP_MAKE_MAGICSTAMP(0)) {
+		/* Temporarily increment ref_count here. */
+		atomic_set(&heapmemmp_module->ref_count,
+					HEAPMEMMP_MAKE_MAGICSTAMP(1));
+
+		/*  Check if any heapmemmp instances have not been
+		 *  deleted/closed so far. if there any, delete or close them
+		 */
+		list_for_each_entry(obj, &heapmemmp_module->obj_list,
+								list_elem) {
+			if (obj->owner.proc_id == multiproc_get_id(NULL))
+				retval = heapmemmp_delete(&obj->top);
+			else
+				retval = heapmemmp_close(obj->top);
+
+			if (list_empty(&heapmemmp_module->obj_list))
+				break;
+
+			if (retval < 0)
+				goto error;
+		}
+
+		/* Again reset ref_count. */
+		atomic_set(&heapmemmp_module->ref_count,
+					HEAPMEMMP_MAKE_MAGICSTAMP(0));
+
+		if (likely(heapmemmp_module->nameserver != NULL)) {
+			retval = nameserver_delete(&heapmemmp_module->
+								nameserver);
+			if (unlikely(retval != 0))
+				goto error;
+		}
+
+		/* Delete the list lock */
+		lock = heapmemmp_module->local_lock;
+		retval = mutex_lock_interruptible(lock);
+		if (retval)
+			goto error;
+
+		heapmemmp_module->local_lock = NULL;
+		mutex_unlock(lock);
+		kfree(lock);
+		memset(&heapmemmp_module->cfg, 0,
+				sizeof(struct heapmemmp_config));
+	}
+
+	return 0;
+
+error:
+	printk(KERN_ERR "heapmemmp_destroy failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapmemmp_destroy);
+
+/*
+ *  This will get the intialization prams for a heapmemmp
+ *  module instance
+ */
+void heapmemmp_params_init(struct heapmemmp_params *params)
+{
+	s32 retval  = 0;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	BUG_ON(params == NULL);
+
+	memcpy(params, &heapmemmp_module->default_inst_params,
+				sizeof(struct heapmemmp_params));
+
+	return;
+error:
+	printk(KERN_ERR "heapmemmp_params_init failed status: %x\n", retval);
+}
+EXPORT_SYMBOL(heapmemmp_params_init);
+
+/*
+ *  This will create a new instance of heapmemmp module
+ *  This is an internal function as both heapmemmp_create
+ *  and heapmemmp_open use the functionality
+ *
+ *  NOTE: The lock to protect the shared memory area
+ *  used by heapmemmp is provided by the consumer of
+ *  heapmemmp module
+ */
+int _heapmemmp_create(void **handle_ptr, const struct heapmemmp_params *params,
+				u32 create_flag)
+{
+	s32 retval  = 0;
+	struct heapmemmp_obj *obj = NULL;
+	struct heapmemmp_object *handle = NULL;
+	void *gate_handle = NULL;
+	void *local_addr = NULL;
+	u32 *shared_shm_base;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	BUG_ON(handle_ptr == NULL);
+
+	BUG_ON(params == NULL);
+
+	/* No need for parameter checks, since this is an internal function. */
+
+	/* Initialize return parameter. */
+	*handle_ptr = NULL;
+
+	handle = kmalloc(sizeof(struct heapmemmp_object), GFP_KERNEL);
+	if (handle == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+
+	obj =  kmalloc(sizeof(struct heapmemmp_obj), GFP_KERNEL);
+	if (obj == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+
+	handle->obj = (struct heapmemmp_obj *)obj;
+	handle->alloc = &heapmemmp_alloc;
+	handle->free  = &heapmemmp_free;
+	handle->get_stats = &heapmemmp_get_stats;
+	handle->is_blocking = &heapmemmp_isblocking;
+
+	obj->ns_key = NULL;
+	obj->alloc_size = 0;
+
+	/* Put in local ilst */
+	retval = mutex_lock_interruptible(heapmemmp_module->local_lock);
+	if (retval < 0)
+		goto error;
+
+	INIT_LIST_HEAD(&obj->list_elem);
+	list_add(&heapmemmp_module->obj_list, &obj->list_elem);
+	mutex_unlock(heapmemmp_module->local_lock);
+
+	if (create_flag == false) {
+		obj->owner.creator = false;
+		obj->owner.open_count = 0;
+		obj->owner.proc_id = MULTIPROC_INVALIDID;
+		obj->top = handle;
+
+		obj->attrs = (struct heapmemmp_attrs *) params->shared_addr;
+
+		/* No need to Cache_inv- already done in openByAddr() */
+		obj->buf = (char *) sharedregion_get_ptr((u32 *)obj->
+							attrs->buf_ptr);
+		obj->buf_size	  = obj->attrs->head.size;
+		obj->region_id	 = sharedregion_get_id(obj->buf);
+		obj->cache_enabled = sharedregion_is_cache_enabled(obj->
+								region_id);
+
+		/* Set min_align */
+		obj->min_align = sizeof(struct heapmemmp_header);
+		if (sharedregion_get_cache_line_size(obj->region_id)
+			> obj->min_align) {
+			obj->min_align = sharedregion_get_cache_line_size(
+							obj->region_id);
+		}
+
+		local_addr = sharedregion_get_ptr((u32 *)obj->attrs->
+								gatemp_addr);
+		retval = gatemp_open_by_addr(local_addr, &gate_handle);
+		if (retval < 0) {
+			retval = -EFAULT;
+			goto error;
+		}
+		obj->gate = gate_handle;
+
+
+	} else {
+		obj->owner.creator = true;
+		obj->owner.open_count = 1;
+		obj->owner.proc_id = multiproc_self();
+		obj->top = handle;
+
+		/* Creating the gate */
+		if (params->gate != NULL)
+			obj->gate = params->gate;
+		else {
+			/* If no gate specified, get the default system gate */
+			obj->gate = gatemp_get_default_remote();
+		}
+
+		if (obj->gate == NULL) {
+			retval = -EFAULT;
+			goto error;
+		}
+
+		obj->buf_size = params->shared_buf_size;
+
+		if (params->shared_addr == NULL) {
+			/* Creating using a shared region ID */
+			/* It is allowed to have NULL name for an anonymous,
+			 * not to be opened by name, heap.
+			 */
+			/* Will be allocated in post_init */
+			obj->attrs = NULL;
+			obj->region_id = params->region_id;
+		} else {
+			/* Creating using shared_addr */
+			obj->region_id = sharedregion_get_id(params->
+								shared_addr);
+
+			/* Assert that the buffer is in a valid shared
+			 * region
+			 */
+			if (obj->region_id == SHAREDREGION_INVALIDREGIONID) {
+				retval = -EFAULT;
+				goto error;
+			} else if ((u32) params->shared_addr
+				 % sharedregion_get_cache_line_size(obj->
+				region_id) != 0) {
+				retval = -EFAULT;
+				goto error;
+			}
+			/* obj->buf will get alignment-adjusted in
+			 * postInit
+			 */
+			obj->buf = (char *)((u32)params->shared_addr + \
+						sizeof(struct heapmemmp_attrs));
+			obj->attrs = (struct heapmemmp_attrs *)
+							params->shared_addr;
+		}
+
+		obj->cache_enabled = sharedregion_is_cache_enabled(
+							   obj->region_id);
+
+		/* Set min_align */
+		obj->min_align = sizeof(struct heapmemmp_header);
+		if (sharedregion_get_cache_line_size(obj->region_id)
+			> obj->min_align)
+			obj->min_align = sharedregion_get_cache_line_size(
+							obj->region_id);
+		retval = heapmemmp_post_init(handle);
+		if (retval < 0) {
+			retval = -EFAULT;
+			goto error;
+		}
+
+		/* Populate the params member */
+		memcpy(&obj->params, params, sizeof(struct heapmemmp_params));
+		if (params->name != NULL) {
+			obj->params.name = kmalloc(strlen(params->name) + 1,
+								GFP_KERNEL);
+			if (obj->params.name == NULL) {
+				retval  = -ENOMEM;
+				goto error;
+			}
+			strncpy(obj->params.name, params->name,
+						strlen(params->name) + 1);
+		}
+
+		/* We will store a shared pointer in the NameServer */
+		shared_shm_base = sharedregion_get_srptr(obj->attrs,
+							   obj->region_id);
+		if (obj->params.name != NULL) {
+			obj->ns_key =
+			  nameserver_add_uint32(heapmemmp_module->nameserver,
+						params->name,
+						(u32) shared_shm_base);
+			if (obj->ns_key == NULL) {
+				retval = -EFAULT;
+				goto error;
+			}
+		}
+	}
+
+	*handle_ptr = (void *)handle;
+	return retval;
+
+error:
+	/* Do whatever cleanup is required*/
+	if (create_flag == true)
+		heapmemmp_delete(handle_ptr);
+	else
+		heapmemmp_close(handle_ptr);
+	printk(KERN_ERR "_heapmemmp_create failed status: %x\n", retval);
+	return retval;
+}
+
+/*
+ *  This will create a new instance of heapmemmp module
+ */
+void *heapmemmp_create(const struct heapmemmp_params *params)
+{
+	s32 retval = 0;
+	struct heapmemmp_object *handle = NULL;
+	struct heapmemmp_params sparams;
+
+	BUG_ON(params == NULL);
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (params == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (params->shared_buf_size == 0) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	memcpy(&sparams, (void *)params, sizeof(struct heapmemmp_params));
+	retval = _heapmemmp_create((void **)&handle, params, true);
+	if (retval < 0)
+		goto error;
+
+	return (void *)handle;
+
+error:
+	printk(KERN_ERR "heapmemmp_create failed status: %x\n", retval);
+	return (void *)handle;
+}
+EXPORT_SYMBOL(heapmemmp_create);
+
+/*
+ *  This will delete an instance of heapmemmp module
+ */
+int heapmemmp_delete(void **handle_ptr)
+{
+	int status = 0;
+	struct heapmemmp_object *handle = NULL;
+	struct heapmemmp_obj *obj = NULL;
+	struct heapmemmp_params *params = NULL;
+	struct heapmemmp_object *region_heap = NULL;
+	s32 retval = 0;
+	int *key = 0;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(handle_ptr == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	handle = (struct heapmemmp_object *)(*handle_ptr);
+	if (WARN_ON(handle == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	obj = (struct heapmemmp_obj *)handle->obj;
+	if (obj != NULL) {
+		if (obj->owner.proc_id != multiproc_self()) {
+			status = -ENODEV;
+			goto error;
+		}
+
+		/* Take the local lock */
+		key = gatemp_enter(obj->gate);
+
+		if (obj->owner.open_count > 1) {
+			retval = -ENODEV;
+			goto device_busy_error;
+		}
+
+		retval = mutex_lock_interruptible(heapmemmp_module->local_lock);
+		if (retval < 0)
+			goto lock_error;
+
+		/* Remove frmo the local list */
+		list_del(&obj->list_elem);
+
+		mutex_unlock(heapmemmp_module->local_lock);
+
+		params = (struct heapmemmp_params *) &obj->params;
+
+		if (likely(params->name != NULL)) {
+			if (likely(obj->ns_key != NULL)) {
+				nameserver_remove_entry(heapmemmp_module->
+					nameserver, obj->ns_key);
+				obj->ns_key = NULL;
+			}
+			kfree(params->name);
+		}
+
+		/* Set status to 'not created' */
+	    if (obj->attrs != NULL) {
+#if 0
+			obj->attrs->status = 0;
+			if (obj->cache_enabled) {
+				cache_wbinv(obj->attrs,
+					sizeof(struct heapmemmp_attrs),
+					CACHE_TYPE_ALL, true);
+			}
+#endif
+		}
+
+		/* Release the shared lock */
+		gatemp_leave(obj->gate, key);
+
+		/* If necessary, free shared memory  if memory is internally
+		 * allocated
+		 */
+		region_heap = sharedregion_get_heap(obj->region_id);
+
+		if ((region_heap != NULL) &&
+			(obj->params.shared_addr == NULL) &&
+			(obj->attrs != NULL)) {
+			sl_heap_free(region_heap, obj->attrs, obj->alloc_size);
+		}
+
+		kfree(obj);
+		kfree(region_heap);
+
+		*handle_ptr = NULL;
+	} else {	/* obj == NULL */
+		kfree(handle);
+		*handle_ptr = NULL;
+	}
+
+	return 0;
+
+lock_error:
+device_busy_error:
+	gatemp_leave(obj->gate, key);
+
+error:
+	printk(KERN_ERR "heapmemmp_delete failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapmemmp_delete);
+
+/*
+ *  This will opens a created instance of heapmemmp
+ *  module
+ */
+int heapmemmp_open(char *name, void **handle_ptr)
+{
+	s32 retval = 0;
+	u32 *shared_shm_base = SHAREDREGION_INVALIDSRPTR;
+	void *shared_addr = NULL;
+	struct heapmemmp_obj *obj = NULL;
+	bool done_flag = false;
+	struct list_head *elem = NULL;
+
+	BUG_ON(name  == NULL);
+	BUG_ON(handle_ptr == NULL);
+
+	if (unlikely(
+		atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (name == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (handle_ptr == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* First check in the local list */
+	list_for_each(elem, &heapmemmp_module->obj_list) {
+		obj = (struct heapmemmp_obj *)elem;
+		if (obj->params.name != NULL) {
+			if (strcmp(obj->params.name, name)
+				== 0) {
+				retval = mutex_lock_interruptible(
+					heapmemmp_module->local_lock);
+				if (retval < 0)
+					goto error;
+				/* Check if we have created the heapmemmp */
+				/* or not */
+				if (obj->owner.proc_id == multiproc_self())
+					obj->owner.open_count++;
+
+				*handle_ptr = (void *)obj->top;
+				mutex_unlock(heapmemmp_module->local_lock);
+				done_flag = true;
+				break;
+			}
+		}
+	}
+
+	if (likely(done_flag == false)) {
+		/* Find in name server */
+		retval = nameserver_get_uint32(heapmemmp_module->nameserver,
+						name,
+						&shared_shm_base,
+						NULL);
+		if (unlikely(retval < 0))
+			goto error;
+
+		/*
+		 * Convert from shared region pointer to local address
+		 */
+		shared_addr = sharedregion_get_ptr(shared_shm_base);
+		if (unlikely(shared_addr == NULL)) {
+			retval = -EINVAL;
+			goto error;
+		}
+
+		retval = heapmemmp_open_by_addr(shared_addr, handle_ptr);
+
+		if (unlikely(retval < 0))
+			goto error;
+	}
+
+	return 0;
+
+error:
+	printk(KERN_ERR "heapmemmp_open failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapmemmp_open);
+
+/*
+ *  This will closes previously opened/created instance
+ *  of heapmemmp module
+ */
+int heapmemmp_close(void **handle_ptr)
+{
+	struct heapmemmp_object *handle = NULL;
+	struct heapmemmp_obj *obj = NULL;
+	s32 retval = 0;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(handle_ptr == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(*handle_ptr == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	handle = (struct heapmemmp_object *)(*handle_ptr);
+	obj = (struct heapmemmp_obj *)handle->obj;
+
+	if (obj != NULL) {
+		retval = mutex_lock_interruptible(heapmemmp_module->
+								local_lock);
+		if (retval)
+			goto error;
+
+		/* opening an instance created locally */
+		if (obj->owner.proc_id == multiproc_self())
+				obj->owner.open_count--;
+
+		/* Check if HeapMemMP is opened on same processor and
+		 * this is the last closure.
+		 */
+		if ((obj->owner.creator == false) &&
+				(obj->owner.open_count == 0)) {
+			list_del(&obj->list_elem);
+
+			if (obj->gate != NULL) {
+				/* Close the instance gate */
+				gatemp_close(&obj->gate);
+			}
+
+			/* Now free the handle */
+			kfree(obj);
+			obj = NULL;
+			kfree(handle);
+			*handle_ptr = NULL;
+		}
+
+		mutex_unlock(heapmemmp_module->local_lock);
+	} else {
+		kfree(handle);
+		*handle_ptr = NULL;
+	}
+	return 0;
+
+error:
+	printk(KERN_ERR "heapmemmp_close failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapmemmp_close);
+
+/*
+ *  This will allocs a block of memory
+ */
+void *heapmemmp_alloc(void *hphandle, u32 size, u32 align)
+{
+	char *alloc_addr = NULL;
+	struct heapmemmp_object *handle = NULL;
+	struct heapmemmp_obj *obj = NULL;
+	int *key = 0;
+	struct heapmemmp_header *prev_header;
+	struct heapmemmp_header *new_header;
+	struct heapmemmp_header *cur_header;
+	u32 cur_size;
+	u32 adj_size;
+	u32 remain_size;
+	u32 adj_align;
+	u32 offset;
+	s32 retval = 0;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+	if (WARN_ON(hphandle == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(size == 0)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	handle = (struct heapmemmp_object *)(hphandle);
+	obj = (struct heapmemmp_obj *)handle->obj;
+	if (WARN_ON(obj == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	adj_size = size;
+
+	/* Make size requested a multipel of min_align */
+	offset = (adj_size & (obj->min_align - 1));
+	if (offset != 0)
+		adj_size += (obj->min_align - offset);
+
+	/*
+	 *  Make sure the alignment is at least as large as obj->min_align
+	 *  Note: adjAlign must be a power of 2 (by function constraint) and
+	 *  obj->min_align is also a power of 2,
+	 */
+	adj_align = align;
+	if (adj_align == 0)
+		adj_align =  obj->min_align;
+
+	if (adj_align & (obj->min_align - 1))
+		/* adj_align is less than obj->min_align */
+		adj_align = obj->min_align;
+
+	/* No need to Cache_inv Attrs- 'head' should be constant */
+	prev_header = (struct heapmemmp_header *) &obj->attrs->head;
+
+	key = gatemp_enter(obj->gate);
+	/*
+	 *  The block will be allocated from cur_header. Maintain a pointer to
+	 *  prev_header so prev_header->next can be updated after the alloc.
+	 */
+#if 0
+	if (unlikely(obj->cache_enabled))
+		Cache_inv(prev_header,
+			   sizeof(struct heapmemmp_header),
+			   Cache_Type_ALL,
+			   true); /* A1 */
+#endif
+	cur_header = (struct heapmemmp_header *)
+				sharedregion_get_ptr(prev_header->next);
+	/* A1 */
+
+	/* Loop over the free list. */
+	while (cur_header != NULL) {
+#if 0
+		/* Invalidate cur_header */
+		if (unlikely(obj->cache_enabled))
+			Cache_inv(cur_header,
+				  sizeof(struct heapmemmp_header),
+				  Cache_Type_ALL,
+				  true); /* A2 */
+#endif
+
+		cur_size = cur_header->size;
+
+		/*
+		 *  Determine the offset from the beginning to make sure
+		 *  the alignment request is honored.
+		 */
+		offset = (u32)cur_header & (adj_align - 1);
+		if (offset)
+			offset = adj_align - offset;
+
+		/* Internal Assert that offset is a multiple of */
+		/* obj->min_align */
+		if (((offset & (obj->min_align - 1)) != 0)) {
+			retval = -EINVAL;
+			goto error;
+		}
+		/* big enough? */
+
+		/* This is the "else" part of the next if block, but we are */
+		/* moving it here to save indent space */
+		if (cur_size < (adj_size + offset)) {
+			prev_header = cur_header;
+			cur_header = sharedregion_get_ptr(cur_header->next);
+			/* We can quit this iteration of the while loop here */
+			continue;
+		}
+
+		/* if (cur_size >= (adj_size + offset)) */
+
+		/* Set the pointer that will be returned. */
+		/* Alloc from front */
+		alloc_addr = (char *) ((u32) cur_header + offset);
+		/*
+		 *  Determine the remaining memory after the
+		 *  allocated block.
+		 *  Note: this cannot be negative because of above
+		 *  comparison.
+		 */
+		remain_size = cur_size - adj_size - offset;
+
+		/* Internal Assert that remain_size is a multiple of
+		 * obj->min_align
+		 */
+		if (((remain_size & (obj->min_align - 1)) != 0)) {
+			alloc_addr = (u32) NULL;
+			break;
+		}
+		/*
+		 *  If there is memory at the beginning (due to alignment
+		 *  requirements), maintain it in the list.
+		 *
+		 *  offset and remain_size must be multiples of sizeof(struct
+		 *  heapmemmp_header). Therefore the address of the new_header
+		 *  below must be a multiple of the sizeof(struct
+		 *  heapmemmp_header), thus maintaining the requirement.
+		 */
+		if (offset) {
+			/* Adjust the cur_header size accordingly */
+			cur_header->size = offset; /* B2 */
+			/* Cache wb at end of this if block */
+
+			/*
+			 *  If there is remaining memory, add into the free
+			 *  list.
+			 *  Note: no need to coalesce and we have heapmemmp
+			 *  locked so it is safe.
+			 */
+			if (offset && remain_size) {
+				new_header = (struct heapmemmp_header *)
+						((u32) alloc_addr + adj_size);
+
+				/* cur_header has been inv at top of 'while' */
+				/* loop */
+				new_header->next = cur_header->next;  /* B1 */
+				new_header->size = remain_size;       /* B1 */
+#if 0
+				if (unlikely(obj->cache_enabled))
+					/* Writing back cur_header will */
+					/* cache-wait */
+					Cache_wbInv(new_header,
+						sizeof(struct
+							heapmemmp_header),
+						Cache_Type_ALL,
+						false); /* B1 */
+#endif
+
+				cur_header->next = sharedregion_get_srptr
+							(new_header,
+							 obj->region_id);
+				BUG_ON(cur_header->next
+					== SHAREDREGION_INVALIDSRPTR);
+			}
+#if 0
+			/* Write back (and invalidate) new_header and */
+			/* cur_header */
+			if (unlikely(obj->cache_enabled))
+				/* B2 */
+				Cache_wbInv(cur_header,
+					 sizeof(struct heapmemmp_header),
+					 Cache_Type_ALL,
+					 true);
+#endif
+		} else if (remain_size) {
+			/*
+			 *  If there is any remaining, link it in,
+			 *  else point to the next free block.
+			 *  Note: no need to coalesce and we have heapmemmp
+			 *  locked so it is safe.
+			 */
+
+			new_header = (struct heapmemmp_header *)
+				((u32) alloc_addr + adj_size);
+
+			new_header->next = cur_header->next; /* A2, B3  */
+			new_header->size = remain_size;      /* B3      */
+
+#if 0
+			if (unlikely(obj->cache_enabled))
+				/* Writing back prev_header will cache-wait */
+				Cache_wbInv(new_header,
+				 sizeof(struct heapmemmp_header),
+				 Cache_Type_ALL,
+				 false); /* B3 */
+#endif
+
+			/* B4 */
+			prev_header->next = sharedregion_get_srptr(new_header,
+							obj->region_id);
+		} else
+			/* cur_header has been inv at top of 'while' loop */
+			prev_header->next = cur_header->next; /* A2, B4 */
+
+#if 0
+		if (unlikely(obj->cache_enabled))
+			/* B4 */
+			Cache_wbInv(prev_header,
+					 sizeof(struct heapmemmp_header),
+					 Cache_Type_ALL,
+					 true);
+#endif
+
+		/* Success, return the allocated memory */
+		break;
+
+	}
+
+	gatemp_leave(obj->gate, key);
+
+	if (alloc_addr == NULL)
+		printk(KERN_ERR "heapmemmp_alloc returned NULL\n");
+	return alloc_addr;
+
+error:
+	printk(KERN_ERR "heapmemmp_alloc failed status: %x\n", retval);
+	return NULL;
+}
+EXPORT_SYMBOL(heapmemmp_alloc);
+
+/*
+ *  This will free a block of memory
+ */
+int heapmemmp_free(void *hphandle, void *addr, u32 size)
+{
+	struct heapmemmp_object *handle = NULL;
+	s32 retval = 0;
+	struct heapmemmp_obj *obj = NULL;
+	int *key = 0;
+	struct heapmemmp_header *next_header;
+	struct heapmemmp_header *new_header;
+	struct heapmemmp_header *cur_header;
+	u32 offset;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto error;
+	}
+	if (WARN_ON(hphandle == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(addr == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	handle = (struct heapmemmp_object *)(hphandle);
+	obj = (struct heapmemmp_obj *)handle->obj;
+	if (WARN_ON(obj == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/*
+	 * obj->attrs never changes, doesn't need Gate protection
+	 * and Cache invalidate
+	 */
+	cur_header = (struct heapmemmp_header *) &(obj->attrs->head);
+
+	/* Restore size to actual allocated size */
+	offset = size & (obj->min_align - 1);
+	if (offset != 0)
+		size += obj->min_align - offset;
+
+	key = gatemp_enter(obj->gate);
+
+	new_header = (struct heapmemmp_header *) addr;
+
+#if 0
+	if (unlikely(obj->cacheEnabled)) {
+		/* A1 */
+		Cache_inv(cur_header,
+				   sizeof(struct heapmemmp_header),
+				   Cache_Type_ALL,
+				   true);
+	}
+#endif
+	next_header = sharedregion_get_ptr(cur_header->next);
+
+	if (unlikely(!(((u32)new_header >= (u32)obj->buf)
+				&& ((u32)new_header + size
+					<= (u32)obj->buf + obj->buf_size)))) {
+		retval = -EFAULT;
+		goto error;
+	}
+	/* Go down freelist and find right place for buf */
+	while ((next_header != NULL) && (next_header < new_header)) {
+#if 0
+		if (unlikely(obj->cacheEnabled))
+			Cache_inv(next_header,
+				   sizeof(struct heapmemmp_header),
+				   Cache_Type_ALL,
+				   true); /* A2 */
+#endif
+
+		/* Make sure the addr is not in this free block */
+		if (unlikely((u32)new_header < \
+				((u32)next_header + next_header->size))) {
+			/* A2 */
+			retval = -EFAULT;
+			goto error;
+		}
+
+		cur_header = next_header;
+		/* A2 */
+		next_header = sharedregion_get_ptr(next_header->next);
+	}
+
+	new_header->next = sharedregion_get_srptr(next_header,
+							obj->region_id);
+	new_header->size = size;
+
+	/* B1, A1 */
+	cur_header->next = sharedregion_get_srptr(new_header,
+							obj->region_id);
+
+	/* Join contiguous free blocks */
+	if (next_header != NULL) {
+		/*
+		 *  Verify the free size is not overlapping. Not all cases
+		 *  are detectable, but it is worth a shot. Note: only do
+		 *  this assert if next_header is non-NULL.
+		 */
+		if (unlikely(((u32)new_header + size) > (u32)next_header)) {
+			/* A2 */
+			retval = -EFAULT;
+			goto error;
+		}
+		/* Join with upper block */
+		if (((u32)new_header + size) == (u32)next_header) {
+#if 0
+			if (unlikely(obj->cacheEnabled))
+				Cache_inv(next_header,
+					   sizeof(struct heapmemmp_header),
+					   Cache_Type_ALL,
+					   true);
+#endif
+			new_header->next = next_header->next; /* A2, B2 */
+			new_header->size += next_header->size; /* A2, B2 */
+			/* Don't Cache_wbInv, this will be done later */
+		}
+	}
+
+	/*
+	 * Join with lower block. Make sure to check to see if not the
+	 * first block. No need to invalidate attrs since head
+	 * shouldn't change.
+	 */
+	if ((cur_header != &obj->attrs->head)
+		&& (((u32) cur_header + cur_header->size)
+			== (u32) new_header)) {
+		/*
+		 * Don't Cache_inv new_header since new_header has
+		 * data that hasn't been written back yet (B2)
+		 */
+		cur_header->next = new_header->next; /* B1, B2 */
+		cur_header->size += new_header->size; /* B1, B2 */
+	}
+#if 0
+		if (unlikely(obj->cacheEnabled)) {
+			Cache_wbInv(cur_header,
+					 sizeof(struct heapmemmp_header),
+					 Cache_Type_ALL,
+					 false); /* B1 */
+			Cache_wbInv(new_header,
+					 sizeof(struct heapmemmp_header),
+					 Cache_Type_ALL,
+					 true);  /* B2 */
+		}
+#endif
+
+	gatemp_leave(obj->gate, key);
+	return 0;
+
+error:
+	printk(KERN_ERR "heapmemmp_free failed status: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(heapmemmp_free);
+
+/*
+ *  This will get memory statistics
+ */
+void heapmemmp_get_stats(void *hphandle, struct memory_stats *stats)
+{
+	struct heapmemmp_object *object = NULL;
+	struct heapmemmp_obj *obj = NULL;
+	struct heapmemmp_header *cur_header = NULL;
+	int *key = 0;
+	s32 status = 0;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		status = -ENODEV;
+		goto error;
+	}
+	if (WARN_ON(hphandle == NULL)) {
+		status  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(stats == NULL)) {
+		status  = -EINVAL;
+		goto error;
+	}
+
+	object = (struct heapmemmp_object *)(hphandle);
+	obj = (struct heapmemmp_obj *)object->obj;
+	if (WARN_ON(obj == NULL)) {
+		status = -EINVAL;
+		goto error;
+	}
+
+	stats->total_size = obj->buf_size;
+	stats->total_free_size = 0; /* determined later */
+	stats->largest_free_size = 0; /* determined later */
+
+	key = gatemp_enter(obj->gate);
+	cur_header = sharedregion_get_ptr(obj->attrs->head.next);
+
+	while (cur_header != NULL) {
+#if 0
+		/* Invalidate cur_header */
+		if (unlikely(obj->cacheEnabled)) {
+			Cache_inv(cur_header,
+				   sizeof(struct heapmemmp_header),
+				   Cache_Type_ALL,
+				   true);
+		}
+#endif
+		stats->total_free_size += cur_header->size;
+		if (stats->largest_free_size < cur_header->size)
+			stats->largest_free_size = cur_header->size;
+
+		/* This condition is required to avoid assertions during call
+		 * to SharedRegion_getPtr  because at the end of the
+		 * calculation cur_header->next  will become
+		 * SHAREDREGION_INVALIDSRPTR.
+		 */
+		if (cur_header->next != SHAREDREGION_INVALIDSRPTR)
+			cur_header = sharedregion_get_ptr(cur_header->next);
+		else
+			cur_header = NULL;
+	}
+
+	gatemp_leave(obj->gate, key);
+error:
+	if (status < 0)
+		printk(KERN_ERR "heapmemmp_get_stats status: %x\n", status);
+}
+EXPORT_SYMBOL(heapmemmp_get_stats);
+
+/*
+ *  Indicate whether the heap may block during an alloc or free call
+ */
+bool heapmemmp_isblocking(void *handle)
+{
+	bool isblocking = false;
+	s32 retval  = 0;
+
+	if (WARN_ON(handle == NULL)) {
+		retval  = -EINVAL;
+		goto error;
+	}
+
+	/* TBD: Figure out how to determine whether the gate is blocking */
+	isblocking = true;
+
+	/* retval true  Heap blocks during alloc/free calls */
+	/* retval false Heap does not block during alloc/free calls */
+	return isblocking;
+
+error:
+	printk(KERN_ERR "heapmemmp_isblocking status: %x\n", retval);
+	return isblocking;
+}
+EXPORT_SYMBOL(heapmemmp_isblocking);
+
+/*
+ *  This will get extended statistics
+ */
+void heapmemmp_get_extended_stats(void *hphandle,
+				 struct heapmemmp_extended_stats *stats)
+{
+	int status = 0;
+	struct heapmemmp_object *object = NULL;
+	struct heapmemmp_obj *obj = NULL;
+
+	if (atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+				HEAPMEMMP_MAKE_MAGICSTAMP(0),
+				HEAPMEMMP_MAKE_MAGICSTAMP(1)) == true) {
+		status = -ENODEV;
+		goto error;
+	}
+	if (WARN_ON(heapmemmp_module->nameserver == NULL)) {
+		status  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(hphandle == NULL)) {
+		status  = -EINVAL;
+		goto error;
+	}
+	if (WARN_ON(stats == NULL)) {
+		status = -EINVAL;
+		goto error;
+	}
+
+	object = (struct heapmemmp_object *)hphandle;
+	obj = (struct heapmemmp_obj *)object->obj;
+	if (WARN_ON(obj == NULL)) {
+		status = -EINVAL;
+		goto error;
+	}
+
+	stats->buf   = obj->buf;
+	stats->size  = obj->buf_size;
+
+	return;
+
+error:
+	printk(KERN_ERR "heapmemmp_get_extended_stats status: %x\n",
+			status);
+}
+EXPORT_SYMBOL(heapmemmp_get_extended_stats);
+
+/*
+ *  This will get amount of shared memory required for
+ *  creation of each instance
+ */
+int heapmemmp_shared_mem_req(const struct heapmemmp_params *params)
+{
+	int mem_req = 0;
+	s32 retval = 0;
+	u32 region_id;
+	u32 min_align;
+
+	if (params == NULL) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (params->shared_addr == NULL)
+		region_id = params->region_id;
+	else
+		region_id = sharedregion_get_id(params->shared_addr);
+
+	if (region_id == SHAREDREGION_INVALIDREGIONID)  {
+		retval = -EFAULT;
+		goto error;
+	}
+
+	min_align = sizeof(struct heapmemmp_header);
+	if (sharedregion_get_cache_line_size(region_id) > min_align)
+		min_align = sharedregion_get_cache_line_size(region_id);
+
+	/* Add size of heapmemmp Attrs */
+	mem_req = ROUND_UP(sizeof(struct heapmemmp_attrs), min_align);
+
+	/* Add the buffer size */
+	mem_req += params->shared_buf_size;
+
+	/* Make sure the size is a multiple of min_align (round down) */
+	mem_req = (mem_req / min_align) * min_align;
+
+	return mem_req;
+
+error:
+	printk(KERN_ERR "heapmemmp_shared_mem_req retval: %x\n",
+		retval);
+	return mem_req;
+}
+EXPORT_SYMBOL(heapmemmp_shared_mem_req);
+
+
+/*
+ *  Open existing heapmemmp based on address
+ */
+int
+heapmemmp_open_by_addr(void *shared_addr, void **handle_ptr)
+{
+	s32 retval = 0;
+	bool done_flag = false;
+	struct heapmemmp_attrs *attrs = NULL;
+	struct list_head *elem = NULL;
+	u16 id = 0;
+	struct heapmemmp_params params;
+	struct heapmemmp_obj *obj = NULL;
+
+	BUG_ON(handle_ptr == NULL);
+	BUG_ON(shared_addr == NULL);
+
+	if (unlikely(atomic_cmpmask_and_lt(&(heapmemmp_module->ref_count),
+					HEAPMEMMP_MAKE_MAGICSTAMP(0),
+					HEAPMEMMP_MAKE_MAGICSTAMP(1))
+					 == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (unlikely(handle_ptr == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* First check in the local list */
+	list_for_each(elem, (struct list_head *)&heapmemmp_module->obj_list) {
+		if (obj->params.shared_addr == shared_addr) {
+			retval = mutex_lock_interruptible(heapmemmp_module->
+								local_lock);
+			if (retval < 0)
+				goto error;
+
+			if (obj->owner.proc_id == multiproc_self())
+				obj->owner.open_count++;
+
+			mutex_unlock(heapmemmp_module->local_lock);
+			*handle_ptr = obj->top;
+			done_flag = true;
+			break;
+		}
+	}
+
+	/* If not already existing locally, create object locally for open. */
+	if (unlikely(done_flag == false)) {
+		heapmemmp_params_init(&params);
+		params.shared_addr = shared_addr;
+		attrs = (struct heapmemmp_attrs *) shared_addr;
+		id = sharedregion_get_id(shared_addr);
+#if 0
+		if (unlikely(sharedregion_is_cache_enabled(id))) {
+			Cache_inv(attrs,
+				  sizeof(struct heapmemmp_attrs),
+				  Cache_Type_ALL,
+				  true);
+		}
+#endif
+		if (unlikely(attrs->status != HEAPMEMMP_CREATED)) {
+			*handle_ptr = NULL;
+			retval = -ENOENT;
+			goto error;
+		}
+
+		retval = _heapmemmp_create(handle_ptr, &params, false);
+
+		if (unlikely(retval < 0))
+			goto error;
+	}
+	return 0;
+
+error:
+	printk(KERN_ERR "heapmemmp_open_by_addr status: %x\n",
+		retval);
+
+	return retval;
+}
+
+
+/* =============================================================================
+ * Internal functions
+ * =============================================================================
+ */
+/*
+ *  Slice and dice the buffer up into the correct size blocks and
+ *  add to the freelist.
+ */
+int heapmemmp_post_init(struct heapmemmp_object *handle)
+{
+	s32 retval = 0;
+	struct heapmemmp_obj *obj = NULL;
+	struct heapmemmp_object *region_heap = NULL;
+	struct heapmemmp_params params;
+
+	BUG_ON(handle == NULL);
+
+	obj = (struct heapmemmp_obj *) handle->obj;
+	if (obj->attrs == NULL) {
+		heapmemmp_params_init(&params);
+		params.region_id = obj->region_id;
+		params.shared_buf_size = obj->buf_size;
+		obj->alloc_size = heapmemmp_shared_mem_req(&params);
+		region_heap = sharedregion_get_heap(obj->region_id);
+
+		if (region_heap == NULL) {
+			retval = -EFAULT;
+			goto error;
+		}
+
+		obj->attrs = sl_heap_alloc(region_heap,
+					obj->alloc_size,
+					obj->min_align);
+
+		if (obj->attrs == NULL) {
+			retval = -ENOMEM;
+			goto error;
+		}
+		obj->buf = (void *)((u32)obj->attrs +
+				sizeof(struct heapmemmp_attrs));
+	}
+
+	/* Round obj->buf up by obj->min_align */
+	obj->buf = (void *) ROUND_UP((u32)obj->buf, (obj->min_align));
+
+	if (unlikely(obj->buf_size
+			< sharedregion_get_cache_line_size(obj->region_id))) {
+		retval = -EFAULT;
+		goto error;
+	}
+
+	/* Make sure the size is a multiple of obj->min_align */
+	obj->buf_size = (obj->buf_size / obj->min_align) * obj->min_align;
+
+	obj->attrs->gatemp_addr = gatemp_get_shared_addr(obj->gate);
+	obj->attrs->buf_ptr = sharedregion_get_srptr(obj->buf, obj->region_id);
+
+	/* Store computed obj->buf_size in shared mem */
+	obj->attrs->head.size = obj->buf_size;
+
+	/* Place the initial header */
+	heapmemmp_restore((struct heapmemmp_object *) handle);
+
+	/* Last thing, set the status */
+	obj->attrs->status = HEAPMEMMP_CREATED;
+#if 0
+	if (unlikely(obj->cacheEnabled))
+		Cache_wbInv((Ptr) obj->attrs,
+					 sizeof(heapmemmp_Attrs),
+					 Cache_Type_ALL,
+					 true);
+#endif
+
+	return 0;
+error:
+	printk(KERN_ERR "heapmemmp_post_init status: %x\n",
+		retval);
+	return retval;
+}
+
+
+/*
+ *  Restore an instance to it's original created state.
+ */
+void
+heapmemmp_restore(void *handle)
+{
+	struct heapmemmp_header *beg_header = NULL;
+	struct heapmemmp_obj    *obj        = NULL;
+
+	obj = ((struct heapmemmp_object *) handle)->obj;
+	BUG_ON(obj == NULL);
+
+	/*
+	 *  Fill in the top of the memory block
+	 *  next: pointer will be NULL (end of the list)
+	 *  size: size of this block
+	 *  NOTE: no need to Cache_inv because obj->attrs->bufPtr
+	 *  should be const
+	 */
+	beg_header = (struct heapmemmp_header *) obj->buf;
+	beg_header->next = (u32 *)SHAREDREGION_INVALIDSRPTR;
+	beg_header->size = obj->buf_size;
+
+	obj->attrs->head.next = (u32 *)obj->attrs->buf_ptr;
+#if 0
+	if (unlikely(obj->cacheEnabled)) {
+		Cache_wbInv((Ptr)&(obj->attrs->head),
+				   sizeof(struct heapmemmp_header),
+				   Cache_Type_ALL,
+				   false);
+		Cache_wbInv(begHeader,
+			    sizeof(struct heapmemmp_header),
+			    Cache_Type_ALL,
+			    true);
+	}
+#endif
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/heapmemmp_ioctl.c b/drivers/dsp/syslink/multicore_ipc/heapmemmp_ioctl.c
new file mode 100644
index 000000000000..56a0828c2098
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/heapmemmp_ioctl.c
@@ -0,0 +1,478 @@
+/*
+ *  heapmemmp_ioctl.c
+ *
+ *  Heap module manages fixed size buffers that can be used
+ *  in a multiprocessor system with shared memory.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/uaccess.h>
+#include <linux/types.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+#include <heap.h>
+#include <heapmemmp_ioctl.h>
+#include <sharedregion.h>
+
+/*
+ * ======== heapmemmp_ioctl_alloc ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_alloc function
+ */
+static int heapmemmp_ioctl_alloc(struct heapmemmp_cmd_args *cargs)
+{
+	u32 *block_srptr = SHAREDREGION_INVALIDSRPTR;
+	void *block;
+	s32 index;
+	s32 status = 0;
+
+	block = heapmemmp_alloc(cargs->args.alloc.handle,
+				cargs->args.alloc.size,
+				cargs->args.alloc.align);
+	if (block != NULL) {
+		index = sharedregion_get_id(block);
+		block_srptr = sharedregion_get_srptr(block, index);
+	}
+	/* The error on above fn will be a null ptr. We are not
+	checking that condition here. We are passing whatever
+	we are getting from the heapmem module. So IOCTL will succed,
+	but the actual fn might be failed inside heapmem
+	*/
+	BUG_ON(index == SHAREDREGION_INVALIDREGIONID);
+	cargs->args.alloc.block_srptr = block_srptr;
+	BUG_ON(cargs->args.alloc.block_srptr == SHAREDREGION_INVALIDSRPTR);
+	cargs->api_status = 0;
+	return status;
+}
+
+/*
+ * ======== heapmemmp_ioctl_free ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_free function
+ */
+static int heapmemmp_ioctl_free(struct heapmemmp_cmd_args *cargs)
+{
+	char *block;
+
+	block = sharedregion_get_ptr(cargs->args.free.block_srptr);
+	BUG_ON(block == NULL);
+	cargs->api_status  = heapmemmp_free(cargs->args.free.handle, block,
+					cargs->args.free.size);
+	return 0;
+}
+
+/*
+ * ======== heapmemmp_ioctl_params_init ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_params_init function
+ */
+static int heapmemmp_ioctl_params_init(struct heapmemmp_cmd_args *cargs)
+{
+	struct heapmemmp_params params;
+	s32 status = 0;
+	u32 size;
+
+	heapmemmp_params_init(&params);
+	cargs->api_status = 0;
+	size = copy_to_user(cargs->args.params_init.params, &params,
+				sizeof(struct heapmemmp_params));
+	if (size)
+		status = -EFAULT;
+
+	return status;
+}
+
+/*
+ * ======== heapmemmp_ioctl_create ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_create function
+ */
+static int heapmemmp_ioctl_create(struct heapmemmp_cmd_args *cargs)
+{
+	struct heapmemmp_params params;
+	s32 status = 0;
+	u32 size;
+	void *handle = NULL;
+
+	size = copy_from_user(&params, cargs->args.create.params,
+				sizeof(struct heapmemmp_params));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	if (cargs->args.create.name_len > 0) {
+		params.name = kmalloc(cargs->args.create.name_len, GFP_KERNEL);
+		if (params.name == NULL) {
+			status = -ENOMEM;
+			goto exit;
+		}
+
+		params.name[cargs->args.create.name_len] = '\0';
+		size = copy_from_user(params.name,
+					cargs->args.create.params->name,
+					cargs->args.create.name_len);
+		if (size) {
+			status = -EFAULT;
+			goto name_from_usr_error;
+		}
+	}
+
+	params.shared_addr = sharedregion_get_ptr((u32 *)
+				cargs->args.create.shared_addr_srptr);
+	params.gate = cargs->args.create.knl_gate;
+	handle = heapmemmp_create(&params);
+	cargs->args.create.handle = handle;
+	cargs->api_status  = 0;
+
+name_from_usr_error:
+	if (cargs->args.create.name_len > 0)
+		kfree(params.name);
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== heapmemmp_ioctl_delete ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_delete function
+ */
+static int heapmemmp_ioctl_delete(struct heapmemmp_cmd_args *cargs)
+{
+	cargs->api_status = heapmemmp_delete(&cargs->args.delete.handle);
+	return 0;
+}
+
+/*
+ * ======== heapmemmp_ioctl_open ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_open function
+ */
+static int heapmemmp_ioctl_open(struct heapmemmp_cmd_args *cargs)
+{
+	s32 status = 0;
+	u32 size = 0;
+	void *handle = NULL;
+	char *name = NULL;
+
+	if (cargs->args.open.name_len > 0) {
+		name = kmalloc(cargs->args.open.name_len, GFP_KERNEL);
+		if (name == NULL) {
+			status = -ENOMEM;
+			goto exit;
+		}
+
+		size = copy_from_user(name, cargs->args.open.name,
+					cargs->args.open.name_len);
+		if (size) {
+			status = -EFAULT;
+			goto exit;
+		}
+	}
+
+	cargs->api_status = heapmemmp_open(cargs->args.open.name, &handle);
+	cargs->args.open.handle = handle;
+
+	if (cargs->args.open.name_len > 0)
+		kfree(name);
+exit:
+	return status;
+}
+
+/*
+ * ======== heapmemmp_ioctl_open_by_addr ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_open_by_addr function
+ */
+static int heapmemmp_ioctl_open_by_addr(struct heapmemmp_cmd_args *cargs)
+{
+	void *handle = NULL;
+
+	cargs->api_status = heapmemmp_open_by_addr((void *)
+				cargs->args.open_by_addr.shared_addr_srptr,
+								&handle);
+	cargs->args.open_by_addr.handle = handle;
+
+	return 0;
+}
+
+
+/*
+ * ======== heapmemmp_ioctl_close ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_close function
+ */
+static int heapmemmp_ioctl_close(struct heapmemmp_cmd_args *cargs)
+{
+	cargs->api_status = heapmemmp_close(cargs->args.close.handle);
+	return 0;
+}
+
+/*
+ * ======== heapmemmp_ioctl_shared_mem_req ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_shared_mem_req function
+ */
+static int heapmemmp_ioctl_shared_mem_req(struct heapmemmp_cmd_args *cargs)
+{
+	struct heapmemmp_params params;
+	s32 status = 0;
+	ulong size;
+	u32 bytes;
+
+	size = copy_from_user(&params, cargs->args.shared_mem_req.params,
+					sizeof(struct heapmemmp_params));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+	if (params.shared_addr != NULL) {
+		params.shared_addr = sharedregion_get_ptr(
+				cargs->args.shared_mem_req.shared_addr_srptr);
+	}
+	bytes = heapmemmp_shared_mem_req(&params);
+	cargs->args.shared_mem_req.bytes = bytes;
+	cargs->api_status = 0;
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== heapmemmp_ioctl_get_config ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_get_config function
+ */
+static int heapmemmp_ioctl_get_config(struct heapmemmp_cmd_args *cargs)
+{
+	struct heapmemmp_config config;
+	s32 status = 0;
+	ulong size;
+
+	cargs->api_status = heapmemmp_get_config(&config);
+	size = copy_to_user(cargs->args.get_config.config, &config,
+					sizeof(struct heapmemmp_config));
+	if (size)
+		status = -EFAULT;
+
+	return status;
+}
+
+/*
+ * ======== heapmemmp_ioctl_setup ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_setup function
+ */
+static int heapmemmp_ioctl_setup(struct heapmemmp_cmd_args *cargs)
+{
+	struct heapmemmp_config config;
+	s32 status = 0;
+	ulong size;
+
+	size = copy_from_user(&config, cargs->args.setup.config,
+					sizeof(struct heapmemmp_config));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = heapmemmp_setup(&config);
+
+exit:
+	return status;
+}
+/*
+ * ======== heapmemmp_ioctl_destroy ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_destroy function
+ */
+static int heapmemmp_ioctl_destroy(struct heapmemmp_cmd_args *cargs)
+{
+	cargs->api_status = heapmemmp_destroy();
+	return 0;
+}
+
+
+/*
+ * ======== heapmemmp_ioctl_get_stats ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_get_stats function
+ */
+static int heapmemmp_ioctl_get_stats(struct heapmemmp_cmd_args *cargs)
+{
+	struct memory_stats stats;
+	s32 status = 0;
+	ulong size;
+
+	heapmemmp_get_stats(cargs->args.get_stats.handle, &stats);
+	cargs->api_status = 0;
+
+	size = copy_to_user(cargs->args.get_stats.stats, &stats,
+					sizeof(struct memory_stats));
+	if (size)
+		status = -EFAULT;
+
+	return status;
+}
+
+/*
+ * ======== heapmemmp_ioctl_get_extended_stats ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_get_extended_stats function
+ */
+static int heapmemmp_ioctl_get_extended_stats(struct heapmemmp_cmd_args *cargs)
+{
+	struct heapmemmp_extended_stats stats;
+	s32 status = 0;
+	ulong size;
+
+	heapmemmp_get_extended_stats(cargs->args.get_extended_stats.handle,
+								&stats);
+	cargs->api_status = 0;
+
+	size = copy_to_user(cargs->args.get_extended_stats.stats, &stats,
+				sizeof(struct heapmemmp_extended_stats));
+	if (size)
+		status = -EFAULT;
+
+	return status;
+}
+
+/*
+ * ======== heapmemmp_ioctl_restore ========
+ *  Purpose:
+ *  This ioctl interface to heapmemmp_get_extended_stats function
+ */
+static int heapmemmp_ioctl_restore(struct heapmemmp_cmd_args *cargs)
+{
+	heapmemmp_restore(cargs->args.restore.handle);
+	cargs->api_status = 0;
+	return 0;
+}
+
+/*
+ * ======== heapmemmp_ioctl ========
+ *  Purpose:
+ *  This ioctl interface for heapmem module
+ */
+int heapmemmp_ioctl(struct inode *pinode, struct file *filp,
+			unsigned int cmd, unsigned long  args)
+{
+	s32 status = 0;
+	s32 size = 0;
+	struct heapmemmp_cmd_args __user *uarg =
+				(struct heapmemmp_cmd_args __user *)args;
+	struct heapmemmp_cmd_args cargs;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+
+	if (status) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg,
+					sizeof(struct heapmemmp_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_HEAPMEMMP_ALLOC:
+		status = heapmemmp_ioctl_alloc(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_FREE:
+		status = heapmemmp_ioctl_free(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_PARAMS_INIT:
+		status = heapmemmp_ioctl_params_init(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_CREATE:
+		status = heapmemmp_ioctl_create(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_DELETE:
+		status  = heapmemmp_ioctl_delete(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_OPEN:
+		status  = heapmemmp_ioctl_open(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_OPENBYADDR:
+		status  = heapmemmp_ioctl_open_by_addr(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_CLOSE:
+		status = heapmemmp_ioctl_close(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_SHAREDMEMREQ:
+		status = heapmemmp_ioctl_shared_mem_req(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_GETCONFIG:
+		status = heapmemmp_ioctl_get_config(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_SETUP:
+		status = heapmemmp_ioctl_setup(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_DESTROY:
+		status = heapmemmp_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_GETSTATS:
+		status = heapmemmp_ioctl_get_stats(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_GETEXTENDEDSTATS:
+		status = heapmemmp_ioctl_get_extended_stats(&cargs);
+		break;
+
+	case CMD_HEAPMEMMP_RESTORE:
+		status = heapmemmp_ioctl_restore(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		status = -ENOTTY;
+		break;
+	}
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs,
+				sizeof(struct heapmemmp_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+exit:
+	return status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/ipc.c b/drivers/dsp/syslink/multicore_ipc/ipc.c
new file mode 100644
index 000000000000..7bcc697ce8b7
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/ipc.c
@@ -0,0 +1,1550 @@
+/*
+ *  ipc.c
+ *
+ *  This module is primarily used to configure IPC-wide settings and
+ *           initialize IPC at runtime
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+/* Standard headers */
+#include <linux/types.h>
+#include <linux/module.h>
+
+#include <syslink/atomic_linux.h>
+
+/* Module headers */
+#include <multiproc.h>
+#include <ipc.h>
+#include <platform.h>
+
+#include <gatemp.h>
+#include <sharedregion.h>
+#include <notify.h>
+#include <notify_ducatidriver.h>
+#include <notify_setup_proxy.h>
+
+#include <heap.h>
+#include <heapbufmp.h>
+#include <heapmemmp.h>
+
+#include <messageq.h>
+#include <nameserver.h>
+#include <nameserver_remotenotify.h>
+
+/* Ipu Power Management Header (ipu_pm) */
+#include "../ipu_pm/ipu_pm.h"
+/* =============================================================================
+ * Macros
+ * =============================================================================
+ */
+/* Macro to make a correct module magic number with ref_count */
+#define IPC_MAKE_MAGICSTAMP(x)((IPC_MODULEID << 16u) | (x))
+
+/* flag for starting processor synchronization */
+#define IPC_PROCSYNCSTART    1
+
+/* flag for finishing processor synchronization */
+#define IPC_PROCSYNCFINISH   2
+
+#define ROUND_UP(a, b)	(((a) + ((b) - 1)) & (~((b) - 1)))
+
+/* =============================================================================
+ * Enums & Structures
+ * =============================================================================
+ */
+
+/* The structure used for reserving memory in SharedRegion */
+struct ipc_reserved {
+	VOLATILE u32	started_key;
+	u32		*notify_sr_ptr;
+	u32		*nsrn_sr_ptr;
+	u32		*transport_sr_ptr;
+	u32		*ipu_pm_sr_ptr;
+	u32		*config_list_head;
+};
+
+
+/* head of the config list */
+struct ipc_config_head {
+	VOLATILE u32 first;
+	/* Address of first config entry */
+};
+
+
+/*
+ *  This structure captures Configuration details of a module/instance
+ *  written by a slave to synchornize with a remote slave/HOST
+ */
+struct ipc_config_entry {
+	VOLATILE u32 remote_proc_id;
+	/* Remote processor identifier */
+	VOLATILE u32 local_proc_id;
+	/* Config Entry owner processor identifier */
+	VOLATILE u32 tag;
+	/* Unique tag to distinguish config from other config entries */
+	VOLATILE u32 size;
+	/* Size of the config pointer */
+	VOLATILE u32 next;
+	/* Address of next config entry (In SRPtr format) */
+};
+
+/*
+ *  This structure defines the fields that are to be configured
+ *  between the executing processor and a remote processor.
+ */
+struct ipc_entry {
+	u16	remote_proc_id; /* the remote processor id   */
+	bool	setup_notify; /* whether to setup Notify   */
+	bool	setup_messageq; /* whether to setup messageq */
+	bool	setup_ipu_pm; /* whether to setup ipu_pm */
+};
+
+/* Ipc instance structure. */
+struct ipc_proc_entry {
+	void			*local_config_list;
+	void			*remote_config_list;
+	void			*user_obj;
+	bool			slave;
+	struct ipc_entry	entry;
+	bool			is_attached;
+};
+
+
+/* Module state structure */
+struct ipc_module_state {
+	s32			ref_count;
+	atomic_t		start_ref_count;
+	void			*ipc_shared_addr;
+	void			*gatemp_shared_addr;
+	enum ipc_proc_sync	proc_sync;
+	struct ipc_config	cfg;
+	struct ipc_proc_entry	proc_entry[MULTIPROC_MAXPROCESSORS];
+};
+
+
+/* =============================================================================
+ * Forward declaration
+ * =============================================================================
+ */
+/*
+ *  ======== ipc_get_master_addr() ========
+ */
+static void *ipc_get_master_addr(u16 remote_proc_id, void *shared_addr);
+
+/*
+ *  ======== ipc_get_region0_reserved_size ========
+ *  Returns the amount of memory to be reserved for Ipc in SharedRegion 0.
+ *
+ *  This is used for synchronizing processors.
+ */
+static u32 ipc_get_region0_reserved_size(void);
+
+/*
+ *  ======== ipc_get_slave_addr() ========
+ */
+static void *ipc_get_slave_addr(u16 remote_proc_id, void *shared_addr);
+
+/*
+ *  ======== ipc_proc_sync_start ========
+ *  Starts the process of synchronizing processors.
+ *
+ *  Shared memory in region 0 will be used.  The processor which owns
+ *  SharedRegion 0 writes its reserve memory address in region 0
+ *  to let the other processors know it has started.  It then spins
+ *  until the other processors start.  The other processors write their
+ *  reserve memory address in region 0 to let the owner processor
+ *  know they've started.  The other processors then spin until the
+ *  owner processor writes to let them know its finished the process
+ *  of synchronization before continuing.
+ */
+static int ipc_proc_sync_start(u16 remote_proc_id, void *shared_addr);
+
+/*
+ *  ======== ipc_proc_sync_finish ========
+ *  Finishes the process of synchronizing processors.
+ *
+ *  Each processor writes its reserve memory address in SharedRegion 0
+ *  to let the other processors know its finished the process of
+ *  synchronization.
+ */
+static int ipc_proc_sync_finish(u16 remote_proc_id, void *shared_addr);
+
+/*
+ *  ======== ipc_reserved_size_per_proc ========
+ *  The amount of memory required to be reserved per processor.
+ */
+static u32 ipc_reserved_size_per_proc(void);
+
+/* TODO: figure these out */
+#define gate_enter_system() 0
+#define gate_leave_system(key) {}
+
+/* =============================================================================
+ * Globals
+ * =============================================================================
+ */
+static struct ipc_module_state ipc_module_state = {
+	.proc_sync = IPC_PROCSYNC_ALL,
+	.ref_count = 0,
+};
+static struct ipc_module_state *ipc_module = &ipc_module_state;
+
+/* =============================================================================
+ * APIs
+ * =============================================================================
+ */
+/*
+ * ========== ipc_attach ==========
+ * attaches to a remote processor
+ */
+int ipc_attach(u16 remote_proc_id)
+{
+	int status = 0;
+#if 0
+	u32 reserved_size = ipc_reserved_size_per_proc();
+	bool cache_enabled = sharedregion_is_cache_enabled(0);
+#endif
+	void *notify_shared_addr;
+	void *msgq_shared_addr;
+	void *nsrn_shared_addr;
+	void *ipu_pm_shared_addr;
+	u32 notify_mem_req;
+	VOLATILE struct ipc_reserved *slave;
+	struct ipc_proc_entry *ipc;
+
+	/* determine if self is master or slave */
+	if (multiproc_self() < remote_proc_id)
+		ipc_module->proc_entry[remote_proc_id].slave = true;
+	else
+		ipc_module->proc_entry[remote_proc_id].slave = false;
+
+	/* determine the slave's slot */
+	slave = ipc_get_slave_addr(remote_proc_id, ipc_module->ipc_shared_addr);
+#if 0
+	if (cache_enabled)
+		Cache_inv((void *)slave, reserved_size, Cache_Type_ALL, true);
+#endif
+	/* get the attach paramters associated with remote_proc_id */
+	ipc = &(ipc_module->proc_entry[remote_proc_id]);
+
+	/* Synchronize the processors. */
+	status = ipc_proc_sync_start(remote_proc_id, ipc_module->
+							ipc_shared_addr);
+
+	if (status < 0)
+		printk(KERN_ERR "ipc_attach : ipc_proc_sync_start "
+			"failed [0x%x]\n", status);
+	else
+		printk(KERN_ERR "ipc_proc_sync_start : status [0x%x]\n",
+			status);
+
+
+	if (status >= 0) {
+		/* must be called before SharedRegion_attach */
+		status = gatemp_attach(remote_proc_id, ipc_module->
+							gatemp_shared_addr);
+		if (status < 0)
+			printk(KERN_ERR "ipc_attach : gatemp_attach "
+				"failed [0x%x]\n", status);
+		else
+			printk(KERN_ERR "gatemp_attach : status [0x%x]\n",
+				status);
+
+	}
+
+	/* retrieves the SharedRegion Heap handles */
+	if (status >= 0) {
+		status = sharedregion_attach(remote_proc_id);
+		if (status < 0)
+			printk(KERN_ERR "ipc_attach : sharedregion_attach "
+				"failed [0x%x]\n", status);
+		else
+			printk(KERN_ERR "sharedregion_attach : status "
+				"[0x%x]\n", status);
+	}
+
+	/* attach Notify if not yet attached and specified to set internal
+								setup */
+	if (status >= 0 && !notify_is_registered(remote_proc_id, 0) &&
+		(ipc->entry.setup_notify)) {
+		/* call notify_attach */
+		if (ipc_module->proc_entry[remote_proc_id].slave) {
+			notify_mem_req = notify_shared_mem_req(remote_proc_id,
+				ipc_module->ipc_shared_addr);
+			notify_shared_addr = sl_heap_alloc(
+					sharedregion_get_heap(0),
+					notify_mem_req,
+					sharedregion_get_cache_line_size(0));
+			memset(notify_shared_addr, 0, notify_mem_req);
+			slave->notify_sr_ptr = sharedregion_get_srptr(
+							notify_shared_addr, 0);
+			if (slave->notify_sr_ptr ==
+						SHAREDREGION_INVALIDSRPTR) {
+				status = IPC_E_FAIL;
+				printk(KERN_ERR "ipc_attach : "
+					"sharedregion_get_srptr "
+					"failed [0x%x]\n", status);
+			} else {
+				printk(KERN_ERR
+					"sharedregion_get_srptr : "
+					"status [0x%x]\n", status);
+			}
+		} else {
+			notify_shared_addr = sharedregion_get_ptr(slave->
+							notify_sr_ptr);
+			if (notify_shared_addr == NULL) {
+				status = IPC_E_FAIL;
+				printk(KERN_ERR "ipc_attach : "
+					"sharedregion_get_ptr "
+					"failed [0x%x]\n", status);
+			} else {
+				printk(KERN_ERR
+					"sharedregion_get_ptr : "
+					"status [0x%x]\n", status);
+			}
+		}
+
+		if (status >= 0) {
+			status = notify_attach(remote_proc_id,
+							notify_shared_addr);
+			if (status < 0)
+				printk(KERN_ERR "ipc_attach : "
+					"notify_attach "
+					"failed [0x%x]\n", status);
+			else
+					printk(KERN_ERR
+						"notify_attach : "
+						"status [0x%x]\n", status);
+		}
+	}
+
+	/* Must come before Notify because depends on default Notify */
+	if (status >= 0 && ipc->entry.setup_notify && ipc->entry.setup_ipu_pm) {
+		if (ipc_module->proc_entry[remote_proc_id].slave) {
+			ipu_pm_shared_addr = sl_heap_alloc
+					(sharedregion_get_heap(0),
+					ipu_pm_mem_req(NULL),
+					sharedregion_get_cache_line_size(0));
+
+			slave->ipu_pm_sr_ptr =
+				sharedregion_get_srptr(ipu_pm_shared_addr, 0);
+			if (slave->ipu_pm_sr_ptr ==
+					SHAREDREGION_INVALIDSRPTR) {
+				status = IPC_E_FAIL;
+				printk(KERN_ERR "ipc_attach : "
+					"sharedregion_get_srptr "
+					"failed [0x%x]\n", status);
+			} else {
+				printk(KERN_ERR
+					"sharedregion_get_srptr : "
+					"status [0x%x]\n", status);
+			}
+		} else {
+			ipu_pm_shared_addr =
+				sharedregion_get_ptr(slave->ipu_pm_sr_ptr);
+			if (ipu_pm_shared_addr == NULL) {
+				status = IPC_E_FAIL;
+				printk(KERN_ERR "ipc_attach : "
+					"sharedregion_get_ptr "
+					"failed [0x%x]\n", status);
+			} else {
+				printk(KERN_ERR
+					"sharedregion_get_ptr : "
+					"status [0x%x]\n", status);
+			}
+		}
+
+		if (status >= 0) {
+			/* create the nameserver_remotenotify instances */
+			status = ipu_pm_attach(remote_proc_id,
+							ipu_pm_shared_addr);
+
+			if (status < 0)
+				printk(KERN_ERR "ipc_attach : "
+					"ipu_pm_attach "
+					"failed [0x%x]\n", status);
+			else
+				printk(KERN_ERR
+					"ipu_pm_attach : "
+					"status [0x%x]\n", status);
+		}
+	}
+	/* Must come after gatemp_start because depends on default GateMP */
+	if (status >= 0 && ipc->entry.setup_notify) {
+		if (ipc_module->proc_entry[remote_proc_id].slave) {
+			nsrn_shared_addr = sl_heap_alloc(
+					sharedregion_get_heap(0),
+					nameserver_remotenotify_shared_mem_req(
+									NULL),
+					sharedregion_get_cache_line_size(0));
+
+			slave->nsrn_sr_ptr =
+				sharedregion_get_srptr(nsrn_shared_addr, 0);
+			if (slave->nsrn_sr_ptr == SHAREDREGION_INVALIDSRPTR) {
+				status = IPC_E_FAIL;
+				printk(KERN_ERR "ipc_attach : "
+					"sharedregion_get_srptr "
+					"failed [0x%x]\n", status);
+			} else {
+				printk(KERN_ERR
+					"sharedregion_get_srptr : "
+					"status [0x%x]\n", status);
+			}
+		} else {
+			nsrn_shared_addr =
+				sharedregion_get_ptr(slave->nsrn_sr_ptr);
+			if (nsrn_shared_addr == NULL) {
+				status = IPC_E_FAIL;
+				printk(KERN_ERR "ipc_attach : "
+					"sharedregion_get_ptr "
+					"failed [0x%x]\n", status);
+			} else {
+				printk(KERN_ERR
+					"sharedregion_get_ptr : "
+					"status [0x%x]\n", status);
+			}
+		}
+
+		if (status >= 0) {
+			/* create the nameserver_remotenotify instances */
+			status = nameserver_remotenotify_attach(remote_proc_id,
+							nsrn_shared_addr);
+
+			if (status < 0)
+				printk(KERN_ERR "ipc_attach : "
+					"nameserver_remotenotify_attach "
+					"failed [0x%x]\n", status);
+			else
+				printk(KERN_ERR
+					"nameserver_remotenotify_attach : "
+					"status [0x%x]\n", status);
+		}
+	}
+
+	/* Must come after gatemp_start because depends on default GateMP */
+	if (status >= 0 && ipc->entry.setup_messageq) {
+		if (ipc_module->proc_entry[remote_proc_id].slave) {
+			msgq_shared_addr = sl_heap_alloc
+					(sharedregion_get_heap(0),
+					messageq_shared_mem_req(ipc_module->
+							ipc_shared_addr),
+					sharedregion_get_cache_line_size(0));
+
+			slave->transport_sr_ptr =
+				sharedregion_get_srptr(msgq_shared_addr, 0);
+			if (slave->transport_sr_ptr ==
+					SHAREDREGION_INVALIDSRPTR) {
+				status = IPC_E_FAIL;
+				printk(KERN_ERR "ipc_attach : "
+					"sharedregion_get_srptr "
+					"failed [0x%x]\n", status);
+			} else {
+				printk(KERN_ERR
+					"sharedregion_get_srptr : "
+					"status [0x%x]\n", status);
+			}
+		} else {
+			msgq_shared_addr = sharedregion_get_ptr(slave->
+							transport_sr_ptr);
+			if (msgq_shared_addr == NULL) {
+				status = IPC_E_FAIL;
+				printk(KERN_ERR "ipc_attach : "
+					"sharedregion_get_ptr "
+					"failed [0x%x]\n", status);
+			} else {
+				printk(KERN_ERR
+					"sharedregion_get_ptr : "
+					"status [0x%x]\n", status);
+			}
+		}
+
+		if (status >= 0) {
+			/* create the messageq Transport instances */
+			status = messageq_attach(remote_proc_id,
+							msgq_shared_addr);
+			if (status < 0)
+				printk(KERN_ERR "ipc_attach : "
+					"messageq_attach "
+					"failed [0x%x]\n", status);
+			else
+				printk(KERN_ERR
+					"messageq_attach : "
+					"status [0x%x]\n", status);
+		}
+	}
+#if 0
+	if (cache_enabled) {
+		if (ipc_module->proc_entry[remote_proc_id].slave)
+			Cache_wbInv((void *)slave, reserved_size,
+						Cache_Type_ALL, true);
+	}
+#endif
+
+	if (status >= 0) {
+		/* Finish the processor synchronization */
+		status = ipc_proc_sync_finish(remote_proc_id,
+						ipc_module->ipc_shared_addr);
+		if (status < 0)
+			printk(KERN_ERR "ipc_attach : "
+				"ipc_proc_sync_finish "
+				"failed [0x%x]\n", status);
+		else
+			printk(KERN_ERR
+				"ipc_proc_sync_finish : "
+				"status [0x%x]\n", status);
+	}
+
+	if (status >= 0)
+		ipc->is_attached = true;
+	else
+		printk(KERN_ERR "ipc_attach failed! status = 0x%x\n", status);
+
+	return status;
+}
+
+
+/*
+ * ============= ipc_detach ==============
+ * detaches from a remote processor
+ */
+int ipc_detach(u16 remote_proc_id)
+{
+	int status = 0;
+#if 0
+	u32 reserved_size = ipc_reserved_size_per_proc();
+#endif
+	bool cache_enabled = sharedregion_is_cache_enabled(0);
+	void *ipu_pm_shared_addr;
+	void *notify_shared_addr;
+	void *nsrn_shared_addr;
+	void *msgq_shared_addr;
+	VOLATILE struct ipc_reserved *slave;
+	VOLATILE struct ipc_reserved *master;
+	struct ipc_proc_entry *ipc;
+	u32 nsrn_mem_req = nameserver_remotenotify_shared_mem_req(NULL);
+		/* prefetching into local variable because of
+					later space restrictions */
+
+	/* get the paramters associated with remote_proc_id */
+	ipc = &(ipc_module->proc_entry[remote_proc_id]);
+
+	if (ipc->is_attached == false) {
+		status = IPC_E_INVALIDSTATE;
+		goto exit;
+	}
+
+	/* determine the slave's slot */
+	slave = ipc_get_slave_addr(remote_proc_id, ipc_module->
+							ipc_shared_addr);
+
+	if (slave != NULL) {
+#if 0
+		if (unlikely(cache_enabled))
+			Cache_inv((void *) slave, reserved_size,
+						Cache_Type_ALL, true);
+#endif
+		if (ipc->entry.setup_messageq) {
+			/* call messageq_detach for remote processor */
+			status = messageq_detach(remote_proc_id);
+			if (status < 0)
+				printk(KERN_ERR "ipc_detach : "
+					"messageq_detach "
+					"failed [0x%x]\n", status);
+			else
+				printk(KERN_ERR
+					"messageq_detach : "
+					"status [0x%x]\n", status);
+
+			/* free the memory if slave processor */
+			if (ipc_module->proc_entry[remote_proc_id].slave) {
+				/* get the pointer to messageq transport
+							instance */
+				msgq_shared_addr = sharedregion_get_ptr(
+						slave->transport_sr_ptr);
+
+				if (msgq_shared_addr != NULL) {
+					/* free the memory back to sharedregion
+								0 heap */
+					sl_heap_free(sharedregion_get_heap(0),
+						msgq_shared_addr,
+						messageq_shared_mem_req(
+							msgq_shared_addr));
+				}
+
+				/* set the pointer for messageq transport
+						instance back to invalid */
+				slave->transport_sr_ptr =
+						SHAREDREGION_INVALIDSRPTR;
+			}
+		}
+
+		if (ipc->entry.setup_notify) {
+			/* call nameserver_remotenotify_detach for
+							remote processor */
+			status = nameserver_remotenotify_detach(
+							remote_proc_id);
+			if (status < 0)
+				printk(KERN_ERR "ipc_detach : "
+					"nameserver_remotenotify_detach "
+					"failed [0x%x]\n", status);
+			else
+				printk(KERN_ERR
+					"nameserver_remotenotify_detach : "
+					"status [0x%x]\n", status);
+
+			/* free the memory if slave processor */
+			if (ipc_module->proc_entry[remote_proc_id].slave) {
+				/* get the pointer to NSRN instance */
+				nsrn_shared_addr = sharedregion_get_ptr(
+							slave->nsrn_sr_ptr);
+
+				if (nsrn_shared_addr != NULL)
+					/* free the memory back to
+							SharedRegion 0 heap */
+					sl_heap_free(sharedregion_get_heap(0),
+						nsrn_shared_addr,
+						nsrn_mem_req);
+
+				/* set the pointer for NSRN instance back
+								to invalid */
+				slave->nsrn_sr_ptr =
+						SHAREDREGION_INVALIDSRPTR;
+			}
+		}
+
+		if (ipc->entry.setup_notify && ipc->entry.setup_ipu_pm) {
+			/* call ipu_pm_detach for remote processor */
+			status = ipu_pm_detach(remote_proc_id);
+			if (status < 0)
+				printk(KERN_ERR "ipc_detach : "
+					"ipu_pm_detach "
+					"failed [0x%x]\n", status);
+			else
+				printk(KERN_ERR
+					"ipu_pm_detach : "
+					"status [0x%x]\n", status);
+
+			/* free the memory if slave processor */
+			if (ipc_module->proc_entry[remote_proc_id].slave) {
+				/* get the pointer to NSRN instance */
+				ipu_pm_shared_addr = sharedregion_get_ptr(
+							slave->ipu_pm_sr_ptr);
+
+				if (ipu_pm_shared_addr != NULL)
+					/* free the memory back to
+							SharedRegion 0 heap */
+					sl_heap_free(sharedregion_get_heap(1),
+						ipu_pm_shared_addr,
+						ipu_pm_mem_req(NULL));
+
+				/* set the pointer for NSRN instance back
+								to invalid */
+				slave->ipu_pm_sr_ptr =
+						SHAREDREGION_INVALIDSRPTR;
+			}
+		}
+
+		if (ipc->entry.setup_notify) {
+			/* call notify_detach for remote processor */
+			status = notify_detach(remote_proc_id);
+			if (status < 0)
+				printk(KERN_ERR "ipc_detach : "
+					"notify_detach "
+					"failed [0x%x]\n", status);
+			else
+				printk(KERN_ERR
+					"notify_detach : "
+					"status [0x%x]\n", status);
+
+			/* free the memory if slave processor */
+			if (ipc_module->proc_entry[remote_proc_id].slave) {
+				/* get the pointer to Notify instance */
+				notify_shared_addr = sharedregion_get_ptr(
+							slave->notify_sr_ptr);
+
+				if (notify_shared_addr != NULL) {
+					/* free the memory back to
+							SharedRegion 0 heap */
+					sl_heap_free(sharedregion_get_heap(0),
+						notify_shared_addr,
+						notify_shared_mem_req(
+							remote_proc_id,
+							notify_shared_addr));
+				}
+
+				/* set the pointer for Notify instance
+							back to invalid */
+				slave->notify_sr_ptr =
+						SHAREDREGION_INVALIDSRPTR;
+			}
+		}
+
+		if (unlikely(cache_enabled)) {
+			if (ipc_module->proc_entry[remote_proc_id].slave) {
+				slave->started_key = 0;
+				slave->config_list_head =
+						SHAREDREGION_INVALIDSRPTR;
+#if 0
+				Cache_wbInv((void *)slave, reserved_size,
+							Cache_Type_ALL, true);
+#endif
+			} else {
+				/* determine the master's slot */
+				master = ipc_get_master_addr(remote_proc_id,
+						ipc_module->ipc_shared_addr);
+
+				if (master != NULL) {
+					master->started_key = 0;
+					master->config_list_head =
+						SHAREDREGION_INVALIDSRPTR;
+#if 0
+					Cache_wbInv((void *) master,
+								reserved_size,
+								Cache_Type_ALL,
+								true);
+#endif
+				}
+			}
+		}
+
+		/* Now detach the SharedRegion */
+		status = sharedregion_detach(remote_proc_id);
+		BUG_ON(status < 0);
+
+		/* Now detach the GateMP */
+		status = gatemp_detach(remote_proc_id, ipc_module->
+							gatemp_shared_addr);
+		BUG_ON(status < 0);
+	}
+	ipc->is_attached = false;
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_detach failed with status [0x%x]\n",
+								status);
+	return status;
+}
+
+
+/*
+ * ========= ipc_control ==========
+ * Function to destroy an ipc instance for a slave
+ */
+int
+ipc_control(u16 proc_id, u32 cmd_id, void *arg)
+{
+	int status = IPC_S_SUCCESS;
+
+	switch (cmd_id) {
+	case IPC_CONTROLCMD_LOADCALLBACK:
+	{
+#if defined CONFIG_SYSLINK_USE_SYSMGR
+		status = platform_load_callback(proc_id, arg);
+		if (status < 0)
+			printk(KERN_ERR "ipc_control : platform_load_callback "
+				"failed [0x%x]\n", status);
+#endif
+	}
+	break;
+
+	case IPC_CONTROLCMD_STARTCALLBACK:
+	{
+#if defined CONFIG_SYSLINK_USE_SYSMGR
+		status = platform_start_callback(proc_id, arg);
+		if (status < 0)
+			printk(KERN_ERR "ipc_control : platform_start_callback"
+				" failed [0x%x]\n", status);
+#endif
+	}
+	break;
+
+	case IPC_CONTROLCMD_STOPCALLBACK:
+	{
+#if defined CONFIG_SYSLINK_USE_SYSMGR
+		status = platform_stop_callback(proc_id, arg);
+		if (status < 0)
+			printk(KERN_ERR "ipc_control : platform_stop_callback"
+				" failed [0x%x]\n", status);
+#endif
+	}
+	break;
+
+	default:
+	{
+		status = -EINVAL;
+		printk(KERN_ERR "ipc_control : invalid "
+				" command code [0x%x]\n", cmd_id);
+	}
+	break;
+	}
+
+	return status;
+}
+
+
+/*
+ *  ======== ipc_get_master_addr ========
+ */
+void *ipc_get_master_addr(u16 remote_proc_id, void *shared_addr)
+{
+	u32 reserved_size = ipc_reserved_size_per_proc();
+	int slot;
+	u16 master_id;
+	VOLATILE struct ipc_reserved *master;
+
+	/* determine the master's proc_id and slot */
+	if (multiproc_self() < remote_proc_id) {
+		master_id = remote_proc_id;
+		slot = multiproc_self();
+	} else {
+		master_id = multiproc_self();
+		slot = remote_proc_id;
+	}
+
+	/* determine the reserve address for master between self and remote */
+	master = (struct ipc_reserved *)((u32)shared_addr +
+			((master_id * reserved_size) +
+			(slot * sizeof(struct ipc_reserved))));
+
+	return (void *)master;
+}
+
+/*
+ *  ======== ipc_get_region0_reserved_size ========
+ */
+u32 ipc_get_region0_reserved_size(void)
+{
+	u32 reserved_size = ipc_reserved_size_per_proc();
+
+	/* Calculate the total amount to reserve */
+	reserved_size = reserved_size * multiproc_get_num_processors();
+
+	return reserved_size;
+}
+
+/*
+ *  ======== Ipc_getSlaveAddr ========
+ */
+void *ipc_get_slave_addr(u16 remote_proc_id, void *shared_addr)
+{
+	u32 reserved_size = ipc_reserved_size_per_proc();
+	int slot;
+	u16 slave_id;
+	VOLATILE struct ipc_reserved *slave;
+
+	/* determine the slave's proc_id and slot */
+	if (multiproc_self() < remote_proc_id) {
+		slave_id = multiproc_self();
+		slot = remote_proc_id - 1;
+	} else {
+		slave_id = remote_proc_id;
+		slot = multiproc_self() - 1;
+	}
+
+	/* determine the reserve address for slave between self and remote */
+	slave = (struct ipc_reserved *)((u32)shared_addr +
+			((slave_id * reserved_size) +
+			(slot * sizeof(struct ipc_reserved))));
+
+	return (void *)slave;
+}
+
+/*
+ *  ======== Ipc_proc_syncStart ========
+ *  The owner of SharedRegion 0 writes to its reserve memory address
+ *  in region 0 to let the other processors know it has started.
+ *  It then spins until the other processors start.
+ *  The other processors write their reserve memory address in
+ *  region 0 to let the owner processor know they've started.
+ *  The other processors then spin until the owner processor writes
+ *  to let them know that its finished the process of synchronization
+ *  before continuing.
+ */
+int ipc_proc_sync_start(u16 remote_proc_id, void *shared_addr)
+{
+#if 0
+	u32 reserved_size = ipc_reserved_size_per_proc();
+	bool cache_enabled = sharedregion_is_cache_enabled(0);
+#endif
+	int status = 0;
+	VOLATILE struct ipc_reserved *self;
+	VOLATILE struct ipc_reserved *remote;
+	struct ipc_proc_entry *ipc;
+
+	/* don't do any synchronization if proc_sync is NONE */
+	if (ipc_module->proc_sync != IPC_PROCSYNC_NONE) {
+		/* determine self and remote pointers */
+		if (ipc_module->proc_entry[remote_proc_id].slave) {
+			self = ipc_get_slave_addr(remote_proc_id, shared_addr);
+			remote = ipc_get_master_addr(remote_proc_id,
+								shared_addr);
+		} else {
+			self = ipc_get_master_addr(remote_proc_id, shared_addr);
+			remote = ipc_get_slave_addr(remote_proc_id,
+								shared_addr);
+		}
+
+		/* construct the config list */
+		ipc = &(ipc_module->proc_entry[remote_proc_id]);
+
+		ipc->local_config_list = (void *)&self->config_list_head;
+		ipc->remote_config_list = (void *)&remote->config_list_head;
+
+		((struct ipc_config_head *)ipc->local_config_list)->first =
+						(u32)SHAREDREGION_INVALIDSRPTR;
+#if 0
+		if (cache_enabled) {
+			Cache_wbInv(ipc->local_config_list,
+					 reserved_size,
+					 Cache_Type_ALL,
+					 true);
+		}
+#endif
+
+		if (ipc_module->proc_entry[remote_proc_id].slave) {
+			/* set my processor's reserved key to start */
+			self->started_key = IPC_PROCSYNCSTART;
+#if 0
+			/* write back my processor's reserve key */
+			if (cache_enabled)
+				Cache_wbInv((void *)self, reserved_size,
+							Cache_Type_ALL, true);
+
+			/* wait for remote processor to start */
+			if (cache_enabled)
+				Cache_inv((void *)remote, reserved_size,
+							Cache_Type_ALL, true);
+#endif
+			if (remote->started_key != IPC_PROCSYNCSTART)
+				status = IPC_E_FAIL;
+			goto exit;
+		}
+
+#if 0
+		/*  wait for remote processor to start */
+		Cache_inv((void *)remote, reserved_size, Cache_Type_ALL, true);
+#endif
+		if ((self->started_key != IPC_PROCSYNCSTART) &&
+			(remote->started_key != IPC_PROCSYNCSTART)) {
+			status = IPC_E_FAIL;
+			goto exit;
+		}
+
+		if (status >= 0) {
+			/* set my processor's reserved key to start */
+			self->started_key = IPC_PROCSYNCSTART;
+#if 0
+			/* write my processor's reserve key back */
+			if (cache_enabled)
+				Cache_wbInv((void *)self, reserved_size,
+							Cache_Type_ALL, true);
+
+			/* wait for remote processor to finish */
+			Cache_inv((void *)remote, reserved_size,
+							Cache_Type_ALL, true);
+#endif
+			if (remote->started_key != IPC_PROCSYNCFINISH) {
+				status = IPC_E_FAIL;
+				goto exit;
+			}
+		}
+	}
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_proc_sync_start failed: status [0x%x]\n",
+								status);
+	else
+		printk(KERN_ERR "ipc_proc_sync_start done\n");
+
+	return status;
+}
+
+/*
+ *  ======== Ipc_proc_syncFinish ========
+ *  Each processor writes its reserve memory address in SharedRegion 0
+ *  to let the other processors know its finished the process of
+ *  synchronization.
+ */
+int ipc_proc_sync_finish(u16 remote_proc_id, void *shared_addr)
+{
+#if 0
+	u32 reserved_size = ipc_reserved_size_per_proc();
+	bool cache_enabled = sharedregion_is_cache_enabled(0);
+#endif
+	VOLATILE struct ipc_reserved *self;
+	VOLATILE struct ipc_reserved *remote;
+
+	/* don't do any synchronization if proc_sync is NONE */
+	if (ipc_module->proc_sync != IPC_PROCSYNC_NONE) {
+		/* determine self pointer */
+		if (ipc_module->proc_entry[remote_proc_id].slave) {
+			self = ipc_get_slave_addr(remote_proc_id, shared_addr);
+			remote = ipc_get_master_addr(remote_proc_id,
+					shared_addr);
+		} else {
+			self = ipc_get_master_addr(remote_proc_id,
+								shared_addr);
+			remote = ipc_get_slave_addr(remote_proc_id,
+								shared_addr);
+		}
+		/* set my processor's reserved key to finish */
+		self->started_key = IPC_PROCSYNCFINISH;
+#if 0
+		/* write back my processor's reserve key */
+		if (cache_enabled)
+			Cache_wbInv((void *)self, reserved_size,
+						Cache_Type_ALL, true);
+#endif
+		/* if slave processor, wait for remote to finish sync */
+		if (ipc_module->proc_entry[remote_proc_id].slave) {
+			/* wait for remote processor to finish */
+			do {
+#if 0
+				if (cacheEnabled) {
+					Cache_inv((Ptr)remote, reservedSize,
+						Cache_Type_ALL, TRUE);
+				}
+#endif
+			} while (remote->started_key != IPC_PROCSYNCFINISH);
+		}
+	}
+
+	return IPC_S_SUCCESS;
+}
+
+/*
+ * ======== ipc_read_config ========
+ */
+int ipc_read_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size)
+{
+#if 0
+	bool cache_enabled = sharedregion_is_cache_enabled(0);
+#endif
+	int status = IPC_E_FAIL;
+	VOLATILE struct ipc_config_entry *entry;
+
+	if (ipc_module->ref_count == 0) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (ipc_module->proc_entry[remote_proc_id].is_attached == false) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+
+#if 0
+	if (cache_enabled) {
+		Cache_inv(ipc_module->proc_entry[remote_proc_id].
+						remote_config_list,
+				sharedregion_get_cache_line_size(0),
+				Cache_Type_ALL,
+				true);
+	}
+#endif
+	entry = (struct ipc_config_entry *)((struct ipc_config_head *)
+		ipc_module->proc_entry[remote_proc_id].remote_config_list)->
+									first;
+
+	while ((u32 *)entry != SHAREDREGION_INVALIDSRPTR) {
+		entry = (struct ipc_config_entry *)
+				sharedregion_get_ptr((u32 *)entry);
+		if (entry == NULL) {
+			status = IPC_E_FAIL;
+			goto exit;
+		}
+#if 0
+		/* Traverse the list to find the tag */
+		if (cache_enabled) {
+			Cache_inv((void *)entry,
+				size + sizeof(struct ipc_config_entry),
+				Cache_Type_ALL,
+				true);
+		}
+#endif
+
+		if ((entry->remote_proc_id == multiproc_self()) &&
+			(entry->local_proc_id == remote_proc_id) &&
+			(entry->tag == tag)) {
+
+			if (size == entry->size)
+				memcpy(cfg,
+					(void *)((u32)entry + sizeof(struct
+							ipc_config_entry)),
+					entry->size);
+			else
+				status = IPC_E_FAIL;
+		} else {
+			entry = (struct ipc_config_entry *)entry->next;
+		}
+	}
+
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_read_config failed: status [0x%x]\n",
+								status);
+
+	return status;
+}
+
+/*
+ *  ======== ipc_reserved_size_per_proc ========
+ */
+u32 ipc_reserved_size_per_proc(void)
+{
+	u32 reserved_size = sizeof(struct ipc_reserved) *
+					multiproc_get_num_processors();
+	u32 cache_line_size = sharedregion_get_cache_line_size(0);
+
+	/* Calculate amount to reserve per processor */
+	if (cache_line_size > reserved_size)
+		/* Use cache_line_size if larger than reserved_size */
+		reserved_size = cache_line_size;
+	else
+		/* Round reserved_size to cache_line_size */
+		reserved_size = ROUND_UP(reserved_size, cache_line_size);
+
+	return reserved_size;
+}
+
+/*!
+ *  ======== ipc_write_config ========
+ */
+int ipc_write_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size)
+{
+#if 0
+	bool cache_enabled = sharedregion_is_cache_enabled(0);
+#endif
+	u32 cache_line_size = sharedregion_get_cache_line_size(0);
+	int status = IPC_S_SUCCESS;
+	struct ipc_config_entry *entry;
+
+	if (ipc_module->ref_count == 0) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (ipc_module->proc_entry[remote_proc_id].is_attached == false) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	/* Allocate memory from the shared heap (System Heap) */
+	entry = sl_heap_alloc(sharedregion_get_heap(0),
+				size + sizeof(struct ipc_config_entry),
+				cache_line_size);
+
+	if (entry == NULL) {
+		status = IPC_E_FAIL;
+		goto exit;
+	}
+
+	entry->remote_proc_id = remote_proc_id;
+	entry->local_proc_id = multiproc_self();
+	entry->tag = tag;
+	entry->size = size;
+	memcpy((void *)((u32)entry + sizeof(struct ipc_config_entry)),
+								cfg, size);
+
+	/* Create a linked-list of config */
+	if (((struct ipc_config_head *)ipc_module->
+		proc_entry[remote_proc_id].local_config_list)->first
+		== (u32)SHAREDREGION_INVALIDSRPTR) {
+
+		entry->next = (u32)SHAREDREGION_INVALIDSRPTR;
+		((struct ipc_config_head *)ipc_module->
+			proc_entry[remote_proc_id].local_config_list)->first =
+				(u32)sharedregion_get_srptr(entry, 0);
+
+		if (((struct ipc_config_head *)ipc_module->
+			proc_entry[remote_proc_id].local_config_list)->first
+			== (u32)SHAREDREGION_INVALIDSRPTR)
+			status = IPC_E_FAIL;
+	} else {
+		entry->next = ((struct ipc_config_head *)ipc_module->
+			proc_entry[remote_proc_id].local_config_list)->first;
+
+		((struct ipc_config_head *)ipc_module->
+			proc_entry[remote_proc_id].local_config_list)->first =
+			(u32)sharedregion_get_srptr(entry, 0);
+		if (((struct ipc_config_head *)ipc_module->
+			proc_entry[remote_proc_id].local_config_list)->first
+			== (u32)SHAREDREGION_INVALIDSRPTR)
+			status = IPC_E_FAIL;
+	}
+#if 0
+	if (cache_enabled) {
+		Cache_wbInv(ipc_module->proc_entry[remote_proc_id].
+							local_config_list,
+			sharedregion_get_cache_line_size(0),
+			Cache_Type_ALL,
+			false);
+
+		Cache_wbInv(entry,
+			size + sizeof(struct ipc_config_entry),
+			Cache_Type_ALL,
+			true);
+	}
+#endif
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_write_config failed: status [0x%x]\n",
+								status);
+
+	return status;
+}
+
+
+/*
+ *  ======== ipc_start ========
+ */
+int ipc_start(void)
+{
+	int status = 0;
+	int i;
+	struct sharedregion_entry entry;
+	void *ipc_shared_addr;
+	void *gatemp_shared_addr;
+	struct gatemp_params gatemp_params;
+	bool line_available;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits
+	 * is written with module Id to ensure correctness of ref_count
+	 * variable.
+	 */
+	atomic_cmpmask_and_set(&(ipc_module->start_ref_count),
+						IPC_MAKE_MAGICSTAMP(0),
+						IPC_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&(ipc_module->start_ref_count))
+		!= IPC_MAKE_MAGICSTAMP(1u)) {
+		status = IPC_S_SUCCESS;
+		goto exit;
+	}
+
+	/* get region 0 information */
+	sharedregion_get_entry(0, &entry);
+
+	/* if entry is not valid then return */
+	if (entry.is_valid == false) {
+		status = IPC_E_FAIL;
+		goto exit;
+	}
+	/*
+	 *  Need to reserve memory in region 0 for processor synchronization.
+	 *  This must done before SharedRegion_start().
+	 */
+	ipc_shared_addr = sharedregion_reserve_memory(0,
+					ipc_get_region0_reserved_size());
+
+	/* must reserve memory for gatemp before sharedregion_start() */
+	gatemp_shared_addr = sharedregion_reserve_memory(0,
+					gatemp_get_region0_reserved_size());
+
+	/* Init params for default gate(must match those in gatemp_start() */
+	gatemp_params_init(&gatemp_params);
+	gatemp_params.local_protect = GATEMP_LOCALPROTECT_TASKLET;
+
+	if (multiproc_get_num_processors() > 1)
+		gatemp_params.remote_protect = GATEMP_REMOTEPROTECT_SYSTEM;
+	else
+		gatemp_params.remote_protect = GATEMP_REMOTEPROTECT_NONE;
+
+	/* reserve memory for default gate before SharedRegion_start() */
+	sharedregion_reserve_memory(0, gatemp_shared_mem_req(&gatemp_params));
+
+	/* clear the reserved memory */
+	sharedregion_clear_reserved_memory();
+
+	/* Set shared addresses */
+	ipc_module->ipc_shared_addr = ipc_shared_addr;
+	ipc_module->gatemp_shared_addr = gatemp_shared_addr;
+
+	/* create default GateMP, must be called before sharedregion_start */
+	status = gatemp_start(ipc_module->gatemp_shared_addr);
+	if (status < 0) {
+		status = IPC_E_FAIL;
+		goto exit;
+	}
+
+	/* create HeapMemMP in each SharedRegion */
+	status = sharedregion_start();
+	if (status < 0) {
+		status = IPC_E_FAIL;
+		goto exit;
+	}
+
+	/* Call attach for all procs if proc_sync is ALL */
+	if (ipc_module->proc_sync == IPC_PROCSYNC_ALL) {
+		/* Must attach to owner first to get default GateMP and
+		 * HeapMemMP */
+		if (multiproc_self() != entry.owner_proc_id) {
+			do {
+				status = ipc_attach(entry.owner_proc_id);
+			} while (status < 0);
+		}
+
+		/* Loop to attach to all other processors */
+		for (i = 0; i < multiproc_get_num_processors(); i++) {
+			if ((i == multiproc_self())
+					|| (i == entry.owner_proc_id))
+				continue;
+			line_available =
+				notify_setup_proxy_int_line_available(i);
+			if (!line_available)
+				continue;
+			/* call Ipc_attach for every remote processor */
+			do {
+				status = ipc_attach(i);
+			} while (status < 0);
+		}
+	}
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_start failed: status [0x%x]\n",
+								status);
+
+	return status;
+}
+
+
+/*
+ *  ======== ipc_stop ========
+ */
+int ipc_stop(void)
+{
+	int status = IPC_S_SUCCESS;
+	int tmp_status = IPC_S_SUCCESS;
+	struct sharedregion_entry entry;
+	struct gatemp_params gatemp_params;
+
+	if (unlikely(atomic_cmpmask_and_lt(&(ipc_module->start_ref_count),
+				   IPC_MAKE_MAGICSTAMP(0),
+				   IPC_MAKE_MAGICSTAMP(1)) == true)) {
+		status = IPC_E_FAIL;
+		goto exit;
+	}
+
+	if (likely(atomic_dec_return(&ipc_module->start_ref_count)
+				== IPC_MAKE_MAGICSTAMP(0))) {
+		/* get region 0 information */
+		sharedregion_get_entry(0, &entry);
+
+		/* if entry is not valid then return */
+		if (entry.is_valid == false) {
+			status = IPC_E_FAIL;
+			goto exit;
+		}
+
+
+		/*
+		*  Need to unreserve memory in region 0 for processor
+		*  synchronization. This must done before sharedregion_stop().
+		*/
+		sharedregion_unreserve_memory(0,
+					ipc_get_region0_reserved_size());
+
+		/* must unreserve memory for GateMP before
+							sharedregion_stop() */
+		sharedregion_unreserve_memory(0,
+					gatemp_get_region0_reserved_size());
+
+		/* Init params for default gate (must match those
+						in gatemp_stop() */
+		gatemp_params_init(&gatemp_params);
+		gatemp_params.local_protect = GATEMP_LOCALPROTECT_TASKLET;
+
+		if (multiproc_get_num_processors() > 1)
+			gatemp_params.remote_protect =
+					GATEMP_REMOTEPROTECT_SYSTEM;
+		else
+			gatemp_params.remote_protect =
+					GATEMP_REMOTEPROTECT_NONE;
+
+		/* unreserve memory for default gate before
+					sharedregion_stop() */
+		sharedregion_unreserve_memory(0,
+			gatemp_shared_mem_req(&gatemp_params));
+
+		/* Delete heapmemmp in each sharedregion */
+		status = sharedregion_stop();
+		if (status < 0) {
+			status = IPC_E_FAIL;
+			goto exit;
+		}
+
+		/* delete default gatemp, must be called after
+		 * sharedregion_stop
+		 */
+		tmp_status = gatemp_stop();
+		if ((tmp_status < 0) && (status >= 0)) {
+			status = IPC_E_FAIL;
+			goto exit;
+		}
+
+		ipc_module->gatemp_shared_addr = NULL;
+		ipc_module->ipc_shared_addr = NULL;
+	}
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_stop failed: status [0x%x]\n", status);
+
+	return status;
+}
+
+
+/*
+ *  ======== ipc_get_config ========
+ */
+void ipc_get_config(struct ipc_config *cfg_params)
+{
+	int key;
+	int status = 0;
+
+	BUG_ON(cfg_params == NULL);
+
+	if (cfg_params == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+
+	key = gate_enter_system();
+	if (ipc_module->ref_count == 0)
+		cfg_params->proc_sync = IPC_PROCSYNC_ALL;
+	else
+		memcpy((void *) cfg_params, (void *) &ipc_module->cfg,
+						sizeof(struct ipc_config));
+
+	gate_leave_system(key);
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_get_config failed: status [0x%x]\n",
+								status);
+
+}
+
+
+/* Sets up ipc for this processor. */
+int ipc_setup(const struct ipc_config *cfg)
+{
+	int status = IPC_S_SUCCESS;
+	struct ipc_config tmp_cfg;
+	int key;
+	int i;
+
+	key = gate_enter_system();
+	ipc_module->ref_count++;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits is
+	 * written with module Id to ensure correctness of ref_count variable.
+	 */
+	if (ipc_module->ref_count > 1) {
+		status = IPC_S_ALREADYSETUP;
+		gate_leave_system(key);
+		goto exit;
+	}
+
+	gate_leave_system(key);
+	if (cfg == NULL) {
+		ipc_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	/* Copy the cfg */
+	memcpy(&ipc_module->cfg, cfg, sizeof(struct ipc_config));
+
+	ipc_module->proc_sync = cfg->proc_sync;
+
+	status = platform_setup();
+	if (status < 0) {
+		key = gate_enter_system();
+		ipc_module->ref_count--;
+		gate_leave_system(key);
+		status = IPC_E_FAIL;
+		goto exit;
+	}
+
+	/* Following can be done regardless of status */
+	for (i = 0; i < multiproc_get_num_processors(); i++)
+		ipc_module->proc_entry[i].is_attached = false;
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_setup failed: status [0x%x]\n", status);
+
+	return status;
+}
+
+
+/*
+ * =========== ipc_destroy ==========
+ * Destroys ipc for this processor.
+ */
+int ipc_destroy(void)
+{
+	int status = IPC_S_SUCCESS;
+	int key;
+
+	key = gate_enter_system();
+	ipc_module->ref_count--;
+
+	if (ipc_module->ref_count < 0) {
+		gate_leave_system(key);
+		status = IPC_E_INVALIDSTATE;
+		goto exit;
+	}
+
+	if (ipc_module->ref_count == 0) {
+		gate_leave_system(key);
+		status = platform_destroy();
+		if (status < 0) {
+			status = IPC_E_FAIL;
+			goto exit;
+		}
+	} else
+		gate_leave_system(key);
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "ipc_destroy failed: status [0x%x]\n", status);
+
+	return status;
+}
+
+
+/*
+ * ====== ipc_create =======
+ *  Creates a IPC.
+ */
+int ipc_create(u16 remote_proc_id, struct ipc_params *params)
+{
+	ipc_module->proc_entry[remote_proc_id].entry.setup_messageq =
+							params->setup_messageq;
+	ipc_module->proc_entry[remote_proc_id].entry.setup_notify =
+							params->setup_notify;
+	ipc_module->proc_entry[remote_proc_id].entry.setup_ipu_pm =
+							params->setup_ipu_pm;
+	ipc_module->proc_entry[remote_proc_id].entry.remote_proc_id =
+							remote_proc_id;
+
+	/* Assert that the proc_sync is same as configured for the module. */
+	BUG_ON(ipc_module->proc_sync != params->proc_sync);
+
+	return IPC_S_SUCCESS;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/ipc_drv.c b/drivers/dsp/syslink/multicore_ipc/ipc_drv.c
new file mode 100644
index 000000000000..bf6966a0ba3d
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/ipc_drv.c
@@ -0,0 +1,240 @@
+/*
+ *  ipc_drv.c
+ *
+ *  IPC driver module.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kdev_t.h>
+#include <linux/fs.h>
+#include <linux/moduleparam.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+#include <linux/slab.h>
+#include <ipc_ioctl.h>
+#include <drv_notify.h>
+#include <nameserver.h>
+
+#define IPC_NAME		"syslink_ipc"
+#define IPC_MAJOR		0
+#define IPC_MINOR		0
+#define IPC_DEVICES		1
+
+struct ipc_device {
+	struct cdev cdev;
+};
+
+struct ipc_device *ipc_device;
+static struct class *ipc_class;
+
+s32 ipc_major = IPC_MAJOR;
+s32 ipc_minor = IPC_MINOR;
+char *ipc_name = IPC_NAME;
+
+module_param(ipc_name, charp, 0);
+MODULE_PARM_DESC(ipc_name, "Device name, default = syslink_ipc");
+
+module_param(ipc_major, int, 0);	/* Driver's major number */
+MODULE_PARM_DESC(ipc_major, "Major device number, default = 0 (auto)");
+
+module_param(ipc_minor, int, 0);	/* Driver's minor number */
+MODULE_PARM_DESC(ipc_minor, "Minor device number, default = 0 (auto)");
+
+MODULE_AUTHOR("Texas Instruments");
+MODULE_LICENSE("GPL v2");
+
+/*
+ * ======== ipc_open ========
+ *  This function is invoked when an application
+ *  opens handle to the ipc driver
+ */
+int ipc_open(struct inode *inode, struct file *filp)
+{
+	s32 retval = 0;
+	struct ipc_device *dev;
+
+	dev = container_of(inode->i_cdev, struct ipc_device, cdev);
+	filp->private_data = dev;
+	return retval;
+}
+
+/*
+ * ======== ipc_release ========
+ *  This function is invoked when an application
+ *  closes handle to the ipc driver
+ */
+int ipc_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+/*
+ * ======== ipc_ioctl ========
+ *  This function  provides IO interface  to the
+ *  ipc driver
+ */
+int ipc_ioctl(struct inode *ip, struct file *filp, u32 cmd, ulong arg)
+{
+	s32 retval = 0;
+	void __user *argp = (void __user *)arg;
+
+	/* Verify the memory and ensure that it is not is kernel
+	     address space
+	*/
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		retval = !access_ok(VERIFY_WRITE, argp, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		retval = !access_ok(VERIFY_READ, argp, _IOC_SIZE(cmd));
+
+	if (retval) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	retval = ipc_ioc_router(cmd, (ulong)argp);
+	return retval;
+
+exit:
+	return retval;
+}
+
+const struct file_operations ipc_fops = {
+	.open = ipc_open,
+	.release = ipc_release,
+	.ioctl = ipc_ioctl,
+	.read = notify_drv_read,
+	.mmap = notify_drv_mmap,
+};
+
+/*
+ * ======== ipc_modules_init ========
+ *  IPC Initialization routine. will initialize various
+ *  sub components (modules) of IPC.
+ */
+static int ipc_modules_init(void)
+{
+	/* Setup the notify_drv module */
+	_notify_drv_setup();
+
+	return 0;
+}
+
+/*
+ * ======== ipc_modules_exit ========
+ *  IPC cleanup routine. will cleanup of various
+ *  sub components (modules) of IPC.
+ */
+static void ipc_modules_exit(void)
+{
+	/* Destroy the notify_drv module */
+	_notify_drv_destroy();
+}
+
+/*
+ * ======== ipc_init ========
+ *  Initialization routine. Executed when the driver is
+ *  loaded (as a kernel module), or when the system
+ *  is booted (when included as part of the kernel
+ *  image).
+ */
+static int __init ipc_init(void)
+{
+	dev_t dev ;
+	s32 retval = 0;
+
+	retval = alloc_chrdev_region(&dev, ipc_minor, IPC_DEVICES,
+							ipc_name);
+	ipc_major = MAJOR(dev);
+
+	if (retval < 0) {
+		printk(KERN_ERR "ipc_init: can't get major %x\n", ipc_major);
+		goto exit;
+	}
+
+	ipc_device = kmalloc(sizeof(struct ipc_device), GFP_KERNEL);
+	if (!ipc_device) {
+		printk(KERN_ERR "ipc_init: memory allocation failed for "
+			"ipc_device\n");
+		retval = -ENOMEM;
+		goto unreg_exit;
+	}
+
+	memset(ipc_device, 0, sizeof(struct ipc_device));
+	retval = ipc_modules_init();
+	if (retval) {
+		printk(KERN_ERR "ipc_init: ipc initialization failed\n");
+		goto unreg_exit;
+
+	}
+	ipc_class = class_create(THIS_MODULE, "syslink_ipc");
+	if (IS_ERR(ipc_class)) {
+		printk(KERN_ERR "ipc_init: error creating ipc class\n");
+		retval = PTR_ERR(ipc_class);
+		goto unreg_exit;
+	}
+
+	device_create(ipc_class, NULL, MKDEV(ipc_major, ipc_minor), NULL,
+								ipc_name);
+	cdev_init(&ipc_device->cdev, &ipc_fops);
+	ipc_device->cdev.owner = THIS_MODULE;
+	retval = cdev_add(&ipc_device->cdev, dev, IPC_DEVICES);
+	if (retval) {
+		printk(KERN_ERR "ipc_init: failed to add the ipc device\n");
+		goto class_exit;
+	}
+	return retval;
+
+class_exit:
+	class_destroy(ipc_class);
+
+unreg_exit:
+	unregister_chrdev_region(dev, IPC_DEVICES);
+	kfree(ipc_device);
+
+exit:
+	return retval;
+}
+
+/*
+ * ======== ipc_exit ========
+ *  This function is invoked during unlinking of ipc
+ *  module from the kernel. ipc resources are
+ *  freed in this function.
+ */
+static void __exit ipc_exit(void)
+{
+	dev_t devno;
+
+	ipc_modules_exit();
+	devno = MKDEV(ipc_major, ipc_minor);
+	if (ipc_device) {
+		cdev_del(&ipc_device->cdev);
+		kfree(ipc_device);
+	}
+	unregister_chrdev_region(devno, IPC_DEVICES);
+	if (ipc_class) {
+		/* remove the device from sysfs */
+		device_destroy(ipc_class, MKDEV(ipc_major, ipc_minor));
+		class_destroy(ipc_class);
+	}
+}
+
+/*
+ *  ipc driver initialization and de-initialization functions
+ */
+module_init(ipc_init);
+module_exit(ipc_exit);
diff --git a/drivers/dsp/syslink/multicore_ipc/ipc_ioctl.c b/drivers/dsp/syslink/multicore_ipc/ipc_ioctl.c
new file mode 100644
index 000000000000..252f23ea73eb
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/ipc_ioctl.c
@@ -0,0 +1,69 @@
+/*
+ *  ipc_ioctl.c
+ *
+ *  This is the collection of ioctl functions that will invoke various ipc
+ *  module level functions based on user comands
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/uaccess.h>
+
+#include <ipc_ioctl.h>
+#include <multiproc_ioctl.h>
+#include <nameserver_ioctl.h>
+#include <heapbufmp_ioctl.h>
+#include <sharedregion_ioctl.h>
+#include <gatemp_ioctl.h>
+#include <listmp_ioctl.h>
+#include <messageq_ioctl.h>
+#include <sysipc_ioctl.h>
+/*#include <sysmemmgr_ioctl.h>*/
+#include <heapmemmp_ioctl.h>
+#include <drv_notify.h>
+
+/*
+ *  This will route the ioctl commands to proper modules
+ */
+int ipc_ioc_router(u32 cmd, ulong arg)
+{
+	s32 retval = 0;
+	u32 ioc_nr = _IOC_NR(cmd);
+
+	if (ioc_nr >= MULTIPROC_BASE_CMD && ioc_nr <= MULTIPROC_END_CMD)
+		retval = multiproc_ioctl(NULL, NULL, cmd, arg);
+	else if (ioc_nr >= NAMESERVER_BASE_CMD && ioc_nr <= NAMESERVER_END_CMD)
+		retval = nameserver_ioctl(NULL, NULL, cmd, arg);
+	else if (ioc_nr >= HEAPBUFMP_BASE_CMD && ioc_nr <= HEAPBUFMP_END_CMD)
+		retval = heapbufmp_ioctl(NULL, NULL, cmd, arg);
+	else if (ioc_nr >= SHAREDREGION_BASE_CMD &&
+					ioc_nr <= SHAREDREGION_END_CMD)
+		retval = sharedregion_ioctl(NULL, NULL, cmd, arg);
+	else if (ioc_nr >= GATEMP_BASE_CMD && ioc_nr <= GATEMP_END_CMD)
+		retval = gatemp_ioctl(NULL, NULL, cmd, arg);
+	else if (ioc_nr >= LISTMP_BASE_CMD && ioc_nr <= LISTMP_END_CMD)
+		retval = listmp_ioctl(NULL, NULL, cmd, arg);
+	else if (ioc_nr >= MESSAGEQ_BASE_CMD && ioc_nr <= MESSAGEQ_END_CMD)
+		retval = messageq_ioctl(NULL, NULL, cmd, arg);
+	else if (ioc_nr >= IPC_BASE_CMD && ioc_nr <= IPC_END_CMD)
+		retval = sysipc_ioctl(NULL, NULL, cmd, arg);
+/*	else if (ioc_nr >= SYSMEMMGR_BASE_CMD && ioc_nr <= SYSMEMMGR_END_CMD)
+		retval = sysmemmgr_ioctl(NULL, NULL, cmd, arg);*/
+	else if (ioc_nr >= HEAPMEMMP_BASE_CMD && ioc_nr <= HEAPMEMMP_END_CMD)
+		retval = heapmemmp_ioctl(NULL, NULL, cmd, arg);
+	else if (ioc_nr >= NOTIFY_BASE_CMD && ioc_nr <= NOTIFY_END_CMD)
+		retval = notify_drv_ioctl(NULL, NULL, cmd, arg);
+	else
+		retval = -ENOTTY;
+
+	return retval;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/listmp.c b/drivers/dsp/syslink/multicore_ipc/listmp.c
new file mode 100644
index 000000000000..466a7cbab65d
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/listmp.c
@@ -0,0 +1,1472 @@
+/*
+ *  listmp.c
+ *
+ *  The listmp is a linked-list based module designed to be
+ *  used in a multi-processor environment.  It is designed to
+ *  provide a means of communication between different processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+#include <linux/module.h>
+
+/* Utilities headers */
+#include <linux/list.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+/* Syslink headers */
+#include <syslink/atomic_linux.h>
+
+/* Module level headers */
+#include <multiproc.h>
+#include <nameserver.h>
+#include <sharedregion.h>
+#include <gatemp.h>
+#include "_listmp.h"
+#include <listmp.h>
+
+
+/* =============================================================================
+ * Globals
+ * =============================================================================
+ */
+/* Macro to make a correct module magic number with ref_count */
+#define LISTMP_MAKE_MAGICSTAMP(x)	((LISTMP_MODULEID << 12u) | (x))
+
+/* Name of the reserved NameServer used for listmp. */
+#define LISTMP_NAMESERVER		"ListMP"
+
+#define ROUND_UP(a, b)			(((a) + ((b) - 1)) & (~((b) - 1)))
+
+/* =============================================================================
+ * Structures and Enums
+ * =============================================================================
+ */
+/* structure for listmp module state */
+struct listmp_module_object {
+	atomic_t ref_count;
+	/* Reference count */
+	void *ns_handle;
+	/* Handle to the local NameServer used for storing listmp objects */
+	struct list_head obj_list;
+	/* List holding created listmp objects */
+	struct mutex *local_lock;
+	/* Handle to lock for protecting obj_list */
+	struct listmp_config cfg;
+	/* Current config values */
+	struct listmp_config default_cfg;
+	/* Default config values */
+	struct listmp_params default_inst_params;
+	/* Default instance creation parameters */
+};
+
+/* Structure for the internal Handle for the listmp. */
+struct listmp_object{
+	struct list_head list_elem;
+	/* Used for creating a linked list */
+	VOLATILE struct listmp_attrs *attrs;
+	/* Shared memory attributes */
+	void *ns_key;
+	/* nameserver key  required for remove */
+	void *gatemp_handle;
+	/* Gate for critical regions */
+	u32 alloc_size;
+	/* Shared memory allocated */
+	u16 region_id;
+	/* SharedRegion ID */
+	bool cache_enabled;
+	/* Whether to do cache calls */
+	struct listmp_proc_attrs owner;
+	/* Creator's attributes associated with an instance */
+	struct listmp_params params;
+	/* the parameter structure */
+	void *top;
+	/* Pointer to the top Object */
+};
+
+/* =============================================================================
+ * Globals
+ * =============================================================================
+ */
+/* Variable for holding state of the nameserver module. */
+static struct listmp_module_object listmp_state = {
+			.default_cfg.max_runtime_entries = 32,
+			.default_cfg.max_name_len = 32,
+			.default_inst_params.shared_addr = 0,
+			.default_inst_params.name = NULL,
+			.default_inst_params.gatemp_handle = NULL,
+			.default_inst_params.region_id = 0,
+};
+
+/* Pointer to the listmp module state */
+static struct listmp_module_object *listmp_module = &listmp_state;
+
+/* =============================================================================
+ * Function definitions
+ * =============================================================================
+ */
+/* Creates a new instance of listmp module. This is an internal
+ * function because both listmp_create and
+ * listmp_open call use the same functionality. */
+static int _listmp_create(struct listmp_object **handle_ptr,
+				struct listmp_params *params, u32 create_flag);
+
+
+/* =============================================================================
+ * Function API's
+ * =============================================================================
+ */
+/* Function to get configuration parameters to setup the listmp module. */
+void listmp_get_config(struct listmp_config *cfg_params)
+{
+	int status = 0;
+
+	if (WARN_ON(unlikely(cfg_params == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	if (atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+			LISTMP_MAKE_MAGICSTAMP(0),
+			LISTMP_MAKE_MAGICSTAMP(1)) == true) {
+		/* If setup has not yet been called) */
+		memcpy(cfg_params, &listmp_module->default_cfg,
+			sizeof(struct listmp_config));
+	} else {
+		memcpy(cfg_params, &listmp_module->cfg,
+			sizeof(struct listmp_config));
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_get_config failed: status = 0x%x\n",
+			status);
+	}
+	return;
+}
+
+/* Function to setup the listmp module. */
+int listmp_setup(const struct listmp_config *cfg)
+{
+	int status = 0;
+	int status1 = 0;
+	void *nshandle = NULL;
+	struct nameserver_params params;
+	struct listmp_config tmp_cfg;
+
+	/* This sets the ref_count variable if not initialized, upper 16 bits is
+	 * written with module Id to ensure correctness of ref_count variable.
+	 */
+	atomic_cmpmask_and_set(&listmp_module->ref_count,
+			LISTMP_MAKE_MAGICSTAMP(0),
+			LISTMP_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&listmp_module->ref_count)
+				!= LISTMP_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	if (cfg == NULL) {
+		listmp_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	if (WARN_ON(cfg->max_name_len == 0)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* Initialize the parameters */
+	nameserver_params_init(&params);
+	params.max_value_len = 4;
+	params.max_name_len = cfg->max_name_len;
+	/* Create the nameserver for modules */
+	nshandle = nameserver_create(LISTMP_NAMESERVER, &params);
+	if (unlikely(nshandle == NULL)) {
+		status = LISTMP_E_FAIL;
+		goto exit;
+	}
+	listmp_module->ns_handle = nshandle;
+
+	/* Construct the list object */
+	INIT_LIST_HEAD(&listmp_module->obj_list);
+	/* Create a lock for protecting list object */
+	listmp_module->local_lock = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (listmp_module->local_lock == NULL) {
+		status = -ENOMEM;
+		goto clean_nameserver;
+	}
+	mutex_init(listmp_module->local_lock);
+
+	/* Copy the cfg */
+	memcpy(&listmp_module->cfg, cfg, sizeof(struct listmp_config));
+	return 0;
+
+clean_nameserver:
+	status1 = nameserver_delete(&(listmp_module->ns_handle));
+	WARN_ON(status1 < 0);
+	atomic_set(&listmp_module->ref_count, LISTMP_MAKE_MAGICSTAMP(0));
+exit:
+	printk(KERN_ERR "listmp_setup failed! status = 0x%x\n", status);
+	return status;
+}
+
+/* Function to destroy the listmp module. */
+int listmp_destroy(void)
+{
+	int status = 0;
+	int status1 = 0;
+	struct list_head *elem = NULL;
+	struct list_head *head = &listmp_module->obj_list;
+	struct list_head *next;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (!(atomic_dec_return(&listmp_module->ref_count) == \
+				LISTMP_MAKE_MAGICSTAMP(0))) {
+		status = 1;
+		goto exit;
+	}
+
+	/* Temporarily increment ref_count here. */
+	atomic_set(&listmp_module->ref_count, LISTMP_MAKE_MAGICSTAMP(1));
+	/* Check if any listmp instances have not been
+	 * deleted so far. If not, delete them. */
+	for (elem = (head)->next; elem != (head); elem = next) {
+		/* Retain the next pointer so it doesn't get overwritten */
+		next = elem->next;
+		if (((struct listmp_object *) elem)->owner.proc_id == \
+			multiproc_self()) {
+			status1 = listmp_delete((void **)
+					&(((struct listmp_object *)elem)->top));
+			WARN_ON(status1 < 0);
+		} else {
+			status1 = listmp_close((void **)
+					&(((struct listmp_object *)elem)->top));
+			WARN_ON(status1 < 0);
+		}
+	}
+
+	if (likely(listmp_module->ns_handle != NULL)) {
+		/* Delete the nameserver for modules */
+		status = nameserver_delete(&(listmp_module->ns_handle));
+		WARN_ON(status < 0);
+	}
+
+	/* Destruct the list object */
+	list_del(&listmp_module->obj_list);
+	/* Delete the list lock */
+	kfree(listmp_module->local_lock);
+	listmp_module->local_lock = NULL;
+
+	memset(&listmp_module->cfg, 0, sizeof(struct listmp_config));
+
+	/* Again reset ref_count. */
+	atomic_set(&listmp_module->ref_count, LISTMP_MAKE_MAGICSTAMP(0));
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_destroy failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+
+/* Function to initialize the config-params structure with supplier-specified
+ * defaults before instance creation. */
+void listmp_params_init(struct listmp_params *params)
+{
+	s32 status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	memcpy((void *)params, (void *)&listmp_module->default_inst_params,
+		sizeof(struct listmp_params));
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_params_init failed! status = 0x%x\n",
+			status);
+	}
+	return;
+}
+
+/* Creates a new instance of listmp module. */
+void *listmp_create(const struct listmp_params *params)
+{
+	s32 status = 0;
+	struct listmp_object *obj = NULL;
+	struct listmp_params sparams;
+	u32 key;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	memcpy(&sparams, params, sizeof(struct listmp_params));
+
+	key = mutex_lock_interruptible(listmp_module->local_lock);
+	if (key)
+		goto exit;
+	status = _listmp_create(&obj, &sparams, (u32) true);
+	mutex_unlock(listmp_module->local_lock);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_create failed! status = 0x%x\n",
+			status);
+	}
+	return (void *)obj;
+}
+
+/* Deletes a instance of listmp instance object. */
+int listmp_delete(void **listmp_handleptr)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	struct listmp_params *params = NULL;
+	u32 key;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handleptr == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(*listmp_handleptr == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)(*listmp_handleptr);
+	params = (struct listmp_params *)&obj->params;
+
+	if (unlikely(obj->owner.proc_id != multiproc_self())) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (unlikely(obj->owner.open_count > 1)) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (unlikely(obj->owner.open_count != 1)) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	/* Remove from  the local list */
+	key = mutex_lock_interruptible(listmp_module->local_lock);
+	list_del(&obj->list_elem);
+	mutex_unlock(listmp_module->local_lock);
+
+	if (likely(params->name != NULL)) {
+		/* Free memory for the name */
+		kfree(params->name);
+		/* Remove from the name server */
+		if (obj->ns_key != NULL) {
+			nameserver_remove_entry(listmp_module->ns_handle,
+						obj->ns_key);
+			obj->ns_key = NULL;
+		}
+	}
+
+	/* Now free the obj */
+	kfree(obj);
+	obj = NULL;
+	*listmp_handleptr = NULL;
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_delete failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+
+/* Function to open a listmp instance */
+int listmp_open(char *name, void **listmp_handleptr)
+{
+	int status = 0;
+	void *shared_addr = NULL;
+	bool done_flag = false;
+	struct list_head *elem;
+	u32 key;
+	u32 shared_shm_base;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handleptr == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* First check in the local list */
+	list_for_each(elem, &listmp_module->obj_list) {
+		if (((struct listmp_object *)elem)->params.name != NULL) {
+			if (strcmp(((struct listmp_object *)elem)->params.name,
+				name) == 0) {
+				key = mutex_lock_interruptible(
+					listmp_module->local_lock);
+				if (((struct listmp_object *)elem)
+					->owner.proc_id == multiproc_self())
+					((struct listmp_object *)elem)
+						->owner.open_count++;
+				mutex_unlock(listmp_module->local_lock);
+				*listmp_handleptr = \
+					(((struct listmp_object *)elem)->top);
+				done_flag = true;
+				break;
+			}
+		}
+	}
+
+	if (likely(done_flag == false)) {
+		/* Find in name server */
+		status = nameserver_get_uint32(listmp_module->ns_handle,
+			name, &shared_shm_base, NULL);
+		if (unlikely(status < 0)) {
+			status = ((status == -ENOENT) ? status : -1);
+			goto exit;
+		}
+		shared_addr = sharedregion_get_ptr((u32 *)shared_shm_base);
+		if (unlikely(shared_addr == NULL)) {
+			status = LISTMP_E_FAIL;
+			goto exit;
+		}
+		status = listmp_open_by_addr(shared_addr, listmp_handleptr);
+	}
+
+#if 0
+	if (status >= 0) {
+		attrs = (struct listmp_attrs *) (params->shared_addr);
+		if (unlikely(attrs->status != (LISTMP_CREATED)))
+				status = LISTMP_E_NOTCREATED;
+		else if (unlikely(attrs->version !=
+					(LISTMP_VERSION)))
+				status = LISTMP_E_VERSION;
+	}
+
+	if (likely(status >= 0))
+		*listmp_handleptr = (listmp_handle)
+				_listmp_create(params, false);
+#endif
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "listmp_open failed! status = 0x%x\n", status);
+	return status;
+}
+
+/* Function to open a listmp instance by address */
+int listmp_open_by_addr(void *shared_addr, void **listmp_handleptr)
+{
+	int status = 0;
+	bool done_flag = false;
+	struct listmp_params params;
+	struct list_head *elem;
+	u32 key;
+	struct listmp_attrs *attrs;
+	u16 id;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(listmp_handleptr == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(shared_addr == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* First check in the local list */
+	list_for_each(elem, &listmp_module->obj_list) {
+		if (((struct listmp_object *)elem)->params.shared_addr == \
+			shared_addr) {
+			key = mutex_lock_interruptible(
+						listmp_module->local_lock);
+			if (((struct listmp_object *)elem)->owner.proc_id == \
+				multiproc_self())
+				((struct listmp_object *)elem)
+							->owner.open_count++;
+			mutex_unlock(listmp_module->local_lock);
+			*listmp_handleptr = \
+				(((struct listmp_object *)elem)->top);
+			done_flag = true;
+			break;
+		}
+	}
+
+	if (likely(done_flag == false)) {
+		listmp_params_init(&params);
+		params.shared_addr = shared_addr;
+
+		attrs = (struct listmp_attrs *)(shared_addr);
+		id = sharedregion_get_id(shared_addr);
+#if 0
+		if (sharedregion_is_cache_enabled(id))
+			Cache_inv(in_use, num * sizeof(u8), Cache_Type_ALL,
+				true);
+#endif
+		if (unlikely(attrs->status != LISTMP_CREATED)) {
+			*listmp_handleptr = NULL;
+			status = -ENOENT;
+		} else {
+			key = mutex_lock_interruptible(
+				listmp_module->local_lock);
+			status = _listmp_create((struct listmp_object **)
+						listmp_handleptr, &params,
+						(u32) false);
+			mutex_unlock(listmp_module->local_lock);
+		}
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_open failed! "
+			"status = 0x%x\n", status);
+	}
+	return status;
+}
+
+/* Function to close a previously opened instance */
+int listmp_close(void **listmp_handleptr)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	struct listmp_params *params = NULL;
+	u32 key;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handleptr == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(*listmp_handleptr == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)(*listmp_handleptr);
+	params = (struct listmp_params *)&obj->params;
+
+	key = mutex_lock_interruptible(listmp_module->local_lock);
+	if (unlikely(obj->owner.proc_id == multiproc_self()))
+		(obj)->owner.open_count--;
+
+	/* Check if ListMP is opened on same processor*/
+	if (likely((((struct listmp_object *)obj)->owner.creator == false))) {
+		list_del(&obj->list_elem);
+		/* remove from the name server */
+		if (params->name != NULL)
+			/* Free memory for the name */
+			kfree(params->name);
+		gatemp_close(&obj->gatemp_handle);
+
+		kfree(obj);
+		obj = NULL;
+		*listmp_handleptr = NULL;
+	}
+
+	mutex_unlock(listmp_module->local_lock);
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "listmp_close failed! status = 0x%x\n", status);
+	return status;
+}
+
+/* Function to check if the shared memory list is empty */
+bool listmp_empty(void *listmp_handle)
+{
+	int status = 0;
+	bool is_empty = false;
+	struct listmp_object *obj = NULL;
+	int *key;
+	struct listmp_elem *shared_head;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handle == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+	key = gatemp_enter(obj->gatemp_handle);
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)&(obj->attrs->head),
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+
+	/*  true if list is empty */
+	shared_head = (struct listmp_elem *)(sharedregion_get_srptr(
+				(void *)&(obj->attrs->head), obj->region_id));
+	dsb();
+	if (obj->attrs->head.next == shared_head)
+		is_empty = true;
+
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	return is_empty;
+}
+
+/* Retrieves the gatemp handle associated with the listmp instance. */
+void *listmp_get_gate(void *listmp_handle)
+{
+	struct listmp_object *obj = NULL;
+	void *gatemp_handle = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+	gatemp_handle = obj->gatemp_handle;
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "listmp_get_gate failed! status = 0x%x",
+			retval);
+	}
+	return gatemp_handle;
+}
+
+/* Function to get head element from a shared memory list */
+void *listmp_get_head(void *listmp_handle)
+{
+	struct listmp_object *obj = NULL;
+	struct listmp_elem *elem = NULL;
+	struct listmp_elem *local_head_next = NULL;
+	struct listmp_elem *local_next = NULL;
+	s32 retval = 0;
+	int *key = NULL;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+	key = gatemp_enter(obj->gatemp_handle);
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)&(obj->attrs->head),
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+
+	local_head_next = sharedregion_get_ptr((u32 *)obj->attrs->head.next);
+	WARN_ON(local_head_next == NULL);
+	dsb();
+	/* See if the listmp_object was empty */
+	if (local_head_next != (struct listmp_elem *)&obj->attrs->head) {
+		/* Elem to return */
+		elem = local_head_next;
+		WARN_ON(elem == NULL);
+		dsb();
+#if 0
+		if (unlikely(obj->cache_enabled)) {
+			Cache_inv((void *)local_head_next,
+				sizeof(struct listmp_elem), Cache_Type_ALL,
+				true);
+		}
+#endif
+		local_next = sharedregion_get_ptr((u32 *)elem->next);
+		WARN_ON(local_next == NULL);
+
+		/* Fix the head of the list next pointer */
+		obj->attrs->head.next = elem->next;
+		dsb();
+		/* Fix the prev pointer of the new first elem on the list */
+		local_next->prev = local_head_next->prev;
+#if 0
+		if (unlikely(obj->cache_enabled)) {
+			Cache_inv((void *)&(obj->attrs->head),
+				sizeof(struct listmp_elem), Cache_Type_ALL,
+				true);
+			Cache_inv((void *)local_next,
+				sizeof(struct listmp_elem), Cache_Type_ALL,
+				true);
+		}
+#endif
+	}
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "listmp_get_head failed! status = 0x%x",
+			retval);
+	}
+	return elem;
+}
+
+/* Function to get tail element from a shared memory list */
+void *listmp_get_tail(void *listmp_handle)
+{
+	struct listmp_object *obj = NULL;
+	struct listmp_elem *elem = NULL;
+	int *key;
+	struct listmp_elem *local_head_prev = NULL;
+	struct listmp_elem *local_prev = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(listmp_module->ns_handle == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+	key = gatemp_enter(obj->gatemp_handle);
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)&(obj->attrs->head),
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+
+	local_head_prev = sharedregion_get_ptr((u32 *)obj->attrs->head.prev);
+	WARN_ON(local_head_prev == NULL);
+
+	/* See if the listmp_object was empty */
+	if (local_head_prev != (struct listmp_elem *)&obj->attrs->head) {
+		/* Elem to return */
+		elem = local_head_prev;
+		WARN_ON(elem == NULL);
+#if 0
+		if (unlikely(obj->cache_enabled)) {
+			Cache_inv((void *)local_head_prev,
+				sizeof(struct listmp_elem), Cache_Type_ALL,
+				true);
+		}
+#endif
+		local_prev = sharedregion_get_ptr((u32 *)elem->prev);
+		WARN_ON(local_prev == NULL);
+
+		/* Fix the head of the list prev pointer */
+		obj->attrs->head.prev = elem->prev;
+		/* Fix the next pointer of the new last elem on the list */
+		local_prev->next = local_head_prev->next;
+#if 0
+		if (unlikely(obj->cache_enabled)) {
+			Cache_inv((void *)&(obj->attrs->head),
+				sizeof(struct listmp_elem), Cache_Type_ALL,
+				true);
+			Cache_inv((void *)local_prev,
+				sizeof(struct listmp_elem), Cache_Type_ALL,
+				true);
+		}
+#endif
+	}
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "listmp_get_tail failed! status = 0x%x",
+			retval);
+	}
+	return elem;
+}
+
+/* Function to put head element into a shared memory list */
+int listmp_put_head(void *listmp_handle, struct listmp_elem *elem)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	struct listmp_elem *local_next_elem = NULL;
+	int *key;
+	struct listmp_elem *shared_elem = NULL;
+	u32 index;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handle == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(elem == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+	dsb();
+	index = sharedregion_get_id(elem);
+	shared_elem = (struct listmp_elem *)sharedregion_get_srptr((void *)elem,
+									index);
+	WARN_ON((u32 *)shared_elem == SHAREDREGION_INVALIDSRPTR);
+	dsb();
+
+	key = gatemp_enter(obj->gatemp_handle);
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)&(obj->attrs->head),
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	/* Add the new elem into the list */
+	elem->next = obj->attrs->head.next;
+	dsb();
+	local_next_elem = sharedregion_get_ptr((u32 *)elem->next);
+	WARN_ON(local_next_elem == NULL);
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)local_next_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	elem->prev = local_next_elem->prev;
+	local_next_elem->prev = shared_elem;
+	obj->attrs->head.next = shared_elem;
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		/* Need to do cache operations */
+		Cache_inv((void *)local_next_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+		Cache_inv((void *)&(obj->attrs->head),
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+		/* writeback invalidate only the elem structure */
+		Cache_inv((void *)elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_put_head failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+
+/* Function to put tail element into a shared memory list */
+int listmp_put_tail(void *listmp_handle, struct listmp_elem *elem)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	int *key;
+	struct listmp_elem *local_prev_elem = NULL;
+	struct listmp_elem *shared_elem = NULL;
+	u32 index;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(listmp_handle == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(elem == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+	dsb();
+	/* Safe to do outside the gate */
+	index = sharedregion_get_id(elem);
+	shared_elem = (struct listmp_elem *)sharedregion_get_srptr((void *)elem,
+									index);
+	WARN_ON((u32 *)shared_elem == SHAREDREGION_INVALIDSRPTR);
+	dsb();
+
+	key = gatemp_enter(obj->gatemp_handle);
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)&(obj->attrs->head),
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	elem->prev = obj->attrs->head.prev;
+	dsb();
+	local_prev_elem = sharedregion_get_ptr((u32 *)elem->prev);
+	WARN_ON(local_prev_elem == NULL);
+	dsb();
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)local_next_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	/* Add the new elem into the list */
+	elem->next = local_prev_elem->next;
+	local_prev_elem->next = shared_elem;
+	obj->attrs->head.prev = shared_elem;
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		/* Need to do cache operations */
+		Cache_inv((void *)local_prev_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+		Cache_inv((void *)&(obj->attrs->head),
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+		/* writeback invalidate only the elem structure */
+		Cache_inv((void *)elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_put_tail failed! "
+			"status = 0x%x\n", status);
+	}
+	return status;
+}
+
+/* Function to insert an element into a shared memory list */
+int listmp_insert(void *listmp_handle, struct listmp_elem *new_elem,
+			struct listmp_elem *cur_elem)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	struct listmp_elem *local_prev_elem = NULL;
+	int *key;
+	struct listmp_elem *shared_new_elem = NULL;
+	struct listmp_elem *shared_cur_elem = NULL;
+	u32 index;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(new_elem == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(cur_elem == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+	dsb();
+	/* Get SRPtr for new_elem */
+	index = sharedregion_get_id(new_elem);
+	shared_new_elem = (struct listmp_elem *)
+				sharedregion_get_srptr((void *)new_elem, index);
+	WARN_ON((u32 *)shared_new_elem == SHAREDREGION_INVALIDSRPTR);
+	dsb();
+	/* Get SRPtr for cur_elem */
+	index = sharedregion_get_id(cur_elem);
+	shared_cur_elem = (struct listmp_elem *)
+				sharedregion_get_srptr((void *)cur_elem, index);
+	WARN_ON((u32 *)shared_cur_elem == SHAREDREGION_INVALIDSRPTR);
+	dsb();
+
+	key = gatemp_enter(obj->gatemp_handle);
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)cur_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	local_prev_elem = sharedregion_get_ptr((u32 *)cur_elem->prev);
+	WARN_ON(local_prev_elem == NULL);
+	dsb();
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)local_prev_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	new_elem->next = shared_cur_elem;
+	new_elem->prev = cur_elem->prev;
+	local_prev_elem->next = shared_new_elem;
+	cur_elem->prev = shared_new_elem;
+	dsb();
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		/* Need to do cache operations */
+		Cache_inv((void *)local_prev_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+		Cache_inv((void *)cur_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+		/* writeback invalidate only the elem structure */
+		Cache_inv((void *)new_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_insert failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+
+/* Function to remove a element from a shared memory list */
+int listmp_remove(void *listmp_handle, struct listmp_elem *elem)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	struct listmp_elem *local_prev_elem = NULL;
+	struct listmp_elem *local_next_elem = NULL;
+	int *key;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(elem == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+
+	key = gatemp_enter(obj->gatemp_handle);
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	local_prev_elem = sharedregion_get_ptr((u32 *)elem->prev);
+	local_next_elem = sharedregion_get_ptr((u32 *)elem->next);
+	dsb();
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		/* Need to do cache operations */
+		Cache_inv((void *)local_prev_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+		Cache_inv((void *)local_next_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	local_prev_elem->next = elem->next;
+	local_next_elem->prev = elem->prev;
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		/* Need to do cache operations */
+		Cache_inv((void *)local_prev_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+		Cache_inv((void *)local_next_elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "listmp_remove failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+
+/* Function to traverse to next element in shared memory list */
+void *listmp_next(void *listmp_handle, struct listmp_elem *elem)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	struct listmp_elem *ret_elem = NULL;
+	int *key;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+
+	key = gatemp_enter(obj->gatemp_handle);
+	/* If element is NULL start at head */
+	if (elem == NULL)
+		elem = (struct listmp_elem *)&obj->attrs->head;
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	ret_elem = sharedregion_get_ptr((u32 *)elem->next);
+	WARN_ON(ret_elem == NULL);
+	/*  NULL if list is empty */
+	if (ret_elem == (struct listmp_elem *)&obj->attrs->head)
+		ret_elem = NULL;
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "listmp_next failed! status = 0x%x\n", status);
+	return ret_elem;
+}
+
+/* Function to traverse to prev element in shared memory list */
+void *listmp_prev(void *listmp_handle, struct listmp_elem *elem)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	struct listmp_elem *ret_elem = NULL;
+	int *key;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(listmp_module->ref_count),
+				LISTMP_MAKE_MAGICSTAMP(0),
+				LISTMP_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	obj = (struct listmp_object *)listmp_handle;
+
+	key = gatemp_enter(obj->gatemp_handle);
+	/* If element is NULL start at head */
+	if (elem == NULL)
+		elem = (struct listmp_elem *)&obj->attrs->head;
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+	ret_elem = sharedregion_get_ptr((u32 *)elem->prev);
+	WARN_ON(ret_elem == NULL);
+	/*  NULL if list is empty */
+	if (ret_elem == (struct listmp_elem *)&obj->attrs->head)
+		ret_elem = NULL;
+	gatemp_leave(obj->gatemp_handle, key);
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "listmp_prev failed! status = 0x%x\n", status);
+	return ret_elem;
+}
+
+/* Function to return the amount of shared memory required for creation of
+ * each instance. */
+uint listmp_shared_mem_req(const struct listmp_params *params)
+{
+	int retval = 0;
+	uint mem_req = 0;
+	uint min_align;
+	u16 region_id;
+
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (params->shared_addr == NULL)
+		region_id = params->region_id;
+	else
+		region_id = sharedregion_get_id(params->shared_addr);
+	WARN_ON(region_id == SHAREDREGION_INVALIDREGIONID);
+
+	/*min_align = Memory_getMaxDefaultTypeAlign();*/min_align = 4;
+	if (sharedregion_get_cache_line_size(region_id) > min_align)
+		min_align = sharedregion_get_cache_line_size(region_id);
+
+	mem_req = ROUND_UP(sizeof(struct listmp_attrs), min_align);
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "listmp_shared_mem_req failed! status = 0x%x\n",
+			retval);
+	}
+	return mem_req;
+}
+
+/* Clears a listmp element's pointers */
+static void _listmp_elem_clear(struct listmp_elem *elem)
+{
+	u32 *shared_elem;
+	int id;
+
+	WARN_ON(elem == NULL);
+
+	id = sharedregion_get_id(elem);
+	shared_elem = sharedregion_get_srptr(elem, id);
+	elem->next = elem->prev = (struct listmp_elem *)shared_elem;
+#if 0
+	if (unlikely(obj->cache_enabled)) {
+		Cache_inv((void *)elem,
+			sizeof(struct listmp_elem), Cache_Type_ALL, true);
+	}
+#endif
+}
+
+/* Creates a new instance of listmp module. This is an internal
+ * function because both listmp_create and
+ * listmp_open call use the same functionality. */
+static int _listmp_create(struct listmp_object **handle_ptr,
+				struct listmp_params *params, u32 create_flag)
+{
+	int status = 0;
+	struct listmp_object *obj = NULL;
+	void *local_addr  = NULL;
+	u32 *shared_shm_base;
+	struct listmp_params sparams;
+	u16 name_len;
+
+	if (WARN_ON(unlikely(handle_ptr == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* Allow local lock not being provided. Don't do protection if local
+	* lock is not provided.
+	*/
+	/* Create the handle */
+	obj = kzalloc(sizeof(struct listmp_object), GFP_KERNEL);
+	*handle_ptr = obj;
+	if (obj == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	/* Populate the params member */
+	memcpy((void *)&obj->params, (void *)params,
+			sizeof(struct listmp_params));
+
+	if (create_flag == false) {
+		/* Update attrs */
+		obj->attrs = (struct listmp_attrs *)params->shared_addr;
+		obj->region_id = sharedregion_get_id((void *)&obj->attrs->head);
+		obj->cache_enabled = sharedregion_is_cache_enabled(
+								obj->region_id);
+		/* get the local address of the SRPtr */
+		local_addr = sharedregion_get_ptr(obj->attrs->gatemp_addr);
+		status = gatemp_open_by_addr(local_addr, &(obj->gatemp_handle));
+		if (status < 0)
+			goto error;
+	} else {
+		INIT_LIST_HEAD(&obj->list_elem);
+
+		/* init the gate */
+		if (params->gatemp_handle != NULL)
+			obj->gatemp_handle = params->gatemp_handle;
+		else
+			obj->gatemp_handle = gatemp_get_default_remote();
+		if (obj->gatemp_handle == NULL)
+			goto error;
+
+		if (params->shared_addr == NULL) {
+			obj->region_id = params->region_id;
+			obj->cache_enabled = sharedregion_is_cache_enabled(
+								obj->region_id);
+
+			listmp_params_init(&sparams);
+			sparams.region_id = params->region_id;
+			obj->alloc_size = listmp_shared_mem_req(&sparams);
+
+			/* HeapMemMP will do the alignment * */
+			obj->attrs = sl_heap_alloc(
+					sharedregion_get_heap(obj->region_id),
+					obj->alloc_size,
+					0);
+			if (obj->attrs == NULL) {
+				status = -ENOMEM;
+				goto error;
+			}
+		} else {
+			obj->region_id = sharedregion_get_id(
+							params->shared_addr);
+			if (unlikely(obj->region_id == \
+				SHAREDREGION_INVALIDREGIONID)) {
+				status = -1;
+				goto error;
+			}
+			if (((u32) params->shared_addr % \
+				sharedregion_get_cache_line_size(
+							obj->region_id)) != 0) {
+				status = -EFAULT;
+				goto error;
+			}
+
+			obj->cache_enabled = sharedregion_is_cache_enabled(
+								obj->region_id);
+			obj->attrs = (struct listmp_attrs *)params->shared_addr;
+		}
+
+		_listmp_elem_clear((struct listmp_elem *)&obj->attrs->head);
+		obj->attrs->gatemp_addr = gatemp_get_shared_addr(
+							obj->gatemp_handle);
+#if 0
+		if (unlikely(obj->cache_enabled)) {
+			Cache_inv((void *)obj->attrs,
+				sizeof(struct listmp_attrs), Cache_Type_ALL,
+				true);
+		}
+#endif
+		if (obj->params.name != NULL) {
+			name_len = strlen(obj->params.name) + 1;
+			/* Copy the name */
+			obj->params.name = kmalloc(name_len, GFP_KERNEL);
+			if (obj->params.name == NULL) {
+				/*  NULL if Memory allocation failed for
+				name */
+				status = -ENOMEM;
+				goto error;
+			}
+			strncpy(obj->params.name, params->name, name_len);
+			shared_shm_base = sharedregion_get_srptr((void *)
+						obj->attrs, obj->region_id);
+			WARN_ON(shared_shm_base == SHAREDREGION_INVALIDSRPTR);
+
+			/* Add list instance to name server */
+			obj->ns_key = nameserver_add_uint32(
+					listmp_module->ns_handle, params->name,
+					(u32)shared_shm_base);
+			if (unlikely(obj->ns_key == NULL)) {
+				status = -EFAULT;
+				goto error;
+			}
+		}
+		obj->attrs->status = LISTMP_CREATED;
+	}
+
+	/* Update owner and opener details */
+	if (create_flag == true) {
+		obj->owner.creator = true;
+		obj->owner.open_count = 1;
+		obj->owner.proc_id = multiproc_self();
+	} else {
+		obj->owner.creator = false;
+		obj->owner.open_count = 0;
+		obj->owner.proc_id = MULTIPROC_INVALIDID;
+	}
+	obj->top = obj;
+
+	/* Put in the module list */
+	/* Function is called already with mutex acquired. So, no need to lock
+	 * here */
+	INIT_LIST_HEAD(&obj->list_elem);
+	list_add_tail((&obj->list_elem), &listmp_module->obj_list);
+	return 0;
+
+error:
+	if (status < 0) {
+		if (create_flag == true) {
+			if (obj->params.name != NULL) {
+				if (obj->ns_key != NULL) {
+					nameserver_remove_entry(
+						listmp_module->ns_handle,
+						obj->ns_key);
+				}
+				kfree(obj->params.name);
+			}
+			if (params->shared_addr == NULL) {
+				if (obj->attrs != NULL) {
+					sl_heap_free(sharedregion_get_heap(
+							obj->region_id),
+							(void *)obj->attrs,
+							obj->alloc_size);
+				}
+			}
+		}
+		kfree(obj);
+		obj = NULL;
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "_listmp_create failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/listmp_ioctl.c b/drivers/dsp/syslink/multicore_ipc/listmp_ioctl.c
new file mode 100644
index 000000000000..7b2b50e4200f
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/listmp_ioctl.c
@@ -0,0 +1,564 @@
+/*
+ *  listmp_ioctl.c
+ *
+ *  This file implements all the ioctl operations required on the
+ *  listmp module.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Linux headers */
+#include <linux/uaccess.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+/* Module Headers */
+#include <listmp.h>
+#include <_listmp.h>
+#include <listmp_ioctl.h>
+#include <sharedregion.h>
+
+/* ioctl interface to listmp_get_config function */
+static inline int listmp_ioctl_get_config(struct listmp_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct listmp_config config;
+
+	listmp_get_config(&config);
+	size = copy_to_user(cargs->args.get_config.config, &config,
+				sizeof(struct listmp_config));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = 0;
+exit:
+	return retval;
+}
+
+/* ioctl interface to listmp_setup function */
+static inline int listmp_ioctl_setup(struct listmp_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct listmp_config config;
+
+	size = copy_from_user(&config, cargs->args.setup.config,
+				sizeof(struct listmp_config));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = listmp_setup(&config);
+
+exit:
+	return retval;
+}
+
+/* ioctl interface to listmp_destroy function */
+static inline int listmp_ioctl_destroy(struct listmp_cmd_args *cargs)
+{
+	cargs->api_status = listmp_destroy();
+	return 0;
+}
+
+/* ioctl interface to listmp_params_init function */
+static inline int listmp_ioctl_params_init(struct listmp_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct listmp_params params;
+
+	size = copy_from_user(&params,
+				cargs->args.params_init.params,
+				sizeof(struct listmp_params));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	listmp_params_init(&params);
+	size = copy_to_user(cargs->args.params_init.params, &params,
+				sizeof(struct listmp_params));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = 0;
+
+exit:
+	return retval;
+}
+
+/* ioctl interface to listmp_create function */
+static inline int listmp_ioctl_create(struct listmp_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct listmp_params params;
+
+	size = copy_from_user(&params, cargs->args.create.params,
+					sizeof(struct listmp_params));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	/* Allocate memory for the name */
+	if (cargs->args.create.name_len > 0) {
+		params.name = kmalloc(cargs->args.create.name_len, GFP_KERNEL);
+		if (params.name == NULL) {
+			retval = -ENOMEM;
+			goto exit;
+		}
+		/* Copy the name */
+		size = copy_from_user(params.name,
+					cargs->args.create.params->name,
+					cargs->args.create.name_len);
+		if (size) {
+			retval = -EFAULT;
+			goto free_name;
+		}
+	}
+
+	params.shared_addr = sharedregion_get_ptr(
+				(u32 *)cargs->args.create.shared_addr_srptr);
+
+	/* Update gate in params. */
+	params.gatemp_handle = cargs->args.create.knl_gate;
+	cargs->args.create.listmp_handle = listmp_create(&params);
+
+	size = copy_to_user(cargs->args.create.params, &params,
+				sizeof(struct listmp_params));
+	if (!size)
+		goto free_name;
+
+	/* Error copying, so delete the handle */
+	retval = -EFAULT;
+	if (cargs->args.create.listmp_handle)
+		listmp_delete(&cargs->args.create.listmp_handle);
+
+free_name:
+	if (cargs->args.create.name_len > 0)
+		kfree(params.name);
+
+	cargs->api_status = 0;
+exit:
+	return retval;
+}
+
+/* ioctl interface to listmp_delete function */
+static inline int listmp_ioctl_delete(struct listmp_cmd_args *cargs)
+{
+	cargs->api_status = listmp_delete(
+		&(cargs->args.delete_instance.listmp_handle));
+	return 0;
+}
+
+/* ioctl interface to listmp_open function */
+static inline int listmp_ioctl_open(struct listmp_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	char *name = NULL;
+	void *listmp_handle = NULL;
+
+	if (cargs->args.open.name_len > 0) {
+		name = kmalloc(cargs->args.open.name_len, GFP_KERNEL);
+		if (name == NULL) {
+			retval = -ENOMEM;
+			goto exit;
+		}
+		/* Copy the name */
+		size = copy_from_user(name, cargs->args.open.name,
+					cargs->args.open.name_len);
+		if (size) {
+			retval = -EFAULT;
+			goto free_name;
+		}
+	}
+
+	/* Update gate in params. */
+	cargs->api_status = listmp_open(name, &listmp_handle);
+	cargs->args.open.listmp_handle = listmp_handle;
+
+free_name:
+	if (cargs->args.open.name_len > 0)
+		kfree(name);
+exit:
+	return retval;
+}
+
+/* ioctl interface to listmp_open_by_addr function */
+static inline int listmp_ioctl_open_by_addr(struct listmp_cmd_args *cargs)
+{
+	s32 retval = 0;
+	void *listmp_handle = NULL;
+	void *shared_addr = NULL;
+
+	/* For open_by_addr, the shared_add_srptr may be invalid */
+	if (cargs->args.open_by_addr.shared_addr_srptr != \
+		(u32)SHAREDREGION_INVALIDSRPTR) {
+		shared_addr = sharedregion_get_ptr((u32 *)
+				cargs->args.open_by_addr.shared_addr_srptr);
+	}
+
+	/* Update gate in params. */
+	cargs->api_status = listmp_open_by_addr(shared_addr, &listmp_handle);
+	cargs->args.open_by_addr.listmp_handle = listmp_handle;
+
+	return retval;
+}
+
+/* ioctl interface to listmp_close function */
+static inline int listmp_ioctl_close(struct listmp_cmd_args *cargs)
+{
+	cargs->api_status = listmp_close(&cargs->args.close.listmp_handle);
+	return 0;
+}
+
+/* ioctl interface to listmp_empty function */
+static inline int listmp_ioctl_isempty(struct listmp_cmd_args *cargs)
+{
+	cargs->args.is_empty.is_empty = \
+		listmp_empty(cargs->args.is_empty.listmp_handle);
+	cargs->api_status = 0;
+	return 0;
+}
+
+/* ioctl interface to listmp_get_head function */
+static inline int listmp_ioctl_get_head(struct listmp_cmd_args *cargs)
+{
+	struct listmp_elem *elem;
+	u32 *elem_srptr = SHAREDREGION_INVALIDSRPTR;
+	int index;
+
+	cargs->api_status = LISTMP_E_FAIL;
+
+	elem = listmp_get_head(cargs->args.get_head.listmp_handle);
+	if (unlikely(elem == NULL))
+		goto exit;
+
+	index = sharedregion_get_id(elem);
+	if (unlikely(index < 0))
+		goto exit;
+
+	elem_srptr = sharedregion_get_srptr((void *)elem, index);
+	cargs->api_status = 0;
+
+exit:
+	cargs->args.get_head.elem_srptr = elem_srptr;
+	return 0;
+}
+
+/* ioctl interface to listmp_get_tail function */
+static inline int listmp_ioctl_get_tail(struct listmp_cmd_args *cargs)
+{
+	struct listmp_elem *elem;
+	u32 *elem_srptr = SHAREDREGION_INVALIDSRPTR;
+	int index;
+
+	cargs->api_status = LISTMP_E_FAIL;
+
+	elem = listmp_get_tail(cargs->args.get_tail.listmp_handle);
+	if (unlikely(elem == NULL))
+		goto exit;
+
+	index = sharedregion_get_id(elem);
+	if (unlikely(index < 0))
+		goto exit;
+
+	elem_srptr = sharedregion_get_srptr((void *)elem, index);
+	cargs->api_status = 0;
+
+exit:
+	cargs->args.get_tail.elem_srptr = elem_srptr;
+	return 0;
+}
+
+/* ioctl interface to listmp_put_head function */
+static inline int listmp_ioctl_put_head(struct listmp_cmd_args *cargs)
+{
+	struct listmp_elem *elem;
+
+	elem = (struct listmp_elem *) sharedregion_get_ptr(
+					cargs->args.put_head.elem_srptr);
+	cargs->api_status = listmp_put_head(
+		cargs->args.put_head.listmp_handle, elem);
+
+	return 0;
+}
+
+/* ioctl interface to listmp_put_tail function */
+static inline int listmp_ioctl_put_tail(struct listmp_cmd_args *cargs)
+{
+	struct listmp_elem *elem;
+
+	elem = (struct listmp_elem *) sharedregion_get_ptr(
+					cargs->args.put_tail.elem_srptr);
+	cargs->api_status = listmp_put_tail(
+		cargs->args.put_head.listmp_handle, elem);
+
+	return 0;
+}
+
+/* ioctl interface to listmp_insert function */
+static inline int listmp_ioctl_insert(struct listmp_cmd_args *cargs)
+{
+	struct listmp_elem *new_elem;
+	struct listmp_elem *cur_elem;
+	int status = -1;
+
+	new_elem = (struct listmp_elem *) sharedregion_get_ptr(
+					cargs->args.insert.new_elem_srptr);
+	if (unlikely(new_elem == NULL))
+		goto exit;
+
+	cur_elem = (struct listmp_elem *) sharedregion_get_ptr(
+					cargs->args.insert.cur_elem_srptr);
+	if (unlikely(cur_elem == NULL))
+		goto exit;
+
+	status = listmp_insert(cargs->args.insert.listmp_handle, new_elem,
+				cur_elem);
+exit:
+	cargs->api_status = status;
+	return 0;
+}
+
+/* ioctl interface to listmp_remove function */
+static inline int listmp_ioctl_remove(struct listmp_cmd_args *cargs)
+{
+	struct listmp_elem *elem;
+
+	elem = (struct listmp_elem *) sharedregion_get_ptr(
+					cargs->args.remove.elem_srptr);
+	cargs->api_status = listmp_remove(
+				cargs->args.get_head.listmp_handle, elem);
+
+	return 0;
+}
+
+/* ioctl interface to listmp_next function */
+static inline int listmp_ioctl_next(struct listmp_cmd_args *cargs)
+{
+	struct listmp_elem *elem = NULL;
+	struct listmp_elem *ret_elem = NULL;
+	u32 *next_elem_srptr = SHAREDREGION_INVALIDSRPTR;
+	int index;
+
+	if (cargs->args.next.elem_srptr != NULL) {
+		elem = (struct listmp_elem *) sharedregion_get_ptr(
+						cargs->args.next.elem_srptr);
+	}
+	ret_elem = (struct listmp_elem *) listmp_next(
+					cargs->args.next.listmp_handle, elem);
+	if (unlikely(ret_elem == NULL))
+		goto exit;
+
+	index = sharedregion_get_id(ret_elem);
+	if (unlikely(index < 0))
+		goto exit;
+
+	next_elem_srptr = sharedregion_get_srptr((void *)ret_elem, index);
+	cargs->api_status = 0;
+
+exit:
+	cargs->args.next.next_elem_srptr = next_elem_srptr;
+	return 0;
+}
+
+/* ioctl interface to listmp_prev function */
+static inline int listmp_ioctl_prev(struct listmp_cmd_args *cargs)
+{
+	struct listmp_elem *elem = NULL;
+	struct listmp_elem *ret_elem = NULL;
+	u32 *prev_elem_srptr = SHAREDREGION_INVALIDSRPTR;
+	int index;
+
+	if (cargs->args.next.elem_srptr != NULL) {
+		elem = (struct listmp_elem *) sharedregion_get_ptr(
+						cargs->args.prev.elem_srptr);
+	}
+	ret_elem = (struct listmp_elem *) listmp_prev(
+					cargs->args.prev.listmp_handle, elem);
+	if (unlikely(ret_elem == NULL))
+		goto exit;
+
+	index = sharedregion_get_id(ret_elem);
+	if (unlikely(index < 0))
+		goto exit;
+
+	prev_elem_srptr = sharedregion_get_srptr((void *)ret_elem, index);
+	cargs->api_status = 0;
+
+exit:
+	cargs->args.prev.prev_elem_srptr = prev_elem_srptr;
+	return 0;
+
+}
+
+/* ioctl interface to listmp_shared_mem_req function */
+static inline int listmp_ioctl_shared_mem_req(struct listmp_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct listmp_params params;
+
+	size = copy_from_user(&params, cargs->args.shared_mem_req.params,
+				sizeof(struct listmp_params));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	params.shared_addr = sharedregion_get_ptr(
+			cargs->args.shared_mem_req.shared_addr_srptr);
+	cargs->args.shared_mem_req.bytes = listmp_shared_mem_req(&params);
+	cargs->api_status = 0;
+
+exit:
+	return retval;
+}
+
+/* ioctl interface function for listmp module */
+int listmp_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args)
+{
+	int os_status = 0;
+	struct listmp_cmd_args __user *uarg =
+			(struct listmp_cmd_args __user *)args;
+	struct listmp_cmd_args cargs;
+	unsigned long size;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		os_status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		os_status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+	if (os_status) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg, sizeof(struct listmp_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_LISTMP_GETCONFIG:
+		os_status = listmp_ioctl_get_config(&cargs);
+		break;
+
+	case CMD_LISTMP_SETUP:
+		os_status = listmp_ioctl_setup(&cargs);
+		break;
+
+	case CMD_LISTMP_DESTROY:
+		os_status = listmp_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_LISTMP_PARAMS_INIT:
+		os_status = listmp_ioctl_params_init(&cargs);
+		break;
+
+	case CMD_LISTMP_CREATE:
+		os_status = listmp_ioctl_create(&cargs);
+		break;
+
+	case CMD_LISTMP_DELETE:
+		os_status = listmp_ioctl_delete(&cargs);
+		break;
+
+	case CMD_LISTMP_OPEN:
+		os_status = listmp_ioctl_open(&cargs);
+		break;
+
+	case CMD_LISTMP_CLOSE:
+		os_status = listmp_ioctl_close(&cargs);
+		break;
+
+	case CMD_LISTMP_ISEMPTY:
+		os_status = listmp_ioctl_isempty(&cargs);
+		break;
+
+	case CMD_LISTMP_GETHEAD:
+		os_status = listmp_ioctl_get_head(&cargs);
+		break;
+
+	case CMD_LISTMP_GETTAIL:
+		os_status = listmp_ioctl_get_tail(&cargs);
+		break;
+
+	case CMD_LISTMP_PUTHEAD:
+		os_status = listmp_ioctl_put_head(&cargs);
+		break;
+
+	case CMD_LISTMP_PUTTAIL:
+		os_status = listmp_ioctl_put_tail(&cargs);
+		break;
+
+	case CMD_LISTMP_INSERT:
+		os_status = listmp_ioctl_insert(&cargs);
+		break;
+
+	case CMD_LISTMP_REMOVE:
+		os_status = listmp_ioctl_remove(&cargs);
+		break;
+
+	case CMD_LISTMP_NEXT:
+		os_status = listmp_ioctl_next(&cargs);
+		break;
+
+	case CMD_LISTMP_PREV:
+		os_status = listmp_ioctl_prev(&cargs);
+		break;
+
+	case CMD_LISTMP_SHAREDMEMREQ:
+		os_status = listmp_ioctl_shared_mem_req(&cargs);
+		break;
+
+	case CMD_LISTMP_OPENBYADDR:
+		os_status = listmp_ioctl_open_by_addr(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		os_status = -ENOTTY;
+		break;
+	}
+	if (os_status < 0)
+		goto exit;
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs, sizeof(struct listmp_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+	return os_status;
+
+exit:
+	printk(KERN_ERR "listmp_ioctl failed: status = 0x%x\n", os_status);
+	return os_status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/messageq.c b/drivers/dsp/syslink/multicore_ipc/messageq.c
new file mode 100644
index 000000000000..38d91091447d
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/messageq.c
@@ -0,0 +1,1618 @@
+/*
+ *  messageq.c
+ *
+ *  The messageQ module supports the structured sending and receiving of
+ *  variable length messages. This module can be used for homogeneous or
+ *  heterogeneous multi-processor messaging.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/*!
+ *  MessageQ provides more sophisticated messaging than other modules. It is
+ *  typically used for complex situations such as multi-processor messaging.
+ *
+ *  The following are key features of the MessageQ module:
+ *  -Writers and readers can be relocated to another processor with no
+ *   runtime code changes.
+ *  -Timeouts are allowed when receiving messages.
+ *  -Readers can determine the writer and reply back.
+ *  -Receiving a message is deterministic when the timeout is zero.
+ *  -Messages can reside on any message queue.
+ *  -Supports zero-copy transfers.
+ *  -Can send and receive from any type of thread.
+ *  -Notification mechanism is specified by application.
+ *  -Allows QoS (quality of service) on message buffer pools. For example,
+ *   using specific buffer pools for specific message queues.
+ *
+ *  Messages are sent and received via a message queue. A reader is a thread
+ *  that gets (reads) messages from a message queue. A writer is a thread that
+ *  puts (writes) a message to a message queue. Each message queue has one
+ *  reader and can have many writers. A thread may read from or write to
+ *  multiple message queues.
+ *
+ *  Conceptually, the reader thread owns a message queue. The reader thread
+ *  creates a message queue. Writer threads  a created message queues to
+ *  get access to them.
+ *
+ *  Message queues are identified by a system-wide unique name. Internally,
+ *  MessageQ uses the NameServer module for managing
+ *  these names. The names are used for opening a message queue. Using
+ *  names is not required.
+ *
+ *  Messages must be allocated from the MessageQ module. Once a message is
+ *  allocated, it can be sent on any message queue. Once a message is sent, the
+ *  writer loses ownership of the message and should not attempt to modify the
+ *  message. Once the reader receives the message, it owns the message. It
+ *  may either free the message or re-use the message.
+ *
+ *  Messages in a message queue can be of variable length. The only
+ *  requirement is that the first field in the definition of a message must be a
+ *  MsgHeader structure. For example:
+ *  typedef struct MyMsg {
+ *	  messageq_MsgHeader header;
+ *	  ...
+ *  } MyMsg;
+ *
+ *  The MessageQ API uses the messageq_MsgHeader internally. Your application
+ *  should not modify or directly access the fields in the messageq_MsgHeader.
+ *
+ *  All messages sent via the MessageQ module must be allocated from a
+ *  Heap implementation. The heap can be used for
+ *  other memory allocation not related to MessageQ.
+ *
+ *  An application can use multiple heaps. The purpose of having multiple
+ *  heaps is to allow an application to regulate its message usage. For
+ *  example, an application can allocate critical messages from one heap of fast
+ *  on-chip memory and non-critical messages from another heap of slower
+ *  external memory
+ *
+ *  MessageQ does support the usage of messages that allocated via the
+ *  alloc function. Please refer to the static_msg_init
+ *  function description for more details.
+ *
+ *  In a multiple processor system, MessageQ communications to other
+ *  processors via MessageQ_transport} instances. There must be one and
+ *  only one IMessageQ_transport instance for each processor where communication
+ *  is desired.
+ *  So on a four processor system, each processor must have three
+ *  IMessageQ_transport instance.
+ *
+ *  The user only needs to create the IMessageQ_transport instances. The
+ *  instances are responsible for registering themselves with MessageQ.
+ *  This is accomplished via the register_transport function.
+ */
+
+
+
+/* Standard headers */
+#include <linux/types.h>
+#include <linux/module.h>
+
+/* Utilities headers */
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+#include <linux/semaphore.h>
+
+/* Syslink headers */
+#include <syslink/atomic_linux.h>
+
+/* Module level headers */
+#include <nameserver.h>
+#include <multiproc.h>
+#include <transportshm_setup_proxy.h>
+#include <heap.h>
+#include <messageq.h>
+#include <transportshm.h>
+
+
+/*  Macro to make a correct module magic number with refCount */
+#define MESSAGEQ_MAKE_MAGICSTAMP(x) ((MESSAGEQ_MODULEID << 12u) | (x))
+
+/* =============================================================================
+ * Globals
+ * =============================================================================
+ */
+/*!
+ *  @brief  Name of the reserved NameServer used for MessageQ.
+ */
+#define MESSAGEQ_NAMESERVER  "MessageQ"
+
+/*! Mask to extract priority setting */
+#define MESSAGEQ_TRANSPORTPRIORITYMASK	0x1
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+/* structure for MessageQ module state */
+struct messageq_module_object {
+	atomic_t ref_count;
+	/* Reference count */
+	void *ns_handle;
+	/* Handle to the local NameServer used for storing GP objects */
+	struct mutex *gate_handle;
+	/* Handle of gate to be used for local thread safety */
+	struct messageq_config cfg;
+	/* Current config values */
+	struct messageq_config default_cfg;
+	/* Default config values */
+	struct messageq_params default_inst_params;
+	/* Default instance creation parameters */
+	void *transports[MULTIPROC_MAXPROCESSORS][MESSAGEQ_NUM_PRIORITY_QUEUES];
+	/* Transport to be set in messageq_register_transport */
+	void **queues; /*messageq_handle *queues;*/
+	/* Grow option */
+	void **heaps; /*Heap_Handle *heaps; */
+	/* Heap to be set in messageq_registerHeap */
+	u16 num_queues;
+	/* Heap to be set in messageq_registerHeap */
+	u16 num_heaps;
+	/* Number of Heaps */
+	bool can_free_queues;
+	/* Grow option */
+	u16 seq_num;
+	/* sequence number */
+};
+
+/* Structure for the Handle for the MessageQ. */
+struct messageq_object {
+	struct messageq_params params;
+	/*! Instance specific creation parameters */
+	u32 queue;
+	/* Unique id */
+	struct list_head normal_list;
+	/* Embedded List objects */
+	struct list_head high_list;
+	/* Embedded List objects */
+	void *ns_key;
+	/* NameServer key */
+	struct semaphore *synchronizer;
+	/* Semaphore used for synchronizing message events */
+};
+
+
+static struct messageq_module_object messageq_state = {
+				.ns_handle = NULL,
+				.gate_handle = NULL,
+				.queues = NULL,
+				.heaps = NULL,
+				.num_queues = 1,
+				.num_heaps = 1,
+				.can_free_queues = false,
+				.default_cfg.trace_flag = false,
+				.default_cfg.num_heaps = 1,
+				.default_cfg.max_runtime_entries = 32,
+				.default_cfg.max_name_len = 32,
+				.default_inst_params.synchronizer = NULL
+};
+
+/* Pointer to the MessageQ module state */
+static struct messageq_module_object *messageq_module = &messageq_state;
+
+/* =============================================================================
+ * Constants
+ * =============================================================================
+ */
+/* Used to denote a message that was initialized
+ * with the messageq_static_msg_init function. */
+#define MESSAGEQ_STATICMSG 0xFFFF
+
+
+/* =============================================================================
+ * Forward declarations of internal functions
+ * =============================================================================
+ */
+/* Grow the MessageQ table */
+static u16 _messageq_grow(struct messageq_object *obj);
+
+/* Initializes a message not obtained from MessageQ_alloc */
+static void messageq_msg_init(messageq_msg msg);
+
+/* =============================================================================
+ * APIS
+ * =============================================================================
+ */
+/*
+ * ======== messageq_get_config ========
+ *  Purpose:
+ *  Function to get the default configuration for the MessageQ
+ *  module.
+ *
+ *  This function can be called by the application to get their
+ *  configuration parameter to MessageQ_setup filled in by the
+ *  MessageQ module with the default parameters. If the user does
+ *  not wish to make any change in the default parameters, this API
+ *  is not required to be called.
+ *  the listmp_sharedmemory module.
+ */
+void messageq_get_config(struct messageq_config *cfg)
+{
+	if (WARN_ON(unlikely(cfg == NULL)))
+		goto exit;
+
+	if (likely(atomic_cmpmask_and_lt(&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true)) {
+		/* (If setup has not yet been called) */
+		memcpy(cfg, &messageq_module->default_cfg,
+			sizeof(struct messageq_config));
+	} else {
+		memcpy(cfg, &messageq_module->cfg,
+			sizeof(struct messageq_config));
+	}
+	return;
+
+exit:
+	printk(KERN_ERR "messageq_get_config: Argument of type "
+		"(struct messageq_config *) passed is null!\n");
+}
+EXPORT_SYMBOL(messageq_get_config);
+
+/*
+ * ======== messageq_setup ========
+ *  Purpose:
+ *  Function to setup the MessageQ module.
+ *
+ *  This function sets up the MessageQ module. This function must
+ *  be called before any other instance-level APIs can be invoked.
+ *  Module-level configuration needs to be provided to this
+ *  function. If the user wishes to change some specific config
+ *  parameters, then MessageQ_getConfig can be called to get the
+ *  configuration filled with the default values. After this, only
+ *  the required configuration values can be changed. If the user
+ *  does not wish to make any change in the default parameters, the
+ *  application can simply call MessageQ with NULL parameters.
+ *  The default parameters would get automatically used.
+ */
+int messageq_setup(const struct messageq_config *cfg)
+{
+	int status = 0;
+	struct nameserver_params params;
+	struct messageq_config tmpcfg;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of refCount variable.
+	*/
+	atomic_cmpmask_and_set(&messageq_module->ref_count,
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(0));
+	if (unlikely(atomic_inc_return(&messageq_module->ref_count)
+				!= MESSAGEQ_MAKE_MAGICSTAMP(1))) {
+		return 1;
+	}
+
+	if (unlikely(cfg == NULL)) {
+		messageq_get_config(&tmpcfg);
+		cfg = &tmpcfg;
+	}
+
+	if (WARN_ON(unlikely(cfg->max_name_len == 0))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(cfg->max_runtime_entries == 0))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* User has not provided any gate handle, so create a default
+	* handle for protecting list object */
+	messageq_module->gate_handle = kmalloc(sizeof(struct mutex),
+				GFP_KERNEL);
+	if (unlikely(messageq_module->gate_handle == NULL)) {
+		/*! @retval MESSAGEQ_E_FAIL Failed to create lock! */
+		status = MESSAGEQ_E_FAIL;
+		printk(KERN_ERR "messageq_setup: Failed to create a "
+			"mutex.\n");
+		status = -ENOMEM;
+		goto exit;
+	}
+	mutex_init(messageq_module->gate_handle);
+
+	memcpy(&messageq_module->cfg, (void *) cfg,
+		sizeof(struct messageq_config));
+	/* Initialize the parameters */
+	nameserver_params_init(&params);
+	params.max_value_len = sizeof(u32);
+	params.max_name_len = cfg->max_name_len;
+	params.max_runtime_entries = cfg->max_runtime_entries;
+
+	messageq_module->seq_num = 0;
+
+	/* Create the nameserver for modules */
+	messageq_module->ns_handle = nameserver_create(MESSAGEQ_NAMESERVER,
+								&params);
+	if (unlikely(messageq_module->ns_handle == NULL)) {
+		/*! @retval MESSAGEQ_E_FAIL Failed to create the
+		 * MessageQ nameserver*/
+		status = MESSAGEQ_E_FAIL;
+		printk(KERN_ERR "messageq_setup: Failed to create the messageq"
+			"nameserver!\n");
+		goto exit;
+	}
+
+	messageq_module->num_heaps = cfg->num_heaps;
+	messageq_module->heaps = kzalloc(sizeof(void *) * \
+				messageq_module->num_heaps, GFP_KERNEL);
+	if (unlikely(messageq_module->heaps == NULL)) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	messageq_module->num_queues = cfg->max_runtime_entries;
+	messageq_module->queues = kzalloc(sizeof(struct messageq_object *) * \
+				messageq_module->num_queues, GFP_KERNEL);
+	if (unlikely(messageq_module->queues == NULL)) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	memset(&(messageq_module->transports), 0, (sizeof(void *) * \
+				MULTIPROC_MAXPROCESSORS * \
+				MESSAGEQ_NUM_PRIORITY_QUEUES));
+	return status;
+
+exit:
+	if (status < 0) {
+		messageq_destroy();
+		printk(KERN_ERR "messageq_setup failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_setup);
+
+/* Function to destroy the MessageQ module. */
+int messageq_destroy(void)
+{
+	int status = 0;
+	int tmp_status = 0;
+	u32 i;
+
+	if (unlikely(atomic_cmpmask_and_lt(&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (!(atomic_dec_return(&messageq_module->ref_count)
+					== MESSAGEQ_MAKE_MAGICSTAMP(0))) {
+		status = 1;
+		goto exit;
+	}
+
+	/* Temporarily increment the refcount */
+	atomic_set(&messageq_module->ref_count, MESSAGEQ_MAKE_MAGICSTAMP(1));
+
+	/* Delete any Message Queues that have not been deleted so far. */
+	for (i = 0; i < messageq_module->num_queues; i++) {
+		if (messageq_module->queues[i] != NULL) {
+			tmp_status = \
+				messageq_delete(&(messageq_module->queues[i]));
+			if (unlikely(tmp_status < 0 && status >= 0)) {
+				status = tmp_status;
+				printk(KERN_ERR "messageq_destroy: "
+					"messageq_delete failed for queue %d",
+					i);
+			}
+		}
+	}
+
+	if (likely(messageq_module->ns_handle != NULL)) {
+		/* Delete the nameserver for modules */
+		tmp_status = nameserver_delete(&messageq_module->ns_handle);
+		if (unlikely(tmp_status < 0 && status >= 0)) {
+			status = tmp_status;
+			printk(KERN_ERR "messageq_destroy: "
+				"nameserver_delete failed");
+		}
+	}
+
+	/* Delete the gate if created internally */
+	if (likely(messageq_module->gate_handle != NULL)) {
+		kfree(messageq_module->gate_handle);
+		messageq_module->gate_handle = NULL;
+	}
+
+	memset(&(messageq_module->transports), 0, (sizeof(void *) * \
+		MULTIPROC_MAXPROCESSORS * MESSAGEQ_NUM_PRIORITY_QUEUES));
+	if (likely(messageq_module->heaps != NULL)) {
+		kfree(messageq_module->heaps);
+		messageq_module->heaps = NULL;
+	}
+	if (likely(messageq_module->queues != NULL)) {
+		kfree(messageq_module->queues);
+		messageq_module->queues = NULL;
+	}
+
+	memset(&messageq_module->cfg, 0, sizeof(struct messageq_config));
+	messageq_module->num_queues = 0;
+	messageq_module->num_heaps = 1;
+	messageq_module->can_free_queues = true;
+	atomic_set(&messageq_module->ref_count, MESSAGEQ_MAKE_MAGICSTAMP(0));
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_destroy failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_destroy);
+
+/* Initialize this config-params structure with supplier-specified
+ *  defaults before instance creation. */
+void messageq_params_init(struct messageq_params *params)
+{
+	if (unlikely(atomic_cmpmask_and_lt(&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))
+		goto exit;
+	if (WARN_ON(unlikely(params == NULL))) {
+		printk(KERN_ERR "messageq_params_init failed:Argument of "
+			"type(messageq_params *) is NULL!\n");
+		goto exit;
+	}
+
+	memcpy(params, &(messageq_module->default_inst_params),
+		sizeof(struct messageq_params));
+
+exit:
+	return;
+}
+EXPORT_SYMBOL(messageq_params_init);
+
+/* Creates a new instance of MessageQ module. */
+void *messageq_create(char *name, const struct messageq_params *params)
+{
+	int status = 0;
+	struct messageq_object *obj = NULL;
+	bool found = false;
+	u16 count = 0;
+	int  i;
+	u16 start;
+	u16 queueIndex = 0;
+
+	if (unlikely(atomic_cmpmask_and_lt(&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	/* Create the generic obj */
+	obj = kzalloc(sizeof(struct messageq_object), 0);
+	if (unlikely(obj == NULL)) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	status = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (status)
+		goto exit;
+	start = 0; /* Statically allocated objects not supported */
+	count = messageq_module->num_queues;
+	/* Search the dynamic array for any holes */
+	for (i = start; i < count ; i++) {
+		if (messageq_module->queues[i] == NULL) {
+			messageq_module->queues[i] = (void *) obj;
+			queueIndex = i;
+			found = true;
+			break;
+		}
+	}
+	/*
+	 *  If no free slot was found:
+	 *  - if no growth allowed, raise an error
+	 *  - if growth is allowed, grow the array
+	 */
+	if (unlikely(found == false)) {
+		/* Growth is always allowed */
+		queueIndex = _messageq_grow(obj);
+		if (unlikely(queueIndex == MESSAGEQ_INVALIDMESSAGEQ)) {
+			mutex_unlock(messageq_module->gate_handle);
+			status = MESSAGEQ_E_FAIL;
+			printk(KERN_ERR "messageq_create: Failed to grow the "
+				"queue array!");
+			goto exit;
+		}
+	}
+
+	if (params != NULL) {
+		/* Populate the params member */
+		memcpy((void *) &obj->params, (void *)params,
+			sizeof(struct messageq_params));
+		if (unlikely(params->synchronizer == NULL))
+			obj->synchronizer = \
+				kzalloc(sizeof(struct semaphore), GFP_KERNEL);
+		else
+			obj->synchronizer = params->synchronizer;
+	} else {
+		/*obj->synchronizer = OsalSemaphore_create(
+				OsalSemaphore_Type_Binary
+				| OsalSemaphore_IntType_Interruptible);*/
+		obj->synchronizer = kzalloc(sizeof(struct semaphore),
+						GFP_KERNEL);
+	}
+	if (unlikely(obj->synchronizer == NULL)) {
+		mutex_unlock(messageq_module->gate_handle);
+		status = MESSAGEQ_E_FAIL;
+		printk(KERN_ERR "messageq_create: Failed to create "
+			"synchronizer semaphore!\n");
+		goto exit;
+	} else {
+		sema_init(obj->synchronizer, 0);
+	}
+	mutex_unlock(messageq_module->gate_handle);
+
+	/* Construct the list object */
+	INIT_LIST_HEAD(&obj->normal_list);
+	INIT_LIST_HEAD(&obj->high_list);
+
+	/* Update processor information */
+	obj->queue = ((u32)(multiproc_self()) << 16) | queueIndex;
+	if (likely(name != NULL)) {
+		obj->ns_key = nameserver_add_uint32(messageq_module->ns_handle,
+						name, obj->queue);
+		if (unlikely(obj->ns_key == NULL)) {
+			status = MESSAGEQ_E_FAIL;
+			printk(KERN_ERR "messageq_create: Failed to add "
+				"the messageq name!\n");
+		}
+	}
+
+exit:
+	if (unlikely(status < 0)) {
+		messageq_delete((void **)&obj);
+		printk(KERN_ERR "messageq_create failed! status = 0x%x\n",
+			status);
+	}
+	return (void *) obj;
+}
+EXPORT_SYMBOL(messageq_create);
+
+/* Deletes a instance of MessageQ module. */
+int messageq_delete(void **msg_handleptr)
+{
+	int status = 0;
+	int tmp_status = 0;
+	struct messageq_object *obj = NULL;
+	messageq_msg temp_msg;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(msg_handleptr == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(*msg_handleptr == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct messageq_object *) (*msg_handleptr);
+
+	/* Take the local lock */
+	status = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (status)
+		goto exit;
+
+	if (unlikely(obj->ns_key != NULL)) {
+		/* remove from the name serve */
+		status = nameserver_remove_entry(messageq_module->ns_handle,
+			obj->ns_key);
+		if (unlikely(status < 0)) {
+			printk(KERN_ERR "messageq_delete: nameserver_remove_"
+				"entry failed! status = 0x%x", status);
+		}
+	}
+
+	/* Remove all the messages for the message queue's normal_list queue
+	 * and free the list */
+	while (true) {
+		if (!list_empty(&obj->normal_list)) {
+			temp_msg = (messageq_msg) (obj->normal_list.next);
+			list_del_init(obj->normal_list.next);
+		} else
+			break;
+		tmp_status = messageq_free(temp_msg);
+		if (unlikely((tmp_status < 0) && (status >= 0))) {
+			status = tmp_status;
+			printk(KERN_ERR "messageq_delete: messageq_free failed"
+				" for normal_list!");
+		}
+	}
+	list_del(&obj->normal_list);
+
+	/* Remove all the messages for the message queue's normal_list queue
+	 * and free the list */
+	while (true) {
+		if (!list_empty(&obj->high_list)) {
+			temp_msg = (messageq_msg) (obj->high_list.next);
+			list_del_init(obj->high_list.next);
+		} else
+			break;
+		tmp_status = messageq_free(temp_msg);
+		if (unlikely((tmp_status < 0) && (status >= 0))) {
+			status = tmp_status;
+			printk(KERN_ERR "messageq_delete: messageq_free failed"
+				" for high_list!");
+		}
+	}
+	list_del(&obj->high_list);
+
+	/*if (obj->synchronizer != NULL)
+		status = OsalSemaphore_delete(&obj->synchronizer);*/
+	if (obj->synchronizer != NULL) {
+		kfree(obj->synchronizer);
+		obj->synchronizer = NULL;
+	}
+	/* Clear the MessageQ obj from array. */
+	messageq_module->queues[obj->queue & 0xFFFF] = NULL;
+
+	/* Release the local lock */
+	mutex_unlock(messageq_module->gate_handle);
+
+	/* Now free the obj */
+	kfree(obj);
+	*msg_handleptr = NULL;
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_delete failed! status = 0x%x\n",
+			status);;
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_delete);
+
+/* Opens a created instance of MessageQ module. */
+int messageq_open(char *name, u32 *queue_id)
+{
+	int status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(queue_id == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* Initialize return queue ID to invalid. */
+	*queue_id = MESSAGEQ_INVALIDMESSAGEQ;
+	status = nameserver_get_uint32(messageq_module->ns_handle, name,
+					queue_id, NULL);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_open failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_open);
+
+/* Closes previously opened/created instance of MessageQ module. */
+int messageq_close(u32 *queue_id)
+{
+	s32 status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(queue_id == NULL))) {
+		printk(KERN_ERR "messageq_close: queue_id passed is NULL!\n");
+		status = -EINVAL;
+		goto exit;
+	}
+
+	*queue_id = MESSAGEQ_INVALIDMESSAGEQ;
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_close failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_close);
+
+/* Retrieve a message */
+int messageq_get(void *messageq_handle, messageq_msg *msg,
+							u32 timeout)
+{
+	int status = 0;
+	struct messageq_object *obj = (struct messageq_object *)messageq_handle;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(msg == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(obj == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* Keep looping while there is no element in the list */
+	/* Take the local lock */
+	status = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (status)
+		goto exit;
+	if (!list_empty(&obj->high_list)) {
+		*msg = (messageq_msg) (obj->high_list.next);
+		list_del_init(obj->high_list.next);
+	}
+	/* Leave the local lock */
+	mutex_unlock(messageq_module->gate_handle);
+	while (*msg == NULL) {
+		status = mutex_lock_interruptible(messageq_module->gate_handle);
+		if (status)
+			goto exit;
+		if (!list_empty(&obj->normal_list)) {
+			*msg = (messageq_msg) (obj->normal_list.next);
+			list_del_init(obj->normal_list.next);
+		}
+		mutex_unlock(messageq_module->gate_handle);
+
+		if (*msg == NULL) {
+			/*
+			 *  Block until notified.  If pend times-out, no message
+			 *  should be returned to the caller
+			 */
+			/*! @retval NULL timeout has occurred */
+			if (obj->synchronizer != NULL) {
+				/* TODO: cater to different timeout values */
+				/*status = OsalSemaphore_pend(
+					obj->synchronizer, timeout); */
+				if (timeout == MESSAGEQ_FOREVER) {
+					if (down_interruptible
+							(obj->synchronizer)) {
+						status = -ERESTARTSYS;
+					}
+				} else {
+					status = down_timeout(obj->synchronizer,
+						msecs_to_jiffies(timeout));
+				}
+				if (status < 0) {
+					*msg = NULL;
+					break;
+				}
+			}
+			status = mutex_lock_interruptible(
+					messageq_module->gate_handle);
+			if (status)
+				goto exit;
+			if (!list_empty(&obj->high_list)) {
+				*msg = (messageq_msg) (obj->high_list.next);
+				list_del_init(obj->high_list.next);
+			}
+			mutex_unlock(messageq_module->gate_handle);
+		}
+	}
+
+exit:
+	if (unlikely((messageq_module->cfg.trace_flag == true) || \
+		((*msg != NULL) && \
+		(((*msg)->flags & MESSAGEQ_TRACEMASK) != 0)))) {
+		printk(KERN_INFO "messageq_get: *msg = 0x%x seq_num = 0x%x "
+			"src_proc = 0x%x obj = 0x%x\n", (uint)(*msg),
+			((*msg)->seq_num), ((*msg)->src_proc), (uint)(obj));
+	}
+	if (status < 0 && status != -ETIME)
+		printk(KERN_ERR "messageq_get failed! status = 0x%x\n", status);
+	return status;
+}
+EXPORT_SYMBOL(messageq_get);
+
+/* Count the number of messages in the queue */
+int messageq_count(void *messageq_handle)
+{
+	struct messageq_object *obj = (struct messageq_object *)messageq_handle;
+	int count = 0;
+	struct list_head *elem;
+	int key;
+	s32 status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(obj == NULL)) {
+		status = -EINVAL;
+		printk(KERN_ERR "messageq_count: obj passed is NULL!\n");
+		goto exit;
+	}
+
+	key = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (key < 0)
+		return key;
+
+	list_for_each(elem, &obj->high_list) {
+		count++;
+	}
+	list_for_each(elem, &obj->normal_list) {
+		count++;
+	}
+	mutex_unlock(messageq_module->gate_handle);
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "messageq_count failed! status = 0x%x", status);
+	return count;
+}
+EXPORT_SYMBOL(messageq_count);
+
+/* Initialize a static message */
+void messageq_static_msg_init(messageq_msg msg, u32 size)
+{
+	s32 status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(msg == NULL)) {
+		printk(KERN_ERR "messageq_static_msg_init: msg is invalid!\n");
+		goto exit;
+	}
+
+	/* Fill in the fields of the message */
+	messageq_msg_init(msg);
+	msg->heap_id = MESSAGEQ_STATICMSG;
+	msg->msg_size = size;
+
+	if (unlikely((messageq_module->cfg.trace_flag == true) || \
+		(((*msg).flags & MESSAGEQ_TRACEMASK) != 0))) {
+		printk(KERN_INFO "messageq_static_msg_init: msg = 0x%x "
+			"seq_num = 0x%x src_proc = 0x%x", (uint)(msg),
+			(msg)->seq_num, (msg)->src_proc);
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_static_msg_init failed! "
+			"status = 0x%x", status);
+	}
+	return;
+}
+EXPORT_SYMBOL(messageq_static_msg_init);
+
+/* Allocate a message and initial the needed fields (note some
+ * of the fields in the header at set via other APIs or in the
+ * messageq_put function. */
+messageq_msg messageq_alloc(u16 heap_id, u32 size)
+{
+	int status = 0;
+	messageq_msg msg = NULL;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(heap_id >= messageq_module->num_heaps))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(messageq_module->heaps[heap_id] == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* Allocate the message. No alignment requested */
+	msg = sl_heap_alloc(messageq_module->heaps[heap_id], size, 0);
+	if (msg == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	/* Fill in the fields of the message */
+	messageq_msg_init(msg);
+	msg->msg_size = size;
+	msg->heap_id = heap_id;
+
+	if (unlikely((messageq_module->cfg.trace_flag == true) || \
+		(((*msg).flags & MESSAGEQ_TRACEMASK) != 0))) {
+		printk(KERN_INFO "messageq_alloc: msg = 0x%x seq_num = 0x%x "
+			"src_proc = 0x%x", (uint)(msg), (msg)->seq_num,
+			(msg)->src_proc);
+	}
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "messageq_alloc failed! status = 0x%x", status);
+	return msg;
+}
+EXPORT_SYMBOL(messageq_alloc);
+
+/* Frees the message. */
+int messageq_free(messageq_msg msg)
+{
+	u32 status = 0;
+	void *heap = NULL;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(msg == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (unlikely(msg->heap_id == MESSAGEQ_STATICMSG)) {
+		status = MESSAGEQ_E_CANNOTFREESTATICMSG;
+		goto exit;
+	}
+	if (unlikely(msg->heap_id >= messageq_module->num_heaps)) {
+		status = MESSAGEQ_E_INVALIDHEAPID;
+		goto exit;
+	}
+	if (unlikely(messageq_module->heaps[msg->heap_id] == NULL)) {
+		status = MESSAGEQ_E_INVALIDHEAPID;
+		goto exit;
+	}
+
+	if (unlikely((messageq_module->cfg.trace_flag == true) || \
+		(((*msg).flags & MESSAGEQ_TRACEMASK) != 0))) {
+		printk(KERN_INFO "messageq_free: msg = 0x%x seq_num = 0x%x "
+			"src_proc = 0x%x", (uint)(msg), (msg)->seq_num,
+			(msg)->src_proc);
+	}
+	heap = messageq_module->heaps[msg->heap_id];
+	sl_heap_free(heap, msg, msg->msg_size);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_free failed! status = 0x%x\n",
+			status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_free);
+
+/* Put a message in the queue */
+int messageq_put(u32 queue_id, messageq_msg msg)
+{
+	int status = 0;
+	u16 dst_proc_id = (u16)(queue_id >> 16);
+	struct messageq_object *obj = NULL;
+	void *transport = NULL;
+	u32 priority;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(queue_id == MESSAGEQ_INVALIDMESSAGEQ))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(msg == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	msg->dst_id = (u16)(queue_id);
+	msg->dst_proc = (u16)(queue_id >> 16);
+	if (likely(dst_proc_id != multiproc_self())) {
+		if (unlikely(dst_proc_id >= multiproc_get_num_processors())) {
+			/* Invalid destination processor id */
+			status = MESSAGEQ_E_INVALIDPROCID;
+			goto exit;
+		}
+
+		priority = (u32)((msg->flags) & MESSAGEQ_TRANSPORTPRIORITYMASK);
+		/* Call the transport associated with this message queue */
+		transport = messageq_module->transports[dst_proc_id][priority];
+		if (transport == NULL) {
+			/* Try the other transport */
+			priority = !priority;
+			transport =
+			messageq_module->transports[dst_proc_id][priority];
+		}
+
+		if (unlikely(transport == NULL)) {
+			status = -ENODEV;
+			goto exit;
+		}
+		status = transportshm_put(transport, msg);
+		if (unlikely(status < 0))
+			goto exit;
+	} else {
+		/* It is a local MessageQ */
+		obj = (struct messageq_object *)
+				(messageq_module->queues[(u16)(queue_id)]);
+		status = mutex_lock_interruptible(messageq_module->gate_handle);
+		if (status < 0)
+			goto exit;
+		if ((msg->flags & MESSAGEQ_PRIORITYMASK) == \
+			MESSAGEQ_URGENTPRI) {
+			list_add((struct list_head *) msg, &obj->high_list);
+		} else {
+			if ((msg->flags & MESSAGEQ_PRIORITYMASK) == \
+				MESSAGEQ_NORMALPRI) {
+				list_add_tail((struct list_head *) msg,
+					&obj->normal_list);
+			} else {
+				list_add_tail((struct list_head *) msg,
+					&obj->high_list);
+			}
+		}
+		mutex_unlock(messageq_module->gate_handle);
+
+		/* Notify the reader. */
+		if (obj->synchronizer != NULL) {
+			up(obj->synchronizer);
+			/*OsalSemaphore_post(obj->synchronizer);*/
+		}
+	}
+	if (unlikely((messageq_module->cfg.trace_flag == true) || \
+		(((*msg).flags & MESSAGEQ_TRACEMASK) != 0))) {
+		printk(KERN_INFO "messageq_put: msg = 0x%x seq_num = 0x%x "
+			"src_proc = 0x%x dst_proc_id = 0x%x\n", (uint)(msg),
+			(msg)->seq_num, (msg)->src_proc, (msg)->dst_proc);
+	}
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "messageq_put failed! status = 0x%x\n", status);
+	return status;
+}
+EXPORT_SYMBOL(messageq_put);
+
+/* Register a heap */
+int messageq_register_heap(void *heap_handle, u16 heap_id)
+{
+	int status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(heap_handle == NULL))) {
+		/*! @retval -EINVAL Invalid heap_id */
+		status = -EINVAL;
+		goto exit;
+	}
+	/* Make sure the heap_id is valid */
+	if (WARN_ON(unlikely(heap_id >= messageq_module->num_heaps))) {
+		/*! @retval -EINVAL Invalid heap_id */
+		status = -EINVAL;
+		goto exit;
+	}
+
+	status = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (status)
+		goto exit;
+	if (messageq_module->heaps[heap_id] == NULL)
+		messageq_module->heaps[heap_id] = heap_handle;
+	else {
+		/*! @retval MESSAGEQ_E_ALREADYEXISTS Specified heap is
+		already registered. */
+		status = MESSAGEQ_E_ALREADYEXISTS;
+	}
+	mutex_unlock(messageq_module->gate_handle);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_register_heap failed! "
+			"status = 0x%x\n", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_register_heap);
+
+/* Unregister a heap */
+int messageq_unregister_heap(u16 heap_id)
+{
+	int status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	/* Make sure the heap_id is valid */
+	if (WARN_ON(unlikely(heap_id >= messageq_module->num_heaps))) {
+		/*! @retval -EINVAL Invalid heap_id */
+		status = -EINVAL;
+		goto exit;
+	}
+
+	status = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (status)
+		goto exit;
+	if (messageq_module->heaps != NULL)
+		messageq_module->heaps[heap_id] = NULL;
+	mutex_unlock(messageq_module->gate_handle);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_unregister_heap failed! "
+			"status = 0x%x\n", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_unregister_heap);
+
+/* Register a transport */
+int messageq_register_transport(void *messageq_transportshm_handle,
+				 u16 proc_id, u32 priority)
+{
+	int  status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(messageq_transportshm_handle == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	status = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (status)
+		goto exit;
+	if (messageq_module->transports[proc_id][priority] == NULL) {
+		messageq_module->transports[proc_id][priority] = \
+			messageq_transportshm_handle;
+	} else {
+		/*! @retval MESSAGEQ_E_ALREADYEXISTS Specified transport is
+		already registered. */
+		status = MESSAGEQ_E_ALREADYEXISTS;
+	}
+	mutex_unlock(messageq_module->gate_handle);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_register_transport failed! "
+			"status = 0x%x\n", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(messageq_register_transport);
+
+/* Unregister a transport */
+void messageq_unregister_transport(u16 proc_id, u32 priority)
+{
+	int  status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(proc_id >= multiproc_get_num_processors())) {
+		/*! @retval MESSAGEQ_E_PROCIDINVALID Invalid proc_id */
+		status = -EINVAL;
+		goto exit;
+	}
+
+	status = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (status)
+		goto exit;
+	if (messageq_module->transports[proc_id][priority] != NULL)
+		messageq_module->transports[proc_id][priority] = NULL;
+	mutex_unlock(messageq_module->gate_handle);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_unregister_transport failed! "
+			"status = 0x%x\n", status);
+	}
+	return;
+}
+EXPORT_SYMBOL(messageq_unregister_transport);
+
+/* Set the destination queue of the message. */
+void messageq_set_reply_queue(void *messageq_handle, messageq_msg msg)
+{
+	s32 status = 0;
+
+	struct messageq_object *obj = \
+			(struct messageq_object *) messageq_handle;
+
+	if (WARN_ON(unlikely(messageq_handle == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(msg == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	msg->reply_id = (u16)(obj->queue);
+	msg->reply_proc = (u16)(obj->queue >> 16);
+	return;
+
+exit:
+	printk(KERN_ERR "messageq_set_reply_queue failed: status = 0x%x",
+		status);
+	return;
+}
+EXPORT_SYMBOL(messageq_set_reply_queue);
+
+/* Get the queue _id of the message. */
+u32 messageq_get_queue_id(void *messageq_handle)
+{
+	struct messageq_object *obj = \
+			(struct messageq_object *) messageq_handle;
+	u32 queue_id = MESSAGEQ_INVALIDMESSAGEQ;
+
+	if (WARN_ON(unlikely(obj == NULL))) {
+		printk(KERN_ERR "messageq_get_queue_id: obj passed is NULL!\n");
+		goto exit;
+	}
+
+	queue_id = (obj->queue);
+
+exit:
+	return queue_id;
+}
+EXPORT_SYMBOL(messageq_get_queue_id);
+
+/* Get the proc _id of the message. */
+u16 messageq_get_proc_id(void *messageq_handle)
+{
+	struct messageq_object *obj = \
+			(struct messageq_object *) messageq_handle;
+	u16 proc_id = MULTIPROC_INVALIDID;
+
+	if (WARN_ON(unlikely(obj == NULL))) {
+		printk(KERN_ERR "messageq_get_proc_id: obj passed is NULL!\n");
+		goto exit;
+	}
+
+	proc_id = (u16)(obj->queue >> 16);
+
+exit:
+	return proc_id;
+}
+EXPORT_SYMBOL(messageq_get_proc_id);
+
+/* Get the destination queue of the message. */
+u32 messageq_get_dst_queue(messageq_msg msg)
+{
+	u32 queue_id = MESSAGEQ_INVALIDMESSAGEQ;
+
+	if (WARN_ON(unlikely(msg == NULL))) {
+		printk(KERN_ERR "messageq_get_dst_queue: msg passed is "
+			"NULL!\n");
+		goto exit;
+	}
+
+	/*construct queue value */
+	if (msg->dst_id != (u32)MESSAGEQ_INVALIDMESSAGEQ)
+		queue_id = ((u32) multiproc_self() << 16) | msg->dst_id;
+
+exit:
+	return queue_id;
+}
+EXPORT_SYMBOL(messageq_get_dst_queue);
+
+/* Get the message id of the message. */
+u16 messageq_get_msg_id(messageq_msg msg)
+{
+	u16 id = MESSAGEQ_INVALIDMSGID;
+
+	if (WARN_ON(unlikely(msg == NULL))) {
+		printk(KERN_ERR "messageq_get_msg_id: msg passed is NULL!\n");
+		goto exit;
+	}
+
+	id = msg->msg_id;
+
+exit:
+	return id;
+}
+EXPORT_SYMBOL(messageq_get_msg_id);
+
+/* Get the message size of the message. */
+u32 messageq_get_msg_size(messageq_msg msg)
+{
+	u32 size = 0;
+
+	if (WARN_ON(unlikely(msg == NULL))) {
+		printk(KERN_ERR "messageq_get_msg_size: msg passed is NULL!\n");
+		goto exit;
+	}
+
+	size = msg->msg_size;
+
+exit:
+	return size;
+}
+EXPORT_SYMBOL(messageq_get_msg_size);
+
+/* Get the message priority of the message. */
+u32 messageq_get_msg_pri(messageq_msg msg)
+{
+	u32 priority = MESSAGEQ_NORMALPRI;
+
+	if (WARN_ON(unlikely(msg == NULL))) {
+		printk(KERN_ERR "messageq_get_msg_pri: msg passed is NULL!\n");
+		goto exit;
+	}
+
+	priority = ((u32)(msg->flags & MESSAGEQ_PRIORITYMASK));
+
+exit:
+	return priority;
+}
+EXPORT_SYMBOL(messageq_get_msg_pri);
+
+/* Get the embedded source message queue out of the message. */
+u32 messageq_get_reply_queue(messageq_msg msg)
+{
+	u32 queue = MESSAGEQ_INVALIDMESSAGEQ;
+
+	if (WARN_ON(unlikely(msg == NULL))) {
+		printk(KERN_ERR "messageq_get_reply_queue: msg passed is "
+			"NULL!\n");
+		goto exit;
+	}
+
+	if (msg->reply_id != (u16)MESSAGEQ_INVALIDMESSAGEQ)
+		queue = ((u32)(msg->reply_proc) << 16) | msg->reply_id;
+
+exit:
+	return queue;
+}
+EXPORT_SYMBOL(messageq_get_reply_queue);
+
+/* Set the message id of the message. */
+void messageq_set_msg_id(messageq_msg msg, u16 msg_id)
+{
+	if (WARN_ON(unlikely(msg == NULL))) {
+		printk(KERN_ERR "messageq_set_msg_id: msg passed is NULL!\n");
+		goto exit;
+	}
+
+	msg->msg_id = msg_id;
+
+exit:
+	return;
+}
+EXPORT_SYMBOL(messageq_set_msg_id);
+
+/* Set the priority of the message. */
+void messageq_set_msg_pri(messageq_msg msg, u32 priority)
+{
+	if (WARN_ON(unlikely(msg == NULL))) {
+		printk(KERN_ERR "messageq_set_msg_pri: msg passed is NULL!\n");
+		goto exit;
+	}
+
+	msg->flags = priority & MESSAGEQ_PRIORITYMASK;
+
+exit:
+	return;
+}
+EXPORT_SYMBOL(messageq_set_msg_pri);
+
+/* Sets the tracing of a message */
+void messageq_set_msg_trace(messageq_msg msg, bool trace_flag)
+{
+	if (WARN_ON(unlikely(msg == NULL))) {
+		printk(KERN_ERR "messageq_set_msg_trace: msg passed is "
+			"NULL!\n");
+		goto exit;
+	}
+
+	msg->flags = (msg->flags & ~MESSAGEQ_TRACEMASK) | \
+			(trace_flag << MESSAGEQ_TRACESHIFT);
+
+	printk(KERN_INFO "messageq_set_msg_trace: msg = 0x%x, seq_num = 0x%x"
+			"src_proc = 0x%x trace_flag = 0x%x", (uint)msg,
+			msg->seq_num, msg->src_proc, trace_flag);
+exit:
+	return;
+}
+
+/* Returns the amount of shared memory used by one transport instance.
+ *
+ *  The MessageQ module itself does not use any shared memory but the
+ *  underlying transport may use some shared memory.
+ */
+uint messageq_shared_mem_req(void *shared_addr)
+{
+	uint mem_req;
+
+	if (likely(multiproc_get_num_processors() > 1)) {
+		/* Determine device-specific shared memory requirements */
+		mem_req = messageq_setup_transport_proxy_shared_mem_req(
+								shared_addr);
+	} else {
+		/* Only 1 processor: no shared memory needed */
+		mem_req = 0;
+	}
+
+	return mem_req;
+}
+EXPORT_SYMBOL(messageq_shared_mem_req);
+
+/* Calls the SetupProxy to setup the MessageQ transports. */
+int messageq_attach(u16 remote_proc_id, void *shared_addr)
+{
+	int status = MESSAGEQ_S_SUCCESS;
+
+	if (likely(multiproc_get_num_processors() > 1)) {
+		/* Use the messageq_setup_transport_proxy to attach
+		 * transports */
+		status = messageq_setup_transport_proxy_attach(
+						remote_proc_id, shared_addr);
+		if (status < 0) {
+			printk(KERN_ERR "messageq_attach failed in transport"
+					"setup, status = 0x%x", status);
+		}
+	}
+
+	/*! @retval MESSAGEQ_S_SUCCESS Operation successfully completed! */
+	return status;
+}
+EXPORT_SYMBOL(messageq_attach);
+
+/* Calls the SetupProxy to detach the MessageQ transports. */
+int messageq_detach(u16 remote_proc_id)
+{
+	int status = MESSAGEQ_S_SUCCESS;
+
+	if (likely(multiproc_get_num_processors() > 1)) {
+		/* Use the messageq_setup_transport_proxy to detach
+		 * transports */
+		status = messageq_setup_transport_proxy_detach(remote_proc_id);
+		if (unlikely(status < 0)) {
+			printk(KERN_ERR "messageq_detach failed in transport"
+					"detach, status = 0x%x", status);
+		}
+	}
+
+	/*! @retval MESSAGEQ_S_SUCCESS Operation successfully completed! */
+	return status;
+}
+EXPORT_SYMBOL(messageq_detach);
+
+/* =============================================================================
+ * Internal functions
+ * =============================================================================
+ */
+/* Grow the MessageQ table */
+u16 _messageq_grow(struct messageq_object *obj)
+{
+	u16 queue_index = messageq_module->num_queues;
+	int old_size;
+	void **queues;
+	void **oldqueues;
+
+	/* No parameter validation required since this is an internal func. */
+	old_size = (messageq_module->num_queues) * \
+			sizeof(struct messageq_object *);
+	queues = kmalloc(old_size + sizeof(struct messageq_object *),
+				GFP_KERNEL);
+	if (queues == NULL) {
+		printk(KERN_ERR "_messageq_grow: Growing the messageq "
+			"failed!\n");
+		goto exit;
+	}
+
+	/* Copy contents into new table */
+	memcpy(queues, messageq_module->queues, old_size);
+	/* Fill in the new entry */
+	queues[queue_index] = (void *)obj;
+	/* Hook-up new table */
+	oldqueues = messageq_module->queues;
+	messageq_module->queues = queues;
+	messageq_module->num_queues++;
+
+	/* Delete old table if not statically defined*/
+	if (messageq_module->can_free_queues == true)
+		kfree(oldqueues);
+	else
+		messageq_module->can_free_queues = true;
+
+exit:
+	return queue_index;
+}
+
+/* This is a helper function to initialize a message. */
+static void messageq_msg_init(messageq_msg msg)
+{
+	s32 status = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(messageq_module->ref_count),
+				MESSAGEQ_MAKE_MAGICSTAMP(0),
+				MESSAGEQ_MAKE_MAGICSTAMP(1)) == true))) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (WARN_ON(unlikely(msg == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	msg->reply_id = (u16) MESSAGEQ_INVALIDMESSAGEQ;
+	msg->msg_id = MESSAGEQ_INVALIDMSGID;
+	msg->dst_id = (u16) MESSAGEQ_INVALIDMESSAGEQ;
+	msg->flags = MESSAGEQ_HEADERVERSION | MESSAGEQ_NORMALPRI;
+	msg->src_proc = multiproc_self();
+
+	status = mutex_lock_interruptible(messageq_module->gate_handle);
+	if (status < 0)
+		goto exit;
+	msg->seq_num  = messageq_module->seq_num++;
+	mutex_unlock(messageq_module->gate_handle);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "messageq_msg_init: Invalid NULL msg "
+			"specified!\n");
+	}
+	return;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/messageq_ioctl.c b/drivers/dsp/syslink/multicore_ipc/messageq_ioctl.c
new file mode 100644
index 000000000000..bd4cc527557e
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/messageq_ioctl.c
@@ -0,0 +1,566 @@
+/*
+ *  messageq_ioctl.c
+ *
+ *  This file implements all the ioctl operations required on the messageq
+ *  module.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Linux headers */
+#include <linux/uaccess.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+/* Module Headers */
+#include <messageq.h>
+#include <messageq_ioctl.h>
+#include <sharedregion.h>
+
+/*
+ * ======== messageq_ioctl_put ========
+ *  Purpose:
+ *  This ioctl interface to messageq_put function
+ */
+static inline int messageq_ioctl_put(struct messageq_cmd_args *cargs)
+{
+	int status = 0;
+	messageq_msg msg;
+
+	msg = (messageq_msg) sharedregion_get_ptr(cargs->args.put.msg_srptr);
+	if (unlikely(msg == NULL))
+		goto exit;
+
+	status = messageq_put(cargs->args.put.queue_id, msg);
+
+	cargs->api_status = status;
+exit:
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_get ========
+ *  Purpose:
+ *  This ioctl interface to messageq_get function
+ */
+static inline int messageq_ioctl_get(struct messageq_cmd_args *cargs)
+{
+	messageq_msg msg = NULL;
+	u32 *msg_srptr = SHAREDREGION_INVALIDSRPTR;
+	u16 index;
+
+	cargs->api_status = messageq_get(cargs->args.get.messageq_handle,
+					&msg,
+					cargs->args.get.timeout);
+	if (unlikely(cargs->api_status < 0))
+		goto exit;
+
+	index = sharedregion_get_id(msg);
+	if (unlikely(index < 0)) {
+		cargs->api_status = index;
+		goto exit;
+	}
+
+	msg_srptr = sharedregion_get_srptr(msg, index);
+
+exit:
+	cargs->args.get.msg_srptr = msg_srptr;
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_count ========
+ *  Purpose:
+ *  This ioctl interface to messageq_count function
+ */
+static inline int messageq_ioctl_count(struct messageq_cmd_args *cargs)
+{
+	int result = messageq_count(cargs->args.count.messageq_handle);
+	if (result < 0)
+		cargs->api_status = result;
+	else
+		cargs->args.count.count = result;
+
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_alloc ========
+ *  Purpose:
+ *  This ioctl interface to messageq_alloc function
+ */
+static inline int messageq_ioctl_alloc(struct messageq_cmd_args *cargs)
+{
+	messageq_msg msg;
+	u32 *msg_srptr = SHAREDREGION_INVALIDSRPTR;
+	u16 index;
+
+	msg = messageq_alloc(cargs->args.alloc.heap_id, cargs->args.alloc.size);
+	if (unlikely(msg == NULL))
+		goto exit;
+
+	index = sharedregion_get_id(msg);
+	if (unlikely(index < 0))
+		goto exit;
+
+	msg_srptr = sharedregion_get_srptr(msg, index);
+
+	cargs->api_status = 0;
+exit:
+	cargs->args.alloc.msg_srptr = msg_srptr;
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_free ========
+ *  Purpose:
+ *  This ioctl interface to messageq_free function
+ */
+static inline int messageq_ioctl_free(struct messageq_cmd_args *cargs)
+{
+	int status = 0;
+	messageq_msg msg;
+
+	msg = sharedregion_get_ptr(cargs->args.free.msg_srptr);
+	if (unlikely(msg == NULL))
+		goto exit;
+	status = messageq_free(msg);
+
+	cargs->api_status = status;
+exit:
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_params_init ========
+ *  Purpose:
+ *  This ioctl interface to messageq_params_init function
+ */
+static inline int messageq_ioctl_params_init(struct messageq_cmd_args *cargs)
+{
+	s32 retval = 0;
+	int status = 0;
+	unsigned long size;
+	struct messageq_params params;
+
+	messageq_params_init(&params);
+	size = copy_to_user(cargs->args.params_init.params, &params,
+				sizeof(struct messageq_params));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = status;
+exit:
+	return retval;
+}
+
+/*
+ * ======== messageq_ioctl_create ========
+ *  Purpose:
+ *  This ioctl interface to messageq_create function
+ */
+static inline int messageq_ioctl_create(struct messageq_cmd_args *cargs)
+{
+	s32 retval = 0;
+	int status = 0;
+	unsigned long size;
+	struct messageq_params params;
+	char *name = NULL;
+
+	if (cargs->args.create.params != NULL) {
+		size = copy_from_user(&params, cargs->args.create.params,
+						sizeof(struct messageq_params));
+		if (size) {
+			retval = -EFAULT;
+			goto exit;
+		}
+	}
+
+	/* Allocate memory for the name */
+	if (cargs->args.create.name_len > 0) {
+		name = kmalloc(cargs->args.create.name_len, GFP_KERNEL);
+		if (name == NULL) {
+			retval = -ENOMEM;
+			goto exit;
+		}
+		size = copy_from_user(name, cargs->args.create.name,
+						cargs->args.create.name_len);
+		if (size) {
+			retval = -EFAULT;
+			goto free_name;
+		}
+	}
+
+	if (cargs->args.create.params != NULL) {
+		cargs->args.create.messageq_handle = \
+			messageq_create(name, &params);
+	} else {
+		cargs->args.create.messageq_handle = \
+			messageq_create(name, NULL);
+	}
+
+	if (cargs->args.create.messageq_handle != NULL) {
+		cargs->args.create.queue_id = messageq_get_queue_id(
+					 cargs->args.create.messageq_handle);
+	}
+
+free_name:
+	if (cargs->args.create.name_len > 0)
+		kfree(name);
+
+	cargs->api_status = status;
+exit:
+	return retval;
+}
+
+/*
+ * ======== messageq_ioctl_delete ========
+ *  Purpose:
+ *  This ioctl interface to messageq_delete function
+ */
+static inline int messageq_ioctl_delete(struct messageq_cmd_args *cargs)
+{
+	cargs->api_status =
+		messageq_delete(&(cargs->args.delete_messageq.messageq_handle));
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_open ========
+ *  Purpose:
+ *  This ioctl interface to messageq_open function
+ */
+static inline int messageq_ioctl_open(struct messageq_cmd_args *cargs)
+{
+	s32 retval = 0;
+	int status = 0;
+	unsigned long size;
+	char *name = NULL;
+	u32 queue_id = MESSAGEQ_INVALIDMESSAGEQ;
+
+	/* Allocate memory for the name */
+	if (cargs->args.open.name_len > 0) {
+		name = kmalloc(cargs->args.open.name_len, GFP_KERNEL);
+		if (name == NULL) {
+			retval = -ENOMEM;
+			goto exit;
+		}
+		size = copy_from_user(name, cargs->args.open.name,
+						cargs->args.open.name_len);
+		if (size) {
+			retval = -EFAULT;
+			goto free_name;
+		}
+	}
+
+	status = messageq_open(name, &queue_id);
+	cargs->args.open.queue_id = queue_id;
+
+free_name:
+	if (cargs->args.open.name_len > 0)
+		kfree(name);
+
+	cargs->api_status = status;
+exit:
+	return retval;
+}
+
+/*
+ * ======== messageq_ioctl_close ========
+ *  Purpose:
+ *  This ioctl interface to messageq_close function
+ */
+static inline int messageq_ioctl_close(struct messageq_cmd_args *cargs)
+{
+	u32 queue_id = cargs->args.close.queue_id;
+	messageq_close(&queue_id);
+	cargs->args.close.queue_id = queue_id;
+
+	cargs->api_status = 0;
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_get_config ========
+ *  Purpose:
+ *  This ioctl interface to messageq_get_config function
+ */
+static inline int messageq_ioctl_get_config(struct messageq_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct messageq_config config;
+
+	messageq_get_config(&config);
+	size = copy_to_user(cargs->args.get_config.config, &config,
+				sizeof(struct messageq_config));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = 0;
+exit:
+	return retval;
+}
+
+/*
+ * ======== messageq_ioctl_setup ========
+ *  Purpose:
+ *  This ioctl interface to messageq_setup function
+ */
+static inline int messageq_ioctl_setup(struct messageq_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct messageq_config config;
+
+	size = copy_from_user(&config, cargs->args.setup.config,
+					sizeof(struct messageq_config));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status =  messageq_setup(&config);
+
+exit:
+	return retval;
+}
+
+/*
+ * ======== messageq_ioctl_destroy ========
+ *  Purpose:
+ *  This ioctl interface to messageq_destroy function
+ */
+static inline int messageq_ioctl_destroy(struct messageq_cmd_args *cargs)
+{
+	cargs->api_status = messageq_destroy();
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_register_heap ========
+ *  Purpose:
+ *  This ioctl interface to messageq_register_heap function
+ */
+static inline int messageq_ioctl_register_heap(struct messageq_cmd_args *cargs)
+{
+	cargs->api_status = \
+		messageq_register_heap(cargs->args.register_heap.heap_handle,
+				cargs->args.register_heap.heap_id);
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_unregister_heap ========
+ *  Purpose:
+ *  This ioctl interface to messageq_unregister_heap function
+ */
+static inline int messageq_ioctl_unregister_heap(
+					struct messageq_cmd_args *cargs)
+{
+	cargs->api_status =  messageq_unregister_heap(
+				cargs->args.unregister_heap.heap_id);
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_attach ========
+ *  Purpose:
+ *  This ioctl interface to messageq_ioctl_attach function
+ */
+static inline int messageq_ioctl_attach(struct messageq_cmd_args *cargs)
+{
+	void *shared_addr;
+
+	shared_addr = sharedregion_get_ptr(
+				cargs->args.attach.shared_addr_srptr);
+	if (unlikely(shared_addr == NULL)) {
+		cargs->api_status = -1;
+		goto exit;
+	}
+	cargs->api_status = messageq_attach(cargs->args.attach.remote_proc_id,
+				shared_addr);
+
+exit:
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_detach ========
+ *  Purpose:
+ *  This ioctl interface to messageq_ioctl_detach function
+ */
+static inline int messageq_ioctl_detach(struct messageq_cmd_args *cargs)
+{
+	cargs->api_status = messageq_detach(cargs->args.detach.remote_proc_id);
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl_sharedmem_req ========
+ *  Purpose:
+ *  This ioctl interface to messageq_ioctl_sharedmem_req function
+ */
+static inline int messageq_ioctl_shared_mem_req(struct messageq_cmd_args *cargs)
+{
+	void *shared_addr;
+
+	shared_addr = sharedregion_get_ptr(
+				cargs->args.shared_mem_req.shared_addr_srptr);
+	if (unlikely(shared_addr == NULL)) {
+		cargs->api_status = -1;
+		goto exit;
+	}
+	cargs->args.shared_mem_req.mem_req = \
+			messageq_shared_mem_req(shared_addr);
+	cargs->api_status = 0;
+
+exit:
+	return 0;
+}
+
+/*
+ * ======== messageq_ioctl ========
+ *  Purpose:
+ *  ioctl interface function for messageq module
+ */
+int messageq_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args)
+{
+	int os_status = 0;
+	struct messageq_cmd_args __user *uarg =
+				(struct messageq_cmd_args __user *)args;
+	struct messageq_cmd_args cargs;
+	unsigned long size;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		os_status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		os_status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+	if (os_status) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg, sizeof(struct messageq_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_MESSAGEQ_PUT:
+		os_status = messageq_ioctl_put(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_GET:
+		os_status = messageq_ioctl_get(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_COUNT:
+		os_status = messageq_ioctl_count(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_ALLOC:
+		os_status = messageq_ioctl_alloc(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_FREE:
+		os_status = messageq_ioctl_free(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_PARAMS_INIT:
+		os_status = messageq_ioctl_params_init(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_CREATE:
+		os_status = messageq_ioctl_create(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_DELETE:
+		os_status = messageq_ioctl_delete(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_OPEN:
+		os_status = messageq_ioctl_open(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_CLOSE:
+		os_status = messageq_ioctl_close(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_GETCONFIG:
+		os_status = messageq_ioctl_get_config(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_SETUP:
+		os_status = messageq_ioctl_setup(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_DESTROY:
+		os_status = messageq_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_REGISTERHEAP:
+		os_status = messageq_ioctl_register_heap(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_UNREGISTERHEAP:
+		os_status = messageq_ioctl_unregister_heap(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_ATTACH:
+		os_status = messageq_ioctl_attach(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_DETACH:
+		os_status = messageq_ioctl_detach(&cargs);
+		break;
+
+	case CMD_MESSAGEQ_SHAREDMEMREQ:
+		os_status = messageq_ioctl_shared_mem_req(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		os_status = -ENOTTY;
+		break;
+	}
+
+	if ((cargs.api_status == -ERESTARTSYS) || (cargs.api_status == -EINTR))
+		os_status = -ERESTARTSYS;
+
+	if (os_status < 0)
+		goto exit;
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs, sizeof(struct messageq_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+	return os_status;
+
+exit:
+	printk(KERN_ERR "messageq_ioctl failed: status = 0x%x\n", os_status);
+	return os_status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/multiproc.c b/drivers/dsp/syslink/multicore_ipc/multiproc.c
new file mode 100644
index 000000000000..df9ddf57e0a6
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/multiproc.c
@@ -0,0 +1,301 @@
+/*
+*  multiproc.c
+*
+*  Many multi-processor modules have the concept of processor id. MultiProc
+*  centeralizes the processor id management.
+*
+*  Copyright (C) 2008-2009 Texas Instruments, Inc.
+*
+*  This package is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License version 2 as
+*  published by the Free Software Foundation.
+*
+*  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+*  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+*  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+*  PURPOSE.
+*/
+
+/*
+ *  ======== multiproc.c ========
+ *  Notes:
+ *  The processor id start at 0 and ascend without skipping values till maximum_
+ *  no_of_processors - 1
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+#include <linux/module.h>
+#include <syslink/atomic_linux.h>
+/* Utilities headers */
+#include <linux/string.h>
+
+/* Module level headers */
+#include <multiproc.h>
+
+/* Macro to make a correct module magic number with ref_count */
+#define MULTIPROC_MAKE_MAGICSTAMP(x) ((MULTIPROC_MODULEID << 12u) | (x))
+
+/*
+ *  multiproc module state object
+ */
+struct multiproc_module_object {
+	struct multiproc_config cfg; /*  Module configuration structure */
+	struct multiproc_config def_cfg; /* Default module configuration */
+	atomic_t ref_count; /* Reference count */
+	u16 id;	/* Local processor ID */
+};
+
+static struct multiproc_module_object multiproc_state = {
+	.def_cfg.num_processors = 4,
+	.def_cfg.name_list[0][0] = "Tesla",
+	.def_cfg.name_list[1][0] = "AppM3",
+	.def_cfg.name_list[2][0] = "SysM3",
+	.def_cfg.name_list[3][0] = "MPU",
+	.def_cfg.id = 3,
+	.id = MULTIPROC_INVALIDID
+};
+
+/*
+ * ========= multiproc_module =========
+ *  Pointer to the MultiProc module state.
+ */
+static struct multiproc_module_object *multiproc_module = &multiproc_state;
+
+
+/*
+ * ======== multiproc_get_config ========
+ *  Purpose:
+ *  This will get the default configuration for the multiproc module
+ */
+void multiproc_get_config(struct multiproc_config *cfg)
+{
+	BUG_ON(cfg == NULL);
+	if (atomic_cmpmask_and_lt(
+			&(multiproc_module->ref_count),
+			MULTIPROC_MAKE_MAGICSTAMP(0),
+			MULTIPROC_MAKE_MAGICSTAMP(1)) == true) {
+			/* (If setup has not yet been called) */
+		memcpy(cfg, &multiproc_module->def_cfg,
+				sizeof(struct multiproc_config));
+	} else {
+		memcpy(cfg, &multiproc_module->cfg,
+				sizeof(struct multiproc_config));
+	}
+}
+EXPORT_SYMBOL(multiproc_get_config);
+
+/*
+ * ======== multiproc_setup ========
+ *  Purpose:
+ *  This function sets up the multiproc module. This function
+ *  must be called before any other instance-level APIs can be
+ *  invoked
+ */
+s32 multiproc_setup(struct multiproc_config *cfg)
+{
+	s32	status = 0;
+	struct multiproc_config tmp_cfg;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of ref_count variable.
+	*/
+	atomic_cmpmask_and_set(&multiproc_module->ref_count,
+				MULTIPROC_MAKE_MAGICSTAMP(0),
+				MULTIPROC_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&multiproc_module->ref_count)
+					!= MULTIPROC_MAKE_MAGICSTAMP(1u)) {
+		status = 1;
+	} else {
+		if (cfg == NULL) {
+			multiproc_get_config(&tmp_cfg);
+			cfg = &tmp_cfg;
+		}
+
+		memcpy(&multiproc_module->cfg, cfg,
+				sizeof(struct multiproc_config));
+		multiproc_module->id = cfg->id;
+	}
+
+	return status;
+}
+EXPORT_SYMBOL(multiproc_setup);
+
+/*
+ * ======== multiproc_setup ========
+ *  Purpose:
+ *  This function destroy the multiproc module.
+ *  Once this function is called, other multiproc module APIs,
+ *  except for the multiproc_get_config API cannot be called
+ *  anymore.
+ */
+s32 multiproc_destroy(void)
+{
+	int status = 0;
+
+	if (atomic_cmpmask_and_lt(
+			&(multiproc_module->ref_count),
+			MULTIPROC_MAKE_MAGICSTAMP(0),
+			MULTIPROC_MAKE_MAGICSTAMP(1)) == true) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	atomic_dec_return(&multiproc_module->ref_count);
+
+exit:
+	return status;
+}
+EXPORT_SYMBOL(multiproc_destroy);
+
+/*
+ * ======== multiProc_set_local_id ========
+ *  Purpose:
+ *  This will set the processor id of local processor on run time
+ */
+int multiproc_set_local_id(u16 proc_id)
+{
+	int status = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(multiproc_module->ref_count),
+			MULTIPROC_MAKE_MAGICSTAMP(0),
+			MULTIPROC_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (WARN_ON(proc_id >= MULTIPROC_MAXPROCESSORS)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	multiproc_module->cfg.id = proc_id;
+
+exit:
+	return status;
+}
+EXPORT_SYMBOL(multiproc_set_local_id);
+
+/*
+ * ======== multiProc_get_local_id ========
+ *  Purpose:
+ *  This will get the processor id from proccessor name
+ */
+u16 multiproc_get_id(const char *proc_name)
+{
+	s32 i;
+	u16 proc_id = MULTIPROC_INVALIDID;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(multiproc_module->ref_count),
+			MULTIPROC_MAKE_MAGICSTAMP(0),
+			MULTIPROC_MAKE_MAGICSTAMP(1)) == true))
+		goto exit;
+
+	/* If the name is NULL, just return the local id */
+	if (proc_name == NULL)
+		proc_id = multiproc_module->cfg.id;
+	else {
+		for (i = 0; i < multiproc_module->cfg.num_processors ; i++) {
+			if (strcmp(proc_name,
+				&multiproc_module->cfg.name_list[i][0]) == 0) {
+				proc_id = i;
+				break;
+			}
+		}
+	}
+
+exit:
+	return proc_id;
+}
+EXPORT_SYMBOL(multiproc_get_id);
+
+/*
+ * ======== multiProc_set_local_id ========
+ *  Purpose:
+ *  This will get the processor name from proccessor id
+ */
+char *multiproc_get_name(u16 proc_id)
+{
+	char *proc_name = NULL;
+
+	/* On error condition return NULL pointer, else entry from name list */
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(multiproc_module->ref_count),
+			MULTIPROC_MAKE_MAGICSTAMP(0),
+			MULTIPROC_MAKE_MAGICSTAMP(1)) == true))
+		goto exit;
+
+	if (WARN_ON(proc_id >= MULTIPROC_MAXPROCESSORS))
+		goto exit;
+
+	proc_name = multiproc_module->cfg.name_list[proc_id];
+
+exit:
+	return proc_name;
+}
+EXPORT_SYMBOL(multiproc_get_name);
+
+/*
+ * ======== multiproc_get_num_processors ========
+ *  Purpose:
+ *  This will get the number of processors in the system
+ */
+u16 multiproc_get_num_processors(void)
+{
+	return multiproc_module->cfg.num_processors;
+}
+EXPORT_SYMBOL(multiproc_get_num_processors);
+
+/*
+ * ======== multiproc_self ========
+ *  Purpose:
+ *  Return Id of current processor
+ */
+u16 multiproc_self(void)
+{
+	return multiproc_module->id;
+}
+EXPORT_SYMBOL(multiproc_self);
+
+/*
+ * ======== multiproc_get_slot ========
+ * Determines the offset for any two processors.
+ */
+u32 multiproc_get_slot(u16 remote_proc_id)
+{
+	u32 slot = 0u;
+	u32 i;
+	u32 j;
+	u32 small_id;
+	u32 large_id;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(multiproc_module->ref_count),
+			MULTIPROC_MAKE_MAGICSTAMP(0),
+			MULTIPROC_MAKE_MAGICSTAMP(1)) == true))
+		goto exit;
+
+	if (remote_proc_id > multiproc_self()) {
+		small_id = multiproc_self();
+		large_id = remote_proc_id;
+	} else {
+		large_id = multiproc_self();
+		small_id = remote_proc_id;
+	}
+
+	/* determine what offset to create for the remote Proc Id */
+	for (i = 0; i < multiproc_module->cfg.num_processors; i++) {
+		for (j = i + 1; j < multiproc_module->cfg.num_processors; j++) {
+			if ((small_id == i) && (large_id == j))
+				break;
+			slot++;
+		}
+	}
+
+exit:
+	return slot;
+}
+EXPORT_SYMBOL(multiproc_get_slot);
diff --git a/drivers/dsp/syslink/multicore_ipc/multiproc_ioctl.c b/drivers/dsp/syslink/multicore_ipc/multiproc_ioctl.c
new file mode 100644
index 000000000000..8f36304f3397
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/multiproc_ioctl.c
@@ -0,0 +1,171 @@
+/*
+*  multiproc_ioctl.c
+*
+*  This provides the ioctl interface for multiproc module
+*
+*  Copyright (C) 2008-2009 Texas Instruments, Inc.
+*
+*  This package is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License version 2 as
+*  published by the Free Software Foundation.
+*
+*  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+*  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+*  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+*  PURPOSE.
+*/
+#include <linux/uaccess.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <multiproc.h>
+#include <multiproc_ioctl.h>
+
+/*
+ * ======== mproc_ioctl_setup ========
+ *  Purpose:
+ *  This wrapper function will call the multproc function
+ *  to setup the module
+ */
+static int mproc_ioctl_setup(struct multiproc_cmd_args *cargs)
+{
+	struct multiproc_config config;
+	s32 status = 0;
+	ulong size;
+
+	size = copy_from_user(&config,
+				cargs->args.setup.config,
+				sizeof(struct multiproc_config));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = multiproc_setup(&config);
+
+exit:
+	return status;
+}
+
+/*
+ * ======== mproc_ioctl_destroy ========
+ *	Purpose:
+ *	This wrapper function will call the multproc function
+ *	to destroy the module
+ */
+static int mproc_ioctl_destroy(struct multiproc_cmd_args *cargs)
+{
+	cargs->api_status = multiproc_destroy();
+	return 0;
+}
+
+/*
+ * ======== mproc_ioctl_get_config ========
+ *	Purpose:
+ *	This wrapper function will call the multproc function
+ *	to get the default configuration the module
+ */
+static int mproc_ioctl_get_config(struct multiproc_cmd_args *cargs)
+{
+	struct multiproc_config config;
+	u32 size;
+
+	multiproc_get_config(&config);
+	size = copy_to_user(cargs->args.get_config.config, &config,
+				sizeof(struct multiproc_config));
+	if (size) {
+		cargs->api_status = -EFAULT;
+		return 0;
+	}
+	cargs->api_status = 0;
+	return 0;
+}
+
+/*
+ * ======== mproc_ioctl_setup ========
+ *	Purpose:
+ *	This wrapper function will call the multproc function
+ *	to setup the module
+ */
+static int multiproc_ioctl_set_local_id(struct multiproc_cmd_args *cargs)
+{
+	cargs->api_status = multiproc_set_local_id(cargs->args.set_local_id.id);
+	return 0;
+}
+
+/*
+ * ======== multiproc_ioctl ========
+ *  Purpose:
+ *  This ioctl interface for multiproc module
+ */
+int multiproc_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args)
+{
+	s32 status = 0;
+	s32 size = 0;
+	struct multiproc_cmd_args __user *uarg =
+				(struct multiproc_cmd_args __user *)args;
+	struct multiproc_cmd_args cargs;
+
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+
+	if (status) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg,
+					sizeof(struct multiproc_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_MULTIPROC_SETUP:
+		status = mproc_ioctl_setup(&cargs);
+		break;
+
+	case CMD_MULTIPROC_DESTROY:
+		status = mproc_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_MULTIPROC_GETCONFIG:
+		status = mproc_ioctl_get_config(&cargs);
+		break;
+
+	case CMD_MULTIPROC_SETLOCALID:
+		status = multiproc_ioctl_set_local_id(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		status = -ENOTTY;
+		break;
+	}
+
+	if ((cargs.api_status == -ERESTARTSYS) || (cargs.api_status == -EINTR))
+		status = -ERESTARTSYS;
+
+	if (status < 0)
+		goto exit;
+
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs, sizeof(struct multiproc_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+exit:
+	return status;
+
+}
+
diff --git a/drivers/dsp/syslink/multicore_ipc/nameserver.c b/drivers/dsp/syslink/multicore_ipc/nameserver.c
new file mode 100644
index 000000000000..4278da5eca34
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/nameserver.c
@@ -0,0 +1,1540 @@
+/*
+ *  nameserver.c
+ *
+ *  The nameserver module manages local name/value pairs that
+ *  enables an application and other modules to store and retrieve
+ *  values based on a name.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <syslink/atomic_linux.h>
+
+#include <nameserver.h>
+#include <multiproc.h>
+#include <nameserver_remote.h>
+
+#define NS_MAX_NAME_LEN				32
+#define NS_MAX_RUNTIME_ENTRY			(~0)
+#define NS_MAX_VALUE_LEN			4
+
+/*
+ *  The dynamic name/value table looks like the following. This approach allows
+ *  each instance table to have different value and different name lengths.
+ *  The names block is allocated on the create. The size of that block is
+ *  (max_runtime_entries * max_name_en). That block is sliced and diced up and
+ *  given to each table entry.
+ *  The same thing is done for the values block.
+ *
+ *     names                    table                  values
+ *   -------------           -------------          -------------
+ *   |           |<-\        |   elem    |   /----->|           |
+ *   |           |   \-------|   name    |  /       |           |
+ *   |           |           |   value   |-/        |           |
+ *   |           |           |   len     |          |           |
+ *   |           |<-\        |-----------|          |           |
+ *   |           |   \       |   elem    |          |           |
+ *   |           |    \------|   name    |  /------>|           |
+ *   |           |           |   value   |-/        |           |
+ *   -------------           |   len     |          |           |
+ *                           -------------          |           |
+ *                                                  |           |
+ *                                                  |           |
+ *                                                  -------------
+ *
+ *  There is an optimization for small values (e.g. <= sizeof(UInt32).
+ *  In this case, there is no values block allocated. Instead the value
+  *  field is used directly.  This optimization occurs and is managed when
+ *  obj->max_value_len <= sizeof(Us3232).
+ *
+ *  The static create is a little different. The static entries point directly
+ *  to a name string (and value). Since it points directly to static items,
+ *  this entries cannot be removed.
+ *  If max_runtime_entries is non-zero, a names and values block is created.
+ *  Here is an example of a table with 1 static entry and 2 dynamic entries
+ *
+ *                           ------------
+ *  this entries cannot be removed.
+ *  If max_runtime_entries is non-zero, a names and values block is created.
+ *  Here is an example of a table with 1 static entry and 2 dynamic entries
+ *
+ *                           ------------
+ *                           |   elem   |
+ *      "myName" <-----------|   name   |----------> someValue
+ *                           |   value  |
+ *     names                 |   len    |              values
+ *   -------------           -------------          -------------
+ *   |           |<-\        |   elem    |   /----->|           |
+ *   |           |   \-------|   name    |  /       |           |
+ *   |           |           |   value   |-/        |           |
+ *   |           |           |   len     |          |           |
+ *   |           |<-\        |-----------|          |           |
+ *   |           |   \       |   elem    |          |           |
+ *   |           |    \------|   name    |  /------>|           |
+ *   |           |           |   value   |-/        |           |
+ *   -------------           |   len     |          |           |
+ *                           -------------          |           |
+ *                                                  |           |
+ *                                                  |           |
+ *                                                  -------------
+ *
+ *  NameServerD uses a freeList and namelist to maintain the empty
+ *  and filled-in entries. So when a name/value pair is added, an entry
+ *  is pulled off the freeList, filled-in and placed on the namelist.
+ *  The reverse happens on a remove.
+ *
+ *  For static adds, the entries are placed on the namelist statically.
+ *
+ *  For dynamic creates, the freeList is populated in postInt and there are no
+ *  entries placed on the namelist (this happens when the add is called).
+ *
+ */
+
+/* Macro to make a correct module magic number with refCount */
+#define NAMESERVER_MAKE_MAGICSTAMP(x) ((NAMESERVER_MODULEID << 12u) | (x))
+
+/*
+ *  A name/value table entry
+ */
+struct nameserver_table_entry {
+	struct list_head elem; /* List element */
+	u32 hash; /* Hash value */
+	char *name; /* Name portion of name/value pair */
+	u32 len; /* Length of the value field. */
+	void *buf; /* Value portion of name/value entry */
+	bool collide; /* Does the hash collides? */
+	struct nameserver_table_entry *next; /* Pointer to the next entry,
+					used incase of collision only */
+};
+
+/*
+ * A nameserver instance object
+ */
+struct nameserver_object {
+	struct list_head elem;
+	char *name; /* Name of the instance */
+	struct list_head name_list; /* Filled entries list */
+	struct mutex *gate_handle; /* Gate for critical regions */
+	struct nameserver_params params; /* The parameter structure */
+	u32 count; /* Counter for entries */
+};
+
+
+/* nameserver module state object */
+struct nameserver_module_object {
+	struct list_head obj_list; /* List holding created objects */
+	struct mutex *mod_gate_handle; /* Handle to module gate */
+	struct nameserver_remote_object **remote_handle_list;
+	/* List of Remote driver handles for processors */
+	atomic_t ref_count; /* Reference count */
+	struct nameserver_params def_inst_params;
+	/* Default instance paramters */
+	struct nameserver_config def_cfg; /* Default module configuration */
+	struct nameserver_config cfg; /* Module configuration */
+
+};
+
+/*
+ * Variable for holding state of the nameserver module.
+ */
+static struct nameserver_module_object nameserver_state = {
+	.def_cfg.reserved = 0x0,
+	.def_inst_params.max_runtime_entries = 0u,
+	.def_inst_params.table_heap = NULL,
+	.def_inst_params.check_existing = true,
+	.def_inst_params.max_value_len = 0u,
+	.def_inst_params.max_name_len = 16u,
+	.mod_gate_handle = NULL,
+	.remote_handle_list = NULL,
+};
+
+/*
+ *  Pointer to the SharedRegion module state
+ */
+static struct nameserver_module_object *nameserver_module = &(nameserver_state);
+
+/*
+ * Lookup table for CRC calculation.
+ */
+static const u32 nameserver_crc_table[256u] = {
+  0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
+  0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+  0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+  0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+  0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
+  0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+  0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
+  0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+  0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+  0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+  0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
+  0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+  0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
+  0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+  0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+  0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+  0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
+  0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+  0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
+  0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+  0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+  0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+  0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
+  0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+  0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+  0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+  0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+  0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+  0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
+  0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+  0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
+  0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+  0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+  0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+  0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+  0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+  0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
+  0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+  0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+  0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+  0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
+  0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+  0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+
+/* Function to calculate hash for a string */
+static u32 _nameserver_string_hash(const char *string);
+
+#if 0
+/* This will return true if the entry is found in the table */
+static bool _nameserver_is_entry_found(const char *name, u32 hash,
+				struct list_head *list,
+				struct nameserver_table_entry **entry);
+#endif
+
+/* This will return true if the hash is found in the table */
+static bool _nameserver_is_hash_found(const char *name, u32 hash,
+				struct list_head *list,
+				struct nameserver_table_entry **entry);
+
+/* This will return true if entry is found in the hash collide list */
+static bool _nameserver_check_for_entry(const char *name,
+					struct nameserver_table_entry **entry);
+
+/* Function to get the default configuration for the NameServer module. */
+void nameserver_get_config(struct nameserver_config *cfg)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(cfg == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (atomic_cmpmask_and_lt(&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true) {
+		/* (If setup has not yet been called) */
+		memcpy(cfg, &nameserver_module->def_cfg,
+			sizeof(struct nameserver_config));
+	} else {
+		memcpy(cfg, &nameserver_module->cfg,
+			sizeof(struct nameserver_config));
+	}
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_get_config failed! retval = 0x%x",
+			retval);
+	}
+	return;
+}
+EXPORT_SYMBOL(nameserver_get_config);
+
+/* This will setup the nameserver module */
+int nameserver_setup(void)
+{
+	struct nameserver_remote_object **list = NULL;
+	s32 retval = 0;
+	u16 nr_procs = 0;
+
+	/* This sets the ref_count variable if not initialized, upper 16 bits is
+	*   written with module Id to ensure correctness of refCount variable
+	*/
+	atomic_cmpmask_and_set(&nameserver_module->ref_count,
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&nameserver_module->ref_count)
+				!= NAMESERVER_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	INIT_LIST_HEAD(&nameserver_state.obj_list),
+
+	nameserver_module->mod_gate_handle = kmalloc(sizeof(struct mutex),
+						GFP_KERNEL);
+	if (nameserver_module->mod_gate_handle == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+	/* mutex is initialized with state = UNLOCKED */
+	mutex_init(nameserver_module->mod_gate_handle);
+
+	nr_procs = multiproc_get_num_processors();
+	list = kmalloc(nr_procs * sizeof(struct nameserver_remote_object *),
+					GFP_KERNEL);
+	if (list == NULL) {
+		retval = -ENOMEM;
+		goto remote_alloc_fail;
+	}
+	memset(list, 0, nr_procs * sizeof(struct nameserver_remote_object *));
+	nameserver_module->remote_handle_list = list;
+
+	return 0;
+
+remote_alloc_fail:
+	kfree(nameserver_module->mod_gate_handle);
+exit:
+	printk(KERN_ERR "nameserver_setup failed, retval: %x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_setup);
+
+/* This will destroy the nameserver module */
+int nameserver_destroy(void)
+{
+	s32 retval = 0;
+	struct mutex *lock = NULL;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (!(atomic_dec_return(&nameserver_module->ref_count)
+					== NAMESERVER_MAKE_MAGICSTAMP(0))) {
+		retval = 1;
+		goto exit;
+	}
+
+	if (WARN_ON(nameserver_module->mod_gate_handle == NULL)) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	/* If a nameserver instance exist, do not proceed  */
+	if (!list_empty(&nameserver_module->obj_list)) {
+		retval = -EBUSY;
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(nameserver_module->mod_gate_handle);
+	if (retval)
+		goto exit;
+
+	lock = nameserver_module->mod_gate_handle;
+	nameserver_module->mod_gate_handle = NULL;
+	mutex_unlock(lock);
+	kfree(lock);
+	kfree(nameserver_module->remote_handle_list);
+	nameserver_module->remote_handle_list = NULL;
+	return 0;
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_destroy failed, retval: %x\n",
+			retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_destroy);
+
+/* Initialize this config-params structure with supplier-specified
+ * defaults before instance creation. */
+void nameserver_params_init(struct nameserver_params *params)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	memcpy(params, &nameserver_module->def_inst_params,
+		sizeof(struct nameserver_params));
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_params_init failed! status = 0x%x",
+			retval);
+	}
+	return;
+}
+EXPORT_SYMBOL(nameserver_params_init);
+
+/* This will create a name server instance */
+void *nameserver_create(const char *name,
+			const struct nameserver_params *params)
+{
+	struct nameserver_object *new_obj = NULL;
+	u32 name_len;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	name_len = strlen(name) + 1;
+	if (name_len > params->max_name_len) {
+		retval = -E2BIG;
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(nameserver_module->mod_gate_handle);
+	if (retval)
+		goto exit;
+
+	/* check if the name is already registered or not */
+	new_obj = nameserver_get_handle(name);
+	if (new_obj != NULL) {
+		retval = -EEXIST;
+		goto error_handle;
+	}
+
+	new_obj = kmalloc(sizeof(struct nameserver_object), GFP_KERNEL);
+	if (new_obj == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+
+	new_obj->name = kmalloc(name_len, GFP_ATOMIC);
+	if (new_obj->name == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+
+	strncpy(new_obj->name, name, name_len);
+	memcpy(&new_obj->params, params, sizeof(struct nameserver_params));
+	if (params->max_value_len < sizeof(u32))
+		new_obj->params.max_value_len = sizeof(u32);
+	else
+		new_obj->params.max_value_len = params->max_value_len;
+
+	new_obj->gate_handle = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (new_obj->gate_handle == NULL) {
+			retval = -ENOMEM;
+			goto error_mutex;
+	}
+
+	mutex_init(new_obj->gate_handle);
+	new_obj->count = 0;
+	/* Put in the nameserver instance to local list */
+	INIT_LIST_HEAD(&new_obj->name_list);
+	INIT_LIST_HEAD(&new_obj->elem);
+	list_add(&new_obj->elem, &nameserver_module->obj_list);
+	mutex_unlock(nameserver_module->mod_gate_handle);
+	return (void *)new_obj;
+
+error_mutex:
+	kfree(new_obj->name);
+error:
+	kfree(new_obj);
+error_handle:
+	mutex_unlock(nameserver_module->mod_gate_handle);
+exit:
+	printk(KERN_ERR "nameserver_create failed retval:%x\n", retval);
+	return NULL;
+}
+EXPORT_SYMBOL(nameserver_create);
+
+/* Function to construct a name server. */
+void nameserver_construct(void *handle, const char *name,
+				const struct nameserver_params *params)
+{
+	struct nameserver_object *obj = NULL;
+	u32 name_len = 0;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params->table_heap == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	/* check if the name is already registered or not */
+	if (nameserver_get_handle(name)) {
+		retval = -EEXIST; /* NameServer_E_ALREADYEXISTS */
+		goto exit;
+	}
+	name_len = strlen(name) + 1;
+	if (name_len > params->max_name_len) {
+		retval = -E2BIG;
+		goto exit;
+	}
+
+	obj = (struct nameserver_object *) handle;
+	/* Allocate memory for the name */
+	obj->name = kmalloc(name_len, GFP_ATOMIC);
+	if (obj->name == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+
+	/* Copy the name */
+	strncpy(obj->name, name, strlen(name) + 1u);
+	/* Copy the params */
+	memcpy((void *) &obj->params, (void *) params,
+			sizeof(struct nameserver_params));
+
+	if (params->max_value_len < sizeof(u32))
+		obj->params.max_value_len = sizeof(u32);
+	else
+		obj->params.max_value_len = params->max_value_len;
+
+	/* Construct the list */
+	INIT_LIST_HEAD(&obj->name_list);
+
+	obj->gate_handle = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (obj->gate_handle == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+	mutex_init(obj->gate_handle);
+
+	/* Initialize the count */
+	obj->count = 0u;
+
+	/* Put in the local list */
+	retval = mutex_lock_interruptible(nameserver_module->mod_gate_handle);
+	if (retval)
+		goto exit;
+	INIT_LIST_HEAD(&obj->elem);
+	list_add(&obj->elem, &nameserver_module->obj_list);
+	mutex_unlock(nameserver_module->mod_gate_handle);
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_construct failed! retval = 0x%x",
+			retval);
+	}
+	return;
+}
+
+/* This will delete a name server instance */
+int nameserver_delete(void **handle)
+{
+	struct nameserver_object *temp_obj = NULL;
+	struct mutex *gate_handle = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(*handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	temp_obj = (struct nameserver_object *) (*handle);
+	if (WARN_ON(unlikely((temp_obj->name == NULL) &&
+		(nameserver_get_handle(temp_obj->name) == NULL)))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	gate_handle = temp_obj->gate_handle;
+	retval = mutex_lock_interruptible(gate_handle);
+	if (retval)
+		goto exit;
+
+	/* Do not proceed if an entry in the in the table */
+	if (temp_obj->count != 0) {
+		retval = -EBUSY;
+		goto error;
+	}
+
+	retval = mutex_lock_interruptible(nameserver_module->mod_gate_handle);
+	if (retval)
+		goto error;
+	list_del(&temp_obj->elem);
+	mutex_unlock(nameserver_module->mod_gate_handle);
+
+	/* free the memory allocated for instance name */
+	kfree(temp_obj->name);
+	temp_obj->name = NULL;
+
+	/* Free the memory used for handle */
+	INIT_LIST_HEAD(&temp_obj->name_list);
+	kfree(temp_obj);
+	*handle = NULL;
+	mutex_unlock(gate_handle);
+	kfree(gate_handle);
+	return 0;
+
+error:
+	mutex_unlock(gate_handle);
+exit:
+	printk(KERN_ERR "nameserver_delete failed retval:%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_delete);
+
+/* Function to destroy a name server. */
+void nameserver_destruct(void *handle)
+{
+	struct nameserver_object *obj = NULL;
+	struct mutex *gate_handle = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct nameserver_object *) handle;
+	if (nameserver_get_handle(obj->name) == NULL) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	/* enter the critical section */
+	gate_handle = obj->gate_handle;
+	retval = mutex_lock_interruptible(gate_handle);
+	if (retval)
+		goto exit;
+	/* Do not proceed if an entry in the in the table */
+	if (obj->count != 0) {
+		retval = -EBUSY;
+		goto error;
+	}
+
+	retval = mutex_lock_interruptible(nameserver_module->mod_gate_handle);
+	if (retval)
+		goto error;
+	list_del(&obj->elem);
+	mutex_unlock(nameserver_module->mod_gate_handle);
+
+	/* free the memory allocated for the name */
+	kfree(obj->name);
+	obj->name = NULL;
+
+	/* Destruct the list */
+	INIT_LIST_HEAD(&obj->name_list);
+
+	/* Free the memory used for obj */
+	memset(obj, 0, sizeof(struct nameserver_object));
+
+	/* leave the critical section */
+	mutex_unlock(gate_handle);
+	kfree(gate_handle);
+	return;
+
+error:
+	/* leave the critical section */
+	mutex_unlock(obj->gate_handle);
+
+exit:
+	printk(KERN_ERR "nameserver_destruct failed! status = 0x%x", retval);
+	return;
+}
+
+/* This will add an entry into a nameserver instance */
+void *nameserver_add(void *handle, const char *name,
+		void *buf, u32 len)
+{
+	struct nameserver_table_entry *node = NULL;
+	struct nameserver_table_entry *new_node = NULL;
+	struct nameserver_object *temp_obj = NULL;
+	bool found = false;
+	bool exact_entry = false;
+	u32 hash;
+	u32 name_len;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(buf == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(len == 0))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	temp_obj = (struct nameserver_object *)handle;
+	retval = mutex_lock_interruptible(temp_obj->gate_handle);
+	if (retval)
+		goto exit;
+	if (temp_obj->count >= temp_obj->params.max_runtime_entries) {
+		retval = -ENOSPC;
+		goto error;
+	}
+
+	/* make the null char in to account */
+	name_len = strlen(name) + 1;
+	if (name_len > temp_obj->params.max_name_len) {
+		retval = -E2BIG;
+		goto error;
+	}
+
+	/* TODO : hash and collide ?? */
+	hash = _nameserver_string_hash(name);
+	found = _nameserver_is_hash_found(name, hash,
+					&temp_obj->name_list, &node);
+	if (found == true)
+		exact_entry = _nameserver_check_for_entry(name, &node);
+
+	if (exact_entry == true && temp_obj->params.check_existing == true) {
+		retval = -EEXIST;
+		goto error;
+	}
+
+	new_node = kmalloc(sizeof(struct nameserver_table_entry), GFP_KERNEL);
+	if (new_node == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+
+	new_node->hash    = hash;
+	new_node->collide = found;
+	new_node->len     = len;
+	new_node->next    = NULL;
+	new_node->name    = kmalloc(name_len, GFP_KERNEL);
+	if (new_node->name == NULL) {
+		retval = -ENOMEM;
+		goto error_name;
+	}
+	new_node->buf  = kmalloc(len, GFP_KERNEL);
+	if (new_node->buf == NULL) {
+		retval = -ENOMEM;
+		goto error_buf;
+	}
+
+	strncpy(new_node->name, name, name_len);
+	memcpy(new_node->buf, buf, len);
+	if (found == true) {
+		/* If hash is found, need to stitch the list to link the
+		* new node to the existing node with the same hash. */
+		new_node->next = node->next;
+		node->next = new_node;
+		node->collide = found;
+	} else
+		list_add(&new_node->elem, &temp_obj->name_list);
+	temp_obj->count++;
+	mutex_unlock(temp_obj->gate_handle);
+	return new_node;
+
+error_buf:
+	kfree(new_node->name);
+error_name:
+	kfree(new_node);
+error:
+	mutex_unlock(temp_obj->gate_handle);
+exit:
+	printk(KERN_ERR "nameserver_add failed status: %x\n", retval);
+	return NULL;
+}
+EXPORT_SYMBOL(nameserver_add);
+
+/* This will add a Uint32 value into a nameserver instance */
+void *nameserver_add_uint32(void *handle, const char *name,
+			u32 value)
+{
+	s32 retval = 0;
+	struct nameserver_table_entry *new_node = NULL;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	new_node = nameserver_add(handle, name, &value, sizeof(u32));
+
+exit:
+	if (retval < 0 || new_node == NULL) {
+		printk(KERN_ERR "nameserver_add_uint32 failed! status = 0x%x "
+			"new_node = 0x%x", retval, (u32)new_node);
+	}
+	return new_node;
+}
+EXPORT_SYMBOL(nameserver_add_uint32);
+
+/* This will remove a name/value pair from a name server */
+int nameserver_remove(void *handle, const char *name)
+{
+	struct nameserver_object *temp_obj = NULL;
+	struct nameserver_table_entry *entry = NULL;
+	struct nameserver_table_entry *prev = NULL;
+	bool found = false;
+	u32 hash;
+	u32 name_len;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	temp_obj = (struct nameserver_object *)handle;
+	name_len = strlen(name) + 1;
+	if (name_len > temp_obj->params.max_name_len) {
+		retval = -E2BIG;
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(temp_obj->gate_handle);
+	if (retval)
+		goto exit;
+
+	hash = _nameserver_string_hash(name);
+	found = _nameserver_is_hash_found(name, hash,
+					&temp_obj->name_list, &entry);
+	if (found == false) {
+		retval = -ENOENT;
+		goto error;
+	}
+
+	if (entry->collide == true) {
+		if (strcmp(entry->name, name) == 0u) {
+			kfree(entry->buf);
+			kfree(entry->name);
+			entry->hash = entry->next->hash;
+			entry->name = entry->next->name;
+			entry->len = entry->next->len;
+			entry->buf = entry->next->buf;
+			entry->collide = entry->next->collide;
+			entry->next = entry->next->next;
+			kfree(entry->next);
+			temp_obj->count--;
+		} else {
+			found = false;
+			prev = entry;
+			entry = entry->next;
+			while (entry) {
+				if (strcmp(entry->name, name) == 0u) {
+					kfree(entry->buf);
+					kfree(entry->name);
+					prev->next = entry->next;
+					kfree(entry);
+					temp_obj->count--;
+					found = true;
+					break;
+				}
+				prev = entry;
+				entry = entry->next;
+			}
+			if (found == false) {
+				retval = -ENOENT;
+				goto error;
+			}
+		}
+	} else {
+		kfree(entry->buf);
+		kfree(entry->name);
+		list_del(&entry->elem);
+		kfree(entry);
+		temp_obj->count--;
+	}
+
+	mutex_unlock(temp_obj->gate_handle);
+	return 0;
+
+error:
+	mutex_unlock(temp_obj->gate_handle);
+exit:
+	printk(KERN_ERR "nameserver_remove failed status:%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_remove);
+
+/* This will  remove a name/value pair from a name server */
+int nameserver_remove_entry(void *nshandle, void *nsentry)
+{
+	struct nameserver_table_entry *node = NULL;
+	struct nameserver_object *obj = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(nshandle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(nsentry == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct nameserver_object *)nshandle;
+	node = (struct nameserver_table_entry *)nsentry;
+	retval = mutex_lock_interruptible(obj->gate_handle);
+	if (retval)
+		goto exit;
+
+	kfree(node->buf);
+	kfree(node->name);
+	list_del(&node->elem);
+	kfree(node);
+	obj->count--;
+	mutex_unlock(obj->gate_handle);
+	return 0;
+
+exit:
+	printk(KERN_ERR "nameserver_remove_entry failed status:%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_remove_entry);
+
+
+/* This will retrieve the value portion of a name/value
+ * pair from local table */
+int nameserver_get_local(void *handle, const char *name,
+			void *value, u32 *len)
+{
+	struct nameserver_object *temp_obj = NULL;
+	struct nameserver_table_entry *entry = NULL;
+	bool found = false;
+	u32 hash;
+	u32 length = 0;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(value == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(len == 0))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(*len == 0))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	length = *len;
+	temp_obj = (struct nameserver_object *)handle;
+	retval = mutex_lock_interruptible(temp_obj->gate_handle);
+	if (retval)
+		goto exit;
+
+	hash = _nameserver_string_hash(name);
+	found = _nameserver_is_hash_found(name, hash,
+					&temp_obj->name_list, &entry);
+	if (found == false) {
+		retval = -ENOENT;
+		goto error;
+	}
+
+	if (entry->collide == true) {
+		found = _nameserver_check_for_entry(name, &entry);
+		if (found == false) {
+			retval = -ENOENT;
+			goto error;
+		}
+	}
+
+	if (entry->len >= length) {
+		memcpy(value, entry->buf, length);
+		*len = length;
+	} else {
+		memcpy(value, entry->buf, entry->len);
+		*len = entry->len;
+	}
+
+error:
+	mutex_unlock(temp_obj->gate_handle);
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "nameserver_get_local entry not found!\n");
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_get_local);
+
+/* This will retrieve the value portion of a name/value
+ * pair from local table */
+int nameserver_get(void *handle, const char *name,
+		void *value, u32 *len, u16 proc_id[])
+{
+	struct nameserver_object *temp_obj = NULL;
+	u16 max_proc_id;
+	u16 local_proc_id;
+	s32 retval = -ENOENT;
+	u32 i;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(value == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(len == 0))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(*len == 0))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	temp_obj = (struct nameserver_object *)handle;
+	max_proc_id = multiproc_get_num_processors();
+	local_proc_id = multiproc_self();
+	if (proc_id == NULL) {
+		retval = nameserver_get_local(temp_obj, name, value, len);
+		if (retval == -ENOENT) {
+			for (i = 0; i < max_proc_id; i++) {
+				/* Skip current processor */
+				if (i == local_proc_id)
+					continue;
+
+				if (nameserver_module->remote_handle_list[i] \
+					== NULL)
+					continue;
+
+				retval = nameserver_remote_get(
+						nameserver_module->
+						remote_handle_list[i],
+						temp_obj->name, name, value,
+						len, NULL);
+				if (retval >= 0 || ((retval < 0) &&
+					(retval != -ENOENT)))
+					break;
+			}
+		}
+		goto exit;
+	}
+
+	for (i = 0; i < max_proc_id; i++) {
+		/* Skip processor with invalid id */
+		if (proc_id[i] == MULTIPROC_INVALIDID)
+			continue;
+
+		if (i == local_proc_id) {
+			retval = nameserver_get_local(temp_obj,
+							name, value, len);
+		} else {
+			retval = nameserver_remote_get(
+					nameserver_module->
+					remote_handle_list[proc_id[i]],
+					temp_obj->name, name, value, len, NULL);
+		}
+		if (retval >= 0 || ((retval < 0) && (retval != -ENOENT)))
+			break;
+	}
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "nameserver_get failed: status=%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_get);
+
+/* Gets a 32-bit value by name */
+int nameserver_get_uint32(void *handle, const char *name, void *value,
+				u16 proc_id[])
+{
+	/* Initialize retval to not found */
+	int retval = -ENOENT;
+	u32 len = sizeof(u32);
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(value == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	retval = nameserver_get(handle, name, value, &len, proc_id);
+
+exit:
+	/* -ENOENT is a valid run-time failure. */
+	if ((retval < 0) && (retval != -ENOENT)) {
+		printk(KERN_ERR "nameserver_get_uint32 failed! status = 0x%x",
+			retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_get_uint32);
+
+/* Gets a 32-bit value by name from the local table
+ *
+ * If the name is found, the 32-bit value is copied into the value
+ * argument and a success retval is returned.
+ *
+ * If the name is not found, zero is returned in len and the contents
+ * of value are not modified. Not finding a name is not considered
+ * an error.
+ *
+ * This function only searches the local name/value table. */
+int nameserver_get_local_uint32(void *handle, const char *name, void *value)
+{
+	int retval = 0;
+	u32 len = sizeof(u32);
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(value == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	retval = nameserver_get_local(handle, name, value, &len);
+
+exit:
+	/* -ENOENT is a valid run-time failure. */
+	if ((retval < 0) && (retval != -ENOENT)) {
+		printk(KERN_ERR "nameserver_get_local_uint32 failed! "
+			"status = 0x%x", retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_get_local_uint32);
+
+/* This will retrieve the value portion of a name/value
+ * pair from local table. Returns the number of characters that
+ * matched with an entry. So if "abc" was an entry and you called
+ * match with "abcd", this function will have the "abc" entry.
+ * The return would be 3 since three characters matched */
+int nameserver_match(void *handle, const char *name, u32 *value)
+{
+	struct nameserver_object *temp_obj = NULL;
+	struct nameserver_table_entry *node = NULL;
+	struct nameserver_table_entry *temp = NULL;
+	u32 len = 0;
+	u32 found_len = 0;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(value == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	temp_obj = (struct nameserver_object *)handle;
+	retval = mutex_lock_interruptible(temp_obj->gate_handle);
+	if (retval)
+		goto exit;
+	list_for_each_entry(node, &temp_obj->name_list, elem) {
+		temp = node;
+		while (temp) {
+			len = strlen(temp->name);
+			if (len > found_len) {
+				if (strncmp(temp->name, name, len) == 0u) {
+					*value = (u32)temp->buf;
+					found_len = len;
+				}
+			}
+			temp = temp->next;
+		}
+	}
+	mutex_unlock(temp_obj->gate_handle);
+
+exit:
+	if (retval < 0)
+		printk(KERN_ERR "nameserver_match failed status:%x\n", retval);
+	return found_len;
+}
+EXPORT_SYMBOL(nameserver_match);
+
+/* This will get the handle of a nameserver instance from name */
+void *nameserver_get_handle(const char *name)
+{
+	struct nameserver_object *obj = NULL;
+	bool found = false;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	list_for_each_entry(obj, &nameserver_module->obj_list, elem) {
+		if (strcmp(obj->name, name) == 0) {
+			found = true;
+			break;
+		}
+	}
+	if (found == false) {
+		retval = -ENOENT;
+		goto exit;
+	}
+	return (void *)obj;
+
+exit:
+	printk(KERN_ERR "nameserver_get_handle failed! status = 0x%x", retval);
+	return (void *)NULL;
+}
+EXPORT_SYMBOL(nameserver_get_handle);
+
+/* =============================================================================
+ * Internal functions
+ * =============================================================================
+ */
+/* Function to register a remote driver for a processor */
+int nameserver_register_remote_driver(void *handle, u16 proc_id)
+{
+	s32 retval = 0;
+	u16 proc_count;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	proc_count = multiproc_get_num_processors();
+	if (WARN_ON(unlikely(proc_id >= proc_count))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	nameserver_module->remote_handle_list[proc_id] = \
+		(struct nameserver_remote_object *)handle;
+	return 0;
+
+exit:
+	printk(KERN_ERR "nameserver_register_remote_driver failed! "
+		"status:%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_register_remote_driver);
+
+/* Function to unregister a remote driver. */
+int nameserver_unregister_remote_driver(u16 proc_id)
+{
+	s32 retval = 0;
+	u16 proc_count;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	proc_count = multiproc_get_num_processors();
+	if (WARN_ON(proc_id >= proc_count)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	nameserver_module->remote_handle_list[proc_id] = NULL;
+	return 0;
+
+exit:
+	printk(KERN_ERR "nameserver_unregister_remote_driver failed! "
+		"status:%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_unregister_remote_driver);
+
+/* Determines if a remote driver is registered for the specified id. */
+bool nameserver_is_registered(u16 proc_id)
+{
+	bool registered = false;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+				&(nameserver_module->ref_count),
+				NAMESERVER_MAKE_MAGICSTAMP(0),
+				NAMESERVER_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	registered = (nameserver_module->remote_handle_list[proc_id] != NULL);
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_is_registered failed! "
+			"status = 0x%x", retval);
+	}
+	return registered;
+}
+EXPORT_SYMBOL(nameserver_is_registered);
+
+/* Function to calculate hash for a string */
+static u32 _nameserver_string_hash(const char *string)
+{
+	u32 i;
+	u32 hash ;
+	u32 len = strlen(string);
+
+	for (i = 0, hash = len; i < len; i++)
+		hash = (hash >> 8) ^
+			nameserver_crc_table[(hash & 0xff)] ^ string[i];
+
+	return hash;
+}
+
+#if 0
+/* This will return true if the entry is found in the table */
+static bool _nameserver_is_entry_found(const char *name, u32 hash,
+				struct list_head *list,
+				struct nameserver_table_entry **entry)
+{
+	struct nameserver_table_entry *node = NULL;
+	bool hash_match = false;
+	bool name_match = false;
+
+	list_for_each_entry(node, list, elem) {
+		/* Hash not matches, take next node */
+		if (node->hash == hash)
+			hash_match = true;
+		else
+			continue;
+		/* If the name matches, incase hash is duplicate */
+		if (strcmp(node->name, name) == 0)
+			name_match = true;
+
+		if (hash_match && name_match) {
+			if (entry != NULL)
+				*entry = node;
+			return true;
+		}
+
+		hash_match = false;
+		name_match = false;
+	}
+	return false;
+}
+#endif
+
+/* This will return true if the hash is found in the table */
+static bool _nameserver_is_hash_found(const char *name, u32 hash,
+				struct list_head *list,
+				struct nameserver_table_entry **entry)
+{
+	struct nameserver_table_entry *node = NULL;
+
+	/* No parameter checking as function is internal */
+
+	list_for_each_entry(node, list, elem) {
+		/* Hash not matches, take next node */
+		if (node->hash == hash) {
+			*entry = node;
+			return true;
+		}
+	}
+	return false;
+}
+
+/* This will return true if entry is found in the hash collide list */
+static bool _nameserver_check_for_entry(const char *name,
+					struct nameserver_table_entry **entry)
+{
+	struct nameserver_table_entry *temp = NULL;
+	bool found = false;
+
+	/* No parameter checking as function is internal */
+
+	temp = *entry;
+	while (temp) {
+		if (strcmp(((struct nameserver_table_entry *)temp)->name,
+				name) == 0u) {
+			*entry = temp;
+			found = true;
+			break;
+		}
+		temp = temp->next;
+	}
+
+	return found;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/nameserver_ioctl.c b/drivers/dsp/syslink/multicore_ipc/nameserver_ioctl.c
new file mode 100644
index 000000000000..c4cc75e40cb6
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/nameserver_ioctl.c
@@ -0,0 +1,593 @@
+/*
+* nameserver_ioctl.c
+*
+* This provides the ioctl interface for nameserver module
+*
+* Copyright (C) 2008-2009 Texas Instruments, Inc.
+*
+* This package is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE.
+*/
+#include <linux/uaccess.h>
+#include <linux/types.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <nameserver.h>
+#include <nameserver_ioctl.h>
+
+/*
+ *  FUNCTIONS NEED TO BE REVIEWED OPTIMIZED!
+ */
+
+/*
+ * ======== nameserver_ioctl_setup ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  setup nameserver module
+ */
+static int nameserver_ioctl_setup(
+			struct nameserver_cmd_args *cargs)
+{
+	cargs->api_status = nameserver_setup();
+	return 0;
+}
+
+/*
+ * ======== nameserver_ioctl_destroy ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  destroy nameserver module
+ */
+static int nameserver_ioctl_destroy(
+			struct nameserver_cmd_args *cargs)
+{
+	cargs->api_status = nameserver_destroy();
+	return 0;
+}
+
+/*
+ * ======== nameserver_ioctl_params_init ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  get the default configuration of a nameserver instance
+ */
+static int nameserver_ioctl_params_init(struct nameserver_cmd_args *cargs)
+{
+	struct nameserver_params params;
+	s32 status = 0;
+	ulong size;
+
+	nameserver_params_init(&params);
+	size = copy_to_user(cargs->args.params_init.params, &params,
+				sizeof(struct nameserver_params));
+	if (size)
+		status = -EFAULT;
+	cargs->api_status = 0;
+	return status;
+}
+
+/*
+ * ======== nameserver_ioctl_get_handle ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  get the handle of a nameserver instance from name
+ */
+static int nameserver_ioctl_get_handle(struct nameserver_cmd_args *cargs)
+{
+	void *handle = NULL;
+	char *name = NULL;
+	s32 status = 0;
+	ulong size;
+
+	name = kmalloc(cargs->args.get_handle.name_len, GFP_KERNEL);
+	if (name == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	name[cargs->args.get_handle.name_len] = '\0';
+	size = copy_from_user(name, cargs->args.get_handle.name,
+				cargs->args.get_handle.name_len);
+	if (size) {
+		status = -EFAULT;
+		goto name_from_usr_error;
+	}
+
+	handle = nameserver_get_handle(name);
+	cargs->args.get_handle.handle = handle;
+	cargs->api_status = 0;
+
+name_from_usr_error:
+	kfree(name);
+
+exit:
+	return status;
+}
+
+/*
+ * ======== nameserver_ioctl_create ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  create a name server instance
+ */
+static int nameserver_ioctl_create(struct nameserver_cmd_args *cargs)
+{
+	struct nameserver_params params;
+	void *handle = NULL;
+	char *name = NULL;
+	s32 status = 0;
+	ulong size;
+
+	name = kmalloc(cargs->args.create.name_len, GFP_KERNEL);
+	if (name == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	name[cargs->args.get_handle.name_len] = '\0';
+	size = copy_from_user(name, cargs->args.create.name,
+				cargs->args.create.name_len);
+	if (size) {
+		status = -EFAULT;
+		goto copy_from_usr_error;
+	}
+
+	size = copy_from_user(&params, cargs->args.create.params,
+				sizeof(struct nameserver_params));
+	if (size) {
+		status = -EFAULT;
+		goto copy_from_usr_error;
+	}
+
+	handle = nameserver_create(name, &params);
+	cargs->args.create.handle = handle;
+	cargs->api_status = 0;
+
+copy_from_usr_error:
+	kfree(name);
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== nameserver_ioctl_delete ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  delete a name server instance
+ */
+static int nameserver_ioctl_delete(struct nameserver_cmd_args *cargs)
+{
+	cargs->api_status =
+		nameserver_delete(&cargs->args.delete_instance.handle);
+	return 0;
+}
+
+/*
+ * ======== nameserver_ioctl_add ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  add an entry into a nameserver instance
+ */
+static int nameserver_ioctl_add(struct nameserver_cmd_args *cargs)
+{
+	char *name = NULL;
+	char *buf = NULL;
+	void *entry;
+	s32 status = 0;
+	ulong size;
+
+	name = kmalloc(cargs->args.add.name_len, GFP_KERNEL);
+	if (name == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	name[cargs->args.get_handle.name_len] = '\0';
+	size = copy_from_user(name, cargs->args.add.name,
+				cargs->args.add.name_len);
+	if (size) {
+		status = -EFAULT;
+		goto name_from_usr_error;
+	}
+
+	buf = kmalloc(cargs->args.add.len, GFP_KERNEL);
+	if (buf == NULL) {
+		status = -ENOMEM;
+		goto buf_alloc_error;
+	}
+
+	size = copy_from_user(buf, cargs->args.add.buf,
+					cargs->args.add.len);
+	if (size) {
+		status = -EFAULT;
+		goto buf_from_usr_error;
+	}
+
+	entry = nameserver_add(cargs->args.add.handle, name, buf,
+						cargs->args.add.len);
+	cargs->args.add.entry = entry;
+	cargs->args.add.node = entry;
+	cargs->api_status = 0;
+
+buf_from_usr_error:
+	kfree(buf);
+
+buf_alloc_error: /* Fall through */
+name_from_usr_error:
+	kfree(name);
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== nameserver_ioctl_add_uint32 ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  add a Uint32 entry into a nameserver instance
+ */
+static int nameserver_ioctl_add_uint32(struct nameserver_cmd_args *cargs)
+{
+	char *name = NULL;
+	void *entry;
+	s32 status = 0;
+	ulong size;
+
+	name = kmalloc(cargs->args.addu32.name_len, GFP_KERNEL);
+	if (name == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	name[cargs->args.get_handle.name_len] = '\0';
+	size = copy_from_user(name, cargs->args.addu32.name,
+				cargs->args.addu32.name_len);
+	if (size) {
+		status = -EFAULT;
+		goto name_from_usr_error;
+	}
+
+	entry = nameserver_add_uint32(cargs->args.addu32.handle, name,
+						cargs->args.addu32.value);
+	cargs->args.addu32.entry = entry;
+	cargs->api_status = 0;
+
+name_from_usr_error:
+	kfree(name);
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== nameserver_ioctl_match ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function
+ *  to retrieve the value portion of a name/value
+ *  pair from local table
+ */
+static int nameserver_ioctl_match(struct nameserver_cmd_args *cargs)
+{
+	char *name = NULL;
+	s32 status = 0;
+	ulong size;
+
+	name = kmalloc(cargs->args.match.name_len, GFP_KERNEL);
+	if (name == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	name[cargs->args.get_handle.name_len] = '\0';
+	size = copy_from_user(name, cargs->args.match.name,
+				cargs->args.match.name_len);
+	if (size) {
+		status = -EFAULT;
+		goto name_from_usr_error;
+	}
+
+	cargs->args.match.count = nameserver_match(cargs->args.match.handle,
+					name, &cargs->args.match.value);
+	cargs->api_status = 0;
+
+name_from_usr_error: /* Fall through */
+	kfree(name);
+
+exit:
+	return status;
+}
+
+/*
+ * ======== nameserver_ioctl_remove ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  remove a name/value pair from a name server
+ */
+static int nameserver_ioctl_remove(struct nameserver_cmd_args *cargs)
+{
+	char *name = NULL;
+	s32 status = 0;
+	ulong size;
+
+	name = kmalloc(cargs->args.remove.name_len, GFP_KERNEL);
+	if (name == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	name[cargs->args.get_handle.name_len] = '\0';
+	size = copy_from_user(name, cargs->args.remove.name,
+				cargs->args.remove.name_len);
+	if (size) {
+		status = -EFAULT;
+		goto name_from_usr_error;
+	}
+
+	cargs->api_status =
+		nameserver_remove(cargs->args.remove.handle, name);
+
+name_from_usr_error:
+	kfree(name);
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== nameserver_ioctl_remove_entry ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  remove an entry from a name server
+ */
+static int nameserver_ioctl_remove_entry(struct nameserver_cmd_args *cargs)
+{
+	cargs->api_status = nameserver_remove_entry(
+						cargs->args.remove_entry.handle,
+						cargs->args.remove_entry.entry);
+	return 0;
+}
+
+/*
+ * ======== nameserver_ioctl_get_local ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  retrieve the value portion of a name/value pair from local table
+ */
+static int nameserver_ioctl_get_local(struct nameserver_cmd_args *cargs)
+{
+	char *name = NULL;
+	char *value = NULL;
+	s32 status = 0;
+	ulong size;
+
+	name = kmalloc(cargs->args.get_local.name_len, GFP_KERNEL);
+	if (name == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	name[cargs->args.get_handle.name_len] = '\0';
+	value = kmalloc(cargs->args.get_local.len, GFP_KERNEL);
+	if (value == NULL) {
+		status = -ENOMEM;
+		goto value_alloc_error;
+	}
+
+	size = copy_from_user(name, cargs->args.get_local.name,
+				cargs->args.get_local.name_len);
+	if (size) {
+		status = -EFAULT;
+		goto name_from_usr_error;
+	}
+
+	cargs->api_status = nameserver_get_local(
+					cargs->args.get_local.handle, name,
+					value, &cargs->args.get_local.len);
+	size = copy_to_user(cargs->args.get_local.value, value,
+				cargs->args.get_local.len);
+	if (size)
+		status = -EFAULT;
+
+name_from_usr_error:
+	kfree(value);
+
+value_alloc_error:
+	kfree(name);
+
+exit:
+	return status;
+}
+
+
+/*
+ * ======== nameserver_ioctl_get ========
+ *  Purpose:
+ *  This wrapper function will call the nameserver function to
+ *  retrieve the value portion of a name/value pair from table
+ */
+static int nameserver_ioctl_get(struct nameserver_cmd_args *cargs)
+{
+	char *name = NULL;
+	char *value = NULL;
+	u16 *proc_id = NULL;
+	s32 status = 0;
+	ulong size;
+
+	name = kmalloc(cargs->args.get.name_len, GFP_KERNEL);
+	if (name == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	name[cargs->args.get_handle.name_len] = '\0';
+	value = kmalloc(cargs->args.get.len, GFP_KERNEL);
+	if (value == NULL) {
+		status = -ENOMEM;
+		goto value_alloc_error;
+	}
+
+	if (cargs->args.get.proc_len > 0) {
+		proc_id = kmalloc(cargs->args.get.proc_len, GFP_KERNEL);
+		if (proc_id == NULL) {
+			status = -ENOMEM;
+			goto proc_alloc_error;
+		}
+	}
+
+	size = copy_from_user(name, cargs->args.get.name,
+				cargs->args.get.name_len);
+	if (size) {
+		status = -EFAULT;
+		goto name_from_usr_error;
+	}
+
+	status = copy_from_user(proc_id, cargs->args.get.proc_id,
+					cargs->args.get.proc_len);
+	if (size) {
+		status = -EFAULT;
+		goto proc_from_usr_error;
+	}
+
+	cargs->api_status = nameserver_get(cargs->args.get.handle, name, value,
+					&cargs->args.get.len, proc_id);
+	size = copy_to_user(cargs->args.get.value, value,
+				cargs->args.get.len);
+	if (size)
+		status = -EFAULT;
+
+
+proc_from_usr_error: /* Fall through */
+name_from_usr_error:
+	kfree(proc_id);
+
+proc_alloc_error:
+	kfree(value);
+
+value_alloc_error:
+	kfree(name);
+
+exit:
+	return status;
+}
+
+/*
+ * ======== nameserver_ioctl ========
+ *  Purpose:
+ *  This ioctl interface for nameserver module
+ */
+int nameserver_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args)
+{
+	s32 status = 0;
+	s32 size = 0;
+	struct nameserver_cmd_args __user *uarg =
+				(struct nameserver_cmd_args __user *)args;
+	struct nameserver_cmd_args cargs;
+
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+
+	if (status) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg,
+					sizeof(struct nameserver_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_NAMESERVER_ADD:
+		status = nameserver_ioctl_add(&cargs);
+		break;
+
+	case CMD_NAMESERVER_ADDUINT32:
+		status = nameserver_ioctl_add_uint32(&cargs);
+		break;
+
+	case CMD_NAMESERVER_GET:
+		status = nameserver_ioctl_get(&cargs);
+		break;
+
+	case CMD_NAMESERVER_GETLOCAL:
+		status = nameserver_ioctl_get_local(&cargs);
+		break;
+
+	case CMD_NAMESERVER_MATCH:
+		status = nameserver_ioctl_match(&cargs);
+		break;
+
+	case CMD_NAMESERVER_REMOVE:
+		status = nameserver_ioctl_remove(&cargs);
+		break;
+
+	case CMD_NAMESERVER_REMOVEENTRY:
+		status = nameserver_ioctl_remove_entry(&cargs);
+		break;
+
+	case CMD_NAMESERVER_PARAMS_INIT:
+		status = nameserver_ioctl_params_init(&cargs);
+		break;
+
+	case CMD_NAMESERVER_CREATE:
+		status = nameserver_ioctl_create(&cargs);
+		break;
+
+	case CMD_NAMESERVER_DELETE:
+		status = nameserver_ioctl_delete(&cargs);
+		break;
+
+	case CMD_NAMESERVER_GETHANDLE:
+		status = nameserver_ioctl_get_handle(&cargs);
+		break;
+
+	case CMD_NAMESERVER_SETUP:
+		status = nameserver_ioctl_setup(&cargs);
+		break;
+
+	case CMD_NAMESERVER_DESTROY:
+		status = nameserver_ioctl_destroy(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		status = -ENOTTY;
+		break;
+	}
+
+	if ((cargs.api_status == -ERESTARTSYS) || (cargs.api_status == -EINTR))
+		status = -ERESTARTSYS;
+
+	if (status < 0)
+		goto exit;
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs, sizeof(struct nameserver_cmd_args));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+exit:
+	return status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/nameserver_remote.c b/drivers/dsp/syslink/multicore_ipc/nameserver_remote.c
new file mode 100644
index 000000000000..adc949927c9f
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/nameserver_remote.c
@@ -0,0 +1,48 @@
+/*
+ *  nameserver_remote.c
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+
+#include <nameserver_remote.h>
+
+/* This will get data from remote name server */
+int nameserver_remote_get(const struct nameserver_remote_object *handle,
+				const char *instance_name, const char *name,
+				void *value, u32 *value_len, void *reserved)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (WARN_ON(unlikely(((instance_name == NULL) || (name == NULL)
+		|| (value == NULL) || (value_len == NULL))))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	retval = handle->get(handle, instance_name,
+						name, value, value_len, NULL);
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_remote_get failed! status = 0x%x",
+			retval);
+	}
+	return retval;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/nameserver_remotenotify.c b/drivers/dsp/syslink/multicore_ipc/nameserver_remotenotify.c
new file mode 100644
index 000000000000..9dd60557a5f4
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/nameserver_remotenotify.c
@@ -0,0 +1,824 @@
+/*
+ *  nameserver_remotenotify.c
+ *
+ *  The nameserver_remotenotify module provides functionality to get name
+ *  value pair from a remote nameserver.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/string.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/semaphore.h>
+
+/* Syslink headers */
+#include <syslink/atomic_linux.h>
+
+/* Module level headers */
+#include <multiproc.h>
+#include <sharedregion.h>
+#include <gate_remote.h>
+#include <gatemp.h>
+#include <nameserver.h>
+#include <nameserver_remotenotify.h>
+#include <notify.h>
+
+
+/*
+ *  Macro to make a correct module magic number with refCount
+ */
+#define NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(x)	\
+			((NAMESERVERREMOTENOTIFY_MODULEID << 12u) | (x))
+
+/*
+ *  Cache line length
+ *  TODO: Short-term hack. Make parameter or figure out some other way!
+ */
+#define NAMESERVERREMOTENOTIFY_CACHESIZE	128
+
+/*
+ *  Maximum length of value buffer that can be stored in the NameServer
+ *  managed by this NameServerRemoteNotify instance. Value in 4-byte words
+ */
+#define NAMESERVERREMOTENOTIFY_MAXVALUEBUFLEN	75
+
+/* Defines the nameserver_remotenotify state object, which contains all the
+ * module specific information
+ */
+struct nameserver_remotenotify_module_object {
+	struct nameserver_remotenotify_config cfg;
+	struct nameserver_remotenotify_config def_cfg;
+	struct nameserver_remotenotify_params def_inst_params;
+	bool is_setup;
+	void *gate_handle;
+	atomic_t ref_count;
+	void *nsr_handles[MULTIPROC_MAXPROCESSORS];
+};
+
+/*
+ *  NameServer remote transport packet definition
+ */
+struct nameserver_remotenotify_message {
+	u32 request; /* If this is a request set to 1 */
+	u32 response; /* If this is a response set to 1 */
+	u32 request_status; /* If request sucessful set to 1 */
+	u32 value; /* Holds value if len <= 4 */
+	u32 value_len; /* Len of value */
+	u32 instance_name[8]; /* Name of NameServer instance */
+	u32 name[8]; /* Size is 8 to align to 128 cache line boundary */
+	u32 value_buf[NAMESERVERREMOTENOTIFY_MAXVALUEBUFLEN];
+		/* Supports up to 300-byte value */
+};
+
+/*
+ *  NameServer remote transport state object definition
+ */
+struct nameserver_remotenotify_obj {
+	struct nameserver_remotenotify_message *msg[2];
+	struct nameserver_remotenotify_params params;
+	u16 region_id;
+	u16 remote_proc_id;
+	bool cache_enable;
+	struct mutex *local_gate;
+	void *gatemp;
+	struct semaphore *sem_handle; /* Binary semaphore */
+	u16 notify_event_id;
+};
+
+/*
+ *  NameServer remote transport state object definition
+ */
+struct nameserver_remotenotify_object {
+	int (*get)(void *,
+		const char *instance_name, const char *name,
+		void *value, u32 value_len, void *reserved);
+	void *obj; /* Implementation specific object */
+};
+
+/*
+ *  nameserver_remotenotify state object variable
+ */
+static struct nameserver_remotenotify_module_object
+				nameserver_remotenotify_state = {
+	.is_setup = false,
+	.gate_handle = NULL,
+	.def_cfg.notify_event_id = 1u,
+	.def_inst_params.gatemp = NULL,
+	.def_inst_params.shared_addr = 0x0,
+};
+
+static void _nameserver_remotenotify_callback(u16 proc_id, u16 line_id,
+					u32 event_id, uint *arg, u32 payload);
+
+/*
+ * This will get the default configuration for the  nameserver remote
+ * module. This function can be called by the application to get their
+ * configuration parameter to nameserver_remotenotify_setup filled
+ * in by the nameserver_remotenotify module with the default
+ * parameters. If the user does not wish to make any change in the
+ * default parameters, this API is not required to be called
+ */
+void nameserver_remotenotify_get_config(
+			struct nameserver_remotenotify_config *cfg)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(cfg == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (nameserver_remotenotify_state.is_setup == false)
+		memcpy(cfg, &(nameserver_remotenotify_state.def_cfg),
+			sizeof(struct nameserver_remotenotify_config));
+	else
+		memcpy(cfg, &(nameserver_remotenotify_state.cfg),
+			sizeof(struct nameserver_remotenotify_config));
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_remotenotify_get_config failed!"
+			" retval = 0x%x", retval);
+	}
+	return;
+}
+EXPORT_SYMBOL(nameserver_remotenotify_get_config);
+
+/*
+ * This will setup the nameserver_remotenotify module
+ * This function sets up the nameserver_remotenotify module. This
+ * function must be called before any other instance-level APIs can
+ * be invoked
+ * Module-level configuration needs to be provided to this
+ * function. If the user wishes to change some specific config
+ * parameters, then nameserver_remotenotify_get_config can be called
+ * to get the configuration filled with the default values. After
+ * this, only the required configuration values can be changed. If
+ * the user does not wish to make any change in the default
+ * parameters, the application can simply call
+ * nameserver_remotenotify_setup with NULL parameters. The default
+ * parameters would get automatically used
+ */
+int nameserver_remotenotify_setup(struct nameserver_remotenotify_config *cfg)
+{
+	struct nameserver_remotenotify_config tmp_cfg;
+	s32 retval = 0;
+	struct mutex *lock = NULL;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of refCount variable.
+	*/
+	atomic_cmpmask_and_set(&nameserver_remotenotify_state.ref_count,
+				NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+				NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&nameserver_remotenotify_state.ref_count)
+				!= NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	if (cfg == NULL) {
+		nameserver_remotenotify_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	/* Create a default gate handle for local module protection */
+	lock = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (lock == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+	mutex_init(lock);
+	nameserver_remotenotify_state.gate_handle = lock;
+
+	memcpy(&nameserver_remotenotify_state.cfg, cfg,
+		sizeof(struct nameserver_remotenotify_config));
+	memset(&nameserver_remotenotify_state.nsr_handles, 0,
+		(sizeof(void *) * MULTIPROC_MAXPROCESSORS));
+	nameserver_remotenotify_state.is_setup = true;
+	return 0;
+
+exit:
+	printk(KERN_ERR "nameserver_remotenotify_setup failed! retval = 0x%x",
+		retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_remotenotify_setup);
+
+/*
+ * This will destroy the nameserver_remotenotify module.
+ * Once this function is called, other nameserver_remotenotify
+ * module APIs, except for the nameserver_remotenotify_get_config
+ * API  cannot be called anymore.
+ */
+int nameserver_remotenotify_destroy(void)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(nameserver_remotenotify_state.ref_count),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (!(atomic_dec_return(&nameserver_remotenotify_state.ref_count)
+			== NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0))) {
+		retval = 1;
+		goto exit;
+	}
+
+	kfree(nameserver_remotenotify_state.gate_handle);
+
+	nameserver_remotenotify_state.is_setup = false;
+	return 0;
+
+exit:
+	printk(KERN_ERR "nameserver_remotenotify_destroy failed! retval = 0x%x",
+		retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_remotenotify_destroy);
+
+/* This will get the current configuration values */
+void nameserver_remotenotify_params_init(
+				struct nameserver_remotenotify_params *params)
+{
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(nameserver_remotenotify_state.ref_count),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		printk(KERN_ERR "nameserver_remotenotify_params_init failed: "
+			"Module is not initialized!\n");
+		return;
+	}
+
+	if (WARN_ON(unlikely(params == NULL))) {
+		printk(KERN_ERR "nameserver_remotenotify_params_init failed: "
+			"Argument of type(nameserver_remotenotify_params *) "
+			"is NULL!\n");
+		return;
+	}
+
+	memcpy(params, &(nameserver_remotenotify_state.def_inst_params),
+		sizeof(struct nameserver_remotenotify_params));
+
+}
+EXPORT_SYMBOL(nameserver_remotenotify_params_init);
+
+/* This will be called when a notify event is received */
+static void _nameserver_remotenotify_callback(u16 proc_id, u16 line_id,
+					u32 event_id, uint *arg, u32 payload)
+{
+	struct nameserver_remotenotify_obj *handle = NULL;
+	u16  offset = 0;
+	void *nshandle = NULL;
+	u32 value_len;
+	int *key;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(nameserver_remotenotify_state.ref_count),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(arg == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	handle = (struct nameserver_remotenotify_obj *)arg;
+	if ((multiproc_self() > proc_id))
+		offset = 1;
+
+#if 0
+	if (handle->cache_enable) {
+		/* write back shared memory that was modified */
+		Cache_wbInv(handle->msg[0],
+			sizeof(struct nameserver_remotenotify_message) << 1,
+			Cache_Type_ALL, TRUE);
+	}
+#endif
+
+	if (handle->msg[1 - offset]->request != true)
+		goto signal_response;
+
+	/* This is a request */
+	value_len = handle->msg[1 - offset]->value_len;
+	nshandle = nameserver_get_handle((const char *)
+				handle->msg[1 - offset]->instance_name);
+	if (nshandle != NULL) {
+		/* Search for the NameServer entry */
+		if (value_len == sizeof(u32)) {
+			retval = nameserver_get_local_uint32(nshandle,
+					(const char *) handle->msg[1 - offset]->
+					name, &handle->msg[1 - offset]->value);
+		} else {
+			retval = nameserver_get_local(nshandle,
+					(const char *) handle->msg[1 - offset]->
+					name,
+					&handle->msg[1 - offset]->value_buf,
+					&value_len);
+		}
+	}
+	BUG_ON(retval != 0 && retval != -ENOENT);
+
+	key = gatemp_enter(handle->gatemp);
+	if (retval == 0) {
+		handle->msg[1 - offset]->request_status = true;
+		handle->msg[1 - offset]->value_len = value_len;
+	}
+	/* Send a response back */
+	handle->msg[1 - offset]->response = true;
+	handle->msg[1 - offset]->request = false;
+
+#if 0
+	if (handle->cache_enable) {
+		/* write back shared memory that was modified */
+		Cache_wbInv(handle->msg[1 - offset],
+			sizeof(struct nameserver_remotenotify_message),
+			Cache_Type_ALL, TRUE);
+	}
+#endif
+	/* now we can leave the gate */
+	gatemp_leave(handle->gatemp, key);
+
+	/*
+	*  The NotifyDriver handle must exists at this point,
+	*  otherwise the notify_sendEvent should have failed
+	*/
+	retval = notify_send_event(handle->remote_proc_id, 0,
+			(handle->notify_event_id  | (NOTIFY_SYSTEMKEY << 16)),
+			0xCBC7, false);
+
+signal_response:
+	if (handle->msg[offset]->response == true)
+		up(handle->sem_handle);
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_remotenotify_callback failed! "
+			"status = 0x%x\n", retval);
+	}
+	return;
+}
+
+/* This will get a remote name value pair */
+int nameserver_remotenotify_get(void *rhandle, const char *instance_name,
+				const char *name, void *value, u32 *value_len,
+				void *reserved)
+{
+	struct nameserver_remotenotify_object *handle = NULL;
+	struct nameserver_remotenotify_obj *obj = NULL;
+	s32 offset = 0;
+	s32 len;
+	int *key;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(nameserver_remotenotify_state.ref_count),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(rhandle == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(instance_name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(name == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(value == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(value_len == 0))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((*value_len == 0) || \
+		(*value_len > NAMESERVERREMOTENOTIFY_MAXVALUEBUFLEN)))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	handle = (struct nameserver_remotenotify_object *)rhandle;
+	obj = (struct nameserver_remotenotify_obj *)handle->obj;
+	if (multiproc_self() > obj->remote_proc_id)
+		offset = 1;
+
+#if 0
+	if (obj->cache_enable) {
+		/* write back shared memory that was modified */
+		Cache_wbInv(obj->msg[offset],
+			sizeof(struct nameserver_remotenotify_message),
+			Cache_Type_ALL, TRUE);
+	}
+#endif
+	/* Allow only one request to be procesed at a time */
+	retval = mutex_lock_interruptible(obj->local_gate);
+	if (retval)
+		goto exit;
+
+	key = gatemp_enter(obj->gatemp);
+	/* This is a request message */
+	obj->msg[offset]->request = 1;
+	obj->msg[offset]->response = 0;
+	obj->msg[offset]->request_status = 0;
+	obj->msg[offset]->value_len = *value_len;
+	len = strlen(instance_name) + 1; /* Take termination null char */
+	if (len >= 32) {
+		retval = -EINVAL;
+		goto inval_len_error;
+	}
+	strncpy((char *)obj->msg[offset]->instance_name, instance_name, len);
+	len = strlen(name) + 1;
+	if (len >= 32) {
+		retval = -EINVAL;
+		goto inval_len_error;
+	}
+	strncpy((char *)obj->msg[offset]->name, name, len);
+
+	/* Send the notification to remote processor */
+	retval = notify_send_event(obj->remote_proc_id, 0,
+			(obj->notify_event_id  | (NOTIFY_SYSTEMKEY << 16)),
+			0x8307, /* Payload */
+			false); /* Not sending a payload */
+	if (retval < 0) {
+		/* Undo previous operations */
+		obj->msg[offset]->request = 0;
+		obj->msg[offset]->value_len = 0;
+		goto notify_error;
+	}
+	gatemp_leave(obj->gatemp, key);
+
+	/* Pend on the semaphore */
+	retval = down_interruptible(obj->sem_handle);
+	if (retval)
+		goto exit;
+
+	key = gatemp_enter(obj->gatemp);
+
+	if (obj->cache_enable) {
+#if 0
+		/* write back shared memory that was modified */
+		Cache_wbInv(obj->msg[offset],
+			sizeof(struct nameserver_remotenotify_message),
+			Cache_Type_ALL, TRUE);
+#endif
+	}
+	if (obj->msg[offset]->request_status != true) {
+		retval = -ENOENT;
+		goto request_error;
+	}
+
+	if (obj->msg[offset]->value_len == sizeof(u32))
+		memcpy((void *)value, (void *) &(obj->msg[offset]->value),
+			sizeof(u32));
+	else
+		memcpy((void *)value, (void *)&(obj->msg[offset]->value_buf),
+			obj->msg[offset]->value_len);
+	*value_len = obj->msg[offset]->value_len;
+
+	obj->msg[offset]->request_status = false;
+	retval = 0;
+
+inval_len_error:
+notify_error:
+request_error:
+	obj->msg[offset]->request = 0;
+	obj->msg[offset]->response = 0;
+	gatemp_leave(obj->gatemp, key);
+exit:
+	/* un-block so that subsequent requests can be honored */
+	mutex_unlock(obj->local_gate);
+
+	if (retval < 0)
+		printk(KERN_ERR "nameserver_remotenotify_get failed! "
+			"status = 0x%x", retval);
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_remotenotify_get);
+
+/* This will setup the nameserver remote module */
+void *nameserver_remotenotify_create(u16 remote_proc_id,
+			const struct nameserver_remotenotify_params *params)
+{
+	struct nameserver_remotenotify_object *handle = NULL;
+	struct nameserver_remotenotify_obj *obj = NULL;
+	u32 offset = 0;
+	s32 retval = 0;
+	s32 retval1 = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(nameserver_remotenotify_state.ref_count),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((remote_proc_id == multiproc_self()) &&
+			(remote_proc_id >= multiproc_get_num_processors())))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params->shared_addr == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	obj = kzalloc(sizeof(struct nameserver_remotenotify_obj), GFP_KERNEL);
+	handle = kmalloc(sizeof(struct nameserver_remotenotify_object),
+								GFP_KERNEL);
+	if (obj == NULL || handle == NULL) {
+		retval = -ENOMEM;
+		goto mem_error;
+	}
+
+	handle->get = (void *)&nameserver_remotenotify_get;
+	handle->obj = (void *)obj;
+	obj->local_gate = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (obj->local_gate == NULL) {
+		retval = -ENOMEM;
+		goto mem_error;
+	}
+
+	obj->remote_proc_id = remote_proc_id;
+	if (multiproc_self() > remote_proc_id)
+		offset = 1;
+
+	obj->region_id = sharedregion_get_id(params->shared_addr);
+	if (((u32) params->shared_addr % sharedregion_get_cache_line_size(
+		obj->region_id)) != 0) {
+		retval = -EFAULT;
+		goto notify_error;
+	}
+
+	obj->msg[0] = (struct nameserver_remotenotify_message *)
+				(params->shared_addr);
+	obj->msg[1] = (struct nameserver_remotenotify_message *)
+				((u32)obj->msg[0] +
+				sizeof(struct nameserver_remotenotify_message));
+	obj->gatemp = params->gatemp;
+	obj->remote_proc_id = remote_proc_id;
+	obj->notify_event_id = \
+			nameserver_remotenotify_state.cfg.notify_event_id;
+	/* Clear out self shared structures */
+	memset(obj->msg[offset], 0,
+			sizeof(struct nameserver_remotenotify_message));
+	memcpy((void *)&obj->params, (void *)params,
+				sizeof(struct nameserver_remotenotify_params));
+
+	/* determine cacheability of the object from the regionId */
+	obj->cache_enable = sharedregion_is_cache_enabled(obj->region_id);
+	if (obj->cache_enable) {
+#if 0
+		/* write back shared memory that was modified */
+		Cache_wbInv(obj->msg[offset],
+			sizeof(struct nameserver_remotenotify_message),
+			Cache_Type_ALL, TRUE);
+#endif
+	}
+
+	retval = notify_register_event_single(remote_proc_id,
+					0, /* TBD: Interrupt line id */
+					(obj->notify_event_id | \
+						(NOTIFY_SYSTEMKEY << 16)),
+					_nameserver_remotenotify_callback,
+					(void *)obj);
+	if (retval < 0)
+		goto notify_error;
+
+	retval = nameserver_register_remote_driver((void *)handle,
+							remote_proc_id);
+	obj->sem_handle = kzalloc(sizeof(struct semaphore), GFP_KERNEL);
+	if (obj->sem_handle == NULL) {
+		retval = -ENOMEM;
+		goto sem_alloc_error;
+	}
+
+	sema_init(obj->sem_handle, 0);
+	/* its is at the end since its init state = unlocked? */
+	mutex_init(obj->local_gate);
+	return (void *)handle;
+
+sem_alloc_error:
+	nameserver_unregister_remote_driver(remote_proc_id);
+	/* Do we want to check the staus ? */
+	retval1 = notify_unregister_event_single(obj->remote_proc_id, 0,
+			(obj->notify_event_id | (NOTIFY_SYSTEMKEY << 16)));
+
+notify_error:
+	kfree(obj->local_gate);
+
+mem_error:
+	kfree(obj);
+	kfree(handle);
+
+exit:
+	printk(KERN_ERR "nameserver_remotenotify_create failed! "
+		"status = 0x%x\n", retval);
+	return NULL;
+}
+EXPORT_SYMBOL(nameserver_remotenotify_create);
+
+/* This will delete the nameserver remote transport instance */
+int nameserver_remotenotify_delete(void **rhandle)
+{
+	struct nameserver_remotenotify_object *handle = NULL;
+	struct nameserver_remotenotify_obj *obj = NULL;
+	s32 retval = 0;
+	s32 retval1 = 0;
+	struct mutex *gate = NULL;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(nameserver_remotenotify_state.ref_count),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((rhandle == NULL) || (*rhandle == NULL)))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	handle = (struct nameserver_remotenotify_object *)(*rhandle);
+	obj = (struct nameserver_remotenotify_obj *)handle->obj;
+	if (obj == NULL) {
+		retval = -EINVAL;
+		goto free_handle;
+	}
+
+	gate = obj->local_gate;
+	retval = mutex_lock_interruptible(gate);
+	if (retval)
+		goto free_handle;
+
+	kfree(obj->sem_handle);
+	obj->sem_handle = NULL;
+
+	retval1 = nameserver_unregister_remote_driver(obj->remote_proc_id);
+	/* Do we have to bug_on/warn_on oops here intead of exit ?*/
+	if (retval1 < 0 && retval >= 0)
+		retval = retval1;
+
+	/* Unregister the event from Notify */
+	retval1 = notify_unregister_event_single(obj->remote_proc_id, 0,
+			(obj->notify_event_id | (NOTIFY_SYSTEMKEY << 16)));
+	if (retval1 < 0 && retval >= 0)
+		retval = retval1;
+	kfree(obj);
+	mutex_unlock(gate);
+	kfree(gate);
+
+free_handle:
+	kfree(handle);
+	*rhandle = NULL;
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "nameserver_remotenotify_delete failed! "
+			"status = 0x%x\n", retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(nameserver_remotenotify_delete);
+
+/* This will give shared memory requirements for the
+ * nameserver remote transport instance */
+uint nameserver_remotenotify_shared_mem_req(const
+			struct nameserver_remotenotify_params *params)
+{
+	uint total_size;
+
+	/* params is not used- to remove warning. */
+	(void)params;
+
+	/* Two Message structs are required. One for sending request and
+	 * another one for sending response. */
+	if (multiproc_get_num_processors() > 1)
+		total_size = \
+			(2 * sizeof(struct nameserver_remotenotify_message));
+
+	return total_size;
+}
+EXPORT_SYMBOL(nameserver_remotenotify_shared_mem_req);
+
+int nameserver_remotenotify_attach(u16 remote_proc_id, void *shared_addr)
+{
+	struct nameserver_remotenotify_params nsr_params;
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(nameserver_remotenotify_state.ref_count),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(shared_addr == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(gatemp_get_default_remote() == NULL))) {
+		retval = -1;
+		goto exit;
+	}
+
+	/* Use default GateMP */
+	nameserver_remotenotify_params_init(&nsr_params);
+	nsr_params.gatemp = gatemp_get_default_remote();
+	nsr_params.shared_addr = shared_addr;
+
+	/* create only if notify driver has been created to remote proc */
+	if (!notify_is_registered(remote_proc_id, 0)) {
+		retval = -1;
+		goto exit;
+	}
+
+	nameserver_remotenotify_state.nsr_handles[remote_proc_id] =
+		nameserver_remotenotify_create(remote_proc_id, &nsr_params);
+	if (nameserver_remotenotify_state.nsr_handles[remote_proc_id] == NULL) {
+			retval = -1;
+			goto exit;
+	}
+	return 0;
+
+exit:
+	printk(KERN_ERR "nameserver_remotenotify_attach failed! status = 0x%x",
+		retval);
+	return retval;
+}
+
+void *_nameserver_remotenotify_get_handle(u16 remote_proc_id)
+{
+	void *handle = NULL;
+
+	if (remote_proc_id <= multiproc_get_num_processors()) {
+		handle = \
+		nameserver_remotenotify_state.nsr_handles[remote_proc_id];
+	}
+
+	return handle;
+};
+
+
+int nameserver_remotenotify_detach(u16 remote_proc_id)
+{
+	void *handle = NULL;
+	int retval = 0;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(nameserver_remotenotify_state.ref_count),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(0),
+			NAMESERVERREMOTENOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	handle = _nameserver_remotenotify_get_handle(remote_proc_id);
+	if (handle == NULL) {
+		retval = -1;
+		goto exit;
+	}
+
+	nameserver_remotenotify_delete(&handle);
+	nameserver_remotenotify_state.nsr_handles[remote_proc_id] = NULL;
+	return 0;
+
+exit:
+	printk(KERN_ERR "nameserver_remotenotify_detach failed! status = 0x%x",
+		retval);
+	return retval;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/platform.c b/drivers/dsp/syslink/multicore_ipc/platform.c
new file mode 100644
index 000000000000..e58b7ddb9944
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/platform.c
@@ -0,0 +1,1877 @@
+/*
+ *  platform.c
+ *
+ *  Implementation of platform initialization logic for Syslink IPC.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+/* Standard header files */
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+/* SysLink device specific headers */
+#include "../procmgr/proc4430/proc4430.h"
+
+/* Ipu Power Management Header (ipu_pm) */
+#include "../ipu_pm/ipu_pm.h"
+/* Module level headers */
+#include <multiproc.h>
+#include <platform.h>
+#include <gatemp.h>
+#include <gatepeterson.h>
+#include <gatehwspinlock.h>
+#include <sharedregion.h>
+#include <listmp.h>
+#include <_listmp.h>
+#include <heap.h>
+#include <heapbufmp.h>
+#include <heapmemmp.h>
+#include <messageq.h>
+#include <transportshm.h>
+#include <notify.h>
+#include <ipc.h>
+
+#include <notify_ducatidriver.h>
+#include <nameserver.h>
+#include <nameserver_remote.h>
+#include <nameserver_remotenotify.h>
+#include <procmgr.h>
+
+#include <platform_mem.h>
+
+
+/** ============================================================================
+ *  Macros.
+ *  ============================================================================
+ */
+#define RESETVECTOR_SYMBOL          "_Ipc_ResetVector"
+
+/** ============================================================================
+ *  Application specific configuration, please change these value according to
+ *  your application's need.
+ *  ============================================================================
+ */
+/*! @brief Start of IPC shared memory */
+#define SHAREDMEMORY_PHY_BASEADDR	CONFIG_DUCATI_BASEIMAGE_PHYS_ADDR
+#define SHAREDMEMORY_PHY_BASESIZE	0x00100000
+
+/*! @brief Start of IPC shared memory for SysM3 */
+#define SHAREDMEMORY_PHY_BASEADDR_SYSM3	SHAREDMEMORY_PHY_BASEADDR
+#define SHAREDMEMORY_PHY_BASESIZE_SYSM3	0x00054000
+
+/*! @brief Start of IPC shared memory AppM3 */
+#define SHAREDMEMORY_PHY_BASEADDR_APPM3 (SHAREDMEMORY_PHY_BASEADDR + 0x54000)
+#define SHAREDMEMORY_PHY_BASESIZE_APPM3 0x000AC000
+
+/*! @brief Start of IPC SHM for SysM3 */
+#define SHAREDMEMORY_SLV_VRT_BASEADDR_SYSM3	0xA0000000
+#define SHAREDMEMORY_SLV_VRT_BASESIZE_SYSM3	0x00054000
+
+/*! @brief Start of IPC SHM for AppM3 */
+#define SHAREDMEMORY_SLV_VRT_BASEADDR_APPM3	0xA0054000
+#define SHAREDMEMORY_SLV_VRT_BASESIZE_APPM3	0x000AC000
+
+/*! @brief Start of Code memory for SysM3 */
+#define SHAREDMEMORY_SLV_VRT_CODE0_BASEADDR	0x00000000
+#define SHAREDMEMORY_SLV_VRT_CODE0_BASESIZE	0x00200000
+
+/*! @brief Start of Code section for SysM3 */
+#define SHAREDMEMORY_PHY_CODE0_BASEADDR (SHAREDMEMORY_PHY_BASEADDR + 0x100000)
+#define SHAREDMEMORY_PHY_CODE0_BASESIZE		0x00200000
+
+/*! @brief Start of Code memory for SysM3 */
+#define SHAREDMEMORY_SLV_VRT_CODE1_BASEADDR	0x00800000
+#define SHAREDMEMORY_SLV_VRT_CODE1_BASESIZE	0x00200000
+
+/*! @brief Start of Code section for SysM3 */
+#define SHAREDMEMORY_PHY_CODE1_BASEADDR (SHAREDMEMORY_PHY_CODE0_BASEADDR + \
+					SHAREDMEMORY_SLV_VRT_CODE1_BASEADDR)
+#define SHAREDMEMORY_PHY_CODE1_BASESIZE		0x00200000
+
+/*! @brief Start of Const section for SysM3 */
+#define SHAREDMEMORY_PHY_CONST0_BASEADDR (SHAREDMEMORY_PHY_CODE0_BASEADDR + \
+						0x1000000)
+#define SHAREDMEMORY_PHY_CONST0_BASESIZE	0x00100000
+
+/*! @brief Start of Const section for SysM3 */
+#define SHAREDMEMORY_SLV_VRT_CONST0_BASEADDR	0x80000000
+#define SHAREDMEMORY_SLV_VRT_CONST0_BASESIZE	0x00100000
+
+/*! @brief Start of Const section for AppM3 */
+#define SHAREDMEMORY_PHY_CONST1_BASEADDR (SHAREDMEMORY_PHY_CONST0_BASEADDR + \
+					SHAREDMEMORY_SLV_VRT_CONST0_BASESIZE)
+#define SHAREDMEMORY_PHY_CONST1_BASESIZE	0x00100000
+
+/*! @brief Start of Const section for AppM3 */
+#define SHAREDMEMORY_SLV_VRT_CONST1_BASEADDR	0x80100000
+#define SHAREDMEMORY_SLV_VRT_CONST1_BASESIZE	0x00100000
+
+/*! @brief Start of SW DMM shared memory */
+#define SHAREDMEMORY_SWDMM_PHY_BASEADDR (SHAREDMEMORY_PHY_BASEADDR + 0x2400000)
+#define SHAREDMEMORY_SWDMM_PHY_BASESIZE	0x00C00000
+
+/*! @brief Start of SW DMM SHM for Ducati */
+#define SHAREDMEMORY_SWDMM_SLV_VRT_BASEADDR	0x81300000
+#define SHAREDMEMORY_SWDMM_SLV_VRT_BASESIZE	0x00C00000
+
+#define USE_NEW_PROCMGR		0
+
+/** ============================================================================
+ *  Struct & Enums.
+ *  ============================================================================
+ */
+
+/* Struct for reading platform specific gate peterson configuration values */
+struct platform_gaterpeterson_params {
+	u32 shared_mem_addr;	/* Shared memory address */
+	u32 shared_mem_size;	/* Shared memory size */
+	u32 remote_proc_id;	/* Remote processor identifier */
+};
+
+struct platform_notify_ducatidrv_params {
+	u32 shared_mem_addr;	/* Shared memory address */
+	u32 shared_mem_size;	/* Shared memory size */
+	u16 remote_proc_id;	/* Remote processor identifier */
+};
+
+struct platform_nameserver_remotenotify_params {
+	u32 shared_mem_addr;	/* Shared memory address */
+	u32 shared_mem_size;	/* Shared memory size */
+	u32 notify_event_no;	/* Notify Event number to used */
+};
+
+struct platform_heapbuf_params {
+	u32 shared_mem_addr;	/* Shared memory address */
+	u32 shared_mem_size;	/* Shared memory size */
+	u32 shared_buf_addr;	/* Shared memory address */
+	u32 shared_buf_size;	/* Shared memory size */
+	u32 num_blocks;
+	u32 block_size;
+};
+
+struct platform_transportshm_params {
+	u32 shared_mem_addr;	/* Shared memory address */
+	u32 shared_mem_size;	/* Shared memory size */
+	u32 notify_event_no;	/* Notify Event number */
+};
+
+/** ============================================================================
+ *  Application specific configuration, please change these value according to
+ *  your application's need.
+ *  ============================================================================
+ */
+/*
+ * Structure defining config parameters for overall System.
+ */
+struct platform_config {
+	struct multiproc_config			multiproc_config;
+	/* multiproc_config parameter */
+
+	struct gatemp_config			gatemp_config;
+	/* gatemp_config parameter */
+
+	struct gatepeterson_config		gatepeterson_config;
+	/* gatepeterson_config parameter */
+
+	struct gatehwspinlock_config		gatehwspinlock_config;
+	/* gatehwspinlock parameter */
+
+	struct sharedregion_config		sharedregion_config;
+	/* sharedregion_config parameter */
+
+	struct messageq_config			messageq_config;
+	/* messageq_config parameter */
+
+	struct notify_config			notify_config;
+	/* notify config parameter */
+	struct ipu_pm_config			ipu_pm_config;
+	/* ipu_pm config parameter */
+
+	struct proc_mgr_config			proc_mgr_config;
+	/* processor manager config parameter */
+
+	struct heapbufmp_config			heapbufmp_config;
+	/* heapbufmp_config parameter */
+
+	struct heapmemmp_config			heapmemmp_config;
+	/* heapmemmp_config parameter */
+#if 0
+
+	struct heapmultibuf_config		heapmultibuf_config;
+	/* heapmultibuf_config parameter */
+#endif
+	struct listmp_config			listmp_config;
+	/* listmp_config parameter */
+
+	struct transportshm_config		transportshm_config;
+	/* transportshm_config parameter */
+#if 0
+	struct ringio_config			ringio_config;
+	/* ringio_config parameter */
+
+	struct ringiotransportshm_config	ringiotransportshm_config;
+	/* ringiotransportshm_config parameter */
+#endif
+	struct notify_ducatidrv_config		notify_ducatidrv_config;
+	/* notify_ducatidrv_config parameter */
+
+	struct nameserver_remotenotify_config	nameserver_remotenotify_config;
+	/* nameserver_remotenotify_config parameter */
+#if 0
+	struct clientnotifymgr_config		clinotifymgr_config_params;
+	/* clientnotifymgr_config parameter */
+
+	struct frameqbufmgr_config		frameqbufmgr_config_params;
+	/* frameqbufmgr_config parameter */
+
+	struct frameq_config			frameq_config_params;
+	/* frameq_config parameter */
+#endif
+};
+
+
+/* struct embedded into slave binary */
+struct platform_slave_config {
+	u32 cache_line_size;
+	u32 br_offset;
+	u32 sr0_memory_setup;
+	u32 setup_messageq;
+	u32 setup_notify;
+	u32 setup_ipu_pm;
+	u32 proc_sync;
+	u32 num_srs;
+};
+
+struct platform_proc_config_params {
+	u32 use_notify;
+	u32 use_messageq;
+	u32 use_heapbuf;
+	u32 use_frameq;
+	u32 use_ring_io;
+	u32 use_listmp;
+	u32 use_nameserver;
+};
+
+/* shared region configuration */
+struct platform_slave_sr_config {
+	u32 entry_base;
+	u32 entry_len;
+	u32 owner_proc_id;
+	u32 id;
+	u32 create_heap;
+	u32 cache_line_size;
+};
+
+/* Shared region configuration information for host side. */
+struct platform_host_sr_config {
+	u16 ref_count;
+};
+
+/* structure for platform instance */
+struct platform_object {
+	void				*pm_handle;
+	/* handle to the proc_mgr instance used */
+	void				*phandle;
+	/* handle to the processor instance used */
+	struct platform_slave_config	slave_config;
+	/* slave embedded config */
+	struct platform_slave_sr_config	*slave_sr_config;
+	/* shared region details from slave */
+};
+
+
+/* structure for platform instance */
+struct platform_module_state {
+	bool multiproc_init_flag;
+	/* multiproc initialize flag */
+	bool gatemp_init_flag;
+	/* gatemp initialize flag */
+	bool gatepeterson_init_flag;
+	/* gatepeterson initialize flag */
+	bool gatehwspinlock_init_flag;
+	/* gatehwspinlock initialize flag */
+	bool sharedregion_init_flag;
+	/* sharedregion initialize flag */
+	bool listmp_init_flag;
+	/* listmp initialize flag */
+	bool messageq_init_flag;
+	/* messageq initialize flag */
+	bool ringio_init_flag;
+	/* ringio initialize flag */
+	bool notify_init_flag;
+	/* notify initialize flag */
+	bool ipu_pm_init_flag;
+	/* ipu_pm initialize flag */
+	bool proc_mgr_init_flag;
+	/* processor manager initialize flag */
+	bool heapbufmp_init_flag;
+	/* heapbufmp initialize flag */
+	bool heapmemmp_init_flag;
+	/* heapmemmp initialize flag */
+	bool heapmultibuf_init_flag;
+	/* heapbufmp initialize flag */
+	bool nameserver_init_flag;
+	/* nameserver initialize flag */
+	bool transportshm_init_flag;
+	/* transportshm initialize flag */
+	bool ringiotransportshm_init_flag;
+	/* ringiotransportshm initialize flag */
+	bool notify_ducatidrv_init_flag;
+	/* notify_ducatidrv initialize flag */
+	bool nameserver_remotenotify_init_flag;
+	/* nameserverremotenotify initialize flag */
+	bool clientnotifymgr_init_flag;
+	/* clientnotifymgr initialize flag */
+	bool frameqbufmgr_init_flag;
+	/* frameqbufmgr initialize flag */
+	bool frameq_init_flag;
+	/* frameq initialize flag */
+	bool platform_init_flag;
+	/* flag to indicate platform initialization status */
+	bool platform_mem_init_flag;
+	/* Platform memory manager initialize flag */
+};
+
+
+/* =============================================================================
+ * GLOBALS
+ * =============================================================================
+ */
+static struct platform_object platform_objects[MULTIPROC_MAXPROCESSORS];
+static struct platform_module_state platform_module_state;
+static struct platform_module_state *platform_module = &platform_module_state;
+static u16 platform_num_srs_unmapped;
+static struct platform_host_sr_config *platform_host_sr_config;
+
+/* ============================================================================
+ *  Forward declarations of internal functions.
+ * ============================================================================
+ */
+static int _platform_setup(void);
+static int _platform_destroy(void);
+
+/* function to read slave memory */
+static int
+_platform_read_slave_memory(u16 proc_id,
+			    u32 addr,
+			    void *value,
+			    u32 *num_bytes);
+
+/* function to write slave memory */
+static int
+_platform_write_slave_memory(u16 proc_id,
+			     u32 addr,
+			     void *value,
+			     u32 *num_bytes);
+
+
+/** ============================================================================
+ *  Macros and types
+ *  ============================================================================
+ */
+/*!
+ *  @brief  Number of slave memory entries for OMAP4430.
+ */
+#define NUM_MEM_ENTRIES			6
+
+/*!
+ *  @brief  Position of reset vector memory region in the memEntries array.
+ */
+#define RESET_VECTOR_ENTRY_ID		0
+
+
+/** ============================================================================
+ *  Globals
+ *  ============================================================================
+ */
+/*!
+ *  @brief  Array of memory entries for OMAP4430
+ */
+static struct proc4430_mem_entry mem_entries[NUM_MEM_ENTRIES] = {
+	{
+		"DUCATI_CODE_SYSM3",	/* NAME	 : Name of the memory region */
+		SHAREDMEMORY_PHY_CODE0_BASEADDR,
+		/* PHYSADDR	 : Physical address */
+		SHAREDMEMORY_SLV_VRT_CODE0_BASEADDR,
+		/* SLAVEVIRTADDR  : Slave virtual address */
+		(u32) -1u,
+		/* MASTERVIRTADDR : Master virtual address (if known) */
+		SHAREDMEMORY_SLV_VRT_CODE0_BASESIZE,
+		/* SIZE		 : Size of the memory region */
+		true,		/* SHARE : Shared access memory? */
+	},
+	{
+		"DUCATI_CODE_APPM3",	/* NAME	 : Name of the memory region */
+		SHAREDMEMORY_PHY_CODE1_BASEADDR,
+		/* PHYSADDR : Physical address */
+		SHAREDMEMORY_SLV_VRT_CODE1_BASEADDR,
+		/* SLAVEVIRTADDR  : Slave virtual address */
+		(u32) -1u,
+		/* MASTERVIRTADDR : Master virtual address (if known) */
+		SHAREDMEMORY_SLV_VRT_CODE1_BASESIZE,
+		/* SIZE		 : Size of the memory region */
+		true,		/* SHARE : Shared access memory? */
+	},
+	{
+		"DUCATI_SHM_SYSM3",	/* NAME	 : Name of the memory region */
+		SHAREDMEMORY_PHY_BASEADDR_SYSM3,
+		/* PHYSADDR	 : Physical address */
+		SHAREDMEMORY_SLV_VRT_BASEADDR_SYSM3,
+		/* SLAVEVIRTADDR  : Slave virtual address */
+		(u32) -1u,
+		/* MASTERVIRTADDR : Master virtual address (if known) */
+		SHAREDMEMORY_SLV_VRT_BASESIZE_SYSM3,
+		/* SIZE		 : Size of the memory region */
+		true,		/* SHARE : Shared access memory? */
+	},
+	{
+		"DUCATI_SHM_APPM3",	/* NAME	 : Name of the memory region */
+		SHAREDMEMORY_PHY_BASEADDR_APPM3,
+		/* PHYSADDR : Physical address */
+		SHAREDMEMORY_SLV_VRT_BASEADDR_APPM3,
+		/* SLAVEVIRTADDR  : Slave virtual address */
+		(u32) -1u,
+		/* MASTERVIRTADDR : Master virtual address (if known) */
+		SHAREDMEMORY_SLV_VRT_BASESIZE_APPM3,
+		/* SIZE		 : Size of the memory region */
+		true,		/* SHARE : Shared access memory? */
+	},
+	{
+		"DUCATI_CONST_SYSM3",	/* NAME	 : Name of the memory region */
+		SHAREDMEMORY_PHY_CONST0_BASEADDR,
+		/* PHYSADDR	     : Physical address */
+		SHAREDMEMORY_SLV_VRT_CONST0_BASEADDR,
+		/* SLAVEVIRTADDR  : Slave virtual address */
+		(u32) -1u,
+		/* MASTERVIRTADDR : Master virtual address (if known) */
+		SHAREDMEMORY_SLV_VRT_CONST0_BASESIZE,
+		/* SIZE		: Size of the memory region */
+		true,		/* SHARE : Shared access memory? */
+	},
+	{
+		"DUCATI_CONST_APPM3",	/* NAME	 : Name of the memory region */
+		SHAREDMEMORY_PHY_CONST1_BASEADDR,
+		/* PHYSADDR	     : Physical address */
+		SHAREDMEMORY_SLV_VRT_CONST1_BASEADDR,
+		/* SLAVEVIRTADDR  : Slave virtual address */
+		(u32) -1u,
+		/* MASTERVIRTADDR : Master virtual address (if known) */
+		SHAREDMEMORY_SLV_VRT_CONST1_BASESIZE,
+		/* SIZE		: Size of the memory region */
+		true,		/* SHARE : Shared access memory? */
+	}
+
+};
+
+
+
+
+
+/* =============================================================================
+ * APIS
+ * =============================================================================
+ */
+
+/*
+ * ======== platform_get_config =======
+ *  function to get the default values for confiurations.
+ */
+void
+platform_get_config(struct platform_config *config)
+{
+	int status = PLATFORM_S_SUCCESS;
+
+	BUG_ON(config == NULL);
+	if (config == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* get the gatepeterson default config */
+	multiproc_get_config(&config->multiproc_config);
+
+	/* get the gatemp default config */
+	gatemp_get_config(&config->gatemp_config);
+
+	/* get the gatepeterson default config */
+	gatepeterson_get_config(&config->gatepeterson_config);
+
+	/* get the gatehwspinlock default config */
+	gatehwspinlock_get_config(&config->gatehwspinlock_config);
+
+	/* get the sharedregion default config */
+	sharedregion_get_config(&config->sharedregion_config);
+
+	/* get the messageq default config */
+	messageq_get_config(&config->messageq_config);
+
+	/* get the notify default config */
+	notify_get_config(&config->notify_config);
+	/* get the ipu_pm default config */
+	ipu_pm_get_config(&config->ipu_pm_config);
+
+	/* get the procmgr default config */
+	proc_mgr_get_config(&config->proc_mgr_config);
+
+	/* get the heapbufmpfault config */
+	heapbufmp_get_config(&config->heapbufmp_config);
+
+	/* get the heapmemmpfault config */
+	heapmemmp_get_config(&config->heapmemmp_config);
+#if 0
+	/* get the heapmultibuf default config */
+	heapmultibuf_get_config(&config->heapmultibuf_config
+#endif
+	/* get the listmp default config */
+	listmp_get_config(&config->listmp_config);
+
+	/* get the transportshm default config */
+	transportshm_get_config(&config->transportshm_config);
+	/* get the notifyshmdriver default config */
+	notify_ducatidrv_get_config(&config->notify_ducatidrv_config);
+
+	/* get the nameserver_remotenotify default config */
+	nameserver_remotenotify_get_config(&config->
+				nameserver_remotenotify_config);
+#if 0
+	/* get the clientnotifymgr default config */
+	clientnotifymgr_get_config(&config->clinotifymgr_config_params);
+
+	/*  get the frameqbufmgr default config */
+	frameqbufmgr_get_config(&config->frameqbufmgr_config_params);
+	/*  get the frameq default config */
+	frameq_get_config(&config->frameqcfg_params);
+
+	/*  get the ringio default config */
+	ringio_get_config(&config->ringio_config);
+
+	/*  get the ringiotransportshm default config */
+	ringiotransportshm_get_config(&config->ringiotransportshm_config);
+#endif
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "platform_get_config failed! status = 0x%x\n",
+								status);
+	return;
+}
+
+
+/*
+ * ======== platform_override_config ======
+ * Function to override the default configuration values.
+ *
+ */
+int
+platform_override_config(struct platform_config *config)
+{
+	int status = PLATFORM_S_SUCCESS;
+
+	BUG_ON(config == NULL);
+
+	if (config == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* Override the multiproc_config default config */
+	config->multiproc_config.num_processors = 4;
+	config->multiproc_config.id = 3;
+	strcpy(config->multiproc_config.name_list[0], "Tesla");
+	strcpy(config->multiproc_config.name_list[1], "AppM3");
+	strcpy(config->multiproc_config.name_list[2], "SysM3");
+	strcpy(config->multiproc_config.name_list[3], "MPU");
+
+	/* Override the gate,p default config */
+	config->gatemp_config.num_resources = 64;
+
+	/* Override the Sharedregion default config */
+	config->sharedregion_config.cache_line_size = 128;
+
+	/* Override the LISTMP default config */
+
+	/* Override the MESSAGEQ default config */
+	config->messageq_config.num_heaps = 2;
+
+	/* Override the NOTIFY default config */
+
+	/* Override the PROCMGR default config */
+
+	/* Override the HeapBuf default config */
+
+	/* Override the LISTMPSHAREDMEMORY default config */
+
+	/* Override the MESSAGEQTRANSPORTSHM default config */
+
+	/* Override the NOTIFYSHMDRIVER default config */
+
+	/* Override the NAMESERVERREMOTENOTIFY default config */
+
+	/* Override the  ClientNotifyMgr default config */
+	/* Override the  FrameQBufMgr default config */
+
+	/* Override the FrameQ default config */
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "platform_override_config failed! status "
+				"= 0x%x\n", status);
+	return status;
+}
+
+/*
+ * ======= platform_setup ========
+ *       function to setup platform.
+ *              TBD: logic would change completely in the final system.
+ */
+int
+platform_setup(void)
+{
+	int status = PLATFORM_S_SUCCESS;
+	struct platform_config _config;
+	struct platform_config *config;
+	struct platform_mem_map_info m_info;
+
+	platform_get_config(&_config);
+	config = &_config;
+
+	/* Initialize PlatformMem */
+	status = platform_mem_setup();
+	if (status < 0) {
+		printk(KERN_ERR "platform_setup : platform_mem_setup "
+			"failed [0x%x]\n", status);
+	} else {
+		printk(KERN_ERR "platform_mem_setup : status [0x%x]\n" ,
+			status);
+		platform_module->platform_mem_init_flag = true;
+	}
+
+	platform_override_config(config);
+
+	status = multiproc_setup(&(config->multiproc_config));
+	if (status < 0) {
+		printk(KERN_ERR "platform_setup : multiproc_setup "
+			"failed [0x%x]\n", status);
+	} else {
+		printk(KERN_ERR "platform_setup : status [0x%x]\n", status);
+		platform_module->multiproc_init_flag = true;
+	}
+
+	/* Initialize ProcMgr */
+	if (status >= 0) {
+		status = proc_mgr_setup(&(config->proc_mgr_config));
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : proc_mgr_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "proc_mgr_setup : status [0x%x]\n",
+				status);
+			platform_module->proc_mgr_init_flag = true;
+		}
+	}
+
+	/* Initialize SharedRegion */
+	if (status >= 0) {
+		status = sharedregion_setup(&config->sharedregion_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : sharedregion_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "sharedregion_setup : status [0x%x]\n",
+				status);
+			platform_module->sharedregion_init_flag = true;
+		}
+	}
+
+	/* Initialize Notify DucatiDriver */
+	if (status >= 0) {
+		status = notify_ducatidrv_setup(&config->
+						notify_ducatidrv_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : "
+				"notify_ducatidrv_setup failed [0x%x]\n",
+				status);
+		} else {
+			printk(KERN_ERR "notify_ducatidrv_setup : "
+				"status [0x%x]\n", status);
+			platform_module->notify_ducatidrv_init_flag = true;
+		}
+	}
+
+	/* Initialize Notify */
+	if (status >= 0) {
+		status = notify_setup(&config->notify_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : notify_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "notify_setup : status [0x%x]\n",
+				status);
+			platform_module->notify_init_flag = true;
+		}
+	}
+
+	/* Initialize ipu_pm */
+	if (status >= 0) {
+		status = ipu_pm_setup(&config->ipu_pm_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : ipu_pm_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "ipu_pm_setup : status [0x%x]\n",
+				status);
+			platform_module->ipu_pm_init_flag = true;
+		}
+	}
+	/* Initialize NameServer */
+	if (status >= 0) {
+		status = nameserver_setup();
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : nameserver_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "nameserver_setup : status [0x%x]\n",
+				status);
+			platform_module->nameserver_init_flag = true;
+		}
+	}
+
+	/* Initialize GateMP */
+	if (status >= 0) {
+		status = gatemp_setup(&config->gatemp_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : gatemp_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "gatemp_setup : status [0x%x]\n",
+				status);
+			platform_module->gatemp_init_flag = true;
+		}
+	}
+
+	/* Initialize GatePeterson */
+	if (status >= 0) {
+		status = gatepeterson_setup(&config->gatepeterson_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : gatepeterson_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "gatepeterson_setup : status [0x%x]\n",
+				status);
+			platform_module->gatepeterson_init_flag = true;
+		}
+	}
+
+	/* Initialize GateHWSpinlock */
+	if (status >= 0) {
+		m_info.src  = 0x4A0F6000;
+		m_info.size = 0x1000;
+		m_info.is_cached = false;
+		status = platform_mem_map(&m_info);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : platform_mem_map "
+				"failed [0x%x]\n", status);
+		} else {
+			config->gatehwspinlock_config.num_locks = 64;
+			config->gatehwspinlock_config.base_addr = \
+							m_info.dst + 0x800;
+			status = gatehwspinlock_setup(&config->
+							gatehwspinlock_config);
+			if (status < 0) {
+				printk(KERN_ERR "platform_setup : "
+					"gatehwspinlock_setup failed [0x%x]\n",
+					status);
+			} else
+				platform_module->gatehwspinlock_init_flag =
+									true;
+		}
+	}
+
+	/* Initialize MessageQ */
+	if (status >= 0) {
+		status = messageq_setup(&config->messageq_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : messageq_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "messageq_setup : status [0x%x]\n",
+				status);
+			platform_module->messageq_init_flag = true;
+		}
+	}
+#if 0
+	/* Initialize RingIO */
+	if (status >= 0) {
+		status = ringio_setup(&config->ringio_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : ringio_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "ringio_setup : status [0x%x]\n",
+				status);
+			platform_module->ringio_init_flag = true;
+		}
+	}
+
+	/* Initialize RingIOTransportShm */
+	if (status >= 0) {
+		status = ringiotransportshm_setup(&config->
+						ringiotransportshm_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : "
+				"ringiotransportshm_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "ringiotransportshm_setup : status "
+				"[0x%x]\n", status);
+			platform_module->ringiotransportshm_init_flag = true;
+		}
+	}
+#endif
+	/* Initialize HeapBufMP */
+	if (status >= 0) {
+		status = heapbufmp_setup(&config->heapbufmp_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : heapbufmp_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "heapbufmp_setup : status [0x%x]\n",
+				status);
+			platform_module->heapbufmp_init_flag = true;
+		}
+	}
+
+	/* Initialize HeapMemMP */
+	if (status >= 0) {
+		status = heapmemmp_setup(&config->heapmemmp_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : heapmemmp_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "heapmemmp_setup : status [0x%x]\n",
+				status);
+			platform_module->heapmemmp_init_flag = true;
+		}
+	}
+#if 0
+	/* Initialize HeapMultiBuf */
+	if (status >= 0) {
+		status = heapmultibuf_setup(&config->heapmultibuf_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : heapmultibuf_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "heapmultibuf_setup : status [0x%x]\n",
+				status);
+			platform_module->heapmultibuf_init_flag = true;
+		}
+	}
+#endif
+	/* Initialize ListMP */
+	if (status >= 0) {
+		status = listmp_setup(
+				&config->listmp_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : "
+				"listmp_setup failed [0x%x]\n",
+				status);
+		} else {
+			printk(KERN_ERR "listmp_setup : "
+				"status [0x%x]\n", status);
+			platform_module->listmp_init_flag = true;
+		}
+	}
+
+	/* Initialize TransportShm */
+	if (status >= 0) {
+		status = transportshm_setup(
+				 &config->transportshm_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : "
+				"transportshm_setup failed [0x%x]\n",
+				status);
+		} else {
+			printk(KERN_ERR "transportshm_setup : "
+				"status [0x%x]\n", status);
+			platform_module->transportshm_init_flag = true;
+		}
+	}
+
+	/* Initialize NameServerRemoteNotify */
+	if (status >= 0) {
+		status = nameserver_remotenotify_setup(
+				 &config->nameserver_remotenotify_config);
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : "
+				"nameserver_remotenotify_setup failed "
+				"[0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "nameserver_remotenotify_setup : "
+				"status [0x%x]\n", status);
+			platform_module->nameserver_remotenotify_init_flag =
+									true;
+		}
+	}
+#if 0
+	/* Get the ClientNotifyMgr default config */
+	if (status >= 0) {
+		status = ClientNotifyMgr_setup(&config->cliNotifyMgrCfgParams);
+		if (status < 0)
+			GT_setFailureReason(curTrace,
+					 GT_4CLASS,
+					 "Platform_setup",
+					 status,
+					 "ClientNotifyMgr_setup failed!");
+		else
+			Platform_module->clientNotifyMgrInitFlag = true;
+	}
+
+	/* Get the FrameQBufMgr default config */
+	if (status >= 0) {
+		status = FrameQBufMgr_setup(&config->frameQBufMgrCfgParams);
+		if (status < 0)
+			GT_setFailureReason(curTrace,
+					 GT_4CLASS,
+					 "Platform_setup",
+					 status,
+					 "FrameQBufMgr_setup failed!");
+		else
+			Platform_module->frameQBufMgrInitFlag = true;
+	}
+	/* Get the FrameQ default config */
+	if (status >= 0) {
+		status = FrameQ_setup(&config->frameQCfgParams);
+		if (status < 0)
+			GT_setFailureReason(curTrace,
+				 GT_4CLASS,
+				 "Platform_setup",
+				 status,
+				 "FrameQ_setup failed!");
+	else
+		Platform_module->frameQInitFlag = true;
+	}
+#endif
+
+	if (status >= 0) {
+		memset(platform_objects, 0,
+			(sizeof(struct platform_object) * \
+				multiproc_get_num_processors()));
+	}
+
+
+	/* Initialize Platform */
+	if (status >= 0) {
+		status = _platform_setup();
+		if (status < 0) {
+			printk(KERN_ERR "platform_setup : _platform_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "_platform_setup : status [0x%x]\n",
+				status);
+			platform_module->platform_init_flag = true;
+		}
+
+	}
+
+	return status;
+}
+
+
+/*
+ * =========== platform_destroy ==========
+ *  Function to destroy the System.
+ */
+int
+platform_destroy(void)
+{
+	int status = PLATFORM_S_SUCCESS;
+	struct platform_mem_unmap_info u_info;
+
+	/* Finalize Platform module*/
+	if (platform_module->platform_init_flag == true) {
+		status = _platform_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : _platform_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->platform_init_flag = false;
+		}
+	}
+#if 0
+	/* Finalize Frame module */
+	if (Platform_module->frameQInitFlag == true) {
+		status = FrameQ_destroy();
+		if (status < 0)
+			GT_setFailureReason(curTrace,
+					 GT_4CLASS,
+					 "Platform_destroy",
+					 status,
+					 "FrameQ_destroy failed!");
+		else
+			Platform_module->frameQInitFlag = false;
+	}
+
+	/* Finalize FrameQBufMgr module */
+	if (Platform_module->frameQBufMgrInitFlag == true) {
+		status = FrameQBufMgr_destroy();
+		if (status < 0)
+			GT_setFailureReason(curTrace,
+					 GT_4CLASS,
+					 "Platform_destroy",
+					 status,
+					 "FrameQBufMgr_destroy failed!");
+		else
+			Platform_module->frameQBufMgrInitFlag = false;
+	}
+
+	/* Finalize ClientNotifyMgr module */
+	if (Platform_module->clientNotifyMgrInitFlag == true) {
+		status = ClientNotifyMgr_destroy();
+		if (status < 0)
+			GT_setFailureReason(curTrace,
+					 GT_4CLASS,
+					 "Platform_destroy",
+					 status,
+					 "ClientNotifyMgr_destroy failed!");
+		else
+			Platform_module->clientNotifyMgrInitFlag = false;
+	}
+#endif
+	/* Finalize NameServerRemoteNotify module */
+	if (platform_module->nameserver_remotenotify_init_flag == true) {
+		status = nameserver_remotenotify_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"nameserver_remotenotify_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->nameserver_remotenotify_init_flag \
+				= false;
+		}
+	}
+
+	/* Finalize TransportShm module */
+	if (platform_module->transportshm_init_flag == true) {
+		status = transportshm_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"transportshm_destroy failed "
+				"[0x%x]\n", status);
+		} else {
+			platform_module->transportshm_init_flag = \
+				false;
+		}
+	}
+
+	/* Finalize ListMP module */
+	if (platform_module->listmp_init_flag == true) {
+		status = listmp_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"listmp_destroy failed [0x%x]\n",
+				status);
+		} else {
+			platform_module->listmp_init_flag = \
+				false;
+		}
+	}
+#if 0
+	/* Finalize HeapMultiBuf module */
+	if (platform_module->heapmultibuf_init_flag == true) {
+		status = heapmultibuf_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"heapmultibuf_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->heapmultibuf_init_flag = false;
+		}
+	}
+#endif
+	/* Finalize HeapBufMP module */
+	if (platform_module->heapbufmp_init_flag == true) {
+		status = heapbufmp_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : heapbufmp_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->heapbufmp_init_flag = false;
+		}
+	}
+
+	/* Finalize HeapMemMP module */
+	if (platform_module->heapmemmp_init_flag == true) {
+		status = heapmemmp_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : heapmemmp_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->heapmemmp_init_flag = false;
+		}
+	}
+
+	/* Finalize MessageQ module */
+	if (platform_module->messageq_init_flag == true) {
+		status = messageq_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : messageq_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->messageq_init_flag = false;
+		}
+	}
+#if 0
+	/* Finalize RingIO module */
+	if (platform_module->ringio_init_flag == true) {
+		status = ringio_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : ringio_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->ringio_init_flag = false;
+		}
+	}
+
+
+	/* Finalize RingIOTransportShm module */
+	if (platform_module->ringiotransportshm_init_flag == true) {
+		status = ringiotransportshm_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+					"ringiotransportshm_destroy "
+					"failed [0x%x]\n", status);
+		} else {
+			platform_module->ringiotransportshm_init_flag = false;
+		}
+	}
+#endif
+	/* Finalize GatePeterson module */
+	if (platform_module->gatepeterson_init_flag == true) {
+		status = gatepeterson_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"gatepeterson_destroy failed [0x%x]\n", status);
+		} else {
+			platform_module->gatepeterson_init_flag = false;
+		}
+	}
+
+	/* Finalize GateHWSpinlock module */
+	if (platform_module->gatehwspinlock_init_flag == true) {
+		status = gatehwspinlock_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"gatehwspinlock_destroy failed "
+				"[0x%x]\n", status);
+		} else {
+			platform_module->gatehwspinlock_init_flag = false;
+		}
+
+		u_info.addr = 0x4A0F6000;
+		u_info.size = 0x1000;
+		u_info.is_cached = false;
+		status = platform_mem_unmap(&u_info);
+		if (status < 0)
+			printk(KERN_ERR "platform_destroy : platform_mem_unmap"
+						" failed [0x%x]\n", status);
+	}
+
+	/* Finalize GateMP module */
+	if (platform_module->gatemp_init_flag == true) {
+		status = gatemp_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"gatemp_destroy failed [0x%x]\n", status);
+		} else {
+			platform_module->gatemp_init_flag = false;
+		}
+	}
+
+	/* Finalize NameServer module */
+	if (platform_module->nameserver_init_flag == true) {
+		status = nameserver_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : nameserver_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->nameserver_init_flag = false;
+		}
+	}
+	/* Finalize ipu_pm module */
+	if (platform_module->ipu_pm_init_flag == true) {
+		status = ipu_pm_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : ipu_pm_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->ipu_pm_init_flag = false;
+		}
+	}
+
+	/* Finalize Notify Ducati Driver module */
+	if (platform_module->notify_ducatidrv_init_flag == true) {
+		status = notify_ducatidrv_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"notify_ducatidrv_destroy failed [0x%x]\n",
+				status);
+		} else {
+			platform_module->notify_ducatidrv_init_flag = false;
+		}
+	}
+
+	/* Finalize Notify module */
+	if (platform_module->notify_init_flag == true) {
+		status = notify_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : notify_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->notify_init_flag = false;
+		}
+	}
+
+	/* Finalize SharedRegion module */
+	if (platform_module->sharedregion_init_flag == true) {
+		status = sharedregion_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"sharedregion_destroy failed [0x%x]\n", status);
+		} else {
+			platform_module->sharedregion_init_flag = false;
+		}
+	}
+
+	/* Finalize ProcMgr module */
+	if (platform_module->proc_mgr_init_flag == true) {
+		status = proc_mgr_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : proc_mgr_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->proc_mgr_init_flag = false;
+		}
+	}
+
+	/* Finalize MultiProc module */
+	if (platform_module->multiproc_init_flag == true) {
+		status = multiproc_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : multiproc_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			platform_module->multiproc_init_flag = false;
+		}
+	}
+
+	/* Finalize PlatformMem module */
+	if (platform_module->platform_mem_init_flag == true) {
+		status = platform_mem_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "platform_destroy : "
+				"platform_mem_destroy failed [0x%x]\n", status);
+		} else {
+			platform_module->platform_mem_init_flag = false;
+		}
+	}
+
+	if (status >= 0)
+		memset(platform_objects,
+			0,
+			(sizeof(struct platform_object) *
+				multiproc_get_num_processors()));
+
+	return status;
+}
+
+/*
+ * ======== platform_setup ========
+ *  Purpose:
+ *  TBD: logic would change completely in the final system.
+ */
+s32 _platform_setup(void)
+{
+
+	s32 status = 0;
+	struct proc4430_config proc_config;
+	struct proc_mgr_params params;
+	struct proc4430_params proc_params;
+	u16 proc_id;
+	struct platform_object *handle;
+	void *proc_mgr_handle;
+	void *proc_mgr_proc_handle;
+
+	/* Create the SysM3 ProcMgr object */
+	proc4430_get_config(&proc_config);
+	status = proc4430_setup(&proc_config);
+	if (status < 0)
+		goto exit;
+
+	/* Get MultiProc ID by name. */
+	proc_id = multiproc_get_id("SysM3");
+	handle = &platform_objects[proc_id];
+
+	/* Create an instance of the Processor object for OMAP4430 */
+	proc4430_params_init(NULL, &proc_params);
+	/* TODO: SysLink-38 has these in individual Proc Objects */
+	proc_params.num_mem_entries = NUM_MEM_ENTRIES;
+	proc_params.mem_entries = mem_entries;
+	proc_params.reset_vector_mem_entry = RESET_VECTOR_ENTRY_ID;
+	proc_mgr_proc_handle = proc4430_create(proc_id, &proc_params);
+	if (proc_mgr_proc_handle == NULL) {
+		status = PLATFORM_E_FAIL;
+		goto proc_create_fail;
+	}
+
+	/* Initialize parameters */
+	proc_mgr_params_init(NULL, &params);
+	params.proc_handle = proc_mgr_proc_handle;
+	proc_mgr_handle = proc_mgr_create(proc_id, &params);
+	if (proc_mgr_handle == NULL) {
+		status = PLATFORM_E_FAIL;
+		goto proc_mgr_create_fail;
+	}
+
+	/* SysM3 and AppM3 use the same handle */
+	handle->phandle = proc_mgr_proc_handle;
+	handle->pm_handle = proc_mgr_handle;
+
+	proc_mgr_handle = NULL;
+	proc_mgr_proc_handle = NULL;
+
+
+	/* Create the AppM3 ProcMgr object */
+	/* Get MultiProc ID by name. */
+	proc_id = multiproc_get_id("AppM3");
+	handle = &platform_objects[proc_id];
+
+	/* Create an instance of the Processor object for OMAP4430 */
+	proc4430_params_init(NULL, &proc_params);
+	proc_params.num_mem_entries = NUM_MEM_ENTRIES;
+	proc_params.mem_entries = mem_entries;
+	proc_params.reset_vector_mem_entry = RESET_VECTOR_ENTRY_ID;
+	proc_mgr_proc_handle = proc4430_create(proc_id, &proc_params);
+	if (proc_mgr_proc_handle == NULL) {
+		status = PLATFORM_E_FAIL;
+		goto proc_create_fail;
+	}
+
+	/* Initialize parameters */
+	proc_mgr_params_init(NULL, &params);
+	params.proc_handle = proc_mgr_proc_handle;
+	proc_mgr_handle = proc_mgr_create(proc_id, &params);
+	if (proc_mgr_handle == NULL) {
+		status = PLATFORM_E_FAIL;
+		goto proc_mgr_create_fail;
+	}
+
+	handle->phandle = proc_mgr_proc_handle;
+	handle->pm_handle = proc_mgr_handle;
+
+	/* TODO: See if we need to do proc_mgr_attach on both SysM3 & AppM3
+	 * to set the memory maps before hand. Or fix ProcMgr_open &
+	 * ProcMgr_attach from the userspace */
+	return status;
+
+proc_create_fail:
+proc_mgr_create_fail:
+	/* Clean up created objects */
+	_platform_destroy();
+exit:
+	return status;
+}
+
+
+/*
+ * ======== platform_destroy ========
+ *  Purpose:
+ *  Function to finalize the platform.
+ */
+s32 _platform_destroy(void)
+{
+	s32 status = 0;
+	struct platform_object *handle;
+	int i;
+
+	for (i = 0; i < MULTIPROC_MAXPROCESSORS; i++) {
+		handle = &platform_objects[i];
+
+		/* Delete the Processor instances */
+		if (handle->phandle != NULL) {
+			status = proc4430_delete(&handle->phandle);
+			WARN_ON(status < 0);
+		}
+
+		if (handle->pm_handle != NULL) {
+			status = proc_mgr_delete(&handle->pm_handle);
+			WARN_ON(status < 0);
+		}
+	}
+
+	status = proc4430_destroy();
+	WARN_ON(status < 0);
+
+	return status;
+}
+
+
+/*
+ * ======== platform_load_callback ========
+ *  Purpose:
+ *  Function called by proc_mgr when slave is in loaded state.
+ */
+int platform_load_callback(u16 proc_id, void *arg)
+{
+	int status = PLATFORM_S_SUCCESS;
+	struct platform_object *handle;
+	u32 start;
+	u32 num_bytes;
+	struct sharedregion_entry entry;
+	u32 m_addr = 0;
+	/*struct proc_mgr_addr_info ai;*/
+	struct ipc_params ipc_params;
+	int i;
+	void *pm_handle;
+
+	handle = &platform_objects[proc_id];
+	pm_handle = handle->pm_handle;
+
+	/* TODO: hack */
+	start = (u32)arg;	/* start address passed in as argument */
+
+	/* Read the slave config */
+	num_bytes = sizeof(struct platform_slave_config);
+	status = _platform_read_slave_memory(proc_id,
+					start,
+					&handle->slave_config,
+					&num_bytes);
+	if (status < 0) {
+		status = PLATFORM_E_FAIL;
+		goto exit;
+	}
+
+	if (platform_host_sr_config == NULL)
+		platform_host_sr_config = kmalloc(sizeof(struct
+				platform_host_sr_config) * handle->
+					slave_config.num_srs, GFP_KERNEL);
+
+	if (platform_host_sr_config == NULL) {
+		status = -ENOMEM;
+		goto alloced_host_sr_config_exit;
+	}
+
+	if (handle->slave_config.num_srs > 0) {
+		num_bytes = handle->slave_config.num_srs * sizeof(struct
+						platform_slave_sr_config);
+		handle->slave_sr_config = kmalloc(num_bytes, GFP_KERNEL);
+		if (handle->slave_sr_config == NULL) {
+			status = -ENOMEM;
+			goto exit;
+		} else {
+			status = _platform_read_slave_memory(
+					proc_id,
+					start + sizeof(struct
+						platform_slave_config),
+					handle->slave_sr_config,
+					&num_bytes);
+			if (status < 0) {
+				status = PLATFORM_E_FAIL;
+				goto alloced_slave_sr_config_exit;
+			}
+		}
+	}
+
+	if (status >= 0) {
+		ipc_params.setup_messageq = handle->slave_config.setup_messageq;
+		ipc_params.setup_notify = handle->slave_config.setup_notify;
+		ipc_params.setup_ipu_pm = handle->slave_config.setup_ipu_pm;
+		ipc_params.proc_sync = handle->slave_config.proc_sync;
+		status = ipc_create(proc_id, &ipc_params);
+		if (status < 0) {
+			status = PLATFORM_E_FAIL;
+			goto alloced_slave_sr_config_exit;
+		}
+	}
+
+	/* Setup the shared memory for region with owner == host */
+	/* TODO: May need to replace proc_mgr_map with platform_mem_map */
+	for (i = 0; i < handle->slave_config.num_srs; i++) {
+		status = sharedregion_get_entry(i, &entry);
+		if (status < 0) {
+			status = PLATFORM_E_FAIL;
+			goto alloced_slave_sr_config_exit;
+		}
+		BUG_ON(!((entry.is_valid == false)
+			|| ((entry.is_valid == true)
+				&& (entry.len == (handle->
+					slave_sr_config[i].entry_len)))));
+
+		platform_host_sr_config[i].ref_count++;
+
+		/* Add the entry only if previously not added */
+		if (entry.is_valid == false) {
+			/* Translate the slave address to master */
+
+			/* This SharedRegion is already pre-mapped. So, no need
+			 * to do a new mapping. Just need to translate to get
+			 * the master virtual address */
+			status = proc_mgr_translate_addr(pm_handle,
+				(void **)&m_addr,
+				PROC_MGR_ADDRTYPE_MASTERKNLVIRT,
+				(void *)handle->slave_sr_config[i].entry_base,
+				PROC_MGR_ADDRTYPE_SLAVEVIRT);
+			if (status < 0) {
+				status = PLATFORM_E_FAIL;
+				goto alloced_slave_sr_config_exit;
+			}
+
+			/* TODO: compatibility with new procmgr */
+			/* No need to map this to Slave. Slave is pre-mapped */
+			/*status = proc_mgr_map(pm_handle,
+				handle->slave_sr_config[i].entry_base,
+				handle->slave_sr_config[i].entry_len,
+				&ai.addr[PROC_MGR_ADDRTYPE_MASTERKNLVIRT],
+				&handle->slave_sr_config[i].entry_len,
+				PROC_MGR_MAPTYPE_VIRT);
+			if (status < 0) {
+				status = PLATFORM_E_FAIL;
+				goto alloced_slave_sr_config_exit;
+			}
+
+			memset((u32 *)ai.addr[PROC_MGR_ADDRTYPE_MASTERKNLVIRT],
+				0, handle->slave_sr_config[i].entry_len); */
+			memset((u32 *)m_addr, 0,
+				handle->slave_sr_config[i].entry_len);
+			memset(&entry, 0, sizeof(struct sharedregion_entry));
+			/*entry.base = (void *)ai.
+					addr[PROC_MGR_ADDRTYPE_MASTERKNLVIRT];*/
+			entry.base = (void *) m_addr;
+			entry.len = handle->slave_sr_config[i].entry_len;
+			entry.owner_proc_id = handle->slave_sr_config[i].
+							owner_proc_id;
+			entry.is_valid = true;
+			entry.cache_line_size = handle->slave_sr_config[i].
+							cache_line_size;
+			entry.create_heap = handle->slave_sr_config[i].
+								create_heap;
+			_sharedregion_set_entry(handle->slave_sr_config[i].id,
+						&entry);
+		}
+	}
+
+	/* Read sr0_memory_setup */
+	num_bytes = sizeof(struct platform_slave_config);
+	handle->slave_config.sr0_memory_setup = 1;
+	status = _platform_write_slave_memory(proc_id,
+						start,
+						&handle->slave_config,
+						&num_bytes);
+	if (status < 0) {
+		status = PLATFORM_E_FAIL;
+		goto alloced_slave_sr_config_exit;
+	}
+
+	status = ipc_start();
+	if (status < 0) {
+		status = PLATFORM_E_FAIL;
+		goto alloced_slave_sr_config_exit;
+	}
+
+	return 0;
+
+alloced_slave_sr_config_exit:
+	kfree(handle->slave_sr_config);
+
+alloced_host_sr_config_exit:
+	kfree(platform_host_sr_config);
+exit:
+	if (status < 0)
+		printk(KERN_ERR "platform_load_callback failed, status [0x%x]\n",
+			status);
+
+	return status;
+}
+EXPORT_SYMBOL(platform_load_callback);
+
+
+/*
+ * ======== platform_start_callback ========
+ *  Purpose:
+ *  Function called by proc_mgr when slave is in started state.
+ *  FIXME: logic would change completely in the final system.
+ */
+int platform_start_callback(u16 proc_id, void *arg)
+{
+	int status = PLATFORM_S_SUCCESS;
+
+	do {
+		status = ipc_attach(proc_id);
+		msleep(1);
+	} while (status < 0);
+
+	if (status < 0)
+		printk(KERN_ERR "platform_load_callback failed, status [0x%x]\n",
+			status);
+
+	return status;
+}
+EXPORT_SYMBOL(platform_start_callback);
+/* FIXME: since application has to call this API for now */
+
+
+/*
+ * ======== platform_stop_callback ========
+ *  Purpose:
+ *  Function called by proc_mgr when slave is in stopped state.
+ *  FIXME: logic would change completely in the final system.
+ */
+int platform_stop_callback(u16 proc_id, void *arg)
+{
+	int status = PLATFORM_S_SUCCESS;
+	u32 i;
+	u32 m_addr;
+	struct platform_object *handle;
+	void *pm_handle;
+
+	handle = (struct platform_object *)&platform_objects[proc_id];
+	pm_handle = handle->pm_handle;
+	/* delete the System manager instance here */
+	for (i = 0;
+		((handle->slave_sr_config != NULL) &&
+			(i < handle->slave_config.num_srs));
+		i++) {
+			platform_host_sr_config[i].ref_count--;
+			if (platform_host_sr_config[i].ref_count == 0) {
+				platform_num_srs_unmapped++;
+			/* Translate the slave address to master */
+			/* TODO: backwards compatibility with old procmgr */
+			status = proc_mgr_translate_addr(pm_handle,
+				(void **)&m_addr,
+				PROC_MGR_ADDRTYPE_MASTERKNLVIRT,
+				(void *)handle->slave_sr_config[i].entry_base,
+				PROC_MGR_ADDRTYPE_SLAVEVIRT);
+			if (status < 0) {
+				status = PLATFORM_E_FAIL;
+				continue;
+			}
+
+			status = proc_mgr_unmap(pm_handle, m_addr);
+		}
+	}
+
+	if (platform_num_srs_unmapped == handle->slave_config.num_srs) {
+		if (handle->slave_sr_config != NULL) {
+			kfree(handle->slave_sr_config);
+			handle->slave_sr_config = NULL;
+		}
+		if (platform_host_sr_config != NULL) {
+			kfree(platform_host_sr_config);
+			platform_host_sr_config = NULL;
+			platform_num_srs_unmapped = 0;
+		}
+	}
+
+	ipc_detach(proc_id);
+
+	ipc_stop();
+
+	return status;
+}
+EXPORT_SYMBOL(platform_stop_callback);
+
+/*  ============================================================================
+ *  Internal functions
+ *  ============================================================================
+ */
+/* Function to read slave memory */
+int
+_platform_read_slave_memory(u16 proc_id,
+			    u32 addr,
+			    void *value,
+			    u32 *num_bytes)
+{
+	int status = 0;
+	bool done = false;
+	struct platform_object *handle;
+	u32 m_addr;
+	void *pm_handle;
+
+	handle = (struct platform_object *)&platform_objects[proc_id];
+	BUG_ON(handle == NULL);
+	if (handle == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	pm_handle = handle->pm_handle;
+	BUG_ON(pm_handle == NULL);
+	if (pm_handle == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* TODO: backwards compatibility with old procmgr */
+	status = proc_mgr_translate_addr(pm_handle,
+					(void **)&m_addr,
+					PROC_MGR_ADDRTYPE_MASTERKNLVIRT,
+					(void *)addr,
+					PROC_MGR_ADDRTYPE_SLAVEVIRT);
+	if (status >= 0) {
+		memcpy(value, (void *) m_addr, *num_bytes);
+		done = true;
+		printk(KERN_ERR "_platform_read_slave_memory successful! "
+			"status = 0x%x, proc_id = %d, addr = 0x%x, "
+			"m_addr = 0x%x, size = 0x%x", status, proc_id, addr,
+			m_addr, *num_bytes);
+	} else {
+		printk(KERN_ERR "_platform_read_slave_memory failed! "
+			"status = 0x%x, proc_id = %d, addr = 0x%x, "
+			"m_addr = 0x%x, size = 0x%x", status, proc_id, addr,
+			m_addr, *num_bytes);
+		status = PLATFORM_E_FAIL;
+		goto exit;
+	}
+
+	/* This code path is not validated for OMAP4, as it does not comply
+	 * with the latest ProcMgr */
+	if (done == false) {
+		/* Map the address */
+		/* TODO: backwards compatibility with old procmgr */
+		status = proc_mgr_map(pm_handle,
+			addr,
+			*num_bytes,
+			&m_addr,
+			num_bytes,
+			PROC_MGR_MAPTYPE_VIRT);
+		if (status < 0) {
+			status = PLATFORM_E_FAIL;
+			goto exit;
+		}
+	}
+
+	if (done == false) {
+		status = proc_mgr_read(pm_handle,
+					addr,
+					num_bytes,
+					value);
+		if (status < 0) {
+			status = PLATFORM_E_FAIL;
+			goto exit;
+		}
+	}
+
+	if (done == false) {
+		/* Unmap the address */
+		/* TODO: backwards compatibility with old procmgr */
+		status = proc_mgr_unmap(pm_handle, m_addr);
+		if (status < 0) {
+			status = PLATFORM_E_FAIL;
+			goto exit;
+		}
+	}
+exit:
+	return status;
+}
+
+
+/* Function to write slave memory */
+int _platform_write_slave_memory(u16 proc_id, u32 addr, void *value,
+					u32 *num_bytes)
+{
+	int status = 0;
+	bool done = false;
+	struct platform_object *handle;
+	u32 m_addr;
+	void *pm_handle = NULL;
+
+	handle = (struct platform_object *)&platform_objects[proc_id];
+	BUG_ON(handle == NULL);
+	if (handle == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	pm_handle = handle->pm_handle;
+	BUG_ON(pm_handle == NULL);
+	if (pm_handle == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* Translate the slave address to master address */
+	/* TODO: backwards compatibility with old procmgr */
+	status = proc_mgr_translate_addr(pm_handle,
+					(void **)&m_addr,
+					PROC_MGR_ADDRTYPE_MASTERKNLVIRT,
+					(void *)addr,
+					PROC_MGR_ADDRTYPE_SLAVEVIRT);
+	if (status >= 0) {
+		memcpy((void *) m_addr, value, *num_bytes);
+		done = true;
+		printk(KERN_ERR "_platform_write_slave_memory successful! "
+			"status = 0x%x, proc_id = %d, addr = 0x%x, "
+			"m_addr = 0x%x, size = 0x%x", status, proc_id, addr,
+			m_addr, *num_bytes);
+	} else {
+		printk(KERN_ERR "_platform_write_slave_memory failed! "
+			"status = 0x%x, proc_id = %d, addr = 0x%x, "
+			"m_addr = 0x%x, size = 0x%x", status, proc_id, addr,
+			m_addr, *num_bytes);
+		status = PLATFORM_E_FAIL;
+		goto exit;
+	}
+
+	/* This code path is not validated for OMAP4, as it does not comply
+	 * with the latest ProcMgr */
+	if (done == false) {
+		/* Map the address */
+		/* TODO: backwards compatibility with old procmgr */
+		status = proc_mgr_map(pm_handle,
+			addr,
+			*num_bytes,
+			&m_addr,
+			num_bytes,
+			PROC_MGR_MAPTYPE_VIRT);
+		if (status < 0) {
+			status = PLATFORM_E_FAIL;
+			goto exit;
+		}
+	}
+
+	if (done == false) {
+		status = proc_mgr_write(pm_handle,
+					addr,
+					num_bytes,
+					value);
+		if (status < 0) {
+			status = PLATFORM_E_FAIL;
+			goto exit;
+		}
+	}
+
+	if (done == false) {
+		/* Map the address */
+		/* TODO: backwards compatibility with old procmgr */
+		status = proc_mgr_unmap(pm_handle, m_addr);
+		if (status < 0) {
+			status = PLATFORM_E_FAIL;
+			goto exit;
+		}
+	}
+
+exit:
+	return status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/platform_mem.c b/drivers/dsp/syslink/multicore_ipc/platform_mem.c
new file mode 100644
index 000000000000..1eaa3cba5e52
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/platform_mem.c
@@ -0,0 +1,325 @@
+/*
+ *  platform_mem.c
+ *
+ * Target memory management interface implementation.
+ *
+ *  This abstracts the Memory management interface in the kernel
+ *  code. Allocation, Freeing-up, copy and address translate are
+ *  supported for the kernel memory management.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Linux specific header files */
+#include <linux/types.h>
+#include <linux/vmalloc.h>
+#include <linux/string.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <platform_mem.h>
+#include <atomic_linux.h>
+
+/* Macro to make a correct module magic number with ref_count */
+#define PLATFORM_MEM_MAKE_MAGICSTAMP(x) ((PLATFORM_MEM_MODULEID << 12u) | (x))
+
+/*
+ *  Structure for containing
+ */
+struct platform_mem_map_table_info {
+	struct list_head mem_entry; /* Pointer to mem_entry entry */
+	u32	physical_address; /* Actual address */
+	u32	knl_virtual_address; /* Mapped address */
+	u32	size; /* Size of the region mapped */
+	u16	ref_count; /* Reference count of mapped entry */
+	bool	is_cached;
+};
+
+/*
+ *  Structure defining state object of system memory manager
+ */
+struct platform_mem_module_object {
+	atomic_t ref_count; /* Reference count */
+	struct list_head map_table; /* Head of map table */
+	struct mutex *gate; /* Pointer to lock */
+};
+
+
+/*
+ *  Object containing state of the platform mem module
+ */
+static struct platform_mem_module_object platform_mem_state;
+
+/*
+ * ======== platform_mem_setup ========
+ *  Purpose:
+ *  This will initialize the platform mem module.
+ */
+int platform_mem_setup(void)
+{
+	s32 retval = 0;
+
+	atomic_cmpmask_and_set(&platform_mem_state.ref_count,
+				PLATFORM_MEM_MAKE_MAGICSTAMP(0),
+				PLATFORM_MEM_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&platform_mem_state.ref_count)
+				!= PLATFORM_MEM_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	/* Create the Gate handle */
+	platform_mem_state.gate =
+			kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (platform_mem_state.gate == NULL) {
+			retval = -ENOMEM;
+		goto gate_create_fail;
+	}
+
+	/* Construct the map table */
+	INIT_LIST_HEAD(&platform_mem_state.map_table);
+	mutex_init(platform_mem_state.gate);
+	goto exit;
+
+gate_create_fail:
+	atomic_set(&platform_mem_state.ref_count,
+			PLATFORM_MEM_MAKE_MAGICSTAMP(0));
+exit:
+	return retval;
+}
+EXPORT_SYMBOL(platform_mem_setup);
+
+/*
+ * ======== platform_mem_destroy ========
+ *  Purpose:
+ *  This will finalize the platform mem module.
+ */
+int platform_mem_destroy(void)
+{
+	s32 retval = 0;
+	struct platform_mem_map_table_info *info = NULL, *temp = NULL;
+
+	if (atomic_cmpmask_and_lt(&(platform_mem_state.ref_count),
+				  PLATFORM_MEM_MAKE_MAGICSTAMP(0),
+				  PLATFORM_MEM_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	if (atomic_dec_return(&platform_mem_state.ref_count)
+			== PLATFORM_MEM_MAKE_MAGICSTAMP(0)) {
+		/* Delete the node in the map table */
+		list_for_each_entry_safe(info, temp,
+						&platform_mem_state.map_table,
+						mem_entry) {
+			iounmap((unsigned int *) info->knl_virtual_address);
+			list_del(&info->mem_entry);
+			kfree(info);
+		}
+		list_del(&platform_mem_state.map_table);
+		/* Delete the gate handle */
+		kfree(platform_mem_state.gate);
+	}
+
+exit:
+	return  retval;
+}
+EXPORT_SYMBOL(platform_mem_destroy);
+
+/*
+ * ======== platform_mem_map ========
+ *  Purpose:
+ *  This will  maps a memory area into virtual space.
+ */
+int platform_mem_map(memory_map_info *map_info)
+{
+	int retval = 0;
+	bool exists = false;
+	struct platform_mem_map_table_info *info = NULL;
+	struct list_head *list_info = NULL;
+
+	if (atomic_cmpmask_and_lt(&(platform_mem_state.ref_count),
+				PLATFORM_MEM_MAKE_MAGICSTAMP(0),
+				PLATFORM_MEM_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(map_info == NULL)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (map_info->src == (u32) NULL) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(platform_mem_state.gate);
+	if (retval)
+		goto exit;
+
+	/* First check if the mapping already exists in the map table */
+	list_for_each(list_info, (struct list_head *)
+		&platform_mem_state.map_table) {
+		if ((((struct platform_mem_map_table_info *)
+			list_info)->physical_address == map_info->src) && \
+			(((struct platform_mem_map_table_info *)
+			list_info)->is_cached == map_info->is_cached)) {
+			exists = true;
+			map_info->dst = ((struct platform_mem_map_table_info *)
+						list_info)->knl_virtual_address;
+			/* Increase the refcount. */
+			((struct platform_mem_map_table_info *)
+				list_info)->ref_count++;
+			break;
+		}
+	}
+	if (exists) {
+		mutex_unlock(platform_mem_state.gate);
+		goto exit;
+	}
+
+	map_info->dst = 0;
+	if (map_info->is_cached == true)
+		map_info->dst = (u32) ioremap((dma_addr_t)
+					(map_info->src), map_info->size);
+	else
+		map_info->dst = (u32) ioremap_nocache((dma_addr_t)
+					(map_info->src), map_info->size);
+	if (map_info->dst == 0) {
+		retval = -EFAULT;
+		goto ioremap_fail;
+	}
+
+	info = kmalloc(sizeof(struct platform_mem_map_table_info), GFP_KERNEL);
+	if (info == NULL) {
+		retval = -ENOMEM;
+		goto ioremap_fail;
+	}
+	/* Populate the info */
+	info->physical_address = map_info->src;
+	info->knl_virtual_address = map_info->dst;
+	info->size = map_info->size;
+	info->ref_count = 1;
+	info->is_cached = map_info->is_cached;
+	/* Put the info into the list */
+	list_add(&info->mem_entry, &platform_mem_state.map_table);
+	mutex_unlock(platform_mem_state.gate);
+	goto exit;
+
+ioremap_fail:
+	mutex_unlock(platform_mem_state.gate);
+exit:
+	return retval;
+}
+EXPORT_SYMBOL(platform_mem_map);
+
+/*
+ * ======== platform_mem_unmap ========
+ *  Purpose:
+ *  This will  unmaps a memory area into virtual space.
+ */
+int platform_mem_unmap(memory_unmap_info *unmap_info)
+{
+	s32 retval = 0;
+	bool found = false;
+	struct platform_mem_map_table_info *info = NULL;
+
+	if (atomic_cmpmask_and_lt(&(platform_mem_state.ref_count),
+			  PLATFORM_MEM_MAKE_MAGICSTAMP(0),
+			  PLATFORM_MEM_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (unmap_info == NULL) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	if (unmap_info->addr == (u32) NULL) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(platform_mem_state.gate);
+	if (retval)
+		goto exit;
+
+	list_for_each_entry(info,
+		(struct list_head *)&platform_mem_state.map_table, mem_entry) {
+		if ((info->knl_virtual_address == unmap_info->addr) && \
+			(info->is_cached == unmap_info->is_cached)) {
+			info->ref_count--;
+			found = true;
+			break;
+		}
+	}
+	if (!found) {
+		mutex_unlock(platform_mem_state.gate);
+		goto exit;
+	}
+
+	if (info->ref_count == 0) {
+		list_del(&info->mem_entry);
+		kfree(info);
+		iounmap((unsigned int *) unmap_info->addr);
+	}
+	mutex_unlock(platform_mem_state.gate);
+
+exit:
+	return retval;
+}
+EXPORT_SYMBOL(platform_mem_unmap);
+
+/*
+ * ======== platform_mem_translate ========
+ *  Purpose:
+ *  This will translate an address.
+ */
+void *platform_mem_translate(void *src_addr, enum memory_xlt_flags flags)
+{
+	void *buf = NULL;
+	struct platform_mem_map_table_info *tinfo  = NULL;
+	u32 frm_addr;
+	u32 to_addr;
+	s32 retval = 0;
+
+	if (atomic_cmpmask_and_lt(&(platform_mem_state.ref_count),
+				PLATFORM_MEM_MAKE_MAGICSTAMP(0),
+				PLATFORM_MEM_MAKE_MAGICSTAMP(1)) == true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+
+	retval = mutex_lock_interruptible(platform_mem_state.gate);
+	if (retval)
+		goto exit;
+
+	/* Traverse to the node in the map table */
+	list_for_each_entry(tinfo, &platform_mem_state.map_table, mem_entry) {
+		frm_addr = (flags == PLATFORM_MEM_XLT_FLAGS_VIRT2PHYS) ?
+			tinfo->knl_virtual_address : tinfo->physical_address;
+		to_addr = (flags == PLATFORM_MEM_XLT_FLAGS_VIRT2PHYS) ?
+			tinfo->physical_address : tinfo->knl_virtual_address;
+		if ((((u32) src_addr) >= frm_addr)
+			&& (((u32) src_addr) < (frm_addr + tinfo->size))) {
+			buf = (void *) (to_addr + ((u32)src_addr - frm_addr));
+			break;
+		}
+	}
+	mutex_unlock(platform_mem_state.gate);
+
+exit:
+	return buf;
+}
+EXPORT_SYMBOL(platform_mem_translate);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/dsp/syslink/multicore_ipc/sharedregion.c b/drivers/dsp/syslink/multicore_ipc/sharedregion.c
new file mode 100644
index 000000000000..843d83ac695c
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/sharedregion.c
@@ -0,0 +1,1606 @@
+/*
+ *  sharedregion.c
+ *
+ *  The SharedRegion module is designed to be used in a
+ *  multi-processor environment where there are memory regions
+ *  that are shared and accessed across different processors
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <syslink/atomic_linux.h>
+
+#include <multiproc.h>
+#include <nameserver.h>
+#include <heapmemmp.h>
+#include <sharedregion.h>
+
+/* Macro to make a correct module magic number with refCount */
+#define SHAREDREGION_MAKE_MAGICSTAMP(x)   ((SHAREDREGION_MODULEID << 16u) | (x))
+
+#define SHAREDREGION_MAX_REGIONS_DEFAULT  4
+
+#define ROUND_UP(a, b)	(((a) + ((b) - 1)) & (~((b) - 1)))
+
+/* Module state object */
+struct sharedregion_module_object {
+	atomic_t ref_count; /* Reference count */
+	struct mutex *local_lock; /* Handle to a gate instance */
+	struct sharedregion_region *regions; /* Pointer to the regions */
+	struct sharedregion_config cfg; /* Current config values */
+	struct sharedregion_config def_cfg; /* Default config values */
+	u32 num_offset_bits;
+	/* no. of bits for the offset for a SRPtr. This value is calculated */
+	u32 offset_mask; /* offset bitmask using for generating a SRPtr */
+};
+
+/* Shared region state object variable with default settings */
+static struct sharedregion_module_object sharedregion_state = {
+	.num_offset_bits = 0,
+	.regions = NULL,
+	.local_lock = NULL,
+	.offset_mask = 0,
+	.def_cfg.num_entries = 4u,
+	.def_cfg.translate = true,
+	.def_cfg.cache_line_size = 128u
+};
+
+/* Pointer to the SharedRegion module state */
+static struct sharedregion_module_object *sharedregion_module = \
+							&sharedregion_state;
+
+/* Checks to make sure overlap does not exists.
+ * Return error if overlap found. */
+static int _sharedregion_check_overlap(void *base, u32 len);
+
+/* Return the number of offsetBits bits */
+static u32 _sharedregion_get_num_offset_bits(void);
+
+/* This will get the sharedregion module configuration */
+int sharedregion_get_config(struct sharedregion_config *config)
+{
+	BUG_ON((config == NULL));
+	if (atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true) {
+		memcpy(config, &sharedregion_module->def_cfg,
+			sizeof(struct sharedregion_config));
+	} else {
+		memcpy(config, &sharedregion_module->cfg,
+			sizeof(struct sharedregion_config));
+	}
+	return 0;
+}
+EXPORT_SYMBOL(sharedregion_get_config);
+
+/* This will get setup the sharedregion module */
+int sharedregion_setup(const struct sharedregion_config *config)
+{
+	struct sharedregion_config tmpcfg;
+	u32 i;
+	s32 retval = 0;
+
+	/* This sets the refCount variable is not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of refCount variable
+	*/
+	atomic_cmpmask_and_set(&sharedregion_module->ref_count,
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&sharedregion_module->ref_count)
+			!= SHAREDREGION_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	if (config == NULL) {
+		sharedregion_get_config(&tmpcfg);
+		config = &tmpcfg;
+	}
+	if (config != NULL) {
+		if (WARN_ON(config->num_entries == 0)) {
+			retval = -EINVAL;
+			goto error;
+		}
+	}
+
+	memcpy(&sharedregion_module->cfg, config,
+		sizeof(struct sharedregion_config));
+	sharedregion_module->cfg.translate = true;
+
+	sharedregion_module->regions = kmalloc(
+					(sizeof(struct sharedregion_region) * \
+					sharedregion_module->cfg.num_entries),
+					GFP_KERNEL);
+	if (sharedregion_module->regions == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		sharedregion_module->regions[i].entry.base = NULL;
+		sharedregion_module->regions[i].entry.len = 0;
+		sharedregion_module->regions[i].entry.owner_proc_id = 0;
+		sharedregion_module->regions[i].entry.is_valid = false;
+		sharedregion_module->regions[i].entry.cache_enable = true;
+		sharedregion_module->regions[i].entry.cache_line_size =
+			sharedregion_module->cfg.cache_line_size;
+		sharedregion_module->regions[i].entry.create_heap = false;
+		sharedregion_module->regions[i].reserved_size = 0;
+		sharedregion_module->regions[i].heap = NULL;
+		sharedregion_module->regions[i].entry.name = NULL;
+	}
+
+	/* set the defaults for region 0  */
+	sharedregion_module->regions[0].entry.create_heap = true;
+	sharedregion_module->regions[0].entry.owner_proc_id = multiproc_self();
+
+	sharedregion_module->num_offset_bits = \
+					_sharedregion_get_num_offset_bits();
+	sharedregion_module->offset_mask =
+		(1 << sharedregion_module->num_offset_bits) - 1;
+
+	sharedregion_module->local_lock = kmalloc(sizeof(struct mutex),
+						GFP_KERNEL);
+	if (sharedregion_module->local_lock == NULL) {
+		retval = -ENOMEM;
+		goto gate_create_fail;
+	}
+	mutex_init(sharedregion_module->local_lock);
+
+	return 0;
+
+gate_create_fail:
+	kfree(sharedregion_module->regions);
+
+error:
+	printk(KERN_ERR "sharedregion_setup failed status:%x\n", retval);
+	sharedregion_destroy();
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_setup);
+
+/* This will get destroy the sharedregion module */
+int sharedregion_destroy(void)
+{
+	s32 retval = 0;
+	void *local_lock = NULL;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (!(atomic_dec_return(&sharedregion_module->ref_count)
+			== SHAREDREGION_MAKE_MAGICSTAMP(0))) {
+		retval = 1;
+		goto error;
+	}
+
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+	kfree(sharedregion_module->regions);
+	memset(&sharedregion_module->cfg, 0,
+		sizeof(struct sharedregion_config));
+	sharedregion_module->num_offset_bits = 0;
+	sharedregion_module->offset_mask = 0;
+	mutex_unlock(sharedregion_module->local_lock);
+
+	kfree(local_lock);
+	return 0;
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_destroy failed status:%x\n",
+			retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_destroy);
+
+/* Creates a heap by owner of region for each SharedRegion.
+ * Function is called by Ipc_start(). Requires that SharedRegion 0
+ * be valid before calling start(). */
+int sharedregion_start(void)
+{
+	int retval = 0;
+	struct sharedregion_region *region = NULL;
+	void *shared_addr = NULL;
+	struct heapmemmp_object *heap_handle = NULL;
+	struct heapmemmp_params params;
+	int i;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if ((sharedregion_module->cfg.num_entries == 0) ||
+		(sharedregion_module->regions[0].entry.is_valid == false)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	/*
+	 *  Loop through shared regions. If an owner of a region is specified
+	 *  and create_heap has been specified for the SharedRegion, then
+	 *  the owner creates a HeapMemMP and the other processors open it.
+	 */
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		region = &(sharedregion_module->regions[i]);
+		if ((region->entry.is_valid)
+			&& (region->entry.owner_proc_id == multiproc_self())
+			&& (region->entry.create_heap)
+			&& (region->heap == NULL)) {
+			/* get the next free address in each region */
+			shared_addr = (void *)((u32) region->entry.base
+						+ region->reserved_size);
+
+			/* Create the HeapMemMP in the region. */
+			heapmemmp_params_init(&params);
+			params.shared_addr = shared_addr;
+			params.shared_buf_size =
+				region->entry.len - region->reserved_size;
+
+			/* Adjust to account for the size of HeapMemMP_Attrs */
+			params.shared_buf_size -=
+				((heapmemmp_shared_mem_req(&params) - \
+					params.shared_buf_size));
+			heap_handle = heapmemmp_create(&params);
+			if (heap_handle == NULL) {
+				retval = -1;
+				break;
+			} else {
+				region->heap = heap_handle;
+			}
+		}
+	}
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_start failed status:%x\n",
+			retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_start);
+
+/* Function to stop the SharedRegion module */
+int sharedregion_stop(void)
+{
+	int retval = 0;
+	int tmp_status = 0;
+	struct sharedregion_region *region = NULL;
+	int i;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON((sharedregion_module->cfg.num_entries == 0)
+		|| (sharedregion_module->regions[0].entry.is_valid == false))) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	/*
+	 *  Loop through shared regions. If an owner of a region is specified
+	 *  and create_heap has been specified for the SharedRegion, then
+	 *  the other processors close it and the owner deletes the HeapMemMP.
+	 */
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		region = &(sharedregion_module->regions[i]);
+		if ((region->entry.is_valid)
+			&& (region->entry.owner_proc_id == multiproc_self())
+			&& (region->entry.create_heap)
+			&& (region->heap != NULL)) {
+			/* Delete heap */
+			tmp_status = heapmemmp_delete((void **)&(region->heap));
+			if ((tmp_status < 0) && (retval >= 0))
+				retval = -1;
+		}
+		memset(region, 0, sizeof(struct sharedregion_region));
+	}
+
+	/* set the defaults for region 0  */
+	sharedregion_module->regions[0].entry.create_heap = true;
+	sharedregion_module->regions[0].entry.owner_proc_id = multiproc_self();
+
+error:
+	if (retval < 0)
+		printk(KERN_ERR "sharedregion_stop failed status:%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_stop);
+
+/* Opens a heap, for non-owner processors, for each SharedRegion. */
+int sharedregion_attach(u16 remote_proc_id)
+{
+	int retval = 0;
+	struct sharedregion_region *region = NULL;
+	void *shared_addr = NULL;
+	int i;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON((remote_proc_id > MULTIPROC_MAXPROCESSORS))) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/*
+	 *  Loop through the regions and open the heap if not owner
+	 */
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		region = &(sharedregion_module->regions[i]);
+		if ((region->entry.is_valid) && \
+			(region->entry.owner_proc_id != multiproc_self()) && \
+			(region->entry.owner_proc_id != \
+			SHAREDREGION_DEFAULTOWNERID) && \
+			(region->entry.create_heap) && (region->heap == NULL)) {
+			/* SharedAddr should match creator's for each region */
+			shared_addr = (void *)((u32) region->entry.base +
+							region->reserved_size);
+
+			/* Heap should already be created so open by address */
+			retval = heapmemmp_open_by_addr(shared_addr,
+						(void **) &(region->heap));
+			if (retval < 0) {
+				retval = -1;
+				break;
+			}
+		}
+	}
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_attach failed status:%x\n",
+			retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_attach);
+
+/* Closes a heap, for non-owner processors, for each SharedRegion. */
+int sharedregion_detach(u16 remote_proc_id)
+{
+	int retval = 0;
+	int tmp_status = 0;
+	struct sharedregion_region *region = NULL;
+	u16 i;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON((remote_proc_id > MULTIPROC_MAXPROCESSORS))) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/*
+	 *  Loop through the regions and open the heap if not owner
+	 */
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		region = &(sharedregion_module->regions[i]);
+		if ((region->entry.is_valid) && \
+			(region->entry.owner_proc_id != multiproc_self()) && \
+			(region->entry.owner_proc_id != \
+			SHAREDREGION_DEFAULTOWNERID) && \
+			(region->entry.create_heap) && (region->heap != NULL)) {
+			/* Heap should already be created so open by address */
+			tmp_status = heapmemmp_close((void **) &(region->heap));
+			if ((tmp_status < 0) && (retval >= 0)) {
+				retval = -1;
+				printk(KERN_ERR "sharedregion_detach: "
+					"heapmemmp_close failed!");
+			}
+		}
+	}
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_detach failed status:%x\n",
+			retval);
+	}
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_detach);
+
+/* This will return the address pointer associated with the
+ * shared region pointer */
+void *sharedregion_get_ptr(u32 *srptr)
+{
+	struct sharedregion_region *region = NULL;
+	void *return_ptr = NULL;
+	u16 region_id;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (srptr == SHAREDREGION_INVALIDSRPTR)
+		goto error;
+
+	if (sharedregion_module->cfg.translate == false)
+		return_ptr = (void *)srptr;
+	else {
+		region_id = \
+			((u32)(srptr) >> sharedregion_module->num_offset_bits);
+		if (region_id >= sharedregion_module->cfg.num_entries) {
+			retval = -EINVAL;
+			goto error;
+		}
+
+		region = &(sharedregion_module->regions[region_id]);
+		return_ptr = (void *)(((u32)srptr & \
+					sharedregion_module->offset_mask) + \
+					(u32) region->entry.base);
+	}
+	return return_ptr;
+
+error:
+	printk(KERN_ERR "sharedregion_get_ptr failed 0x%x\n", retval);
+	return (void *)NULL;
+
+}
+EXPORT_SYMBOL(sharedregion_get_ptr);
+
+/* This will return sharedregion pointer associated with the
+ * an address in a shared region area registered with the
+ * sharedregion module */
+u32 *sharedregion_get_srptr(void *addr, u16 id)
+{
+	struct sharedregion_region *region = NULL;
+	u32 *ret_ptr = SHAREDREGION_INVALIDSRPTR ;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(addr == NULL))
+		goto error;
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries))
+		goto error;
+
+	if (sharedregion_module->cfg.translate == false)
+		ret_ptr = (u32 *)addr;
+	else {
+		region = &(sharedregion_module->regions[id]);
+		/*
+		 *  Note: The very last byte on the very last id cannot be
+		 *        mapped because SharedRegion_INVALIDSRPTR which is ~0
+		 *        denotes an error. Since pointers should be word
+		 *        aligned, we don't expect this to be a problem.
+		 *
+		 *        ie: numEntries = 4, id = 3, base = 0x00000000,
+		 *            len = 0x40000000 ==> address 0x3fffffff would be
+		 *            invalid because the SRPtr for this address is
+		 *            0xffffffff
+		 */
+		if (((u32) addr >= (u32) region->entry.base) && ((u32) addr < \
+			((u32) region->entry.base + region->entry.len))) {
+			ret_ptr = (u32 *)
+				((id << sharedregion_module->num_offset_bits) |
+				((u32) addr - (u32) region->entry.base));
+		}
+	}
+	return ret_ptr;
+
+error:
+	printk(KERN_ERR	"sharedregion_get_srptr failed 0x%x\n", retval);
+	return (u32 *)NULL;
+}
+EXPORT_SYMBOL(sharedregion_get_srptr);
+
+#if 0
+/*
+ * ======== sharedregion_add ========
+ *  Purpose:
+ *  This will add a memory segment to the lookup table
+ *  during runtime by base and length
+ */
+int sharedregion_add(u32 index, void *base, u32 len)
+{
+	struct sharedregion_info *entry = NULL;
+	struct sharedregion_info *table = NULL;
+	s32 retval = 0;
+	u32 i;
+	u16 myproc_id;
+	bool overlap = false;
+	bool same = false;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (index >= sharedregion_module->cfg.num_entries ||
+			sharedregion_module->region_size < len) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	myproc_id = multiproc_get_id(NULL);
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+
+
+	table = sharedregion_module->table;
+	/* Check for overlap */
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		entry = (table
+			 + (myproc_id * sharedregion_module->cfg.num_entries)
+			 + i);
+		if (entry->is_valid) {
+			/* Handle duplicate entry */
+			if ((base == entry->base) && (len == entry->len)) {
+				same = true;
+				break;
+			}
+
+			if ((base >= entry->base) &&
+				(base < (void *)
+					((u32)entry->base + entry->len))) {
+				overlap = true;
+				break;
+			}
+
+			if ((base < entry->base) &&
+				(void *)((u32)base + len) >= entry->base) {
+				overlap = true;
+				break;
+			}
+		}
+	}
+
+	if (same) {
+		retval = 1;
+		goto success;
+	}
+
+	if (overlap) {
+		/* FHACK: FIX ME */
+		retval = 1;
+		goto mem_overlap_error;
+	}
+
+	entry = (table
+		 + (myproc_id * sharedregion_module->cfg.num_entries)
+		 + index);
+	if (entry->is_valid == false) {
+		entry->base = base;
+		entry->len = len;
+		entry->is_valid = true;
+
+	} else {
+		/* FHACK: FIX ME */
+		sharedregion_module->ref_count_table[(myproc_id *
+					sharedregion_module->cfg.num_entries)
+					+ index] += 1;
+		retval = 1;
+		goto dup_entry_error;
+	}
+
+success:
+	mutex_unlock(sharedregion_module->local_lock);
+	return 0;
+
+dup_entry_error: /* Fall through */
+mem_overlap_error:
+	printk(KERN_WARNING "sharedregion_add entry exists status: %x\n",
+		retval);
+	mutex_unlock(sharedregion_module->local_lock);
+
+error:
+	if (retval < 0)
+		printk(KERN_ERR "sharedregion_add failed status:%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_add);
+
+/*
+ * ======== sharedregion_remove ========
+ *  Purpose:
+ *  This will removes a memory segment to the lookup table
+ *  during runtime by base and length
+ */
+int sharedregion_remove(u32 index)
+{
+	struct sharedregion_info *entry = NULL;
+	struct sharedregion_info *table = NULL;
+	u16 myproc_id;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (index >= sharedregion_module->cfg.num_entries) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+
+	myproc_id = multiproc_get_id(NULL);
+	table = sharedregion_module->table;
+	entry = (table
+		 + (myproc_id * sharedregion_module->cfg.num_entries)
+		 + index);
+
+	if (sharedregion_module->ref_count_table[(myproc_id *
+			sharedregion_module->cfg.num_entries)
+			+ index] > 0)
+		sharedregion_module->ref_count_table[(myproc_id *
+					sharedregion_module->cfg.num_entries)
+					+ index] -= 1;
+	else {
+		entry->is_valid = false;
+		entry->base = NULL;
+		entry->len = 0;
+	}
+	mutex_unlock(sharedregion_module->local_lock);
+	return 0;
+
+error:
+	printk(KERN_ERR "sharedregion_remove failed status:%x\n", retval);
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_remove);
+
+/*
+ * ======== sharedregion_get_table_info ========
+ *  Purpose:
+ *  This will get the table entry information for the
+ *  specified index and id
+ */
+int sharedregion_get_table_info(u32 index, u16 proc_id,
+				struct sharedregion_info *info)
+{
+	struct sharedregion_info *entry = NULL;
+	struct sharedregion_info *table = NULL;
+	u16 proc_count;
+	s32 retval = 0;
+
+	BUG_ON(info == NULL);
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	proc_count = multiproc_get_max_processors();
+	if (index >= sharedregion_module->cfg.num_entries ||
+			proc_id >= proc_count) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+
+	table = sharedregion_module->table;
+	entry = (table
+		 + (proc_id * sharedregion_module->cfg.num_entries)
+		 + index);
+	memcpy((void *) info, (void *) entry, sizeof(struct sharedregion_info));
+	mutex_unlock(sharedregion_module->local_lock);
+	return 0;
+
+error:
+	printk(KERN_ERR "sharedregion_get_table_info failed status:%x\n",
+		retval);
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_get_table_info);
+
+/*
+ * ======== sharedregion_set_table_info ========
+ *  Purpose:
+ *  This will set the table entry information for the
+ *  specified index and id
+ */
+int sharedregion_set_table_info(u32 index, u16 proc_id,
+				struct sharedregion_info *info)
+{
+	struct sharedregion_info *entry = NULL;
+	struct sharedregion_info *table = NULL;
+	u16 proc_count;
+	s32 retval = 0;
+
+	BUG_ON(info == NULL);
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	proc_count = multiproc_get_max_processors();
+	if (index >= sharedregion_module->cfg.num_entries ||
+			proc_id >= proc_count) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+
+	table = sharedregion_module->table;
+	entry = (table
+		 + (proc_id * sharedregion_module->cfg.num_entries)
+		 + index);
+	memcpy((void *) entry, (void *) info, sizeof(struct sharedregion_info));
+	mutex_unlock(sharedregion_module->local_lock);
+	return 0;
+
+error:
+	printk(KERN_ERR "sharedregion_set_table_info failed status:%x\n",
+		retval);
+	return retval;
+}
+EXPORT_SYMBOL(sharedregion_set_table_info);
+#endif
+
+/* Return the region info */
+void sharedregion_get_region_info(u16 id, struct sharedregion_region *region)
+{
+	struct sharedregion_region *regions = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(region == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	regions = &(sharedregion_module->regions[id]);
+	memcpy((void *) region, (void *) regions,
+		sizeof(struct sharedregion_region));
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_get_region_info failed: "
+			"status = 0x%x", retval);
+	}
+	return;
+}
+
+/* Whether address translation is enabled */
+bool sharedregion_translate_enabled(void)
+{
+	return sharedregion_module->cfg.translate;
+}
+
+/* Gets the number of regions */
+u16 sharedregion_get_num_regions(void)
+{
+	return sharedregion_module->cfg.num_entries;
+}
+
+/* Sets the table information entry in the table */
+int sharedregion_set_entry(u16 id, struct sharedregion_entry *entry)
+{
+	int retval = 0;
+	struct sharedregion_region *region = NULL;
+	void *shared_addr = NULL;
+	struct heapmemmp_object *heap_handle = NULL;
+	struct heapmemmp_object **heap_handle_ptr = NULL;
+	struct heapmemmp_params params;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(entry == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	region = &(sharedregion_module->regions[id]);
+
+	/* Make sure region does not overlap existing ones */
+	retval = _sharedregion_check_overlap(region->entry.base,
+						region->entry.len);
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_set_entry: Entry is overlapping "
+			"existing entry!");
+		goto error;
+	}
+	if (region->entry.is_valid) {
+		/*region entry should be invalid at this point */
+		retval = -EEXIST;
+		printk(KERN_ERR "_sharedregion_setEntry: Entry already exists");
+		goto error;
+	}
+	if ((entry->cache_enable) && (entry->cache_line_size == 0)) {
+		/* if cache enabled, cache line size must != 0 */
+		retval = -1;
+		printk(KERN_ERR "_sharedregion_setEntry: If cache enabled, "
+			"cache line size must != 0");
+		goto error;
+	}
+
+	/* needs to be thread safe */
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+	/* set specified region id to entry values */
+	memcpy((void *)&(region->entry), (void *)entry,
+		sizeof(struct sharedregion_entry));
+	mutex_unlock(sharedregion_module->local_lock);
+
+	if (entry->owner_proc_id == multiproc_self()) {
+		if ((entry->create_heap) && (region->heap == NULL)) {
+			/* get current Ptr (reserve memory with size of 0) */
+			shared_addr = sharedregion_reserve_memory(id, 0);
+			heapmemmp_params_init(&params);
+			params.shared_addr = shared_addr;
+			params.shared_buf_size = region->entry.len - \
+						region->reserved_size;
+
+			/*
+			 *  Calculate size of HeapMemMP_Attrs and adjust
+			 *  shared_buf_size. Size of HeapMemMP_Attrs =
+			 *  HeapMemMP_sharedMemReq(&params) -
+			 *  params.shared_buf_size
+			 */
+			params.shared_buf_size -= \
+				(heapmemmp_shared_mem_req(&params) - \
+				params.shared_buf_size);
+
+			heap_handle = heapmemmp_create(&params);
+			if (heap_handle == NULL) {
+				region->entry.is_valid = false;
+				retval = -ENOMEM;
+				goto error;
+			} else
+				region->heap = heap_handle;
+		}
+	} else {
+		if ((entry->create_heap) && (region->heap == NULL)) {
+			/* shared_addr should match creator's for each region */
+			shared_addr = (void *)((u32) region->entry.base
+						+ region->reserved_size);
+
+			/* set the pointer to a heap handle */
+			heap_handle_ptr = \
+				(struct heapmemmp_object **) &(region->heap);
+
+			/* open the heap by address */
+			retval = heapmemmp_open_by_addr(shared_addr, (void **)
+							heap_handle_ptr);
+			if (retval < 0) {
+				region->entry.is_valid = false;
+				retval = -1;
+				goto error;
+			}
+		}
+	}
+	return 0;
+
+error:
+	printk(KERN_ERR "sharedregion_set_entry failed! status = 0x%x", retval);
+	return retval;
+}
+
+/* Clears the region in the table */
+int sharedregion_clear_entry(u16 id)
+{
+	int retval = 0;
+	struct sharedregion_region *region = NULL;
+	struct heapmemmp_object *heapmem_ptr = NULL;
+	u16 my_id;
+	u16 owner_proc_id;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* Need to make sure not trying to clear Region 0 */
+	if (WARN_ON(id == 0)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	my_id = multiproc_self();
+
+	/* Needs to be thread safe */
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+	region = &(sharedregion_module->regions[id]);
+
+	/* Store these fields to local variables */
+	owner_proc_id = region->entry.owner_proc_id;
+	heapmem_ptr = region->heap;
+
+	/* Clear region to their defaults */
+	region->entry.is_valid = false;
+	region->entry.base = NULL;
+	region->entry.len = 0u;
+	region->entry.owner_proc_id = SHAREDREGION_DEFAULTOWNERID;
+	region->entry.cache_enable = true;
+	region->entry.cache_line_size = \
+				sharedregion_module->cfg.cache_line_size;
+	region->entry.create_heap = false;
+	region->entry.name = NULL;
+	region->reserved_size = 0u;
+	region->heap = NULL;
+	mutex_unlock(sharedregion_module->local_lock);
+
+	/* Delete or close previous created heap outside the gate */
+	if (heapmem_ptr != NULL) {
+		if (owner_proc_id == my_id) {
+			retval = heapmemmp_delete((void **) &heapmem_ptr);
+			if (retval < 0) {
+				retval = -1;
+				goto error;
+			}
+		} else if (owner_proc_id != (u16) SHAREDREGION_DEFAULTOWNERID) {
+			retval = heapmemmp_close((void **) &heapmem_ptr);
+			if (retval < 0) {
+				retval = -1;
+				goto error;
+			}
+		}
+	}
+	return 0;
+
+error:
+	printk(KERN_ERR "sharedregion_clear_entry failed! status = 0x%x",
+		retval);
+	return retval;
+}
+
+/* Clears the reserve memory for each region in the table */
+void sharedregion_clear_reserved_memory(void)
+{
+	struct sharedregion_region *region = NULL;
+	int i;
+
+	/*
+	 *  Loop through shared regions. If an owner of a region is specified,
+	 *  the owner zeros out the reserved memory in each region.
+	 */
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		region = &(sharedregion_module->regions[i]);
+		if ((region->entry.is_valid) && \
+			(region->entry.owner_proc_id == multiproc_self())) {
+			/* Clear reserved memory */
+			memset(region->entry.base, 0, region->reserved_size);
+
+			/* Writeback invalidate cache if enabled in region */
+			if (region->entry.cache_enable) {
+				/* TODO: Enable cache */
+				/* Cache_wbInv(region->entry.base,
+						region->reserved_size,
+						Cache_Type_ALL,
+						true); */
+			}
+		}
+	}
+}
+
+/* Initializes the entry fields */
+void sharedregion_entry_init(struct sharedregion_entry *entry)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(entry == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* init the entry to default values */
+	entry->base = NULL;
+	entry->len = 0;
+	entry->owner_proc_id = SHAREDREGION_DEFAULTOWNERID;
+	entry->cache_enable = false; /*Set to true once cache API is done */
+	entry->cache_line_size = sharedregion_module->cfg.cache_line_size;
+	entry->create_heap = false;
+	entry->name = NULL;
+	entry->is_valid = false;
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_entry_init failed: "
+			"status = 0x%x", retval);
+	}
+	return;
+}
+
+/* Returns Heap Handle of associated id */
+void *sharedregion_get_heap(u16 id)
+{
+	struct heapmemmp_object *heap = NULL;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/*
+	 *  If translate == true or translate == false
+	 *  and 'id' is not INVALIDREGIONID, then assert id is valid.
+	 *  Return the heap associated with the region id.
+	 *
+	 *  If those conditions are not met, the id is from
+	 *  an addres in local memory so return NULL.
+	 */
+	if ((sharedregion_module->cfg.translate) || \
+			((sharedregion_module->cfg.translate == false) && \
+			(id != SHAREDREGION_INVALIDREGIONID))) {
+		heap = sharedregion_module->regions[id].heap;
+	}
+	return (void *)heap;
+
+error:
+	printk(KERN_ERR "sharedregion_get_heap failed: status = 0x%x", retval);
+	return (void *)NULL;
+}
+
+/* This will return the id for the specified address pointer. */
+u16 sharedregion_get_id(void *addr)
+{
+	struct sharedregion_region *region = NULL;
+	u16 region_id = SHAREDREGION_INVALIDREGIONID;
+	u16 i;
+	s32 retval = -ENOENT;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(addr == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval) {
+		retval = -ENODEV;
+		goto error;
+	}
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		region = &(sharedregion_module->regions[i]);
+		if (region->entry.is_valid && (addr >= region->entry.base) &&
+			(addr < (void *)((u32)region->entry.base + \
+			(region->entry.len)))) {
+			region_id = i;
+			retval = 0;
+			break;
+		}
+	}
+	mutex_unlock(sharedregion_module->local_lock);
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_get_id failed: "
+			"status = 0x%x", retval);
+	}
+	return region_id;
+}
+EXPORT_SYMBOL(sharedregion_get_id);
+
+/* Returns the id of shared region that matches name.
+ * Returns sharedregion_INVALIDREGIONID if no region is found. */
+u16 sharedregion_get_id_by_name(char *name)
+{
+	struct sharedregion_region *region = NULL;
+	u16 region_id = SHAREDREGION_INVALIDREGIONID;
+	u16 i;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(name == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/* Needs to be thread safe */
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+	/* loop through entries to find matching name */
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		region = &(sharedregion_module->regions[i]);
+		if (region->entry.is_valid) {
+			if (strcmp(region->entry.name, name) == 0) {
+				region_id = i;
+				break;
+			}
+		}
+	}
+	mutex_unlock(sharedregion_module->local_lock);
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_get_id_by_name failed: "
+			"status = 0x%x", retval);
+	}
+	return region_id;
+}
+
+/* Gets the entry information for the specified region id */
+int sharedregion_get_entry(u16 id, struct sharedregion_entry *entry)
+{
+	int retval = 0;
+	struct sharedregion_region *region = NULL;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(entry == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	region = &(sharedregion_module->regions[id]);
+	memcpy((void *) entry, (void *) &(region->entry),
+			sizeof(struct sharedregion_entry));
+	return 0;
+
+error:
+	printk(KERN_ERR "sharedregion_get_entry failed: status = 0x%x", retval);
+	return retval;
+}
+
+/* Get cache line size */
+uint sharedregion_get_cache_line_size(u16 id)
+{
+	uint cache_line_size = sizeof(int);
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/*
+	 *  If translate == true or translate == false
+	 *  and 'id' is not INVALIDREGIONID, then assert id is valid.
+	 *  Return the heap associated with the region id.
+	 *
+	 *  If those conditions are not met, the id is from
+	 *  an addres in local memory so return NULL.
+	 */
+	if ((sharedregion_module->cfg.translate) || \
+			((sharedregion_module->cfg.translate == false) && \
+			(id != SHAREDREGION_INVALIDREGIONID))) {
+		cache_line_size =
+			sharedregion_module->regions[id].entry.cache_line_size;
+	}
+	return cache_line_size;
+
+error:
+	printk(KERN_ERR "sharedregion_get_cache_line_size failed: "
+		"status = 0x%x", retval);
+	return cache_line_size;
+}
+
+/* Is cache enabled? */
+bool sharedregion_is_cache_enabled(u16 id)
+{
+	bool cache_enable = false;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/*
+	 *  If translate == true or translate == false
+	 *  and 'id' is not INVALIDREGIONID, then assert id is valid.
+	 *  Return the heap associated with the region id.
+	 *
+	 *  If those conditions are not met, the id is from
+	 *  an address in local memory so return NULL.
+	 */
+	if ((sharedregion_module->cfg.translate) || \
+			((sharedregion_module->cfg.translate == false) && \
+			(id != SHAREDREGION_INVALIDREGIONID))) {
+		cache_enable = \
+			sharedregion_module->regions[id].entry.cache_enable;
+	}
+	return cache_enable;
+
+error:
+	printk(KERN_ERR "sharedregion_is_cache_enabled failed: "
+		"status = 0x%x", retval);
+	return false;
+}
+
+/* Reserves the specified amount of memory from the specified region id. */
+void *sharedregion_reserve_memory(u16 id, uint size)
+{
+	void *ret_ptr = NULL;
+	struct sharedregion_region *region = NULL;
+	u32 min_align;
+	uint new_size;
+	uint cur_size;
+	uint cache_line_size = 0;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(sharedregion_module->regions[id].entry.is_valid == false)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/*TODO: min_align = Memory_getMaxDefaultTypeAlign();*/min_align = 4;
+	cache_line_size = sharedregion_get_cache_line_size(id);
+	if (cache_line_size > min_align)
+		min_align = cache_line_size;
+
+	region = &(sharedregion_module->regions[id]);
+
+	/* Set the current size to the reserved_size */
+	cur_size = region->reserved_size;
+
+	/* No need to round here since cur_size is already aligned */
+	ret_ptr = (void *)((u32) region->entry.base + cur_size);
+
+	/*  Round the new size to the min alignment since */
+	new_size = ROUND_UP(size, min_align);
+
+	/* Need to make sure (cur_size + new_size) is smaller than region len */
+	if (region->entry.len < (cur_size + new_size)) {
+		retval = -EINVAL;
+		printk(KERN_ERR "sharedregion_reserve_memory: Too large size "
+					"is requested to be reserved!");
+		goto error;
+	}
+
+	/* Add the new size to current size */
+	region->reserved_size = cur_size + new_size;
+	return ret_ptr;
+
+error:
+	printk(KERN_ERR "sharedregion_reserve_memory failed: "
+		"status = 0x%x", retval);
+	return (void *)NULL;
+}
+
+/* Unreserve the specified amount of memory from the specified region id. */
+void sharedregion_unreserve_memory(u16 id, uint size)
+{
+	struct sharedregion_region *region = NULL;
+	u32 min_align;
+	uint new_size;
+	uint cur_size;
+	uint cache_line_size = 0;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(sharedregion_module->regions[id].entry.is_valid == false)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	/*TODO: min_align = Memory_getMaxDefaultTypeAlign();*/min_align = 4;
+	cache_line_size = sharedregion_get_cache_line_size(id);
+	if (cache_line_size > min_align)
+		min_align = cache_line_size;
+
+	region = &(sharedregion_module->regions[id]);
+
+	/* Set the current size to the unreservedSize */
+	cur_size = region->reserved_size;
+
+	/*  Round the new size to the min alignment since */
+	new_size = ROUND_UP(size, min_align);
+
+	/* Add the new size to current size */
+	region->reserved_size = cur_size - new_size;
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "sharedregion_unreserve_memory failed: "
+			"status = 0x%x", retval);
+	}
+	return;
+}
+
+/* =============================================================================
+ *  Internal Functions
+ * =============================================================================
+ */
+/* Checks to make sure overlap does not exists. */
+int _sharedregion_check_overlap(void *base, u32 len)
+{
+	int retval = 0;
+	struct sharedregion_region *region = NULL;
+	u32 i;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+
+	/* check whether new region overlaps existing ones */
+	for (i = 0; i < sharedregion_module->cfg.num_entries; i++) {
+		region = &(sharedregion_module->regions[i]);
+		if (region->entry.is_valid) {
+			if (base >= region->entry.base) {
+				if (base < (void *)((u32) region->entry.base
+							+ region->entry.len)) {
+					retval = -1;
+					printk(KERN_ERR "_sharedregion_check_"
+						"_overlap failed: Specified "
+						"region falls within another "
+						"region!");
+					break;
+				}
+			} else {
+				if ((void *)((u32) base + len) > \
+					region->entry.base) {
+					retval = -1;
+					printk(KERN_ERR "_sharedregion_check_"
+						"_overlap failed: Specified "
+						"region spans across multiple "
+						"regions!");
+					break;
+				}
+			}
+		}
+	}
+
+	mutex_unlock(sharedregion_module->local_lock);
+	return 0;
+
+error:
+	printk(KERN_ERR "_sharedregion_check_overlap failed: "
+		"status = 0x%x", retval);
+	return retval;
+}
+
+/* Return the number of offset_bits bits */
+u32 _sharedregion_get_num_offset_bits(void)
+{
+	u32 num_entries = sharedregion_module->cfg.num_entries;
+	u32 index_bits = 0;
+	u32 num_offset_bits = 0;
+	s32 retval = 0;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (num_entries == 0 || num_entries == 1)
+		index_bits = num_entries;
+	else {
+		num_entries = num_entries - 1;
+
+		/* determine the number of bits for the index */
+		while (num_entries) {
+			index_bits++;
+			num_entries = num_entries >> 1;
+		}
+	}
+	num_offset_bits = 32 - index_bits;
+
+error:
+	if (retval < 0) {
+		printk(KERN_ERR "_sharedregion_get_num_offset_bits failed: "
+			"status = 0x%x", retval);
+	}
+	return num_offset_bits;
+}
+
+/* Sets the table information entry in the table (doesn't create heap). */
+int _sharedregion_set_entry(u16 id, struct sharedregion_entry *entry)
+{
+	int retval = 0;
+	struct sharedregion_region *region = NULL;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(sharedregion_module->ref_count),
+				SHAREDREGION_MAKE_MAGICSTAMP(0),
+				SHAREDREGION_MAKE_MAGICSTAMP(1)) == true)) {
+		retval = -ENODEV;
+		goto error;
+	}
+
+	if (WARN_ON(entry == NULL)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (WARN_ON(id >= sharedregion_module->cfg.num_entries)) {
+		retval = -EINVAL;
+		goto error;
+	}
+
+	region = &(sharedregion_module->regions[id]);
+
+	/* Make sure region does not overlap existing ones */
+	retval = _sharedregion_check_overlap(region->entry.base,
+						region->entry.len);
+	if (retval < 0) {
+		printk(KERN_ERR "_sharedregion_set_entry: Entry is overlapping "
+			"existing entry!");
+		goto error;
+	}
+	if (region->entry.is_valid) {
+		/*region entry should be invalid at this point */
+		retval = -EEXIST;
+		printk(KERN_ERR "_sharedregion_set_entry: ntry already exists");
+		goto error;
+	}
+	/* Fail if cacheEnabled and cache_line_size equal 0 */
+	if ((entry->cache_enable) && (entry->cache_line_size == 0)) {
+		/* if cache enabled, cache line size must != 0 */
+		retval = -1;
+		printk(KERN_ERR "_sharedregion_set_entry: If cache enabled, "
+			"cache line size must != 0");
+		goto error;
+	}
+
+	/* needs to be thread safe */
+	retval = mutex_lock_interruptible(sharedregion_module->local_lock);
+	if (retval)
+		goto error;
+	/* set specified region id to entry values */
+	memcpy((void *)&(region->entry), (void *)entry,
+		sizeof(struct sharedregion_entry));
+	mutex_unlock(sharedregion_module->local_lock);
+	return 0;
+
+error:
+	printk(KERN_ERR "_sharedregion_set_entry failed! status = 0x%x",
+		retval);
+	return retval;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/sharedregion_ioctl.c b/drivers/dsp/syslink/multicore_ipc/sharedregion_ioctl.c
new file mode 100644
index 000000000000..646e34a00790
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/sharedregion_ioctl.c
@@ -0,0 +1,479 @@
+/*
+ *  sharedregion_ioctl.c
+ *
+ *  The sharedregion module is designed to be used in a
+ *  multi-processor environment where there are memory regions
+ *  that are shared and accessed across different processors
+ *
+ *  Copyright (C) 2008-2010 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include <linux/uaccess.h>
+#include <linux/types.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+
+#include <multiproc.h>
+#include <sharedregion.h>
+#include <sharedregion_ioctl.h>
+#include <platform_mem.h>
+
+/* This ioctl interface to sharedregion_get_config function */
+static int sharedregion_ioctl_get_config(struct sharedregion_cmd_args *cargs)
+{
+
+	struct sharedregion_config config;
+	s32 status = 0;
+	s32 size;
+
+	sharedregion_get_config(&config);
+	size = copy_to_user(cargs->args.get_config.config, &config,
+				sizeof(struct sharedregion_config));
+	if (size)
+		status = -EFAULT;
+
+	cargs->api_status = 0;
+	return status;
+}
+
+
+/* This ioctl interface to sharedregion_setup function */
+static int sharedregion_ioctl_setup(struct sharedregion_cmd_args *cargs)
+{
+	struct sharedregion_config config;
+	struct sharedregion_region region;
+	u16 i;
+	s32 status = 0;
+	s32 size;
+
+	size = copy_from_user(&config, cargs->args.setup.config,
+				sizeof(struct sharedregion_config));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = sharedregion_setup(&config);
+	if (cargs->api_status < 0)
+		goto exit;
+
+	for (i = 0; i < config.num_entries; i++) {
+		sharedregion_get_region_info(i, &region);
+		if (region.entry.is_valid == true) {
+			/* Convert kernel virtual address to physical
+			 * addresses */
+			/*region.entry.base = MemoryOS_translate(
+					(Ptr) region.entry.base,
+					Memory_XltFlags_Virt2Phys);*/
+			region.entry.base = platform_mem_translate(
+					region.entry.base,
+					PLATFORM_MEM_XLT_FLAGS_VIRT2PHYS);
+			if (region.entry.base == NULL) {
+				printk(KERN_ERR "sharedregion_ioctl_setup: "
+					"failed to translate region virtual "
+					"address.\n");
+				status = -ENOMEM;
+				goto exit;
+			}
+			size = copy_to_user((void *)
+					&(cargs->args.setup.regions[i]),
+					&region,
+					sizeof(struct sharedregion_region));
+			if (size) {
+				status = -EFAULT;
+				goto exit;
+			}
+		}
+	}
+
+exit:
+	return status;
+}
+
+/* This ioctl interface to sharedregion_destroy function */
+static int sharedregion_ioctl_destroy(
+				struct sharedregion_cmd_args *cargs)
+{
+	cargs->api_status = sharedregion_destroy();
+	return 0;
+}
+
+/* This ioctl interface to sharedregion_start function */
+static int sharedregion_ioctl_start(struct sharedregion_cmd_args *cargs)
+{
+	cargs->api_status = sharedregion_start();
+	return 0;
+}
+
+/* This ioctl interface to sharedregion_stop function */
+static int sharedregion_ioctl_stop(struct sharedregion_cmd_args *cargs)
+{
+	cargs->api_status = sharedregion_stop();
+	return 0;
+}
+
+/* This ioctl interface to sharedregion_attach function */
+static int sharedregion_ioctl_attach(struct sharedregion_cmd_args *cargs)
+{
+	cargs->api_status = sharedregion_attach(
+					cargs->args.attach.remote_proc_id);
+	return 0;
+}
+
+/* This ioctl interface to sharedregion_detach function */
+static int sharedregion_ioctl_detach(struct sharedregion_cmd_args *cargs)
+{
+	cargs->api_status = sharedregion_detach(
+					cargs->args.detach.remote_proc_id);
+	return 0;
+}
+
+/* This ioctl interface to sharedregion_get_heap function */
+static int sharedregion_ioctl_get_heap(struct sharedregion_cmd_args *cargs)
+{
+	struct heap_object *heap_handle = NULL;
+	s32 status = 0;
+
+	heap_handle = (struct heap_object *) sharedregion_get_heap(
+						cargs->args.get_heap.id);
+	if (heap_handle != NULL)
+		cargs->api_status = 0;
+	else {
+		printk(KERN_ERR "sharedregion_ioctl_get_heap failed: "
+			"heap_handle is NULL!");
+		cargs->api_status = -1;
+	}
+
+	cargs->args.get_heap.heap_handle = heap_handle;
+
+	return status;
+}
+
+/* This ioctl interface to sharedregion_clear_entry function */
+static int sharedregion_ioctl_clear_entry(struct sharedregion_cmd_args *cargs)
+{
+	cargs->api_status = sharedregion_clear_entry(
+					cargs->args.clear_entry.id);
+	return 0;
+}
+
+/* This ioctl interface to sharedregion_set_entry function */
+static int sharedregion_ioctl_set_entry(struct sharedregion_cmd_args *cargs)
+{
+	struct sharedregion_entry entry;
+	s32 status = 0;
+
+	entry = cargs->args.set_entry.entry;
+	/* entry.base = Memory_translate ((Ptr)cargs->args.setEntry.entry.base,
+				Memory_XltFlags_Phys2Virt); */
+	entry.base = platform_mem_translate(
+			(void *)cargs->args.set_entry.entry.base,
+			PLATFORM_MEM_XLT_FLAGS_PHYS2VIRT);
+	if (entry.base == NULL) {
+		printk(KERN_ERR "sharedregion_ioctl_set_entry: failed to"
+			"translate region virtual address.\n");
+		status = -ENOMEM;
+		goto exit;
+	}
+
+	cargs->api_status = sharedregion_set_entry(cargs->args.set_entry.id,
+							&entry);
+
+exit:
+	return status;
+}
+
+/* This ioctl interface to sharedregion_reserve_memory function */
+static int sharedregion_ioctl_reserve_memory
+					(struct sharedregion_cmd_args *cargs)
+{
+	/* Ignore the return value. */
+	sharedregion_reserve_memory(cargs->args.reserve_memory.id,
+					cargs->args.reserve_memory.size);
+	cargs->api_status = 0;
+	return 0;
+}
+
+/* This ioctl interface to sharedregion_clear_reserved_memory function */
+static int sharedregion_ioctl_clear_reserved_memory(
+					struct sharedregion_cmd_args *cargs)
+{
+	/* Ignore the return value. */
+	sharedregion_clear_reserved_memory();
+	cargs->api_status = 0;
+	return 0;
+}
+
+/* This ioctl interface to sharedregion_get_region_info function */
+static int sharedregion_ioctl_get_region_info(
+				struct sharedregion_cmd_args *cargs)
+{
+	struct sharedregion_config config;
+	struct sharedregion_region region;
+	u16 i;
+	s32 status = 0;
+	s32 size;
+
+	sharedregion_get_config(&config);
+	for (i = 0; i < config.num_entries; i++) {
+		sharedregion_get_region_info(i, &region);
+		if (region.entry.is_valid == true) {
+			/* Convert the kernel virtual address to physical
+			* addresses */
+			/*region.entry.base = MemoryOS_translate (
+					(Ptr)region.entry.base,
+					Memory_XltFlags_Virt2Phys);*/
+			region.entry.base = platform_mem_translate(
+					region.entry.base,
+					PLATFORM_MEM_XLT_FLAGS_VIRT2PHYS);
+			if (region.entry.base == NULL) {
+				printk(KERN_ERR
+					"sharedregion_ioctl_get_region_info: "
+					"failed to translate region virtual "
+					"address.\n");
+				status = -ENOMEM;
+				goto exit;
+			}
+
+			size = copy_to_user(&(cargs->args.setup.regions[i]),
+					&region,
+					sizeof(struct sharedregion_region));
+			if (size) {
+				status = -EFAULT;
+				goto exit;
+			}
+		} else {
+			region.entry.base = NULL;
+			size = copy_to_user(&(cargs->args.setup.regions[i]),
+					&region,
+					sizeof(struct sharedregion_region));
+			if (size) {
+				status = -EFAULT;
+				goto exit;
+			}
+		}
+	}
+	cargs->api_status = 0;
+
+exit:
+	if (status < 0)
+		cargs->api_status = -1;
+	return status;
+}
+
+#if 0
+/*
+ * ======== sharedregion_ioctl_add ========
+ *  Purpose:
+ *  This ioctl interface to sharedregion_add function
+ */
+static int sharedregion_ioctl_add(struct sharedregion_cmd_args *cargs)
+{
+	u32 base = (u32)platform_mem_translate(cargs->args.add.base,
+					PLATFORM_MEM_XLT_FLAGS_PHYS2VIRT);
+	cargs->api_status = sharedregion_add(cargs->args.add.index,
+					(void *)base, cargs->args.add.len);
+	return 0;
+}
+
+/*
+ * ======== sharedregion_ioctl_get_index ========
+ *  Purpose:
+ *  This ioctl interface to sharedregion_get_index function
+ */
+static int sharedregion_ioctl_get_index(struct sharedregion_cmd_args *cargs)
+{
+	s32 index = 0;
+
+	index = sharedregion_get_index(cargs->args.get_index.addr);
+	cargs->args.get_index.index = index;
+	cargs->api_status = 0;
+	return 0;
+}
+
+/*
+ * ======== sharedregion_ioctl_get_ptr ========
+ *  Purpose:
+ *  This ioctl interface to sharedregion_get_ptr function
+ */
+static int sharedregion_ioctl_get_ptr(struct sharedregion_cmd_args *cargs)
+{
+	void *addr = NULL;
+
+	addr = sharedregion_get_ptr(cargs->args.get_ptr.srptr);
+	/* We are not checking the return from the module, its user
+	responsibilty to pass proper value to application
+	*/
+	cargs->args.get_ptr.addr = addr;
+	cargs->api_status = 0;
+	return 0;
+}
+
+/*
+ * ======== sharedregion_ioctl_get_srptr ========
+ *  Purpose:
+ *  This ioctl interface to sharedregion_get_srptr function
+ */
+static int sharedregion_ioctl_get_srptr(struct sharedregion_cmd_args *cargs)
+{
+	u32 *srptr = NULL;
+
+	srptr = sharedregion_get_srptr(cargs->args.get_srptr.addr,
+					cargs->args.get_srptr.index);
+	/* We are not checking the return from the module, its user
+	responsibilty to pass proper value to application
+	*/
+	cargs->args.get_srptr.srptr = srptr;
+	cargs->api_status = 0;
+	return 0;
+}
+
+/*
+ * ======== sharedregion_ioctl_remove ========
+ *  Purpose:
+ *  This ioctl interface to sharedregion_remove function
+ */
+static int sharedregion_ioctl_remove(struct sharedregion_cmd_args *cargs)
+{
+	cargs->api_status = sharedregion_remove(cargs->args.remove.index);
+	return 0;
+}
+
+/*
+ * ======== sharedregion_ioctl_set_table_info ========
+ *  Purpose:
+ *  This ioctl interface to sharedregion_set_table_info function
+ */
+static int sharedregion_ioctl_set_table_info(
+			struct sharedregion_cmd_args *cargs)
+{
+	struct sharedregion_info info;
+	s32 status = 0;
+	s32 size;
+
+	size = copy_from_user(&info, cargs->args.set_table_info.info,
+				sizeof(struct sharedregion_info));
+	if (size) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = sharedregion_set_table_info(
+				cargs->args.set_table_info.index,
+				cargs->args.set_table_info.proc_id, &info);
+
+exit:
+	return status;
+}
+#endif
+
+/* This ioctl interface for sharedregion module */
+int sharedregion_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args)
+{
+	s32 os_status = 0;
+	s32 size = 0;
+	struct sharedregion_cmd_args __user *uarg =
+				(struct sharedregion_cmd_args __user *)args;
+	struct sharedregion_cmd_args cargs;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		os_status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		os_status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+
+	if (os_status) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg,
+					sizeof(struct sharedregion_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_SHAREDREGION_GETCONFIG:
+		os_status = sharedregion_ioctl_get_config(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_SETUP:
+		os_status = sharedregion_ioctl_setup(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_DESTROY:
+		os_status = sharedregion_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_START:
+		os_status = sharedregion_ioctl_start(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_STOP:
+		os_status = sharedregion_ioctl_stop(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_ATTACH:
+		os_status = sharedregion_ioctl_attach(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_DETACH:
+		os_status = sharedregion_ioctl_detach(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_GETHEAP:
+		os_status = sharedregion_ioctl_get_heap(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_CLEARENTRY:
+		os_status = sharedregion_ioctl_clear_entry(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_SETENTRY:
+		os_status = sharedregion_ioctl_set_entry(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_RESERVEMEMORY:
+		os_status = sharedregion_ioctl_reserve_memory(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_CLEARRESERVEDMEMORY:
+		os_status = sharedregion_ioctl_clear_reserved_memory(&cargs);
+		break;
+
+	case CMD_SHAREDREGION_GETREGIONINFO:
+		os_status = sharedregion_ioctl_get_region_info(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		os_status = -ENOTTY;
+		break;
+	}
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs, sizeof(struct sharedregion_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+exit:
+	if (os_status < 0) {
+		printk(KERN_ERR "sharedregion_ioctl failed! status = 0x%x",
+			os_status);
+	}
+	return os_status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/sysipc_ioctl.c b/drivers/dsp/syslink/multicore_ipc/sysipc_ioctl.c
new file mode 100644
index 000000000000..9fa1af213b7d
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/sysipc_ioctl.c
@@ -0,0 +1,207 @@
+/*
+ *  sysipc_ioctl.c
+ *
+ *  This file implements all the ioctl operations required on the sysmgr
+ *  module.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Linux headers */
+#include <linux/uaccess.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+/* Module Headers */
+#include <ipc.h>
+#include <sysipc_ioctl.h>
+/*#include <platform.h>*/
+
+
+/*
+ * ioctl interface to ipc_setup function
+ */
+static inline int sysipc_ioctl_setup(struct sysipc_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct ipc_config config;
+
+	size = copy_from_user(&config, cargs->args.setup.config,
+					sizeof(struct ipc_config));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = ipc_setup(&config);
+
+exit:
+	return retval;
+}
+
+/*
+ * ioctl interface to ipc_control function
+ */
+static inline int sysipc_ioctl_control(struct sysipc_cmd_args *cargs)
+{
+	cargs->api_status = ipc_control(cargs->args.control.proc_id,
+					cargs->args.control.cmd_id,
+					cargs->args.control.arg);
+	return 0;
+}
+
+/*
+ * ioctl interface to ipc_read_config function
+ */
+static inline int sysipc_ioctl_read_config(struct sysipc_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	void *cfg = NULL;
+
+	cfg = kzalloc(cargs->args.read_config.size, GFP_KERNEL);
+	if (cfg == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+
+	cargs->api_status = ipc_read_config(
+					cargs->args.read_config.remote_proc_id,
+					cargs->args.read_config.tag, cfg,
+					cargs->args.read_config.size);
+
+	size = copy_to_user(cargs->args.read_config.cfg, cfg,
+					cargs->args.read_config.size);
+	if (size)
+		retval = -EFAULT;
+
+	kfree(cfg);
+
+exit:
+	return retval;
+}
+
+/*
+ * ioctl interface to ipc_write_config function
+ */
+static inline int sysipc_ioctl_write_config(struct sysipc_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	void *cfg = NULL;
+
+	cfg = kzalloc(cargs->args.write_config.size, GFP_KERNEL);
+	if (cfg == NULL) {
+		retval = -ENOMEM;
+		goto exit;
+	}
+
+	size = copy_from_user(cfg, cargs->args.write_config.cfg,
+					cargs->args.write_config.size);
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = ipc_write_config(
+					cargs->args.write_config.remote_proc_id,
+					cargs->args.write_config.tag, cfg,
+					cargs->args.write_config.size);
+
+	kfree(cfg);
+
+exit:
+	return retval;
+}
+
+/*
+ * ioctl interface to sysmgr_destroy function
+ */
+static inline int sysipc_ioctl_destroy(struct sysipc_cmd_args *cargs)
+{
+	cargs->api_status = ipc_destroy();
+	return 0;
+}
+
+/*
+ * ioctl interface function for sysmgr module
+ */
+int sysipc_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args)
+{
+	int os_status = 0;
+	struct sysipc_cmd_args __user *uarg =
+				(struct sysipc_cmd_args __user *)args;
+	struct sysipc_cmd_args cargs;
+	unsigned long size;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		os_status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		os_status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+	if (os_status) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg, sizeof(struct sysipc_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_IPC_SETUP:
+		os_status = sysipc_ioctl_setup(&cargs);
+		break;
+
+	case CMD_IPC_DESTROY:
+		os_status = sysipc_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_IPC_CONTROL:
+		os_status = sysipc_ioctl_control(&cargs);
+		break;
+
+	case CMD_IPC_READCONFIG:
+		os_status = sysipc_ioctl_read_config(&cargs);
+		break;
+
+	case CMD_IPC_WRITECONFIG:
+		os_status = sysipc_ioctl_write_config(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		os_status = -ENOTTY;
+		break;
+	}
+	if (os_status < 0)
+		goto exit;
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs, sizeof(struct sysipc_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+exit:
+	return os_status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/sysmemmgr.c b/drivers/dsp/syslink/multicore_ipc/sysmemmgr.c
new file mode 100644
index 000000000000..42c64e3d8972
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/sysmemmgr.c
@@ -0,0 +1,459 @@
+/*
+ *  sysmemmgr.c
+ *
+ *  Manager for the Slave system memory. Slave system level memory is allocated
+ *  through this modules.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+/* Standard headers */
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+/* Utils headers */
+#include <linux/vmalloc.h>
+#include <syslink/atomic_linux.h>
+#include <syslink/platform_mem.h>
+/*#include <GateMutex.h>
+#include <Memory.h>
+#include <Trace.h>*/
+
+
+/* Module level headers */
+#include <sysmemmgr.h>
+/*#include <BuddyPageAllocator.h>*/
+
+
+/* =============================================================================
+ * Macros
+ * =============================================================================
+ */
+/*! @brief Event reserved for System memory manager */
+#define SYSMEMMGR_EVENTNO		12
+
+/* Macro to make a correct module magic number with ref_count */
+#define SYSMEMMGR_MAKE_MAGICSTAMP(x)	((SYSMEMMGR_MODULEID << 12) | (x))
+
+/* =============================================================================
+ * Structs & Enums
+ * =============================================================================
+ */
+/*! @brief Structure containing list of buffers. The list is kept sorted by
+ * address. */
+struct sysmemmgr_static_mem_struct {
+	struct sysmemmgr_static_mem_struct *next;
+	/*!< Pointer to next entry */
+	u32 address;
+	/*!< Address of this entry */
+	u32 size;
+	/*!< Size of this entry */
+};
+
+
+/*! @brief Static memory manager object. */
+struct sysmemmgr_static_mem_mgr_obj {
+	struct sysmemmgr_static_mem_struct head;
+	/*!< Pointer to head entry */
+	struct sysmemmgr_static_mem_struct tail;
+	/*!< Pointer to tail entry */
+};
+
+/*!
+ *  @brief  Structure defining state object of system memory manager.
+ */
+struct sysmemmgr_module_object {
+	atomic_t ref_count;
+	/*!< Reference count */
+	struct sysmemmgr_static_mem_mgr_obj static_mem_obj;
+	/*!< Static memory manager object */
+	struct mutex *gate_handle;
+	/*!< Pointer to lock */
+	struct sysmemmgr_config cfg;
+	/*!< Current configuration values */
+	struct sysmemmgr_config default_cfg;
+	/*!< Default configuration values */
+};
+
+
+/*!
+ *  @brief  Object containing state of the system memory manager.
+ */
+static struct sysmemmgr_module_object sysmemmgr_state = {
+	.default_cfg.sizeof_valloc = 0x100000,
+	.default_cfg.sizeof_palloc = 0x100000,
+	.default_cfg.page_size = 0x1000,
+	.default_cfg.event_no = SYSMEMMGR_EVENTNO,
+};
+
+
+/* =============================================================================
+ * APIS
+ * =============================================================================
+ */
+/*
+ * ======== sysmemmgr_get_config ========
+ *  Purpose:
+ *  Function to get the default values for configuration.
+ */
+void sysmemmgr_get_config(struct sysmemmgr_config *config)
+{
+	if (WARN_ON(config == NULL))
+		goto err_exit;
+
+	if (atomic_cmpmask_and_lt(&(sysmemmgr_state.ref_count),
+				SYSMEMMGR_MAKE_MAGICSTAMP(0),
+				SYSMEMMGR_MAKE_MAGICSTAMP(1)) == true)
+		memcpy((void *) config, (void *)(&sysmemmgr_state.default_cfg),
+				sizeof(struct sysmemmgr_config));
+	else
+		memcpy((void *) config, (void *)(&sysmemmgr_state.cfg),
+				sizeof(struct sysmemmgr_config));
+
+	return;
+
+err_exit:
+	printk(KERN_ERR "sysmemmgr_get_config: Argument of type "
+		"(struct sysmemmgr_config *) passed is NULL\n");
+	return;
+}
+
+
+/*
+ * ======== sysmemmgr_setup ========
+ *  Purpose:
+ *  Function to get the default values for configuration.
+ */
+int sysmemmgr_setup(struct sysmemmgr_config *config)
+{
+	int status = 0;
+	struct sysmemmgr_static_mem_mgr_obj *smmObj = NULL;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits is
+	 * written with module Id to ensure correctness of ref_count variable.
+	 */
+	atomic_cmpmask_and_set(&sysmemmgr_state.ref_count,
+		SYSMEMMGR_MAKE_MAGICSTAMP(0), SYSMEMMGR_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&sysmemmgr_state.ref_count) != \
+			SYSMEMMGR_MAKE_MAGICSTAMP(1)) {
+		status = SYSMEMMGR_S_ALREADYSETUP;
+		goto exit;
+	}
+
+	if (WARN_ON(config == NULL)) {
+		/* Config parameters are not provided */
+		status = -EINVAL;
+		goto err_config;
+	}
+	if (WARN_ON((config->static_virt_base_addr == (u32) NULL)
+			&& (config->static_mem_size != 0))) {
+		/* Virtual Base address of static memory region is NULL */
+		status = -EINVAL;
+		goto err_virt_addr;
+	}
+	if (WARN_ON((config->static_phys_base_addr == (u32) NULL)
+			&& (config->static_mem_size != 0))) {
+		/*Physical Base address of static memory region is NULL */
+		status = -EINVAL;
+		goto err_phys_addr;
+	}
+
+	/* Copy the config parameters to the module state */
+	memcpy((void *)(&sysmemmgr_state.cfg), (void *) config,
+		sizeof(struct sysmemmgr_config));
+
+	/* Create the static memory allocator */
+	if (config->static_mem_size != 0) {
+		smmObj = &sysmemmgr_state.static_mem_obj;
+		smmObj->head.address = config->static_virt_base_addr;
+		smmObj->head.size = 0;
+		smmObj->tail.address = (config->static_virt_base_addr + \
+						config->static_mem_size);
+		smmObj->tail.size = 0;
+		smmObj->head.next = &smmObj->tail;
+		smmObj->tail.next = NULL;
+	}
+
+	/* Create the lock */
+	sysmemmgr_state.gate_handle = kzalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (sysmemmgr_state.gate_handle == NULL) {
+		/* Failed to create gate handle */
+		status = -ENOMEM;
+		goto err_mem_gate;
+	}
+	return 0;
+
+err_mem_gate:
+	printk(KERN_ERR "sysmemmgr_setup: Failed to create gate handle\n");
+	goto exit;
+
+err_phys_addr:
+	printk(KERN_ERR "sysmemmgr_setup: Physical Base address of static "
+		"memory region is NULL\n");
+	goto exit;
+
+err_virt_addr:
+	printk(KERN_ERR "sysmemmgr_setup: Virtual Base address of static "
+		"memory region is NULL\n");
+	goto exit;
+
+err_config:
+	printk(KERN_ERR "sysmemmgr_setup: Argument of type "
+		"(struct sysmemmgr_config *) passed is NULL\n");
+	goto exit;
+
+exit:
+	if (status < 0) {
+		atomic_set(&sysmemmgr_state.ref_count,
+			SYSMEMMGR_MAKE_MAGICSTAMP(0));
+	}
+	return status;
+}
+
+
+/*
+ * ======== sysmemmgr_destroy ========
+ *  Purpose:
+ *  Function to finalize the system memory manager module.
+ */
+int sysmemmgr_destroy(void)
+{
+	int status = 0;
+
+	if (atomic_cmpmask_and_lt(&(sysmemmgr_state.ref_count),
+		SYSMEMMGR_MAKE_MAGICSTAMP(0), SYSMEMMGR_MAKE_MAGICSTAMP(1)) == \
+		true) {
+		/*! @retval SYSMEMMGR_E_INVALIDSTATE Module was not
+		 *  initialized */
+		status = SYSMEMMGR_E_INVALIDSTATE;
+		goto err_exit;
+	}
+
+	if (atomic_dec_return(&sysmemmgr_state.ref_count) == \
+		SYSMEMMGR_MAKE_MAGICSTAMP(0)) {
+		/* Delete the lock */
+		kfree(sysmemmgr_state.gate_handle);
+	}
+	return 0;
+
+err_exit:
+	printk(KERN_ERR "sysmemgr_destroy: Module was not initialized\n");
+	return status;
+}
+
+
+/*
+ * ======== sysmemmgr_alloc ========
+ *  Purpose:
+ *  Function to allocate a memory block.
+ */
+void *sysmemmgr_alloc(u32 size, enum sysmemmgr_allocflag flag)
+{
+	int status = 0;
+	struct sysmemmgr_static_mem_mgr_obj *smObj  = NULL;
+	struct sysmemmgr_static_mem_struct *ptr = NULL;
+	struct sysmemmgr_static_mem_struct *newptr = NULL;
+	void *ret_ptr = NULL;
+
+	if (atomic_cmpmask_and_lt(&(sysmemmgr_state.ref_count),
+		SYSMEMMGR_MAKE_MAGICSTAMP(0), SYSMEMMGR_MAKE_MAGICSTAMP(1)) == \
+		true) {
+		/*! @retval SYSMEMMGR_E_INVALIDSTATE Module was not
+		 *  initialized */
+		status = SYSMEMMGR_E_INVALIDSTATE;
+		goto err_exit;
+	}
+
+	if ((flag & sysmemmgr_allocflag_physical) && \
+		!(flag & sysmemmgr_allocflag_dma)) {
+		/* TBD: works with DMM
+		ret_ptr = platform_mem_alloc (size, 0,
+			MemoryOS_MemTypeFlags_Physical); */
+		if (ret_ptr == NULL) {
+			if (sysmemmgr_state.cfg.static_mem_size == 0) {
+				/* Memory pool is not configured. */
+				status = -ENOMEM;
+				goto exit;
+			}
+
+			smObj = &sysmemmgr_state.static_mem_obj;
+			ptr = &smObj->head;
+			while (ptr && ptr->next) {
+				if (((ptr->next->address - \
+					(ptr->address + ptr->size)) >= size))
+					break;
+				ptr = ptr->next;
+			}
+
+			if (ptr->next == NULL) {
+				status = -ENOMEM;
+				goto exit;
+			}
+
+			newptr = vmalloc(
+				sizeof(struct sysmemmgr_static_mem_struct));
+			if (newptr != NULL) {
+				newptr->address = ptr->address + ptr->size;
+				newptr->size = size;
+				newptr->next = ptr->next;
+				ptr->next = newptr;
+				ret_ptr = (void *) newptr->address;
+			} else {
+				status = -ENOMEM;
+			}
+		}
+		goto exit;
+	}
+
+	if (flag & sysmemmgr_allocflag_physical) {
+		ret_ptr = kmalloc(size, GFP_KERNEL);
+		if (ret_ptr == NULL)
+			status = -ENOMEM;
+		goto exit;
+	}
+
+	if (flag & sysmemmgr_allocflag_dma) {
+		ret_ptr = kmalloc(size, GFP_KERNEL | GFP_DMA);
+		if (ret_ptr == NULL)
+			status = -ENOMEM;
+		goto exit;
+	}
+
+	ret_ptr = vmalloc(size);
+	if (ret_ptr == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+
+err_exit:
+	printk(KERN_ERR "sysmemgr_alloc: Module was not initialized\n");
+exit:
+	if (WARN_ON(ret_ptr == NULL))
+		printk(KERN_ERR "sysmemmgr_alloc: Allocation failed\n");
+	return ret_ptr;
+}
+
+
+/*
+ * ======== sysmemmgr_free ========
+ *  Purpose:
+ *  Function to de-allocate a previous allocated memory block.
+ */
+int sysmemmgr_free(void *blk, u32 size, enum sysmemmgr_allocflag flag)
+{
+	int status = 0;
+	struct sysmemmgr_static_mem_mgr_obj *smObj = NULL;
+	struct sysmemmgr_static_mem_struct *ptr = NULL;
+	struct sysmemmgr_static_mem_struct *prev = NULL;
+
+	if (atomic_cmpmask_and_lt(&(sysmemmgr_state.ref_count),
+		SYSMEMMGR_MAKE_MAGICSTAMP(0), SYSMEMMGR_MAKE_MAGICSTAMP(1)) == \
+		true) {
+		/*! @retval SYSMEMMGR_E_INVALIDSTATE Module was not
+		 *  initialized */
+		status = SYSMEMMGR_E_INVALIDSTATE;
+		goto err_exit;
+	}
+
+	if ((flag & sysmemmgr_allocflag_physical) && \
+		!(flag & sysmemmgr_allocflag_dma)) {
+		if (((u32) blk >= sysmemmgr_state.cfg.static_virt_base_addr)
+			&& ((u32) blk < \
+			(sysmemmgr_state.cfg.static_virt_base_addr + \
+			sysmemmgr_state.cfg.static_mem_size))) {
+			smObj = &sysmemmgr_state.static_mem_obj;
+			ptr = &smObj->head;
+			while (ptr && ptr->next) {
+				if (ptr->next->address == (u32) blk)
+					break;
+				ptr = ptr->next;
+			}
+			prev = ptr;
+			ptr  = ptr->next;
+			prev->next = ptr->next;
+
+			/* Free the node */
+			vfree(ptr);
+		} else {
+			kfree(blk);
+		}
+	} else if (flag & sysmemmgr_allocflag_physical) {
+		kfree(blk);
+	} else if (flag & sysmemmgr_allocflag_dma) {
+		kfree(blk);
+	} else {
+		vfree(blk);
+	}
+	return 0;
+
+err_exit:
+	printk(KERN_ERR "sysmemgr_free: Module was not initialized\n");
+	return status;
+}
+
+
+/*
+ * ======== sysmemmgr_setup ========
+ *  Purpose:
+ *  Function to translate an address among different address spaces.
+ */
+void *sysmemmgr_translate(void *src_addr, enum sysmemmgr_xltflag flags)
+{
+	void *ret_ptr = NULL;
+
+	switch (flags) {
+	case sysmemmgr_xltflag_kvirt2phys:
+	{
+		if (((u32) src_addr >= \
+			sysmemmgr_state.cfg.static_virt_base_addr) && \
+			((u32) src_addr < \
+			(sysmemmgr_state.cfg.static_virt_base_addr + \
+				sysmemmgr_state.cfg.static_mem_size))) {
+			ret_ptr = (void *)(((u32) src_addr - \
+				sysmemmgr_state.cfg.static_virt_base_addr) + \
+				(sysmemmgr_state.cfg.static_phys_base_addr));
+		} else {
+			ret_ptr = platform_mem_translate(src_addr,
+					PLATFORM_MEM_XLT_FLAGS_VIRT2PHYS);
+		}
+	}
+	break;
+
+	case sysmemmgr_xltflag_phys2kvirt:
+	{
+		if (((u32) src_addr >= \
+			sysmemmgr_state.cfg.static_phys_base_addr) && \
+			((u32) src_addr < \
+			(sysmemmgr_state.cfg.static_phys_base_addr + \
+				sysmemmgr_state.cfg.static_mem_size))) {
+			ret_ptr = (void *)(((u32) src_addr - \
+				sysmemmgr_state.cfg.static_phys_base_addr) + \
+				(sysmemmgr_state.cfg.static_virt_base_addr));
+		} else {
+			ret_ptr = platform_mem_translate(src_addr,
+					PLATFORM_MEM_XLT_FLAGS_PHYS2VIRT);
+		}
+	}
+	break;
+
+	default:
+	{
+		printk(KERN_ALERT "sysmemmgr_translate: Unhandled translation "
+			"flag\n");
+	}
+	break;
+	}
+
+	return ret_ptr;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/sysmemmgr_ioctl.c b/drivers/dsp/syslink/multicore_ipc/sysmemmgr_ioctl.c
new file mode 100644
index 000000000000..591e04849873
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/sysmemmgr_ioctl.c
@@ -0,0 +1,227 @@
+/*
+ *  sysmemmgr_ioctl.c
+ *
+ *  This file implements all the ioctl operations required on the sysmemmgr
+ *  module.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Linux headers */
+#include <linux/uaccess.h>
+#include <linux/bug.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+
+/* Module Headers */
+#include <sysmemmgr.h>
+#include <sysmemmgr_ioctl.h>
+
+
+/*
+ * ======== sysmemmgr_ioctl_get_config ========
+ *  Purpose:
+ *  This ioctl interface to sysmemmgr_get_config function
+ */
+static inline int sysmemmgr_ioctl_get_config(struct sysmemmgr_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct sysmemmgr_config config;
+
+	sysmemmgr_get_config(&config);
+	size = copy_to_user(cargs->args.get_config.config, &config,
+				sizeof(struct sysmemmgr_config));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = 0;
+exit:
+	return retval;
+}
+
+/*
+ * ======== sysmemmgr_ioctl_setup ========
+ *  Purpose:
+ *  This ioctl interface to sysmemmgr_setup function
+ */
+static inline int sysmemmgr_ioctl_setup(struct sysmemmgr_cmd_args *cargs)
+{
+	s32 retval = 0;
+	unsigned long size;
+	struct sysmemmgr_config config;
+
+	if (cargs->args.setup.config == NULL) {
+		cargs->api_status = sysmemmgr_setup(NULL);
+		goto exit;
+	}
+
+	size = copy_from_user(&config, cargs->args.setup.config,
+					sizeof(struct sysmemmgr_config));
+	if (size) {
+		retval = -EFAULT;
+		goto exit;
+	}
+
+	cargs->api_status = sysmemmgr_setup(&config);
+
+exit:
+	return retval;
+}
+
+/*
+ * ======== sysmemmgr_ioctl_destroy ========
+ *  Purpose:
+ *  This ioctl interface to sysmemmgr_destroy function
+ */
+static inline int sysmemmgr_ioctl_destroy(struct sysmemmgr_cmd_args *cargs)
+{
+	cargs->api_status = sysmemmgr_destroy();
+	return 0;
+}
+
+/*
+ * ======== sysmemmgr_ioctl_alloc ========
+ *  Purpose:
+ *  This ioctl interface to sysmemmgr_alloc function
+ */
+static inline int sysmemmgr_ioctl_alloc(struct sysmemmgr_cmd_args *cargs)
+{
+	void *kbuf = NULL;
+	void *phys = NULL;
+
+	kbuf = sysmemmgr_alloc(cargs->args.alloc.size,
+				cargs->args.alloc.flags);
+	if (unlikely(kbuf == NULL))
+		goto exit;
+
+	/* If the flag is not virtually contiguous */
+	if (cargs->args.alloc.flags != sysmemmgr_allocflag_virtual)
+		phys = sysmemmgr_translate(kbuf, sysmemmgr_xltflag_kvirt2phys);
+	cargs->api_status = 0;
+
+exit:
+	cargs->args.alloc.kbuf = kbuf;
+	cargs->args.alloc.kbuf = phys;
+	return 0;
+}
+
+/*
+ * ======== sysmemmgr_ioctl_free ========
+ *  Purpose:
+ *  This ioctl interface to sysmemmgr_free function
+ */
+static inline int sysmemmgr_ioctl_free(struct sysmemmgr_cmd_args *cargs)
+{
+	cargs->api_status = sysmemmgr_free(cargs->args.free.kbuf,
+						cargs->args.free.size,
+						cargs->args.alloc.flags);
+	return 0;
+}
+
+/*
+ * ======== sysmemmgr_ioctl_translate ========
+ *  Purpose:
+ *  This ioctl interface to sysmemmgr_translate function
+ */
+static inline int sysmemmgr_ioctl_translate(struct sysmemmgr_cmd_args *cargs)
+{
+	cargs->args.translate.ret_ptr = sysmemmgr_translate(
+						cargs->args.translate.buf,
+						cargs->args.translate.flags);
+	WARN_ON(cargs->args.translate.ret_ptr == NULL);
+	cargs->api_status = 0;
+	return 0;
+}
+
+/*
+ * ======== sysmemmgr_ioctl ========
+ *  Purpose:
+ *  ioctl interface function for sysmemmgr module
+ */
+int sysmemmgr_ioctl(struct inode *inode, struct file *filp,
+				unsigned int cmd, unsigned long args)
+{
+	int os_status = 0;
+	struct sysmemmgr_cmd_args __user *uarg =
+				(struct sysmemmgr_cmd_args __user *)args;
+	struct sysmemmgr_cmd_args cargs;
+	unsigned long size;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		os_status = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		os_status = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+	if (os_status) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	/* Copy the full args from user-side */
+	size = copy_from_user(&cargs, uarg, sizeof(struct sysmemmgr_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+	switch (cmd) {
+	case CMD_SYSMEMMGR_GETCONFIG:
+		os_status = sysmemmgr_ioctl_get_config(&cargs);
+		break;
+
+	case CMD_SYSMEMMGR_SETUP:
+		os_status = sysmemmgr_ioctl_setup(&cargs);
+		break;
+
+	case CMD_SYSMEMMGR_DESTROY:
+		os_status = sysmemmgr_ioctl_destroy(&cargs);
+		break;
+
+	case CMD_SYSMEMMGR_ALLOC:
+		os_status = sysmemmgr_ioctl_alloc(&cargs);
+		break;
+
+	case CMD_SYSMEMMGR_FREE:
+		os_status = sysmemmgr_ioctl_free(&cargs);
+		break;
+
+	case CMD_SYSMEMMGR_TRANSLATE:
+		os_status = sysmemmgr_ioctl_translate(&cargs);
+		break;
+
+	default:
+		WARN_ON(cmd);
+		os_status = -ENOTTY;
+		break;
+	}
+
+	if ((cargs.api_status == -ERESTARTSYS) || (cargs.api_status == -EINTR))
+		os_status = -ERESTARTSYS;
+
+	if (os_status < 0)
+		goto exit;
+
+	/* Copy the full args to the user-side. */
+	size = copy_to_user(uarg, &cargs, sizeof(struct sysmemmgr_cmd_args));
+	if (size) {
+		os_status = -EFAULT;
+		goto exit;
+	}
+
+exit:
+	return os_status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/sysmgr.c b/drivers/dsp/syslink/multicore_ipc/sysmgr.c
new file mode 100644
index 000000000000..bbf9b4be4b27
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/sysmgr.c
@@ -0,0 +1,846 @@
+/*
+ *  sysmgr.c
+ *
+ *  Implementation of System manager.
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+
+/* Standard headers */
+#include <linux/types.h>
+#include <linux/module.h>
+
+#include <syslink/atomic_linux.h>
+
+/* Module headers */
+#include <multiproc.h>
+#include <sysmemmgr.h>
+#include <sysmgr.h>
+#include <_sysmgr.h>
+#include <platform.h>
+#include <platform_mem.h>
+
+#include <gatepeterson.h>
+#include <sharedregion.h>
+#include <listmp.h>
+#include <messageq.h>
+#include <messageq_transportshm.h>
+#include <notify.h>
+/*#include <notify_driver.h>*/
+#include <notify_ducatidriver.h>
+
+#include <nameserver.h>
+#include <nameserver_remote.h>
+#include <nameserver_remotenotify.h>
+#include <procmgr.h>
+#include <heap.h>
+#include <heapbuf.h>
+
+/* =============================================================================
+ * Macros
+ * =============================================================================
+ */
+/*!
+ *  @def    BOOTLOADPAGESIZE
+ *  @brief  Error code base for System manager.
+ */
+#define BOOTLOADPAGESIZE			(0x1000) /* 4K page size */
+
+/*!
+ *  @def    SYSMGR_ENTRYVALIDITYSTAMP
+ *  @brief  Validity stamp for boot load page entries.
+ */
+#define SYSMGR_ENTRYVALIDITYSTAMP		(0xBABAC0C0)
+
+/*!
+ *  @def    SYSMGR_ENTRYVALIDSTAMP
+ *  @brief  Validity stamp for boot load page entries.
+ */
+#define SYSMGR_ENTRYVALIDSTAMP			(0xBABAC0C0)
+
+/*!
+ *  @def    SYSMGR_SCALABILITYHANDSHAKESTAMP
+ *  @brief  scalability configuration handshake value.
+ */
+#define SYSMGR_SCALABILITYHANDSHAKESTAMP	(0xBEEF0000)
+
+/*!
+ *  @def    SYSMGR_SETUPHANDSHAKESTAMP
+ *  @brief  Platform configured handshake value.
+ */
+#define SYSMGR_SETUPHANDSHAKESTAMP		(0xBEEF0001)
+
+/*!
+ *  @def    SYSMGR_DESTROYHANDSHAKESTAMP
+ *  @brief  Destroy handshake value.
+ */
+#define SYSMGR_DESTROYHANDSHAKESTAMP		(0xBEEF0002)
+
+/*!
+ *  @def    SYSMGR_BOOTLOADPAGESIZE
+ *  @brief  Boot load page size.
+ */
+#define SYSMGR_BOOTLOADPAGESIZE			(0x00001000)
+
+/* Macro to make a correct module magic number with ref_count */
+#define SYSMGR_MAKE_MAGICSTAMP(x)		((SYSMGR_MODULEID << 12) | (x))
+
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+/*! @brief structure for System manager boot load page entry */
+struct sysmgr_bootload_page_entry {
+	VOLATILE u32 offset;
+	/* Offset of next entry (-1 if not present) */
+	VOLATILE u32 valid;
+	/* Validity of the entry */
+	VOLATILE u32 size;
+	/* Size of the entry data */
+	VOLATILE u32 cmd_id;
+	/* Command ID */
+};
+
+/*! @brief structure containg system manager state object */
+struct sysmgr_boot_load_page {
+	VOLATILE struct sysmgr_bootload_page_entry host_config;
+	/* First entry, host specific configuration in the boot load page */
+	u8 padding1[(BOOTLOADPAGESIZE/2) - \
+		sizeof(struct sysmgr_bootload_page_entry)];
+	/* Padding1 */
+	VOLATILE u32 handshake;
+	/* Handshake variable, wrote by slave to indicate configuration done. */
+	VOLATILE struct sysmgr_bootload_page_entry slave_config;
+	/* First entry, slave specific configuration in the boot load page */
+	u8 padding2[(BOOTLOADPAGESIZE/2) - \
+			sizeof(struct sysmgr_bootload_page_entry) - \
+			sizeof(u32)];
+	/* Padding2 */
+};
+
+/*! @brief structure for System manager module state */
+struct sysmgr_module_object {
+	atomic_t ref_count;
+	/* Reference count */
+	struct sysmgr_config config;
+	/* Overall system configuration */
+	struct sysmgr_boot_load_page *boot_load_page[MULTIPROC_MAXPROCESSORS];
+	/* Boot load page of the slaves */
+	bool platform_mem_init_flag;
+	/* Platform memory manager initialize flag */
+	bool multiproc_init_flag;
+	/* Multiproc Initialize flag */
+	bool gatepeterson_init_flag;
+	/* Gatepeterson Initialize flag */
+	bool sharedregion_init_flag;
+	/* Sharedregion Initialize flag */
+	bool listmp_init_flag;
+	/* Listmp Initialize flag */
+	bool messageq_init_flag;
+	/* Messageq Initialize flag */
+	bool notify_init_flag;
+	/* Notify Initialize flag */
+	bool proc_mgr_init_flag;
+	/* Processor manager Initialize flag */
+	bool heapbuf_init_flag;
+	/* Heapbuf Initialize flag */
+	bool nameserver_init_flag;
+	/* Nameserver_remotenotify Initialize flag */
+	bool listmp_sharedmemory_init_flag;
+	/* Listmp_sharedmemory Initialize flag */
+	bool messageq_transportshm_init_flag;
+	/* Messageq_transportshm Initialize flag */
+	bool notify_ducatidrv_init_flag;
+	/* notify_ducatidrv Initialize flag */
+	bool nameserver_remotenotify_init_flag;
+	/* nameserver_remotenotify Initialize flag */
+	bool platform_init_flag;
+	/* Flag to indicate platform initialization status */
+};
+
+
+/* =============================================================================
+ * Globals
+ * =============================================================================
+ */
+/*!
+ *  @var    sysmgr_state
+ *
+ *  @brief  Variable holding state of system manager.
+ */
+static struct sysmgr_module_object sysmgr_state;
+
+
+/* =============================================================================
+ * APIS
+ * =============================================================================
+ */
+/*
+ * ======== sysmgr_get_config ========
+ *  Purpose:
+ *  Function to get the default values for configuration.
+ */
+void sysmgr_get_config(struct sysmgr_config *config)
+{
+	s32 status = 0;
+
+	if (WARN_ON(config == NULL)) {
+		status = -EINVAL;
+		printk(KERN_ALERT "sysmgr_get_config [0x%x] : Argument of type"
+				" (sysmgr_get_config *) passed is null!",
+				status);
+		return;
+	}
+
+	/* Get the gatepeterson default config */
+	multiproc_get_config(&config->multiproc_cfg);
+
+	/* Get the gatepeterson default config */
+	gatepeterson_get_config(&config->gatepeterson_cfg);
+
+	/* Get the sharedregion default config */
+	sharedregion_get_config(&config->sharedregion_cfg);
+
+	/* Get the messageq default config */
+	messageq_get_config(&config->messageq_cfg);
+
+	/* Get the notify default config */
+	notify_get_config(&config->notify_cfg);
+
+	/* Get the proc_mgr default config */
+	proc_mgr_get_config(&config->proc_mgr_cfg);
+
+	/* Get the heapbuf default config */
+	heapbuf_get_config(&config->heapbuf_cfg);
+
+	/* Get the listmp_sharedmemory default config */
+	listmp_sharedmemory_get_config(&config->listmp_sharedmemory_cfg);
+
+	/* Get the messageq_transportshm default config */
+	messageq_transportshm_get_config(&config->messageq_transportshm_cfg);
+
+	/* Get the notify_ducati driver default config */
+	notify_ducatidrv_getconfig(&config->notify_ducatidrv_cfg);
+
+	/* Get the nameserver_remotenotify default config */
+	nameserver_remotenotify_get_config(
+		&config->nameserver_remotenotify_cfg);
+}
+EXPORT_SYMBOL(sysmgr_get_config);
+
+/*
+ * ======== sysmgr_get_object_config ========
+ *  Purpose:
+ *  Function to get the SysMgr Object configuration from Slave.
+ */
+u32 sysmgr_get_object_config(u16 proc_id, void *config, u32 cmd_id, u32 size)
+{
+	struct sysmgr_bootload_page_entry *entry = NULL;
+	u32 offset = 0;
+	u32 ret = 0;
+	struct sysmgr_boot_load_page *blp = NULL;
+
+	if ((proc_id < 0) || (proc_id >= MULTIPROC_MAXPROCESSORS)) {
+		ret = 0;
+		goto exit;
+	}
+
+	blp = (struct sysmgr_boot_load_page *)
+			sysmgr_state.boot_load_page[proc_id];
+
+	entry = (struct sysmgr_bootload_page_entry *) &blp->slave_config;
+	while (entry->valid == SYSMGR_ENTRYVALIDSTAMP) {
+		if (entry->cmd_id == cmd_id) {
+			if (size == entry->size) {
+				memcpy(config, (void *)((u32)entry + \
+				sizeof(struct sysmgr_bootload_page_entry)),
+				size);
+				ret = size;
+				break;
+			}
+		}
+		if (entry->offset != -1) {
+			offset += entry->offset;
+			entry = (struct sysmgr_bootload_page_entry *)
+				((u32) &blp->slave_config + entry->offset);
+		} else {
+			break;
+		}
+	}
+
+exit:
+	/* return number of bytes wrote to the boot load page */
+	return ret;
+}
+
+
+/*
+ * ======== sysmgr_put_object_config ========
+ *  Purpose:
+ *  Function to put the SysMgr Object configuration to Slave.
+ */
+u32 sysmgr_put_object_config(u16 proc_id, void *config, u32 cmd_id, u32 size)
+{
+	struct sysmgr_bootload_page_entry *entry = NULL;
+	struct sysmgr_bootload_page_entry *prev = NULL;
+	u32 offset = 0;
+	struct sysmgr_boot_load_page *blp = NULL;
+
+	if ((proc_id < 0) || (proc_id >= MULTIPROC_MAXPROCESSORS)) {
+		size = 0;
+		goto exit;
+	}
+
+	/* Get the boot load page pointer */
+	blp = sysmgr_state.boot_load_page[proc_id];
+
+	/* Put the entry at the end of list */
+	entry = (struct sysmgr_bootload_page_entry *) &blp->host_config;
+	while (entry->valid == SYSMGR_ENTRYVALIDSTAMP) {
+		prev  = entry;
+		if (entry->offset != -1) {
+			offset += entry->offset;
+			entry = (struct sysmgr_bootload_page_entry *)
+				((u32) &blp->host_config + entry->offset);
+		} else {
+			break;
+		}
+	}
+
+	/* First entry has prev set to NULL */
+	if (prev == NULL) {
+		entry->offset = -1;
+		entry->cmd_id  = cmd_id;
+		entry->size   = size;
+		memcpy((void *)((u32)entry + \
+			sizeof(struct sysmgr_bootload_page_entry)),
+			config, size);
+		entry->valid  = SYSMGR_ENTRYVALIDSTAMP;
+	} else {
+		entry = (struct sysmgr_bootload_page_entry *)((u32)entry + \
+				sizeof(struct sysmgr_bootload_page_entry) + \
+				entry->size);
+		entry->offset = -1;
+		entry->cmd_id = cmd_id;
+		entry->size = size;
+		memcpy((void *)((u32)entry + \
+			sizeof(struct sysmgr_bootload_page_entry)),
+			config, size);
+		entry->valid = SYSMGR_ENTRYVALIDSTAMP;
+
+		/* Attach the new created entry */
+		prev->offset = ((u32) entry - (u32) &blp->host_config);
+	}
+
+exit:
+	/* return number of bytes wrote to the boot load page */
+	return size;
+}
+
+
+/*
+ * ======== sysmgr_setup ========
+ *  Purpose:
+ *  Function to setup the System.
+ */
+s32 sysmgr_setup(const struct sysmgr_config *cfg)
+{
+	s32 status = 0;
+	struct sysmgr_config *config = NULL;
+
+	/* This sets the ref_count variable is not initialized, upper 16 bits is
+	 * written with module Id to ensure correctness of ref_count variable.
+	 */
+	atomic_cmpmask_and_set(&sysmgr_state.ref_count,
+				SYSMGR_MAKE_MAGICSTAMP(0),
+				SYSMGR_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&sysmgr_state.ref_count)
+			!= SYSMGR_MAKE_MAGICSTAMP(1)) {
+		status = 1;
+		goto exit;
+	}
+
+	if (cfg == NULL) {
+		sysmgr_get_config(&sysmgr_state.config);
+		config = &sysmgr_state.config;
+	} else {
+		memcpy((void *) (&sysmgr_state.config), (void *) cfg,
+				sizeof(struct sysmgr_config));
+		config = (struct sysmgr_config *) cfg;
+	}
+
+	/* Initialize PlatformMem */
+	status = platform_mem_setup();
+	if (status < 0) {
+		printk(KERN_ERR "sysmgr_setup : platform_mem_setup "
+			"failed [0x%x]\n", status);
+	} else {
+		printk(KERN_ERR "platform_mem_setup : status [0x%x]\n" ,
+			status);
+		sysmgr_state.platform_mem_init_flag = true;
+	}
+
+	/* Override the platform specific configuration */
+	platform_override_config(config);
+
+	status = multiproc_setup(&(config->multiproc_cfg));
+	if (status < 0) {
+		printk(KERN_ERR "sysmgr_setup : multiproc_setup "
+			"failed [0x%x]\n", status);
+	} else {
+		printk(KERN_ERR "sysmgr_setup : status [0x%x]\n" , status);
+		sysmgr_state.multiproc_init_flag = true;
+	}
+
+	/* Initialize ProcMgr */
+	if (status >= 0) {
+		status = proc_mgr_setup(&(config->proc_mgr_cfg));
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : proc_mgr_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "proc_mgr_setup : status [0x%x]\n" ,
+				status);
+			sysmgr_state.proc_mgr_init_flag = true;
+		}
+	}
+
+	/* Initialize SharedRegion */
+	if (status >= 0) {
+		status = sharedregion_setup(&config->sharedregion_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : sharedregion_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "sharedregion_setup : status [0x%x]\n" ,
+				status);
+			sysmgr_state.sharedregion_init_flag = true;
+		}
+	}
+
+	/* Initialize Notify */
+	if (status >= 0) {
+		status = notify_setup(&config->notify_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : notify_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "notify_setup : status [0x%x]\n" ,
+				status);
+			sysmgr_state.notify_init_flag = true;
+		}
+	}
+
+	/* Initialize NameServer */
+	if (status >= 0) {
+		status = nameserver_setup();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : nameserver_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "nameserver_setup : status [0x%x]\n" ,
+				status);
+			sysmgr_state.nameserver_init_flag = true;
+		}
+	}
+
+	/* Initialize GatePeterson */
+	if (status >= 0) {
+		status = gatepeterson_setup(&config->gatepeterson_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : gatepeterson_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "gatepeterson_setup : status [0x%x]\n" ,
+				status);
+			sysmgr_state.gatepeterson_init_flag = true;
+		}
+	}
+
+	/* Intialize MessageQ */
+	if (status >= 0) {
+		status = messageq_setup(&config->messageq_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : messageq_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "messageq_setup : status [0x%x]\n" ,
+				status);
+			sysmgr_state.messageq_init_flag = true;
+		}
+	}
+
+	/* Intialize HeapBuf */
+	if (status >= 0) {
+		status = heapbuf_setup(&config->heapbuf_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : heapbuf_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "heapbuf_setup : status [0x%x]\n" ,
+				status);
+			sysmgr_state.heapbuf_init_flag = true;
+		}
+	}
+
+	/* Initialize ListMPSharedMemory */
+	if (status >= 0) {
+		status = listmp_sharedmemory_setup(
+				&config->listmp_sharedmemory_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : "
+				"listmp_sharedmemory_setup failed [0x%x]\n",
+				status);
+		} else {
+			printk(KERN_ERR "listmp_sharedmemory_setup : "
+				"status [0x%x]\n" , status);
+			sysmgr_state.listmp_sharedmemory_init_flag = true;
+		}
+	}
+
+	/* Initialize MessageQTransportShm */
+	if (status >= 0) {
+		status = messageq_transportshm_setup(
+				 &config->messageq_transportshm_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : "
+				"messageq_transportshm_setup failed [0x%x]\n",
+				status);
+		} else {
+			printk(KERN_ERR "messageq_transportshm_setup : "
+				"status [0x%x]\n", status);
+			sysmgr_state.messageq_transportshm_init_flag = true;
+		}
+	}
+
+	/* Initialize Notify DucatiDriver */
+	if (status >= 0) {
+		status = notify_ducatidrv_setup(&config->notify_ducatidrv_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : "
+				"notify_ducatidrv_setup failed [0x%x]\n",
+				status);
+		} else {
+			printk(KERN_ERR "notify_ducatidrv_setup : "
+				"status [0x%x]\n" , status);
+			sysmgr_state.notify_ducatidrv_init_flag = true;
+		}
+	}
+
+	/* Initialize NameServerRemoteNotify */
+	if (status >= 0) {
+		status = nameserver_remotenotify_setup(
+				 &config->nameserver_remotenotify_cfg);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : "
+				"nameserver_remotenotify_setup failed [0x%x]\n",
+				status);
+		} else {
+			printk(KERN_ERR "nameserver_remotenotify_setup : "
+				"status [0x%x]\n" , status);
+			sysmgr_state.nameserver_remotenotify_init_flag = true;
+		}
+	}
+
+	if (status >= 0) {
+		/* Call platform setup function */
+		status = platform_setup(config);
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_setup : platform_setup "
+				"failed [0x%x]\n", status);
+		} else {
+			printk(KERN_ERR "platform_setup : status [0x%x]\n" ,
+				status);
+			sysmgr_state.platform_init_flag = true;
+		}
+	}
+
+exit:
+	if (status < 0)
+		atomic_set(&sysmgr_state.ref_count, SYSMGR_MAKE_MAGICSTAMP(0));
+
+	return status;
+}
+EXPORT_SYMBOL(sysmgr_setup);
+
+/*
+ * ======== sysmgr_setup ========
+ *  Purpose:
+ *  Function to finalize the System.
+ */
+s32 sysmgr_destroy(void)
+{
+	s32 status = 0;
+
+	if (atomic_cmpmask_and_lt(&(sysmgr_state.ref_count),
+				SYSMGR_MAKE_MAGICSTAMP(0),
+				SYSMGR_MAKE_MAGICSTAMP(1)) != false) {
+		/*! @retval SYSMGR_E_INVALIDSTATE Module was not initialized */
+		status = SYSMGR_E_INVALIDSTATE;
+		goto exit;
+	}
+
+	if (atomic_dec_return(&sysmgr_state.ref_count)
+			!= SYSMGR_MAKE_MAGICSTAMP(0)) {
+		status = 1;
+		goto exit;
+	}
+
+	/* Finalize Platform module*/
+	if (sysmgr_state.platform_init_flag == true) {
+		status = platform_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : platform_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.platform_init_flag = false;
+		}
+	}
+
+	/* Finalize NameServerRemoteNotify module */
+	if (sysmgr_state.nameserver_remotenotify_init_flag == true) {
+		status = nameserver_remotenotify_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : "
+				"nameserver_remotenotify_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.nameserver_remotenotify_init_flag \
+				= false;
+		}
+	}
+
+	/* Finalize Notify Ducati Driver module */
+	if (sysmgr_state.notify_ducatidrv_init_flag == true) {
+		status = notify_ducatidrv_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : "
+				"notify_ducatidrv_destroy failed [0x%x]\n",
+				status);
+		} else {
+			sysmgr_state.notify_ducatidrv_init_flag = false;
+		}
+	}
+
+	/* Finalize MessageQTransportShm module */
+	if (sysmgr_state.messageq_transportshm_init_flag == true) {
+		status = messageq_transportshm_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : "
+				"messageq_transportshm_destroy failed [0x%x]\n",
+				status);
+		} else {
+			sysmgr_state.messageq_transportshm_init_flag = \
+				false;
+		}
+	}
+
+	/* Finalize ListMPSharedMemory module */
+	if (sysmgr_state.listmp_sharedmemory_init_flag == true) {
+		status = listmp_sharedmemory_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : "
+				"listmp_sharedmemory_destroy failed [0x%x]\n",
+				status);
+		} else {
+			sysmgr_state.listmp_sharedmemory_init_flag = \
+				false;
+		}
+	}
+
+	/* Finalize HeapBuf module */
+	if (sysmgr_state.heapbuf_init_flag == true) {
+		status = heapbuf_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : heapbuf_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.heapbuf_init_flag = false;
+		}
+	}
+
+	/* Finalize MessageQ module */
+	if (sysmgr_state.messageq_init_flag == true) {
+		status = messageq_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : messageq_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.messageq_init_flag = false;
+		}
+	}
+
+	/* Finalize GatePeterson module */
+	if (sysmgr_state.gatepeterson_init_flag == true) {
+		status = gatepeterson_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : "
+				"gatepeterson_destroy failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.gatepeterson_init_flag = false;
+		}
+	}
+
+	/* Finalize NameServer module */
+	if (sysmgr_state.nameserver_init_flag == true) {
+		status = nameserver_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : nameserver_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.nameserver_init_flag = false;
+		}
+	}
+
+	/* Finalize Notify module */
+	if (sysmgr_state.notify_init_flag == true) {
+		status = notify_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : sysmgr_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.notify_init_flag = false;
+		}
+	}
+
+	/* Finalize SharedRegion module */
+	if (sysmgr_state.sharedregion_init_flag == true) {
+		status = sharedregion_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : "
+				"sharedregion_destroy failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.sharedregion_init_flag = false;
+		}
+	}
+
+	/* Finalize ProcMgr module */
+	if (sysmgr_state.proc_mgr_init_flag == true) {
+		status = proc_mgr_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : proc_mgr_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.proc_mgr_init_flag = false;
+		}
+	}
+
+	/* Finalize MultiProc module */
+	if (sysmgr_state.multiproc_init_flag == true) {
+		status = multiproc_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : multiproc_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.proc_mgr_init_flag = false;
+		}
+	}
+
+	/* Finalize PlatformMem module */
+	if (sysmgr_state.platform_mem_init_flag == true) {
+		status = platform_mem_destroy();
+		if (status < 0) {
+			printk(KERN_ERR "sysmgr_destroy : platform_mem_destroy "
+				"failed [0x%x]\n", status);
+		} else {
+			sysmgr_state.platform_mem_init_flag = false;
+		}
+	}
+
+	atomic_set(&sysmgr_state.ref_count, SYSMGR_MAKE_MAGICSTAMP(0));
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "sysmgr_destroy : failed with "
+			"status = [0x%x]\n", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(sysmgr_destroy);
+
+/*
+ * ======== sysmgr_set_boot_load_page ========
+ *  Purpose:
+ *  Function to set the boot load page address for a slave.
+ */
+void sysmgr_set_boot_load_page(u16 proc_id, u32 boot_load_page)
+{
+	struct sysmgr_boot_load_page *temp = \
+		(struct sysmgr_boot_load_page *) boot_load_page;
+
+	if ((proc_id < 0) || (proc_id >= MULTIPROC_MAXPROCESSORS)) {
+		printk(KERN_ERR
+		"sysmgr_set_boot_load_page failed: Invalid proc_id passed\n");
+		return;
+	}
+
+	/* Initialize the host config area */
+	sysmgr_state.boot_load_page[proc_id] = temp;
+	temp->host_config.offset = -1;
+	temp->host_config.valid = 0;
+	temp->handshake = 0;
+}
+
+
+/*
+ * ======== sysmgr_wait_for_scalability_info ========
+ *  Purpose:
+ *  Function to wait for scalability handshake value.
+ */
+void sysmgr_wait_for_scalability_info(u16 proc_id)
+{
+	VOLATILE struct sysmgr_boot_load_page *temp = NULL;
+
+	if ((proc_id < 0) || (proc_id >= MULTIPROC_MAXPROCESSORS)) {
+		printk(KERN_ERR "sysmgr_wait_for_scalability_info failed: "
+			"Invalid proc_id passed\n");
+		return;
+	}
+	temp = sysmgr_state.boot_load_page[proc_id];
+
+	printk(KERN_ERR "sysmgr_wait_for_scalability_info: BF while temp->handshake:%x\n",
+		temp->handshake);
+	while (temp->handshake != SYSMGR_SCALABILITYHANDSHAKESTAMP)
+		;
+	printk(KERN_ERR "sysmgr_wait_for_scalability_info:AF while temp->handshake:%x\n",
+		temp->handshake);
+
+	/* Reset the handshake value for reverse synchronization */
+	temp->handshake = 0;
+}
+
+
+/*
+ * ======== sysmgr_wait_for_slave_setup ========
+ *  Purpose:
+ *  Function to wait for slave to complete setup.
+ */
+void sysmgr_wait_for_slave_setup(u16 proc_id)
+{
+	VOLATILE struct sysmgr_boot_load_page *temp = NULL;
+
+	if ((proc_id < 0) || (proc_id >= MULTIPROC_MAXPROCESSORS)) {
+		printk(KERN_ERR "sysmgr_wait_for_slave_setup failed: "
+			"Invalid proc_id passed\n");
+		return;
+	}
+	temp = sysmgr_state.boot_load_page[proc_id];
+
+	while (temp->handshake != SYSMGR_SETUPHANDSHAKESTAMP)
+		;
+
+	/* Reset the handshake value for reverse synchronization */
+	temp->handshake = 0;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/transportshm.c b/drivers/dsp/syslink/multicore_ipc/transportshm.c
new file mode 100644
index 000000000000..9ce61cf03c6e
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/transportshm.c
@@ -0,0 +1,1160 @@
+/*
+ *  transportshm.c
+ *
+ *  Shared Memory Transport module
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/string.h>
+#include <linux/slab.h>
+
+/* Syslink headers */
+#include <syslink/atomic_linux.h>
+/* Module level headers */
+#include <multiproc.h>
+#include <sharedregion.h>
+#include <nameserver.h>
+#include <gatepeterson.h>
+#include <notify.h>
+#include <messageq.h>
+#include <listmp.h>
+#include <gatemp.h>
+#include <transportshm.h>
+
+/* =============================================================================
+ * Globals
+ * =============================================================================
+ */
+
+/* Indicates that the transport is up. */
+#define TRANSPORTSHM_UP	0xBADC0FFE
+
+/* transportshm Version. */
+#define TRANSPORTSHM_VERSION	1
+
+/*!
+ *  @brief  Macro to make a correct module magic number with refCount
+ */
+#define TRANSPORTSHM_MAKE_MAGICSTAMP(x)                                \
+				((TRANSPORTSHM_MODULEID << 12u) | (x))
+
+#define ROUND_UP(a, b)	(((a) + ((b) - 1)) & (~((b) - 1)))
+
+typedef void (*transportshm_err_fxn)(enum transportshm_reason reason,
+					void *handle,
+					void *msg,
+					u32 info);
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+/*
+ *  Defines the transportshm state object, which contains all the
+ *           module specific information.
+ */
+struct transportshm_module_object {
+	atomic_t ref_count;
+	/* Flag to indicate initialization state of transportshr */
+	struct transportshm_config cfg;
+	/* transportshm configuration structure */
+	struct transportshm_config def_cfg;
+	/* Default module configuration */
+	struct transportshm_params def_inst_params;
+	/* Default instance parameters */
+	void *gate_handle;
+	/* Handle to the gate for local thread safety */
+	void *transports
+		[MULTIPROC_MAXPROCESSORS][MESSAGEQ_NUM_PRIORITY_QUEUES];
+	/* Transport to be set in messageq_register_transport */
+	transportshm_err_fxn err_fxn;
+	/* Error function */
+
+};
+
+/*
+ * Structure of attributes in shared memory
+ */
+struct transportshm_attrs {
+	VOLATILE u32 flag;		/* flag */
+	VOLATILE u32 creator_proc_id;	/* Creator processor ID */
+	VOLATILE u32 notify_event_id;	/* Notify event number */
+	VOLATILE u16 priority;		/* priority */
+	VOLATILE u32 *gatemp_addr;	/* gatemp shared memory srptr */
+};
+
+/*
+ * Structure defining config parameters for the MessageQ transport
+ *  instances.
+ */
+struct transportshm_object {
+	VOLATILE struct transportshm_attrs *self;
+	/* Attributes for local processor in shared memory */
+	VOLATILE struct transportshm_attrs *other;
+	/* Attributes for remote processor in shared memory */
+	void *local_list;
+	/* List for this processor	*/
+	void *remote_list;
+	/* List for remote processor	*/
+	VOLATILE int status;
+	/* Current status		 */
+	u32 alloc_size;
+	/* Shared memory allocated	 */
+	bool cache_enabled;
+	/* Whether to cache calls	 */
+	int notify_event_id;
+	/* Notify event to be used	*/
+	u16 region_id;
+	/* The shared region id		*/
+	u16 remote_proc_id;
+	/* dst proc id			*/
+	u32 priority;
+	/* Priority of messages supported by this transport */
+	void *gate;
+	/* Gate for critical regions	*/
+	struct transportshm_params params;
+	/* Instance specific parameters  */
+};
+
+/* =============================================================================
+ *  Globals
+ * =============================================================================
+ */
+/*
+ *  @var    transportshm_state
+ *
+ * transportshm state object variable
+ */
+static struct transportshm_module_object transportshm_state = {
+	.gate_handle = NULL,
+	.def_cfg.err_fxn = NULL,
+	.def_inst_params.gate = NULL,
+	.def_inst_params.shared_addr = 0x0,
+	.def_inst_params.notify_event_id = (u32)(-1),
+	.def_inst_params.priority = MESSAGEQ_NORMALPRI
+};
+
+/* Pointer to module state */
+static struct transportshm_module_object *transportshm_module =
+							&transportshm_state;
+
+/* =============================================================================
+ * Forward declarations of internal functions
+ * =============================================================================
+ */
+/* Callback function registered with the Notify module. */
+static void _transportshm_notify_fxn(u16 proc_id,
+				     u16 line_id,
+				     u32 event_id,
+				     uint *arg,
+				     u32 payload);
+
+/* Function to create/open the handle. */
+static int _transportshm_create(struct transportshm_object **handle_ptr,
+				u16 proc_id,
+				const struct transportshm_params *params,
+				bool create_flag);
+
+/* =============================================================================
+ * APIs called directly by applications
+ * =============================================================================
+ */
+/*
+ * ======== transportshm_get_config ========
+ *  Purpose:
+ *  Get the default configuration for the transportshm
+ *  module.
+ *
+ *  This function can be called by the application to get their
+ *  configuration parameter to transportshm_setup filled in
+ *  by the transportshm module with the default parameters.
+ *  If the user does not wish to make any change in the default
+ *  parameters, this API is not required to be called.
+ */
+void transportshm_get_config(struct transportshm_config *cfg)
+{
+	if (WARN_ON(cfg == NULL))
+		goto exit;
+
+	if (atomic_cmpmask_and_lt(&(transportshm_module->ref_count),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1)) == true) {
+		memcpy(cfg, &(transportshm_module->def_cfg),
+			sizeof(struct transportshm_config));
+	} else {
+		memcpy(cfg, &(transportshm_module->cfg),
+			sizeof(struct transportshm_config));
+	}
+	return;
+
+exit:
+	printk(KERN_ERR "transportshm_get_config: Argument of type"
+		"(struct transportshm_config *) passed is null!\n");
+}
+
+
+/*
+ * ======== transportshm_setup ========
+ *  Purpose:
+ *  Setup the transportshm module.
+ *
+ *  This function sets up the transportshm module. This
+ *  function must be called before any other instance-level APIs can
+ *  be invoked.
+ *  Module-level configuration needs to be provided to this
+ *  function. If the user wishes to change some specific config
+ *  parameters, then transportshm_getconfig can be called
+ *  to get the configuration filled with the default values. After
+ *  this, only the required configuration values can be changed. If
+ *  the user does not wish to make any change in the default
+ *  parameters, the application can simply call
+ *  transportshm_setup with NULL parameters. The default
+ *  parameters would get automatically used.
+ */
+int transportshm_setup(const struct transportshm_config *cfg)
+{
+	int status = TRANSPORTSHM_SUCCESS;
+	struct transportshm_config tmpCfg;
+
+	/* This sets the refCount variable is not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of refCount variable.
+	*/
+	atomic_cmpmask_and_set(&transportshm_module->ref_count,
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&transportshm_module->ref_count)
+		!= TRANSPORTSHM_MAKE_MAGICSTAMP(1u)) {
+		return 1;
+	}
+
+	if (cfg == NULL) {
+		transportshm_get_config(&tmpCfg);
+		cfg = &tmpCfg;
+	}
+
+	transportshm_module->gate_handle = \
+				kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (transportshm_module->gate_handle == NULL) {
+		/* @retval TRANSPORTSHM_E_FAIL Failed to create
+		GateMutex! */
+		status = TRANSPORTSHM_E_FAIL;
+		printk(KERN_ERR "transportshm_setup: Failed to create "
+			"mutex!\n");
+		atomic_set(&transportshm_module->ref_count,
+				TRANSPORTSHM_MAKE_MAGICSTAMP(0));
+		goto exit;
+	}
+	mutex_init(transportshm_module->gate_handle);
+
+	/* Copy the user provided values into the state object. */
+	memcpy(&transportshm_module->cfg, cfg,
+			sizeof(struct transportshm_config));
+	memset(&(transportshm_module->transports), 0, (sizeof(void *) * \
+		MULTIPROC_MAXPROCESSORS * MESSAGEQ_NUM_PRIORITY_QUEUES));
+	return status;
+
+exit:
+	printk(KERN_ERR "transportshm_setup failed: status = 0x%x",
+		status);
+	return status;
+}
+
+
+/*
+ * ======== transportshm_destroy ========
+ *  Purpose:
+ *  Destroy the transportshm module.
+ *
+ *  Once this function is called, other transportshm module
+ *  APIs, except for the transportshm_getConfig API cannot
+ *  be called anymore.
+ */
+int transportshm_destroy(void)
+{
+	struct transportshm_object *obj = NULL;
+	int status = 0;
+	u16 i;
+	u16 j;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(transportshm_module->ref_count),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (!(atomic_dec_return(&transportshm_module->ref_count)
+				== TRANSPORTSHM_MAKE_MAGICSTAMP(0))) {
+		status = 1;
+		goto exit;
+	}
+
+	/* Temporarily increment ref_count here. */
+	atomic_set(&transportshm_module->ref_count,
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1));
+
+	/* Delete any Transports that have not been deleted so far. */
+	for (i = 0; i < MULTIPROC_MAXPROCESSORS; i++) {
+		for (j = 0 ; j < MESSAGEQ_NUM_PRIORITY_QUEUES; j++) {
+			if (transportshm_module->transports[i][j] != \
+				NULL) {
+				obj = (struct transportshm_object *)
+					transportshm_module->transports[i][j];
+				if (obj->self != NULL) {
+					if (obj->self->creator_proc_id
+							== multiproc_self())
+						transportshm_delete(
+							&(transportshm_module->
+							transports[i][j]));
+					else
+						transportshm_close(
+							&(transportshm_module->
+							transports[i][j]));
+				}
+			}
+		}
+	}
+
+	/* Decrease the ref_count */
+	atomic_set(&transportshm_module->ref_count,
+				TRANSPORTSHM_MAKE_MAGICSTAMP(0));
+
+	if (transportshm_module->gate_handle != NULL) {
+		kfree(transportshm_module->gate_handle);
+		transportshm_module->gate_handle = NULL;
+	}
+	return 0;
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "transportshm_destroy failed: "
+			"status = 0x%x\n", status);
+	return status;
+}
+
+
+/*
+ * ======== transportshm_params_init ========
+ *  Purpose:
+ *  Get Instance parameters
+ */
+void transportshm_params_init(struct transportshm_params *params)
+{
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(transportshm_module->ref_count),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1)) == true)) {
+		printk(KERN_ERR "transportshm_params_init: Module was "
+				" not initialized\n");
+		goto exit;
+	}
+
+	if (WARN_ON(params == NULL)) {
+		printk(KERN_ERR "transportshm_params_init: Argument of"
+				" type (struct transportshm_params *) "
+				"is NULL!");
+		goto exit;
+	}
+
+	memcpy(params, &(transportshm_module->def_inst_params),
+			sizeof(struct transportshm_params));
+
+exit:
+	return;
+}
+
+/*
+ * ======== transportshm_create ========
+ *  Purpose:
+ *  Create a transport instance. This function waits for the remote
+ *  processor to complete its transport creation. Hence it must be
+ *  called only after the remote processor is running.
+ */
+void *transportshm_create(u16 proc_id,
+			const struct transportshm_params *params)
+{
+	struct transportshm_object *handle = NULL;
+	int status = 0;
+
+	BUG_ON(params == NULL);
+	BUG_ON(!(proc_id < multiproc_get_num_processors()));
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(transportshm_module->ref_count),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (WARN_ON(params == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (transportshm_module->transports[proc_id][params->priority] \
+		!= NULL) {
+		/* Specified transport is already registered. */
+		status = MESSAGEQ_E_ALREADYEXISTS;
+		goto exit;
+	}
+
+	status = _transportshm_create(&handle, proc_id, params, true);
+
+	if (status < 0) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	return handle;
+
+exit:
+	printk(KERN_ERR "transportshm_create failed: status = 0x%x\n",
+		status);
+	return handle;
+}
+
+
+/*
+ * ======== transportshm_delete ========
+ *  Purpose:
+ *  Delete instance
+ */
+int transportshm_delete(void **handle_ptr)
+{
+	int status = 0;
+	int tmp_status = 0;
+	struct transportshm_object *handle;
+	u16 proc_id;
+
+	u32 key;
+
+	key = mutex_lock_interruptible(transportshm_state.gate_handle);
+
+	if (key < 0)
+		goto mutex_fail;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(transportshm_module->ref_count),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (WARN_ON(handle_ptr == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(*handle_ptr == NULL)) {
+		status = -EINVAL;
+		printk(KERN_WARNING "transportshm_delete: Invalid NULL"
+			" mqtshm_handle specified! status = 0x%x\n", status);
+		goto exit;
+	}
+
+	handle = (struct transportshm_object *) (*handle_ptr);
+
+	if (handle != NULL) {
+		proc_id = handle->self->creator_proc_id;
+		/* Clear handle in the local array */
+		transportshm_module->
+			transports[proc_id][handle->priority] = NULL;
+		if (handle->self != NULL) {
+			/* clear the self flag */
+			handle->self->flag = 0;
+#if 0
+			if (EXPECT_FALSE(handle->cache_enabled)) {
+				Cache_wbinv((Ptr)&(handle->self->flag),
+					sharedregion_get_cache_line_size(
+							handle->region_id),
+					Cache_Type_ALL,
+					true);
+			}
+#endif
+		}
+
+		if (handle->local_list != NULL) {
+			status = listmp_delete(&handle->local_list);
+
+			if (status < 0)
+				printk(KERN_WARNING "transportshm_delete: "
+					"Failed to delete local listmp "
+					"instance!\n");
+		}
+
+		if (handle->remote_list != NULL) {
+			tmp_status = listmp_close(&handle->remote_list);
+			if ((tmp_status < 0) && (status >= 0)) {
+				status = tmp_status;
+				printk(KERN_WARNING "transportshm_delete: "
+					"Failed to close remote listmp "
+					"instance!\n");
+			}
+		}
+
+		messageq_unregister_transport(handle->
+				remote_proc_id, handle->params.priority);
+
+		tmp_status = notify_unregister_event_single(handle->
+							remote_proc_id,
+						0,
+						handle->notify_event_id);
+		if (tmp_status < 0) {
+			status = tmp_status;
+			printk(KERN_WARNING "transportshm_delete: Failed to "
+				"unregister notify event!\n");
+		}
+
+		kfree(handle);
+		*handle_ptr = NULL;
+	}
+
+	return status;
+
+exit:
+	mutex_unlock(transportshm_state.gate_handle);
+mutex_fail:
+	if (status < 0)
+		printk(KERN_ERR "transportshm_delete failed: "
+			"status = 0x%x\n", status);
+	return status;
+}
+
+/*
+ * ========== transportshm_open_by_addr ===========
+ * Open a transport instance
+ */
+int
+transportshm_open_by_addr(void *shared_addr, void **handle_ptr)
+{
+	int status = 0;
+	struct transportshm_attrs *attrs = NULL;
+	struct transportshm_params params;
+	u16 id;
+
+	BUG_ON(shared_addr == NULL);
+	BUG_ON(handle_ptr == NULL);
+
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(transportshm_module->ref_count),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+
+	if (shared_addr == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	if (handle_ptr == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	attrs = (struct transportshm_attrs *) shared_addr;
+	id = sharedregion_get_id(shared_addr);
+
+	if (id == SHAREDREGION_INVALIDREGIONID) {
+		status = -EFAULT;
+		goto exit;
+	}
+	if (((u32) shared_addr % sharedregion_get_cache_line_size(id) != 0)) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+#if 0
+	/* invalidate the attrs before using it */
+	if (EXPECT_FALSE(SharedRegion_isCacheEnabled(id))) {
+		Cache_inv((Ptr) attrs,
+			sizeof(struct transportshm_attrs),
+			Cache_Type_ALL,
+			true);
+	}
+#endif
+	transportshm_params_init(&params);
+	/* set params field */
+	params.shared_addr = shared_addr;
+	params.notify_event_id = attrs->notify_event_id | \
+						(NOTIFY_SYSTEMKEY << 16);
+	params.priority = attrs->priority;
+
+	if (unlikely(attrs->flag != TRANSPORTSHM_UP)) {
+		status = -EFAULT;
+		*handle_ptr = NULL;
+		goto exit;
+	}
+
+	/* Create the object */
+	status = _transportshm_create((struct transportshm_object **)
+					handle_ptr,
+					attrs->creator_proc_id, &params, false);
+	if (status < 0)
+		goto exit;
+
+	return status;
+
+exit:
+	printk(KERN_ERR "transportshm_open_by_addr failed: status = 0x%x\n",
+		status);
+	return status;
+}
+
+/*
+ * ========== transportshm_close ===========
+ * Close an opened transport instance
+ */
+int
+transportshm_close(void **handle_ptr)
+{
+	int status = 0;
+	int tmp_status = 0;
+	struct transportshm_object *obj;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(transportshm_module->ref_count),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(handle_ptr == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(*handle_ptr == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct transportshm_object *)(*handle_ptr);
+	transportshm_module->transports[obj->remote_proc_id]
+					[obj->params.priority] = NULL;
+
+	if (obj->other != NULL) {
+		/* other flag was set by remote proc */
+		obj->other->flag = 0;
+#if 0
+		if (EXPECT_FALSE(obj->cache_enabled)) {
+			Cache_wbInv(&(obj->other->flag),
+				 sharedregion_get_cache_line_size
+						(obj->region_id),
+				 Cache_Type_ALL,
+				 TRUE);
+		}
+#endif
+	}
+
+	if (obj->gate != NULL) {
+		status = gatemp_close(&obj->gate);
+		if (status < 0) {
+			status = TRANSPORTSHM_E_FAIL;
+			printk(KERN_ERR "transportshm_close: "
+				"gatemp_close failed, status [0x%x]\n",
+				status);
+		}
+	}
+
+	if (obj->local_list != NULL) {
+		tmp_status = listmp_close(&obj->local_list);
+		if ((tmp_status < 0) && (status >= 0)) {
+			status = TRANSPORTSHM_E_FAIL;
+			printk(KERN_ERR "transportshm_close: "
+				"listmp_close(local_list) failed, "
+				"status [0x%x]\n", status);
+		}
+	}
+
+	if (obj->remote_list != NULL) {
+		tmp_status = listmp_close(&obj->remote_list);
+		if ((tmp_status < 0) && (status >= 0)) {
+			status = TRANSPORTSHM_E_FAIL;
+			printk(KERN_ERR "transportshm_close: "
+				"listmp_close(remote_list) failed, "
+				"status [0x%x]\n", status);
+		}
+	}
+
+	messageq_unregister_transport(obj->remote_proc_id,
+					obj->params.priority);
+
+	tmp_status = notify_unregister_event_single(obj->remote_proc_id, 0,
+			(obj->notify_event_id | (NOTIFY_SYSTEMKEY << 16)));
+	if ((tmp_status < 0) && (status >= 0))
+		status = TRANSPORTSHM_E_FAIL;
+
+	kfree(obj);
+	*handle_ptr = NULL;
+exit:
+	if (status < 0)
+		printk(KERN_ERR "transportshm_close failed: status = 0x%x\n",
+								status);
+	return status;
+}
+
+
+/*
+ * ======== transportshm_put ========
+ *  Purpose:
+ *  Put msg to remote list
+*/
+int transportshm_put(void *handle, void *msg)
+{
+	int status = 0;
+	struct transportshm_object *obj = NULL;
+	/*int *key;*/
+
+	if (WARN_ON(atomic_cmpmask_and_lt(
+			&(transportshm_module->ref_count),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(0),
+			TRANSPORTSHM_MAKE_MAGICSTAMP(1)) == true)) {
+		status = -ENODEV;
+		goto exit;
+	}
+	if (WARN_ON(handle == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+	if (WARN_ON(msg == NULL)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	obj = (struct transportshm_object *)handle;
+#if 0
+	/* writeback invalidate the message */
+	if (EXPECT_FALSE(obj->cache_enabled)) {
+		Cache_wbinv((Ptr) msg,
+		 ((MessageQ_Msg)(msg))->msgSize,
+		 Cache_Type_ALL,
+		 true);
+	}
+#endif
+	/* make sure ListMP_put and sendEvent are done before remote executes */
+	/*key = gatemp_enter(obj->gate);*/
+	status = listmp_put_tail(obj->remote_list, (struct listmp_elem *) msg);
+	if (status < 0) {
+		printk(KERN_ERR "transportshm_put: Failed to put "
+			"message in the shared list! status = 0x%x\n", status);
+		goto exit_with_gate;
+	}
+
+	status = notify_send_event(obj->remote_proc_id, 0,
+				obj->notify_event_id, 0, false);
+	if (status < 0)
+		goto notify_send_fail;
+	else
+		goto exit_with_gate;
+
+
+notify_send_fail:
+	printk(KERN_ERR "transportshm_put: Notification to remote "
+		"processor failed, status = 0x%x\n", status);
+	/* If sending the event failed, then remove the element from the */
+	/* list.  Ignore the status of remove. */
+	listmp_remove(obj->remote_list, (struct listmp_elem *) msg);
+
+exit_with_gate:
+	/*gatemp_leave(obj->gate, key);*/
+exit:
+	if (status < 0)
+		printk(KERN_ERR "transportshm_put failed: "
+			"status = 0x%x\n", status);
+	return status;
+}
+
+/*
+ * ======== transportshm_control ========
+ *  Purpose:
+ *  Control Function
+*/
+int transportshm_control(void *handle, u32 cmd, u32 *cmd_arg)
+{
+	BUG_ON(handle == NULL);
+
+	printk(KERN_ALERT "transportshm_control not supported!\n");
+	return TRANSPORTSHM_E_NOTSUPPORTED;
+}
+
+/*
+ * ======== transportshm_get_status ========
+ *  Purpose:
+ *  Get status
+ */
+enum transportshm_status transportshm_get_status(void *handle)
+{
+	struct transportshm_object *obj = \
+			(struct transportshm_object *) handle;
+
+	BUG_ON(obj == NULL);
+
+	return obj->status;
+}
+
+/*
+ * ======== transportshm_put ========
+ *  Purpose:
+ *  Get shared memory requirements.
+ */
+u32 transportshm_shared_mem_req(const struct transportshm_params *params)
+{
+	u32 mem_req = 0;
+	s32 min_align;
+	u16 region_id;
+	struct listmp_params list_params;
+	s32 status = 0;
+
+	if (params == NULL) {
+		status = -EINVAL;
+		goto exit;
+	}
+	region_id = sharedregion_get_id(params->shared_addr);
+
+	if (region_id == SHAREDREGION_INVALIDREGIONID)  {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	min_align = 4; /*memory_get_max_default_type_align(); */
+	if (sharedregion_get_cache_line_size(region_id) > min_align)
+		min_align = sharedregion_get_cache_line_size(region_id);
+
+	/* for the Attrs structure */
+	mem_req = ROUND_UP(sizeof(struct transportshm_attrs), min_align);
+
+	/* for the second Attrs structure */
+	mem_req += ROUND_UP(sizeof(struct transportshm_attrs), min_align);
+
+	listmp_params_init(&list_params);
+	list_params.region_id = region_id;
+	/* for local listMP */
+	mem_req += listmp_shared_mem_req(&list_params);
+
+	/* for remote listMP */
+	mem_req += listmp_shared_mem_req(&list_params);
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "transportshm_shared_mem_req failed: "
+			"status = 0x%x\n", status);
+
+	return mem_req;
+}
+
+
+/* =============================================================================
+ * internal functions
+ * =============================================================================
+ */
+/*
+ * ======== _transportshm_notify_fxn ========
+ *  Purpose:
+ *  Callback function registered with the Notify module.
+ */
+void _transportshm_notify_fxn(u16 proc_id, u16 line_id, u32 event_no,
+					uint *arg, u32 payload)
+{
+	struct transportshm_object *obj = NULL;
+	messageq_msg msg = NULL;
+	u32 queue_id;
+	u32 key;
+
+	key = mutex_lock_interruptible(transportshm_state.gate_handle);
+
+	if (key < 0)
+		goto mutex_fail;
+
+	if (WARN_ON(arg == NULL))
+		goto exit;
+
+	obj = (struct transportshm_object *)arg;
+	/*  While there is are messages, get them out and send them to
+	 *  their final destination. */
+	if (obj->local_list)
+		msg = (messageq_msg) listmp_get_head(obj->local_list);
+	else
+		goto exit;
+	while (msg != NULL) {
+		/* Get the destination message queue Id */
+		queue_id = messageq_get_dst_queue(msg);
+
+		/* put the message to the destination queue */
+		messageq_put(queue_id, msg);
+		if (obj->local_list)
+			msg = (messageq_msg)
+				listmp_get_head(obj->local_list);
+		else
+			msg = NULL;
+	}
+	mutex_unlock(transportshm_state.gate_handle);
+	return;
+
+exit:
+	mutex_unlock(transportshm_state.gate_handle);
+mutex_fail:
+	printk(KERN_ERR "transportshm_notify_fxn: argument passed is "
+		"NULL!\n");
+	return;
+}
+
+
+/*
+ * ======== transportshm_delete ========
+ *  Purpose:
+ *  This will set the asynchronous error function for the transport module
+ */
+void transportshm_set_err_fxn(	void (*err_fxn)(
+				enum transportshm_reason reason,
+				void *handle,
+				void *msg,
+				u32 info))
+{
+	int key;
+
+	key = mutex_lock_interruptible(transportshm_module->gate_handle);
+	if (key < 0)
+		goto exit;
+
+	transportshm_module->cfg.err_fxn = err_fxn;
+	mutex_unlock(transportshm_module->gate_handle);
+
+exit:
+	return;
+}
+
+
+/*
+ * ========= _transportshm_create =========
+ *  Purpose:
+ *  Internal function for create()/open()
+ */
+int _transportshm_create(struct transportshm_object **handle_ptr, u16 proc_id,
+		const struct transportshm_params *params, bool create_flag)
+{
+	int status = 0;
+	struct transportshm_object *handle = NULL;
+	void *local_addr = NULL;
+	int local_index;
+	int remote_index;
+	u32 min_align;
+	struct listmp_params listmp_params[2];
+
+	BUG_ON(handle_ptr == NULL);
+	BUG_ON(params == NULL);
+	BUG_ON(proc_id >= multiproc_get_num_processors());
+
+	/*
+	 *  Determine who gets the '0' slot and who gets the '1' slot
+	 *  The '0' slot is given to the lower multiproc id.
+	 */
+	if (multiproc_self() < proc_id) {
+		local_index = 0;
+		remote_index = 1;
+	} else {
+		local_index = 1;
+		remote_index = 0;
+	}
+
+	handle = kzalloc(sizeof(struct transportshm_object), GFP_KERNEL);
+	if (handle == NULL) {
+		status = -ENOMEM;
+		goto exit;
+	}
+	*handle_ptr = handle;
+
+	if (create_flag == false) {
+		/* Open by shared addr */
+		handle->self = (struct transportshm_attrs *)
+							params->shared_addr;
+		handle->region_id = sharedregion_get_id(params->shared_addr);
+		BUG_ON(handle->region_id == SHAREDREGION_INVALIDREGIONID);
+
+		handle->cache_enabled = sharedregion_is_cache_enabled(handle->
+								region_id);
+
+		local_addr = sharedregion_get_ptr((u32 *)handle->self->
+								gatemp_addr);
+		BUG_ON(local_addr == NULL);
+
+		status = gatemp_open_by_addr(local_addr, &handle->gate);
+		if (status < 0) {
+			status = -EFAULT;
+			goto exit;
+		}
+	} else {
+		/* Init the gate for ListMP create below */
+		if (params->gate != NULL)
+			handle->gate = params->gate;
+		else
+			handle->gate = gatemp_get_default_remote();
+
+		if (handle->gate == NULL) {
+			status = -EFAULT;
+			goto exit;
+		}
+		memcpy(&(handle->params), params,
+				sizeof(struct transportshm_params));
+		handle->region_id = sharedregion_get_id(params->shared_addr);
+
+		/* Assert that the buffer is in a valid shared
+		 * region
+		 */
+		if (handle->region_id == SHAREDREGION_INVALIDREGIONID) {
+			status = -EFAULT;
+			goto exit;
+		}
+		if (((u32)params->shared_addr
+			% sharedregion_get_cache_line_size(handle->region_id)
+			!= 0)) {
+			status = -EFAULT;
+			goto exit;
+		}
+
+		/* set handle's cache_enabled, type, attrs */
+		handle->cache_enabled = sharedregion_is_cache_enabled(
+							handle->region_id);
+		handle->self = (struct transportshm_attrs *)
+							params->shared_addr;
+	}
+
+	/* Determine the minimum alignment to align to */
+	min_align = 4; /*memory_get_max_default_type_align(); */
+	if (sharedregion_get_cache_line_size(handle->region_id) > min_align)
+		min_align = sharedregion_get_cache_line_size(handle->
+								region_id);
+	/*
+	 *  Carve up the shared memory.
+	 *  If cache is enabled, these need to be on separate cache
+	 *  lines. This is done with min_align and ROUND_UP function.
+	 */
+
+	handle->other = (struct transportshm_attrs *)(((u32)handle->self) +
+		(ROUND_UP(sizeof(struct transportshm_attrs), min_align)));
+
+
+	listmp_params_init(&(listmp_params[0]));
+	listmp_params[0].gatemp_handle = handle->gate;
+	listmp_params[0].shared_addr = (void *)(((u32)handle->other)
+		 + (ROUND_UP(sizeof(struct transportshm_attrs), min_align)));
+
+	listmp_params_init(&listmp_params[1]);
+	listmp_params[1].gatemp_handle = handle->gate;
+	listmp_params[1].shared_addr = (void *)
+			(((u32)listmp_params[0].shared_addr)
+			+ listmp_shared_mem_req(&listmp_params[0]));
+
+	handle->notify_event_id = params->notify_event_id;
+	handle->priority = params->priority;
+	handle->remote_proc_id = proc_id;
+
+	if (create_flag == true) {
+		handle->local_list =
+				listmp_create(&(listmp_params[local_index]));
+		if (handle->local_list == NULL) {
+			status = -EFAULT;
+			goto exit;
+		}
+		handle->remote_list = listmp_create(
+					&(listmp_params[remote_index]));
+		if (handle->remote_list == NULL) {
+			status = -EFAULT;
+			goto exit;
+		}
+	} else {
+		/* Open the local ListMP instance */
+		status = listmp_open_by_addr(
+				listmp_params[local_index].shared_addr,
+				&(handle->local_list));
+		if (status < 0) {
+			status = -EFAULT;
+			goto exit;
+		}
+
+		status = listmp_open_by_addr(
+				listmp_params[remote_index].shared_addr,
+				&(handle->remote_list));
+		if (status < 0) {
+			status = -EFAULT;
+			goto exit;
+		}
+	}
+
+	status = notify_register_event_single(proc_id,
+						0, /* lineId */
+						params->notify_event_id,
+						_transportshm_notify_fxn,
+						handle);
+	if (status < 0) {
+		status = -EFAULT;
+		goto exit;
+	}
+
+	if (create_flag == true) {
+		handle->self->creator_proc_id = multiproc_self();
+		handle->self->notify_event_id = handle->notify_event_id;
+		handle->self->priority = handle->priority;
+
+		/* Store the GateMP shared_addr in the Attrs */
+		handle->self->gatemp_addr =
+					gatemp_get_shared_addr(handle->gate);
+		handle->self->flag = TRANSPORTSHM_UP;
+#if 0
+		if (EXPECT_FALSE(handle->cache_enabled)) {
+			Cache_wbinv((Ptr) handle->self,
+				     sizeof(struct transportshm_attrs),
+				     Cache_Type_ALL,
+				     true);
+		}
+#endif
+	} else {
+		handle->other->flag = TRANSPORTSHM_UP;
+#if 0
+		if (EXPECT_FALSE(handle->cache_enabled)) {
+			Cache_wb((Ptr)&(handle->other->flag),
+				min_align,
+				Cache_Type_ALL,
+				true);
+		}
+#endif
+	}
+
+	/* Register the transport with MessageQ */
+	status = messageq_register_transport(handle, proc_id,
+							params->priority);
+	if (status < 0) {
+		status = -EFAULT;
+		goto exit;
+	}
+	handle->status = TRANSPORTSHM_UP;
+	/* Set handle in the local array. */
+	transportshm_module->transports[handle->remote_proc_id]
+		[handle->params.priority] = handle;
+
+	return status;
+
+exit:
+	/* Cleanup in case of error. */
+	if (create_flag == true)
+		transportshm_delete((void **)handle_ptr);
+	else
+		transportshm_close((void **)handle_ptr);
+
+	return status;
+}
diff --git a/drivers/dsp/syslink/multicore_ipc/transportshm_setup.c b/drivers/dsp/syslink/multicore_ipc/transportshm_setup.c
new file mode 100644
index 000000000000..d41e8b5749d6
--- /dev/null
+++ b/drivers/dsp/syslink/multicore_ipc/transportshm_setup.c
@@ -0,0 +1,205 @@
+/*
+ *  transportshm_setup.c
+ *
+ *  Shared Memory Transport setup module
+ *
+ *  Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+/* Standard headers */
+#include <linux/types.h>
+
+/* Utilities headers */
+#include <linux/string.h>
+#include <linux/slab.h>
+
+/* Syslink headers */
+#include <syslink/atomic_linux.h>
+/* Module level headers */
+#include <multiproc.h>
+#include <sharedregion.h>
+#include <nameserver.h>
+#include <gatepeterson.h>
+#include <notify.h>
+#include <messageq.h>
+#include <listmp.h>
+#include <gatemp.h>
+#include <transportshm.h>
+
+/* =============================================================================
+ * Structures & Enums
+ * =============================================================================
+ */
+/* structure for transportshm_setup module state */
+struct transportshm_setup_module_object {
+	void *handles[MULTIPROC_MAXPROCESSORS];
+	/* Store a handle per remote proc */
+};
+
+
+/* =============================================================================
+ *  Globals
+ * =============================================================================
+ */
+static struct transportshm_setup_module_object transportshm_setup_state = {
+	.handles[0] = NULL
+};
+
+/* Pointer to the transportshm_setup module state */
+static struct transportshm_setup_module_object *transportshm_setup_module =
+						&transportshm_setup_state;
+
+
+/* =============================================================================
+ *  Functions
+ * =============================================================================
+ */
+/*
+ * =========== transportshm_setup_attach ===========
+ * Function that will be called in messageq_attach.  Creates a
+ * transportshm object for a given processor
+ */
+int transportshm_setup_attach(u16 remote_proc_id, u32 *shared_addr)
+{
+	s32 status = 0;
+	struct transportshm_params params;
+	void *handle;
+
+	BUG_ON(remote_proc_id >= MULTIPROC_MAXPROCESSORS);
+
+	if (WARN_ON(unlikely(shared_addr == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	/* Init the transport parameters */
+	transportshm_params_init(&params);
+	params.gate = gatemp_get_default_remote();
+	params.shared_addr = shared_addr;
+
+	/* Make sure notify driver has been created */
+	if (unlikely(notify_is_registered(remote_proc_id, 0) == false)) {
+		status = TRANSPORTSHM_E_FAIL;
+		goto exit;
+	}
+
+	if (multiproc_self() < remote_proc_id) {
+		handle = transportshm_create(remote_proc_id, &params);
+		if (unlikely(handle == NULL)) {
+			status = TRANSPORTSHM_E_FAIL;
+			goto exit;
+		}
+
+		transportshm_setup_module->handles[remote_proc_id] = handle;
+	} else {
+		status = transportshm_open_by_addr(params.shared_addr, &handle);
+		if (status < 0)
+			goto exit;
+
+		transportshm_setup_module->handles[remote_proc_id] = handle;
+	}
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "transportshm_setup_attach failed! status "
+			"= 0x%x", status);
+	return status;
+}
+
+/*
+ * =========== transportshm_setup_detach ===========
+ * Function that will be called in messageq_detach.  Deletes a
+ * transportshm object created by transportshm_setup_attach.
+ */
+int transportshm_setup_detach(u16 remote_proc_id)
+{
+	int status = 0;
+	void *handle = NULL;
+
+	if (WARN_ON(remote_proc_id >= MULTIPROC_MAXPROCESSORS)) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	handle = transportshm_setup_module->handles[remote_proc_id];
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = -EINVAL;
+		goto exit;
+	}
+
+	if (multiproc_self() < remote_proc_id) {
+		/* Delete the transport */
+		status = transportshm_delete(&handle);
+		if (unlikely(status < 0)) {
+			status = TRANSPORTSHM_E_FAIL;
+			goto exit;
+		}
+		transportshm_setup_module->handles[remote_proc_id] = NULL;
+	} else {
+		status = transportshm_close(&handle);
+		if (unlikely(status < 0)) {
+			status = TRANSPORTSHM_E_FAIL;
+			goto exit;
+		}
+		transportshm_setup_module->handles[remote_proc_id] = NULL;
+	}
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "transportshm_setup_detach failed! status "
+			"= 0x%x", status);
+	return status;
+}
+
+
+/*
+ * =========== transportshm_setup_shared_mem_req ===========
+ * Function that returns the amount of shared memory required
+ */
+u32 transportshm_setup_shared_mem_req(u32 *shared_addr)
+{
+	u32 mem_req = 0x0;
+	int status = 0;
+	struct transportshm_params params;
+
+	/* Don't do anything if only 1 processor in system */
+	if (likely(multiproc_get_num_processors() != 1)) {
+		BUG_ON(shared_addr == NULL);
+
+		if (unlikely(shared_addr == NULL)) {
+			status = -EINVAL;
+			goto exit;
+		}
+
+		transportshm_params_init(&params);
+		params.shared_addr = shared_addr;
+
+		mem_req += transportshm_shared_mem_req(&params);
+	}
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "transportshm_setup_shared_mem_req failed! "
+			"status = 0x%x", status);
+	return mem_req;
+}
+
+/* Determines if a transport has been registered to a remote processor */
+bool transportshm_setup_is_registered(u16 remote_proc_id)
+{
+	bool registered;
+
+	registered = (transportshm_setup_module->handles[remote_proc_id] !=
+				NULL);
+
+	return registered;
+}
diff --git a/drivers/dsp/syslink/notify_ducatidriver/notify_ducati.c b/drivers/dsp/syslink/notify_ducatidriver/notify_ducati.c
new file mode 100644
index 000000000000..048898e83dbc
--- /dev/null
+++ b/drivers/dsp/syslink/notify_ducatidriver/notify_ducati.c
@@ -0,0 +1,1330 @@
+/*
+ * notify_ducati.c
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#include <linux/spinlock.h>
+#include <linux/semaphore.h>
+#include <linux/timer.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <plat/mailbox.h>
+
+#include <syslink/multiproc.h>
+#include <syslink/atomic_linux.h>
+#include <syslink/sharedregion.h>
+#include <syslink/notify_driver.h>
+#include <syslink/notifydefs.h>
+#include <syslink/notify_driverdefs.h>
+#include <syslink/notify_ducatidriver.h>
+
+
+
+#define NOTIFYDUCATIDRIVER_MEM_ALIGN	0
+
+#define NOTIFYDUCATIDRIVER_MAX_EVENTS	32
+
+#define NOTIFYNONSHMDRV_MAX_EVENTS	1
+
+#define NOTIFYNONSHMDRV_RESERVED_EVENTS	1
+
+#define NOTIFYDRV_DUCATI_RECV_MBX	2
+
+#define NOTIFYDRV_DUCATI_SEND_MBX	3
+
+/* Get address of event entry. */
+#define EVENTENTRY(event_chart, align, event_id)			\
+			((struct notify_ducatidrv_event_entry *)	\
+			((u32)event_chart + (align * event_id)));
+
+/* Stamp indicating that the Notify Shared Memory driver on the
+ * processor has been initialized. */
+#define NOTIFYDUCATIDRIVER_INIT_STAMP	0xA9C8B7D6
+
+/* Flag indicating event is set. */
+#define NOTIFYDUCATIDRIVER_UP		1
+
+/* Flag indicating event is not set. */
+#define NOTIFYDUCATIDRIVER_DOWN		0
+
+/*FIX ME: Make use of Multi Proc module */
+#define SELF_ID		0
+
+#define OTHER_ID	1
+
+#define PROC_TESLA	0
+#define PROC_DUCATI	1
+#define PROC_GPP	2
+#define PROCSYSM3	2
+#define PROCAPPM3	3
+#define MAX_SUBPROC_EVENTS	15
+
+/* Macro to make a correct module magic number with refCount */
+#define NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(x) \
+				((NOTIFY_DUCATIDRIVER_MODULEID << 12u) | (x))
+
+#define ROUND_UP(a, b)	(((a) + ((b) - 1)) & (~((b) - 1)))
+
+static struct omap_mbox *ducati_mbox;
+static int notify_ducatidrv_isr(void *ntfy_msg);
+static bool notify_ducatidrv_isr_callback(void *ref_data, void* ntfy_msg);
+
+
+/* Defines the notify_ducatidrv state object, which contains all
+ * the module specific information. */
+struct notify_ducatidrv_module {
+	atomic_t ref_count;
+	/* Reference count */
+	struct notify_ducatidrv_config cfg;
+	/* NotifyDriverShm configuration structure */
+	struct notify_ducatidrv_config def_cfg;
+	/* Default module configuration */
+	struct notify_ducatidrv_params def_inst_params;
+	/* Default instance parameters */
+	struct mutex *gate_handle;
+	/* Handle to the gate for local thread safety */
+	struct notify_ducatidrv_object *driver_handles
+				[MULTIPROC_MAXPROCESSORS][NOTIFY_MAX_INTLINES];
+	/* Loader handle array. */
+	atomic_t mbox_ref_count;
+	/* Reference count for enabling/disabling mailbox interrupt */
+};
+
+/* Notify ducati driver instance object. */
+struct notify_ducatidrv_object {
+	struct notify_ducatidrv_params params;
+	/* Instance parameters (configuration values) */
+	VOLATILE struct notify_ducatidrv_proc_ctrl *self_proc_ctrl;
+	/* Pointer to control structure in shared memory for self processor. */
+	VOLATILE struct notify_ducatidrv_proc_ctrl *other_proc_ctrl;
+	/* Pointer to control structure in shared memory for remote processor.*/
+	VOLATILE struct notify_ducatidrv_event_entry *self_event_chart;
+	/* Pointer to event chart for local processor */
+	VOLATILE struct notify_ducatidrv_event_entry *other_event_chart;
+	/* Pointer to event chart for remote processor */
+	u32 reg_chart[NOTIFY_MAXEVENTS];
+	/* Local event registration chart for tracking registered events. */
+	u16 self_id;
+	/* Self ID used for identification of local control region */
+	u16 other_id;
+	/* Other ID used for identification of remote control region */
+	u16 remote_proc_id;
+	/* Processor ID of the remote processor which which this driver instance
+	 communicates. */
+	struct notify_driver_object *drv_handle;
+	/* Common NotifyDriver handle */
+	u32 nesting;
+	/* For disable/restore nesting */
+	u32 cache_enabled;
+	/* Whether to perform cache calls */
+	u32 event_entry_size;
+	/* Spacing between event entries   */
+	u32 num_events;
+	/* Number of events configured */
+};
+
+
+static struct notify_ducatidrv_module notify_ducatidriver_state = {
+	.gate_handle = NULL,
+	.def_inst_params.shared_addr = 0x0,
+	.def_inst_params.cache_enabled = false,
+	.def_inst_params.cache_line_size = 128u,
+	.def_inst_params.remote_proc_id = MULTIPROC_INVALIDID,
+	.def_inst_params.line_id = 0,
+	.def_inst_params.local_int_id = (u32) -1,
+	.def_inst_params.remote_int_id = (u32) -1
+};
+
+/* Get the default configuration for the notify_ducatidrv module. */
+void notify_ducatidrv_get_config(struct notify_ducatidrv_config *cfg)
+{
+	int status = NOTIFY_S_SUCCESS;
+
+	if (WARN_ON(unlikely(cfg == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	if (atomic_cmpmask_and_lt(&(notify_ducatidriver_state.ref_count),
+					NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0),
+					NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(1))
+					== true)
+		memcpy(cfg, &(notify_ducatidriver_state.def_cfg),
+			sizeof(struct notify_ducatidrv_config));
+	else
+		memcpy(cfg, &(notify_ducatidriver_state.cfg),
+			sizeof(struct notify_ducatidrv_config));
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_get_config failed! "
+			"status = 0x%x", status);
+	}
+	return;
+}
+EXPORT_SYMBOL(notify_ducatidrv_get_config);
+
+/* Setup the notify_ducatidrv module. */
+int notify_ducatidrv_setup(struct notify_ducatidrv_config *cfg)
+{
+	int status = 0;
+	struct notify_ducatidrv_config tmp_cfg;
+	u16 i;
+	u16 j;
+
+	/* Init the ref_count to 0 */
+	atomic_cmpmask_and_set(&(notify_ducatidriver_state.ref_count),
+					NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0),
+					NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&(notify_ducatidriver_state.ref_count)) !=
+		NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(1u)) {
+		return NOTIFY_S_ALREADYSETUP;
+	}
+	atomic_set(&(notify_ducatidriver_state.mbox_ref_count), 0);
+
+	if (cfg == NULL) {
+		notify_ducatidrv_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	/* Create a default gate handle here */
+	notify_ducatidriver_state.gate_handle =
+			kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (notify_ducatidriver_state.gate_handle == NULL) {
+		status = NOTIFY_E_MEMORY;
+		goto error_exit;
+	}
+	mutex_init(notify_ducatidriver_state.gate_handle);
+
+	for (i = 0 ; i < MULTIPROC_MAXPROCESSORS; i++)
+		for (j = 0 ; j < NOTIFY_MAX_INTLINES; j++)
+			notify_ducatidriver_state.driver_handles[i][j] = NULL;
+
+	memcpy(&notify_ducatidriver_state.cfg, cfg,
+			sizeof(struct notify_ducatidrv_config));
+
+	/* Initialize the maibox module for Ducati */
+	if (ducati_mbox == NULL) {
+		ducati_mbox = omap_mbox_get("mailbox-2");
+		if (ducati_mbox == NULL) {
+			printk(KERN_ERR "Failed in omap_mbox_get()\n");
+			status = NOTIFY_E_INVALIDSTATE;
+			goto error_mailbox_get_failed;
+		}
+		ducati_mbox->rxq->callback =
+				(int (*)(void *))notify_ducatidrv_isr;
+	}
+	return 0;
+
+error_mailbox_get_failed:
+	kfree(notify_ducatidriver_state.gate_handle);
+error_exit:
+	atomic_set(&(notify_ducatidriver_state.ref_count),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0));
+	printk(KERN_ERR "notify_ducatidrv_setup failed! status = 0x%x", status);
+	return status;
+}
+EXPORT_SYMBOL(notify_ducatidrv_setup);
+
+/* Destroy the notify_ducatidrv module. */
+int notify_ducatidrv_destroy(void)
+{
+	int status = NOTIFY_S_SUCCESS;
+	u16 i;
+	u16 j;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(notify_ducatidriver_state.ref_count),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (!(atomic_dec_return(&notify_ducatidriver_state.ref_count) == \
+				NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0)))
+		return NOTIFY_S_ALREADYSETUP;
+
+	/* Temporarily increment the refcount */
+	atomic_set(&(notify_ducatidriver_state.ref_count),
+					NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(1));
+
+	for (i = 0 ; i < MULTIPROC_MAXPROCESSORS; i++) {
+		for (j = 0 ; j < NOTIFY_MAX_INTLINES; j++) {
+			if (notify_ducatidriver_state.driver_handles[i][j] != \
+				NULL) {
+				notify_ducatidrv_delete(
+					&notify_ducatidriver_state.\
+						driver_handles[i][j]);
+			}
+		}
+	}
+
+	if (notify_ducatidriver_state.gate_handle != NULL)
+		kfree(notify_ducatidriver_state.gate_handle);
+
+	atomic_set(&(notify_ducatidriver_state.ref_count),
+		NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0));
+
+	/* Finalize the maibox module for Ducati */
+	omap_mbox_put(ducati_mbox);
+	ducati_mbox = NULL;
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_destroy failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(notify_ducatidrv_destroy);
+
+/* Function to initialize the parameters for this notify_ducatidrv instance. */
+void notify_ducatidrv_params_init(struct notify_ducatidrv_params *params)
+{
+	int status = NOTIFY_S_SUCCESS;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(notify_ducatidriver_state.ref_count),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	/*Return updated notify_ducatidrv instance specific parameters*/
+	memcpy(params, &(notify_ducatidriver_state.def_inst_params),
+		sizeof(struct notify_ducatidrv_params));
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_params_init failed! "
+			"status = 0x%x", status);
+	}
+	return;
+}
+EXPORT_SYMBOL(notify_ducatidrv_params_init);
+
+/* Function to create an instance of this Notify ducati driver. */
+struct notify_ducatidrv_object *notify_ducatidrv_create(
+				const struct notify_ducatidrv_params *params)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_object *obj = NULL;
+	struct notify_driver_object *drv_handle = NULL;
+	struct notify_driver_fxn_table fxn_table;
+	u32 i;
+	u16 region_id;
+	uint region_cache_size;
+	uint min_align;
+	struct notify_ducatidrv_event_entry *event_entry;
+	u32 proc_ctrl_size;
+	u32 shm_va;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(notify_ducatidriver_state.ref_count),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((params->remote_proc_id == MULTIPROC_INVALIDID)
+			|| (params->remote_proc_id == multiproc_self())))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params->line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(((u32)params->shared_addr % \
+		(u32) params->cache_line_size)) != 0)) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	status = mutex_lock_interruptible(
+				notify_ducatidriver_state.gate_handle);
+	if (status)
+		goto exit;
+
+	/* Check if driver already exists. */
+	drv_handle = notify_get_driver_handle(params->remote_proc_id,
+						params->line_id);
+	if (drv_handle != NULL) {
+		status = NOTIFY_E_ALREADYEXISTS;
+		goto error_unlock_and_return;
+	}
+
+	/* Function table information */
+	fxn_table.register_event = (void *)&notify_ducatidrv_register_event;
+	fxn_table.unregister_event = (void *)&notify_ducatidrv_unregister_event;
+	fxn_table.send_event = (void *)&notify_ducatidrv_send_event;
+	fxn_table.disable = (void *)&notify_ducatidrv_disable;
+	fxn_table.enable = (void *)&notify_ducatidrv_enable;
+	fxn_table.disable_event = (void *)&notify_ducatidrv_disable_event;
+	fxn_table.enable_event = (void *)&notify_ducatidrv_enable_event;
+
+	/* Register driver with the Notify module. */
+	status = notify_register_driver(params->remote_proc_id,
+					params->line_id, &fxn_table,
+					&drv_handle);
+	if (status < 0) {
+		status = NOTIFY_E_FAIL;
+		goto error_clean_and_exit;
+	}
+
+	/* Allocate memory for the notify_ducatidrv_object object. */
+	obj = kzalloc(sizeof(struct notify_ducatidrv_object), GFP_ATOMIC);
+	if (obj == NULL) {
+		status = NOTIFY_E_MEMORY;
+		goto error_clean_and_exit;
+	}
+	memcpy(&(obj->params), (void *) params,
+				sizeof(struct notify_ducatidrv_params));
+	obj->num_events = notify_state.cfg.num_events;
+	/* Set the handle in the driverHandles array. */
+	notify_ducatidriver_state.driver_handles
+		[params->remote_proc_id][params->line_id] = obj;
+	/* Point to the generic drvHandle object from this specific
+	 * NotifyDriverShm object. */
+	obj->drv_handle = drv_handle;
+
+	/* Determine obj->cacheEnabled using params->cacheEnabled and
+	 * SharedRegion cache flag setting, if applicable. */
+	obj->cache_enabled = params->cache_enabled;
+	min_align = params->cache_line_size;
+	region_id = sharedregion_get_id((void *)params->shared_addr);
+	if (region_id != SHAREDREGION_INVALIDREGIONID) {
+		/* Override the user cacheEnabled setting if the region
+		 * cacheEnabled is FALSE. */
+		if (!sharedregion_is_cache_enabled(region_id))
+			obj->cache_enabled = false;
+
+		region_cache_size = sharedregion_get_cache_line_size(region_id);
+
+		/* Override the user cache line size setting if the region
+		 * cache line size is smaller. */
+		if (region_cache_size < min_align)
+			min_align = region_cache_size;
+	}
+
+	if ((u32)params->shared_addr % min_align != 0) {
+		status = NOTIFY_E_FAIL;
+		goto error_clean_and_exit;
+	}
+	obj->remote_proc_id = params->remote_proc_id;
+	obj->nesting = 0;
+	if (params->remote_proc_id > multiproc_self()) {
+		obj->self_id = SELF_ID;
+		obj->other_id = OTHER_ID;
+	} else {
+		obj->self_id  = OTHER_ID;
+		obj->other_id = SELF_ID;
+	}
+
+	proc_ctrl_size = ROUND_UP(sizeof(struct notify_ducatidrv_proc_ctrl),
+				min_align);
+
+	/* Save the eventEntrySize in obj since we will need it at runtime to
+	 * index the event charts */
+	/* TODO: Check if this shm_va needs to be passed instead of params->
+	 * shared_addr */
+	shm_va = get_ducati_virt_mem();
+	obj->event_entry_size = ROUND_UP(
+				sizeof(struct notify_ducatidrv_event_entry),
+				min_align);
+	obj->self_proc_ctrl = (struct notify_ducatidrv_proc_ctrl *)
+					((u32) params->shared_addr + \
+					(obj->self_id * proc_ctrl_size));
+	obj->other_proc_ctrl = (struct notify_ducatidrv_proc_ctrl *)
+					((u32) params->shared_addr + \
+					(obj->other_id * proc_ctrl_size));
+	obj->self_event_chart = (struct notify_ducatidrv_event_entry *)
+					((u32) params->shared_addr + \
+					(2 * proc_ctrl_size) + \
+					(obj->event_entry_size * \
+					obj->num_events * obj->self_id));
+	obj->other_event_chart  = (struct notify_ducatidrv_event_entry *)
+					((u32) params->shared_addr + \
+					(2 * proc_ctrl_size) + \
+					(obj->event_entry_size * \
+					obj->num_events * obj->other_id));
+
+	for (i = 0; i < obj->num_events; i++)
+		obj->reg_chart[i] = (u32)-1;
+
+	/* All events initially unflagged */
+	for (i = 0; i < obj->num_events; i++) {
+		event_entry = EVENTENTRY(obj->self_event_chart,
+					obj->event_entry_size, i);
+		event_entry->flag = 0;
+	}
+
+	/* All events initially not registered */
+	obj->self_proc_ctrl->event_reg_mask = 0x0;
+
+	/* Enable all events initially.*/
+	obj->self_proc_ctrl->event_enable_mask = 0xFFFFFFFF;
+
+
+	/*Set up the ISR on the MPU-Ducati FIFO */
+	if (atomic_inc_return(&(notify_ducatidriver_state.mbox_ref_count)) == 1)
+		omap_mbox_enable_irq(ducati_mbox, IRQ_RX);
+	obj->self_proc_ctrl->recv_init_status = NOTIFYDUCATIDRIVER_INIT_STAMP;
+	obj->self_proc_ctrl->send_init_status = NOTIFYDUCATIDRIVER_INIT_STAMP;
+
+#if 0
+	/* Write back our own ProcCtrl */
+	if (obj->cache_enabled) {
+		Cache_wbInv((void *) obj->self_proc_ctrl,
+			sizeof(struct notify_ducatidrv_proc_ctrl),
+			Cache_Type_ALL, true);
+	}
+#endif
+
+	drv_handle->is_init = NOTIFY_DRIVERINITSTATUS_DONE;
+	mutex_unlock(notify_ducatidriver_state.gate_handle);
+	return obj;
+
+error_clean_and_exit:
+	if (obj != NULL) {
+		if (obj->self_proc_ctrl != NULL) {
+			/* Clear initialization status in shared memory. */
+			obj->self_proc_ctrl->recv_init_status = 0x0;
+			obj->self_proc_ctrl->recv_init_status = 0x0;
+			obj->self_proc_ctrl = NULL;
+#if 0
+			/* Write back our own ProcCtrl */
+			if (obj->cache_enabled) {
+				Cache_wbInv((void *) obj->self_proc_ctrl,
+				sizeof(struct notify_ducatidrv_proc_ctrl),
+				Cache_Type_ALL, true);
+			}
+#endif
+			kfree(obj);
+			obj = NULL;
+		}
+	}
+	if (drv_handle != NULL) {
+		/* Unregister driver from the Notify module*/
+		notify_unregister_driver(drv_handle);
+		notify_ducatidriver_state.driver_handles
+			[params->remote_proc_id][params->line_id] = NULL;
+		drv_handle = NULL;
+	}
+error_unlock_and_return:
+	/* Leave critical section protection. */
+	mutex_unlock(notify_ducatidriver_state.gate_handle);
+exit:
+	printk(KERN_ERR "notify_ducatidrv_create failed! status = 0x%x",
+		status);
+	return NULL;
+}
+EXPORT_SYMBOL(notify_ducatidrv_create);
+
+/* Function to delete the instance of shared memory driver */
+int notify_ducatidrv_delete(struct notify_ducatidrv_object **handle_ptr)
+{
+	int status = NOTIFY_S_SUCCESS;
+	int tmp_status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_object *obj = NULL;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(notify_ducatidriver_state.ref_count),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+
+	if (WARN_ON(unlikely(handle_ptr == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(*handle_ptr == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	obj = (struct notify_ducatidrv_object *)(*handle_ptr);
+	if (obj != NULL) {
+		/* Uninstall the ISRs & Disable the Mailbox interrupt.*/
+		if (atomic_dec_and_test(
+			&(notify_ducatidriver_state.mbox_ref_count)))
+			omap_mbox_disable_irq(ducati_mbox, IRQ_RX);
+
+		if (obj->self_proc_ctrl != NULL) {
+			/* Clear initialization status in shared memory. */
+			obj->self_proc_ctrl->recv_init_status = 0x0;
+			obj->self_proc_ctrl->recv_init_status = 0x0;
+			obj->self_proc_ctrl = NULL;
+#if 0
+			/* Write back our own ProcCtrl */
+			if (obj->cache_enabled) {
+				Cache_wbInv((void *) obj->self_proc_ctrl,
+				sizeof(struct notify_ducatidrv_proc_ctrl),
+				Cache_Type_ALL, true);
+			}
+#endif
+		}
+
+		tmp_status = notify_unregister_driver(obj->drv_handle);
+		if (status >= 0 && tmp_status < 0)
+			status = tmp_status;
+
+		notify_ducatidriver_state.driver_handles
+			[obj->params.remote_proc_id][obj->params.line_id] = \
+									NULL;
+
+		kfree(obj);
+		obj = NULL;
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_delete failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(notify_ducatidrv_delete);
+
+/* Register a callback for an event with the Notify driver. */
+int notify_ducatidrv_register_event(struct notify_driver_object *handle,
+					u32 event_id)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_object *obj;
+	VOLATILE struct notify_ducatidrv_event_entry *event_entry;
+	int i;
+	int j;
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->is_init != \
+					NOTIFY_DRIVERINITSTATUS_DONE))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle->driver_handle == NULL))) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit;
+	}
+
+	obj = (struct notify_ducatidrv_object *)
+				handle->notify_handle->driver_handle;
+	if (WARN_ON(unlikely(obj->reg_chart == NULL))) {
+		status = NOTIFY_E_FAIL;
+		goto exit;
+	}
+
+	/* This function is only called for the first register, i.e. when the
+	 * first callback is being registered. */
+	/* Add an entry for the registered event into the Event Registration
+	 * Chart, in ascending order of event numbers (and decreasing
+	 * priorities). There is no need to make this atomic since
+	 * Notify_exec cannot preempt: shared memory hasn't been modified yet.
+	 */
+	for (i = 0 ; i < obj->num_events; i++) {
+		/* Find the correct slot in the registration array. */
+		if (obj->reg_chart[i] == (u32) -1) {
+			for (j = (i - 1); j >= 0; j--) {
+				if (event_id < obj->reg_chart[j]) {
+					obj->reg_chart[j + 1] = \
+						obj->reg_chart[j];
+					i = j;
+				} else {
+					/* End the loop, slot found. */
+					j = -1;
+				}
+			}
+			obj->reg_chart[i] = event_id;
+			break;
+		}
+	}
+
+	/* Clear any pending unserviced event as there are no listeners
+	 * for the pending event */
+	event_entry = EVENTENTRY(obj->self_event_chart, obj->event_entry_size,
+					event_id);
+	event_entry->flag = NOTIFYDUCATIDRIVER_DOWN;
+
+	/* Set the registered bit in shared memory and write back */
+	set_bit(event_id, (unsigned long *)
+			&(obj->self_proc_ctrl->event_reg_mask));
+
+#if 0
+	/* Write back both the flag and the reg mask */
+	if (obj->cache_enabled) {
+		/* Writeback eventRegMask */
+		Cache_wbInv((void *) obj->self_proc_ctrl,
+			sizeof(struct notify_ducatidrv_proc_ctrl),
+			Cache_Type_ALL, true);
+		/* Writeback event entry */
+		Cache_wbInv((void *) event_entry,
+			sizeof(struct notify_ducatidrv_event_entry),
+			Cache_Type_ALL, true);
+	}
+#endif
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_register_event failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+
+/* Unregister a callback for an event with the Notify driver. */
+int notify_ducatidrv_unregister_event(struct notify_driver_object *handle,
+					u32 event_id)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_object *obj;
+	VOLATILE struct notify_ducatidrv_event_entry *event_entry;
+	int i;
+	int j;
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->is_init != \
+					NOTIFY_DRIVERINITSTATUS_DONE))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle->driver_handle == NULL))) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit;
+	}
+
+	obj = (struct notify_ducatidrv_object *)
+				handle->notify_handle->driver_handle;
+	if (WARN_ON(unlikely(obj->reg_chart == NULL))) {
+		status = NOTIFY_E_FAIL;
+		goto exit;
+	}
+
+	/* This function is only called for the last unregister, i.e. when the
+	 * final remaining callback is being unregistered.
+	 * Unset the registered bit in shared memory */
+	clear_bit(event_id, (unsigned long *)
+			&(obj->self_proc_ctrl->event_reg_mask));
+
+	/* Clear any pending unserviced event as there are no listeners
+	 * for the pending event.  This should be done only after the event
+	 * is unregistered from shared memory so the other processor doesn't
+	 * successfully send an event our way immediately after unflagging this
+	 * event. */
+	event_entry = EVENTENTRY(obj->self_event_chart, obj->event_entry_size,
+					event_id);
+	event_entry->flag = NOTIFYDUCATIDRIVER_DOWN;
+
+#if 0
+	/* Write back both the flag and the reg mask */
+	if (obj->cache_enabled) {
+		/* Writeback event entry */
+		Cache_wbInv((void *) event_entry,
+			sizeof(struct notify_ducatidrv_event_entry),
+			Cache_Type_ALL, true);
+		/* Writeback eventRegMask */
+		Cache_wbInv((void *) obj->self_proc_ctrl,
+			sizeof(struct notify_ducatidrv_proc_ctrl),
+			Cache_Type_ALL, true);
+	}
+#endif
+
+	/* Re-arrange eventIds in the Event Registration Chart so there is
+	 * no gap caused by the removal of this eventId
+	 *
+	 * There is no need to make this atomic since Notify_exec cannot
+	 * preempt: the event has already been disabled in shared memory
+	 * (see above) */
+	for (i = 0 ; i < obj->num_events; i++) {
+		/* Find the correct slot in the registration array. */
+		if (event_id == obj->reg_chart[i]) {
+			obj->reg_chart[i] = (u32) -1;
+			for (j = (i + 1); (obj->reg_chart[j] != (u32)-1) && \
+				(j != obj->num_events); j++)
+				obj->reg_chart[j - 1] = obj->reg_chart[j];
+
+			if (j == obj->num_events)
+				obj->reg_chart[j - 1] = (u32)-1;
+
+			break;
+		}
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_unregister_event failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+
+/* Send a notification event to the registered users for this
+ * notification on the specified processor. */
+int notify_ducatidrv_send_event(struct notify_driver_object *handle,
+				u32 event_id, u32 payload, bool wait_clear)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_object *obj;
+	VOLATILE struct notify_ducatidrv_event_entry *event_entry;
+	int max_poll_count;
+	int i = 0;
+	mbox_msg_t msg;
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->is_init != \
+					NOTIFY_DRIVERINITSTATUS_DONE))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle->driver_handle == NULL))) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit;
+	}
+
+	obj = (struct notify_ducatidrv_object *)
+				handle->notify_handle->driver_handle;
+	if (WARN_ON(unlikely(obj->reg_chart == NULL))) {
+		status = NOTIFY_E_FAIL;
+		goto exit;
+	}
+
+	dsb();
+	event_entry = EVENTENTRY(obj->other_event_chart, obj->event_entry_size,
+					event_id);
+#if 0
+	/* Invalidate cache for the other processor's procCtrl. */
+	if (obj->cache_enabled) {
+		Cache_wbInv((void *) obj->other_proc_ctrl,
+			sizeof(struct notify_ducatidrv_proc_ctrl),
+			Cache_Type_ALL, true);
+	}
+#endif
+	max_poll_count = notify_state.cfg.send_event_poll_count;
+
+	/* Check whether driver on other processor is initialized */
+	if (obj->other_proc_ctrl->recv_init_status != \
+					NOTIFYDUCATIDRIVER_INIT_STAMP) {
+		/* This may be used for polling till other-side driver is ready,
+		 * so do not set failure reason. */
+		status = NOTIFY_E_NOTINITIALIZED;
+		goto exit;
+	}
+	/* Check if other side has registered to receive this event. */
+	if (!test_bit(event_id, (unsigned long *)
+				&obj->other_proc_ctrl->event_reg_mask)) {
+		status = NOTIFY_E_EVTNOTREGISTERED;
+		/* This may be used for polling till other-side is ready, so
+		* do not set failure reason. */
+		goto exit;
+	}
+	if (!test_bit(event_id, (unsigned long *)
+				&obj->other_proc_ctrl->event_enable_mask)) {
+		status = NOTIFY_E_EVTDISABLED;
+		/* This may be used for polling till other-side is ready, so
+		* do not set failure reason. */
+		goto exit;
+	}
+#if 0
+	if (obj->cache_enabled) {
+		Cache_inv((void *)event_entry,
+			sizeof(struct notify_ducatidrv_event_entry),
+			Cache_Type_ALL, TRUE);
+	}
+#endif
+	dsb();
+	status = mutex_lock_interruptible(
+				notify_ducatidriver_state.gate_handle);
+	if (status)
+		goto exit;
+
+	if (wait_clear == true) {
+		/*Wait for completion of prev
+		event from other side*/
+		while ((event_entry->flag != NOTIFYDUCATIDRIVER_DOWN) && \
+			(status >= 0)) {
+			/* Leave critical section protection. Create a window
+			 * of opportunity for other interrupts to be handled.*/
+			mutex_unlock(notify_ducatidriver_state.gate_handle);
+			i++;
+			if ((max_poll_count != (u32)-1) && \
+				(i == max_poll_count)) {
+				status = NOTIFY_E_TIMEOUT;
+				break;
+			}
+
+#if 0
+			if (obj->cache_enabled) {
+				Cache_inv((void *)event_entry,
+				sizeof(struct notify_ducatidrv_event_entry),
+				Cache_Type_ALL, TRUE);
+			}
+#endif
+			dsb();
+
+			/* Enter critical section protection. */
+			status = mutex_lock_interruptible(
+					notify_ducatidriver_state.gate_handle);
+		}
+	}
+
+	if (status >= 0) {
+		/* Set the event bit field and payload. */
+		event_entry->payload = payload;
+		event_entry->flag = NOTIFYDUCATIDRIVER_UP;
+
+#if 0
+		if (obj->cache_enabled) {
+			Cache_inv((void *)event_entry,
+			sizeof(struct notify_ducatidrv_event_entry),
+			Cache_Type_ALL, TRUE);
+		}
+#endif
+		dsb();
+
+		/* Send an interrupt with the event information to the
+		 * remote processor */
+		msg = ((obj->remote_proc_id << 16) | event_id);
+		status = omap_mbox_msg_send(ducati_mbox, msg);
+
+		/* Leave critical section protection. */
+		mutex_unlock(notify_ducatidriver_state.gate_handle);
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_sendevent failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+
+/* Disable all events for this Notify driver.*/
+int notify_ducatidrv_disable(struct notify_driver_object *handle)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_object *obj;
+
+	/* All the below parameter checking is unnecessary, but added to
+	 * make sure the driver object is initialized properly */
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->is_init != \
+					NOTIFY_DRIVERINITSTATUS_DONE))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle->driver_handle == NULL))) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit;
+	}
+
+	obj = (struct notify_ducatidrv_object *)
+				handle->notify_handle->driver_handle;
+	if (WARN_ON(unlikely(obj->reg_chart == NULL))) {
+		status = NOTIFY_E_FAIL;
+		goto exit;
+	}
+
+	/* Disable the mailbox interrupt associated with ducati mailbox */
+	omap_mbox_disable_irq(ducati_mbox, IRQ_RX);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_disable failed! "
+			"status = 0x%x", status);
+	}
+	/*No flags to be returned. */
+	return 0;
+}
+
+/* Restore the notify_ducatidrv to the state before the last disable was
+ * called. */
+void notify_ducatidrv_enable(struct notify_driver_object *handle)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_object *obj;
+
+	/* All the below parameter checking is unnecessary, but added to
+	 * make sure the driver object is initialized properly */
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->is_init != \
+					NOTIFY_DRIVERINITSTATUS_DONE))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle->driver_handle == NULL))) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit;
+	}
+
+	obj = (struct notify_ducatidrv_object *)
+				handle->notify_handle->driver_handle;
+	if (WARN_ON(unlikely(obj->reg_chart == NULL))) {
+		status = NOTIFY_E_FAIL;
+		goto exit;
+	}
+
+	/*Enable the receive interrupt for ducati */
+	omap_mbox_enable_irq(ducati_mbox, IRQ_RX);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_enable failed! "
+			"status = 0x%x", status);
+	}
+	return;
+}
+
+/* Disable a specific event for this Notify ducati driver */
+void notify_ducatidrv_disable_event(struct notify_driver_object *handle,
+					u32 event_id)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_object *obj;
+	VOLATILE struct notify_ducatidrv_event_entry *event_entry;
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->is_init != \
+					NOTIFY_DRIVERINITSTATUS_DONE))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle->driver_handle == NULL))) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit;
+	}
+
+	obj = (struct notify_ducatidrv_object *)
+		handle->notify_handle->driver_handle;
+	if (event_id > obj->num_events) {
+		status = NOTIFY_E_FAIL;
+		goto exit;
+	}
+
+	/* Enter critical section protection. */
+	status = mutex_lock_interruptible(
+					notify_ducatidriver_state.gate_handle);
+	if (status)
+		goto exit;
+	clear_bit(event_id, (unsigned long *)
+			&(obj->self_proc_ctrl->event_enable_mask));
+	/* Leave critical section protection. */
+	mutex_unlock(notify_ducatidriver_state.gate_handle);
+#if 0
+	if (obj->cache_enabled) {
+		/* Writeback event_enable_mask */
+		Cache_wbInv((void *) obj->self_proc_ctrl,
+			sizeof(struct notify_ducatidrv_proc_ctrl),
+			Cache_Type_ALL, true);
+	}
+#endif
+
+	event_entry = EVENTENTRY(obj->self_event_chart, obj->event_entry_size,
+					event_id)
+#if 0
+	if (obj->cache_enabled) {
+		/* Writeback event entry */
+		Cache_wbInv((void *) event_entry,
+			sizeof(struct notify_ducatidrv_event_entry),
+			Cache_Type_ALL, true);
+	}
+#endif
+
+	/* Disable incoming Notify interrupts.  This is done to ensure that the
+	 * eventEntry->flag is read atomically with any write back to shared
+	 * memory */
+	notify_ducatidrv_disable(handle);
+
+	/* Is the local notify_ducatidrv_disable_event happening between the
+	 * following two notify_ducatidrv_send_event operations on the remote
+	 * processor?
+	 * 1. Writing notify_ducatidrv_UP to shared memory
+	 * 2. Sending the interrupt across
+	 * If so, we should handle this event so the other core isn't left
+	 * spinning until the event is re-enabled and the next
+	 * notify_ducatidrv_isr executes This race condition is very rare but we
+	 * need to account for it: */
+	if (event_entry->flag == NOTIFYDUCATIDRIVER_UP) {
+		/* Acknowledge the event. No need to store the payload. The
+		 * other side will not send this event again even though flag is
+		 * down, because the event is now disabled. So the payload
+		 * within the eventChart will not get overwritten. */
+		event_entry->flag = NOTIFYDUCATIDRIVER_DOWN;
+#if 0
+		/* Write back acknowledgement */
+		if (obj->cache_enabled) {
+			Cache_wbInv(event_entry,
+				sizeof(struct notify_ducatidrv_event_entry),
+				Cache_Type_ALL, TRUE);
+		}
+#endif
+		/* Execute the callback function. This will execute in a Task
+		 * or Swi context (not Hwi!) */
+		notify_exec(obj->drv_handle->notify_handle, event_id,
+			event_entry->payload);
+	}
+
+	/* Re-enable incoming Notify interrupts */
+	notify_ducatidrv_enable(handle);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_disable_event failed! "
+			"status = 0x%x", status);
+	}
+	return;
+}
+
+/* Enable a specific event for this Notify ducati driver */
+void notify_ducatidrv_enable_event(struct notify_driver_object *handle,
+								u32 event_id)
+{
+	int status = 0;
+	struct notify_ducatidrv_object *obj;
+
+	if (WARN_ON(unlikely(handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->is_init != \
+					NOTIFY_DRIVERINITSTATUS_DONE))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(handle->notify_handle->driver_handle == NULL))) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit;
+	}
+
+	obj = (struct notify_ducatidrv_object *)
+		handle->notify_handle->driver_handle;
+	if (event_id > obj->num_events) {
+		status = NOTIFY_E_FAIL;
+		goto exit;
+	}
+
+	/* Enter critical section protection. */
+	status = mutex_lock_interruptible(
+					notify_ducatidriver_state.gate_handle);
+	if (status)
+		goto exit;
+	set_bit(event_id, (unsigned long *)
+			&(obj->self_proc_ctrl->event_enable_mask));
+	/* Leave critical section protection. */
+	mutex_unlock(notify_ducatidriver_state.gate_handle);
+#if 0
+	if (obj->cache_enabled) {
+		/* Writeback event_enable_mask */
+		Cache_wbInv((void *) obj->self_proc_ctrl,
+			sizeof(struct notify_ducatidrv_proc_ctrl),
+			Cache_Type_ALL, true);
+	}
+#endif
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_enable_event failed! "
+			"status = 0x%x", status);
+	}
+	return;
+}
+
+/* Get the shared memory requirements for the notify_ducatidrv. */
+uint notify_ducatidrv_shared_mem_req(
+				const struct notify_ducatidrv_params *params)
+{
+	uint mem_req = 0;
+	u16 region_id;
+	uint region_cache_size;
+	uint min_align;
+	s32 status = NOTIFY_S_SUCCESS;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(
+			&(notify_ducatidriver_state.ref_count),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(0),
+			NOTIFYDUCATIDRIVER_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(params == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	/* Determine obj->cache_enabled using params->cache_enabled and
+	 * sharedregion cache flag setting, if applicable. */
+	min_align = params->cache_line_size;
+	region_id = sharedregion_get_id((void *) params->shared_addr);
+	if (region_id != SHAREDREGION_INVALIDREGIONID) {
+		region_cache_size = sharedregion_get_cache_line_size(region_id);
+
+		/* Override the user cache line size setting if the region
+		 * cache line size is smaller. */
+		if (region_cache_size < min_align)
+			min_align = region_cache_size;
+	}
+
+	/* Determine obj->eventEntrySize which will be used to ROUND_UP
+	 * addresses */
+	mem_req = ((ROUND_UP(sizeof(struct notify_ducatidrv_proc_ctrl),
+			min_align)) * 2) + \
+			((ROUND_UP(sizeof(struct notify_ducatidrv_event_entry),
+			min_align) * 2 * notify_state.cfg.num_events));
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_ducatidrv_shared_mem_req failed!"
+			" status = 0x%x", status);
+	}
+	return mem_req;
+}
+
+/* This function implements the interrupt service routine for the interrupt
+ * received from the Ducati processor. */
+static int notify_ducatidrv_isr(void *ntfy_msg)
+{
+	/* Decode the msg to identify the processor that has sent the message */
+	u32 proc_id = (u32)ntfy_msg;
+
+	/* Call the corresponding prpc_id callback */
+	notify_ducatidrv_isr_callback(notify_ducatidriver_state.driver_handles
+		[proc_id][0], ntfy_msg);
+
+	return 0;
+}
+EXPORT_SYMBOL(notify_ducatidrv_isr);
+
+static bool notify_ducatidrv_isr_callback(void *ref_data, void *notify_msg)
+{
+	u32 payload = 0;
+	u32 i = 0;
+	VOLATILE struct notify_ducatidrv_event_entry  *event_entry;
+	struct notify_ducatidrv_object *obj;
+	u32 event_id;
+
+	obj = (struct notify_ducatidrv_object *) ref_data;
+
+	dsb();
+	/* Execute the loop till no asserted event is found for one complete
+	 * loop through all registered events */
+	do {
+		/* Check if the entry is a valid registered event.*/
+		event_id = obj->reg_chart[i];
+		if (event_id == (u32) -1)
+			break;
+
+		event_entry = EVENTENTRY(obj->self_event_chart,
+					obj->event_entry_size, event_id);
+#if 0
+		if (obj->cache_enabled) {
+			Cache_inv((void *)event_entry,
+			sizeof(struct notify_ducatidrv_event_entry),
+			Cache_Type_ALL, TRUE);
+		}
+#endif
+		dsb();
+
+		/* Determine the current high priority event.*/
+		/* Check if the event is set and enabled.*/
+		if (event_entry->flag == NOTIFYDUCATIDRIVER_UP &&
+			test_bit(event_id, (unsigned long *)
+				&obj->self_proc_ctrl->event_enable_mask)) {
+			payload = event_entry->payload;
+
+			/* Acknowledge the event. */
+			event_entry->flag = NOTIFYDUCATIDRIVER_DOWN;
+
+			/* Write back acknowledgement */
+#if 0
+			if (obj->cache_enabled) {
+				Cache_inv((void *)event_entry,
+				sizeof(struct notify_ducatidrv_event_entry),
+				Cache_Type_ALL, TRUE);
+			}
+#endif
+			dsb();
+
+			/* Execute the callback function */
+			notify_exec(obj->drv_handle->notify_handle, event_id,
+					payload);
+			/* reinitialize the event check counter. */
+			i = 0;
+		} else {
+			/* check for next event. */
+			i++;
+		}
+	} while ((event_id != (u32) -1) && (i < obj->num_events));
+
+	return true;
+}
diff --git a/drivers/dsp/syslink/omap_notify/drv_notify.c b/drivers/dsp/syslink/omap_notify/drv_notify.c
new file mode 100644
index 000000000000..fcdc4425e837
--- /dev/null
+++ b/drivers/dsp/syslink/omap_notify/drv_notify.c
@@ -0,0 +1,928 @@
+/*
+ * drv_notify.c
+ *
+ * Syslink support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <generated/autoconf.h>
+#include <linux/spinlock.h>
+#include <linux/semaphore.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <asm/pgtable.h>
+#include <linux/types.h>
+#include <linux/cdev.h>
+
+
+#include <syslink/platform_mem.h>
+#include <syslink/drv_notify.h>
+#include <syslink/notify_driver.h>
+#include <syslink/notify.h>
+#include <syslink/notify_ioctl.h>
+
+
+/** ============================================================================
+ *  Macros and types
+ *  ============================================================================
+ */
+/* Maximum number of user supported. */
+#define MAX_PROCESSES 32
+
+/*Structure of Event callback argument passed to register fucntion*/
+struct notify_drv_event_cbck {
+	struct list_head element; /* List element header */
+	u16 proc_id; /* Processor identifier */
+	u16 line_id; /* line identifier */
+	u32 event_id; /* Event identifier */
+	notify_fn_notify_cbck func; /* Callback function for the event. */
+	void *param; /* User callback argument. */
+	u32 pid; /* Process Identifier for user process. */
+};
+
+/* Keeps the information related to Event.*/
+struct notify_drv_event_state {
+	struct list_head buf_list;
+	/* Head of received event list. */
+	u32 pid;
+	/* User process ID. */
+	u32 ref_count;
+	/*Reference count, used when multiple Notify_registerEvent are called
+	from same process space(multi threads/processes). */
+	struct semaphore *semhandle;
+	/* Semaphore for waiting on event. */
+	struct semaphore *tersemhandle;
+	/* Termination synchronization semaphore. */
+};
+
+/* NotifyDrv module state object */
+struct notify_drv_module_object {
+	bool is_setup;
+	/* Indicates whether the module has been already setup */
+	bool open_ref_count;
+	/* Open reference count. */
+	struct mutex *gate_handle;
+	/* Handle of gate to be used for local thread safety */
+	struct list_head event_cbck_list;
+	/* List containg callback arguments for all registered handlers from
+	 * user mode. */
+	struct list_head single_event_cbck_list;
+	/* List containg callback arguments for all registered handlers from
+	 user mode for 'single' registrations. */
+	struct notify_drv_event_state event_state[MAX_PROCESSES];
+	/* List for all user processes registered. */
+};
+
+struct notify_drv_module_object notifydrv_state = {
+	.is_setup = false,
+	.open_ref_count = 0,
+	.gate_handle = NULL
+	/*.event_cbck_list = NULL,
+	.single_event_cbck_list = NULL*/
+};
+
+
+/* Attach a process to notify user support framework. */
+static int notify_drv_attach(u32 pid);
+
+/* Detach a process from notify user support framework. */
+static int notify_drv_detach(u32 pid);
+
+/* This function implements the callback registered with IPS. Here to pass
+ * event no. back to user function (so that it can do another level of
+ * demultiplexing of callbacks) */
+static void _notify_drv_callback(u16 proc_id, u16 line_id, u32 event_id,
+					uint *arg, u32 payload);
+
+/* This function adds a data to a registered process. */
+static int _notify_drv_add_buf_by_pid(u16 proc_id, u16 line_id, u32 pid,
+			u32 event_id, u32 data, notify_fn_notify_cbck cb_fxn,
+			void *param);
+
+
+
+/*
+ * read data from the driver
+ */
+int notify_drv_read(struct file *filp, char *dst, size_t size,
+		loff_t *offset)
+{
+
+	bool flag = false;
+	struct notify_drv_event_packet *u_buf = NULL;
+	int ret_val = 0;
+	u32 i;
+	struct list_head *elem;
+	struct notify_drv_event_packet t_buf;
+
+	if (WARN_ON(notifydrv_state.is_setup == false)) {
+		ret_val = -EFAULT;
+		goto func_end;
+	}
+
+	ret_val = copy_from_user((void *)&t_buf,
+				(void *)dst,
+				sizeof(struct notify_drv_event_packet));
+	if (WARN_ON(ret_val != 0))
+		ret_val = -EFAULT;
+
+	for (i = 0; i < MAX_PROCESSES; i++) {
+		if (notifydrv_state.event_state[i].pid == t_buf.pid) {
+			flag = true;
+			break;
+		}
+	}
+	if (flag == false) {
+		ret_val = -EFAULT;
+		goto func_end;
+	}
+
+	/* Wait for the event */
+	ret_val = down_interruptible(notifydrv_state.event_state[i].semhandle);
+	if (ret_val < 0) {
+		ret_val = -ERESTARTSYS;
+		goto func_end;
+	}
+	WARN_ON(mutex_lock_interruptible(notifydrv_state.gate_handle));
+	elem = ((struct list_head *)
+			&(notifydrv_state.event_state[i].buf_list))->next;
+	u_buf = container_of(elem, struct notify_drv_event_packet, element);
+	list_del(elem);
+	mutex_unlock(notifydrv_state.gate_handle);
+	if (u_buf == NULL) {
+		ret_val = -EFAULT;
+		goto func_end;
+	}
+	ret_val = copy_to_user((void *)dst, u_buf,
+			sizeof(struct notify_drv_event_packet));
+	if (WARN_ON(ret_val != 0))
+		ret_val = -EFAULT;
+	ret_val = sizeof(struct notify_drv_event_packet);
+
+	if (u_buf->is_exit == true)
+		up(notifydrv_state.event_state[i].tersemhandle);
+
+	kfree(u_buf);
+	u_buf = NULL;
+
+func_end:
+	return ret_val;
+}
+
+int notify_drv_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+		vma->vm_end - vma->vm_start, vma->vm_page_prot))
+		return -EAGAIN;
+	return 0;
+}
+
+/* ioctl function for of Linux Notify driver. */
+int notify_drv_ioctl(struct inode *inode, struct file *filp, u32 cmd,
+					unsigned long args)
+{
+	int status = NOTIFY_S_SUCCESS;
+	int os_status = 0;
+	unsigned long size;
+	struct notify_cmd_args *cmd_args = (struct notify_cmd_args *)args;
+	struct notify_cmd_args common_args;
+
+	switch (cmd) {
+	case CMD_NOTIFY_GETCONFIG:
+	{
+		struct notify_cmd_args_get_config *src_args =
+				(struct notify_cmd_args_get_config *)args;
+		struct notify_config cfg;
+
+		notify_get_config(&cfg);
+		size = copy_to_user((void *) (src_args->cfg),
+			(const void *) &cfg, sizeof(struct notify_config));
+		if (WARN_ON(size != 0))
+			os_status = -EFAULT;
+	}
+	break;
+
+	case CMD_NOTIFY_SETUP:
+	{
+		struct notify_cmd_args_setup *src_args =
+					(struct notify_cmd_args_setup *) args;
+		struct notify_config cfg;
+
+		size = copy_from_user((void *) &cfg,
+					(const void *) (src_args->cfg),
+					sizeof(struct notify_config));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+		status = notify_setup(&cfg);
+	}
+	break;
+
+	case CMD_NOTIFY_DESTROY:
+	{
+		/* copy_from_user is not needed for Notify_getConfig, since the
+		 * user's config is not used.
+		 */
+		status = notify_destroy();
+	}
+	break;
+
+	case CMD_NOTIFY_REGISTEREVENTSINGLE:
+	{
+		struct notify_cmd_args_register_event src_args;
+		struct notify_drv_event_cbck *cbck = NULL;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *) &src_args,
+				(const void *) (args),
+				sizeof(struct notify_cmd_args_register_event));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+
+		cbck = kmalloc(sizeof(struct notify_drv_event_cbck),
+					GFP_ATOMIC);
+		WARN_ON(cbck == NULL);
+		cbck->proc_id = src_args.proc_id;
+		cbck->line_id = src_args.line_id;
+		cbck->event_id = src_args.event_id;
+		cbck->pid = src_args.pid;
+		cbck->func = src_args.fn_notify_cbck;
+		cbck->param = src_args.cbck_arg;
+		status = notify_register_event_single(src_args.proc_id,
+					src_args.line_id, src_args.event_id,
+					_notify_drv_callback, (void *)cbck);
+		if (status < 0) {
+			/* This does not impact return status of this function,
+			 * so retval comment is not used. */
+			kfree(cbck);
+		} else {
+			WARN_ON(mutex_lock_interruptible
+					(notifydrv_state.gate_handle));
+			INIT_LIST_HEAD((struct list_head *)&(cbck->element));
+			list_add_tail(&(cbck->element),
+				&(notifydrv_state.single_event_cbck_list));
+			mutex_unlock(notifydrv_state.gate_handle);
+		}
+	}
+	break;
+
+	case CMD_NOTIFY_REGISTEREVENT:
+	{
+		struct notify_cmd_args_register_event src_args;
+		struct notify_drv_event_cbck *cbck = NULL;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *) &src_args,
+				(const void *) (args),
+				sizeof(struct notify_cmd_args_register_event));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+
+		cbck = kmalloc(sizeof(struct notify_drv_event_cbck),
+					GFP_ATOMIC);
+		WARN_ON(cbck == NULL);
+		cbck->proc_id = src_args.proc_id;
+		cbck->line_id = src_args.line_id;
+		cbck->event_id = src_args.event_id;
+		cbck->func = src_args.fn_notify_cbck;
+		cbck->param = src_args.cbck_arg;
+		cbck->pid = src_args.pid;
+		status = notify_register_event(src_args.proc_id,
+					src_args.line_id, src_args.event_id,
+					_notify_drv_callback, (void *)cbck);
+		if (status < 0) {
+			/* This does not impact return status of this function,
+			 * so retval comment is not used. */
+			kfree(cbck);
+		} else {
+			WARN_ON(mutex_lock_interruptible
+					(notifydrv_state.gate_handle));
+			INIT_LIST_HEAD((struct list_head *)&(cbck->element));
+			list_add_tail(&(cbck->element),
+				&(notifydrv_state.event_cbck_list));
+			mutex_unlock(notifydrv_state.gate_handle);
+		}
+	}
+	break;
+
+	case CMD_NOTIFY_UNREGISTEREVENTSINGLE:
+	{
+		bool found = false;
+		u32 pid;
+		struct notify_drv_event_cbck *cbck = NULL;
+		struct list_head *entry = NULL;
+		struct notify_cmd_args_unregister_event src_args;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *)&src_args, (const void *)(args),
+			sizeof(struct notify_cmd_args_unregister_event));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+
+		WARN_ON(mutex_lock_interruptible(notifydrv_state.gate_handle));
+		pid = src_args.pid;
+		list_for_each(entry, (struct list_head *)
+			&(notifydrv_state.single_event_cbck_list)) {
+			cbck = (struct notify_drv_event_cbck *)(entry);
+			if ((cbck->proc_id == src_args.proc_id) &&
+				(cbck->line_id == src_args.line_id) &&
+				(cbck->event_id == src_args.event_id) &&
+				(cbck->pid == pid)) {
+					found = true;
+					break;
+			}
+		}
+		mutex_unlock(notifydrv_state.gate_handle);
+		if (found == false) {
+			status = NOTIFY_E_NOTFOUND;
+			goto func_end;
+		}
+		status = notify_unregister_event_single(src_args.proc_id,
+				src_args.line_id, src_args.event_id);
+		/* This check is needed at run-time also to propagate the
+		 * status to user-side. This must not be optimized out. */
+		if (status >= 0) {
+			WARN_ON(mutex_lock_interruptible
+						(notifydrv_state.gate_handle));
+			list_del((struct list_head *)cbck);
+			mutex_unlock(notifydrv_state.gate_handle);
+			kfree(cbck);
+		}
+	}
+	break;
+
+	case CMD_NOTIFY_UNREGISTEREVENT:
+	{
+		bool found = false;
+		u32 pid;
+		struct notify_drv_event_cbck *cbck = NULL;
+		struct list_head *entry = NULL;
+		struct notify_cmd_args_unregister_event src_args;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *)&src_args, (const void *)(args),
+			sizeof(struct notify_cmd_args_unregister_event));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+
+		WARN_ON(mutex_lock_interruptible(notifydrv_state.gate_handle));
+		pid = src_args.pid;
+		list_for_each(entry, (struct list_head *)
+			&(notifydrv_state.event_cbck_list)) {
+			cbck = (struct notify_drv_event_cbck *)(entry);
+			if ((cbck->func == src_args.fn_notify_cbck) &&
+				(cbck->param == src_args.cbck_arg) &&
+				(cbck->proc_id == src_args.proc_id) &&
+				(cbck->line_id == src_args.line_id) &&
+				(cbck->event_id == src_args.event_id) &&
+				(cbck->pid == pid)) {
+					found = true;
+					break;
+			}
+		}
+		mutex_unlock(notifydrv_state.gate_handle);
+		if (found == false) {
+			status = NOTIFY_E_NOTFOUND;
+			goto func_end;
+		}
+		status = notify_unregister_event(src_args.proc_id,
+				src_args.line_id, src_args.event_id,
+				_notify_drv_callback, (void *) cbck);
+		/* This check is needed at run-time also to propagate the
+		 * status to user-side. This must not be optimized out. */
+		if (status >= 0) {
+			WARN_ON(mutex_lock_interruptible
+						(notifydrv_state.gate_handle));
+			list_del((struct list_head *)cbck);
+			mutex_unlock(notifydrv_state.gate_handle);
+			kfree(cbck);
+		}
+	}
+	break;
+
+	case CMD_NOTIFY_SENDEVENT:
+	{
+		struct notify_cmd_args_send_event src_args;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *) &src_args,
+				(const void *) (args),
+				sizeof(struct notify_cmd_args_send_event));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+		status = notify_send_event(src_args.proc_id, src_args.line_id,
+				src_args.event_id, src_args.payload,
+				src_args.wait_clear);
+	}
+	break;
+
+	case CMD_NOTIFY_DISABLE:
+	{
+		struct notify_cmd_args_disable src_args;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *) &src_args,
+				(const void *) (args),
+				sizeof(struct notify_cmd_args_disable));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+		src_args.flags = notify_disable(src_args.proc_id,
+							src_args.line_id);
+
+		/* Copy the full args to user-side */
+		size = copy_to_user((void *) (args), (const void *) &src_args,
+					sizeof(struct notify_cmd_args_disable));
+		/* This check is needed at run-time also since it depends on
+		 * run environment. It must not be optimized out. */
+		if (WARN_ON(size != 0))
+			os_status = -EFAULT;
+	}
+	break;
+
+	case CMD_NOTIFY_RESTORE:
+	{
+		struct notify_cmd_args_restore src_args;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *) &src_args,
+				(const void *)(args),
+				sizeof(struct notify_cmd_args_restore));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+		notify_restore(src_args.proc_id, src_args.line_id,
+			src_args.key);
+	}
+	break;
+
+	case CMD_NOTIFY_DISABLEEVENT:
+	{
+		struct notify_cmd_args_disable_event src_args;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *) &src_args,
+				(const void *)(args),
+				sizeof(struct notify_cmd_args_disable_event));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+		notify_disable_event(src_args.proc_id, src_args.line_id,
+						src_args.event_id);
+	}
+	break;
+
+	case CMD_NOTIFY_ENABLEEVENT:
+	{
+		struct notify_cmd_args_enable_event src_args;
+
+		/* Copy the full args from user-side. */
+		size = copy_from_user((void *)&src_args,
+				(const void *)(args),
+				sizeof(struct notify_cmd_args_enable_event));
+		if (WARN_ON(size != 0)) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+		notify_enable_event(src_args.proc_id, src_args.line_id,
+						src_args.event_id);
+	}
+	break;
+
+	case CMD_NOTIFY_THREADATTACH:
+	{
+		u32 pid = *((u32 *)args);
+		status = notify_drv_attach(pid);
+	}
+	break;
+
+	case CMD_NOTIFY_THREADDETACH:
+	{
+		u32 pid = *((u32 *)args);
+		status = notify_drv_detach(pid);
+	}
+	break;
+
+	case CMD_NOTIFY_ATTACH:
+	{
+		struct notify_cmd_args_attach src_args;
+		void *knl_shared_addr;
+
+		size = copy_from_user((void *) &src_args, (const void *)(args),
+					sizeof(struct notify_cmd_args_attach));
+		if (size != 0) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+
+		/* knl_shared_addr = Memory_translate(src_args.shared_addr,
+						Memory_XltFlags_Phys2Virt); */
+		knl_shared_addr = platform_mem_translate(
+					(void *)src_args.shared_addr,
+					PLATFORM_MEM_XLT_FLAGS_PHYS2VIRT);
+		status = notify_attach(src_args.proc_id, knl_shared_addr);
+	}
+	break;
+
+	case CMD_NOTIFY_DETACH:
+	{
+		struct notify_cmd_args_detach src_args;
+
+		size = copy_from_user((void *) &src_args,
+					(const void *)(args),
+					sizeof(struct notify_cmd_args_detach));
+		if (size != 0) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+
+		status = notify_detach(src_args.proc_id);
+	}
+	break;
+
+	case CMD_NOTIFY_SHAREDMEMREQ:
+	{
+		struct notify_cmd_args_shared_mem_req src_args;
+		void *knl_shared_addr;
+
+		size = copy_from_user((void *) &src_args,
+				(const void *)(args),
+				sizeof(struct notify_cmd_args_shared_mem_req));
+		if (size != 0) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+
+		/* knl_shared_addr = Memory_translate(src_args.shared_addr,
+						Memory_XltFlags_Phys2Virt); */
+		knl_shared_addr = platform_mem_translate(
+					(void *)src_args.shared_addr,
+					PLATFORM_MEM_XLT_FLAGS_PHYS2VIRT);
+		status = notify_shared_mem_req(src_args.proc_id,
+						knl_shared_addr);
+	}
+	break;
+
+	case CMD_NOTIFY_ISREGISTERED:
+	{
+		struct notify_cmd_args_is_registered src_args;
+
+		size = copy_from_user((void *) &src_args,
+				(const void *)(args),
+				sizeof(struct notify_cmd_args_is_registered));
+		if (size != 0) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+
+		src_args.is_registered = notify_is_registered(src_args.proc_id,
+						src_args.line_id);
+		size = copy_to_user((void *) (args),
+				(const void *)&src_args,
+				sizeof(struct notify_cmd_args_is_registered));
+		if (size != 0) {
+			os_status = -EFAULT;
+			goto func_end;
+		}
+	}
+	break;
+
+	default:
+	{
+		/* This does not impact return status of this function,so retval
+		 * comment is not used. */
+		status = NOTIFY_E_INVALIDARG;
+		printk(KERN_ERR "not valid command\n");
+	}
+	break;
+	}
+
+func_end:
+	/* Set the status and copy the common args to user-side. */
+	common_args.api_status = status;
+	size = copy_to_user((void *) cmd_args, (const void *) &common_args,
+				sizeof(struct notify_cmd_args));
+	if (size < 0)
+		os_status = -EFAULT;
+	return os_status;
+}
+
+/* This function implements the callback registered with IPS. Here
+ * to pass event no. back to user function(so that it can do another
+ * level of demultiplexing of callbacks) */
+static void _notify_drv_callback(u16 proc_id, u16 line_id, u32 event_id,
+					uint *arg, u32 payload)
+{
+	struct notify_drv_event_cbck *cbck;
+	int status = 0;
+
+	if (WARN_ON(notifydrv_state.is_setup == false)) {
+		status = -EFAULT;
+		goto func_end;
+	}
+
+	if (WARN_ON(arg == NULL)) {
+		status = -EINVAL;
+		goto func_end;
+	}
+
+	cbck = (struct notify_drv_event_cbck *)arg;
+	status = _notify_drv_add_buf_by_pid(proc_id, line_id, cbck->pid,
+				event_id, payload, cbck->func, cbck->param);
+
+func_end:
+	if (status < 0) {
+		printk(KERN_ERR "_notify_drv_callback failed! status = 0x%x",
+			status);
+	}
+	return;
+}
+
+/* This function adds a data to a registered process. */
+static int _notify_drv_add_buf_by_pid(u16 proc_id, u16 line_id, u32 pid,
+					u32 event_id, u32 data,
+					notify_fn_notify_cbck cb_fxn,
+					void *param)
+{
+	s32 status = 0;
+	bool flag = false;
+	bool is_exit = false;
+	struct notify_drv_event_packet *u_buf = NULL;
+	u32 i;
+
+	WARN_ON(mutex_lock_interruptible(notifydrv_state.gate_handle));
+	for (i = 0; (i < MAX_PROCESSES) && (flag != true); i++) {
+		if (notifydrv_state.event_state[i].pid == pid) {
+			flag = true;
+			break;
+		}
+	}
+	mutex_unlock(notifydrv_state.gate_handle);
+
+	if (WARN_ON(flag == false)) {
+		status = -EFAULT;
+		goto func_end;
+	}
+
+	u_buf = kmalloc(sizeof(struct notify_drv_event_packet), GFP_ATOMIC);
+	if (u_buf == NULL) {
+		status = -ENOMEM;
+		goto func_end;
+	}
+
+	INIT_LIST_HEAD((struct list_head *)&u_buf->element);
+	u_buf->proc_id = proc_id;
+	u_buf->line_id = line_id;
+	u_buf->data = data;
+	u_buf->event_id = event_id;
+	u_buf->func = cb_fxn;
+	u_buf->param = param;
+	u_buf->is_exit = false;
+	if (u_buf->event_id == (u32) -1) {
+		u_buf->is_exit = true;
+		is_exit = true;
+	}
+	WARN_ON(mutex_lock_interruptible(notifydrv_state.gate_handle));
+	list_add_tail((struct list_head *)&(u_buf->element),
+		(struct list_head *)&(notifydrv_state.event_state[i].buf_list));
+	mutex_unlock(notifydrv_state.gate_handle);
+	up(notifydrv_state.event_state[i].semhandle);
+
+	/* Termination packet */
+	if (is_exit == true) {
+		if (down_interruptible(
+			notifydrv_state.event_state[i].tersemhandle))
+			status = NOTIFY_E_OSFAILURE;
+	}
+
+func_end:
+	if (status < 0) {
+		printk(KERN_ERR "_notify_drv_add_buf_by_pid failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+
+/* Module setup function.*/
+void _notify_drv_setup(void)
+{
+	int i;
+
+	INIT_LIST_HEAD((struct list_head *)&(notifydrv_state.event_cbck_list));
+	INIT_LIST_HEAD(
+		(struct list_head *)&(notifydrv_state.single_event_cbck_list));
+	notifydrv_state.gate_handle = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	mutex_init(notifydrv_state.gate_handle);
+	for (i = 0; i < MAX_PROCESSES; i++) {
+		notifydrv_state.event_state[i].pid = -1;
+		notifydrv_state.event_state[i].ref_count = 0;
+		INIT_LIST_HEAD((struct list_head *)
+			&(notifydrv_state.event_state[i].buf_list));
+	}
+	notifydrv_state.is_setup = true;
+}
+
+/* Module destroy function.*/
+void _notify_drv_destroy(void)
+{
+	int i;
+	struct notify_drv_event_packet *packet;
+	struct list_head *entry;
+	struct notify_drv_event_cbck *cbck;
+
+	for (i = 0; i < MAX_PROCESSES; i++) {
+		notifydrv_state.event_state[i].pid = -1;
+		notifydrv_state.event_state[i].ref_count = 0;
+		/* Free event packets for any received but unprocessed events.*/
+		list_for_each(entry, (struct list_head *)
+				&(notifydrv_state.event_state[i].buf_list)) {
+			packet = (struct notify_drv_event_packet *)entry;
+			if (packet != NULL)
+				kfree(packet);
+		}
+		INIT_LIST_HEAD(&notifydrv_state.event_state[i].buf_list);
+	}
+
+	/* Clear any event registrations that were not unregistered. */
+	list_for_each(entry, (struct list_head *)
+			&(notifydrv_state.event_cbck_list)) {
+		cbck = (struct notify_drv_event_cbck *)(entry);
+		if (cbck != NULL)
+			kfree(cbck);
+	}
+	INIT_LIST_HEAD(&notifydrv_state.event_cbck_list);
+
+	/* Clear any event registrations that were not unregistered from single
+	* list. */
+	list_for_each(entry,
+		(struct list_head *)&(notifydrv_state.single_event_cbck_list)) {
+		cbck = (struct notify_drv_event_cbck *)(entry);
+		if (cbck != NULL)
+			kfree(cbck);
+	}
+	INIT_LIST_HEAD(&notifydrv_state.single_event_cbck_list);
+
+	mutex_destroy(notifydrv_state.gate_handle);
+	kfree(notifydrv_state.gate_handle);
+	notifydrv_state.is_setup = false;
+	return;
+}
+
+/* Attach a process to notify user support framework. */
+static int notify_drv_attach(u32 pid)
+{
+	bool flag = false;
+	bool is_init = false;
+	u32 i;
+	struct semaphore *sem_handle = NULL;
+	struct semaphore *ter_sem_handle = NULL;
+	int ret_val = 0;
+
+	if (WARN_ON(notifydrv_state.is_setup == false)) {
+		ret_val = NOTIFY_E_FAIL;
+		goto exit;
+	}
+
+	WARN_ON(mutex_lock_interruptible(notifydrv_state.gate_handle));
+	for (i = 0; (i < MAX_PROCESSES); i++) {
+		if (notifydrv_state.event_state[i].pid == pid) {
+			notifydrv_state.event_state[i].ref_count++;
+			is_init = true;
+			break;
+		}
+	}
+	if (is_init == true) {
+		mutex_unlock(notifydrv_state.gate_handle);
+		return 0;
+	}
+
+	sem_handle = kmalloc(sizeof(struct semaphore), GFP_ATOMIC);
+	ter_sem_handle = kmalloc(sizeof(struct semaphore), GFP_ATOMIC);
+	if (sem_handle == NULL || ter_sem_handle == NULL) {
+		ret_val = -ENOMEM;
+		goto sem_fail;
+	}
+	sema_init(sem_handle, 0);
+	/* Create the termination semaphore */
+	sema_init(ter_sem_handle, 0);
+
+	/* Search for an available slot for user process. */
+	for (i = 0; i < MAX_PROCESSES; i++) {
+		if (notifydrv_state.event_state[i].pid == -1) {
+			notifydrv_state.event_state[i].semhandle = \
+						sem_handle;
+			notifydrv_state.event_state[i].tersemhandle = \
+						ter_sem_handle;
+			notifydrv_state.event_state[i].pid = pid;
+			notifydrv_state.event_state[i].ref_count = 1;
+			INIT_LIST_HEAD(&(notifydrv_state.event_state[i].
+							buf_list));
+			flag = true;
+			break;
+		}
+	}
+	mutex_unlock(notifydrv_state.gate_handle);
+
+	if (WARN_ON(flag != true)) {
+		/* Max users have registered. No more clients
+		 * can be supported */
+		ret_val = NOTIFY_E_RESOURCE;
+		goto sem_fail;
+	}
+
+	return 0;
+
+sem_fail:
+	kfree(ter_sem_handle);
+	kfree(sem_handle);
+exit:
+	return ret_val;
+}
+
+
+/* Detach a process from notify user support framework. */
+static int notify_drv_detach(u32 pid)
+{
+	s32 status = NOTIFY_S_SUCCESS;
+	bool flag = false;
+	u32 i;
+	struct semaphore *sem_handle;
+	struct semaphore *ter_sem_handle;
+
+	if (WARN_ON(notifydrv_state.is_setup == false)) {
+		status = NOTIFY_E_FAIL;
+		goto func_end;
+	}
+
+	/* Send the termination packet to notify thread */
+	status = _notify_drv_add_buf_by_pid(0, 0, pid, (u32)-1, (u32)0, NULL,
+						NULL);
+
+	WARN_ON(mutex_lock_interruptible(notifydrv_state.gate_handle));
+	for (i = 0; i < MAX_PROCESSES; i++) {
+		if (notifydrv_state.event_state[i].pid == pid) {
+			if (notifydrv_state.event_state[i].ref_count == 1) {
+				/* Last client being unregistered for this
+				* process*/
+				notifydrv_state.event_state[i].pid = -1;
+				notifydrv_state.event_state[i].ref_count = 0;
+				sem_handle =
+				notifydrv_state.event_state[i].semhandle;
+				ter_sem_handle =
+				notifydrv_state.event_state[i].tersemhandle;
+				INIT_LIST_HEAD((struct list_head *)
+				&(notifydrv_state.event_state[i].buf_list));
+				notifydrv_state.event_state[i].semhandle =
+								NULL;
+				notifydrv_state.event_state[i].tersemhandle =
+								NULL;
+				flag = true;
+				break;
+			} else
+				notifydrv_state.event_state[i].ref_count--;
+		}
+	}
+	mutex_unlock(notifydrv_state.gate_handle);
+
+	if ((flag == false) && (i == MAX_PROCESSES)) {
+		/* The specified user process was not found registered with
+		 * Notify Driver module. */
+		status = NOTIFY_E_NOTFOUND;
+	} else {
+		kfree(sem_handle);
+		kfree(ter_sem_handle);
+	}
+
+func_end:
+	return status;
+}
diff --git a/drivers/dsp/syslink/omap_notify/notify.c b/drivers/dsp/syslink/omap_notify/notify.c
new file mode 100644
index 000000000000..c826121b486e
--- /dev/null
+++ b/drivers/dsp/syslink/omap_notify/notify.c
@@ -0,0 +1,1140 @@
+/*
+ * notify.c
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <asm/pgtable.h>
+
+#include <syslink/atomic_linux.h>
+#include <syslink/multiproc.h>
+#include <syslink/notify.h>
+#include <syslink/_notify.h>
+#include <syslink/notifydefs.h>
+#include <syslink/notify_driver.h>
+#include <syslink/notify_setup_proxy.h>
+
+struct notify_event_listener {
+	struct list_head element;
+	struct notify_event_callback callback;
+};
+
+/* Function registered with notify_exec when multiple registrations are present
+ * for the events. */
+static void _notify_exec_many(u16 proc_id, u16 line_id, u32 event_id, uint *arg,
+			u32 payload);
+
+struct notify_module_object notify_state = {
+	.def_cfg.num_events = 32u,
+	.def_cfg.send_event_poll_count = -1u,
+	.def_cfg.num_lines = 1u,
+	.def_cfg.reserved_events = 3u,
+	.gate_handle = NULL,
+	.local_notify_handle = NULL
+};
+
+/* Get the default configuration for the Notify module. */
+void notify_get_config(struct notify_config *cfg)
+{
+	s32 retval = 0;
+
+	if (WARN_ON(unlikely(cfg == NULL))) {
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	if (atomic_cmpmask_and_lt(&(notify_state.ref_count),
+			NOTIFY_MAKE_MAGICSTAMP(0),
+			NOTIFY_MAKE_MAGICSTAMP(1)) == true)
+		memcpy(cfg, &notify_state.def_cfg,
+			sizeof(struct notify_config));
+	else
+		memcpy(cfg, &notify_state.cfg, sizeof(struct notify_config));
+
+exit:
+	if (retval < 0) {
+		printk(KERN_ERR "notify_get_config failed! status = 0x%x",
+			retval);
+	}
+	return;
+}
+EXPORT_SYMBOL(notify_get_config);
+
+/* This function sets up the Notify module. This function must be called
+ * before any other instance-level APIs can be invoked. */
+int notify_setup(struct notify_config *cfg)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_config tmp_cfg;
+
+	atomic_cmpmask_and_set(&notify_state.ref_count,
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(0));
+	if (atomic_inc_return(&notify_state.ref_count)
+				!= NOTIFY_MAKE_MAGICSTAMP(1u)) {
+		return NOTIFY_S_ALREADYSETUP;
+	}
+
+	if (cfg == NULL) {
+		notify_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	if (cfg->num_events > NOTIFY_MAXEVENTS) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (cfg->num_lines > NOTIFY_MAX_INTLINES) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (cfg->reserved_events > cfg->num_events) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	notify_state.gate_handle = kmalloc(sizeof(struct mutex), GFP_ATOMIC);
+	if (notify_state.gate_handle == NULL) {
+		status = NOTIFY_E_FAIL;
+		goto exit;
+	}
+	/*User has not provided any gate handle,
+	so create a default handle.*/
+	mutex_init(notify_state.gate_handle);
+
+	memcpy(&notify_state.cfg, cfg, sizeof(struct notify_config));
+	notify_state.local_enable_mask = -1u;
+	notify_state.start_complete = false;
+	memset(&notify_state.drivers, 0, (sizeof(struct notify_driver_object) *
+				NOTIFY_MAX_DRIVERS * NOTIFY_MAX_INTLINES));
+
+	/* tbd: Should return Notify_Handle */
+	notify_state.local_notify_handle = notify_create(NULL, multiproc_self(),
+								0, NULL);
+	if (notify_state.local_notify_handle == NULL) {
+		status = NOTIFY_E_FAIL;
+		goto local_notify_fail;
+	}
+	return 0;
+
+local_notify_fail:
+	kfree(notify_state.gate_handle);
+exit:
+	atomic_set(&notify_state.ref_count, NOTIFY_MAKE_MAGICSTAMP(0));
+	printk(KERN_ERR "notify_setup failed! status = 0x%x", status);
+	return status;
+}
+EXPORT_SYMBOL(notify_setup);
+
+/* Once this function is called, other Notify module APIs,
+ * except for the Notify_getConfig API cannot be called anymore. */
+int notify_destroy(void)
+{
+	int i;
+	int j;
+	int status = NOTIFY_S_SUCCESS;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (!(atomic_dec_return(&notify_state.ref_count)
+			== NOTIFY_MAKE_MAGICSTAMP(0)))
+		return NOTIFY_S_ALREADYSETUP;
+
+	/* Temporarily increment refCount here. */
+	atomic_set(&notify_state.ref_count, NOTIFY_MAKE_MAGICSTAMP(1));
+	if (notify_state.local_notify_handle != NULL)
+		status = notify_delete(&notify_state.local_notify_handle);
+	atomic_set(&notify_state.ref_count, NOTIFY_MAKE_MAGICSTAMP(0));
+
+	/* Check if any Notify driver instances have
+	 * not been deleted so far. If not, assert. */
+	for (i = 0; i < NOTIFY_MAX_DRIVERS; i++)
+		for (j = 0; j < NOTIFY_MAX_INTLINES; j++)
+			WARN_ON(notify_state.drivers[i][j].is_init != false);
+
+	kfree(notify_state.gate_handle);
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "notify_destroy failed! status = 0x%x", status);
+	return status;
+}
+EXPORT_SYMBOL(notify_destroy);
+
+/* Function to create an instance of Notify driver */
+struct notify_object *notify_create(void *driver_handle, u16 remote_proc_id,
+			u16 line_id, const struct notify_params *params)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_object *obj = NULL;
+	uint i;
+
+	/* driver_handle can be NULL for local create */
+	/* params can be NULL */
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(remote_proc_id >= \
+					multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	/* Allocate memory for the Notify object. */
+	obj = kzalloc(sizeof(struct notify_object), GFP_KERNEL);
+	if (obj == NULL) {
+		status = NOTIFY_E_MEMORY;
+		goto exit;
+	}
+
+	obj->remote_proc_id = remote_proc_id;
+	obj->line_id = line_id;
+	obj->nesting = 0;
+
+	for (i = 0; i < notify_state.cfg.num_events; i++)
+		INIT_LIST_HEAD(&obj->event_list[i]);
+
+	/* Used solely for remote driver
+	 * (NULL if remote_proc_id == self) */
+	obj->driver_handle = driver_handle;
+	/* Send this handle to the NotifyDriver */
+	status = notify_set_driver_handle(remote_proc_id, line_id, obj);
+	if (status < 0)
+		goto notify_handle_fail;
+
+	/* For local notify */
+	if (driver_handle == NULL)
+		/* Set driver status to indicate that it is done. */
+		notify_state.drivers[multiproc_self()][line_id].is_init =
+			NOTIFY_DRIVERINITSTATUS_DONE;
+	return obj;
+
+notify_handle_fail:
+	notify_set_driver_handle(remote_proc_id, line_id, NULL);
+	kfree(obj);
+	obj = NULL;
+exit:
+	if (status < 0)
+		printk(KERN_ERR "notify_create failed! status = 0x%x", status);
+	return obj;
+}
+
+
+/* Function to delete an instance of Notify driver */
+int notify_delete(struct notify_object **handle_ptr)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_object *obj;
+	u16 i;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((handle_ptr == NULL) || (*handle_ptr == NULL)))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	obj = (struct notify_object *)(*handle_ptr);
+
+	if (obj->remote_proc_id == multiproc_self()) {
+		notify_state.drivers[multiproc_self()][obj->line_id].is_init =
+			NOTIFY_DRIVERINITSTATUS_NOTDONE;
+	}
+	notify_set_driver_handle(obj->remote_proc_id, obj->line_id, NULL);
+	for (i = 0; i < notify_state.cfg.num_events; i++)
+		INIT_LIST_HEAD(&obj->event_list[i]);
+
+	kfree(obj);
+	obj = NULL;
+	*handle_ptr = NULL;
+
+exit:
+	if (status < 0)
+		printk(KERN_ERR "notify_delete failed! status = 0x%x", status);
+	return status;
+}
+
+/* This function registers a callback for a specific event with the
+ * Notify module. */
+int notify_register_event(u16 proc_id, u16 line_id, u32 event_id,
+		notify_fn_notify_cbck notify_callback_fxn, void *cbck_arg)
+{
+	int status = NOTIFY_S_SUCCESS;
+	u32 stripped_event_id = (event_id & NOTIFY_EVENT_MASK);
+	struct notify_driver_object *driver_handle;
+	struct list_head *event_list;
+	struct notify_event_listener *listener;
+	bool list_was_empty;
+	struct notify_object *obj;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(notify_callback_fxn == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((stripped_event_id >= \
+					notify_state.cfg.num_events)))) {
+		status = NOTIFY_E_EVTNOTREGISTERED;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(!ISRESERVED(event_id,
+				notify_state.cfg.reserved_events)))) {
+		status = NOTIFY_E_EVTRESERVED;
+		goto exit;
+	}
+
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	listener = kmalloc(sizeof(struct notify_event_listener), GFP_KERNEL);
+	if (listener == NULL) {
+		status = NOTIFY_E_MEMORY;
+		goto exit_unlock_mutex;
+	}
+	listener->callback.fn_notify_cbck = notify_callback_fxn;
+	listener->callback.cbck_arg = cbck_arg;
+
+	event_list = &(obj->event_list[stripped_event_id]);
+	list_was_empty = list_empty(event_list);
+	list_add_tail((struct list_head *) listener, event_list);
+	mutex_unlock(notify_state.gate_handle);
+	if (list_was_empty) {
+		/* Registering this event for the first time. Need to
+		 * register the callback function.
+		 */
+		status = notify_register_event_single(proc_id, line_id,
+					event_id, _notify_exec_many,
+					(uint *) obj);
+	}
+	goto exit;
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_register_event failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(notify_register_event);
+
+/* This function registers a single callback for a specific event with the
+ * Notify module. */
+int notify_register_event_single(u16 proc_id, u16 line_id, u32 event_id,
+		notify_fn_notify_cbck notify_callback_fxn, void *cbck_arg)
+{
+	int status = NOTIFY_S_SUCCESS;
+	u32 stripped_event_id = (event_id & NOTIFY_EVENT_MASK);
+	struct notify_driver_object *driver_handle;
+	struct notify_object *obj;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(notify_callback_fxn == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((stripped_event_id >= \
+					notify_state.cfg.num_events)))) {
+		status = NOTIFY_E_EVTNOTREGISTERED;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(!ISRESERVED(event_id,
+				notify_state.cfg.reserved_events)))) {
+		status = NOTIFY_E_EVTRESERVED;
+		goto exit;
+	}
+
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	if (obj->callbacks[stripped_event_id].fn_notify_cbck != NULL) {
+		status = NOTIFY_E_ALREADYEXISTS;
+		goto exit_unlock_mutex;
+	}
+
+	obj->callbacks[stripped_event_id].fn_notify_cbck = notify_callback_fxn;
+	obj->callbacks[stripped_event_id].cbck_arg = cbck_arg;
+
+	if (proc_id != multiproc_self()) {
+		status = driver_handle->fxn_table.register_event(driver_handle,
+							stripped_event_id);
+	}
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_register_event_single failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(notify_register_event_single);
+
+/* This function un-registers the callback for the specific event with
+ * the Notify module. */
+int notify_unregister_event(u16 proc_id, u16 line_id, u32 event_id,
+		notify_fn_notify_cbck notify_callback_fxn, void *cbck_arg)
+{
+	int status = NOTIFY_S_SUCCESS;
+	u32 stripped_event_id = (event_id & NOTIFY_EVENT_MASK);
+	struct notify_event_listener *listener;
+	bool found = false;
+	struct notify_driver_object *driver_handle;
+	struct list_head *event_list;
+	struct notify_object *obj;
+	/*int *sys_key;*/
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(notify_callback_fxn == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((stripped_event_id >= \
+					notify_state.cfg.num_events)))) {
+		status = NOTIFY_E_EVTNOTREGISTERED;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(!ISRESERVED(event_id,
+				notify_state.cfg.reserved_events)))) {
+		status = NOTIFY_E_EVTRESERVED;
+		goto exit;
+	}
+
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	event_list = &(obj->event_list[stripped_event_id]);
+	if (list_empty(event_list)) {
+		status = NOTIFY_E_NOTFOUND;
+		goto exit_unlock_mutex;
+	}
+
+	list_for_each_entry(listener, event_list, element) {
+		/* Hash not matches, take next node */
+		if ((listener->callback.fn_notify_cbck == notify_callback_fxn)
+			&& (listener->callback.cbck_arg == cbck_arg)) {
+			found = true;
+			break;
+		}
+	}
+	if (found == false) {
+		status = NOTIFY_E_NOTFOUND;
+		goto exit_unlock_mutex;
+	}
+	/*sys_key = Gate_enterSystem();*/
+	list_del((struct list_head *)listener);
+	/*Gate_leaveSystem(sys_key);*/
+	mutex_unlock(notify_state.gate_handle);
+
+	if (list_empty(event_list)) {
+		status = notify_unregister_event_single(proc_id, line_id,
+								event_id);
+	}
+	kfree(listener);
+	goto exit;
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_unregister_event failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(notify_unregister_event);
+
+/* This function un-registers a single callback for the specific event with
+ * the Notify module. */
+int notify_unregister_event_single(u16 proc_id, u16 line_id, u32 event_id)
+{
+	int status = NOTIFY_S_SUCCESS;
+	u32 stripped_event_id = (event_id & NOTIFY_EVENT_MASK);
+	struct notify_driver_object *driver_handle;
+	struct notify_object *obj;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((stripped_event_id >= \
+					notify_state.cfg.num_events)))) {
+		status = NOTIFY_E_EVTNOTREGISTERED;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(!ISRESERVED(event_id,
+				notify_state.cfg.reserved_events)))) {
+		status = NOTIFY_E_EVTRESERVED;
+		goto exit;
+	}
+
+	status = mutex_lock_interruptible(notify_state.gate_handle);
+	if (status)
+		goto exit;
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	if (obj->callbacks[stripped_event_id].fn_notify_cbck == NULL) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj->callbacks[stripped_event_id].fn_notify_cbck = NULL;
+	obj->callbacks[stripped_event_id].cbck_arg = NULL;
+	if (proc_id != multiproc_self()) {
+		status = driver_handle->fxn_table.unregister_event(
+					driver_handle, stripped_event_id);
+	}
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_unregister_event_single failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(notify_unregister_event_single);
+
+/* This function sends a notification to the specified event. */
+int notify_send_event(u16 proc_id, u16 line_id, u32 event_id, u32 payload,
+				bool wait_clear)
+{
+	int status = NOTIFY_S_SUCCESS;
+	u32 stripped_event_id = (event_id & NOTIFY_EVENT_MASK);
+	struct notify_driver_object *driver_handle;
+	struct notify_object *obj;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((stripped_event_id >= \
+					notify_state.cfg.num_events)))) {
+		status = NOTIFY_E_EVTNOTREGISTERED;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(!ISRESERVED(event_id,
+				notify_state.cfg.reserved_events)))) {
+		status = NOTIFY_E_EVTRESERVED;
+		goto exit;
+	}
+
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+			WARN_ON(1);
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	if (proc_id != multiproc_self()) {
+		status = driver_handle->fxn_table.send_event(driver_handle,
+					stripped_event_id, payload, wait_clear);
+	} else {
+		/* If nesting == 0 (the driver is enabled) and the event is
+		 * enabled, send the event */
+		if (obj->callbacks[stripped_event_id].fn_notify_cbck == NULL) {
+			/* No callbacks are registered locally for the event. */
+			status = NOTIFY_E_EVTNOTREGISTERED;
+		} else if (obj->nesting != 0) {
+			/* Driver is disabled */
+			status = NOTIFY_E_FAIL;
+		} else if (!test_bit(stripped_event_id, (unsigned long *)
+				&notify_state.local_enable_mask)) {
+			/* Event is disabled */
+			status = NOTIFY_E_EVTDISABLED;
+		} else {
+			/* Leave critical section protection. */
+			mutex_unlock(notify_state.gate_handle);
+			/* Execute the callback function registered to the
+			 * event */
+			notify_exec(obj, event_id, payload);
+			/* Enter critical section protection. TBD: nesting */
+			if (mutex_lock_interruptible(notify_state.gate_handle))
+				WARN_ON(1);
+		}
+	}
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_send_event failed! status = 0x%x",
+			status);
+	}
+	return status;
+}
+EXPORT_SYMBOL(notify_send_event);
+
+/* This function disables all events. This is equivalent to global
+ * interrupt disable, however restricted within interrupts handled by
+ * the Notify module. All callbacks registered for all events are
+ * disabled with this API. It is not possible to disable a specific
+ * callback. */
+u32 notify_disable(u16 proc_id, u16 line_id)
+{
+	uint key = 0;
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_driver_object *driver_handle;
+	struct notify_object *obj;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj->nesting++;
+	if (obj->nesting == 1) {
+		/* Disable receiving all events */
+		if (proc_id != multiproc_self())
+			driver_handle->fxn_table.disable(driver_handle);
+	}
+	key = obj->nesting;
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0)
+		printk(KERN_ERR "notify_disable failed! status = 0x%x", status);
+	return key;
+}
+EXPORT_SYMBOL(notify_disable);
+
+/* This function restores the Notify module to the state before the
+ * last notify_disable() was called. This is equivalent to global
+ * interrupt restore, however restricted within interrupts handled by
+ * the Notify module. All callbacks registered for all events as
+ * specified in the flags are enabled with this API. It is not possible
+ * to enable a specific callback. */
+void notify_restore(u16 proc_id, u16 line_id, u32 key)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_driver_object *driver_handle;
+	struct notify_object *obj;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	if (key != obj->nesting) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit_unlock_mutex;
+	}
+
+	obj->nesting--;
+	if (obj->nesting == 0) {
+		/* Enable receiving events */
+		if (proc_id != multiproc_self())
+			driver_handle->fxn_table.enable(driver_handle);
+	}
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0)
+		printk(KERN_ERR "notify_restore failed! status = 0x%x", status);
+	return;
+}
+EXPORT_SYMBOL(notify_restore);
+
+/* This function disables a specific event. All callbacks registered
+ * for the specific event are disabled with this API. It is not
+ * possible to disable a specific callback. */
+void notify_disable_event(u16 proc_id, u16 line_id, u32 event_id)
+{
+	int status = 0;
+	u32 stripped_event_id = (event_id & NOTIFY_EVENT_MASK);
+	struct notify_driver_object *driver_handle;
+	struct notify_object *obj;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((stripped_event_id >= \
+					notify_state.cfg.num_events)))) {
+		status = NOTIFY_E_EVTNOTREGISTERED;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(!ISRESERVED(event_id,
+				notify_state.cfg.reserved_events)))) {
+		status = NOTIFY_E_EVTRESERVED;
+		goto exit;
+	}
+
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	if (proc_id != multiproc_self()) {
+		driver_handle->fxn_table.disable_event(driver_handle,
+							stripped_event_id);
+	} else {
+		clear_bit(stripped_event_id,
+			(unsigned long *) &notify_state.local_enable_mask);
+	}
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_disable_event failed! status = 0x%x",
+			status);
+	}
+	return;
+}
+EXPORT_SYMBOL(notify_disable_event);
+
+/* This function enables a specific event. All callbacks registered for
+ * this specific event are enabled with this API. It is not possible to
+ * enable a specific callback. */
+void notify_enable_event(u16 proc_id, u16 line_id, u32 event_id)
+{
+	int status = 0;
+	u32 stripped_event_id = (event_id & NOTIFY_EVENT_MASK);
+	struct notify_driver_object *driver_handle;
+	struct notify_object *obj;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely((stripped_event_id >= \
+					notify_state.cfg.num_events)))) {
+		status = NOTIFY_E_EVTNOTREGISTERED;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(!ISRESERVED(event_id,
+				notify_state.cfg.reserved_events)))) {
+		status = NOTIFY_E_EVTRESERVED;
+		goto exit;
+	}
+
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_DRIVERNOTREGISTERED;
+		goto exit_unlock_mutex;
+	}
+	if (WARN_ON(driver_handle->is_init != NOTIFY_DRIVERINITSTATUS_DONE)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	obj = (struct notify_object *)driver_handle->notify_handle;
+	if (WARN_ON(obj == NULL)) {
+		status = NOTIFY_E_FAIL;
+		goto exit_unlock_mutex;
+	}
+
+	if (proc_id != multiproc_self()) {
+		driver_handle->fxn_table.enable_event(driver_handle,
+							stripped_event_id);
+	} else {
+		set_bit(stripped_event_id,
+			(unsigned long *)&notify_state.local_enable_mask);
+	}
+
+exit_unlock_mutex:
+	mutex_unlock(notify_state.gate_handle);
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_enable_event failed! status = 0x%x",
+			status);
+	}
+	return;
+}
+EXPORT_SYMBOL(notify_enable_event);
+
+/* Whether notification via interrupt line has been registered. */
+bool notify_is_registered(u16 proc_id, u16 line_id)
+{
+	int status = NOTIFY_S_SUCCESS;
+	bool is_registered = false;
+	struct notify_driver_object *driver_handle;
+
+	if (WARN_ON(unlikely(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+				NOTIFY_MAKE_MAGICSTAMP(0),
+				NOTIFY_MAKE_MAGICSTAMP(1)) == true))) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id >= multiproc_get_num_processors()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(line_id >= NOTIFY_MAX_INTLINES))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	driver_handle = notify_get_driver_handle(proc_id, line_id);
+	if ((driver_handle != NULL) && (driver_handle->notify_handle != NULL))
+		is_registered = true;
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_is_registered failed! status = 0x%x",
+			status);
+	}
+	return is_registered;
+}
+EXPORT_SYMBOL(notify_is_registered);
+
+/* Creates notify drivers and registers them with Notify */
+int notify_attach(u16 proc_id, void *shared_addr)
+{
+	int status = NOTIFY_S_SUCCESS;
+
+	/* Use the NotifySetup proxy to setup drivers */
+	status = notify_setup_proxy_attach(proc_id, shared_addr);
+
+	notify_state.start_complete = true;
+
+	return status;
+}
+EXPORT_SYMBOL(notify_attach);
+
+/* Creates notify drivers and registers them with Notify */
+int notify_detach(u16 proc_id)
+{
+	int status = 0;
+
+	/* Use the NotifySetup proxy to destroy drivers */
+	status = notify_setup_proxy_detach(proc_id);
+
+	notify_state.start_complete = false;
+
+	return status;
+}
+EXPORT_SYMBOL(notify_detach);
+
+/* Returns the total amount of shared memory used by the Notify module
+ * and all instances after notify_start has been called. */
+uint notify_shared_mem_req(u16 proc_id, void *shared_addr)
+{
+	uint mem_req = 0x0;
+
+	if (multiproc_get_num_processors() > 1)
+		/* Determine device-specific shared memory requirements */
+		mem_req = notify_setup_proxy_shared_mem_req(proc_id,\
+								shared_addr);
+	else
+		/* Only 1 processor: no shared memory needed */
+		mem_req = 0;
+
+	return mem_req;
+}
+
+/* Indicates whether notify_start is completed. */
+inline bool _notify_start_complete(void)
+{
+	return notify_state.start_complete;
+}
+
+/* Function registered as callback with the Notify driver */
+void notify_exec(struct notify_object *obj, u32 event_id, u32 payload)
+{
+	struct notify_event_callback *callback;
+
+	WARN_ON(obj == NULL);
+	WARN_ON(event_id >= notify_state.cfg.num_events);
+
+	callback = &(obj->callbacks[event_id]);
+	WARN_ON(callback->fn_notify_cbck == NULL);
+
+	/* Execute the callback function with its argument and the payload */
+	callback->fn_notify_cbck(obj->remote_proc_id, obj->line_id, event_id,
+				callback->cbck_arg, payload);
+}
+
+
+/* Function registered with notify_exec when multiple registrations are present
+ * for the events. */
+void _notify_exec_many(u16 proc_id, u16 line_id, u32 event_id, uint *arg,
+			u32 payload)
+{
+	struct notify_object *obj = (struct notify_object *)arg;
+	struct list_head *event_list;
+	struct notify_event_listener *listener;
+
+	WARN_ON(proc_id >= multiproc_get_num_processors());
+	WARN_ON(obj == NULL);
+	WARN_ON(line_id >= NOTIFY_MAX_INTLINES);
+	WARN_ON(event_id >= notify_state.cfg.num_events);
+
+	/* Both loopback and the the event itself are enabled */
+	event_list = &(obj->event_list[event_id]);
+
+	/* Enter critical section protection. */
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	/* Use "NULL" to get the first EventListener on the list */
+	list_for_each_entry(listener, event_list, element) {
+		/* Leave critical section protection. */
+		mutex_unlock(notify_state.gate_handle);
+		listener->callback.fn_notify_cbck(proc_id, line_id, event_id,
+				listener->callback.cbck_arg, payload);
+		/* Enter critical section protection. */
+		if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+			WARN_ON(1);
+	}
+
+	/* Leave critical section protection. */
+	mutex_unlock(notify_state.gate_handle);
+}
diff --git a/drivers/dsp/syslink/omap_notify/notify_driver.c b/drivers/dsp/syslink/omap_notify/notify_driver.c
new file mode 100644
index 000000000000..2de9ae90d49c
--- /dev/null
+++ b/drivers/dsp/syslink/omap_notify/notify_driver.c
@@ -0,0 +1,186 @@
+/*
+ * notify_driver.c
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/uaccess.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <asm/pgtable.h>
+
+#include <syslink/gt.h>
+#include <syslink/notify.h>
+#include <syslink/notify_driver.h>
+#include <syslink/notifydefs.h>
+#include <syslink/atomic_linux.h>
+
+
+/* Function to register driver with the Notify module. */
+int notify_register_driver(u16 remote_proc_id,
+			u16 line_id,
+			struct notify_driver_fxn_table *fxn_table,
+			struct notify_driver_object **driver_handle)
+{
+	int status = NOTIFY_S_SUCCESS;
+	struct notify_driver_object *drv_handle = NULL;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+			NOTIFY_MAKE_MAGICSTAMP(0),
+			NOTIFY_MAKE_MAGICSTAMP(1)) == true)) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(fxn_table == NULL)) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(remote_proc_id >= multiproc_get_num_processors())) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(line_id >= NOTIFY_MAX_INTLINES)) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(driver_handle == NULL)) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	*driver_handle = NULL;
+	if (mutex_lock_interruptible(notify_state.gate_handle) != 0)
+		WARN_ON(1);
+	drv_handle = &(notify_state.drivers[remote_proc_id][line_id]);
+	if (drv_handle->is_init == NOTIFY_DRIVERINITSTATUS_DONE) {
+		status = NOTIFY_E_ALREADYEXISTS;
+		mutex_unlock(notify_state.gate_handle);
+		goto exit;
+	}
+	mutex_unlock(notify_state.gate_handle);
+	WARN_ON(status < 0);
+
+	/*Complete registration of the driver. */
+	memcpy(&(drv_handle->fxn_table), fxn_table,
+				sizeof(struct notify_driver_fxn_table));
+	drv_handle->notify_handle = NULL; /* Initialize to NULL. */
+	drv_handle->is_init = NOTIFY_DRIVERINITSTATUS_DONE;
+	*driver_handle = drv_handle;
+
+exit:
+	return status;
+}
+EXPORT_SYMBOL(notify_register_driver);
+
+/* Function to unregister driver with the Notify module. */
+int notify_unregister_driver(struct notify_driver_object *drv_handle)
+{
+	int status = NOTIFY_E_FAIL;
+	s32 key;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+			NOTIFY_MAKE_MAGICSTAMP(0),
+			NOTIFY_MAKE_MAGICSTAMP(1)) == true)) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(drv_handle == NULL)) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	key = mutex_lock_interruptible(notify_state.gate_handle);
+	if (key)
+		goto exit;
+
+	/* Unregister the driver. */
+	drv_handle->is_init = NOTIFY_DRIVERINITSTATUS_NOTDONE;
+	mutex_unlock(notify_state.gate_handle);
+	status = NOTIFY_S_SUCCESS;
+
+exit:
+	return status;
+}
+EXPORT_SYMBOL(notify_unregister_driver);
+
+/* Function to set the Notify object handle maintained within the
+ * Notify module. */
+int notify_set_driver_handle(u16 remote_proc_id, u16 line_id,
+				struct notify_object *handle)
+{
+	s32 status = NOTIFY_S_SUCCESS;
+
+	/* Handle can be set to NULL */
+	if (WARN_ON(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+			NOTIFY_MAKE_MAGICSTAMP(0),
+			NOTIFY_MAKE_MAGICSTAMP(1)) == true)) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(remote_proc_id >= multiproc_get_num_processors())) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(line_id >= NOTIFY_MAX_INTLINES)) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	notify_state.drivers[remote_proc_id][line_id].notify_handle = handle;
+
+exit:
+	return status;
+}
+EXPORT_SYMBOL(notify_set_driver_handle);
+
+
+/* Function to find and return the driver handle maintained within
+ * the Notify module. */
+struct notify_driver_object *notify_get_driver_handle(u16 remote_proc_id,
+					u16 line_id)
+{
+	struct notify_driver_object *handle = NULL;
+	s32 status = NOTIFY_S_SUCCESS;
+
+	if (WARN_ON(atomic_cmpmask_and_lt(&(notify_state.ref_count),
+			NOTIFY_MAKE_MAGICSTAMP(0),
+			NOTIFY_MAKE_MAGICSTAMP(1)) == true)) {
+		status = NOTIFY_E_INVALIDSTATE;
+		goto exit;
+	}
+	if (WARN_ON(remote_proc_id >= multiproc_get_num_processors())) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(line_id >= NOTIFY_MAX_INTLINES)) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	handle = &(notify_state.drivers[remote_proc_id][line_id]);
+	/* Check whether the driver handle slot is occupied. */
+	if (handle->is_init == NOTIFY_DRIVERINITSTATUS_NOTDONE)
+		handle = NULL;
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_get_driver_handle failed! "
+			"status = 0x%x\n", status);
+	}
+	return handle;
+}
+EXPORT_SYMBOL(notify_get_driver_handle);
diff --git a/drivers/dsp/syslink/omap_notify/plat/omap4_notify_setup.c b/drivers/dsp/syslink/omap_notify/plat/omap4_notify_setup.c
new file mode 100644
index 000000000000..016ffb2fad9f
--- /dev/null
+++ b/drivers/dsp/syslink/omap_notify/plat/omap4_notify_setup.c
@@ -0,0 +1,165 @@
+/*
+ * omap4_notify_setup.c
+ *
+ * OMAP4 device-specific functions to setup the Notify module.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/* Linux headers */
+#include <linux/spinlock.h>
+/*#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <asm/pgtable.h>*/
+
+/* Module headers */
+#include <syslink/multiproc.h>
+
+#include <syslink/notify.h>
+#include <syslink/notify_setup_proxy.h>
+#include <syslink/notify_ducatidriver.h>
+#include <syslink/notify_driver.h>
+#include <syslink/notifydefs.h>
+
+
+/* Handle to the NotifyDriver for line 0 */
+static struct notify_ducatidrv_object *notify_setup_driver_handles[
+						MULTIPROC_MAXPROCESSORS];
+
+/* Handle to the Notify objects */
+static
+struct notify_object *notify_setup_notify_handles[MULTIPROC_MAXPROCESSORS];
+
+
+/* Function to perform device specific setup for Notify module.
+ * This function creates the Notify drivers. */
+int notify_setup_omap4_attach(u16 proc_id, void *shared_addr)
+{
+	s32 status = NOTIFY_S_SUCCESS;
+	struct notify_ducatidrv_params notify_shm_params;
+
+	if (WARN_ON(unlikely(shared_addr == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+	if (WARN_ON(unlikely(proc_id == multiproc_self()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	notify_ducatidrv_params_init(&notify_shm_params);
+
+	/* Currently not supporting caching on host side. */
+	notify_shm_params.cache_enabled = false;
+	notify_shm_params.line_id = 0;
+	notify_shm_params.local_int_id = 77u; /* TBD: Ipc_getConfig */
+	notify_shm_params.remote_int_id = 0u; /* TBD: Ipc_getConfig */
+	notify_shm_params.remote_proc_id = proc_id;
+	notify_shm_params.shared_addr = shared_addr;
+
+	notify_setup_driver_handles[proc_id] = notify_ducatidrv_create(
+							&notify_shm_params);
+	if (notify_setup_driver_handles[proc_id] == NULL) {
+		status = NOTIFY_E_FAIL;
+		printk(KERN_ERR "notify_setup_omap4_attach: "
+			"notify_ducatidrv_create failed! status = 0x%x",
+			status);
+		goto exit;
+	}
+
+	notify_setup_notify_handles[proc_id] = \
+			notify_create(notify_setup_driver_handles[proc_id],
+					proc_id, 0u, NULL);
+	if (notify_setup_notify_handles[proc_id] == NULL) {
+		status = NOTIFY_E_FAIL;
+		printk(KERN_ERR "notify_setup_omap4_attach: notify_create "
+			"failed!");
+		goto exit;
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_setup_omap4_attach failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+
+
+/* Function to perform device specific destroy for Notify module.
+ * This function deletes the Notify drivers. */
+int notify_setup_omap4_detach(u16 proc_id)
+{
+	s32 status = NOTIFY_S_SUCCESS;
+	s32 tmp_status = NOTIFY_S_SUCCESS;
+
+	if (WARN_ON(unlikely(proc_id == multiproc_self()))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	/* Delete the notify driver to the M3 (Line 0) */
+	status = notify_delete(&(notify_setup_notify_handles[proc_id]));
+	if (status < 0) {
+		printk(KERN_ERR "notify_setup_omap4_detach: notify_delete "
+			"failed for line 0!");
+	}
+
+	tmp_status = notify_ducatidrv_delete(
+				&(notify_setup_driver_handles[proc_id]));
+	if ((tmp_status < 0) && (status >= 0)) {
+		status = tmp_status;
+		printk(KERN_ERR "notify_setup_omap4_detach: "
+			"notify_ducatidrv_delete failed for line 0!");
+	}
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_setup_omap4_detach failed! "
+			"status = 0x%x", status);
+	}
+	return status;
+}
+
+
+/* Return the amount of shared memory required  */
+uint notify_setup_omap4_shared_mem_req(u16 remote_proc_id, void *shared_addr)
+{
+	int status = NOTIFY_S_SUCCESS;
+	uint mem_req = 0x0;
+	struct notify_ducatidrv_params params;
+
+	if (WARN_ON(unlikely(shared_addr == NULL))) {
+		status = NOTIFY_E_INVALIDARG;
+		goto exit;
+	}
+
+	notify_ducatidrv_params_init(&params);
+	params.shared_addr = shared_addr;
+
+	mem_req = notify_ducatidrv_shared_mem_req(&params);
+
+exit:
+	if (status < 0) {
+		printk(KERN_ERR "notify_setup_omap4_shared_mem_req failed!"
+			" status = 0x%x", status);
+	}
+	return mem_req;
+}
+
+bool notify_setup_omap4_int_line_available(u16 remote_proc_id)
+{
+	return true;
+}
diff --git a/drivers/dsp/syslink/procmgr/Kbuild b/drivers/dsp/syslink/procmgr/Kbuild
new file mode 100644
index 000000000000..58f6d3155250
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/Kbuild
@@ -0,0 +1,10 @@
+libomap_syslink_proc = processor.o procmgr.o procmgr_drv.o
+
+obj-$(CONFIG_SYSLINK_PROC)        += syslink_proc.o
+syslink_proc-objs = $(libomap_syslink_proc) 
+
+ccflags-y += -Wno-strict-prototypes
+
+#Header files
+ccflags-y += -Iarch/arm/plat-omap/include/syslink
+
diff --git a/drivers/dsp/syslink/procmgr/proc4430/Kbuild b/drivers/dsp/syslink/procmgr/proc4430/Kbuild
new file mode 100644
index 000000000000..f82f2e23f79a
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/Kbuild
@@ -0,0 +1,10 @@
+libomap_proc4430 = proc4430.o proc4430_drv.o dmm4430.o \
+		   ducatienabler.o hw_mmu.o
+
+obj-$(CONFIG_SYSLINK_PROC)        += syslink_proc4430.o
+syslink_proc4430-objs = $(libomap_proc4430)
+
+ccflags-y += -Wno-strict-prototypes -DUSE_LEVEL_1_MACROS
+
+#Header files
+ccflags-y += -Iarch/arm/plat-omap/include/syslink
diff --git a/drivers/dsp/syslink/procmgr/proc4430/dmm4430.c b/drivers/dsp/syslink/procmgr/proc4430/dmm4430.c
new file mode 100644
index 000000000000..227cba7ce43b
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/dmm4430.c
@@ -0,0 +1,356 @@
+/*
+ * dmm4430.c
+ *
+ * Syslink support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ *  ======== dmm.c ========
+ *  Purpose:
+ *The Dynamic Memory Manager (DMM) module manages the DSP Virtual address
+ *space that can be directly mapped to any MPU buffer or memory region
+ *
+ *  Public Functions:
+ *dmm_create_tables
+ *dmm_create
+ *dmm_destroy
+ *dmm_exit
+ *dmm_init
+ *dmm_map_memory
+ *DMM_Reset
+ *dmm_reserve_memory
+ *dmm_unmap_memory
+ *dmm_unreserve_memory
+ *
+ *  Private Functions:
+ *add_region
+ *create_region
+ *get_region
+ *	get_free_region
+ *	get_mapped_region
+ *
+ *  Notes:
+ *Region: Generic memory entitiy having a start address and a size
+ *Chunk:  Reserved region
+ *
+ *!
+ */
+
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/vmalloc.h>
+#include <linux/slab.h>
+#include <asm/page.h>
+#include "dmm4430.h"
+
+
+#define DMM_ADDR_VIRTUAL(x, a)						\
+	do {								\
+		x = (((struct map_page *)(a) - p_virt_mapping_tbl) * PAGE_SIZE \
+						+ dyn_mem_map_begin);\
+	} while (0)
+
+#define DMM_ADDR_TO_INDEX(i, a)						\
+	do {								\
+		i = (((a) - dyn_mem_map_begin) / PAGE_SIZE);		\
+	} while (0)
+
+struct map_page {
+	u32 region_size:31;
+	u32 b_reserved:1;
+};
+
+/*  Create the free list */
+static struct map_page *p_virt_mapping_tbl;
+static u32 i_freeregion;	/* The index of free region */
+static u32 i_freesize;
+static u32 table_size;/* The size of virtual and physical pages tables */
+static u32 dyn_mem_map_begin;
+struct mutex *dmm_lock;
+
+static struct map_page *get_free_region(u32 size);
+static struct map_page *get_mapped_region(u32 addr);
+
+/*  ======== dmm_create_tables ========
+ *  Purpose:
+ *Create table to hold information of the virtual memory that is reserved
+ *for DSP.
+ */
+int dmm_create_tables(u32 addr, u32 size)
+{
+	int status = 0;
+
+	dmm_delete_tables();
+	if (WARN_ON(mutex_lock_interruptible(dmm_lock)) < 0) {
+		status = -EFAULT;
+		goto func_exit;
+	}
+	dyn_mem_map_begin = addr;
+	table_size = (size/PAGE_SIZE) + 1;
+	/*  Create the free list */
+	p_virt_mapping_tbl = (struct map_page *)vmalloc(
+					table_size*sizeof(struct map_page));
+	if (WARN_ON(p_virt_mapping_tbl == NULL))
+		status = -ENOMEM;
+	/* On successful allocation,
+	* all entries are zero ('free') */
+	i_freeregion = 0;
+	i_freesize = table_size*PAGE_SIZE;
+	p_virt_mapping_tbl[0].region_size = table_size;
+	mutex_unlock(dmm_lock);
+
+func_exit:
+	return status;
+}
+
+/*
+ *  ======== dmm_create ========
+ *  Purpose:
+ *Create a dynamic memory manager object.
+ */
+int dmm_create(void)
+{
+	int status = 0;
+	dmm_lock = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (WARN_ON(dmm_lock == NULL)) {
+		status = -EFAULT;
+		goto func_exit;
+	}
+	mutex_init(dmm_lock);
+func_exit:
+	return status;
+}
+
+/*
+ *  ======== dmm_destroy ========
+ *  Purpose:
+ *Release the communication memory manager resources.
+ */
+void dmm_destroy(void)
+{
+	dmm_delete_tables();
+	kfree(dmm_lock);
+}
+
+
+/*
+ *  ======== dmm_delete_tables ========
+ *  Purpose:
+ *Delete DMM Tables.
+ */
+void dmm_delete_tables(void)
+{
+	/* Delete all DMM tables */
+	WARN_ON(mutex_lock_interruptible(dmm_lock));
+	if (p_virt_mapping_tbl != NULL) {
+		vfree(p_virt_mapping_tbl);
+		p_virt_mapping_tbl = NULL;
+	}
+	mutex_unlock(dmm_lock);
+}
+
+/*
+ *  ======== dmm_init ========
+ *  Purpose:
+ *Initializes private state of DMM module.
+ */
+void dmm_init(void)
+{
+	p_virt_mapping_tbl = NULL ;
+	table_size = 0;
+	return;
+}
+
+/*
+ *  ======== dmm_reserve_memory ========
+ *  Purpose:
+ *Reserve a chunk of virtually contiguous DSP/IVA address space.
+ */
+int dmm_reserve_memory(u32 size, u32 *p_rsv_addr)
+{
+	int status = 0;
+	struct map_page *node;
+	u32 rsv_addr = 0;
+	u32 rsv_size = 0;
+
+	if (WARN_ON(mutex_lock_interruptible(dmm_lock)) < 0) {
+		status = -EFAULT;
+		goto func_exit;
+	}
+
+	/* Try to get a DSP chunk from the free list */
+	node = get_free_region(size);
+	if (node != NULL) {
+		/*  DSP chunk of given size is available. */
+		DMM_ADDR_VIRTUAL(rsv_addr, node);
+		/* Calculate the number entries to use */
+		rsv_size = size/PAGE_SIZE;
+		if (rsv_size < node->region_size) {
+			/* Mark remainder of free region */
+			node[rsv_size].b_reserved = false;
+			node[rsv_size].region_size =
+				node->region_size - rsv_size;
+		}
+		/*  get_region will return first fit chunk. But we only use what
+			is requested. */
+		node->b_reserved = true;
+		node->region_size = rsv_size;
+		/* Return the chunk's starting address */
+		*p_rsv_addr = rsv_addr;
+	} else
+		/*dSP chunk of given size is not available */
+		status = -ENOMEM;
+
+	mutex_unlock(dmm_lock);
+func_exit:
+	return status;
+}
+
+
+/*
+ *  ======== dmm_unreserve_memory ========
+ *  Purpose:
+ *Free a chunk of reserved DSP/IVA address space.
+ */
+int dmm_unreserve_memory(u32 rsv_addr, u32 *psize)
+{
+	struct map_page *chunk;
+	int status = 0;
+
+	WARN_ON(mutex_lock_interruptible(dmm_lock));
+
+	/* Find the chunk containing the reserved address */
+	chunk = get_mapped_region(rsv_addr);
+	if (chunk == NULL)
+		status = -ENXIO;
+	WARN_ON(status < 0);
+	if (status == 0) {
+		chunk->b_reserved = false;
+		*psize = chunk->region_size * PAGE_SIZE;
+		/* NOTE: We do NOT coalesce free regions here.
+		 * Free regions are coalesced in get_region(), as it traverses
+		 *the whole mapping table
+		 */
+	}
+	mutex_unlock(dmm_lock);
+	return status;
+}
+
+/*
+ *  ======== get_free_region ========
+ *  Purpose:
+ *  Returns the requested free region
+ */
+static struct map_page *get_free_region(u32 size)
+{
+	struct map_page *curr_region = NULL;
+	u32 i = 0;
+	u32 region_size = 0;
+	u32 next_i = 0;
+
+	if (p_virt_mapping_tbl == NULL)
+		return curr_region;
+	if (size > i_freesize) {
+		/* Find the largest free region
+		* (coalesce during the traversal) */
+		while (i < table_size) {
+			region_size = p_virt_mapping_tbl[i].region_size;
+			next_i = i+region_size;
+			if (p_virt_mapping_tbl[i].b_reserved == false) {
+				/* Coalesce, if possible */
+				if (next_i < table_size &&
+				p_virt_mapping_tbl[next_i].b_reserved
+							== false) {
+					p_virt_mapping_tbl[i].region_size +=
+					p_virt_mapping_tbl[next_i].region_size;
+					continue;
+				}
+				region_size *= PAGE_SIZE;
+				if (region_size > i_freesize) 	{
+					i_freeregion = i;
+					i_freesize = region_size;
+				}
+			}
+			i = next_i;
+		}
+	}
+	if (size <= i_freesize) {
+		curr_region = p_virt_mapping_tbl + i_freeregion;
+		i_freeregion += (size / PAGE_SIZE);
+		i_freesize -= size;
+	}
+	return curr_region;
+}
+
+/*
+ *  ======== get_mapped_region ========
+ *  Purpose:
+ *  Returns the requestedmapped region
+ */
+static struct map_page *get_mapped_region(u32 addr)
+{
+	u32 i = 0;
+	struct map_page *curr_region = NULL;
+
+	if (p_virt_mapping_tbl == NULL)
+		return curr_region;
+
+	DMM_ADDR_TO_INDEX(i, addr);
+	if (i < table_size && (p_virt_mapping_tbl[i].b_reserved))
+		curr_region = p_virt_mapping_tbl + i;
+	return curr_region;
+}
+
+#ifdef DSP_DMM_DEBUG
+int dmm_mem_map_dump(void)
+{
+	struct map_page *curNode = NULL;
+	u32 i;
+	u32 freemem = 0;
+	u32 bigsize = 0;
+
+	WARN_ON(mutex_lock_interruptible(dmm_lock));
+
+	if (p_virt_mapping_tbl != NULL) {
+		for (i = 0; i < table_size; i +=
+				p_virt_mapping_tbl[i].region_size) {
+			curNode = p_virt_mapping_tbl + i;
+			if (curNode->b_reserved == true)	{
+				/*printk("RESERVED size = 0x%x, "
+					"Map size = 0x%x\n",
+					(curNode->region_size * PAGE_SIZE),
+					(curNode->b_mapped == false) ? 0 :
+					(curNode->mapped_size * PAGE_SIZE));
+*/
+			} else {
+/*				printk("UNRESERVED size = 0x%x\n",
+					(curNode->region_size * PAGE_SIZE));
+*/
+				freemem += (curNode->region_size * PAGE_SIZE);
+				if (curNode->region_size > bigsize)
+					bigsize = curNode->region_size;
+			}
+		}
+	}
+	printk(KERN_INFO "Total DSP VA FREE memory = %d Mbytes\n",
+			freemem/(1024*1024));
+	printk(KERN_INFO "Total DSP VA USED memory= %d Mbytes \n",
+			(((table_size * PAGE_SIZE)-freemem))/(1024*1024));
+	printk(KERN_INFO "DSP VA - Biggest FREE block = %d Mbytes \n\n",
+			(bigsize*PAGE_SIZE/(1024*1024)));
+	mutex_unlock(dmm_lock);
+
+	return 0;
+}
+#endif
diff --git a/drivers/dsp/syslink/procmgr/proc4430/dmm4430.h b/drivers/dsp/syslink/procmgr/proc4430/dmm4430.h
new file mode 100644
index 000000000000..7d879f4fe123
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/dmm4430.h
@@ -0,0 +1,50 @@
+/*
+ * dmm.h
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2005-2006 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ *  ======== dmm.h ========
+ *  Purpose:
+ *The Dynamic Memory Mapping(DMM) module manages the DSP Virtual address
+ *space that can be directly mapped to any MPU buffer or memory region
+ *
+ *  Public Functions:
+ *
+ */
+
+#ifndef DMM_4430_
+#define DMM_4430_
+
+#include <linux/types.h>
+
+int dmm_reserve_memory(u32 size, u32 *p_rsv_addr);
+
+int dmm_unreserve_memory(u32 rsv_addr, u32 *psize);
+
+void dmm_destroy(void);
+
+void dmm_delete_tables(void);
+
+int dmm_create(void);
+
+void dmm_init(void);
+
+int dmm_create_tables(u32 addr, u32 size);
+
+#ifdef DSP_DMM_DEBUG
+int dmm_mem_map_dump(void);
+#endif
+#endif/* DMM_4430_ */
diff --git a/drivers/dsp/syslink/procmgr/proc4430/ducatienabler.c b/drivers/dsp/syslink/procmgr/proc4430/ducatienabler.c
new file mode 100644
index 000000000000..bd7055b4e563
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/ducatienabler.c
@@ -0,0 +1,866 @@
+/*
+ * ducatienabler.c
+ *
+ * Syslink driver support for TI OMAP processors.
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/gfp.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <asm/page.h>
+#include <linux/kernel.h>
+#include <linux/pagemap.h>
+
+
+#include <generated/autoconf.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <linux/semaphore.h>
+#include <linux/uaccess.h>
+#include <asm/irq.h>
+#include <linux/io.h>
+#include <linux/syscalls.h>
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/stddef.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/file.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/ctype.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/vmalloc.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/pagemap.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+
+#include <linux/interrupt.h>
+#include <plat/irqs.h>
+
+#include <syslink/ducatienabler.h>
+#include <syslink/MMUAccInt.h>
+
+#include <plat/iommu.h>
+#include "../../../arch/arm/plat-omap/iopgtable.h"
+
+
+#ifdef DEBUG_DUCATI_IPC
+#define DPRINTK(fmt, args...) printk(KERN_INFO "%s: " fmt, __func__, ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+
+#define base_ducati_l2_mmuPhys			0x55082000
+
+/* Attributes of L2 page tables for DSP MMU.*/
+struct page_info {
+	/* Number of valid PTEs in the L2 PT*/
+	u32 num_entries;
+};
+
+enum pagetype {
+	SECTION = 0,
+	LARGE_PAGE = 1,
+	SMALL_PAGE = 2,
+	SUPER_SECTION  = 3
+};
+
+
+static u32 shm_phys_addr;
+static u32 shm_virt_addr;
+
+struct iommu *ducati_iommu_ptr;
+
+static void bad_page_dump(u32 pa, struct page *pg)
+{
+	pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
+	pr_emerg("Bad page state in process '%s'\n", current->comm);
+	BUG();
+}
+
+/*============================================
+ * This function calculates PTE address (MPU virtual) to be updated
+ *  It also manages the L2 page tables
+ */
+static int pte_set(u32 pa, u32 va, u32 size, struct hw_mmu_map_attrs_t *attrs)
+{
+	struct iotlb_entry tlb_entry;
+	switch (size) {
+	case HW_PAGE_SIZE_16MB:
+		tlb_entry.pgsz = MMU_CAM_PGSZ_16M;
+		break;
+	case HW_PAGE_SIZE_1MB:
+		tlb_entry.pgsz = MMU_CAM_PGSZ_1M;
+		break;
+	case HW_PAGE_SIZE_64KB:
+		tlb_entry.pgsz = MMU_CAM_PGSZ_64K;
+		break;
+	case HW_PAGE_SIZE_4KB:
+		tlb_entry.pgsz = MMU_CAM_PGSZ_4K;
+		break;
+	}
+	tlb_entry.prsvd = MMU_CAM_P;
+	tlb_entry.valid = MMU_CAM_V;
+	switch (attrs->element_size) {
+	case HW_ELEM_SIZE_8BIT:
+		tlb_entry.elsz = MMU_RAM_ELSZ_8;
+		break;
+	case HW_ELEM_SIZE_16BIT:
+		tlb_entry.elsz = MMU_RAM_ELSZ_16;
+		break;
+	case HW_ELEM_SIZE_32BIT:
+		tlb_entry.elsz = MMU_RAM_ELSZ_32;
+		break;
+	case HW_ELEM_SIZE_64BIT:
+		tlb_entry.elsz = 0x3; /* No translation */
+		break;
+	}
+	switch (attrs->endianism) {
+	case HW_LITTLE_ENDIAN:
+		tlb_entry.endian = MMU_RAM_ENDIAN_LITTLE;
+		break;
+	case HW_BIG_ENDIAN:
+		tlb_entry.endian = MMU_RAM_ENDIAN_BIG;
+		break;
+	}
+	switch (attrs->mixedSize) {
+	case HW_MMU_TLBES:
+		tlb_entry.mixed = 0;
+		break;
+	case HW_MMU_CPUES:
+		tlb_entry.mixed = MMU_RAM_MIXED;
+		break;
+	}
+	tlb_entry.da = va;
+	tlb_entry.pa = pa;
+	DPRINTK("pte set ducati_iommu_ptr = 0x%x, tlb_entry = 0x%x \n",
+					ducati_iommu_ptr, tlb_entry);
+	if (iopgtable_store_entry(ducati_iommu_ptr, &tlb_entry))
+		goto error_exit;
+	return 0;
+error_exit:
+	printk(KERN_ERR "pte set failure \n");
+	return -EFAULT;
+}
+
+
+/*=============================================
+ * This function calculates the optimum page-aligned addresses and sizes
+ * Caller must pass page-aligned values
+ */
+static int pte_update(u32 pa, u32 va, u32 size,
+			struct hw_mmu_map_attrs_t *map_attrs)
+{
+	u32 i;
+	u32 all_bits;
+	u32 pa_curr = pa;
+	u32 va_curr = va;
+	u32 num_bytes = size;
+	int status = 0;
+	u32 pg_size[] = {HW_PAGE_SIZE_16MB, HW_PAGE_SIZE_1MB,
+			   HW_PAGE_SIZE_64KB, HW_PAGE_SIZE_4KB};
+	DPRINTK("> pte_update  pa %x, va %x, "
+		 "size %x, map_attrs %x\n", pa, va, size, (u32)map_attrs);
+	while (num_bytes && (status == 0)) {
+		/* To find the max. page size with which both PA & VA are
+		 * aligned */
+		all_bits = pa_curr | va_curr;
+		DPRINTK("all_bits %x, pa_curr %x, va_curr %x, "
+			 "num_bytes %x\n ",
+			all_bits, pa_curr, va_curr, num_bytes);
+
+		for (i = 0; i < 4; i++) {
+			if ((num_bytes >= pg_size[i]) && ((all_bits &
+			   (pg_size[i] - 1)) == 0)) {
+				DPRINTK("pg_size %x\n", pg_size[i]);
+				status = pte_set(pa_curr,
+					va_curr, pg_size[i], map_attrs);
+				pa_curr += pg_size[i];
+				va_curr += pg_size[i];
+				num_bytes -= pg_size[i];
+				 /* Don't try smaller sizes. Hopefully we have
+				 * reached an address aligned to a bigger page
+				 * size */
+				break;
+			}
+		}
+	}
+	DPRINTK("< pte_update status %x num_bytes %x\n", status, num_bytes);
+	return status;
+}
+
+/*
+ *  ======== ducati_mem_unmap ========
+ *      Invalidate the PTEs for the DSP VA block to be unmapped.
+ *
+ *      PTEs of a mapped memory block are contiguous in any page table
+ *      So, instead of looking up the PTE address for every 4K block,
+ *      we clear consecutive PTEs until we unmap all the bytes
+ */
+int ducati_mem_unmap(u32 da, u32 num_bytes)
+{
+	u32 bytes;
+	struct page *pg = NULL;
+	int temp = 0;
+	u32 nent;
+	u32 phyaddress;
+	s32 numofBytes = num_bytes;
+
+	 while (num_bytes > 0) {
+		u32 *iopgd = iopgd_offset(ducati_iommu_ptr, da);
+		if (*iopgd & IOPGD_TABLE) {
+			u32 *iopte = iopte_offset(iopgd, da);
+			if (*iopte & IOPTE_LARGE) {
+				nent = 16;
+				/* rewind to the 1st entry */
+				iopte = (u32 *)((u32)iopte & IOLARGE_MASK);
+			} else
+				nent = 1;
+			phyaddress = (*iopte) & IOPAGE_MASK;
+		} else {
+			if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
+				nent = 4096;
+				/* rewind to the 1st entry */
+				iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK);
+			} else
+				nent = 256;
+			phyaddress = (*iopgd) & IOPGD_MASK;
+		}
+		for (temp = 0; temp < nent; temp++) {
+			if (pfn_valid(__phys_to_pfn(phyaddress))) {
+				pg = phys_to_page(phyaddress);
+				if (page_count(pg) < 1) {
+					pr_info("DSPBRIDGE:UNMAP function: "
+						"COUNT 0 FOR PA 0x%x,"
+						" size = 0x%x\n",
+						phyaddress, numofBytes);
+					bad_page_dump(phyaddress, pg);
+				}
+				SetPageDirty(pg);
+				page_cache_release(pg);
+			}
+			phyaddress += HW_PAGE_SIZE_4KB;
+		}
+		bytes = iopgtable_clear_entry(ducati_iommu_ptr, da);
+		num_bytes -= bytes;
+		da += bytes;
+	}
+	return 0;
+}
+
+
+/*
+ *  ======== ducati_mem_virtToPhys ========
+ *  This funciton provides the translation from
+ *  Remote virtual address to Physical address
+ */
+
+inline u32 ducati_mem_virtToPhys(u32 da)
+{
+#if 0
+	/* FIXME: temp work around till L2MMU issue
+	 * is resolved
+	 */
+	u32 *iopgd = iopgd_offset(ducati_iommu_ptr, da);
+	u32 phyaddress;
+
+	if (*iopgd & IOPGD_TABLE) {
+		u32 *iopte = iopte_offset(iopgd, da);
+		if (*iopte & IOPTE_LARGE) {
+			phyaddress = *iopte & IOLARGE_MASK;
+			phyaddress |= (da & (IOLARGE_SIZE - 1));
+		} else
+			phyaddress = (*iopte) & IOPAGE_MASK;
+	} else {
+		if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
+			phyaddress = *iopgd & IOSUPER_MASK;
+			phyaddress |= (da & (IOSUPER_SIZE - 1));
+		} else {
+			phyaddress = (*iopgd) & IOPGD_MASK;
+			phyaddress |= (da & (IOPGD_SIZE - 1));
+		}
+	}
+#endif
+	return da;
+}
+
+
+/*
+ *  ======== user_va2pa ========
+ *  Purpose:
+ *      This function walks through the Linux page tables to convert a userland
+ *      virtual address to physical address
+ */
+u32 user_va2pa(struct mm_struct *mm, u32 address)
+{
+	pgd_t *pgd;
+	pmd_t *pmd;
+	pte_t *ptep, pte;
+
+	pgd = pgd_offset(mm, address);
+	if (!(pgd_none(*pgd) || pgd_bad(*pgd))) {
+		pmd = pmd_offset(pgd, address);
+		if (!(pmd_none(*pmd) || pmd_bad(*pmd))) {
+			ptep = pte_offset_map(pmd, address);
+			if (ptep) {
+				pte = *ptep;
+				if (pte_present(pte))
+					return pte & PAGE_MASK;
+			}
+		}
+	}
+
+	return 0;
+}
+
+/*============================================
+ * This function maps MPU buffer to the DSP address space. It performs
+* linear to physical address translation if required. It translates each
+* page since linear addresses can be physically non-contiguous
+* All address & size arguments are assumed to be page aligned (in proc.c)
+ *
+ */
+int ducati_mem_map(u32 mpu_addr, u32 ul_virt_addr,
+				u32 num_bytes, u32 map_attr)
+{
+	u32 attrs;
+	int status = 0;
+	struct hw_mmu_map_attrs_t hw_attrs;
+	struct vm_area_struct *vma;
+	struct mm_struct *mm = current->mm;
+	struct task_struct *curr_task = current;
+	u32 write = 0;
+	u32 da = ul_virt_addr;
+	u32 pa = 0;
+	int pg_i = 0;
+	int pg_num = 0;
+	struct page *mappedPage, *pg;
+	int num_usr_pages = 0;
+
+	DPRINTK("> WMD_BRD_MemMap  pa %x, va %x, "
+		 "size %x, map_attr %x\n", mpu_addr, ul_virt_addr,
+		 num_bytes, map_attr);
+	if (num_bytes == 0)
+		return -EINVAL;
+	if (map_attr != 0) {
+		attrs = map_attr;
+	} else {
+		/* Assign default attributes */
+		attrs = DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE32;
+	}
+	/* Take mapping properties */
+	if (attrs & DSP_MAPBIGENDIAN)
+		hw_attrs.endianism = HW_BIG_ENDIAN;
+	else
+		hw_attrs.endianism = HW_LITTLE_ENDIAN;
+
+	hw_attrs.mixedSize = (enum hw_mmu_mixed_size_t)
+			     ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2);
+	/* Ignore element_size if mixedSize is enabled */
+	if (hw_attrs.mixedSize == 0) {
+		if (attrs & DSP_MAPELEMSIZE8) {
+			/* Size is 8 bit */
+			hw_attrs.element_size = HW_ELEM_SIZE_8BIT;
+		} else if (attrs & DSP_MAPELEMSIZE16) {
+			/* Size is 16 bit */
+			hw_attrs.element_size = HW_ELEM_SIZE_16BIT;
+		} else if (attrs & DSP_MAPELEMSIZE32) {
+			/* Size is 32 bit */
+			hw_attrs.element_size = HW_ELEM_SIZE_32BIT;
+		} else if (attrs & DSP_MAPELEMSIZE64) {
+			/* Size is 64 bit */
+			hw_attrs.element_size = HW_ELEM_SIZE_64BIT;
+		} else {
+			/* Mixedsize isn't enabled, so size can't be
+			 * zero here */
+			DPRINTK("WMD_BRD_MemMap: MMU element size is zero\n");
+			return -EINVAL;
+		}
+	} else {
+		/* If mixedSize set to 1, no conversion is
+		 * required. for element size */
+		hw_attrs.element_size = HW_ELEM_SIZE_64BIT;
+	}
+	/*
+	 * Do OS-specific user-va to pa translation.
+	 * Combine physically contiguous regions to reduce TLBs.
+	 * Pass the translated pa to PteUpdate.
+	 */
+	if ((attrs & DSP_MAPPHYSICALADDR)) {
+		status = pte_update(mpu_addr, ul_virt_addr, num_bytes,
+								&hw_attrs);
+		goto func_cont;
+	}
+	/*
+	 * Important Note: mpu_addr is mapped from user application process
+	 * to current process - it must lie completely within the current
+	 * virtual memory address space in order to be of use to us here!
+	 */
+	down_read(&mm->mmap_sem);
+	vma = find_vma(mm, mpu_addr);
+	/*
+	 * It is observed that under some circumstances, the user buffer is
+	 * spread across several VMAs. So loop through and check if the entire
+	 * user buffer is covered
+	 */
+	while ((vma) && (mpu_addr + num_bytes > vma->vm_end)) {
+		/* jump to the next VMA region */
+		vma = find_vma(mm, vma->vm_end + 1);
+	}
+	if (!vma) {
+		status = -EINVAL;
+		up_read(&mm->mmap_sem);
+		goto func_cont;
+	}
+	if (vma->vm_flags & VM_IO) {
+		num_usr_pages = num_bytes / PAGE_SIZE;
+		/* Get the physical addresses for user buffer */
+		for (pg_i = 0; pg_i < num_usr_pages; pg_i++) {
+			pa = user_va2pa(mm, mpu_addr);
+			if (!pa) {
+				status = -EFAULT;
+				pr_err("DSPBRIDGE: VM_IO mapping physical"
+						"address is invalid\n");
+				break;
+			}
+			if (pfn_valid(__phys_to_pfn(pa))) {
+				pg = phys_to_page(pa);
+				get_page(pg);
+				if (page_count(pg) < 1) {
+					pr_err("Bad page in VM_IO buffer\n");
+					bad_page_dump(pa, pg);
+				}
+			}
+			status = pte_set(pa, da, HW_PAGE_SIZE_4KB, &hw_attrs);
+			if (WARN_ON(status < 0))
+				break;
+			mpu_addr += HW_PAGE_SIZE_4KB;
+			da += HW_PAGE_SIZE_4KB;
+		}
+	} else {
+		num_usr_pages =  num_bytes / PAGE_SIZE;
+		if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
+			write = 1;
+
+		for (pg_i = 0; pg_i < num_usr_pages; pg_i++) {
+			pg_num = get_user_pages(curr_task, mm, mpu_addr, 1,
+						write, 1, &mappedPage, NULL);
+			if (pg_num > 0) {
+				if (page_count(mappedPage) < 1) {
+					pr_err("Bad page count after doing"
+							"get_user_pages on"
+							"user buffer\n");
+					bad_page_dump(page_to_phys(mappedPage),
+								mappedPage);
+				}
+				status = pte_set(page_to_phys(mappedPage), da,
+					HW_PAGE_SIZE_4KB, &hw_attrs);
+				if (WARN_ON(status < 0))
+					break;
+				da += HW_PAGE_SIZE_4KB;
+				mpu_addr += HW_PAGE_SIZE_4KB;
+			} else {
+				pr_err("DSPBRIDGE: get_user_pages FAILED,"
+						"MPU addr = 0x%x,"
+						"vma->vm_flags = 0x%lx,"
+						"get_user_pages Err"
+						"Value = %d, Buffer"
+						"size=0x%x\n", mpu_addr,
+						vma->vm_flags, pg_num,
+						num_bytes);
+				status = -EFAULT;
+				break;
+			}
+		}
+	}
+	up_read(&mm->mmap_sem);
+func_cont:
+	/* Don't propogate Linux or HW status to upper layers */
+	if (status < 0) {
+		/*
+		 * Roll out the mapped pages incase it failed in middle of
+		 * mapping
+		 */
+		if (pg_i)
+			ducati_mem_unmap(ul_virt_addr, (pg_i * PAGE_SIZE));
+	}
+	WARN_ON(status < 0);
+	DPRINTK("< WMD_BRD_MemMap status %x\n", status);
+	return status;
+
+}
+
+ /*=========================================
+ * Decides a TLB entry size
+ *
+ */
+static int get_mmu_entry_size(u32  pa, u32 size, enum pagetype *size_tlb,
+								u32 *entry_size)
+{
+	int status = 0;
+	bool  page_align_4kb  = false;
+	bool  page_align_64kb = false;
+	bool  page_align_1mb = false;
+	bool  page_align_16mb = false;
+	u32 phys_addr = pa;
+
+	/*  First check the page alignment*/
+	if ((phys_addr % PAGE_SIZE_4KB)  == 0)
+		page_align_4kb  = true;
+	if ((phys_addr % PAGE_SIZE_64KB) == 0)
+		page_align_64kb = true;
+	if ((phys_addr % PAGE_SIZE_1MB)  == 0)
+		page_align_1mb  = true;
+	if ((phys_addr % PAGE_SIZE_16MB)  == 0)
+		page_align_16mb  = true;
+
+	if ((!page_align_64kb) && (!page_align_1mb)  && (!page_align_4kb)) {
+		status = -EINVAL;
+		goto error_exit;
+	}
+		/*  Now decide the entry size */
+		if (size >= PAGE_SIZE_16MB) {
+			if (page_align_16mb) {
+				*size_tlb   = SUPER_SECTION;
+				*entry_size = PAGE_SIZE_16MB;
+			} else if (page_align_1mb) {
+				*size_tlb   = SECTION;
+				*entry_size = PAGE_SIZE_1MB;
+			} else if (page_align_64kb) {
+				*size_tlb   = LARGE_PAGE;
+				*entry_size = PAGE_SIZE_64KB;
+			} else if (page_align_4kb) {
+				*size_tlb   = SMALL_PAGE;
+				*entry_size = PAGE_SIZE_4KB;
+			} else {
+				status = -EINVAL;
+				goto error_exit;
+			}
+		} else if (size >= PAGE_SIZE_1MB && size < PAGE_SIZE_16MB) {
+			if (page_align_1mb) {
+				*size_tlb   = SECTION;
+				*entry_size = PAGE_SIZE_1MB;
+			} else if (page_align_64kb) {
+				*size_tlb   = LARGE_PAGE;
+				*entry_size = PAGE_SIZE_64KB;
+			} else if (page_align_4kb) {
+				*size_tlb   = SMALL_PAGE;
+				*entry_size = PAGE_SIZE_4KB;
+			} else {
+				status = -EINVAL;
+				goto error_exit;
+			}
+		} else if (size > PAGE_SIZE_4KB &&
+				size < PAGE_SIZE_1MB) {
+			if (page_align_64kb) {
+				*size_tlb   = LARGE_PAGE;
+				*entry_size = PAGE_SIZE_64KB;
+			} else if (page_align_4kb) {
+				*size_tlb   = SMALL_PAGE;
+				*entry_size = PAGE_SIZE_4KB;
+			} else {
+				status = -EINVAL;
+				goto error_exit;
+			}
+		} else if (size == PAGE_SIZE_4KB) {
+				if (page_align_4kb) {
+					*size_tlb   = SMALL_PAGE;
+					*entry_size = PAGE_SIZE_4KB;
+				} else {
+					status = -EINVAL;
+					goto error_exit;
+				}
+			} else {
+				status = -EINVAL;
+				goto error_exit;
+			}
+
+	DPRINTK("< GetMMUEntrySize status %x\n", status);
+	return 0;
+error_exit:
+	DPRINTK("< GetMMUEntrySize FAILED !!!!!!\n");
+	return status;
+}
+
+/*=========================================
+ * Add DSP MMU entries corresponding to given MPU-Physical address
+ * and DSP-virtual address
+ */
+static int add_dsp_mmu_entry(u32  *phys_addr, u32 *dsp_addr,
+						u32 size)
+{
+	u32 mapped_size = 0;
+	enum pagetype size_tlb = SECTION;
+	u32 entry_size = 0;
+	int status = 0;
+	struct iotlb_entry tlb_entry;
+	int retval = 0;
+
+
+	DPRINTK("Entered add_dsp_mmu_entry phys_addr = "
+		 "0x%x, dsp_addr = 0x%x,size = 0x%x\n",
+		*phys_addr, *dsp_addr, size);
+
+	while ((mapped_size < size) && (status == 0)) {
+		status = get_mmu_entry_size(*phys_addr,
+			(size - mapped_size), &size_tlb, &entry_size);
+		if (status < 0)
+			goto error_exit;
+
+		if (size_tlb == SUPER_SECTION)
+			tlb_entry.pgsz = MMU_CAM_PGSZ_16M;
+
+		else if (size_tlb == SECTION)
+			tlb_entry.pgsz = MMU_CAM_PGSZ_1M;
+
+		else if (size_tlb == LARGE_PAGE)
+			tlb_entry.pgsz = MMU_CAM_PGSZ_64K;
+
+		else if (size_tlb == SMALL_PAGE)
+			tlb_entry.pgsz = MMU_CAM_PGSZ_4K;
+
+		tlb_entry.elsz = MMU_RAM_ELSZ_16;
+		tlb_entry.endian = MMU_RAM_ENDIAN_LITTLE;
+		tlb_entry.mixed = MMU_RAM_MIXED;
+		tlb_entry.prsvd = MMU_CAM_P;
+		tlb_entry.valid = MMU_CAM_V;
+
+		tlb_entry.da = *dsp_addr;
+		tlb_entry.pa = *phys_addr;
+		DPRINTK("pte set ducati_iommu_ptr = 0x%x, tlb_entry = 0x%x \n",
+						ducati_iommu_ptr, tlb_entry);
+		retval = load_iotlb_entry(ducati_iommu_ptr, &tlb_entry);
+		if (retval < 0)
+			goto error_exit;
+		mapped_size  += entry_size;
+		*phys_addr   += entry_size;
+		*dsp_addr   += entry_size;
+	}
+
+	return 0;
+error_exit:
+	printk(KERN_ERR "pte set failure retval = 0x%x, status = 0x%x \n",
+							retval, status);
+	return retval;
+}
+
+
+/*=============================================
+ * Add DSP MMU entries corresponding to given MPU-Physical address
+ * and DSP-virtual address
+ *
+ */
+#if 0
+static int add_entry_ext(u32 *phys_addr, u32 *dsp_addr,
+					u32 size)
+{
+	u32 mapped_size = 0;
+	enum pagetype     size_tlb = SECTION;
+	u32 entry_size = 0;
+	int status = 0;
+	u32 page_size = HW_PAGE_SIZE_1MB;
+	u32 flags = 0;
+
+	flags = (DSP_MAPELEMSIZE32 | DSP_MAPLITTLEENDIAN |
+					DSP_MAPPHYSICALADDR);
+	while ((mapped_size < size) && (status == 0)) {
+
+		/*  get_mmu_entry_size fills the size_tlb and entry_size
+		based on alignment and size of memory to map
+		to DSP - size */
+		status = get_mmu_entry_size(*phys_addr,
+				(size - mapped_size),
+				&size_tlb,
+				&entry_size);
+
+		if (size_tlb == SUPER_SECTION)
+			page_size = HW_PAGE_SIZE_16MB;
+		else if (size_tlb == SECTION)
+			page_size = HW_PAGE_SIZE_1MB;
+		else if (size_tlb == LARGE_PAGE)
+			page_size = HW_PAGE_SIZE_64KB;
+		else if (size_tlb == SMALL_PAGE)
+			page_size = HW_PAGE_SIZE_4KB;
+
+		if (status == 0) {
+
+			ducati_mem_map(*phys_addr,
+			*dsp_addr, page_size, flags);
+			mapped_size  += entry_size;
+			*phys_addr   += entry_size;
+			*dsp_addr   += entry_size;
+		}
+	}
+	return status;
+}
+#endif
+
+void ducati_tlb_dump(void)
+{
+#if defined CONFIG_OMAP_IOMMU_DEBUG_MODULE
+	char *p;
+
+	p = kmalloc(1000, GFP_KERNEL);
+	dump_tlb_entries(ducati_iommu_ptr, p, 1000);
+	printk(KERN_INFO "%8s %8s %2s\n", "cam:", "ram:", "preserved");
+	printk(KERN_INFO "-----------------------------------------\n");
+	printk(KERN_INFO "%s", p);
+	kfree(p);
+#endif
+	return;
+}
+
+/*================================
+ * Initialize the Ducati MMU.
+ */
+int  ducati_mmu_init(u32 a_phy_addr)
+{
+	int ret_val = 0;
+	u32 phys_addr = 0;
+	u32 num_l4_entries;
+	u32 i = 0;
+	u32 num_l3_mem_entries = 0;
+	u32 virt_addr = 0;
+
+	num_l4_entries = (sizeof(l4_map) / sizeof(struct mmu_entry));
+	num_l3_mem_entries = sizeof(l3_memory_regions) /
+					  sizeof(struct memory_entry);
+
+	DPRINTK("\n  Programming Ducati MMU using linear address \n");
+
+	phys_addr = a_phy_addr;
+
+	printk(KERN_ALERT "  Programming Ducati memory regions\n");
+	printk(KERN_ALERT "=========================================\n");
+	for (i = 0; i < num_l3_mem_entries; i++) {
+
+		printk(KERN_ALERT "VA = [0x%x] of size [0x%x] at PA = [0x%x]\n",
+				l3_memory_regions[i].ul_virt_addr,
+				l3_memory_regions[i].ul_size, phys_addr);
+
+		/* OMAP4430 SDC code */
+		/* Adjust below logic if using cacheable shared memory */
+		if (l3_memory_regions[i].ul_virt_addr == \
+			DUCATI_MEM_IPC_HEAP0_ADDR) {
+			shm_phys_addr = phys_addr;
+		}
+		virt_addr = l3_memory_regions[i].ul_virt_addr;
+		ret_val = add_dsp_mmu_entry(&phys_addr, &virt_addr,
+					(l3_memory_regions[i].ul_size));
+
+		if (WARN_ON(ret_val < 0))
+			goto error_exit;
+	}
+
+	printk(KERN_ALERT "  Programming Ducati L4 peripherals\n");
+	printk(KERN_ALERT "=========================================\n");
+	for (i = 0; i < num_l4_entries; i++) {
+		printk(KERN_INFO "PA [0x%x] VA [0x%x] size [0x%x]\n",
+				l4_map[i].ul_phy_addr, l4_map[i].ul_virt_addr,
+				l4_map[i].ul_size);
+		virt_addr = l4_map[i].ul_virt_addr;
+		phys_addr = l4_map[i].ul_phy_addr;
+		ret_val = add_dsp_mmu_entry(&phys_addr,
+			&virt_addr, (l4_map[i].ul_size));
+		if (WARN_ON(ret_val < 0)) {
+
+			DPRINTK("**** Failed to map Peripheral ****");
+			DPRINTK("Phys addr [0x%x] Virt addr [0x%x] size [0x%x]",
+				l4_map[i].ul_phy_addr, l4_map[i].ul_virt_addr,
+				l4_map[i].ul_size);
+			DPRINTK(" Status [0x%x]", ret_val);
+			goto error_exit;
+		}
+	}
+	ducati_tlb_dump();
+	return 0;
+error_exit:
+	return ret_val;
+}
+
+
+/*========================================
+ * This sets up the Ducati processor
+ *
+ */
+int ducati_setup(void)
+{
+	int ret_val = 0;
+
+	ducati_iommu_ptr = iommu_get("ducati");
+	/* Disable TWL in iommu */
+	iommu_set_twl(ducati_iommu_ptr, false);
+	if (IS_ERR(ducati_iommu_ptr)) {
+		pr_err("Error iommu_get\n");
+		return -EFAULT;
+	}
+	ret_val = ducati_mmu_init(CONFIG_DUCATI_BASEIMAGE_PHYS_ADDR);
+	if (WARN_ON(ret_val < 0))
+		goto error_exit;
+	return 0;
+error_exit:
+	WARN_ON(1);
+	printk(KERN_ERR "DUCATI SETUP FAILED !!!!!\n");
+	return ret_val;
+}
+EXPORT_SYMBOL(ducati_setup);
+
+/*============================================
+ * De-Initialize the Ducati MMU and free the
+ * memory allocation for L1 and L2 pages
+ *
+ */
+void ducati_destroy(void)
+{
+	iommu_put(ducati_iommu_ptr);
+	return;
+}
+EXPORT_SYMBOL(ducati_destroy);
+
+/*============================================
+ * Returns the ducati virtual address for IPC shared memory
+ *
+ */
+u32 get_ducati_virt_mem(void)
+{
+	/*shm_virt_addr = (u32)ioremap(shm_phys_addr, DUCATI_SHARED_IPC_LEN);*/
+	shm_virt_addr = (u32)ioremap(shm_phys_addr, DUCATI_MEM_IPC_SHMEM_LEN);
+	return shm_virt_addr;
+}
+EXPORT_SYMBOL(get_ducati_virt_mem);
+
+/*============================================
+ * Unmaps the ducati virtual address for IPC shared memory
+ *
+ */
+void unmap_ducati_virt_mem(u32 shm_virt_addr)
+{
+	iounmap((unsigned int *) shm_virt_addr);
+	return;
+}
+EXPORT_SYMBOL(unmap_ducati_virt_mem);
+
diff --git a/drivers/dsp/syslink/procmgr/proc4430/hw_mmu.c b/drivers/dsp/syslink/procmgr/proc4430/hw_mmu.c
new file mode 100644
index 000000000000..ba0547456ab3
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/hw_mmu.c
@@ -0,0 +1,661 @@
+/*
+ * hw_mbox.c
+ *
+ * Syslink driver support for OMAP Processors.
+ *
+ *  Copyright (C) 2008-2009 Texas Instruments, Inc.
+ *
+ *  This package is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ *  IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ *  WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR
+ *  PURPOSE.
+ */
+
+#include<linux/kernel.h>
+#include<linux/module.h>
+
+#include <syslink/GlobalTypes.h>
+#include <syslink/MMURegAcM.h>
+#include <syslink/hw_defs.h>
+#include <syslink/hw_mmu.h>
+
+#define MMU_BASE_VAL_MASK        0xFC00
+#define MMU_PAGE_MAX             3
+#define MMU_ELEMENTSIZE_MAX      3
+#define MMU_ADDR_MASK            0xFFFFF000
+#define MMU_TTB_MASK             0xFFFFC000
+#define MMU_SECTION_ADDR_MASK    0xFFF00000
+#define MMU_SSECTION_ADDR_MASK   0xFF000000
+#define MMU_PAGE_TABLE_MASK      0xFFFFFC00
+#define MMU_LARGE_PAGE_MASK      0xFFFF0000
+#define MMU_SMALL_PAGE_MASK      0xFFFFF000
+
+#define MMU_LOAD_TLB        0x00000001
+#define NUM_TLB_ENTRIES 32
+
+
+
+/*
+* type: hw_mmu_pgsiz_t
+*
+* desc:  Enumerated Type used to specify the MMU Page Size(SLSS)
+*
+*
+*/
+enum hw_mmu_pgsiz_t {
+	HW_MMU_SECTION,
+	HW_MMU_LARGE_PAGE,
+	HW_MMU_SMALL_PAGE,
+	HW_MMU_SUPERSECTION
+
+};
+
+/*
+* function : mmu_flsh_entry
+*/
+
+static hw_status mmu_flsh_entry(const u32   base_address);
+
+ /*
+* function : mme_set_cam_entry
+*
+*/
+
+static hw_status mme_set_cam_entry(const u32    base_address,
+	const u32    page_size,
+	const u32    preserve_bit,
+	const u32    valid_bit,
+	const u32    virt_addr_tag);
+
+/*
+* function  : mmu_set_ram_entry
+*/
+static hw_status mmu_set_ram_entry(const u32        base_address,
+	const u32        physical_addr,
+	enum hw_endianism_t      endianism,
+	enum hw_elemnt_siz_t    element_size,
+	enum hw_mmu_mixed_size_t   mixedSize);
+
+/*
+* hw functions
+*
+*/
+
+hw_status hw_mmu_enable(const u32 base_address)
+{
+	hw_status status = RET_OK;
+
+	MMUMMU_CNTLMMUEnableWrite32(base_address, HW_SET);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_enable);
+
+hw_status hw_mmu_disable(const u32 base_address)
+{
+	hw_status status = RET_OK;
+
+	MMUMMU_CNTLMMUEnableWrite32(base_address, HW_CLEAR);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_disable);
+
+hw_status hw_mmu_autoidle_en(const u32 base_address)
+{
+	hw_status status;
+
+	status = mmu_sisconf_auto_idle_set32(base_address, HW_SET);
+	status = RET_OK;
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_autoidle_en);
+
+hw_status hw_mmu_nulck_set(const u32 base_address, u32 *num_lcked_entries)
+{
+	hw_status status = RET_OK;
+
+	*num_lcked_entries = MMUMMU_LOCKBaseValueRead32(base_address);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_nulck_set);
+
+
+hw_status hw_mmu_numlocked_set(const u32 base_address, u32 num_lcked_entries)
+{
+	hw_status status = RET_OK;
+
+	MMUMMU_LOCKBaseValueWrite32(base_address, num_lcked_entries);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_numlocked_set);
+
+
+hw_status hw_mmu_vctm_numget(const u32 base_address, u32 *vctm_entry_num)
+{
+	hw_status status = RET_OK;
+
+	*vctm_entry_num = MMUMMU_LOCKCurrentVictimRead32(base_address);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_vctm_numget);
+
+
+hw_status hw_mmu_victim_numset(const u32 base_address, u32 vctm_entry_num)
+{
+	hw_status status = RET_OK;
+
+	mmu_lck_crnt_vctmwite32(base_address, vctm_entry_num);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_victim_numset);
+
+hw_status hw_mmu_tlb_flushAll(const u32 base_address)
+{
+	hw_status status = RET_OK;
+
+	MMUMMU_GFLUSHGlobalFlushWrite32(base_address, HW_SET);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_tlb_flushAll);
+
+hw_status hw_mmu_eventack(const u32 base_address, u32 irq_mask)
+{
+	hw_status status = RET_OK;
+
+	MMUMMU_IRQSTATUSWriteRegister32(base_address, irq_mask);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_eventack);
+
+hw_status hw_mmu_event_disable(const u32 base_address, u32 irq_mask)
+{
+	hw_status status = RET_OK;
+	u32 irqReg;
+	irqReg = MMUMMU_IRQENABLEReadRegister32(base_address);
+
+	MMUMMU_IRQENABLEWriteRegister32(base_address, irqReg & ~irq_mask);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_event_disable);
+
+hw_status hw_mmu_event_enable(const u32 base_address, u32 irq_mask)
+{
+	hw_status status = RET_OK;
+	u32 irqReg;
+
+	irqReg = MMUMMU_IRQENABLEReadRegister32(base_address);
+
+	MMUMMU_IRQENABLEWriteRegister32(base_address, irqReg | irq_mask);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_event_enable);
+
+hw_status hw_mmu_event_status(const u32 base_address, u32 *irq_mask)
+{
+	hw_status status = RET_OK;
+
+	*irq_mask = MMUMMU_IRQSTATUSReadRegister32(base_address);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_event_status);
+
+hw_status hw_mmu_flt_adr_rd(const u32 base_address, u32 *addr)
+{
+	hw_status status = RET_OK;
+
+	/*Check the input Parameters*/
+	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
+					RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+	/* read values from register */
+	*addr = MMUMMU_FAULT_ADReadRegister32(base_address);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_flt_adr_rd);
+
+
+hw_status hw_mmu_ttbset(const u32 base_address, u32 ttb_phys_addr)
+{
+	hw_status status = RET_OK;
+	u32 loadTTB;
+
+	/*Check the input Parameters*/
+	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
+					RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+
+	loadTTB = ttb_phys_addr & ~0x7FUL;
+	/* write values to register */
+	MMUMMU_TTBWriteRegister32(base_address, loadTTB);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_ttbset);
+
+hw_status hw_mmu_twl_enable(const u32 base_address)
+{
+	hw_status status = RET_OK;
+
+	MMUMMU_CNTLTWLEnableWrite32(base_address, HW_SET);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_twl_enable);
+
+hw_status hw_mmu_twl_disable(const u32 base_address)
+{
+	hw_status status = RET_OK;
+
+	MMUMMU_CNTLTWLEnableWrite32(base_address, HW_CLEAR);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_twl_disable);
+
+
+hw_status hw_mmu_tlb_flush(const u32 base_address,
+	u32 virtual_addr,
+	u32 page_size)
+{
+	hw_status status = RET_OK;
+	u32 virt_addr_tag;
+	enum hw_mmu_pgsiz_t pg_sizeBits;
+
+	switch (page_size) {
+	case HW_PAGE_SIZE_4KB:
+	pg_sizeBits = HW_MMU_SMALL_PAGE;
+	break;
+
+	case HW_PAGE_SIZE_64KB:
+	pg_sizeBits = HW_MMU_LARGE_PAGE;
+	break;
+
+	case HW_PAGE_SIZE_1MB:
+	pg_sizeBits = HW_MMU_SECTION;
+	break;
+
+	case HW_PAGE_SIZE_16MB:
+	pg_sizeBits = HW_MMU_SUPERSECTION;
+	break;
+
+	default:
+	return RET_FAIL;
+	}
+
+	/* Generate the 20-bit tag from virtual address */
+	virt_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
+
+	mme_set_cam_entry(base_address, pg_sizeBits, 0, 0, virt_addr_tag);
+
+	mmu_flsh_entry(base_address);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_tlb_flush);
+
+
+hw_status hw_mmu_tlb_add(const u32        base_address,
+	u32              physical_addr,
+	u32              virtual_addr,
+	u32              page_size,
+	u32              entryNum,
+	struct hw_mmu_map_attrs_t    *map_attrs,
+	enum hw_set_clear_t       preserve_bit,
+	enum hw_set_clear_t       valid_bit)
+{
+	hw_status  status = RET_OK;
+	u32 lockReg;
+	u32 virt_addr_tag;
+	enum hw_mmu_pgsiz_t mmu_pg_size;
+
+	/*Check the input Parameters*/
+	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
+				RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+	CHECK_INPUT_RANGE_MIN0(page_size, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE,
+				RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+	CHECK_INPUT_RANGE_MIN0(map_attrs->element_size,
+			MMU_ELEMENTSIZE_MAX, RET_PARAM_OUT_OF_RANGE,
+				RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+
+		switch (page_size) {
+		case HW_PAGE_SIZE_4KB:
+		mmu_pg_size = HW_MMU_SMALL_PAGE;
+		break;
+
+		case HW_PAGE_SIZE_64KB:
+		mmu_pg_size = HW_MMU_LARGE_PAGE;
+		break;
+
+		case HW_PAGE_SIZE_1MB:
+		mmu_pg_size = HW_MMU_SECTION;
+		break;
+
+		case HW_PAGE_SIZE_16MB:
+		mmu_pg_size = HW_MMU_SUPERSECTION;
+		break;
+
+		default:
+		return RET_FAIL;
+		}
+
+	lockReg = mmu_lckread_reg_32(base_address);
+
+	/* Generate the 20-bit tag from virtual address */
+	virt_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
+
+	/* Write the fields in the CAM Entry Register */
+	mme_set_cam_entry(base_address,  mmu_pg_size, preserve_bit, valid_bit,
+	virt_addr_tag);
+
+	/* Write the different fields of the RAM Entry Register */
+	/* endianism of the page,Element Size of the page (8, 16, 32, 64 bit) */
+	mmu_set_ram_entry(base_address, physical_addr,
+	map_attrs->endianism, map_attrs->element_size, map_attrs->mixedSize);
+
+	/* Update the MMU Lock Register */
+	/* currentVictim between lockedBaseValue and (MMU_Entries_Number - 1) */
+	mmu_lck_crnt_vctmwite32(base_address, entryNum);
+
+	/* Enable loading of an entry in TLB by writing 1 into LD_TLB_REG
+	register */
+	mmu_ld_tlbwrt_reg32(base_address, MMU_LOAD_TLB);
+
+
+	mmu_lck_write_reg32(base_address, lockReg);
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_tlb_add);
+
+
+
+hw_status hw_mmu_pte_set(const u32        pg_tbl_va,
+	u32              physical_addr,
+	u32              virtual_addr,
+	u32              page_size,
+	struct hw_mmu_map_attrs_t    *map_attrs)
+{
+	hw_status status = RET_OK;
+	u32 pte_addr, pte_val;
+	long int num_entries = 1;
+
+	switch (page_size) {
+
+	case HW_PAGE_SIZE_4KB:
+	pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, virtual_addr &
+		MMU_SMALL_PAGE_MASK);
+	pte_val = ((physical_addr & MMU_SMALL_PAGE_MASK) |
+	(map_attrs->endianism << 9) |
+	(map_attrs->element_size << 4) |
+	(map_attrs->mixedSize << 11) | 2
+	);
+	break;
+
+	case HW_PAGE_SIZE_64KB:
+	num_entries = 16;
+	pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va, virtual_addr &
+		MMU_LARGE_PAGE_MASK);
+	pte_val = ((physical_addr & MMU_LARGE_PAGE_MASK) |
+	(map_attrs->endianism << 9) |
+	(map_attrs->element_size << 4) |
+	(map_attrs->mixedSize << 11) | 1
+	);
+	break;
+
+	case HW_PAGE_SIZE_1MB:
+	pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, virtual_addr &
+		MMU_SECTION_ADDR_MASK);
+	pte_val = ((((physical_addr & MMU_SECTION_ADDR_MASK) |
+	(map_attrs->endianism << 15) |
+	(map_attrs->element_size << 10) |
+	(map_attrs->mixedSize << 17)) &
+	~0x40000) | 0x2
+	);
+	break;
+
+	case HW_PAGE_SIZE_16MB:
+	num_entries = 16;
+	pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, virtual_addr &
+		MMU_SSECTION_ADDR_MASK);
+	pte_val = (((physical_addr & MMU_SSECTION_ADDR_MASK) |
+	(map_attrs->endianism << 15) |
+	(map_attrs->element_size << 10) |
+	(map_attrs->mixedSize << 17)
+	) | 0x40000 | 0x2
+	);
+	break;
+
+	case HW_MMU_COARSE_PAGE_SIZE:
+	pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va, virtual_addr &
+		MMU_SECTION_ADDR_MASK);
+	pte_val = (physical_addr & MMU_PAGE_TABLE_MASK) | 1;
+	break;
+
+	default:
+	return RET_FAIL;
+	}
+
+	while (--num_entries >= 0)
+		((u32 *)pte_addr)[num_entries] = pte_val;
+
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_pte_set);
+
+hw_status hw_mmu_pte_clear(const u32  pg_tbl_va,
+	u32        virtual_addr,
+	u32        pg_size)
+{
+	hw_status status = RET_OK;
+	u32 pte_addr;
+	long int num_entries = 1;
+
+	switch (pg_size) {
+	case HW_PAGE_SIZE_4KB:
+	pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
+			virtual_addr & MMU_SMALL_PAGE_MASK);
+	break;
+
+	case HW_PAGE_SIZE_64KB:
+	num_entries = 16;
+	pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
+			virtual_addr & MMU_LARGE_PAGE_MASK);
+	break;
+
+	case HW_PAGE_SIZE_1MB:
+	case HW_MMU_COARSE_PAGE_SIZE:
+	pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
+			virtual_addr & MMU_SECTION_ADDR_MASK);
+	break;
+
+	case HW_PAGE_SIZE_16MB:
+	num_entries = 16;
+	pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
+			virtual_addr & MMU_SSECTION_ADDR_MASK);
+	break;
+
+	default:
+	return RET_FAIL;
+	}
+
+	while (--num_entries >= 0)
+		((u32 *)pte_addr)[num_entries] = 0;
+
+	return status;
+}
+EXPORT_SYMBOL(hw_mmu_pte_clear);
+
+/*
+* function: mmu_flsh_entry
+*/
+static hw_status mmu_flsh_entry(const u32 base_address)
+{
+	hw_status status = RET_OK;
+	u32 flushEntryData = 0x1;
+
+	/*Check the input Parameters*/
+	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
+				RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+
+	/* write values to register */
+	MMUMMU_FLUSH_ENTRYWriteRegister32(base_address, flushEntryData);
+
+	return status;
+}
+EXPORT_SYMBOL(mmu_flsh_entry);
+/*
+* function : mme_set_cam_entry
+*/
+static hw_status mme_set_cam_entry(const u32    base_address,
+	const u32    page_size,
+	const u32    preserve_bit,
+	const u32    valid_bit,
+	const u32    virt_addr_tag)
+{
+	hw_status status = RET_OK;
+	u32 mmuCamReg;
+
+	/*Check the input Parameters*/
+	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
+				RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+
+	mmuCamReg = (virt_addr_tag << 12);
+	mmuCamReg = (mmuCamReg) | (page_size) |  (valid_bit << 2)
+						| (preserve_bit << 3);
+
+	/* write values to register */
+	MMUMMU_CAMWriteRegister32(base_address, mmuCamReg);
+
+	return status;
+}
+EXPORT_SYMBOL(mme_set_cam_entry);
+/*
+* function: mmu_set_ram_entry
+*/
+static hw_status mmu_set_ram_entry(const u32       base_address,
+	const u32       physical_addr,
+	enum hw_endianism_t     endianism,
+	enum hw_elemnt_siz_t   element_size,
+	enum hw_mmu_mixed_size_t  mixedSize)
+{
+	hw_status status = RET_OK;
+	u32 mmuRamReg;
+
+	/*Check the input Parameters*/
+	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
+					RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+	CHECK_INPUT_RANGE_MIN0(element_size, MMU_ELEMENTSIZE_MAX,
+					RET_PARAM_OUT_OF_RANGE,
+					RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
+
+
+	mmuRamReg = (physical_addr & MMU_ADDR_MASK);
+	mmuRamReg = (mmuRamReg) | ((endianism << 9) |  (element_size << 7)
+					| (mixedSize << 6));
+
+	/* write values to register */
+	MMUMMU_RAMWriteRegister32(base_address, mmuRamReg);
+
+	return status;
+
+}
+EXPORT_SYMBOL(mmu_set_ram_entry);
+
+u32 hw_mmu_fault_dump(const u32 base_address)
+{
+	u32 reg;
+
+	reg = MMUMMU_FAULT_ADReadRegister32(base_address);
+	printk(KERN_INFO "Fault Address Address = 0x%x\n", reg);
+	reg = MMUMMU_FAULT_PCReadRegister32(base_address);
+	printk(KERN_INFO "Fault PC Register Address = 0x%x\n", reg);
+	reg = MMUMMU_FAULT_STATUSReadRegister32(base_address);
+	printk(KERN_INFO "Fault PC address doesn't show right value in DUCATI"
+				"because of HW limitation\n");
+	printk(KERN_INFO "Fault Status Register  = 0x%x\n", reg);
+	reg = MMUMMU_FAULT_EMUAddressReadRegister32(base_address);
+	printk(KERN_INFO "Fault EMU  Address = 0x%x\n", reg);
+	return 0;
+}
+EXPORT_SYMBOL(hw_mmu_fault_dump);
+
+long hw_mmu_tlb_dump(const u32 base_address, bool shw_inv_entries)
+{
+	u32 i;
+	u32 lockSave;
+	u32 cam;
+	u32 ram;
+
+
+	/*  Save off the lock register contents,
+	we'll restore it when we are done  */
+
+	lockSave = mmu_lckread_reg_32(base_address);
+
+	printk(KERN_INFO "TLB locked entries = %u, current victim = %u\n",
+		((lockSave & MMU_MMU_LOCK_BaseValue_MASK)
+		>> MMU_MMU_LOCK_BaseValue_OFFSET),
+		((lockSave & MMU_MMU_LOCK_CurrentVictim_MASK)
+		>> MMU_MMU_LOCK_CurrentVictim_OFFSET));
+	printk(KERN_INFO "=============================================\n");
+	for (i = 0; i < NUM_TLB_ENTRIES; i++) {
+		mmu_lck_crnt_vctmwite32(base_address, i);
+		cam = MMUMMU_CAMReadRegister32(base_address);
+		ram = MMUMMU_RAMReadRegister32(base_address);
+
+		if ((cam & 0x4) != 0) {
+			printk(KERN_INFO "TLB Entry [0x%2x]: VA = 0x%8x "
+				"PA = 0x%8x Protected = 0x%1x\n",
+				i, (cam & MMU_ADDR_MASK), (ram & MMU_ADDR_MASK),
+				(cam & 0x8) ? 1 : 0);
+
+		} else if (shw_inv_entries != false)
+			printk(KERN_ALERT "TLB Entry [0x%x]: <INVALID>\n", i);
+	}
+	mmu_lck_write_reg32(base_address, lockSave);
+	return RET_OK;
+}
+EXPORT_SYMBOL(hw_mmu_tlb_dump);
+
+u32 hw_mmu_pte_phyaddr(u32 pte_val, u32 pte_size)
+{
+	u32	ret_val = 0;
+
+	switch (pte_size) {
+
+	case HW_PAGE_SIZE_4KB:
+		ret_val = pte_val & MMU_SMALL_PAGE_MASK;
+		break;
+	case HW_PAGE_SIZE_64KB:
+		ret_val = pte_val & MMU_LARGE_PAGE_MASK;
+		break;
+
+	case HW_PAGE_SIZE_1MB:
+		ret_val = pte_val & MMU_SECTION_ADDR_MASK;
+		break;
+	case HW_PAGE_SIZE_16MB:
+		ret_val = pte_val & MMU_SSECTION_ADDR_MASK;
+		break;
+	default:
+		/*  Invalid  */
+		break;
+
+	}
+
+	return ret_val;
+}
+EXPORT_SYMBOL(hw_mmu_pte_phyaddr);
diff --git a/drivers/dsp/syslink/procmgr/proc4430/proc4430.c b/drivers/dsp/syslink/procmgr/proc4430/proc4430.c
new file mode 100644
index 000000000000..cf798a95c6c7
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/proc4430.c
@@ -0,0 +1,1085 @@
+/*
+ * proc4430.c
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/vmalloc.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+/* Module level headers */
+#include "../procdefs.h"
+#include "../processor.h"
+#include <procmgr.h>
+#include "../procmgr_drvdefs.h"
+#include "proc4430.h"
+#include "../../ipu_pm/ipu_pm.h"
+#include "dmm4430.h"
+#include <syslink/multiproc.h>
+#include <syslink/ducatienabler.h>
+#include <syslink/platform_mem.h>
+#include <syslink/atomic_linux.h>
+
+#define DUCATI_DMM_START_ADDR			0xa0000000
+#define DUCATI_DMM_POOL_SIZE			0x6000000
+
+#define SYS_M3					2
+#define APP_M3					1
+#define CORE_PRM_BASE				OMAP2_L4_IO_ADDRESS(0x4a306700)
+#define CORE_CM2_DUCATI_CLKSTCTRL               OMAP2_L4_IO_ADDRESS(0x4A008900)
+#define CORE_CM2_DUCATI_CLKCTRL			OMAP2_L4_IO_ADDRESS(0x4A008920)
+#define RM_MPU_M3_RSTCTRL_OFFSET		0x210
+#define RM_MPU_M3_RSTST_OFFSET			0x214
+#define RM_MPU_M3_RST1				0x1
+#define RM_MPU_M3_RST2				0x2
+#define RM_MPU_M3_RST3				0x4
+
+#define OMAP4430PROC_MODULEID          (u16) 0xbbec
+
+/* Macro to make a correct module magic number with refCount */
+#define OMAP4430PROC_MAKE_MAGICSTAMP(x) ((OMAP4430PROC_MODULEID << 12u) | (x))
+
+/*OMAP4430 Module state object */
+struct proc4430_module_object {
+	u32 config_size;
+	/* Size of configuration structure */
+	struct proc4430_config cfg;
+	/* OMAP4430 configuration structure */
+	struct proc4430_config def_cfg;
+	/* Default module configuration */
+	struct proc4430_params def_inst_params;
+	/* Default parameters for the OMAP4430 instances */
+	void *proc_handles[MULTIPROC_MAXPROCESSORS];
+	/* Processor handle array. */
+	struct mutex *gate_handle;
+	/* void * of gate to be used for local thread safety */
+	atomic_t ref_count;
+};
+
+/*
+  OMAP4430 instance object.
+ */
+struct proc4430_object {
+	struct proc4430_params params;
+	/* Instance parameters (configuration values) */
+	atomic_t attach_count;
+	/* attach reference count */
+};
+
+
+/* =================================
+ *  Globals
+ * =================================
+ */
+/*
+  OMAP4430 state object variable
+ */
+
+static struct proc4430_module_object proc4430_state = {
+	.config_size = sizeof(struct proc4430_config),
+	.gate_handle = NULL,
+	.def_inst_params.num_mem_entries = 0u,
+	.def_inst_params.mem_entries = NULL,
+	.def_inst_params.reset_vector_mem_entry = 0
+};
+
+
+/* =================================
+ * APIs directly called by applications
+ * =================================
+ */
+/*
+ * Function to get the default configuration for the OMAP4430
+ * module.
+ *
+ * This function can be called by the application to get their
+ * configuration parameter to proc4430_setup filled in by the
+ * OMAP4430 module with the default parameters. If the user
+ * does not wish to make any change in the default parameters, this
+ * API is not required to be called.
+ */
+void proc4430_get_config(struct proc4430_config *cfg)
+{
+	BUG_ON(cfg == NULL);
+	memcpy(cfg, &(proc4430_state.def_cfg),
+			sizeof(struct proc4430_config));
+}
+EXPORT_SYMBOL(proc4430_get_config);
+
+/*
+ * Function to setup the OMAP4430 module.
+ *
+ * This function sets up the OMAP4430 module. This function
+ * must be called before any other instance-level APIs can be
+ * invoked.
+ * Module-level configuration needs to be provided to this
+ * function. If the user wishes to change some specific config
+ * parameters, then proc4430_get_config can be called to get the
+ * configuration filled with the default values. After this, only
+ * the required configuration values can be changed. If the user
+ * does not wish to make any change in the default parameters, the
+ * application can simply call proc4430_setup with NULL
+ * parameters. The default parameters would get automatically used.
+ */
+int proc4430_setup(struct proc4430_config *cfg)
+{
+	int retval = 0;
+	struct proc4430_config tmp_cfg;
+	atomic_cmpmask_and_set(&proc4430_state.ref_count,
+			OMAP4430PROC_MAKE_MAGICSTAMP(0),
+				 OMAP4430PROC_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&proc4430_state.ref_count) !=
+				OMAP4430PROC_MAKE_MAGICSTAMP(1)) {
+		return 1;
+	}
+
+	if (cfg == NULL) {
+		proc4430_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+
+	dmm_create();
+	dmm_create_tables(DUCATI_DMM_START_ADDR, DUCATI_DMM_POOL_SIZE);
+
+	/* Create a default gate handle for local module protection. */
+	proc4430_state.gate_handle =
+		kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (proc4430_state.gate_handle == NULL) {
+		retval = -ENOMEM;
+		goto error;
+	}
+
+	mutex_init(proc4430_state.gate_handle);
+
+	/* Initialize the name to handles mapping array. */
+	memset(&proc4430_state.proc_handles, 0,
+		(sizeof(void *) * MULTIPROC_MAXPROCESSORS));
+
+	/* Copy the user provided values into the state object. */
+	memcpy(&proc4430_state.cfg, cfg,
+				sizeof(struct proc4430_config));
+
+	return 0;
+
+error:
+	atomic_dec_return(&proc4430_state.ref_count);
+	dmm_delete_tables();
+	dmm_destroy();
+
+	return retval;
+}
+EXPORT_SYMBOL(proc4430_setup);
+
+/*
+ * Function to destroy the OMAP4430 module.
+ *
+ * Once this function is called, other OMAP4430 module APIs,
+ * except for the proc4430_get_config API cannot be called
+ * anymore.
+ */
+int proc4430_destroy(void)
+{
+	int retval = 0;
+	u16 i;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		retval = -ENODEV;
+		goto exit;
+	}
+	if (!(atomic_dec_return(&proc4430_state.ref_count)
+			== OMAP4430PROC_MAKE_MAGICSTAMP(0))) {
+
+		retval = 1;
+		goto exit;
+	}
+
+	/* Check if any OMAP4430 instances have not been
+	 * deleted so far. If not,delete them.
+	 */
+
+	for (i = 0; i < MULTIPROC_MAXPROCESSORS; i++) {
+		if (proc4430_state.proc_handles[i] == NULL)
+			continue;
+		proc4430_delete(&(proc4430_state.proc_handles[i]));
+	}
+
+	/* Check if the gate_handle was created internally. */
+	if (proc4430_state.gate_handle != NULL) {
+		mutex_destroy(proc4430_state.gate_handle);
+		kfree(proc4430_state.gate_handle);
+	}
+
+exit:
+	return retval;
+}
+EXPORT_SYMBOL(proc4430_destroy);
+
+/*=================================================
+ * Function to initialize the parameters for this Processor
+ * instance.
+ */
+void proc4430_params_init(void *handle, struct proc4430_params *params)
+{
+	struct proc4430_object *proc_object = (struct proc4430_object *)handle;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_params_init failed "
+			"Module not initialized");
+		return;
+	}
+
+	if (WARN_ON(params == NULL)) {
+		printk(KERN_ERR "proc4430_params_init failed "
+			"Argument of type proc4430_params * "
+			"is NULL");
+		return;
+	}
+
+	if (handle == NULL)
+		memcpy(params, &(proc4430_state.def_inst_params),
+				sizeof(struct proc4430_params));
+	else
+		memcpy(params, &(proc_object->params),
+				sizeof(struct proc4430_params));
+}
+EXPORT_SYMBOL(proc4430_params_init);
+
+/*===================================================
+ *Function to create an instance of this Processor.
+ *
+ */
+void *proc4430_create(u16 proc_id, const struct proc4430_params *params)
+{
+	struct processor_object *handle = NULL;
+	struct proc4430_object *object = NULL;
+
+	BUG_ON(!IS_VALID_PROCID(proc_id));
+	BUG_ON(params == NULL);
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_create failed "
+			"Module not initialized");
+		goto error;
+	}
+
+	/* Enter critical section protection. */
+	WARN_ON(mutex_lock_interruptible(proc4430_state.gate_handle));
+	if (proc4430_state.proc_handles[proc_id] != NULL) {
+		handle = proc4430_state.proc_handles[proc_id];
+		goto func_end;
+	} else {
+		handle = (struct processor_object *)
+			vmalloc(sizeof(struct processor_object));
+		if (WARN_ON(handle == NULL))
+			goto func_end;
+
+		handle->proc_fxn_table.attach = &proc4430_attach;
+		handle->proc_fxn_table.detach = &proc4430_detach;
+		handle->proc_fxn_table.start = &proc4430_start;
+		handle->proc_fxn_table.stop = &proc4430_stop;
+		handle->proc_fxn_table.read = &proc4430_read;
+		handle->proc_fxn_table.write = &proc4430_write;
+		handle->proc_fxn_table.control = &proc4430_control;
+		handle->proc_fxn_table.translateAddr =
+					 &proc4430_translate_addr;
+		handle->proc_fxn_table.map = &proc4430_map;
+		handle->proc_fxn_table.unmap = &proc4430_unmap;
+		handle->proc_fxn_table.procinfo = &proc4430_proc_info;
+		handle->proc_fxn_table.virt_to_phys = &proc4430_virt_to_phys;
+		handle->state = PROC_MGR_STATE_UNKNOWN;
+		handle->object = vmalloc(sizeof(struct proc4430_object));
+		handle->proc_id = proc_id;
+		object = (struct proc4430_object *)handle->object;
+		if (params != NULL) {
+			/* Copy params into instance object. */
+			memcpy(&(object->params), (void *)params,
+					sizeof(struct proc4430_params));
+		}
+		if ((params != NULL) && (params->mem_entries != NULL)
+					&& (params->num_mem_entries > 0)) {
+			/* Allocate memory for, and copy mem_entries table*/
+			object->params.mem_entries = vmalloc(sizeof(struct
+						proc4430_mem_entry) *
+						params->num_mem_entries);
+			memcpy(object->params.mem_entries,
+				params->mem_entries,
+				(sizeof(struct proc4430_mem_entry) *
+				 params->num_mem_entries));
+		}
+		handle->boot_mode = PROC_MGR_BOOTMODE_NOLOAD;
+		/* Set the handle in the state object. */
+		proc4430_state.proc_handles[proc_id] = handle;
+	}
+
+func_end:
+	mutex_unlock(proc4430_state.gate_handle);
+error:
+	return (void *)handle;
+}
+EXPORT_SYMBOL(proc4430_create);
+
+/*=================================================
+ * Function to delete an instance of this Processor.
+ *
+ * The user provided pointer to the handle is reset after
+ * successful completion of this function.
+ *
+ */
+int proc4430_delete(void **handle_ptr)
+{
+	int retval = 0;
+	struct proc4430_object *object = NULL;
+	struct processor_object *handle;
+
+	BUG_ON(handle_ptr == NULL);
+	BUG_ON(*handle_ptr == NULL);
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_delete failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+
+	handle = (struct processor_object *)(*handle_ptr);
+	BUG_ON(!IS_VALID_PROCID(handle->proc_id));
+	/* Enter critical section protection. */
+	WARN_ON(mutex_lock_interruptible(proc4430_state.gate_handle));
+	/* Reset handle in PwrMgr handle array. */
+	proc4430_state.proc_handles[handle->proc_id] = NULL;
+	/* Free memory used for the OMAP4430 object. */
+	if (handle->object != NULL) {
+		object = (struct proc4430_object *)handle->object;
+		if (object->params.mem_entries != NULL) {
+			vfree(object->params.mem_entries);
+			object->params.mem_entries = NULL;
+		}
+		vfree(handle->object);
+		handle->object = NULL;
+	}
+	/* Free memory used for the Processor object. */
+	vfree(handle);
+	*handle_ptr = NULL;
+	/* Leave critical section protection. */
+	mutex_unlock(proc4430_state.gate_handle);
+	return retval;
+}
+EXPORT_SYMBOL(proc4430_delete);
+
+/*===================================================
+ * Function to open a handle to an instance of this Processor. This
+ * function is called when access to the Processor is required from
+ * a different process.
+ */
+int proc4430_open(void **handle_ptr, u16 proc_id)
+{
+	int retval = 0;
+
+	BUG_ON(handle_ptr == NULL);
+	BUG_ON(!IS_VALID_PROCID(proc_id));
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_open failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+
+	/* Initialize return parameter handle. */
+	*handle_ptr = NULL;
+
+	/* Check if the PwrMgr exists and return the handle if found. */
+	if (proc4430_state.proc_handles[proc_id] == NULL) {
+		retval = -ENODEV;
+		goto func_exit;
+	} else
+		*handle_ptr = proc4430_state.proc_handles[proc_id];
+func_exit:
+	return retval;
+}
+EXPORT_SYMBOL(proc4430_open);
+
+/*===============================================
+ * Function to close a handle to an instance of this Processor.
+ *
+ */
+int proc4430_close(void *handle)
+{
+	int retval = 0;
+
+	BUG_ON(handle == NULL);
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_close failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+
+	/* nothing to be done for now */
+	return retval;
+}
+EXPORT_SYMBOL(proc4430_close);
+
+/* =================================
+ * APIs called by Processor module (part of function table interface)
+ * =================================
+ */
+/*================================
+ * Function to initialize the slave processor
+ *
+ */
+int proc4430_attach(void *handle, struct processor_attach_params *params)
+{
+	int retval = 0;
+
+	struct processor_object *proc_handle = NULL;
+	struct proc4430_object *object = NULL;
+	u32 map_count = 0;
+	u32 i;
+	memory_map_info map_info;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_attach failed"
+			"Module not initialized");
+		return -ENODEV;
+	}
+
+	if (WARN_ON(handle == NULL)) {
+		printk(KERN_ERR "proc4430_attach failed"
+			"Driver handle is NULL");
+		return -EINVAL;
+	}
+
+	if (WARN_ON(params == NULL)) {
+		printk(KERN_ERR "proc4430_attach failed"
+			"Argument processor_attach_params * is NULL");
+		return -EINVAL;
+	}
+
+	proc_handle = (struct processor_object *)handle;
+
+	object = (struct proc4430_object *)proc_handle->object;
+
+	atomic_cmpmask_and_set(&object->attach_count,
+				OMAP4430PROC_MAKE_MAGICSTAMP(0),
+				OMAP4430PROC_MAKE_MAGICSTAMP(0));
+	atomic_inc_return(&object->attach_count);
+
+	printk(KERN_ERR "proc4430_attach num_mem_entries = %d",
+				object->params.num_mem_entries);
+	/* Return memory information in params. */
+	for (i = 0; (i < object->params.num_mem_entries); i++) {
+		/* If the configured master virtual address is invalid, get the
+		* actual address by mapping the physical address into master
+		* kernel memory space.
+		*/
+		if ((object->params.mem_entries[i].master_virt_addr == (u32)-1)
+		&& (object->params.mem_entries[i].shared == true)) {
+			map_info.src = object->params.mem_entries[i].phys_addr;
+			map_info.size = object->params.mem_entries[i].size;
+			map_info.is_cached = false;
+			retval = platform_mem_map(&map_info);
+			if (retval != 0) {
+				printk(KERN_ERR "proc4430_attach failed\n");
+				return -EFAULT;
+			}
+			map_count++;
+			object->params.mem_entries[i].master_virt_addr =
+								map_info.dst;
+			params->mem_entries[i].addr
+				[PROC_MGR_ADDRTYPE_MASTERKNLVIRT] =
+								map_info.dst;
+			params->mem_entries[i].addr
+				[PROC_MGR_ADDRTYPE_SLAVEVIRT] =
+			(object->params.mem_entries[i].slave_virt_addr);
+			/* User virtual will be filled by user side. For now,
+			fill in the physical address so that it can be used
+			by mmap to remap this region into user-space */
+			params->mem_entries[i].addr
+				[PROC_MGR_ADDRTYPE_MASTERUSRVIRT] = \
+				object->params.mem_entries[i].phys_addr;
+			params->mem_entries[i].size =
+				object->params.mem_entries[i].size;
+		}
+	}
+	params->num_mem_entries = map_count;
+	return retval;
+}
+
+
+/*==========================================
+ * Function to detach from the Processor.
+ *
+ */
+int proc4430_detach(void *handle)
+{
+	struct processor_object *proc_handle = NULL;
+	struct proc4430_object *object = NULL;
+	u32 i;
+	memory_unmap_info unmap_info;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+
+		printk(KERN_ERR "proc4430_detach failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+	if (WARN_ON(handle == NULL)) {
+		printk(KERN_ERR "proc4430_detach failed "
+			"Argument Driverhandle is NULL");
+		return -EINVAL;
+	}
+
+	proc_handle = (struct processor_object *)handle;
+	object = (struct proc4430_object *)proc_handle->object;
+
+	if (!(atomic_dec_return(&object->attach_count) == \
+		OMAP4430PROC_MAKE_MAGICSTAMP(0)))
+		return 1;
+
+	for (i = 0; (i < object->params.num_mem_entries); i++) {
+		if ((object->params.mem_entries[i].master_virt_addr > 0)
+		    && (object->params.mem_entries[i].shared == true)) {
+			unmap_info.addr =
+				object->params.mem_entries[i].master_virt_addr;
+			unmap_info.size = object->params.mem_entries[i].size;
+			platform_mem_unmap(&unmap_info);
+			object->params.mem_entries[i].master_virt_addr =
+				(u32)-1;
+		}
+	}
+	return 0;
+}
+
+/*==========================================
+ * Function to start the slave processor
+ *
+ * Start the slave processor running from its entry point.
+ * Depending on the boot mode, this involves configuring the boot
+ * address and releasing the slave from reset.
+ *
+ */
+int proc4430_start(void *handle, u32 entry_pt,
+			struct processor_start_params *start_params)
+{
+	u32 reg;
+	int counter = 10;
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+
+		printk(KERN_ERR "proc4430_start failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+
+	/*FIXME: Remove handle and entry_pt if not used */
+	if (WARN_ON(start_params == NULL)) {
+		printk(KERN_ERR "proc4430_start failed "
+			"Argument processor_start_params * is NULL");
+		return -EINVAL;
+	}
+
+	reg = __raw_readl(CORE_PRM_BASE + RM_MPU_M3_RSTST_OFFSET);
+	printk(KERN_INFO "proc4430_start: Reset Status [0x%x]", reg);
+	reg = __raw_readl(CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+	printk(KERN_INFO "proc4430_start: Reset Control [0x%x]", reg);
+
+	switch (start_params->params->proc_id) {
+	case SYS_M3:
+		/* Module is managed automatically by HW */
+		__raw_writel(0x01, CORE_CM2_DUCATI_CLKCTRL);
+		/* Enable the M3 clock */
+		__raw_writel(0x02, CORE_CM2_DUCATI_CLKSTCTRL);
+		do {
+			reg = __raw_readl(CORE_CM2_DUCATI_CLKSTCTRL);
+			if (reg & 0x100) {
+				printk(KERN_INFO "M3 clock enabled:"
+				"CORE_CM2_DUCATI_CLKSTCTRL = 0x%x\n", reg);
+				break;
+			}
+			msleep(1);
+		} while (--counter);
+		if (counter == 0) {
+			printk(KERN_ERR "FAILED TO ENABLE DUCATI M3 CLOCK !\n");
+			return -EFAULT;
+		}
+		/* Check that releasing resets would indeed be effective */
+		reg = __raw_readl(CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		if (reg != 7) {
+			printk(KERN_ERR "proc4430_start: Resets in not proper state!\n");
+			__raw_writel(0x7,
+				CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		}
+
+		/* De-assert RST3, and clear the Reset status */
+		printk(KERN_INFO "De-assert RST3\n");
+		__raw_writel(0x3, CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		while (!(__raw_readl(CORE_PRM_BASE + RM_MPU_M3_RSTST_OFFSET)
+			& 0x4))
+			;
+		printk(KERN_INFO "RST3 released!");
+		__raw_writel(0x4, CORE_PRM_BASE + RM_MPU_M3_RSTST_OFFSET);
+		ducati_setup();
+
+		/* De-assert RST1, and clear the Reset status */
+		printk(KERN_INFO "De-assert RST1\n");
+		__raw_writel(0x2, CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		while (!(__raw_readl(CORE_PRM_BASE + RM_MPU_M3_RSTST_OFFSET)
+			& 0x1))
+			;
+		printk(KERN_INFO "RST1 released!");
+		__raw_writel(0x1, CORE_PRM_BASE + RM_MPU_M3_RSTST_OFFSET);
+		break;
+	case APP_M3:
+		/* De-assert RST2, and clear the Reset status */
+		printk(KERN_INFO "De-assert RST2\n");
+		__raw_writel(0x0, CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		while (!(__raw_readl(CORE_PRM_BASE + RM_MPU_M3_RSTST_OFFSET)
+			& 0x2))
+			;
+		printk(KERN_INFO "RST2 released!");
+		__raw_writel(0x2, CORE_PRM_BASE + RM_MPU_M3_RSTST_OFFSET);
+		break;
+	default:
+		printk(KERN_ERR "proc4430_start: ERROR input\n");
+		break;
+	}
+	return 0;
+}
+
+
+/*
+ * Function to stop the slave processor
+ *
+ * Stop the execution of the slave processor. Depending on the boot
+ * mode, this may result in placing the slave processor in reset.
+ *
+ *  @param	  handle	void * to the Processor instance
+ *
+ *  @sa		 proc4430_start, OMAP3530_halResetCtrl
+ */
+int
+proc4430_stop(void *handle, struct processor_stop_params *stop_params)
+{
+	u32 reg;
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_stop failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+	switch (stop_params->params->proc_id) {
+	case SYS_M3:
+		printk(KERN_INFO "Assert RST1 and RST2\n");
+		__raw_writel(0x3, CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		reg = __raw_readl(CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		ducati_destroy();
+		printk(KERN_INFO "Assert RST1 and RST2 and RST3\n");
+		__raw_writel(0x7, CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		/* Disable the M3 clock */
+		__raw_writel(0x01, CORE_CM2_DUCATI_CLKSTCTRL);
+		break;
+	case APP_M3:
+		printk(KERN_INFO "Assert RST2\n");
+		__raw_writel(0x2, CORE_PRM_BASE + RM_MPU_M3_RSTCTRL_OFFSET);
+		break;
+	default:
+		printk(KERN_ERR "proc4430_stop: ERROR input\n");
+		break;
+	}
+	return 0;
+}
+
+
+/*==============================================
+ *	 Function to read from the slave processor's memory.
+ *
+ * Read from the slave processor's memory and copy into the
+ * provided buffer.
+ */
+int proc4430_read(void *handle, u32 proc_addr, u32 *num_bytes,
+						void *buffer)
+{
+	int retval = 0;
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_read failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+
+	/* TODO */
+	return retval;
+}
+
+
+/*==============================================
+ * Function to write into the slave processor's memory.
+ *
+ * Read from the provided buffer and copy into the slave
+ * processor's memory.
+ *
+ */
+int proc4430_write(void *handle, u32 proc_addr, u32 *num_bytes,
+						void *buffer)
+{
+	int retval = 0;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_write failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+
+	/* TODO */
+	return retval;
+}
+
+
+/*=========================================================
+ * Function to perform device-dependent operations.
+ *
+ * Performs device-dependent control operations as exposed by this
+ * implementation of the Processor module.
+ */
+int proc4430_control(void *handle, int cmd, void *arg)
+{
+	int retval = 0;
+
+	/*FIXME: Remove handle,etc if not used */
+
+#ifdef CONFIG_SYSLINK_DUCATI_PM
+	/* For purpose testing */
+	switch (cmd) {
+	case PM_SUSPEND:
+	case PM_RESUME:
+		retval = ipu_pm_notifications(cmd);
+		break;
+	default:
+		printk(KERN_ERR "Invalid notification\n");
+	}
+	if (retval != PM_SUCCESS)
+		printk(KERN_ERR "Error in notifications\n");
+#endif
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_control failed "
+			"Module not initialized");
+		return -ENODEV;
+	}
+
+	return retval;
+}
+
+
+/*=====================================================
+ * Function to translate between two types of address spaces.
+ *
+ * Translate between the specified address spaces.
+ */
+int proc4430_translate_addr(void *handle,
+		void **dst_addr, enum proc_mgr_addr_type dst_addr_type,
+		void *src_addr, enum proc_mgr_addr_type src_addr_type)
+{
+	int retval = 0;
+	struct processor_object *proc_handle = NULL;
+	struct proc4430_object *object = NULL;
+	struct proc4430_mem_entry *entry = NULL;
+	bool found = false;
+	u32 fm_addr_base = (u32)NULL;
+	u32 to_addr_base = (u32)NULL;
+	u32 i;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_translate_addr failed "
+			"Module not initialized");
+		retval = -ENODEV;
+		goto error_exit;
+	}
+
+	if (WARN_ON(handle == NULL)) {
+		retval = -EINVAL;
+		goto error_exit;
+	}
+	if (WARN_ON(dst_addr == NULL)) {
+		retval = -EINVAL;
+		goto error_exit;
+	}
+	if (WARN_ON(dst_addr_type > PROC_MGR_ADDRTYPE_ENDVALUE)) {
+		retval = -EINVAL;
+		goto error_exit;
+	}
+	if (WARN_ON(src_addr == NULL)) {
+		retval = -EINVAL;
+		goto error_exit;
+	}
+	if (WARN_ON(src_addr_type > PROC_MGR_ADDRTYPE_ENDVALUE)) {
+		retval = -EINVAL;
+		goto error_exit;
+	}
+
+	proc_handle = (struct processor_object *)handle;
+	object = (struct proc4430_object *)proc_handle->object;
+	*dst_addr = NULL;
+	for (i = 0 ; i < object->params.num_mem_entries ; i++) {
+		entry = &(object->params.mem_entries[i]);
+		fm_addr_base =
+			(src_addr_type == PROC_MGR_ADDRTYPE_MASTERKNLVIRT) ?
+			entry->master_virt_addr : entry->slave_virt_addr;
+		to_addr_base =
+			(dst_addr_type == PROC_MGR_ADDRTYPE_MASTERKNLVIRT) ?
+			entry->master_virt_addr : entry->slave_virt_addr;
+		/* Determine whether which way to convert */
+		if (((u32)src_addr < (fm_addr_base + entry->size)) &&
+			((u32)src_addr >= fm_addr_base)) {
+			found = true;
+			*dst_addr = (void *)(((u32)src_addr - fm_addr_base)
+				+ to_addr_base);
+			break;
+		}
+	}
+
+	/* This check must not be removed even with build optimize. */
+	if (WARN_ON(found == false)) {
+		/*Failed to translate address. */
+		retval = -ENXIO;
+		goto error_exit;
+	}
+	return 0;
+
+error_exit:
+	return retval;
+}
+
+
+/*=================================================
+ * Function to map slave address to host address space
+ *
+ * Map the provided slave address to master address space. This
+ * function also maps the specified address to slave MMU space.
+ */
+int proc4430_map(void *handle, u32 proc_addr,
+	u32 size, u32 *mapped_addr, u32 *mapped_size, u32 map_attribs)
+{
+	int retval = 0;
+	u32 da_align;
+	u32 da;
+	u32 va_align;
+	u32 size_align;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_map failed "
+			"Module not initialized");
+		retval = -ENODEV;
+		goto error_exit;
+	}
+
+	/*FIXME: Remove handle,etc if not used */
+
+	/* FIX ME: Temporary work around until the dynamic memory mapping
+	  * for Tiler address space is available
+	  */
+	if ((map_attribs & DSP_MAPTILERADDR)) {
+		da_align = user_va2pa(current->mm, proc_addr);
+		*mapped_addr = (da_align | (proc_addr & (PAGE_SIZE - 1)));
+		return 0;
+	}
+
+	/* Calculate the page-aligned PA, VA and size */
+	va_align = PG_ALIGN_LOW(proc_addr, PAGE_SIZE);
+	size_align = PG_ALIGN_HIGH(size + (u32)proc_addr - va_align, PAGE_SIZE);
+
+	dmm_reserve_memory(size_align, &da);
+	da_align = PG_ALIGN_LOW((u32)da, PAGE_SIZE);
+	retval = ducati_mem_map(va_align, da_align, size_align, map_attribs);
+
+	/* Mapped address = MSB of DA | LSB of VA */
+	*mapped_addr = (da_align | (proc_addr & (PAGE_SIZE - 1)));
+
+error_exit:
+	return retval;
+}
+
+/*=================================================
+ * Function to unmap slave address to host address space
+ *
+ * UnMap the provided slave address to master address space. This
+ * function also unmaps the specified address to slave MMU space.
+ */
+int proc4430_unmap(void *handle, u32 mapped_addr)
+{
+	int da_align;
+	int ret_val = 0;
+	int size_align;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_map failed "
+			"Module not initialized");
+		ret_val = -1;
+		goto error_exit;
+	}
+
+	/*FIXME: Remove handle,etc if not used */
+
+	da_align = PG_ALIGN_LOW((u32)mapped_addr, PAGE_SIZE);
+	ret_val = dmm_unreserve_memory(da_align, &size_align);
+	if (WARN_ON(ret_val < 0))
+		goto error_exit;
+	ret_val = ducati_mem_unmap(da_align, size_align);
+	if (WARN_ON(ret_val < 0))
+		goto error_exit;
+	return 0;
+
+error_exit:
+	printk(KERN_WARNING "proc4430_unmap failed !!!!\n");
+	return ret_val;
+}
+
+/*=================================================
+ * Function to return list of translated mem entries
+ *
+ * This function takes the remote processor address as
+ * an input and returns the mapped Page entries in the
+ * buffer passed
+ */
+int proc4430_virt_to_phys(void *handle, u32 da, u32 *mapped_entries,
+						u32 num_of_entries)
+{
+	int da_align;
+	int i;
+	int ret_val = 0;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_virt_to_phys failed "
+			"Module not initialized");
+		ret_val = -EFAULT;
+		goto error_exit;
+	}
+
+	if (handle == NULL || mapped_entries == NULL || num_of_entries == 0) {
+		ret_val = -EFAULT;
+		goto error_exit;
+	}
+	da_align = PG_ALIGN_LOW((u32)da, PAGE_SIZE);
+	for (i = 0; i < num_of_entries; i++) {
+		mapped_entries[i] = ducati_mem_virtToPhys(da_align);
+		da_align += PAGE_SIZE;
+	}
+	return 0;
+
+error_exit:
+	printk(KERN_WARNING "proc4430_virtToPhys failed !!!!\n");
+	return ret_val;
+}
+
+
+/*=================================================
+ * Function to return PROC4430 mem_entries info
+ *
+ */
+int proc4430_proc_info(void *handle, struct proc_mgr_proc_info *procinfo)
+{
+	struct processor_object *proc_handle = NULL;
+	struct proc4430_object *object = NULL;
+	struct proc4430_mem_entry *entry = NULL;
+	int i;
+
+	if (atomic_cmpmask_and_lt(&proc4430_state.ref_count,
+					OMAP4430PROC_MAKE_MAGICSTAMP(0),
+					OMAP4430PROC_MAKE_MAGICSTAMP(1))
+					== true) {
+		printk(KERN_ERR "proc4430_proc_info failed "
+			"Module not initialized");
+		goto error_exit;
+	}
+
+	if (WARN_ON(handle == NULL))
+		goto error_exit;
+	if (WARN_ON(procinfo == NULL))
+		goto error_exit;
+
+	proc_handle = (struct processor_object *)handle;
+
+	object = (struct proc4430_object *)proc_handle->object;
+
+	for (i = 0 ; i < object->params.num_mem_entries ; i++) {
+		entry = &(object->params.mem_entries[i]);
+		procinfo->mem_entries[i].addr[PROC_MGR_ADDRTYPE_MASTERKNLVIRT]
+						= entry->master_virt_addr;
+		procinfo->mem_entries[i].addr[PROC_MGR_ADDRTYPE_SLAVEVIRT]
+						= entry->slave_virt_addr;
+		procinfo->mem_entries[i].size = entry->size;
+	}
+	procinfo->num_mem_entries = object->params.num_mem_entries;
+	procinfo->boot_mode = proc_handle->boot_mode;
+	return 0;
+
+error_exit:
+	printk(KERN_WARNING "proc4430_proc_info failed !!!!\n");
+	return -EFAULT;
+}
diff --git a/drivers/dsp/syslink/procmgr/proc4430/proc4430.h b/drivers/dsp/syslink/procmgr/proc4430/proc4430.h
new file mode 100644
index 000000000000..5903daeadaa3
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/proc4430.h
@@ -0,0 +1,147 @@
+/*
+ * proc4430.h
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+
+
+#ifndef _SYSLINK_PROC_4430_H_
+#define _SYSLINK_PROC_4430_H_
+
+
+/* Module headers */
+#include <procmgr.h>
+#include "../procdefs.h"
+#include <linux/types.h>
+
+/*
+  Module configuration structure.
+ */
+struct proc4430_config {
+	struct mutex *gate_handle;
+	/* void * of gate to be used for local thread safety */
+};
+
+/*
+  Memory entry for slave memory map configuration
+ */
+struct proc4430_mem_entry {
+	char name[PROCMGR_MAX_STRLEN];
+	/* Name identifying the memory region. */
+	u32 phys_addr;
+	/* Physical address of the memory region. */
+	u32 slave_virt_addr;
+	/* Slave virtual address of the memory region. */
+	u32 master_virt_addr;
+	/* Master virtual address of the memory region. If specified as -1,
+	* the master virtual address is assumed to be invalid, and shall be
+	* set internally within the Processor module. */
+	u32 size;
+	/* Size (in bytes) of the memory region. */
+	bool shared;
+	/* Flag indicating whether the memory region is shared between master
+	* and slave. */
+};
+
+/*
+  Configuration parameters specific to this processor.
+ */
+struct proc4430_params {
+	int num_mem_entries;
+	/* Number of memory regions to be configured. */
+	struct proc4430_mem_entry *mem_entries;
+	/* Array of information structures for memory regions
+	* to be configured. */
+	u32 reset_vector_mem_entry;
+	/* Index of the memory entry within the mem_entries array,
+	* which is the resetVector memory region. */
+};
+
+
+/* Function to initialize the slave processor */
+int proc4430_attach(void *handle, struct processor_attach_params *params);
+
+/* Function to finalize the slave processor */
+int proc4430_detach(void *handle);
+
+/* Function to start the slave processor */
+int proc4430_start(void *handle, u32 entry_pt,
+		struct processor_start_params *params);
+
+/* Function to start the stop processor */
+int proc4430_stop(void *handle,
+			struct processor_stop_params *params);
+
+/* Function to read from the slave processor's memory. */
+int proc4430_read(void *handle, u32 proc_addr, u32 *num_bytes,
+						void *buffer);
+
+/* Function to write into the slave processor's memory. */
+int proc4430_write(void *handle, u32 proc_addr, u32 *num_bytes,
+					void *buffer);
+
+/* Function to perform device-dependent operations. */
+int proc4430_control(void *handle, int cmd, void *arg);
+
+/* Function to translate between two types of address spaces. */
+int proc4430_translate_addr(void *handle, void **dst_addr,
+			enum proc_mgr_addr_type dst_addr_type,
+			void *src_addr, enum proc_mgr_addr_type src_addr_type);
+
+/* Function to map slave address to host address space */
+int proc4430_map(void *handle, u32 proc_addr, u32 size, u32 *mapped_addr,
+					u32 *mapped_size, u32 map_attribs);
+
+/* Function to unmap the slave address to host address space */
+int proc4430_unmap(void *handle, u32 mapped_addr);
+
+/* Function to retrive physical address translations */
+int proc4430_virt_to_phys(void *handle, u32 da, u32 *mapped_entries,
+					u32 num_of_entries);
+
+/* =================================================
+ *  APIs
+ * =================================================
+ */
+
+/* Function to get the default configuration for the OMAP4430PROC module */
+void proc4430_get_config(struct proc4430_config *cfg);
+
+/* Function to setup the OMAP4430PROC module. */
+int proc4430_setup(struct proc4430_config *cfg);
+
+/* Function to destroy the OMAP4430PROC module. */
+int proc4430_destroy(void);
+
+/* Function to initialize the parameters for this processor instance. */
+void proc4430_params_init(void *handle,
+			 struct proc4430_params *params);
+
+/* Function to create an instance of this processor. */
+void *proc4430_create(u16 proc_id, const struct proc4430_params *params);
+
+/* Function to delete an instance of this processor. */
+int proc4430_delete(void **handle_ptr);
+
+/* Function to open an instance of this processor. */
+int proc4430_open(void **handle_ptr, u16 proc_id);
+
+/* Function to close an instance of this processor. */
+int proc4430_close(void *handle);
+
+/* Function to get the proc info */
+int proc4430_proc_info(void *handle, struct proc_mgr_proc_info *procinfo);
+
+#endif
diff --git a/drivers/dsp/syslink/procmgr/proc4430/proc4430_drv.c b/drivers/dsp/syslink/procmgr/proc4430/proc4430_drv.c
new file mode 100644
index 000000000000..77d47ccee9ac
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/proc4430_drv.c
@@ -0,0 +1,401 @@
+/*
+ * proc4430_drv.c
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <generated/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/uaccess.h>
+#include <linux/platform_device.h>
+
+
+/* Module headers */
+#include "proc4430.h"
+#include "proc4430_drvdefs.h"
+
+
+
+/** ============================================================================
+ *  Macros and types
+ *  ============================================================================
+ */
+#define PROC4430_NAME "syslink-proc4430"
+
+static char *driver_name = PROC4430_NAME;
+
+static s32 driver_major;
+
+static s32 driver_minor;
+
+struct proc_4430_dev {
+	struct cdev cdev;
+};
+
+static struct proc_4430_dev *proc_4430_device;
+
+static struct class *proc_4430_class;
+
+
+
+/** ============================================================================
+ *  Forward declarations of internal functions
+ *  ============================================================================
+ */
+/* Linux driver function to open the driver object. */
+static int proc4430_drv_open(struct inode *inode, struct file *filp);
+
+/* Linux driver function to close the driver object. */
+static int proc4430_drv_release(struct inode *inode, struct file *filp);
+
+/* Linux driver function to invoke the APIs through ioctl. */
+static int proc4430_drv_ioctl(struct inode *inode,
+			struct file *filp, unsigned int cmd,
+			unsigned long args);
+
+/* Linux driver function to map memory regions to user space. */
+static int proc4430_drv_mmap(struct file *filp,
+			struct vm_area_struct *vma);
+
+/* Module initialization function for Linux driver. */
+static int __init proc4430_drv_initializeModule(void);
+
+/* Module finalization  function for Linux driver. */
+static void  __exit proc4430_drv_finalizeModule(void);
+
+
+
+/** ============================================================================
+ *  Globals
+ *  ============================================================================
+ */
+
+/*
+  File operations table for PROC4430.
+ */
+static const struct file_operations proc_4430_fops = {
+	.open = proc4430_drv_open,
+	.release = proc4430_drv_release,
+	.ioctl = proc4430_drv_ioctl,
+	.mmap = proc4430_drv_mmap,
+};
+
+static int proc4430_drv_open(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+static int proc4430_drv_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+
+/*
+  Linux driver function to invoke the APIs through ioctl.
+ *
+ */
+static int proc4430_drv_ioctl(struct inode *inode, struct file *filp,
+		unsigned int cmd, unsigned long args)
+{
+	int retval = 0;
+	struct proc_mgr_cmd_args *cmd_args = (struct proc_mgr_cmd_args *)args;
+	struct proc_mgr_cmd_args command_args;
+
+	switch (cmd) {
+	case CMD_PROC4430_GETCONFIG:
+	{
+		struct proc4430_cmd_args_get_config *src_args =
+			(struct proc4430_cmd_args_get_config *)args;
+		struct proc4430_config cfg;
+
+		/* copy_from_useris not needed for
+		* proc4430_get_config, since the
+		* user's config is not used.
+		*/
+		proc4430_get_config(&cfg);
+
+		retval = copy_to_user((void *)(src_args->cfg),
+				(const void *)&cfg,
+				sizeof(struct proc4430_config));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+	}
+	break;
+
+	case CMD_PROC4430_SETUP:
+	{
+		struct proc4430_cmd_args_setup *src_args =
+			(struct proc4430_cmd_args_setup *)args;
+		struct proc4430_config cfg;
+
+		retval = copy_from_user((void *)&cfg,
+			(const void *)(src_args->cfg),
+			sizeof(struct proc4430_config));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		proc4430_setup(&cfg);
+	}
+	break;
+
+	case CMD_PROC4430_DESTROY:
+	{
+		proc4430_destroy();
+	}
+	break;
+
+	case CMD_PROC4430_PARAMS_INIT:
+	{
+		struct proc4430_cmd_args_params_init src_args;
+		struct proc4430_params params;
+
+		/* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc4430_cmd_args_params_init));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		proc4430_params_init(src_args.handle, &params);
+		retval = copy_to_user((void *)(src_args.params),
+			(const void *) &params,
+			sizeof(struct proc4430_params));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+	}
+	break;
+
+	case CMD_PROC4430_CREATE:
+	{
+		struct proc4430_cmd_args_create   src_args;
+		struct proc4430_params params;
+		struct proc4430_mem_entry *entries = NULL;
+
+		/* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+				(const void *)(args),
+				sizeof(struct proc4430_cmd_args_create));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_from_user((void *) &params,
+			(const void *)(src_args.params),
+			sizeof(struct proc4430_params));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		/* Copy the contents of mem_entries from user-side */
+		if (params.num_mem_entries) {
+			entries = vmalloc(params.num_mem_entries * \
+				sizeof(struct proc4430_mem_entry));
+			if (WARN_ON(!entries))
+				goto func_exit;
+			retval = copy_from_user((void *) (entries),
+				(const void *)(params.mem_entries),
+				params.num_mem_entries * \
+				sizeof(struct proc4430_mem_entry));
+			if (WARN_ON(retval < 0)) {
+				vfree(entries);
+				goto func_exit;
+			}
+			params.mem_entries = entries;
+		}
+		src_args.handle = proc4430_create(src_args.proc_id,
+							&params);
+		if (WARN_ON(src_args.handle == NULL))
+			goto func_exit;
+		retval = copy_to_user((void *)(args),
+				(const void *)&src_args,
+				sizeof(struct proc4430_cmd_args_create));
+		/* Free the memory created */
+		if (params.num_mem_entries)
+			vfree(entries);
+	}
+	break;
+
+	case CMD_PROC4430_DELETE:
+	{
+		struct proc4430_cmd_args_delete src_args;
+
+		/* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc4430_cmd_args_delete));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = proc4430_delete(&(src_args.handle));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROC4430_OPEN:
+	{
+		struct proc4430_cmd_args_open src_args;
+
+		/*Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+				(const void *)(args),
+				sizeof(struct proc4430_cmd_args_open));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = proc4430_open(&(src_args.handle),
+					src_args.proc_id);
+		retval = copy_to_user((void *)(args),
+				(const void *)&src_args,
+			sizeof(struct proc4430_cmd_args_open));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROC4430_CLOSE:
+	{
+		struct proc4430_cmd_args_close src_args;
+
+		/*Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc4430_cmd_args_close));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = proc4430_close(src_args.handle);
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	default:
+	{
+		printk(KERN_ERR "unsupported ioctl\n");
+	}
+	break;
+	}
+func_exit:
+	/* Set the status and copy the common args to user-side. */
+	command_args.api_status = retval;
+	retval = copy_to_user((void *) cmd_args,
+		(const void *) &command_args,
+		 sizeof(struct proc_mgr_cmd_args));
+	WARN_ON(retval < 0);
+	return retval;
+}
+
+
+/*
+  Linux driver function to map memory regions to user space.
+ *
+ */
+static int proc4430_drv_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot);
+
+	if (remap_pfn_range(vma,
+			 vma->vm_start,
+			 vma->vm_pgoff,
+			 vma->vm_end - vma->vm_start,
+			 vma->vm_page_prot)) {
+		return -EAGAIN;
+	}
+	return 0;
+}
+
+
+/** ==================================================================
+ *  Functions required for multiple .ko modules configuration
+ *  ==================================================================
+ */
+/*
+  Module initialization  function for Linux driver.
+ */
+static int __init proc4430_drv_initializeModule(void)
+{
+	dev_t dev = 0 ;
+	int retval;
+
+	/* Display the version info and created date/time */
+	printk(KERN_INFO "proc4430_drv_initializeModule\n");
+
+	if (driver_major) {
+		dev = MKDEV(driver_major, driver_minor);
+		retval = register_chrdev_region(dev, 1, driver_name);
+	} else {
+		retval = alloc_chrdev_region(&dev, driver_minor, 1,
+				 driver_name);
+		driver_major = MAJOR(dev);
+	}
+
+	proc_4430_device = kmalloc(sizeof(struct proc_4430_dev), GFP_KERNEL);
+	if (!proc_4430_device) {
+		retval = -ENOMEM;
+		unregister_chrdev_region(dev, 1);
+		goto exit;
+	}
+	memset(proc_4430_device, 0, sizeof(struct proc_4430_dev));
+	cdev_init(&proc_4430_device->cdev, &proc_4430_fops);
+	proc_4430_device->cdev.owner = THIS_MODULE;
+	proc_4430_device->cdev.ops = &proc_4430_fops;
+
+	retval = cdev_add(&proc_4430_device->cdev, dev, 1);
+
+	if (retval) {
+		printk(KERN_ERR "Failed to add the syslink proc_4430 device\n");
+		goto exit;
+	}
+
+	/* udev support */
+	proc_4430_class = class_create(THIS_MODULE, "syslink-proc4430");
+
+	if (IS_ERR(proc_4430_class)) {
+		printk(KERN_ERR "Error creating bridge class\n");
+		goto exit;
+	}
+	device_create(proc_4430_class, NULL, MKDEV(driver_major, driver_minor),
+			NULL, PROC4430_NAME);
+exit:
+	return 0;
+}
+
+/*
+ function to finalize the driver module.
+ */
+static void __exit proc4430_drv_finalizeModule(void)
+{
+	dev_t devno = 0;
+
+	/* FIX ME: THIS MIGHT NOT BE THE RIGHT PLACE TO CALL THE SETUP */
+	proc4430_destroy();
+
+	devno = MKDEV(driver_major, driver_minor);
+	if (proc_4430_device) {
+		cdev_del(&proc_4430_device->cdev);
+		kfree(proc_4430_device);
+	}
+	unregister_chrdev_region(devno, 1);
+	if (proc_4430_class) {
+		/* remove the device from sysfs */
+		device_destroy(proc_4430_class, MKDEV(driver_major,
+						driver_minor));
+		class_destroy(proc_4430_class);
+	}
+	return;
+}
+
+/*
+  Macro calls that indicate initialization and finalization functions
+ *		  to the kernel.
+ */
+MODULE_LICENSE("GPL v2");
+module_init(proc4430_drv_initializeModule);
+module_exit(proc4430_drv_finalizeModule);
diff --git a/drivers/dsp/syslink/procmgr/proc4430/proc4430_drvdefs.h b/drivers/dsp/syslink/procmgr/proc4430/proc4430_drvdefs.h
new file mode 100644
index 000000000000..4176d731f1d4
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/proc4430/proc4430_drvdefs.h
@@ -0,0 +1,169 @@
+/*
+ * proc4430_drvdefs.h
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef _SYSLINK_PROC4430_H
+#define _SYSLINK_PROC4430_H
+
+
+/* Module headers */
+#include "../procmgr_drvdefs.h"
+#include "proc4430.h"
+
+
+/*  ----------------------------------------------------------------------------
+ *  IOCTL command IDs for OMAP4430PROC
+ *  ----------------------------------------------------------------------------
+ */
+/*
+ * Base command ID for OMAP4430PROC
+ */
+#define PROC4430_BASE_CMD		 0x200
+
+/*
+ * Command for PROC4430_getConfig
+ */
+#define CMD_PROC4430_GETCONFIG		(PROC4430_BASE_CMD + 1)
+
+/*
+ * Command for PROC4430_setup
+ */
+#define CMD_PROC4430_SETUP		(PROC4430_BASE_CMD + 2)
+
+/*
+ * Command for PROC4430_setup
+ */
+#define CMD_PROC4430_DESTROY		(PROC4430_BASE_CMD + 3)
+
+/*
+ * Command for PROC4430_destroy
+ */
+#define CMD_PROC4430_PARAMS_INIT	(PROC4430_BASE_CMD + 4)
+
+/*
+ * Command for PROC4430_create
+ */
+#define CMD_PROC4430_CREATE		(PROC4430_BASE_CMD + 5)
+
+/*
+ * Command for PROC4430_delete
+ */
+#define CMD_PROC4430_DELETE		(PROC4430_BASE_CMD + 6)
+
+/*
+ * Command for PROC4430_open
+ */
+#define CMD_PROC4430_OPEN		(PROC4430_BASE_CMD + 7)
+
+/*
+ * Command for PROC4430_close
+ */
+#define CMD_PROC4430_CLOSE		(PROC4430_BASE_CMD + 8)
+
+
+/*  ---------------------------------------------------
+ *  Command arguments for OMAP4430PROC
+ *  ---------------------------------------------------
+ */
+/*
+ * Command arguments for PROC4430_getConfig
+ */
+struct proc4430_cmd_args_get_config {
+	struct proc_mgr_cmd_args command_args;
+	/* Common command args */
+	struct proc4430_config *cfg;
+	/* Pointer to the OMAP4430PROC module configuration structure
+	* in which the default config is to be returned. */
+};
+
+/*
+ * Command arguments for PROC4430_setup
+ */
+struct proc4430_cmd_args_setup {
+	struct proc_mgr_cmd_args command_args;
+	/* Common command args */
+	struct proc4430_config *cfg;
+	/* Optional OMAP4430PROC module configuration. If provided as NULL,
+	* default configuration is used. */
+};
+
+/*
+ * Command arguments for PROC4430_destroy
+ */
+struct proc4430_cmd_args_destroy {
+	struct proc_mgr_cmd_args command_args;
+	/* Common command args */
+};
+
+/*
+ * Command arguments for struct struct proc4430_params_init
+ */
+struct proc4430_cmd_args_params_init {
+	struct proc_mgr_cmd_args command_args;
+	/* Common command args */
+	void *handle;
+	/* void * to the processor instance. */
+	struct proc4430_params *params;
+	/* Configuration parameters. */
+};
+
+/*
+ * Command arguments for PROC4430_create
+ */
+struct proc4430_cmd_args_create {
+	struct proc_mgr_cmd_args	 command_args;
+	/* Common command args */
+	u16 proc_id;
+	/* Processor ID for which this processor instance is required. */
+	struct proc4430_params *params;
+	/*Configuration parameters. */
+	void *handle;
+	/* void * to the created processor instance. */
+};
+
+/*
+ * Command arguments for PROC4430_delete
+ */
+struct proc4430_cmd_args_delete {
+	struct proc_mgr_cmd_args command_args;
+	/* Common command args */
+	void *handle;
+	/* Pointer to handle to the processor instance */
+};
+
+/*
+ * Command arguments for PROC4430_open
+ */
+struct proc4430_cmd_args_open {
+	struct proc_mgr_cmd_args command_args;
+	/* Common command args */
+	u16 proc_id;
+	/* Processor ID addressed by this OMAP4430PROC instance. */
+	void *handle;
+	/* Return parameter: void * to the processor instance */
+};
+
+/*
+ * Command arguments for PROC4430_close
+ */
+struct proc4430_cmd_args_close {
+	struct proc_mgr_cmd_args command_args;
+	/* Common command args */
+	void *handle;
+	/* void * to the processor instance */
+};
+
+#endif
diff --git a/drivers/dsp/syslink/procmgr/procdefs.h b/drivers/dsp/syslink/procmgr/procdefs.h
new file mode 100644
index 000000000000..eb73626d27e1
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/procdefs.h
@@ -0,0 +1,203 @@
+/*
+ * procdefs.h
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef SYSLINK_PROCDEFS_H
+#define SYSLINK_PROCDEFS_H
+
+#include <linux/types.h>
+
+/* Module level headers */
+#include <procmgr.h>
+
+
+/* =============================
+ *  Macros and types
+ * =============================
+ */
+/*
+ * Enumerates the types of Endianism of slave processor.
+ */
+enum processor_endian{
+	PROCESSOR_ENDIAN_DEFAULT = 0,
+	/* Default endianism (no conversion required) */
+	PROCESSOR_ENDIAN_BIG = 1,
+	/* Big endian */
+	PROCESSOR_ENDIAN_LITTLE = 2,
+	/* Little endian */
+	PROCESSOR_ENDIAN_ENDVALUE = 3
+	/* End delimiter indicating start of invalid values for this enum */
+};
+
+
+/*
+ * Configuration parameters for attaching to the slave Processor
+ */
+struct processor_attach_params {
+	struct proc_mgr_attach_params *params;
+	/* Common attach parameters for ProcMgr */
+	u16 num_mem_entries;
+	/* Number of valid memory entries */
+	struct proc_mgr_addr_info mem_entries[PROCMGR_MAX_MEMORY_REGIONS];
+	/* Configuration of memory regions */
+};
+
+/*
+ *Configuration parameters for starting the slave Processor
+ */
+struct processor_start_params {
+	struct proc_mgr_start_params *params;
+	/* Common start parameters for ProcMgr */
+};
+
+/*
+ *Configuration parameters for stopping the slave Processor
+ */
+struct processor_stop_params {
+	struct proc_mgr_stop_params *params;
+	/* Common start parameters for ProcMgr */
+};
+/*
+ * Function pointer type for the function to attach to the processor.
+ */
+typedef int (*processor_attach_fxn) (void *handle,
+				struct processor_attach_params *params);
+
+/*
+ * Function pointer type for the function to detach from the
+ * procssor
+ */
+typedef int (*processor_detach_fxn) (void *handle);
+
+/*
+ * Function pointer type for the function to start the processor.
+ */
+typedef int (*processor_start_fxn) (void *handle, u32 entry_pt,
+					struct processor_start_params *params);
+
+/*
+ *Function pointer type for the function to stop the processor.
+ */
+typedef int (*processor_stop_fxn) (void *handle,
+					struct processor_stop_params *params);
+
+/*
+ * Function pointer type for the function to read from the slave
+ *		processor's memory.
+ */
+typedef int (*processor_read_fxn) (void *handle, u32 proc_addr,
+				u32 *num_bytes, void *buffer);
+
+/*
+ *Function pointer type for the function to write into the slave
+ *processor's memory.
+ */
+typedef int (*processor_write_fxn) (void *handle, u32 proc_addr,
+				u32 *num_bytes, void *buffer);
+
+/*
+ *Function pointer type for the function to perform device-dependent
+ *		operations.
+ */
+typedef int (*processor_control_fxn) (void *handle, int cmd, void *arg);
+
+/*
+ *Function pointer type for the function to translate between
+ *		two types of address spaces.
+ */
+typedef int (*processor_translate_addr_fxn) (void *handle, void **dst_addr,
+		enum proc_mgr_addr_type dstAddrType, void *srcAddr,
+		enum proc_mgr_addr_type srcAddrType);
+
+/*
+ *Function pointer type for the function to map address to slave
+ *		address space
+ */
+typedef int (*processor_map_fxn) (void *handle, u32 proc_addr, u32 size,
+			u32 *mapped_addr, u32 *mapped_size, u32 map_attribs);
+
+/*
+ *Function pointer type for the function to map address to slave
+ *		address space
+ */
+typedef int (*processor_unmap_fxn) (void *handle, u32 mapped_addr);
+
+/*
+ *Function pointer type for the function that returns proc info
+ */
+typedef int (*processor_proc_info) (void *handle,
+				struct  proc_mgr_proc_info *proc_info);
+
+/*
+ *Function pointer type for the function that returns proc info
+ */
+typedef int (*processor_virt_to_phys_fxn) (void *handle, u32 da,
+			u32 *mapped_entries, u32 num_of_entries);
+
+
+/* =============================
+ *  Function table interface
+ * =============================
+ */
+/*
+ *Function table interface for Processor.
+ */
+struct processor_fxn_table {
+	processor_attach_fxn attach;
+	/* Function to attach to the slave processor */
+	processor_detach_fxn detach;
+	/* Function to detach from the slave processor */
+	processor_start_fxn start;
+	/* Function to start the slave processor */
+	processor_stop_fxn stop;
+	/* Function to stop the slave processor */
+	processor_read_fxn read;
+	/* Function to read from the slave processor's memory */
+	processor_write_fxn write;
+	/* Function to write into the slave processor's memory */
+	processor_control_fxn  control;
+	/* Function to perform device-dependent control function */
+	processor_translate_addr_fxn translateAddr;
+	/* Function to translate between address ranges */
+	processor_map_fxn map;
+	/* Function to map slave addresses to master address space */
+	processor_unmap_fxn unmap;
+	/* Function to unmap slave addresses to master address space */
+	processor_proc_info procinfo;
+	/* Function to convert Virtual to Physical pages */
+	processor_virt_to_phys_fxn virt_to_phys;
+};
+
+/* =============================
+ * Processor structure
+ * =============================
+ */
+/*
+ *  Generic Processor object. This object defines the handle type for all
+ *  Processor operations.
+ */
+struct processor_object {
+	struct processor_fxn_table proc_fxn_table;
+	/* interface function table to plug into the generic Processor. */
+	enum proc_mgr_state state;
+	/* State of the slave processor */
+	enum proc_mgr_boot_mode boot_mode;
+	/* Boot mode for the slave processor. */
+	void *object;
+	/* Pointer to Processor-specific object. */
+	u16 proc_id;
+	/* Processor ID addressed by this Processor instance. */
+};
+#endif
diff --git a/drivers/dsp/syslink/procmgr/processor.c b/drivers/dsp/syslink/procmgr/processor.c
new file mode 100644
index 000000000000..4548d12ad967
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/processor.c
@@ -0,0 +1,398 @@
+/*
+ * processor.c
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+
+/* Module level headers */
+#include "procdefs.h"
+#include "processor.h"
+
+
+
+/* =========================================
+ * Functions called by ProcMgr
+ * =========================================
+ */
+/*
+ * Function to attach to the Processor.
+ *
+ * This function calls into the specific Processor implementation
+ * to attach to it.
+ * This function is called from the ProcMgr attach function, and
+ * hence is used to perform any activities that may be required
+ * once the slave is powered up.
+ * Depending on the type of Processor, this function may or may not
+ * perform any activities.
+ */
+inline int processor_attach(void *handle,
+				struct processor_attach_params *params)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	BUG_ON(params == NULL);
+	BUG_ON(proc_handle->proc_fxn_table.attach == NULL);
+
+	proc_handle->boot_mode = params->params->boot_mode;
+	retval = proc_handle->proc_fxn_table.attach(handle, params);
+
+	if (proc_handle->boot_mode == PROC_MGR_BOOTMODE_BOOT)
+		proc_handle->state = PROC_MGR_STATE_POWERED;
+	else if (proc_handle->boot_mode == PROC_MGR_BOOTMODE_NOLOAD)
+		proc_handle->state = PROC_MGR_STATE_LOADED;
+	else if (proc_handle->boot_mode == PROC_MGR_BOOTMODE_NOBOOT)
+		proc_handle->state = PROC_MGR_STATE_RUNNNING;
+	return retval;
+}
+
+
+/*
+ * Function to detach from the Processor.
+ *
+ * This function calls into the specific Processor implementation
+ * to detach from it.
+ * This function is called from the ProcMgr detach function, and
+ * hence is useful to perform any activities that may be required
+ * before the slave is powered down.
+ * Depending on the type of Processor, this function may or may not
+ * perform any activities.
+ */
+inline int processor_detach(void *handle)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+					(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	BUG_ON(proc_handle->proc_fxn_table.detach == NULL);
+
+	retval = proc_handle->proc_fxn_table.detach(handle);
+	/* For all boot modes, at the end of detach, the Processor is in
+	* unknown state.
+	*/
+	proc_handle->state = PROC_MGR_STATE_UNKNOWN;
+	return retval;
+}
+
+
+/*
+ * Function to start the processor.
+ *
+ * This function calls into the specific Processor implementation
+ * to start the slave processor running.
+ * This function starts the slave processor running, in most
+ * devices, by programming its entry point into the boot location
+ * of the slave processor and releasing it from reset.
+ * The handle specifies the specific Processor instance to be used.
+ *
+ *  @param  handle void * to the Processor object
+ *  @param  entryPt	Entry point of the file loaded on the slave Processor
+ *
+ *  @sa	 Processor_stop
+ */
+inline int processor_start(void *handle, u32 entry_pt,
+				struct processor_start_params *params)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+					(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	/* entryPt may be 0 for some devices. Cannot check for valid/invalid. */
+	BUG_ON(params == NULL);
+	BUG_ON(proc_handle->proc_fxn_table.start == NULL);
+	retval = proc_handle->proc_fxn_table.start(handle, entry_pt, params);
+
+	if ((proc_handle->boot_mode == PROC_MGR_BOOTMODE_BOOT)
+		|| (proc_handle->boot_mode == PROC_MGR_BOOTMODE_NOLOAD))
+		proc_handle->state = PROC_MGR_STATE_RUNNNING;
+
+	return retval;
+}
+
+
+/*
+ * Function to stop the processor.
+ *
+ * This function calls into the specific Processor implementation
+ * to stop the slave processor.
+ * This function stops the slave processor running, in most
+ * devices, by placing it in reset.
+ * The handle specifies the specific Processor instance to be used.
+ */
+inline int processor_stop(void *handle,
+				struct processor_stop_params *params)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+					(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	BUG_ON(proc_handle->proc_fxn_table.stop == NULL);
+
+	retval = proc_handle->proc_fxn_table.stop(handle, params);
+
+	if ((proc_handle->boot_mode == PROC_MGR_BOOTMODE_BOOT)
+	||  (proc_handle->boot_mode == PROC_MGR_BOOTMODE_NOLOAD))
+		proc_handle->state = PROC_MGR_STATE_RESET;
+
+	return retval;
+}
+
+
+/*
+ * Function to read from the slave processor's memory.
+ *
+ * This function calls into the specific Processor implementation
+ * to read from the slave processor's memory. It reads from the
+ * specified address in the processor's address space and copies
+ * the required number of bytes into the specified buffer.
+ * It returns the number of bytes actually read in the num_bytes
+ * parameter.
+ * Depending on the processor implementation, it may result in
+ * reading from shared memory or across a peripheral physical
+ * connectivity.
+ * The handle specifies the specific Processor instance to be used.
+ */
+inline int processor_read(void *handle, u32 proc_addr,
+			u32 *num_bytes, void *buffer)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	BUG_ON(proc_addr == 0);
+	BUG_ON(num_bytes == 0);
+	BUG_ON(buffer == NULL);
+	BUG_ON(proc_handle->proc_fxn_table.read == NULL);
+
+	retval = proc_handle->proc_fxn_table.read(handle, proc_addr,
+						num_bytes, buffer);
+	return retval;
+}
+
+
+/*
+ * Function to write into the slave processor's memory.
+ *
+ * This function calls into the specific Processor implementation
+ * to write into the slave processor's memory. It writes into the
+ * specified address in the processor's address space and copies
+ * the required number of bytes from the specified buffer.
+ * It returns the number of bytes actually written in the num_bytes
+ * parameter.
+ * Depending on the processor implementation, it may result in
+ * writing into shared memory or across a peripheral physical
+ * connectivity.
+ * The handle specifies the specific Processor instance to be used.
+ */
+inline int processor_write(void *handle, u32 proc_addr, u32 *num_bytes,
+							void *buffer)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+	BUG_ON(handle == NULL);
+	BUG_ON(proc_addr == 0);
+	BUG_ON(num_bytes == 0);
+	BUG_ON(buffer == NULL);
+	BUG_ON(proc_handle->proc_fxn_table.write == NULL);
+
+	retval = proc_handle->proc_fxn_table.write(handle, proc_addr,
+						num_bytes, buffer);
+	return retval;
+}
+
+
+/*
+ * Function to get the current state of the slave Processor.
+ *
+ * This function gets the state of the slave processor as
+ * maintained on the master Processor state machine. It does not
+ * go to the slave processor to get its actual state at the time
+ * when this API is called.
+ */
+enum proc_mgr_state processor_get_state(void *handle)
+{
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+
+	return proc_handle->state;
+}
+
+
+/*
+ * Function to set the current state of the slave Processor
+ * to specified value.
+ *
+ * This function is used to set the state of the processor to the
+ * value as specified. This function may be used by external
+ * entities that affect the state of the slave processor, such as
+ * PwrMgr, error handler, or ProcMgr.
+ */
+void processor_set_state(void *handle, enum proc_mgr_state state)
+{
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	proc_handle->state = state;
+}
+
+
+/*
+ * Function to perform device-dependent operations.
+ *
+ * This function calls into the specific Processor implementation
+ * to perform device dependent control operations. The control
+ * operations supported by the device are exposed directly by the
+ * specific implementation of the Processor interface. These
+ * commands and their specific argument types are used with this
+ * function.
+ */
+inline int processor_control(void *handle, int cmd, void *arg)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	BUG_ON(proc_handle->proc_fxn_table.control == NULL);
+
+	retval = proc_handle->proc_fxn_table.control(handle, cmd, arg);
+	return retval;
+}
+
+
+/*
+ * Function to translate between two types of address spaces.
+ *
+ * This function translates addresses between two types of address
+ * spaces. The destination and source address types are indicated
+ * through parameters specified in this function.
+ */
+inline int processor_translate_addr(void *handle, void **dst_addr,
+		enum proc_mgr_addr_type dst_addr_type, void *src_addr,
+		enum proc_mgr_addr_type src_addr_type)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+					(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	BUG_ON(dst_addr == NULL);
+	BUG_ON(src_addr == NULL);
+	BUG_ON(dst_addr_type >= PROC_MGR_ADDRTYPE_ENDVALUE);
+	BUG_ON(src_addr_type >= PROC_MGR_ADDRTYPE_ENDVALUE);
+	BUG_ON(proc_handle->proc_fxn_table.translateAddr == NULL);
+
+	retval = proc_handle->proc_fxn_table.translateAddr(handle,
+			dst_addr, dst_addr_type, src_addr, src_addr_type);
+	return retval;
+}
+
+
+/*
+ * Function to map address to slave address space.
+ *
+ * This function maps the provided slave address to a host address
+ * and returns the mapped address and size.
+ */
+inline int processor_map(void *handle, u32 proc_addr, u32 size,
+			u32 *mapped_addr, u32 *mapped_size, u32 map_attribs)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+
+	BUG_ON(handle == NULL);
+	BUG_ON(proc_addr == 0);
+	BUG_ON(size == 0);
+	BUG_ON(mapped_addr == NULL);
+	BUG_ON(mapped_size == NULL);
+	BUG_ON(proc_handle->proc_fxn_table.map == NULL);
+
+	retval = proc_handle->proc_fxn_table.map(handle, proc_addr,
+			size, mapped_addr, mapped_size, map_attribs);
+	return retval;
+}
+
+/*
+ * Function to unmap address to slave address space.
+ *
+ * This function unmap the provided slave address
+ */
+inline int processor_unmap(void *handle, u32 mapped_addr)
+{
+	int retval = 0;
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+
+	retval = proc_handle->proc_fxn_table.unmap(handle, mapped_addr);
+	return retval;
+}
+
+/*
+ * Function that registers for notification when the slave
+ * processor transitions to any of the states specified.
+ *
+ * This function allows the user application to register for
+ * changes in processor state and take actions accordingly.
+
+ */
+inline int processor_register_notify(void *handle, proc_mgr_callback_fxn fxn,
+				void *args, enum proc_mgr_state state[])
+{
+	int retval = 0;
+
+	BUG_ON(handle == NULL);
+	BUG_ON(fxn == NULL);
+
+	/* TODO: TBD: To be implemented. */
+	return retval;
+}
+
+/*
+ * Function that returns the proc instance mem info
+ */
+int processor_get_proc_info(void *handle, struct proc_mgr_proc_info *procinfo)
+{
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+	int retval;
+	retval = proc_handle->proc_fxn_table.procinfo(proc_handle, procinfo);
+	return retval;
+}
+
+/*
+ * Function that returns the address translations
+ */
+int processor_virt_to_phys(void *handle, u32 da, u32 *mapped_entries,
+						u32 num_of_entries)
+{
+	struct processor_object *proc_handle =
+				(struct processor_object *)handle;
+	int retval;
+	retval = proc_handle->proc_fxn_table.virt_to_phys(handle, da,
+				mapped_entries, num_of_entries);
+	return retval;
+}
diff --git a/drivers/dsp/syslink/procmgr/processor.h b/drivers/dsp/syslink/procmgr/processor.h
new file mode 100644
index 000000000000..b4f78581839e
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/processor.h
@@ -0,0 +1,84 @@
+/*
+ * processor.h
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef SYSLINK_PROCESSOR_H_
+#define SYSLINK_PROCESSOR_H_
+
+#include <linux/types.h>
+
+/* Module level headers */
+#include "procdefs.h"
+
+/* ===================================
+ *  APIs
+ * ===================================
+ */
+/* Function to attach to the Processor. */
+int processor_attach(void *handle, struct processor_attach_params *params);
+
+/* Function to detach from the Processor. */
+int processor_detach(void *handle);
+
+/* Function to start the processor. */
+int processor_start(void *handle, u32 entry_pt,
+				struct processor_start_params *params);
+
+/* Function to stop the processor. */
+int processor_stop(void *handle,
+			struct processor_stop_params *params);
+
+/* Function to read from the slave processor's memory. */
+int processor_read(void *handle, u32 proc_addr, u32 *num_bytes, void *buffer);
+
+/* Function to read write into the slave processor's memory. */
+int processor_write(void *handle, u32 proc_addr, u32 *num_bytes, void *buffer);
+
+/* Function to get the current state of the slave Processor as maintained on
+ * the master Processor state machine.
+ */
+enum proc_mgr_state processor_get_state(void *handle);
+
+/* Function to set the current state of the slave Processor to specified value.
+ */
+void processor_set_state(void *handle, enum proc_mgr_state state);
+
+/* Function to perform device-dependent operations. */
+int processor_control(void *handle, int cmd, void *arg);
+
+/* Function to translate between two types of address spaces. */
+int processor_translate_addr(void *handle, void **dst_addr,
+	enum proc_mgr_addr_type dst_addr_type, void *src_addr,
+	enum proc_mgr_addr_type src_addr_type);
+
+/* Function to map address to slave address space */
+int processor_map(void *handle, u32 proc_addr, u32 size, u32 *mapped_addr,
+					u32 *mapped_size, u32 map_attribs);
+/* Function to unmap address to slave address space */
+int processor_unmap(void *handle, u32 mapped_addr);
+
+/* Function that registers for notification when the slave processor
+ * transitions to any of the states specified.
+ */
+int processor_register_notify(void *handle, proc_mgr_callback_fxn fxn,
+		void *args, enum proc_mgr_state state[]);
+
+/* Function that returns the return value of specific processor info
+ */
+int processor_get_proc_info(void *handle, struct proc_mgr_proc_info *procinfo);
+
+int processor_virt_to_phys(void *handle, u32 da, u32 *mapped_entries,
+						u32 num_of_entries);
+#endif
diff --git a/drivers/dsp/syslink/procmgr/procmgr.c b/drivers/dsp/syslink/procmgr/procmgr.c
new file mode 100644
index 000000000000..f7f963e4d781
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/procmgr.c
@@ -0,0 +1,958 @@
+/*
+ * procmgr.c
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/vmalloc.h>
+#include <linux/slab.h>
+#include <asm/atomic.h>
+
+/* Module level headers */
+#include <procmgr.h>
+#include "procdefs.h"
+#include "processor.h"
+#include <syslink/atomic_linux.h>
+
+/* ================================
+ *  Macros and types
+ * ================================
+ */
+/*! @brief Macro to make a correct module magic number with refCount */
+#define PROCMGR_MAKE_MAGICSTAMP(x) ((PROCMGR_MODULEID << 12u) | (x))
+
+/*
+ *  ProcMgr Module state object
+ */
+struct proc_mgr_module_object {
+	atomic_t ref_count;
+	u32 config_size;
+	/* Size of configuration structure */
+	struct proc_mgr_config cfg;
+	/* ProcMgr configuration structure */
+	struct proc_mgr_config def_cfg;
+	/* Default module configuration */
+	struct proc_mgr_params def_inst_params;
+	/* Default parameters for the ProcMgr instances */
+	struct proc_mgr_attach_params def_attach_params;
+	/* Default parameters for the ProcMgr attach function */
+	struct proc_mgr_start_params  def_start_params;
+	/* Default parameters for the ProcMgr start function */
+	struct proc_mgr_stop_params  def_stop_params;
+	/* Default parameters for the ProcMgr stop function */
+	struct mutex *gate_handle;
+	/* handle of gate to be used for local thread safety */
+	void *proc_handles[MULTIPROC_MAXPROCESSORS];
+	/* Array of handles of ProcMgr instances */
+};
+
+/*
+ * ProcMgr instance object
+ */
+struct proc_mgr_object {
+	u16 proc_id;
+	/* Processor ID associated with this ProcMgr. */
+	struct processor_object *proc_handle;
+	/* Processor ID of the processor being represented by this instance. */
+	void *loader_handle;
+	/*!< Handle to the Loader object associated with this ProcMgr. */
+	void *pwr_handle;
+	/*!< Handle to the PwrMgr object associated with this ProcMgr. */
+	/*!< Processor ID of the processor being represented by this instance */
+	struct proc_mgr_params params;
+	/* ProcMgr instance params structure */
+	struct proc_mgr_attach_params attach_params;
+	/* ProcMgr attach params structure */
+	struct proc_mgr_start_params  start_params;
+	/* ProcMgr start params structure */
+	struct proc_mgr_stop_params  stop_params;
+	/* ProcMgr start params structure */
+	u32 file_id;
+	/*!< File ID of the loaded static executable */
+	u16 num_mem_entries;
+	/* Number of valid memory entries */
+	struct proc_mgr_addr_info mem_entries[PROCMGR_MAX_MEMORY_REGIONS];
+	/* Configuration of memory regions */
+};
+
+struct proc_mgr_module_object proc_mgr_obj_state = {
+	.config_size = sizeof(struct proc_mgr_config),
+	.def_cfg.gate_handle = NULL,
+	.gate_handle = NULL,
+	.def_inst_params.proc_handle   = NULL,
+	.def_attach_params.boot_mode = PROC_MGR_BOOTMODE_BOOT,
+	.def_start_params.proc_id = 0
+};
+
+
+/*======================================
+ * Function to get the default configuration for the ProcMgr
+ * module.
+ *
+* This function can be called by the application to get their
+* configuration parameter to ProcMgr_setup filled in by the
+* ProcMgr module with the default parameters. If the user does
+* not wish to make any change in the default parameters, this API
+* is not required to be called.
+ */
+void proc_mgr_get_config(struct proc_mgr_config *cfg)
+{
+	BUG_ON(cfg == NULL);
+	memcpy(cfg, &proc_mgr_obj_state.def_cfg,
+			sizeof(struct proc_mgr_config));
+	return;
+}
+EXPORT_SYMBOL(proc_mgr_get_config);
+
+/*
+ * Function to setup the ProcMgr module.
+ *
+ *This function sets up the ProcMgr module. This function must
+ *be called before any other instance-level APIs can be invoked.
+ *Module-level configuration needs to be provided to this
+ *function. If the user wishes to change some specific config
+ *parameters, then ProcMgr_getConfig can be called to get the
+ *configuration filled with the default values. After this, only
+ *the required configuration values can be changed. If the user
+ *does not wish to make any change in the default parameters, the
+ *application can simply call ProcMgr_setup with NULL parameters.
+ *The default parameters would get automatically used.
+ */
+int proc_mgr_setup(struct proc_mgr_config *cfg)
+{
+	int retval = 0;
+	struct proc_mgr_config tmp_cfg;
+
+	/* This sets the refCount variable is not initialized, upper 16 bits is
+	* written with module Id to ensure correctness of refCount variable.
+	*/
+	atomic_cmpmask_and_set(&proc_mgr_obj_state.ref_count,
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(0));
+
+	if (atomic_inc_return(&proc_mgr_obj_state.ref_count)
+		!= PROCMGR_MAKE_MAGICSTAMP(1u))
+		return 0;
+	if (cfg == NULL) {
+		proc_mgr_get_config(&tmp_cfg);
+		cfg = &tmp_cfg;
+	}
+	if (cfg->gate_handle != NULL) {
+		proc_mgr_obj_state.gate_handle = cfg->gate_handle;
+	} else {
+		/* User has not provided any gate handle, so create a
+		*default handle.
+		*/
+		proc_mgr_obj_state.gate_handle = kmalloc(sizeof(struct mutex),
+						GFP_KERNEL);
+		mutex_init(proc_mgr_obj_state.gate_handle);
+	}
+	memcpy(&proc_mgr_obj_state.cfg, cfg, sizeof(struct proc_mgr_config));
+	/* Initialize the procHandles array. */
+	memset(&proc_mgr_obj_state.proc_handles, 0,
+		(sizeof(void *) * MULTIPROC_MAXPROCESSORS));
+	return retval;
+}
+EXPORT_SYMBOL(proc_mgr_setup);
+
+/*==================================
+ *  Function to destroy the ProcMgr module.
+ *
+ * Once this function is called, other ProcMgr module APIs, except
+ * for the proc_mgr_get_config API cannot be called anymore.
+ */
+int proc_mgr_destroy(void)
+{
+	int retval = 0;
+	int i;
+
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_destroy: Error - module not initialized\n");
+		return -EFAULT;
+	}
+	if (atomic_dec_return(&proc_mgr_obj_state.ref_count)
+		 == PROCMGR_MAKE_MAGICSTAMP(0)) {
+
+		/* Check if any ProcMgr instances have not been deleted so far
+		*. If not,delete them
+		*/
+		for (i = 0 ; i < MULTIPROC_MAXPROCESSORS; i++) {
+			if (proc_mgr_obj_state.proc_handles[i] != NULL)
+				proc_mgr_delete
+				(&(proc_mgr_obj_state.proc_handles[i]));
+		}
+
+		mutex_destroy(proc_mgr_obj_state.gate_handle);
+		kfree(proc_mgr_obj_state.gate_handle);
+		/* Decrease the refCount */
+		atomic_set(&proc_mgr_obj_state.ref_count,
+			PROCMGR_MAKE_MAGICSTAMP(0));
+	}
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_destroy);
+
+/*=====================================
+ *  Function to initialize the parameters for the ProcMgr instance.
+ *
+ * This function can be called by the application to get their
+ * configuration parameter to ProcMgr_create filled in by the
+ * ProcMgr module with the default parameters.
+ */
+void proc_mgr_params_init(void *handle, struct proc_mgr_params *params)
+{
+	struct proc_mgr_object *proc_handle = (struct proc_mgr_object *)handle;
+
+	if (WARN_ON(params == NULL))
+		goto exit;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_params_init: Error - module not initialized\n");
+	}
+	if (handle == NULL) {
+		memcpy(params, &(proc_mgr_obj_state.def_inst_params),
+				sizeof(struct proc_mgr_params));
+	} else {
+		/* Return updated ProcMgr instance specific parameters. */
+		memcpy(params, &(proc_handle->params),
+				sizeof(struct proc_mgr_params));
+	}
+exit:
+	return;
+}
+EXPORT_SYMBOL(proc_mgr_params_init);
+
+/*=====================================
+ *  Function to create a ProcMgr object for a specific slave
+ * processor.
+ *
+ * This function creates an instance of the ProcMgr module and
+ * returns an instance handle, which is used to access the
+ * specified slave processor. The processor ID specified here is
+ * the ID of the slave processor as configured with the MultiProc
+ * module.
+ * Instance-level configuration needs to be provided to this
+ * function. If the user wishes to change some specific config
+ * parameters, then struct proc_mgr_params_init can be called to get the
+ * configuration filled with the default values. After this, only
+ * the required configuration values can be changed. For this
+ * API, the params argument is not optional, since the user needs
+ * to provide some essential values such as loader, PwrMgr and
+ * Processor instances to be used with this ProcMgr instance.
+ */
+void *proc_mgr_create(u16 proc_id, const struct proc_mgr_params *params)
+{
+	struct proc_mgr_object *handle = NULL;
+
+	BUG_ON(!IS_VALID_PROCID(proc_id));
+	BUG_ON(params == NULL);
+	BUG_ON(params->proc_handle == NULL);
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_create: Error - module not initialized\n");
+		return NULL;
+	}
+	if (proc_mgr_obj_state.proc_handles[proc_id] != NULL) {
+		handle = proc_mgr_obj_state.proc_handles[proc_id];
+		printk(KERN_WARNING "proc_mgr_create:"
+			"Processor already exists for specified"
+			"%d  proc_id, handle = 0x%x\n", proc_id, (u32)handle);
+		return handle;
+	}
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	handle = (struct proc_mgr_object *)
+				vmalloc(sizeof(struct proc_mgr_object));
+	BUG_ON(handle == NULL);
+	memset(handle, 0, sizeof(struct proc_mgr_object));
+	memcpy(&(handle->params), params, sizeof(struct proc_mgr_params));
+	handle->proc_id = proc_id;
+	handle->proc_handle = params->proc_handle;
+	handle->loader_handle = params->loader_handle;
+	handle->pwr_handle = params->pwr_handle;
+	proc_mgr_obj_state.proc_handles[proc_id] = handle;
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return handle;
+}
+EXPORT_SYMBOL(proc_mgr_create);
+
+/*===================================
+ *  Function to delete a ProcMgr object for a specific slave
+ * processor.
+ *
+ * Once this function is called, other ProcMgr instance level APIs
+ * that require the instance handle cannot be called.
+ *
+ */
+int
+proc_mgr_delete(void **handle_ptr)
+{
+	int retval = 0;
+	struct proc_mgr_object *handle;
+
+	BUG_ON(handle_ptr == NULL);
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_delete: Error - module not initialized\n");
+		return -EFAULT;
+	}
+
+	handle = (struct proc_mgr_object *)(*handle_ptr);
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	proc_mgr_obj_state.proc_handles[handle->proc_id] = NULL;
+	vfree(handle);
+	*handle_ptr = NULL;
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;
+}
+EXPORT_SYMBOL(proc_mgr_delete);
+
+/*======================================
+ *  Function to open a handle to an existing ProcMgr object handling
+ * the proc_id.
+ *
+ * This function returns a handle to an existing ProcMgr instance
+ * created for this proc_id. It enables other entities to access
+ * and use this ProcMgr instance.
+ */
+int proc_mgr_open(void **handle_ptr, u16 proc_id)
+{
+	int retval = 0;
+
+	BUG_ON(handle_ptr == NULL);
+	BUG_ON(!IS_VALID_PROCID(proc_id));
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_open: Error - module not initialized\n");
+		return -EFAULT;
+	}
+
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	*handle_ptr = proc_mgr_obj_state.proc_handles[proc_id];
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;
+}
+EXPORT_SYMBOL(proc_mgr_open);
+
+/*=====================================
+ *  Function to close this handle to the ProcMgr instance.
+ *
+ * This function closes the handle to the ProcMgr instance
+ * obtained through proc_mgr_open call made earlier.
+ */
+int proc_mgr_close(void *handle)
+{
+	int retval = 0;
+
+	BUG_ON(handle == NULL);
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_close: Error - module not initialized\n");
+		return -EFAULT;
+	}
+	/* Nothing to be done for closing the handle. */
+	return retval;
+}
+EXPORT_SYMBOL(proc_mgr_close);
+
+/*========================================
+ *  Function to initialize the parameters for the ProcMgr attach
+ * function.
+ *
+ * This function can be called by the application to get their
+ * configuration parameter to proc_mgr_attach filled in by the
+ * ProcMgr module with the default parameters. If the user does
+ * not wish to make any change in the default parameters, this API
+ * is not required to be called.
+ */
+void proc_mgr_get_attach_params(void *handle,
+				struct proc_mgr_attach_params *params)
+{
+	struct proc_mgr_object *proc_mgr_handle =
+				(struct proc_mgr_object *)handle;
+	BUG_ON(params == NULL);
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_get_attach_params:"
+			"Error - module not initialized\n");
+	}
+	if (handle == NULL) {
+		memcpy(params, &(proc_mgr_obj_state.def_attach_params),
+				sizeof(struct proc_mgr_attach_params));
+	} else {
+		/* Return updated ProcMgr instance specific parameters. */
+		memcpy(params, &(proc_mgr_handle->attach_params),
+				sizeof(struct proc_mgr_attach_params));
+	}
+	return;
+}
+EXPORT_SYMBOL(proc_mgr_get_attach_params);
+
+/*
+ *  Function to attach the client to the specified slave and also
+ * initialize the slave (if required).
+ *
+ * This function attaches to an instance of the ProcMgr module and
+ * performs any hardware initialization required to power up the
+ * slave device. This function also performs the required state
+ * transitions for this ProcMgr instance to ensure that the local
+ * object representing the slave device correctly indicates the
+ * state of the slave device. Depending on the slave boot mode
+ * being used, the slave may be powered up, in reset, or even
+ * running state.
+ * Configuration parameters need to be provided to this
+ * function. If the user wishes to change some specific config
+ * parameters, then proc_mgr_get_attach_params can be called to get
+ * the configuration filled with the default values. After this,
+ * only the required configuration values can be changed. If the
+ * user does not wish to make any change in the default parameters,
+ * the application can simply call proc_mgr_attach with NULL
+ * parameters.
+ * The default parameters would get automatically used.
+ */
+int proc_mgr_attach(void *handle, struct proc_mgr_attach_params *params)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+				(struct proc_mgr_object *)handle;
+	struct proc_mgr_attach_params tmp_params;
+	struct processor_attach_params proc_attach_params;
+
+	if (params == NULL) {
+		proc_mgr_get_attach_params(handle, &tmp_params);
+		params = &tmp_params;
+	}
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_attach:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	if (WARN_ON(handle == NULL)) {
+		retval = -EFAULT;
+		goto exit;
+	}
+	if (WARN_ON(params->boot_mode == PROC_MGR_BOOTMODE_ENDVALUE)) {
+		retval = -EINVAL;
+		goto exit;
+	}
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	/* Copy the user provided values into the instance object. */
+	memcpy(&(proc_mgr_handle->attach_params), params,
+				sizeof(struct proc_mgr_attach_params));
+	proc_attach_params.params = params;
+	proc_attach_params.num_mem_entries = 0;
+	/* Attach to the specified Processor instance. */
+	retval = processor_attach(proc_mgr_handle->proc_handle,
+					&proc_attach_params);
+	proc_mgr_handle->num_mem_entries = proc_attach_params.num_mem_entries;
+	printk(KERN_INFO "proc_mgr_attach:proc_mgr_handle->num_mem_entries = %d\n",
+			proc_mgr_handle->num_mem_entries);
+	/* Store memory information in local object.*/
+	memcpy(&(proc_mgr_handle->mem_entries),
+		&(proc_attach_params.mem_entries),
+		sizeof(proc_mgr_handle->mem_entries));
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+exit:
+	return retval;
+}
+EXPORT_SYMBOL(proc_mgr_attach);
+
+/*===================================
+ *  Function to detach the client from the specified slave and also
+ * finalze the slave (if required).
+ *
+ * This function detaches from an instance of the ProcMgr module
+ * and performs any hardware finalization required to power down
+ * the slave device. This function also performs the required state
+ * transitions for this ProcMgr instance to ensure that the local
+ * object representing the slave device correctly indicates the
+ * state of the slave device. Depending on the slave boot mode
+ * being used, the slave may be powered down, in reset, or left in
+ * its original state.
+*/
+int proc_mgr_detach(void *handle)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+				(struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_detach:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(handle == NULL);
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	/* Detach from the Processor. */
+	retval = processor_detach(proc_mgr_handle->proc_handle);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;
+}
+EXPORT_SYMBOL(proc_mgr_detach);
+
+/*===============================
+ *  Function to initialize the parameters for the ProcMgr start
+ * function.
+ *
+ * This function can be called by the application to get their
+ * configuration parameter to proc_mgr_start filled in by the
+ * ProcMgr module with the default parameters. If the user does
+ * not wish to make any change in the default parameters, this API
+ * is not required to be called.
+ *
+ */
+void proc_mgr_get_start_params(void *handle,
+				struct proc_mgr_start_params *params)
+{
+	struct proc_mgr_object *proc_mgr_handle =
+					(struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_get_start_params:"
+			"Error - module not initialized\n");
+	}
+	BUG_ON(params == NULL);
+
+	if (handle == NULL) {
+		memcpy(params, &(proc_mgr_obj_state.def_start_params),
+				sizeof(struct proc_mgr_start_params));
+	} else {
+		/* Return updated ProcMgr instance specific parameters. */
+		memcpy(params, &(proc_mgr_handle->start_params),
+				sizeof(struct proc_mgr_start_params));
+	}
+	return;
+}
+EXPORT_SYMBOL(proc_mgr_get_start_params);
+
+/*==========================================
+ *  Function to start the slave processor running.
+ *
+ * Function to start execution of the loaded code on the slave
+ * from the entry point specified in the slave executable loaded
+ * earlier by call to proc_mgr_load ().
+ * After successful completion of this function, the ProcMgr
+ * instance is expected to be in the proc_mgr_State_Running state.
+ */
+int proc_mgr_start(void *handle, u32 entry_point,
+			struct proc_mgr_start_params *params)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+					(struct proc_mgr_object *)handle;
+	struct proc_mgr_start_params   tmp_params;
+	struct processor_start_params proc_params;
+
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_start:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(handle == NULL);
+
+	if (params == NULL) {
+		proc_mgr_get_start_params(handle, &tmp_params);
+		params = &tmp_params;
+	}
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	memcpy(&(proc_mgr_handle->start_params), params,
+					sizeof(struct proc_mgr_start_params));
+	/* Start the slave processor running. */
+	proc_params.params = params;
+	retval = processor_start(proc_mgr_handle->proc_handle,
+						entry_point, &proc_params);
+
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_start);
+
+/*========================================
+ *  Function to stop the slave processor.
+ *
+ * Function to stop execution of the slave processor.
+ * Depending on the boot mode, after successful completion of this
+ * function, the ProcMgr instance may be in the proc_mgr_State_Reset
+ * state.
+ *
+ */
+int proc_mgr_stop(void *handle, struct proc_mgr_stop_params *params)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+				(struct proc_mgr_object *)handle;
+	struct processor_stop_params proc_params;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_stop:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(handle == NULL);
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	proc_params.params = params;
+	retval = processor_stop(proc_mgr_handle->proc_handle,
+						&proc_params);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_stop);
+
+/*===================================
+ *  Function to get the current state of the slave Processor.
+ *
+ * This function gets the state of the slave processor as
+ * maintained on the master Processor state machine. It does not
+ * go to the slave processor to get its actual state at the time
+ * when this API is called.
+ *
+ */
+enum proc_mgr_state proc_mgr_get_state(void *handle)
+{
+	struct proc_mgr_object *proc_mgr_handle =
+				(struct proc_mgr_object *)handle;
+	enum proc_mgr_state state = PROC_MGR_STATE_UNKNOWN;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_get_state:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(handle == NULL);
+
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	state = processor_get_state(proc_mgr_handle->proc_handle);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return state;
+}
+EXPORT_SYMBOL(proc_mgr_get_state);
+
+/*==================================================
+ *  Function to read from the slave processor's memory.
+ *
+ * This function reads from the specified address in the
+ * processor's address space and copies the required number of
+ * bytes into the specified buffer.
+ * It returns the number of bytes actually read in thenum_bytes
+ * parameter.
+ */
+int proc_mgr_read(void *handle, u32 proc_addr, u32 *num_bytes, void *buffer)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+					(struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_read:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(handle == NULL);
+	BUG_ON(proc_addr == 0);
+	BUG_ON(num_bytes == NULL);
+	BUG_ON(buffer == NULL);
+
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+
+	retval = processor_read(proc_mgr_handle->proc_handle, proc_addr,
+							num_bytes, buffer);
+	WARN_ON(retval < 0);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;
+}
+EXPORT_SYMBOL(proc_mgr_read);
+
+/*
+ *  Function to write into the slave processor's memory.
+ *
+ * This function writes into the specified address in the
+ * processor's address space and copies the required number of
+ * bytes from the specified buffer.
+ * It returns the number of bytes actually written in thenum_bytes
+ * parameter.
+ */
+int proc_mgr_write(void *handle, u32 proc_addr, u32 *num_bytes, void *buffer)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+					(struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_write:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(proc_addr == 0);
+	BUG_ON(num_bytes == NULL);
+	BUG_ON(buffer == NULL);
+
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	retval = processor_write(proc_mgr_handle->proc_handle, proc_addr,
+							num_bytes, buffer);
+	WARN_ON(retval < 0);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_write);
+
+
+/*===================================
+ *  Function to perform device-dependent operations.
+ *
+ * This function performs control operations supported by the
+ * as exposed directly by the specific implementation of the
+ * Processor interface. These commands and their specific argument
+ * types are used with this function.
+ */
+int proc_mgr_control(void *handle, int cmd, void *arg)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle
+					= (struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_control:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(handle == NULL);
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	/* Perform device-dependent control operation. */
+	retval = processor_control(proc_mgr_handle->proc_handle, cmd, arg);
+	WARN_ON(retval < 0);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_control);
+
+/*========================================
+ *  Function to translate between two types of address spaces.
+ *
+ * This function translates addresses between two types of address
+ * spaces. The destination and source address types are indicated
+ * through parameters specified in this function.
+ */
+int proc_mgr_translate_addr(void *handle, void **dst_addr,
+		enum proc_mgr_addr_type dst_addr_type, void *src_addr,
+		enum proc_mgr_addr_type src_addr_type)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+					(struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_translate_addr:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(dst_addr == NULL);
+	BUG_ON(handle == NULL);
+	BUG_ON(dst_addr_type > PROC_MGR_ADDRTYPE_ENDVALUE);
+	BUG_ON(src_addr == NULL);
+	BUG_ON(src_addr_type > PROC_MGR_ADDRTYPE_ENDVALUE);
+
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	/* Translate the address. */
+	retval = processor_translate_addr(proc_mgr_handle->proc_handle,
+		dst_addr, dst_addr_type, src_addr, src_addr_type);
+	WARN_ON(retval < 0);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_translate_addr);
+
+/*============================================
+ *  Function to map address to slave address space.
+ *
+ * This function maps the provided slave address to a host address
+ * and returns the mapped address and size.
+ *
+ */
+int proc_mgr_map(void *handle, u32 proc_addr, u32 size, u32 *mapped_addr,
+			u32 *mapped_size, u32 map_attribs)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+				(struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_map:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(handle == NULL);
+	BUG_ON(proc_addr == 0);
+	BUG_ON(mapped_addr == NULL);
+	BUG_ON(mapped_size == NULL);
+
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+
+	/* Map to host address space. */
+	retval = processor_map(proc_mgr_handle->proc_handle, proc_addr,
+				size, mapped_addr, mapped_size, map_attribs);
+	WARN_ON(retval < 0);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_map);
+
+/*============================================
+ *  Function to unmap address to slave address space.
+ *
+ * This function unmaps the provided slave address to a host address
+ *
+ */
+int proc_mgr_unmap(void *handle, u32 mapped_addr)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+				(struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_unmap:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+
+	/* Map to host address space. */
+	retval = processor_unmap(proc_mgr_handle->proc_handle, mapped_addr);
+	WARN_ON(retval < 0);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_unmap);
+
+/*=================================
+ *  Function that registers for notification when the slave
+ * processor transitions to any of the states specified.
+ *
+ * This function allows the user application to register for
+ * changes in processor state and take actions accordingly.
+ *
+ */
+int proc_mgr_register_notify(void *handle, proc_mgr_callback_fxn fxn,
+				void *args, enum proc_mgr_state state[])
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle
+				= (struct proc_mgr_object *)handle;
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_register_notify:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	BUG_ON(handle == NULL);
+	BUG_ON(fxn == NULL);
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+	retval = processor_register_notify(proc_mgr_handle->proc_handle, fxn,
+					args, state);
+	WARN_ON(retval < 0);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;
+}
+EXPORT_SYMBOL(proc_mgr_register_notify);
+
+/*
+ *  Function that returns information about the characteristics of
+ * the slave processor.
+ */
+int proc_mgr_get_proc_info(void *handle, struct proc_mgr_proc_info *proc_info)
+{
+	struct proc_mgr_object *proc_mgr_handle =
+					(struct proc_mgr_object *)handle;
+	struct processor_object *proc_handle;
+
+	struct proc_mgr_proc_info proc_info_test;
+
+	if (atomic_cmpmask_and_lt(&(proc_mgr_obj_state.ref_count),
+		PROCMGR_MAKE_MAGICSTAMP(0), PROCMGR_MAKE_MAGICSTAMP(1))
+		 == true) {
+		printk(KERN_ERR "proc_mgr_get_proc_info:"
+			"Error - module not initialized\n");
+		return -EFAULT;
+	}
+	if (WARN_ON(handle == NULL))
+		goto error_exit;
+	if (WARN_ON(proc_info == NULL))
+		goto error_exit;
+	proc_handle = proc_mgr_handle->proc_handle;
+	if (WARN_ON(proc_handle == NULL))
+		goto error_exit;
+
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+
+	processor_get_proc_info(proc_handle, &proc_info_test);
+	/* Return bootMode information. */
+	proc_info->boot_mode = proc_mgr_handle->attach_params.boot_mode;
+	/* Return memory information. */
+	proc_info->num_mem_entries = proc_mgr_handle->num_mem_entries;
+	memcpy(&(proc_info->mem_entries),
+			&(proc_mgr_handle->mem_entries),
+			sizeof(proc_mgr_handle->mem_entries));
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return 0;
+error_exit:
+	return -EFAULT;
+}
+EXPORT_SYMBOL(proc_mgr_get_proc_info);
+
+/*============================================
+ *  Function to get virtual to physical address translations
+ *
+ * This function retrieves physical entries
+ *
+ */
+int proc_mgr_virt_to_phys(void *handle, u32 da, u32 *mapped_entries,
+						u32 num_of_entries)
+{
+	int retval = 0;
+	struct proc_mgr_object *proc_mgr_handle =
+				(struct proc_mgr_object *)handle;
+
+	WARN_ON(mutex_lock_interruptible(proc_mgr_obj_state.gate_handle));
+
+	/* Map to host address space. */
+	retval = processor_virt_to_phys(proc_mgr_handle->proc_handle, da,
+				mapped_entries, num_of_entries);
+	WARN_ON(retval < 0);
+	mutex_unlock(proc_mgr_obj_state.gate_handle);
+	return retval;;
+}
+EXPORT_SYMBOL(proc_mgr_virt_to_phys);
+
diff --git a/drivers/dsp/syslink/procmgr/procmgr_drv.c b/drivers/dsp/syslink/procmgr/procmgr_drv.c
new file mode 100644
index 000000000000..54c72ab011de
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/procmgr_drv.c
@@ -0,0 +1,759 @@
+/*
+ * procmgr_drv.c
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#include <generated/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/platform_device.h>
+
+/* Module headers */
+#include <procmgr.h>
+#include "procmgr_drvdefs.h"
+
+#define PROCMGR_NAME "syslink-procmgr"
+
+static char *driver_name = PROCMGR_NAME;
+
+static s32 driver_major;
+
+static s32 driver_minor;
+
+struct procmgr_dev {
+	struct cdev cdev;
+};
+
+struct platform_device	*omap_proc_dev;
+static struct platform_device	*procmgr_pdev;
+static struct procmgr_dev *procmgr_device;
+
+static struct class *proc_mgr_class;
+
+
+/** ====================================
+ *  Forward declarations of internal functions
+ *  ====================================
+ */
+/* Linux driver function to open the driver object. */
+static int proc_mgr_drv_open(struct inode *inode, struct file *filp);
+
+/* Linux driver function to close the driver object. */
+static int proc_mgr_drv_release(struct inode *inode, struct file *filp);
+
+/* Linux driver function to invoke the APIs through ioctl. */
+static int proc_mgr_drv_ioctl(struct inode *inode,
+				 struct file *filp,
+				 unsigned int cmd,
+				 unsigned long args);
+
+/* Linux driver function to map memory regions to user space. */
+static int proc_mgr_drv_mmap(struct file *filp, struct vm_area_struct *vma);
+
+/* Module initialization function for Linux driver. */
+static int __init proc_mgr_drv_initialize_module(void);
+
+/* Module finalization  function for Linux driver. */
+static void  __exit proc_mgr_drv_finalize_module(void);
+
+/* Platform driver probe function */
+static int __devinit proc_mgr_probe(struct platform_device *pdev);
+
+/* Platform driver remove function */
+static int __devexit proc_mgr_remove(struct platform_device *pdev);
+
+/*
+ * name   DriverOps
+ *
+ * desc   Function to invoke the APIs through ioctl
+ *
+ */
+static const struct file_operations procmgr_fops = {
+	.open  =  proc_mgr_drv_open,
+	.ioctl =  proc_mgr_drv_ioctl,
+	.release = proc_mgr_drv_release,
+	.mmap = proc_mgr_drv_mmap,
+} ;
+
+/* Imtiaz changed places */
+static struct platform_driver procmgr_driver = {
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = PROCMGR_NAME,
+	},
+	.probe		= proc_mgr_probe,
+	.remove		= __devexit_p(proc_mgr_remove),
+	.shutdown	= NULL,
+	.suspend	= NULL,
+	.resume		= NULL,
+};
+
+/*
+* brief  Linux specific function to open the driver.
+ */
+static int proc_mgr_drv_open(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+/*
+* brief  Linux driver function to close the driver object.
+ */
+static int proc_mgr_drv_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+/*
+* Linux driver function to invoke the APIs through ioctl.
+ */
+static int proc_mgr_drv_ioctl(struct inode *inode, struct file *filp,
+			unsigned int cmd, unsigned long args)
+{
+	int retval = 0;
+	struct proc_mgr_cmd_args *cmd_args = (struct proc_mgr_cmd_args *)args;
+	struct proc_mgr_cmd_args command_args;
+
+	switch (cmd) {
+	case CMD_PROCMGR_GETCONFIG:
+	{
+		struct proc_mgr_cmd_args_get_config *src_args =
+			(struct proc_mgr_cmd_args_get_config *)args;
+		struct proc_mgr_config cfg;
+
+		/* copy_from_user is not needed for proc_mgr_get_config,
+		* since the user's config is not used.
+		*/
+		proc_mgr_get_config(&cfg);
+
+		retval = copy_to_user((void *)(src_args->cfg),
+				(const void *)&cfg,
+				sizeof(struct proc_mgr_config));
+
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_SETUP:
+	{
+		struct proc_mgr_cmd_args_setup *src_args =
+			(struct proc_mgr_cmd_args_setup *)args;
+		struct proc_mgr_config cfg;
+
+		retval = copy_from_user((void *)&cfg,
+				(const void *)(src_args->cfg),
+				sizeof(struct proc_mgr_config));
+
+		/* This check is needed at run-time also since it
+		* depends on run environment.
+		* It must not be optimized out.
+		*/
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+
+		 retval = proc_mgr_setup(&cfg);
+	}
+	break;
+
+	case CMD_PROCMGR_DESTROY:
+	{
+		retval = proc_mgr_destroy();
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_PARAMS_INIT:
+	{
+		struct proc_mgr_cmd_args_params_init src_args;
+		struct proc_mgr_params params;
+
+		/* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc_mgr_cmd_args_params_init));
+
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+
+			proc_mgr_params_init(src_args.handle, &params);
+
+		/* Copy only the params to user-side */
+		retval = copy_to_user((void *)(src_args.params),
+				(const void *)&params,
+				sizeof(struct proc_mgr_params));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_CREATE:
+	{
+		struct proc_mgr_cmd_args_create src_args;
+
+		/* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_create));
+
+		src_args.handle = proc_mgr_create(src_args.proc_id,
+					 &(src_args.params));
+		if (src_args.handle == NULL) {
+			retval = -EFAULT;
+			goto func_exit;
+		}
+		retval = copy_to_user((void *)(args),
+			(const void *)&src_args,
+			sizeof(struct proc_mgr_cmd_args_create));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_DELETE:
+	{
+		struct proc_mgr_cmd_args_delete src_args;
+
+		/* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_delete));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+
+		retval = proc_mgr_delete(&(src_args.handle));
+	}
+	break;
+
+	case CMD_PROCMGR_OPEN:
+	{
+		struct proc_mgr_cmd_args_open src_args;
+
+		/* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_open));
+
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_open(&(src_args.handle),
+						src_args.proc_id);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = proc_mgr_get_proc_info(src_args.handle,
+				&(src_args.proc_info));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(args), (const void *)&src_args,
+				sizeof(struct proc_mgr_cmd_args_open));
+		WARN_ON(retval);
+	}
+	break;
+
+	case CMD_PROCMGR_CLOSE:
+	{
+		struct proc_mgr_cmd_args_close src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_close));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_close(&(src_args.handle));
+	}
+	break;
+
+	case CMD_PROCMGR_GETATTACHPARAMS:
+	{
+		struct proc_mgr_cmd_args_get_attach_params src_args;
+		struct proc_mgr_attach_params params;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_get_attach_params));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		proc_mgr_get_attach_params(src_args.handle, &params);
+		retval = copy_to_user((void *)(src_args.params),
+				(const void *)&params,
+				sizeof(struct proc_mgr_attach_params));
+		WARN_ON(retval);
+	}
+	break;
+
+	case CMD_PROCMGR_ATTACH:
+	{
+		struct proc_mgr_cmd_args_attach src_args;
+		struct proc_mgr_attach_params  params;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_attach));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		/* Copy params from user-side. */
+		retval = copy_from_user((void *)&params,
+			(const void *)(src_args.params),
+			sizeof(struct proc_mgr_attach_params));
+		retval = proc_mgr_attach(src_args.handle, &params);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		/* Get memory information. */
+		retval = proc_mgr_get_proc_info(src_args.handle,
+					&(src_args.proc_info));
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(args),
+			(const void *)&src_args,
+			sizeof(struct proc_mgr_cmd_args_attach));
+	}
+	break;
+
+	case CMD_PROCMGR_DETACH:
+	{
+		struct proc_mgr_cmd_args_detach src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_detach));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_detach(src_args.handle);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+	}
+	break;
+
+	case CMD_PROCMGR_GETSTARTPARAMS:
+	{
+		struct proc_mgr_cmd_args_get_start_params src_args;
+		struct proc_mgr_start_params params;
+
+		/* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_get_start_params));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		proc_mgr_get_start_params(src_args.handle, &params);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(src_args.params),
+				(const void *)&params,
+				sizeof(struct proc_mgr_start_params));
+		WARN_ON(retval);
+	}
+	break;
+
+	case CMD_PROCMGR_START:
+	{
+		struct proc_mgr_cmd_args_start  src_args;
+		struct proc_mgr_start_params   params;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc_mgr_cmd_args_start));
+		/* Copy params from user-side. */
+		retval = copy_from_user((void *)&params,
+			(const void *)(src_args.params),
+			sizeof(struct proc_mgr_start_params));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_start(src_args.handle,
+				src_args.entry_point, &params);
+
+		WARN_ON(retval);
+	}
+	break;
+
+	case CMD_PROCMGR_STOP:
+	{
+		struct proc_mgr_cmd_args_stop src_args;
+
+		struct proc_mgr_stop_params   params;
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc_mgr_cmd_args_stop));
+		/* Copy params from user-side. */
+		retval = copy_from_user((void *)&params,
+			(const void *)(src_args.params),
+			sizeof(struct proc_mgr_stop_params));
+
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_stop(src_args.handle, &params);
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_GETSTATE:
+	{
+		struct proc_mgr_cmd_args_get_state src_args;
+		enum proc_mgr_state procmgrstate;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc_mgr_cmd_args_get_state));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		procmgrstate = proc_mgr_get_state(src_args.handle);
+		src_args.proc_mgr_state = procmgrstate;
+		retval = copy_to_user((void *)(args), (const void *)&src_args,
+			sizeof(struct proc_mgr_cmd_args_get_state));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_READ:
+	{
+		struct proc_mgr_cmd_args_read src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc_mgr_cmd_args_read));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_read(src_args.handle,
+			src_args.proc_addr, &(src_args.num_bytes),
+			src_args.buffer);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(args),
+				(const void *)&src_args,
+				sizeof(struct proc_mgr_cmd_args_read));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_WRITE:
+	{
+		struct proc_mgr_cmd_args_write src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc_mgr_cmd_args_write));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_write(src_args.handle,
+			src_args.proc_addr, &(src_args.num_bytes),
+			src_args.buffer);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(args),
+			(const void *)&src_args,
+			sizeof(struct proc_mgr_cmd_args_write));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_CONTROL:
+	{
+		struct proc_mgr_cmd_args_control src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc_mgr_cmd_args_control));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_control(src_args.handle,
+			src_args.cmd, src_args.arg);
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_TRANSLATEADDR:
+	{
+		struct proc_mgr_cmd_args_translate_addr src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_translate_addr));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_translate_addr(src_args.handle,
+			&(src_args.dst_addr), src_args.dst_addr_type,
+			src_args.src_addr, src_args.src_addr_type);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(args),
+			(const void *)&src_args, sizeof
+			(struct proc_mgr_cmd_args_translate_addr));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_MAP:
+	{
+		struct proc_mgr_cmd_args_map src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_map));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_map(src_args.handle,
+				src_args.proc_addr, src_args.size,
+				&(src_args.mapped_addr),
+				&(src_args.mapped_size),
+				src_args.map_attribs);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(args),
+				(const void *)&src_args,
+				sizeof(struct proc_mgr_cmd_args_map));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_UNMAP:
+	{
+		struct proc_mgr_cmd_args_unmap src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_unmap));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_unmap(src_args.handle,
+						(src_args.mapped_addr));
+		WARN_ON(retval < 0);
+	}
+
+	case CMD_PROCMGR_REGISTERNOTIFY:
+	{
+		struct proc_mgr_cmd_args_register_notify src_args;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_register_notify));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_register_notify(src_args.handle,
+				src_args.callback_fxn,
+				src_args.args, src_args.state);
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_GETPROCINFO:
+	{
+		struct proc_mgr_cmd_args_get_proc_info src_args;
+		struct proc_mgr_proc_info proc_info;
+
+		 /* Copy the full args from user-side. */
+		retval = copy_from_user((void *)&src_args,
+		(const void *)(args),
+		sizeof(struct proc_mgr_cmd_args_get_proc_info));
+		if (WARN_ON(retval != 0))
+			goto func_exit;
+		retval = proc_mgr_get_proc_info
+			(src_args.handle, &proc_info);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(src_args.proc_info),
+				(const void *) &proc_info,
+				sizeof(struct proc_mgr_proc_info));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	case CMD_PROCMGR_GETVIRTTOPHYS:
+	{
+		struct proc_mgr_cmd_args_get_virt_to_phys src_args;
+
+		retval = copy_from_user((void *)&src_args,
+			(const void *)(args),
+			sizeof(struct proc_mgr_cmd_args_get_virt_to_phys));
+		retval = proc_mgr_virt_to_phys(src_args.handle,
+					src_args.da, (src_args.mem_entries),
+					src_args.num_of_entries);
+		if (WARN_ON(retval < 0))
+			goto func_exit;
+		retval = copy_to_user((void *)(args), (const void *)&src_args,
+			sizeof(struct proc_mgr_cmd_args_get_virt_to_phys));
+		WARN_ON(retval < 0);
+	}
+	break;
+
+	default:
+		printk(KERN_ERR"PROC_MGR_DRV: WRONG IOCTL !!!!\n");
+		BUG_ON(1);
+	break;
+	}
+func_exit:
+	/* Set the retval and copy the common args to user-side. */
+	command_args.api_status = retval;
+	retval = copy_to_user((void *)cmd_args,
+		(const void *)&command_args, sizeof(struct proc_mgr_cmd_args));
+
+	WARN_ON(retval < 0);
+	return retval;
+}
+
+
+/*
+  Driver function to map memory regions to user space.
+ */
+static int proc_mgr_drv_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot);
+	vma->vm_flags |= VM_RESERVED;
+
+	if (remap_pfn_range(vma,
+			 vma->vm_start,
+			 vma->vm_pgoff,
+			 vma->vm_end - vma->vm_start,
+			 vma->vm_page_prot)) {
+		return -EAGAIN;
+	}
+	return 0;
+}
+
+static int __devinit proc_mgr_probe(struct platform_device *pdev)
+{
+	dev_t dev = 0 ;
+	int retval = -ENOMEM;
+
+	/* Display the version info and created date/time */
+	dev_dbg(&omap_proc_dev->dev, "Entering %s function\n\n", __func__);
+
+	if (driver_major) {
+		dev = MKDEV(driver_major, driver_minor);
+		retval = register_chrdev_region(dev, 1, driver_name);
+	} else {
+		retval = alloc_chrdev_region(&dev, driver_minor, 1,
+				 driver_name);
+		driver_major = MAJOR(dev);
+	}
+
+	procmgr_device = kmalloc(sizeof(struct procmgr_dev), GFP_KERNEL);
+	if (!procmgr_device) {
+		retval = -ENOMEM;
+		unregister_chrdev_region(dev, 1);
+		goto exit;
+	}
+	memset(procmgr_device, 0, sizeof(struct procmgr_dev));
+	cdev_init(&procmgr_device->cdev, &procmgr_fops);
+	procmgr_device->cdev.owner = THIS_MODULE;
+	procmgr_device->cdev.ops = &procmgr_fops;
+
+	retval = cdev_add(&procmgr_device->cdev, dev, 1);
+
+	if (retval) {
+		printk(KERN_ERR "Failed to add the syslink procmgr device\n");
+		goto exit;
+	}
+
+	/* udev support */
+	proc_mgr_class = class_create(THIS_MODULE, "syslink-procmgr");
+
+	if (IS_ERR(proc_mgr_class)) {
+		printk(KERN_ERR "Error creating bridge class\n");
+		goto exit;
+	}
+	device_create(proc_mgr_class, NULL, MKDEV(driver_major, driver_minor),
+			NULL, PROCMGR_NAME);
+
+exit:
+	dev_dbg(&omap_proc_dev->dev, "Leaving %s function\n\n", __func__);
+	return retval;
+}
+
+
+static int __devexit proc_mgr_remove(struct platform_device *pdev)
+{
+	dev_t devno = 0;
+
+	dev_dbg(&omap_proc_dev->dev, "Entering %s function\n", __func__);
+	devno = MKDEV(driver_major, driver_minor);
+	if (procmgr_device) {
+		cdev_del(&procmgr_device->cdev);
+		kfree(procmgr_device);
+	}
+	unregister_chrdev_region(devno, 1);
+	if (proc_mgr_class) {
+		/* remove the device from sysfs */
+		device_destroy(proc_mgr_class, MKDEV(driver_major,
+						driver_minor));
+		class_destroy(proc_mgr_class);
+	}
+	dev_dbg(&omap_proc_dev->dev, "Entering %s function\n", __func__);
+	return 0;
+}
+
+/*
+* Module initialization  function for Linux driver.
+ */
+static int __init proc_mgr_drv_initialize_module(void)
+{
+	int retval = -ENOMEM;
+
+	procmgr_pdev = platform_device_alloc(PROCMGR_NAME, -1);
+	if (!procmgr_pdev) {
+		printk(KERN_ERR "%s:device allocation failed\n", __func__);
+		return -ENOMEM;
+	}
+	retval = platform_device_add(procmgr_pdev);
+	if (retval)
+		goto err_out;
+
+	/*Saving the context for future use*/
+	omap_proc_dev = procmgr_pdev;
+
+	retval = platform_driver_register(&procmgr_driver);
+	if (!retval)
+		return retval;
+err_out:
+	platform_device_put(procmgr_pdev);
+	return retval;
+}
+
+/*
+* driver function to finalize the driver module.
+ */
+static void __exit proc_mgr_drv_finalize_module(void)
+{
+
+	dev_dbg(&omap_proc_dev->dev, "Entering %s function\n", __func__);
+	platform_device_unregister(procmgr_pdev);
+	platform_driver_unregister(&procmgr_driver);
+	dev_dbg(&omap_proc_dev->dev, "Leaving %s function\n", __func__);
+}
+
+/*
+* brief  Macro calls that indicate initialization and finalization functions
+ *	to the kernel.
+ */
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Mugdha Kamoolkar");
+module_init(proc_mgr_drv_initialize_module);
+module_exit(proc_mgr_drv_finalize_module);
diff --git a/drivers/dsp/syslink/procmgr/procmgr_drvdefs.h b/drivers/dsp/syslink/procmgr/procmgr_drvdefs.h
new file mode 100644
index 000000000000..2be14bf7a20e
--- /dev/null
+++ b/drivers/dsp/syslink/procmgr/procmgr_drvdefs.h
@@ -0,0 +1,541 @@
+/*
+ * procmgr_drvdefs.h
+ *
+ * Syslink driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef SYSLINK_PROCMGR_DRVDEFS_H
+#define SYSLINK_PROCMGR_DRVDEFS_H
+
+#include <linux/types.h>
+
+/* Module headers */
+#include <procmgr.h>
+
+
+/* =================================
+ *  Macros and types
+ * =================================
+ */
+/*
+ * Base structure for ProcMgr command args. This needs to be the first
+ *  field in all command args structures.
+ */
+struct proc_mgr_cmd_args {
+	int api_status;
+	/*Status of the API being called. */
+};
+
+/*  --------------------------------------
+ *  IOCTL command IDs for ProcMgr
+ *  ---------------------------------------
+ */
+/*
+ * Base command ID for ProcMgr
+ */
+#define PROCMGR_BASE_CMD			0x100
+
+/*
+ * Command for ProcMgr_getConfig
+ */
+#define CMD_PROCMGR_GETCONFIG		(PROCMGR_BASE_CMD + 1)
+
+/*
+ * Command for ProcMgr_setup
+ */
+#define CMD_PROCMGR_SETUP			(PROCMGR_BASE_CMD + 2)
+
+/*
+ * Command for ProcMgr_setup
+ */
+#define CMD_PROCMGR_DESTROY			(PROCMGR_BASE_CMD + 3)
+
+/*
+ * Command for ProcMgr_destroy
+ */
+#define CMD_PROCMGR_PARAMS_INIT		(PROCMGR_BASE_CMD + 4)
+
+/*
+ * Command for ProcMgr_create
+ */
+#define CMD_PROCMGR_CREATE			(PROCMGR_BASE_CMD + 5)
+
+/*
+ * Command for ProcMgr_delete
+ */
+#define CMD_PROCMGR_DELETE			(PROCMGR_BASE_CMD + 6)
+
+/*
+ * Command for ProcMgr_open
+ */
+#define CMD_PROCMGR_OPEN			(PROCMGR_BASE_CMD + 7)
+
+/*
+ * Command for ProcMgr_close
+ */
+#define CMD_PROCMGR_CLOSE			(PROCMGR_BASE_CMD + 8)
+
+/*
+ * Command for ProcMgr_getAttachParams
+ */
+#define CMD_PROCMGR_GETATTACHPARAMS		(PROCMGR_BASE_CMD + 9)
+
+/*
+ * Command for ProcMgr_attach
+ */
+#define CMD_PROCMGR_ATTACH			(PROCMGR_BASE_CMD + 10)
+
+/*
+ * Command for ProcMgr_detach
+ */
+#define CMD_PROCMGR_DETACH			(PROCMGR_BASE_CMD + 11)
+
+/*
+ * Command for ProcMgr_load
+ */
+#define CMD_PROCMGR_LOAD			(PROCMGR_BASE_CMD + 12)
+
+/*
+ * Command for ProcMgr_unload
+ */
+#define CMD_PROCMGR_UNLOAD			(PROCMGR_BASE_CMD + 13)
+
+/*
+ * Command for ProcMgr_getStartParams
+ */
+#define CMD_PROCMGR_GETSTARTPARAMS		(PROCMGR_BASE_CMD + 14)
+
+/*
+ * Command for ProcMgr_start
+ */
+#define CMD_PROCMGR_START			(PROCMGR_BASE_CMD + 15)
+
+/*
+ * Command for ProcMgr_stop
+ */
+#define CMD_PROCMGR_STOP			(PROCMGR_BASE_CMD + 16)
+
+/*
+ * Command for ProcMgr_getState
+ */
+#define CMD_PROCMGR_GETSTATE			(PROCMGR_BASE_CMD + 17)
+
+/*
+ * Command for ProcMgr_read
+ */
+#define CMD_PROCMGR_READ			(PROCMGR_BASE_CMD + 18)
+
+/*
+ * Command for ProcMgr_write
+ */
+#define CMD_PROCMGR_WRITE			(PROCMGR_BASE_CMD + 19)
+
+/*
+ * Command for ProcMgr_control
+ */
+#define CMD_PROCMGR_CONTROL			(PROCMGR_BASE_CMD + 20)
+
+/*
+ * Command for ProcMgr_translateAddr
+ */
+#define CMD_PROCMGR_TRANSLATEADDR		(PROCMGR_BASE_CMD + 22)
+
+/*
+ * Command for ProcMgr_getSymbolAddress
+ */
+#define CMD_PROCMGR_GETSYMBOLADDRESS		(PROCMGR_BASE_CMD + 23)
+
+/*
+ * Command for ProcMgr_map
+ */
+#define CMD_PROCMGR_MAP				(PROCMGR_BASE_CMD + 24)
+
+/*
+ * Command for ProcMgr_registerNotify
+ */
+#define CMD_PROCMGR_REGISTERNOTIFY		(PROCMGR_BASE_CMD + 25)
+
+/*
+ * Command for ProcMgr_getProcInfo
+ */
+#define CMD_PROCMGR_GETPROCINFO			(PROCMGR_BASE_CMD + 26)
+
+/*
+ * Command for ProcMgr_unmap
+ */
+#define CMD_PROCMGR_UNMAP			(PROCMGR_BASE_CMD + 27)
+
+/*
+ * Command for ProcMgr_getVirtToPhysPages
+ */
+#define CMD_PROCMGR_GETVIRTTOPHYS		(PROCMGR_BASE_CMD + 28)
+
+
+
+
+/*  ----------------------------------------------------------------------------
+ *  Command arguments for ProcMgr
+ *  ----------------------------------------------------------------------------
+ */
+/*
+ * Command arguments for ProcMgr_getConfig
+ */
+struct proc_mgr_cmd_args_get_config {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	struct proc_mgr_config *cfg;
+	/*Pointer to the ProcMgr module configuration structure in which the
+	 default config is to be returned. */
+};
+
+/*
+ * Command arguments for ProcMgr_setup
+ */
+struct proc_mgr_cmd_args_setup {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	struct proc_mgr_config *cfg;
+	/*Optional ProcMgr module configuration. If provided as NULL, default
+	 configuration is used. */
+};
+
+/*
+ * Command arguments for ProcMgr_destroy
+ */
+struct proc_mgr_cmd_args_destroy {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+};
+
+/*
+ * Command arguments for ProcMgr_Params_init
+ */
+struct proc_mgr_cmd_args_params_init {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object. */
+	struct proc_mgr_params *params;
+	/*Pointer to the ProcMgr instance params structure in which the default
+	 params is to be returned. */
+};
+
+/*
+ * Command arguments for ProcMgr_create
+ */
+struct proc_mgr_cmd_args_create {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	u16 proc_id;
+	/*Processor ID represented by this ProcMgr instance */
+	struct proc_mgr_params  params;
+	/*ProcMgr instance configuration parameters. */
+	void *handle;
+	/*Handle to the created ProcMgr object */
+};
+
+/*
+ * Command arguments for ProcMgr_delete
+ */
+struct proc_mgr_cmd_args_delete{
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Pointer to Handle to the ProcMgr object */
+};
+
+/*
+ * Command arguments for ProcMgr_open
+ */
+struct proc_mgr_cmd_args_open {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	u16 proc_id;
+	/*Processor ID represented by this ProcMgr instance */
+	void *handle;
+	/*Handle to the opened ProcMgr object. */
+	struct proc_mgr_proc_info proc_info;
+	/*Processor information.  */
+};
+
+/*
+ * Command arguments for ProcMgr_close
+ */
+struct proc_mgr_cmd_args_close{
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	struct proc_mgr_proc_info proc_info;
+	/*Processor information.  */
+};
+
+/*
+ * Command arguments for ProcMgr_getAttachParams
+ */
+struct proc_mgr_cmd_args_get_attach_params{
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object. */
+	struct proc_mgr_attach_params *params;
+	/*Pointer to the ProcMgr attach params structure in which the default
+	 params is to be returned. */
+};
+
+/*
+ * Command arguments for ProcMgr_attach
+ */
+struct proc_mgr_cmd_args_attach {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object. */
+	struct proc_mgr_attach_params *params;
+	/*Optional ProcMgr attach parameters.  */
+	struct proc_mgr_proc_info proc_info;
+	/*Processor information.  */
+};
+
+/*
+ * Command arguments for ProcMgr_detach
+ */
+struct proc_mgr_cmd_args_detach {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	struct proc_mgr_proc_info proc_info;
+	/*Processor information.  */
+};
+
+
+/*
+ * Command arguments for ProcMgr_getStartParams
+ */
+struct proc_mgr_cmd_args_get_start_params {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Entry point for the image*/
+	u32 entry_point;
+	/*Handle to the ProcMgr object */
+	struct proc_mgr_start_params *params;
+	/*Pointer to the ProcMgr start params structure in which the default
+	 params is to be returned. */
+};
+
+/*
+ * Command arguments for ProcMgr_start
+ */
+struct proc_mgr_cmd_args_start {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Entry point for the image*/
+	u32 entry_point;
+	/*Handle to the ProcMgr object */
+	struct proc_mgr_start_params *params;
+	/*Optional ProcMgr start parameters. */
+};
+
+/*
+ * Command arguments for ProcMgr_stop
+ */
+struct proc_mgr_cmd_args_stop {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	struct proc_mgr_stop_params *params;
+	/*Optional ProcMgr stop parameters. */
+};
+
+/*
+ * Command arguments for ProcMgr_getState
+ */
+struct proc_mgr_cmd_args_get_state {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/* Handle to the ProcMgr object */
+	enum proc_mgr_state proc_mgr_state;
+	/*Current state of the ProcMgr object. */
+};
+
+/*
+ * Command arguments for ProcMgr_read
+ */
+struct proc_mgr_cmd_args_read {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	u32 proc_addr;
+	/*Address in space processor's address space of the memory region to
+	 read from. */
+	u32 num_bytes;
+	/*IN/OUT parameter. As an IN-parameter, it takes in the number of bytes
+	 to be read. When the function returns, this parameter contains the
+	 number of bytes actually read. */
+	void *buffer;
+	/*User-provided buffer in which the slave processor's memory contents
+	 are to be copied. */
+};
+
+/*
+ * Command arguments for ProcMgr_write
+ */
+struct proc_mgr_cmd_args_write {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	u32 proc_addr;
+	/*Address in space processor's address space of the memory region to
+	 write into. */
+	u32 num_bytes;
+	/*IN/OUT parameter. As an IN-parameter, it takes in the number of bytes
+	 to be written. When the function returns, this parameter contains the
+	 number of bytes actually written. */
+	void *buffer;
+	/*User-provided buffer from which the data is to be written into the
+	 slave processor's memory. */
+};
+
+/*
+ * Command arguments for ProcMgr_control
+ */
+struct proc_mgr_cmd_args_control {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	int cmd;
+	/*Device specific processor command */
+	void *arg;
+	/*Arguments specific to the type of command. */
+};
+
+/*
+ * Command arguments for ProcMgr_translateAddr
+ */
+struct proc_mgr_cmd_args_translate_addr {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	void *dst_addr;
+	/*Return parameter: Pointer to receive the translated address. */
+	enum proc_mgr_addr_type dst_addr_type;
+	/*Destination address type requested */
+	void *src_addr;
+	/*Source address in the source address space */
+	enum proc_mgr_addr_type src_addr_type;
+	/*Source address type */
+};
+
+/*
+ * Command arguments for ProcMgr_getSymbolAddress
+ */
+struct proc_mgr_cmd_args_get_symbol_address {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	u32 file_id;
+	/*ID of the file received from the load function */
+	char *symbol_name;
+	/*Name of the symbol */
+	u32 sym_value;
+	/*Return parameter: Symbol address */
+};
+
+/*
+ * Command arguments for ProcMgr_map
+ */
+struct proc_mgr_cmd_args_map {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	u32 proc_addr;
+	/*Slave address to be mapped */
+	u32 size;
+	/*Size (in bytes) of region to be mapped */
+	u32 mapped_addr;
+	/*Return parameter: Mapped address in host address space */
+	u32 mapped_size;
+	/*Return parameter: Mapped size */
+	u32 map_attribs;
+	/*Type of mapping. */
+};
+
+/*
+ * Command arguments for ProcMgr_map
+ */
+struct proc_mgr_cmd_args_unmap {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	u32 mapped_addr;
+	/* Mapped address in host address space */
+};
+
+/*
+ * Command arguments for ProcMgr_registerNotify
+ */
+struct proc_mgr_cmd_args_register_notify {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	int (*callback_fxn)(u16 proc_id, void *handle,
+		enum proc_mgr_state from_state, enum proc_mgr_state to_state);
+	/*Handling function to be registered. */
+	void *args;
+	/*Optional arguments associated with the handler fxn. */
+	enum proc_mgr_state state[];
+	/*Array of target states for which registration is required. */
+};
+
+/*
+ * Command arguments for ProcMgr_getProcInfo
+ */
+struct proc_mgr_cmd_args_get_proc_info {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	/*Handle to the ProcMgr object */
+	struct proc_mgr_proc_info *proc_info;
+	/*Pointer to the ProcInfo object to be populated. */
+};
+
+/*
+ * Command arguments for ProcMgr_virtToPhys
+ */
+struct proc_mgr_cmd_args_get_virt_to_phys {
+	struct proc_mgr_cmd_args commond_args;
+	/*Common command args */
+	void *handle;
+	u32 da;
+	/* mem entries buffer */
+	u32 *mem_entries;
+	/* number of entries */
+	u32 num_of_entries;
+};
+
+#endif
+
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 043ee8dd871b..043ee8dd871b 100755..100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
diff --git a/drivers/input/misc/sfh7741.c b/drivers/input/misc/sfh7741.c
index a1aba9edd0e9..a1aba9edd0e9 100755..100644
--- a/drivers/input/misc/sfh7741.c
+++ b/drivers/input/misc/sfh7741.c
diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig
index a28541b2b1a2..3872c958bcef 100644
--- a/drivers/media/Kconfig
+++ b/drivers/media/Kconfig
@@ -143,4 +143,8 @@ config USB_DABUSB
 	  module will be called dabusb.
 endif # DAB
 
+source "drivers/media/video/dmm/Kconfig"
+
+source "drivers/media/video/tiler/Kconfig"
+
 endif # MEDIA_SUPPORT
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 9644cf760aaa..39af9315dff5 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -613,6 +613,8 @@ config VIDEO_ISIF
 	   To compile this driver as a module, choose M here: the
 	   module will be called vpfe.
 
+source "drivers/media/video/omap/Kconfig"
+
 source "drivers/media/video/bt8xx/Kconfig"
 
 config VIDEO_PMS
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index c51c386559f2..5b20a26d81a0 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -167,7 +167,10 @@ obj-$(CONFIG_VIDEO_SAA7164)     += saa7164/
 
 obj-$(CONFIG_VIDEO_IR_I2C)  += ir-kbd-i2c.o
 
-obj-$(CONFIG_ARCH_DAVINCI)	+= davinci/
+obj-$(CONFIG_DMM_OMAP)  += dmm/
+obj-$(CONFIG_TILER_OMAP)  += tiler/
+
+obj-$(CONFIG_ARCH_OMAP)	+= omap/
 
 EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
 EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
diff --git a/drivers/media/video/dmm/Kconfig b/drivers/media/video/dmm/Kconfig
new file mode 100644
index 000000000000..4af47ea0aef6
--- /dev/null
+++ b/drivers/media/video/dmm/Kconfig
@@ -0,0 +1,6 @@
+config DMM_OMAP
+	tristate "OMAP DMM support"
+	default y
+	help
+           DMM driver for OMAP based boards.
+
diff --git a/drivers/media/video/dmm/Makefile b/drivers/media/video/dmm/Makefile
new file mode 100644
index 000000000000..494e70569aab
--- /dev/null
+++ b/drivers/media/video/dmm/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_DMM_OMAP) += dmm_omap.o
+dmm_omap-objs = dmm.o tmm_pat.o
+
diff --git a/drivers/media/video/dmm/dmm.c b/drivers/media/video/dmm/dmm.c
new file mode 100644
index 000000000000..8663b36a5e72
--- /dev/null
+++ b/drivers/media/video/dmm/dmm.c
@@ -0,0 +1,335 @@
+/*
+ * dmm.c
+ *
+ * DMM driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cdev.h>            /* struct cdev */
+#include <linux/kdev_t.h>          /* MKDEV() */
+#include <linux/fs.h>              /* register_chrdev_region() */
+#include <linux/device.h>          /* struct class */
+#include <linux/platform_device.h> /* platform_device() */
+#include <linux/err.h>             /* IS_ERR() */
+#include <linux/io.h>              /* ioremap() */
+#include <linux/errno.h>
+#include <linux/slab.h>
+
+#include <mach/dmm.h>
+
+#undef __DEBUG__
+#define BITS_32(in_NbBits) ((((u32)1 << in_NbBits) - 1) | ((u32)1 << in_NbBits))
+#define BITFIELD_32(in_UpBit, in_LowBit)\
+	(BITS_32(in_UpBit) & ~((BITS_32(in_LowBit)) >> 1))
+#define BF BITFIELD_32
+
+#ifdef __DEBUG__
+#define DEBUG(x, y) printk(KERN_NOTICE "%s()::%d:%s=(0x%08x)\n", \
+				__func__, __LINE__, x, (s32)y);
+#else
+#define DEBUG(x, y)
+#endif
+
+static s32 dmm_major;
+static s32 dmm_minor;
+
+struct dmm_dev {
+	struct cdev cdev;
+};
+
+static struct dmm_dev *dmm_device;
+static struct class *dmmdev_class;
+
+static struct platform_driver dmm_driver_ldm = {
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "dmm",
+	},
+	.probe = NULL,
+	.shutdown = NULL,
+	.remove = NULL,
+};
+
+s32 dmm_pat_refill(struct dmm *dmm, struct pat *pd, enum pat_mode mode)
+{
+	void __iomem *r = NULL;
+	u32 v = -1, w = -1;
+
+	/* Only manual refill supported */
+	if (mode != MANUAL)
+		return -EFAULT;
+
+	/*
+	 * Check that the DMM_PAT_STATUS register
+	 * has not reported an error.
+	*/
+	r = (void __iomem *)((u32)dmm->base | DMM_PAT_STATUS__0);
+	v = __raw_readl(r);
+	if ((v & 0xFC00) != 0) {
+		while (1)
+			printk(KERN_ERR "dmm_pat_refill() error.\n");
+	}
+
+	/* Set "next" register to NULL */
+	r = (void __iomem *)((u32)dmm->base | DMM_PAT_DESCR__0);
+	v = __raw_readl(r);
+	w = (v & (~(BF(31, 4)))) | ((((u32)NULL) << 4) & BF(31, 4));
+	__raw_writel(w, r);
+
+	/* Set area to be refilled */
+	r = (void __iomem *)((u32)dmm->base | DMM_PAT_AREA__0);
+	v = __raw_readl(r);
+	w = (v & (~(BF(30, 24)))) | ((((s8)pd->area.y1) << 24) & BF(30, 24));
+	__raw_writel(w, r);
+
+	v = __raw_readl(r);
+	w = (v & (~(BF(23, 16)))) | ((((s8)pd->area.x1) << 16) & BF(23, 16));
+	__raw_writel(w, r);
+
+	v = __raw_readl(r);
+	w = (v & (~(BF(14, 8)))) | ((((s8)pd->area.y0) << 8) & BF(14, 8));
+	__raw_writel(w, r);
+
+	v = __raw_readl(r);
+	w = (v & (~(BF(7, 0)))) | ((((s8)pd->area.x0) << 0) & BF(7, 0));
+	__raw_writel(w, r);
+	wmb();
+
+#ifdef __DEBUG__
+	printk(KERN_NOTICE "\nx0=(%d),y0=(%d),x1=(%d),y1=(%d)\n",
+						(char)pd->area.x0,
+						(char)pd->area.y0,
+						(char)pd->area.x1,
+						(char)pd->area.y1);
+#endif
+
+	/* First, clear the DMM_PAT_IRQSTATUS register */
+	r = (void __iomem *)((u32)dmm->base | (u32)DMM_PAT_IRQSTATUS);
+	__raw_writel(0xFFFFFFFF, r);
+	wmb();
+
+	r = (void __iomem *)((u32)dmm->base | (u32)DMM_PAT_IRQSTATUS_RAW);
+	v = 0xFFFFFFFF;
+
+	while (v != 0x0) {
+		v = __raw_readl(r);
+		DEBUG("DMM_PAT_IRQSTATUS_RAW", v);
+	}
+
+	/* Fill data register */
+	r = (void __iomem *)((u32)dmm->base | DMM_PAT_DATA__0);
+	v = __raw_readl(r);
+
+	/* Apply 4 bit left shft to counter the 4 bit right shift */
+	w = (v & (~(BF(31, 4)))) | ((((u32)(pd->data >> 4)) << 4) & BF(31, 4));
+	__raw_writel(w, r);
+	wmb();
+
+	/* Read back PAT_DATA__0 to see if write was successful */
+	v = 0x0;
+	while (v != pd->data) {
+		v = __raw_readl(r);
+		DEBUG("DMM_PAT_DATA__0", v);
+	}
+
+	r = (void __iomem *)((u32)dmm->base | (u32)DMM_PAT_CTRL__0);
+	v = __raw_readl(r);
+
+	w = (v & (~(BF(31, 28)))) | ((((u32)pd->ctrl.ini) << 28) & BF(31, 28));
+	__raw_writel(w, r);
+
+	v = __raw_readl(r);
+	w = (v & (~(BF(16, 16)))) | ((((u32)pd->ctrl.sync) << 16) & BF(16, 16));
+	__raw_writel(w, r);
+
+	v = __raw_readl(r);
+	w = (v & (~(BF(9, 8)))) | ((((u32)pd->ctrl.lut_id) << 8) & BF(9, 8));
+	__raw_writel(w, r);
+
+	v = __raw_readl(r);
+	w = (v & (~(BF(6, 4)))) | ((((u32)pd->ctrl.dir) << 4) & BF(6, 4));
+	__raw_writel(w, r);
+
+	v = __raw_readl(r);
+	w = (v & (~(BF(0, 0)))) | ((((u32)pd->ctrl.start) << 0) & BF(0, 0));
+	__raw_writel(w, r);
+	wmb();
+
+	/*
+	 * Now, check if PAT_IRQSTATUS_RAW has been
+	 * set after the PAT has been refilled
+	 */
+	r = (void __iomem *)((u32)dmm->base | (u32)DMM_PAT_IRQSTATUS_RAW);
+	v = 0x0;
+	while ((v & 0x3) != 0x3) {
+		v = __raw_readl(r);
+		DEBUG("DMM_PAT_IRQSTATUS_RAW", v);
+	}
+
+	/* Again, clear the DMM_PAT_IRQSTATUS register */
+	r = (void __iomem *)((u32)dmm->base | (u32)DMM_PAT_IRQSTATUS);
+	__raw_writel(0xFFFFFFFF, r);
+	wmb();
+
+	r = (void __iomem *)((u32)dmm->base | (u32)DMM_PAT_IRQSTATUS_RAW);
+	v = 0xFFFFFFFF;
+
+	while (v != 0x0) {
+		v = __raw_readl(r);
+		DEBUG("DMM_PAT_IRQSTATUS_RAW", v);
+	}
+
+	/* Again, set "next" register to NULL to clear any PAT STATUS errors */
+	r = (void __iomem *)((u32)dmm->base | DMM_PAT_DESCR__0);
+	v = __raw_readl(r);
+	w = (v & (~(BF(31, 4)))) | ((((u32)NULL) << 4) & BF(31, 4));
+	__raw_writel(w, r);
+
+	/*
+	 * Now, check that the DMM_PAT_STATUS register
+	 * has not reported an error before exiting.
+	*/
+	r = (void __iomem *)((u32)dmm->base | DMM_PAT_STATUS__0);
+	v = __raw_readl(r);
+	if ((v & 0xFC00) != 0) {
+		while (1)
+			printk(KERN_ERR "dmm_pat_refill() error.\n");
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(dmm_pat_refill);
+
+static s32 dmm_open(struct inode *ip, struct file *filp)
+{
+	return 0;
+}
+
+static s32 dmm_release(struct inode *ip, struct file *filp)
+{
+	return 0;
+}
+
+static const struct file_operations dmm_fops = {
+	.open    = dmm_open,
+	.release = dmm_release,
+};
+
+struct dmm *dmm_pat_init(u32 id)
+{
+	u32 base = 0;
+	struct dmm *dmm = NULL;
+	switch (id) {
+	case 0:
+		/* only support id 0 for now */
+		base = DMM_BASE;
+		break;
+	default:
+		return NULL;
+	}
+
+	dmm = kmalloc(sizeof(*dmm), GFP_KERNEL);
+	if (!dmm)
+		return NULL;
+
+	dmm->base = ioremap(base, DMM_SIZE);
+	if (!dmm->base) {
+		kfree(dmm);
+		return NULL;
+	}
+
+	__raw_writel(0x88888888, dmm->base + DMM_PAT_VIEW__0);
+	__raw_writel(0x88888888, dmm->base + DMM_PAT_VIEW__1);
+	__raw_writel(0x80808080, dmm->base + DMM_PAT_VIEW_MAP__0);
+	__raw_writel(0x80000000, dmm->base + DMM_PAT_VIEW_MAP_BASE);
+	__raw_writel(0x88888888, dmm->base + DMM_TILER_OR__0);
+	__raw_writel(0x88888888, dmm->base + DMM_TILER_OR__1);
+
+	return dmm;
+}
+EXPORT_SYMBOL(dmm_pat_init);
+
+/**
+ * Clean up the physical address translator.
+ * @param dmm    Device data
+ * @return an error status.
+ */
+void dmm_pat_release(struct dmm *dmm)
+{
+	if (dmm) {
+		iounmap(dmm->base);
+		kfree(dmm);
+	}
+}
+EXPORT_SYMBOL(dmm_pat_release);
+
+static s32 __init dmm_init(void)
+{
+	dev_t dev  = 0;
+	s32 r = -1;
+	struct device *device = NULL;
+
+	if (dmm_major) {
+		dev = MKDEV(dmm_major, dmm_minor);
+		r = register_chrdev_region(dev, 1, "dmm");
+	} else {
+		r = alloc_chrdev_region(&dev, dmm_minor, 1, "dmm");
+		dmm_major = MAJOR(dev);
+	}
+
+	dmm_device = kmalloc(sizeof(*dmm_device), GFP_KERNEL);
+	if (!dmm_device) {
+		unregister_chrdev_region(dev, 1);
+		return -ENOMEM;
+	}
+	memset(dmm_device, 0x0, sizeof(struct dmm_dev));
+
+	cdev_init(&dmm_device->cdev, &dmm_fops);
+	dmm_device->cdev.owner = THIS_MODULE;
+	dmm_device->cdev.ops = &dmm_fops;
+
+	r = cdev_add(&dmm_device->cdev, dev, 1);
+	if (r)
+		printk(KERN_ERR "cdev_add():failed\n");
+
+	dmmdev_class = class_create(THIS_MODULE, "dmm");
+
+	if (IS_ERR(dmmdev_class)) {
+		printk(KERN_ERR "class_create():failed\n");
+		goto EXIT;
+	}
+
+	device = device_create(dmmdev_class, NULL, dev, NULL, "dmm");
+	if (device == NULL)
+		printk(KERN_ERR "device_create() fail\n");
+
+	r = platform_driver_register(&dmm_driver_ldm);
+
+EXIT:
+	return r;
+}
+
+static void __exit dmm_exit(void)
+{
+	platform_driver_unregister(&dmm_driver_ldm);
+	cdev_del(&dmm_device->cdev);
+	kfree(dmm_device);
+	device_destroy(dmmdev_class, MKDEV(dmm_major, dmm_minor));
+	class_destroy(dmmdev_class);
+}
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("davidsin@ti.com");
+module_init(dmm_init);
+module_exit(dmm_exit);
diff --git a/drivers/media/video/dmm/tmm.h b/drivers/media/video/dmm/tmm.h
new file mode 100644
index 000000000000..deaeca51a905
--- /dev/null
+++ b/drivers/media/video/dmm/tmm.h
@@ -0,0 +1,107 @@
+/*
+ * tmm.h
+ *
+ * TMM interface definition for TI TILER.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef TMM_H
+#define TMM_H
+
+#include <mach/dmm.h>
+/**
+ * TMM interface
+ */
+struct tmm {
+	void *pvt;
+
+	/* function table */
+	u32 *(*get)    (struct tmm *tmm, s32 num_pages);
+	void (*free)   (struct tmm *tmm, u32 *pages);
+	s32  (*map)    (struct tmm *tmm, struct pat_area area, u32 page_pa);
+	void (*clear)  (struct tmm *tmm, struct pat_area area);
+	void (*deinit) (struct tmm *tmm);
+};
+
+/**
+ * Request a set of pages from the DMM free page stack.
+ * @return a pointer to a list of physical page addresses.
+ */
+static inline
+u32 *tmm_get(struct tmm *tmm, s32 num_pages)
+{
+	if (tmm && tmm->pvt)
+		return tmm->get(tmm, num_pages);
+	return NULL;
+}
+
+/**
+ * Return a set of used pages to the DMM free page stack.
+ * @param list a pointer to a list of physical page addresses.
+ */
+static inline
+void tmm_free(struct tmm *tmm, u32 *pages)
+{
+	if (tmm && tmm->pvt)
+		tmm->free(tmm, pages);
+}
+
+/**
+ * Program the physical address translator.
+ * @param area PAT area
+ * @param list of pages
+ */
+static inline
+s32 tmm_map(struct tmm *tmm, struct pat_area area, u32 page_pa)
+{
+	if (tmm && tmm->map && tmm->pvt)
+		return tmm->map(tmm, area, page_pa);
+	return -ENODEV;
+}
+
+/**
+ * Clears the physical address translator.
+ * @param area PAT area
+ */
+static inline
+void tmm_clear(struct tmm *tmm, struct pat_area area)
+{
+	if (tmm && tmm->clear && tmm->pvt)
+		tmm->clear(tmm, area);
+}
+
+/**
+ * Checks whether tiler memory manager supports mapping
+ */
+static inline
+bool tmm_can_map(struct tmm *tmm)
+{
+	return tmm && tmm->map;
+}
+
+/**
+ * Deinitialize tiler memory manager
+ */
+static inline
+void tmm_deinit(struct tmm *tmm)
+{
+	if (tmm && tmm->pvt)
+		tmm->deinit(tmm);
+}
+
+/**
+ * TMM implementation for PAT support.
+ *
+ * Initialize TMM for PAT with given id.
+ */
+struct tmm *tmm_pat_init(u32 pat_id);
+
+#endif
diff --git a/drivers/media/video/dmm/tmm_pat.c b/drivers/media/video/dmm/tmm_pat.c
new file mode 100644
index 000000000000..6374fac49169
--- /dev/null
+++ b/drivers/media/video/dmm/tmm_pat.c
@@ -0,0 +1,331 @@
+/*
+ * tmm_pat.c
+ *
+ * DMM driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/mmzone.h>
+#include <asm/cacheflush.h>
+#include <linux/mutex.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+
+#include "tmm.h"
+
+/**
+ * Number of pages to allocate when
+ * refilling the free page stack.
+ */
+#define MAX 16
+#define DMM_PAGE 0x1000
+
+/* Max pages in free page stack */
+#define PAGE_CAP (256 * 40)
+
+/* Number of pages currently allocated */
+static unsigned long count;
+
+/**
+  * Used to keep track of mem per
+  * dmm_get_pages call.
+  */
+struct fast {
+	struct list_head list;
+	struct mem **mem;
+	u32 *pa;
+	u32 num;
+};
+
+/**
+ * Used to keep track of the page struct ptrs
+ * and physical addresses of each page.
+ */
+struct mem {
+	struct list_head list;
+	struct page *pg;
+	u32 pa;
+};
+
+/**
+ * TMM PAT private structure
+ */
+struct dmm_mem {
+	struct fast fast_list;
+	struct mem free_list;
+	struct mem used_list;
+	struct mutex mtx;
+	struct dmm *dmm;
+};
+
+static void dmm_free_fast_list(struct fast *fast)
+{
+	struct list_head *pos = NULL, *q = NULL;
+	struct fast *f = NULL;
+	s32 i = 0;
+
+	/* mutex is locked */
+	list_for_each_safe(pos, q, &fast->list) {
+		f = list_entry(pos, struct fast, list);
+		for (i = 0; i < f->num; i++)
+			__free_page(f->mem[i]->pg);
+		kfree(f->pa);
+		kfree(f->mem);
+		list_del(pos);
+		kfree(f);
+	}
+}
+
+static u32 fill_page_stack(struct mem *mem, struct mutex *mtx)
+{
+	s32 i = 0;
+	struct mem *m = NULL;
+
+	for (i = 0; i < MAX; i++) {
+		m = kmalloc(sizeof(*m), GFP_KERNEL);
+		if (!m)
+			return -ENOMEM;
+		memset(m, 0x0, sizeof(*m));
+
+		m->pg = alloc_page(GFP_KERNEL | GFP_DMA);
+		if (!m->pg) {
+			kfree(m);
+			return -ENOMEM;
+		}
+
+		m->pa = page_to_phys(m->pg);
+
+		/**
+		 * Note: we need to flush the cache
+		 * entry for each page we allocate.
+		*/
+		dmac_flush_range((void *)page_address(m->pg),
+					(void *)page_address(m->pg) + DMM_PAGE);
+		outer_flush_range(m->pa, m->pa + DMM_PAGE);
+
+		mutex_lock(mtx);
+		count++;
+		list_add(&m->list, &mem->list);
+		mutex_unlock(mtx);
+	}
+	return 0x0;
+}
+
+static void dmm_free_page_stack(struct mem *mem)
+{
+	struct list_head *pos = NULL, *q = NULL;
+	struct mem *m = NULL;
+
+	/* mutex is locked */
+	list_for_each_safe(pos, q, &mem->list) {
+		m = list_entry(pos, struct mem, list);
+		__free_page(m->pg);
+		list_del(pos);
+		kfree(m);
+	}
+}
+
+static void tmm_pat_deinit(struct tmm *tmm)
+{
+	struct dmm_mem *pvt = (struct dmm_mem *) tmm->pvt;
+
+	mutex_lock(&pvt->mtx);
+	dmm_free_fast_list(&pvt->fast_list);
+	dmm_free_page_stack(&pvt->free_list);
+	dmm_free_page_stack(&pvt->used_list);
+	mutex_destroy(&pvt->mtx);
+}
+
+static u32 *tmm_pat_get_pages(struct tmm *tmm, s32 n)
+{
+	s32 i = 0;
+	struct list_head *pos = NULL, *q = NULL;
+	struct mem *m = NULL;
+	struct fast *f = NULL;
+	struct dmm_mem *pvt = (struct dmm_mem *) tmm->pvt;
+
+	if (n <= 0 || n > 0x8000)
+		return NULL;
+
+	if (list_empty_careful(&pvt->free_list.list))
+		if (fill_page_stack(&pvt->free_list, &pvt->mtx))
+			return NULL;
+
+	f = kmalloc(sizeof(*f), GFP_KERNEL);
+	if (!f)
+		return NULL;
+	memset(f, 0x0, sizeof(*f));
+
+	/* array of mem struct pointers */
+	f->mem = kmalloc(n * sizeof(*f->mem), GFP_KERNEL);
+	if (!f->mem) {
+		kfree(f); return NULL;
+	}
+	memset(f->mem, 0x0, n * sizeof(*f->mem));
+
+	/* array of physical addresses */
+	f->pa = kmalloc(n * sizeof(*f->pa), GFP_KERNEL);
+	if (!f->pa) {
+		kfree(f->mem); kfree(f); return NULL;
+	}
+	memset(f->pa, 0x0, n * sizeof(*f->pa));
+
+	/*
+	 * store the number of mem structs so that we
+	 * know how many to free later.
+	 */
+	f->num = n;
+
+	for (i = 0; i < n; i++) {
+		if (list_empty_careful(&pvt->free_list.list))
+			if (fill_page_stack(&pvt->free_list, &pvt->mtx))
+				goto cleanup;
+
+		mutex_lock(&pvt->mtx);
+		pos = NULL;
+		q = NULL;
+
+		/*
+		 * remove one mem struct from the free list and
+		 * add the address to the fast struct mem array
+		 */
+		list_for_each_safe(pos, q, &pvt->free_list.list) {
+			m = list_entry(pos, struct mem, list);
+			f->mem[i] = m;
+			list_del(pos);
+			break;
+		}
+		mutex_unlock(&pvt->mtx);
+
+		if (m != NULL)
+			f->pa[i] = m->pa;
+		else
+			goto cleanup;
+	}
+
+	mutex_lock(&pvt->mtx);
+	list_add(&f->list, &pvt->fast_list.list);
+	mutex_unlock(&pvt->mtx);
+
+	if (f != NULL)
+		return f->pa;
+cleanup:
+	for (; i > 0; i--) {
+		mutex_lock(&pvt->mtx);
+		list_add(&f->mem[i - 1]->list, &pvt->free_list.list);
+		mutex_unlock(&pvt->mtx);
+	}
+	kfree(f->pa);
+	kfree(f->mem);
+	kfree(f);
+	return NULL;
+}
+
+static void tmm_pat_free_pages(struct tmm *tmm, u32 *list)
+{
+	struct dmm_mem *pvt = (struct dmm_mem *) tmm->pvt;
+	struct list_head *pos = NULL, *q = NULL;
+	struct fast *f = NULL;
+	s32 i = 0;
+
+	mutex_lock(&pvt->mtx);
+	pos = NULL;
+	q = NULL;
+	list_for_each_safe(pos, q, &pvt->fast_list.list) {
+		f = list_entry(pos, struct fast, list);
+		if (f->pa[0] == list[0]) {
+			for (i = 0; i < f->num; i++) {
+				if (count < PAGE_CAP) {
+					list_add(
+					&((struct mem *)f->mem[i])->list,
+					&pvt->free_list.list);
+				} else {
+					__free_page(
+						((struct mem *)f->mem[i])->pg);
+					count--;
+				}
+				list_add(&((struct mem *)f->mem[i])->list,
+							&pvt->free_list.list);
+			}
+			list_del(pos);
+			kfree(f->pa);
+			kfree(f->mem);
+			kfree(f);
+			break;
+		}
+	}
+	mutex_unlock(&pvt->mtx);
+}
+
+static s32 tmm_pat_map(struct tmm *tmm, struct pat_area area, u32 page_pa)
+{
+	struct dmm_mem *pvt = (struct dmm_mem *) tmm->pvt;
+	struct pat pat_desc = {0};
+
+	/* send pat descriptor to dmm driver */
+	pat_desc.ctrl.dir = 0;
+	pat_desc.ctrl.ini = 0;
+	pat_desc.ctrl.lut_id = 0;
+	pat_desc.ctrl.start = 1;
+	pat_desc.ctrl.sync = 0;
+	pat_desc.area = area;
+	pat_desc.next = NULL;
+
+	/* must be a 16-byte aligned physical address */
+	pat_desc.data = page_pa;
+	return dmm_pat_refill(pvt->dmm, &pat_desc, MANUAL);
+}
+
+struct tmm *tmm_pat_init(u32 pat_id)
+{
+	struct tmm *tmm = NULL;
+	struct dmm_mem *pvt = NULL;
+
+	struct dmm *dmm = dmm_pat_init(pat_id);
+	if (dmm)
+		tmm = kmalloc(sizeof(*tmm), GFP_KERNEL);
+	if (tmm)
+		pvt = kmalloc(sizeof(*pvt), GFP_KERNEL);
+	if (pvt) {
+		/* private data */
+		pvt->dmm = dmm;
+		INIT_LIST_HEAD(&pvt->free_list.list);
+		INIT_LIST_HEAD(&pvt->used_list.list);
+		INIT_LIST_HEAD(&pvt->fast_list.list);
+		mutex_init(&pvt->mtx);
+
+		count = 0;
+		if (list_empty_careful(&pvt->free_list.list))
+			if (fill_page_stack(&pvt->free_list, &pvt->mtx))
+				goto error;
+
+		/* public data */
+		tmm->pvt = pvt;
+		tmm->deinit = tmm_pat_deinit;
+		tmm->get = tmm_pat_get_pages;
+		tmm->free = tmm_pat_free_pages;
+		tmm->map = tmm_pat_map;
+		tmm->clear = NULL;   /* not yet supported */
+
+		return tmm;
+	}
+
+error:
+	kfree(pvt);
+	kfree(tmm);
+	dmm_pat_release(dmm);
+	return NULL;
+}
+EXPORT_SYMBOL(tmm_pat_init);
+
diff --git a/drivers/media/video/omap/Kconfig b/drivers/media/video/omap/Kconfig
new file mode 100644
index 000000000000..e332033e870a
--- /dev/null
+++ b/drivers/media/video/omap/Kconfig
@@ -0,0 +1,17 @@
+config VIDEO_OMAP2_VOUT
+	tristate "OMAP2/OMAP3/OMAP4 V4L2-Display driver"
+	depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
+	select VIDEOBUF_GEN
+	select VIDEOBUF_DMA_SG
+	select OMAP2_DSS
+	select OMAP2_VRAM
+	default n
+	---help---
+	  V4L2 Display driver support for OMAP2/3/4 based boards.
+
+config OMAP2_VRFB
+	bool
+	depends on ARCH_OMAP2 || ARCH_OMAP3
+	default y if VIDEO_OMAP2_VOUT
+	help
+	  VRFB used in V4L2 in OMAP2,3
diff --git a/drivers/media/video/omap/Makefile b/drivers/media/video/omap/Makefile
new file mode 100644
index 000000000000..2ab8fb265a9f
--- /dev/null
+++ b/drivers/media/video/omap/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the omap video device drivers.
+#
+
+# OMAP2/3 Display driver
+omap-vout-mod-objs := omap_vout.o omap_voutlib.o omap_wb.o
+obj-$(CONFIG_VIDEO_OMAP2_VOUT) += omap-vout-mod.o
diff --git a/drivers/media/video/omap/omap_vout.c b/drivers/media/video/omap/omap_vout.c
new file mode 100644
index 000000000000..3d6516d0f42a
--- /dev/null
+++ b/drivers/media/video/omap/omap_vout.c
@@ -0,0 +1,3129 @@
+/*
+ * omap_vout.c
+ *
+ * Copyright (C) 2005-2010 Texas Instruments.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * Leveraged code from the OMAP2 camera driver
+ * Video-for-Linux (Version 2) camera capture driver for
+ * the OMAP24xx camera controller.
+ *
+ * Author: Andy Lowe (source@mvista.com)
+ *
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ * Copyright (C) 2010 Texas Instruments.
+ *
+ * History:
+ * 20-APR-2006 Khasim		Modified VRFB based Rotation,
+ *				The image data is always read from 0 degree
+ *				view and written
+ *				to the virtual space of desired rotation angle
+ * 4-DEC-2006  Jian		Changed to support better memory management
+ *
+ * 17-Nov-2008 Hardik		Changed driver to use video_ioctl2
+ *
+ * 23-Feb-2010 Vaibhav		Modified to use new DSS2 interface
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <linux/videodev2.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+
+#include <media/videobuf-dma-sg.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-device.h>
+
+#include <asm/processor.h>
+#include <plat/dma.h>
+#include <plat/vram.h>
+#include <plat/vrfb.h>
+#include <plat/display.h>
+#include <plat/cpu.h>
+
+#include "omap_voutlib.h"
+#include "omap_voutdef.h"
+
+#include <mach/tiler.h>
+MODULE_AUTHOR("Texas Instruments");
+MODULE_DESCRIPTION("OMAP Video for Linux Video out driver");
+MODULE_LICENSE("GPL");
+
+
+/* Driver Configuration macros */
+#define VOUT_NAME		"omap_vout"
+
+enum omap_vout_channels {
+	OMAP_VIDEO1 = 0,
+	OMAP_VIDEO2,
+	OMAP_VIDEO3,
+};
+
+enum dma_channel_state {
+	DMA_CHAN_NOT_ALLOTED = 0,
+	DMA_CHAN_ALLOTED,
+};
+
+#define QQVGA_WIDTH		160
+#define QQVGA_HEIGHT		120
+
+/* Max Resolution supported by the driver */
+#ifdef CONFIG_ARCH_OMAP4
+#define VID_MAX_WIDTH		2048	/* Largest width */
+#define VID_MAX_HEIGHT		2048	/* Largest height */
+#else
+#define VID_MAX_WIDTH		1280	/* Largest width */
+#define VID_MAX_HEIGHT		720	/* Largest height */
+#endif
+/* Mimimum requirement is 2x2 for DSS */
+#define VID_MIN_WIDTH		2
+#define VID_MIN_HEIGHT		2
+
+/* 2048 x 2048 is max res supported by OMAP display controller */
+#define MAX_PIXELS_PER_LINE     2048
+
+#define VRFB_TX_TIMEOUT         1000
+
+/* Max buffer size tobe allocated during init */
+#define OMAP_VOUT_MAX_BUF_SIZE (VID_MAX_WIDTH*VID_MAX_HEIGHT*4)
+
+static struct videobuf_queue_ops video_vbq_ops;
+/* Variables configurable through module params*/
+static u32 video1_numbuffers = 3;
+static u32 video2_numbuffers = 3;
+static u32 video1_bufsize = OMAP_VOUT_MAX_BUF_SIZE;
+static u32 video2_bufsize = OMAP_VOUT_MAX_BUF_SIZE;
+static u32 video3_numbuffers = 3;
+static u32 video3_bufsize = OMAP_VOUT_MAX_BUF_SIZE;
+static u32 vid1_static_vrfb_alloc;
+static u32 vid2_static_vrfb_alloc;
+static int debug;
+
+/* Module parameters */
+module_param(video1_numbuffers, uint, S_IRUGO);
+MODULE_PARM_DESC(video1_numbuffers,
+	"Number of buffers to be allocated at init time for Video1 device.");
+
+module_param(video2_numbuffers, uint, S_IRUGO);
+MODULE_PARM_DESC(video2_numbuffers,
+	"Number of buffers to be allocated at init time for Video2 device.");
+
+module_param(video1_bufsize, uint, S_IRUGO);
+MODULE_PARM_DESC(video1_bufsize,
+	"Size of the buffer to be allocated for video1 device");
+
+module_param(video2_bufsize, uint, S_IRUGO);
+MODULE_PARM_DESC(video2_bufsize,
+	"Size of the buffer to be allocated for video2 device");
+
+module_param(video3_numbuffers, uint, S_IRUGO);
+MODULE_PARM_DESC(video3_numbuffers, "Number of buffers to be allocated at \
+		init time for Video3 device.");
+
+module_param(video3_bufsize, uint, S_IRUGO);
+MODULE_PARM_DESC(video1_bufsize, "Size of the buffer to be allocated for \
+		video3 device");
+module_param(vid1_static_vrfb_alloc, bool, S_IRUGO);
+MODULE_PARM_DESC(vid1_static_vrfb_alloc,
+	"Static allocation of the VRFB buffer for video1 device");
+
+module_param(vid2_static_vrfb_alloc, bool, S_IRUGO);
+MODULE_PARM_DESC(vid2_static_vrfb_alloc,
+	"Static allocation of the VRFB buffer for video2 device");
+
+module_param(debug, bool, S_IRUGO);
+MODULE_PARM_DESC(debug, "Debug level (0-1)");
+
+/* Local Helper functions */
+enum omap_color_mode video_mode_to_dss_mode(
+		struct v4l2_pix_format *pix);
+static void omap_vout_isr(void *arg, unsigned int irqstatus);
+static void omap_vout_cleanup_device(struct omap_vout_device *vout);
+
+/* list of image formats supported by OMAP2 video pipelines */
+const static struct v4l2_fmtdesc omap_formats[] = {
+	{
+		/* Note:  V4L2 defines RGB565 as:
+		 *
+		 *      Byte 0                    Byte 1
+		 *      g2 g1 g0 r4 r3 r2 r1 r0   b4 b3 b2 b1 b0 g5 g4 g3
+		 *
+		 * We interpret RGB565 as:
+		 *
+		 *      Byte 0                    Byte 1
+		 *      g2 g1 g0 b4 b3 b2 b1 b0   r4 r3 r2 r1 r0 g5 g4 g3
+		 */
+		.description = "RGB565, le",
+		.pixelformat = V4L2_PIX_FMT_RGB565,
+	},
+	{
+		/* Note:  V4L2 defines RGB32 as: RGB-8-8-8-8  we use
+		 *  this for RGB24 unpack mode, the last 8 bits are ignored
+		 * */
+		.description = "RGB32, le",
+		.pixelformat = V4L2_PIX_FMT_RGB32,
+	},
+	{
+		/* Note:  V4L2 defines RGB24 as: RGB-8-8-8  we use
+		 *        this for RGB24 packed mode
+		 *
+		 */
+		.description = "RGB24, le",
+		.pixelformat = V4L2_PIX_FMT_RGB24,
+	},
+	{
+		.description = "YUYV (YUV 4:2:2), packed",
+		.pixelformat = V4L2_PIX_FMT_YUYV,
+	},
+	{
+		.description = "UYVY, packed",
+		.pixelformat = V4L2_PIX_FMT_UYVY,
+	},
+	{
+	 .description = "NV12 - YUV420 format",
+	 .pixelformat = V4L2_PIX_FMT_NV12,
+	},
+};
+
+#define NUM_OUTPUT_FORMATS (ARRAY_SIZE(omap_formats))
+
+#ifndef CONFIG_ARCH_OMAP4
+/*
+ * Allocate buffers
+ */
+static unsigned long omap_vout_alloc_buffer(u32 buf_size, u32 *phys_addr)
+{
+	u32 order, size;
+	unsigned long virt_addr, addr;
+
+	size = PAGE_ALIGN(buf_size);
+	order = get_order(size);
+	virt_addr = __get_free_pages(GFP_KERNEL | GFP_DMA, order);
+	addr = virt_addr;
+
+	if (virt_addr) {
+		while (size > 0) {
+			SetPageReserved(virt_to_page(addr));
+			addr += PAGE_SIZE;
+			size -= PAGE_SIZE;
+		}
+	}
+	*phys_addr = (u32) virt_to_phys((void *) virt_addr);
+	return virt_addr;
+}
+#endif
+/*
+ * Free buffers
+ */
+static void omap_vout_free_buffer(unsigned long virtaddr, u32 phys_addr,
+			 u32 buf_size)
+{
+	u32 order, size;
+	unsigned long addr = virtaddr;
+
+	size = PAGE_ALIGN(buf_size);
+	order = get_order(size);
+
+	while (size > 0) {
+		ClearPageReserved(virt_to_page(addr));
+		addr += PAGE_SIZE;
+		size -= PAGE_SIZE;
+	}
+	free_pages((unsigned long) virtaddr, order);
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+ * Function for allocating video buffers
+ */
+static int omap_vout_allocate_vrfb_buffers(struct omap_vout_device *vout,
+		unsigned int *count, int startindex)
+{
+	int i, j;
+
+	for (i = 0; i < *count; i++) {
+		if (!vout->smsshado_virt_addr[i]) {
+			vout->smsshado_virt_addr[i] =
+				omap_vout_alloc_buffer(vout->smsshado_size,
+						&vout->smsshado_phy_addr[i]);
+		}
+		if (!vout->smsshado_virt_addr[i] && startindex != -1) {
+			if (V4L2_MEMORY_MMAP == vout->memory && i >= startindex)
+				break;
+		}
+		if (!vout->smsshado_virt_addr[i]) {
+			for (j = 0; j < i; j++) {
+				omap_vout_free_buffer(
+						vout->smsshado_virt_addr[j],
+						vout->smsshado_size);
+				vout->smsshado_virt_addr[j] = 0;
+				vout->smsshado_phy_addr[j] = 0;
+			}
+			*count = 0;
+			return -ENOMEM;
+		}
+		memset((void *) vout->smsshado_virt_addr[i], 0,
+				vout->smsshado_size);
+	}
+	return 0;
+}
+#endif
+/*
+ * Try format
+ */
+int omap_vout_try_format(struct v4l2_pix_format *pix)
+{
+	int ifmt, bpp = 0;
+
+	pix->height = clamp(pix->height, (u32)VID_MIN_HEIGHT,
+			(u32)VID_MAX_HEIGHT);
+	pix->width = clamp(pix->width, (u32)VID_MIN_WIDTH, (u32)VID_MAX_WIDTH);
+
+	for (ifmt = 0; ifmt < NUM_OUTPUT_FORMATS; ifmt++) {
+		if (pix->pixelformat == omap_formats[ifmt].pixelformat)
+			break;
+	}
+
+	if (ifmt == NUM_OUTPUT_FORMATS)
+		ifmt = 0;
+
+	pix->pixelformat = omap_formats[ifmt].pixelformat;
+	pix->field = V4L2_FIELD_ANY;
+	pix->priv = 0;
+
+	switch (pix->pixelformat) {
+	case V4L2_PIX_FMT_YUYV:
+	case V4L2_PIX_FMT_UYVY:
+	default:
+		pix->colorspace = V4L2_COLORSPACE_JPEG;
+		bpp = YUYV_BPP;
+		break;
+	case V4L2_PIX_FMT_RGB565:
+	case V4L2_PIX_FMT_RGB565X:
+		pix->colorspace = V4L2_COLORSPACE_SRGB;
+		bpp = RGB565_BPP;
+		break;
+	case V4L2_PIX_FMT_RGB24:
+		pix->colorspace = V4L2_COLORSPACE_SRGB;
+		bpp = RGB24_BPP;
+		break;
+	case V4L2_PIX_FMT_RGB32:
+	case V4L2_PIX_FMT_BGR32:
+		pix->colorspace = V4L2_COLORSPACE_SRGB;
+		bpp = RGB32_BPP;
+		break;
+	case V4L2_PIX_FMT_NV12:
+		pix->colorspace = V4L2_COLORSPACE_JPEG;
+		bpp = 1; /* TODO: check this? */
+		break;
+	}
+	/* :NOTE: NV12 has width bytes per line in both Y and UV sections */
+	pix->bytesperline = pix->width * bpp;
+	pix->bytesperline = (pix->bytesperline + PAGE_SIZE - 1) &
+		~(PAGE_SIZE - 1);
+	/* :TODO: add 2-pixel round restrictions to YUYV and NV12 formats */
+	pix->sizeimage = pix->bytesperline * pix->height;
+	if (V4L2_PIX_FMT_NV12 == pix->pixelformat)
+		pix->sizeimage += pix->sizeimage >> 1;
+	return bpp;
+}
+
+
+#ifndef CONFIG_ARCH_OMAP4
+/*
+ * omap_vout_uservirt_to_phys: This inline function is used to convert user
+ * space virtual address to physical address.
+ */
+static u32 omap_vout_uservirt_to_phys(u32 virtp)
+{
+	unsigned long physp = 0;
+	struct vm_area_struct *vma;
+	struct mm_struct *mm = current->mm;
+
+	vma = find_vma(mm, virtp);
+	/* For kernel direct-mapped memory, take the easy way */
+	if (virtp >= PAGE_OFFSET) {
+		physp = virt_to_phys((void *) virtp);
+	} else if (vma && (vma->vm_flags & VM_IO)
+			&& vma->vm_pgoff) {
+		/* this will catch, kernel-allocated,
+		   mmaped-to-usermode addresses */
+		physp = (vma->vm_pgoff << PAGE_SHIFT) + (virtp - vma->vm_start);
+	} else {
+		/* otherwise, use get_user_pages() for general userland pages */
+		int res, nr_pages = 1;
+		struct page *pages;
+		down_read(&current->mm->mmap_sem);
+
+		res = get_user_pages(current, current->mm, virtp, nr_pages,
+				1, 0, &pages, NULL);
+		up_read(&current->mm->mmap_sem);
+
+		if (res == nr_pages) {
+			physp =  __pa(page_address(&pages[0]) +
+					(virtp & ~PAGE_MASK));
+		} else {
+			printk(KERN_WARNING VOUT_NAME
+					"get_user_pages failed\n");
+			return 0;
+		}
+	}
+
+	return physp;
+}
+
+/* Wakes up the application once the DMA transfer to VRFB space is completed.
+ */
+static void omap_vout_vrfb_dma_tx_callback(int lch, u16 ch_status, void *data)
+{
+	struct vid_vrfb_dma *t = (struct vid_vrfb_dma *) data;
+
+	t->tx_status = 1;
+	wake_up_interruptible(&t->wait);
+}
+
+/*
+ * Release the VRFB context once the module exits
+ */
+static void omap_vout_release_vrfb(struct omap_vout_device *vout)
+{
+	int i;
+
+	for (i = 0; i < 4; i++)
+		omap_vrfb_release_ctx(&vout->vrfb_context[i]);
+
+	if (vout->vrfb_dma_tx.req_status == DMA_CHAN_ALLOTED) {
+		vout->vrfb_dma_tx.req_status = DMA_CHAN_NOT_ALLOTED;
+		omap_free_dma(vout->vrfb_dma_tx.dma_ch);
+	}
+
+}
+#endif
+/*
+ * Return true if rotation is 90 or 270
+ */
+static inline int rotate_90_or_270(const struct omap_vout_device *vout)
+{
+	return (vout->rotation == dss_rotation_90_degree ||
+			vout->rotation == dss_rotation_270_degree);
+}
+
+/*
+ * Return true if rotation is enabled
+ */
+static inline int rotation_enabled(const struct omap_vout_device *vout)
+{
+	return vout->rotation || vout->mirror;
+}
+
+/*
+ * Reverse the rotation degree if mirroring is enabled
+ */
+static inline int calc_rotation(const struct omap_vout_device *vout)
+{
+#ifndef CONFIG_ARCH_OMAP4
+	if (!vout->mirror)
+		return vout->rotation;
+
+	switch (vout->rotation) {
+	case dss_rotation_90_degree:
+		return dss_rotation_270_degree;
+	case dss_rotation_270_degree:
+		return dss_rotation_90_degree;
+	case dss_rotation_180_degree:
+		return dss_rotation_0_degree;
+	default:
+		return dss_rotation_180_degree;
+	}
+#else
+	return vout->rotation;
+#endif
+	return dss_rotation_180_degree;
+}
+
+/*
+ * Free the V4L2 buffers
+ */
+static void omap_vout_free_buffers(struct omap_vout_device *vout)
+{
+	int i, numbuffers;
+
+	/* Allocate memory for the buffers */
+	if (OMAP_VIDEO3 == vout->vid) {
+		numbuffers = video3_numbuffers;
+		vout->buffer_size = video3_bufsize;
+	} else {
+		numbuffers = (vout->vid) ?  video2_numbuffers : video1_numbuffers;
+		vout->buffer_size = (vout->vid) ? video2_bufsize : video1_bufsize;
+	}
+
+	for (i = 0; i < numbuffers; i++) {
+		omap_vout_free_buffer(vout->buf_virt_addr[i],
+			 vout->buf_phy_addr[i], vout->buffer_size);
+		vout->buf_phy_addr[i] = 0;
+		vout->buf_virt_addr[i] = 0;
+	}
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+/*
+ * Free VRFB buffers
+ */
+static void omap_vout_free_vrfb_buffers(struct omap_vout_device *vout)
+{
+	int j;
+
+	for (j = 0; j < 4; j++) {
+		omap_vout_free_buffer(vout->smsshado_virt_addr[j],
+				vout->smsshado_size);
+		vout->smsshado_virt_addr[j] = 0;
+		vout->smsshado_phy_addr[j] = 0;
+	}
+}
+
+/*
+ * Allocate the buffers for the VRFB space.  Data is copied from V4L2
+ * buffers to the VRFB buffers using the DMA engine.
+ */
+static int omap_vout_vrfb_buffer_setup(struct omap_vout_device *vout,
+			  unsigned int *count, unsigned int startindex)
+{
+	int i;
+	bool yuv_mode;
+
+	/* Allocate the VRFB buffers only if the buffers are not
+	 * allocated during init time.
+	 */
+	if ((rotation_enabled(vout)) &&
+			!vout->vrfb_static_allocation)
+		if (omap_vout_allocate_vrfb_buffers(vout, count, startindex))
+			return -ENOMEM;
+
+	if (vout->dss_mode == OMAP_DSS_COLOR_YUV2 ||
+			vout->dss_mode == OMAP_DSS_COLOR_UYVY)
+		yuv_mode = true;
+	else
+		yuv_mode = false;
+
+	for (i = 0; i < *count; i++) {
+		omap_vrfb_setup(&vout->vrfb_context[i],
+				vout->smsshado_phy_addr[i],
+				vout->pix.width, vout->pix.height,
+				vout->bpp, yuv_mode);
+	}
+	return 0;
+}
+#endif
+
+static void omap_vout_tiler_buffer_free(struct omap_vout_device *vout,
+					unsigned int count,
+					unsigned int startindex)
+{
+	int i;
+
+	if (startindex < 0)
+		startindex = 0;
+	if (startindex + count > VIDEO_MAX_FRAME)
+		count = VIDEO_MAX_FRAME - startindex;
+
+	for (i = startindex; i < startindex + count; i++) {
+		if (vout->buf_phy_addr_alloced[i])
+			tiler_free(vout->buf_phy_addr_alloced[i]);
+		if (vout->buf_phy_uv_addr_alloced[i])
+			tiler_free(vout->buf_phy_uv_addr_alloced[i]);
+		vout->buf_phy_addr[i] = 0;
+		vout->buf_phy_addr_alloced[i] = 0;
+		vout->buf_phy_uv_addr[i] = 0;
+		vout->buf_phy_uv_addr_alloced[i] = 0;
+	}
+}
+
+/* Allocate the buffers for  TILER space.  Ideally, the buffers will be ONLY
+ in tiler space, with different rotated views available by just a convert.
+ */
+static int omap_vout_tiler_buffer_setup(struct omap_vout_device *vout,
+					unsigned int *count, unsigned int startindex,
+					struct v4l2_pix_format *pix)
+{
+	int i, aligned = 1;
+	enum tiler_fmt fmt;
+
+	/* normalize buffers to allocate so we stay within bounds */
+	int start = (startindex < 0) ? 0 : startindex;
+	int n_alloc = (start + *count > VIDEO_MAX_FRAME)
+		? VIDEO_MAX_FRAME - start : *count;
+	int bpp = omap_vout_try_format(pix);
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "tiler buffer alloc:\n"
+		"count - %d, start -%d :\n", *count, startindex);
+
+	/* special allocation scheme for NV12 format */
+	if (OMAP_DSS_COLOR_NV12 == video_mode_to_dss_mode(pix)) {
+		tiler_alloc_packed_nv12(&n_alloc, pix->width,
+			pix->height,
+			(void **) vout->buf_phy_addr + start,
+			(void **) vout->buf_phy_uv_addr + start,
+			(void **) vout->buf_phy_addr_alloced + start,
+			(void **) vout->buf_phy_uv_addr_alloced + start,
+			aligned);
+	} else {
+		/* Only bpp of 1, 2, and 4 is supported by tiler */
+		fmt = (bpp == 1 ? TILFMT_8BIT :
+			bpp == 2 ? TILFMT_16BIT :
+			bpp == 4 ? TILFMT_32BIT : TILFMT_INVALID);
+		if (fmt == TILFMT_INVALID)
+			return -ENOMEM;
+
+		tiler_alloc_packed(&n_alloc, fmt, pix->width,
+			pix->height,
+			(void **) vout->buf_phy_addr + start,
+			(void **) vout->buf_phy_addr_alloced + start,
+			aligned);
+	}
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
+			"allocated %d buffers\n", n_alloc);
+
+	if (n_alloc < *count) {
+		if (n_alloc && (startindex == -1 ||
+			V4L2_MEMORY_MMAP != vout->memory)) {
+			/* TODO: check this condition's logic */
+			omap_vout_tiler_buffer_free(vout, n_alloc, start);
+			*count = 0;
+			return -ENOMEM;
+		}
+	}
+
+	for (i = start; i < start + n_alloc; i++) {
+		v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
+				"y=%08lx (%d) uv=%08lx (%d)\n",
+				vout->buf_phy_addr[i],
+				vout->buf_phy_addr_alloced[i] ? 1 : 0,
+				vout->buf_phy_uv_addr[i],
+				vout->buf_phy_uv_addr_alloced[i] ? 1 : 0);
+	}
+
+	*count = n_alloc;
+
+	return 0;
+}
+/* Free tiler buffers */
+static void omap_vout_free_tiler_buffers(struct omap_vout_device *vout)
+{
+	omap_vout_tiler_buffer_free(vout, vout->buffer_allocated, 0);
+	vout->buffer_allocated = 0;
+}
+/* Convert V4L2 rotation to DSS rotation
+ *	V4L2 understand 0, 90, 180, 270.
+ *	Convert to 0, 1, 2 and 3 repsectively for DSS
+ */
+static int v4l2_rot_to_dss_rot(int v4l2_rotation, enum dss_rotation *rotation,
+		bool mirror)
+{
+	switch (v4l2_rotation) {
+	case 90:
+		*rotation = dss_rotation_90_degree;
+		return 0;
+	case 180:
+		*rotation = dss_rotation_180_degree;
+		return 0;
+	case 270:
+		*rotation = dss_rotation_270_degree;
+		return 0;
+	case 0:
+		*rotation = dss_rotation_0_degree;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+
+}
+
+/*
+ * Calculate the buffer offsets from which the streaming should
+ * start. This offset calculation is mainly required because of
+ * the VRFB 32 pixels alignment with rotation.
+ */
+static int omap_vout_calculate_offset(struct omap_vout_device *vout, int idx)
+{
+	struct omap_overlay *ovl;
+	enum dss_rotation rotation;
+	struct omapvideo_info *ovid;
+#ifndef CONFIG_ARCH_OMAP4
+	bool mirroring = vout->mirror;
+#endif
+	struct omap_dss_device *cur_display;
+	struct v4l2_rect *crop = &vout->crop;
+	struct v4l2_pix_format *pix = &vout->pix;
+	int *cropped_offset = vout->cropped_offset + idx;
+	int vr_ps = 1, ps = 2;
+#ifndef CONFIG_ARCH_OMAP4
+	int temp_ps = 2;
+	int offset = 0;
+#endif
+	int *cropped_uv_offset = vout->cropped_uv_offset + idx;
+	int ctop = 0, cleft = 0, line_length = 0;
+	unsigned long addr = 0, uv_addr = 0;
+
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+	/* get the display device attached to the overlay */
+	if (!ovl->manager || !ovl->manager->device)
+		return -1;
+	cur_display = ovl->manager->device;
+
+	rotation = calc_rotation(vout);
+
+	if (V4L2_PIX_FMT_YUYV == pix->pixelformat ||
+			V4L2_PIX_FMT_UYVY == pix->pixelformat) {
+		if (rotation_enabled(vout)) {
+			/*
+			 * ps    - Actual pixel size for YUYV/UYVY for
+			 *              VRFB/Mirroring is 4 bytes
+			 * vr_ps - Virtually pixel size for YUYV/UYVY is
+			 *              2 bytes
+			 */
+			ps = 4;
+			vr_ps = 2;
+		} else {
+			ps = 2;	/* otherwise the pixel size is 2 byte */
+		}
+	} else if (V4L2_PIX_FMT_RGB32 == pix->pixelformat) {
+		ps = 4;
+	} else if (V4L2_PIX_FMT_RGB24 == pix->pixelformat) {
+		ps = 3;
+	}
+	vout->ps = ps;
+	vout->vr_ps = vr_ps;
+
+	if (rotation_enabled(vout)) {
+		line_length = MAX_PIXELS_PER_LINE;
+		ctop = (pix->height - crop->height) - crop->top;
+		cleft = (pix->width - crop->width) - crop->left;
+	} else {
+		line_length = pix->width;
+	}
+	vout->line_length = line_length;
+#ifndef CONFIG_ARCH_OMAP4
+	switch (rotation) {
+	case dss_rotation_90_degree:
+		offset = vout->vrfb_context[0].yoffset *
+			vout->vrfb_context[0].bytespp;
+		temp_ps = ps / vr_ps;
+		if (mirroring == 0) {
+			*cropped_offset = offset + line_length *
+				temp_ps * cleft + crop->top * temp_ps;
+		} else {
+			*cropped_offset = offset + line_length * temp_ps *
+				cleft + crop->top * temp_ps + (line_length *
+				((crop->width / (vr_ps)) - 1) * ps);
+		}
+		break;
+	case dss_rotation_180_degree:
+		offset = ((MAX_PIXELS_PER_LINE * vout->vrfb_context[0].yoffset *
+			vout->vrfb_context[0].bytespp) +
+			(vout->vrfb_context[0].xoffset *
+			vout->vrfb_context[0].bytespp));
+		if (mirroring == 0) {
+			*cropped_offset = offset + (line_length * ps * ctop) +
+				(cleft / vr_ps) * ps;
+
+		} else {
+			*cropped_offset = offset + (line_length * ps * ctop) +
+				(cleft / vr_ps) * ps + (line_length *
+				(crop->height - 1) * ps);
+		}
+		break;
+	case dss_rotation_270_degree:
+		offset = MAX_PIXELS_PER_LINE * vout->vrfb_context[0].xoffset *
+			vout->vrfb_context[0].bytespp;
+		temp_ps = ps / vr_ps;
+		if (mirroring == 0) {
+			*cropped_offset = offset + line_length *
+			    temp_ps * crop->left + ctop * ps;
+		} else {
+			*cropped_offset = offset + line_length *
+				temp_ps * crop->left + ctop * ps +
+				(line_length * ((crop->width / vr_ps) - 1) *
+				 ps);
+		}
+		break;
+	case dss_rotation_0_degree:
+		if (mirroring == 0) {
+			*cropped_offset = (line_length * ps) *
+				crop->top + (crop->left / vr_ps) * ps;
+		} else {
+			*cropped_offset = (line_length * ps) *
+				crop->top + (crop->left / vr_ps) * ps +
+				(line_length * (crop->height - 1) * ps);
+		}
+		break;
+	default:
+		*cropped_offset = (line_length * ps * crop->top) /
+			vr_ps + (crop->left * ps) / vr_ps +
+			((crop->width / vr_ps) - 1) * ps;
+		break;
+	}
+#else
+	/* :TODO: change v4l2 to send TSPtr as tiled addresses to DSS2 */
+	addr = tiler_get_natural_addr(vout->queued_buf_addr[idx]);
+
+	if (OMAP_DSS_COLOR_NV12 == vout->dss_mode) {
+		*cropped_offset = tiler_stride(addr) * crop->top + crop->left;
+		uv_addr = tiler_get_natural_addr(
+			vout->queued_buf_uv_addr[idx]);
+		/* :TODO: only allow even crops for NV12 */
+		*cropped_uv_offset = tiler_stride(uv_addr) * (crop->top >> 1)
+			+ (crop->left & ~1);
+	} else {
+		*cropped_offset =
+			tiler_stride(addr) * crop->top + crop->left * ps;
+	}
+#endif
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "%s Offset:%x\n",
+			__func__, *cropped_offset);
+	return 0;
+}
+
+/*
+ * Convert V4L2 pixel format to DSS pixel format
+ */
+enum omap_color_mode video_mode_to_dss_mode(
+			struct v4l2_pix_format *pix)
+{
+#if 0 /* TODO: Take care of OMAP2,OMAP3 Video1 also */
+	struct omap_overlay *ovl;
+	struct omapvideo_info *ovid;
+	struct v4l2_pix_format *pix = &vout->pix;
+
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+#endif
+
+	switch (pix->pixelformat) {
+	case V4L2_PIX_FMT_NV12:
+		return OMAP_DSS_COLOR_NV12;
+	case 0:
+		break;
+	case V4L2_PIX_FMT_YUYV:
+		return OMAP_DSS_COLOR_YUV2;
+
+	case V4L2_PIX_FMT_UYVY:
+		return OMAP_DSS_COLOR_UYVY;
+
+	case V4L2_PIX_FMT_RGB565:
+		return OMAP_DSS_COLOR_RGB16;
+
+	case V4L2_PIX_FMT_RGB24:
+		return OMAP_DSS_COLOR_RGB24P;
+
+	case V4L2_PIX_FMT_RGB32:
+#if 0 /* TODO: Take care of OMAP2,OMAP3 Video1 also */
+		return (ovl->id == OMAP_DSS_VIDEO1) ?
+			OMAP_DSS_COLOR_RGB24U : OMAP_DSS_COLOR_ARGB32;
+#endif
+		return OMAP_DSS_COLOR_ARGB32;
+	case V4L2_PIX_FMT_BGR32:
+		return OMAP_DSS_COLOR_RGBX32;
+
+	default:
+		return -EINVAL;
+	}
+	return -EINVAL;
+}
+
+#if 0 /* Used for non Tiler NV12 */
+/* helper function: for NV12, returns uv buffer address given single buffer
+ * for yuv - y buffer will still be in the input.
+ * used only for non-TILER case
+*/
+u32 omapvid_get_uvbase_nv12(u32 paddr, int height, int width)
+{
+	u32 puv_addr = 0;
+
+	puv_addr = (paddr + (height * width));
+	return puv_addr;
+}
+#endif
+/*
+ * Setup the overlay
+ */
+int omapvid_setup_overlay(struct omap_vout_device *vout,
+		struct omap_overlay *ovl, int posx, int posy, int outw,
+		int outh, u32 addr, u32 uv_addr)
+{
+	int ret = 0;
+	struct omap_overlay_info info;
+	int cropheight, cropwidth, pixheight, pixwidth;
+
+	if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 &&
+			(outw != vout->pix.width || outh != vout->pix.height)) {
+		ret = -EINVAL;
+		goto setup_ovl_err;
+	}
+
+		vout->dss_mode = video_mode_to_dss_mode(&vout->pix);
+	if (vout->dss_mode == -EINVAL) {
+		ret = -EINVAL;
+		goto setup_ovl_err;
+	}
+
+	/* Setup the input plane parameters according to
+	 * rotation value selected.
+	 */
+	if (rotate_90_or_270(vout)) {
+		cropheight = vout->crop.width;
+		cropwidth = vout->crop.height;
+		pixheight = vout->pix.width;
+		pixwidth = vout->pix.height;
+	} else {
+		cropheight = vout->crop.height;
+		cropwidth = vout->crop.width;
+		pixheight = vout->pix.height;
+		pixwidth = vout->pix.width;
+	}
+
+	ovl->get_overlay_info(ovl, &info);
+	if (addr)
+		info.paddr = addr;
+	if (OMAP_DSS_COLOR_NV12 == vout->dss_mode)
+		info.p_uv_addr = uv_addr;
+	else
+		info.p_uv_addr = (u32) NULL;
+	info.vaddr = NULL;
+	info.width = cropwidth;
+	info.height = cropheight;
+	info.color_mode = vout->dss_mode;
+	info.mirror = vout->mirror;;
+	info.pos_x = posx;
+	info.pos_y = posy;
+	info.out_width = outw;
+	info.out_height = outh;
+	info.global_alpha =
+		vout->vid_info.overlays[0]->info.global_alpha;
+#ifndef CONFIG_ARCH_OMAP4
+	if (!rotation_enabled(vout)) {
+		info.rotation = 0;
+		info.rotation_type = OMAP_DSS_ROT_DMA;
+		info.screen_width = pixwidth;
+	} else {
+		info.rotation = vout->rotation;
+		info.rotation_type = OMAP_DSS_ROT_VRFB;
+		info.screen_width = 2048;
+	}
+#else
+	info.rotation_type = OMAP_DSS_ROT_TILER;
+	info.screen_width = pixwidth;
+	info.rotation = vout->rotation;
+#endif
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
+		"%s info.enable=%d info.addr=%x info.width=%d\n info.height=%d "
+		"info.color_mode=%d info.rotation=%d info.mirror=%d\n "
+		"info.posx=%d info.posy=%d info.out_width = %d \n"
+		"info.out_height=%d info.rotation_type=%d"
+		" info.screen_width=%d\n",
+		__func__, info.enabled, info.paddr, info.width, info.height,
+		info.color_mode, info.rotation, info.mirror, info.pos_x,
+		info.pos_y, info.out_width, info.out_height, info.rotation_type,
+		info.screen_width);
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "info.puvaddr=%x\n",
+			info.p_uv_addr);
+	ret = ovl->set_overlay_info(ovl, &info);
+	if (ret)
+		goto setup_ovl_err;
+
+	return 0;
+
+setup_ovl_err:
+	v4l2_warn(&vout->vid_dev->v4l2_dev, "setup_overlay failed\n");
+	return ret;
+}
+
+/*
+ * Initialize the overlay structure
+ */
+int omapvid_init(struct omap_vout_device *vout, u32 addr, u32 uv_addr)
+{
+	int ret = 0, i;
+	struct v4l2_window *win;
+	struct omap_overlay *ovl;
+	int posx, posy, outw, outh, temp;
+	struct omap_video_timings *timing;
+	struct omapvideo_info *ovid = &vout->vid_info;
+
+	win = &vout->win;
+	for (i = 0; i < ovid->num_overlays; i++) {
+		ovl = ovid->overlays[i];
+		if (!ovl->manager || !ovl->manager->device)
+			return -EINVAL;
+
+		timing = &ovl->manager->device->panel.timings;
+
+		outw = win->w.width;
+		outh = win->w.height;
+		posx = win->w.left;
+		posy = win->w.top;
+		switch (vout->rotation) {
+		case dss_rotation_90_degree:
+			/* Invert the height and width for 90
+			 * and 270 degree rotation
+			 */
+			temp = outw;
+			outw = outh;
+			outh = temp;
+#ifndef CONFIG_ARCH_OMAP4
+			posy = (timing->y_res - win->w.width)-
+				win->w.left;
+			posx = win->w.top;
+#endif
+			break;
+
+		case dss_rotation_180_degree:
+#ifndef CONFIG_ARCH_OMAP4
+			posx = (timing->x_res - win->w.width) -
+				win->w.left;
+			posy = (timing->y_res - win->w.height) -
+				win->w.top;
+#endif
+			break;
+
+		case dss_rotation_270_degree:
+			temp = outw;
+			outw = outh;
+			outh = temp;
+#ifndef CONFIG_ARCH_OMAP4
+			posy = win->w.left;
+			posx = (timing->x_res - win->w.height)
+				- win->w.top;
+#endif
+			break;
+
+		default:
+			posx = win->w.left;
+			posy = win->w.top;
+			break;
+		}
+
+		ret = omapvid_setup_overlay(vout, ovl, posx, posy, outw,
+				outh, addr, uv_addr);
+		if (ret)
+			goto omapvid_init_err;
+	}
+	return 0;
+
+omapvid_init_err:
+	v4l2_warn(&vout->vid_dev->v4l2_dev, "apply_changes failed\n");
+	return ret;
+}
+
+/*
+ * Apply the changes set the go bit of DSS
+ */
+int omapvid_apply_changes(struct omap_vout_device *vout)
+{
+	int i;
+	struct omap_overlay *ovl;
+	struct omapvideo_info *ovid = &vout->vid_info;
+
+	for (i = 0; i < ovid->num_overlays; i++) {
+		ovl = ovid->overlays[i];
+		if (!ovl->manager || !ovl->manager->device)
+			return -EINVAL;
+		ovl->manager->apply(ovl->manager);
+	}
+
+	return 0;
+}
+
+/* Video buffer call backs */
+
+/*
+ * Buffer setup function is called by videobuf layer when REQBUF ioctl is
+ * called. This is used to setup buffers and return size and count of
+ * buffers allocated. After the call to this buffer, videobuf layer will
+ * setup buffer queue depending on the size and count of buffers
+ */
+static int omap_vout_buffer_setup(struct videobuf_queue *q, unsigned int *count,
+			  unsigned int *size)
+{
+	int i;
+#ifndef CONFIG_ARCH_OMAP4
+	int startindex = 0, j;
+	u32 phy_addr = 0, virt_addr = 0;
+#endif
+	struct omap_vout_device *vout = q->priv_data;
+
+	if (!vout)
+		return -EINVAL;
+
+	if (V4L2_BUF_TYPE_VIDEO_OUTPUT != q->type)
+		return -EINVAL;
+
+#ifndef CONFIG_ARCH_OMAP4
+	startindex = (vout->vid == OMAP_VIDEO1) ?
+		video1_numbuffers : video2_numbuffers;
+	if (V4L2_MEMORY_MMAP == vout->memory && *count < startindex)
+		*count = startindex;
+
+	if ((rotation_enabled(vout))
+			&& *count > 4)
+		*count = 4;
+
+	/* If rotation is enabled, allocate memory for VRFB space also */
+	if (rotation_enabled(vout)) {
+		if (omap_vout_vrfb_buffer_setup(vout, count, startindex))
+			return -ENOMEM;
+	}
+
+	if (V4L2_MEMORY_MMAP != vout->memory)
+		return 0;
+
+	/* Now allocated the V4L2 buffers */
+	*size = PAGE_ALIGN(vout->pix.width * vout->pix.height * vout->bpp);
+	startindex = (vout->vid == OMAP_VIDEO1) ?
+		video1_numbuffers : video2_numbuffers;
+	for (i = startindex; i < *count; i++) {
+		vout->buffer_size = *size;
+
+		virt_addr = omap_vout_alloc_buffer(vout->buffer_size,
+				&phy_addr);
+		if (!virt_addr) {
+			if (!rotation_enabled(vout))
+				break;
+			/* Free the VRFB buffers if no space for V4L2 buffers */
+			for (j = i; j < *count; j++) {
+				omap_vout_free_buffer(
+						vout->smsshado_virt_addr[j],
+						vout->smsshado_size);
+				vout->smsshado_virt_addr[j] = 0;
+				vout->smsshado_phy_addr[j] = 0;
+			}
+		}
+		vout->buf_virt_addr[i] = virt_addr;
+		vout->buf_phy_addr[i] = phy_addr;
+	}
+	*count = vout->buffer_allocated = i;
+
+#else
+
+	/* tiler_alloc_buf to be called here
+	pre-requisites: rotation, format?
+	based on that buffers will be allocated.
+	*/
+	/* Now allocated the V4L2 buffers */
+	/* i is the block-width - either 4K or 8K, depending upon input width*/
+	i = (vout->pix.width * vout->bpp +
+		TILER_PAGE - 1) & ~(TILER_PAGE - 1);
+
+	/* for NV12 format, buffer is height + height / 2*/
+	if (OMAP_DSS_COLOR_NV12 == vout->dss_mode)
+		*size = vout->buffer_size = (vout->pix.height * 3/2 * i);
+	else
+		*size = vout->buffer_size = (vout->pix.height * i);
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
+			"\nheight=%d, size = %d, vout->buffer_sz=%d\n",
+			vout->pix.height, *size, vout->buffer_size);
+	if (omap_vout_tiler_buffer_setup(vout, count, 0, &vout->pix))
+			return -ENOMEM;
+#endif
+	if (V4L2_MEMORY_MMAP != vout->memory)
+		return 0;
+	return 0;
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+/*
+ * Free the V4L2 buffers additionally allocated than default
+ * number of buffers and free all the VRFB buffers
+ */
+static void omap_vout_free_allbuffers(struct omap_vout_device *vout)
+{
+	int num_buffers = 0, i;
+
+	num_buffers = (vout->vid == OMAP_VIDEO1) ?
+		video1_numbuffers : video2_numbuffers;
+	for (i = num_buffers; i < vout->buffer_allocated; i++) {
+		if (vout->buf_virt_addr[i]) {
+			omap_vout_free_buffer(vout->buf_virt_addr[i],
+					vout->buffer_size);
+		}
+		vout->buf_virt_addr[i] = 0;
+		vout->buf_phy_addr[i] = 0;
+	}
+	/* Free the VRFB buffers only if they are allocated
+	 * during reqbufs.  Don't free if init time allocated
+	 */
+	if (!vout->vrfb_static_allocation) {
+		for (i = 0; i < 4; i++) {
+			if (vout->smsshado_virt_addr[i]) {
+				omap_vout_free_buffer(
+						vout->smsshado_virt_addr[i],
+						vout->smsshado_size);
+				vout->smsshado_virt_addr[i] = 0;
+				vout->smsshado_phy_addr[i] = 0;
+			}
+		}
+	}
+	vout->buffer_allocated = num_buffers;
+}
+#endif
+
+/*
+ * This function will be called when VIDIOC_QBUF ioctl is called.
+ * It prepare buffers before give out for the display. This function
+ * converts user space virtual address into physical address if userptr memory
+ * exchange mechanism is used. If rotation is enabled, it copies entire
+ * buffer into VRFB memory space before giving it to the DSS.
+ */
+static int omap_vout_buffer_prepare(struct videobuf_queue *q,
+			    struct videobuf_buffer *vb,
+			    enum v4l2_field field)
+{
+#ifndef CONFIG_ARCH_OMAP4
+	struct vid_vrfb_dma *tx;
+	enum dss_rotation rotation;
+#endif
+	struct videobuf_dmabuf *dmabuf = NULL;
+	struct omap_vout_device *vout = q->priv_data;
+#ifndef CONFIG_ARCH_OMAP4
+	u32 dest_frame_index = 0, src_element_index = 0;
+	u32 dest_element_index = 0, src_frame_index = 0;
+	u32 elem_count = 0, frame_count = 0, pixsize = 2;
+#endif
+	if (VIDEOBUF_NEEDS_INIT == vb->state) {
+		vb->width = vout->pix.width;
+		vb->height = vout->pix.height;
+		vb->size = vb->width * vb->height * vout->bpp;
+		vb->field = field;
+	}
+	vb->state = VIDEOBUF_PREPARED;
+#ifndef CONFIG_ARCH_OMAP4
+	/* if user pointer memory mechanism is used, get the physical
+	 * address of the buffer
+	 */
+	if (V4L2_MEMORY_USERPTR == vb->memory) {
+		if (0 == vb->baddr)
+			return -EINVAL;
+		/* Virtual address */
+		/* priv points to struct videobuf_pci_sg_memory. But we went
+		 * pointer to videobuf_dmabuf, which is member of
+		 * videobuf_pci_sg_memory */
+		dmabuf = videobuf_to_dma(q->bufs[vb->i]);
+		dmabuf->vmalloc = (void *) vb->baddr;
+
+		/* Physical address */
+		dmabuf->bus_addr =
+			(dma_addr_t) omap_vout_uservirt_to_phys(vb->baddr);
+	}
+
+	if (!rotation_enabled(vout)) {
+		dmabuf = videobuf_to_dma(q->bufs[vb->i]);
+
+		vout->queued_buf_addr[vb->i] = (u8 *) dmabuf->bus_addr;
+		return 0;
+	}
+	dmabuf = videobuf_to_dma(q->bufs[vb->i]);
+	/* If rotation is enabled, copy input buffer into VRFB
+	 * memory space using DMA. We are copying input buffer
+	 * into VRFB memory space of desired angle and DSS will
+	 * read image VRFB memory for 0 degree angle
+	 */
+	pixsize = vout->bpp * vout->vrfb_bpp;
+	/*
+	 * DMA transfer in double index mode
+	 */
+
+	/* Frame index */
+	dest_frame_index = ((MAX_PIXELS_PER_LINE * pixsize) -
+			(vout->pix.width * vout->bpp)) + 1;
+
+	/* Source and destination parameters */
+	src_element_index = 0;
+	src_frame_index = 0;
+	dest_element_index = 1;
+	/* Number of elements per frame */
+	elem_count = vout->pix.width * vout->bpp;
+	frame_count = vout->pix.height;
+	tx = &vout->vrfb_dma_tx;
+	tx->tx_status = 0;
+	omap_set_dma_transfer_params(tx->dma_ch, OMAP_DMA_DATA_TYPE_S32,
+			(elem_count / 4), frame_count, OMAP_DMA_SYNC_ELEMENT,
+			tx->dev_id, 0x0);
+	/* src_port required only for OMAP1 */
+	omap_set_dma_src_params(tx->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
+			dmabuf->bus_addr, src_element_index, src_frame_index);
+	/*set dma source burst mode for VRFB */
+	omap_set_dma_src_burst_mode(tx->dma_ch, OMAP_DMA_DATA_BURST_16);
+	rotation = calc_rotation(vout);
+
+	/* dest_port required only for OMAP1 */
+	omap_set_dma_dest_params(tx->dma_ch, 0, OMAP_DMA_AMODE_DOUBLE_IDX,
+			vout->vrfb_context[vb->i].paddr[0], dest_element_index,
+			dest_frame_index);
+	/*set dma dest burst mode for VRFB */
+	omap_set_dma_dest_burst_mode(tx->dma_ch, OMAP_DMA_DATA_BURST_16);
+	omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 0x20, 0);
+
+	omap_start_dma(tx->dma_ch);
+	interruptible_sleep_on_timeout(&tx->wait, VRFB_TX_TIMEOUT);
+
+	if (tx->tx_status == 0) {
+		omap_stop_dma(tx->dma_ch);
+		return -EINVAL;
+	}
+	/* Store buffers physical address into an array. Addresses
+	 * from this array will be used to configure DSS */
+	vout->queued_buf_addr[vb->i] = (u8 *)
+		vout->vrfb_context[vb->i].paddr[rotation];
+#else /* TILER to be used */
+
+	/* Here, we need to use the physical addresses given by Tiler:
+	*/
+	dmabuf = videobuf_to_dma(q->bufs[vb->i]);
+	vout->queued_buf_addr[vb->i] = (u8 *) dmabuf->bus_addr;
+	vout->queued_buf_uv_addr[vb->i] = (u8 *) dmabuf->vmalloc;
+
+#endif
+	return 0;
+}
+
+/*
+ * Buffer queue funtion will be called from the videobuf layer when _QBUF
+ * ioctl is called. It is used to enqueue buffer, which is ready to be
+ * displayed.
+ */
+static void omap_vout_buffer_queue(struct videobuf_queue *q,
+			  struct videobuf_buffer *vb)
+{
+	struct omap_vout_device *vout = q->priv_data;
+
+	/* Driver is also maintainig a queue. So enqueue buffer in the driver
+	 * queue */
+	list_add_tail(&vb->queue, &vout->dma_queue);
+
+	vb->state = VIDEOBUF_QUEUED;
+}
+
+/*
+ * Buffer release function is called from videobuf layer to release buffer
+ * which are already allocated
+ */
+static void omap_vout_buffer_release(struct videobuf_queue *q,
+			    struct videobuf_buffer *vb)
+{
+	struct omap_vout_device *vout = q->priv_data;
+
+	vb->state = VIDEOBUF_NEEDS_INIT;
+
+	if (V4L2_MEMORY_MMAP != vout->memory)
+		return;
+}
+
+/*
+ *  File operations
+ */
+static void omap_vout_vm_open(struct vm_area_struct *vma)
+{
+	struct omap_vout_device *vout = vma->vm_private_data;
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
+		"vm_open [vma=%08lx-%08lx]\n", vma->vm_start, vma->vm_end);
+	vout->mmap_count++;
+}
+
+static void omap_vout_vm_close(struct vm_area_struct *vma)
+{
+	struct omap_vout_device *vout = vma->vm_private_data;
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
+		"vm_close [vma=%08lx-%08lx]\n", vma->vm_start, vma->vm_end);
+	vout->mmap_count--;
+}
+
+static struct vm_operations_struct omap_vout_vm_ops = {
+	.open	= omap_vout_vm_open,
+	.close	= omap_vout_vm_close,
+};
+
+static int omap_vout_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	int i;
+	void *pos;
+#ifndef CONFIG_ARCH_OMAP4
+	unsigned long start = vma->vm_start;
+	unsigned long size = (vma->vm_end - vma->vm_start);
+#endif
+	struct videobuf_dmabuf *dmabuf = NULL;
+	struct omap_vout_device *vout = file->private_data;
+	struct videobuf_queue *q = &vout->vbq;
+	int j = 0, k = 0, m = 0, p = 0, m_increment = 0;
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
+			" %s pgoff=0x%lx, start=0x%lx, end=0x%lx\n", __func__,
+			vma->vm_pgoff, vma->vm_start, vma->vm_end);
+
+	/* look for the buffer to map */
+	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+		if (NULL == q->bufs[i])
+			continue;
+		if (V4L2_MEMORY_MMAP != q->bufs[i]->memory)
+			continue;
+		if (q->bufs[i]->boff == (vma->vm_pgoff << PAGE_SHIFT))
+			break;
+	}
+
+	if (VIDEO_MAX_FRAME == i) {
+		v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev,
+				"offset invalid [offset=0x%lx]\n",
+				(vma->vm_pgoff << PAGE_SHIFT));
+		return -EINVAL;
+	}
+	q->bufs[i]->baddr = vma->vm_start;
+
+	vma->vm_flags |= VM_RESERVED;
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+	vma->vm_ops = &omap_vout_vm_ops;
+	vma->vm_private_data = (void *) vout;
+	dmabuf = videobuf_to_dma(q->bufs[i]);
+	pos = dmabuf->vmalloc;
+#ifndef CONFIG_ARCH_OMAP4
+	vma->vm_pgoff = virt_to_phys((void *)pos) >> PAGE_SHIFT;
+	while (size > 0) {
+		unsigned long pfn;
+		pfn = virt_to_phys((void *) pos) >> PAGE_SHIFT;
+		if (remap_pfn_range(vma, start, pfn, PAGE_SIZE, PAGE_SHARED))
+			return -EAGAIN;
+		start += PAGE_SIZE;
+		pos += PAGE_SIZE;
+		size -= PAGE_SIZE;
+	}
+#else /* Tiler remapping */
+	pos = (void *) dmabuf->bus_addr;
+	/* get line width */
+	/* for NV12, Y buffer is 1bpp*/
+	if (OMAP_DSS_COLOR_NV12 == vout->dss_mode) {
+		p = (vout->pix.width +
+			TILER_PAGE - 1) & ~(TILER_PAGE - 1);
+		m_increment = 64 * TILER_WIDTH;
+	} else {
+		p = (vout->pix.width * vout->bpp +
+			TILER_PAGE - 1) & ~(TILER_PAGE - 1);
+
+		if (vout->bpp > 1)
+			m_increment = 2*64*TILER_WIDTH;
+		else
+			m_increment = 64 * TILER_WIDTH;
+	}
+
+	for (j = 0; j < vout->pix.height; j++) {
+		/* map each page of the line */
+	#if 0
+		if (0)
+			printk(KERN_NOTICE
+				"Y buffer %s::%s():%d: vm_start+%d = 0x%lx,"
+				"dma->vmalloc+%d = 0x%lx, w=0x%x\n",
+				__FILE__, __func__, __LINE__,
+				k, vma->vm_start + k, m,
+				(pos + m), p);
+	#endif
+		vma->vm_pgoff =
+			((unsigned long)pos + m) >> PAGE_SHIFT;
+
+		if (remap_pfn_range(vma, vma->vm_start + k,
+			((unsigned long)pos + m) >> PAGE_SHIFT,
+			p, vma->vm_page_prot))
+				return -EAGAIN;
+		k += p;
+		m += m_increment;
+	}
+	m = 0;
+
+	/* UV Buffer in case of NV12 format */
+	if (OMAP_DSS_COLOR_NV12 == vout->dss_mode) {
+		pos = dmabuf->vmalloc;
+		/* UV buffer is 2 bpp, but half size, so p remains */
+		m_increment = 2*64*TILER_WIDTH;
+
+		/* UV buffer is height / 2*/
+		for (j = 0; j < vout->pix.height / 2; j++) {
+			/* map each page of the line */
+		#if 0
+			if (0)
+				printk(KERN_NOTICE
+				"UV buffer %s::%s():%d: vm_start+%d = 0x%lx,"
+				"dma->vmalloc+%d = 0x%lx, w=0x%x\n",
+				__FILE__, __func__, __LINE__,
+				k, vma->vm_start + k, m,
+				(pos + m), p);
+		#endif
+			vma->vm_pgoff =
+				((unsigned long)pos + m) >> PAGE_SHIFT;
+
+			if (remap_pfn_range(vma, vma->vm_start + k,
+				((unsigned long)pos + m) >> PAGE_SHIFT,
+				p, vma->vm_page_prot))
+				return -EAGAIN;
+			k += p;
+			m += m_increment;
+		}
+	}
+
+#endif
+	vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */
+	vout->mmap_count++;
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "Exiting %s\n", __func__);
+
+	return 0;
+}
+
+static int omap_vout_release(struct file *file)
+{
+	unsigned int ret, i;
+	struct videobuf_queue *q;
+	struct omapvideo_info *ovid;
+	struct omap_vout_device *vout = file->private_data;
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "Entering %s\n", __func__);
+	ovid = &vout->vid_info;
+
+	if (!vout)
+		return 0;
+
+	q = &vout->vbq;
+	/* Disable all the overlay managers connected with this interface */
+	for (i = 0; i < ovid->num_overlays; i++) {
+		struct omap_overlay *ovl = ovid->overlays[i];
+		if (ovl->manager && ovl->manager->device) {
+			struct omap_overlay_info info;
+			ovl->get_overlay_info(ovl, &info);
+			info.enabled = 0;
+			ovl->set_overlay_info(ovl, &info);
+		}
+	}
+	/* Turn off the pipeline */
+	ret = omapvid_apply_changes(vout);
+	if (ret)
+		v4l2_warn(&vout->vid_dev->v4l2_dev,
+				"Unable to apply changes\n");
+
+	/* Free all buffers */
+#ifndef CONFIG_ARCH_OMAP4
+	omap_vout_free_allbuffers(vout);
+#else
+	omap_vout_free_tiler_buffers(vout);
+#endif
+	videobuf_mmap_free(q);
+
+	/* Even if apply changes fails we should continue
+	   freeing allocated memeory */
+	if (vout->streaming) {
+		u32 mask = 0;
+
+		mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN |
+			DISPC_IRQ_EVSYNC_ODD;
+		omap_dispc_unregister_isr(omap_vout_isr, vout, mask);
+		vout->streaming = 0;
+
+		videobuf_streamoff(q);
+		videobuf_queue_cancel(q);
+	}
+
+	if (vout->mmap_count != 0)
+		vout->mmap_count = 0;
+
+	vout->opened -= 1;
+	file->private_data = NULL;
+
+	if (vout->buffer_allocated)
+		videobuf_mmap_free(q);
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "Exiting %s\n", __func__);
+	return ret;
+}
+
+static int omap_vout_open(struct file *file)
+{
+	struct videobuf_queue *q;
+	struct omap_vout_device *vout = NULL;
+
+	vout = video_drvdata(file);
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "Entering %s\n", __func__);
+
+	if (vout == NULL)
+		return -ENODEV;
+
+	/* for now, we only support single open */
+	if (vout->opened)
+		return -EBUSY;
+
+	vout->opened += 1;
+
+	file->private_data = vout;
+	vout->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+
+	q = &vout->vbq;
+	video_vbq_ops.buf_setup = omap_vout_buffer_setup;
+	video_vbq_ops.buf_prepare = omap_vout_buffer_prepare;
+	video_vbq_ops.buf_release = omap_vout_buffer_release;
+	video_vbq_ops.buf_queue = omap_vout_buffer_queue;
+	spin_lock_init(&vout->vbq_lock);
+
+	videobuf_queue_sg_init(q, &video_vbq_ops, NULL, &vout->vbq_lock,
+			vout->type, V4L2_FIELD_NONE, sizeof
+			(struct videobuf_buffer), vout);
+
+	v4l2_dbg(1, debug, &vout->vid_dev->v4l2_dev, "Exiting %s\n", __func__);
+	return 0;
+}
+
+/*
+ * V4L2 ioctls
+ */
+static int vidioc_querycap(struct file *file, void *fh,
+		struct v4l2_capability *cap)
+{
+	struct omap_vout_device *vout = fh;
+
+	strlcpy(cap->driver, VOUT_NAME, sizeof(cap->driver));
+	strlcpy(cap->card, vout->vfd->name, sizeof(cap->card));
+	cap->bus_info[0] = '\0';
+	cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT;
+
+	return 0;
+}
+
+static int vidioc_enum_fmt_vid_out(struct file *file, void *fh,
+			struct v4l2_fmtdesc *fmt)
+{
+	int index = fmt->index;
+	enum v4l2_buf_type type = fmt->type;
+
+	fmt->index = index;
+	fmt->type = type;
+	if (index >= NUM_OUTPUT_FORMATS)
+		return -EINVAL;
+
+	fmt->flags = omap_formats[index].flags;
+	strlcpy(fmt->description, omap_formats[index].description,
+			sizeof(fmt->description));
+	fmt->pixelformat = omap_formats[index].pixelformat;
+
+	return 0;
+}
+
+static int vidioc_g_fmt_vid_out(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	struct omap_vout_device *vout = fh;
+
+	f->fmt.pix = vout->pix;
+	return 0;
+
+}
+
+static int vidioc_try_fmt_vid_out(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	struct omap_overlay *ovl;
+	struct omapvideo_info *ovid;
+	struct omap_video_timings *timing;
+	struct omap_vout_device *vout = fh;
+
+	if (vout->streaming)
+		return -EBUSY;
+
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+
+	if (!ovl->manager || !ovl->manager->device)
+		return -EINVAL;
+	/* get the display device attached to the overlay */
+	timing = &ovl->manager->device->panel.timings;
+
+	vout->fbuf.fmt.height = timing->y_res;
+	vout->fbuf.fmt.width = timing->x_res;
+
+	omap_vout_try_format(&f->fmt.pix);
+	return 0;
+}
+
+static int vidioc_s_fmt_vid_out(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	int ret, bpp;
+	struct omap_overlay *ovl;
+	struct omapvideo_info *ovid;
+	struct omap_video_timings *timing;
+	struct omap_vout_device *vout = fh;
+
+	if (vout->streaming)
+		return -EBUSY;
+
+	mutex_lock(&vout->lock);
+
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+
+	/* get the display device attached to the overlay */
+	if (!ovl->manager || !ovl->manager->device) {
+		ret = -EINVAL;
+		goto s_fmt_vid_out_exit;
+	}
+	timing = &ovl->manager->device->panel.timings;
+
+	/* We dont support RGB24-packed mode if vrfb rotation
+	 * is enabled*/
+	if ((rotation_enabled(vout)) &&
+			f->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) {
+		ret = -EINVAL;
+		goto s_fmt_vid_out_exit;
+	}
+
+	/* get the framebuffer parameters */
+
+#ifndef CONFIG_ARCH_OMAP4
+	if (rotate_90_or_270(vout)) {
+		vout->fbuf.fmt.height = timing->x_res;
+		vout->fbuf.fmt.width = timing->y_res;
+	} else {
+#endif
+		vout->fbuf.fmt.height = timing->y_res;
+		vout->fbuf.fmt.width = timing->x_res;
+#ifndef CONFIG_ARCH_OMAP4
+	}
+#endif
+	/* change to samller size is OK */
+
+	bpp = omap_vout_try_format(&f->fmt.pix);
+	if (V4L2_PIX_FMT_NV12 == f->fmt.pix.pixelformat)
+		f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height * 3/2;
+	else
+		f->fmt.pix.sizeimage = f->fmt.pix.width *
+					f->fmt.pix.height * bpp;
+
+	/* try & set the new output format */
+	vout->bpp = bpp;
+	vout->pix = f->fmt.pix;
+	vout->vrfb_bpp = 1;
+
+	/* If YUYV then vrfb bpp is 2, for  others its 1 */
+	if (V4L2_PIX_FMT_YUYV == vout->pix.pixelformat ||
+			V4L2_PIX_FMT_UYVY == vout->pix.pixelformat)
+		vout->vrfb_bpp = 2;
+
+	/* set default crop and win */
+	omap_vout_new_format(&vout->pix, &vout->fbuf, &vout->crop, &vout->win);
+
+	/* Save the changes in the overlay strcuture */
+	ret = omapvid_init(vout, 0, 0);
+	if (ret) {
+		v4l2_err(&vout->vid_dev->v4l2_dev, "failed to change mode\n");
+		goto s_fmt_vid_out_exit;
+	}
+
+	ret = 0;
+
+s_fmt_vid_out_exit:
+	mutex_unlock(&vout->lock);
+	return ret;
+}
+
+static int vidioc_try_fmt_vid_overlay(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	int ret = 0;
+	struct omap_vout_device *vout = fh;
+	struct v4l2_window *win = &f->fmt.win;
+
+	ret = omap_vout_try_window(&vout->fbuf, win);
+
+	if (!ret) {
+		if (vout->vid == OMAP_VIDEO1)
+			win->global_alpha = 255;
+		else
+			win->global_alpha = f->fmt.win.global_alpha;
+	}
+
+	return ret;
+}
+
+static int vidioc_s_fmt_vid_overlay(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	int ret = 0;
+	struct omap_overlay *ovl;
+	struct omapvideo_info *ovid;
+	struct omap_vout_device *vout = fh;
+	struct v4l2_window *win = &f->fmt.win;
+
+	mutex_lock(&vout->lock);
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+
+	ret = omap_vout_new_window(&vout->crop, &vout->win, &vout->fbuf, win);
+	if (!ret) {
+		/* Video1 plane does not support global alpha for OMAP 2/3 */
+		if ((cpu_is_omap24xx() || cpu_is_omap34xx()) &&
+			    ovl->id == OMAP_DSS_VIDEO1)
+			vout->win.global_alpha = 255;
+		else
+			vout->win.global_alpha = f->fmt.win.global_alpha;
+
+		vout->win.chromakey = f->fmt.win.chromakey;
+	}
+	mutex_unlock(&vout->lock);
+	return ret;
+}
+
+static int vidioc_enum_fmt_vid_overlay(struct file *file, void *fh,
+			struct v4l2_fmtdesc *fmt)
+{
+	int index = fmt->index;
+	enum v4l2_buf_type type = fmt->type;
+
+	fmt->index = index;
+	fmt->type = type;
+	if (index >= NUM_OUTPUT_FORMATS)
+		return -EINVAL;
+
+	fmt->flags = omap_formats[index].flags;
+	strlcpy(fmt->description, omap_formats[index].description,
+			sizeof(fmt->description));
+	fmt->pixelformat = omap_formats[index].pixelformat;
+	return 0;
+}
+
+static int vidioc_g_fmt_vid_overlay(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	u32 key_value =  0;
+	struct omap_overlay *ovl;
+	struct omapvideo_info *ovid;
+	struct omap_vout_device *vout = fh;
+	struct omap_overlay_manager_info info;
+	struct v4l2_window *win = &f->fmt.win;
+
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+
+	win->w = vout->win.w;
+	win->field = vout->win.field;
+	win->global_alpha = vout->win.global_alpha;
+
+	if (ovl->manager && ovl->manager->get_manager_info) {
+		ovl->manager->get_manager_info(ovl->manager, &info);
+		key_value = info.trans_key;
+	}
+	win->chromakey = key_value;
+	return 0;
+}
+
+static int vidioc_cropcap(struct file *file, void *fh,
+		struct v4l2_cropcap *cropcap)
+{
+	struct omap_vout_device *vout = fh;
+	struct v4l2_pix_format *pix = &vout->pix;
+
+	if (cropcap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		return -EINVAL;
+
+	/* Width and height are always even */
+	cropcap->bounds.width = pix->width & ~1;
+	cropcap->bounds.height = pix->height & ~1;
+
+	omap_vout_default_crop(&vout->pix, &vout->fbuf, &cropcap->defrect);
+	cropcap->pixelaspect.numerator = 1;
+	cropcap->pixelaspect.denominator = 1;
+	return 0;
+}
+
+static int vidioc_g_crop(struct file *file, void *fh, struct v4l2_crop *crop)
+{
+	struct omap_vout_device *vout = fh;
+
+	if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		return -EINVAL;
+	crop->c = vout->crop;
+	return 0;
+}
+
+static int vidioc_s_crop(struct file *file, void *fh, struct v4l2_crop *crop)
+{
+	int ret = -EINVAL;
+	struct omap_vout_device *vout = fh;
+	struct omapvideo_info *ovid;
+	struct omap_overlay *ovl;
+	struct omap_video_timings *timing;
+
+	/* Currently we only allow changing the crop position while
+	   streaming.  */
+	if (vout->streaming &&
+	    (crop->c.height != vout->crop.height ||
+	     crop->c.width != vout->crop.width))
+		return -EBUSY;
+
+	mutex_lock(&vout->lock);
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+
+	if (!ovl->manager || !ovl->manager->device) {
+		ret = -EINVAL;
+		goto s_crop_err;
+	}
+	/* get the display device attached to the overlay */
+	timing = &ovl->manager->device->panel.timings;
+
+	if (rotate_90_or_270(vout)) {
+		vout->fbuf.fmt.height = timing->x_res;
+		vout->fbuf.fmt.width = timing->y_res;
+	} else {
+		vout->fbuf.fmt.height = timing->y_res;
+		vout->fbuf.fmt.width = timing->x_res;
+	}
+
+	if (crop->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		ret = omap_vout_new_crop(&vout->pix, &vout->crop, &vout->win,
+				&vout->fbuf, &crop->c);
+
+s_crop_err:
+	mutex_unlock(&vout->lock);
+	return ret;
+}
+
+static int vidioc_queryctrl(struct file *file, void *fh,
+		struct v4l2_queryctrl *ctrl)
+{
+	switch (ctrl->id) {
+	case V4L2_CID_ROTATE:
+		v4l2_ctrl_query_fill(ctrl, 0, 270, 90, 0);
+		break;
+	case V4L2_CID_BG_COLOR:
+		v4l2_ctrl_query_fill(ctrl, 0, 0xFFFFFF, 1, 0);
+		break;
+	case V4L2_CID_VFLIP:
+		v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0);
+	default:
+		ctrl->name[0] = '\0';
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int vidioc_g_ctrl(struct file *file, void *fh, struct v4l2_control *ctrl)
+{
+	struct omap_vout_device *vout = fh;
+
+	switch (ctrl->id) {
+	case V4L2_CID_ROTATE:
+		ctrl->value = vout->control[0].value;
+		return 0;
+	case V4L2_CID_BG_COLOR:
+	{
+		struct omap_overlay_manager_info info;
+		struct omap_overlay *ovl;
+		ovl = vout->vid_info.overlays[0];
+
+		if (!ovl->manager || !ovl->manager->get_manager_info)
+			return -EINVAL;
+
+		ovl->manager->get_manager_info(ovl->manager, &info);
+		ctrl->value = info.default_color;
+		return 0;
+	}
+	case V4L2_CID_VFLIP:
+		ctrl->value = vout->control[2].value;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int vidioc_s_ctrl(struct file *file, void *fh, struct v4l2_control *a)
+{
+	struct omap_vout_device *vout = fh;
+
+	switch (a->id) {
+	case V4L2_CID_ROTATE:
+	{
+		int rotation = a->value;
+
+		mutex_lock(&vout->lock);
+
+		if (rotation &&
+			vout->pix.pixelformat == V4L2_PIX_FMT_RGB24) {
+			mutex_unlock(&vout->lock);
+			return -EINVAL;
+		}
+
+		if ((v4l2_rot_to_dss_rot(rotation, &vout->rotation,
+				vout->mirror))) {
+			mutex_unlock(&vout->lock);
+			return -EINVAL;
+		}
+
+		vout->control[0].value = rotation;
+		mutex_unlock(&vout->lock);
+		return 0;
+	}
+	case V4L2_CID_BG_COLOR:
+	{
+		struct omap_overlay *ovl;
+		unsigned int  color = a->value;
+		struct omap_overlay_manager_info info;
+
+		ovl = vout->vid_info.overlays[0];
+
+		mutex_lock(&vout->lock);
+		if (!ovl->manager || !ovl->manager->get_manager_info) {
+			mutex_unlock(&vout->lock);
+			return -EINVAL;
+		}
+
+		ovl->manager->get_manager_info(ovl->manager, &info);
+		info.default_color = color;
+		if (ovl->manager->set_manager_info(ovl->manager, &info)) {
+			mutex_unlock(&vout->lock);
+			return -EINVAL;
+		}
+
+		vout->control[1].value = color;
+		mutex_unlock(&vout->lock);
+		return 0;
+	}
+	case V4L2_CID_VFLIP:
+	{
+		struct omap_overlay *ovl;
+		struct omapvideo_info *ovid;
+		unsigned int  mirror = a->value;
+
+		ovid = &vout->vid_info;
+		ovl = ovid->overlays[0];
+
+		mutex_lock(&vout->lock);
+
+		if (mirror  && vout->pix.pixelformat == V4L2_PIX_FMT_RGB24) {
+			mutex_unlock(&vout->lock);
+			return -EINVAL;
+		}
+		vout->mirror = mirror;
+		vout->control[2].value = mirror;
+		mutex_unlock(&vout->lock);
+		return 0;
+	}
+	case V4L2_CID_WB:
+	{
+		int enabled = a->value;
+		mutex_lock(&vout->lock);
+		if (enabled)
+			vout->wb_enabled = true;
+		else
+			vout->wb_enabled = false;
+		mutex_unlock(&vout->lock);
+		return 0;
+	}
+	default:
+		return -EINVAL;
+	}
+}
+
+static int vidioc_reqbufs(struct file *file, void *fh,
+			struct v4l2_requestbuffers *req)
+{
+	int ret = 0;
+	unsigned int i;
+#ifndef CONFIG_ARCH_OMAP4
+	unsigned int num_buffers = 0;
+#endif
+	struct omap_vout_device *vout = fh;
+	struct videobuf_queue *q = &vout->vbq;
+	struct videobuf_dmabuf *dmabuf = NULL;
+
+	if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || (req->count < 0))
+		return -EINVAL;
+	/* if memory is not mmp or userptr
+	   return error */
+	if ((V4L2_MEMORY_MMAP != req->memory) &&
+			(V4L2_MEMORY_USERPTR != req->memory))
+		return -EINVAL;
+
+	mutex_lock(&vout->lock);
+	/* Cannot be requested when streaming is on */
+	if (vout->streaming) {
+		ret = -EBUSY;
+		goto reqbuf_err;
+	}
+
+	/* If buffers are already allocated free them */
+	if (q->bufs[0] && (V4L2_MEMORY_MMAP == q->bufs[0]->memory)) {
+		if (vout->mmap_count) {
+			ret = -EBUSY;
+			goto reqbuf_err;
+		}
+#ifndef CONFIG_ARCH_OMAP4
+		num_buffers = (vout->vid == OMAP_VIDEO1) ?
+			video1_numbuffers : video2_numbuffers;
+		for (i = num_buffers; i < vout->buffer_allocated; i++) {
+			dmabuf = videobuf_to_dma(q->bufs[i]);
+			omap_vout_free_buffer((u32)dmabuf->vmalloc,
+				dmabuf->bus_addr, vout->buffer_size);
+			vout->buf_virt_addr[i] = 0;
+			vout->buf_phy_addr[i] = 0;
+		}
+		vout->buffer_allocated = num_buffers;
+#else
+		omap_vout_tiler_buffer_free(vout, vout->buffer_allocated, 0);
+		vout->buffer_allocated = 0;
+#endif
+		videobuf_mmap_free(q);
+	} else if (q->bufs[0] && (V4L2_MEMORY_USERPTR == q->bufs[0]->memory)) {
+		if (vout->buffer_allocated) {
+			videobuf_mmap_free(q);
+			for (i = 0; i < vout->buffer_allocated; i++) {
+				kfree(q->bufs[i]);
+				q->bufs[i] = NULL;
+			}
+			vout->buffer_allocated = 0;
+		}
+	}
+
+	/*store the memory type in data structure */
+	vout->memory = req->memory;
+
+	INIT_LIST_HEAD(&vout->dma_queue);
+
+	/* call videobuf_reqbufs api */
+	ret = videobuf_reqbufs(q, req);
+	if (ret < 0)
+		goto reqbuf_err;
+
+	vout->buffer_allocated = req->count;
+	for (i = 0; i < req->count; i++) {
+		dmabuf = videobuf_to_dma(q->bufs[i]);
+#ifndef CONFIG_ARCH_OMAP4
+		dmabuf->vmalloc = (void *) vout->buf_virt_addr[i];
+#else
+		if (V4L2_PIX_FMT_NV12 == vout->pix.pixelformat)
+			dmabuf->vmalloc = (void *) vout->buf_phy_uv_addr[i];
+			/* dmabuf->vmalloc = (void *) omapvid_get_uvbase_nv12(
+							vout->buf_phy_addr[i],
+							vout->pix.height,
+							vout->pix.width); */
+						 /* Used for non Tiler NV12 */
+
+		else
+			dmabuf->vmalloc = NULL;
+#endif
+		dmabuf->bus_addr = (dma_addr_t) vout->buf_phy_addr[i];
+		dmabuf->sglen = 1;
+	}
+reqbuf_err:
+	mutex_unlock(&vout->lock);
+	return ret;
+}
+
+static int vidioc_querybuf(struct file *file, void *fh,
+			struct v4l2_buffer *b)
+{
+	struct omap_vout_device *vout = fh;
+
+	return videobuf_querybuf(&vout->vbq, b);
+}
+
+static int vidioc_qbuf(struct file *file, void *fh,
+			struct v4l2_buffer *buffer)
+{
+	struct omap_vout_device *vout = fh;
+	struct videobuf_queue *q = &vout->vbq;
+	int ret = 0;
+	u32 addr = 0, uv_addr = 0;
+
+	if ((V4L2_BUF_TYPE_VIDEO_OUTPUT != buffer->type) ||
+			(buffer->index >= vout->buffer_allocated) ||
+			(q->bufs[buffer->index]->memory != buffer->memory)) {
+		return -EINVAL;
+	}
+	if (V4L2_MEMORY_USERPTR == buffer->memory) {
+		if ((buffer->length < vout->pix.sizeimage) ||
+				(0 == buffer->m.userptr)) {
+			return -EINVAL;
+		}
+	}
+
+#ifndef CONFIG_ARCH_OMAP4
+	if ((rotation_enabled(vout)) &&
+			vout->vrfb_dma_tx.req_status == DMA_CHAN_NOT_ALLOTED) {
+		v4l2_warn(&vout->vid_dev->v4l2_dev,
+				"DMA Channel not allocated for Rotation\n");
+		return -EINVAL;
+	}
+#endif
+	ret = videobuf_qbuf(q, buffer);
+	/* record buffer offset from crop window */
+	if (omap_vout_calculate_offset(vout, buffer->index)) {
+		printk(KERN_ERR "Could not calculate buffer offset\n");
+		return -EINVAL;
+	}
+	if (vout->wb_enabled && vout->streaming && vout->buf_empty) {
+		addr = (unsigned long) vout->queued_buf_addr[vout->cur_frm->i]
+			+ vout->cropped_offset[vout->cur_frm->i];
+		uv_addr = (unsigned long) vout->queued_buf_uv_addr[vout->cur_frm->i]
+			+ vout->cropped_uv_offset[vout->cur_frm->i];
+		vout->buf_empty = false;
+		omapvid_init(vout, addr, uv_addr);
+	}
+	return ret;
+}
+
+static int vidioc_dqbuf(struct file *file, void *fh,
+			struct v4l2_buffer *b)
+{
+	struct omap_vout_device *vout = fh;
+	struct videobuf_queue *q = &vout->vbq;
+
+	if (!vout->streaming)
+		return -EINVAL;
+
+	if (file->f_flags & O_NONBLOCK)
+		/* Call videobuf_dqbuf for non blocking mode */
+		return videobuf_dqbuf(q, (struct v4l2_buffer *)b, 1);
+	else
+		/* Call videobuf_dqbuf for  blocking mode */
+		return videobuf_dqbuf(q, (struct v4l2_buffer *)b, 0);
+}
+
+static int vidioc_streamon(struct file *file, void *fh,
+			enum v4l2_buf_type i)
+{
+	int ret = 0, j;
+	u32 addr = 0, mask = 0;
+	u32 uv_addr = 0;
+	struct omap_vout_device *vout = fh;
+	struct videobuf_queue *q = &vout->vbq;
+	struct omapvideo_info *ovid = &vout->vid_info;
+
+	mutex_lock(&vout->lock);
+
+	if (vout->streaming) {
+		ret = -EBUSY;
+		goto streamon_err;
+	}
+
+	ret = videobuf_streamon(q);
+	if (ret < 0)
+		goto streamon_err;
+
+	if (list_empty(&vout->dma_queue)) {
+		ret = -EIO;
+		goto streamon_err;
+	}
+	/* Get the next frame from the buffer queue */
+	vout->next_frm = vout->cur_frm = list_entry(vout->dma_queue.next,
+			struct videobuf_buffer, queue);
+	/* Remove buffer from the buffer queue */
+	list_del(&vout->cur_frm->queue);
+	/* Mark state of the current frame to active */
+	vout->cur_frm->state = VIDEOBUF_ACTIVE;
+	/* Initialize field_id and started member */
+	vout->field_id = 0;
+
+	/* set flag here. Next QBUF will start DMA */
+	vout->streaming = 1;
+
+	vout->first_int = 1;
+
+	addr = (unsigned long) vout->queued_buf_addr[vout->cur_frm->i]
+		+ vout->cropped_offset[vout->cur_frm->i];
+	uv_addr = (unsigned long) vout->queued_buf_uv_addr[vout->cur_frm->i]
+		+ vout->cropped_uv_offset[vout->cur_frm->i];
+
+	mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN |
+			DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_FRAMEDONE |
+			DISPC_IRQ_FRAMEDONE2 | DISPC_IRQ_VSYNC2;
+
+	if (vout->wb_enabled)
+		mask |= DISPC_IRQ_FRAMEDONE_WB;
+
+	omap_dispc_register_isr(omap_vout_isr, vout, mask);
+
+	for (j = 0; j < ovid->num_overlays; j++) {
+		struct omap_overlay *ovl = ovid->overlays[j];
+		if (ovl->manager && ovl->manager->device) {
+			struct omap_overlay_info info;
+			ovl->get_overlay_info(ovl, &info);
+			info.enabled = 1;
+			info.paddr = addr;
+			info.p_uv_addr = uv_addr;
+			if (ovl->set_overlay_info(ovl, &info)) {
+				ret = -EINVAL;
+				goto streamon_err;
+			}
+		}
+	}
+
+	/* First save the configuration in ovelray structure */
+	ret = omapvid_init(vout, addr, uv_addr);
+	if (ret)
+		v4l2_err(&vout->vid_dev->v4l2_dev,
+				"failed to set overlay info\n");
+	if (!vout->wb_enabled) {
+		/* Enable the pipeline and set the Go bit */
+		ret = omapvid_apply_changes(vout);
+		if (ret)
+			v4l2_err(&vout->vid_dev->v4l2_dev, "failed to change mode\n");
+	}
+	ret = 0;
+
+streamon_err:
+	mutex_unlock(&vout->lock);
+	return ret;
+}
+
+static int vidioc_streamoff(struct file *file, void *fh,
+			enum v4l2_buf_type i)
+{
+	u32 mask = 0;
+	int ret = 0, j;
+	struct omap_vout_device *vout = fh;
+	struct omapvideo_info *ovid = &vout->vid_info;
+
+	if (!vout->streaming)
+		return -EINVAL;
+
+	vout->streaming = 0;
+	mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN |
+			DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_FRAMEDONE |
+			DISPC_IRQ_FRAMEDONE2 | DISPC_IRQ_VSYNC2;
+
+	if (vout->wb_enabled)
+			mask |= DISPC_IRQ_FRAMEDONE_WB;
+
+	omap_dispc_unregister_isr(omap_vout_isr, vout, mask);
+
+	for (j = 0; j < ovid->num_overlays; j++) {
+		struct omap_overlay *ovl = ovid->overlays[j];
+		if (ovl->manager && ovl->manager->device) {
+			struct omap_overlay_info info;
+
+			ovl->get_overlay_info(ovl, &info);
+			info.enabled = 0;
+			ret = ovl->set_overlay_info(ovl, &info);
+			if (ret) {
+				v4l2_err(&vout->vid_dev->v4l2_dev,
+					"failed to update overlay info\n");
+				return ret;
+			}
+		}
+	}
+
+	/* Turn of the pipeline */
+	ret = omapvid_apply_changes(vout);
+	if (ret) {
+		v4l2_err(&vout->vid_dev->v4l2_dev, "failed to change mode\n");
+		return ret;
+	}
+	INIT_LIST_HEAD(&vout->dma_queue);
+	videobuf_streamoff(&vout->vbq);
+	videobuf_queue_cancel(&vout->vbq);
+
+	return 0;
+}
+
+static int vidioc_s_fbuf(struct file *file, void *fh,
+				struct v4l2_framebuffer *a)
+{
+	int enable = 0;
+	struct omap_overlay *ovl;
+	struct omapvideo_info *ovid;
+	struct omap_vout_device *vout = fh;
+	struct omap_overlay_manager_info info;
+	enum omap_dss_trans_key_type key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
+
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+
+	/* OMAP DSS doesn't support Source and Destination color
+	   key together */
+	if ((a->flags & V4L2_FBUF_FLAG_SRC_CHROMAKEY) &&
+			(a->flags & V4L2_FBUF_FLAG_CHROMAKEY))
+		return -EINVAL;
+	/* OMAP DSS Doesn't support the Destination color key
+	   and alpha blending together */
+	if ((a->flags & V4L2_FBUF_FLAG_CHROMAKEY) &&
+			(a->flags & V4L2_FBUF_FLAG_LOCAL_ALPHA))
+		return -EINVAL;
+
+	if ((a->flags & V4L2_FBUF_FLAG_SRC_CHROMAKEY)) {
+		vout->fbuf.flags |= V4L2_FBUF_FLAG_SRC_CHROMAKEY;
+		key_type =  OMAP_DSS_COLOR_KEY_VID_SRC;
+	} else
+		vout->fbuf.flags &= ~V4L2_FBUF_FLAG_SRC_CHROMAKEY;
+
+	if ((a->flags & V4L2_FBUF_FLAG_CHROMAKEY)) {
+		vout->fbuf.flags |= V4L2_FBUF_FLAG_CHROMAKEY;
+		key_type =  OMAP_DSS_COLOR_KEY_GFX_DST;
+	} else
+		vout->fbuf.flags &=  ~V4L2_FBUF_FLAG_CHROMAKEY;
+
+	if (a->flags & (V4L2_FBUF_FLAG_CHROMAKEY |
+				V4L2_FBUF_FLAG_SRC_CHROMAKEY))
+		enable = 1;
+	else
+		enable = 0;
+	if (ovl->manager && ovl->manager->get_manager_info &&
+			ovl->manager->set_manager_info) {
+
+		ovl->manager->get_manager_info(ovl->manager, &info);
+		info.trans_enabled = enable;
+		info.trans_key_type = key_type;
+		info.trans_key = vout->win.chromakey;
+
+		if (ovl->manager->set_manager_info(ovl->manager, &info))
+			return -EINVAL;
+	}
+	if (a->flags & V4L2_FBUF_FLAG_LOCAL_ALPHA) {
+		vout->fbuf.flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA;
+		enable = 1;
+	} else {
+		vout->fbuf.flags &= ~V4L2_FBUF_FLAG_LOCAL_ALPHA;
+		enable = 0;
+	}
+	if (ovl->manager && ovl->manager->get_manager_info &&
+			ovl->manager->set_manager_info) {
+		ovl->manager->get_manager_info(ovl->manager, &info);
+		info.alpha_enabled = enable;
+		if (ovl->manager->set_manager_info(ovl->manager, &info))
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int vidioc_g_fbuf(struct file *file, void *fh,
+		struct v4l2_framebuffer *a)
+{
+	struct omap_overlay *ovl;
+	struct omapvideo_info *ovid;
+	struct omap_vout_device *vout = fh;
+	struct omap_overlay_manager_info info;
+
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+
+	a->flags = 0x0;
+	a->capability = V4L2_FBUF_CAP_LOCAL_ALPHA | V4L2_FBUF_CAP_CHROMAKEY
+		| V4L2_FBUF_CAP_SRC_CHROMAKEY;
+
+	if (ovl->manager && ovl->manager->get_manager_info) {
+		ovl->manager->get_manager_info(ovl->manager, &info);
+		if (info.trans_key_type == OMAP_DSS_COLOR_KEY_VID_SRC)
+			a->flags |= V4L2_FBUF_FLAG_SRC_CHROMAKEY;
+		if (info.trans_key_type == OMAP_DSS_COLOR_KEY_GFX_DST)
+			a->flags |= V4L2_FBUF_FLAG_CHROMAKEY;
+	}
+	if (ovl->manager && ovl->manager->get_manager_info) {
+		ovl->manager->get_manager_info(ovl->manager, &info);
+		if (info.alpha_enabled)
+			a->flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA;
+	}
+
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops vout_ioctl_ops = {
+	.vidioc_querycap      			= vidioc_querycap,
+	.vidioc_enum_fmt_vid_out 		= vidioc_enum_fmt_vid_out,
+	.vidioc_g_fmt_vid_out			= vidioc_g_fmt_vid_out,
+	.vidioc_try_fmt_vid_out			= vidioc_try_fmt_vid_out,
+	.vidioc_s_fmt_vid_out			= vidioc_s_fmt_vid_out,
+	.vidioc_queryctrl    			= vidioc_queryctrl,
+	.vidioc_g_ctrl       			= vidioc_g_ctrl,
+	.vidioc_s_fbuf				= vidioc_s_fbuf,
+	.vidioc_g_fbuf				= vidioc_g_fbuf,
+	.vidioc_s_ctrl       			= vidioc_s_ctrl,
+	.vidioc_try_fmt_vid_overlay 		= vidioc_try_fmt_vid_overlay,
+	.vidioc_s_fmt_vid_overlay		= vidioc_s_fmt_vid_overlay,
+	.vidioc_enum_fmt_vid_overlay		= vidioc_enum_fmt_vid_overlay,
+	.vidioc_g_fmt_vid_overlay		= vidioc_g_fmt_vid_overlay,
+	.vidioc_cropcap				= vidioc_cropcap,
+	.vidioc_g_crop				= vidioc_g_crop,
+	.vidioc_s_crop				= vidioc_s_crop,
+	.vidioc_reqbufs				= vidioc_reqbufs,
+	.vidioc_querybuf			= vidioc_querybuf,
+	.vidioc_qbuf				= vidioc_qbuf,
+	.vidioc_dqbuf				= vidioc_dqbuf,
+	.vidioc_streamon			= vidioc_streamon,
+	.vidioc_streamoff			= vidioc_streamoff,
+};
+
+static const struct v4l2_file_operations omap_vout_fops = {
+	.owner 		= THIS_MODULE,
+	.ioctl 		= video_ioctl2,
+	.mmap 		= omap_vout_mmap,
+	.open 		= omap_vout_open,
+	.release 	= omap_vout_release,
+};
+
+/* Init functions used during driver intitalization */
+/* Initial setup of video_data */
+static int __init omap_vout_setup_video_data(struct omap_vout_device *vout)
+{
+	struct video_device *vfd;
+	struct v4l2_pix_format *pix;
+	struct v4l2_control *control;
+	struct omap_dss_device *display =
+		vout->vid_info.overlays[0]->manager->device;
+
+	/* set the default pix */
+	pix = &vout->pix;
+
+	/* Set the default picture of QVGA  */
+	pix->width = QQVGA_WIDTH;
+	pix->height = QQVGA_HEIGHT;
+
+	/* Default pixel format is RGB 5-6-5 */
+	pix->pixelformat = V4L2_PIX_FMT_RGB565;
+	pix->field = V4L2_FIELD_ANY;
+	pix->bytesperline = pix->width * 2;
+	pix->sizeimage = pix->bytesperline * pix->height;
+	pix->priv = 0;
+	pix->colorspace = V4L2_COLORSPACE_JPEG;
+
+	vout->bpp = RGB565_BPP;
+	vout->fbuf.fmt.width  =  display->panel.timings.x_res;
+	vout->fbuf.fmt.height =  display->panel.timings.y_res;
+
+	/* Set the data structures for the overlay parameters*/
+	vout->win.global_alpha = 255;
+	vout->fbuf.flags = 0;
+	vout->fbuf.capability = V4L2_FBUF_CAP_LOCAL_ALPHA |
+		V4L2_FBUF_CAP_SRC_CHROMAKEY | V4L2_FBUF_CAP_CHROMAKEY;
+	vout->win.chromakey = 0;
+
+	omap_vout_new_format(pix, &vout->fbuf, &vout->crop, &vout->win);
+
+	/*Initialize the control variables for
+	  rotation, flipping and background color. */
+	control = vout->control;
+	control[0].id = V4L2_CID_ROTATE;
+	control[0].value = 0;
+	vout->rotation = 0;
+	vout->mirror = 0;
+	vout->control[2].id = V4L2_CID_HFLIP;
+	vout->control[2].value = 0;
+	vout->vrfb_bpp = 2;
+
+	control[1].id = V4L2_CID_BG_COLOR;
+	control[1].value = 0;
+
+	/* initialize the video_device struct */
+	vfd = vout->vfd = video_device_alloc();
+
+	if (!vfd) {
+		printk(KERN_ERR VOUT_NAME ": could not allocate"
+				" video device struct\n");
+		return -ENOMEM;
+	}
+	vfd->release = video_device_release;
+	vfd->ioctl_ops = &vout_ioctl_ops;
+
+	strlcpy(vfd->name, VOUT_NAME, sizeof(vfd->name));
+	vfd->vfl_type = VFL_TYPE_GRABBER;
+
+	/* need to register for a VID_HARDWARE_* ID in videodev.h */
+	vfd->fops = &omap_vout_fops;
+	mutex_init(&vout->lock);
+
+	vfd->minor = -1;
+	return 0;
+
+}
+
+/* Setup video buffers */
+static int __init omap_vout_setup_video_bufs(struct platform_device *pdev,
+		int vid_num)
+{
+#ifndef CONFIG_ARCH_OMAP4
+	u32 numbuffers;
+	int ret = 0, i, j;
+	int image_width, image_height;
+#endif
+	struct video_device *vfd;
+	struct omap_vout_device *vout;
+#ifndef CONFIG_ARCH_OMAP4
+	int static_vrfb_allocation = 0, vrfb_num_bufs = 4;
+#endif
+	struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
+	struct omap2video_device *vid_dev =
+		container_of(v4l2_dev, struct omap2video_device, v4l2_dev);
+
+	vout = vid_dev->vouts[vid_num];
+	vfd = vout->vfd;
+
+#ifndef CONFIG_ARCH_OMAP4
+	numbuffers = (vid_num == 0) ? video1_numbuffers : video2_numbuffers;
+	vout->buffer_size = (vid_num == 0) ? video1_bufsize : video2_bufsize;
+	dev_info(&pdev->dev, "Buffer Size = %d\n", vout->buffer_size);
+
+	for (i = 0; i < numbuffers; i++) {
+		vout->buf_virt_addr[i] =
+			omap_vout_alloc_buffer(vout->buffer_size,
+					(u32 *) &vout->buf_phy_addr[i]);
+		if (!vout->buf_virt_addr[i]) {
+			numbuffers = i;
+			ret = -ENOMEM;
+			goto free_buffers;
+		}
+	}
+	for (i = 0; i < 4; i++) {
+		if (omap_vrfb_request_ctx(&vout->vrfb_context[i])) {
+			dev_info(&pdev->dev, ": VRFB allocation failed\n");
+			for (j = 0; j < i; j++)
+				omap_vrfb_release_ctx(&vout->vrfb_context[j]);
+			ret = -ENOMEM;
+			goto free_buffers;
+		}
+	}
+	vout->cropped_offset = 0;
+
+	/* Calculate VRFB memory size */
+	/* allocate for worst case size */
+	image_width = VID_MAX_WIDTH / TILE_SIZE;
+	if (VID_MAX_WIDTH % TILE_SIZE)
+		image_width++;
+
+	image_width = image_width * TILE_SIZE;
+	image_height = VID_MAX_HEIGHT / TILE_SIZE;
+
+	if (VID_MAX_HEIGHT % TILE_SIZE)
+		image_height++;
+
+	image_height = image_height * TILE_SIZE;
+	vout->smsshado_size = PAGE_ALIGN(image_width * image_height * 2 * 2);
+
+	/*
+	 * Request and Initialize DMA, for DMA based VRFB transfer
+	 */
+	vout->vrfb_dma_tx.dev_id = OMAP_DMA_NO_DEVICE;
+	vout->vrfb_dma_tx.dma_ch = -1;
+	vout->vrfb_dma_tx.req_status = DMA_CHAN_ALLOTED;
+	ret = omap_request_dma(vout->vrfb_dma_tx.dev_id, "VRFB DMA TX",
+			omap_vout_vrfb_dma_tx_callback,
+			(void *) &vout->vrfb_dma_tx, &vout->vrfb_dma_tx.dma_ch);
+	if (ret < 0) {
+		vout->vrfb_dma_tx.req_status = DMA_CHAN_NOT_ALLOTED;
+		dev_info(&pdev->dev, ": failed to allocate DMA Channel for"
+				" video%d\n", vfd->minor);
+	}
+	init_waitqueue_head(&vout->vrfb_dma_tx.wait);
+
+	/* Allocate VRFB buffers if selected through bootargs */
+	static_vrfb_allocation = (vid_num == 0) ?
+		vid1_static_vrfb_alloc : vid2_static_vrfb_alloc;
+
+	/* statically allocated the VRFB buffer is done through
+	   commands line aruments */
+	if (static_vrfb_allocation) {
+		if (omap_vout_allocate_vrfb_buffers(vout, &vrfb_num_bufs, -1)) {
+			ret =  -ENOMEM;
+			goto release_vrfb_ctx;;
+		}
+		vout->vrfb_static_allocation = 1;
+	}
+	return 0;
+
+release_vrfb_ctx:
+	for (j = 0; j < 4; j++)
+		omap_vrfb_release_ctx(&vout->vrfb_context[j]);
+
+free_buffers:
+	for (i = 0; i < numbuffers; i++) {
+		omap_vout_free_buffer(vout->buf_virt_addr[i],
+				vout->buf_phy_addr[i], vout->buffer_size);
+		vout->buf_virt_addr[i] = 0;
+		vout->buf_phy_addr[i] = 0;
+	}
+	return ret;
+#endif
+
+	/* NOTE: OMAP4, if TILER allocation, then nothing to pre-allocate */
+	return 0;
+}
+
+/* Create video out devices */
+static int __init omap_vout_create_video_devices(struct platform_device *pdev)
+{
+	int ret = 0, k;
+	struct omap_vout_device *vout;
+	struct video_device *vfd = NULL;
+	struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
+
+	struct omap2video_device *vid_dev = container_of(v4l2_dev,
+			struct omap2video_device, v4l2_dev);
+
+	for (k = 0; k < pdev->num_resources; k++) {
+
+		vout = kmalloc(sizeof(struct omap_vout_device), GFP_KERNEL);
+		if (!vout) {
+			dev_err(&pdev->dev, ": could not allocate memory\n");
+			return -ENOMEM;
+		}
+		memset(vout, 0, sizeof(struct omap_vout_device));
+
+		vout->vid = k;
+		vid_dev->vouts[k] = vout;
+		vout->vid_dev = vid_dev;
+		/* Select video2 if only 1 overlay is controlled by V4L2 */
+		if (!cpu_is_omap44xx()) {
+			if (pdev->num_resources == 1)
+				vout->vid_info.overlays[0] = vid_dev->overlays[k + 2];
+			else
+			/* Else select video1 and video2 one by one. */
+				vout->vid_info.overlays[0] = vid_dev->overlays[k + 1];
+		} else {
+			vout->vid_info.overlays[0] =
+				vid_dev->overlays[
+					k + (4 - pdev->num_resources)];
+		}
+		vout->vid_info.num_overlays = 1;
+		vout->vid_info.id = k + 1;
+		vid_dev->num_videos++;
+
+		/* Setup the default configuration for the video devices
+		 */
+		if (omap_vout_setup_video_data(vout) != 0) {
+			ret = -ENOMEM;
+			goto error;
+		}
+
+		/* Allocate default number of buffers for the video streaming
+		 * and reserve the VRFB space for rotation
+		 */
+		if (omap_vout_setup_video_bufs(pdev, k) != 0) {
+			ret = -ENOMEM;
+			goto error1;
+		}
+
+		/* Register the Video device with V4L2
+		 */
+		vfd = vout->vfd;
+		if (video_register_device(vfd, VFL_TYPE_GRABBER, k + 1) < 0) {
+			dev_err(&pdev->dev, ": Could not register "
+					"Video for Linux device\n");
+			vfd->minor = -1;
+			ret = -ENODEV;
+			goto error2;
+		}
+		video_set_drvdata(vfd, vout);
+
+		/* Configure the overlay structure */
+		ret = omapvid_init(vid_dev->vouts[k], 0, 0);
+		if (!ret)
+			goto success;
+
+error2:
+#ifndef CONFIG_ARCH_OMAP4
+		omap_vout_release_vrfb(vout);
+#endif
+		omap_vout_free_buffers(vout);
+error1:
+		video_device_release(vfd);
+error:
+		kfree(vout);
+		return ret;
+
+success:
+		dev_info(&pdev->dev, ": registered and initialized"
+				" video device %d\n", vfd->minor);
+		if (k == (pdev->num_resources - 1))
+			return 0;
+	}
+
+	return -ENODEV;
+}
+/* Driver functions */
+static int omap_vout_remove(struct platform_device *pdev)
+{
+	int k;
+	struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
+	struct omap2video_device *vid_dev = container_of(v4l2_dev, struct
+			omap2video_device, v4l2_dev);
+
+	v4l2_device_unregister(v4l2_dev);
+	for (k = 0; k < pdev->num_resources; k++)
+		omap_vout_cleanup_device(vid_dev->vouts[k]);
+
+	for (k = 0; k < vid_dev->num_displays; k++) {
+		if (vid_dev->displays[k]->state != OMAP_DSS_DISPLAY_DISABLED)
+			vid_dev->displays[k]->driver->disable(vid_dev->displays[k]);
+
+		omap_dss_put_device(vid_dev->displays[k]);
+	}
+	kfree(vid_dev);
+	return 0;
+}
+
+static int __init omap_vout_probe(struct platform_device *pdev)
+{
+	int ret = 0, i;
+	struct omap_overlay *ovl;
+	struct omap_dss_device *dssdev = NULL;
+	struct omap_dss_device *def_display;
+	struct omap2video_device *vid_dev = NULL;
+	int num_vid_channels;
+
+	if (pdev->num_resources == 0) {
+		dev_err(&pdev->dev, "probed for an unknown device\n");
+		return -ENODEV;
+	}
+
+	vid_dev = kzalloc(sizeof(struct omap2video_device), GFP_KERNEL);
+	if (vid_dev == NULL)
+		return -ENOMEM;
+
+	vid_dev->num_displays = 0;
+	for_each_dss_dev(dssdev) {
+		omap_dss_get_device(dssdev);
+		vid_dev->displays[vid_dev->num_displays++] = dssdev;
+	}
+
+	if (vid_dev->num_displays == 0) {
+		dev_err(&pdev->dev, "no displays\n");
+		ret = -EINVAL;
+		goto probe_err0;
+	}
+
+	vid_dev->num_overlays = omap_dss_get_num_overlays();
+	for (i = 0; i < vid_dev->num_overlays; i++)
+		vid_dev->overlays[i] = omap_dss_get_overlay(i);
+
+	vid_dev->num_managers = omap_dss_get_num_overlay_managers();
+	for (i = 0; i < vid_dev->num_managers; i++)
+		vid_dev->managers[i] = omap_dss_get_overlay_manager(i);
+
+	/* Get the Video1 overlay and video2 overlay.
+	 * Setup the Display attached to that overlays
+	 */
+	num_vid_channels = (cpu_is_omap44xx()) ? 3 : 2;
+
+	for (i = 1; i < num_vid_channels + 1; i++) {
+		ovl = omap_dss_get_overlay(i);
+		if (ovl->manager && ovl->manager->device) {
+			def_display = ovl->manager->device;
+		} else {
+			dev_warn(&pdev->dev, "cannot find display\n");
+			def_display = NULL;
+		}
+		if (def_display) {
+			struct omap_dss_driver *dssdrv = def_display->driver;
+
+			ret = dssdrv->enable(def_display);
+			if (ret) {
+				/* Here we are not considering a error
+				 *  as display may be enabled by frame
+				 *  buffer driver
+				 */
+				dev_warn(&pdev->dev,
+					"'%s' Display already enabled\n",
+					def_display->name);
+			}
+			/* set the update mode */
+			if (def_display->caps &
+					OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
+#ifdef CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE
+				if (dssdrv->enable_te)
+					dssdrv->enable_te(def_display, 1);
+				if (dssdrv->set_update_mode)
+					dssdrv->set_update_mode(def_display,
+							OMAP_DSS_UPDATE_AUTO);
+#else	/* MANUAL_UPDATE */
+				if (dssdrv->enable_te)
+					dssdrv->enable_te(def_display, 1);
+				if (dssdrv->set_update_mode)
+					dssdrv->set_update_mode(def_display,
+							OMAP_DSS_UPDATE_MANUAL);
+#endif
+			} else {
+				if (dssdrv->set_update_mode)
+					dssdrv->set_update_mode(def_display,
+							OMAP_DSS_UPDATE_AUTO);
+			}
+		}
+	}
+
+	if (v4l2_device_register(&pdev->dev, &vid_dev->v4l2_dev) < 0) {
+		dev_err(&pdev->dev, "v4l2_device_register failed\n");
+		ret = -ENODEV;
+		goto probe_err1;
+	}
+
+	ret = omap_vout_create_video_devices(pdev);
+	if (ret)
+		goto probe_err2;
+
+#if 0 /* Auto update feature not available */
+	for (i = 0; i < vid_dev->num_displays; i++) {
+		struct omap_dss_device *display = vid_dev->displays[i];
+
+		if (display->driver->update)
+			display->driver->update(display, 0, 0,
+					display->panel.timings.x_res,
+					display->panel.timings.y_res);
+	}
+#endif
+	return 0;
+
+probe_err2:
+	v4l2_device_unregister(&vid_dev->v4l2_dev);
+probe_err1:
+	for (i = 1; i < 3; i++) {
+		def_display = NULL;
+		ovl = omap_dss_get_overlay(i);
+		if (ovl->manager && ovl->manager->device)
+			def_display = ovl->manager->device;
+
+		if (def_display && def_display->driver)
+			def_display->driver->disable(def_display);
+	}
+probe_err0:
+	kfree(vid_dev);
+	return ret;
+}
+
+static struct platform_driver omap_vout_driver = {
+	.driver = {
+		.name = VOUT_NAME,
+	},
+	.probe = omap_vout_probe,
+	.remove = omap_vout_remove,
+};
+
+void omap_vout_isr(void *arg, unsigned int irqstatus)
+{
+	int ret;
+	u32 addr, fid;
+	u32 uv_addr;
+	struct omap_overlay *ovl;
+	struct timeval timevalue;
+	struct omapvideo_info *ovid;
+	struct omap_dss_device *cur_display;
+	struct omap_vout_device *vout = (struct omap_vout_device *)arg;
+	int irq = 0;
+	u32 flags;
+#if !(CONFIG_OMAP2_DSS_HDMI)
+	u32 fid;
+#endif
+	if (!vout->streaming)
+		return;
+
+	if (vout->wb_enabled) {
+		if ((irqstatus &  DISPC_IRQ_GFX_END_WIN) &&
+			!(irqstatus &  DISPC_IRQ_FRAMEDONE_WB))
+			return;
+	}
+	ovid = &vout->vid_info;
+	ovl = ovid->overlays[0];
+	/* get the display device attached to the overlay */
+	if (!ovl->manager || !ovl->manager->device)
+		return;
+	cur_display = ovl->manager->device;
+
+	if (cur_display->channel == OMAP_DSS_CHANNEL_LCD)
+		irq = DISPC_IRQ_FRAMEDONE;
+	else if (cur_display->channel == OMAP_DSS_CHANNEL_LCD2)
+		irq = DISPC_IRQ_FRAMEDONE2;
+	spin_lock_irqsave(&vout->vbq_lock, flags);
+	do_gettimeofday(&timevalue);
+
+	if (vout->wb_enabled &&
+		(irqstatus & DISPC_IRQ_FRAMEDONE_WB))
+		goto wb;
+
+	switch (cur_display->type) {
+
+	case OMAP_DISPLAY_TYPE_DSI:
+		if (!(irqstatus & irq))
+			goto vout_isr_err;
+		break;
+
+	case OMAP_DISPLAY_TYPE_DPI:
+		if (!(irqstatus & (DISPC_IRQ_VSYNC | DISPC_IRQ_VSYNC2)))
+			goto vout_isr_err;
+#ifdef CONFIG_PANEL_PICO_DLP
+		if (dispc_go_busy(OMAP_DSS_CHANNEL_LCD2)) {
+			printk(KERN_INFO "dpi busy %d\n", cur_display->type);
+			goto vout_isr_err;
+		}
+#endif
+		break;
+#if CONFIG_OMAP2_DSS_HDMI
+	case OMAP_DISPLAY_TYPE_HDMI:
+		if (!(irqstatus & DISPC_IRQ_EVSYNC_EVEN))
+			goto vout_isr_err;
+
+		break;
+#else
+	case OMAP_DISPLAY_TYPE_VENC:
+		if (vout->first_int) {
+			vout->first_int = 0;
+			goto vout_isr_err;
+		}
+		if (irqstatus & DISPC_IRQ_EVSYNC_ODD)
+			fid = 1;
+		else if (irqstatus & DISPC_IRQ_EVSYNC_EVEN)
+			fid = 0;
+		else
+			goto vout_isr_err;
+		fid = 1;
+		vout->field_id ^= 1;
+		if (fid != vout->field_id) {
+			if (0 == fid)
+				vout->field_id = fid;
+
+			goto vout_isr_err;
+		}
+		if (0 == fid) {
+			if (vout->cur_frm == vout->next_frm)
+				goto vout_isr_err;
+			vout->cur_frm->ts = timevalue;
+			vout->cur_frm->state = VIDEOBUF_DONE;
+			wake_up_interruptible(&vout->cur_frm->done);
+			vout->cur_frm = vout->next_frm;
+			goto vout_isr_err;
+		} else if (1 == fid) {
+			if (list_empty(&vout->dma_queue) ||
+			    (vout->cur_frm != vout->next_frm)) {
+				goto vout_isr_err;
+			}
+			goto venc;
+		}
+#endif
+	default:
+		goto vout_isr_err;
+	}
+wb:
+	if (!vout->first_int && (vout->cur_frm != vout->next_frm)) {
+		vout->cur_frm->ts = timevalue;
+		vout->cur_frm->state = VIDEOBUF_DONE;
+		wake_up_interruptible(&vout->cur_frm->done);
+		vout->cur_frm = vout->next_frm;
+		}
+
+	vout->first_int = 0;
+
+	if (list_empty(&vout->dma_queue)) {
+		vout->buf_empty = true;
+		goto vout_isr_err;
+	}
+#if !(CONFIG_OMAP2_DSS_HDMI)
+venc:
+#endif
+
+	vout->next_frm = list_entry(vout->dma_queue.next,
+						struct videobuf_buffer, queue);
+	list_del(&vout->next_frm->queue);
+
+	vout->next_frm->state = VIDEOBUF_ACTIVE;
+	addr = (unsigned long)
+				vout->queued_buf_addr[vout->next_frm->i] +
+				+ vout->cropped_offset[vout->next_frm->i];
+	uv_addr = (unsigned long)vout->queued_buf_uv_addr[
+				vout->next_frm->i]
+				+ vout->cropped_uv_offset[vout->next_frm->i];
+
+	/* First save the configuration in ovelray structure */
+	ret = omapvid_init(vout, addr, uv_addr);
+	if (ret)
+		printk(KERN_ERR VOUT_NAME
+				"failed to set overlay info\n");
+	if (!vout->wb_enabled) {
+		/* Enable the pipeline and set the Go bit */
+		ret = omapvid_apply_changes(vout);
+		if (ret)
+			printk(KERN_ERR VOUT_NAME
+					"failed to change mode\n");
+	}
+#ifdef CONFIG_PANEL_PICO_DLP
+	if (sysfs_streq(cur_display->name, "pico_DLP"))
+		dispc_go(OMAP_DSS_CHANNEL_LCD2);
+#endif
+
+vout_isr_err:
+	spin_unlock_irqrestore(&vout->vbq_lock, flags);
+}
+
+static void omap_vout_cleanup_device(struct omap_vout_device *vout)
+{
+	struct video_device *vfd;
+
+	if (!vout)
+		return;
+
+	vfd = vout->vfd;
+	if (vfd) {
+		if (vfd->minor == -1) {
+			/*
+			 * The device was never registered, so release the
+			 * video_device struct directly.
+			 */
+			video_device_release(vfd);
+		} else {
+			/*
+			 * The unregister function will release the video_device
+			 * struct as well as unregistering it.
+			 */
+			video_unregister_device(vfd);
+		}
+	}
+
+#ifndef CONFIG_ARCH_OMAP4
+	omap_vout_release_vrfb(vout);
+#endif
+	omap_vout_free_buffers(vout);
+#ifndef CONFIG_ARCH_OMAP4
+	/* Free the VRFB buffer if allocated
+	 * init time
+	 */
+	if (vout->vrfb_static_allocation)
+		omap_vout_free_vrfb_buffers(vout);
+#else
+	omap_vout_free_tiler_buffers(vout);
+#endif
+	kfree(vout);
+}
+
+static int __init omap_vout_init(void)
+{
+	if (platform_driver_register(&omap_vout_driver) != 0) {
+		printk(KERN_ERR VOUT_NAME ":Could not register Video driver\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static void omap_vout_cleanup(void)
+{
+	platform_driver_unregister(&omap_vout_driver);
+}
+
+late_initcall(omap_vout_init);
+module_exit(omap_vout_cleanup);
diff --git a/drivers/media/video/omap/omap_voutdef.h b/drivers/media/video/omap/omap_voutdef.h
new file mode 100644
index 000000000000..d3294ec66697
--- /dev/null
+++ b/drivers/media/video/omap/omap_voutdef.h
@@ -0,0 +1,164 @@
+/*
+ * omap_voutdef.h
+ *
+ * Copyright (C) 2010 Texas Instruments.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef OMAP_VOUTDEF_H
+#define OMAP_VOUTDEF_H
+
+#include <plat/display.h>
+
+#define YUYV_BPP        2
+#define RGB565_BPP      2
+#define RGB24_BPP       3
+#define RGB32_BPP       4
+#define TILE_SIZE       32
+#define YUYV_VRFB_BPP   2
+#define RGB_VRFB_BPP    1
+#define MAX_CID		3
+#define MAC_VRFB_CTXS	4
+#ifdef CONFIG_ARCH_OMAP4
+#define MAX_VOUT_DEV	3
+#define MAX_OVLS	4
+#define MAX_DISPLAYS	4
+#else
+#define MAX_VOUT_DEV	2
+#define MAX_OVLS	3
+#define MAX_DISPLAYS	3
+#endif
+#define MAX_MANAGERS	3
+
+/* Enum for Rotation
+ * DSS understands rotation in 0, 1, 2, 3 context
+ * while V4L2 driver understands it as 0, 90, 180, 270
+ */
+enum dss_rotation {
+	dss_rotation_0_degree	= 0,
+	dss_rotation_90_degree	= 1,
+	dss_rotation_180_degree	= 2,
+	dss_rotation_270_degree = 3,
+};
+/*
+ * This structure is used to store the DMA transfer parameters
+ * for VRFB hidden buffer
+ */
+struct vid_vrfb_dma {
+	int dev_id;
+	int dma_ch;
+	int req_status;
+	int tx_status;
+	wait_queue_head_t wait;
+};
+
+struct omapvideo_info {
+	int id;
+	int num_overlays;
+	struct omap_overlay *overlays[MAX_OVLS];
+};
+
+struct omap2video_device {
+	struct mutex  mtx;
+
+	int state;
+
+	struct v4l2_device v4l2_dev;
+	int num_videos;
+	struct omap_vout_device *vouts[MAX_VOUT_DEV];
+
+	int num_displays;
+	struct omap_dss_device *displays[MAX_DISPLAYS];
+	int num_overlays;
+	struct omap_overlay *overlays[MAX_OVLS];
+	int num_managers;
+	struct omap_overlay_manager *managers[MAX_MANAGERS];
+};
+
+/* per-device data structure */
+struct omap_vout_device {
+
+	struct omapvideo_info vid_info;
+	struct video_device *vfd;
+	struct omap2video_device *vid_dev;
+	int vid;
+	int opened;
+
+	/* we don't allow to change image fmt/size once buffer has
+	 * been allocated
+	 */
+	int buffer_allocated;
+	/* allow to reuse previously allocated buffer which is big enough */
+	int buffer_size;
+	/* keep buffer info across opens */
+	unsigned long buf_virt_addr[VIDEO_MAX_FRAME];
+	unsigned long buf_phy_addr[VIDEO_MAX_FRAME];
+	/* keep which buffers we actually allocated (via tiler) */
+	unsigned long buf_phy_uv_addr_alloced[VIDEO_MAX_FRAME];
+	unsigned long buf_phy_addr_alloced[VIDEO_MAX_FRAME];
+
+/* NV12 support*/
+	unsigned long buf_phy_uv_addr[VIDEO_MAX_FRAME];
+	u8 *queued_buf_uv_addr[VIDEO_MAX_FRAME];
+	enum omap_color_mode dss_mode;
+
+	/* we don't allow to request new buffer when old buffers are
+	 * still mmaped
+	 */
+	int mmap_count;
+
+	spinlock_t vbq_lock;		/* spinlock for videobuf queues */
+	unsigned long field_count;	/* field counter for videobuf_buffer */
+
+	/* non-NULL means streaming is in progress. */
+	bool streaming;
+
+	struct v4l2_pix_format pix;
+	struct v4l2_rect crop;
+	struct v4l2_window win;
+	struct v4l2_framebuffer fbuf;
+
+	/* Lock to protect the shared data structures in ioctl */
+	struct mutex lock;
+
+	/* V4L2 control structure for different control id */
+	struct v4l2_control control[MAX_CID];
+	enum dss_rotation rotation;
+	bool mirror;
+	int flicker_filter;
+	/* V4L2 control structure for different control id */
+
+	int bpp; /* bytes per pixel */
+	int vrfb_bpp; /* bytes per pixel with respect to VRFB */
+
+	struct vid_vrfb_dma vrfb_dma_tx;
+	unsigned int smsshado_phy_addr[MAC_VRFB_CTXS];
+	unsigned int smsshado_virt_addr[MAC_VRFB_CTXS];
+	struct vrfb vrfb_context[MAC_VRFB_CTXS];
+	bool vrfb_static_allocation;
+	unsigned int smsshado_size;
+	unsigned char pos;
+
+	int ps, vr_ps, line_length, first_int, field_id;
+	enum v4l2_memory memory;
+	struct videobuf_buffer *cur_frm, *next_frm;
+	struct list_head dma_queue;
+	u8 *queued_buf_addr[VIDEO_MAX_FRAME];
+	u32 cropped_offset[VIDEO_MAX_FRAME];
+	u32 cropped_uv_offset[VIDEO_MAX_FRAME];
+	s32 tv_field1_offset;
+	void *isr_handle;
+
+	/* Buffer queue variables */
+	struct omap_vout_device *vout;
+	enum v4l2_buf_type type;
+	struct videobuf_queue vbq;
+	int io_allowed;
+	/* writeback variables*/
+	bool wb_enabled;
+	bool buf_empty;
+};
+#endif	/* ifndef OMAP_VOUTDEF_H */
diff --git a/drivers/media/video/omap/omap_voutlib.c b/drivers/media/video/omap/omap_voutlib.c
new file mode 100644
index 000000000000..e47546404d74
--- /dev/null
+++ b/drivers/media/video/omap/omap_voutlib.c
@@ -0,0 +1,259 @@
+/*
+ * omap_voutlib.c
+ *
+ * Copyright (C) 2005-2010 Texas Instruments.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * Based on the OMAP2 camera driver
+ * Video-for-Linux (Version 2) camera capture driver for
+ * the OMAP24xx camera controller.
+ *
+ * Author: Andy Lowe (source@mvista.com)
+ *
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ * Copyright (C) 2010 Texas Instruments.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <plat/cpu.h>
+
+MODULE_AUTHOR("Texas Instruments");
+MODULE_DESCRIPTION("OMAP Video library");
+MODULE_LICENSE("GPL");
+
+/* Return the default overlay cropping rectangle in crop given the image
+ * size in pix and the video display size in fbuf.  The default
+ * cropping rectangle is the largest rectangle no larger than the capture size
+ * that will fit on the display.  The default cropping rectangle is centered in
+ * the image.  All dimensions and offsets are rounded down to even numbers.
+ */
+void omap_vout_default_crop(struct v4l2_pix_format *pix,
+		  struct v4l2_framebuffer *fbuf, struct v4l2_rect *crop)
+{
+	crop->width = (pix->width < fbuf->fmt.width) ?
+		pix->width : fbuf->fmt.width;
+	crop->height = (pix->height < fbuf->fmt.height) ?
+		pix->height : fbuf->fmt.height;
+	crop->width &= ~1;
+	crop->height &= ~1;
+	crop->left = ((pix->width - crop->width) >> 1) & ~1;
+	crop->top = ((pix->height - crop->height) >> 1) & ~1;
+}
+EXPORT_SYMBOL_GPL(omap_vout_default_crop);
+
+/* Given a new render window in new_win, adjust the window to the
+ * nearest supported configuration.  The adjusted window parameters are
+ * returned in new_win.
+ * Returns zero if succesful, or -EINVAL if the requested window is
+ * impossible and cannot reasonably be adjusted.
+ */
+int omap_vout_try_window(struct v4l2_framebuffer *fbuf,
+			struct v4l2_window *new_win)
+{
+	struct v4l2_rect try_win;
+
+	/* make a working copy of the new_win rectangle */
+	try_win = new_win->w;
+
+	/* adjust the preview window so it fits on the display by clipping any
+	 * offscreen areas
+	 */
+	if (try_win.left < 0) {
+		try_win.width += try_win.left;
+		try_win.left = 0;
+	}
+	if (try_win.top < 0) {
+		try_win.height += try_win.top;
+		try_win.top = 0;
+	}
+	try_win.width = (try_win.width < fbuf->fmt.width) ?
+		try_win.width : fbuf->fmt.width;
+	try_win.height = (try_win.height < fbuf->fmt.height) ?
+		try_win.height : fbuf->fmt.height;
+	if (try_win.left + try_win.width > fbuf->fmt.width)
+		try_win.width = fbuf->fmt.width - try_win.left;
+	if (try_win.top + try_win.height > fbuf->fmt.height)
+		try_win.height = fbuf->fmt.height - try_win.top;
+	try_win.width &= ~1;
+	try_win.height &= ~1;
+
+	if (try_win.width <= 0 || try_win.height <= 0)
+		return -EINVAL;
+
+	/* We now have a valid preview window, so go with it */
+	new_win->w = try_win;
+	new_win->field = V4L2_FIELD_ANY;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(omap_vout_try_window);
+
+/* Given a new render window in new_win, adjust the window to the
+ * nearest supported configuration.  The image cropping window in crop
+ * will also be adjusted if necessary.  Preference is given to keeping the
+ * the window as close to the requested configuration as possible.  If
+ * successful, new_win, vout->win, and crop are updated.
+ * Returns zero if succesful, or -EINVAL if the requested preview window is
+ * impossible and cannot reasonably be adjusted.
+ */
+int omap_vout_new_window(struct v4l2_rect *crop,
+		struct v4l2_window *win, struct v4l2_framebuffer *fbuf,
+		struct v4l2_window *new_win)
+{
+	int err;
+
+	err = omap_vout_try_window(fbuf, new_win);
+	if (err)
+		return err;
+
+	/* update our preview window */
+	win->w = new_win->w;
+	win->field = new_win->field;
+	win->chromakey = new_win->chromakey;
+
+	/* adjust the cropping window to allow for resizing limitations */
+	if ((crop->height/win->w.height) >= 4) {
+		/* The maximum vertical downsizing ratio is 4:1 */
+		crop->height = win->w.height * 4;
+	}
+	if ((crop->width/win->w.width) >= 4) {
+		/* The maximum horizontal downsizing ratio is 4:1 */
+		crop->width = win->w.width * 4;
+	}
+	return 0;
+}
+EXPORT_SYMBOL_GPL(omap_vout_new_window);
+
+/* Given a new cropping rectangle in new_crop, adjust the cropping rectangle to
+ * the nearest supported configuration.  The image render window in win will
+ * also be adjusted if necessary.  The preview window is adjusted such that the
+ * horizontal and vertical rescaling ratios stay constant.  If the render
+ * window would fall outside the display boundaries, the cropping rectangle
+ * will also be adjusted to maintain the rescaling ratios.  If successful, crop
+ * and win are updated.
+ * Returns zero if succesful, or -EINVAL if the requested cropping rectangle is
+ * impossible and cannot reasonably be adjusted.
+ */
+int omap_vout_new_crop(struct v4l2_pix_format *pix,
+	      struct v4l2_rect *crop, struct v4l2_window *win,
+	      struct v4l2_framebuffer *fbuf, const struct v4l2_rect *new_crop)
+{
+	struct v4l2_rect try_crop;
+	unsigned long vresize, hresize;
+
+	/* make a working copy of the new_crop rectangle */
+	try_crop = *new_crop;
+
+	/* adjust the cropping rectangle so it fits in the image */
+	if (try_crop.left < 0) {
+		try_crop.width += try_crop.left;
+		try_crop.left = 0;
+	}
+	if (try_crop.top < 0) {
+		try_crop.height += try_crop.top;
+		try_crop.top = 0;
+	}
+	try_crop.width = (try_crop.width < pix->width) ?
+		try_crop.width : pix->width;
+	try_crop.height = (try_crop.height < pix->height) ?
+		try_crop.height : pix->height;
+	if (try_crop.left + try_crop.width > pix->width)
+		try_crop.width = pix->width - try_crop.left;
+	if (try_crop.top + try_crop.height > pix->height)
+		try_crop.height = pix->height - try_crop.top;
+	try_crop.width &= ~1;
+	try_crop.height &= ~1;
+	if (try_crop.width <= 0 || try_crop.height <= 0)
+		return -EINVAL;
+
+	if (cpu_is_omap24xx() && crop->height != win->w.height) {
+		/* If we're resizing vertically, we can't support a crop width
+		 * wider than 768 pixels.
+		 */
+		if (try_crop.width > 768)
+			try_crop.width = 768;
+	}
+	/* vertical resizing */
+	vresize = (1024 * crop->height) / win->w.height;
+	if (vresize > 4096)
+		vresize = 4096;
+	else if (vresize == 0)
+		vresize = 1;
+	win->w.height = ((1024 * try_crop.height) / vresize) & ~1;
+	if (win->w.height == 0)
+		win->w.height = 2;
+	if (win->w.height + win->w.top > fbuf->fmt.height) {
+		/* We made the preview window extend below the bottom of the
+		 * display, so clip it to the display boundary and resize the
+		 * cropping height to maintain the vertical resizing ratio.
+		 */
+		win->w.height = (fbuf->fmt.height - win->w.top) & ~1;
+		if (try_crop.height == 0)
+			try_crop.height = 2;
+	}
+	/* horizontal resizing */
+	hresize = (1024 * crop->width) / win->w.width;
+	if (hresize > 4096)
+		hresize = 4096;
+	else if (hresize == 0)
+		hresize = 1;
+	win->w.width = ((1024 * try_crop.width) / hresize) & ~1;
+	if (win->w.width == 0)
+		win->w.width = 2;
+	if (win->w.width + win->w.left > fbuf->fmt.width) {
+		/* We made the preview window extend past the right side of the
+		 * display, so clip it to the display boundary and resize the
+		 * cropping width to maintain the horizontal resizing ratio.
+		 */
+		win->w.width = (fbuf->fmt.width - win->w.left) & ~1;
+		if (try_crop.width == 0)
+			try_crop.width = 2;
+	}
+
+	/* Check for resizing constraints */
+	if ((try_crop.height/win->w.height) >= 4) {
+		/* The maximum vertical downsizing ratio is 4:1 */
+		try_crop.height = win->w.height * 4;
+	}
+	if ((try_crop.width/win->w.width) >= 4) {
+		/* The maximum horizontal downsizing ratio is 4:1 */
+		try_crop.width = win->w.width * 4;
+	}
+
+	/* update our cropping rectangle and we're done */
+	*crop = try_crop;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(omap_vout_new_crop);
+
+/* Given a new format in pix and fbuf,  crop and win
+ * structures are initialized to default values. crop
+ * is initialized to the largest window size that will fit on the display.  The
+ * crop window is centered in the image. win is initialized to
+ * the same size as crop and is centered on the display.
+ * All sizes and offsets are constrained to be even numbers.
+ */
+void omap_vout_new_format(struct v4l2_pix_format *pix,
+		struct v4l2_framebuffer *fbuf, struct v4l2_rect *crop,
+		struct v4l2_window *win)
+{
+	/* crop defines the preview source window in the image capture
+	 * buffer
+	 */
+	omap_vout_default_crop(pix, fbuf, crop);
+
+	/* win defines the preview target window on the display */
+	win->w.width = crop->width;
+	win->w.height = crop->height;
+	win->w.left = ((fbuf->fmt.width - win->w.width) >> 1) & ~1;
+	win->w.top = ((fbuf->fmt.height - win->w.height) >> 1) & ~1;
+}
+EXPORT_SYMBOL_GPL(omap_vout_new_format);
+
diff --git a/drivers/media/video/omap/omap_voutlib.h b/drivers/media/video/omap/omap_voutlib.h
new file mode 100644
index 000000000000..a60b16e8bfc3
--- /dev/null
+++ b/drivers/media/video/omap/omap_voutlib.h
@@ -0,0 +1,34 @@
+/*
+ * omap_voutlib.h
+ *
+ * Copyright (C) 2010 Texas Instruments.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#ifndef OMAP_VOUTLIB_H
+#define OMAP_VOUTLIB_H
+
+extern void omap_vout_default_crop(struct v4l2_pix_format *pix,
+		struct v4l2_framebuffer *fbuf, struct v4l2_rect *crop);
+
+extern int omap_vout_new_crop(struct v4l2_pix_format *pix,
+		struct v4l2_rect *crop, struct v4l2_window *win,
+		struct v4l2_framebuffer *fbuf,
+		const struct v4l2_rect *new_crop);
+
+extern int omap_vout_try_window(struct v4l2_framebuffer *fbuf,
+		struct v4l2_window *new_win);
+
+extern int omap_vout_new_window(struct v4l2_rect *crop,
+		struct v4l2_window *win, struct v4l2_framebuffer *fbuf,
+		struct v4l2_window *new_win);
+
+extern void omap_vout_new_format(struct v4l2_pix_format *pix,
+		struct v4l2_framebuffer *fbuf, struct v4l2_rect *crop,
+		struct v4l2_window *win);
+#endif	/* #ifndef OMAP_VOUTLIB_H */
+
diff --git a/drivers/media/video/omap/omap_wb.c b/drivers/media/video/omap/omap_wb.c
new file mode 100644
index 000000000000..ba39899f897c
--- /dev/null
+++ b/drivers/media/video/omap/omap_wb.c
@@ -0,0 +1,1153 @@
+/*
+ * drivers/media/video/omap/omap_wb.c
+ *
+ * Copyright (C) 2005-2009 Texas Instruments.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * Leveraged code from the OMAP2 camera driver
+ * Video-for-Linux (Version 2) camera capture driver for
+ * the OMAP24xx camera controller.
+ *
+ * Author: Andy Lowe (source@mvista.com)
+ *
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ * Copyright (C) 2009 Texas Instruments.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <linux/videodev2.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <media/videobuf-dma-sg.h>
+#include <media/v4l2-dev.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-device.h>
+
+#include <asm/processor.h>
+#include <plat/dma.h>
+#include <plat/vram.h>
+#include <plat/display.h>
+
+#include "omap_wbdef.h"
+#include "omap_voutlib.h"
+#include <mach/tiler.h>
+
+#define WB_NAME "omap_wb"
+
+#define QQVGA_WIDTH		160
+#define QQVGA_HEIGHT	120
+
+struct mutex wb_lock;
+static struct videobuf_queue_ops video_vbq_ops;
+
+static int debug_wb;
+
+module_param(debug_wb, bool, S_IRUGO);
+MODULE_PARM_DESC(debug_wb, "Debug level (0-1)");
+
+int omap_vout_try_format(struct v4l2_pix_format *pix);
+enum omap_color_mode video_mode_to_dss_mode(
+			struct v4l2_pix_format *pix);
+void omap_wb_isr(void *arg, unsigned int irqstatus);
+int	omap_dss_wb_apply(struct omap_overlay_manager *mgr, struct omap_writeback *wb);
+
+int omap_setup_wb(struct omap_wb_device *wb_device, u32 addr, u32 uv_addr)
+{
+	struct omap_writeback *wb;
+	struct omap_overlay_manager *mgr = NULL;
+	struct omap_writeback_info wb_info;
+	int r = 0;
+	int i = 0;
+	wb_info.enabled = true;
+	wb_info.info_dirty = true;
+	wb_info.capturemode = wb_device->capturemode;
+	wb_info.dss_mode = wb_device->dss_mode;
+	wb_info.height = wb_device->height;
+	wb_info.width = wb_device->width;
+	wb_info.source = wb_device->source;
+	wb_info.source_type = wb_device->source_type;
+	wb_info.paddr = addr;
+	wb_info.puv_addr = uv_addr;
+
+	v4l2_dbg(1, debug_wb, &wb_device->wb_dev->v4l2_dev,
+			"omap_write back struct contents :\n"
+			"enabled = %d\n infodirty = %d\n"
+			"capturemode = %d\n dss_mode = %d\n"
+			"height = %d\n width = %d\n source = %d\n"
+			"source_type = %d\n paddr =%x\n puvaddr = %x\n",
+			wb_info.enabled, wb_info.info_dirty, wb_info.capturemode,
+			wb_info.dss_mode, wb_info.height, wb_info.width,
+			wb_info.source, wb_info.source_type, wb_info.paddr,
+			wb_info.puv_addr);
+
+	for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
+			/* Fix : checking for mgr will shift to DSS2 */
+			mgr = omap_dss_get_overlay_manager(i);
+			if (strcmp(mgr->name, "lcd") == 0)
+				break;
+	}
+
+	wb = omap_dss_get_wb(0);
+
+	if (!wb) {
+		printk(KERN_ERR WB_NAME "couldn't get wb struct\n");
+		r = -EINVAL;
+		goto err;
+	}
+	wb->enabled = true;
+	wb->info_dirty = true;
+
+	r = wb->set_wb_info(wb, &wb_info);
+	if (r) {
+		printk(KERN_ERR WB_NAME "wb_info not set\n");
+		goto err;
+	}
+	r = omap_dss_wb_apply(mgr, wb);
+err:
+	return r;
+}
+
+/*
+ *
+ * IOCTL interface.
+ *
+ */
+
+static int vidioc_querycap(struct file *file, void *fh,
+		struct v4l2_capability *cap)
+{
+	struct omap_wb_device *wb = fh;
+
+	strlcpy(cap->driver, WB_NAME,
+		sizeof(cap->driver));
+	strlcpy(cap->card, wb->vfd->name, sizeof(cap->card));
+	cap->bus_info[0] = '\0';
+	cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
+	return 0;
+}
+
+static int vidioc_g_fmt_vid_wb(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	struct omap_wb_device *wb = fh;
+
+	f->fmt.pix = wb->pix;
+	return 0;
+
+}
+
+static int vidioc_s_fmt_vid_wb(struct file *file, void *fh,
+			struct v4l2_format *f)
+{
+	struct omap_wb_device *wb = fh;
+	int bpp;
+
+	if (wb->streaming)
+		return -EBUSY;
+
+	mutex_lock(&wb->lock);
+
+	bpp = omap_vout_try_format(&f->fmt.pix);
+
+	if (V4L2_PIX_FMT_NV12 == f->fmt.pix.pixelformat)
+		f->fmt.pix.sizeimage = f->fmt.pix.width *
+					f->fmt.pix.height * 3/2;
+	else
+		f->fmt.pix.sizeimage = f->fmt.pix.width *
+					f->fmt.pix.height * bpp;
+
+	/* try & set the new output format */
+	wb->bpp = bpp;
+	wb->pix = f->fmt.pix;
+
+	mutex_unlock(&wb->lock);
+
+	return 0;
+}
+
+static int vidioc_reqbufs(struct file *file, void *fh,
+			struct v4l2_requestbuffers *req)
+{
+	struct omap_wb_device *wb = fh;
+	struct videobuf_queue *q = &wb->vbq;
+	unsigned int i;
+	int ret = 0;
+	struct videobuf_dmabuf *dmabuf = NULL;
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev, "entered REQbuf: \n");
+
+	if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) || (req->count < 0))
+		return -EINVAL;
+
+	/* if memory is not mmp or userptr
+	   return error */
+	if ((V4L2_MEMORY_MMAP != req->memory) &&
+		(V4L2_MEMORY_USERPTR != req->memory))
+		return -EINVAL;
+
+	mutex_lock(&wb->lock);
+
+	/* Cannot be requested when streaming is on */
+	if (wb->streaming) {
+		mutex_unlock(&wb->lock);
+		return -EBUSY;
+	}
+
+	/* If buffers are already allocated free them */
+	if (q->bufs[0] && (V4L2_MEMORY_MMAP == q->bufs[0]->memory)) {
+		if (wb->mmap_count) {
+			mutex_unlock(&wb->lock);
+			return -EBUSY;
+		}
+
+		videobuf_mmap_free(q);
+		} else if (q->bufs[0] && (V4L2_MEMORY_USERPTR == q->bufs[0]->memory)) {
+			if (wb->buffer_allocated) {
+				videobuf_mmap_free(q);
+				for (i = 0; i < wb->buffer_allocated; i++) {
+					kfree(q->bufs[i]);
+					q->bufs[i] = NULL;
+				}
+				wb->buffer_allocated = 0;
+			}
+	}
+	/*store the memory type in data structure */
+	wb->memory = req->memory;
+
+	INIT_LIST_HEAD(&wb->dma_queue);
+
+	/* call videobuf_reqbufs api */
+	ret = videobuf_reqbufs(q, req);
+	if (ret < 0) {
+		mutex_unlock(&wb->lock);
+		return ret;
+	}
+
+	wb->buffer_allocated = req->count;
+	for (i = 0; i < req->count; i++) {
+		dmabuf = videobuf_to_dma(q->bufs[i]);
+
+		if (V4L2_PIX_FMT_NV12 == wb->pix.pixelformat)
+			dmabuf->vmalloc = (void *) wb->buf_phy_uv_addr[i];
+		else
+			dmabuf->vmalloc = NULL;
+
+		dmabuf->bus_addr = (dma_addr_t) wb->buf_phy_addr[i];
+		dmabuf->sglen = 1;
+	}
+	mutex_unlock(&wb->lock);
+	return 0;
+}
+
+static int vidioc_querybuf(struct file *file, void *fh,
+			struct v4l2_buffer *b)
+{
+	struct omap_wb_device *wb = fh;
+
+	return videobuf_querybuf(&wb->vbq, b);
+}
+
+static int vidioc_qbuf(struct file *file, void *fh,
+			struct v4l2_buffer *buffer)
+{
+	struct omap_wb_device *wb = fh;
+	struct videobuf_queue *q = &wb->vbq;
+	int ret = 0;
+	u32 addr = 0, uv_addr = 0;
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+		"entered qbuf: buffer address: %x\n", (unsigned int) buffer);
+
+	if ((V4L2_BUF_TYPE_VIDEO_CAPTURE != buffer->type) ||
+			(buffer->index >= wb->buffer_allocated) ||
+
+			(q->bufs[buffer->index]->memory != buffer->memory)) {
+		return -EINVAL;
+	}
+	if (V4L2_MEMORY_USERPTR == buffer->memory) {
+		if ((buffer->length < wb->pix.sizeimage) ||
+			(0 == buffer->m.userptr)) {
+			return -EINVAL;
+		}
+	}
+
+	ret = videobuf_qbuf(q, buffer);
+
+	if (wb->streaming && wb->buf_empty) {
+		addr = (unsigned long)wb->queued_buf_addr[wb->next_frm->i];
+		uv_addr = (unsigned long) wb->queued_buf_uv_addr[wb->cur_frm->i];
+		wb->buf_empty = 0;
+		omap_setup_wb(wb, addr, uv_addr);
+	}
+	return ret;
+}
+
+static int vidioc_dqbuf(struct file *file, void *fh,
+			struct v4l2_buffer *b)
+{
+	struct omap_wb_device *wb = fh;
+	struct videobuf_queue *q = &wb->vbq;
+	int ret = 0;
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+		"entered DQbuf: buffer address: %x \n", (unsigned int) b);
+
+	if (!wb->streaming)
+		return -EINVAL;
+
+	if (file->f_flags & O_NONBLOCK)
+		/* Call videobuf_dqbuf for non blocking mode */
+		ret = videobuf_dqbuf(q, (struct v4l2_buffer *)b, 1);
+	else
+		/* Call videobuf_dqbuf for  blocking mode */
+		ret = videobuf_dqbuf(q, (struct v4l2_buffer *)b, 0);
+	return ret;
+}
+
+static int vidioc_streamon(struct file *file, void *fh,
+			enum v4l2_buf_type i)
+{
+	struct omap_wb_device *wb = fh;
+	struct videobuf_queue *q = &wb->vbq;
+	u32 addr = 0, uv_addr = 0;
+	int r = 0;
+	u32 mask = 0;
+
+	mutex_lock(&wb->lock);
+
+	if (wb->streaming) {
+		mutex_unlock(&wb->lock);
+		return -EBUSY;
+	}
+
+	r = videobuf_streamon(q);
+	if (r < 0) {
+		mutex_unlock(&wb->lock);
+		return r;
+	}
+
+	if (list_empty(&wb->dma_queue)) {
+		mutex_unlock(&wb->lock);
+		return -EIO;
+	}
+	/* Get the next frame from the buffer queue */
+	wb->next_frm = wb->cur_frm = list_entry(wb->dma_queue.next,
+				struct videobuf_buffer, queue);
+	/* Remove buffer from the buffer queue */
+	list_del(&wb->cur_frm->queue);
+	/* Mark state of the current frame to active */
+	wb->cur_frm->state = VIDEOBUF_ACTIVE;
+
+	/* set flag here. Next QBUF will start DMA */
+	wb->streaming = 1;
+
+	wb->first_int = 1;
+
+	addr = (unsigned long) wb->queued_buf_addr[wb->cur_frm->i];
+
+	uv_addr = (unsigned long) wb->queued_buf_uv_addr[wb->cur_frm->i];
+
+	mask = DISPC_IRQ_FRAMEDONE_WB;
+
+	r = omap_dispc_register_isr(omap_wb_isr, wb, mask);
+
+	r = omap_setup_wb(wb, addr, uv_addr);
+	if (r)
+		printk(KERN_ERR WB_NAME "error in setup_wb\n");
+
+	mutex_unlock(&wb->lock);
+	return r;
+}
+
+static int vidioc_streamoff(struct file *file, void *fh,
+			enum v4l2_buf_type i)
+{
+	struct omap_wb_device *wb = fh;
+	u32 mask = 0;
+
+	if (!wb->streaming)
+		return -EINVAL;
+
+	wb->streaming = 0;
+	mask = DISPC_IRQ_FRAMEDONE_WB;
+
+	omap_dispc_unregister_isr(omap_wb_isr, wb, mask);
+
+	INIT_LIST_HEAD(&wb->dma_queue);
+	videobuf_streamoff(&wb->vbq);
+	videobuf_queue_cancel(&wb->vbq);
+	return 0;
+}
+
+static int vidioc_default_wb(struct file *file, void *fh,
+			     int cmd, void *arg)
+{
+	struct v4l2_writeback_ioctl_data *wb_data = NULL;
+	struct omap_wb_device *wb = fh;
+	int r = -1;
+	enum omap_color_mode dss_mode;
+
+	switch (cmd) {
+	case VIDIOC_CUSTOM_S_WB:
+		wb_data  = (struct v4l2_writeback_ioctl_data *)arg;
+
+		if (!wb_data) {
+			return -EINVAL;
+			printk(KERN_ERR WB_NAME "error in S_WB\n");
+		}
+		mutex_lock(&wb->lock);
+		wb->enabled = wb_data->enabled;
+		wb->pix = wb_data->pix;
+		wb->source = wb_data->source;
+		wb->capturemode = wb_data->capturemode;
+		/* source type hardcoded for now */
+		wb->source_type = V4L2_WB_SOURCE_OVERLAY;
+
+		dss_mode = video_mode_to_dss_mode(&wb->pix);
+
+		if (dss_mode == -EINVAL) {
+			printk(KERN_ERR WB_NAME "invalid dss_mode\n");
+			r = -EINVAL;
+			goto err;
+		}
+
+		mutex_unlock(&wb->lock);
+
+		break;
+
+	case VIDIOC_CUSTOM_G_WB:
+		wb_data  = (struct v4l2_writeback_ioctl_data *)arg;
+
+		if (!wb_data) {
+			printk(KERN_ERR WB_NAME "error in G_WB\n");
+			return -EINVAL;
+		}
+		mutex_lock(&wb->lock);
+
+		wb_data->pix = wb->pix;
+		wb_data->source = wb->source;
+		wb_data->capturemode = wb->capturemode;
+		wb_data->source_type = V4L2_WB_SOURCE_OVERLAY;
+
+		mutex_unlock(&wb->lock);
+
+		break;
+	default:
+		BUG();
+	}
+	return 0;
+
+	err:
+	mutex_unlock(&wb->lock);
+	return r;
+}
+
+static const struct v4l2_ioctl_ops wb_ioctl_fops = {
+	.vidioc_querycap	= vidioc_querycap,
+	.vidioc_g_fmt_vid_cap	= vidioc_g_fmt_vid_wb,
+	.vidioc_s_fmt_vid_cap	= vidioc_s_fmt_vid_wb,
+	.vidioc_reqbufs		= vidioc_reqbufs,
+	.vidioc_querybuf	= vidioc_querybuf,
+	.vidioc_qbuf		= vidioc_qbuf,
+	.vidioc_dqbuf		= vidioc_dqbuf,
+	.vidioc_streamon	= vidioc_streamon,
+	.vidioc_streamoff	= vidioc_streamoff,
+	.vidioc_default		= vidioc_default_wb,
+};
+
+static void omap_wb_tiler_buffer_free(struct omap_wb_device *wb,
+					unsigned int count,
+					unsigned int startindex)
+{
+	int i;
+
+	if (startindex < 0)
+		startindex = 0;
+	if (startindex + count > VIDEO_MAX_FRAME)
+		count = VIDEO_MAX_FRAME - startindex;
+
+	for (i = startindex; i < startindex + count; i++) {
+		if (wb->buf_phy_addr_alloced[i])
+			tiler_free(wb->buf_phy_addr_alloced[i]);
+		if (wb->buf_phy_uv_addr_alloced[i])
+			tiler_free(wb->buf_phy_uv_addr_alloced[i]);
+		wb->buf_phy_addr[i] = 0;
+		wb->buf_phy_addr_alloced[i] = 0;
+		wb->buf_phy_uv_addr[i] = 0;
+		wb->buf_phy_uv_addr_alloced[i] = 0;
+	}
+}
+
+/* Allocate the buffers for  TILER space.  Ideally, the buffers will be ONLY
+ in tiler space, with different rotated views available by just a convert.
+ */
+static int omap_wb_tiler_buffer_setup(struct omap_wb_device *wb,
+					unsigned int *count, unsigned int startindex,
+					struct v4l2_pix_format *pix)
+{
+	int i, aligned = 1;
+	enum tiler_fmt fmt;
+
+	/* normalize buffers to allocate so we stay within bounds */
+	int start = (startindex < 0) ? 0 : startindex;
+	int n_alloc = (start + *count > VIDEO_MAX_FRAME)
+		? VIDEO_MAX_FRAME - start : *count;
+	int bpp = omap_vout_try_format(pix);
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev, "tiler buffer alloc:\n"
+		"count - %d, start -%d :\n", *count, startindex);
+
+	/* special allocation scheme for NV12 format */
+	if (OMAP_DSS_COLOR_NV12 == video_mode_to_dss_mode(pix)) {
+		tiler_alloc_packed_nv12(&n_alloc, pix->width,
+			pix->height,
+			(void **) wb->buf_phy_addr + start,
+			(void **) wb->buf_phy_uv_addr + start,
+			(void **) wb->buf_phy_addr_alloced + start,
+			(void **) wb->buf_phy_uv_addr_alloced + start,
+			aligned);
+	} else {
+		/* Only bpp of 1, 2, and 4 is supported by tiler */
+		fmt = (bpp == 1 ? TILFMT_8BIT :
+			bpp == 2 ? TILFMT_16BIT :
+			bpp == 4 ? TILFMT_32BIT : TILFMT_INVALID);
+		if (fmt == TILFMT_INVALID)
+			return -ENOMEM;
+
+		tiler_alloc_packed(&n_alloc, fmt, pix->width,
+			pix->height,
+			(void **) wb->buf_phy_addr + start,
+			(void **) wb->buf_phy_addr_alloced + start,
+			aligned);
+	}
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+			"allocated %d buffers\n", n_alloc);
+
+	if (n_alloc < *count) {
+		if (n_alloc && (startindex == -1 ||
+			V4L2_MEMORY_MMAP != wb->memory)) {
+			/* TODO: check this condition's logic */
+			omap_wb_tiler_buffer_free(wb, n_alloc, start);
+			*count = 0;
+			return -ENOMEM;
+		}
+	}
+
+	for (i = start; i < start + n_alloc; i++) {
+		v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+				"y=%08lx (%d) uv=%08lx (%d)\n",
+				wb->buf_phy_addr[i],
+				wb->buf_phy_addr_alloced[i] ? 1 : 0,
+				wb->buf_phy_uv_addr[i],
+				wb->buf_phy_uv_addr_alloced[i] ? 1 : 0);
+	}
+
+	*count = n_alloc;
+
+	return 0;
+}
+
+/* Free tiler buffers */
+static void omap_wb_free_tiler_buffers(struct omap_wb_device *wb)
+{
+	omap_wb_tiler_buffer_free(wb, wb->buffer_allocated, 0);
+	wb->buffer_allocated = 0;
+}
+
+
+/* Video buffer call backs */
+
+/* Buffer setup function is called by videobuf layer when REQBUF ioctl is
+ * called. This is used to setup buffers and return size and count of
+ * buffers allocated. After the call to this buffer, videobuf layer will
+ * setup buffer queue depending on the size and count of buffers
+ */
+static int omap_wb_buffer_setup(struct videobuf_queue *q, unsigned int *count,
+			  unsigned int *size)
+{
+	struct omap_wb_device *wb = q->priv_data;
+	int i;
+
+	if (!wb)
+		return -EINVAL;
+
+	if (V4L2_BUF_TYPE_VIDEO_CAPTURE != q->type)
+		return -EINVAL;
+
+	/* Now allocated the V4L2 buffers */
+	/* i is the block-width - either 4K or 8K, depending upon input width*/
+	i = (wb->pix.width * wb->bpp +
+		TILER_PAGE - 1) & ~(TILER_PAGE - 1);
+
+	/* for NV12 format, buffer is height + height / 2*/
+	if (OMAP_DSS_COLOR_NV12 == wb->dss_mode)
+		*size = wb->buffer_size = (wb->pix.height * 3/2 * i);
+	else
+		*size = wb->buffer_size = (wb->pix.height * i);
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+			"\nheight=%d, size = %d, wb->buffer_sz=%d\n",
+			wb->pix.height, *size, wb->buffer_size);
+	if (omap_wb_tiler_buffer_setup(wb, count, 0, &wb->pix))
+			return -ENOMEM;
+
+	if (V4L2_MEMORY_MMAP != wb->memory)
+		return 0;
+
+	return 0;
+}
+
+/* This function will be called when VIDIOC_QBUF ioctl is called.
+ * It prepare buffers before give out for the display. This function
+ * user space virtual address into physical address if userptr memory
+ * exchange mechanism is used. If rotation is enabled, it copies entire
+ * buffer into VRFB memory space before giving it to the DSS.
+ */
+static int omap_wb_buffer_prepare(struct videobuf_queue *q,
+			    struct videobuf_buffer *vb,
+			    enum v4l2_field field)
+{
+	struct omap_wb_device *wb = q->priv_data;
+	struct videobuf_dmabuf *dmabuf = NULL;
+
+	if (VIDEOBUF_NEEDS_INIT == vb->state) {
+		vb->width = wb->pix.width;
+		vb->height = wb->pix.height;
+		vb->size = vb->width * vb->height * wb->bpp;
+		vb->field = field;
+	}
+	vb->state = VIDEOBUF_PREPARED;
+
+	/* Here, we need to use the physical addresses given by Tiler:
+	*/
+	dmabuf = videobuf_to_dma(q->bufs[vb->i]);
+	wb->queued_buf_addr[vb->i] = (u8 *) dmabuf->bus_addr;
+	wb->queued_buf_uv_addr[vb->i] = (u8 *) dmabuf->vmalloc;
+	return 0;
+}
+
+/* Buffer queue funtion will be called from the videobuf layer when _QBUF
+ * ioctl is called. It is used to enqueue buffer, which is ready to be
+ * displayed. */
+static void omap_wb_buffer_queue(struct videobuf_queue *q,
+			  struct videobuf_buffer *vb)
+{
+	struct omap_wb_device *wb = q->priv_data;
+
+	/* Driver is also maintainig a queue. So enqueue buffer in the driver
+	 * queue */
+	list_add_tail(&vb->queue, &wb->dma_queue);
+
+	vb->state = VIDEOBUF_QUEUED;
+}
+
+/* Buffer release function is called from videobuf layer to release buffer
+ * which are already allocated */
+static void omap_wb_buffer_release(struct videobuf_queue *q,
+			    struct videobuf_buffer *vb)
+{
+	struct omap_wb_device *wb = q->priv_data;
+
+	vb->state = VIDEOBUF_NEEDS_INIT;
+
+	if (V4L2_MEMORY_MMAP != wb->memory)
+		return;
+}
+
+/*
+ *  File operations
+ */
+static void omap_wb_vm_open(struct vm_area_struct *vma)
+{
+	struct omap_wb_device *wb = vma->vm_private_data;
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+	"vm_open [vma=%08lx-%08lx]\n", vma->vm_start, vma->vm_end);
+	wb->mmap_count++;
+}
+
+static void omap_wb_vm_close(struct vm_area_struct *vma)
+{
+	struct omap_wb_device *wb = vma->vm_private_data;
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+	"vm_close [vma=%08lx-%08lx]\n", vma->vm_start, vma->vm_end);
+	wb->mmap_count--;
+}
+
+static struct vm_operations_struct omap_wb_vm_ops = {
+	.open = omap_wb_vm_open,
+	.close = omap_wb_vm_close,
+};
+
+static int omap_wb_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct omap_wb_device *wb = file->private_data;
+	struct videobuf_queue *q = &wb->vbq;
+	int i;
+	void *pos;
+	struct videobuf_dmabuf *dmabuf = NULL;
+
+	int j = 0, k = 0, m = 0, p = 0, m_increment = 0;
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+		" %s pgoff=0x%lx, start=0x%lx, end=0x%lx\n", __func__,
+		vma->vm_pgoff, vma->vm_start, vma->vm_end);
+
+	/* look for the buffer to map */
+	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+		if (NULL == q->bufs[i])
+			continue;
+		if (V4L2_MEMORY_MMAP != q->bufs[i]->memory)
+			continue;
+		if (q->bufs[i]->boff == (vma->vm_pgoff << PAGE_SHIFT))
+			break;
+	}
+
+	if (VIDEO_MAX_FRAME == i) {
+		v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev,
+		"offset invalid [offset=0x%lx]\n",
+			(vma->vm_pgoff << PAGE_SHIFT));
+		return -EINVAL;
+	}
+	q->bufs[i]->baddr = vma->vm_start;
+
+	vma->vm_flags |= VM_RESERVED;
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+	vma->vm_ops = &omap_wb_vm_ops;
+	vma->vm_private_data = (void *) wb;
+
+	dmabuf = videobuf_to_dma(q->bufs[i]);
+
+	pos = (void *) dmabuf->bus_addr;
+	/* get line width */
+	/* for NV12, Y buffer is 1bpp*/
+
+	if (OMAP_DSS_COLOR_NV12 == wb->dss_mode) {
+		p = (wb->pix.width +
+			TILER_PAGE - 1) & ~(TILER_PAGE - 1);
+		m_increment = 64 * TILER_WIDTH;
+	} else {
+		p = (wb->pix.width * wb->bpp +
+			TILER_PAGE - 1) & ~(TILER_PAGE - 1);
+
+		if (wb->bpp > 1)
+			m_increment = 2*64*TILER_WIDTH;
+		else
+			m_increment = 64 * TILER_WIDTH;
+	}
+
+	for (j = 0; j < wb->pix.height; j++) {
+		/* map each page of the line */
+
+		vma->vm_pgoff =
+			((unsigned long)pos + m) >> PAGE_SHIFT;
+
+		if (remap_pfn_range(vma, vma->vm_start + k,
+			((unsigned long)pos + m) >> PAGE_SHIFT,
+			p, vma->vm_page_prot))
+				return -EAGAIN;
+		k += p;
+		m += m_increment;
+	}
+	m = 0;
+
+	/* UV Buffer in case of NV12 format */
+	if (OMAP_DSS_COLOR_NV12 == wb->dss_mode) {
+		pos = dmabuf->vmalloc;
+		/* UV buffer is 2 bpp, but half size, so p remains */
+		m_increment = 2*64*TILER_WIDTH;
+
+		/* UV buffer is height / 2*/
+		for (j = 0; j < wb->pix.height / 2; j++) {
+			/* map each page of the line */
+			vma->vm_pgoff =
+				((unsigned long)pos + m) >> PAGE_SHIFT;
+
+			if (remap_pfn_range(vma, vma->vm_start + k,
+				((unsigned long)pos + m) >> PAGE_SHIFT,
+				p, vma->vm_page_prot))
+				return -EAGAIN;
+			k += p;
+			m += m_increment;
+		}
+	}
+
+	vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */
+	wb->mmap_count++;
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev, "Exiting %s\n", __func__);
+	return 0;
+}
+
+static int omap_wb_release(struct file *file)
+{
+
+	struct omap_wb_device *wb = file->private_data;
+	struct videobuf_queue *q;
+	unsigned int r = 0;
+
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev, "Entering %s\n", __func__);
+
+	if (!wb)
+		return 0;
+
+	q = &wb->vbq;
+
+	omap_wb_free_tiler_buffers(wb);
+
+	videobuf_mmap_free(q);
+
+	/* Even if apply changes fails we should continue
+	   freeing allocated memeory */
+	if (wb->streaming) {
+		u32 mask = 0;
+
+		mask = DISPC_IRQ_FRAMEDONE_WB;
+
+		omap_dispc_unregister_isr(omap_wb_isr, wb, mask);
+		wb->streaming = 0;
+
+		videobuf_streamoff(q);
+		videobuf_queue_cancel(q);
+	}
+
+	if (wb->mmap_count != 0)
+		wb->mmap_count = 0;
+
+	wb->opened -= 1;
+	file->private_data = NULL;
+
+	if (wb->buffer_allocated)
+		videobuf_mmap_free(q);
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev, "Exiting %s\n", __func__);
+	return r;
+}
+
+static int omap_wb_open(struct file *file)
+{
+	struct omap_wb_device *wb = NULL;
+	struct videobuf_queue *q;
+
+	wb = video_drvdata(file);
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev, "Entering %s\n", __func__);
+
+	if (wb == NULL)
+		return -ENODEV;
+
+	/* for now, we only support single open */
+	if (wb->opened)
+		return -EBUSY;
+
+	wb->opened += 1;
+	wb->enabled = true;
+	file->private_data = wb;
+	wb->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+	q = &wb->vbq;
+	video_vbq_ops.buf_setup = omap_wb_buffer_setup;
+	video_vbq_ops.buf_prepare = omap_wb_buffer_prepare;
+	video_vbq_ops.buf_release = omap_wb_buffer_release;
+	video_vbq_ops.buf_queue = omap_wb_buffer_queue;
+	spin_lock_init(&wb->vbq_lock);
+
+	videobuf_queue_sg_init(q, &video_vbq_ops, NULL, &wb->vbq_lock,
+			       wb->type, V4L2_FIELD_NONE, sizeof
+			       (struct videobuf_buffer), wb);
+	v4l2_dbg(1, debug_wb, &wb->wb_dev->v4l2_dev, "Exiting %s\n", __func__);
+	return 0;
+}
+
+static struct v4l2_file_operations wb_fops = {
+	.owner		= THIS_MODULE,
+	.ioctl	 = video_ioctl2,
+	.mmap	 = omap_wb_mmap,
+	.open	 = omap_wb_open,
+	.release = omap_wb_release,
+};
+
+
+/* Init functions used during driver intitalization */
+/* Initial setup of video_data */
+static int __init omap_wb_setup_video_data(struct omap_wb_device *wb)
+{
+	struct v4l2_pix_format *pix;
+	struct video_device *vfd;
+
+	/* set the default pix */
+	pix = &wb->pix;
+
+	/* Set the default picture of QVGA  */
+	pix->width = QQVGA_WIDTH;
+	pix->height = QQVGA_HEIGHT;
+
+	/* Default pixel format is RGB 5-6-5 */
+	pix->pixelformat = V4L2_PIX_FMT_RGB32;
+	pix->field = V4L2_FIELD_ANY;
+	pix->bytesperline = pix->width * 2;
+	pix->sizeimage = pix->bytesperline * pix->height;
+	pix->priv = 0;
+	pix->colorspace = V4L2_COLORSPACE_JPEG;
+
+	wb->width = pix->width;
+	wb->height = pix->height;
+	wb->bpp = RGB565_BPP;
+	wb->enabled = false;
+	wb->buffer_allocated = 0;
+	wb->capturemode = V4L2_WB_CAPTURE_ALL;
+	wb->source = V4L2_WB_OVERLAY0;
+	wb->source_type =  V4L2_WB_SOURCE_OVERLAY;
+	wb->dss_mode = OMAP_DSS_COLOR_ARGB32;
+	/* initialize the video_device struct */
+	vfd = wb->vfd = video_device_alloc();
+
+	if (!vfd) {
+		printk(KERN_ERR WB_NAME ": could not allocate"
+				" WB device struct\n");
+		return -ENOMEM;
+	}
+	vfd->release = video_device_release;
+	vfd->ioctl_ops = &wb_ioctl_fops;
+
+	strlcpy(vfd->name, WB_NAME, sizeof(vfd->name));
+	vfd->vfl_type = VFL_TYPE_GRABBER;
+
+	/* need to register for a VID_HARDWARE_* ID in videodev.h */
+	vfd->fops = &wb_fops;
+	mutex_init(&wb->lock);
+
+	vfd->minor = -1;
+	return 0;
+}
+
+
+/* Create wb devices */
+static int __init omap_wb_create_video_devices(struct platform_device *pdev)
+{
+	int r = 0, k;
+	struct omap_wb_device *wb;
+	struct video_device *vfd = NULL;
+	struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
+
+	struct omap2wb_device *wb_dev = container_of(v4l2_dev, struct
+			omap2wb_device, v4l2_dev);
+
+	for (k = 0; k < pdev->num_resources; k++) {
+
+		wb = kmalloc(sizeof(struct omap_wb_device), GFP_KERNEL);
+		if (!wb) {
+			printk(KERN_ERR WB_NAME
+					": could not allocate memory\n");
+			return -ENOMEM;
+		}
+
+		memset(wb, 0, sizeof(struct omap_wb_device));
+
+		wb->wid = k;
+		wb->wb_dev = wb_dev;
+
+		/* Setup the default configuration for the wb devices
+		 */
+		if (omap_wb_setup_video_data(wb) != 0) {
+			r = -ENOMEM;
+			goto error;
+		}
+
+		/* Register the Video device with V4L2
+		 */
+		vfd = wb->vfd;
+		if (video_register_device(vfd, VFL_TYPE_GRABBER, k + 1) < 0) {
+			printk(KERN_ERR WB_NAME ": could not register "
+					"Video for Linux device\n");
+			vfd->minor = -1;
+			r = -ENODEV;
+			goto error1;
+		}
+		video_set_drvdata(vfd, wb);
+
+		goto success;
+
+error1:
+	video_device_release(vfd);
+error:
+	kfree(wb);
+	return r;
+
+success:
+	printk(KERN_INFO WB_NAME ": registered and initialized "
+			"wb device %d [v4l2]\n", vfd->minor);
+	if (k == (pdev->num_resources - 1))
+		return 0;
+	}
+	return -ENODEV;
+
+}
+
+/* Driver functions */
+
+static void omap_wb_cleanup_device(struct omap_wb_device *wb)
+{
+	struct video_device *vfd;
+
+	if (!wb)
+		return;
+
+	vfd = wb->vfd;
+
+	if (vfd) {
+		if (vfd->minor == -1) {
+			/*
+			 * The device was never registered, so release the
+			 * video_device struct directly.
+			 */
+			video_device_release(vfd);
+		} else {
+			/*
+			 * The unregister function will release the video_device
+			 * struct as well as unregistering it.
+			 */
+			video_unregister_device(vfd);
+		}
+	}
+
+	omap_wb_free_tiler_buffers(wb);
+
+	kfree(wb);
+}
+
+static int omap_wb_remove(struct platform_device *pdev)
+{
+
+	struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
+	struct omap2wb_device *wb_dev = container_of(v4l2_dev, struct
+			omap2wb_device, v4l2_dev);
+	int k;
+
+	v4l2_device_unregister(v4l2_dev);
+	for (k = 0; k < pdev->num_resources; k++)
+		omap_wb_cleanup_device(wb_dev->wb);
+
+	kfree(wb_dev);
+
+	return 0;
+}
+
+static int __init omap_wb_probe(struct platform_device *pdev)
+{
+	int r = 0;
+	struct omap2wb_device *wb_dev = NULL;
+
+	if (pdev->num_resources == 0) {
+		dev_err(&pdev->dev, "probed for an unknown device\n");
+		r = -ENODEV;
+		return r;
+	}
+
+	wb_dev = kzalloc(sizeof(struct omap2wb_device), GFP_KERNEL);
+	if (wb_dev == NULL) {
+		r = -ENOMEM;
+		return r;
+	}
+
+	if (v4l2_device_register(&pdev->dev, &wb_dev->v4l2_dev) < 0) {
+		printk(KERN_ERR WB_NAME "v4l2_device_register failed\n");
+		return -ENODEV;
+	}
+
+	r = omap_wb_create_video_devices(pdev);
+	if (r)
+		goto error0;
+
+	return 0;
+
+error0:
+	kfree(wb_dev);
+	return r;
+}
+
+static struct platform_driver omap_wb_driver = {
+	.driver = {
+		   .name = WB_NAME,
+		   },
+	.probe = omap_wb_probe,
+	.remove = omap_wb_remove,
+};
+void omap_wb_isr(void *arg, unsigned int irqstatus)
+{
+	struct timeval timevalue = {0};
+	int r = 0;
+	struct omap_wb_device *wb =
+	    (struct omap_wb_device *) arg;
+	u32 addr, uv_addr, flags;
+
+	spin_lock_irqsave(&wb->vbq_lock, flags);
+
+	if (!wb->first_int && (wb->cur_frm != wb->next_frm)) {
+		wb->cur_frm->ts = timevalue;
+		wb->cur_frm->state = VIDEOBUF_DONE;
+		wake_up_interruptible(&wb->cur_frm->done);
+		wb->cur_frm = wb->next_frm;
+		}
+
+	wb->first_int = 0;
+	if (list_empty(&wb->dma_queue)) {
+		wb->buf_empty = true;
+		spin_unlock_irqrestore(&wb->vbq_lock, flags);
+		return;
+	}
+
+	wb->next_frm = list_entry(wb->dma_queue.next,
+		struct videobuf_buffer, queue);
+	list_del(&wb->next_frm->queue);
+
+	wb->next_frm->state = VIDEOBUF_ACTIVE;
+	addr = (unsigned long)wb->queued_buf_addr[wb->next_frm->i];
+
+#ifdef CONFIG_ARCH_OMAP4
+	uv_addr = (unsigned long)wb->queued_buf_uv_addr[
+		wb->next_frm->i];
+#endif
+	r = omap_setup_wb(wb, addr, uv_addr);
+	if (r)
+		printk(KERN_ERR WB_NAME "error in setup_wb %d\n", r);
+
+	spin_unlock_irqrestore(&wb->vbq_lock, flags);
+}
+
+static int __init omap_wb_init(void)
+{
+
+	if (platform_driver_register(&omap_wb_driver) != 0) {
+		printk(KERN_ERR WB_NAME ": could not register \
+				WB driver\n");
+		return -EINVAL;
+	}
+	mutex_init(&wb_lock);
+	return 0;
+}
+
+static void omap_wb_cleanup(void)
+{
+	platform_driver_unregister(&omap_wb_driver);
+}
+
+late_initcall(omap_wb_init);
+module_exit(omap_wb_cleanup);
+
diff --git a/drivers/media/video/omap/omap_wbdef.h b/drivers/media/video/omap/omap_wbdef.h
new file mode 100644
index 000000000000..accabf537b06
--- /dev/null
+++ b/drivers/media/video/omap/omap_wbdef.h
@@ -0,0 +1,93 @@
+/*
+ * drivers/media/video/omap/omap_wbdef.h
+ *
+ * Copyright (C) 2009 Texas Instruments.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <plat/display.h>
+#include <linux/videodev2.h>
+
+#define YUYV_BPP        2
+#define RGB565_BPP      2
+#define RGB24_BPP       3
+#define RGB32_BPP       4
+#define TILE_SIZE       32
+
+struct omap2wb_device {
+	struct mutex  mtx;
+
+	int state;
+	struct v4l2_device v4l2_dev;
+	struct omap_wb_device *wb;
+};
+
+struct omap_wb_device {
+
+	struct video_device *vfd;
+	int wid;
+	int opened;
+	struct omap2wb_device *wb_dev;
+	/* we don't allow to change image fmt/size once buffer has
+	 * been allocated
+	 */
+	int buffer_allocated;
+	/* allow to reuse previously allocated buffer which is big enough */
+	int buffer_size;
+	/* keep buffer info across opens */
+	unsigned long buf_virt_addr[VIDEO_MAX_FRAME];
+	unsigned long buf_phy_addr[VIDEO_MAX_FRAME];
+	/* keep which buffers we actually allocated (via tiler) */
+	unsigned long buf_phy_uv_addr_alloced[VIDEO_MAX_FRAME];
+	unsigned long buf_phy_addr_alloced[VIDEO_MAX_FRAME];
+
+	/* NV12 support*/
+	unsigned long buf_phy_uv_addr[VIDEO_MAX_FRAME];
+	u8 *queued_buf_uv_addr[VIDEO_MAX_FRAME];
+
+	enum omap_color_mode dss_mode;
+
+	unsigned long						width;
+	unsigned long						height;
+	/* we don't allow to request new buffer when old buffers are
+	 * still mmaped
+	 */
+	int mmap_count;
+
+	spinlock_t vbq_lock;		/* spinlock for videobuf queues */
+	unsigned long field_count;	/* field counter for videobuf_buffer */
+
+	bool enabled;
+	/* non-NULL means streaming is in progress. */
+	bool streaming;
+
+	struct v4l2_pix_format pix;
+	struct v4l2_window win;
+
+	/* Lock to protect the shared data structures in ioctl */
+	struct mutex lock;
+
+	int bpp; /* bytes per pixel */
+
+	int ps, vr_ps, line_length, first_int, field_id;
+	enum v4l2_memory memory;
+	struct videobuf_buffer *cur_frm, *next_frm;
+	struct list_head dma_queue;
+	u8 *queued_buf_addr[VIDEO_MAX_FRAME];
+	void *isr_handle;
+
+	/* Buffer queue variables */
+	struct omap_wb_device *wb;
+	enum v4l2_buf_type type;
+	struct videobuf_queue vbq;
+	int io_allowed;
+
+	/*write back specific*/
+	enum v4l2_writeback_source			source;
+	enum v4l2_writeback_source_type		source_type;
+	enum v4l2_writeback_capturemode		capturemode;
+	bool buf_empty;
+};
diff --git a/drivers/media/video/tiler/Kconfig b/drivers/media/video/tiler/Kconfig
new file mode 100644
index 000000000000..fabbb59a6c8d
--- /dev/null
+++ b/drivers/media/video/tiler/Kconfig
@@ -0,0 +1,6 @@
+config TILER_OMAP
+	tristate "OMAP TILER support"
+	default y
+	help
+           TILER driver for OMAP based boards.
+
diff --git a/drivers/media/video/tiler/Makefile b/drivers/media/video/tiler/Makefile
new file mode 100644
index 000000000000..e6dbe24ce9d3
--- /dev/null
+++ b/drivers/media/video/tiler/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_TILER_OMAP) += tcm/
+obj-$(CONFIG_TILER_OMAP) += tiler_omap.o
+tiler_omap-objs = tiler.o tiler_pack.o tiler_rot.o
+
diff --git a/drivers/media/video/tiler/tcm/Makefile b/drivers/media/video/tiler/tcm/Makefile
new file mode 100644
index 000000000000..f03f3b7c862f
--- /dev/null
+++ b/drivers/media/video/tiler/tcm/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_TILER_OMAP) += tcm_sita.o
+
diff --git a/drivers/media/video/tiler/tcm/_tcm_sita.h b/drivers/media/video/tiler/tcm/_tcm_sita.h
new file mode 100644
index 000000000000..75de584c747d
--- /dev/null
+++ b/drivers/media/video/tiler/tcm/_tcm_sita.h
@@ -0,0 +1,91 @@
+/*
+ * _tcm_sita.h
+ *
+ * SImple Tiler Allocator (SiTA) private structures.
+ *
+ * Author: Ravi Ramachandra <r.ramachandra@ti.com>
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _TCM_SITA_H_
+#define _TCM_SITA_H_
+
+#include "tcm.h"
+
+#define TL_CORNER       0
+#define TR_CORNER       1
+#define BL_CORNER       3
+#define BR_CORNER       4
+
+/*Provide inclusive length between co-ordinates */
+#define INCL_LEN(high, low)		((high) - (low) + 1)
+#define INCL_LEN_MOD(start, end)   ((start) > (end) ? (start) - (end) + 1 : \
+		(end) - (start) + 1)
+
+#define BOUNDARY(stat) ((stat)->top_boundary + (stat)->bottom_boundary + \
+				(stat)->left_boundary + (stat)->right_boundary)
+#define OCCUPIED(stat) ((stat)->top_occupied + (stat)->bottom_occupied + \
+				(stat)->left_occupied + (stat)->right_occupied)
+
+enum Criteria {
+	CR_MAX_NEIGHS       = 0x01,
+	CR_FIRST_FOUND      = 0x10,
+	CR_BIAS_HORIZONTAL  = 0x20,
+	CR_BIAS_VERTICAL    = 0x40,
+	CR_DIAGONAL_BALANCE = 0x80
+};
+
+struct nearness_factor {
+	s32 x;
+	s32 y;
+};
+
+/*
+ * Area info kept
+ */
+struct area_spec {
+	struct tcm_area area;
+	struct list_head list;
+};
+
+/*
+ * Everything is a rectangle with four sides 	and on
+ * each side you could have a boundary or another Tile.
+ * The tile could be Occupied or Not. These info is stored
+ */
+struct neighbour_stats {
+	u16 left_boundary;
+	u16 left_occupied;
+	u16 top_boundary;
+	u16 top_occupied;
+	u16 right_boundary;
+	u16 right_occupied;
+	u16 bottom_boundary;
+	u16 bottom_occupied;
+};
+
+struct slot {
+	u8 busy;		/* is slot occupied */
+	struct tcm_area parent; /* parent area */
+	u32 reserved;
+};
+
+struct sita_pvt {
+	u16 width;
+	u16 height;
+	struct list_head res;	/* all allocations */
+	struct mutex mtx;
+	struct tcm_pt div_pt;	/* divider point splitting container */
+	struct slot **map;	/* container slots */
+};
+
+#endif /* _TCM_SITA_H_ */
diff --git a/drivers/media/video/tiler/tcm/tcm.h b/drivers/media/video/tiler/tcm/tcm.h
new file mode 100644
index 000000000000..d205dad32a46
--- /dev/null
+++ b/drivers/media/video/tiler/tcm/tcm.h
@@ -0,0 +1,352 @@
+/*
+ * tcm.h
+ *
+ * TILER container manager specification and support functions for TI
+ * processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _TCM_H_
+#define _TCM_H_
+
+#include <linux/init.h>
+#include <linux/module.h>
+
+struct tcm;
+
+struct tcm_pt {
+	u16 x;
+	u16 y;
+};
+
+struct tcm_area {
+	bool is2d;		/* whether are is 1d or 2d */
+	struct tcm    *tcm;	/* parent */
+	struct tcm_pt  p0;
+	struct tcm_pt  p1;
+};
+
+struct tcm {
+	u16 width, height;	/* container dimensions */
+
+	/* 'pvt' structure shall contain any tcm details (attr) along with
+	linked list of allocated areas and mutex for mutually exclusive access
+	to the list.  It may also contain copies of width and height to notice
+	any changes to the publicly available width and height fields. */
+	void *pvt;
+
+	/* function table */
+	s32 (*reserve_2d)(struct tcm *tcm, u16 height, u16 width, u8 align,
+			  struct tcm_area *area);
+	s32 (*reserve_1d)(struct tcm *tcm, u32 slots, struct tcm_area *area);
+	s32 (*free)      (struct tcm *tcm, struct tcm_area *area);
+	s32 (*get_parent)(struct tcm *tcm, struct tcm_pt *pt,
+			  struct tcm_area *area);
+	void (*deinit)   (struct tcm *tcm);
+};
+
+/*=============================================================================
+    BASIC TILER CONTAINER MANAGER INTERFACE
+=============================================================================*/
+
+/*
+ * NOTE:
+ *
+ * Since some basic parameter checking is done outside the TCM algorithms,
+ * TCM implementation do NOT have to check the following:
+ *
+ *   area pointer is NULL
+ *   width and height fits within container
+ *   number of pages is more than the size of the container
+ *
+ */
+
+/**
+ * Template for <ALGO_NAME>_tcm_init method.  Define as:
+ * TCM_INIT(<ALGO_NAME>_tcm_init)
+ *
+ * Allocates and initializes a tiler container manager.
+ *
+ * @param width		Width of container
+ * @param height	Height of container
+ * @param attr		Container manager specific configuration
+ *  			arguments.  Please describe these in
+ *  			your header file.
+ *
+ * @return Pointer to the allocated and initialized container
+ *  	   manager.  NULL on failure.  DO NOT leak any memory on
+ *  	   failure!
+ */
+#define TCM_INIT(name, attr_t) \
+struct tcm *name(u16 width, u16 height, typeof(attr_t) *attr);
+
+/**
+ * Deinitialize tiler container manager.
+ *
+ * @author Ravi Ramachandra (3/1/2010)
+ *
+ * @param tcm	Pointer to container manager.
+ *
+ * @return 0 on success, non-0 error value on error.  The call
+ *  	   should free as much memory as possible and meaningful
+ *  	   even on failure.  Some error codes: -ENODEV: invalid
+ *  	   manager.
+ */
+static inline void tcm_deinit(struct tcm *tcm)
+{
+	if (tcm)
+		tcm->deinit(tcm);
+}
+
+/**
+ * Reserves a 2D area in the container.
+ *
+ * @author Ravi Ramachandra (3/1/2010)
+ *
+ * @param tcm		Pointer to container manager.
+ * @param height	Height(in pages) of area to be reserved.
+ * @param width		Width(in pages) of area to be reserved.
+ * @param align		Alignment requirement for top-left corner of area. Not
+ *  			all values may be supported by the container manager,
+ * 			but it must support 0 (1), 32 and 64.
+ *  			0 value is equivalent to 1.
+ * @param area		Pointer to where the reserved area should be stored.
+ *
+ * @return 0 on success.  Non-0 error code on failure.  Also,
+ *  	   the tcm field of the area will be set to NULL on
+ *  	   failure.  Some error codes: -ENODEV: invalid manager,
+ *  	   -EINVAL: invalid area, -ENOMEM: not enough space for
+ *  	    allocation.
+ */
+static inline s32 tcm_reserve_2d(struct tcm *tcm, u16 width, u16 height,
+				 u16 align, struct tcm_area *area)
+{
+	/* perform rudimentary error checking */
+	s32 res = (tcm  == NULL ? -ENODEV :
+		   area == NULL ? -EINVAL :
+		   (height > tcm->height || width > tcm->width) ? -ENOMEM :
+		   tcm->reserve_2d(tcm, height, width, align, area));
+
+	if (area)
+		area->tcm = res ? NULL : tcm;
+
+	return res;
+}
+
+/**
+ * Reserves a 1D area in the container.
+ *
+ * @author Ravi Ramachandra (3/1/2010)
+ *
+ * @param tcm		Pointer to container manager.
+ * @param slots		Number of (contiguous) slots to reserve.
+ * @param area		Pointer to where the reserved area should be stored.
+ *
+ * @return 0 on success.  Non-0 error code on failure.  Also,
+ *  	   the tcm field of the area will be set to NULL on
+ *  	   failure.  Some error codes: -ENODEV: invalid manager,
+ *  	   -EINVAL: invalid area, -ENOMEM: not enough space for
+ *  	    allocation.
+ */
+static inline s32 tcm_reserve_1d(struct tcm *tcm, u32 slots,
+				 struct tcm_area *area)
+{
+	/* perform rudimentary error checking */
+	s32 res = (tcm  == NULL ? -ENODEV :
+		   area == NULL ? -EINVAL :
+		   slots > (tcm->width * (u32) tcm->height) ? -ENOMEM :
+		   tcm->reserve_1d(tcm, slots, area));
+
+	if (area)
+		area->tcm = res ? NULL : tcm;
+
+	return res;
+}
+
+/**
+ * Free a previously reserved area from the container.
+ *
+ * @author Ravi Ramachandra (3/1/2010)
+ *
+ * @param area	Pointer to area reserved by a prior call to
+ *  		tcm_reserve_1d or tcm_reserve_2d call, whether
+ *  		it was successful or not. (Note: all fields of
+ *  		the structure must match.)
+ *
+ * @return 0 on success.  Non-0 error code on failure.  Also, the tcm
+ *  	   field of the area is set to NULL on success to avoid subsequent
+ *  	   freeing.  This call will succeed even if supplying
+ *  	   the area from a failed reserved call.
+ */
+static inline s32 tcm_free(struct tcm_area *area)
+{
+	s32 res = 0; /* free succeeds by default */
+
+	if (area && area->tcm) {
+		res = area->tcm->free(area->tcm, area);
+		if (res == 0)
+			area->tcm = NULL;
+	}
+
+	return res;
+}
+
+
+/**
+ * Retrieves the parent area (1D or 2D) for a given co-ordinate in the
+ * container.
+ *
+ * @author Ravi Ramachandra (3/1/2010)
+ *
+ * @param tcm		Pointer to container manager.
+ * @param pt		Pointer to the coordinates of a slot in the container.
+ * @param area		Pointer to where the reserved area should be stored.
+ *
+ * @return 0 on success.  Non-0 error code on failure.  Also,
+ *  	   the tcm field of the area will be set to NULL on
+ *  	   failure.  Some error codes: -ENODEV: invalid manager,
+ *  	   -EINVAL: invalid area, -ENOENT: coordinate is not part of any
+ * 	   active area.
+ */
+static inline s32 tcm_get_parent(struct tcm *tcm, struct tcm_pt *pt,
+				 struct tcm_area *area)
+{
+	s32 res = (tcm  == NULL ? -ENODEV :
+		   area == NULL ? -EINVAL :
+		   (pt->x >= tcm->width || pt->y >= tcm->height) ? -ENOENT :
+		   tcm->get_parent(tcm, pt, area));
+
+	if (area)
+		area->tcm = res ? NULL : tcm;
+
+	return res;
+}
+
+/*=============================================================================
+    HELPER FUNCTION FOR ANY TILER CONTAINER MANAGER
+=============================================================================*/
+
+/**
+ * This method slices off the topmost 2D slice from the parent area, and stores
+ * it in the 'slice' parameter.  The 'parent' parameter will get modified to
+ * contain the remaining portion of the area.  If the whole parent area can
+ * fit in a 2D slice, its tcm pointer is set to NULL to mark that it is no
+ * longer a valid area.
+ *
+ * @author Lajos Molnar (3/17/2010)
+ *
+ * @param parent	Pointer to a VALID parent area that will get modified
+ * @param slice		Pointer to the slice area that will get modified
+ */
+static inline void tcm_slice(struct tcm_area *parent, struct tcm_area *slice)
+{
+	*slice = *parent;
+
+	/* check if we need to slice */
+	if (slice->tcm && !slice->is2d &&
+		slice->p0.y != slice->p1.y &&
+		(slice->p0.x || (slice->p1.x != slice->tcm->width - 1))) {
+		/* set end point of slice (start always remains) */
+		slice->p1.x = slice->tcm->width - 1;
+		slice->p1.y = (slice->p0.x) ? slice->p0.y : slice->p1.y - 1;
+		/* adjust remaining area */
+		parent->p0.x = 0;
+		parent->p0.y = slice->p1.y + 1;
+	} else {
+		/* mark this as the last slice */
+		parent->tcm = NULL;
+	}
+}
+
+/**
+ * Verifies if a tcm area is logically valid.
+ *
+ * @param area		Pointer to tcm area
+ *
+ * @return TRUE if area is logically valid, FALSE otherwise.
+ */
+static inline bool tcm_area_is_valid(struct tcm_area *area)
+{
+	return (area && area->tcm &&
+		/* coordinate bounds */
+		area->p1.x < area->tcm->width &&
+		area->p1.y < area->tcm->height &&
+		area->p0.y <= area->p1.y &&
+		/* 1D coordinate relationship + p0.x check */
+		((!area->is2d &&
+		  area->p0.x < area->tcm->width &&
+		  area->p0.x + area->p0.y * area->tcm->width <=
+		  area->p1.x + area->p1.y * area->tcm->width) ||
+		 /* 2D coordinate relationship */
+		 (area->is2d &&
+		  area->p0.x <= area->p1.x))
+	       );
+}
+
+/* see if a coordinate is within an area */
+static inline bool __tcm_is_in(struct tcm_pt *p, struct tcm_area *a)
+{
+	u16 i;
+
+	if (a->is2d) {
+		return p->x >= a->p0.x && p->x <= a->p1.x &&
+		       p->y >= a->p0.y && p->y <= a->p1.y;
+	} else {
+		i = p->x + p->y * a->tcm->width;
+		return i >= a->p0.x + a->p0.y * a->tcm->width &&
+		       i <= a->p1.x + a->p1.y * a->tcm->width;
+	}
+}
+
+/* calculate area width */
+static inline u16 __tcm_area_width(struct tcm_area *area)
+{
+	return area->p1.x - area->p0.x + 1;
+}
+
+/* calculate area height */
+static inline u16 __tcm_area_height(struct tcm_area *area)
+{
+	return area->p1.y - area->p0.y + 1;
+}
+
+/* calculate number of slots in an area */
+static inline u16 __tcm_sizeof(struct tcm_area *area)
+{
+	return area->is2d ?
+		__tcm_area_width(area) * __tcm_area_height(area) :
+		(area->p1.x - area->p0.x + 1) + (area->p1.y - area->p0.y) *
+							area->tcm->width;
+}
+#define tcm_sizeof(area) __tcm_sizeof(&(area))
+#define tcm_awidth(area) __tcm_area_width(&(area))
+#define tcm_aheight(area) __tcm_area_height(&(area))
+#define tcm_is_in(pt, area) __tcm_is_in(&(pt), &(area))
+
+/**
+ * Iterate through 2D slices of a valid area. Behaves
+ * syntactically as a for(;;) statement.
+ *
+ * @param var		Name of a local variable of type 'struct
+ *  			tcm_area *' that will get modified to
+ *  			contain each slice.
+ * @param area		Pointer to the VALID parent area. This
+ *  			structure will not get modified
+ *  			throughout the loop.
+ *
+ */
+#define tcm_for_each_slice(var, area, safe) \
+	for (safe = area, \
+	     tcm_slice(&safe, &var); \
+	     var.tcm; tcm_slice(&safe, &var))
+
+#endif /* _TCM_H_ */
diff --git a/drivers/media/video/tiler/tcm/tcm_sita.c b/drivers/media/video/tiler/tcm/tcm_sita.c
new file mode 100644
index 000000000000..0aea8f12be21
--- /dev/null
+++ b/drivers/media/video/tiler/tcm/tcm_sita.c
@@ -0,0 +1,1358 @@
+/*
+ * tcm_sita.c
+ *
+ * Author: Ravi Ramachandra <r.ramachandra@ti.com>
+ *
+ * SImple Tiler Allocator (SiTA): 2D and 1D allocation(reservation) algorithm
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+#include <linux/slab.h>
+
+#include "_tcm_sita.h"
+#include "tcm_sita.h"
+
+#define TCM_ALG_NAME "tcm_sita"
+#include "tcm_utils.h"
+
+#define X_SCAN_LIMITER	1
+#define Y_SCAN_LIMITER	1
+
+#define ALIGN_DOWN(value, align) ((value) & ~((align) - 1))
+
+/* Individual selection criteria for different scan areas */
+static s32 CR_L2R_T2B = CR_BIAS_HORIZONTAL;
+static s32 CR_R2L_T2B = CR_DIAGONAL_BALANCE;
+#ifdef SCAN_BOTTOM_UP
+static s32 CR_R2L_B2T = CR_FIRST_FOUND;
+static s32 CR_L2R_B2T = CR_DIAGONAL_BALANCE;
+#endif
+
+/*********************************************
+ *	TCM API - Sita Implementation
+ *********************************************/
+static s32 sita_reserve_2d(struct tcm *tcm, u16 h, u16 w, u8 align,
+		    struct tcm_area *area);
+static s32 sita_reserve_1d(struct tcm *tcm, u32 slots, struct tcm_area
+		    *area);
+static s32 sita_free(struct tcm *tcm, struct tcm_area *to_be_removed_area);
+static s32 sita_get_parent(struct tcm *tcm, struct tcm_pt *pt,
+			struct tcm_area *area);
+static void sita_deinit(struct tcm *tcm);
+
+/*********************************************
+ *	Main Scanner functions
+ *********************************************/
+static s32 scan_areas_and_find_fit(struct tcm *tcm, u16 w, u16 h, u16 stride,
+				   struct tcm_area *area);
+
+static s32 scan_l2r_t2b(struct tcm *tcm, u16 w, u16 h, u16 stride,
+			struct tcm_area *field, struct tcm_area *area);
+
+static s32 scan_r2l_t2b(struct tcm *tcm, u16 w, u16 h, u16 stride,
+			struct tcm_area *field, struct tcm_area *area);
+
+#ifdef SCAN_BOTTOM_UP
+static s32 scan_l2r_b2t(struct tcm *tcm, u16 w, u16 h, u16 stride,
+			struct tcm_area *field, struct tcm_area *area);
+
+static s32 scan_r2l_b2t(struct tcm *tcm, u16 w, u16 h, u16 stride,
+			struct tcm_area *field, struct tcm_area *area);
+#endif
+static s32 scan_r2l_b2t_one_dim(struct tcm *tcm, u32 num_pages,
+			struct tcm_area *field, struct tcm_area *area);
+
+/*********************************************
+ *	Support Infrastructure Methods
+ *********************************************/
+static s32 check_fit_r_and_b(struct tcm *tcm, u16 w, u16 h, u16 left_x,
+			     u16 top_y);
+
+static s32 check_fit_r_one_dim(struct tcm *tcm, u16 x, u16 y, u32 num_pages,
+			       u16 *busy_x, u16 *busy_y);
+
+static void select_candidate(struct tcm *tcm, u16 w, u16 h,
+			struct list_head *maybes, struct tcm_area *field,
+			s32 criteria, struct tcm_area *area);
+
+static void get_nearness_factor(struct tcm_area *field,
+		       struct tcm_area *candidate, struct nearness_factor *nf);
+
+static s32 get_busy_neigh_stats(struct tcm *tcm, u16 width, u16 height,
+			struct tcm_area *top_left_corner,
+			struct neighbour_stats *neighbour_stat);
+
+static void fill_1d_area(struct tcm *tcm,
+			struct tcm_area *area, struct slot slot);
+
+static void fill_2d_area(struct tcm *tcm,
+		       struct tcm_area *area, struct slot slot);
+
+static s32 move_left(struct tcm *tcm, u16 x, u16 y, u32 num_pages,
+		     u16 *xx, u16 *yy);
+static s32 move_right(struct tcm *tcm, u16 x, u16 y, u32 num_pages,
+		      u16 *xx, u16 *yy);
+/*********************************************/
+
+/*********************************************
+ *	Utility Methods
+ *********************************************/
+
+/* TODO: check if element allocation succeeded */
+
+/* insert a given area at the end of a given list */
+static
+struct area_spec *insert_element(struct list_head *head, struct tcm_area *area)
+{
+	struct area_spec *elem;
+
+	elem = kmalloc(sizeof(*elem), GFP_KERNEL);
+	if (elem) {
+		elem->area = *area;
+		list_add_tail(&elem->list, head);
+	}
+	return elem;
+}
+
+static
+s32 rem_element_with_match(struct list_head *head,
+			   struct tcm_area *area, u16 *is2d)
+{
+	struct area_spec *elem = NULL;
+
+	/*If the area to be removed matchs the list head itself,
+	we need to put the next one as list head */
+	list_for_each_entry(elem, head, list) {
+		if (elem->area.p0.x == area->p0.x
+			&& elem->area.p0.y == area->p0.y
+			&& elem->area.p1.x == area->p1.x
+			&& elem->area.p1.y == area->p1.y) {
+
+			*is2d = elem->area.is2d;
+			list_del(&elem->list);
+
+			kfree(elem);
+			return 0;
+		}
+	}
+	return -ENOENT;
+}
+
+static
+void clean_list(struct list_head *head)
+{
+	struct area_spec *elem = NULL, *elem_ = NULL;
+
+	list_for_each_entry_safe(elem, elem_, head, list) {
+		list_del(&elem->list);
+		kfree(elem);
+	}
+}
+
+#if 0
+static
+void dump_list_entries(struct list_head *head)
+{
+	struct area_spec *elem = NULL;
+
+	P1("Printing List Entries:\n");
+
+	list_for_each_entry(elem, head, list) {
+		printk(KERN_NOTICE "%dD:" AREA_FMT "\n", elem->area.type,
+					AREA(elem->area));
+	}
+
+	P1("List Finished\n");
+}
+
+static
+s32 dump_neigh_stats(struct neighbour_stats *neighbour)
+{
+	P1("Top  Occ:Boundary  %d:%d\n", neighbour->top_occupied,
+						neighbour->top_boundary);
+	P1("Bot  Occ:Boundary  %d:%d\n", neighbour->bottom_occupied,
+						neighbour->bottom_boundary);
+	P1("Left Occ:Boundary  %d:%d\n", neighbour->left_occupied,
+						neighbour->left_boundary);
+	P1("Rigt Occ:Boundary  %d:%d\n", neighbour->right_occupied,
+						neighbour->right_boundary);
+	return 0;
+}
+#endif
+
+struct tcm *sita_init(u16 width, u16 height, struct tcm_pt *attr)
+{
+	struct tcm *tcm = NULL;
+	struct sita_pvt *pvt = NULL;
+	struct slot init_tile = {0};
+	struct tcm_area area = {0};
+	s32 i = 0;
+
+	if (width == 0 || height == 0)
+		goto error;
+
+	tcm = kmalloc(sizeof(*tcm), GFP_KERNEL);
+	pvt = kmalloc(sizeof(*pvt), GFP_KERNEL);
+	if (!tcm || !pvt)
+		goto error;
+
+	memset(tcm, 0, sizeof(*tcm));
+	memset(pvt, 0, sizeof(*pvt));
+
+	/* Updating the pointers to SiTA implementation APIs */
+	tcm->height = height;
+	tcm->width = width;
+	tcm->reserve_2d = sita_reserve_2d;
+	tcm->reserve_1d = sita_reserve_1d;
+	tcm->get_parent = sita_get_parent;
+	tcm->free = sita_free;
+	tcm->deinit = sita_deinit;
+	tcm->pvt = (void *)pvt;
+
+	INIT_LIST_HEAD(&pvt->res);
+	pvt->height = height;
+	pvt->width = width;
+
+	mutex_init(&(pvt->mtx));
+
+	/* Creating tam map */
+	pvt->map = kmalloc(sizeof(*pvt->map) * pvt->width, GFP_KERNEL);
+
+	if (!pvt->map)
+		goto error;
+
+	for (i = 0; i < pvt->width; i++) {
+		pvt->map[i] =
+			kmalloc(sizeof(**pvt->map) * pvt->height,
+								GFP_KERNEL);
+		if (pvt->map[i] == NULL) {
+			while (i--)
+				kfree(pvt->map[i]);
+			kfree(pvt->map);
+			goto error;
+		}
+	}
+
+	if (attr && attr->x <= pvt->width && attr->y <= pvt->height) {
+		pvt->div_pt.x = attr->x;
+		pvt->div_pt.y = attr->y;
+
+	} else {
+		/* Defaulting to 3:1 ratio on width for 2D area split */
+		/* Defaulting to 3:1 ratio on height for 2D and 1D split */
+		pvt->div_pt.x = (pvt->width * 3) / 4;
+		pvt->div_pt.y = (pvt->height * 3) / 4;
+	}
+
+	area.p1.x = width - 1;
+	area.p1.y = height - 1;
+
+	mutex_lock(&(pvt->mtx));
+	fill_2d_area(tcm, &area, init_tile);
+	mutex_unlock(&(pvt->mtx));
+	return tcm;
+
+error:
+	kfree(tcm);
+	kfree(pvt);
+	return NULL;
+}
+
+static void sita_deinit(struct tcm *tcm)
+{
+	struct slot init_tile = {0};
+	struct sita_pvt *pvt = NULL;
+	struct tcm_area area = {0};
+	s32 i = 0;
+
+	pvt = (struct sita_pvt *)tcm->pvt;
+	if (pvt) {
+		area.p1.x = pvt->width - 1;
+		area.p1.y = pvt->height - 1;
+
+		mutex_lock(&(pvt->mtx));
+		fill_2d_area(tcm, &area, init_tile);
+		mutex_unlock(&(pvt->mtx));
+
+		mutex_destroy(&(pvt->mtx));
+
+		for (i = 0; i < pvt->height; i++) {
+			kfree(pvt->map[i]);
+			pvt->map[i] = NULL;
+		}
+		kfree(pvt->map);
+		pvt->map = NULL;
+		kfree(pvt);
+	}
+}
+
+/**
+ * @description: Allocate 1d pages if the required number of pages are
+ * available in the container
+ *
+ * @input:num_pages to be allocated
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ * area contain co-ordinates of start and end Tiles(inclusive)
+ */
+static s32 sita_reserve_1d(struct tcm *tcm, u32 num_pages,
+			   struct tcm_area *area)
+{
+	s32 ret = 0;
+	struct tcm_area field = {0};
+	struct slot slot = {0};
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	area->is2d = false;
+
+	mutex_lock(&(pvt->mtx));
+#ifdef RESTRICT_1D
+	/* scan within predefined 1D boundary */
+	assign(&field, pvt->width - 1, pvt->height - 1, 0, pvt->div_pt.y);
+#else
+	/* Scanning entire container */
+	assign(&field, pvt->width - 1, pvt->height - 1, 0, 0);
+#endif
+	ret = scan_r2l_b2t_one_dim(tcm, num_pages,
+				   &field, area);
+	/* There is not much to select, we pretty much give the first one
+	   which accomodates */
+	if (!ret) {
+		slot.busy = true;
+		slot.parent = *area;
+		/* inserting into tiler container */
+		fill_1d_area(tcm, area, slot);
+		/* updating the list of allocations */
+		insert_element(&pvt->res, area);
+	}
+	mutex_unlock(&(pvt->mtx));
+	return ret;
+}
+
+/**
+ * @description: Allocate 2d area on availability in the container
+ *
+ * @input:'w'idth and 'h'eight of the 2d area, 'align'ment specification
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ * area contain co-ordinates of TL corner Tile and BR corner Tile of
+ * the rectangle (inclusive)
+ */
+static s32 sita_reserve_2d(struct tcm *tcm, u16 h, u16 w, u8 align,
+			   struct tcm_area *area)
+{
+	s32 ret = 0;
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+	/* we only support 1, 32 and 64 as alignment */
+	u16 stride = align <= 1 ? 1 : align <= 32 ? 32 : 64;
+	struct slot slot = {0};
+
+	area->is2d = true;
+
+	/* align must be 2 power */
+	if (align & (align - 1) || align > 64)
+		return -EINVAL;
+
+	mutex_lock(&(pvt->mtx));
+	ret = scan_areas_and_find_fit(tcm, w, h, stride, area);
+	if (!ret) {
+		slot.busy = true;
+		slot.parent = *area;
+
+		fill_2d_area(tcm, area, slot);
+		insert_element(&(pvt->res), area);
+	}
+	mutex_unlock(&(pvt->mtx));
+	return ret;
+}
+
+/**
+ * @description: unreserve 2d or 1D allocations if previously allocated
+ *
+ * @input:'area' specification: for 2D this should contain
+ * TL Corner and BR Corner of the 2D area, or for 1D allocation this should
+ * contain the start and end Tiles
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ * the to_be_removed_area is removed from g_allocation_list and the
+ * corresponding tiles are marked 'NOT_OCCUPIED'
+ *
+ */
+static s32 sita_free(struct tcm *tcm, struct tcm_area *area)
+{
+	s32 ret = 0;
+	struct slot slot = {0};
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+	u16 is2d;
+
+	slot.busy = false;
+	mutex_lock(&(pvt->mtx));
+	/*First we check if the given Area is aleast valid in our list*/
+	ret = rem_element_with_match(&(pvt->res), area, &is2d);
+
+	/* If we found a positive match & removed the area details from list
+	 * then we clear the contents of the associated tiles in the global
+	 * container*/
+	if (!ret) {
+		if (is2d)
+			fill_2d_area(tcm, area, slot);
+		else
+			fill_1d_area(tcm, area, slot);
+	}
+	mutex_unlock(&(pvt->mtx));
+	return ret;
+}
+
+/**
+ * @description: raster scan right to left from top to bottom; find if there is
+ * a free area to fit a given w x h inside the 'scan area'. If there is a free
+ * area, then adds to maybes candidates, which later is sent for selection
+ * as per pre-defined criteria.
+ *
+ * @input:'w x h' width and height of the allocation area.
+ * 'stride' - 64/32/None for start address alignment
+ * 'field' - area in which the scan operation should take place
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ * the 'area' area contains TL and BR corners of the allocated area
+ *
+ */
+static s32 scan_r2l_t2b(struct tcm *tcm, u16 w, u16 h, u16 stride,
+		 struct tcm_area *field, struct tcm_area *area)
+{
+	s32 xx = 0, yy = 0;
+	s16 start_x = -1, end_x = -1, start_y = -1, end_y = -1;
+	s16 found_x = -1, found_y = -1;
+	LIST_HEAD(maybes);
+	struct tcm_area candidate = {0};
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	PA(2, "scan_r2l_t2b:", field);
+
+	start_x = field->p0.x;
+	end_x = field->p1.x;
+	start_y = field->p0.y;
+	end_y = field->p1.y;
+
+	/* check scan area co-ordinates */
+	if (field->p0.x < field->p1.x ||
+	    field->p1.y < field->p0.y)
+		return -EINVAL;
+
+	/* check if allocation would fit in scan area */
+	if (w > INCL_LEN(start_x, end_x) || h > INCL_LEN(end_y, start_y))
+		return -ENOSPC;
+
+	/* adjust start_x and end_y, as allocation would not fit beyond */
+	start_x = ALIGN_DOWN(start_x - w + 1, stride); /* - 1 to be inclusive */
+	end_y = end_y - h + 1;
+
+	/* check if allocation would still fit in scan area */
+	if (start_x < end_x)
+		return -ENOSPC;
+
+	P2("ali=%d x=%d..%d y=%d..%d", stride, start_x, end_x, start_y, end_y);
+
+	/*
+	 * Start scanning: These scans are always inclusive ones  so if we are
+	 * given a start x = 0 is a valid value  so if we have a end_x = 255,
+	 * 255th element is also checked
+	 */
+	for (yy = start_y; yy <= end_y; yy++) {
+		for (xx = start_x; xx >= end_x; xx -= stride) {
+			if (!pvt->map[xx][yy].busy) {
+				if (check_fit_r_and_b(tcm, w, h, xx, yy)) {
+					P3("found shoulder: %d,%d", xx, yy);
+					found_x = xx;
+					found_y = yy;
+					/* Insert this candidate, it is just a
+						co-ordinate, reusing Area */
+					assign(&candidate, xx, yy, 0, 0);
+					insert_element(&maybes, &candidate);
+#ifdef X_SCAN_LIMITER
+					/* change upper x bound */
+					end_x = xx + 1;
+#endif
+					break;
+				}
+			} else {
+				/* Optimization required only for Non Aligned,
+				Aligned anyways skip by 32/64 tiles at a time */
+				if (stride == 1 &&
+				    pvt->map[xx][yy].parent.is2d) {
+					xx = pvt->map[xx][yy].parent.p0.x;
+					P3("moving to: %d,%d", xx, yy);
+				}
+			}
+		}
+
+		/* if you find a free area shouldering the given scan area on
+		   then we can break */
+#ifdef Y_SCAN_LIMITER
+		if (found_x == start_x)
+			break;
+#endif
+	}
+
+	if (list_empty(&maybes))
+		return -ENOSPC;
+
+	select_candidate(tcm, w, h, &maybes, field, CR_R2L_T2B, area);
+	/* dump_list_entries(maybes); */
+	clean_list(&maybes);
+	return 0;
+}
+
+#ifdef SCAN_BOTTOM_UP
+/**
+ * @description: raster scan right to left from bottom to top; find if there is
+ * a free area to fit a given w x h inside the 'scan area'. If there is a free
+ * area, then adds to maybes candidates, which later is sent for selection
+ * as per pre-defined criteria.
+ *
+ * @input:'w x h' width and height of the allocation area.
+ * 'stride' - 64/32/None for start address alignment
+ * 'field' - area in which the scan operation should take place
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ * the 'area' area contains TL and BR corners of the allocated area
+ *
+ */
+static s32 scan_r2l_b2t(struct tcm *tcm, u16 w, u16 h, u16 stride,
+			struct tcm_area *field, struct tcm_area *area)
+{
+	/* TODO: Should I check scan area?
+	 * Might have to take it as input during initialization
+	 */
+	s32 xx = 0, yy = 0;
+	s16 start_x = -1, end_x = -1, start_y = -1, end_y = -1;
+	s16 found_x = -1, found_y = -1;
+	LIST_HEAD(maybes);
+	struct tcm_area candidate = {0};
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	PA(2, "scan_r2l_b2t:", field);
+
+	start_x = field->p0.x;
+	end_x = field->p1.x;
+	start_y = field->p0.y;
+	end_y = field->p1.y;
+
+	/* check scan area co-ordinates */
+	if (field->p1.x < field->p0.x ||
+	    field->p1.y < field->p0.y)
+		return -EINVAL;
+
+	/* check if allocation would fit in scan area */
+	if (w > INCL_LEN(start_x, end_x) || h > INCL_LEN(start_y, end_y))
+		return -ENOSPC;
+
+	/* adjust start_x and start_y, as allocation would not fit beyond */
+	start_x = ALIGN_DOWN(start_x - w + 1, stride); /* + 1 to be inclusive */
+	start_y = start_y - h + 1;
+
+	/* check if allocation would still fit in scan area */
+	if (start_x < end_x)
+		return -ENOSPC;
+
+	P2("ali=%d x=%d..%d y=%d..%d", stride, start_x, end_x, start_y, end_y);
+
+	/*
+	 * Start scanning: These scans are always inclusive ones  so if we are
+	 * given a start x = 0 is a valid value  so if we have a end_x = 255,
+	 * 255th element is also checked
+	 */
+	for (yy = start_y; yy >= end_y; yy--) {
+		for (xx = start_x; xx >= end_x; xx -= stride) {
+			if (!pvt->map[xx][yy].busy) {
+				if (check_fit_r_and_b(tcm, w, h, xx, yy)) {
+					P3("found shoulder: %d,%d", xx, yy);
+					found_x = xx;
+					found_y = yy;
+					/* Insert this candidate, it is just a
+						co-ordinate, reusing Area */
+					assign(&candidate, xx, yy, 0, 0);
+					insert_element(&maybes, &candidate);
+#ifdef X_SCAN_LIMITER
+					/* change upper x bound */
+					end_x = xx + 1;
+#endif
+					break;
+				}
+			} else {
+				/* Optimization required only for Non Aligned,
+				Aligned anyways skip by 32/64 tiles at a time */
+				if (stride == 1 &&
+				    pvt->map[xx][yy].parent.is2d) {
+					xx = pvt->map[xx][yy].parent.p0.x;
+					P3("moving to: %d,%d", xx, yy);
+				}
+			}
+
+		}
+
+		/* if you find a free area shouldering the given scan area on
+		   then we can break */
+#ifdef Y_SCAN_LIMITER
+		if (found_x == start_x)
+			break;
+#endif
+	}
+
+	if (list_empty(&maybes))
+		return -ENOSPC;
+
+	select_candidate(tcm, w, h, &maybes, field, CR_R2L_B2T, area);
+	/* dump_list_entries(maybes); */
+	clean_list(&maybes);
+	return 0;
+}
+#endif
+
+/**
+ * @description: raster scan left to right from top to bottom; find if there is
+ * a free area to fit a given w x h inside the 'scan area'. If there is a free
+ * area, then adds to maybes candidates, which later is sent for selection
+ * as per pre-defined criteria.
+ *
+ * @input:'w x h' width and height of the allocation area.
+ * 'stride' - 64/32/None for start address alignment
+ * 'field' - area in which the scan operation should take place
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ * the 'area' area contains TL and BR corners of the allocated area
+ *
+ */
+s32 scan_l2r_t2b(struct tcm *tcm, u16 w, u16 h, u16 stride,
+		 struct tcm_area *field, struct tcm_area *area)
+{
+	s32 xx = 0, yy = 0;
+	s16 start_x = -1, end_x = -1, start_y = -1, end_y = -1;
+	s16 found_x = -1, found_y = -1;
+	LIST_HEAD(maybes);
+	struct tcm_area candidate = {0};
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	PA(2, "scan_l2r_t2b:", field);
+
+	start_x = field->p0.x;
+	end_x = field->p1.x;
+	start_y = field->p0.y;
+	end_y = field->p1.y;
+
+	/* check scan area co-ordinates */
+	if (field->p1.x < field->p0.x ||
+	    field->p1.y < field->p0.y)
+		return -EINVAL;
+
+	/* check if allocation would fit in scan area */
+	if (w > INCL_LEN(end_x, start_x) || h > INCL_LEN(end_y, start_y))
+		return -ENOSPC;
+
+	start_x = ALIGN(start_x, stride);
+
+	/* check if allocation would still fit in scan area */
+	if (w > INCL_LEN(end_x, start_x))
+		return -ENOSPC;
+
+	/* adjust end_x and end_y, as allocation would not fit beyond */
+	end_x = end_x - w + 1; /* + 1 to be inclusive */
+	end_y = end_y - h + 1;
+
+	P2("ali=%d x=%d..%d y=%d..%d", stride, start_x, end_x, start_y, end_y);
+
+	/*
+	 * Start scanning: These scans are always inclusive ones  so if we are
+	 * given a start x = 0 is a valid value  so if we have a end_x = 255,
+	 * 255th element is also checked
+	 */
+	for (yy = start_y; yy <= end_y; yy++) {
+		for (xx = start_x; xx <= end_x; xx += stride) {
+			/* if NOT occupied */
+			if (!pvt->map[xx][yy].busy) {
+				if (check_fit_r_and_b(tcm, w, h, xx, yy)) {
+					P3("found shoulder: %d,%d", xx, yy);
+					found_x = xx;
+					found_y = yy;
+					/* Insert this candidate, it is just a
+						co-ordinate, reusing Area */
+					assign(&candidate, xx, yy, 0, 0);
+					insert_element(&maybes, &candidate);
+#ifdef X_SCAN_LIMITER
+					/* change upper x bound */
+					end_x = xx - 1;
+#endif
+					break;
+				}
+			} else {
+				/* Optimization required only for Non Aligned,
+				Aligned anyways skip by 32/64 tiles at a time */
+				if (stride == 1 &&
+				    pvt->map[xx][yy].parent.is2d) {
+					xx = pvt->map[xx][yy].parent.p1.x;
+					P3("moving to: %d,%d", xx, yy);
+				}
+			}
+		}
+		/* if you find a free area shouldering the given scan area on
+		   then we can break */
+#ifdef Y_SCAN_LIMITER
+		if (found_x == start_x)
+			break;
+#endif
+	}
+
+	if (list_empty(&maybes))
+		return -ENOSPC;
+
+	select_candidate(tcm, w, h, &maybes, field, CR_L2R_T2B, area);
+	/* dump_list_entries(maybes); */
+	clean_list(&maybes);
+	return 0;
+}
+
+#ifdef SCAN_BOTTOM_UP
+/**
+ * @description: raster scan left to right from bottom to top; find if there is
+ * a free area to fit a given w x h inside the 'scan area'. If there is a free
+ * area, then adds to maybes candidates, which later is sent for selection
+ * as per pre-defined criteria.
+ *
+ * @input:'w x h' width and height of the allocation area.
+ * 'stride' - 64/32/None for start address alignment
+ * 'field' - area in which the scan operation should take place
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ * the 'area' area contains TL and BR corners of the allocated area
+ *
+ */
+static s32 scan_l2r_b2t(struct tcm *tcm, u16 w, u16 h, u16 stride,
+			struct tcm_area *field, struct tcm_area *area)
+{
+	s32 xx = 0, yy = 0;
+	s16 start_x = -1, end_x = -1, start_y = -1, end_y = -1;
+	s16 found_x = -1, found_y = -1;
+	LIST_HEAD(maybes);
+	struct tcm_area candidate = {0};
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	PA(2, "scan_l2r_b2t:", field);
+
+	start_x = field->p0.x;
+	end_x = field->p1.x;
+	start_y = field->p0.y;
+	end_y = field->p1.y;
+
+	/* check scan area co-ordinates */
+	if (field->p1.x < field->p0.x ||
+	    field->p0.y < field->p1.y)
+		return -EINVAL;
+
+	/* check if allocation would fit in scan area */
+	if (w > INCL_LEN(end_x, start_x) || h > INCL_LEN(start_y, end_y))
+		return -ENOSPC;
+
+	start_x = ALIGN(start_x, stride);
+
+	/* check if allocation would still fit in scan area */
+	if (w > INCL_LEN(end_x, start_x))
+		return -ENOSPC;
+
+	/* adjust end_x and start_y, as allocation would not fit beyond */
+	end_x = end_x - w + 1; /* + 1 to be inclusive */
+	start_y = start_y - h + 1;
+
+	P2("ali=%d x=%d..%d y=%d..%d", stride, start_x, end_x, start_y, end_y);
+
+	/*
+	 * Start scanning: These scans are always inclusive ones  so if we are
+	 * given a start x = 0 is a valid value  so if we have a end_x = 255,
+	 * 255th element is also checked
+	 */
+	for (yy = start_y; yy >= end_y; yy--) {
+		for (xx = start_x; xx <= end_x; xx += stride) {
+			/* if NOT occupied */
+			if (!pvt->map[xx][yy].busy) {
+				if (check_fit_r_and_b(tcm, w, h, xx, yy)) {
+					P3("found shoulder: %d,%d", xx, yy);
+					found_x = xx;
+					found_y = yy;
+					/* Insert this candidate, it is just a
+					 co-ordinate, reusing Area */
+					assign(&candidate, xx, yy, 0, 0);
+					insert_element(&maybes, &candidate);
+#ifdef X_SCAN_LIMITER
+					/* change upper x bound */
+					end_x = xx - 1;
+#endif
+					break;
+				}
+			} else {
+				/* Optimization required only for Non Aligned,
+				Aligned anyways skip by 32/64 tiles at a time */
+				if (stride == 1 &&
+				    pvt->map[xx][yy].parent.is2d) {
+					xx = pvt->map[xx][yy].parent.p1.x;
+					P3("moving to: %d,%d", xx, yy);
+				}
+			}
+		}
+
+		/* if you find a free area shouldering the given scan area on
+		   then we can break */
+#ifdef Y_SCAN_LIMITER
+		if (found_x == start_x)
+			break;
+#endif
+	}
+
+	if (list_empty(&maybes))
+		return -ENOSPC;
+
+	select_candidate(tcm, w, h, &maybes, field, CR_L2R_B2T, area);
+	/* dump_list_entries(maybes); */
+	clean_list(&maybes);
+	return 0;
+}
+#endif
+/*
+Note: In General the cordinates specified in the scan area area relevant to the
+scan sweep directions. i.e A scan Area from Top Left Corner will have
+p0.x <= p1.x and p0.y <= p1.y. Where as A scan Area from bottom Right Corner
+will have p1.x <= p0.x and p1.y <= p0.y
+*/
+
+/**
+ * @description: raster scan right to left from bottom to top; find if there are
+ * continuous free pages(one slot is one page, continuity always from left to
+ * right) inside the 'scan area'. If there are enough continous free pages,
+ * then it returns the start and end Tile/page co-ordinates inside 'area'
+ *
+ * @input:'num_pages' required,
+ * 'field' - area in which the scan operation should take place
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ * the 'area' area contains start and end slot (inclusive).
+ *
+ */
+static s32 scan_r2l_b2t_one_dim(struct tcm *tcm, u32 num_pages,
+		 struct tcm_area *field, struct tcm_area *area)
+{
+	s32 fit = false;
+	u16 x, y;
+	u16 left_x, left_y, busy_x, busy_y;
+	s32 ret = 0;
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	/* check scan area co-ordinates */
+	if (field->p0.y < field->p1.y)
+		return -EINVAL;
+
+	PA(2, "scan_r2l_b2t_one_dim:", field);
+
+	/* Note: Checking sanctity of scan area
+	 * The reason for checking this that 1D allocations assume that the X
+	 ranges the entire TilerSpace X ie ALL Columns
+	 * The scan area can limit only the Y ie, Num of Rows for 1D allocation.
+	 We also expect we could have only 1 row for 1D allocation
+	 * i.e our field p0.y and p1.y may have a same value.
+	 */
+
+	/* only support full width 1d scan area */
+	if (pvt->width != field->p0.x - field->p1.x + 1)
+		return -EINVAL;
+
+	/* check if allocation would fit in scan area */
+	if (num_pages > pvt->width * INCL_LEN(field->p0.y, field->p1.y))
+		return -ENOSPC;
+
+	left_x = field->p0.x;
+	left_y = field->p0.y;
+	while (!ret) {
+		x = left_x;
+		y = left_y;
+
+		if (!pvt->map[x][y].busy) {
+			ret = move_left(tcm, x, y, num_pages - 1,
+					&left_x, &left_y);
+			if (ret)
+				break; /* out of space */
+
+			P3("moved left %d slots: %d,%d", num_pages - 1,
+						left_x, left_y);
+			fit = check_fit_r_one_dim(tcm, left_x, left_y,
+				  num_pages, &busy_x, &busy_y);
+			if (fit) {
+				assign(area, left_x, left_y,
+				       busy_x, busy_y);
+				break;
+			} else {
+				/* no fit, continue at the busy slot */
+				x = busy_x;
+				y = busy_y;
+			}
+		}
+
+		/* now the tile is occupied, skip busy region */
+		if (pvt->map[x][y].parent.is2d) {
+			busy_x = pvt->map[x][y].parent.p0.x;
+			busy_y = y;
+		} else {
+			busy_x = pvt->map[x][y].parent.p0.x;
+			busy_y = pvt->map[x][y].parent.p0.y;
+		}
+		x = busy_x;
+		y = busy_y;
+
+		P3("moving left from: %d,%d", x, y);
+		ret = move_left(tcm, x, y, 1, &left_x, &left_y);
+	}
+
+	return fit ? 0 : -ENOSPC;
+}
+
+/**
+ * @description:
+ *
+ *
+ *
+ *
+ * @input:
+ *
+ *
+ * @return 0 on success, non-0 error value on failure. On success
+ */
+static s32 scan_areas_and_find_fit(struct tcm *tcm, u16 w, u16 h, u16 stride,
+			    struct tcm_area *area)
+{
+	s32 ret = 0;
+	struct tcm_area field = {0};
+	u16 boundary_x = 0, boundary_y = 0;
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+	s32 need_scan = 2;
+
+	if (stride > 1) {
+		boundary_x = pvt->div_pt.x - 1;
+		boundary_y = pvt->div_pt.y - 1;
+
+		/* more intelligence here */
+		if (w > pvt->div_pt.x) {
+			boundary_x = pvt->width - 1;
+			need_scan--;
+		}
+		if (h > pvt->div_pt.y) {
+			boundary_y = pvt->height - 1;
+			need_scan--;
+		}
+
+		assign(&field, 0, 0, boundary_x, boundary_y);
+		ret = scan_l2r_t2b(tcm, w, h, stride, &field, area);
+		if (ret != 0 && need_scan) {
+			/* scan the entire container if nothing found */
+			assign(&field, 0, 0, pvt->width - 1, pvt->height - 1);
+			ret = scan_l2r_t2b(tcm, w, h, stride, &field, area);
+		}
+	} else if (stride == 1) {
+		boundary_x = pvt->div_pt.x;
+		boundary_y = pvt->div_pt.y - 1;
+
+		/* more intelligence here */
+		if (w > (pvt->width - pvt->div_pt.x)) {
+			boundary_x = 0;
+			need_scan--;
+		}
+		if (h > pvt->div_pt.y) {
+			boundary_y = pvt->height - 1;
+			need_scan--;
+		}
+
+		assign(&field, pvt->width - 1, 0, boundary_x, boundary_y);
+		ret = scan_r2l_t2b(tcm, w, h, stride, &field, area);
+
+		if (ret != 0 && need_scan) {
+			/* scan the entire container if nothing found */
+			assign(&field, pvt->width - 1, 0, 0,
+			       pvt->height - 1);
+			ret = scan_r2l_t2b(tcm, w, h, stride, &field,
+					   area);
+		}
+	}
+
+	/* 3/30/2010: moved aligned to left, and unaligned to right side. */
+#if 0
+	else if (stride == 1) {
+		/* use 64-align area so we don't grow down and shrink 1D area */
+		if (h > pvt->div_pt.y) {
+			need_scan -= 2;
+			assign(&field, 0, 0, pvt->width - 1, pvt->height - 1);
+			ret = scan_l2r_t2b(tcm, w, h, stride, &field, area);
+		} else {
+			assign(&field, 0, pvt->div_pt.y - 1, pvt->width - 1, 0);
+			/* scan up in 64 and 32 areas accross whole width */
+			ret = scan_l2r_b2t(tcm, w, h, stride, &field, area);
+		}
+
+		if (ret != 0 && need_scan) {
+			assign(&field, 0, 0, pvt->width - 1, pvt->height - 1);
+			ret = scan_l2r_t2b(tcm,  w, h, stride, &field, area);
+		}
+	}
+#endif
+	return ret;
+}
+
+static s32 check_fit_r_and_b(struct tcm *tcm, u16 w, u16 h, u16 left_x,
+			     u16 top_y)
+{
+	u16 xx = 0, yy = 0;
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	for (yy = top_y; yy < top_y + h; yy++) {
+		for (xx = left_x; xx < left_x + w; xx++) {
+			if (pvt->map[xx][yy].busy)
+				return false;
+		}
+	}
+	return true;
+}
+
+static s32 check_fit_r_one_dim(struct tcm *tcm, u16 x, u16 y, u32 num_pages,
+			u16 *busy_x, u16 *busy_y)
+{
+	s32 ret = 0;
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+	s32 i = 0;
+	*busy_x = x;
+	*busy_y = y;
+
+	P2("checking fit for %d pages from %d,%d", num_pages, x, y);
+	while (i < num_pages) {
+		if (pvt->map[x][y].busy) {
+			/* go to the start of the blocking allocation
+			   to avoid unecessary checking */
+			if (pvt->map[x][y].parent.is2d) {
+				*busy_x = pvt->map[x][y].parent.p0.x;
+				*busy_y = y;
+			} else {
+				*busy_x = pvt->map[x][y].parent.p0.x;
+				*busy_y = pvt->map[x][y].parent.p0.y;
+			}
+			/* TODO: Could also move left in case of 2D */
+			P2("after busy slot at: %d,%d", *busy_x, *busy_y);
+			return false;
+		}
+
+		i++;
+
+		/* break here so busy_x, busy_y will be correct */
+		if (i == num_pages)
+			break;
+
+		ret = move_right(tcm, x, y, 1, busy_x, busy_y);
+		if (ret)
+			return false;
+
+		x = *busy_x;
+		y = *busy_y;
+	}
+
+	return true;
+}
+
+static void fill_2d_area(struct tcm *tcm, struct tcm_area *area,
+			struct slot slot)
+{
+	s32 x, y;
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	PA(2, "fill 2d area", area);
+	for (x = area->p0.x; x <= area->p1.x; ++x)
+		for (y = area->p0.y; y <= area->p1.y; ++y)
+			pvt->map[x][y] = slot;
+}
+
+/* area should be a valid area */
+static void fill_1d_area(struct tcm *tcm, struct tcm_area *area,
+			struct slot slot)
+{
+	u16 x = 0, y = 0;
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	PA(2, "fill 1d area", area);
+	x = area->p0.x;
+	y = area->p0.y;
+
+	while (!(x == area->p1.x && y == area->p1.y)) {
+		pvt->map[x++][y] = slot;
+		if (x == pvt->width) {
+			x = 0;
+			y++;
+		}
+	}
+	/* set the last slot */
+	pvt->map[x][y] = slot;
+}
+
+static void select_candidate(struct tcm *tcm, u16 w, u16 h,
+		     struct list_head *maybes,
+		     struct tcm_area *field, s32 criteria,
+		     struct tcm_area *area)
+{
+	/* bookkeeping the best match and the one evaluated */
+	struct area_spec *best = NULL;
+	struct nearness_factor best_factor = {0};
+	struct neighbour_stats best_stats = {0};
+	u16 win_neighs = 0;
+
+	/* bookkeeping the current one being evaluated */
+	struct area_spec *elem = NULL;
+	struct nearness_factor factor = {0};
+	struct neighbour_stats stats = {0};
+	u16 neighs = 0;
+
+	bool better; /* whether current is better */
+
+	/* we default to the 1st candidate */
+	best = list_first_entry(maybes, struct area_spec, list);
+
+	/*i f there is only one candidate then that is the selection*/
+
+	/* If first found is enabled then we just provide bluntly the first
+	found candidate
+	  * NOTE: For Horizontal bias we just give the first found, because our
+	  * scan is Horizontal raster based and the first candidate will always
+	  * be the same as if selecting the Horizontal one.
+	  */
+	if (list_is_singular(maybes) ||
+	    criteria & CR_FIRST_FOUND || criteria & CR_BIAS_HORIZONTAL)
+		/* Note: Sure we could have done this in the previous function,
+		but just wanted this to be cleaner so having
+		  * one place where the selection is made. Here I am returning
+		  the first one
+		  */
+		goto done;
+
+	/* lets calculate for the first candidate and assign him the best and
+	replace with the one who has better credentials w/ to the criteria */
+
+	get_busy_neigh_stats(tcm, w, h, &best->area, &best_stats);
+	win_neighs = BOUNDARY(&best_stats) +
+			   OCCUPIED(&best_stats);
+	get_nearness_factor(field, &best->area, &best_factor);
+
+	list_for_each_entry(elem, maybes->next, list) {
+		better = false;
+
+		/* calculate required statistics */
+		get_busy_neigh_stats(tcm, w, h, &elem->area, &stats);
+		get_nearness_factor(field, &elem->area, &factor);
+		neighs =  BOUNDARY(&stats) + OCCUPIED(&stats);
+
+		/* see if this are is better than the best so far */
+
+		/* neighbor check */
+		if ((criteria & CR_MAX_NEIGHS) &&
+			neighs > win_neighs)
+			better = true;
+
+		/* vertical bias check */
+		if ((criteria & CR_BIAS_VERTICAL) &&
+		/*
+		 * NOTE: not checking if lengths are same, because that does not
+		 * find new shoulders on the same row after a fit
+		 */
+			INCL_LEN_MOD(elem->area.p0.y, field->p0.y) >
+			INCL_LEN_MOD(best->area.p0.y, field->p0.y))
+			better = true;
+
+		/* diagonal balance check */
+		if ((criteria & CR_DIAGONAL_BALANCE) &&
+			win_neighs <= neighs &&
+			(win_neighs < neighs ||
+			 /* this implies that neighs and occupied match */
+			 OCCUPIED(&best_stats) < OCCUPIED(&stats) ||
+			 (OCCUPIED(&best_stats) == OCCUPIED(&stats) &&
+			  /* check the nearness factor */
+			  best_factor.x + best_factor.y > factor.x + factor.y)))
+			better = true;
+
+		if (better) {
+			best = elem;
+			best_factor = factor;
+			best_stats = stats;
+			win_neighs = neighs;
+		}
+	}
+
+done:
+	assign(area, best->area.p0.x, best->area.p0.y,
+	       best->area.p0.x + w - 1, best->area.p0.y + h - 1);
+}
+
+/* get the nearness factor of an area in a search field */
+static void get_nearness_factor(struct tcm_area *field,
+			struct tcm_area *area, struct nearness_factor *nf)
+{
+	/* For the following calculation we need worry of +/- sign, the
+	relative distances take of this. Multiplied by 1000, there
+	is no floating point arithmetic used in kernel */
+
+	nf->x = (s32)(area->p0.x - field->p0.x) * 1000 /
+		(field->p1.x - field->p0.x);
+	nf->y = (s32)(area->p0.y - field->p0.y) * 1000 /
+		(field->p1.y - field->p0.y);
+}
+
+/* Neighbours
+ *
+ *   |<-----T------>|
+ *  _ _______________  _
+ * L |     Ar       | R
+ * _ |______________|_
+ *   |<-----B------>|
+ */
+static s32 get_busy_neigh_stats(struct tcm *tcm, u16 width, u16 height,
+			 struct tcm_area *top_left_corner,
+			 struct neighbour_stats *neighbour_stat)
+{
+	s16 xx = 0, yy = 0;
+	struct tcm_area left_edge;
+	struct tcm_area right_edge;
+	struct tcm_area top_edge;
+	struct tcm_area bottom_edge;
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+
+	if (neighbour_stat == NULL)
+		return -EINVAL;
+
+	if (width == 0 || height == 0)
+		return -EINVAL;
+
+	/* Clearing any exisiting values */
+	memset(neighbour_stat, 0, sizeof(*neighbour_stat));
+
+	/* Finding Top Edge */
+	assign(&top_edge, top_left_corner->p0.x, top_left_corner->p0.y,
+	       top_left_corner->p0.x + width - 1, top_left_corner->p0.y);
+
+	/* Finding Bottom Edge */
+	assign(&bottom_edge, top_left_corner->p0.x,
+	       top_left_corner->p0.y+height - 1,
+	       top_left_corner->p0.x + width - 1,
+	       top_left_corner->p0.y + height - 1);
+
+	/* Finding Left Edge */
+	assign(&left_edge, top_left_corner->p0.x, top_left_corner->p0.y,
+	       top_left_corner->p0.x, top_left_corner->p0.y + height - 1);
+
+	/* Finding Right Edge */
+	assign(&right_edge, top_left_corner->p0.x + width - 1,
+		top_left_corner->p0.y,
+		top_left_corner->p0.x + width - 1,
+		top_left_corner->p0.y + height - 1);
+
+	/* dump_area(&top_edge);
+	dump_area(&right_edge);
+	dump_area(&bottom_edge);
+	dump_area(&left_edge);
+	*/
+
+	/* Parsing through top & bottom edge */
+	for (xx = top_edge.p0.x; xx <= top_edge.p1.x; xx++) {
+		if (top_edge.p0.y - 1 < 0)
+			neighbour_stat->top_boundary++;
+		else if (pvt->map[xx][top_edge.p0.y - 1].busy)
+			neighbour_stat->top_occupied++;
+
+		if (bottom_edge.p0.y + 1 > pvt->height - 1)
+			neighbour_stat->bottom_boundary++;
+		else if (pvt->map[xx][bottom_edge.p0.y+1].busy)
+			neighbour_stat->bottom_occupied++;
+	}
+
+	/* Parsing throught left and right edge */
+	for (yy = left_edge.p0.y; yy <= left_edge.p1.y; ++yy) {
+		if (left_edge.p0.x - 1 < 0)
+			neighbour_stat->left_boundary++;
+		else if (pvt->map[left_edge.p0.x - 1][yy].busy)
+			neighbour_stat->left_occupied++;
+
+		if (right_edge.p0.x + 1 > pvt->width - 1)
+			neighbour_stat->right_boundary++;
+		else if (pvt->map[right_edge.p0.x + 1][yy].busy)
+			neighbour_stat->right_occupied++;
+
+	}
+
+	return 0;
+}
+
+/**
+	@description: Retrieves the parent area of the page at p0.x, p0.y if
+	occupied
+	@input:co-ordinates of the page (p0.x, p0.y) whoes parent area
+	is required
+	@return 0 on success, non-0 error value on failure. On success
+
+	parent will contain co-ordinates (TL & BR corner) of the parent
+	area
+*/
+static s32 sita_get_parent(struct tcm *tcm, struct tcm_pt *pt,
+		    struct tcm_area *parent)
+{
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+	s32 res = 0;
+
+	mutex_lock(&(pvt->mtx));
+
+	if (pvt->map[pt->x][pt->y].busy) {
+		*parent = pvt->map[pt->x][pt->y].parent;
+	} else {
+		memset(parent, 0, sizeof(*parent));
+		res = -ENOENT;
+	}
+
+	mutex_unlock(&(pvt->mtx));
+
+	return res;
+}
+
+static s32 move_left(struct tcm *tcm, u16 x, u16 y, u32 num_pages,
+		     u16 *xx, u16 *yy)
+{
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+	u32 pos = x + pvt->width * y;
+
+	if (pos < num_pages)
+		return -ENOSPC;
+
+	pos -= num_pages;
+	*xx = pos % pvt->width;
+	*yy = pos / pvt->width;
+	return 0;
+}
+
+static s32 move_right(struct tcm *tcm, u16 x, u16 y, u32 num_pages,
+		      u16 *xx, u16 *yy)
+{
+	struct sita_pvt *pvt = (struct sita_pvt *)tcm->pvt;
+	u32 pos = x + pvt->width * y;
+
+	if (num_pages > pvt->width * pvt->height - pos)
+		return -ENOSPC;
+
+	pos += num_pages;
+	*xx = pos % pvt->width;
+	*yy = pos / pvt->width;
+	return 0;
+}
+
diff --git a/drivers/media/video/tiler/tcm/tcm_sita.h b/drivers/media/video/tiler/tcm/tcm_sita.h
new file mode 100644
index 000000000000..fb5f8e89192c
--- /dev/null
+++ b/drivers/media/video/tiler/tcm/tcm_sita.h
@@ -0,0 +1,39 @@
+/*
+ * tcm_sita.h
+ *
+ * SImple Tiler Allocator (SiTA) interface.
+ *
+ * Author: Ravi Ramachandra <r.ramachandra@ti.com>
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef TCM_SITA_H_
+#define TCM_SITA_H_
+
+#include "tcm.h"
+
+/**
+ * Create a SiTA tiler container manager.
+ *
+ * @param width  Container width
+ * @param height Container height
+ * @param attr   preferred division point between 64-aligned
+ *  		 allocation (top left), 32-aligned allocations
+ *  		 (top right), and page mode allocations (bottom)
+ *
+ * @return TCM instance
+ */
+struct tcm *sita_init(u16 width, u16 height, struct tcm_pt *attr);
+
+TCM_INIT(sita_init, struct tcm_pt);
+
+#endif /* TCM_SITA_H_ */
diff --git a/drivers/media/video/tiler/tcm/tcm_utils.h b/drivers/media/video/tiler/tcm/tcm_utils.h
new file mode 100644
index 000000000000..7d0ed5c149b8
--- /dev/null
+++ b/drivers/media/video/tiler/tcm/tcm_utils.h
@@ -0,0 +1,59 @@
+/*
+ * tcm_utils.h
+ *
+ * Utility functions for implementing TILER container managers.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _TCM_UTILS_H
+#define _TCM_UTILS_H
+
+#include "tcm.h"
+
+#define AREA_FMT   "(%03d %03d)-(%03d %03d)"
+#define AREA(area) (area).p0.x, (area).p0.y, (area).p1.x, (area).p1.y
+
+/* TCM_ALG_NAME must be defined to use the debug methods */
+
+#ifdef DEBUG
+#define IFDEBUG(x) x
+#else
+#define IFDEBUG(x) do { if (0) x; } while (0)
+#endif
+
+#define P(level, fmt, ...) \
+	IFDEBUG(printk(level TCM_ALG_NAME ":%d:%s()" fmt "\n", \
+			__LINE__, __func__, ##__VA_ARGS__))
+
+#define P1(fmt, ...) P(KERN_NOTICE, fmt, ##__VA_ARGS__)
+#define P2(fmt, ...) P(KERN_INFO, fmt, ##__VA_ARGS__)
+#define P3(fmt, ...) P(KERN_DEBUG, fmt, ##__VA_ARGS__)
+
+#define PA(level, msg, p_area) P##level(msg " " AREA_FMT "\n", AREA(*(p_area)))
+
+/* assign coordinates to area */
+static inline
+void assign(struct tcm_area *a, u16 x0, u16 y0, u16 x1, u16 y1)
+{
+	a->p0.x = x0;
+	a->p0.y = y0;
+	a->p1.x = x1;
+	a->p1.y = y1;
+}
+
+static inline
+void dump_area(struct tcm_area *area)
+{
+	printk(KERN_NOTICE AREA_FMT "\n", AREA(*area));
+}
+
+#endif
diff --git a/drivers/media/video/tiler/tiler.c b/drivers/media/video/tiler/tiler.c
new file mode 100644
index 000000000000..0d4e572a3400
--- /dev/null
+++ b/drivers/media/video/tiler/tiler.c
@@ -0,0 +1,1583 @@
+/*
+ * tiler.c
+ *
+ * TILER driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cdev.h>            /* struct cdev */
+#include <linux/kdev_t.h>          /* MKDEV() */
+#include <linux/fs.h>              /* register_chrdev_region() */
+#include <linux/device.h>          /* struct class */
+#include <linux/platform_device.h> /* platform_device() */
+#include <linux/err.h>             /* IS_ERR() */
+#include <linux/uaccess.h>         /* copy_to_user */
+#include <linux/mm.h>
+#include <linux/mm_types.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/dma-mapping.h>
+#include <linux/pagemap.h>         /* page_cache_release() */
+#include <linux/slab.h>
+
+#include <mach/tiler.h>
+#include <mach/dmm.h>
+#include "../dmm/tmm.h"
+#include "tiler_def.h"
+#include "tcm/tcm_sita.h"	/* Algo Specific header */
+
+#include <linux/syscalls.h>
+
+struct tiler_dev {
+	struct cdev cdev;
+};
+
+struct platform_driver tiler_driver_ldm = {
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "tiler",
+	},
+	.probe = NULL,
+	.shutdown = NULL,
+	.remove = NULL,
+};
+
+/* per process (thread group) info */
+struct process_info {
+	struct list_head list;		/* other processes */
+	struct list_head groups;	/* my groups */
+	struct list_head bufs;		/* my registered buffers */
+	pid_t pid;			/* really: thread group ID */
+	u32 refs;			/* open tiler devices, 0 for processes
+					   tracked via kernel APIs */
+	bool kernel;			/* tracking kernel objects */
+};
+
+/* per group info (within a process) */
+struct gid_info {
+	struct list_head by_pid;	/* other groups */
+	struct list_head areas;		/* all areas in this pid/gid */
+	struct list_head reserved;	/* areas pre-reserved */
+	struct list_head onedim;	/* all 1D areas in this pid/gid */
+	u32 gid;			/* group ID */
+	struct process_info *pi;	/* parent */
+};
+
+struct list_head blocks;
+struct list_head procs;
+struct list_head orphan_areas;
+struct list_head orphan_onedim;
+
+struct area_info {
+	struct list_head by_gid;	/* areas in this pid/gid */
+	struct list_head blocks;	/* blocks in this area */
+	u32 nblocks;			/* # of blocks in this area */
+
+	struct tcm_area area;		/* area details */
+	struct gid_info *gi;		/* link to parent, if still alive */
+};
+
+struct mem_info {
+	struct list_head global;	/* reserved / global blocks */
+	u32 sys_addr;          /* system space (L3) tiler addr */
+	u32 num_pg;            /* number of pages in page-list */
+	u32 usr;               /* user space address */
+	u32 *pg_ptr;           /* list of mapped struct page pointers */
+	struct tcm_area area;
+	u32 *mem;              /* list of alloced phys addresses */
+	u32 refs;              /* number of times referenced */
+	bool alloced;			/* still alloced */
+
+	struct list_head by_area;	/* blocks in the same area / 1D */
+	void *parent;			/* area info for 2D, else group info */
+};
+
+struct __buf_info {
+	struct list_head by_pid;		/* list of buffers per pid */
+	struct tiler_buf_info buf_info;
+	struct mem_info *mi[TILER_MAX_NUM_BLOCKS];	/* blocks */
+};
+
+#define TILER_FORMATS 4
+
+static s32 tiler_major;
+static s32 tiler_minor;
+static struct tiler_dev *tiler_device;
+static struct class *tilerdev_class;
+static u32 id;
+static struct mutex mtx;
+static struct tcm *tcm[TILER_FORMATS];
+static struct tmm *tmm[TILER_FORMATS];
+static u32 *dmac_va;
+static dma_addr_t dmac_pa;
+
+#define TCM(fmt)        tcm[(fmt) - TILFMT_8BIT]
+#define TCM_SS(ssptr)   TCM(TILER_GET_ACC_MODE(ssptr))
+#define TCM_SET(fmt, i) tcm[(fmt) - TILFMT_8BIT] = i
+#define TMM(fmt)        tmm[(fmt) - TILFMT_8BIT]
+#define TMM_SS(ssptr)   TMM(TILER_GET_ACC_MODE(ssptr))
+#define TMM_SET(fmt, i) tmm[(fmt) - TILFMT_8BIT] = i
+
+/* get process info, and increment refs for device tracking */
+static struct process_info *__get_pi(pid_t pid, bool kernel)
+{
+	struct process_info *pi;
+
+	/* find process context */
+	mutex_lock(&mtx);
+	list_for_each_entry(pi, &procs, list) {
+		if (pi->pid == pid && pi->kernel == kernel)
+			goto done;
+	}
+
+	/* create process context */
+	pi = kmalloc(sizeof(*pi), GFP_KERNEL);
+	if (!pi)
+		goto done;
+
+	memset(pi, 0, sizeof(*pi));
+	pi->pid = pid;
+	pi->kernel = kernel;
+	INIT_LIST_HEAD(&pi->groups);
+	INIT_LIST_HEAD(&pi->bufs);
+	list_add(&pi->list, &procs);
+done:
+	if (pi && !kernel)
+		pi->refs++;
+	mutex_unlock(&mtx);
+	return pi;
+}
+
+/* allocate an reserved area of size, alignment and link it to gi */
+static struct area_info *area_new(u16 width, u16 height, u16 align,
+				  struct tcm *tcm, struct gid_info *gi)
+{
+	struct area_info *ai = kmalloc(sizeof(*ai), GFP_KERNEL);
+	if (!ai)
+		return NULL;
+
+	/* set up empty area info */
+	memset(ai, 0x0, sizeof(*ai));
+	INIT_LIST_HEAD(&ai->blocks);
+
+	/* reserve an allocation area */
+	if (tcm_reserve_2d(tcm, width, height, align, &ai->area)) {
+		kfree(ai);
+		return NULL;
+	}
+
+	ai->gi = gi;
+	mutex_lock(&mtx);
+	list_add_tail(&ai->by_gid, &gi->areas);
+	mutex_unlock(&mtx);
+	return ai;
+}
+
+/* (must have mutex) free an area and return NULL */
+static inline void _m_area_free(struct area_info *ai)
+{
+	if (ai) {
+		list_del(&ai->by_gid);
+		kfree(ai);
+	}
+}
+
+static s32 __analize_area(enum tiler_fmt fmt, u32 width, u32 height,
+			  u16 *x_area, u16 *y_area, u16 *band,
+			  u16 *align, u16 *offs)
+{
+	/* input: width, height is in pixels, align, offs in bytes */
+	/* output: x_area, y_area, band, align, offs in slots */
+
+	/* slot width, height, and row size */
+	u32 slot_w, slot_h, slot_row, bpp;
+
+	/* align must be 2 power */
+	if (*align & (*align - 1))
+		return -1;
+
+	switch (fmt) {
+	case TILFMT_8BIT:
+		slot_w = DMM_PAGE_DIMM_X_MODE_8;
+		slot_h = DMM_PAGE_DIMM_Y_MODE_8;
+		break;
+	case TILFMT_16BIT:
+		slot_w = DMM_PAGE_DIMM_X_MODE_16;
+		slot_h = DMM_PAGE_DIMM_Y_MODE_16;
+		break;
+	case TILFMT_32BIT:
+		slot_w = DMM_PAGE_DIMM_X_MODE_32;
+		slot_h = DMM_PAGE_DIMM_Y_MODE_32;
+		break;
+	case TILFMT_PAGE:
+		/* adjust size to accomodate offset, only do page alignment */
+		*align = PAGE_SIZE;
+		width += *offs & (PAGE_SIZE - 1);
+
+		/* for 1D area keep the height (1), width is in tiler slots */
+		*x_area = DIV_ROUND_UP(width, TILER_PAGE);
+		*y_area = *band = 1;
+
+		if (*x_area * *y_area > TILER_WIDTH * TILER_HEIGHT)
+			return -1;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+
+	/* get the # of bytes per row in 1 slot */
+	bpp = tilfmt_bpp(fmt);
+	slot_row = slot_w * bpp;
+
+	/* how many slots are can be accessed via one physical page */
+	*band = PAGE_SIZE / slot_row;
+
+	/* minimum alignment is 1 slot, default alignment is page size */
+	*align = ALIGN(*align ? : PAGE_SIZE, slot_row);
+
+	/* offset must be multiple of bpp */
+	if (*offs & (bpp - 1))
+		return -EINVAL;
+
+	/* round down the offset to the nearest slot size, and increase width
+	   to allow space for having the correct offset */
+	width += (*offs & (*align - 1)) / bpp;
+	*offs &= ~(*align - 1);
+
+	/* adjust to slots */
+	*x_area = DIV_ROUND_UP(width, slot_w);
+	*y_area = DIV_ROUND_UP(height, slot_h);
+	*align /= slot_row;
+	*offs /= slot_row;
+
+	if (*x_area > TILER_WIDTH || *y_area > TILER_HEIGHT)
+		return -1;
+	return 0x0;
+}
+
+/**
+ * Find a place where a 2D block would fit into a 2D area of the
+ * same height.
+ *
+ * @author a0194118 (3/19/2010)
+ *
+ * @param w	Width of the block.
+ * @param align	Alignment of the block.
+ * @param offs	Offset of the block (within alignment)
+ * @param ai	Pointer to area info
+ * @param next	Pointer to the variable where the next block
+ *              will be stored.  The block should be inserted
+ *              before this block.
+ *
+ * @return the end coordinate (x1 + 1) where a block would fit,
+ *         or 0 if it does not fit.
+ *
+ * (must have mutex)
+ */
+static u16 _m_blk_find_fit(u16 w, u16 align, u16 offs,
+		     struct area_info *ai, struct list_head **before)
+{
+	int x = ai->area.p0.x + w + offs;
+	struct mem_info *mi;
+
+	/* area blocks are sorted by x */
+	list_for_each_entry(mi, &ai->blocks, by_area) {
+		/* check if buffer would fit before this area */
+		if (x <= mi->area.p0.x) {
+			*before = &mi->by_area;
+			return x;
+		}
+		x = ALIGN(mi->area.p1.x + 1 - offs, align) + w + offs;
+	}
+	*before = &ai->blocks;
+
+	/* check if buffer would fit after last area */
+	return (x <= ai->area.p1.x + 1) ? x : 0;
+}
+
+/* (must have mutex) adds a block to an area with certain x coordinates */
+static inline
+struct mem_info *_m_add2area(struct mem_info *mi, struct area_info *ai,
+				u16 x0, u16 x1, struct list_head *before)
+{
+	mi->parent = ai;
+	mi->area = ai->area;
+	mi->area.p0.x = x0;
+	mi->area.p1.x = x1;
+	list_add_tail(&mi->by_area, before);
+	ai->nblocks++;
+	return mi;
+}
+
+static struct mem_info *get_2d_area(u16 w, u16 h, u16 align, u16 offs, u16 band,
+					struct gid_info *gi, struct tcm *tcm) {
+	struct area_info *ai = NULL;
+	struct mem_info *mi = NULL;
+	struct list_head *before = NULL;
+	u16 x = 0;   /* this holds the end of a potential area */
+
+	/* allocate map info */
+
+	/* see if there is available prereserved space */
+	mutex_lock(&mtx);
+	list_for_each_entry(mi, &gi->reserved, global) {
+		if (mi->area.tcm == tcm &&
+		    tcm_aheight(mi->area) == h &&
+		    tcm_awidth(mi->area) == w &&
+		    (mi->area.p0.x & (align - 1)) == offs) {
+			/* this area is already set up */
+
+			/* remove from reserved list */
+			list_del(&mi->global);
+			goto done;
+		}
+	}
+	mutex_unlock(&mtx);
+
+	/* if not, reserve a block struct */
+	mi = kmalloc(sizeof(*mi), GFP_KERNEL);
+	if (!mi)
+		return mi;
+	memset(mi, 0, sizeof(*mi));
+
+	/* see if allocation fits in one of the existing areas */
+	/* this sets x, ai and before */
+	mutex_lock(&mtx);
+	list_for_each_entry(ai, &gi->areas, by_gid) {
+		if (ai->area.tcm == tcm &&
+		    tcm_aheight(ai->area) == h) {
+			x = _m_blk_find_fit(w, align, offs, ai, &before);
+			if (x) {
+				_m_add2area(mi, ai, x - w, x - 1, before);
+				goto done;
+			}
+		}
+	}
+	mutex_unlock(&mtx);
+
+	/* if no area fit, reserve a new one */
+	ai = area_new(ALIGN(w + offs, max(band, align)), h,
+		      max(band, align), tcm, gi);
+	if (ai) {
+		mutex_lock(&mtx);
+		_m_add2area(mi, ai, ai->area.p0.x + offs,
+			     ai->area.p0.x + offs + w - 1,
+			     &ai->blocks);
+	} else {
+		/* clean up */
+		kfree(mi);
+		return NULL;
+	}
+
+done:
+	mutex_unlock(&mtx);
+	return mi;
+}
+
+/* (must have mutex) */
+static void _m_try_free_group(struct gid_info *gi)
+{
+	if (gi && list_empty(&gi->areas) && list_empty(&gi->onedim)) {
+		BUG_ON(!list_empty(&gi->reserved));
+		list_del(&gi->by_pid);
+
+		/* if group is tracking kernel objects, we may free even
+		   the process info */
+		if (gi->pi->kernel && list_empty(&gi->pi->groups)) {
+			list_del(&gi->pi->list);
+			kfree(gi->pi);
+		}
+
+		kfree(gi);
+	}
+}
+
+static void clear_pat(struct tmm *tmm, struct tcm_area *area)
+{
+	struct pat_area p_area = {0};
+	struct tcm_area slice, area_s;
+
+	tcm_for_each_slice(slice, *area, area_s) {
+		p_area.x0 = slice.p0.x;
+		p_area.y0 = slice.p0.y;
+		p_area.x1 = slice.p1.x;
+		p_area.y1 = slice.p1.y;
+
+		tmm_clear(tmm, p_area);
+	}
+}
+
+/* (must have mutex) free block and any freed areas */
+static s32 _m_free(struct mem_info *mi)
+{
+	struct area_info *ai = NULL;
+	struct page *page = NULL;
+	s32 res = 0;
+	u32 i;
+
+	/* release memory */
+	if (mi->pg_ptr) {
+		for (i = 0; i < mi->num_pg; i++) {
+			page = (struct page *)mi->pg_ptr[i];
+			if (page) {
+				if (!PageReserved(page))
+					SetPageDirty(page);
+				page_cache_release(page);
+			}
+		}
+		kfree(mi->pg_ptr);
+	} else if (mi->mem) {
+		tmm_free(TMM_SS(mi->sys_addr), mi->mem);
+	}
+
+	/* safe deletion as list may not have been assigned */
+	if (mi->global.next)
+		list_del(&mi->global);
+	if (mi->by_area.next)
+		list_del(&mi->by_area);
+
+	/* remove block from area first if 2D */
+	if (mi->area.is2d) {
+		ai = mi->parent;
+
+		/* check to see if area needs removing also */
+		if (ai && !--ai->nblocks) {
+			clear_pat(TMM_SS(mi->sys_addr), &ai->area);
+			res = tcm_free(&ai->area);
+			list_del(&ai->by_gid);
+			/* try to remove parent if it became empty */
+			_m_try_free_group(ai->gi);
+			kfree(ai);
+			ai = NULL;
+		}
+	} else {
+		/* remove 1D area */
+		clear_pat(TMM_SS(mi->sys_addr), &mi->area);
+		res = tcm_free(&mi->area);
+		/* try to remove parent if it became empty */
+		_m_try_free_group(mi->parent);
+	}
+
+	kfree(mi);
+	return res;
+}
+
+/* (must have mutex) returns true if block was freed */
+static bool _m_chk_ref(struct mem_info *mi)
+{
+	/* check references */
+	if (mi->refs)
+		return 0;
+
+	if (_m_free(mi))
+		printk(KERN_ERR "error while removing tiler block\n");
+
+	return 1;
+}
+
+/* (must have mutex) */
+static inline s32 _m_dec_ref(struct mem_info *mi)
+{
+	if (mi->refs-- <= 1)
+		return _m_chk_ref(mi);
+
+	return 0;
+}
+
+/* (must have mutex) */
+static inline void _m_inc_ref(struct mem_info *mi)
+{
+	mi->refs++;
+}
+
+/* (must have mutex) returns true if block was freed */
+static inline bool _m_try_free(struct mem_info *mi)
+{
+	if (mi->alloced) {
+		mi->refs--;
+		mi->alloced = false;
+	}
+	return _m_chk_ref(mi);
+}
+
+static s32 register_buf(struct __buf_info *_b, struct process_info *pi)
+{
+	struct mem_info *mi = NULL;
+	struct tiler_buf_info *b = &_b->buf_info;
+	u32 i, num = b->num_blocks, remain = num;
+
+	/* check validity */
+	if (num > TILER_MAX_NUM_BLOCKS)
+		return -EINVAL;
+
+	mutex_lock(&mtx);
+
+	/* find each block */
+	list_for_each_entry(mi, &blocks, global) {
+		for (i = 0; i < num; i++) {
+			if (!_b->mi[i] && mi->sys_addr == b->blocks[i].ssptr) {
+				_b->mi[i] = mi;
+
+				/* quit if found all*/
+				if (!--remain)
+					break;
+
+			}
+		}
+	}
+
+	/* if found all, register buffer */
+	if (!remain) {
+		b->offset = id;
+		id += 0x1000;
+
+		list_add(&_b->by_pid, &pi->bufs);
+
+		/* using each block */
+		for (i = 0; i < num; i++)
+			_m_inc_ref(_b->mi[i]);
+	}
+
+	mutex_unlock(&mtx);
+
+	return remain ? -EACCES : 0;
+}
+
+/* must have mutex */
+static void _m_unregister_buf(struct __buf_info *_b)
+{
+	u32 i;
+
+	/* unregister */
+	list_del(&_b->by_pid);
+
+	/* no longer using the blocks */
+	for (i = 0; i < _b->buf_info.num_blocks; i++)
+		_m_dec_ref(_b->mi[i]);
+
+	kfree(_b);
+}
+
+/**
+ * Free all info kept by a process:
+ *
+ * all registered buffers, allocated blocks, and unreferenced
+ * blocks.  Any blocks/areas still referenced will move to the
+ * orphaned lists to avoid issues if a new process is created
+ * with the same pid.
+ *
+ * (must have mutex)
+ */
+static void _m_free_process_info(struct process_info *pi)
+{
+	struct area_info *ai, *ai_;
+	struct mem_info *mi, *mi_;
+	struct gid_info *gi, *gi_;
+	struct __buf_info *_b = NULL, *_b_ = NULL;
+	bool ai_autofreed, need2free;
+
+	/* unregister all buffers */
+	list_for_each_entry_safe(_b, _b_, &pi->bufs, by_pid)
+		_m_unregister_buf(_b);
+
+	BUG_ON(!list_empty(&pi->bufs));
+
+	/* free all allocated blocks, and remove unreferenced ones */
+	list_for_each_entry_safe(gi, gi_, &pi->groups, by_pid) {
+
+		/*
+		 * Group info structs when they become empty on an _m_try_free.
+		 * However, if the group info is already empty, we need to
+		 * remove it manually
+		 */
+		need2free = list_empty(&gi->areas) && list_empty(&gi->onedim);
+		list_for_each_entry_safe(ai, ai_, &gi->areas, by_gid) {
+			ai_autofreed = true;
+			list_for_each_entry_safe(mi, mi_, &ai->blocks, by_area)
+				ai_autofreed &= _m_try_free(mi);
+
+			/* save orphaned areas for later removal */
+			if (!ai_autofreed) {
+				need2free = true;
+				ai->gi = NULL;
+				list_move(&ai->by_gid, &orphan_areas);
+			}
+		}
+
+		list_for_each_entry_safe(mi, mi_, &gi->onedim, by_area) {
+			if (!_m_try_free(mi)) {
+				need2free = true;
+				/* save orphaned 1D blocks */
+				mi->parent = NULL;
+				list_move(&mi->by_area, &orphan_onedim);
+			}
+		}
+
+		/* if group is still alive reserved list should have been
+		   emptied as there should be no reference on those blocks */
+		if (need2free) {
+			BUG_ON(!list_empty(&gi->onedim));
+			BUG_ON(!list_empty(&gi->areas));
+			_m_try_free_group(gi);
+		}
+	}
+
+	BUG_ON(!list_empty(&pi->groups));
+	list_del(&pi->list);
+	kfree(pi);
+}
+
+static s32 get_area(u32 sys_addr, struct tcm_pt *pt)
+{
+	enum tiler_fmt fmt;
+
+	sys_addr &= TILER_ALIAS_VIEW_CLEAR;
+	fmt = TILER_GET_ACC_MODE(sys_addr);
+
+	switch (fmt) {
+	case TILFMT_8BIT:
+		pt->x = DMM_HOR_X_PAGE_COOR_GET_8(sys_addr);
+		pt->y = DMM_HOR_Y_PAGE_COOR_GET_8(sys_addr);
+		break;
+	case TILFMT_16BIT:
+		pt->x = DMM_HOR_X_PAGE_COOR_GET_16(sys_addr);
+		pt->y = DMM_HOR_Y_PAGE_COOR_GET_16(sys_addr);
+		break;
+	case TILFMT_32BIT:
+		pt->x = DMM_HOR_X_PAGE_COOR_GET_32(sys_addr);
+		pt->y = DMM_HOR_Y_PAGE_COOR_GET_32(sys_addr);
+		break;
+	case TILFMT_PAGE:
+		pt->x = (sys_addr & 0x7FFFFFF) >> 12;
+		pt->y = pt->x / TILER_WIDTH;
+		pt->x &= (TILER_WIDTH - 1);
+		break;
+	default:
+		return -EFAULT;
+	}
+	return 0x0;
+}
+
+static u32 __get_alias_addr(enum tiler_fmt fmt, u16 x, u16 y)
+{
+	u32 acc_mode = -1;
+	u32 x_shft = -1, y_shft = -1;
+
+	switch (fmt) {
+	case TILFMT_8BIT:
+		acc_mode = 0; x_shft = 6; y_shft = 20;
+		break;
+	case TILFMT_16BIT:
+		acc_mode = 1; x_shft = 7; y_shft = 20;
+		break;
+	case TILFMT_32BIT:
+		acc_mode = 2; x_shft = 7; y_shft = 20;
+		break;
+	case TILFMT_PAGE:
+		acc_mode = 3; y_shft = 8;
+		break;
+	default:
+		return 0;
+		break;
+	}
+
+	if (fmt == TILFMT_PAGE)
+		return (u32)TIL_ALIAS_ADDR((x | y << y_shft) << 12, acc_mode);
+	else
+		return (u32)TIL_ALIAS_ADDR(x << x_shft | y << y_shft, acc_mode);
+}
+
+/* must have mutex */
+static struct gid_info *_m_get_gi(struct process_info *pi, u32 gid)
+{
+	struct gid_info *gi;
+
+	/* see if group already exist */
+	list_for_each_entry(gi, &pi->groups, by_pid) {
+		if (gi->gid == gid)
+			return gi;
+	}
+
+	/* create new group */
+	gi = kmalloc(sizeof(*gi), GFP_KERNEL);
+	if (!gi)
+		return gi;
+
+	memset(gi, 0, sizeof(*gi));
+	INIT_LIST_HEAD(&gi->areas);
+	INIT_LIST_HEAD(&gi->onedim);
+	INIT_LIST_HEAD(&gi->reserved);
+	gi->pi = pi;
+	gi->gid = gid;
+	list_add(&gi->by_pid, &pi->groups);
+	return gi;
+}
+
+static struct mem_info *__get_area(enum tiler_fmt fmt, u32 width, u32 height,
+				   u16 align, u16 offs, struct gid_info *gi)
+{
+	u16 x, y, band;
+	struct mem_info *mi = NULL;
+
+	/* calculate dimensions, band, offs and alignment in slots */
+	if (__analize_area(fmt, width, height, &x, &y, &band, &align, &offs))
+		return NULL;
+
+	if (fmt == TILFMT_PAGE)	{
+		/* 1D areas don't pack */
+		mi = kmalloc(sizeof(*mi), GFP_KERNEL);
+		if (!mi)
+			return NULL;
+		memset(mi, 0x0, sizeof(*mi));
+
+		if (tcm_reserve_1d(TCM(fmt), x * y, &mi->area)) {
+			kfree(mi);
+			return NULL;
+		}
+
+		mutex_lock(&mtx);
+		mi->parent = gi;
+		list_add(&mi->by_area, &gi->onedim);
+	} else {
+		mi = get_2d_area(x, y, align, offs, band, gi, TCM(fmt));
+		if (!mi)
+			return NULL;
+
+		mutex_lock(&mtx);
+	}
+
+	list_add(&mi->global, &blocks);
+	mi->alloced = true;
+	mi->refs++;
+	mutex_unlock(&mtx);
+
+	mi->sys_addr = __get_alias_addr(fmt, mi->area.p0.x, mi->area.p0.y);
+	return mi;
+}
+
+static s32 tiler_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct __buf_info *_b = NULL;
+	struct tiler_buf_info *b = NULL;
+	s32 i = 0, j = 0, k = 0, m = 0, p = 0, bpp = 1;
+	struct list_head *pos = NULL;
+	struct process_info *pi = filp->private_data;
+
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+	/* don't allow mremap */
+	vma->vm_flags |= VM_DONTEXPAND | VM_RESERVED;
+
+	mutex_lock(&mtx);
+	list_for_each(pos, &pi->bufs) {
+		_b = list_entry(pos, struct __buf_info, by_pid);
+		if ((vma->vm_pgoff << PAGE_SHIFT) == _b->buf_info.offset)
+			break;
+	}
+	mutex_unlock(&mtx);
+	if (!_b)
+		return -ENXIO;
+
+	b = &_b->buf_info;
+
+	for (i = 0; i < b->num_blocks; i++) {
+		if (b->blocks[i].fmt >= TILFMT_8BIT &&
+					b->blocks[i].fmt <= TILFMT_32BIT) {
+			/* get line width */
+			bpp = (b->blocks[i].fmt == TILFMT_8BIT ? 1 :
+			       b->blocks[i].fmt == TILFMT_16BIT ? 2 : 4);
+			p = PAGE_ALIGN(b->blocks[i].dim.area.width * bpp);
+
+			for (j = 0; j < b->blocks[i].dim.area.height; j++) {
+				/* map each page of the line */
+				vma->vm_pgoff =
+					(b->blocks[i].ssptr + m) >> PAGE_SHIFT;
+				if (remap_pfn_range(vma, vma->vm_start + k,
+					(b->blocks[i].ssptr + m) >> PAGE_SHIFT,
+					p, vma->vm_page_prot))
+					return -EAGAIN;
+				k += p;
+				if (b->blocks[i].fmt == TILFMT_8BIT)
+					m += 64*TILER_WIDTH;
+				else
+					m += 2*64*TILER_WIDTH;
+			}
+			m = 0;
+		} else if (b->blocks[i].fmt == TILFMT_PAGE) {
+			vma->vm_pgoff = (b->blocks[i].ssptr) >> PAGE_SHIFT;
+			p = PAGE_ALIGN(b->blocks[i].dim.len);
+			if (remap_pfn_range(vma, vma->vm_start + k,
+				(b->blocks[i].ssptr) >> PAGE_SHIFT, p,
+				vma->vm_page_prot))
+				return -EAGAIN;;
+			k += p;
+		}
+	}
+	return 0;
+}
+
+static s32 refill_pat(struct tmm *tmm, struct tcm_area *area, u32 *ptr)
+{
+	s32 res = 0;
+	s32 size = tcm_sizeof(*area) * sizeof(*ptr);
+	u32 *page;
+	dma_addr_t page_pa;
+	struct pat_area p_area = {0};
+	struct tcm_area slice, area_s;
+
+	/* must be a 16-byte aligned physical address */
+	page = dma_alloc_coherent(NULL, size, &page_pa, GFP_ATOMIC);
+	if (!page)
+		return -ENOMEM;
+
+	tcm_for_each_slice(slice, *area, area_s) {
+		p_area.x0 = slice.p0.x;
+		p_area.y0 = slice.p0.y;
+		p_area.x1 = slice.p1.x;
+		p_area.y1 = slice.p1.y;
+
+		memcpy(page, ptr, sizeof(*ptr) * tcm_sizeof(slice));
+		ptr += tcm_sizeof(slice);
+
+		if (tmm_map(tmm, p_area, page_pa)) {
+			res = -EFAULT;
+			break;
+		}
+	}
+
+	dma_free_coherent(NULL, size, page, page_pa);
+
+	return res;
+}
+
+static s32 map_block(enum tiler_fmt fmt, u32 width, u32 height, u32 gid,
+			struct process_info *pi, u32 *sys_addr, u32 usr_addr)
+{
+	u32 i = 0, tmp = -1, *mem = NULL;
+	u8 write = 0;
+	s32 res = -ENOMEM;
+	struct mem_info *mi = NULL;
+	struct page *page = NULL;
+	struct task_struct *curr_task = current;
+	struct mm_struct *mm = current->mm;
+	struct vm_area_struct *vma = NULL;
+	struct gid_info *gi = NULL;
+
+	/* we only support mapping a user buffer in page mode */
+	if (fmt != TILFMT_PAGE)
+		return -EPERM;
+
+	/* check if mapping is supported by tmm */
+	if (!tmm_can_map(TMM(fmt)))
+		return -EPERM;
+
+	/* get group context */
+	mutex_lock(&mtx);
+	gi = _m_get_gi(pi, gid);
+	mutex_unlock(&mtx);
+
+	if (!gi)
+		return -ENOMEM;
+
+	/* reserve area in tiler container */
+	mi = __get_area(fmt, width, height, 0, 0, gi);
+	if (!mi) {
+		mutex_lock(&mtx);
+		_m_try_free_group(gi);
+		mutex_unlock(&mtx);
+		return -ENOMEM;
+	}
+
+	*sys_addr = mi->sys_addr;
+	mi->usr = usr_addr;
+
+	/* allocate pages */
+	mi->num_pg = tcm_sizeof(mi->area);
+
+	mem = kmalloc(mi->num_pg * sizeof(*mem), GFP_KERNEL);
+	if (!mem)
+		goto done;
+	memset(mem, 0x0, sizeof(*mem) * mi->num_pg);
+
+	mi->pg_ptr = kmalloc(mi->num_pg * sizeof(*mi->pg_ptr), GFP_KERNEL);
+	if (!mi->pg_ptr)
+		goto done;
+	memset(mi->pg_ptr, 0x0, sizeof(*mi->pg_ptr) * mi->num_pg);
+
+	/*
+	 * Important Note: usr_addr is mapped from user
+	 * application process to current process - it must lie
+	 * completely within the current virtual memory address
+	 * space in order to be of use to us here.
+	 */
+	down_read(&mm->mmap_sem);
+	vma = find_vma(mm, mi->usr);
+	res = -EFAULT;
+
+	/*
+	 * It is observed that under some circumstances, the user
+	 * buffer is spread across several vmas, so loop through
+	 * and check if the entire user buffer is covered.
+	 */
+	while ((vma) && (mi->usr + width > vma->vm_end)) {
+		/* jump to the next VMA region */
+		vma = find_vma(mm, vma->vm_end + 1);
+	}
+	if (!vma) {
+		printk(KERN_ERR "Failed to get the vma region for "
+			"user buffer.\n");
+		goto fault;
+	}
+
+	if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
+		write = 1;
+
+	tmp = mi->usr;
+	for (i = 0; i < mi->num_pg; i++) {
+		if (get_user_pages(curr_task, mm, tmp, 1, write, 1, &page,
+									NULL)) {
+			if (page_count(page) < 1) {
+				printk(KERN_ERR "Bad page count from"
+							"get_user_pages()\n");
+			}
+			mi->pg_ptr[i] = (u32)page;
+			mem[i] = page_to_phys(page);
+			tmp += PAGE_SIZE;
+		} else {
+			printk(KERN_ERR "get_user_pages() failed\n");
+			goto fault;
+		}
+	}
+	up_read(&mm->mmap_sem);
+
+	/* Ensure the data reaches to main memory before PAT refill */
+	wmb();
+
+	if (refill_pat(TMM(fmt), &mi->area, mem))
+		goto fault;
+
+	res = 0;
+	goto done;
+fault:
+	up_read(&mm->mmap_sem);
+done:
+	if (res) {
+		mutex_lock(&mtx);
+		_m_free(mi);
+		mutex_unlock(&mtx);
+	}
+	kfree(mem);
+	return res;
+}
+
+s32 tiler_mapx(enum tiler_fmt fmt, u32 width, u32 height, u32 gid,
+		       pid_t pid, u32 *sys_addr, u32 usr_addr)
+{
+	return map_block(fmt, width, height, gid, __get_pi(pid, true),
+							sys_addr, usr_addr);
+}
+EXPORT_SYMBOL(tiler_mapx);
+
+s32 tiler_map(enum tiler_fmt fmt, u32 width, u32 height, u32 *sys_addr,
+								u32 usr_addr)
+{
+	return tiler_mapx(fmt, width, height, 0, current->tgid, sys_addr,
+								usr_addr);
+}
+EXPORT_SYMBOL(tiler_map);
+
+s32 free_block(u32 sys_addr, struct process_info *pi)
+{
+	struct gid_info *gi = NULL;
+	struct area_info *ai = NULL;
+	struct mem_info *mi = NULL;
+	s32 res = -ENOENT;
+
+	mutex_lock(&mtx);
+
+	/* find block in process list and free it */
+	list_for_each_entry(gi, &pi->groups, by_pid) {
+		/* currently we know if block is 1D or 2D by the address */
+		if (TILER_GET_ACC_MODE(sys_addr) == TILFMT_PAGE) {
+			list_for_each_entry(mi, &gi->onedim, by_area) {
+				if (mi->sys_addr == sys_addr) {
+					_m_try_free(mi);
+					res = 0;
+					goto done;
+				}
+			}
+		} else {
+			list_for_each_entry(ai, &gi->areas, by_gid) {
+				list_for_each_entry(mi, &ai->blocks, by_area) {
+					if (mi->sys_addr == sys_addr) {
+						_m_try_free(mi);
+						res = 0;
+						goto done;
+					}
+				}
+			}
+		}
+	}
+
+done:
+	mutex_unlock(&mtx);
+
+	/* for debugging, we can set the PAT entries to DMM_LISA_MAP__0 */
+	return res;
+}
+
+s32 tiler_free(u32 sys_addr)
+{
+	struct mem_info *mi;
+	s32 res = -ENOENT;
+
+	mutex_lock(&mtx);
+
+	/* find block in global list and free it */
+	list_for_each_entry(mi, &blocks, global) {
+		if (mi->sys_addr == sys_addr) {
+			_m_try_free(mi);
+			res = 0;
+			break;
+		}
+	}
+	mutex_unlock(&mtx);
+
+	/* for debugging, we can set the PAT entries to DMM_LISA_MAP__0 */
+	return res;
+}
+EXPORT_SYMBOL(tiler_free);
+
+/* :TODO: Currently we do not track enough information from alloc to get back
+   the actual width and height of the container, so we must make a guess.  We
+   do not even have enough information to get the virtual stride of the buffer,
+   which is the real reason for this ioctl */
+s32 find_block(u32 sys_addr, struct tiler_block_info *blk)
+{
+	struct mem_info *i;
+	struct tcm_pt pt;
+
+	if (get_area(sys_addr, &pt))
+		return -EFAULT;
+
+	list_for_each_entry(i, &blocks, global) {
+		if (tcm_is_in(pt, i->area))
+			goto found;
+	}
+
+	blk->fmt = TILFMT_INVALID;
+	blk->dim.len = blk->stride = blk->ssptr = 0;
+	return -EFAULT;
+
+found:
+	blk->ptr = NULL;
+	blk->fmt = TILER_GET_ACC_MODE(sys_addr);
+	blk->ssptr = __get_alias_addr(blk->fmt, i->area.p0.x, i->area.p0.y);
+
+	if (blk->fmt == TILFMT_PAGE) {
+		blk->dim.len = tcm_sizeof(i->area) * TILER_PAGE;
+		blk->stride = 0;
+	} else {
+		blk->stride = blk->dim.area.width =
+			tcm_awidth(i->area) * TILER_BLOCK_WIDTH;
+		blk->dim.area.height = tcm_aheight(i->area)
+							* TILER_BLOCK_HEIGHT;
+		if (blk->fmt != TILFMT_8BIT) {
+			blk->stride <<= 1;
+			blk->dim.area.height >>= 1;
+			if (blk->fmt == TILFMT_32BIT)
+				blk->dim.area.width >>= 1;
+		}
+		blk->stride = PAGE_ALIGN(blk->stride);
+	}
+	return 0;
+}
+
+static s32 alloc_block(enum tiler_fmt fmt, u32 width, u32 height,
+			u32 align, u32 offs, u32 gid, struct process_info *pi,
+			u32 *sys_addr);
+
+static s32 tiler_ioctl(struct inode *ip, struct file *filp, u32 cmd,
+			unsigned long arg)
+{
+	pgd_t *pgd = NULL;
+	pmd_t *pmd = NULL;
+	pte_t *ptep = NULL, pte = 0x0;
+	s32 r = -1;
+	u32 til_addr = 0x0;
+	struct process_info *pi = filp->private_data;
+
+	struct __buf_info *_b = NULL;
+	struct tiler_buf_info buf_info = {0};
+	struct tiler_block_info block_info = {0};
+
+	switch (cmd) {
+	case TILIOC_GBUF:
+		if (copy_from_user(&block_info, (void __user *)arg,
+					sizeof(block_info)))
+			return -EFAULT;
+
+		switch (block_info.fmt) {
+		case TILFMT_PAGE:
+			r = alloc_block(block_info.fmt, block_info.dim.len, 1,
+						0, 0, 0, pi, &til_addr);
+			if (r)
+				return r;
+			break;
+		case TILFMT_8BIT:
+		case TILFMT_16BIT:
+		case TILFMT_32BIT:
+			r = alloc_block(block_info.fmt,
+					block_info.dim.area.width,
+					block_info.dim.area.height,
+					0, 0, 0, pi, &til_addr);
+			if (r)
+				return r;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		block_info.ssptr = til_addr;
+		if (copy_to_user((void __user *)arg, &block_info,
+					sizeof(block_info)))
+			return -EFAULT;
+		break;
+	case TILIOC_FBUF:
+	case TILIOC_UMBUF:
+		if (copy_from_user(&block_info, (void __user *)arg,
+					sizeof(block_info)))
+			return -EFAULT;
+
+		/* search current process first, then all processes */
+		free_block(block_info.ssptr, pi) ?
+			tiler_free(block_info.ssptr) : 0;
+
+		/* free always succeeds */
+		break;
+
+	case TILIOC_GSSP:
+		pgd = pgd_offset(current->mm, arg);
+		if (!(pgd_none(*pgd) || pgd_bad(*pgd))) {
+			pmd = pmd_offset(pgd, arg);
+			if (!(pmd_none(*pmd) || pmd_bad(*pmd))) {
+				ptep = pte_offset_map(pmd, arg);
+				if (ptep) {
+					pte = *ptep;
+					if (pte_present(pte))
+						return (pte & PAGE_MASK) |
+							(~PAGE_MASK & arg);
+				}
+			}
+		}
+		/* va not in page table */
+		return 0x0;
+		break;
+	case TILIOC_MBUF:
+		if (copy_from_user(&block_info, (void __user *)arg,
+					sizeof(block_info)))
+			return -EFAULT;
+
+		if (!block_info.ptr)
+			return -EFAULT;
+
+		if (map_block(block_info.fmt, block_info.dim.len, 1, 0, pi,
+				&block_info.ssptr, (u32)block_info.ptr))
+			return -ENOMEM;
+
+		if (copy_to_user((void __user *)arg, &block_info,
+					sizeof(block_info)))
+			return -EFAULT;
+		break;
+	case TILIOC_QBUF:
+		if (copy_from_user(&buf_info, (void __user *)arg,
+					sizeof(buf_info)))
+			return -EFAULT;
+
+		mutex_lock(&mtx);
+		list_for_each_entry(_b, &pi->bufs, by_pid) {
+			if (buf_info.offset == _b->buf_info.offset) {
+				if (copy_to_user((void __user *)arg,
+					&_b->buf_info,
+					sizeof(_b->buf_info))) {
+					mutex_unlock(&mtx);
+					return -EFAULT;
+				} else {
+					mutex_unlock(&mtx);
+					return 0;
+				}
+			}
+		}
+		mutex_unlock(&mtx);
+		return -EFAULT;
+		break;
+	case TILIOC_RBUF:
+		_b = kmalloc(sizeof(*_b), GFP_KERNEL);
+		if (!_b)
+			return -ENOMEM;
+
+		memset(_b, 0x0, sizeof(*_b));
+
+		if (copy_from_user(&_b->buf_info, (void __user *)arg,
+					sizeof(_b->buf_info))) {
+			kfree(_b); return -EFAULT;
+		}
+
+		r = register_buf(_b, pi);
+		if (r) {
+			kfree(_b); return -EACCES;
+		}
+
+		if (copy_to_user((void __user *)arg, &_b->buf_info,
+					sizeof(_b->buf_info))) {
+			_m_unregister_buf(_b);
+			return -EFAULT;
+		}
+		break;
+	case TILIOC_URBUF:
+		if (copy_from_user(&buf_info, (void __user *)arg,
+					sizeof(buf_info)))
+			return -EFAULT;
+
+		mutex_lock(&mtx);
+		/* buffer registration is per process */
+		list_for_each_entry(_b, &pi->bufs, by_pid) {
+			if (buf_info.offset == _b->buf_info.offset) {
+				_m_unregister_buf(_b);
+				mutex_unlock(&mtx);
+				return 0;
+			}
+		}
+		mutex_unlock(&mtx);
+		return -EFAULT;
+		break;
+	case TILIOC_QUERY_BLK:
+		if (copy_from_user(&block_info, (void __user *)arg,
+					sizeof(block_info)))
+			return -EFAULT;
+
+		if (find_block(block_info.ssptr, &block_info))
+			return -EFAULT;
+
+		if (copy_to_user((void __user *)arg, &block_info,
+			sizeof(block_info)))
+			return -EFAULT;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0x0;
+}
+
+s32 alloc_block(enum tiler_fmt fmt, u32 width, u32 height,
+		   u32 align, u32 offs, u32 gid, struct process_info *pi,
+		   u32 *sys_addr)
+{
+	struct mem_info *mi = NULL;
+	struct gid_info *gi = NULL;
+
+	/* only support up to page alignment */
+	if (align > PAGE_SIZE || offs > align || !pi)
+		return -EINVAL;
+
+	/* get group context */
+	mutex_lock(&mtx);
+	gi = _m_get_gi(pi, gid);
+	mutex_unlock(&mtx);
+
+	if (!gi)
+		return -ENOMEM;
+
+	/* reserve area in tiler container */
+	mi = __get_area(fmt, width, height, align, offs, gi);
+	if (!mi) {
+		mutex_lock(&mtx);
+		_m_try_free_group(gi);
+		mutex_unlock(&mtx);
+		return -ENOMEM;
+	}
+
+	*sys_addr = mi->sys_addr;
+
+	/* allocate and map if mapping is supported */
+	if (tmm_can_map(TMM(fmt))) {
+		mi->num_pg = tcm_sizeof(mi->area);
+
+		mi->mem = tmm_get(TMM(fmt), mi->num_pg);
+		if (!mi->mem)
+			goto cleanup;
+
+		/* Ensure the data reaches to main memory before PAT refill */
+		wmb();
+
+		/* program PAT */
+		if (refill_pat(TMM(fmt), &mi->area, mi->mem))
+			goto cleanup;
+	}
+	return 0;
+
+cleanup:
+	mutex_lock(&mtx);
+	_m_free(mi);
+	mutex_unlock(&mtx);
+	return -ENOMEM;
+
+}
+
+s32 tiler_allocx(enum tiler_fmt fmt, u32 width, u32 height,
+		 u32 align, u32 offs, u32 gid, pid_t pid, u32 *sys_addr)
+{
+	return alloc_block(fmt, width, height, align, offs, gid,
+			      __get_pi(pid, true), sys_addr);
+}
+EXPORT_SYMBOL(tiler_allocx);
+
+s32 tiler_alloc(enum tiler_fmt fmt, u32 width, u32 height, u32 *sys_addr)
+{
+	return tiler_allocx(fmt, width, height, 0, 0,
+			    0, current->tgid, sys_addr);
+}
+EXPORT_SYMBOL(tiler_alloc);
+
+
+static void reserve_nv12_blocks(u32 n, u32 width, u32 height,
+				  u32 align, u32 offs, u32 gid, pid_t pid)
+{
+}
+
+static void reserve_blocks(u32 n, enum tiler_fmt fmt, u32 width, u32 height,
+			     u32 align, u32 offs, u32 gid, pid_t pid)
+{
+}
+
+/* reserve area for n identical buffers */
+s32 tiler_reservex(u32 n, struct tiler_buf_info *b, pid_t pid)
+{
+	u32 i;
+
+	if (b->num_blocks > TILER_MAX_NUM_BLOCKS)
+		return -EINVAL;
+
+	for (i = 0; i < b->num_blocks; i++) {
+		/* check for NV12 reservations */
+		if (i + 1 < b->num_blocks &&
+		    b->blocks[i].fmt == TILFMT_8BIT &&
+		    b->blocks[i + 1].fmt == TILFMT_16BIT &&
+		    b->blocks[i].dim.area.height ==
+			b->blocks[i + 1].dim.area.height &&
+		    b->blocks[i].dim.area.width ==
+			b->blocks[i + 1].dim.area.width) {
+			reserve_nv12_blocks(n,
+					      b->blocks[i].dim.area.width,
+					      b->blocks[i].dim.area.height,
+					      0, /* align */
+					      0, /* offs */
+					      0, /* gid */
+					      pid);
+			i++;
+		} else if (b->blocks[i].fmt >= TILFMT_8BIT &&
+			   b->blocks[i].fmt <= TILFMT_32BIT) {
+			/* other 2D reservations */
+			reserve_blocks(n,
+					 b->blocks[i].fmt,
+					 b->blocks[i].dim.area.width,
+					 b->blocks[i].dim.area.height,
+					 0, /* align */
+					 0, /* offs */
+					 0, /* gid */
+					 pid);
+		} else {
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+EXPORT_SYMBOL(tiler_reservex);
+
+s32 tiler_reserve(u32 n, struct tiler_buf_info *b)
+{
+	return tiler_reservex(n, b, current->tgid);
+}
+EXPORT_SYMBOL(tiler_reserve);
+
+static void __exit tiler_exit(void)
+{
+	struct process_info *pi = NULL, *pi_ = NULL;
+	int i, j;
+
+	mutex_lock(&mtx);
+
+	/* free all process data */
+	list_for_each_entry_safe(pi, pi_, &procs, list)
+		_m_free_process_info(pi);
+
+	/* all lists should have cleared */
+	BUG_ON(!list_empty(&blocks));
+	BUG_ON(!list_empty(&procs));
+	BUG_ON(!list_empty(&orphan_onedim));
+	BUG_ON(!list_empty(&orphan_areas));
+
+	mutex_unlock(&mtx);
+
+	dma_free_coherent(NULL, TILER_WIDTH * TILER_HEIGHT * sizeof(*dmac_va),
+							dmac_va, dmac_pa);
+
+	/* close containers only once */
+	for (i = TILFMT_8BIT; i <= TILFMT_MAX; i++) {
+		/* remove identical containers (tmm is unique per tcm) */
+		for (j = i + 1; j <= TILFMT_MAX; j++)
+			if (TCM(i) == TCM(j)) {
+				TCM_SET(j, NULL);
+				TMM_SET(j, NULL);
+			}
+
+		tcm_deinit(TCM(i));
+		tmm_deinit(TMM(i));
+	}
+
+	mutex_destroy(&mtx);
+	platform_driver_unregister(&tiler_driver_ldm);
+	cdev_del(&tiler_device->cdev);
+	kfree(tiler_device);
+	device_destroy(tilerdev_class, MKDEV(tiler_major, tiler_minor));
+	class_destroy(tilerdev_class);
+}
+
+static s32 tiler_open(struct inode *ip, struct file *filp)
+{
+	struct process_info *pi = __get_pi(current->tgid, false);
+
+	if (!pi)
+		return -ENOMEM;
+
+	filp->private_data = pi;
+	return 0x0;
+}
+
+static s32 tiler_release(struct inode *ip, struct file *filp)
+{
+	struct process_info *pi = filp->private_data;
+
+	mutex_lock(&mtx);
+	/* free resources if last device in this process */
+	if (0 == --pi->refs)
+		_m_free_process_info(pi);
+
+	mutex_unlock(&mtx);
+
+	return 0x0;
+}
+
+static const struct file_operations tiler_fops = {
+	.open    = tiler_open,
+	.ioctl   = tiler_ioctl,
+	.release = tiler_release,
+	.mmap    = tiler_mmap,
+};
+
+static s32 __init tiler_init(void)
+{
+	dev_t dev  = 0;
+	s32 r = -1;
+	struct device *device = NULL;
+	struct tcm_pt div_pt;
+	struct tcm *sita = NULL;
+	struct tmm *tmm_pat = NULL;
+
+	/* Allocate tiler container manager (we share 1 on OMAP4) */
+	div_pt.x = TILER_WIDTH;   /* hardcoded default */
+	div_pt.y = (3 * TILER_HEIGHT) / 4;
+	sita = sita_init(TILER_WIDTH, TILER_HEIGHT, (void *)&div_pt);
+
+	TCM_SET(TILFMT_8BIT, sita);
+	TCM_SET(TILFMT_16BIT, sita);
+	TCM_SET(TILFMT_32BIT, sita);
+	TCM_SET(TILFMT_PAGE, sita);
+
+	/* Allocate tiler memory manager (must have 1 unique TMM per TCM ) */
+	tmm_pat = tmm_pat_init(0);
+	TMM_SET(TILFMT_8BIT, tmm_pat);
+	TMM_SET(TILFMT_16BIT, tmm_pat);
+	TMM_SET(TILFMT_32BIT, tmm_pat);
+	TMM_SET(TILFMT_PAGE, tmm_pat);
+
+	/**
+	  * Array of physical pages for PAT programming, which must be a 16-byte
+	  * aligned physical address
+	*/
+	dmac_va = dma_alloc_coherent(NULL, TILER_WIDTH * TILER_HEIGHT *
+					sizeof(*dmac_va), &dmac_pa, GFP_ATOMIC);
+	if (!dmac_va)
+		return -ENOMEM;
+
+	tiler_device = kmalloc(sizeof(*tiler_device), GFP_KERNEL);
+	if (!tiler_device || !sita || !tmm_pat) {
+		r = -ENOMEM;
+		goto error;
+	}
+
+	memset(tiler_device, 0x0, sizeof(*tiler_device));
+	if (tiler_major) {
+		dev = MKDEV(tiler_major, tiler_minor);
+		r = register_chrdev_region(dev, 1, "tiler");
+	} else {
+		r = alloc_chrdev_region(&dev, tiler_minor, 1, "tiler");
+		tiler_major = MAJOR(dev);
+	}
+
+	cdev_init(&tiler_device->cdev, &tiler_fops);
+	tiler_device->cdev.owner = THIS_MODULE;
+	tiler_device->cdev.ops   = &tiler_fops;
+
+	r = cdev_add(&tiler_device->cdev, dev, 1);
+	if (r)
+		printk(KERN_ERR "cdev_add():failed\n");
+
+	tilerdev_class = class_create(THIS_MODULE, "tiler");
+
+	if (IS_ERR(tilerdev_class)) {
+		printk(KERN_ERR "class_create():failed\n");
+		goto error;
+	}
+
+	device = device_create(tilerdev_class, NULL, dev, NULL, "tiler");
+	if (device == NULL)
+		printk(KERN_ERR "device_create() fail\n");
+
+	r = platform_driver_register(&tiler_driver_ldm);
+
+	mutex_init(&mtx);
+	INIT_LIST_HEAD(&blocks);
+	INIT_LIST_HEAD(&procs);
+	INIT_LIST_HEAD(&orphan_areas);
+	INIT_LIST_HEAD(&orphan_onedim);
+	id = 0xda7a000;
+
+error:
+	/* TODO: error handling for device registration */
+	if (r) {
+		kfree(tiler_device);
+		tcm_deinit(sita);
+		tmm_deinit(tmm_pat);
+	}
+
+	return r;
+}
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("David Sin <davidsin@ti.com>");
+MODULE_AUTHOR("Lajos Molnar <molnar@ti.com>");
+module_init(tiler_init);
+module_exit(tiler_exit);
diff --git a/drivers/media/video/tiler/tiler_def.h b/drivers/media/video/tiler/tiler_def.h
new file mode 100644
index 000000000000..d92bfde8e452
--- /dev/null
+++ b/drivers/media/video/tiler/tiler_def.h
@@ -0,0 +1,158 @@
+/*
+ * tiler_def.h
+ *
+ * TILER driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef TILER_DEF_H
+#define TILER_DEF_H
+
+#define ROUND_UP_2P(a, b) (((a) + (b) - 1) & ~((b) - 1))
+#define DIVIDE_UP(a, b) (((a) + (b) - 1) / (b))
+#define ROUND_UP(a, b) (DIVIDE_UP(a, b) * (b))
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+
+#define TILER_ACC_MODE_SHIFT  (27)
+#define TILER_ACC_MODE_MASK   (3)
+#define TILER_GET_ACC_MODE(x) ((enum tiler_fmt) (1 + \
+(((u32)x & (TILER_ACC_MODE_MASK<<TILER_ACC_MODE_SHIFT))>>TILER_ACC_MODE_SHIFT)))
+
+#define TILER_ALIAS_BASE    (0x60000000)
+#define TILER_ACC_MODE_SHIFT  (27)
+#define DMM_ACC_MODE_SHIFT  (27)
+
+#define TIL_ALIAS_ADDR(x, access_mode)\
+((void *)(TILER_ALIAS_BASE | (u32)x | (access_mode << TILER_ACC_MODE_SHIFT)))
+
+#define TIL_ADDR(x, r, yi, xi, a)\
+((void *)((u32)x | (r << DMM_ROTATION_SHIFT) |\
+(yi << DMM_Y_INVERT_SHIFT) | (xi << DMM_X_INVERT_SHIFT) |\
+(a << DMM_ACC_MODE_SHIFT)))
+
+#define TILER_ALIAS_VIEW_CLEAR    (~0xE0000000)
+
+#define DMM_X_INVERT_SHIFT        (29)
+#define DMM_GET_X_INVERTED(x) ((((u32)x & (1<<DMM_X_INVERT_SHIFT)) > 0) ? 1 : 0)
+#define DMM_Y_INVERT_SHIFT        (30)
+#define DMM_GET_Y_INVERTED(x) ((((u32)x & (1<<DMM_Y_INVERT_SHIFT)) > 0) ? 1 : 0)
+
+#define DMM_ROTATION_SHIFT        (31)
+#define DMM_GET_ROTATED(x)\
+((((u32)x & ((u32)1<<DMM_ROTATION_SHIFT)) > 0) ? 1 : 0)
+
+#define DMM_ALIAS_VIEW_CLEAR    (~0xE0000000)
+
+#define DMM_TILE_DIMM_X_MODE_8    (32)
+#define DMM_TILE_DIMM_Y_MODE_8    (32)
+
+#define DMM_TILE_DIMM_X_MODE_16    (32)
+#define DMM_TILE_DIMM_Y_MODE_16    (16)
+
+#define DMM_TILE_DIMM_X_MODE_32    (16)
+#define DMM_TILE_DIMM_Y_MODE_32    (16)
+
+#define DMM_PAGE_DIMM_X_MODE_8    (DMM_TILE_DIMM_X_MODE_8*2)
+#define DMM_PAGE_DIMM_Y_MODE_8    (DMM_TILE_DIMM_Y_MODE_8*2)
+
+#define DMM_PAGE_DIMM_X_MODE_16    (DMM_TILE_DIMM_X_MODE_16*2)
+#define DMM_PAGE_DIMM_Y_MODE_16    (DMM_TILE_DIMM_Y_MODE_16*2)
+
+#define DMM_PAGE_DIMM_X_MODE_32    (DMM_TILE_DIMM_X_MODE_32*2)
+#define DMM_PAGE_DIMM_Y_MODE_32    (DMM_TILE_DIMM_Y_MODE_32*2)
+
+#define DMM_HOR_X_ADDRSHIFT_8            (0)
+#define DMM_HOR_X_ADDRMASK_8            (0x3FFF)
+#define DMM_HOR_X_COOR_GET_8(x)\
+	(((unsigned long)x >> DMM_HOR_X_ADDRSHIFT_8) & DMM_HOR_X_ADDRMASK_8)
+#define DMM_HOR_X_PAGE_COOR_GET_8(x)\
+				(DMM_HOR_X_COOR_GET_8(x)/DMM_PAGE_DIMM_X_MODE_8)
+
+#define DMM_HOR_Y_ADDRSHIFT_8            (14)
+#define DMM_HOR_Y_ADDRMASK_8            (0x1FFF)
+#define DMM_HOR_Y_COOR_GET_8(x)\
+	(((unsigned long)x >> DMM_HOR_Y_ADDRSHIFT_8) & DMM_HOR_Y_ADDRMASK_8)
+#define DMM_HOR_Y_PAGE_COOR_GET_8(x)\
+				(DMM_HOR_Y_COOR_GET_8(x)/DMM_PAGE_DIMM_Y_MODE_8)
+
+#define DMM_HOR_X_ADDRSHIFT_16            (1)
+#define DMM_HOR_X_ADDRMASK_16            (0x7FFE)
+#define DMM_HOR_X_COOR_GET_16(x)        (((unsigned long)x >> \
+				DMM_HOR_X_ADDRSHIFT_16) & DMM_HOR_X_ADDRMASK_16)
+#define DMM_HOR_X_PAGE_COOR_GET_16(x)    (DMM_HOR_X_COOR_GET_16(x) /           \
+				DMM_PAGE_DIMM_X_MODE_16)
+
+#define DMM_HOR_Y_ADDRSHIFT_16            (15)
+#define DMM_HOR_Y_ADDRMASK_16            (0xFFF)
+#define DMM_HOR_Y_COOR_GET_16(x)        (((unsigned long)x >>                  \
+				DMM_HOR_Y_ADDRSHIFT_16) & DMM_HOR_Y_ADDRMASK_16)
+#define DMM_HOR_Y_PAGE_COOR_GET_16(x)    (DMM_HOR_Y_COOR_GET_16(x) /           \
+				DMM_PAGE_DIMM_Y_MODE_16)
+
+#define DMM_HOR_X_ADDRSHIFT_32            (2)
+#define DMM_HOR_X_ADDRMASK_32            (0x7FFC)
+#define DMM_HOR_X_COOR_GET_32(x)        (((unsigned long)x >>                  \
+				DMM_HOR_X_ADDRSHIFT_32) & DMM_HOR_X_ADDRMASK_32)
+#define DMM_HOR_X_PAGE_COOR_GET_32(x)    (DMM_HOR_X_COOR_GET_32(x) /           \
+				DMM_PAGE_DIMM_X_MODE_32)
+
+#define DMM_HOR_Y_ADDRSHIFT_32            (15)
+#define DMM_HOR_Y_ADDRMASK_32            (0xFFF)
+#define DMM_HOR_Y_COOR_GET_32(x)        (((unsigned long)x >>                  \
+				DMM_HOR_Y_ADDRSHIFT_32) & DMM_HOR_Y_ADDRMASK_32)
+#define DMM_HOR_Y_PAGE_COOR_GET_32(x)    (DMM_HOR_Y_COOR_GET_32(x) /           \
+				DMM_PAGE_DIMM_Y_MODE_32)
+
+#define DMM_VER_X_ADDRSHIFT_8            (14)
+#define DMM_VER_X_ADDRMASK_8            (0x1FFF)
+#define DMM_VER_X_COOR_GET_8(x)\
+	(((unsigned long)x >> DMM_VER_X_ADDRSHIFT_8) & DMM_VER_X_ADDRMASK_8)
+#define DMM_VER_X_PAGE_COOR_GET_8(x)\
+				(DMM_VER_X_COOR_GET_8(x)/DMM_PAGE_DIMM_X_MODE_8)
+
+#define DMM_VER_Y_ADDRSHIFT_8            (0)
+#define DMM_VER_Y_ADDRMASK_8            (0x3FFF)
+#define DMM_VER_Y_COOR_GET_8(x)\
+	(((unsigned long)x >> DMM_VER_Y_ADDRSHIFT_8) & DMM_VER_Y_ADDRMASK_8)
+#define DMM_VER_Y_PAGE_COOR_GET_8(x)\
+				(DMM_VER_Y_COOR_GET_8(x)/DMM_PAGE_DIMM_Y_MODE_8)
+
+#define DMM_VER_X_ADDRSHIFT_16            (14)
+#define DMM_VER_X_ADDRMASK_16            (0x1FFF)
+#define DMM_VER_X_COOR_GET_16(x)        (((unsigned long)x >>                  \
+				DMM_VER_X_ADDRSHIFT_16) & DMM_VER_X_ADDRMASK_16)
+#define DMM_VER_X_PAGE_COOR_GET_16(x)    (DMM_VER_X_COOR_GET_16(x) /           \
+				DMM_PAGE_DIMM_X_MODE_16)
+
+#define DMM_VER_Y_ADDRSHIFT_16            (0)
+#define DMM_VER_Y_ADDRMASK_16            (0x3FFF)
+#define DMM_VER_Y_COOR_GET_16(x)        (((unsigned long)x >>                  \
+				DMM_VER_Y_ADDRSHIFT_16) & DMM_VER_Y_ADDRMASK_16)
+#define DMM_VER_Y_PAGE_COOR_GET_16(x)    (DMM_VER_Y_COOR_GET_16(x) /           \
+				DMM_PAGE_DIMM_Y_MODE_16)
+
+#define DMM_VER_X_ADDRSHIFT_32            (15)
+#define DMM_VER_X_ADDRMASK_32            (0xFFF)
+#define DMM_VER_X_COOR_GET_32(x)        (((unsigned long)x >>                  \
+				DMM_VER_X_ADDRSHIFT_32) & DMM_VER_X_ADDRMASK_32)
+#define DMM_VER_X_PAGE_COOR_GET_32(x)    (DMM_VER_X_COOR_GET_32(x) /           \
+				DMM_PAGE_DIMM_X_MODE_32)
+
+#define DMM_VER_Y_ADDRSHIFT_32            (0)
+#define DMM_VER_Y_ADDRMASK_32            (0x7FFF)
+#define DMM_VER_Y_COOR_GET_32(x)        (((unsigned long)x >>                  \
+				DMM_VER_Y_ADDRSHIFT_32) & DMM_VER_Y_ADDRMASK_32)
+#define DMM_VER_Y_PAGE_COOR_GET_32(x)    (DMM_VER_Y_COOR_GET_32(x) /           \
+				DMM_PAGE_DIMM_Y_MODE_32)
+
+#endif
diff --git a/drivers/media/video/tiler/tiler_pack.c b/drivers/media/video/tiler/tiler_pack.c
new file mode 100644
index 000000000000..e21846909bc3
--- /dev/null
+++ b/drivers/media/video/tiler/tiler_pack.c
@@ -0,0 +1,269 @@
+/*
+ * tiler_pack.c
+ *
+ * TILER driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <mach/tiler.h>
+#include "tiler_def.h"
+
+void tiler_alloc_packed(s32 *count, enum tiler_fmt fmt, u32 width, u32 height,
+			void **sysptr, void **allocptr, s32 aligned)
+{
+	int til_width, bpp, bpt, buf_width, alloc_width, map_width;
+	int buf_map_width, n_per_m, m_per_a, i = 0, m, n;
+
+	/* Check input parameters for correctness */
+	if (!width || !height || !sysptr || !allocptr || !count ||
+	    *count <= 0 || fmt < TILFMT_8BIT || fmt > TILFMT_32BIT) {
+		if (count)
+			*count = 0;
+		return;
+	}
+
+	/* tiler page width in pixels, bytes per pixel, tiler page in bytes */
+	til_width = fmt == TILFMT_32BIT ? 32 : 64;
+	bpp = 1 << (fmt - TILFMT_8BIT);
+	bpt = til_width * bpp;
+
+	/* width of buffer in tiled pages */
+	buf_width = DIVIDE_UP(width, til_width);
+
+	/* :TODO: for now tiler allocation width is 64-multiple */
+	alloc_width = ROUND_UP_2P(buf_width, 64);
+	map_width = TILER_PAGE / bpt;
+
+	/* ensure alignment if needed */
+	buf_map_width = ROUND_UP_2P(buf_width, map_width);
+
+	/* number of buffers in a map window */
+	n_per_m = aligned ? 1 : (buf_map_width / buf_width);
+
+	/* number of map windows per allocation */
+	m_per_a = alloc_width / buf_map_width;
+
+	printk(KERN_INFO "packing %d*%d buffers into an allocation\n",
+	       n_per_m, m_per_a);
+
+	while (i < *count) {
+		/* allocate required width of a frame to fit remaining
+		   frames */
+		int n_alloc, m_alloc, tiles, res;
+		void *base;
+
+		n_alloc = MIN(*count - i, m_per_a * n_per_m);
+		m_alloc = DIVIDE_UP(n_alloc, n_per_m);
+		tiles = ((m_alloc - 1) * map_width +
+			 buf_width * (n_alloc - (m_alloc - 1) * n_per_m));
+
+		res = tiler_alloc(fmt, til_width * tiles, height,
+				      (u32 *)sysptr + i);
+		if (res != 0)
+			break;
+
+		/* mark allocation */
+		base = allocptr[i] = sysptr[i];
+		i++;
+
+		/* portion out remaining buffers */
+		for (m = 0; m < m_per_a; m++, base += bpt * buf_map_width) {
+			for (n = 0; n < n_per_m; n++) {
+				/* first buffer is already allocated */
+				if (n + m == 0)
+					continue;
+
+				/* stop if we are done */
+				if (i == *count)
+					break;
+
+				/* set buffer address */
+				sysptr[i] = base + bpt * n * buf_width;
+				allocptr[i++] = NULL;
+			}
+		}
+	}
+
+	/* mark how many buffers we allocated */
+	*count = i;
+}
+EXPORT_SYMBOL(tiler_alloc_packed);
+
+static int layout_packed_nv12(char *offsets, int y_width, int uv_width,
+			      void **buf, int blocks, int i,
+			      void **y_sysptr, void **uv_sysptr,
+			      void **y_allocptr, void **uv_allocptr)
+{
+	int j;
+	for (j = 0; j < blocks; j++, offsets += 3) {
+		int page_offset = (63 & (int) offsets[0])
+			+ y_width * ((int) offsets[1])
+			+ uv_width * (int) offsets[2];
+		void *base = buf[offsets[0] >> 6] + 64 * page_offset;
+
+		if (j & 1) {
+			/* convert 8-bit to 16-bit view */
+			/* this formula only works for even ys */
+			uv_sysptr[i] = base + (0x3FFF & (unsigned long) base)
+				+ 0x8000000;
+			uv_allocptr[i] = page_offset ? NULL : uv_sysptr[i];
+			i++;
+		} else {
+			y_sysptr[i] = base;
+			y_allocptr[i] = page_offset ? NULL : y_sysptr[i];
+		}
+	}
+	return i;
+}
+
+void tiler_alloc_packed_nv12(s32 *count, u32 width, u32 height, void **y_sysptr,
+				void **uv_sysptr, void **y_allocptr,
+				void **uv_allocptr, s32 aligned)
+{
+	/* optimized packing table */
+	/* we read this table from beginning to end, and determine whether
+	   the optimization meets our requirement (e.g. allocating at least
+	   i buffers, with max w y-width, and alignment a. If not, we get
+	   to the next element.  Otherwise we do the allocation.  The table
+	   is constructed in such a way that if an interim tiler allocation
+	   fails, the next matching rule for the scenario will be able to
+	   use the buffers already allocated. */
+
+#define MAX_BUFS_TO_PACK 3
+	void *buf[MAX_BUFS_TO_PACK];
+	int   n_buf, buf_w[MAX_BUFS_TO_PACK];
+
+	char packing[] = {
+		/* min(i), max(w), aligned, buffers to alloc */
+		5, 16, 0, 2,
+			/* buffer widths in a + b * w(y) + c * w(uv) */
+			64, 0, 0,  64, 0, 0,
+				/* tiler-page offsets in
+				   a + b * w(y) + c * w(uv) */
+				0,   0, 0,  32,  0, 0,
+				16,  0, 0,  40,  0, 0,
+				64,  0, 0,  96,  0, 0,
+				80,  0, 0,  104, 0, 0,
+				112, 0, 0,  56,  0, 0,
+
+		2, 16, 0, 1,
+			32, 0, 2,
+				0,   0, 0,  32,  0, 0,
+				0,   0, 2,  32,  0, 1,
+
+		2, 20, 0, 1,
+			42, 1, 0,
+				0,   0, 0,  32,  0, 0,
+				42,  0, 0,  21,  0, 0,
+
+		3, 24, 0, 2,
+			48, 0, 1,  32, 1, 0,
+				0,   0, 0,  64,  0, 0,
+				24,  0, 0,  76,  0, 0,
+				96,  0, 0,  48,  0, 0,
+
+		4, 32, 0, 3,
+			48, 0, 1,  32, 1, 0,  32, 1, 0,
+				0,   0, 0,  32,  0, 0,
+				96,  0, 0,  48,  0, 0,
+				64,  0, 0,  128, 0, 0,
+				160, 0, 0,  144, 0, 0,
+
+		/* this is needed for soft landing if prior allocation fails
+		   after two buffers */
+		2, 32, 1, 2,
+			32, 0, 1,  32, 0, 1,
+				0,  0, 0,  32, 0, 0,
+				64, 0, 0,  96, 0, 0,
+
+		1, 32, 1, 1,
+			32, 0, 1,
+				0, 0, 0,  32, 0, 0,
+
+		2, 64, 1, 3,
+			0, 1, 0,  32, 0, 1,  0, 1, 0,
+				0,   0, 0,  64, 0, 0,
+				128, 0, 0,  96, 0, 0,
+		/* this is the basic NV12 allocation using 2 buffers */
+		1, 0, 1, 2,
+			0, 1, 0,  0, 0, 1,
+				0, 0, 0,  64, 0, 0,
+		0 };
+	int y_width, uv_width, i = 0;
+
+	/* Check input parameters for correctness */
+	if (!width || !height || !y_sysptr || !y_allocptr || !count ||
+	    !uv_sysptr || !uv_allocptr || *count <= 0) {
+		if (count)
+			*count = 0;
+		return;
+	}
+
+	y_width = DIVIDE_UP(width, 64);
+	uv_width = DIVIDE_UP(width >> 1, 64);
+
+	while (i < *count) {
+		int n_alloc = *count - i;
+		char *p = packing;
+		n_buf = 0;
+
+		/* skip packings that do not apply */
+		while (*p) {
+			/* see if this packing applies */
+			if (p[0] <= n_alloc &&
+			    (!p[1] || p[1] >= y_width) &&
+			    (!aligned || p[2])) {
+
+				/* allocate buffers */
+				while (n_buf < p[3]) {
+					buf_w[n_buf] = p[4 + 3 * n_buf] +
+						y_width * p[5 + 3 * n_buf] +
+						uv_width * p[6 + 3 * n_buf];
+
+					if (0 != tiler_alloc(
+						TILFMT_8BIT, buf_w[n_buf] * 64,
+						height, (u32 *)buf + n_buf))
+						break;
+					n_buf++;
+				}
+
+				/* if successfully allocated buffers */
+				if (n_buf >= p[3]) {
+					i = layout_packed_nv12(p + 4 + 3 * p[3],
+							       y_width,
+							       uv_width,
+							       buf, 2 * p[0], i,
+							       y_sysptr,
+							       uv_sysptr,
+							       y_allocptr,
+							       uv_allocptr);
+					break;
+				}
+			}
+
+			p += 4 + 3 * p[3] + 6 * p[0];
+		}
+
+		/* if allocation failed free any outstanding buffers and stop */
+		if (!*p) {
+			while (n_buf > 0)
+				tiler_free((unsigned long)(buf[--n_buf]));
+			break;
+		}
+	}
+
+	/* mark how many buffers we allocated */
+	*count = i;
+}
+EXPORT_SYMBOL(tiler_alloc_packed_nv12);
diff --git a/drivers/media/video/tiler/tiler_rot.c b/drivers/media/video/tiler/tiler_rot.c
new file mode 100644
index 000000000000..aa38d72187db
--- /dev/null
+++ b/drivers/media/video/tiler/tiler_rot.c
@@ -0,0 +1,239 @@
+/*
+ * tiler_rot.c
+ *
+ * TILER driver support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <mach/tiler.h>
+#include "tiler_def.h"
+
+#define DMM_SHIFT_PER_X_8 0
+#define DMM_SHIFT_PER_Y_8 0
+#define DMM_SHIFT_PER_X_16 0
+#define DMM_SHIFT_PER_Y_16 1
+#define DMM_SHIFT_PER_X_32 1
+#define DMM_SHIFT_PER_Y_32 1
+#define DMM_SHIFT_PER_X_PAGE 6
+#define DMM_SHIFT_PER_Y_PAGE 6
+
+#define DMM_TILER_THE(NAME) (1 << DMM_TILER_##NAME##_BITS)
+#define DMM_TILER_THE_(N, NAME) (1 << DMM_TILER_##NAME##_BITS_(N))
+
+#define DMM_TILER_CONT_WIDTH_BITS  14
+#define DMM_TILER_CONT_HEIGHT_BITS 13
+
+#define DMM_SHIFT_PER_P_(N) (DMM_SHIFT_PER_X_##N + DMM_SHIFT_PER_Y_##N)
+
+#define DMM_TILER_CONT_HEIGHT_BITS_(N) \
+	(DMM_TILER_CONT_HEIGHT_BITS - DMM_SHIFT_PER_Y_##N)
+#define DMM_TILER_CONT_WIDTH_BITS_(N) \
+	(DMM_TILER_CONT_WIDTH_BITS - DMM_SHIFT_PER_X_##N)
+
+#define DMM_TILER_MASK(bits) ((1 << (bits)) - 1)
+
+#define DMM_TILER_GET_OFFSET_(N, var) \
+	((((u32) var) & DMM_TILER_MASK(DMM_TILER_CONT_WIDTH_BITS + \
+	DMM_TILER_CONT_HEIGHT_BITS)) >> DMM_SHIFT_PER_P_(N))
+
+#define DMM_TILER_GET_0_X_(N, var) \
+	(DMM_TILER_GET_OFFSET_(N, var) & \
+	DMM_TILER_MASK(DMM_TILER_CONT_WIDTH_BITS_(N)))
+#define DMM_TILER_GET_0_Y_(N, var) \
+	(DMM_TILER_GET_OFFSET_(N, var) >> DMM_TILER_CONT_WIDTH_BITS_(N))
+#define DMM_TILER_GET_90_X_(N, var) \
+	(DMM_TILER_GET_OFFSET_(N, var) & \
+	DMM_TILER_MASK(DMM_TILER_CONT_HEIGHT_BITS_(N)))
+#define DMM_TILER_GET_90_Y_(N, var) \
+	(DMM_TILER_GET_OFFSET_(N, var) >> DMM_TILER_CONT_HEIGHT_BITS_(N))
+
+#define DMM_TILER_STRIDE_0_(N) \
+	(DMM_TILER_THE(CONT_WIDTH) << DMM_SHIFT_PER_Y_##N)
+#define DMM_TILER_STRIDE_90_(N) \
+	(DMM_TILER_THE(CONT_HEIGHT) << DMM_SHIFT_PER_X_##N)
+
+void tiler_get_natural_xy(u32 tsptr, u32 *x, u32 *y)
+{
+	u32 x_bits, y_bits, offset;
+	enum tiler_fmt fmt;
+
+	fmt = TILER_GET_ACC_MODE(tsptr);
+
+	switch (fmt) {
+	case TILFMT_8BIT:
+		x_bits = DMM_TILER_CONT_WIDTH_BITS_(8);
+		y_bits = DMM_TILER_CONT_HEIGHT_BITS_(8);
+		offset = DMM_TILER_GET_OFFSET_(8, tsptr);
+		break;
+	case TILFMT_16BIT:
+		x_bits = DMM_TILER_CONT_WIDTH_BITS_(16);
+		y_bits = DMM_TILER_CONT_HEIGHT_BITS_(16);
+		offset = DMM_TILER_GET_OFFSET_(16, tsptr);
+		break;
+	case TILFMT_32BIT:
+		x_bits = DMM_TILER_CONT_WIDTH_BITS_(32);
+		y_bits = DMM_TILER_CONT_HEIGHT_BITS_(32);
+		offset = DMM_TILER_GET_OFFSET_(32, tsptr);
+		break;
+	case TILFMT_PAGE:
+	default:
+		x_bits = DMM_TILER_CONT_WIDTH_BITS_(PAGE);
+		y_bits = DMM_TILER_CONT_HEIGHT_BITS_(PAGE);
+		offset = DMM_TILER_GET_OFFSET_(PAGE, tsptr);
+		break;
+	}
+
+	if (DMM_GET_ROTATED(tsptr)) {
+		*x = offset >> y_bits;
+		*y = offset & DMM_TILER_MASK(y_bits);
+	} else {
+		*x = offset & DMM_TILER_MASK(x_bits);
+		*y = offset >> x_bits;
+	}
+
+	if (DMM_GET_X_INVERTED(tsptr))
+		*x ^= DMM_TILER_MASK(x_bits);
+	if (DMM_GET_Y_INVERTED(tsptr))
+		*y ^= DMM_TILER_MASK(y_bits);
+}
+
+u32 tiler_get_address(struct tiler_view_orient orient,
+			enum tiler_fmt fmt, u32 x, u32 y)
+{
+	u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
+
+	switch (fmt) {
+	case TILFMT_8BIT:
+		x_bits = DMM_TILER_CONT_WIDTH_BITS_(8);
+		y_bits = DMM_TILER_CONT_HEIGHT_BITS_(8);
+		alignment = DMM_SHIFT_PER_P_(8);
+		break;
+	case TILFMT_16BIT:
+		x_bits = DMM_TILER_CONT_WIDTH_BITS_(16);
+		y_bits = DMM_TILER_CONT_HEIGHT_BITS_(16);
+		alignment = DMM_SHIFT_PER_P_(16);
+		break;
+	case TILFMT_32BIT:
+		x_bits = DMM_TILER_CONT_WIDTH_BITS_(32);
+		y_bits = DMM_TILER_CONT_HEIGHT_BITS_(32);
+		alignment = DMM_SHIFT_PER_P_(32);
+		break;
+	case TILFMT_PAGE:
+	default:
+		x_bits = DMM_TILER_CONT_WIDTH_BITS_(PAGE);
+		y_bits = DMM_TILER_CONT_HEIGHT_BITS_(PAGE);
+		alignment = DMM_SHIFT_PER_P_(PAGE);
+		break;
+	}
+
+	x_mask = DMM_TILER_MASK(x_bits);
+	y_mask = DMM_TILER_MASK(y_bits);
+	if (x < 0 || x > x_mask || y < 0 || y > y_mask)
+		return 0;
+
+	if (orient.x_invert)
+		x ^= x_mask;
+	if (orient.y_invert)
+		y ^= y_mask;
+
+	if (orient.rotate_90)
+		tmp = ((x << y_bits) + y);
+	else
+		tmp = ((y << x_bits) + x);
+
+	return (u32)
+		TIL_ADDR((tmp << alignment), (orient.rotate_90 ? 1 : 0),
+			(orient.y_invert ? 1 : 0), (orient.x_invert ? 1 : 0),
+			(fmt - 1));
+}
+
+u32 tiler_reorient_addr(u32 tsptr, struct tiler_view_orient orient)
+{
+	u32 x, y;
+
+	tiler_get_natural_xy(tsptr, &x, &y);
+	return tiler_get_address(orient, TILER_GET_ACC_MODE(tsptr), x, y);
+}
+EXPORT_SYMBOL(tiler_reorient_addr);
+
+u32 tiler_get_natural_addr(void *sys_ptr)
+{
+	return (u32)sys_ptr & DMM_ALIAS_VIEW_CLEAR;
+}
+EXPORT_SYMBOL(tiler_get_natural_addr);
+
+u32 tiler_reorient_topleft(u32 tsptr, struct tiler_view_orient orient,
+				u32 width, u32 height)
+{
+	enum tiler_fmt fmt;
+	u32 x, y;
+
+	fmt = TILER_GET_ACC_MODE(tsptr);
+
+	tiler_get_natural_xy(tsptr, &x, &y);
+
+	if (DMM_GET_X_INVERTED(tsptr))
+		x -= width - 1;
+	if (DMM_GET_Y_INVERTED(tsptr))
+		y -= height - 1;
+
+	if (orient.x_invert)
+		x += width - 1;
+	if (orient.y_invert)
+		y += height - 1;
+
+	return tiler_get_address(orient, fmt, x, y);
+}
+EXPORT_SYMBOL(tiler_reorient_topleft);
+
+u32 tiler_stride(u32 tsptr)
+{
+	enum tiler_fmt fmt;
+
+	fmt = TILER_GET_ACC_MODE(tsptr);
+
+	switch (fmt) {
+	case TILFMT_8BIT:
+		return DMM_GET_ROTATED(tsptr) ?
+			DMM_TILER_STRIDE_90_(8) : DMM_TILER_STRIDE_0_(8);
+	case TILFMT_16BIT:
+		return DMM_GET_ROTATED(tsptr) ?
+			DMM_TILER_STRIDE_90_(16) : DMM_TILER_STRIDE_0_(16);
+	case TILFMT_32BIT:
+		return DMM_GET_ROTATED(tsptr) ?
+			DMM_TILER_STRIDE_90_(32) : DMM_TILER_STRIDE_0_(32);
+	default:
+		return 0;
+	}
+}
+EXPORT_SYMBOL(tiler_stride);
+
+void tiler_rotate_view(struct tiler_view_orient *orient, u32 rotation)
+{
+	rotation = (rotation / 90) & 3;
+
+	if (rotation & 2) {
+		orient->x_invert = !orient->x_invert;
+		orient->y_invert = !orient->y_invert;
+	}
+
+	if (rotation & 1) {
+		if (orient->rotate_90)
+			orient->y_invert = !orient->y_invert;
+		else
+			orient->x_invert = !orient->x_invert;
+		orient->rotate_90 = !orient->rotate_90;
+	}
+}
+EXPORT_SYMBOL(tiler_rotate_view);
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index d30724c35775..19355ed5601a 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -119,7 +119,7 @@
 #endif
 
 #if defined(CONFIG_TWL4030_CODEC) || defined(CONFIG_TWL4030_CODEC_MODULE) ||\
-	defined(CONFIG_SND_SOC_TWL6030) || defined(CONFIG_SND_SOC_TWL6030_MODULE)
+	defined(CONFIG_SND_SOC_ABE_TWL6040) || defined(CONFIG_SND_SOC_TWL6040_MODULE)
 #define twl_has_codec()	true
 #else
 #define twl_has_codec()	false
@@ -736,7 +736,7 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 	/* Phoenix*/
 	if (twl_has_codec() && pdata->codec && twl_class_is_6030()) {
 		sub_chip_id = twl_map[TWL_MODULE_AUDIO_VOICE].sid;
-		child = add_child(sub_chip_id, "twl6030_codec",
+		child = add_child(sub_chip_id, "twl6040_codec",
 				pdata->codec, sizeof(*pdata->codec),
 				false, 0, 0);
 		if (IS_ERR(child))
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4c738ec5d7e6..fc053ac98003 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -351,5 +351,6 @@ source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
 source "drivers/misc/iwmc3200top/Kconfig"
+source "drivers/misc/ti-st/Kconfig"
 
 endif # MISC_DEVICES
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 403012a5bdac..f2b1227c2200 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -32,3 +32,4 @@ obj-y				+= eeprom/
 obj-y				+= cb710/
 obj-$(CONFIG_VMWARE_BALLOON)	+= vmware_balloon.o
 obj-$(CONFIG_SENSORS_BH1780)	+= bh1780gli.o
+obj-y				+= ti-st/
diff --git a/drivers/misc/ti-st/Kconfig b/drivers/misc/ti-st/Kconfig
new file mode 100644
index 000000000000..a14cd8af8114
--- /dev/null
+++ b/drivers/misc/ti-st/Kconfig
@@ -0,0 +1,32 @@
+#
+# TI's shared transport line discipline and the protocol
+# drivers.
+#
+menu "Texas Instruments shared transport line discipline"
+    config TI_ST
+    tristate "shared transport core driver"
+    select FW_LOADER
+    help
+	This enables the shared transport core driver for TI
+	BT / FM and GPS combo chips.This enables protocol drivers
+	to register themselves with core and send data, the responses
+	are returned to relevant protocol drivers based on their
+	packet types.
+
+    config TI_ST_BT
+    tristate "BlueZ bluetooth driver for ST"
+    select BT
+    select TI_ST
+    help
+	This enables the Bluetooth driver for TI BT/FM/GPS combo devices
+	This makes use of shared transport line discipline core driver to
+	communicate with the BT core of the combo chip.
+
+    config TI_ST_FM
+    tristate "fm driver for ST"
+    select TI_ST
+    help
+	This enables the FM driver for TI BT/FM/GPS combo devices
+	This makes use of shared transport line discipline core driver to
+	communicate with the FM core of the combo chip.
+endmenu
diff --git a/drivers/misc/ti-st/Makefile b/drivers/misc/ti-st/Makefile
new file mode 100644
index 000000000000..c5d80fb5d314
--- /dev/null
+++ b/drivers/misc/ti-st/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for TI's shared transport line discipline
+# and it's protocol drivers.
+#
+obj-$(CONFIG_TI_ST) 	+= st_drv.o
+st_drv-objs		:= st_core.o st_kim.o st_ll.o
+obj-$(CONFIG_TI_ST_BT)	+= bt_drv.o
+obj-$(CONFIG_TI_ST_FM)	+= fm_drv.o
+fm_drv-objs		:= fmdrv_core.o fmdrv_v4l2.o fmdrv_st.o fmdrv_mixer.o fmdrv_chr.o
diff --git a/drivers/misc/ti-st/bt_drv.c b/drivers/misc/ti-st/bt_drv.c
new file mode 100644
index 000000000000..d8420b5c91fa
--- /dev/null
+++ b/drivers/misc/ti-st/bt_drv.c
@@ -0,0 +1,502 @@
+/*
+ *  Texas Instrument's Bluetooth Driver For Shared Transport.
+ *
+ *  Bluetooth Driver acts as interface between HCI CORE and
+ *  TI Shared Transport Layer.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+
+#include "st.h"
+#include "bt_drv.h"
+
+/* Define this macro to get debug msg */
+#undef DEBUG
+
+#ifdef DEBUG
+#define BT_DRV_DBG(fmt, arg...)  printk(KERN_INFO "(btdrv):"fmt"\n" , ## arg)
+#define BTDRV_API_START()        printk(KERN_INFO "(btdrv): %s Start\n", \
+	__func__)
+#define BTDRV_API_EXIT(errno)    printk(KERN_INFO "(btdrv): %s Exit(%d)\n", \
+	__func__, errno)
+#else
+#define BT_DRV_DBG(fmt, arg...)
+#define BTDRV_API_START()
+#define BTDRV_API_EXIT(errno)
+#endif
+
+#define BT_DRV_ERR(fmt, arg...)  printk(KERN_ERR "(btdrv):"fmt"\n" , ## arg)
+
+static int reset;
+static struct hci_st *hst;
+
+/* Increments HCI counters based on pocket ID (cmd,acl,sco) */
+static inline void hci_st_tx_complete(struct hci_st *hst, int pkt_type)
+{
+	struct hci_dev *hdev;
+
+	BTDRV_API_START();
+
+	hdev = hst->hdev;
+
+	/* Update HCI stat counters */
+	switch (pkt_type) {
+	case HCI_COMMAND_PKT:
+		hdev->stat.cmd_tx++;
+		break;
+
+	case HCI_ACLDATA_PKT:
+		hdev->stat.acl_tx++;
+		break;
+
+	case HCI_SCODATA_PKT:
+		hdev->stat.cmd_tx++;
+		break;
+	}
+
+	BTDRV_API_EXIT(0);
+}
+
+/* ------- Interfaces to Shared Transport ------ */
+
+/* Called by ST layer to indicate protocol registration completion
+ * status.hci_st_open() function will wait for signal from this
+ * API when st_register() function returns ST_PENDING.
+ */
+static void hci_st_registration_completion_cb(char data)
+{
+	BTDRV_API_START();
+
+	/* hci_st_open() function needs value of 'data' to know
+	 * the registration status(success/fail),So have a back
+	 * up of it.
+	 */
+	hst->streg_cbdata = data;
+
+	/* Got a feedback from ST for BT driver registration
+	 * request.Wackup hci_st_open() function to continue
+	 * it's open operation.
+	 */
+	complete(&hst->wait_for_btdrv_reg_completion);
+
+	BTDRV_API_EXIT(0);
+}
+
+/* Called by Shared Transport layer when receive data is
+ * available */
+static long hci_st_receive(struct sk_buff *skb)
+{
+	int err;
+	int len;
+
+	BTDRV_API_START();
+
+	err = 0;
+	len = 0;
+
+	if (skb == NULL) {
+		BT_DRV_ERR("Invalid SKB received from ST");
+		BTDRV_API_EXIT(-EFAULT);
+		return -EFAULT;
+	}
+	if (!hst) {
+		kfree_skb(skb);
+		BT_DRV_ERR("Invalid hci_st memory,freeing SKB");
+		BTDRV_API_EXIT(-EFAULT);
+		return -EFAULT;
+	}
+	if (!test_bit(BT_DRV_RUNNING, &hst->flags)) {
+		kfree_skb(skb);
+		BT_DRV_ERR("Device is not running,freeing SKB");
+		BTDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+
+	len = skb->len;
+	skb->dev = (struct net_device *)hst->hdev;
+
+	/* Forward skb to HCI CORE layer */
+	err = hci_recv_frame(skb);
+	if (err) {
+		kfree_skb(skb);
+		BT_DRV_ERR("Unable to push skb to HCI CORE(%d),freeing SKB",
+			   err);
+		BTDRV_API_EXIT(err);
+		return err;
+	}
+	hst->hdev->stat.byte_rx += len;
+
+	BTDRV_API_EXIT(0);
+	return 0;
+}
+
+/* ------- Interfaces to HCI layer ------ */
+
+/* Called from HCI core to initialize the device */
+static int hci_st_open(struct hci_dev *hdev)
+{
+	static struct st_proto_s hci_st_proto;
+	unsigned long timeleft;
+	int err;
+
+	BTDRV_API_START();
+
+	err = 0;
+
+	BT_DRV_DBG("%s %p", hdev->name, hdev);
+
+	/* Already registered with ST ? */
+	if (test_bit(BT_ST_REGISTERED, &hst->flags)) {
+		BT_DRV_ERR("Registered with ST already,open called again?");
+		BTDRV_API_EXIT(0);
+		return 0;
+	}
+
+	/* Populate BT driver info required by ST */
+	memset(&hci_st_proto, 0, sizeof(hci_st_proto));
+
+	/* BT driver ID */
+	hci_st_proto.type = ST_BT;
+
+	/* Receive function which called from ST */
+	hci_st_proto.recv = hci_st_receive;
+
+	/* Packet match function may used in future */
+	hci_st_proto.match_packet = NULL;
+
+	/* Callback to be called when registration is pending */
+	hci_st_proto.reg_complete_cb = hci_st_registration_completion_cb;
+
+	/* This is write function pointer of ST. BT driver will make use of this
+	 * for sending any packets to chip. ST will assign and give to us, so
+	 * make it as NULL */
+	hci_st_proto.write = NULL;
+
+	/* Register with ST layer */
+	err = st_register(&hci_st_proto);
+	if (err == ST_ERR_PENDING) {
+		/* Prepare wait-for-completion handler data structures.
+		 * Needed to syncronize this and st_registration_completion_cb()
+		 * functions.
+		 */
+		init_completion(&hst->wait_for_btdrv_reg_completion);
+
+		/* Reset ST registration callback status flag , this value
+		 * will be updated in hci_st_registration_completion_cb()
+		 * function whenever it called from ST driver.
+		 */
+		hst->streg_cbdata = -EINPROGRESS;
+
+		/* ST is busy with other protocol registration(may be busy with
+		 * firmware download).So,Wait till the registration callback
+		 * (passed as a argument to st_register() function) getting
+		 * called from ST.
+		 */
+		BT_DRV_DBG(" %s waiting for reg completion signal from ST",
+			   __func__);
+
+		timeleft =
+		    wait_for_completion_timeout
+		    (&hst->wait_for_btdrv_reg_completion,
+		     msecs_to_jiffies(BT_REGISTER_TIMEOUT));
+		if (!timeleft) {
+			BT_DRV_ERR("Timeout(%ld sec),didn't get reg"
+				   "completion signal from ST",
+				   BT_REGISTER_TIMEOUT / 1000);
+			BTDRV_API_EXIT(-ETIMEDOUT);
+			return -ETIMEDOUT;
+		}
+
+		/* Is ST registration callback called with ERROR value? */
+		if (hst->streg_cbdata != 0) {
+			BT_DRV_ERR("ST reg completion CB called with invalid"
+				   "status %d", hst->streg_cbdata);
+			BTDRV_API_EXIT(-EAGAIN);
+			return -EAGAIN;
+		}
+		err = 0;
+	} else if (err == ST_ERR_FAILURE) {
+		BT_DRV_ERR("st_register failed %d", err);
+		BTDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+
+	/* Do we have proper ST write function? */
+	if (hci_st_proto.write != NULL) {
+		/* We need this pointer for sending any Bluetooth pkts */
+		hst->st_write = hci_st_proto.write;
+	} else {
+		BT_DRV_ERR("failed to get ST write func pointer");
+
+		/* Undo registration with ST */
+		err = st_unregister(ST_BT);
+		if (err < 0)
+			BT_DRV_ERR("st_unregister failed %d", err);
+
+		hst->st_write = NULL;
+		BTDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+
+	/* Registration with ST layer is completed successfully,
+	 * now chip is ready to accept commands from HCI CORE.
+	 * Mark HCI Device flag as RUNNING
+	 */
+	set_bit(HCI_RUNNING, &hdev->flags);
+
+	/* Registration with ST successful */
+	set_bit(BT_ST_REGISTERED, &hst->flags);
+
+	BTDRV_API_EXIT(err);
+	return err;
+}
+
+/* Close device */
+static int hci_st_close(struct hci_dev *hdev)
+{
+	int err;
+
+	BTDRV_API_START();
+
+	err = 0;
+
+	/* Unregister from ST layer */
+	if (test_and_clear_bit(BT_ST_REGISTERED, &hst->flags)) {
+		err = st_unregister(ST_BT);
+		if (err != ST_SUCCESS) {
+			BT_DRV_ERR("st_unregister failed %d", err);
+			BTDRV_API_EXIT(-EBUSY);
+			return -EBUSY;
+		}
+	}
+
+	hst->st_write = NULL;
+
+	/* ST layer would have moved chip to inactive state.
+	 * So,clear HCI device RUNNING flag.
+	 */
+	if (!test_and_clear_bit(HCI_RUNNING, &hdev->flags)) {
+		BTDRV_API_EXIT(0);
+		return 0;
+	}
+
+	BTDRV_API_EXIT(err);
+	return err;
+}
+
+/* Called from HCI CORE , Sends frames to Shared Transport */
+static int hci_st_send_frame(struct sk_buff *skb)
+{
+	struct hci_dev *hdev;
+	struct hci_st *hst;
+	long len;
+
+	BTDRV_API_START();
+
+	if (skb == NULL) {
+		BT_DRV_ERR("Invalid skb received from HCI CORE");
+		BTDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	hdev = (struct hci_dev *)skb->dev;
+	if (!hdev) {
+		BT_DRV_ERR("SKB received for invalid HCI Device (hdev=NULL)");
+		BTDRV_API_EXIT(-ENODEV);
+		return -ENODEV;
+	}
+	if (!test_bit(HCI_RUNNING, &hdev->flags)) {
+		BT_DRV_ERR("Device is not running");
+		BTDRV_API_EXIT(-EBUSY);
+		return -EBUSY;
+	}
+
+	hst = (struct hci_st *)hdev->driver_data;
+
+	/* Prepend skb with frame type */
+	memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1);
+
+	BT_DRV_DBG(" %s: type %d len %d", hdev->name, bt_cb(skb)->pkt_type,
+		   skb->len);
+
+	/* Insert skb to shared transport layer's transmit queue.
+	 * Freeing skb memory is taken care in shared transport layer,
+	 * so don't free skb memory here.
+	 */
+	if (!hst->st_write) {
+		kfree_skb(skb);
+		BT_DRV_ERR(" Can't write to ST, st_write null?");
+		BTDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+	len = hst->st_write(skb);
+	if (len < 0) {
+		/* Something went wrong in st write , free skb memory */
+		kfree_skb(skb);
+		BT_DRV_ERR(" ST write failed (%ld)", len);
+		BTDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+
+	/* ST accepted our skb. So, Go ahead and do rest */
+	hdev->stat.byte_tx += len;
+	hci_st_tx_complete(hst, bt_cb(skb)->pkt_type);
+
+	BTDRV_API_EXIT(0);
+	return 0;
+}
+
+static void hci_st_destruct(struct hci_dev *hdev)
+{
+	BTDRV_API_START();
+
+	if (!hdev) {
+		BT_DRV_ERR("Destruct called with invalid HCI Device"
+			   "(hdev=NULL)");
+		BTDRV_API_EXIT(0);
+		return;
+	}
+
+	BT_DRV_DBG("%s", hdev->name);
+
+	/* free hci_st memory */
+	if (hdev->driver_data != NULL)
+		kfree(hdev->driver_data);
+
+	BTDRV_API_EXIT(0);
+	return;
+}
+
+/* Creates new HCI device */
+static int hci_st_register_dev(struct hci_st *hst)
+{
+	struct hci_dev *hdev;
+
+	BTDRV_API_START();
+
+	/* Initialize and register HCI device */
+	hdev = hci_alloc_dev();
+	if (!hdev) {
+		BT_DRV_ERR("Can't allocate HCI device");
+		BTDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	BT_DRV_DBG(" HCI device allocated. hdev= %p", hdev);
+
+	hst->hdev = hdev;
+	hdev->bus = HCI_UART;
+	hdev->driver_data = hst;
+	hdev->open = hci_st_open;
+	hdev->close = hci_st_close;
+	hdev->flush = NULL;
+	hdev->send = hci_st_send_frame;
+	hdev->destruct = hci_st_destruct;
+	hdev->owner = THIS_MODULE;
+
+	if (reset)
+		set_bit(HCI_QUIRK_NO_RESET, &hdev->quirks);
+
+	if (hci_register_dev(hdev) < 0) {
+		BT_DRV_ERR("Can't register HCI device");
+		hci_free_dev(hdev);
+		BTDRV_API_EXIT(-ENODEV);
+		return -ENODEV;
+	}
+
+	BT_DRV_DBG(" HCI device registered. hdev= %p", hdev);
+	BTDRV_API_EXIT(0);
+	return 0;
+}
+
+/* ------- Module Init interface ------ */
+
+static int __init bt_drv_init(void)
+{
+	int err;
+
+	BTDRV_API_START();
+
+	err = 0;
+
+	BT_DRV_DBG(" Bluetooth Driver Version %s", VERSION);
+
+	/* Allocate local resource memory */
+	hst = kzalloc(sizeof(struct hci_st), GFP_KERNEL);
+	if (!hst) {
+		BT_DRV_ERR("Can't allocate control structure");
+		BTDRV_API_EXIT(-ENFILE);
+		return -ENFILE;
+	}
+
+	/* Expose "hciX" device to user space */
+	err = hci_st_register_dev(hst);
+	if (err) {
+		/* Release local resource memory */
+		kfree(hst);
+
+		BT_DRV_ERR("Unable to expose hci0 device(%d)", err);
+		BTDRV_API_EXIT(err);
+		return err;
+	}
+	set_bit(BT_DRV_RUNNING, &hst->flags);
+
+	BTDRV_API_EXIT(err);
+	return err;
+}
+
+/* ------- Module Exit interface ------ */
+
+static void __exit bt_drv_exit(void)
+{
+	BTDRV_API_START();
+
+	/* Deallocate local resource's memory  */
+	if (hst) {
+		struct hci_dev *hdev = hst->hdev;
+
+		if (hdev == NULL) {
+			BT_DRV_ERR("Invalid hdev memory");
+			kfree(hst);
+		} else {
+			hci_st_close(hdev);
+			if (test_and_clear_bit(BT_DRV_RUNNING, &hst->flags)) {
+				/* Remove HCI device (hciX) created
+				 * in module init.
+				 */
+				hci_unregister_dev(hdev);
+
+				/* Free HCI device memory */
+				hci_free_dev(hdev);
+			}
+		}
+	}
+	BTDRV_API_EXIT(0);
+}
+
+module_init(bt_drv_init);
+module_exit(bt_drv_exit);
+
+/* ------ Module Info ------ */
+
+module_param(reset, bool, 0644);
+MODULE_PARM_DESC(reset, "Send HCI reset command on initialization");
+MODULE_AUTHOR("Raja Mani <raja_mani@ti.com>");
+MODULE_DESCRIPTION("Bluetooth Driver for TI Shared Transport" VERSION);
+MODULE_VERSION(VERSION);
+MODULE_LICENSE("GPL");
diff --git a/drivers/misc/ti-st/bt_drv.h b/drivers/misc/ti-st/bt_drv.h
new file mode 100644
index 000000000000..a0beebec8465
--- /dev/null
+++ b/drivers/misc/ti-st/bt_drv.h
@@ -0,0 +1,61 @@
+/*
+ *  Texas Instrument's Bluetooth Driver For Shared Transport.
+ *
+ *  Bluetooth Driver acts as interface between HCI CORE and
+ *  TI Shared Transport Layer.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _BT_DRV_H
+#define _BT_DRV_H
+
+/* Bluetooth Driver Version */
+#define VERSION               "1.0"
+
+/* Defines number of seconds to wait for reg completion
+ * callback getting called from ST (in case,registration
+ * with ST returns PENDING status)
+ */
+#define BT_REGISTER_TIMEOUT   msecs_to_jiffies(6000)	/* 6 sec */
+
+/* BT driver's local status */
+#define BT_DRV_RUNNING        0
+#define BT_ST_REGISTERED      1
+
+/* BT driver operation structure */
+struct hci_st {
+
+	/* hci device pointer which binds to bt driver */
+	struct hci_dev *hdev;
+
+	/* used locally,to maintain various BT driver status */
+	unsigned long flags;
+
+	/* to hold ST registration callback  status */
+	char streg_cbdata;
+
+	/* write function pointer of ST driver */
+	long (*st_write) (struct sk_buff *);
+
+	/* Wait on comepletion handler needed to synchronize
+	 * hci_st_open() and hci_st_registration_completion_cb()
+	 * functions.*/
+	struct completion wait_for_btdrv_reg_completion;
+};
+
+#endif
diff --git a/drivers/misc/ti-st/fm.h b/drivers/misc/ti-st/fm.h
new file mode 100644
index 000000000000..be41453649ed
--- /dev/null
+++ b/drivers/misc/ti-st/fm.h
@@ -0,0 +1,13 @@
+struct fm_event_hdr {
+	unsigned char plen;
+} __attribute__ ((packed));
+
+#define FM_MAX_FRAME_SIZE 0xFF	/* TODO: */
+#define FM_EVENT_HDR_SIZE 1	/* size of fm_event_hdr */
+#define ST_FM_CH8_PKT 0x8
+
+/* gps stuff */
+struct gps_event_hdr {
+unsigned char opcode;
+unsigned short plen;
+} __attribute__ ((packed));
diff --git a/drivers/misc/ti-st/fmdrv.h b/drivers/misc/ti-st/fmdrv.h
new file mode 100644
index 000000000000..b675973d7c89
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv.h
@@ -0,0 +1,261 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  Common header for all FM driver sub-modules.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _FM_DRV_H
+#define _FM_DRV_H
+
+#include <linux/skbuff.h>
+#include <linux/interrupt.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <linux/timer.h>
+#include <linux/version.h>
+
+/* Driver version */
+#define FM_DRV_VERSION            "0.01"
+
+/* Should match with FM_DRV_VERSION */
+#define FM_DRV_RADIO_VERSION      KERNEL_VERSION(0, 0, 1)
+
+/* Driver name */
+#define FM_DRV_NAME               "ti_fmdrv"
+
+/* Card short name */
+#define FM_DRV_CARD_SHORT_NAME    "TI FM Radio"
+
+/* Card long name */
+#define FM_DRV_CARD_LONG_NAME     "Texas Instruments FM Radio"
+
+/* Define this macro to get debug msg */
+#ifdef DEBUG
+#define FM_DRV_DBG(fmt, arg...)  \
+	pr_info("(fmdrv): "fmt"\n" , ## arg)
+#define FMDRV_API_START()        \
+	pr_info("(fmdrv): %s Start\n", __func__)
+#define FMDRV_API_EXIT(errno)    \
+	pr_info("(fmdrv): %s Exit(%d)\n", __func__, errno)
+#define FM_DUMP_TXRX_PKT
+#else
+#define FM_DRV_DBG(fmt, arg...)
+#define FMDRV_API_START()
+#define FMDRV_API_EXIT(errno)
+#endif
+
+#define FM_DRV_ERR(fmt, arg...)  \
+	pr_err("(fmdrv): "fmt"\n" , ## arg)
+
+#define FM_ST_NOT_CLAIMED  0
+#define FM_ST_CLAIMED      1
+
+#define FM_ST_SUCCESS      0
+#define FM_ST_FAILED      -1
+
+/* Flag info */
+#define FM_INTTASK_RUNNING            0
+#define FM_INTTASK_SCHEDULE_PENDING   1
+#define FM_FIRMWARE_DW_INPROGRESS     2
+#define FM_CORE_READY                 3
+#define FM_CORE_TRANSPORT_READY       4
+#define FM_AF_SWITCH_INPROGRESS	      5
+#define FM_CORE_TX_XMITING	      6
+
+/* FM packet TX timeout */
+#define FM_DRV_TX_TIMEOUT      (5*HZ)	/* 5 seconds */
+
+/* Seek operation timeout */
+#define FM_DRV_RX_SEEK_TIMEOUT (20*HZ)	/* 20 seconds */
+
+/* To know the number of entries in array */
+#define NO_OF_ENTRIES_IN_ARRAY(array) (sizeof(array) / sizeof(array[0]))
+
+/* Firmware download option */
+enum {
+	FM_MODE_OFF,
+	FM_MODE_TX,
+	FM_MODE_RX,
+	FM_MODE_ENTRY_MAX
+};
+
+#define FM_RX_RDS_INFO_FIELD_MAX	8	/* 4 Group * 2 Bytes */
+
+/* RX RDS data format */
+struct fm_rdsdata_format {
+	union {
+		struct {
+			unsigned char rdsBuff[FM_RX_RDS_INFO_FIELD_MAX];
+		} groupDataBuff;
+		struct {
+			unsigned short piData;
+			unsigned char blockB_byte1;
+			unsigned char blockB_byte2;
+			unsigned char blockC_byte1;
+			unsigned char blockC_byte2;
+			unsigned char blockD_byte1;
+			unsigned char blockD_byte2;
+		} groupGeneral;
+		struct {
+			unsigned short piData;
+			unsigned char blockB_byte1;
+			unsigned char blockB_byte2;
+			unsigned char firstAf;
+			unsigned char secondAf;
+			unsigned char firstPsByte;
+			unsigned char secondPsByte;
+		} group0A;
+
+		struct {
+			unsigned short piData;
+			unsigned char blockB_byte1;
+			unsigned char blockB_byte2;
+			unsigned short piData2;
+			unsigned char firstPsByte;
+			unsigned char secondPsByte;
+		} group0B;
+	} rdsData;
+};
+
+typedef void (*Int_Handler_ProtoType) (void);
+
+/* FM region (Europe/US, Japan) info */
+struct region_info {
+	unsigned int channel_spacing;
+	unsigned int bottom_frequency;
+	unsigned int top_frequency;
+	unsigned char region_index;
+};
+/* FM Interrupt processing related info */
+struct fm_irq {
+	unsigned char stage_index;
+	unsigned short flag;	/* FM interrupt flag */
+	unsigned short mask;	/* FM interrupt mask */
+	/* Interrupt process timeout handler */
+	struct timer_list int_timeout_timer;
+	unsigned char irq_service_timeout_retry;
+	Int_Handler_ProtoType *fm_IntActionHandlerTable;
+};
+
+/* RDS info */
+struct fm_rds {
+	unsigned char flag;	/* RX RDS on/off status */
+	unsigned char last_block_index;	/* Last received RDS block */
+
+	/* RDS buffer */
+	wait_queue_head_t read_queue;
+	unsigned int buf_size;	/* Size is always multiple of 3 */
+	unsigned int wr_index;
+	unsigned int rd_index;
+	unsigned char *buffer;
+};
+
+#define FM_RDS_MAX_AF_LIST		25
+
+/* Current RX channel Alternate Frequency cache.
+ * This info is used to switch to other freq (AF)
+ * when current channel signal strengh is below RSSI threshold.
+ */
+struct tuned_station_info {
+	unsigned short picode;
+	unsigned int af_cache[FM_RDS_MAX_AF_LIST];
+	unsigned char no_of_items_in_afcache;
+	unsigned char af_list_max;
+};
+
+/* FM RX mode info */
+struct fm_rx {
+	struct region_info region;	/* Current selected band */
+	unsigned int curr_freq;	/* Current RX frquency */
+	unsigned char curr_mute_mode;	/* Current mute mode */
+	/* RF dependent soft mute mode */
+	unsigned char curr_rf_depend_mute;
+	unsigned short curr_volume;	/* Current volume level */
+	short curr_rssi_threshold;	/* Current RSSI threshold level */
+	/* Holds the index of the current AF jump */
+	unsigned char cur_Afjump_index;
+	/* Will hold the frequency before the jump */
+	unsigned int freq_before_jump;
+	unsigned char rds_mode;	/* RDS operation mode (RDS/RDBS) */
+	unsigned char af_mode;	/* Alternate frequency on/off */
+	struct tuned_station_info cur_station_info;
+	struct fm_rds rds;
+};
+
+/*
+ * FM TX RDS data
+ *
+ * @ text_type: is the text following PS or RT
+ * @ text: radio text string which could either be PS or RT
+ * @ af_freq: alternate frequency for Tx
+ * TODO: to be declared in application
+ */
+struct tx_rds {
+	unsigned char text_type;
+	unsigned char text[25];
+	unsigned int af_freq;
+};
+/*
+ * FM TX global data
+ *
+ * @ pwr_lvl: Power Level of the Transmission from mixer control
+ * @ xmit_state: Transmission state = Updated locally upon Start/Stop
+ * @ audio_io: i2S/Analog
+ * @ tx_frq: Transmission frequency
+ */
+struct fmtx_data {
+	unsigned char pwr_lvl;
+	unsigned char xmit_state;
+	unsigned char audio_io;
+	unsigned long tx_frq;
+	struct tx_rds rds;
+};
+
+/* FM driver operation structure */
+struct fmdrv_ops {
+	struct video_device *v4l2dev;	/* V4L2 video device pointer */
+	struct snd_card *card;	/* Card which holds FM mixer controls */
+	unsigned short asci_id;
+	spinlock_t rds_buff_lock;
+	spinlock_t resp_skb_lock;
+
+	long flag;		/*  FM driver state machine info */
+
+	struct sk_buff_head rx_q;	/* RX queue */
+	struct tasklet_struct rx_task;	/* RX Tasklet */
+
+	struct sk_buff_head tx_q;	/* TX queue */
+	struct tasklet_struct tx_task;	/* TX Tasklet */
+	unsigned long last_tx_jiffies;	/* Timestamp of last pkt sent */
+	atomic_t tx_cnt;	/* Number of packets can send at a time */
+
+	struct sk_buff *response_skb;	/* Response from the chip */
+	/* Main task completion handler */
+	struct completion maintask_completion;
+	/* Opcode of last command sent to the chip */
+	unsigned char last_sent_pkt_opcode;
+	/* Handler used for wakeup when response packet is received */
+	struct completion *response_completion;
+	struct fm_irq irq_info;
+	unsigned char curr_fmmode; /* Current FM chip mode (TX, RX, OFF) */
+	struct fm_rx rx;	/* FM receiver info */
+	struct fmtx_data tx_data;
+};
+
+#endif
diff --git a/drivers/misc/ti-st/fmdrv_chr.c b/drivers/misc/ti-st/fmdrv_chr.c
new file mode 100644
index 000000000000..a5a8e0664acc
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_chr.c
@@ -0,0 +1,779 @@
+/*
+ *   FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *   Copyright (C) 2009 Texas Instruments
+ *   Written by Raghavendra Shenoy (x0099675@ti.com)
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License version 2 as
+ *   published by the Free Software Foundation.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+
+#include <linux/tty.h>
+#include <linux/sched.h>
+
+#include <linux/poll.h>
+#include <linux/delay.h>
+#include <linux/skbuff.h>
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
+
+#include <linux/uaccess.h>
+
+#include "fmdrv_st.h"
+#include "fmdrv_chr.h"
+
+/* Structure that has FM character driver data */
+struct fm_chrdrv_ops *fm_chr_dev;
+
+/* File operations structure initialization */
+const struct file_operations fm_chr_ops = {
+	.owner = THIS_MODULE,
+	.fasync = fm_chr_fasync,
+	.open = fm_chr_open,
+	.read = fm_chr_read,
+	.write = fm_chr_write,
+	.poll = fm_chr_poll,
+	.ioctl = fm_chr_ioctl,
+	.release = fm_chr_release,
+};
+
+/* Converting Channel-8 response to Channel-4 response */
+static struct sk_buff *convert2_channel_4(struct sk_buff *ch8_skb)
+{
+	struct evt_cmd_complete *evt;
+	struct sk_buff *ch4_skb;
+
+	unsigned char ncmds;	/* num_hci cmds */
+	unsigned char status;
+	unsigned char pkt_type;
+
+	unsigned short opcode;
+	unsigned short hci_vs_opcode;
+
+	unsigned char *ptr, *chan4_mem;
+	unsigned char chan4_index, chan8_index;
+	unsigned char num_hci, param_len, fm_opcode;
+	unsigned char read_write, evt_code, cmd_len, int_len, chan8_cmd_len;
+
+	FM_CHR_DRV_START();
+
+	fm_opcode = read_write = 0;
+	chan8_index = chan4_index = 0;
+	int_len = num_hci = cmd_len = param_len = 0;
+	opcode = 0x0000;
+
+	ptr = NULL;
+	ch4_skb = NULL;
+	chan4_mem = NULL;
+
+	chan8_cmd_len = ch8_skb->data[CHAN8_RESP_CMD_LEN_POS];
+	if ((chan8_cmd_len + CHAN8_RESP_CMD_LEN_SIZE + CHAN8_RESP_TYPE_SIZE) !=
+	    ch8_skb->len) {
+		FM_CHR_DRV_ERR(" Channel-8 response length mismatch ");
+
+		return NULL;
+	}
+
+	/* Copy the opcode from Channel-1 command packet.
+	 * Channel-8 response packets can only be converted into Channel-4
+	 * HCI command complete event packets.
+	 *
+	 * Mark the packet type as Channel-4 packet type.
+	 */
+	evt_code = CHAN4_CMD_COMPLETE_TYPE;
+
+	/* Copy the opcode from Channel-8 reponse packet */
+	fm_opcode = ch8_skb->data[CHAN8_RESP_FM_OPCODE_POS];
+
+	/* Conversion logic for response packets with Power mode opcode */
+	if (fm_opcode == CHAN8_FM_PWR_OPCODE) {
+		ch4_skb = alloc_skb(7, GFP_ATOMIC);
+		if (ch4_skb == NULL) {
+			FM_CHR_DRV_ERR(" SKB allocation failed ");
+			return NULL;
+		}
+
+		/* Copy from Channel-8 reponse packet */
+		pkt_type = CHAN4_PKT_TYPE;
+		evt_code = CHAN4_CMD_COMPLETE_TYPE;	/* cmd complete event */
+		ncmds = ch8_skb->data[CHAN8_RESP_NUM_HCI_POS];/* num_hci cmds */
+		param_len = 4;	/* fd37 + num hci cmds */
+		hci_vs_opcode = CHAN1_FM_PWR_OPCODE;
+		status = ch8_skb->data[CHAN8_RESP_STATUS_POS];
+
+		/* Copy to Channel-4 response packet */
+		memcpy(skb_put(ch4_skb, 1), &pkt_type, 1);
+		memcpy(skb_put(ch4_skb, 1), &evt_code, 1);
+		memcpy(skb_put(ch4_skb, 1), &param_len, 1);
+		memcpy(skb_put(ch4_skb, 1), &ncmds, 1);
+		memcpy(skb_put(ch4_skb, 2), &hci_vs_opcode, 2);
+		memcpy(skb_put(ch4_skb, 1), &status, 1);
+
+		/* Trim the data to specified length */
+		skb_trim(ch4_skb, 7);
+
+		return ch4_skb;
+	}
+
+	/* To accomodate an extra 0 that Channel-4 response sends */
+	ch4_skb = alloc_skb((ch8_skb->len + 1), GFP_ATOMIC);
+	if (ch4_skb == NULL) {
+		FM_CHR_DRV_ERR(" SKB allocation failed ");
+
+		return NULL;
+	}
+	skb_put(ch4_skb, ch8_skb->len + 1);
+
+	/*  Copy the command length, NUM_HCI, R/W values from Channl-8 reponse
+	 *  packet
+	 */
+	cmd_len = ch8_skb->data[CHAN8_RESP_CMD_LEN_POS];
+	num_hci = ch8_skb->data[CHAN8_RESP_NUM_HCI_POS];
+	read_write = ch8_skb->data[CHAN8_RESP_RW_POS];
+
+	/* Update Channel-4 response packet's opcode bit */
+	if (read_write == CHAN8_RD_RESP)
+		opcode = CHAN1_READ_OPCODE;
+	else
+		opcode = CHAN1_WRITE_OPCODE;
+
+	param_len = ch8_skb->data[CHAN8_RESP_PARAM_LEN_POS];
+
+	/* Copying the header-data to Channel-4 response packet */
+	ch4_skb->data[CHAN4_TYPE_POS] = CHAN4_PKT_TYPE;
+	ch4_skb->data[CHAN4_EVT_TYPE_POS] = evt_code;
+
+	/* Copying the parameters from Channel-8 response packets to Channel-4
+	 * response packets.
+	 */
+	evt = (void *)&ch4_skb->data[CHAN4_EVT_POS];
+	evt->opcode = opcode;
+	evt->ncmd = num_hci;
+
+	chan8_index = CHAN8_RESP_PARAM_POS;
+	chan4_index = CHAN4_PARAM_POS;
+
+	/* Allocate memory to copy the parameters. The parameters are
+	 * copied from Channel-8 response packet to this memory and then
+	 * copied to Channel-4 response packet.
+	 */
+	chan4_mem = kzalloc((param_len) * (sizeof(unsigned char)), GFP_ATOMIC);
+
+	if (chan4_mem == NULL) {
+		FM_CHR_DRV_ERR(" chan4_mem == NULL ");
+
+		return ch8_skb;
+	}
+
+	int_len = param_len;
+	ptr = (void *)chan4_mem;
+
+	/* The parameters are copied from Channel-8 response packet to the
+	*  intermediate memory location.
+	*/
+	while (param_len--) {
+		*ptr = ch8_skb->data[chan8_index];
+		ptr++;
+		chan8_index++;
+	}
+
+	/* Copy the extra 0 */
+	ch4_skb->data[chan4_index] = 0x00;
+	chan4_index++;
+
+	param_len = int_len;
+	ptr = (void *)chan4_mem;
+
+	/* The parameters are copied from intermediate memory location
+	 * to Channel-4 response packet.
+	 */
+	while (param_len--) {
+		ch4_skb->data[chan4_index++] = *ptr;
+		ptr++;
+	}
+	kfree(chan4_mem);
+	/* plen would be chan8_index - pkt_type - evt code */
+	ch4_skb->data[CHAN4_PLEN_POS] =
+	    chan8_index - CHAN4_PKT_TYPE_SIZE - CHAN4_EVT_TYPE_SIZE;
+
+	return ch4_skb;
+
+}
+
+/* Convert the Channel-1 commands into Channel-8 commands */
+static int convert2_channel_8(struct sk_buff *skb)
+{
+	struct hci_command_hdr *hdr;
+
+	unsigned short chan8_index, chan1_index;
+	unsigned char fm_opcode, read_write, num_params, chan1_cmd_len;
+
+	/* FM power ON/OFF commands */
+	unsigned char fm_pwr_on[] = { 0x08, 0x05, 0xFE, 0x00,
+				      0x02, 0x00, 0x01 };
+	unsigned char fm_pwr_off[] = { 0x08, 0x05, 0xFE, 0x00,
+				      0x02, 0x00, 0x00 };
+
+	FM_CHR_DRV_START();
+
+	hdr = NULL;
+	fm_opcode = 0;
+	read_write = 0;
+	num_params = 0;
+	chan8_index = 0;
+	chan1_index = 0;
+
+	chan1_cmd_len = skb->data[CHAN1_CMD_LEN_POS];
+
+	if ((chan1_cmd_len + CHAN1_TYPE_SIZE + CHAN1_OPCODE_SIZE +
+	     CHAN1_CMD_LEN_SIZE) != skb->len) {
+		FM_CHR_DRV_ERR(" Channel-1 length mismatch ");
+
+		return -1;
+	}
+
+	/* Copy the opcode from Channel-1 command packet */
+	hdr = (void *)&skb->data[CHAN1_TYPE_POS];
+
+	/* Conversion for commands with Power mode opcode */
+	if (hdr->opcode == CHAN1_FM_PWR_OPCODE) {
+		/* Set skb length to zero and skb tail pointer
+		 * to data pointer.
+		 */
+		skb_trim(skb, 0);
+
+		/* For FM Power ON command */
+		if (skb->data[CHAN1_FM_OPCODE_POS] == 0x01) {
+			memcpy(skb_put(skb, sizeof(fm_pwr_on)), fm_pwr_on,
+			       sizeof(fm_pwr_on));
+		} else {
+			/* For Power OFF command */
+			memcpy(skb_put(skb, sizeof(fm_pwr_off)), fm_pwr_off,
+			       sizeof(fm_pwr_off));
+		}
+
+		return 0;
+	}
+
+	/* Copy the parameters from Channel-1 command packet */
+	/* Only the LSB of this value will be used */
+	num_params = skb->data[CHAN1_PARAM_LEN_POS];
+	fm_opcode = skb->data[CHAN1_FM_OPCODE_POS];
+	chan1_index = CHAN1_PARAM_POS;
+
+	/* Copy the Channel-1 header data to Channel-8 header fields */
+	read_write =
+	    (hdr->opcode == CHAN1_READ_OPCODE) ? CHAN8_RD_CMD : CHAN8_WR_CMD;
+	skb->data[CHAN8_TYPE_POS] = CHAN8_PKT_TYPE;
+
+	/* cmd_length/skb->data[1] = fm_opcode + read_write + param_len
+	 * in addition to num_params
+	 */
+	skb->data[CHAN8_FM_OPCODE_POS] = fm_opcode;
+	skb->data[CHAN8_RW_POS] = read_write;
+	chan8_index = CHAN8_PARAM_POS;
+
+	skb->data[CHAN8_CMD_LEN_POS] = num_params + CHAN8_OPCODE_SIZE +
+	    CHAN8_RD_WR_SIZE + CHAN8_PARAM_LEN_SIZE;
+
+	/* Copy the Channel-1 parameters to Channel-8 parameter field */
+
+	/* READ command except read_hw_register */
+	if ((read_write == CHAN8_RD_CMD) &&
+	    (fm_opcode != CHAN1_HW_REG_OPCODE)) {
+		/* Expected bytes to read */
+		skb->data[CHAN8_PARAM_LEN_POS] = num_params;
+
+		chan8_index = CHAN8_PARAM_POS;
+		skb->data[CHAN8_CMD_LEN_POS] = CHAN8_OPCODE_SIZE +
+		    CHAN8_RD_WR_SIZE + CHAN8_PARAM_LEN_SIZE;
+	} else {
+
+		/* skb->data[4] contains length of parameters following */
+		skb->data[CHAN8_PARAM_LEN_POS] = num_params;
+
+		while (num_params) {
+			skb->data[chan8_index] = skb->data[chan1_index];
+			chan8_index++;
+			chan1_index++;
+			num_params--;
+		}
+	}
+
+	skb_trim(skb, chan8_index);
+
+	return 0;
+}
+
+/* Tasklet function which will be scheduled by FM ST sub-module
+ * when data is received
+ */
+long fm_rx_task(void)
+{
+	struct sk_buff *skb;
+	unsigned long flags = 0;
+
+#ifdef VERBOSE
+	int len;
+#endif
+
+	FM_CHR_DRV_START();
+
+	skb = NULL;
+	spin_lock_irqsave(&fm_chr_dev->lock, flags);
+
+	if (skb_queue_empty(&fm_chr_dev->rx_q)) {
+		FM_CHR_DRV_ERR(" Rx Queue empty ");
+		spin_unlock_irqrestore(&fm_chr_dev->lock, flags);
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+
+	/* Dequeue the skb received from the FM_ST interface */
+	skb = skb_dequeue(&fm_chr_dev->rx_q);
+	if (skb == NULL) {
+		FM_CHR_DRV_ERR(" Dequeued skb from Rx queue is NULL ");
+		spin_unlock_irqrestore(&fm_chr_dev->lock, flags);
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+
+	/* Send a signal to TI FM stack when an Interrupt packet arrives */
+	if (skb->data[CHAN8_RESP_FM_OPCODE_POS] == CHAN8_FM_INTERRUPT) {
+		FM_CHR_DRV_VER(" Interrupt arrived: ");
+
+#ifdef VERBOSE
+		for (len = 0; ((skb) && (len < skb->len)); len++)
+			printk(KERN_INFO " 0x%02x ", skb->data[len]);
+		printk("\n");
+#endif
+
+		kfree_skb(skb);
+
+		/* kill_fasync here - Sends the signal. Check if the queue is
+		 * empty. If not, it means that command complete response for
+		 * the previous command is not sent to the stack. Don't send
+		 * the Signal. Set the SIGNAL_PENDING bit. This bit is cleared
+		 * in the read() of the stack, when it reads the command
+		 * complete response.
+		 */
+		if (likely(skb_queue_empty(&fm_chr_dev->rx_q))) {
+			/* Should come here most often */
+			kill_fasync(&fm_chr_dev->fm_fasync, SIGIO, POLLIN);
+			clear_bit(SIGNAL_PENDING, &fm_chr_dev->state_flags);
+		} else {
+			FM_CHR_DRV_VER(" signal not sent..");
+			set_bit(SIGNAL_PENDING, &fm_chr_dev->state_flags);
+		}
+
+		spin_unlock_irqrestore(&fm_chr_dev->lock, flags);
+
+		return FM_CHR_DRV_SUCCESS;
+	}
+
+	/* Queue it back to the queue if the received packet
+	 * is not an interrupt packet
+	 */
+	skb_queue_head(&fm_chr_dev->rx_q, skb);
+	wake_up_interruptible(&fm_chr_dev->fm_data_q);
+
+	spin_unlock_irqrestore(&fm_chr_dev->lock, flags);
+
+	return FM_CHR_DRV_SUCCESS;
+}
+
+/* Functions called from the TI-FM stack */
+int fm_chr_fasync(int fd, struct file *file, int on)
+{
+	FM_CHR_DRV_START();
+
+	return fasync_helper(fd, file, on, &fm_chr_dev->fm_fasync);
+}
+
+int fm_chr_open(struct inode *inod, struct file *fil)
+{
+	int err;
+	int err_st_release;
+
+	FM_CHR_DRV_START();
+
+	err = FM_CHR_DRV_SUCCESS;
+	err_st_release = FM_CHR_DRV_SUCCESS;
+
+	/* Check if V4L2 FM device is already using ST driver */
+	if (fm_st_claim() < FM_CHR_DRV_SUCCESS) {
+		FM_CHR_DRV_ERR(" Other FM device is already active ");
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+
+	/* Register with the FM_ST interface, which will register with the
+	 * ST driver
+	 */
+	err = fm_st_register(&fm_chr_dev->rx_q, &fm_chr_dev->rx_task);
+	if (err < FM_CHR_DRV_SUCCESS) {
+		FM_CHR_DRV_ERR(" Registration with ST Failed ");
+		FM_CHR_DRV_VER(" Releasing FM ST Interface... ");
+
+		err_st_release = fm_st_release();
+		if (err_st_release < FM_CHR_DRV_SUCCESS) {
+			FM_CHR_DRV_ERR(" Failed to release FM ST (%d)",
+				       err_st_release);
+
+			return err;
+		}
+		FM_CHR_DRV_VER(" Successfully released FM_ST interface ");
+
+		return err;
+	}
+
+	/* Initialize the wait queue and the Rx tasklets */
+	init_waitqueue_head(&fm_chr_dev->fm_data_q);
+	tasklet_init(&fm_chr_dev->rx_task, (void *)fm_rx_task,
+		     (unsigned long)fm_chr_dev);
+
+	FM_CHR_DRV_VER(" st_register completed");
+
+	return FM_CHR_DRV_SUCCESS;
+}
+
+int fm_chr_release(struct inode *inod, struct file *fil)
+{
+	int err;
+
+	FM_CHR_DRV_START();
+
+	err = 0;
+
+	/* Clear the asynchronous notifications to the process linked
+	 * with the file descriptor 'fil'
+	 */
+	fm_chr_fasync(-1, fil, 0);
+
+	/* Release the tasklets and the queues */
+	tasklet_kill(&fm_chr_dev->rx_task);
+	skb_queue_purge(&fm_chr_dev->rx_q);
+
+	/* Unregister FM with ST driver */
+	err = fm_st_unregister();
+	if (err < FM_CHR_DRV_SUCCESS) {
+		FM_CHR_DRV_ERR(" Unable to unregister from ST ");
+
+		return err;
+	}
+	FM_CHR_DRV_VER(" Successfully unregistered from ST ");
+
+	/* Release FM ST - FM character driver is not using
+	 * the ST driver
+	 */
+	err = fm_st_release();
+	if (err < FM_CHR_DRV_SUCCESS) {
+		FM_CHR_DRV_ERR(" Failed to release FM ST ");
+
+		return err;
+	}
+	FM_CHR_DRV_VER(" Successfully released FM_ST interface ");
+
+	return FM_CHR_DRV_SUCCESS;
+}
+
+ssize_t fm_chr_write(struct file *fil, const char __user *data,
+		     size_t size, loff_t *offset)
+{
+	int err;
+	struct sk_buff *skb;
+
+#ifdef VERBOSE
+	int len;
+#endif
+
+	FM_CHR_DRV_START();
+
+	err = FM_CHR_DRV_SUCCESS;
+
+	if (data[CHAN1_TYPE_POS] != CHAN1_PKT_TYPE) {
+		FM_CHR_DRV_ERR(" Packet type is not Channel-1 ");
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+
+	/* Allocate the SKB */
+	skb = alloc_skb(size, GFP_ATOMIC);
+	if (!skb) {
+		FM_CHR_DRV_ERR(" Did not allocate SKB ");
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+
+	/* Forward the data from the user space to ST core */
+	if (copy_from_user(skb_put(skb, size), data, size)) {
+		FM_CHR_DRV_ERR(" Unable to copy from user space");
+		kfree_skb(skb);
+
+		return -EFAULT;
+	}
+#ifdef VERBOSE
+	printk(KERN_INFO "Write: Before conversion\n");
+	for (len = 0; ((skb) && (len < skb->len)); len++)
+		printk(KERN_INFO "0x%02x ", skb->data[len]);
+	printk("\n");
+#endif
+
+	/* Convert the Channel-1 command packet to Channel-8 command packet */
+	if (convert2_channel_8(skb) < 0) {
+		FM_CHR_DRV_ERR(" Conversion to Channel-8 failed ");
+		kfree_skb(skb);
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+#ifdef VERBOSE
+	printk(KERN_INFO "Write: After conversion\n");
+	for (len = 0; ((skb) && (len < skb->len)); len++)
+		printk(KERN_INFO "0x%02x ", skb->data[len]);
+	printk("\n");
+#endif
+
+	/* Write to ST driver through FM_ST interface */
+	err = fm_st_send(skb);
+	if (err < FM_CHR_DRV_SUCCESS) {
+		FM_CHR_DRV_ERR(" Cannot write to ST, fm_st_send failed (%d)",
+			       err);
+		kfree_skb(skb);
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+
+	init_waitqueue_head(&fm_chr_dev->fm_data_q);
+
+	return size;
+}
+
+ssize_t fm_chr_read(struct file *fil, char __user *data, size_t size,
+		    loff_t *offset)
+{
+	int len;
+	struct sk_buff *skb;
+	struct sk_buff *ch4_skb;
+	unsigned long flags = 0;
+
+	FM_CHR_DRV_START();
+
+	skb = NULL;
+	ch4_skb = NULL;
+
+	/* Wait till the data is available */
+	if (!wait_event_interruptible_timeout(fm_chr_dev->fm_data_q,
+					      !skb_queue_empty
+					      (&fm_chr_dev->rx_q), 500)) {
+
+		FM_CHR_DRV_ERR(" Read timed out ");
+
+		return -EAGAIN;
+	}
+	FM_CHR_DRV_VER(" Completed Read wait ");
+
+	spin_lock_irqsave(&fm_chr_dev->lock, flags);
+
+	/* Dequeue the data from the queue if the data
+	 * is already available
+	 */
+	if (!skb_queue_empty(&fm_chr_dev->rx_q))
+		skb = skb_dequeue(&fm_chr_dev->rx_q);
+
+	spin_unlock_irqrestore(&fm_chr_dev->lock, flags);
+
+	if (unlikely
+	    (skb == NULL || skb->len == 0 || skb->data == NULL
+	     || skb->cb[0] != CHAN8_PKT_TYPE)) {
+		FM_CHR_DRV_VER(" Length of the response packet is invalid ");
+		kfree_skb(skb);
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+#ifdef VERBOSE
+	printk(KERN_INFO "Read: Before conversion\n");
+	for (len = 0; len < skb->len; len++)
+		printk(KERN_INFO "0x%02x ", skb->data[len]);
+	printk("\n");
+#endif
+
+	/* Convert if the response packet is of Channel-8 type */
+	if (!skb->data[CHAN8_RESP_CMD_LEN_POS]) {
+		kfree(skb);
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+
+	/* Convert the Channel-8 response packet to Channel-4 response packet */
+	ch4_skb = convert2_channel_4(skb);
+
+	if (ch4_skb == NULL) {
+		FM_CHR_DRV_ERR(" Converted SKB is NULL ");
+		kfree(skb);
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+#ifdef VERBOSE
+	printk(KERN_INFO "Read: After conversion\n");
+	for (len = 0; (ch4_skb != NULL) && len < (ch4_skb->len); len++)
+		printk(KERN_INFO "0x%02x ", ch4_skb->data[len]);
+	printk("\n");
+#endif
+
+	if (size >= ch4_skb->len) {
+		/* Forward the data to the user */
+		if (copy_to_user(data, ch4_skb->data, ch4_skb->len)) {
+			FM_CHR_DRV_ERR(" Unable to copy to user space ");
+			kfree_skb(skb);
+			kfree_skb(ch4_skb);
+			spin_unlock_irqrestore(&fm_chr_dev->lock, flags);
+
+			return -EFAULT;
+		}
+	} else {
+		FM_CHR_DRV_ERR(" Buffer overflow ");
+		kfree_skb(skb);
+		kfree_skb(ch4_skb);
+
+		return -ENOMEM;
+	}
+
+	len = ch4_skb->len;
+	kfree(skb);
+	kfree(ch4_skb);
+
+	/* Clear the pending bit that was set when an interrupt packet had
+	 * arrived
+	 */
+	if (test_bit(SIGNAL_PENDING, &fm_chr_dev->state_flags)
+	    && skb_queue_empty(&fm_chr_dev->rx_q)) {
+		FM_CHR_DRV_DBG(" Sending signal ");
+
+		kill_fasync(&fm_chr_dev->fm_fasync, SIGIO, POLLIN);
+		clear_bit(SIGNAL_PENDING, &fm_chr_dev->state_flags);
+	}
+
+	return len;
+}
+
+unsigned int fm_chr_poll(struct file *file, poll_table * wait)
+{
+	unsigned long mask;
+	unsigned long flags = 0;
+
+	FM_CHR_DRV_DBG(" inside %s", __func__);
+
+	mask = 0;
+
+	/* Poll and wait */
+	poll_wait(file, &fm_chr_dev->fm_data_q, wait);
+
+	spin_lock_irqsave(&fm_chr_dev->lock, flags);
+
+	FM_CHR_DRV_VER(" Completed poll ");
+
+	if (!skb_queue_empty(&fm_chr_dev->rx_q))
+		mask |= POLLIN;
+
+	FM_CHR_DRV_VER(" return 0x%02x\n", (unsigned int)mask);
+
+	spin_unlock_irqrestore(&fm_chr_dev->lock, flags);
+
+	return mask;
+}
+
+int fm_chr_ioctl(struct inode *inode, struct file *file,
+		 unsigned int cmd, unsigned long arg)
+{
+	FM_CHR_DRV_START();
+
+	return FM_CHR_DRV_SUCCESS;
+}
+
+/* FM character driver init: Initializes the FM character driver parametes */
+int fm_chr_init(void)
+{
+	FM_CHR_DRV_START();
+
+	fm_chr_dev = kzalloc(sizeof(struct fm_chrdrv_ops), GFP_ATOMIC);
+
+	if (fm_chr_dev == NULL) {
+		FM_CHR_DRV_ERR
+		    (" Cannot allocate memory for FM character driver ");
+
+		return -ENOMEM;
+	}
+
+	skb_queue_head_init(&fm_chr_dev->rx_q);
+
+	/* Initialize wait queue and a flag, so that the
+	 * wait queue can be used later
+	 */
+	init_completion(&fm_chr_dev->reg_completed);
+	init_waitqueue_head(&fm_chr_dev->fm_data_q);
+
+	/* Expose the device FM_CHAR_DEVICE_NAME to user space
+	 * and obtain the major number for the device
+	 */
+	fm_chr_dev->fm_chr_major =
+	    register_chrdev(0, FM_CHAR_DEVICE_NAME, &fm_chr_ops);
+	FM_CHR_DRV_VER(" allocated %d, %d", fm_chr_dev->fm_chr_major, 0);
+
+	if (fm_chr_dev->fm_chr_major < 0) {
+		FM_CHR_DRV_ERR(" register_chrdev failed ");
+
+		return FM_CHR_DRV_ERR_FAILURE;
+	}
+
+	/* udev */
+	fm_chr_dev->fm_chr_class =
+	    class_create(THIS_MODULE, FM_CHAR_DEVICE_NAME);
+	if (IS_ERR(fm_chr_dev->fm_chr_class)) {
+		FM_CHR_DRV_ERR(" Something went wrong in class_create");
+
+		return FM_CHR_DRV_ERR_CLASS;
+	}
+
+	fm_chr_dev->fm_chr_dev =
+	    device_create(fm_chr_dev->fm_chr_class, NULL,
+			  MKDEV(fm_chr_dev->fm_chr_major, 0), NULL,
+			  FM_CHAR_DEVICE_NAME);
+
+	if (IS_ERR(fm_chr_dev->fm_chr_dev)) {
+		FM_CHR_DRV_ERR(" Cannot create the device %s ",
+			       FM_CHAR_DEVICE_NAME);
+
+		return -ENODEV;
+	}
+
+	return FM_CHR_DRV_SUCCESS;
+}
+
+/* FM character driver init: Destroys the FM character driver parametes */
+void fm_chr_exit(void)
+{
+	FM_CHR_DRV_START();
+
+	FM_CHR_DRV_VER(" Freeing up %d", fm_chr_dev->fm_chr_major);
+
+	skb_queue_purge(&fm_chr_dev->rx_q);
+	device_destroy(fm_chr_dev->fm_chr_class,
+		       MKDEV(fm_chr_dev->fm_chr_major, 0));
+
+	class_unregister(fm_chr_dev->fm_chr_class);
+	class_destroy(fm_chr_dev->fm_chr_class);
+
+	unregister_chrdev(fm_chr_dev->fm_chr_major, FM_CHAR_DEVICE_NAME);
+}
diff --git a/drivers/misc/ti-st/fmdrv_chr.h b/drivers/misc/ti-st/fmdrv_chr.h
new file mode 100644
index 000000000000..9b8cc5a45c57
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_chr.h
@@ -0,0 +1,194 @@
+/*
+ *   FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *   Copyright (C) 2009 Texas Instruments
+ *   Written by Raghavendra Shenoy (x0099675@ti.com)
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License version 2 as
+ *   published by the Free Software Foundation.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _FM_CHR_DRV_H
+#define _FM_CHR_DRV_H
+
+/* #define VERBOSE */
+
+/* Debug macros */
+#define FM_CHR_DRV_ERR(fmt, arg...) \
+	pr_err("(fm_chr_drv):"fmt"\n" , ## arg)
+
+#if defined(DEBUG)	/* limited debug messages */
+#define FM_CHR_DRV_DBG(fmt, arg...) \
+	pr_info("(fm_chr_drv):"fmt"\n" , ## arg)
+#define FM_CHR_DRV_VER(fmt, arg...)
+#define	FM_CHR_DRV_START()	\
+	pr_info("(fm_chr_drv): Inside %s\n", __func__)
+#elif defined(VERBOSE)	/* very verbose */
+#define FM_CHR_DRV_DBG(fmt, arg...) \
+	pr_info("(fm_chr_drv):"fmt"\n" , ## arg)
+#define FM_CHR_DRV_VER(fmt, arg...) \
+	pr_info("(fm_chr_drv):"fmt"\n" , ## arg)
+#define FM_CHR_DRV_START()	\
+	pr_info("(fm_chr_drv): Inside %s\n", __func__)
+#else /* Error msgs only */
+#define FM_CHR_DRV_DBG(fmt, arg...)
+#define FM_CHR_DRV_VER(fmt, arg...)
+#define FM_CHR_DRV_START()
+#endif
+
+/* FM device */
+#define FM_CHAR_DEVICE_NAME	"tifm"
+
+/* Macros for packet conversion */
+#define	CHAN1_FM_PWR_OPCODE		0xFD37
+#define	CHAN1_READ_OPCODE		0xFD33
+#define	CHAN1_WRITE_OPCODE		0xFD35
+
+#define CHAN1_HW_REG_OPCODE		0x64
+#define CHAN8_FM_PWR_OPCODE		0xFE
+#define CHAN8_FM_INTERRUPT		0xFF
+#define CHAN8_FM_INTERRUPT_OPCODE	0xF0
+
+/* Packet types */
+#define CHAN1_PKT_TYPE		0x01
+#define CHAN8_PKT_TYPE		0x08
+#define CHAN4_PKT_TYPE		0x04
+#define CHAN4_CMD_COMPLETE_TYPE	0x0E
+
+#define CHAN8_RD_CMD	0x01
+#define CHAN8_WR_CMD	0x00
+
+#define CHAN8_RD_RESP	0x01
+#define CHAN8_WR_RESP	0x00
+
+/* Channel-4 data sizes */
+#define CHAN4_PKT_TYPE_SIZE	1
+#define CHAN4_EVT_TYPE_SIZE	1
+
+/* Channel-8 data sizes */
+#define CHAN8_OPCODE_SIZE	1
+#define CHAN8_RD_WR_SIZE	1
+#define CHAN8_PARAM_LEN_SIZE	1
+
+/* Channel-8 response data sizes */
+#define CHAN8_RESP_TYPE_SIZE	1
+#define CHAN8_RESP_CMD_LEN_SIZE 1
+
+/* HCI-VS data sizes */
+#define CHAN1_TYPE_SIZE		1
+#define CHAN1_OPCODE_SIZE	2
+#define CHAN1_CMD_LEN_SIZE	1
+
+/* HCI-VS data positions */
+#define CHAN1_TYPE_POS		0
+#define CHAN1_OPCODE_POS	1
+#define CHAN1_CMD_LEN_POS	3
+#define CHAN1_FM_OPCODE_POS	4
+#define CHAN1_PARAM_LEN_POS	5
+
+/* Because of an extra Zero appended to param_len */
+#define CHAN1_PARAM_POS		7
+
+/* Channel-8 command positions */
+#define CHAN8_TYPE_POS		0
+#define CHAN8_CMD_LEN_POS	1
+#define CHAN8_FM_OPCODE_POS	2
+#define CHAN8_RW_POS		3
+#define CHAN8_PARAM_LEN_POS	4
+#define CHAN8_PARAM_POS		5
+
+/* Channel-8 response positions */
+#define CHAN8_RESP_CMD_LEN_POS		1
+#define CHAN8_RESP_STATUS_POS		2
+#define CHAN8_RESP_NUM_HCI_POS		3
+#define CHAN8_RESP_FM_OPCODE_POS	4
+#define CHAN8_RESP_RW_POS		5
+#define CHAN8_RESP_PARAM_LEN_POS	6
+#define CHAN8_RESP_PARAM_POS		7
+
+/* Channel-4 data positions */
+#define CHAN4_TYPE_POS		0
+#define CHAN4_EVT_TYPE_POS	1
+#define CHAN4_PLEN_POS		2
+#define CHAN4_EVT_POS		3
+#define CHAN4_PARAM_POS		6
+
+/* Forward declaration file operations */
+void fm_chr_exit(void);
+int fm_chr_init(void);
+
+int fm_chr_fasync(int, struct file *, int);
+
+int fm_chr_open(struct inode *, struct file *);
+int fm_chr_release(struct inode *, struct file *);
+
+ssize_t fm_chr_write(struct file *, const char __user *, size_t, loff_t *);
+ssize_t fm_chr_read(struct file *, char __user *, size_t, loff_t *);
+unsigned int fm_chr_poll(struct file *, poll_table *);
+
+int fm_chr_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+
+long fm_rx_task(void);
+
+/* List of error codes returned by the FM driver */
+enum {
+	FM_CHR_DRV_ERR_FAILURE = -1,	/* check struct */
+	FM_CHR_DRV_SUCCESS,
+	FM_CHR_DRV_ERR_PENDING = -5,	/* to call reg_complete_cb */
+	FM_CHR_DRV_ERR_ALREADY,	/* already registered */
+	FM_CHR_DRV_ERR_INPROGRESS,
+	FM_CHR_DRV_ERR_NOPROTO,	/* protocol not supported */
+	FM_CHR_DRV_ERR_CLASS = -15,
+	FM_CHR_DRV_READ_TIMEOUT,
+};
+
+/* Header structure for HCI command packet */
+struct hci_command_hdr {
+	uint8_t prefix;
+	uint16_t opcode;
+	uint8_t plen;
+} __attribute__ ((packed));
+
+/* Header structure for HCI event packet */
+struct evt_cmd_complete {
+	uint8_t ncmd;
+	uint16_t opcode;
+} __attribute__ ((packed));
+
+/* Flag to send the signal after the command complete
+ * event's skb is removed from the RX queue
+ */
+#define SIGNAL_PENDING	1
+
+/* FM Character driver data */
+struct fm_chrdrv_ops {
+	int fm_chr_major;
+	struct device *fm_chr_dev;
+	struct class *fm_chr_class;
+
+	spinlock_t lock;
+
+	unsigned long state_flags;
+
+	struct sk_buff_head rx_q;
+	struct tasklet_struct rx_task;
+
+	wait_queue_head_t fm_data_q;
+	struct completion reg_completed;
+
+	struct fasync_struct *fm_fasync;
+
+	long (*st_write) (struct sk_buff *);
+};
+
+#endif /*_FM_CHR_DRV_H */
diff --git a/drivers/misc/ti-st/fmdrv_core.c b/drivers/misc/ti-st/fmdrv_core.c
new file mode 100644
index 000000000000..cd4da20cadbe
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_core.c
@@ -0,0 +1,3715 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  This sub-module of FM driver does,
+ *  1) Forming group of Channel-8 commands to perform particular
+ *     functionality (ex., frequency set require more than
+ *     one Channel-8 command to be sent to the chip).
+ *  2) Sending each Channel-8 command to the chip and reading
+ *     response back over Shared Transport.
+ *  3) Managing TX and RX Queues and Tasklets
+ *  4) Handling FM Interrupt packet and taking appropriate action.
+ *  5) Loading FM firmware to the chip (common, TX, and RX
+ *     firmware files based on mode selection)
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/firmware.h>
+#include <linux/delay.h>
+#include "fmdrv.h"
+#include "fmdrv_v4l2.h"
+#include "fmdrv_core.h"
+#include "fmdrv_st.h"
+#include "fmdrv_mixer.h"
+#include "fmdrv_chr.h"
+
+/* -- FM chip register table -- */
+static struct fm_reg_table fm_reg_info[] = {
+	/* ----- FM RX registers -------*/
+	/* opcode, type(rd/wr), reg name */
+	{0x00, REG_RD, "STEREO_GET"},
+	{0x01, REG_RD, "RSSI_LVL_GET"},
+	{0x02, REG_RD, "IF_COUNT_GET"},
+	{0x03, REG_RD, "FLAG_GET"},
+	{0x04, REG_RD, "RDS_SYNC_GET"},
+	{0x05, REG_RD, "RDS_DATA_GET"},
+	{0x0a, REG_WR, "FREQ_SET"},
+	{0x0a, REG_RD, "FREQ_GET"},
+	{0x0b, REG_WR, "AF_FREQ_SET"},
+	{0x0b, REG_RD, "AF_FREQ_GET"},
+	{0x0c, REG_WR, "MOST_MODE_SET"},
+	{0x0c, REG_RD, "MOST_MODE_GET"},
+	{0x0d, REG_WR, "MOST_BLEND_SET"},
+	{0x0d, REG_RD, "MOST_BLEND_GET"},
+	{0x0e, REG_WR, "DEMPH_MODE_SET"},
+	{0x0e, REG_RD, "DEMPH_MODE_GET"},
+	{0x0f, REG_WR, "SEARCH_LVL_SET"},
+	{0x0f, REG_RD, "SEARCH_LVL_GET"},
+	{0x10, REG_WR, "RX_BAND_SET"},
+	{0x10, REG_RD, "RX_BAND_GET"},
+	{0x11, REG_WR, "MUTE_STATUS_SET"},
+	{0x11, REG_RD, "MUTE_STATUS_GET"},
+	{0x12, REG_WR, "RDS_PAUSE_LVL_SET"},
+	{0x12, REG_RD, "RDS_PAUSE_LVL_GET"},
+	{0x13, REG_WR, "RDS_PAUSE_DUR_SET"},
+	{0x13, REG_RD, "RDS_PAUSE_DUR_GET"},
+	{0x14, REG_WR, "RDS_MEM_SET"},
+	{0x14, REG_RD, "RDS_MEM_GET"},
+	{0x15, REG_WR, "RDS_BLK_B_SET"},
+	{0x15, REG_RD, "RDS_BLK_B_GET"},
+	{0x16, REG_WR, "RDS_MSK_B_SET"},
+	{0x16, REG_RD, "RDS_MSK_B_GET"},
+	{0x17, REG_WR, "RDS_PI_MASK_SET"},
+	{0x17, REG_RD, "RDS_PI_MASK_GET"},
+	{0x18, REG_WR, "RDS_PI_SET"},
+	{0x18, REG_RD, "RDS_PI_GET"},
+	{0x19, REG_WR, "RDS_SYSTEM_SET"},
+	{0x19, REG_RD, "RDS_SYSTEM_GET"},
+	{0x1a, REG_WR, "INT_MASK_SET"},
+	{0x1a, REG_RD, "INT_MASK_GET"},
+	{0x1b, REG_WR, "SRCH_DIR_SET"},
+	{0x1b, REG_RD, "SRCH_DIR_GET"},
+	{0x1c, REG_WR, "VOLUME_SET"},
+	{0x1c, REG_RD, "VOLUME_GET"},
+	{0x1d, REG_WR, "AUDIO_ENABLE(SET)"},
+	{0x1d, REG_RD, "AUDIO_ENABLE(GET)"},
+	{0x1e, REG_WR, "PCM_MODE_SET"},
+	{0x1e, REG_RD, "PCM_MODE_SET"},
+	{0x1f, REG_WR, "I2S_MD_CFG_SET"},
+	{0x1f, REG_RD, "I2S_MD_CFG_GET"},
+	{0x20, REG_WR, "POWER_SET"},
+	{0x20, REG_RD, "POWER_GET"},
+	{0x21, REG_WR, "INTx_CONFIG_SET"},
+	{0x21, REG_RD, "INTx_CONFIG_GET"},
+	{0x22, REG_WR, "PULL_EN_SET"},
+	{0x22, REG_RD, "PULL_EN_GET"},
+	{0x23, REG_WR, "HILO_SET"},
+	{0x23, REG_RD, "HILO_GET"},
+	{0x24, REG_WR, "SWITCH2FREF"},
+	{0x25, REG_WR, "FREQ_DRIFT_REP"},
+	{0x28, REG_RD, "PCE_GET"},
+	{0x29, REG_RD, "FIRM_VER_GET"},
+	{0x2a, REG_RD, "ASIC_VER_GET"},
+	{0x2b, REG_RD, "ASIC_ID_GET"},
+	{0x2c, REG_RD, "MAIN_ID_GET"},
+	{0x2d, REG_WR, "TUNER_MODE_SET"},
+	{0x2e, REG_WR, "STOP_SEARCH"},
+	{0x2f, REG_WR, "RDS_CNTRL_SET"},
+	{0x64, REG_WR, "WR_HW_REG"},
+	{0x65, REG_WR, "CODE_DOWNLOAD"},
+	{0x66, REG_WR, "RESET"},
+	{0xfe, REG_WR, "FM_POWER_MODE(SET)"},
+	{0xff, REG_RD, "FM_INTERRUPT"},
+
+	/* --- FM TX registers ------ */
+	{0x37, REG_WR, "CHANL_SET"},
+	{0x37, REG_RD, "CHANL_GET"},
+	{0x38, REG_WR, "CHANL_BW_SET"},
+	{0x38, REG_RD, "CHANL_BW_GET"},
+	{0x87, REG_WR, "REF_SET"},
+	{0x87, REG_RD, "REF_GET"},
+	{0x5a, REG_WR, "POWER_ENB_SET"},
+	{0x3a, REG_WR, "POWER_ATT_SET"},
+	{0x3a, REG_RD, "POWER_ATT_GET"},
+	{0x3b, REG_WR, "POWER_LEL_SET"},
+	{0x3b, REG_RD, "POWER_LEL_GET"},
+	{0x3c, REG_WR, "AUDIO_DEV_SET"},
+	{0x3c, REG_RD, "AUDIO_DEV_GET"},
+	{0x3d, REG_WR, "PILOT_DEV_SET"},
+	{0x3d, REG_RD, "PILOT_DEV_GET"},
+	{0x3e, REG_WR, "RDS_DEV_SET"},
+	{0x3e, REG_RD, "RDS_DEV_GET"},
+	{0x5b, REG_WR, "PUPD_SET"},
+	{0x3f, REG_WR, "AUDIO_IO_SET"},
+	{0x40, REG_WR, "PREMPH_SET"},
+	{0x40, REG_RD, "PREMPH_GET"},
+	{0x41, REG_WR, "TX_BAND_SET"},
+	{0x41, REG_RD, "TX_BAND_GET"},
+	{0x42, REG_WR, "MONO_SET"},
+	{0x42, REG_RD, "MONO_GET"},
+	{0x5C, REG_WR, "MUTE"},
+	{0x43, REG_WR, "MPX_LMT_ENABLE"},
+	{0x06, REG_RD, "LOCK_GET"},
+	{0x5d, REG_WR, "REF_ERR_SET"},
+	{0x44, REG_WR, "PI_SET"},
+	{0x44, REG_RD, "PI_GET"},
+	{0x45, REG_WR, "TYPE_SET"},
+	{0x45, REG_RD, "TYPE_GET"},
+	{0x46, REG_WR, "PTY_SET"},
+	{0x46, REG_RD, "PTY_GET"},
+	{0x47, REG_WR, "AF_SET"},
+	{0x47, REG_RD, "AF_GET"},
+	{0x48, REG_WR, "DISPLAY_SIZE_SET"},
+	{0x48, REG_RD, "DISPLAY_SIZE_GET"},
+	{0x49, REG_WR, "RDS_MODE_SET"},
+	{0x49, REG_RD, "RDS_MODE_GET"},
+	{0x4a, REG_WR, "DISPLAY_MODE_SET"},
+	{0x4a, REG_RD, "DISPLAY_MODE_GET"},
+	{0x62, REG_WR, "LENGHT_SET"},
+	{0x4b, REG_RD, "LENGHT_GET"},
+	{0x4c, REG_WR, "TOGGLE_AB_SET"},
+	{0x4c, REG_RD, "TOGGLE_AB_GET"},
+	{0x4d, REG_WR, "RDS_REP_SET"},
+	{0x4d, REG_RD, "RDS_REP_GET"},
+	{0x63, REG_WR, "RDS_DATA_SET"},
+	{0x5e, REG_WR, "RDS_DATA_ENB"},
+	{0x4e, REG_WR, "TA_SET"},
+	{0x4e, REG_RD, "TA_GET"},
+	{0x4f, REG_WR, "TP_SET"},
+	{0x4f, REG_RD, "TP_GET"},
+	{0x50, REG_WR, "DI_SET"},
+	{0x50, REG_RD, "DI_GET"},
+	{0x51, REG_WR, "MS_SET"},
+	{0x51, REG_RD, "MS_GET"},
+	{0x52, REG_WR, "PS_SCROLL_SPEED_SET"},
+	{0x52, REG_RD, "PS_SCROLL_SPEED_GET"},
+};
+
+/* Region info */
+static struct region_info region_configs[] = {
+	/* Europe/US */
+	{
+	 .channel_spacing = 50,	/* 50 KHz */
+	 .bottom_frequency = 87500,	/* 87.5 MHz */
+	 .top_frequency = 108000,	/* 108 MHz */
+	 .region_index = 0,
+	 },
+	/* Japan */
+	{
+	 .channel_spacing = 50,	/* 50 KHz */
+	 .bottom_frequency = 76000,	/* 76 MHz */
+	 .top_frequency = 90000,	/* 90 MHz */
+	 .region_index = 1,
+	 },
+};
+
+/* Band selection */
+static unsigned char default_radio_region;	/* Europe/US */
+module_param(default_radio_region, byte, 0);
+MODULE_PARM_DESC(default_radio_region, "Region: 0=Europe/US, 1=Japan");
+
+/* RDS buffer blocks */
+static unsigned int default_rds_buf = 300;
+module_param(default_rds_buf, uint, 0444);
+MODULE_PARM_DESC(rds_buf, "RDS buffer entries");
+
+/* FM irq handlers forward declaration */
+static void fm_core_irq_send_flag_getcmd(void);
+static void fm_core_irq_handle_flag_getcmd_resp(void);
+static void fm_core_irq_handle_hw_malfunction(void);
+static void fm_core_irq_handle_rds_start(void);
+static void fm_core_irq_send_rdsdata_getcmd(void);
+static void fm_core_irq_handle_rdsdata_getcmd_resp(void);
+static void fm_core_irq_handle_rds_finish(void);
+static void fm_core_irq_handle_tune_op_ended(void);
+static void fm_core_irq_handle_power_enb(void);
+static void fm_core_irq_handle_low_rssi_start(void);
+static void fm_core_irq_afjump_set_pi(void);
+static void fm_core_irq_handle_set_pi_resp(void);
+static void fm_core_irq_afjump_set_pimask(void);
+static void fm_core_irq_handle_set_pimask_resp(void);
+static void fm_core_irq_afjump_setfreq(void);
+static void fm_core_irq_handle_setfreq_resp(void);
+static void fm_core_irq_afjump_enableint(void);
+static void fm_core_irq_afjump_enableint_resp(void);
+static void fm_core_irq_start_afjump(void);
+static void fm_core_irq_handle_start_afjump_resp(void);
+static void fm_core_irq_afjump_rd_freq(void);
+static void fm_core_irq_afjump_rd_freq_resp(void);
+static void fm_core_irq_handle_low_rssi_finish(void);
+static void fm_core_irq_send_intmsk_cmd(void);
+static void fm_core_irq_handle_intmsk_cmd_resp(void);
+
+/* When FM core receives interrupt packet , following handlers
+ * will be executed one after another to service the interrupt(s) */
+
+/* Interrupt handler index */
+enum fm_irq_handler_index{
+
+	FM_SEND_FLAG_GETCMD_INDEX,
+	FM_HANDLE_FLAG_GETCMD_RESP_INDEX,
+
+	/* HW malfunction irq handler */
+	FM_HW_MAL_FUNC_INDEX,
+
+	/* RDS threshold reached irq handler */
+	FM_RDS_START_INDEX,
+	FM_RDS_SEND_RDS_GETCMD_INDEX,
+	FM_RDS_HANDLE_RDS_GETCMD_RESP_INDEX,
+	FM_RDS_FINISH_INDEX,
+
+	/* Tune operation ended irq handler */
+	FM_HW_TUNE_OP_ENDED_INDEX,
+
+	/* TX power enable irq handler */
+	FM_HW_POWER_ENB_INDEX,
+
+	/* Low RSSI irq handler */
+	FM_LOW_RSSI_START_INDEX,
+	FM_AF_JUMP_SETPI_INDEX,
+	FM_AF_JUMP_HANDLE_SETPI_RESP_INDEX,
+	FM_AF_JUMP_SETPI_MASK_INDEX,
+	FM_AF_JUMP_HANDLE_SETPI_MASK_RESP_INDEX,
+	FM_AF_JUMP_SET_AF_FREQ_INDEX,
+	FM_AF_JUMP_HENDLE_SET_AFFREQ_RESP_INDEX,
+	FM_AF_JUMP_ENABLE_INT_INDEX,
+	FM_AF_JUMP_ENABLE_INT_RESP_INDEX,
+	FM_AF_JUMP_START_AFJUMP_INDEX,
+	FM_AF_JUMP_HANDLE_START_AFJUMP_RESP_INDEX,
+	FM_AF_JUMP_RD_FREQ_INDEX,
+	FM_AF_JUMP_RD_FREQ_RESP_INDEX,
+	FM_LOW_RSSI_FINISH_INDEX,
+
+	/* Interrupt process post action */
+	FM_SEND_INTMSK_CMD_INDEX,
+	FM_HANDLE_INTMSK_CMD_RESP_INDEX,
+};
+
+/* FM interrupt handler table */
+static Int_Handler_ProtoType g_IntHandlerTable[] = {
+	fm_core_irq_send_flag_getcmd,
+	fm_core_irq_handle_flag_getcmd_resp,
+
+	/* HW malfunction irq handler */
+	fm_core_irq_handle_hw_malfunction,
+
+	/* RDS threshold reached irq handler */
+	fm_core_irq_handle_rds_start,
+	fm_core_irq_send_rdsdata_getcmd,
+	fm_core_irq_handle_rdsdata_getcmd_resp,
+	fm_core_irq_handle_rds_finish,
+
+	/* Tune operation ended irq handler */
+	fm_core_irq_handle_tune_op_ended,
+
+	/* TX power enable irq handler */
+	fm_core_irq_handle_power_enb,
+
+	/* Low RSSI irq handler */
+	fm_core_irq_handle_low_rssi_start,
+	fm_core_irq_afjump_set_pi,
+	fm_core_irq_handle_set_pi_resp,
+	fm_core_irq_afjump_set_pimask,
+	fm_core_irq_handle_set_pimask_resp,
+	fm_core_irq_afjump_setfreq,
+	fm_core_irq_handle_setfreq_resp,
+	fm_core_irq_afjump_enableint,
+	fm_core_irq_afjump_enableint_resp,
+	fm_core_irq_start_afjump,
+	fm_core_irq_handle_start_afjump_resp,
+	fm_core_irq_afjump_rd_freq,
+	fm_core_irq_afjump_rd_freq_resp,
+	fm_core_irq_handle_low_rssi_finish,
+
+	/* Interrupt process post action */
+	fm_core_irq_send_intmsk_cmd,
+	fm_core_irq_handle_intmsk_cmd_resp
+};
+
+static struct fmdrv_ops *fmdev;
+
+#ifdef FM_DUMP_TXRX_PKT
+
+ /* To dump outgoing FM Channel-8 packets */
+inline void dump_tx_skb_data(struct sk_buff *skb)
+{
+	int len, len_org;
+	char index;
+	struct fm_cmd_msg_hdr *cmd_hdr;
+
+	cmd_hdr = (struct fm_cmd_msg_hdr *)skb->data;
+	printk(KERN_INFO "<<%shdr:%02x len:%02x opcode:%02x type:%s dlen:%02x",
+	       fm_cb(skb)->completion ? " " : "*", cmd_hdr->header,
+	       cmd_hdr->len, cmd_hdr->fm_opcode,
+	       cmd_hdr->rd_wr ? "RD" : "WR", cmd_hdr->dlen);
+
+	len_org = skb->len - FM_CMD_MSG_HDR_SIZE;
+	if (len_org > 0) {
+		printk("\n   data(%d): ", cmd_hdr->dlen);
+		len = min(len_org, 14);
+		for (index = 0; index < len; index++)
+			printk("%x ",
+			       skb->data[FM_CMD_MSG_HDR_SIZE + index]);
+		printk("%s", (len_org > 14) ? ".." : "");
+	}
+	printk("\n");
+}
+
+ /* To dump incoming FM Channel-8 packets */
+inline void dump_rx_skb_data(struct sk_buff *skb)
+{
+	int len, len_org;
+	char index;
+	struct fm_event_msg_hdr *evt_hdr;
+
+	evt_hdr = (struct fm_event_msg_hdr *)skb->data;
+	printk(KERN_INFO ">> hdr:%02x len:%02x sts:%02x numhci:%02x "
+	    "opcode:%02x type:%s dlen:%02x", evt_hdr->header, evt_hdr->len,
+	    evt_hdr->status, evt_hdr->num_fm_hci_cmds, evt_hdr->fm_opcode,
+	    (evt_hdr->rd_wr) ? "RD" : "WR", evt_hdr->dlen);
+
+	len_org = skb->len - FM_EVT_MSG_HDR_SIZE;
+	if (len_org > 0) {
+		printk("\n   data(%d): ", evt_hdr->dlen);
+		len = min(len_org, 14);
+		for (index = 0; index < len; index++)
+			printk("%x ",
+			       skb->data[FM_EVT_MSG_HDR_SIZE + index]);
+		printk("%s", (len_org > 14) ? ".." : "");
+	}
+	printk("\n");
+}
+#endif
+
+/* Queues FM Channel-8 packet to FM TX queue and schedules FM TX tasklet for
+ * transmission */
+static int __fm_core_send_cmd(unsigned char fmreg_index, void *payload,
+			      int payload_len,
+			      struct completion *wait_completion)
+{
+	struct sk_buff *skb;
+	struct fm_cmd_msg_hdr *cmd_hdr;
+	int size;
+
+	FMDRV_API_START();
+
+	if (fmreg_index >= FM_REG_MAX_ENTRIES) {
+		FM_DRV_ERR("Invalid fm register index");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	if (test_bit(FM_FIRMWARE_DW_INPROGRESS, &fmdev->flag) &&
+			payload == NULL) {
+		FM_DRV_ERR("Payload data is NULL during firmware download");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	if (!test_bit(FM_FIRMWARE_DW_INPROGRESS, &fmdev->flag))
+		size =
+		    FM_CMD_MSG_HDR_SIZE + ((payload == NULL) ? 0 : payload_len);
+	else
+		size = payload_len;
+
+	/* Allocate memory for new packet */
+	skb = alloc_skb(size, GFP_ATOMIC);
+	if (!skb) {
+		FM_DRV_ERR("No memory to create new SKB");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	/* Don't fill FM header info for the commands which come from
+	 * FM firmware file */
+	if (!test_bit(FM_FIRMWARE_DW_INPROGRESS, &fmdev->flag) ||
+	    test_bit(FM_INTTASK_RUNNING, &fmdev->flag)) {
+		/* Fill command header info */
+		cmd_hdr =
+		    (struct fm_cmd_msg_hdr *)skb_put(skb, FM_CMD_MSG_HDR_SIZE);
+		cmd_hdr->header = FM_PKT_LOGICAL_CHAN_NUMBER;	/* 0x08 */
+		/* 3 (fm_opcode,rd_wr,dlen) + payload len) */
+		cmd_hdr->len = ((payload == NULL) ? 0 : payload_len) + 3;
+		/* FM opcode */
+		cmd_hdr->fm_opcode = fm_reg_info[fmreg_index].opcode;
+		/* read/write type */
+		cmd_hdr->rd_wr = fm_reg_info[fmreg_index].type;
+		cmd_hdr->dlen = payload_len;
+		fm_cb(skb)->fm_opcode = fm_reg_info[fmreg_index].opcode;
+	} else if (payload != NULL) {
+		fm_cb(skb)->fm_opcode = *((char *)payload + 2);
+	}
+	/* Fill payload data */
+	if (payload != NULL)
+		memcpy(skb_put(skb, payload_len), payload, payload_len);
+
+	/* Fill completion handler TX tasklet needs
+	 * this info before sending packet to TX Q */
+	fm_cb(skb)->completion = wait_completion;
+
+	/* Add this new packet to TX Q and schedule TX tasklet */
+	skb_queue_tail(&fmdev->tx_q, skb);
+	tasklet_schedule(&fmdev->tx_task);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Sends FM Channel-8 command to the chip and waits for the reponse */
+int fm_core_send_cmd(unsigned char fmreg_index, void *payload, int payload_len,
+		     struct completion *wait_completion, void *reponse,
+		     int *reponse_len)
+{
+	struct sk_buff *skb;
+	struct fm_event_msg_hdr *fm_evt_hdr;
+	unsigned long timeleft;
+	unsigned long flags;
+	int ret;
+
+	FMDRV_API_START();
+
+	init_completion(wait_completion);
+	ret = __fm_core_send_cmd(fmreg_index, payload, payload_len,
+				 wait_completion);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Wait for the reponse from the chip */
+	timeleft = wait_for_completion_timeout(wait_completion,
+					       FM_DRV_TX_TIMEOUT);
+	if (!timeleft) {
+		FM_DRV_ERR("Timeout(%d sec),didn't get reg"
+			   "completion signal from RX tasklet",
+			   jiffies_to_msecs(FM_DRV_TX_TIMEOUT) / 1000);
+		FMDRV_API_EXIT(-ETIMEDOUT);
+		return -ETIMEDOUT;
+	}
+	if (!fmdev->response_skb) {
+		FM_DRV_ERR("Reponse SKB is missing ");
+		FMDRV_API_EXIT(-EFAULT);
+		return -EFAULT;
+	}
+	spin_lock_irqsave(&fmdev->resp_skb_lock, flags);
+	skb = fmdev->response_skb;
+	fmdev->response_skb = NULL;
+	spin_unlock_irqrestore(&fmdev->resp_skb_lock, flags);
+
+	fm_evt_hdr = (void *)skb->data;
+	if (fm_evt_hdr->status != 0) {
+		FM_DRV_ERR("Received event pkt status(%d) is not zero",
+			   fm_evt_hdr->status);
+		kfree_skb(skb);
+		FMDRV_API_EXIT(-EIO);
+		return -EIO;
+	}
+	/* Send reponse data to caller */
+	if (reponse != NULL && reponse_len != NULL && fm_evt_hdr->dlen) {
+		/* Skip header info and copy only response data */
+		skb_pull(skb, sizeof(struct fm_event_msg_hdr));
+		memcpy(reponse, skb->data, fm_evt_hdr->dlen);
+		*reponse_len = fm_evt_hdr->dlen;
+	} else if (reponse_len != NULL && fm_evt_hdr->dlen == 0) {
+		*reponse_len = 0;
+	}
+	kfree_skb(skb);
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Resets RDS cache parameters */
+static inline void fm_core_rx_reset_rds_cache(void)
+{
+	FMDRV_API_START();
+
+	fmdev->rx.rds.flag = FM_RX_RDS_DISABLE;
+	fmdev->rx.rds.last_block_index = 0;
+	fmdev->rx.rds.wr_index = 0;
+	fmdev->rx.rds.rd_index = 0;
+
+	if (fmdev->rx.af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON)
+		fmdev->irq_info.mask |= FM_LEV_EVENT;
+
+	FMDRV_API_EXIT(0);
+}
+
+/* Resets current station info */
+static inline void fm_core_rx_reset_curr_station_info(void)
+{
+	FMDRV_API_START();
+
+	fmdev->rx.cur_station_info.picode = FM_NO_PI_CODE;
+	fmdev->rx.cur_station_info.no_of_items_in_afcache = 0;
+	fmdev->rx.cur_station_info.af_list_max = 0;
+
+	FMDRV_API_EXIT(0);
+}
+
+/* --- Helper functions used in FM interrupt handlers ---*/
+
+static inline char fm_core_check_cmdresp_status(struct sk_buff **skb)
+{
+	struct fm_event_msg_hdr *fm_evt_hdr;
+	unsigned long flags;
+
+	FMDRV_API_START();
+
+	spin_lock_irqsave(&fmdev->resp_skb_lock, flags);
+	*skb = fmdev->response_skb;
+	fmdev->response_skb = NULL;
+	spin_unlock_irqrestore(&fmdev->resp_skb_lock, flags);
+
+	fm_evt_hdr = (void *)(*skb)->data;
+	if (fm_evt_hdr->status != 0) {
+		FM_DRV_ERR("irq : opcode %x response status field is not zero",
+			   fm_evt_hdr->fm_opcode);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return FM_ST_FAILED;
+	}
+
+	FMDRV_API_EXIT(FM_ST_SUCCESS);
+	return FM_ST_SUCCESS;
+}
+
+/* Interrupt process timeout handler */
+static void fm_core_int_timeout_handler(unsigned long data)
+{
+	FMDRV_API_START();
+
+	FM_DRV_DBG("irq : timeout,trying to re-enable fm interrupts");
+	fmdev->irq_info.irq_service_timeout_retry++;
+
+	/* One of the irq handler did not get proper response from the chip.
+	 * So take recovery action here. FM interrupts are disabled in the
+	 * beginning of interrupt process. Therefore reset stage index to
+	 * re-enable default interrupts. So that next interrupt will be
+	 * processed as usual.
+	 */
+	if (fmdev->irq_info.irq_service_timeout_retry <=
+	    FM_IRQ_TIMEOUT_RETRY_MAX) {
+		fmdev->irq_info.stage_index = FM_SEND_INTMSK_CMD_INDEX;
+		fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+							 stage_index] ();
+	} else {
+		/* Retry count reached maximum limit.
+		 * Stop recovery action (interrupt
+		 * reenable process) and reset stage
+		 * index & retry count values
+		 */
+		fmdev->irq_info.stage_index = 0;
+		fmdev->irq_info.irq_service_timeout_retry = 0;
+		FM_DRV_ERR("Recovery action failed during \
+		    irq processing,max retry reached");
+	}
+	FMDRV_API_EXIT(0);
+}
+
+/* --------- FM interrupt handlers ------------*/
+
+static void fm_core_irq_send_flag_getcmd(void)
+{
+	unsigned short flag;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Send FLAG_GET command , to know the source of interrupt */
+	ret = __fm_core_send_cmd(FLAG_GET, NULL, sizeof(flag), NULL);
+	if (ret) {
+		/* Failed to send the cmd , Don't update the stage index &
+		 * Trigger the timer to take recovery action */
+		FM_DRV_ERR("irq : failed to send flag_get command,"
+			   "initiating irq recovery process");
+	} else
+		fmdev->irq_info.stage_index = FM_HANDLE_FLAG_GETCMD_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_flag_getcmd_resp(void)
+{
+	struct sk_buff *skb;
+	struct fm_event_msg_hdr *fm_evt_hdr;
+	char ret;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	}
+	fm_evt_hdr = (void *)skb->data;
+
+	/* Skip header info and copy only response data */
+	skb_pull(skb, sizeof(struct fm_event_msg_hdr));
+	memcpy(&fmdev->irq_info.flag, skb->data, fm_evt_hdr->dlen);
+
+	FM_STORE_BE16_TO_LE16(fmdev->irq_info.flag, fmdev->irq_info.flag);
+	FM_DRV_DBG("irq : flag register(0x%x)", fmdev->irq_info.flag);
+
+	/* Continue next function in interrupt handler table */
+	fmdev->irq_info.stage_index = FM_HW_MAL_FUNC_INDEX;
+
+	FMDRV_API_EXIT(0);
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+}
+
+static void fm_core_irq_handle_hw_malfunction(void)
+{
+	FMDRV_API_START();
+
+	if (fmdev->irq_info.flag & FM_MAL_EVENT & fmdev->irq_info.mask)
+		FM_DRV_ERR("irq : Hw MAL interrupt received - do nothing");
+
+	/* Continue next function in interrupt handler table */
+	fmdev->irq_info.stage_index = FM_RDS_START_INDEX;
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_rds_start(void)
+{
+	FMDRV_API_START();
+
+	if (fmdev->irq_info.flag & FM_RDS_EVENT & fmdev->irq_info.mask) {
+		FM_DRV_DBG("irq : rds threshold reached");
+		fmdev->irq_info.stage_index = FM_RDS_SEND_RDS_GETCMD_INDEX;
+	} else {
+		/* Continue next function in interrupt handler table */
+		fmdev->irq_info.stage_index = FM_HW_TUNE_OP_ENDED_INDEX;
+	}
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_send_rdsdata_getcmd(void)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Send the command to read RDS data from the chip */
+	ret = __fm_core_send_cmd(RDS_DATA_GET, NULL,
+				 (FM_RX_RDS_FIFO_THRESHOLD * 3), NULL);
+	if (ret)
+		FM_DRV_ERR("irq : failed to send rds get commandm,"
+			   "initiating irq recovery process");
+	else
+		fmdev->irq_info.stage_index =
+		    FM_RDS_HANDLE_RDS_GETCMD_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+/* Keeps track of current RX channel AF (Alternate Frequency) */
+static void __fm_core_rx_update_af_cache(unsigned char af)
+{
+	unsigned char index;
+	unsigned int freq;
+	FMDRV_API_START();
+
+	/* First AF indicates the number of AF follows. Reset the list */
+	if ((af >= FM_RDS_1_AF_FOLLOWS) && (af <= FM_RDS_25_AF_FOLLOWS)) {
+		fmdev->rx.cur_station_info.af_list_max =
+		    (af - FM_RDS_1_AF_FOLLOWS + 1);
+		fmdev->rx.cur_station_info.no_of_items_in_afcache = 0;
+		FM_DRV_DBG("No of expected AF : %d",
+			   fmdev->rx.cur_station_info.af_list_max);
+	} else if (((af >= FM_RDS_MIN_AF)
+		    && (fmdev->rx.region.region_index == FM_BAND_EUROPE_US)
+		    && (af <= FM_RDS_MAX_AF)) || ((af >= FM_RDS_MIN_AF)
+						  && (fmdev->rx.region.
+						      region_index ==
+						      FM_BAND_JAPAN)
+						  && (af <=
+						      FM_RDS_MAX_AF_JAPAN))) {
+		freq = fmdev->rx.region.bottom_frequency + (af * 100);
+		/* If the AF is the same
+		 * as the tuned station frequency - ignore it
+		 */
+		if (freq == fmdev->rx.curr_freq) {
+			FM_DRV_DBG("Current frequency(%d) is \
+			    matching with received AF(%d)",
+			    fmdev->rx.curr_freq, freq);
+			return;
+		}
+		/* Do check in AF cache */
+		for (index = 0;
+		     index < fmdev->rx.cur_station_info.no_of_items_in_afcache;
+		     index++) {
+			if (fmdev->rx.cur_station_info.af_cache[index] == freq)
+				break;
+		}
+		/* Reached the limit of the list - ignore the next AF */
+		if (index == fmdev->rx.cur_station_info.af_list_max) {
+			FM_DRV_DBG("AF cache is full");
+			return;
+		}
+
+		/* If we reached the end of the list then
+		 * this AF is not in the list - add it
+		 */
+		if (index == fmdev->rx.cur_station_info.
+				   no_of_items_in_afcache) {
+			FM_DRV_DBG("Storing AF %d into AF cache index %d", freq,
+				   index);
+			fmdev->rx.cur_station_info.af_cache[index] = freq;
+			fmdev->rx.cur_station_info.no_of_items_in_afcache++;
+		}
+	}
+	FMDRV_API_EXIT(0);
+}
+
+/* Converts RDS buffer data from big endian format
+ * to little endian format
+ */
+static void __fm_core_rdsparse_swapbytes(struct fm_rdsdata_format *rds_format)
+{
+	unsigned char byte1;
+	unsigned char index = 0;
+	char *rds_buff;
+
+	FMDRV_API_START();
+
+	/* Since in Orca the 2 RDS Data bytes are in little endian and
+	 * in Dolphin they are in big endian, the parsing of the RDS data
+	 * is chip dependent */
+	if (fmdev->asci_id != 0x6350) {
+		rds_buff = &rds_format->rdsData.groupDataBuff.rdsBuff[0];
+		while (index + 1 < FM_RX_RDS_INFO_FIELD_MAX) {
+			byte1 = rds_buff[index];
+			rds_buff[index] = rds_buff[index + 1];
+			rds_buff[index + 1] = byte1;
+			index += 2;
+		}
+	}
+
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_rdsdata_getcmd_resp(void)
+{
+	struct sk_buff *skb;
+	char *rds_data;
+	char metaData;
+	unsigned char type, block_index;
+	unsigned long group_index;
+	struct fm_rdsdata_format rds_format;
+	int rds_len, ret;
+	unsigned short cur_picode;
+	unsigned char tmpbuf[3];
+	unsigned long flags;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	}
+	/* Skip header info */
+	skb_pull(skb, sizeof(struct fm_event_msg_hdr));
+	rds_data = skb->data;
+	rds_len = skb->len;
+
+	/* Parse the RDS data */
+	while (rds_len >= FM_RDS_BLOCK_SIZE) {
+		metaData = rds_data[2];
+		/* Get the type:
+		 * 0=A, 1=B, 2=C, 3=C', 4=D, 5=E */
+		type = (metaData & 0x07);
+
+		/* Transform the block type
+		 * into an index sequence (0, 1, 2, 3, 4) */
+		block_index = (type <= FM_RDS_BLOCK_C ? type : (type - 1));
+		FM_DRV_DBG("Block index:%d(%s) ", block_index,
+			   (metaData & FM_RDS_STATUS_ERROR_MASK) ? "Bad" :
+			   "Ok");
+		if (((metaData & FM_RDS_STATUS_ERROR_MASK) == 0)
+		    && (block_index == FM_RDS_BLOCK_INDEX_A
+			|| (block_index == fmdev->rx.rds.last_block_index + 1
+			    && block_index <= FM_RDS_BLOCK_INDEX_D))) {
+			/* Skip checkword (control) byte
+			 * and copy only data byte */
+			memcpy(&rds_format.rdsData.groupDataBuff.
+			       rdsBuff[block_index * (FM_RDS_BLOCK_SIZE - 1)],
+			       rds_data, (FM_RDS_BLOCK_SIZE - 1));
+			fmdev->rx.rds.last_block_index = block_index;
+
+			/* If completed a whole group then handle it */
+			if (block_index == FM_RDS_BLOCK_INDEX_D) {
+				FM_DRV_DBG("Good block received");
+				__fm_core_rdsparse_swapbytes(&rds_format);
+
+				/* Extract PI code and store in local cache.
+				 * We need this during AF switch processing */
+				cur_picode =
+				    FM_BE16_TO_LE16(rds_format.rdsData.
+						    groupGeneral.piData);
+				if (fmdev->rx.cur_station_info.picode !=
+				    cur_picode)
+					fmdev->rx.cur_station_info.picode =
+					    cur_picode;
+				FM_DRV_DBG("picode:%d", cur_picode);
+
+				group_index =
+				    (rds_format.rdsData.groupGeneral.
+				     blockB_byte1 >> 3);
+				FM_DRV_DBG("Group:%ld%s", group_index / 2,
+					   (group_index % 2) ? "B" : "A");
+
+				group_index =
+				    1 << (rds_format.rdsData.groupGeneral.
+					  blockB_byte1 >> 3);
+				if (group_index == FM_RDS_GROUP_TYPE_MASK_0A) {
+					__fm_core_rx_update_af_cache
+					    (rds_format.rdsData.group0A.
+					     firstAf);
+					__fm_core_rx_update_af_cache(rds_format.
+								     rdsData.
+								     group0A.
+								     secondAf);
+				}
+			}
+		} else {
+			FM_DRV_DBG("Block sequence mismatch");
+			fmdev->rx.rds.last_block_index = -1;
+		}
+		rds_len -= FM_RDS_BLOCK_SIZE;
+		rds_data += FM_RDS_BLOCK_SIZE;
+	}
+
+     /* Copy raw rds data to internal rds buffer */
+	rds_data = skb->data;
+	rds_len = skb->len;
+
+	spin_lock_irqsave(&fmdev->rds_buff_lock, flags);
+	while (rds_len > 0) {
+		/* Fill RDS buffer as per V4L2 specification.
+		 * Store control byte
+		 */
+		type = (rds_data[2] & 0x07);
+		block_index = (type <= FM_RDS_BLOCK_C ? type : (type - 1));
+		tmpbuf[2] = block_index;	/* Offset name */
+		tmpbuf[2] |= block_index << 3;	/* Received offset */
+
+		/* Store data byte */
+		tmpbuf[0] = rds_data[0];
+		tmpbuf[1] = rds_data[1];
+
+		memcpy(&fmdev->rx.rds.buffer[fmdev->rx.rds.wr_index], &tmpbuf,
+		       FM_RDS_BLOCK_SIZE);
+		fmdev->rx.rds.wr_index =
+		    (fmdev->rx.rds.wr_index +
+		     FM_RDS_BLOCK_SIZE) % fmdev->rx.rds.buf_size;
+
+		/* Check for overflow & start over */
+		if (fmdev->rx.rds.wr_index == fmdev->rx.rds.rd_index) {
+			FM_DRV_DBG("RDS buffer overflow");
+			fmdev->rx.rds.wr_index = 0;
+			fmdev->rx.rds.rd_index = 0;
+			break;
+		}
+		rds_len -= FM_RDS_BLOCK_SIZE;
+		rds_data += FM_RDS_BLOCK_SIZE;
+	}
+	spin_unlock_irqrestore(&fmdev->rds_buff_lock, flags);
+
+	/* Wakeup read queue */
+	if (fmdev->rx.rds.wr_index != fmdev->rx.rds.rd_index)
+		wake_up_interruptible(&fmdev->rx.rds.read_queue);
+
+	fmdev->irq_info.stage_index = FM_RDS_FINISH_INDEX;
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_rds_finish(void)
+{
+	FMDRV_API_START();
+
+	/* Continue next function in interrupt handler table */
+	fmdev->irq_info.stage_index = FM_HW_TUNE_OP_ENDED_INDEX;
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_tune_op_ended(void)
+{
+	FMDRV_API_START();
+
+	if (fmdev->irq_info.flag & (FM_FR_EVENT | FM_BL_EVENT) & fmdev->
+	    irq_info.mask) {
+		FM_DRV_DBG("irq : tune ended/bandlimit reached");
+		if (test_and_clear_bit(FM_AF_SWITCH_INPROGRESS, &fmdev->flag)) {
+			fmdev->irq_info.stage_index = FM_AF_JUMP_RD_FREQ_INDEX;
+		} else {
+			complete(&fmdev->maintask_completion);
+			fmdev->irq_info.stage_index = FM_HW_POWER_ENB_INDEX;
+		}
+	} else
+		fmdev->irq_info.stage_index = FM_HW_POWER_ENB_INDEX;
+
+	FMDRV_API_EXIT(0);
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+}
+
+static void fm_core_irq_handle_power_enb(void)
+{
+	FMDRV_API_START();
+
+	if (fmdev->irq_info.flag & FM_POW_ENB_EVENT) {
+		FM_DRV_DBG("irq : Power Enabled/Disabled");
+		complete(&fmdev->maintask_completion);
+	}
+
+	/* Continue next function in interrupt handler table */
+	fmdev->irq_info.stage_index = FM_LOW_RSSI_START_INDEX;
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_low_rssi_start(void)
+{
+	FMDRV_API_START();
+
+	if ((fmdev->rx.af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON) &&
+	    (fmdev->irq_info.flag & FM_LEV_EVENT & fmdev->irq_info.mask) &&
+	    (fmdev->rx.curr_freq != FM_UNDEFINED_FREQ) &&
+	    (fmdev->rx.cur_station_info.no_of_items_in_afcache != 0)) {
+		FM_DRV_DBG("irq : rssi level has fallen below threshold level");
+
+		/* Disable further low RSSI interrupts */
+		fmdev->irq_info.mask &= ~FM_LEV_EVENT;
+
+		fmdev->rx.cur_Afjump_index = 0;
+		fmdev->rx.freq_before_jump = fmdev->rx.curr_freq;
+		fmdev->irq_info.stage_index = FM_AF_JUMP_SETPI_INDEX;
+	} else {
+		/* Continue next function in interrupt handler table */
+		fmdev->irq_info.stage_index = FM_SEND_INTMSK_CMD_INDEX;
+	}
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_afjump_set_pi(void)
+{
+	int ret;
+	unsigned short payload;
+
+	FMDRV_API_START();
+
+	/* Set PI code - must be updated if the AF list is not empty */
+	payload = FM_LE16_TO_BE16(fmdev->rx.cur_station_info.picode);
+	ret = __fm_core_send_cmd(RDS_PI_SET, &payload, sizeof(payload), NULL);
+	if (ret)
+		FM_DRV_ERR("irq : failed to set PI,"
+			   "initiating irq recovery process");
+	else
+		fmdev->irq_info.stage_index =
+		    FM_AF_JUMP_HANDLE_SETPI_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_set_pi_resp(void)
+{
+	struct sk_buff *skb;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	}
+	/* Continue next function in interrupt handler table */
+	fmdev->irq_info.stage_index = FM_AF_JUMP_SETPI_MASK_INDEX;
+
+	FMDRV_API_EXIT(0);
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+}
+
+static void fm_core_irq_afjump_set_pimask(void)
+{
+	int ret;
+	unsigned short payload;
+
+	FMDRV_API_START();
+
+	/* Set PI mask.
+	 * 0xFFFF = Enable PI code matching
+	 * 0x0000 = Disable PI code matching
+	 */
+	payload = 0x0000;
+	ret =
+	    __fm_core_send_cmd(RDS_PI_MASK_SET, &payload, sizeof(payload),
+			       NULL);
+	if (ret < 0)
+		FM_DRV_ERR("irq : failed to set PI mask,"
+			   "initiating irq recovery process");
+	else
+		fmdev->irq_info.stage_index =
+		    FM_AF_JUMP_HANDLE_SETPI_MASK_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_set_pimask_resp(void)
+{
+	struct sk_buff *skb;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	}
+	/* Continue next function in interrupt handler table */
+	fmdev->irq_info.stage_index = FM_AF_JUMP_SET_AF_FREQ_INDEX;
+	FMDRV_API_EXIT(0);
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+}
+
+static void fm_core_irq_afjump_setfreq(void)
+{
+	unsigned short frq_index;
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("Swtiching to %d KHz\n",
+	       fmdev->rx.cur_station_info.af_cache[fmdev->rx.cur_Afjump_index]);
+	frq_index =
+	    (fmdev->rx.cur_station_info.af_cache[fmdev->rx.cur_Afjump_index] -
+	     fmdev->rx.region.bottom_frequency) /
+	    fmdev->rx.region.channel_spacing;
+
+	FM_STORE_LE16_TO_BE16(payload, frq_index);
+	ret = __fm_core_send_cmd(AF_FREQ_SET, &payload, sizeof(payload), NULL);
+	if (ret < 0)
+		FM_DRV_ERR("irq : failed to set AF freq,"
+			   "initiating irq recovery process");
+	else
+		fmdev->irq_info.stage_index =
+		    FM_AF_JUMP_HENDLE_SET_AFFREQ_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_setfreq_resp(void)
+{
+	struct sk_buff *skb;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	} else {
+		/* Continue next function in interrupt handler table */
+		fmdev->irq_info.stage_index = FM_AF_JUMP_ENABLE_INT_INDEX;
+	}
+	FMDRV_API_EXIT(0);
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+}
+
+static void fm_core_irq_afjump_enableint(void)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Enable FR (tuning operation ended) interrupt */
+	payload = FM_LE16_TO_BE16(FM_FR_EVENT);
+	ret = __fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload), NULL);
+	if (ret)
+		FM_DRV_ERR("irq : failed to enable FR interrupt,"
+			   "initiating irq recovery process");
+	else
+		fmdev->irq_info.stage_index = FM_AF_JUMP_ENABLE_INT_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_afjump_enableint_resp(void)
+{
+	struct sk_buff *skb;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	}
+	/* Continue next function in interrupt handler table */
+	fmdev->irq_info.stage_index = FM_AF_JUMP_START_AFJUMP_INDEX;
+	FMDRV_API_EXIT(0);
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+}
+
+static void fm_core_irq_start_afjump(void)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Issue AF switch start command to the chip */
+	FM_STORE_LE16_TO_BE16(payload, FM_TUNER_AF_JUMP_MODE);
+	ret =
+	    __fm_core_send_cmd(TUNER_MODE_SET, &payload, sizeof(payload), NULL);
+	if (ret)
+		FM_DRV_ERR("irq : failed to start af switch,"
+			   "initiating irq recovery process");
+	else
+		fmdev->irq_info.stage_index =
+		    FM_AF_JUMP_HANDLE_START_AFJUMP_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_start_afjump_resp(void)
+{
+	struct sk_buff *skb;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	}
+	fmdev->irq_info.stage_index = FM_SEND_FLAG_GETCMD_INDEX;
+	set_bit(FM_AF_SWITCH_INPROGRESS, &fmdev->flag);
+	clear_bit(FM_INTTASK_RUNNING, &fmdev->flag);
+
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_afjump_rd_freq(void)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = __fm_core_send_cmd(FREQ_GET, NULL, sizeof(payload), NULL);
+	if (ret)
+		FM_DRV_ERR("irq : failed to read cur freq,"
+			   "initiating irq recovery process");
+	else
+		fmdev->irq_info.stage_index = FM_AF_JUMP_RD_FREQ_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_afjump_rd_freq_resp(void)
+{
+	struct sk_buff *skb;
+	unsigned short read_freq;
+	unsigned int curr_freq, jumped_freq;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	}
+	/* Skip header info and copy only response data */
+	skb_pull(skb, sizeof(struct fm_event_msg_hdr));
+	memcpy(&read_freq, skb->data, sizeof(read_freq));
+	read_freq = FM_BE16_TO_LE16(read_freq);
+	curr_freq = fmdev->rx.region.bottom_frequency +
+	    ((unsigned int)read_freq * fmdev->rx.region.channel_spacing);
+
+	jumped_freq =
+	    fmdev->rx.cur_station_info.af_cache[fmdev->rx.cur_Afjump_index];
+
+	/* If the frequency was changed the jump succeeded */
+	if ((curr_freq != fmdev->rx.freq_before_jump) &&
+	    (curr_freq == jumped_freq)) {
+		FM_DRV_DBG("Successfully switched to alternate frequency %d",
+			   curr_freq);
+		fmdev->rx.curr_freq = curr_freq;
+
+		/* Reset RDS cache */
+		fm_core_rx_reset_rds_cache();
+
+		/* AF feature is on, enable low level RSSI interrupt */
+		if (fmdev->rx.af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON)
+			fmdev->irq_info.mask |= FM_LEV_EVENT;
+
+		/* Call the next stage of general
+		 * interrupts handler to handle other interrupts
+		 */
+		fmdev->irq_info.stage_index = FM_LOW_RSSI_FINISH_INDEX;
+	} else {		/* jump to the next freq in the AF list */
+
+		/* Go to next index in the AF list */
+		fmdev->rx.cur_Afjump_index++;
+
+		/* If we reached the end of the list - stop searching */
+		if (fmdev->rx.cur_Afjump_index >=
+		    fmdev->rx.cur_station_info.no_of_items_in_afcache) {
+			FM_DRV_DBG("AF switch processing failed");
+			/* Call the next stage of general
+			 * interrupts handler to handle other interrupts
+			 */
+			fmdev->irq_info.stage_index = FM_LOW_RSSI_FINISH_INDEX;
+		} else {	/* AF List is not over - try next one */
+
+			FM_DRV_DBG("Trying next frequency in af cache");
+			fmdev->irq_info.stage_index = FM_AF_JUMP_SETPI_INDEX;
+		}
+	}
+	FMDRV_API_EXIT(0);
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+}
+
+static void fm_core_irq_handle_low_rssi_finish(void)
+{
+	FMDRV_API_START();
+
+	/* Continue next function in interrupt handler table */
+	fmdev->irq_info.stage_index = FM_SEND_INTMSK_CMD_INDEX;
+	fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+						 stage_index] ();
+
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_send_intmsk_cmd(void)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Re-enable FM interrupts */
+	FM_STORE_LE16_TO_BE16(payload, fmdev->irq_info.mask);
+	ret = __fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload), NULL);
+	if (ret)
+		FM_DRV_ERR("irq : failed to send int_mask_set cmd,"
+			   "initiating irq recovery process");
+	else
+		fmdev->irq_info.stage_index = FM_HANDLE_INTMSK_CMD_RESP_INDEX;
+
+	/* Start timer to track timeout */
+	mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+		  FM_DRV_TX_TIMEOUT);
+	FMDRV_API_EXIT(0);
+}
+
+static void fm_core_irq_handle_intmsk_cmd_resp(void)
+{
+	struct sk_buff *skb;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Stop timeout timer */
+	del_timer(&fmdev->irq_info.int_timeout_timer);
+
+	ret = fm_core_check_cmdresp_status(&skb);
+	if (ret) {
+		FM_DRV_ERR("Initiating irq recovery process");
+		mod_timer(&fmdev->irq_info.int_timeout_timer, jiffies +
+			  FM_DRV_TX_TIMEOUT);
+		FMDRV_API_EXIT(FM_ST_FAILED);
+		return;
+	}
+	/* This is last function in interrupt table to be executed.
+	 * So, reset stage index to 0.
+	 */
+	fmdev->irq_info.stage_index = FM_SEND_FLAG_GETCMD_INDEX;
+
+	/* Start processing any pending interrupt */
+	if (test_and_clear_bit(FM_INTTASK_SCHEDULE_PENDING, &fmdev->flag)) {
+		FMDRV_API_EXIT(0);
+		fmdev->irq_info.fm_IntActionHandlerTable[fmdev->irq_info.
+							 stage_index]
+		    ();
+	} else
+		clear_bit(FM_INTTASK_RUNNING, &fmdev->flag);
+
+	FMDRV_API_EXIT(0);
+}
+
+/* --------------- FM TX tasklet -----------------*/
+
+/* FM V4L2 interface and FM mixer control interface layer
+ * schedule this tasklet whenever it wants to transmit FM packet.
+ */
+static void fm_core_tx_tasklet(unsigned long arg)
+{
+	struct sk_buff *skb;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Check, is there any timeout happenned to last transmitted packet */
+	if (!atomic_read(&fmdev->tx_cnt) &&
+	    ((jiffies - fmdev->last_tx_jiffies) > FM_DRV_TX_TIMEOUT)) {
+		FM_DRV_ERR("TX timeout occurred");
+		atomic_set(&fmdev->tx_cnt, 1);
+	}
+	/* Send queued FM TX packets */
+	if (atomic_read(&fmdev->tx_cnt)) {
+		skb = skb_dequeue(&fmdev->tx_q);
+		if (skb) {
+			atomic_dec(&fmdev->tx_cnt);
+			fmdev->last_sent_pkt_opcode = fm_cb(skb)->fm_opcode;
+
+			if (fmdev->response_completion != NULL)
+				FM_DRV_ERR
+				    ("Response completion handler is not NULL");
+
+			fmdev->response_completion = fm_cb(skb)->completion;
+#ifdef FM_DUMP_TXRX_PKT
+			dump_tx_skb_data(skb);
+#endif
+			/* Forward SKB to FM ST,
+			 * FM ST will internally forward SKB to ST driver.
+			 */
+			ret = fm_st_send(skb);
+			if (ret < 0) {
+				fmdev->response_completion = NULL;
+				FM_DRV_ERR
+				    ("TX tasklet failed to send skb(%p)", skb);
+				atomic_set(&fmdev->tx_cnt, 1);
+			} else
+				fmdev->last_tx_jiffies = jiffies;
+		}
+	}
+	FMDRV_API_EXIT(0);
+}
+
+/* --------------- FM RX tasklet -----------------*/
+
+/* FM ST will schedule this tasklet whenever it receives
+ * FM packet from ST driver.
+ */
+static void fm_core_rx_tasklet(unsigned long arg)
+{
+	struct fm_event_msg_hdr *fm_evt_hdr;
+	struct sk_buff *skb;
+	unsigned char num_fm_hci_cmds;
+	unsigned long flags;
+
+	FMDRV_API_START();
+
+	/* Process all packets in the RX queue */
+	while ((skb = skb_dequeue(&fmdev->rx_q))) {
+		if (skb->len < sizeof(struct fm_event_msg_hdr)) {
+			FM_DRV_ERR("skb(%p) has only %d bytes"
+				   "atleast need %d bytes to decode",
+				   skb, skb->len,
+				   sizeof(struct fm_event_msg_hdr));
+			kfree_skb(skb);
+			continue;
+		}
+
+		fm_evt_hdr = (void *)skb->data;
+		num_fm_hci_cmds = fm_evt_hdr->num_fm_hci_cmds;
+
+#ifdef FM_DUMP_TXRX_PKT
+		dump_rx_skb_data(skb);
+#endif
+		/* FM interrupt packet? */
+		if (fm_evt_hdr->fm_opcode == fm_reg_info[FM_INTERRUPT].opcode) {
+			/* FM interrupt handler started already? */
+			if (!test_bit(FM_INTTASK_RUNNING, &fmdev->flag)) {
+				set_bit(FM_INTTASK_RUNNING, &fmdev->flag);
+				if (fmdev->irq_info.stage_index != 0) {
+					FM_DRV_ERR("Invalid stage index,"
+						   "resetting to zero");
+					fmdev->irq_info.stage_index = 0;
+				}
+
+				/* Execute first function
+				 * in interrupt handler table
+				 */
+				fmdev->irq_info.fm_IntActionHandlerTable
+				    [fmdev->irq_info.stage_index]
+				    ();
+			} else {
+				set_bit(FM_INTTASK_SCHEDULE_PENDING,
+					&fmdev->flag);
+			}
+			kfree_skb(skb);
+		}
+		/* Anyone waiting for this with completion handler? */
+		else if (fm_evt_hdr->fm_opcode == fmdev->last_sent_pkt_opcode &&
+			 fmdev->response_completion != NULL) {
+			if (fmdev->response_skb != NULL)
+				FM_DRV_ERR("Response SKB pointer is not NULL");
+
+			spin_lock_irqsave(&fmdev->resp_skb_lock, flags);
+			fmdev->response_skb = skb;
+			spin_unlock_irqrestore(&fmdev->resp_skb_lock, flags);
+			complete(fmdev->response_completion);
+
+			fmdev->response_completion = NULL;
+			atomic_set(&fmdev->tx_cnt, 1);
+		}
+		/* Is this for interrupt handler? */
+		else if (fm_evt_hdr->fm_opcode == fmdev->last_sent_pkt_opcode &&
+			 fmdev->response_completion == NULL) {
+			if (fmdev->response_skb != NULL)
+				FM_DRV_ERR("Response SKB pointer is not NULL");
+
+			spin_lock_irqsave(&fmdev->resp_skb_lock, flags);
+			fmdev->response_skb = skb;
+			spin_unlock_irqrestore(&fmdev->resp_skb_lock, flags);
+
+			/* Execute interrupt handler where state index points */
+			fmdev->irq_info.fm_IntActionHandlerTable
+			    [fmdev->irq_info.stage_index]
+			    ();
+
+			kfree_skb(skb);
+			atomic_set(&fmdev->tx_cnt, 1);
+		} else {
+			FM_DRV_ERR("Nobody claimed SKB(%p),purging", skb);
+		}
+
+		/* Check flow control field.
+		 * If Num_FM_HCI_Commands field is not zero,
+		 * schedule FM TX tasklet.
+		 */
+		if (num_fm_hci_cmds && atomic_read(&fmdev->tx_cnt)) {
+			if (!skb_queue_empty(&fmdev->tx_q))
+				tasklet_schedule(&fmdev->tx_task);
+		}
+	}
+	FMDRV_API_EXIT(0);
+}
+
+/* ----- Fucntions exported to FM V4L2 layer ----- */
+int fm_core_tx_set_stereo_mono(unsigned short mode)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("stereo mode: %d", (int)mode);
+
+	/* Set Stereo/Mono mode */
+	FM_STORE_LE16_TO_BE16(payload, (1 - mode));
+	ret = fm_core_send_cmd(MONO_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_tx_set_rds_text(unsigned char *rds_text)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("rds_text: %s", rds_text);
+
+	ret = fm_core_send_cmd(RDS_DATA_SET, rds_text, strlen(rds_text),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Scroll mode */
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)0x1);
+	ret = fm_core_send_cmd(DISPLAY_MODE_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_tx_set_rds_data_mode(unsigned char mode)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("data mode: %d", (int)mode);
+
+	/* Setting unique PI TODO: how unique? */
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)0xcafe);
+	ret = fm_core_send_cmd(PI_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Set decoder id */
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)0xa);
+	ret = fm_core_send_cmd(DI_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* TODO: RDS_MODE_GET? */
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_tx_set_rds_len(unsigned char type, unsigned short len)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("len: %d", (int)len);
+
+	len |= type << 8;
+	FM_STORE_LE16_TO_BE16(payload, len);
+	ret = fm_core_send_cmd(LENGHT_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* TODO: LENGHT_GET? */
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_tx_set_rds_mode(unsigned char rds_en_dis)
+{
+	unsigned short payload;
+	int ret;
+	unsigned char rds_text[] = "Zoom2\n";
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("rds_en_dis:%d(E:%d, D:%d)", rds_en_dis,
+		   FM_RX_RDS_ENABLE, FM_RX_RDS_DISABLE);
+
+	if (rds_en_dis == FM_RX_RDS_ENABLE) {
+		/* Set RDS length */
+		fm_core_tx_set_rds_len(0, strlen(rds_text));
+		/* Set RDS text */
+		fm_core_tx_set_rds_text(rds_text);
+		/* Set RDS mode */
+		fm_core_tx_set_rds_data_mode(0x0);
+	}
+
+	/* Send command to enable RDS */
+	if (rds_en_dis == FM_RX_RDS_ENABLE)
+		FM_STORE_LE16_TO_BE16(payload, 0x01);
+	else
+		FM_STORE_LE16_TO_BE16(payload, 0x00);
+
+	ret = fm_core_send_cmd(RDS_DATA_ENB, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	if (rds_en_dis == FM_RX_RDS_ENABLE) {
+		/* Set RDS length */
+		fm_core_tx_set_rds_len(0, strlen(rds_text));
+		/* Set RDS text */
+		fm_core_tx_set_rds_text(rds_text);
+	}
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_tx_set_radio_text(unsigned char *rds_text, unsigned char rds_type)
+{
+	unsigned short payload;
+	int ret;
+	FMDRV_API_START();
+
+	fm_core_tx_set_rds_mode(0);
+	/* Set RDS length */
+	fm_core_tx_set_rds_len(rds_type, strlen(rds_text));
+	/* Set RDS text */
+	fm_core_tx_set_rds_text(rds_text);
+	/* Set RDS mode */
+	fm_core_tx_set_rds_data_mode(0x0);
+
+	FM_STORE_LE16_TO_BE16(payload, 1);
+	ret = fm_core_send_cmd(RDS_DATA_ENB, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_tx_set_af(unsigned int af)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("AF: %d", af);
+
+	/* Set AF */
+	af = (af - 87500) / 100;
+
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)af);
+	ret = fm_core_send_cmd(TA_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_tx_set_region(unsigned char region_to_set)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("region_to_set %ld(Eu/US %d, Jp %d)",
+		   (unsigned long)region_to_set, FM_BAND_EUROPE_US,
+		   FM_BAND_JAPAN);
+
+	if (region_to_set != FM_BAND_EUROPE_US &&
+	    region_to_set != FM_BAND_JAPAN) {
+		FM_DRV_ERR("Invalid band\n");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+
+	/* Send command to set the band */
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)region_to_set);
+	ret = fm_core_send_cmd(TX_BAND_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_tx_set_mute_mode(unsigned char mute_mode_toset)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("tx: mute mode %ld", (unsigned long)mute_mode_toset);
+	FM_STORE_LE16_TO_BE16(payload, mute_mode_toset);
+	ret = fm_core_send_cmd(MUTE, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set TX Audio I/O */
+static int fm_core_tx_set_audio_io(void)
+{
+	struct fmtx_data *tx = &fmdev->tx_data;
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("tx: audio_io %ld ", (long int)tx->audio_io);
+
+	/* Set Audio I/O Enable */
+	FM_STORE_LE16_TO_BE16(payload, tx->audio_io);
+	ret = fm_core_send_cmd(AUDIO_IO_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* TODO: is audio set? */
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Start TX Transmission */
+static int fm_core_tx_xmit(unsigned char new_xmit_state)
+{
+	struct fmtx_data *tx = &fmdev->tx_data;
+	unsigned short payload;
+	unsigned long timeleft;
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Enable POWER_ENB interrupts */
+	FM_STORE_LE16_TO_BE16(payload, FM_POW_ENB_EVENT);
+	ret = fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+
+	/* Set Power Enable */
+	FM_STORE_LE16_TO_BE16(payload, new_xmit_state);
+	ret = fm_core_send_cmd(POWER_ENB_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Wait for Power Enabled */
+	init_completion(&fmdev->maintask_completion);
+	timeleft = wait_for_completion_timeout(&fmdev->maintask_completion,
+					       FM_DRV_TX_TIMEOUT);
+	if (!timeleft) {
+		FM_DRV_ERR("Timeout(%d sec),didn't get tune ended interrupt",
+			   jiffies_to_msecs(FM_DRV_TX_TIMEOUT) / 1000);
+		FMDRV_API_EXIT(-ETIMEDOUT);
+		return -ETIMEDOUT;
+	}
+
+	set_bit(FM_CORE_TX_XMITING, &fmdev->flag);
+	tx->xmit_state = new_xmit_state;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set TX power level */
+int fm_core_tx_set_pwr_lvl(unsigned char new_pwr_lvl)
+{
+	unsigned short payload;
+	struct fmtx_data *tx = &fmdev->tx_data;
+	int ret;
+
+	FMDRV_API_START();
+
+	FM_DRV_DBG("tx: pwr_level_to_set %ld ", (long int)new_pwr_lvl);
+	/* If the core isn't ready update global variable */
+	if (!test_bit(FM_CORE_READY, &fmdev->flag)) {
+		tx->pwr_lvl = new_pwr_lvl;
+		return 0;
+	}
+
+	/* Set power level */
+	FM_STORE_LE16_TO_BE16(payload, new_pwr_lvl);
+	ret = fm_core_send_cmd(POWER_LEL_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* TODO: is the power level set? */
+	tx->pwr_lvl = new_pwr_lvl;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set TX Frequency */
+static int fm_core_tx_set_frequency(unsigned int freq_to_set)
+{
+	struct fmtx_data *tx = &fmdev->tx_data;
+	unsigned short payload, chanl_index;
+	int ret;
+
+	FMDRV_API_START();
+
+	if (test_bit(FM_CORE_TX_XMITING, &fmdev->flag)) {
+		fm_core_tx_xmit(0);
+		clear_bit(FM_CORE_TX_XMITING, &fmdev->flag);
+	}
+
+	/* Enable FR, BL interrupts */
+	FM_STORE_LE16_TO_BE16(payload, (FM_FR_EVENT | FM_BL_EVENT));
+	ret = fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+
+	tx->tx_frq = (unsigned long)freq_to_set;
+	FM_DRV_DBG("tx: freq_to_set %ld ", (long int)tx->tx_frq);
+
+	chanl_index = freq_to_set / 10;
+	/* Set current tuner channel */
+	FM_STORE_LE16_TO_BE16(payload, chanl_index);
+	ret = fm_core_send_cmd(CHANL_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* TODO:confirm the freq set */
+	fm_core_tx_set_pwr_lvl(tx->pwr_lvl);
+
+	tx->audio_io = 0x01;	/* I2S */
+	fm_core_tx_set_audio_io();
+
+	fm_core_tx_xmit(0x01);	/* Enable transmission */
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Returns availability of RDS data in internel buffer */
+int fm_core_is_rds_data_available(struct file *file,
+				  struct poll_table_struct *pts)
+{
+	FMDRV_API_START();
+
+	poll_wait(file, &fmdev->rx.rds.read_queue, pts);
+	if (fmdev->rx.rds.rd_index != fmdev->rx.rds.wr_index) {
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+
+	FMDRV_API_EXIT(-EAGAIN);
+	return -EAGAIN;
+}
+
+/* Copies RDS data from internal buffer to user buffer */
+int fm_core_transfer_rds_from_internal_buff(struct file *file,
+					    char __user *buf, size_t count)
+{
+	unsigned int block_count;
+	unsigned long flags;
+	int ret;
+	FMDRV_API_START();
+
+	/* Block if no new data available */
+	if (fmdev->rx.rds.wr_index == fmdev->rx.rds.rd_index) {
+		if (file->f_flags & O_NONBLOCK)
+			return -EWOULDBLOCK;
+
+		ret = wait_event_interruptible(fmdev->rx.rds.read_queue,
+					       (fmdev->rx.rds.wr_index !=
+						fmdev->rx.rds.rd_index));
+		if (ret) {
+			FMDRV_API_EXIT(-EINTR);
+			return -EINTR;
+		}
+	}
+
+	/* Calculate block count from byte count */
+	count /= 3;
+	block_count = 0;
+	ret = 0;
+
+	spin_lock_irqsave(&fmdev->rds_buff_lock, flags);
+
+	/* Copy RDS blocks from the internal buffer and to user buffer */
+	while (block_count < count) {
+		if (fmdev->rx.rds.wr_index == fmdev->rx.rds.rd_index)
+			break;
+
+		/* Always transfer complete RDS blocks */
+		if (copy_to_user
+		    (buf, &fmdev->rx.rds.buffer[fmdev->rx.rds.rd_index],
+		     FM_RDS_BLOCK_SIZE))
+			break;
+
+		/* Increment and wrap the read pointer */
+		fmdev->rx.rds.rd_index += FM_RDS_BLOCK_SIZE;
+
+		/* Wrap read pointer */
+		if (fmdev->rx.rds.rd_index >= fmdev->rx.rds.buf_size)
+			fmdev->rx.rds.rd_index = 0;
+
+		/* Increment counters */
+		block_count++;
+		buf += FM_RDS_BLOCK_SIZE;
+		ret += FM_RDS_BLOCK_SIZE;
+	}
+	spin_unlock_irqrestore(&fmdev->rds_buff_lock, flags);
+	return ret;
+}
+
+/* Checks FM core active status and TX/RX/OFF mode status */
+static inline int fm_core_check_mode(unsigned char mode)
+{
+	if (!test_bit(FM_CORE_READY, &fmdev->flag)) {
+		FM_DRV_ERR("FM core is not ready");
+		return -EPERM;
+	}
+	if (mode >= FM_MODE_ENTRY_MAX) {
+		FM_DRV_ERR("Invalid fm mode");
+		return -EPERM;
+	}
+	if (fmdev->curr_fmmode != mode) {
+		FM_DRV_ERR("Current mode is not in %s mode",
+			   mode ? ((mode == 1) ? "TX" : "RX") : "OFF");
+		return -EPERM;
+	}
+	return 0;
+}
+
+/* Set RX Frequency */
+static int fm_core_rx_set_frequency(unsigned int freq_to_set)
+{
+	unsigned long timeleft;
+	unsigned short payload, curr_frq, frq_index;
+	unsigned int curr_frq_in_khz;
+	int ret, resp_len;
+
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (freq_to_set < fmdev->rx.region.bottom_frequency ||
+	    freq_to_set > fmdev->rx.region.top_frequency) {
+		FM_DRV_ERR("Invalid frequency %d", freq_to_set);
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	/* Set audio enable */
+	FM_STORE_LE16_TO_BE16(payload, FM_RX_FM_AUDIO_ENABLE_I2S_AND_ANALOG);
+	ret = fm_core_send_cmd(AUDIO_ENABLE_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Set hilo to automatic selection */
+	FM_STORE_LE16_TO_BE16(payload, FM_RX_IFFREQ_HILO_AUTOMATIC);
+	ret = fm_core_send_cmd(HILO_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Calculate frequency index to write */
+	frq_index = (freq_to_set - fmdev->rx.region.bottom_frequency) /
+	    fmdev->rx.region.channel_spacing;
+
+	/* Set frequency index */
+	FM_STORE_LE16_TO_BE16(payload, frq_index);
+	ret = fm_core_send_cmd(FREQ_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Read flags - just to clear any pending interrupts if we had */
+	ret = fm_core_send_cmd(FLAG_GET, NULL, 2,
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Enable FR, BL interrupts */
+	fmdev->irq_info.mask |= (FM_FR_EVENT | FM_BL_EVENT);
+	FM_STORE_LE16_TO_BE16(payload, fmdev->irq_info.mask);
+	ret = fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Start tune */
+	FM_STORE_LE16_TO_BE16(payload, FM_TUNER_PRESET_MODE);
+	ret = fm_core_send_cmd(TUNER_MODE_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Wait for tune ended interrupt */
+	init_completion(&fmdev->maintask_completion);
+	timeleft = wait_for_completion_timeout(&fmdev->maintask_completion,
+					       FM_DRV_TX_TIMEOUT);
+	if (!timeleft) {
+		FM_DRV_ERR("Timeout(%d sec),didn't get tune ended interrupt",
+			   jiffies_to_msecs(FM_DRV_TX_TIMEOUT) / 1000);
+		FMDRV_API_EXIT(-ETIMEDOUT);
+		return -ETIMEDOUT;
+	}
+
+	/* Read freq back to confirm */
+	ret = fm_core_send_cmd(FREQ_GET, NULL, 2,
+			       &fmdev->maintask_completion, &curr_frq,
+			       &resp_len);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	curr_frq = FM_BE16_TO_LE16(curr_frq);
+	curr_frq_in_khz = (fmdev->rx.region.bottom_frequency
+			   +
+			   ((unsigned int)curr_frq *
+			    fmdev->rx.region.channel_spacing));
+
+	/* Re-enable default FM interrupts */
+	fmdev->irq_info.mask &= ~(FM_FR_EVENT | FM_BL_EVENT);
+	FM_STORE_LE16_TO_BE16(payload, fmdev->irq_info.mask);
+	ret = fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	if (curr_frq_in_khz != freq_to_set) {
+		FM_DRV_ERR("Current chip frequency(%d) is not matching with"
+			   " requested frequency(%d)", curr_frq_in_khz,
+			   freq_to_set);
+		FMDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+
+	/* Update local cache  */
+	fmdev->rx.curr_freq = curr_frq_in_khz;
+
+	/* Reset RDS cache and current station pointers */
+	fm_core_rx_reset_rds_cache();
+	fm_core_rx_reset_curr_station_info();
+
+	/* Do we need to reset anything else? */
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_set_frequency(unsigned int freq_to_set)
+{
+	int ret;
+
+	FMDRV_API_START();
+	switch (fmdev->curr_fmmode) {
+	case FM_MODE_RX:
+		ret = fm_core_rx_set_frequency(freq_to_set);
+		break;
+
+	case FM_MODE_TX:
+		ret = fm_core_tx_set_frequency(freq_to_set);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	FMDRV_API_EXIT(ret);
+	return ret;
+}
+
+int fm_core_get_frequency(unsigned int *cur_tuned_frq)
+{
+	int ret;
+
+	FMDRV_API_START();
+	if (!test_bit(FM_CORE_READY, &fmdev->flag)) {
+		FM_DRV_ERR("FM core is not ready");
+		FMDRV_API_EXIT(-EPERM);
+		return -EPERM;
+	}
+	if (fmdev->rx.curr_freq == FM_UNDEFINED_FREQ) {
+		FM_DRV_ERR("RX frequency is not set");
+		FMDRV_API_EXIT(-EPERM);
+		return -EPERM;
+	}
+	if (cur_tuned_frq == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	ret = 0;
+	switch (fmdev->curr_fmmode) {
+	case FM_MODE_RX:
+		*cur_tuned_frq = fmdev->rx.curr_freq;
+		ret = 0;
+		break;
+
+	case FM_MODE_TX:
+		*cur_tuned_frq = 0;	/* TODO : Change this later */
+		ret = 0;
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	FMDRV_API_EXIT(ret);
+	return ret;
+}
+
+/* Seek */
+int fm_core_rx_seek(unsigned int seek_upward, unsigned int wrap_around)
+{
+	int resp_len;
+	unsigned short curr_frq, next_frq, last_frq;
+	unsigned short payload, int_reason;
+	char offset;
+	unsigned long timeleft;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Read the current frequency from chip */
+	ret = fm_core_send_cmd(FREQ_GET, NULL, sizeof(curr_frq),
+			       &fmdev->maintask_completion, &curr_frq,
+			       &resp_len);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	curr_frq = FM_BE16_TO_LE16(curr_frq);
+
+	last_frq =
+	    (fmdev->rx.region.top_frequency - fmdev->rx.region.bottom_frequency)
+	    / fmdev->rx.region.channel_spacing;
+
+	/* Check the offset in order to be aligned to the 100KHz steps */
+	offset = curr_frq % 2;
+
+	next_frq = seek_upward ? curr_frq + 2 /* Seek Up */ :
+	    curr_frq - 2 /* Seek Down */ ;
+
+	/* Add or subtract offset (0/1) in order
+	 * to stay aligned to the 100KHz steps
+	 */
+	if ((short)next_frq < 0)
+		next_frq = last_frq - offset;
+	else if (next_frq > last_frq)
+		next_frq = 0 + offset;
+
+	/* Set calculated next frequency to perform seek */
+	FM_STORE_LE16_TO_BE16(payload, next_frq);
+	ret = fm_core_send_cmd(FREQ_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Set search direction (0:Seek Down, 1:Seek Up) */
+	FM_STORE_LE16_TO_BE16(payload, (seek_upward ? FM_SEARCH_DIRECTION_UP :
+					FM_SEARCH_DIRECTION_DOWN));
+	ret = fm_core_send_cmd(SEARCH_DIR_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Read flags - just to clear any pending interrupts if we had */
+	ret = fm_core_send_cmd(FLAG_GET, NULL, 2,
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Enable FR, BL interrupts */
+	fmdev->irq_info.mask |= (FM_FR_EVENT | FM_BL_EVENT);
+	FM_STORE_LE16_TO_BE16(payload, fmdev->irq_info.mask);
+	ret = fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Start seek */
+	FM_STORE_LE16_TO_BE16(payload, FM_TUNER_AUTONOMOUS_SEARCH_MODE);
+	ret = fm_core_send_cmd(TUNER_MODE_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Wait for tune ended/band limit reached interrupt */
+	init_completion(&fmdev->maintask_completion);
+	timeleft = wait_for_completion_timeout(&fmdev->maintask_completion,
+					       FM_DRV_RX_SEEK_TIMEOUT);
+	if (!timeleft) {
+		FM_DRV_ERR("Timeout(%d sec),didn't get tune ended interrupt",
+			   jiffies_to_msecs(FM_DRV_RX_SEEK_TIMEOUT) / 1000);
+		FMDRV_API_EXIT(-ETIMEDOUT);
+		return -ETIMEDOUT;
+	}
+	int_reason = fmdev->irq_info.flag & 0x3;
+
+	/* Re-enable default FM interrupts */
+	fmdev->irq_info.mask &= ~(FM_FR_EVENT | FM_BL_EVENT);
+	FM_STORE_LE16_TO_BE16(payload, fmdev->irq_info.mask);
+	ret = fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Read freq to know where operation tune operation stopped */
+	ret = fm_core_send_cmd(FREQ_GET, NULL, 2,
+			       &fmdev->maintask_completion, &curr_frq,
+			       &resp_len);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	curr_frq = FM_BE16_TO_LE16(curr_frq);
+	fmdev->rx.curr_freq = (fmdev->rx.region.bottom_frequency +
+			       ((unsigned int)curr_frq *
+				fmdev->rx.region.channel_spacing));
+
+	/* Reset RDS cache and current station pointers */
+	fm_core_rx_reset_rds_cache();
+	fm_core_rx_reset_curr_station_info();
+
+	/* Return error if band limit is reached */
+	if (int_reason & FM_BL_EVENT) {
+		FM_DRV_DBG("band limit reached\n");
+		FMDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set volume */
+int fm_core_rx_set_volume(unsigned short vol_to_set)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (vol_to_set > FM_RX_VOLUME_MAX) {
+		FM_DRV_ERR("Volume is not within(%d-%d) range",
+			   FM_RX_VOLUME_MIN, FM_RX_VOLUME_MAX);
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	vol_to_set *= FM_RX_VOLUME_GAIN_STEP;
+
+	FM_STORE_LE16_TO_BE16(payload, vol_to_set);
+	ret = fm_core_send_cmd(VOLUME_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	fmdev->rx.curr_volume = vol_to_set;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Get volume */
+int fm_core_rx_get_volume(unsigned short *curr_vol)
+{
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (curr_vol == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	*curr_vol = fmdev->rx.curr_volume / FM_RX_VOLUME_GAIN_STEP;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Returns current band index (0-Europe/US; 1-Japan) */
+int fm_core_region_get(unsigned char *region)
+{
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (region == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	*region = fmdev->rx.region.region_index;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* To get current band's bottom and top frequency */
+int fm_core_rx_get_currband_lowhigh_freq(unsigned int *bottom_frequency,
+					 unsigned int *top_frequency)
+{
+	FMDRV_API_START();
+
+	if (bottom_frequency != NULL)
+		*bottom_frequency = fmdev->rx.region.bottom_frequency;
+
+	if (top_frequency != NULL)
+		*top_frequency = fmdev->rx.region.top_frequency;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Sets band (0-Europe/US; 1-Japan) */
+int fm_core_rx_region_set(unsigned char region_to_set)
+{
+	unsigned short payload;
+	unsigned int new_frq;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (region_to_set != FM_BAND_EUROPE_US &&
+	    region_to_set != FM_BAND_JAPAN) {
+		FM_DRV_ERR("Invalid band\n");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	if (fmdev->rx.region.region_index == region_to_set) {
+		FM_DRV_ERR("Requested band is already configured\n");
+		FMDRV_API_EXIT(-EPERM);
+		return -EPERM;
+	}
+	/* Send cmd to set the band  */
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)region_to_set);
+	ret = fm_core_send_cmd(RX_BAND_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Update local region info cache */
+	memcpy(&fmdev->rx.region, &region_configs[region_to_set],
+	       sizeof(struct region_info));
+
+	/* Check whether current RX frequency is within band boundary */
+	if (fmdev->curr_fmmode == FM_MODE_RX) {
+		new_frq = 0;
+		if (fmdev->rx.curr_freq < fmdev->rx.region.bottom_frequency)
+			new_frq = fmdev->rx.region.bottom_frequency;
+		else if (fmdev->rx.curr_freq > fmdev->rx.region.top_frequency)
+			new_frq = fmdev->rx.region.top_frequency;
+
+		if (new_frq) {
+			FM_DRV_DBG
+			    ("Current freq is not within band limit boundary,"
+			     "switching to %d KHz", new_frq);
+			/* Current RX frequency is not
+			 * within boundary. So, update it
+			 */
+			ret = fm_core_rx_set_frequency(new_frq);
+			if (ret < 0) {
+				FMDRV_API_EXIT(ret);
+				return ret;
+			}
+		}
+	}
+
+	/* TODO : Add above boundary check in TX mode also */
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_region_set(unsigned char region_to_set)
+{
+	int ret;
+
+	FMDRV_API_START();
+	switch (fmdev->curr_fmmode) {
+	case FM_MODE_RX:
+		ret = fm_core_rx_region_set(region_to_set);
+		break;
+
+	case FM_MODE_TX:
+		ret = fm_core_tx_set_region(region_to_set);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	FMDRV_API_EXIT(ret);
+	return ret;
+}
+
+/* Reads current mute mode (Mute Off/On/Attenuate)*/
+int fm_core_rx_get_mute_mode(unsigned char *curr_mute_mode)
+{
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (curr_mute_mode == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	*curr_mute_mode = fmdev->rx.curr_mute_mode;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int __fm_core_config_rx_mute_reg(void)
+{
+	unsigned short payload, muteval;
+	int ret;
+
+	FMDRV_API_START();
+
+	muteval = 0;
+	switch (fmdev->rx.curr_mute_mode) {
+	case FM_MUTE_ON:
+		muteval = FM_RX_MUTE_AC_MUTE_MODE;
+		break;
+	case FM_MUTE_OFF:
+		muteval = FM_RX_MUTE_UNMUTE_MODE;
+		break;
+	case FM_MUTE_ATTENUATE:
+		muteval = FM_RX_MUTE_SOFT_MUTE_FORCE_MODE;
+		break;
+	}
+	if (fmdev->rx.curr_rf_depend_mute == FM_RX_RF_DEPENDENT_MUTE_ON)
+		muteval |= FM_RX_MUTE_RF_DEP_MODE;
+	else
+		muteval &= ~FM_RX_MUTE_RF_DEP_MODE;
+
+	FM_STORE_LE16_TO_BE16(payload, muteval);
+	ret = fm_core_send_cmd(MUTE_STATUS_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Configures mute mode (Mute Off/On/Attenuate) */
+int fm_core_rx_set_mute_mode(unsigned char mute_mode_toset)
+{
+	unsigned char org_state;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (fmdev->rx.curr_mute_mode == mute_mode_toset) {
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+	org_state = fmdev->rx.curr_mute_mode;
+	fmdev->rx.curr_mute_mode = mute_mode_toset;
+
+	ret = __fm_core_config_rx_mute_reg();
+	if (ret < 0) {
+		fmdev->rx.curr_mute_mode = org_state;
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_set_mute_mode(unsigned char mute_mode_toset)
+{
+	int ret;
+
+	FMDRV_API_START();
+	switch (fmdev->curr_fmmode) {
+	case FM_MODE_RX:
+		ret = fm_core_rx_set_mute_mode(mute_mode_toset);
+		break;
+
+	case FM_MODE_TX:
+		ret = fm_core_tx_set_mute_mode(mute_mode_toset);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	FMDRV_API_EXIT(ret);
+	return ret;
+}
+
+/* Gets RF dependent soft mute mode enable/disable status */
+int fm_core_rx_get_rfdepend_softmute(unsigned char *curr_mute_mode)
+{
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (curr_mute_mode == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	*curr_mute_mode = fmdev->rx.curr_rf_depend_mute;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Sets RF dependent soft mute mode */
+int fm_core_rx_set_rfdepend_softmute(unsigned char rfdepend_mute)
+{
+	unsigned char org_state;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (rfdepend_mute != FM_RX_RF_DEPENDENT_MUTE_ON &&
+	    rfdepend_mute != FM_RX_RF_DEPENDENT_MUTE_OFF) {
+		FM_DRV_ERR("Invalid RF dependent soft mute");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	if (fmdev->rx.curr_rf_depend_mute == rfdepend_mute) {
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+
+	org_state = fmdev->rx.curr_rf_depend_mute;
+	fmdev->rx.curr_rf_depend_mute = rfdepend_mute;
+
+	ret = __fm_core_config_rx_mute_reg();
+	if (ret < 0) {
+		fmdev->rx.curr_rf_depend_mute = org_state;
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Returns the signal strength level of current channel */
+int fm_core_rx_get_rssi_level(unsigned short *rssilvl)
+{
+	unsigned short curr_rssi_lel;
+	int resp_len;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (rssilvl == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	/* Read current RSSI level */
+	ret = fm_core_send_cmd(RSSI_LVL_GET, NULL, 2,
+			       &fmdev->maintask_completion, &curr_rssi_lel,
+			       &resp_len);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	*rssilvl = FM_BE16_TO_LE16(curr_rssi_lel);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Sets the signal strength level that once reached
+ * will stop the auto search process
+ */
+int fm_core_rx_set_rssi_threshold(short rssi_lvl_toset)
+{
+	unsigned short payload;
+	int ret;
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (rssi_lvl_toset < FM_RX_RSSI_THRESHOLD_MIN ||
+	    rssi_lvl_toset > FM_RX_RSSI_THRESHOLD_MAX) {
+		FM_DRV_ERR("Invalid RSSI threshold level");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)rssi_lvl_toset);
+	ret = fm_core_send_cmd(SEARCH_LVL_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	fmdev->rx.curr_rssi_threshold = rssi_lvl_toset;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Returns current RX RSSI threshold value */
+int fm_core_rx_get_rssi_threshold(short *curr_rssi_lvl)
+{
+	int ret;
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (curr_rssi_lvl == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	*curr_rssi_lvl = fmdev->rx.curr_rssi_threshold;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Sets RX stereo/mono modes */
+int fm_core_rx_set_stereo_mono(unsigned short mode)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (mode != FM_STEREO_MODE && mode != FM_MONO_MODE) {
+		FM_DRV_ERR("Invalid mode");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	/* Set stereo/mono mode */
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)mode);
+	ret = fm_core_send_cmd(MOST_MODE_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Set stereo blending mode */
+	FM_STORE_LE16_TO_BE16(payload, FM_STEREO_SOFT_BLEND);
+	ret = fm_core_send_cmd(MOST_BLEND_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_set_stereo_mono(unsigned short mode)
+{
+	int ret;
+
+	FMDRV_API_START();
+	switch (fmdev->curr_fmmode) {
+	case FM_MODE_RX:
+		ret = fm_core_rx_set_stereo_mono(mode);
+		break;
+
+	case FM_MODE_TX:
+		ret = fm_core_tx_set_stereo_mono(mode);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	FMDRV_API_EXIT(ret);
+	return ret;
+}
+
+/* Gets current RX stereo/mono mode */
+int fm_core_rx_get_stereo_mono(unsigned short *mode)
+{
+	unsigned short curr_mode;
+	int ret, resp_len;
+
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (mode == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	ret = fm_core_send_cmd(MOST_MODE_GET, NULL, 2,
+			       &fmdev->maintask_completion, &curr_mode,
+			       &resp_len);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	*mode = FM_BE16_TO_LE16(curr_mode);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Chooses RX de-emphasis filter mode (50us/75us) */
+int fm_core_rx_set_deemphasis_mode(unsigned short mode)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (mode != FM_RX_EMPHASIS_FILTER_50_USEC &&
+	    mode != FM_RX_EMPHASIS_FILTER_75_USEC) {
+		FM_DRV_ERR("Invalid rx de-emphasis mode");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	FM_STORE_LE16_TO_BE16(payload, mode);
+	ret = fm_core_send_cmd(DEMPH_MODE_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Gets current RX de-emphasis filter mode */
+int fm_core_rx_get_deemphasis_mode(unsigned short *curr_deemphasis_mode)
+{
+	unsigned short curr_mode;
+	int ret, resp_len;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (curr_deemphasis_mode == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	ret = fm_core_send_cmd(DEMPH_MODE_GET, NULL, 2,
+			       &fmdev->maintask_completion, &curr_mode,
+			       &resp_len);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	*curr_deemphasis_mode = FM_BE16_TO_LE16(curr_mode);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Enable/Disable RX RDS */
+int fm_core_rx_set_rds_mode(unsigned char rds_en_dis)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (rds_en_dis != FM_RX_RDS_ENABLE && rds_en_dis != FM_RX_RDS_DISABLE) {
+		FM_DRV_ERR("Invalid rds option");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	if (rds_en_dis == FM_RX_RDS_ENABLE
+	    && fmdev->rx.rds.flag == FM_RX_RDS_DISABLE) {
+		/* Turn on RX RDS */
+		/* Turn on RDS circuit */
+		FM_STORE_LE16_TO_BE16(payload,
+				      FM_RX_POWET_SET_FM_AND_RDS_BLK_ON);
+		ret =
+		    fm_core_send_cmd(POWER_SET, &payload, sizeof(payload),
+				     &fmdev->maintask_completion, NULL, NULL);
+		FM_CHECK_SEND_CMD_STATUS(ret);
+
+		/* Clear and rest RDS FIFO */
+		FM_STORE_LE16_TO_BE16(payload, FM_RX_RDS_FLUSH_FIFO);
+		ret = fm_core_send_cmd(RDS_CNTRL_SET, &payload, sizeof(payload),
+				       &fmdev->maintask_completion, NULL, NULL);
+		FM_CHECK_SEND_CMD_STATUS(ret);
+
+		/* Read flags - just to clear any
+		 * pending interrupts if we had
+		 */
+		ret = fm_core_send_cmd(FLAG_GET, NULL, 2,
+				       &fmdev->maintask_completion, NULL, NULL);
+		FM_CHECK_SEND_CMD_STATUS(ret);
+
+		/* Set RDS FIFO threshold value */
+		FM_STORE_LE16_TO_BE16(payload, FM_RX_RDS_FIFO_THRESHOLD);
+		ret = fm_core_send_cmd(RDS_MEM_SET, &payload, sizeof(payload),
+				       &fmdev->maintask_completion, NULL, NULL);
+		FM_CHECK_SEND_CMD_STATUS(ret);
+
+		/* Enable RDS interrupt */
+		fmdev->irq_info.mask |= FM_RDS_EVENT;
+		FM_STORE_LE16_TO_BE16(payload, fmdev->irq_info.mask);
+		ret = fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload),
+				       &fmdev->maintask_completion, NULL, NULL);
+		FM_CHECK_SEND_CMD_STATUS(ret);
+
+		/* Update our local flag */
+		fmdev->rx.rds.flag = FM_RX_RDS_ENABLE;
+	} else if (rds_en_dis == FM_RX_RDS_DISABLE
+		   && fmdev->rx.rds.flag == FM_RX_RDS_ENABLE) {
+		/* Turn off RX RDS */
+		/* Turn off RDS circuit */
+		FM_STORE_LE16_TO_BE16(payload, FM_RX_POWER_SET_FM_ON_RDS_OFF);
+		ret = fm_core_send_cmd(POWER_SET, &payload, sizeof(payload),
+				       &fmdev->maintask_completion, NULL, NULL);
+		FM_CHECK_SEND_CMD_STATUS(ret);
+
+		/* Reset RDS pointers */
+		fmdev->rx.rds.last_block_index = 0;
+		fmdev->rx.rds.wr_index = 0;
+		fmdev->rx.rds.rd_index = 0;
+		fm_core_rx_reset_curr_station_info();
+
+		/* Update RDS local cache */
+		fmdev->irq_info.mask &= ~(FM_RDS_EVENT);
+		fmdev->rx.rds.flag = FM_RX_RDS_DISABLE;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_set_rds_mode(unsigned char rds_en_dis)
+{
+	int ret;
+
+	FMDRV_API_START();
+	switch (fmdev->curr_fmmode) {
+	case FM_MODE_RX:
+		ret = fm_core_rx_set_rds_mode(rds_en_dis);
+		break;
+
+	case FM_MODE_TX:
+		ret = fm_core_tx_set_rds_mode(rds_en_dis);
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+	FMDRV_API_EXIT(ret);
+	return ret;
+}
+
+/* Returns current RX RDS enable/disable status */
+int fm_core_rx_get_rds_mode(unsigned char *curr_rds_en_dis)
+{
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (curr_rds_en_dis == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	*curr_rds_en_dis = fmdev->rx.rds.flag;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Sets RDS operation mode (RDS/RDBS) */
+int fm_core_rx_set_rds_system(unsigned char rds_mode)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (rds_mode != FM_RDS_SYSTEM_RDS && rds_mode != FM_RDS_SYSTEM_RBDS) {
+		FM_DRV_ERR("Invalid rds mode");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	/* Set RDS operation mode */
+	FM_STORE_LE16_TO_BE16(payload, (unsigned short)rds_mode);
+	ret = fm_core_send_cmd(RDS_SYSTEM_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	fmdev->rx.rds_mode = rds_mode;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Returns current RDS operation mode */
+int fm_core_rx_get_rds_system(unsigned char *rds_mode)
+{
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (rds_mode == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	*rds_mode = fmdev->rx.rds_mode;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Sends power off command to the chip */
+int fm_core_power_down(void)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+	if (!test_bit(FM_CORE_READY, &fmdev->flag)) {
+		FM_DRV_ERR("FM core is not ready");
+		FMDRV_API_EXIT(-EPERM);
+		return -EPERM;
+	}
+	if (fmdev->curr_fmmode == FM_MODE_OFF) {
+		FM_DRV_ERR("FM chip is already in OFF state");
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+	/* Disable FM functions over Channel-8 */
+	FM_STORE_LE16_TO_BE16(payload, 0x0);
+	ret = fm_core_send_cmd(FM_POWER_MODE, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	/* Unlink from ST. FM GPIO toggling is taken
+	 * care in Shared Transport layer
+	 */
+	ret = fm_core_release();
+	if (ret < 0) {
+		FM_DRV_ERR("FM CORE release failed");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Configures Alternate Frequency switch mode */
+int fm_core_rx_set_af_switch(unsigned char af_mode)
+{
+	unsigned short payload;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (af_mode != FM_RX_RDS_AF_SWITCH_MODE_ON &&
+	    af_mode != FM_RX_RDS_AF_SWITCH_MODE_OFF) {
+		FM_DRV_ERR("Invalid af mode");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	/* Enable/disable low RSSI interrupt based on af_mode */
+	if (af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON)
+		fmdev->irq_info.mask |= FM_LEV_EVENT;
+	else
+		fmdev->irq_info.mask &= ~FM_LEV_EVENT;
+
+	FM_STORE_LE16_TO_BE16(payload, fmdev->irq_info.mask);
+	ret = fm_core_send_cmd(INT_MASK_SET, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	FM_CHECK_SEND_CMD_STATUS(ret);
+
+	fmdev->rx.af_mode = af_mode;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Returns Alternate Frequency switch status */
+int fm_core_rx_get_af_switch(unsigned char *af_mode)
+{
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_check_mode(FM_MODE_RX);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (af_mode == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	*af_mode = fmdev->rx.af_mode;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Reads init command from FM firmware file and loads to the chip */
+static int fm_core_download_firmware(const char *firmware_name)
+{
+	const struct firmware *fw_entry;
+	struct bts_header *fw_header;
+	struct bts_action *action;
+	struct bts_action_delay *delay;
+	char *fw_data;
+	int ret, fw_len, cmd_cnt;
+
+	FMDRV_API_START();
+
+	cmd_cnt = 0;
+	set_bit(FM_FIRMWARE_DW_INPROGRESS, &fmdev->flag);
+
+	/* Read firmware data */
+	ret = request_firmware(&fw_entry, firmware_name, &fmdev->v4l2dev->dev);
+	if (unlikely(ret)) {
+		FM_DRV_ERR("Unable to read firmware(%s) content\n",
+			   firmware_name);
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	FM_DRV_DBG("Firmware(%s) length : %d bytes", firmware_name,
+		   fw_entry->size);
+
+	fw_data = (void *)fw_entry->data;
+	fw_len = fw_entry->size;
+
+	/* Check TI's magic number in firmware file */
+	fw_header = (struct bts_header *)fw_data;
+	if (fw_header->magic != FM_FW_FILE_HEADER_MAGIC) {
+		release_firmware(fw_entry);
+		clear_bit(FM_FIRMWARE_DW_INPROGRESS, &fmdev->flag);
+		FM_DRV_ERR("%s not a legal TI firmware file", firmware_name);
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	FM_DRV_DBG("Firmware(%s) magic number : 0x%x", firmware_name,
+		   fw_header->magic);
+
+	/* Skip file header info , we already verified it */
+	fw_data += sizeof(struct bts_header);
+	fw_len -= sizeof(struct bts_header);
+
+	while (fw_data && fw_len > 0) {
+		action = (struct bts_action *)fw_data;
+
+		switch (action->type) {
+
+		case ACTION_SEND_COMMAND:	/* Send */
+
+			/* Send the command to chip */
+			ret = fm_core_send_cmd(0, action->data, action->size,
+					       &fmdev->maintask_completion,
+					       NULL, NULL);
+			if (unlikely(ret < 0)) {
+				release_firmware(fw_entry);
+				clear_bit(FM_FIRMWARE_DW_INPROGRESS,
+					  &fmdev->flag);
+				FMDRV_API_EXIT(ret);
+				return ret;
+			}
+			cmd_cnt++;
+			break;
+
+		case ACTION_DELAY:	/* Delay */
+			delay = (struct bts_action_delay *)action->data;
+			mdelay(delay->msec);
+			break;
+		}
+
+		fw_data += (sizeof(struct bts_action) + (action->size));
+		fw_len -= (sizeof(struct bts_action) + (action->size));
+	}
+
+	release_firmware(fw_entry);
+	clear_bit(FM_FIRMWARE_DW_INPROGRESS, &fmdev->flag);
+
+	FM_DRV_DBG("Firmare commands(%d) loaded to the chip", cmd_cnt);
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Loads default RX configuration to the chip */
+static int __fm_core_rx_load_default_configuration(void)
+{
+	int ret;
+	FMDRV_API_START();
+
+	/* Set default RX volume level */
+	ret = fm_core_rx_set_volume(FM_DEFAULT_RX_VOLUME);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Set default RX RSSI level threshold */
+	ret = fm_core_rx_set_rssi_threshold(FM_DEFAULT_RSSI_THRESHOLD);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Does FM power on sequence */
+static int fm_core_power_up(unsigned char fw_option)
+{
+	unsigned short payload, asic_id, asic_ver;
+	int resp_len, ret;
+	char fw_name[50];
+
+	FMDRV_API_START();
+	if (fw_option >= FM_MODE_ENTRY_MAX) {
+		FM_DRV_ERR("Invalid firmware download option");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	/* Initialize FM Core. FM GPIO toggling is
+	 * taken care in Shared Transport
+	 */
+	ret = fm_core_prepare();
+	if (ret < 0) {
+		FM_DRV_ERR("Unable to prepare FM CORE");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Enable Channel-8 communication on chip side. This is must for
+	 * reading ASIC ID and ASIC version of the chip.
+	 */
+	FM_STORE_LE16_TO_BE16(payload, FM_ENABLE);
+
+	ret = fm_core_send_cmd(FM_POWER_MODE, &payload, sizeof(payload),
+			       &fmdev->maintask_completion, NULL, NULL);
+	if (ret < 0) {
+		FM_DRV_ERR("Failed enable FM over Channel 8");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	/* Allow the chip to settle down in Channel-8 mode */
+	msleep(5);
+
+	/* Read ASIC ID */
+	ret = fm_core_send_cmd(ASIC_ID_GET, NULL, sizeof(asic_id),
+			       &fmdev->maintask_completion, &asic_id,
+			       &resp_len);
+	if (ret < 0) {
+		FM_DRV_ERR("Failed read FM chip ASIC ID");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Read ASIC version */
+	ret = fm_core_send_cmd(ASIC_VER_GET, NULL, sizeof(asic_ver),
+			       &fmdev->maintask_completion, &asic_ver,
+			       &resp_len);
+	if (ret < 0) {
+		FM_DRV_ERR("Failed read FM chip ASIC Version");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	FM_DRV_DBG("ASIC ID: 0x%x , ASIC Version: %d", FM_BE16_TO_LE16(asic_id),
+		   FM_BE16_TO_LE16(asic_ver));
+
+	/* Frame common firmware file name and load init commands */
+	sprintf(fw_name, "%s_%x.%d.bts", FM_FMC_FW_FILE_START,
+		FM_BE16_TO_LE16(asic_id), FM_BE16_TO_LE16(asic_ver));
+	ret = fm_core_download_firmware(fw_name);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Frame TX or RX firmware file name
+	 * based on request and load init commands.
+	 */
+	sprintf(fw_name, "%s_%x.%d.bts", (fw_option == FM_MODE_RX) ?
+		FM_RX_FW_FILE_START : FM_TX_FW_FILE_START,
+		FM_BE16_TO_LE16(asic_id), FM_BE16_TO_LE16(asic_ver));
+	ret = fm_core_download_firmware(fw_name);
+	if (ret < 0) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* ----- Fucntions exported to FM mixer control layer ----- */
+
+/* All the functions which are exported from this file
+ * to FM mixer controls layer will check FM Core ready
+ * status. If FM Core is not ready, it will return
+ * immediately with an error.
+ */
+
+/* Set FM Modes(TX, RX, OFF) */
+int fm_core_mode_set(unsigned char fm_mode)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	if (fm_mode >= FM_MODE_ENTRY_MAX) {
+		FM_DRV_ERR("Invalid FM mode");
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	if (fmdev->curr_fmmode == fm_mode) {
+		FM_DRV_DBG("Already fm is in mode(%d)", fm_mode);
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+	switch (fm_mode) {
+	case FM_MODE_OFF:	/* OFF Mode */
+		ret = fm_core_power_down();
+		if (ret < 0) {
+			FM_DRV_ERR("Failed to set OFF mode");
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+		break;
+
+	case FM_MODE_TX:	/* TX Mode */
+	case FM_MODE_RX:	/* RX Mode */
+		/* Power down before switching to TX or RX mode */
+		if (fmdev->curr_fmmode != FM_MODE_OFF) {
+			ret = fm_core_power_down();
+			if (ret < 0) {
+				FM_DRV_ERR("Failed to set OFF mode");
+				FMDRV_API_EXIT(ret);
+				return ret;
+			}
+			msleep(30);
+		}
+		/* Load requested mode's firmware */
+		ret = fm_core_power_up(fm_mode);
+		if (ret < 0) {
+			FM_DRV_ERR("Failed to load firmware\n");
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+	}
+	/* Set current mode */
+	fmdev->curr_fmmode = fm_mode;
+
+	/* Set default configuration */
+	if (fmdev->curr_fmmode == FM_MODE_RX) {
+		FM_DRV_DBG("Loading default rx configuration..\n");
+		ret = __fm_core_rx_load_default_configuration();
+		if (ret < 0) {
+			FM_DRV_ERR("Failed to load default values\n");
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Returns current FM mode (TX, RX, OFF) */
+int fm_core_mode_get(unsigned char *fmmode)
+{
+	FMDRV_API_START();
+
+	if (!test_bit(FM_CORE_READY, &fmdev->flag)) {
+		FM_DRV_ERR("FM core is not ready");
+		return -EPERM;
+	}
+	if (fmmode == NULL) {
+		FM_DRV_ERR("Invalid memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+
+	*fmmode = fmdev->curr_fmmode;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* ----------------- FM Core Init -------------- */
+
+/* This function will be called from FM V4L2 open function.
+ * This will request FM ST interface to register with ST driver.
+ */
+int fm_core_prepare(void)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	if (test_bit(FM_CORE_READY, &fmdev->flag)) {
+		FM_DRV_DBG("FM Core is already up");
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+	if (!test_bit(FM_CORE_TRANSPORT_READY, &fmdev->flag)) {
+		FM_DRV_ERR("FM Core transport is not ready");
+		FMDRV_API_EXIT(-EPERM);
+		return -EPERM;
+	}
+
+	/* Request FM ST to get register with ST driver. Send FM Core RX
+	 * queue and RX tasklet pointers to FM ST. FM ST will push
+	 * received FM packet into this queue and schedule this RX
+	 * tasklet.
+	 */
+	ret = fm_st_register(&fmdev->rx_q, &fmdev->rx_task);
+	if (ret < 0) {
+		fm_st_release();
+		FM_DRV_ERR("Unable to register with ST");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	spin_lock_init(&fmdev->rds_buff_lock);
+	spin_lock_init(&fmdev->resp_skb_lock);
+
+	/* Initialize TX queue and TX tasklet */
+	skb_queue_head_init(&fmdev->tx_q);
+	tasklet_init(&fmdev->tx_task, fm_core_tx_tasklet, (unsigned long)fmdev);
+
+	/* Initialize RX Queue and RX tasklet */
+	skb_queue_head_init(&fmdev->rx_q);
+	tasklet_init(&fmdev->rx_task, fm_core_rx_tasklet, (unsigned long)fmdev);
+
+	/* Initialize interrupt related info */
+	fmdev->irq_info.stage_index = 0;
+
+	/* Number of packet can send at a time */
+	atomic_set(&fmdev->tx_cnt, 1);
+
+	fmdev->response_completion = NULL;
+
+	init_timer(&fmdev->irq_info.int_timeout_timer);
+	fmdev->irq_info.int_timeout_timer.function =
+	    &fm_core_int_timeout_handler;
+
+	/* Default interrupt bits to be enabled */
+	fmdev->irq_info.mask =
+	    FM_MAL_EVENT /*| FM_STIC_EVENT <<Enable this later>> */ ;
+
+	/* Region info */
+	memcpy(&fmdev->rx.region, &region_configs[default_radio_region],
+	       sizeof(struct region_info));
+
+	fmdev->rx.curr_mute_mode = FM_MUTE_OFF;
+	fmdev->rx.curr_rf_depend_mute = FM_RX_RF_DEPENDENT_MUTE_OFF;
+	fmdev->rx.rds.flag = FM_RX_RDS_DISABLE;
+	fmdev->rx.curr_freq = FM_UNDEFINED_FREQ;
+	fmdev->rx.rds_mode = FM_RDS_SYSTEM_RDS;
+	fmdev->rx.af_mode = FM_RX_RDS_AF_SWITCH_MODE_OFF;
+	fmdev->irq_info.irq_service_timeout_retry = 0;
+
+	/* RDS ring buffer */
+	fm_core_rx_reset_rds_cache();
+	init_waitqueue_head(&fmdev->rx.rds.read_queue);
+
+	/* Current station info */
+	fm_core_rx_reset_curr_station_info();
+
+	/* FM core is ready */
+	set_bit(FM_CORE_READY, &fmdev->flag);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* -------------- FM Core De-Init ------------- */
+
+/* This function will be called from FM V4L2 release function.
+ * This will request FM ST interface to unregister from ST driver.
+ */
+int fm_core_release(void)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	if (!test_bit(FM_CORE_READY, &fmdev->flag)) {
+		FM_DRV_DBG("FM Core is already down");
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+	/* Sevice pending read */
+	wake_up_interruptible(&fmdev->rx.rds.read_queue);
+
+	/* Stop all tasklets */
+	tasklet_kill(&fmdev->tx_task);
+	tasklet_kill(&fmdev->rx_task);
+
+	/* Flush Tx and Rx queues */
+	skb_queue_purge(&fmdev->tx_q);
+	skb_queue_purge(&fmdev->rx_q);
+
+	fmdev->response_completion = NULL;
+	fmdev->rx.curr_freq = 0;
+
+	/* Unlink from Shared Transport driver */
+	ret = fm_st_unregister();
+	if (ret < 0) {
+		FM_DRV_ERR("Unable to unregister from ST");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	FM_DRV_DBG("Successfully unregistered from ST");
+
+	/* Clear FM Core ready flag */
+	clear_bit(FM_CORE_READY, &fmdev->flag);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_setup_transport(void)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	if (test_bit(FM_CORE_TRANSPORT_READY, &fmdev->flag)) {
+		FM_DRV_ERR("FM Core transport is already up");
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+	/* Check availabilty of FM ST. If FM ST is already claimed
+	 * by FM Char device interface, don't proceed. Both FM Core
+	 * and FM Char device interface can't co-exist.
+	 */
+	ret = fm_st_claim();
+	if (ret < 0) {
+		FM_DRV_ERR
+		    ("FM char device interface is using FM ST, can't coexist");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	set_bit(FM_CORE_TRANSPORT_READY, &fmdev->flag);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_core_release_transport(void)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	if (!test_bit(FM_CORE_TRANSPORT_READY, &fmdev->flag)) {
+		FM_DRV_ERR("FM Core transport is already down");
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+
+	/* Release FM ST */
+	ret = fm_st_release();
+	if (ret < 0) {
+		FM_DRV_ERR("Failed to release FM ST");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	clear_bit(FM_CORE_TRANSPORT_READY, &fmdev->flag);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* ----------- Module Init interface --------- */
+
+static int __init fm_drv_init(void)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = 0;
+
+	FM_DRV_DBG("FM driver version %s", FM_DRV_VERSION);
+
+	/* Allocate local resource memory */
+	fmdev = kzalloc(sizeof(struct fmdrv_ops), GFP_KERNEL);
+	if (!fmdev) {
+		FM_DRV_ERR("Can't allocate operation structure memory");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	fmdev->rx.rds.buf_size = default_rds_buf * FM_RDS_BLOCK_SIZE;
+
+	/* Allocate memory for RDS ring buffer */
+	fmdev->rx.rds.buffer = kzalloc(fmdev->rx.rds.buf_size, GFP_KERNEL);
+	if (fmdev->rx.rds.buffer == NULL) {
+		kfree(fmdev);
+		FM_DRV_ERR("Can't allocate rds ring buffer");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+
+	/* Register with V4L2 subsystem. This will internally
+	 * expose '/dev/radio' device to user space.
+	 */
+	ret = fm_v4l2_init_video_device(fmdev);
+	if (ret < 0) {
+		kfree(fmdev);
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	/* Register with ALSA subsystem. This will internally expose
+	 * set of FM mixer controls via ALSA to user space.
+	 */
+	ret = fm_mixer_init(fmdev);
+	if (ret < 0) {
+		/* Unregister from V4L2 subsystem */
+		fm_v4l2_deinit_video_device(fmdev);
+
+		kfree(fmdev);
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	/* Initialize the FM Character driver */
+	ret = fm_chr_init();
+	if (ret < 0) {
+		FM_DRV_ERR("Can't init FM Character driver");
+		FMDRV_API_EXIT(0);
+		return ret;
+	}
+
+	/* Assign interrupt handling table pointer */
+	fmdev->irq_info.fm_IntActionHandlerTable = g_IntHandlerTable;
+
+	/* Default FM driver mode */
+	fmdev->curr_fmmode = FM_MODE_OFF;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* -------- Module Exit interface -------- */
+
+static void __exit fm_drv_exit(void)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = 0;
+
+	/* Unregister from V4L2 subsystem */
+	ret = fm_v4l2_deinit_video_device(fmdev);
+	if (ret < 0)
+		FM_DRV_ERR("Unable to unregister from V4L2 subsystem(%d)", ret);
+
+	/* Unregister from ALSA subsystem */
+	ret = fm_mixer_deinit(fmdev);
+	if (ret < 0)
+		FM_DRV_ERR("Unable to unregister from ALSA(%d)", ret);
+
+	/* De-initialize the FM Character driver */
+	fm_chr_exit();
+
+	kfree(fmdev->rx.rds.buffer);
+	kfree(fmdev);
+
+	FMDRV_API_EXIT(0);
+}
+
+module_init(fm_drv_init);
+module_exit(fm_drv_exit);
+
+/* ------------- Module Info ------------- */
+
+MODULE_AUTHOR("Raja Mani <raja_mani@ti.com>");
+MODULE_DESCRIPTION("FM Driver for Connectivity chip of Texas Instruments. "
+		   FM_DRV_VERSION);
+MODULE_VERSION(FM_DRV_VERSION);
+MODULE_LICENSE("GPL");
diff --git a/drivers/misc/ti-st/fmdrv_core.h b/drivers/misc/ti-st/fmdrv_core.h
new file mode 100644
index 000000000000..0f33bf7cd883
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_core.h
@@ -0,0 +1,474 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  FM Core module header file
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _FM_CORE_H
+#define _FM_CORE_H
+
+#define REG_RD       0x1
+#define REG_WR      0x0
+
+struct fm_reg_table {
+	unsigned char opcode;
+	unsigned char type;
+	char *name;
+};
+
+/* FM register index */
+enum fm_reg_index {
+	/* FM RX registers */
+	STEREO_GET,
+	RSSI_LVL_GET,
+	IF_COUNT_GET,
+	FLAG_GET,
+	RDS_SYNC_GET,
+	RDS_DATA_GET,
+	FREQ_SET,
+	FREQ_GET,
+	AF_FREQ_SET,
+	AF_FREQ_GET,
+	MOST_MODE_SET,
+	MOST_MODE_GET,
+	MOST_BLEND_SET,
+	MOST_BLEND_GET,
+	DEMPH_MODE_SET,
+	DEMPH_MODE_GET,
+	SEARCH_LVL_SET,
+	SEARCH_LVL_GET,
+	RX_BAND_SET,
+	RX_BAND_GET,
+	MUTE_STATUS_SET,
+	MUTE_STATUS_GET,
+	RDS_PAUSE_LVL_SET,
+	RDS_PAUSE_LVL_GET,
+	RDS_PAUSE_DUR_SET,
+	RDS_PAUSE_DUR_GET,
+	RDS_MEM_SET,
+	RDS_MEM_GET,
+	RDS_BLK_B_SET,
+	RDS_BLK_B_GET,
+	RDS_MSK_B_SET,
+	RDS_MSK_B_GET,
+	RDS_PI_MASK_SET,
+	RDS_PI_MASK_GET,
+	RDS_PI_SET,
+	RDS_PI_GET,
+	RDS_SYSTEM_SET,
+	RDS_SYSTEM_GET,
+	INT_MASK_SET,
+	INT_MASK_GET,
+	SEARCH_DIR_SET,
+	SEARCH_DIR_GET,
+	VOLUME_SET,
+	VOLUME_GET,
+	AUDIO_ENABLE_SET,
+	AUDIO_ENABLE_GET,
+	PCM_MODE_SET,
+	PCM_MODE_GET,
+	I2S_MODE_CONFIG_SET,
+	I2S_MODE_CONFIG_GET,
+	POWER_SET,
+	POWER_GET,
+	INTx_CONFIG_SET,
+	INTx_CONFIG_GET,
+	PULL_EN_SET,
+	PULL_EN_GET,
+	HILO_SET,
+	HILO_GET,
+	SWITCH2FREF,
+	FREQ_DRIFT_REPORT,
+	PCE_GET,
+	FIRM_VER_GET,
+	ASIC_VER_GET,
+	ASIC_ID_GET,
+	MAIN_ID_GET,
+	TUNER_MODE_SET,
+	STOP_SEARCH,
+	RDS_CNTRL_SET,
+	WRITE_HARDWARE_REG,
+	CODE_DOWNLOAD,
+	RESET,
+	FM_POWER_MODE,
+	FM_INTERRUPT,
+
+	/* FM TX registers */
+	CHANL_SET,
+	CHANL_GET,
+	CHANL_BW_SET,
+	CHANL_BW_GET,
+	REF_SET,
+	REF_GET,
+	POWER_ENB_SET,
+	POWER_ATT_SET,
+	POWER_ATT_GET,
+	POWER_LEL_SET,
+	POWER_LEL_GET,
+	AUDIO_DEV_SET,
+	AUDIO_DEV_GET,
+	PILOT_DEV_SET,
+	PILOT_DEV_GET,
+	RDS_DEV_SET,
+	RDS_DEV_GET,
+	PUPD_SET,
+	AUDIO_IO_SET,
+	PREMPH_SET,
+	PREMPH_GET,
+	TX_BAND_SET,
+	TX_BAND_GET,
+	MONO_SET,
+	MONO_GET,
+	MUTE,
+	MPX_LMT_ENABLE,
+	LOCK_GET,
+	REF_ERR_SET,
+	PI_SET,
+	PI_GET,
+	TYPE_SET,
+	TYPE_GET,
+	PTY_SET,
+	PTY_GET,
+	AF_SET,
+	AF_GET,
+	DISPLAY_SIZE_SET,
+	DISPLAY_SIZE_GET,
+	RDS_MODE_SET,
+	RDS_MODE_GET,
+	DISPLAY_MODE_SET,
+	DISPLAY_MODE_GET,
+	LENGHT_SET,
+	LENGHT_GET,
+	TOGGLE_AB_SET,
+	TOGGLE_AB_GET,
+	RDS_REP_SET,
+	RDS_REP_GET,
+	RDS_DATA_SET,
+	RDS_DATA_ENB,
+	TA_SET,
+	TA_GET,
+	TP_SET,
+	TP_GET,
+	DI_SET,
+	DI_GET,
+	MS_SET,
+	MS_GET,
+	PS_SCROLL_SPEED_SET,
+	PS_SCROLL_SPEED_GET,
+
+	FM_REG_MAX_ENTRIES
+};
+
+/* SKB helpers */
+struct fm_skb_cb {
+	__u8 fm_opcode;
+	struct completion *completion;
+};
+
+#define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb))
+
+/* FM Channel-8 command message format */
+struct fm_cmd_msg_hdr {
+	__u8 header;		/* Logical Channel-8 */
+	__u8 len;		/* Number of bytes follows */
+	__u8 fm_opcode;		/* FM Opcode */
+	__u8 rd_wr;		/* Read/Write command */
+	__u8 dlen;		/* Length of payload */
+} __attribute__ ((packed));
+
+#define FM_CMD_MSG_HDR_SIZE    5	/* sizeof(struct fm_cmd_msg_hdr) */
+
+/* FM Channel-8 event messgage format */
+struct fm_event_msg_hdr {
+	__u8 header;		/* Logical Channel-8 */
+	__u8 len;		/* Number of bytes follows */
+	__u8 status;		/* Event status */
+	__u8 num_fm_hci_cmds;	/* Number of pkts the host allowed to send */
+	__u8 fm_opcode;		/* FM Opcode */
+	__u8 rd_wr;		/* Read/Write command */
+	__u8 dlen;		/* Length of payload */
+} __attribute__ ((packed));
+
+#define FM_EVT_MSG_HDR_SIZE     7	/* sizeof(struct fm_event_msg_hdr) */
+
+/* TI's magic number in firmware file */
+#define FM_FW_FILE_HEADER_MAGIC	     0x42535442
+
+/* Firmware header */
+struct bts_header {
+	uint32_t magic;
+	uint32_t version;
+	uint8_t future[24];
+	uint8_t actions[0];
+} __attribute__ ((packed));
+
+/* Firmware action */
+struct bts_action {
+	uint16_t type;
+	uint16_t size;
+	uint8_t data[0];
+} __attribute__ ((packed));
+
+/* Firmware delay */
+struct bts_action_delay {
+	uint32_t msec;
+} __attribute__ ((packed));
+
+#define ACTION_SEND_COMMAND	1
+#define ACTION_WAIT_EVENT	2
+#define ACTION_SERIAL		3
+#define ACTION_DELAY		4
+#define ACTION_REMARKS		6
+
+/* Converts little endian to big endian */
+#define FM_STORE_LE16_TO_BE16(data, value)   \
+	(data = ((value >> 8) | ((value & 0xFF) << 8)))
+#define FM_LE16_TO_BE16(value)   (((value >> 8) | ((value & 0xFF) << 8)))
+
+/* Converts big endian to little endian */
+#define FM_STORE_BE16_TO_LE16(data, value)   \
+	(data = ((value & 0xFF) << 8) | ((value >> 8)))
+#define FM_BE16_TO_LE16(value)   (((value & 0xFF) << 8) | ((value >> 8)))
+
+#define FM_ENABLE   1
+#define FM_DISABLE  0
+
+/* FLAG_GET register bits */
+#define FM_FR_EVENT		(1 << 0)
+#define FM_BL_EVENT		(1 << 1)
+#define FM_RDS_EVENT		(1 << 2)
+#define FM_BBLK_EVENT		(1 << 3)
+#define FM_LSYNC_EVENT		(1 << 4)
+#define FM_LEV_EVENT		(1 << 5)
+#define FM_IFFR_EVENT		(1 << 6)
+#define FM_PI_EVENT		(1 << 7)
+#define FM_PD_EVENT		(1 << 8)
+#define FM_STIC_EVENT		(1 << 9)
+#define FM_MAL_EVENT		(1 << 10)
+#define FM_POW_ENB_EVENT	(1 << 11)
+
+/* Firmware files of the FM, ASIC ID and
+ * ASIC version will be appened to this later
+ */
+#define FM_FMC_FW_FILE_START      ("fmc_ch8")
+#define FM_RX_FW_FILE_START       ("fm_rx_ch8")
+#define FM_TX_FW_FILE_START       ("fm_tx_ch8")
+
+#define FM_CHECK_SEND_CMD_STATUS(ret)  \
+	if (ret < 0) {\
+		FMDRV_API_EXIT(ret);\
+		return ret;\
+	}
+#define FM_UNDEFINED_FREQ		   0xFFFFFFFF
+
+/* Band types */
+#define FM_BAND_EUROPE_US		0
+#define FM_BAND_JAPAN			1
+
+/* Seek directions */
+#define FM_SEARCH_DIRECTION_DOWN	0
+#define FM_SEARCH_DIRECTION_UP		1
+
+/* Tunner modes */
+#define FM_TUNER_STOP_SEARCH_MODE          0
+#define FM_TUNER_PRESET_MODE               1
+#define FM_TUNER_AUTONOMOUS_SEARCH_MODE    2
+#define FM_TUNER_AF_JUMP_MODE              3
+
+/* Min and Max volume */
+#define FM_RX_VOLUME_MIN		0
+#define FM_RX_VOLUME_MAX		70
+
+/* Volume gain step */
+#define FM_RX_VOLUME_GAIN_STEP		0x370
+
+/* Mute modes */
+#define	FM_MUTE_OFF			0
+#define	FM_MUTE_ON			1
+#define	FM_MUTE_ATTENUATE		 2
+
+#define FM_RX_MUTE_UNMUTE_MODE		 0x00
+#define FM_RX_MUTE_RF_DEP_MODE		 0x01
+#define FM_RX_MUTE_AC_MUTE_MODE		 0x02
+#define FM_RX_MUTE_HARD_MUTE_LEFT_MODE	 0x04
+#define FM_RX_MUTE_HARD_MUTE_RIGHT_MODE	 0x08
+#define FM_RX_MUTE_SOFT_MUTE_FORCE_MODE	 0x10
+
+/* RF dependent mute mode */
+#define FM_RX_RF_DEPENDENT_MUTE_ON		1
+#define FM_RX_RF_DEPENDENT_MUTE_OFF		0
+
+/* RSSI threshold min and max */
+#define FM_RX_RSSI_THRESHOLD_MIN       -128
+#define FM_RX_RSSI_THRESHOLD_MAX	127
+
+/* Stereo/Mono mode */
+#define FM_STEREO_MODE			0
+#define FM_MONO_MODE			1
+#define FM_STEREO_SOFT_BLEND		1
+
+/* FM RX De-emphasis filter modes */
+#define FM_RX_EMPHASIS_FILTER_50_USEC	0
+#define FM_RX_EMPHASIS_FILTER_75_USEC	1
+
+/* FM RX RDS modes */
+#define FM_RX_RDS_DISABLE		0
+#define FM_RX_RDS_ENABLE		1
+
+#define FM_NO_PI_CODE			0
+
+/* FM and RX RDS block enable/disable  */
+#define FM_RX_POWER_SET_FM_ON_RDS_OFF        0x1
+#define FM_RX_POWET_SET_FM_AND_RDS_BLK_ON    0x3
+#define FM_RX_POWET_SET_FM_AND_RDS_BLK_OFF   0x0
+
+/* RX RDS */
+#define FM_RX_RDS_FLUSH_FIFO			0x1
+#define FM_RX_RDS_FIFO_THRESHOLD             64	/* tuples */
+#define FM_RDS_BLOCK_SIZE		     3	/* 3 bytes */
+
+/* RDS block types */
+#define FM_RDS_BLOCK_A			    0
+#define FM_RDS_BLOCK_B			    1
+#define FM_RDS_BLOCK_C			    2
+#define FM_RDS_BLOCK_Ctag		    3
+#define FM_RDS_BLOCK_D			    4
+#define FM_RDS_BLOCK_E			    5
+
+#define FM_RDS_BLOCK_INDEX_A		    0
+#define FM_RDS_BLOCK_INDEX_B		    1
+#define FM_RDS_BLOCK_INDEX_C		    2
+#define FM_RDS_BLOCK_INDEX_D		    3
+#define FM_RDS_BLOCK_INDEX_UNKNOWN          0xF0
+
+#define FM_RDS_STATUS_ERROR_MASK	    0x18
+
+/* Represents an RDS group type & version.
+ * There are 15 groups, each group has 2
+ * versions: A and B.
+ */
+#define FM_RDS_GROUP_TYPE_MASK_0A	    ((unsigned long)1<<0)
+#define FM_RDS_GROUP_TYPE_MASK_0B	    ((unsigned long)1<<1)
+#define FM_RDS_GROUP_TYPE_MASK_1A	    ((unsigned long)1<<2)
+#define FM_RDS_GROUP_TYPE_MASK_1B	    ((unsigned long)1<<3)
+#define FM_RDS_GROUP_TYPE_MASK_2A	    ((unsigned long)1<<4)
+#define FM_RDS_GROUP_TYPE_MASK_2B	    ((unsigned long)1<<5)
+#define FM_RDS_GROUP_TYPE_MASK_3A	    ((unsigned long)1<<6)
+#define FM_RDS_GROUP_TYPE_MASK_3B           ((unsigned long)1<<7)
+#define FM_RDS_GROUP_TYPE_MASK_4A	    ((unsigned long)1<<8)
+#define FM_RDS_GROUP_TYPE_MASK_4B	    ((unsigned long)1<<9)
+#define FM_RDS_GROUP_TYPE_MASK_5A	    ((unsigned long)1<<10)
+#define FM_RDS_GROUP_TYPE_MASK_5B	    ((unsigned long)1<<11)
+#define FM_RDS_GROUP_TYPE_MASK_6A	    ((unsigned long)1<<12)
+#define FM_RDS_GROUP_TYPE_MASK_6B	    ((unsigned long)1<<13)
+#define FM_RDS_GROUP_TYPE_MASK_7A	    ((unsigned long)1<<14)
+#define FM_RDS_GROUP_TYPE_MASK_7B	    ((unsigned long)1<<15)
+#define FM_RDS_GROUP_TYPE_MASK_8A           ((unsigned long)1<<16)
+#define FM_RDS_GROUP_TYPE_MASK_8B	    ((unsigned long)1<<17)
+#define FM_RDS_GROUP_TYPE_MASK_9A	    ((unsigned long)1<<18)
+#define FM_RDS_GROUP_TYPE_MASK_9B	    ((unsigned long)1<<19)
+#define FM_RDS_GROUP_TYPE_MASK_10A	    ((unsigned long)1<<20)
+#define FM_RDS_GROUP_TYPE_MASK_10B	    ((unsigned long)1<<21)
+#define FM_RDS_GROUP_TYPE_MASK_11A	    ((unsigned long)1<<22)
+#define FM_RDS_GROUP_TYPE_MASK_11B	    ((unsigned long)1<<23)
+#define FM_RDS_GROUP_TYPE_MASK_12A	    ((unsigned long)1<<24)
+#define FM_RDS_GROUP_TYPE_MASK_12B	    ((unsigned long)1<<25)
+#define FM_RDS_GROUP_TYPE_MASK_13A	    ((unsigned long)1<<26)
+#define FM_RDS_GROUP_TYPE_MASK_13B	    ((unsigned long)1<<27)
+#define FM_RDS_GROUP_TYPE_MASK_14A	    ((unsigned long)1<<28)
+#define FM_RDS_GROUP_TYPE_MASK_14B	    ((unsigned long)1<<29)
+#define FM_RDS_GROUP_TYPE_MASK_15A	    ((unsigned long)1<<30)
+#define FM_RDS_GROUP_TYPE_MASK_15B	    ((unsigned long)1<<31)
+
+/* RX Alternate Frequency info */
+#define FM_RDS_MIN_AF		          1
+#define FM_RDS_MAX_AF		        204
+#define FM_RDS_MAX_AF_JAPAN	        140
+#define FM_RDS_1_AF_FOLLOWS	        225
+#define FM_RDS_25_AF_FOLLOWS	        249
+
+/* RDS system type (RDS/RBDS) */
+#define FM_RDS_SYSTEM_RDS		0
+#define FM_RDS_SYSTEM_RBDS		1
+
+/* AF on/off */
+#define FM_RX_RDS_AF_SWITCH_MODE_ON	1
+#define FM_RX_RDS_AF_SWITCH_MODE_OFF	0
+
+/* Retry count when interrupt process goes wrong */
+#define FM_IRQ_TIMEOUT_RETRY_MAX	5	/* 5 times */
+
+/* Audio IO set values */
+#define FM_RX_FM_AUDIO_ENABLE_I2S		0x01
+#define FM_RX_FM_AUDIO_ENABLE_ANALOG	       0x02
+#define FM_RX_FM_AUDIO_ENABLE_I2S_AND_ANALOG   0x03
+#define FM_RX_FM_AUDIO_ENABLE_DISABLE	       0x00
+
+/* HI/LO set values */
+#define FM_RX_IFFREQ_TO_HI_SIDE                0x0
+#define FM_RX_IFFREQ_TO_LO_SIDE                0x1
+#define FM_RX_IFFREQ_HILO_AUTOMATIC            0x2
+
+/* Default RX mode configuration. Chip will be configured
+ * with this default values after loading RX firmware.
+ */
+#define FM_DEFAULT_RX_VOLUME		10
+#define FM_DEFAULT_RSSI_THRESHOLD	3
+
+/* Functions exported to FM V4L2 layer */
+int fm_core_prepare(void);
+int fm_core_release(void);
+int fm_core_setup_transport(void);
+int fm_core_release_transport(void);
+int fm_core_is_rds_data_available(struct file *, struct poll_table_struct *);
+int fm_core_transfer_rds_from_internal_buff(struct file *,
+					    char __user *, size_t);
+int fm_core_set_frequency(unsigned int);
+int fm_core_get_frequency(unsigned int *);
+int fm_core_rx_get_rssi_level(unsigned short *);
+int fm_core_rx_seek(unsigned int, unsigned int);
+int fm_core_rx_set_volume(unsigned short);
+int fm_core_rx_get_volume(unsigned short *);
+int fm_core_region_get(unsigned char *);
+int fm_core_region_set(unsigned char);
+int fm_core_rx_get_currband_lowhigh_freq(unsigned int *, unsigned int *);
+int fm_core_rx_get_mute_mode(unsigned char *);
+int fm_core_set_mute_mode(unsigned char);
+int fm_core_rx_get_rfdepend_softmute(unsigned char *);
+int fm_core_rx_set_rfdepend_softmute(unsigned char);
+int fm_core_rx_set_rssi_threshold(short);
+int fm_core_rx_get_rssi_threshold(short *);
+int fm_core_set_stereo_mono(unsigned short);
+int fm_core_rx_get_stereo_mono(unsigned short *);
+int fm_core_rx_set_deemphasis_mode(unsigned short);
+int fm_core_rx_get_deemphasis_mode(unsigned short *);
+int fm_core_rx_get_rds_mode(unsigned char *);
+int fm_core_set_rds_mode(unsigned char);
+int fm_core_rx_set_rds_system(unsigned char);
+int fm_core_rx_get_rds_system(unsigned char *);
+int fm_core_rx_set_af_switch(unsigned char);
+int fm_core_rx_get_af_switch(unsigned char *);
+
+int fm_core_mode_set(unsigned char);
+int fm_core_mode_get(unsigned char *);
+
+int fm_core_tx_set_pwr_lvl(unsigned char new_pwr_lvl);
+int fm_core_tx_set_radio_text(unsigned char *, unsigned char);
+int fm_core_tx_set_af(unsigned int);
+#endif
diff --git a/drivers/misc/ti-st/fmdrv_mixer.c b/drivers/misc/ti-st/fmdrv_mixer.c
new file mode 100644
index 000000000000..64f020d2681b
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_mixer.c
@@ -0,0 +1,724 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  This file manages FM driver's ALSA mixer controls.
+ *
+ *  The standard V4L2 subsystem provides limited V4L2 IOCTLs
+ *  to perform FM operation. So, this module will expose
+ *  some of mixer controls (ex., Band Selection,
+ *  FM TX/RX Mode Switch, etc) via ALSA to user space.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <linux/version.h>
+#include <sound/core.h>
+#include <sound/control.h>
+
+#include "fmdrv.h"
+#include "fmdrv_mixer.h"
+#include "fmdrv_core.h"
+
+static int fm_mixer_mode_info(struct snd_kcontrol *kcontrol,
+			      struct snd_ctl_elem_info *uinfo)
+{
+	static char *fm_modes[] = { "Off", "Tx", "Rx" };
+
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = 3;
+	if (uinfo->value.enumerated.item > 2)
+		uinfo->value.enumerated.item = 2;
+	strcpy(uinfo->value.enumerated.name,
+	       fm_modes[uinfo->value.enumerated.item]);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_mode_get(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	int ret;
+	unsigned char current_fmmode;
+
+	FMDRV_API_START();
+	ret = fm_core_mode_get(&current_fmmode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ucontrol->value.enumerated.item[0] = current_fmmode & 3;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_mode_put(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	int changed;
+	unsigned char mode;
+	int ret;
+
+	FMDRV_API_START();
+
+	mode = ucontrol->value.integer.value[0] & 3;
+	ret = fm_core_mode_set(mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static int fm_mixer_region_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	static char *region[] = { "Europe/US", "Japan" };
+
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = 2;
+	if (uinfo->value.enumerated.item > 1)
+		uinfo->value.enumerated.item = 1;
+	strcpy(uinfo->value.enumerated.name,
+	       region[uinfo->value.enumerated.item]);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_region_get(struct snd_kcontrol *kcontrol,
+			       struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned char region;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_region_get(&region);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ucontrol->value.enumerated.item[0] = region & 0x1;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_region_put(struct snd_kcontrol *kcontrol,
+			       struct snd_ctl_elem_value *ucontrol)
+{
+	int ret;
+	unsigned char region;
+	int changed;
+
+	FMDRV_API_START();
+
+	region = ucontrol->value.integer.value[0] & 0x1;
+	ret = fm_core_region_set(region);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static int fm_mixer_rfdepend_mute_info(struct snd_kcontrol *kcontrol,
+				       struct snd_ctl_elem_info *uinfo)
+{
+	static char *region[] = { "Off", "On" };
+
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = 2;
+	if (uinfo->value.enumerated.item > 1)
+		uinfo->value.enumerated.item = 1;
+	strcpy(uinfo->value.enumerated.name,
+	       region[uinfo->value.enumerated.item]);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rfdepend_mute_get(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned char en_dis;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_rx_get_rfdepend_softmute(&en_dis);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ucontrol->value.enumerated.item[0] = en_dis & 0x1;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rfdepend_mute_put(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned char en_dis;
+	int changed, ret;
+
+	FMDRV_API_START();
+
+	en_dis = ucontrol->value.integer.value[0] & 0x1;
+	ret = fm_core_rx_set_rfdepend_softmute(en_dis);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static int fm_mixer_rssi_level_info(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_info *uinfo)
+{
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = -16;
+	uinfo->value.integer.max = 15;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rssi_level_get(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned short curr_rssi_lvl;
+	int ret;
+	FMDRV_API_START();
+
+	ret = fm_core_rx_get_rssi_level(&curr_rssi_lvl);
+	if (ret)
+		return ret;
+
+	ucontrol->value.integer.value[0] = curr_rssi_lvl;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_rssi_threshold_info(struct snd_kcontrol *kcontrol,
+					   struct snd_ctl_elem_info *uinfo)
+{
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = -16;
+	uinfo->value.integer.max = 15;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_rssi_threshold_get(struct snd_kcontrol *kcontrol,
+					  struct snd_ctl_elem_value *ucontrol)
+{
+	short curr_rssi_threshold;
+	int ret;
+	FMDRV_API_START();
+
+	ret = fm_core_rx_get_rssi_threshold(&curr_rssi_threshold);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	ucontrol->value.integer.value[0] = curr_rssi_threshold;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_rssi_threshold_put(struct snd_kcontrol *kcontrol,
+					  struct snd_ctl_elem_value *ucontrol)
+{
+	short rssi_threshold_toset;
+	int changed, ret;
+
+	FMDRV_API_START();
+
+	rssi_threshold_toset = ucontrol->value.integer.value[0];
+	ret = fm_core_rx_set_rssi_threshold(rssi_threshold_toset);
+	if (ret)
+		return ret;
+
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static int fm_mixer_stereo_mono_info(struct snd_kcontrol *kcontrol,
+				     struct snd_ctl_elem_info *uinfo)
+{
+	static char *modes[] = { "Stereo", "Mono" };
+
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = 2;
+	if (uinfo->value.enumerated.item > 1)
+		uinfo->value.enumerated.item = 1;
+	strcpy(uinfo->value.enumerated.name,
+	       modes[uinfo->value.enumerated.item]);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_stereo_mono_get(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned short mode;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_rx_get_stereo_mono(&mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ucontrol->value.enumerated.item[0] = mode & 0x1;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_stereo_mono_put(struct snd_kcontrol *kcontrol,
+				    struct snd_ctl_elem_value *ucontrol)
+{
+	int ret;
+	unsigned short mode;
+	int changed;
+
+	FMDRV_API_START();
+
+	mode = ucontrol->value.integer.value[0] & 0x1;
+	ret = fm_core_set_stereo_mono(mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static int fm_mixer_rx_deemphasis_info(struct snd_kcontrol *kcontrol,
+				       struct snd_ctl_elem_info *uinfo)
+{
+	static char *filter_mode[] = { "50 us", "75 us" };
+
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = 2;
+	if (uinfo->value.enumerated.item > 1)
+		uinfo->value.enumerated.item = 1;
+	strcpy(uinfo->value.enumerated.name,
+	       filter_mode[uinfo->value.enumerated.item]);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_deemphasis_get(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned short mode;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_rx_get_deemphasis_mode(&mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ucontrol->value.enumerated.item[0] = mode & 0x1;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_deemphasis_put(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	int ret;
+	unsigned short mode;
+	int changed;
+
+	FMDRV_API_START();
+
+	mode = ucontrol->value.integer.value[0] & 0x1;
+	ret = fm_core_rx_set_deemphasis_mode(mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static int fm_mixer_rx_rds_switch_info(struct snd_kcontrol *kcontrol,
+				       struct snd_ctl_elem_info *uinfo)
+{
+	static char *rds_mode[] = { "Off", "On" };
+
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = 2;
+	if (uinfo->value.enumerated.item > 1)
+		uinfo->value.enumerated.item = 1;
+	strcpy(uinfo->value.enumerated.name,
+	       rds_mode[uinfo->value.enumerated.item]);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_rds_switch_get(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned char rds_onoff;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_rx_get_rds_mode(&rds_onoff);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ucontrol->value.enumerated.item[0] = rds_onoff & 0x1;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_rds_switch_put(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	int ret;
+	unsigned char rds_onoff;
+	int changed;
+
+	FMDRV_API_START();
+
+	rds_onoff = ucontrol->value.integer.value[0] & 0x1;
+	ret = fm_core_set_rds_mode(rds_onoff);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static int fm_mixer_rx_rds_opmode_info(struct snd_kcontrol *kcontrol,
+				       struct snd_ctl_elem_info *uinfo)
+{
+	static char *rds_mode[] = { "RDS", "RDBS" };
+
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = 2;
+	if (uinfo->value.enumerated.item > 1)
+		uinfo->value.enumerated.item = 1;
+	strcpy(uinfo->value.enumerated.name,
+	       rds_mode[uinfo->value.enumerated.item]);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_rds_opmode_get(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned char rds_mode;
+	int ret;
+
+	FMDRV_API_START();
+	ret = fm_core_rx_get_rds_system(&rds_mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ucontrol->value.enumerated.item[0] = rds_mode & 0x1;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_rds_opmode_put(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	int ret;
+	unsigned char rds_mode;
+	int changed;
+
+	FMDRV_API_START();
+
+	rds_mode = ucontrol->value.integer.value[0] & 0x1;
+	ret = fm_core_rx_set_rds_system(rds_mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static int fm_mixer_rx_af_switch_info(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_info *uinfo)
+{
+	static char *af_mode[] = { "Off", "On" };
+
+	FMDRV_API_START();
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = 2;
+	if (uinfo->value.enumerated.item > 1)
+		uinfo->value.enumerated.item = 1;
+	strcpy(uinfo->value.enumerated.name,
+	       af_mode[uinfo->value.enumerated.item]);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_af_switch_get(struct snd_kcontrol *kcontrol,
+				     struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned char af_mode;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_rx_get_af_switch(&af_mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ucontrol->value.enumerated.item[0] = af_mode & 0x1;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static int fm_mixer_rx_af_switch_put(struct snd_kcontrol *kcontrol,
+				     struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned char af_mode;
+	int changed, ret;
+
+	FMDRV_API_START();
+
+	af_mode = ucontrol->value.integer.value[0] & 0x1;
+	ret = fm_core_rx_set_af_switch(af_mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	changed = 1;
+
+	FMDRV_API_EXIT(changed);
+	return changed;
+}
+
+static struct snd_kcontrol_new snd_fm_controls[] = {
+	{
+	 .name = "Mode Switch",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_mode_info,
+	 .get = fm_mixer_mode_get,
+	 .put = fm_mixer_mode_put,
+	 },
+	{
+	 .name = "Region Switch",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_region_info,
+	 .get = fm_mixer_region_get,
+	 .put = fm_mixer_region_put,
+	 },
+	{
+	 .name = "RF Dependent Mute",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_rfdepend_mute_info,
+	 .get = fm_mixer_rfdepend_mute_get,
+	 .put = fm_mixer_rfdepend_mute_put,
+	 },
+	{
+	 .name = "RSSI Level",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READ,
+	 .info = fm_mixer_rssi_level_info,
+	 .get = fm_mixer_rssi_level_get,
+	 },
+	{
+	 .name = "RSSI Threshold",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_rx_rssi_threshold_info,
+	 .get = fm_mixer_rx_rssi_threshold_get,
+	 .put = fm_mixer_rx_rssi_threshold_put,
+	 },
+	{
+	 .name = "Stereo/Mono",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_stereo_mono_info,
+	 .get = fm_mixer_stereo_mono_get,
+	 .put = fm_mixer_stereo_mono_put,
+	 },
+	{
+	 .name = "De-emphasis Filter",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_rx_deemphasis_info,
+	 .get = fm_mixer_rx_deemphasis_get,
+	 .put = fm_mixer_rx_deemphasis_put,
+	 },
+	{
+	 .name = "RDS Switch",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_rx_rds_switch_info,
+	 .get = fm_mixer_rx_rds_switch_get,
+	 .put = fm_mixer_rx_rds_switch_put,
+	 },
+	{
+	 .name = "RDS Operation Mode",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_rx_rds_opmode_info,
+	 .get = fm_mixer_rx_rds_opmode_get,
+	 .put = fm_mixer_rx_rds_opmode_put,
+	 },
+	{
+	 .name = "AF Switch",
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .index = 0,
+	 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	 .info = fm_mixer_rx_af_switch_info,
+	 .get = fm_mixer_rx_af_switch_get,
+	 .put = fm_mixer_rx_af_switch_put,
+	 },
+};
+
+int fm_mixer_init(struct fmdrv_ops *fmdev)
+{
+	int idx;
+	int ret;
+
+	FMDRV_API_START();
+	/* Allocate new card for FM driver */
+	ret = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
+			THIS_MODULE, 0, &fmdev->card);
+	if (ret < 0) {
+		FM_DRV_ERR("Failed to create new card");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	fmdev->card->private_data = fmdev;
+
+	/* Add FM mixer controls to the card */
+	strcpy(fmdev->card->mixername, FM_DRV_MIXER_NAME);
+	for (idx = 0; idx < NO_OF_ENTRIES_IN_ARRAY(snd_fm_controls); idx++) {
+		ret = snd_ctl_add(fmdev->card,
+				snd_ctl_new1(&snd_fm_controls[idx], fmdev));
+		if (ret < 0) {
+			snd_card_free(fmdev->card);
+			FM_DRV_ERR("Failed to add mixer controls");
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+	}
+
+	/* Register FM card with ALSA */
+	ret = snd_card_register(fmdev->card);
+	if (ret) {
+		snd_card_free(fmdev->card);
+		FM_DRV_ERR("Failed to register new card");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	strcpy(fmdev->card->driver, FM_DRV_NAME);
+	strcpy(fmdev->card->shortname, FM_DRV_CARD_SHORT_NAME);
+	sprintf(fmdev->card->longname, FM_DRV_CARD_LONG_NAME);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_mixer_deinit(struct fmdrv_ops *fmdev)
+{
+	FMDRV_API_START();
+
+	/* Unregister FM card from ALSA */
+	snd_card_free(fmdev->card);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
diff --git a/drivers/misc/ti-st/fmdrv_mixer.h b/drivers/misc/ti-st/fmdrv_mixer.h
new file mode 100644
index 000000000000..92dcadf4f509
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_mixer.h
@@ -0,0 +1,30 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _FM_MIXER_H
+#define _FM_MIXER_H
+
+/* FM mixer name */
+#define FM_DRV_MIXER_NAME   "tifm_mixer"
+
+int fm_mixer_init(struct fmdrv_ops *fmdev);
+int fm_mixer_deinit(struct fmdrv_ops *fmdev);
+
+#endif
diff --git a/drivers/misc/ti-st/fmdrv_st.c b/drivers/misc/ti-st/fmdrv_st.c
new file mode 100644
index 000000000000..383a1e4e2ef9
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_st.c
@@ -0,0 +1,320 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  This file provide interfaces to Shared Transport.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/kernel.h>
+
+#include "st.h"
+#include "fmdrv.h"
+#include "fmdrv_st.h"
+
+static char streg_cbdata;
+
+/* Wait on comepletion handler needed to synchronize
+ * fm_st_register() and fm_st_registration_completion_cb()
+ * functions.
+ */
+static struct completion wait_for_fmdrv_reg_completion;
+
+/* Write function pointer of ST driver */
+long (*g_st_write) (struct sk_buff *skb);
+
+/* RX Queue and RX Tasklet pointer */
+static struct sk_buff_head *g_rx_q;
+static struct tasklet_struct *g_rx_task;
+
+/* Flag to maintain whether FM ST is claimed or not */
+static char is_fm_st_claimed;
+
+/* Called from FM Core and FM Char device interface to claim
+ * FM ST. Who ever comes first, ownership of FM ST will be
+ * given to them.
+ */
+int fm_st_claim(void)
+{
+	FMDRV_API_START();
+
+	/* Give ownership of FM ST to first caller */
+	if (is_fm_st_claimed == FM_ST_NOT_CLAIMED) {
+		is_fm_st_claimed = FM_ST_CLAIMED;
+
+		FMDRV_API_EXIT(FM_ST_SUCCESS);
+		return FM_ST_SUCCESS;
+	}
+
+	FM_DRV_DBG("FM ST claimed already");
+
+	FMDRV_API_EXIT(FM_ST_FAILED);
+	return FM_ST_FAILED;
+}
+
+/* Called from FM Core and FM Char device interface
+ * to release FM ST.
+ */
+int fm_st_release(void)
+{
+	FMDRV_API_START();
+
+	/* Release FM ST if it is already claimed */
+	if (is_fm_st_claimed == FM_ST_CLAIMED) {
+		is_fm_st_claimed = FM_ST_NOT_CLAIMED;
+
+		FMDRV_API_EXIT(FM_ST_SUCCESS);
+		return FM_ST_SUCCESS;
+
+	}
+
+	FM_DRV_ERR("FM ST is not claimed,called again?");
+
+	FMDRV_API_EXIT(FM_ST_FAILED);
+	return FM_ST_FAILED;
+}
+
+/* Called by Shared Transport layer when FM packet is
+ * available
+ */
+static long fm_st_receive(struct sk_buff *skb)
+{
+	FMDRV_API_START();
+
+	if (skb == NULL) {
+		FM_DRV_ERR("Invalid SKB received from ST");
+		FMDRV_API_EXIT(-EFAULT);
+		return -EFAULT;
+	}
+
+	/* Is this FM Channel-8 packet? */
+	if (skb->cb[0] != FM_PKT_LOGICAL_CHAN_NUMBER) {
+		FM_DRV_ERR("Received SKB(%p) is not FM Channel 8 pkt", skb);
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+
+	/* One byte is already reserved for Channel-8 in skb,
+	 * so prepend skb with Channel-8 packet type byte.
+	 */
+	memcpy(skb_push(skb, 1), &skb->cb[0], 1);
+
+	if (g_rx_q != NULL && g_rx_task != NULL) {
+		/* Queue FM packet for FM RX task */
+		skb_queue_tail(g_rx_q, skb);
+		tasklet_schedule(g_rx_task);
+	} else {
+		FM_DRV_ERR
+		    ("Invalid RX queue and RX tasklet pointer,puring skb");
+		kfree_skb(skb);
+		FMDRV_API_EXIT(-EFAULT);
+		return -EFAULT;
+	}
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Forwards FM Packets to Shared Transport */
+int fm_st_send(struct sk_buff *skb)
+{
+	long len;
+
+	FMDRV_API_START();
+
+	if (skb == NULL) {
+		FM_DRV_ERR("Invalid skb, can't send");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+
+	/* Is anyone called without claiming FM ST? */
+	if (is_fm_st_claimed == FM_ST_CLAIMED && g_st_write != NULL) {
+		/* Forward FM packet(SKB) to ST for the transmission */
+		len = g_st_write(skb);
+		if (len < 0) {
+			/* Something went wrong in st write , free skb memory */
+			kfree_skb(skb);
+			FM_DRV_ERR(" ST write failed (%ld)", len);
+			FMDRV_API_EXIT(-EAGAIN);
+			return -EAGAIN;
+		}
+	} else {		/* Nobody calimed FM ST */
+
+		kfree_skb(skb);
+		FM_DRV_ERR("FM ST is not claimed, Can't send skb");
+		FMDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Called by ST layer to indicate protocol registration completion
+ * status. fm_st_register() function will wait for signal from this
+ * API when st_register() function returns ST_PENDING.
+ */
+static void fm_st_registration_completion_cb(char data)
+{
+	FMDRV_API_START();
+
+	/* fm_st_register() function needs value of 'data' to know
+	 * the registration status(success/fail). So, have a back
+	 * up of it.
+	 */
+	streg_cbdata = data;
+
+	/* Got a feedback from ST for FM driver registration
+	 * request. Wackup fm_st_register() function to continue
+	 * it's open operation.
+	 */
+	complete(&wait_for_fmdrv_reg_completion);
+
+	FMDRV_API_EXIT(0);
+}
+
+/* Called from V4L2 RADIO open function (fm_fops_open()) to
+ * register FM driver with Shared Transport
+ */
+int fm_st_register(struct sk_buff_head *rx_q, struct tasklet_struct *rx_task)
+{
+	static struct st_proto_s fm_st_proto;
+	unsigned long timeleft;
+	int ret;
+
+	ret = 0;
+
+	FMDRV_API_START();
+
+	/* Populate FM driver info required by ST */
+	memset(&fm_st_proto, 0, sizeof(fm_st_proto));
+
+	/* FM driver ID */
+	fm_st_proto.type = ST_FM;
+
+	/* Receive function which called from ST */
+	fm_st_proto.recv = fm_st_receive;
+
+	/* Packet match function may used in future */
+	fm_st_proto.match_packet = NULL;
+
+	/* Callback to be called when registration is pending */
+	fm_st_proto.reg_complete_cb = fm_st_registration_completion_cb;
+
+	/* This is write function pointer of ST. BT driver will make use of this
+	 * for sending any packets to chip. ST will assign and give to us, so
+	 * make it as NULL
+	 */
+	fm_st_proto.write = NULL;
+
+	/* Register with ST layer */
+	ret = st_register(&fm_st_proto);
+	if (ret == ST_ERR_PENDING) {
+		/* Prepare wait-for-completion handler data structures.
+		 * Needed to syncronize this and
+		 * fm_st_registration_completion_cb() functions.
+		 */
+		init_completion(&wait_for_fmdrv_reg_completion);
+
+		/* Reset ST registration callback status flag. This value
+		 * will be updated in fm_st_registration_completion_cb()
+		 * function whenever it is called from ST driver.
+		 */
+		streg_cbdata = -EINPROGRESS;
+
+		/* ST is busy with other protocol registration (may be busy with
+		 * firmware download). So, wait till the registration callback
+		 * (passed as a argument to st_register() function) getting
+		 * called from ST.
+		 */
+		FM_DRV_DBG(" %s waiting for reg completion signal from ST",
+			   __func__);
+
+		timeleft =
+		    wait_for_completion_timeout(&wait_for_fmdrv_reg_completion,
+						FM_ST_REGISTER_TIMEOUT);
+		if (!timeleft) {
+			FM_DRV_ERR("Timeout(%d sec), didn't get reg"
+				   "completion signal from ST",
+				   jiffies_to_msecs(FM_ST_REGISTER_TIMEOUT) /
+				   1000);
+			FMDRV_API_EXIT(-ETIMEDOUT);
+			return -ETIMEDOUT;
+		}
+
+		/* Is ST registration callback called with ERROR value? */
+		if (streg_cbdata != 0) {
+			FM_DRV_ERR("ST reg completion CB called with invalid"
+				   "status %d", streg_cbdata);
+			FMDRV_API_EXIT(-EAGAIN);
+			return -EAGAIN;
+		}
+		ret = 0;
+	} else if (ret == ST_ERR_FAILURE) {
+		FM_DRV_ERR("st_register failed %d", ret);
+		FMDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+
+	/* Do we have proper ST write function? */
+	if (fm_st_proto.write != NULL) {
+		/* We need this pointer for sending any FM pkts */
+		g_st_write = fm_st_proto.write;
+	} else {
+		FM_DRV_ERR("Failed to get ST write func pointer");
+
+		/* Undo registration with ST */
+		ret = st_unregister(ST_FM);
+		if (ret < 0)
+			FM_DRV_ERR("st_unregister failed %d", ret);
+
+		FMDRV_API_EXIT(-EAGAIN);
+		return -EAGAIN;
+	}
+
+	/* Store Rx Q and Rx tasklet pointers. This pointers should
+	 * already initialized by caller
+	 */
+	g_rx_task = rx_task;
+	g_rx_q = rx_q;
+
+	FMDRV_API_EXIT(ret);
+	return ret;
+}
+
+/* Unregister FM Driver from Shared Transport */
+int fm_st_unregister(void)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Unregister FM Driver from ST */
+	ret = st_unregister(ST_FM);
+	if (ret != ST_SUCCESS) {
+		FM_DRV_ERR("st_unregister failed %d", ret);
+		FMDRV_API_EXIT(-EBUSY);
+		return -EBUSY;
+	}
+
+	g_rx_task = NULL;
+	g_rx_q = NULL;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
diff --git a/drivers/misc/ti-st/fmdrv_st.h b/drivers/misc/ti-st/fmdrv_st.h
new file mode 100644
index 000000000000..86a400709a63
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_st.h
@@ -0,0 +1,50 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _FM_ST_H
+#define _FM_ST_H
+
+#include <linux/interrupt.h>
+
+/* Defines number of seconds to wait for reg completion
+ * callback getting called from ST (in case, registration
+ * with ST returns PENDING status)
+ */
+#define FM_ST_REGISTER_TIMEOUT   msecs_to_jiffies(6000)	/* 6 sec */
+
+#define FM_PKT_LOGICAL_CHAN_NUMBER  0x08   /* Logical channel 8 */
+
+/* Claim ownership of FM ST */
+int fm_st_claim(void);
+
+/* To release FM ST */
+int fm_st_release(void);
+
+/* Forwards FM Packets to Shared Transport */
+int fm_st_send(struct sk_buff *skb);
+
+/* Register with Shared Transport */
+int fm_st_register(struct sk_buff_head  *rx_q,
+		   struct tasklet_struct *rx_task);
+
+/* Unregister from Shared Transport */
+int fm_st_unregister(void);
+
+#endif
diff --git a/drivers/misc/ti-st/fmdrv_v4l2.c b/drivers/misc/ti-st/fmdrv_v4l2.c
new file mode 100644
index 000000000000..c08fe23a729d
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_v4l2.c
@@ -0,0 +1,588 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  This file provides interfaces to V4L2 subsystem.
+ *
+ *  This module registers with V4L2 subsystem as Radio
+ *  data system interface (/dev/radio). During the registration,
+ *  it will expose two set of function pointers to V4L2 subsystem.
+ *
+ *    1) File operation related API (open, close, read, write, poll...etc).
+ *    2) Set of V4L2 IOCTL complaint API.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include "fmdrv.h"
+#include "fmdrv_v4l2.h"
+#include "fmdrv_core.h"
+
+static unsigned char radio_disconnected;
+
+/* Query control */
+static struct v4l2_queryctrl fmdrv_v4l2_queryctrl[] = {
+	{
+	 .id = V4L2_CID_AUDIO_VOLUME,
+	 .type = V4L2_CTRL_TYPE_INTEGER,
+	 .name = "Volume",
+	 .minimum = FM_RX_VOLUME_MIN,
+	 .maximum = FM_RX_VOLUME_MAX,
+	 .step = 1,
+	 .default_value = FM_DEFAULT_RX_VOLUME,
+	 },
+	{
+	 .id = V4L2_CID_AUDIO_BALANCE,
+	 .flags = V4L2_CTRL_FLAG_DISABLED,
+	 },
+	{
+	 .id = V4L2_CID_AUDIO_BASS,
+	 .flags = V4L2_CTRL_FLAG_DISABLED,
+	 },
+	{
+	 .id = V4L2_CID_AUDIO_TREBLE,
+	 .flags = V4L2_CTRL_FLAG_DISABLED,
+	 },
+	{
+	 .id = V4L2_CID_AUDIO_MUTE,
+	 .type = V4L2_CTRL_TYPE_BOOLEAN,
+	 .name = "Mute",
+	 .minimum = 0,
+	 .maximum = 2,
+	 .step = 1,
+	 .default_value = FM_MUTE_OFF,
+	 },
+	{
+	 .id = V4L2_CID_AUDIO_LOUDNESS,
+	 .flags = V4L2_CTRL_FLAG_DISABLED,
+	 },
+};
+
+/* -- V4L2 RADIO (/dev/radioX) device file operation interfaces --- */
+
+/* Read RDS data */
+static ssize_t fm_v4l2_fops_read(struct file *file, char __user * buf,
+				 size_t count, loff_t *ppos)
+{
+	unsigned char rds_mode;
+	int ret, noof_bytes_copied;
+	FMDRV_API_START();
+
+	if (!radio_disconnected) {
+		FM_DRV_ERR("FM device is already disconnected\n");
+		FMDRV_API_EXIT(-EIO);
+		return -EIO;
+	}
+	/* Turn on RDS mode , if it is disabled */
+	ret = fm_core_rx_get_rds_mode(&rds_mode);
+	if (ret) {
+		FM_DRV_ERR("Unable to read current rds mode");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	if (rds_mode == FM_RX_RDS_DISABLE) {
+		ret = fm_core_set_rds_mode(FM_RX_RDS_ENABLE);
+		if (ret < 0) {
+			FM_DRV_ERR("Unable to enable rds mode");
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+	}
+	/* Copy RDS data from internal buffer to user buffer */
+	noof_bytes_copied =
+	    fm_core_transfer_rds_from_internal_buff(file, buf, count);
+
+	FMDRV_API_EXIT(noof_bytes_copied);
+	return noof_bytes_copied;
+}
+
+/* Write RDS data */
+static ssize_t fm_v4l2_fops_write(struct file *file, const char __user * buf,
+				  size_t count, loff_t *ppos)
+{
+	struct tx_rds rds;
+	int ret;
+	FMDRV_API_START();
+
+	ret = copy_from_user(&rds, buf, sizeof(rds));
+	FM_DRV_DBG("(%d)type: %d, text %s, af %d",
+		   ret, rds.text_type, rds.text, rds.af_freq);
+
+	fm_core_tx_set_radio_text(rds.text, rds.text_type);
+	fm_core_tx_set_af(rds.af_freq);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Poll RDS data */
+static unsigned int fm_v4l2_fops_poll(struct file *file,
+				      struct poll_table_struct *pts)
+{
+	int ret;
+	FMDRV_API_START();
+
+	ret = fm_core_is_rds_data_available(file, pts);
+	if (!ret) {
+		FMDRV_API_EXIT(POLLIN | POLLRDNORM);
+		return POLLIN | POLLRDNORM;
+	}
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* File Open */
+static int fm_v4l2_fops_open(struct file *file)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	/* Don't allow multiple open */
+	if (radio_disconnected) {
+		FM_DRV_ERR("FM device is already opened\n");
+		FMDRV_API_EXIT(-EBUSY);
+		return -EBUSY;
+	}
+
+	/* Request FM Core to link with FM ST */
+	ret = fm_core_setup_transport();
+	if (ret) {
+		FM_DRV_ERR("Unable to setup FM Core transport");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Initialize FM Core */
+	ret = fm_core_prepare();
+	if (ret) {
+		FM_DRV_ERR("Unable to prepare FM CORE");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	FM_DRV_DBG("Load FM RX firmware..");
+	/* By default load FM RX firmware */
+	ret = fm_core_mode_set(FM_MODE_RX);
+	if (ret) {
+		FM_DRV_ERR("Unable to load FM RX firmware");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	radio_disconnected = 1;
+	FM_DRV_DBG("FM CORE is ready");
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* File Release */
+static int fm_v4l2_fops_release(struct file *file)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	if (!radio_disconnected) {
+		FM_DRV_DBG("FM device already closed,close called again?");
+		FMDRV_API_EXIT(0);
+		return 0;
+	}
+
+	FM_DRV_DBG("Turning off..");
+	ret = fm_core_mode_set(FM_MODE_OFF);
+	if (ret) {
+		FM_DRV_ERR("Unable to turn off the chip");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Request FM Core to unlink from ST driver */
+	ret = fm_core_release();
+	if (ret) {
+		FM_DRV_ERR("FM CORE release failed");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	/* Release FM Core transport */
+	ret = fm_core_release_transport();
+	if (ret) {
+		FM_DRV_ERR("Unable to setup FM Core transport");
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	radio_disconnected = 0;
+	FM_DRV_DBG("FM CORE released successfully");
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* V4L2 RADIO (/dev/radioX) device IOCTL interfaces */
+
+/* Query device capabilities */
+static int fm_v4l2_vidioc_querycap(struct file *file, void *priv,
+				   struct v4l2_capability *capability)
+{
+	FMDRV_API_START();
+
+	strlcpy(capability->driver, FM_DRV_NAME, sizeof(capability->driver));
+	strlcpy(capability->card, FM_DRV_CARD_SHORT_NAME,
+		sizeof(capability->card));
+	sprintf(capability->bus_info, "UART");
+	capability->version = FM_DRV_RADIO_VERSION;
+	capability->capabilities = V4L2_CAP_HW_FREQ_SEEK | V4L2_CAP_TUNER |
+	    V4L2_CAP_RADIO | V4L2_CAP_READWRITE | V4L2_CAP_AUDIO;
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Enumerate control items */
+static int fm_v4l2_vidioc_queryctrl(struct file *file, void *priv,
+				    struct v4l2_queryctrl *qc)
+{
+	int index;
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = -EINVAL;
+	if (qc->id < V4L2_CID_BASE) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	/* Search control ID and copy its properties */
+	for (index = 0; index < NO_OF_ENTRIES_IN_ARRAY(fmdrv_v4l2_queryctrl);
+	     index++) {
+		if (qc->id && qc->id == fmdrv_v4l2_queryctrl[index].id) {
+			memcpy(qc, &(fmdrv_v4l2_queryctrl[index]), sizeof(*qc));
+			ret = 0;
+			break;
+		}
+	}
+	FMDRV_API_EXIT(ret);
+	return ret;
+}
+
+/* Get the value of a control */
+static int fm_v4l2_vidioc_g_ctrl(struct file *file, void *priv,
+				 struct v4l2_control *ctrl)
+{
+	int ret;
+	unsigned short curr_vol;
+	unsigned char curr_mute_mode;
+
+	FMDRV_API_START();
+
+	switch (ctrl->id) {
+
+	case V4L2_CID_AUDIO_MUTE:	/* get mute mode */
+		ret = fm_core_rx_get_mute_mode(&curr_mute_mode);
+		if (ret < 0) {
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+		ctrl->value = curr_mute_mode;
+		break;
+
+	case V4L2_CID_AUDIO_VOLUME:	/* get volume */
+		ret = fm_core_rx_get_volume(&curr_vol);
+		if (ret < 0) {
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+		ctrl->value = curr_vol;
+		break;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set the value of a control */
+static int fm_v4l2_vidioc_s_ctrl(struct file *file, void *priv,
+				 struct v4l2_control *ctrl)
+{
+	int ret;
+	FMDRV_API_START();
+
+	switch (ctrl->id) {
+
+	case V4L2_CID_AUDIO_MUTE:	/* set mute */
+		ret = fm_core_set_mute_mode((unsigned char)ctrl->value);
+		if (ret < 0) {
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+		break;
+
+	case V4L2_CID_AUDIO_VOLUME:	/* set volume */
+		ret = fm_core_rx_set_volume((unsigned short)ctrl->value);
+		if (ret < 0) {
+			FMDRV_API_EXIT(ret);
+			return ret;
+		}
+		break;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Get audio attributes */
+static int fm_v4l2_vidioc_g_audio(struct file *file, void *priv,
+				  struct v4l2_audio *audio)
+{
+	FMDRV_API_START();
+
+	memset(audio, 0, sizeof(*audio));
+	audio->index = 0;
+	strcpy(audio->name, "Radio");
+	audio->capability = V4L2_AUDCAP_STEREO;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set audio attributes */
+static int fm_v4l2_vidioc_s_audio(struct file *file, void *priv,
+				  struct v4l2_audio *audio)
+{
+	FMDRV_API_START();
+
+	if (audio->index != 0) {
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Get tuner attributes */
+static int fm_v4l2_vidioc_g_tuner(struct file *file, void *priv,
+				  struct v4l2_tuner *tuner)
+{
+	unsigned int bottom_frequency;
+	unsigned int top_frequency;
+	unsigned short stereo_mono_mode;
+	unsigned short rssilvl;
+	int ret;
+
+	FMDRV_API_START();
+
+	if (tuner->index != 0) {
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	ret =
+	    fm_core_rx_get_currband_lowhigh_freq(&bottom_frequency,
+						 &top_frequency);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ret = fm_core_rx_get_stereo_mono(&stereo_mono_mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	ret = fm_core_rx_get_rssi_level(&rssilvl);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	strcpy(tuner->name, "FM");
+	tuner->type = V4L2_TUNER_RADIO;
+	/* Store rangelow and rangehigh freq in unit of 62.5 KHz */
+	tuner->rangelow = (bottom_frequency * 10000) / 625;
+	tuner->rangehigh = (top_frequency * 10000) / 625;
+	tuner->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
+	tuner->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LOW;
+	tuner->audmode = (stereo_mono_mode ?
+			  V4L2_TUNER_MODE_MONO : V4L2_TUNER_MODE_STEREO);
+
+	/* Actual rssi value lies in between -128 to +127.
+	 * Convert this range from 0 to 255 by adding +128
+	 */
+	rssilvl += 128;
+
+	/* Return signal strength value should be within 0 to 65535.
+	 * Find out correct signal radio by multiplying (65535/255) = 257
+	 */
+	tuner->signal = rssilvl * 257;
+	tuner->afc = 0;
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set tuner attributes */
+static int fm_v4l2_vidioc_s_tuner(struct file *file, void *priv,
+				  struct v4l2_tuner *tuner)
+{
+	unsigned short mode;
+	int ret;
+
+	FMDRV_API_START();
+
+	if ((tuner->index != 0) ||
+	    (tuner->audmode != V4L2_TUNER_MODE_MONO &&
+	     tuner->audmode != V4L2_TUNER_MODE_STEREO)) {
+		FMDRV_API_EXIT(-EINVAL);
+		return -EINVAL;
+	}
+	/* Map V4L2 stereo/mono macro to our local stereo/mono macro */
+	mode = (tuner->audmode == V4L2_TUNER_MODE_STEREO) ?
+	    FM_STEREO_MODE : FM_MONO_MODE;
+	ret = fm_core_set_stereo_mono(mode);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Get tuner or modulator radio frequency */
+static int fm_v4l2_vidioc_g_frequency(struct file *file, void *priv,
+				      struct v4l2_frequency *freq)
+{
+	int ret;
+	FMDRV_API_START();
+
+	ret = fm_core_get_frequency(&freq->frequency);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set tuner or modulator radio frequency */
+static int fm_v4l2_vidioc_s_frequency(struct file *file, void *priv,
+				      struct v4l2_frequency *freq)
+{
+	int ret;
+	FMDRV_API_START();
+
+	/* As per V4L2 specifications user sends the frequency
+	 * in units of 62.5 Hz. But FM chip expects it in units of 1 KHz
+	 * so freq->frequency = ((freq * 62.5)/1000) KHz
+	 */
+	freq->frequency = (unsigned int)((freq->frequency * 625)/10000);
+
+	ret = fm_core_set_frequency(freq->frequency);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+/* Set hardware frequency seek */
+static int fm_v4l2_vidioc_s_hw_freq_seek(struct file *file, void *priv,
+					 struct v4l2_hw_freq_seek *seek)
+{
+	int ret;
+
+	FMDRV_API_START();
+
+	ret = fm_core_rx_seek(seek->seek_upward, seek->wrap_around);
+	if (ret) {
+		FMDRV_API_EXIT(ret);
+		return ret;
+	}
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+static const struct v4l2_file_operations fm_drv_fops = {
+	.owner = THIS_MODULE,
+	.read = fm_v4l2_fops_read,
+	.write = fm_v4l2_fops_write,
+	.poll = fm_v4l2_fops_poll,
+	.ioctl = video_ioctl2,
+	.open = fm_v4l2_fops_open,
+	.release = fm_v4l2_fops_release,
+};
+
+static const struct v4l2_ioctl_ops fm_drv_ioctl_ops = {
+	.vidioc_querycap = fm_v4l2_vidioc_querycap,
+	.vidioc_queryctrl = fm_v4l2_vidioc_queryctrl,
+	.vidioc_g_ctrl = fm_v4l2_vidioc_g_ctrl,
+	.vidioc_s_ctrl = fm_v4l2_vidioc_s_ctrl,
+	.vidioc_g_audio = fm_v4l2_vidioc_g_audio,
+	.vidioc_s_audio = fm_v4l2_vidioc_s_audio,
+	.vidioc_g_tuner = fm_v4l2_vidioc_g_tuner,
+	.vidioc_s_tuner = fm_v4l2_vidioc_s_tuner,
+	.vidioc_g_frequency = fm_v4l2_vidioc_g_frequency,
+	.vidioc_s_frequency = fm_v4l2_vidioc_s_frequency,
+	.vidioc_s_hw_freq_seek = fm_v4l2_vidioc_s_hw_freq_seek,
+};
+
+/*
+ * V4L2 RADIO device parent structure
+ */
+static struct video_device fm_viddev_template = {
+	.fops = &fm_drv_fops,
+	.ioctl_ops = &fm_drv_ioctl_ops,
+	.name = FM_DRV_NAME,
+	.release = video_device_release,
+};
+
+int fm_v4l2_init_video_device(struct fmdrv_ops *fmdev)
+{
+	FMDRV_API_START();
+
+	/* Allocate new video device */
+	fmdev->v4l2dev = video_device_alloc();
+	if (!fmdev->v4l2dev) {
+		FM_DRV_ERR("Can't allocate video device");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+
+	/* Setup FM driver's V4L2 properties */
+	memcpy(fmdev->v4l2dev, &fm_viddev_template, sizeof(fm_viddev_template));
+
+	video_set_drvdata(fmdev->v4l2dev, fmdev);
+
+	/* Register with V4L2 subsystem as RADIO device */
+	if (video_register_device(fmdev->v4l2dev, VFL_TYPE_RADIO, 0)) {
+		video_device_release(fmdev->v4l2dev);
+		fmdev->v4l2dev = NULL;
+
+		FM_DRV_ERR("Could not register video device");
+		FMDRV_API_EXIT(-ENOMEM);
+		return -ENOMEM;
+	}
+	FMDRV_API_EXIT(0);
+	return 0;
+}
+
+int fm_v4l2_deinit_video_device(struct fmdrv_ops *fmdev)
+{
+	FMDRV_API_START();
+
+	/* Unregister RADIO device from V4L2 subsystem */
+	video_unregister_device(fmdev->v4l2dev);
+
+	FMDRV_API_EXIT(0);
+	return 0;
+}
diff --git a/drivers/misc/ti-st/fmdrv_v4l2.h b/drivers/misc/ti-st/fmdrv_v4l2.h
new file mode 100644
index 000000000000..1345a587c0d6
--- /dev/null
+++ b/drivers/misc/ti-st/fmdrv_v4l2.h
@@ -0,0 +1,32 @@
+/*
+ *  FM Driver for Connectivity chip of Texas Instruments.
+ *
+ *  FM V4L2 module header.
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _FM_V4L2_DRV_H
+#define _FM_V4L2_DRV_H
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-ioctl.h>
+
+int fm_v4l2_init_video_device(struct fmdrv_ops *fmdev);
+int fm_v4l2_deinit_video_device(struct fmdrv_ops *fmdev);
+
+#endif
diff --git a/drivers/misc/ti-st/st.h b/drivers/misc/ti-st/st.h
new file mode 100644
index 000000000000..ec821d217b3d
--- /dev/null
+++ b/drivers/misc/ti-st/st.h
@@ -0,0 +1,85 @@
+/*
+ *  Shared Transport Header file
+ *	To be included by the protocol stack drivers for
+ *	Texas Instruments BT,FM and GPS combo chip drivers
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef ST_H
+#define ST_H
+
+#include <linux/skbuff.h>
+/*
+ * st.h
+ */
+
+/* some gpios have active high, others like fm have
+ * active low
+ */
+enum kim_gpio_state {
+	KIM_GPIO_INACTIVE,
+	KIM_GPIO_ACTIVE,
+};
+/*
+ * the list of protocols on chip
+ */
+enum proto_type {
+	ST_BT,
+	ST_FM,
+	ST_GPS,
+	ST_MAX,
+};
+
+enum {
+	ST_ERR_FAILURE = -1,	/* check struct */
+	ST_SUCCESS,
+	ST_ERR_PENDING = -5,	/* to call reg_complete_cb */
+	ST_ERR_ALREADY,		/* already registered */
+	ST_ERR_INPROGRESS,
+	ST_ERR_NOPROTO,		/* protocol not supported */
+};
+
+/* per protocol structure
+ * for BT/FM and GPS
+ */
+struct st_proto_s {
+	enum proto_type type;
+/*
+ * to be called by ST when data arrives
+ */
+	long (*recv) (struct sk_buff *);
+/*
+ * for future use, logic now to be in ST
+ */
+	unsigned char (*match_packet) (const unsigned char *data);
+/*
+ * subsequent registration return PENDING,
+ * signalled complete by this callback function
+ */
+	void (*reg_complete_cb) (char data);
+/*
+ * write function, sent in as NULL and to be returned to
+ * protocol drivers
+ */
+	long (*write) (struct sk_buff *skb);
+};
+
+extern long st_register(struct st_proto_s *new_proto);
+extern long st_unregister(enum proto_type type);
+
+#endif /* ST_H */
diff --git a/drivers/misc/ti-st/st_core.c b/drivers/misc/ti-st/st_core.c
new file mode 100644
index 000000000000..b78a03bccceb
--- /dev/null
+++ b/drivers/misc/ti-st/st_core.c
@@ -0,0 +1,1057 @@
+/*
+ *  Shared Transport Line discipline driver Core
+ *	This hooks up ST KIM driver and ST LL driver
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/tty.h>
+
+/* understand BT, FM and GPS for now */
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+#include <net/bluetooth/hci.h>
+#include "fm.h"
+/*
+ * packet formats for fm and gps
+ * #include "gps.h"
+ */
+#include "st_core.h"
+#include "st_kim.h"
+#include "st_ll.h"
+#include "st.h"
+
+/* all debug macros go in here */
+#define ST_DRV_ERR(fmt, arg...)  printk(KERN_ERR "(stc):"fmt"\n" , ## arg)
+#if defined(DEBUG)		/* limited debug messages */
+#define ST_DRV_DBG(fmt, arg...)  printk(KERN_INFO "(stc):"fmt"\n" , ## arg)
+#define ST_DRV_VER(fmt, arg...)
+#elif defined(VERBOSE)		/* very verbose */
+#define ST_DRV_DBG(fmt, arg...)  printk(KERN_INFO "(stc):"fmt"\n" , ## arg)
+#define ST_DRV_VER(fmt, arg...)  printk(KERN_INFO "(stc):"fmt"\n" , ## arg)
+#else /* error msgs only */
+#define ST_DRV_DBG(fmt, arg...)
+#define ST_DRV_VER(fmt, arg...)
+#endif
+
+#ifdef DEBUG
+/* strings to be used for rfkill entries and by
+ * ST Core to be used for sysfs debug entry
+ */
+#define PROTO_ENTRY(type, name)	name
+const unsigned char *protocol_strngs[] = {
+	PROTO_ENTRY(ST_BT, "Bluetooth"),
+	PROTO_ENTRY(ST_FM, "FM"),
+	PROTO_ENTRY(ST_GPS, "GPS"),
+};
+#endif
+/*
+ * local data instances
+ */
+static struct st_data_s *st_gdata;
+/* function pointer pointing to either,
+ * st_kim_recv during registration to receive fw download responses
+ * st_int_recv after registration to receive proto stack responses
+ */
+void (*st_recv) (const unsigned char *data, long count);
+
+/********************************************************************/
+/* internal misc functions */
+bool is_protocol_list_empty(void)
+{
+	unsigned char i = 0;
+	ST_DRV_DBG(" %s ", __func__);
+	for (i = 0; i < ST_MAX; i++) {
+		if (st_gdata->list[i] != NULL)
+			return ST_NOTEMPTY;
+		/* not empty */
+	}
+	/* list empty */
+	return ST_EMPTY;
+}
+
+/* can be called in from
+ * -- KIM (during fw download)
+ * -- ST Core (during st_write)
+ *
+ *  This is the internal write function - a wrapper
+ *  to tty->ops->write
+ */
+int st_int_write(const unsigned char *data, int count)
+{
+#ifdef VERBOSE			/* for debug */
+	int i;
+#endif
+	struct tty_struct *tty;
+	if (unlikely(st_gdata == NULL || st_gdata->tty == NULL)) {
+		ST_DRV_ERR("tty unavailable to perform write");
+		return ST_ERR_FAILURE;
+	}
+	tty = st_gdata->tty;
+#ifdef VERBOSE
+	printk(KERN_ERR "start data..\n");
+	for (i = 0; i < count; i++)	/* no newlines for each datum */
+		printk(" %x", data[i]);
+	printk(KERN_ERR "\n ..end data\n");
+#endif
+
+	return tty->ops->write(tty, data, count);
+
+}
+
+/*
+ * push the skb received to relevant
+ * protocol stacks
+ */
+void st_send_frame(enum proto_type protoid, struct sk_buff *skb)
+{
+	ST_DRV_DBG(" %s(prot:%d) ", __func__, protoid);
+
+	if (unlikely
+	    (st_gdata == NULL || skb == NULL
+	     || st_gdata->list[protoid] == NULL)) {
+		ST_DRV_ERR("protocol %d not registered, no data to send?",
+			   protoid);
+		kfree_skb(skb);
+		return;
+	}
+	/* this cannot fail
+	 * this shouldn't take long
+	 * - should be just skb_queue_tail for the
+	 *   protocol stack driver
+	 */
+	if (likely(st_gdata->list[protoid]->recv != NULL)) {
+		if (unlikely(st_gdata->list[protoid]->recv(skb)
+			     != ST_SUCCESS)) {
+			ST_DRV_ERR(" proto stack %d's ->recv failed", protoid);
+			kfree_skb(skb);
+			return;
+		}
+	} else {
+		ST_DRV_ERR(" proto stack %d's ->recv null", protoid);
+		kfree_skb(skb);
+	}
+	ST_DRV_DBG(" done %s", __func__);
+	return;
+}
+
+/*
+ * to call registration complete callbacks
+ * of all protocol stack drivers
+ */
+void st_reg_complete(char err)
+{
+	unsigned char i = 0;
+	ST_DRV_DBG(" %s ", __func__);
+	for (i = 0; i < ST_MAX; i++) {
+		if (likely(st_gdata != NULL && st_gdata->list[i] != NULL &&
+			   st_gdata->list[i]->reg_complete_cb != NULL))
+			st_gdata->list[i]->reg_complete_cb(err);
+	}
+}
+
+static inline int st_check_data_len(int protoid, int len)
+{
+	register int room = skb_tailroom(st_gdata->rx_skb);
+
+	ST_DRV_DBG("len %d room %d", len, room);
+
+	if (!len) {
+		/* Received packet has only packet header and
+		 * has zero length payload. So, ask ST CORE to
+		 * forward the packet to protocol driver (BT/FM/GPS)
+		 */
+		st_send_frame(protoid, st_gdata->rx_skb);
+
+	} else if (len > room) {
+		/* Received packet's payload length is larger.
+		 * We can't accommodate it in created skb.
+		 */
+		ST_DRV_ERR("Data length is too large len %d room %d", len,
+			   room);
+		kfree_skb(st_gdata->rx_skb);
+	} else {
+		/* Packet header has non-zero payload length and
+		 * we have enough space in created skb. Lets read
+		 * payload data */
+		st_gdata->rx_state = ST_BT_W4_DATA;
+		st_gdata->rx_count = len;
+		return len;
+	}
+
+	/* Change ST state to continue to process next
+	 * packet */
+	st_gdata->rx_state = ST_W4_PACKET_TYPE;
+	st_gdata->rx_skb = NULL;
+	st_gdata->rx_count = 0;
+
+	return 0;
+}
+
+/* internal function for action when wake-up ack
+ * received
+ */
+static inline void st_wakeup_ack(unsigned char cmd)
+{
+	register struct sk_buff *waiting_skb;
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(&st_gdata->lock, flags);
+	/* de-Q from waitQ and Q in txQ now that the
+	 * chip is awake
+	 */
+	while ((waiting_skb = skb_dequeue(&st_gdata->tx_waitq)))
+		skb_queue_tail(&st_gdata->txq, waiting_skb);
+
+	/* state forwarded to ST LL */
+	st_ll_sleep_state((unsigned long)cmd);
+	spin_unlock_irqrestore(&st_gdata->lock, flags);
+
+	/* wake up to send the recently copied skbs from waitQ */
+	st_tx_wakeup(st_gdata);
+}
+
+/* Decodes received RAW data and forwards to corresponding
+ * client drivers (Bluetooth,FM,GPS..etc).
+ *
+ */
+void st_int_recv(const unsigned char *data, long count)
+{
+	register char *ptr;
+	struct hci_event_hdr *eh;
+	struct hci_acl_hdr *ah;
+	struct hci_sco_hdr *sh;
+	struct fm_event_hdr *fm;
+	struct gps_event_hdr *gps;
+	register int len = 0, type = 0, dlen = 0;
+	static enum proto_type protoid = ST_MAX;
+
+	ST_DRV_DBG("count %ld rx_state %ld"
+		   "rx_count %ld", count, st_gdata->rx_state,
+		   st_gdata->rx_count);
+
+	ptr = (char *)data;
+	/* tty_receive sent null ? */
+	if (unlikely(ptr == NULL)) {
+		ST_DRV_ERR(" received null from TTY ");
+		return;
+	}
+
+	/* Decode received bytes here */
+	while (count) {
+		if (st_gdata->rx_count) {
+			len = min_t(unsigned int, st_gdata->rx_count, count);
+			memcpy(skb_put(st_gdata->rx_skb, len), ptr, len);
+			st_gdata->rx_count -= len;
+			count -= len;
+			ptr += len;
+
+			if (st_gdata->rx_count)
+				continue;
+
+			/* Check ST RX state machine , where are we? */
+			switch (st_gdata->rx_state) {
+
+				/* Waiting for complete packet ? */
+			case ST_BT_W4_DATA:
+				ST_DRV_DBG("Complete pkt received");
+
+				/* Ask ST CORE to forward
+				 * the packet to protocol driver */
+				st_send_frame(protoid, st_gdata->rx_skb);
+
+				st_gdata->rx_state = ST_W4_PACKET_TYPE;
+				st_gdata->rx_skb = NULL;
+				protoid = ST_MAX;	/* is this required ? */
+				continue;
+
+				/* Waiting for Bluetooth event header ? */
+			case ST_BT_W4_EVENT_HDR:
+				eh = (struct hci_event_hdr *)st_gdata->rx_skb->
+				    data;
+
+				ST_DRV_DBG("Event header: evt 0x%2.2x"
+					   "plen %d", eh->evt, eh->plen);
+
+				st_check_data_len(protoid, eh->plen);
+				continue;
+
+				/* Waiting for Bluetooth acl header ? */
+			case ST_BT_W4_ACL_HDR:
+				ah = (struct hci_acl_hdr *)st_gdata->rx_skb->
+				    data;
+				dlen = __le16_to_cpu(ah->dlen);
+
+				ST_DRV_DBG("ACL header: dlen %d", dlen);
+
+				st_check_data_len(protoid, dlen);
+				continue;
+
+				/* Waiting for Bluetooth sco header ? */
+			case ST_BT_W4_SCO_HDR:
+				sh = (struct hci_sco_hdr *)st_gdata->rx_skb->
+				    data;
+
+				ST_DRV_DBG("SCO header: dlen %d", sh->dlen);
+
+				st_check_data_len(protoid, sh->dlen);
+				continue;
+			case ST_FM_W4_EVENT_HDR:
+				fm = (struct fm_event_hdr *)st_gdata->rx_skb->
+				    data;
+				ST_DRV_DBG("FM Header: ");
+				st_check_data_len(ST_FM, fm->plen);
+				continue;
+				/* TODO : Add GPS packet machine logic here */
+			case ST_GPS_W4_EVENT_HDR:
+				/* [0x09 pkt hdr][R/W byte][2 byte len] */
+				gps = (struct gps_event_hdr *)st_gdata->rx_skb->
+				     data;
+				ST_DRV_DBG("GPS Header: ");
+				st_check_data_len(ST_GPS, gps->plen);
+				continue;
+			}	/* end of switch rx_state */
+		}
+
+		/* end of if rx_count */
+		/* Check first byte of packet and identify module
+		 * owner (BT/FM/GPS) */
+		switch (*ptr) {
+
+			/* Bluetooth event packet? */
+		case HCI_EVENT_PKT:
+			ST_DRV_DBG("Event packet");
+			st_gdata->rx_state = ST_BT_W4_EVENT_HDR;
+			st_gdata->rx_count = HCI_EVENT_HDR_SIZE;
+			type = HCI_EVENT_PKT;
+			protoid = ST_BT;
+			break;
+
+			/* Bluetooth acl packet? */
+		case HCI_ACLDATA_PKT:
+			ST_DRV_DBG("ACL packet");
+			st_gdata->rx_state = ST_BT_W4_ACL_HDR;
+			st_gdata->rx_count = HCI_ACL_HDR_SIZE;
+			type = HCI_ACLDATA_PKT;
+			protoid = ST_BT;
+			break;
+
+			/* Bluetooth sco packet? */
+		case HCI_SCODATA_PKT:
+			ST_DRV_DBG("SCO packet");
+			st_gdata->rx_state = ST_BT_W4_SCO_HDR;
+			st_gdata->rx_count = HCI_SCO_HDR_SIZE;
+			type = HCI_SCODATA_PKT;
+			protoid = ST_BT;
+			break;
+
+			/* Channel 8(FM) packet? */
+		case ST_FM_CH8_PKT:
+			ST_DRV_DBG("FM CH8 packet");
+			type = ST_FM_CH8_PKT;
+			st_gdata->rx_state = ST_FM_W4_EVENT_HDR;
+			st_gdata->rx_count = FM_EVENT_HDR_SIZE;
+			protoid = ST_FM;
+			break;
+
+			/* Channel 9(GPS) packet? */
+		case 0x9:	/*ST_LL_GPS_CH9_PKT */
+			ST_DRV_DBG("GPS CH9 packet");
+			type = 0x9;	/* ST_LL_GPS_CH9_PKT; */
+			protoid = ST_GPS;
+			st_gdata->rx_state = ST_GPS_W4_EVENT_HDR;
+			st_gdata->rx_count = 3;	/* GPS_EVENT_HDR_SIZE -1*/
+			break;
+		case LL_SLEEP_IND:
+		case LL_SLEEP_ACK:
+		case LL_WAKE_UP_IND:
+			/* this takes appropriate action based on
+			 * sleep state received --
+			 */
+			st_ll_sleep_state(*ptr);
+			ptr++;
+			count--;
+			continue;
+		case LL_WAKE_UP_ACK:
+			/* wake up ack received */
+			st_wakeup_ack(*ptr);
+			ptr++;
+			count--;
+			continue;
+			/* Unknow packet? */
+		default:
+			ST_DRV_ERR("Unknown packet type %2.2x", (__u8) *ptr);
+			ptr++;
+			count--;
+			continue;
+		};
+		ptr++;
+		count--;
+
+		switch (protoid) {
+		case ST_BT:
+			/* Allocate new packet to hold received data */
+			st_gdata->rx_skb =
+			    bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC);
+			if (!st_gdata->rx_skb) {
+				ST_DRV_ERR("Can't allocate mem for new packet");
+				st_gdata->rx_state = ST_W4_PACKET_TYPE;
+				st_gdata->rx_count = 0;
+				return;
+			}
+			bt_cb(st_gdata->rx_skb)->pkt_type = type;
+			break;
+		case ST_FM:	/* for FM */
+			st_gdata->rx_skb =
+			    alloc_skb(FM_MAX_FRAME_SIZE, GFP_ATOMIC);
+			if (!st_gdata->rx_skb) {
+				ST_DRV_ERR("Can't allocate mem for new packet");
+				st_gdata->rx_state = ST_W4_PACKET_TYPE;
+				st_gdata->rx_count = 0;
+				return;
+			}
+			/* place holder 0x08 */
+			skb_reserve(st_gdata->rx_skb, 1);
+			st_gdata->rx_skb->cb[0] = ST_FM_CH8_PKT;
+			break;
+		case ST_GPS:
+			/* for GPS */
+			st_gdata->rx_skb =
+			    alloc_skb(300 /*GPS_MAX_FRAME_SIZE */ , GFP_ATOMIC);
+			if (!st_gdata->rx_skb) {
+				ST_DRV_ERR("Can't allocate mem for new packet");
+				st_gdata->rx_state = ST_W4_PACKET_TYPE;
+				st_gdata->rx_count = 0;
+				return;
+			}
+			/* place holder 0x09 */
+			skb_reserve(st_gdata->rx_skb, 1);
+			st_gdata->rx_skb->cb[0] = 0x09;	/*ST_GPS_CH9_PKT; */
+			break;
+		case ST_MAX:
+			break;
+		}
+	}
+	ST_DRV_DBG("done %s", __func__);
+	return;
+}
+
+/* internal de-Q function
+ * -- return previous in-completely written skb
+ *  or return the skb in the txQ
+ */
+struct sk_buff *st_int_dequeue(struct st_data_s *st_data)
+{
+	struct sk_buff *returning_skb;
+
+	ST_DRV_VER("%s", __func__);
+	/* if the previous skb wasn't written completely
+	 */
+	if (st_gdata->tx_skb != NULL) {
+		returning_skb = st_gdata->tx_skb;
+		st_gdata->tx_skb = NULL;
+		return returning_skb;
+	}
+
+	/* de-Q from the txQ always if previous write is complete */
+	return skb_dequeue(&st_gdata->txq);
+}
+
+/* internal Q-ing function
+ * will either Q the skb to txq or the tx_waitq
+ * depending on the ST LL state
+ *
+ * lock the whole func - since ll_getstate and Q-ing should happen
+ * in one-shot
+ */
+void st_int_enqueue(struct sk_buff *skb)
+{
+	unsigned long flags = 0;
+
+	ST_DRV_VER("%s", __func__);
+	/* this function can be invoked in more then one context.
+	 * so have a lock */
+	spin_lock_irqsave(&st_gdata->lock, flags);
+
+	switch (st_ll_getstate()) {
+	case ST_LL_AWAKE:
+		ST_DRV_DBG("ST LL is AWAKE, sending normally");
+		skb_queue_tail(&st_gdata->txq, skb);
+		break;
+	case ST_LL_ASLEEP_TO_AWAKE:
+		skb_queue_tail(&st_gdata->tx_waitq, skb);
+		break;
+	case ST_LL_AWAKE_TO_ASLEEP:	/* host cannot be in this state */
+		ST_DRV_ERR("ST LL is illegal state(%ld),"
+			   "purging received skb.", st_ll_getstate());
+		kfree_skb(skb);
+		break;
+
+	case ST_LL_ASLEEP:
+		/* call a function of ST LL to put data
+		 * in tx_waitQ and wake_ind in txQ
+		 */
+		skb_queue_tail(&st_gdata->tx_waitq, skb);
+		st_ll_wakeup();
+		break;
+	default:
+		ST_DRV_ERR("ST LL is illegal state(%ld),"
+			   "purging received skb.", st_ll_getstate());
+		kfree_skb(skb);
+		break;
+	}
+	spin_unlock_irqrestore(&st_gdata->lock, flags);
+	ST_DRV_VER("done %s", __func__);
+	return;
+}
+
+/*
+ * internal wakeup function
+ * called from either
+ * - TTY layer when write's finished
+ * - st_write (in context of the protocol stack)
+ */
+void st_tx_wakeup(struct st_data_s *st_data)
+{
+	struct sk_buff *skb;
+	unsigned long flags;	/* for irq save flags */
+	ST_DRV_VER("%s", __func__);
+	/* check for sending & set flag sending here */
+	if (test_and_set_bit(ST_TX_SENDING, &st_data->tx_state)) {
+		ST_DRV_DBG("ST already sending");
+		/* keep sending */
+		set_bit(ST_TX_WAKEUP, &st_data->tx_state);
+		return;
+		/* TX_WAKEUP will be checked in another
+		 * context
+		 */
+	}
+	do {			/* come back if st_tx_wakeup is set */
+		/* woke-up to write */
+		clear_bit(ST_TX_WAKEUP, &st_data->tx_state);
+		while ((skb = st_int_dequeue(st_data))) {
+			int len;
+			spin_lock_irqsave(&st_data->lock, flags);
+			/* enable wake-up from TTY */
+			set_bit(TTY_DO_WRITE_WAKEUP, &st_data->tty->flags);
+			len = st_int_write(skb->data, skb->len);
+			skb_pull(skb, len);
+			/* if skb->len = len as expected, skb->len=0 */
+			if (skb->len) {
+				/* would be the next skb to be sent */
+				st_data->tx_skb = skb;
+				spin_unlock_irqrestore(&st_gdata->lock, flags);
+				break;
+			}
+			kfree_skb(skb);
+			spin_unlock_irqrestore(&st_gdata->lock, flags);
+		}
+		/* if wake-up is set in another context- restart sending */
+	} while (test_bit(ST_TX_WAKEUP, &st_data->tx_state));
+
+	/* clear flag sending */
+	clear_bit(ST_TX_SENDING, &st_data->tx_state);
+}
+
+/********************************************************************/
+/* functions called from ST KIM
+*/
+void kim_st_list_protocols(char *buf)
+{
+	unsigned long flags = 0;
+#ifdef DEBUG
+	unsigned char i = ST_MAX;
+#endif
+	spin_lock_irqsave(&st_gdata->lock, flags);
+#ifdef DEBUG			/* more detailed log */
+	for (i = 0; i < ST_MAX; i++) {
+		if (i == 0) {
+			sprintf(buf, "%s is %s", protocol_strngs[i],
+				st_gdata->list[i] !=
+				NULL ? "Registered" : "Unregistered");
+		} else {
+			sprintf(buf, "%s\n%s is %s", buf, protocol_strngs[i],
+				st_gdata->list[i] !=
+				NULL ? "Registered" : "Unregistered");
+		}
+	}
+	sprintf(buf, "%s\n", buf);
+#else /* limited info */
+	sprintf(buf, "BT=%c\nFM=%c\nGPS=%c\n",
+		st_gdata->list[ST_BT] != NULL ? 'R' : 'U',
+		st_gdata->list[ST_FM] != NULL ? 'R' : 'U',
+		st_gdata->list[ST_GPS] != NULL ? 'R' : 'U');
+#endif
+	spin_unlock_irqrestore(&st_gdata->lock, flags);
+}
+
+/********************************************************************/
+/*
+ * functions called from protocol stack drivers
+ * to be EXPORT-ed
+ */
+long st_register(struct st_proto_s *new_proto)
+{
+	long err = ST_SUCCESS;
+	unsigned long flags = 0;
+
+	ST_DRV_DBG("%s(%d) ", __func__, new_proto->type);
+	if (st_gdata == NULL || new_proto == NULL || new_proto->recv == NULL
+	    || new_proto->reg_complete_cb == NULL) {
+		ST_DRV_ERR("gdata/new_proto/recv or reg_complete_cb not ready");
+		return ST_ERR_FAILURE;
+	}
+
+	if (new_proto->type < ST_BT || new_proto->type >= ST_MAX) {
+		ST_DRV_ERR("protocol %d not supported", new_proto->type);
+		return ST_ERR_NOPROTO;
+	}
+
+	if (st_gdata->list[new_proto->type] != NULL) {
+		ST_DRV_ERR("protocol %d already registered", new_proto->type);
+		return ST_ERR_ALREADY;
+	}
+
+	/* can be from process context only */
+	spin_lock_irqsave(&st_gdata->lock, flags);
+
+	if (test_bit(ST_REG_IN_PROGRESS, &st_gdata->st_state)) {
+		ST_DRV_DBG(" ST_REG_IN_PROGRESS:%d ", new_proto->type);
+		/* fw download in progress */
+		st_kim_chip_toggle(new_proto->type, KIM_GPIO_ACTIVE);
+
+		st_gdata->list[new_proto->type] = new_proto;
+		new_proto->write = st_write;
+
+		set_bit(ST_REG_PENDING, &st_gdata->st_state);
+		spin_unlock_irqrestore(&st_gdata->lock, flags);
+		return ST_ERR_PENDING;
+	} else if (is_protocol_list_empty() == ST_EMPTY) {
+		ST_DRV_DBG(" protocol list empty :%d ", new_proto->type);
+		set_bit(ST_REG_IN_PROGRESS, &st_gdata->st_state);
+		st_recv = st_kim_recv;
+
+		/* release lock previously held - re-locked below */
+		spin_unlock_irqrestore(&st_gdata->lock, flags);
+
+		/* enable the ST LL - to set default chip state */
+		st_ll_enable();
+		/* this may take a while to complete
+		 * since it involves BT fw download
+		 */
+		err = st_kim_start();
+		if (err != ST_SUCCESS) {
+			clear_bit(ST_REG_IN_PROGRESS, &st_gdata->st_state);
+			if ((is_protocol_list_empty() != ST_EMPTY) &&
+			    (test_bit(ST_REG_PENDING, &st_gdata->st_state))) {
+				ST_DRV_ERR(" KIM failure complete callback ");
+				st_reg_complete(ST_ERR_FAILURE);
+			}
+
+			return ST_ERR_FAILURE;
+		}
+
+		/* the protocol might require other gpios to be toggled
+		 */
+		st_kim_chip_toggle(new_proto->type, KIM_GPIO_ACTIVE);
+
+		clear_bit(ST_REG_IN_PROGRESS, &st_gdata->st_state);
+		st_recv = st_int_recv;
+
+		/* this is where all pending registration
+		 * are signalled to be complete by calling callback functions
+		 */
+		if ((is_protocol_list_empty() != ST_EMPTY) &&
+		    (test_bit(ST_REG_PENDING, &st_gdata->st_state))) {
+			ST_DRV_VER(" call reg complete callback ");
+			st_reg_complete(ST_SUCCESS);
+		}
+		clear_bit(ST_REG_PENDING, &st_gdata->st_state);
+
+		/* check for already registered once more,
+		 * since the above check is old
+		 */
+		if (st_gdata->list[new_proto->type] != NULL) {
+			ST_DRV_ERR(" proto %d already registered ",
+				   new_proto->type);
+			return ST_ERR_ALREADY;
+		}
+
+		spin_lock_irqsave(&st_gdata->lock, flags);
+		st_gdata->list[new_proto->type] = new_proto;
+		new_proto->write = st_write;
+		spin_unlock_irqrestore(&st_gdata->lock, flags);
+		return err;
+	}
+	/* if fw is already downloaded & new stack registers protocol */
+	else {
+		switch (new_proto->type) {
+		case ST_BT:
+			/* do nothing */
+			break;
+		case ST_FM:
+		case ST_GPS:
+			st_kim_chip_toggle(new_proto->type, KIM_GPIO_ACTIVE);
+			break;
+		case ST_MAX:
+		default:
+			ST_DRV_ERR("%d protocol not supported",
+				   new_proto->type);
+			err = ST_ERR_NOPROTO;
+			/* something wrong */
+			break;
+		}
+		st_gdata->list[new_proto->type] = new_proto;
+		new_proto->write = st_write;
+
+		/* lock already held before entering else */
+		spin_unlock_irqrestore(&st_gdata->lock, flags);
+		return err;
+	}
+	ST_DRV_DBG("done %s(%d) ", __func__, new_proto->type);
+}
+EXPORT_SYMBOL_GPL(st_register);
+
+/* to unregister a protocol -
+ * to be called from protocol stack driver
+ */
+long st_unregister(enum proto_type type)
+{
+	long err = ST_SUCCESS;
+	unsigned long flags = 0;
+
+	ST_DRV_DBG("%s: %d ", __func__, type);
+
+	if (type < ST_BT || type >= ST_MAX) {
+		ST_DRV_ERR(" protocol %d not supported", type);
+		return ST_ERR_NOPROTO;
+	}
+
+	spin_lock_irqsave(&st_gdata->lock, flags);
+
+	if (st_gdata->list[type] == NULL) {
+		ST_DRV_ERR(" protocol %d not registered", type);
+		spin_unlock_irqrestore(&st_gdata->lock, flags);
+		return ST_ERR_NOPROTO;
+	}
+
+	st_gdata->list[type] = NULL;
+
+	/* kim ignores BT in the below function
+	 * and handles the rest, BT is toggled
+	 * only in kim_start and kim_stop
+	 */
+	st_kim_chip_toggle(type, KIM_GPIO_INACTIVE);
+	spin_unlock_irqrestore(&st_gdata->lock, flags);
+
+	if ((is_protocol_list_empty() == ST_EMPTY) &&
+	    (!test_bit(ST_REG_PENDING, &st_gdata->st_state))) {
+		ST_DRV_DBG(" all protocols unregistered ");
+
+		/* stop traffic on tty */
+		if (st_gdata->tty) {
+			tty_ldisc_flush(st_gdata->tty);
+			stop_tty(st_gdata->tty);
+		}
+
+		/* all protocols now unregistered */
+		st_kim_stop();
+		/* disable ST LL */
+		st_ll_disable();
+	}
+	return err;
+}
+
+/*
+ * called in protocol stack drivers
+ * via the write function pointer
+ */
+long st_write(struct sk_buff *skb)
+{
+#ifdef DEBUG
+	enum proto_type protoid = ST_MAX;
+#endif
+	long len;
+	struct st_data_s *st_data = st_gdata;
+
+	if (unlikely(skb == NULL || st_gdata == NULL
+		|| st_gdata->tty == NULL)) {
+		ST_DRV_ERR("data/tty unavailable to perform write");
+		return ST_ERR_FAILURE;
+	}
+#ifdef DEBUG			/* open-up skb to read the 1st byte */
+	switch (skb->data[0]) {
+	case HCI_COMMAND_PKT:
+	case HCI_ACLDATA_PKT:
+	case HCI_SCODATA_PKT:
+		protoid = ST_BT;
+		break;
+	case ST_FM_CH8_PKT:
+		protoid = ST_FM;
+		break;
+	case 0x09:
+		protoid = ST_GPS;
+		break;
+	}
+	if (unlikely(st_gdata->list[protoid] == NULL)) {
+		ST_DRV_ERR(" protocol %d not registered, and writing? ",
+			   protoid);
+		return ST_ERR_FAILURE;
+	}
+#endif
+	ST_DRV_DBG("%d to be written", skb->len);
+	len = skb->len;
+
+	/* st_ll to decide where to enqueue the skb */
+	st_int_enqueue(skb);
+	/* wake up */
+	st_tx_wakeup(st_data);
+
+	/* return number of bytes written */
+	return len;
+}
+
+/* for protocols making use of shared transport */
+EXPORT_SYMBOL_GPL(st_unregister);
+
+/********************************************************************/
+/*
+ * functions called from TTY layer
+ */
+static int st_tty_open(struct tty_struct *tty)
+{
+	int err = ST_SUCCESS;
+	ST_DRV_DBG("%s ", __func__);
+
+	st_gdata->tty = tty;
+
+	/* don't do an wakeup for now */
+	clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
+
+	/* mem already allocated
+	 */
+	tty->receive_room = 65536;
+	/* Flush any pending characters in the driver and discipline. */
+	tty_ldisc_flush(tty);
+	tty_driver_flush_buffer(tty);
+	/*
+	 * signal to UIM via KIM that -
+	 * installation of N_SHARED ldisc is complete
+	 */
+	st_kim_complete();
+	ST_DRV_DBG("done %s", __func__);
+	return err;
+}
+
+static void st_tty_close(struct tty_struct *tty)
+{
+	unsigned char i = ST_MAX;
+	unsigned long flags = 0;
+
+	ST_DRV_DBG("%s ", __func__);
+
+	/* TODO:
+	 * if a protocol has been registered & line discipline
+	 * un-installed for some reason - what should be done ?
+	 */
+	spin_lock_irqsave(&st_gdata->lock, flags);
+	for (i = ST_BT; i < ST_MAX; i++) {
+		if (st_gdata->list[i] != NULL)
+			ST_DRV_ERR("%d not un-registered", i);
+		st_gdata->list[i] = NULL;
+	}
+	spin_unlock_irqrestore(&st_gdata->lock, flags);
+	/*
+	 * signal to UIM via KIM that -
+	 * N_SHARED ldisc is un-installed
+	 */
+	st_kim_complete();
+	st_gdata->tty = NULL;
+	/* Flush any pending characters in the driver and discipline. */
+	tty_ldisc_flush(tty);
+	tty_driver_flush_buffer(tty);
+
+	spin_lock_irqsave(&st_gdata->lock, flags);
+	/* empty out txq and tx_waitq */
+	skb_queue_purge(&st_gdata->txq);
+	skb_queue_purge(&st_gdata->tx_waitq);
+	/* reset the TTY Rx states of ST */
+	st_gdata->rx_count = 0;
+	st_gdata->rx_state = ST_W4_PACKET_TYPE;
+	kfree_skb(st_gdata->rx_skb);
+	st_gdata->rx_skb = NULL;
+	spin_unlock_irqrestore(&st_gdata->lock, flags);
+
+	ST_DRV_DBG("%s: done ", __func__);
+}
+
+static void st_tty_receive(struct tty_struct *tty, const unsigned char *data,
+			   char *tty_flags, int count)
+{
+#ifdef VERBOSE
+	long i;
+	printk(KERN_ERR "incoming data...\n");
+	for (i = 0; i < count; i++)
+		printk(" %x", data[i]);
+	printk(KERN_ERR "\n.. data end\n");
+#endif
+
+	/*
+	 * if fw download is in progress then route incoming data
+	 * to KIM for validation
+	 */
+	st_recv(data, count);
+	ST_DRV_VER("done %s", __func__);
+}
+
+/* wake-up function called in from the TTY layer
+ * inside the internal wakeup function will be called
+ */
+static void st_tty_wakeup(struct tty_struct *tty)
+{
+	ST_DRV_DBG("%s ", __func__);
+	/* don't do an wakeup for now */
+	clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
+
+	/* call our internal wakeup */
+	st_tx_wakeup((void *)st_gdata);
+}
+
+static void st_tty_flush_buffer(struct tty_struct *tty)
+{
+	ST_DRV_DBG("%s ", __func__);
+
+	kfree_skb(st_gdata->tx_skb);
+	st_gdata->tx_skb = NULL;
+
+	tty->ops->flush_buffer(tty);
+	return;
+}
+
+/********************************************************************/
+static int __init st_core_init(void)
+{
+	long err;
+	static struct tty_ldisc_ops *st_ldisc_ops;
+
+	/* populate and register to TTY line discipline */
+	st_ldisc_ops = kzalloc(sizeof(*st_ldisc_ops), GFP_KERNEL);
+	if (!st_ldisc_ops) {
+		ST_DRV_ERR("no mem to allocate");
+		return -ENOMEM;
+	}
+
+	st_ldisc_ops->magic = TTY_LDISC_MAGIC;
+	st_ldisc_ops->name = "n_st";	/*"n_hci"; */
+	st_ldisc_ops->open = st_tty_open;
+	st_ldisc_ops->close = st_tty_close;
+	st_ldisc_ops->receive_buf = st_tty_receive;
+	st_ldisc_ops->write_wakeup = st_tty_wakeup;
+	st_ldisc_ops->flush_buffer = st_tty_flush_buffer;
+	st_ldisc_ops->owner = THIS_MODULE;
+
+	err = tty_register_ldisc(N_SHARED, st_ldisc_ops);
+	if (err) {
+		ST_DRV_ERR("error registering %d line discipline %ld",
+			   N_SHARED, err);
+		kfree(st_ldisc_ops);
+		return err;
+	}
+	ST_DRV_DBG("registered n_shared line discipline");
+
+	st_gdata = kzalloc(sizeof(struct st_data_s), GFP_KERNEL);
+	if (!st_gdata) {
+		ST_DRV_ERR("memory allocation failed");
+		err = tty_unregister_ldisc(N_SHARED);
+		if (err)
+			ST_DRV_ERR("unable to un-register ldisc %ld", err);
+		kfree(st_ldisc_ops);
+		err = -ENOMEM;
+		return err;
+	}
+
+	/* Initialize ST TxQ and Tx waitQ queue head. All BT/FM/GPS module skb's
+	 * will be pushed in this queue for actual transmission.
+	 */
+	skb_queue_head_init(&st_gdata->txq);
+	skb_queue_head_init(&st_gdata->tx_waitq);
+
+	/* Locking used in st_int_enqueue() to avoid multiple execution */
+	spin_lock_init(&st_gdata->lock);
+
+	/* ldisc_ops ref to be only used in __exit of module */
+	st_gdata->ldisc_ops = st_ldisc_ops;
+
+	err = st_kim_init();
+	if (err) {
+		ST_DRV_ERR("error during kim initialization(%ld)", err);
+		kfree(st_gdata);
+		err = tty_unregister_ldisc(N_SHARED);
+		if (err)
+			ST_DRV_ERR("unable to un-register ldisc");
+		kfree(st_ldisc_ops);
+		return -1;
+	}
+
+	err = st_ll_init();
+	if (err) {
+		ST_DRV_ERR("error during st_ll initialization(%ld)", err);
+		err = st_kim_deinit();
+		kfree(st_gdata);
+		err = tty_unregister_ldisc(N_SHARED);
+		if (err)
+			ST_DRV_ERR("unable to un-register ldisc");
+		kfree(st_ldisc_ops);
+		return -1;
+	}
+	return 0;
+}
+
+static void __exit st_core_exit(void)
+{
+	long err;
+	/* internal module cleanup */
+	err = st_ll_deinit();
+	if (err)
+		ST_DRV_ERR("error during deinit of ST LL %ld", err);
+	err = st_kim_deinit();
+	if (err)
+		ST_DRV_ERR("error during deinit of ST KIM %ld", err);
+
+	if (st_gdata != NULL) {
+		/* Free ST Tx Qs and skbs */
+		skb_queue_purge(&st_gdata->txq);
+		skb_queue_purge(&st_gdata->tx_waitq);
+		kfree_skb(st_gdata->rx_skb);
+		kfree_skb(st_gdata->tx_skb);
+		/* TTY ldisc cleanup */
+		err = tty_unregister_ldisc(N_SHARED);
+		if (err)
+			ST_DRV_ERR("unable to un-register ldisc %ld", err);
+		kfree(st_gdata->ldisc_ops);
+		/* free the global data pointer */
+		kfree(st_gdata);
+	}
+}
+
+module_init(st_core_init);
+module_exit(st_core_exit);
+MODULE_AUTHOR("Pavan Savoy <pavan_savoy@ti.com>");
+MODULE_DESCRIPTION("Shared Transport Driver for TI BT/FM/GPS combo chips ");
+MODULE_LICENSE("GPL");
diff --git a/drivers/misc/ti-st/st_core.h b/drivers/misc/ti-st/st_core.h
new file mode 100644
index 000000000000..35515b11da66
--- /dev/null
+++ b/drivers/misc/ti-st/st_core.h
@@ -0,0 +1,91 @@
+/*
+ *  Shared Transport Core header file
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef ST_CORE_H
+#define ST_CORE_H
+
+#include <linux/skbuff.h>
+#include "st.h"
+
+/* states of protocol list */
+#define ST_NOTEMPTY	1
+#define ST_EMPTY	0
+
+/*
+ * possible st_states
+ */
+#define ST_INITIALIZING	1
+#define ST_REG_IN_PROGRESS	2
+#define ST_REG_PENDING		3
+#define ST_WAITING_FOR_RESP	4
+
+/*
+ * local data required for ST/KIM/ST-HCI-LL
+ */
+struct st_data_s {
+	unsigned long st_state;
+/*
+ * an instance of tty_struct & ldisc ops to move around
+ */
+	struct tty_struct *tty;
+	struct tty_ldisc_ops *ldisc_ops;
+/*
+ * the tx skb -
+ * if the skb is already dequeued and the tty failed to write the same
+ * maintain the skb to write in the next transaction
+ */
+	struct sk_buff *tx_skb;
+#define ST_TX_SENDING	1
+#define ST_TX_WAKEUP	2
+	unsigned long tx_state;
+/*
+ * list of protocol registered
+ */
+	struct st_proto_s *list[ST_MAX];
+/*
+ * lock
+ */
+	unsigned long rx_state;
+	unsigned long rx_count;
+	struct sk_buff *rx_skb;
+	struct sk_buff_head txq, tx_waitq;
+	spinlock_t lock;	/* ST LL state lock  */
+};
+
+/* point this to tty->driver->write or tty->ops->write
+ * depending upon the kernel version
+ */
+int st_int_write(const unsigned char *, int);
+/* internal write function, passed onto protocol drivers
+ * via the write function ptr of protocol struct
+ */
+long st_write(struct sk_buff *);
+/* function to be called from ST-LL
+ */
+void st_ll_send_frame(enum proto_type, struct sk_buff *);
+/* internal wake up function */
+void st_tx_wakeup(struct st_data_s *st_data);
+
+#ifdef GPS_STUB_TEST
+int gps_chrdrv_stub_write(const unsigned char*, int);
+void gps_chrdrv_stub_init(void);
+#endif
+
+#endif /*ST_CORE_H */
diff --git a/drivers/misc/ti-st/st_kim.c b/drivers/misc/ti-st/st_kim.c
new file mode 100644
index 000000000000..564bdd4979f4
--- /dev/null
+++ b/drivers/misc/ti-st/st_kim.c
@@ -0,0 +1,717 @@
+/*
+ *  Shared Transport Line discipline driver Core
+ *	Init Manager module responsible for GPIO control
+ *	and firmware download
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/jiffies.h>
+#include <linux/firmware.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/gpio.h>
+
+#include <linux/sched.h>
+
+#include "st_kim.h"
+/* understand BT events for fw response */
+#include <net/bluetooth/bluetooth.h>
+#include <net/bluetooth/hci_core.h>
+#include <net/bluetooth/hci.h>
+
+/* all debug macros go in here */
+#define ST_KIM_ERR(fmt, arg...)  printk(KERN_ERR "(stk):"fmt"\n" , ## arg)
+#if defined(DEBUG)		/* limited debug messages */
+#define ST_KIM_DBG(fmt, arg...)  printk(KERN_INFO "(stk):"fmt"\n" , ## arg)
+#define ST_KIM_VER(fmt, arg...)
+#elif defined(VERBOSE)		/* very verbose */
+#define ST_KIM_DBG(fmt, arg...)  printk(KERN_INFO "(stk):"fmt"\n" , ## arg)
+#define ST_KIM_VER(fmt, arg...)  printk(KERN_INFO "(stk):"fmt"\n" , ## arg)
+#else /* error msgs only */
+#define ST_KIM_DBG(fmt, arg...)
+#define ST_KIM_VER(fmt, arg...)
+#endif
+
+static int kim_probe(struct platform_device *pdev);
+static int kim_remove(struct platform_device *pdev);
+static ssize_t show_pid(struct device *dev, struct device_attribute
+			*attr, char *buf);
+static ssize_t store_pid(struct device *dev, struct device_attribute
+			 *devattr, char *buf, size_t count);
+static ssize_t show_list(struct device *dev, struct device_attribute
+			 *attr, char *buf);
+/* KIM platform device driver structure */
+static struct platform_driver kim_platform_driver = {
+	.probe = kim_probe,
+	.remove = kim_remove,
+	/* TODO: ST driver power management during suspend/resume ?
+	 */
+#if 0
+	.suspend = kim_suspend,
+	.resume = kim_resume,
+#endif
+	.driver = {
+		   .name = "kim",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+/* structures specific for sysfs entries */
+static struct kobj_attribute pid_attr =
+__ATTR(pid, 0644, (void *)show_pid, (void *)store_pid);
+
+static struct kobj_attribute list_protocols =
+__ATTR(protocols, 0444, (void *)show_list, NULL);
+
+static struct attribute *uim_attrs[] = {
+	&pid_attr.attr,
+	/* add more debug sysfs entries */
+	&list_protocols.attr,
+	NULL,
+};
+
+static struct attribute_group uim_attr_grp = {
+	.attrs = uim_attrs,
+};
+
+/* strings to be used for rfkill entries and by
+ * ST Core to be used for sysfs debug entry
+ */
+#define PROTO_ENTRY(type, name)	name
+const unsigned char *protocol_names[] = {
+	PROTO_ENTRY(ST_BT, "Bluetooth"),
+	PROTO_ENTRY(ST_FM, "FM"),
+	PROTO_ENTRY(ST_GPS, "GPS"),
+};
+static int kim_toggle_radio(void*, bool);
+static const struct rfkill_ops kim_rfkill_ops = {
+	.set_block = kim_toggle_radio,
+};
+
+static struct kim_data_s *kim_gdata;
+
+/**********************************************************************/
+/* internal functions */
+
+/*
+ * function to return whether the firmware response was proper
+ * in case of error don't complete so that waiting for proper
+ * response times out
+ */
+void validate_firmware_response(struct sk_buff *skb)
+{
+	if (unlikely(skb->data[5] != 0)) {
+		ST_KIM_ERR("no proper response during fw download");
+		ST_KIM_ERR("data6 %x", skb->data[5]);
+		return;		/* keep waiting for the proper response */
+	}
+	/* becos of all the script being downloaded */
+	complete_all(&kim_gdata->kim_rcvd);
+	kfree_skb(skb);
+}
+
+/* check for data len received inside kim_int_recv
+ * most often hit the last case to update state to waiting for data
+ */
+static inline int kim_check_data_len(int len)
+{
+	register int room = skb_tailroom(kim_gdata->rx_skb);
+
+	ST_KIM_DBG("len %d room %d", len, room);
+
+	if (!len) {
+		validate_firmware_response(kim_gdata->rx_skb);
+	} else if (len > room) {
+		/* Received packet's payload length is larger.
+		 * We can't accommodate it in created skb.
+		 */
+		ST_KIM_ERR("Data length is too large len %d room %d", len,
+			   room);
+		kfree_skb(kim_gdata->rx_skb);
+	} else {
+		/* Packet header has non-zero payload length and
+		 * we have enough space in created skb. Lets read
+		 * payload data */
+		kim_gdata->rx_state = ST_BT_W4_DATA;
+		kim_gdata->rx_count = len;
+		return len;
+	}
+
+	/* Change ST LL state to continue to process next
+	 * packet */
+	kim_gdata->rx_state = ST_W4_PACKET_TYPE;
+	kim_gdata->rx_skb = NULL;
+	kim_gdata->rx_count = 0;
+
+	return 0;
+}
+
+/* receive function called during firmware download
+ * - firmware download responses on different UART drivers
+ *   have been observed to come in bursts of different
+ *   tty_receive and hence the logic
+ */
+void kim_int_recv(const unsigned char *data, long count)
+{
+	register char *ptr;
+	struct hci_event_hdr *eh;
+	register int len = 0, type = 0;
+
+	ST_KIM_DBG("%s", __func__);
+	/* Decode received bytes here */
+	ptr = (char *)data;
+	if (unlikely(ptr == NULL)) {
+		ST_KIM_ERR(" received null from TTY ");
+		return;
+	}
+	while (count) {
+		if (kim_gdata->rx_count) {
+			len = min_t(unsigned int, kim_gdata->rx_count, count);
+			memcpy(skb_put(kim_gdata->rx_skb, len), ptr, len);
+			kim_gdata->rx_count -= len;
+			count -= len;
+			ptr += len;
+
+			if (kim_gdata->rx_count)
+				continue;
+
+			/* Check ST RX state machine , where are we? */
+			switch (kim_gdata->rx_state) {
+				/* Waiting for complete packet ? */
+			case ST_BT_W4_DATA:
+				ST_KIM_DBG("Complete pkt received");
+				validate_firmware_response(kim_gdata->rx_skb);
+				kim_gdata->rx_state = ST_W4_PACKET_TYPE;
+				kim_gdata->rx_skb = NULL;
+				continue;
+				/* Waiting for Bluetooth event header ? */
+			case ST_BT_W4_EVENT_HDR:
+				eh = (struct hci_event_hdr *)kim_gdata->
+				    rx_skb->data;
+				ST_KIM_DBG("Event header: evt 0x%2.2x"
+					   "plen %d", eh->evt, eh->plen);
+				kim_check_data_len(eh->plen);
+				continue;
+			}	/* end of switch */
+		}		/* end of if rx_state */
+		switch (*ptr) {
+			/* Bluetooth event packet? */
+		case HCI_EVENT_PKT:
+			ST_KIM_DBG("Event packet");
+			kim_gdata->rx_state = ST_BT_W4_EVENT_HDR;
+			kim_gdata->rx_count = HCI_EVENT_HDR_SIZE;
+			type = HCI_EVENT_PKT;
+			break;
+		default:
+			ST_KIM_DBG("unknown packet");
+			ptr++;
+			count--;
+			continue;
+		}		/* end of switch *ptr */
+		ptr++;
+		count--;
+		kim_gdata->rx_skb =
+		    bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC);
+		if (!kim_gdata->rx_skb) {
+			ST_KIM_ERR("can't allocate mem for new packet");
+			kim_gdata->rx_state = ST_W4_PACKET_TYPE;
+			kim_gdata->rx_count = 0;
+			return;
+		} /* not necessary in this case */
+		bt_cb(kim_gdata->rx_skb)->pkt_type = type;
+	}			/* end of while count */
+	ST_KIM_DBG("done %s", __func__);
+	return;
+}
+
+static long read_local_version(char *bts_scr_name)
+{
+	unsigned short version = 0, chip = 0, min_ver = 0, maj_ver = 0;
+	char read_ver_cmd[] = { 0x01, 0x01, 0x10, 0x00 };
+
+	ST_KIM_DBG("%s", __func__);
+
+	INIT_COMPLETION(kim_gdata->kim_rcvd);
+	if (4 != st_int_write(read_ver_cmd, 4)) {
+		ST_KIM_ERR("kim: couldn't write 4 bytes");
+		return ST_ERR_FAILURE;
+	}
+
+	if (!wait_for_completion_timeout
+	    (&kim_gdata->kim_rcvd, msecs_to_jiffies(CMD_RESP_TIME))) {
+		ST_KIM_ERR(" waiting for ver info- timed out ");
+		return ST_ERR_FAILURE;
+	}
+
+	version =
+	    MAKEWORD(kim_gdata->resp_buffer[13], kim_gdata->resp_buffer[14]);
+	chip = (version & 0x7C00) >> 10;
+	min_ver = (version & 0x007F);
+	maj_ver = (version & 0x0380) >> 7;
+
+	if (version & 0x8000)
+		maj_ver |= 0x0008;
+
+	sprintf(bts_scr_name, "TIInit_%d.%d.%d.bts", chip, maj_ver, min_ver);
+	ST_KIM_DBG("%s", bts_scr_name);
+	return ST_SUCCESS;
+}
+
+/* internal function which parses through the .bts firmware script file
+ * intreprets SEND, DELAY actions only as of now
+ */
+static long download_firmware(void)
+{
+	long err = ST_SUCCESS;
+	long len = 0;
+	register unsigned char *ptr = NULL;
+	register unsigned char *action_ptr = NULL;
+	unsigned char bts_scr_name[30] = { 0 };	/* 30 char long bts scr name? */
+
+	ST_KIM_VER("%s", __func__);
+
+	err = read_local_version(bts_scr_name);
+	if (err != ST_SUCCESS) {
+		ST_KIM_ERR("kim: failed to read local ver");
+		return err;
+	}
+	err =
+	    request_firmware(&kim_gdata->fw_entry, bts_scr_name,
+			     &kim_gdata->kim_pdev->dev);
+	if (unlikely((err != 0) || (kim_gdata->fw_entry->data == NULL) ||
+		     (kim_gdata->fw_entry->size == 0))) {
+		ST_KIM_ERR(" request_firmware failed(errno %ld) for %s", err,
+			   bts_scr_name);
+		return ST_ERR_FAILURE;
+	}
+	ptr = (void *)kim_gdata->fw_entry->data;
+	len = kim_gdata->fw_entry->size;
+	/* bts_header to remove out magic number and
+	 * version
+	 */
+	ptr += sizeof(struct bts_header);
+	len -= sizeof(struct bts_header);
+
+	while (len > 0 && ptr) {
+		ST_KIM_VER(" action size %d, type %d ",
+			   ((struct bts_action *)ptr)->size,
+			   ((struct bts_action *)ptr)->type);
+
+		switch (((struct bts_action *)ptr)->type) {
+		case ACTION_SEND_COMMAND:	/* action send */
+			action_ptr = &(((struct bts_action *)ptr)->data[0]);
+			if (unlikely
+			    (((struct hci_command *)action_ptr)->opcode ==
+			     0xFF36)) {
+				/* ignore remote change
+				 * baud rate HCI VS command */
+				ST_KIM_ERR
+				    (" change remote baud\
+				    rate command in firmware");
+				break;
+			}
+
+			INIT_COMPLETION(kim_gdata->kim_rcvd);
+			err = st_int_write(((struct bts_action_send *)
+					    action_ptr)->data,
+					   ((struct bts_action *)ptr)->size);
+			if (unlikely(err < 0)) {
+				release_firmware(kim_gdata->fw_entry);
+				return ST_ERR_FAILURE;
+			}
+			if (!wait_for_completion_timeout
+			    (&kim_gdata->kim_rcvd,
+			     msecs_to_jiffies(CMD_RESP_TIME))) {
+				ST_KIM_ERR
+				    (" response timeout during fw download ");
+				/* timed out */
+				release_firmware(kim_gdata->fw_entry);
+				return ST_ERR_FAILURE;
+			}
+			break;
+		case ACTION_DELAY:	/* sleep */
+			ST_KIM_DBG("sleep command in scr");
+			action_ptr = &(((struct bts_action *)ptr)->data[0]);
+			mdelay(((struct bts_action_delay *)action_ptr)->msec);
+			break;
+		}
+		len =
+		    len - (sizeof(struct bts_action) +
+			   ((struct bts_action *)ptr)->size);
+		ptr =
+		    ptr + sizeof(struct bts_action) +
+		    ((struct bts_action *)ptr)->size;
+	}
+	/* fw download complete */
+	release_firmware(kim_gdata->fw_entry);
+	return ST_SUCCESS;
+}
+
+/**********************************************************************/
+/* functions called from ST core */
+
+/* function to toggle the GPIO
+ * needs to know whether the GPIO is active high or active low
+ */
+void st_kim_chip_toggle(enum proto_type type, enum kim_gpio_state state)
+{
+	ST_KIM_DBG(" %s ", __func__);
+
+	if (kim_gdata->gpios[type] == -1) {
+		ST_KIM_DBG(" gpio not requested for protocol %s",
+			   protocol_names[type]);
+		return;
+	}
+	switch (type) {
+	case ST_BT:
+		/*Do Nothing */
+		break;
+
+	case ST_FM:
+		if (state == KIM_GPIO_ACTIVE)
+			gpio_set_value(kim_gdata->gpios[ST_FM], GPIO_LOW);
+		else
+			gpio_set_value(kim_gdata->gpios[ST_FM], GPIO_HIGH);
+		break;
+
+	case ST_GPS:
+		if (state == KIM_GPIO_ACTIVE)
+			gpio_set_value(kim_gdata->gpios[ST_GPS], GPIO_HIGH);
+		else
+			gpio_set_value(kim_gdata->gpios[ST_GPS], GPIO_LOW);
+		break;
+
+	case ST_MAX:
+	default:
+		break;
+	}
+
+	return;
+}
+
+/* called from ST Core, when REG_IN_PROGRESS (registration in progress)
+ * can be because of
+ * 1. response to read local version
+ * 2. during send/recv's of firmware download
+ */
+void st_kim_recv(const unsigned char *data, long count)
+{
+	ST_KIM_DBG(" %s ", __func__);
+	/* copy to local buffer */
+	if (unlikely(data[4] == 0x01 && data[5] == 0x10 && data[0] == 0x04)) {
+		/* must be the read_ver_cmd */
+		memcpy(kim_gdata->resp_buffer, data, count);
+		complete_all(&kim_gdata->kim_rcvd);
+		return;
+	} else {
+		kim_int_recv(data, count);
+		/* either completes or times out */
+	}
+	return;
+}
+
+/* to signal completion of line discipline installation
+ * called from ST Core, upon tty_open
+ */
+void st_kim_complete(void)
+{
+	complete(&kim_gdata->ldisc_installed);
+}
+
+/* called from ST Core upon 1st registration
+*/
+long st_kim_start(void)
+{
+	long err = ST_SUCCESS;
+	long retry = POR_RETRY_COUNT;
+	ST_KIM_DBG(" %s", __func__);
+
+	do {
+		/* Configure BT nShutdown to HIGH state */
+		gpio_set_value(kim_gdata->gpios[ST_BT], GPIO_LOW);
+		mdelay(5);	/* FIXME: a proper toggle */
+		gpio_set_value(kim_gdata->gpios[ST_BT], GPIO_HIGH);
+		mdelay(100);
+
+		/* re-initialize the completion */
+		INIT_COMPLETION(kim_gdata->ldisc_installed);
+		/* send signal to UIM */
+		err = kill_pid(find_get_pid(kim_gdata->uim_pid), SIGUSR2, 0);
+		if (err != 0) {
+			ST_KIM_VER(" sending SIGUSR2 to uim failed %ld", err);
+			err = ST_ERR_FAILURE;
+			continue;
+		}
+		/* wait for ldisc to be installed */
+		err = wait_for_completion_timeout(&kim_gdata->ldisc_installed,
+				msecs_to_jiffies(LDISC_TIME));
+		if (!err) {	/* timeout */
+			ST_KIM_ERR("line disc installation timed out ");
+			err = ST_ERR_FAILURE;
+			continue;
+		} else {
+			/* ldisc installed now */
+			ST_KIM_DBG(" line discipline installed ");
+			err = download_firmware();
+			if (err != ST_SUCCESS) {
+				ST_KIM_ERR("download firmware failed");
+				continue;
+			} else {	/* on success don't retry */
+				break;
+			}
+		}
+	} while (retry--);
+	return err;
+}
+
+/* called from ST Core, on the last un-registration
+*/
+long st_kim_stop(void)
+{
+	long err = ST_SUCCESS;
+
+	INIT_COMPLETION(kim_gdata->ldisc_installed);
+	/* send signal to UIM */
+	err = kill_pid(find_get_pid(kim_gdata->uim_pid), SIGUSR2, 1);
+	if (err != 0) {
+		ST_KIM_ERR("sending SIGUSR2 to uim failed %ld", err);
+		return ST_ERR_FAILURE;
+	}
+
+	/* wait for ldisc to be un-installed */
+	err = wait_for_completion_timeout(&kim_gdata->ldisc_installed,
+			msecs_to_jiffies(LDISC_TIME));
+	if (!err) {		/* timeout */
+		ST_KIM_ERR(" timed out waiting for ldisc to be un-installed");
+		return ST_ERR_FAILURE;
+	}
+
+	/* By default configure BT nShutdown to LOW state */
+	gpio_set_value(kim_gdata->gpios[ST_BT], GPIO_LOW);
+	mdelay(1);
+	gpio_set_value(kim_gdata->gpios[ST_BT], GPIO_HIGH);
+	mdelay(1);
+	gpio_set_value(kim_gdata->gpios[ST_BT], GPIO_LOW);
+	return err;
+}
+
+/**********************************************************************/
+/* functions called from subsystems */
+
+/* called when sysfs entry is written to */
+static ssize_t store_pid(struct device *dev, struct device_attribute
+			 *devattr, char *buf, size_t count)
+{
+	ST_KIM_DBG("%s: pid %s ", __func__, buf);
+	sscanf(buf, "%ld", &kim_gdata->uim_pid);
+	/* to be made use by kim_start to signal SIGUSR2
+	 */
+	return strlen(buf);
+}
+
+/* called when sysfs entry is read from */
+static ssize_t show_pid(struct device *dev, struct device_attribute
+			*attr, char *buf)
+{
+	sprintf(buf, "%ld", kim_gdata->uim_pid);
+	return strlen(buf);
+}
+
+/* called when sysfs entry is read from */
+static ssize_t show_list(struct device *dev, struct device_attribute
+			 *attr, char *buf)
+{
+	kim_st_list_protocols(buf);
+	return strlen(buf);
+}
+
+#ifdef LEGACY_RFKILL_SUPPORT
+/* function called from rfkill subsystem, when someone from
+ * user space would write 0/1 on the sysfs entry
+ * /sys/class/rfkill/rfkill0,1,3/state
+ */
+static int kim_toggle_radio(void *data, bool blocked)
+{
+	enum proto_type type = *((enum proto_type *)data);
+	ST_KIM_DBG(" %s: %d ", __func__, type);
+
+	switch (type) {
+	case ST_BT:
+			/* do nothing */
+		break;
+	case ST_FM:
+	case ST_GPS:
+		if (blocked)
+			st_kim_chip_toggle(type, KIM_GPIO_INACTIVE);
+		else
+			st_kim_chip_toggle(type, KIM_GPIO_ACTIVE);
+		break;
+	case ST_MAX:
+		ST_KIM_ERR(" wrong proto type ");
+		break;
+	}
+	return ST_SUCCESS;
+}
+#endif
+
+/**********************************************************************/
+/* functions called from platform device driver subsystem
+ * need to have a relevant platform device entry in the platform's
+ * board-*.c file
+ */
+
+static int kim_probe(struct platform_device *pdev)
+{
+	long status;
+	long proto;
+	long *gpios = pdev->dev.platform_data;
+
+	for (proto = 0; proto < ST_MAX; proto++) {
+		kim_gdata->gpios[proto] = gpios[proto];
+		ST_KIM_VER(" %ld gpio to be requested", gpios[proto]);
+	}
+
+	for (proto = 0; (proto < ST_MAX) && (gpios[proto] != -1); proto++) {
+		/* Claim the Bluetooth/FM/GPIO
+		 * nShutdown gpio from the system
+		 */
+		status = gpio_request(gpios[proto], "kim");
+		if (unlikely(status)) {
+			ST_KIM_ERR(" gpio %ld request failed ", gpios[proto]);
+			proto -= 1;
+			while (proto >= 0) {
+				if (gpios[proto] != -1)
+					gpio_free(gpios[proto]);
+			}
+			return status;
+		}
+
+		/* Configure nShutdown GPIO as output=0 */
+		status =
+		    gpio_direction_output(gpios[proto], 0);
+		if (unlikely(status)) {
+			ST_KIM_ERR(" unable to configure gpio %ld",
+				   gpios[proto]);
+			proto -= 1;
+			while (proto >= 0) {
+				if (gpios[proto] != -1)
+					gpio_free(gpios[proto]);
+			}
+			return status;
+		}
+	}
+	/* pdev to contain BT, FM and GPS enable/N-Shutdown GPIOs
+	 * execute request_gpio, set output direction
+	 */
+	kim_gdata->kim_kobj = kobject_create_and_add("uim", NULL);
+	/* create the sysfs entry for UIM to put in pid */
+	if (sysfs_create_group(kim_gdata->kim_kobj, &uim_attr_grp)) {
+		ST_KIM_ERR(" sysfs entry creation failed");
+		kobject_put(kim_gdata->kim_kobj);
+		/* free requested GPIOs and fail probe */
+		for (proto = ST_BT; proto < ST_MAX; proto++) {
+			if (gpios[proto] != -1)
+				gpio_free(gpios[proto]);
+		}
+		return -1;	/* fail insmod */
+	}
+
+	ST_KIM_DBG(" sysfs entry created ");
+
+	/* get reference of pdev for request_firmware
+	 */
+	kim_gdata->kim_pdev = pdev;
+	init_completion(&kim_gdata->kim_rcvd);
+	init_completion(&kim_gdata->ldisc_installed);
+#ifdef LEGACY_RFKILL_SUPPORT
+	for (proto = 0; (proto < ST_MAX) && (gpios[proto] != -1); proto++) {
+		/* TODO: should all types be rfkill_type_bt ? */
+		kim_gdata->rfkill[proto] = rfkill_alloc(protocol_names[proto],
+			&pdev->dev, RFKILL_TYPE_BLUETOOTH,
+			&kim_rfkill_ops, &proto);
+		if (kim_gdata->rfkill[proto] == NULL) {
+			ST_KIM_ERR("cannot create rfkill entry for gpio %ld",
+				   gpios[proto]);
+			continue;
+		}
+		status = rfkill_register(kim_gdata->rfkill[proto]);
+		if (unlikely(status)) {
+			ST_KIM_ERR("rfkill registration failed for gpio %ld",
+				   gpios[proto]);
+			rfkill_unregister(kim_gdata->rfkill[proto]);
+			continue;
+		}
+		ST_KIM_DBG("rfkill entry created for %ld", gpios[proto]);
+	}
+#endif
+	return ST_SUCCESS;
+}
+
+static int kim_remove(struct platform_device *pdev)
+{
+	/* free the GPIOs requested
+	 */
+	long *gpios = pdev->dev.platform_data;
+	long proto;
+
+	for (proto = 0; (proto < ST_MAX) && (gpios[proto] != -1); proto++) {
+		/* Claim the Bluetooth/FM/GPIO
+		 * nShutdown gpio from the system
+		 */
+		gpio_free(gpios[proto]);
+#ifdef LEGACY_RFKILL_SUPPORT
+		rfkill_unregister(kim_gdata->rfkill[proto]);
+		rfkill_destroy(kim_gdata->rfkill[proto]);
+		kim_gdata->rfkill[proto] = NULL;
+#endif
+	}
+	ST_KIM_DBG("kim: GPIO Freed");
+	/* delete the sysfs entries */
+	sysfs_remove_group(kim_gdata->kim_kobj, &uim_attr_grp);
+	kobject_put(kim_gdata->kim_kobj);
+	kim_gdata->kim_pdev = NULL;
+	return ST_SUCCESS;
+}
+
+/**********************************************************************/
+/* entry point for ST KIM module, called in from ST Core */
+
+long st_kim_init(void)
+{
+	long ret = ST_SUCCESS;
+	kim_gdata = kzalloc(sizeof(struct kim_data_s), GFP_ATOMIC);
+	if (!kim_gdata) {
+		ST_KIM_ERR("no mem to allocate");
+		return -ENOMEM;
+	}
+	ret = platform_driver_register(&kim_platform_driver);
+	if (ret != 0) {
+		ST_KIM_ERR("platform drv registration failed");
+		return ST_ERR_FAILURE;
+	}
+	return ST_SUCCESS;
+}
+
+long st_kim_deinit(void)
+{
+	/* the following returns void */
+	platform_driver_unregister(&kim_platform_driver);
+	kfree(kim_gdata);
+	kim_gdata = NULL;
+	return ST_SUCCESS;
+}
diff --git a/drivers/misc/ti-st/st_kim.h b/drivers/misc/ti-st/st_kim.h
new file mode 100644
index 000000000000..4e73bb49b64f
--- /dev/null
+++ b/drivers/misc/ti-st/st_kim.h
@@ -0,0 +1,151 @@
+/*
+ *  Shared Transport Line discipline driver Core
+ *	Init Manager Module header file
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef ST_KIM_H
+#define ST_KIM_H
+
+#include <linux/types.h>
+#include "st.h"
+#include "st_core.h"
+#include "st_ll.h"
+#include <linux/rfkill.h>
+
+/* time in msec to wait for
+ * line discipline to be installed
+ */
+#define LDISC_TIME	500
+#define CMD_RESP_TIME	500
+#define MAKEWORD(a, b)  ((unsigned short)(((unsigned char)(a)) \
+	| ((unsigned short)((unsigned char)(b))) << 8))
+
+#define GPIO_HIGH 1
+#define GPIO_LOW  0
+
+/* the Power-On-Reset logic, requires to attempt
+ * to download firmware onto chip more than once
+ * since the self-test for chip takes a while
+ */
+#define POR_RETRY_COUNT 5
+/*
+ * legacy rfkill support where-in 3 rfkill
+ * devices are created for the 3 gpios
+ * that ST has requested
+ */
+#define LEGACY_RFKILL_SUPPORT
+/*
+ * header file for ST provided by KIM
+ */
+struct kim_data_s {
+	long uim_pid;
+	struct platform_device *kim_pdev;
+	struct completion kim_rcvd, ldisc_installed;
+	/* MAX len of the .bts firmware script name */
+	char resp_buffer[30];
+	const struct firmware *fw_entry;
+	long gpios[ST_MAX];
+	struct kobject *kim_kobj;
+/* used by kim_int_recv to validate fw response */
+	unsigned long rx_state;
+	unsigned long rx_count;
+	struct sk_buff *rx_skb;
+#ifdef LEGACY_RFKILL_SUPPORT
+	struct rfkill *rfkill[ST_MAX];
+#endif
+};
+
+long st_kim_init(void);
+long st_kim_deinit(void);
+
+long st_kim_start(void);
+long st_kim_stop(void);
+/*
+ * called from st_tty_receive to authenticate fw_download
+ */
+void st_kim_recv(const unsigned char *, long count);
+
+void st_kim_chip_toggle(enum proto_type, enum kim_gpio_state);
+
+void st_kim_complete(void);
+
+/* function called from ST KIM to ST Core, to
+ * list out the protocols registered
+ */
+void kim_st_list_protocols(char *);
+
+/*
+ * BTS headers
+ */
+#define ACTION_SEND_COMMAND     1
+#define ACTION_WAIT_EVENT       2
+#define ACTION_SERIAL           3
+#define ACTION_DELAY            4
+#define ACTION_RUN_SCRIPT       5
+#define ACTION_REMARKS          6
+
+/*
+ *  * BRF Firmware header
+ *   */
+struct bts_header {
+	uint32_t magic;
+	uint32_t version;
+	uint8_t future[24];
+	uint8_t actions[0];
+} __attribute__ ((packed));
+
+/*
+ *  * BRF Actions structure
+ *   */
+struct bts_action {
+	uint16_t type;
+	uint16_t size;
+	uint8_t data[0];
+} __attribute__ ((packed));
+
+struct bts_action_send {
+	uint8_t data[0];
+} __attribute__ ((packed));
+
+struct bts_action_wait {
+	uint32_t msec;
+	uint32_t size;
+	uint8_t data[0];
+} __attribute__ ((packed));
+
+struct bts_action_delay {
+	uint32_t msec;
+} __attribute__ ((packed));
+
+struct bts_action_serial {
+	uint32_t baud;
+	uint32_t flow_control;
+} __attribute__ ((packed));
+
+/* for identifying the change speed HCI VS
+ * command
+ */
+struct hci_command {
+	uint8_t prefix;
+	uint16_t opcode;
+	uint8_t plen;
+	uint32_t speed;
+} __attribute__ ((packed));
+
+
+#endif /* ST_KIM_H */
diff --git a/drivers/misc/ti-st/st_ll.c b/drivers/misc/ti-st/st_ll.c
new file mode 100644
index 000000000000..5e42cbe4ad95
--- /dev/null
+++ b/drivers/misc/ti-st/st_ll.c
@@ -0,0 +1,169 @@
+/*
+ *  Shared Transport driver
+ *	HCI-LL module responsible for TI proprietary HCI_LL protocol
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include "st_ll.h"
+
+/* all debug macros go in here */
+#define ST_LL_ERR(fmt, arg...)  printk(KERN_ERR "(stll):"fmt"\n" , ## arg)
+#if defined(DEBUG)		/* limited debug messages */
+#define ST_LL_DBG(fmt, arg...)  printk(KERN_INFO "(stll):"fmt"\n" , ## arg)
+#define ST_LL_VER(fmt, arg...)
+#elif defined(VERBOSE)		/* very verbose */
+#define ST_LL_DBG(fmt, arg...)  printk(KERN_INFO "(stll):"fmt"\n" , ## arg)
+#define ST_LL_VER(fmt, arg...)  printk(KERN_INFO "(stll):"fmt"\n" , ## arg)
+#else /* error msgs only */
+#define ST_LL_DBG(fmt, arg...)
+#define ST_LL_VER(fmt, arg...)
+#endif
+
+static struct ll_struct_s *ll;
+
+/**********************************************************************/
+/* internal functions */
+static void send_ll_cmd(unsigned char cmd)
+{
+
+	ST_LL_DBG("%s: writing %x", __func__, cmd);
+	st_int_write(&cmd, 1);
+	return;
+}
+
+static void ll_device_want_to_sleep(void)
+{
+	ST_LL_DBG("%s", __func__);
+	/* sanity check */
+	if (ll->ll_state != ST_LL_AWAKE)
+		ST_LL_ERR("ERR hcill: ST_LL_GO_TO_SLEEP_IND"
+			  "in state %ld", ll->ll_state);
+
+	send_ll_cmd(LL_SLEEP_ACK);
+	/* update state */
+	ll->ll_state = ST_LL_ASLEEP;
+}
+
+static void ll_device_want_to_wakeup(void)
+{
+	/* diff actions in diff states */
+	switch (ll->ll_state) {
+	case ST_LL_ASLEEP:
+		send_ll_cmd(LL_WAKE_UP_ACK);	/* send wake_ack */
+		break;
+	case ST_LL_ASLEEP_TO_AWAKE:
+		/* duplicate wake_ind */
+		ST_LL_ERR("duplicate wake_ind while waiting for Wake ack");
+		break;
+	case ST_LL_AWAKE:
+		/* duplicate wake_ind */
+		ST_LL_ERR("duplicate wake_ind already AWAKE");
+		break;
+	case ST_LL_AWAKE_TO_ASLEEP:
+		/* duplicate wake_ind */
+		ST_LL_ERR("duplicate wake_ind");
+		break;
+	}
+	/* update state */
+	ll->ll_state = ST_LL_AWAKE;
+}
+
+/**********************************************************************/
+/* functions invoked by ST Core */
+
+/* called when ST Core wants to
+ * enable ST LL */
+void st_ll_enable(void)
+{
+	ll->ll_state = ST_LL_AWAKE;
+}
+
+/* called when ST Core /local module wants to
+ * disable ST LL */
+void st_ll_disable(void)
+{
+	ll->ll_state = ST_LL_INVALID;
+}
+
+/* called when ST Core wants to update the state */
+void st_ll_wakeup(void)
+{
+	if (likely(ll->ll_state != ST_LL_AWAKE)) {
+		send_ll_cmd(LL_WAKE_UP_IND);	/* WAKE_IND */
+		ll->ll_state = ST_LL_ASLEEP_TO_AWAKE;
+	} else {
+		/* don't send the duplicate wake_indication */
+		ST_LL_ERR(" Chip already AWAKE ");
+	}
+}
+
+/* called when ST Core wants the state */
+unsigned long st_ll_getstate(void)
+{
+	ST_LL_DBG(" returning state %ld", ll->ll_state);
+	return ll->ll_state;
+}
+
+/* called from ST Core, when a PM related packet arrives */
+unsigned long st_ll_sleep_state(unsigned char cmd)
+{
+	switch (cmd) {
+	case LL_SLEEP_IND:	/* sleep ind */
+		ST_LL_DBG("sleep indication recvd");
+		ll_device_want_to_sleep();
+		break;
+	case LL_SLEEP_ACK:	/* sleep ack */
+		ST_LL_ERR("sleep ack rcvd: host shouldn't");
+		break;
+	case LL_WAKE_UP_IND:	/* wake ind */
+		ST_LL_DBG("wake indication recvd");
+		ll_device_want_to_wakeup();
+		break;
+	case LL_WAKE_UP_ACK:	/* wake ack */
+		ST_LL_DBG("wake ack rcvd");
+		ll->ll_state = ST_LL_AWAKE;
+		break;
+	default:
+		ST_LL_ERR(" unknown input/state ");
+		return ST_ERR_FAILURE;
+	}
+	return ST_SUCCESS;
+}
+
+/* Called from ST CORE to initialize ST LL */
+long st_ll_init(void)
+{
+	long err = ST_SUCCESS;
+
+	/* Allocate memory for ST LL private structure */
+	ll = kzalloc(sizeof(*ll), GFP_ATOMIC);
+	if (!ll) {
+		ST_LL_ERR("kzalloc failed to alloc memory for ST LL");
+		err = -ENOMEM;
+		return err;
+	}
+	/* set state to invalid */
+	ll->ll_state = ST_LL_INVALID;
+	return err;
+}
+
+/* Called from ST CORE to de-initialize ST LL */
+long st_ll_deinit(void)
+{
+	kfree(ll);
+	return 0;
+}
diff --git a/drivers/misc/ti-st/st_ll.h b/drivers/misc/ti-st/st_ll.h
new file mode 100644
index 000000000000..2456f190d7f5
--- /dev/null
+++ b/drivers/misc/ti-st/st_ll.h
@@ -0,0 +1,67 @@
+/*
+ *  Shared Transport Low Level (ST LL)
+ *
+ *  Copyright (C) 2009 Texas Instruments
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef ST_LL_H
+#define ST_LL_H
+
+#include <linux/skbuff.h>
+#include "st.h"
+#include "st_core.h"
+
+/* ST LL receiver states */
+#define ST_W4_PACKET_TYPE       0
+#define ST_BT_W4_EVENT_HDR      1
+#define ST_BT_W4_ACL_HDR        2
+#define ST_BT_W4_SCO_HDR        3
+#define ST_BT_W4_DATA           4
+#define ST_FM_W4_EVENT_HDR      5
+#define ST_GPS_W4_EVENT_HDR     6
+
+/* ST LL state machines */
+#define ST_LL_ASLEEP               0
+#define ST_LL_ASLEEP_TO_AWAKE      1
+#define ST_LL_AWAKE                2
+#define ST_LL_AWAKE_TO_ASLEEP      3
+#define ST_LL_INVALID		   4
+
+#define LL_SLEEP_IND	0x30
+#define LL_SLEEP_ACK	0x31
+#define LL_WAKE_UP_IND	0x32
+#define LL_WAKE_UP_ACK	0x33
+
+/* ST LL private information */
+struct ll_struct_s {
+	unsigned long ll_state;	/* ST LL power state */
+};
+
+/* initialize and de-init ST LL */
+long st_ll_init(void);
+long st_ll_deinit(void);
+
+/* enable/disable ST LL along with KIM start/stop
+ * called by ST Core
+ */
+void st_ll_enable(void);
+void st_ll_disable(void);
+
+unsigned long st_ll_getstate(void);
+unsigned long st_ll_sleep_state(unsigned char);
+void st_ll_wakeup(void);
+#endif /* ST_LL_H */
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 3168ebd616b2..2966a3cf84ac 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1335,6 +1335,19 @@ EXPORT_SYMBOL(mmc_resume_host);
 
 #endif
 
+#ifdef CONFIG_TIWLAN_SDIO
+void mmc_set_embedded_sdio_data(struct mmc_host *host,
+				struct sdio_cis *cis,
+				struct sdio_embedded_func *funcs,
+				unsigned int quirks)
+{
+       host->embedded_sdio_data.cis = cis;
+       host->embedded_sdio_data.funcs = funcs;
+	host->embedded_sdio_data.quirks = quirks;
+}
+EXPORT_SYMBOL(mmc_set_embedded_sdio_data);
+#endif
+
 static int __init mmc_init(void)
 {
 	int ret;
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index 2dd4cfe7ca17..d33f7d4348c5 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -24,6 +24,10 @@
 #include "sdio_ops.h"
 #include "sdio_cis.h"
 
+#ifdef CONFIG_TIWLAN_SDIO
+#include <linux/mmc/sdio_ids.h>
+#endif
+
 static int sdio_read_fbr(struct sdio_func *func)
 {
 	int ret;
@@ -293,6 +297,9 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr,
 		goto err;
 	}
 
+#ifdef CONFIG_TIWLAN_SDIO
+	card->quirks = host->embedded_sdio_data.quirks;
+#endif
 	card->type = MMC_TYPE_SDIO;
 
 	/*
@@ -322,6 +329,12 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr,
 	if (err)
 		goto remove;
 
+#ifdef CONFIG_TIWLAN_SDIO
+	if (host->embedded_sdio_data.cis)
+		memcpy(&card->cis, host->embedded_sdio_data.cis,
+		sizeof(struct sdio_cis));
+	else {
+#endif
 	/*
 	 * Read the common CIS tuples.
 	 */
@@ -329,6 +342,10 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr,
 	if (err)
 		goto remove;
 
+#ifdef CONFIG_TIWLAN_SDIO
+       }
+#endif
+
 	if (oldcard) {
 		int same = (card->cis.vendor == oldcard->cis.vendor &&
 			    card->cis.device == oldcard->cis.device);
@@ -578,9 +595,29 @@ int mmc_attach_sdio(struct mmc_host *host, u32 ocr)
 	 * Initialize (but don't add) all present functions.
 	 */
 	for (i = 0; i < funcs; i++, card->sdio_funcs++) {
+#ifdef CONFIG_TIWLAN_SDIO
+		if (host->embedded_sdio_data.funcs) {
+			struct sdio_func *tmp;
+
+			tmp = sdio_alloc_func(host->card);
+			if (IS_ERR(tmp))
+				goto remove;
+			tmp->num = (i + 1);
+			card->sdio_func[i] = tmp;
+			tmp->class = host->embedded_sdio_data.funcs[i].f_class;
+			tmp->max_blksize =
+				host->embedded_sdio_data.funcs[i].f_maxblksize;
+			tmp->vendor = card->cis.vendor;
+			tmp->device = card->cis.device;
+		} else {
+#endif
+
 		err = sdio_init_func(host->card, i + 1);
 		if (err)
 			goto remove;
+#ifdef CONFIG_TIWLAN_SDIO
+	}
+#endif
 	}
 
 	mmc_release_host(host);
diff --git a/drivers/mmc/core/sdio_bus.c b/drivers/mmc/core/sdio_bus.c
index 4a890dcb95ab..af5c1d81258b 100644
--- a/drivers/mmc/core/sdio_bus.c
+++ b/drivers/mmc/core/sdio_bus.c
@@ -21,6 +21,10 @@
 #include "sdio_cis.h"
 #include "sdio_bus.h"
 
+#ifdef CONFIG_TIWLAN_SDIO
+#include <linux/mmc/host.h>
+#endif
+
 /* show configuration fields */
 #define sdio_config_attr(field, format_string)				\
 static ssize_t								\
@@ -200,6 +204,13 @@ static void sdio_release_func(struct device *dev)
 {
 	struct sdio_func *func = dev_to_sdio_func(dev);
 
+#ifdef CONFIG_TIWLAN_SDIO
+    /*
+     * If this device is embedded then we never allocated
+     * cis tables for this func
+     */
+    if (!func->card->host->embedded_sdio_data.funcs)
+#endif
 	sdio_free_func_cis(func);
 
 	if (func->info)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 3abeca657b0e..c0ca3e5951a0 100755..100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1096,6 +1096,9 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 			__func__);
 }
 
+/*
+ * MMC controller IRQ handler
+ */
 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 {
 	struct mmc_data *data;
@@ -1782,6 +1785,30 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		mmc_host_lazy_disable(host->mmc);
 }
 
+#ifdef CONFIG_TIWLAN_SDIO
+static void omap_hsmmc_status_notify_cb(int card_present, void *dev_id)
+{
+       struct omap_hsmmc_host *host = dev_id;
+       struct omap_mmc_slot_data *slot = &mmc_slot(host);
+       int carddetect;
+
+       printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
+                card_present);
+
+       carddetect = slot->card_detect(host->dev, host->slot_id);
+
+       sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
+        if (carddetect) {
+                mmc_detect_change(host->mmc, (HZ * 200) / 1000);
+        } else {
+                mmc_host_enable(host->mmc);
+                omap_hsmmc_reset_controller_fsm(host, SRD);
+                mmc_host_lazy_disable(host->mmc);
+                mmc_detect_change(host->mmc, (HZ * 50) / 1000);
+        }
+}
+#endif
+
 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 {
 	struct omap_hsmmc_host *host = mmc_priv(mmc);
@@ -2215,6 +2242,17 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
 		host->regs	= (u16 *) omap3_mmc_reg_map;
 	host->power_mode = MMC_POWER_OFF;
 
+#ifdef CONFIG_TIWLAN_SDIO
+        if (pdev->id == CONFIG_TIWLAN_MMC_CONTROLLER-1) {
+                if (pdata->slots[0].embedded_sdio != NULL) {
+                        mmc_set_embedded_sdio_data(mmc,
+                        &pdata->slots[0].embedded_sdio->cis,
+                        pdata->slots[0].embedded_sdio->funcs,
+			pdata->slots[0].embedded_sdio->quirks);
+                }
+        }
+#endif
+
 	platform_set_drvdata(pdev, host);
 	INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
 
@@ -2378,6 +2416,15 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
 		pdata->resume = omap_hsmmc_resume_cdirq;
 	}
 
+#ifdef CONFIG_TIWLAN_SDIO
+        else if (mmc_slot(host).register_status_notify) {
+                if (pdev->id == CONFIG_TIWLAN_MMC_CONTROLLER-1) {
+                        mmc_slot(host).register_status_notify(
+                                omap_hsmmc_status_notify_cb, host);
+                }
+        }
+#endif
+
 	omap_hsmmc_disable_irq(host);
 
 	mmc_host_lazy_disable(host->mmc);
diff --git a/drivers/staging/iio/magnetometer/hmc5843.c b/drivers/staging/iio/magnetometer/hmc5843.c
index 3ad5895de4f4..3ad5895de4f4 100755..100644
--- a/drivers/staging/iio/magnetometer/hmc5843.c
+++ b/drivers/staging/iio/magnetometer/hmc5843.c
diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
index d877c361abda..18bb8359c72a 100644
--- a/drivers/video/omap2/Kconfig
+++ b/drivers/video/omap2/Kconfig
@@ -3,6 +3,10 @@ config OMAP2_VRAM
 
 config OMAP2_VRFB
 	bool
+	depends on ARCH_OMAP2 || ARCH_OMAP3
+	default y if FB_OMAP2
+	help
+	  OMAP VRFB buffer support is efficient for rotation
 
 source "drivers/video/omap2/dss/Kconfig"
 source "drivers/video/omap2/omapfb/Kconfig"
diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
index dfb57ee50861..45b92f666506 100644
--- a/drivers/video/omap2/displays/Kconfig
+++ b/drivers/video/omap2/displays/Kconfig
@@ -17,8 +17,15 @@ config PANEL_SHARP_LQ043T1DG01
         tristate "Sharp LQ043T1DG01 LCD Panel"
         depends on OMAP2_DSS
         help
+
           LCD Panel used in TI's OMAP3517 EVM boards
 
+config PANEL_PICO_DLP
+        tristate "OMAP PICO DLP Panel"
+        depends on OMAP2_DSS
+        help
+          LCD Panel used in TI's SDP4430 and EVM boards
+
 config PANEL_TAAL
         tristate "Taal DSI Panel"
         depends on OMAP2_DSS_DSI
@@ -33,8 +40,14 @@ config PANEL_TOPPOLY_TDO35S
 
 config PANEL_TPO_TD043MTEA1
         tristate "TPO TD043MTEA1 LCD Panel"
-        depends on OMAP2_DSS && I2C
+        depends on OMAP2_DSS && SPI
         help
           LCD Panel used in OMAP3 Pandora
 
+config PANEL_ACX565AKM
+	tristate "ACX565AKM Panel"
+	depends on OMAP2_DSS_SDI
+	select BACKLIGHT_CLASS_DEVICE
+	help
+	  This is the LCD panel used on Nokia N900
 endmenu
diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile
index e2bb32168dee..eb7945dca099 100644
--- a/drivers/video/omap2/displays/Makefile
+++ b/drivers/video/omap2/displays/Makefile
@@ -3,5 +3,7 @@ obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o
 obj-$(CONFIG_PANEL_SHARP_LQ043T1DG01) += panel-sharp-lq043t1dg01.o
 
 obj-$(CONFIG_PANEL_TAAL) += panel-taal.o
+obj-$(CONFIG_PANEL_PICO_DLP) +=  panel-picodlp.o
 obj-$(CONFIG_PANEL_TOPPOLY_TDO35S) += panel-toppoly-tdo35s.o
 obj-$(CONFIG_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o
+obj-$(CONFIG_PANEL_ACX565AKM) += panel-acx565akm.o
diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c
new file mode 100644
index 000000000000..1f8eb70e2937
--- /dev/null
+++ b/drivers/video/omap2/displays/panel-acx565akm.c
@@ -0,0 +1,819 @@
+/*
+ * Support for ACX565AKM LCD Panel used on Nokia N900
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Original Driver Author: Imre Deak <imre.deak@nokia.com>
+ * Based on panel-generic.c by Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ * Adapted to new DSS2 framework: Roger Quadros <roger.quadros@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/spi/spi.h>
+#include <linux/jiffies.h>
+#include <linux/sched.h>
+#include <linux/backlight.h>
+#include <linux/fb.h>
+
+#include <plat/display.h>
+
+#define MIPID_CMD_READ_DISP_ID		0x04
+#define MIPID_CMD_READ_RED		0x06
+#define MIPID_CMD_READ_GREEN		0x07
+#define MIPID_CMD_READ_BLUE		0x08
+#define MIPID_CMD_READ_DISP_STATUS	0x09
+#define MIPID_CMD_RDDSDR		0x0F
+#define MIPID_CMD_SLEEP_IN		0x10
+#define MIPID_CMD_SLEEP_OUT		0x11
+#define MIPID_CMD_DISP_OFF		0x28
+#define MIPID_CMD_DISP_ON		0x29
+#define MIPID_CMD_WRITE_DISP_BRIGHTNESS	0x51
+#define MIPID_CMD_READ_DISP_BRIGHTNESS	0x52
+#define MIPID_CMD_WRITE_CTRL_DISP	0x53
+
+#define CTRL_DISP_BRIGHTNESS_CTRL_ON	(1 << 5)
+#define CTRL_DISP_AMBIENT_LIGHT_CTRL_ON	(1 << 4)
+#define CTRL_DISP_BACKLIGHT_ON		(1 << 2)
+#define CTRL_DISP_AUTO_BRIGHTNESS_ON	(1 << 1)
+
+#define MIPID_CMD_READ_CTRL_DISP	0x54
+#define MIPID_CMD_WRITE_CABC		0x55
+#define MIPID_CMD_READ_CABC		0x56
+
+#define MIPID_VER_LPH8923		3
+#define MIPID_VER_LS041Y3		4
+#define MIPID_VER_L4F00311		8
+#define MIPID_VER_ACX565AKM		9
+
+struct acx565akm_device {
+	char		*name;
+	int		enabled;
+	int		model;
+	int		revision;
+	u8		display_id[3];
+	unsigned	has_bc:1;
+	unsigned	has_cabc:1;
+	unsigned	cabc_mode;
+	unsigned long	hw_guard_end;		/* next value of jiffies
+						   when we can issue the
+						   next sleep in/out command */
+	unsigned long	hw_guard_wait;		/* max guard time in jiffies */
+
+	struct spi_device	*spi;
+	struct mutex		mutex;
+
+	struct omap_dss_device	*dssdev;
+	struct backlight_device *bl_dev;
+};
+
+static struct acx565akm_device acx_dev;
+static int acx565akm_bl_update_status(struct backlight_device *dev);
+
+/*--------------------MIPID interface-----------------------------*/
+
+static void acx565akm_transfer(struct acx565akm_device *md, int cmd,
+			      const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
+{
+	struct spi_message	m;
+	struct spi_transfer	*x, xfer[5];
+	int			r;
+
+	BUG_ON(md->spi == NULL);
+
+	spi_message_init(&m);
+
+	memset(xfer, 0, sizeof(xfer));
+	x = &xfer[0];
+
+	cmd &=  0xff;
+	x->tx_buf = &cmd;
+	x->bits_per_word = 9;
+	x->len = 2;
+
+	if (rlen > 1 && wlen == 0) {
+		/*
+		 * Between the command and the response data there is a
+		 * dummy clock cycle. Add an extra bit after the command
+		 * word to account for this.
+		 */
+		x->bits_per_word = 10;
+		cmd <<= 1;
+	}
+	spi_message_add_tail(x, &m);
+
+	if (wlen) {
+		x++;
+		x->tx_buf = wbuf;
+		x->len = wlen;
+		x->bits_per_word = 9;
+		spi_message_add_tail(x, &m);
+	}
+
+	if (rlen) {
+		x++;
+		x->rx_buf	= rbuf;
+		x->len		= rlen;
+		spi_message_add_tail(x, &m);
+	}
+
+	r = spi_sync(md->spi, &m);
+	if (r < 0)
+		dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
+}
+
+static inline void acx565akm_cmd(struct acx565akm_device *md, int cmd)
+{
+	acx565akm_transfer(md, cmd, NULL, 0, NULL, 0);
+}
+
+static inline void acx565akm_write(struct acx565akm_device *md,
+			       int reg, const u8 *buf, int len)
+{
+	acx565akm_transfer(md, reg, buf, len, NULL, 0);
+}
+
+static inline void acx565akm_read(struct acx565akm_device *md,
+			      int reg, u8 *buf, int len)
+{
+	acx565akm_transfer(md, reg, NULL, 0, buf, len);
+}
+
+static void hw_guard_start(struct acx565akm_device *md, int guard_msec)
+{
+	md->hw_guard_wait = msecs_to_jiffies(guard_msec);
+	md->hw_guard_end = jiffies + md->hw_guard_wait;
+}
+
+static void hw_guard_wait(struct acx565akm_device *md)
+{
+	unsigned long wait = md->hw_guard_end - jiffies;
+
+	if ((long)wait > 0 && wait <= md->hw_guard_wait) {
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		schedule_timeout(wait);
+	}
+}
+
+/*----------------------MIPID wrappers----------------------------*/
+
+static void set_sleep_mode(struct acx565akm_device *md, int on)
+{
+	int cmd;
+
+	if (on)
+		cmd = MIPID_CMD_SLEEP_IN;
+	else
+		cmd = MIPID_CMD_SLEEP_OUT;
+	/*
+	 * We have to keep 120msec between sleep in/out commands.
+	 * (8.2.15, 8.2.16).
+	 */
+	hw_guard_wait(md);
+	acx565akm_cmd(md, cmd);
+	hw_guard_start(md, 120);
+}
+
+static void set_display_state(struct acx565akm_device *md, int enabled)
+{
+	int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
+
+	acx565akm_cmd(md, cmd);
+}
+
+static int panel_enabled(struct acx565akm_device *md)
+{
+	u32 disp_status;
+	int enabled;
+
+	acx565akm_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
+	disp_status = __be32_to_cpu(disp_status);
+	enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
+	dev_dbg(&md->spi->dev,
+		"LCD panel %senabled by bootloader (status 0x%04x)\n",
+		enabled ? "" : "not ", disp_status);
+	return enabled;
+}
+
+static int panel_detect(struct acx565akm_device *md)
+{
+	acx565akm_read(md, MIPID_CMD_READ_DISP_ID, md->display_id, 3);
+	dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
+		md->display_id[0], md->display_id[1], md->display_id[2]);
+
+	switch (md->display_id[0]) {
+	case 0x10:
+		md->model = MIPID_VER_ACX565AKM;
+		md->name = "acx565akm";
+		md->has_bc = 1;
+		md->has_cabc = 1;
+		break;
+	case 0x29:
+		md->model = MIPID_VER_L4F00311;
+		md->name = "l4f00311";
+		break;
+	case 0x45:
+		md->model = MIPID_VER_LPH8923;
+		md->name = "lph8923";
+		break;
+	case 0x83:
+		md->model = MIPID_VER_LS041Y3;
+		md->name = "ls041y3";
+		break;
+	default:
+		md->name = "unknown";
+		dev_err(&md->spi->dev, "invalid display ID\n");
+		return -ENODEV;
+	}
+
+	md->revision = md->display_id[1];
+
+	dev_info(&md->spi->dev, "omapfb: %s rev %02x LCD detected\n",
+			md->name, md->revision);
+
+	return 0;
+}
+
+/*----------------------Backlight Control-------------------------*/
+
+static void enable_backlight_ctrl(struct acx565akm_device *md, int enable)
+{
+	u16 ctrl;
+
+	acx565akm_read(md, MIPID_CMD_READ_CTRL_DISP, (u8 *)&ctrl, 1);
+	if (enable) {
+		ctrl |= CTRL_DISP_BRIGHTNESS_CTRL_ON |
+			CTRL_DISP_BACKLIGHT_ON;
+	} else {
+		ctrl &= ~(CTRL_DISP_BRIGHTNESS_CTRL_ON |
+			  CTRL_DISP_BACKLIGHT_ON);
+	}
+
+	ctrl |= 1 << 8;
+	acx565akm_write(md, MIPID_CMD_WRITE_CTRL_DISP, (u8 *)&ctrl, 2);
+}
+
+static void set_cabc_mode(struct acx565akm_device *md, unsigned mode)
+{
+	u16 cabc_ctrl;
+
+	md->cabc_mode = mode;
+	if (!md->enabled)
+		return;
+	cabc_ctrl = 0;
+	acx565akm_read(md, MIPID_CMD_READ_CABC, (u8 *)&cabc_ctrl, 1);
+	cabc_ctrl &= ~3;
+	cabc_ctrl |= (1 << 8) | (mode & 3);
+	acx565akm_write(md, MIPID_CMD_WRITE_CABC, (u8 *)&cabc_ctrl, 2);
+}
+
+static unsigned get_cabc_mode(struct acx565akm_device *md)
+{
+	return md->cabc_mode;
+}
+
+static unsigned get_hw_cabc_mode(struct acx565akm_device *md)
+{
+	u8 cabc_ctrl;
+
+	acx565akm_read(md, MIPID_CMD_READ_CABC, &cabc_ctrl, 1);
+	return cabc_ctrl & 3;
+}
+
+static void acx565akm_set_brightness(struct acx565akm_device *md, int level)
+{
+	int bv;
+
+	bv = level | (1 << 8);
+	acx565akm_write(md, MIPID_CMD_WRITE_DISP_BRIGHTNESS, (u8 *)&bv, 2);
+
+	if (level)
+		enable_backlight_ctrl(md, 1);
+	else
+		enable_backlight_ctrl(md, 0);
+}
+
+static int acx565akm_get_actual_brightness(struct acx565akm_device *md)
+{
+	u8 bv;
+
+	acx565akm_read(md, MIPID_CMD_READ_DISP_BRIGHTNESS, &bv, 1);
+
+	return bv;
+}
+
+
+static int acx565akm_bl_update_status(struct backlight_device *dev)
+{
+	struct acx565akm_device *md = dev_get_drvdata(&dev->dev);
+	int r;
+	int level;
+
+	dev_dbg(&md->spi->dev, "%s\n", __func__);
+
+	mutex_lock(&md->mutex);
+
+	if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
+			dev->props.power == FB_BLANK_UNBLANK)
+		level = dev->props.brightness;
+	else
+		level = 0;
+
+	r = 0;
+	if (md->has_bc)
+		acx565akm_set_brightness(md, level);
+	else if (md->dssdev->set_backlight)
+		r = md->dssdev->set_backlight(md->dssdev, level);
+	else
+		r = -ENODEV;
+
+	mutex_unlock(&md->mutex);
+
+	return r;
+}
+
+static int acx565akm_bl_get_intensity(struct backlight_device *dev)
+{
+	struct acx565akm_device *md = dev_get_drvdata(&dev->dev);
+
+	dev_dbg(&dev->dev, "%s\n", __func__);
+
+	if (!md->has_bc && md->dssdev->set_backlight == NULL)
+		return -ENODEV;
+
+	if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
+			dev->props.power == FB_BLANK_UNBLANK) {
+		if (md->has_bc)
+			return acx565akm_get_actual_brightness(md);
+		else
+			return dev->props.brightness;
+	}
+
+	return 0;
+}
+
+static const struct backlight_ops acx565akm_bl_ops = {
+	.get_brightness = acx565akm_bl_get_intensity,
+	.update_status  = acx565akm_bl_update_status,
+};
+
+/*--------------------Auto Brightness control via Sysfs---------------------*/
+
+static const char *cabc_modes[] = {
+	"off",		/* always used when CABC is not supported */
+	"ui",
+	"still-image",
+	"moving-image",
+};
+
+static ssize_t show_cabc_mode(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	struct acx565akm_device *md = dev_get_drvdata(dev);
+	const char *mode_str;
+	int mode;
+	int len;
+
+	if (!md->has_cabc)
+		mode = 0;
+	else
+		mode = get_cabc_mode(md);
+	mode_str = "unknown";
+	if (mode >= 0 && mode < ARRAY_SIZE(cabc_modes))
+		mode_str = cabc_modes[mode];
+	len = snprintf(buf, PAGE_SIZE, "%s\n", mode_str);
+
+	return len < PAGE_SIZE - 1 ? len : PAGE_SIZE - 1;
+}
+
+static ssize_t store_cabc_mode(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	struct acx565akm_device *md = dev_get_drvdata(dev);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) {
+		const char *mode_str = cabc_modes[i];
+		int cmp_len = strlen(mode_str);
+
+		if (count > 0 && buf[count - 1] == '\n')
+			count--;
+		if (count != cmp_len)
+			continue;
+
+		if (strncmp(buf, mode_str, cmp_len) == 0)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(cabc_modes))
+		return -EINVAL;
+
+	if (!md->has_cabc && i != 0)
+		return -EINVAL;
+
+	mutex_lock(&md->mutex);
+	set_cabc_mode(md, i);
+	mutex_unlock(&md->mutex);
+
+	return count;
+}
+
+static ssize_t show_cabc_available_modes(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	struct acx565akm_device *md = dev_get_drvdata(dev);
+	int len;
+	int i;
+
+	if (!md->has_cabc)
+		return snprintf(buf, PAGE_SIZE, "%s\n", cabc_modes[0]);
+
+	for (i = 0, len = 0;
+	     len < PAGE_SIZE && i < ARRAY_SIZE(cabc_modes); i++)
+		len += snprintf(&buf[len], PAGE_SIZE - len, "%s%s%s",
+			i ? " " : "", cabc_modes[i],
+			i == ARRAY_SIZE(cabc_modes) - 1 ? "\n" : "");
+
+	return len < PAGE_SIZE ? len : PAGE_SIZE - 1;
+}
+
+static DEVICE_ATTR(cabc_mode, S_IRUGO | S_IWUSR,
+		show_cabc_mode, store_cabc_mode);
+static DEVICE_ATTR(cabc_available_modes, S_IRUGO,
+		show_cabc_available_modes, NULL);
+
+static struct attribute *bldev_attrs[] = {
+	&dev_attr_cabc_mode.attr,
+	&dev_attr_cabc_available_modes.attr,
+	NULL,
+};
+
+static struct attribute_group bldev_attr_group = {
+	.attrs = bldev_attrs,
+};
+
+
+/*---------------------------ACX Panel----------------------------*/
+
+static int acx_get_recommended_bpp(struct omap_dss_device *dssdev)
+{
+	return 16;
+}
+
+static struct omap_video_timings acx_panel_timings = {
+	.x_res		= 800,
+	.y_res		= 480,
+	.pixel_clock	= 24000,
+	.hfp		= 28,
+	.hsw		= 4,
+	.hbp		= 24,
+	.vfp		= 3,
+	.vsw		= 3,
+	.vbp		= 4,
+};
+
+static int acx_panel_probe(struct omap_dss_device *dssdev)
+{
+	int r;
+	struct acx565akm_device *md = &acx_dev;
+	struct backlight_device *bldev;
+	int max_brightness, brightness;
+	struct backlight_properties props;
+
+	dev_dbg(&dssdev->dev, "%s\n", __func__);
+	dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+					OMAP_DSS_LCD_IHS;
+	/* FIXME AC bias ? */
+	dssdev->panel.timings = acx_panel_timings;
+
+	if (dssdev->platform_enable)
+		dssdev->platform_enable(dssdev);
+	/*
+	 * After reset we have to wait 5 msec before the first
+	 * command can be sent.
+	 */
+	msleep(5);
+
+	md->enabled = panel_enabled(md);
+
+	r = panel_detect(md);
+	if (r) {
+		dev_err(&dssdev->dev, "%s panel detect error\n", __func__);
+		if (!md->enabled && dssdev->platform_disable)
+			dssdev->platform_disable(dssdev);
+		return r;
+	}
+
+	mutex_lock(&acx_dev.mutex);
+	acx_dev.dssdev = dssdev;
+	mutex_unlock(&acx_dev.mutex);
+
+	if (!md->enabled) {
+		if (dssdev->platform_disable)
+			dssdev->platform_disable(dssdev);
+	}
+
+	/*------- Backlight control --------*/
+
+	props.fb_blank = FB_BLANK_UNBLANK;
+	props.power = FB_BLANK_UNBLANK;
+
+	bldev = backlight_device_register("acx565akm", &md->spi->dev,
+			md, &acx565akm_bl_ops, &props);
+	md->bl_dev = bldev;
+	if (md->has_cabc) {
+		r = sysfs_create_group(&bldev->dev.kobj, &bldev_attr_group);
+		if (r) {
+			dev_err(&bldev->dev,
+				"%s failed to create sysfs files\n", __func__);
+			backlight_device_unregister(bldev);
+			return r;
+		}
+		md->cabc_mode = get_hw_cabc_mode(md);
+	}
+
+	if (md->has_bc)
+		max_brightness = 255;
+	else
+		max_brightness = dssdev->max_backlight_level;
+
+	if (md->has_bc)
+		brightness = acx565akm_get_actual_brightness(md);
+	else if (dssdev->get_backlight)
+		brightness = dssdev->get_backlight(dssdev);
+	else
+		brightness = 0;
+
+	bldev->props.max_brightness = max_brightness;
+	bldev->props.brightness = brightness;
+
+	acx565akm_bl_update_status(bldev);
+	return 0;
+}
+
+static void acx_panel_remove(struct omap_dss_device *dssdev)
+{
+	struct acx565akm_device *md = &acx_dev;
+
+	dev_dbg(&dssdev->dev, "%s\n", __func__);
+	sysfs_remove_group(&md->bl_dev->dev.kobj, &bldev_attr_group);
+	backlight_device_unregister(md->bl_dev);
+	mutex_lock(&acx_dev.mutex);
+	acx_dev.dssdev = NULL;
+	mutex_unlock(&acx_dev.mutex);
+}
+
+static int acx_panel_power_on(struct omap_dss_device *dssdev)
+{
+	struct acx565akm_device *md = &acx_dev;
+	int r;
+
+	dev_dbg(&dssdev->dev, "%s\n", __func__);
+
+	mutex_lock(&md->mutex);
+
+	r = omapdss_sdi_display_enable(dssdev);
+	if (r) {
+		pr_err("%s sdi enable failed\n", __func__);
+		return r;
+	}
+
+	/*FIXME tweak me */
+	msleep(50);
+
+	if (dssdev->platform_enable) {
+		r = dssdev->platform_enable(dssdev);
+		if (r)
+			goto fail;
+	}
+
+	if (md->enabled) {
+		dev_dbg(&md->spi->dev, "panel already enabled\n");
+		mutex_unlock(&md->mutex);
+		return 0;
+	}
+
+	/*
+	 * We have to meet all the following delay requirements:
+	 * 1. tRW: reset pulse width 10usec (7.12.1)
+	 * 2. tRT: reset cancel time 5msec (7.12.1)
+	 * 3. Providing PCLK,HS,VS signals for 2 frames = ~50msec worst
+	 *    case (7.6.2)
+	 * 4. 120msec before the sleep out command (7.12.1)
+	 */
+	msleep(120);
+
+	set_sleep_mode(md, 0);
+	md->enabled = 1;
+
+	/* 5msec between sleep out and the next command. (8.2.16) */
+	msleep(5);
+	set_display_state(md, 1);
+	set_cabc_mode(md, md->cabc_mode);
+
+	mutex_unlock(&md->mutex);
+
+	return acx565akm_bl_update_status(md->bl_dev);
+fail:
+	omapdss_sdi_display_disable(dssdev);
+	return r;
+}
+
+static void acx_panel_power_off(struct omap_dss_device *dssdev)
+{
+	struct acx565akm_device *md = &acx_dev;
+
+	dev_dbg(&dssdev->dev, "%s\n", __func__);
+
+	mutex_lock(&md->mutex);
+
+	if (!md->enabled) {
+		mutex_unlock(&md->mutex);
+		return;
+	}
+	set_display_state(md, 0);
+	set_sleep_mode(md, 1);
+	md->enabled = 0;
+	/*
+	 * We have to provide PCLK,HS,VS signals for 2 frames (worst case
+	 * ~50msec) after sending the sleep in command and asserting the
+	 * reset signal. We probably could assert the reset w/o the delay
+	 * but we still delay to avoid possible artifacts. (7.6.1)
+	 */
+	msleep(50);
+
+	if (dssdev->platform_disable)
+		dssdev->platform_disable(dssdev);
+
+	/* FIXME need to tweak this delay */
+	msleep(100);
+
+	omapdss_sdi_display_disable(dssdev);
+
+	mutex_unlock(&md->mutex);
+}
+
+static int acx_panel_enable(struct omap_dss_device *dssdev)
+{
+	int r;
+
+	dev_dbg(&dssdev->dev, "%s\n", __func__);
+	r = acx_panel_power_on(dssdev);
+
+	if (r)
+		return r;
+
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+	return 0;
+}
+
+static void acx_panel_disable(struct omap_dss_device *dssdev)
+{
+	dev_dbg(&dssdev->dev, "%s\n", __func__);
+	acx_panel_power_off(dssdev);
+	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+}
+
+static int acx_panel_suspend(struct omap_dss_device *dssdev)
+{
+	dev_dbg(&dssdev->dev, "%s\n", __func__);
+	acx_panel_power_off(dssdev);
+	dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
+	return 0;
+}
+
+static int acx_panel_resume(struct omap_dss_device *dssdev)
+{
+	int r;
+
+	dev_dbg(&dssdev->dev, "%s\n", __func__);
+	r = acx_panel_power_on(dssdev);
+	if (r)
+		return r;
+
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+	return 0;
+}
+
+static void acx_panel_set_timings(struct omap_dss_device *dssdev,
+		struct omap_video_timings *timings)
+{
+	int r;
+
+	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
+		omapdss_sdi_display_disable(dssdev);
+
+	dssdev->panel.timings = *timings;
+
+	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
+		r = omapdss_sdi_display_enable(dssdev);
+		if (r)
+			dev_err(&dssdev->dev, "%s enable failed\n", __func__);
+	}
+}
+
+static void acx_panel_get_timings(struct omap_dss_device *dssdev,
+		struct omap_video_timings *timings)
+{
+	*timings = dssdev->panel.timings;
+}
+
+static int acx_panel_check_timings(struct omap_dss_device *dssdev,
+		struct omap_video_timings *timings)
+{
+	return 0;
+}
+
+
+static struct omap_dss_driver acx_panel_driver = {
+	.probe		= acx_panel_probe,
+	.remove		= acx_panel_remove,
+
+	.enable		= acx_panel_enable,
+	.disable	= acx_panel_disable,
+	.suspend	= acx_panel_suspend,
+	.resume		= acx_panel_resume,
+
+	.set_timings	= acx_panel_set_timings,
+	.get_timings	= acx_panel_get_timings,
+	.check_timings	= acx_panel_check_timings,
+
+	.get_recommended_bpp = acx_get_recommended_bpp,
+
+	.driver         = {
+		.name   = "panel-acx565akm",
+		.owner  = THIS_MODULE,
+	},
+};
+
+/*--------------------SPI probe-------------------------*/
+
+static int acx565akm_spi_probe(struct spi_device *spi)
+{
+	struct acx565akm_device *md = &acx_dev;
+
+	dev_dbg(&spi->dev, "%s\n", __func__);
+
+	spi->mode = SPI_MODE_3;
+	md->spi = spi;
+	mutex_init(&md->mutex);
+	dev_set_drvdata(&spi->dev, md);
+
+	omap_dss_register_driver(&acx_panel_driver);
+
+	return 0;
+}
+
+static int acx565akm_spi_remove(struct spi_device *spi)
+{
+	struct acx565akm_device *md = dev_get_drvdata(&spi->dev);
+
+	dev_dbg(&md->spi->dev, "%s\n", __func__);
+	omap_dss_unregister_driver(&acx_panel_driver);
+
+	return 0;
+}
+
+static struct spi_driver acx565akm_spi_driver = {
+	.driver = {
+		.name	= "acx565akm",
+		.bus	= &spi_bus_type,
+		.owner	= THIS_MODULE,
+	},
+	.probe	= acx565akm_spi_probe,
+	.remove	= __devexit_p(acx565akm_spi_remove),
+};
+
+static int __init acx565akm_init(void)
+{
+	return spi_register_driver(&acx565akm_spi_driver);
+}
+
+static void __exit acx565akm_exit(void)
+{
+	spi_unregister_driver(&acx565akm_spi_driver);
+}
+
+module_init(acx565akm_init);
+module_exit(acx565akm_exit);
+
+MODULE_AUTHOR("Nokia Corporation");
+MODULE_DESCRIPTION("acx565akm LCD Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/omap2/displays/panel-picodlp.c b/drivers/video/omap2/displays/panel-picodlp.c
new file mode 100644
index 000000000000..76b01e2a73c9
--- /dev/null
+++ b/drivers/video/omap2/displays/panel-picodlp.c
@@ -0,0 +1,584 @@
+/*
+ * pico_i2c_driver.c
+ * pico DLP driver
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Author: mythripk <mythripk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/input.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <plat/display.h>
+#include<../drivers/video/omap2/dss/dss.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/firmware.h>
+#include "panel-picodlp.h"
+#include <linux/slab.h>
+
+
+#define DRIVER_NAME       "pico_i2c"
+/* How much data we can put into single write block */
+#define MAX_I2C_WRITE_BLOCK_SIZE 32
+#define PICO_MAJOR     1 /* 2 bits */
+#define PICO_MINOR     1 /* 2 bits */
+#define DSI_DIV2            (0x40C)
+#define DSI_DIV_LCD          (16)
+#define DSI_DIV_PCD          (0)
+#define DSI_CONTROL2         (0x238)
+
+static  int display_control_reg   = (0x58000000 + 0x1000);
+void __iomem  *dispc_base;
+
+static struct omap_video_timings pico_ls_timings = {
+	.x_res	        = 864,
+	.y_res	        = 480,
+	.hsw		= 7,
+	.hfp		= 11,
+	.hbp		= 7,
+
+	.vsw		= 2,
+	.vfp		= 3,
+	.vbp		= 14,
+};
+
+struct pico {
+	struct i2c_client    *client;
+	struct mutex xfer_lock;
+	} *sd;
+
+
+static int dlp_read_block(int reg, u8 *data, int len);
+static int pico_i2c_write(int reg, u32 value);
+
+static int dlp_write_block(int reg, const u8 *data, int len)
+{
+	unsigned char wb[MAX_I2C_WRITE_BLOCK_SIZE + 1];
+	struct i2c_msg msg;
+	int r;
+	int i;
+
+	if (len < 1 ||
+	    len > MAX_I2C_WRITE_BLOCK_SIZE) {
+		dev_info(&sd->client->dev, "too long syn_write_block len %d\n",
+			 len);
+		return -EIO;
+	}
+
+	wb[0] = reg & 0xff;
+
+	for (i = 0; i < len; i++)
+		wb[i + 1] = data[i];
+
+	mutex_lock(&sd->xfer_lock);
+
+	msg.addr = sd->client->addr;
+	msg.flags = 0;
+	msg.len = len + 1;
+	msg.buf = wb;
+
+	r = i2c_transfer(sd->client->adapter, &msg, 1);
+	mutex_unlock(&sd->xfer_lock);
+
+		if (r == 1) {
+			for (i = 0; i < len; i++)
+				dev_info(&sd->client->dev,
+					 "addr %x bw 0x%02x[%d]: 0x%02x\n",
+					 sd->client->addr, reg + i, i, data[i]);
+		}
+
+
+	if (r == 1)
+		return 0;
+
+	return r;
+}
+
+static int pico_i2c_write(int reg, u32 value)
+{
+	u8 data[4];
+
+	data[0] = (value & 0xFF000000) >> 24;
+	data[1] = (value & 0x00FF0000) >> 16;
+	data[2] = (value & 0x0000FF00) >> 8;
+	data[3] = (value & 0x000000FF);
+
+	return dlp_write_block(reg, data, 4);
+}
+
+static int dlp_read_block(int reg, u8 *data, int len)
+{
+	unsigned char wb[2];
+	struct i2c_msg msg[2];
+	int r;
+	mutex_lock(&sd->xfer_lock);
+	wb[0] = 0x15 & 0xff;
+	wb[1] = reg & 0xff;
+	msg[0].addr = sd->client->addr;
+	msg[0].len = 2;
+	msg[0].flags = 0;
+	msg[0].buf = wb;
+	msg[1].addr = sd->client->addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = len;
+	msg[1].buf = data;
+
+	r = i2c_transfer(sd->client->adapter, msg, 2);
+	mutex_unlock(&sd->xfer_lock);
+
+
+		if (r == 2) {
+			int i;
+
+			for (i = 0; i < len; i++)
+				dev_info(&sd->client->dev,
+					 "addr %x br 0x%02x[%d]: 0x%02x\n",
+					sd->client->addr, reg + i, i, data[i]);
+		}
+
+
+	if (r == 2)
+		return len;
+
+	return r;
+}
+
+
+static __attribute__ ((unused)) int pico_i2c_read(int reg)
+{
+	int r;
+	u8 data[4];
+	data[1] = data[2] = data[3] = data[0] = 0;
+
+	r = dlp_read_block(reg, data, 4);
+	return (int)data[3] | ((int)(data[2]) << 8) | ((int)(data[1]) << 16) | ((int)(data[0]) << 24);
+}
+
+/*
+ * Configure datapath for splash image operation
+ * @param   flash_address   - I - splash image to load from flash
+ * @param   flash_num_bytes - I - splash image to load from flash
+ * @param   CMT_SEQz        - I - select mailbox to load data to: 0=sequence/DRC, 1=CMT/splash
+ * @param   table_number    - I - splash image to load from flash
+ * @return  0 - no errors
+ *          1 - invalid flash address specified
+ *          2 - invalid mailbox specified
+ *          3 - invalid table_number / mailbox combination
+ */
+int dpp2600_flash_dma(int flash_address, int flash_num_bytes, int CMT_SEQz, int table_number)
+
+{
+	int mailbox_address, mailbox_select;
+
+	/* check argument validity */
+	if (flash_address > 0x1fffff)
+		return 1;
+	if (CMT_SEQz > 1)
+		return 2;
+	if ((CMT_SEQz == 0 && table_number > 6) ||
+		(CMT_SEQz == 1 && table_number > 5))
+		return 3;
+	/* set mailbox parameters */
+	if (CMT_SEQz) {
+		mailbox_address = CMT_SPLASH_LUT_START_ADDR;
+		mailbox_select = CMT_SPLASH_LUT_DEST_SELECT;
+	} else {
+		mailbox_address = SEQ_RESET_LUT_START_ADDR;
+		mailbox_select = SEQ_RESET_LUT_DEST_SELECT;
+	}
+
+	/* configure DMA from flash to LUT */
+	pico_i2c_write(PBC_CONTROL, 0);
+	pico_i2c_write(FLASH_START_ADDR, flash_address);
+	pico_i2c_write(FLASH_READ_BYTES, flash_num_bytes);
+	pico_i2c_write(mailbox_address, 0);
+	pico_i2c_write(mailbox_select, table_number);
+	/* transfer control to flash controller */
+	pico_i2c_write(PBC_CONTROL, 1);
+	mdelay(1000);
+	/* return register access to I2c */
+	pico_i2c_write(PBC_CONTROL, 0);
+	/* close LUT access */
+	pico_i2c_write(mailbox_select, 0);
+	return 0;
+}
+
+/* Configure datapath for parallel RGB operation */
+static void dpp2600_config_rgb(void)
+{
+	/* enable video board output drivers */
+	pico_i2c_write(SEQ_CONTROL, 0);
+	pico_i2c_write(ACTGEN_CONTROL, 0x10);
+	pico_i2c_write(SEQUENCE_MODE, SEQ_LOCK);
+	pico_i2c_write(DATA_FORMAT, RGB888);
+	pico_i2c_write(INPUT_RESOLUTION, WVGA_864_LANDSCAPE);
+	pico_i2c_write(INPUT_SOURCE, PARALLEL_RGB);
+	pico_i2c_write(CPU_IF_SYNC_METHOD, 1);
+	/* turn image back on */
+	pico_i2c_write(SEQ_CONTROL, 1);
+}
+
+/*
+ * Configure datapath for splash image operation
+ * @param   image_number - I - splash image to load from flash
+ * @return  0 - no errors
+ *          1 - invalid image_number specified
+ */
+int dpp2600_config_splash(int image_number)
+{
+	int address, size, resolution;
+	printk("dpp2600 config splash");
+	resolution = QWVGA_LANDSCAPE;
+	switch (image_number) {
+	case 0:
+		address = SPLASH_0_START_ADDR;
+		size = SPLASH_0_SIZE;
+		break;
+	case 1:
+		address = SPLASH_1_START_ADDR;
+		size = SPLASH_1_SIZE;
+		break;
+	case 2:
+		address = SPLASH_2_START_ADDR;
+		size = SPLASH_2_SIZE;
+		break;
+	case 3:
+		address = SPLASH_3_START_ADDR;
+		size = SPLASH_3_SIZE;
+		break;
+	case 4:
+		address = OPT_SPLASH_0_START_ADDR;
+		size = OPT_SPLASH_0_SIZE;
+		resolution = WVGA_DMD_OPTICAL_TEST;
+		break;
+	default:
+		return 1;
+	};
+	/* configure sequence, data format and resolution */
+	pico_i2c_write(SEQ_CONTROL, 0);
+	pico_i2c_write(SEQUENCE_MODE, SEQ_FREE_RUN);
+	pico_i2c_write(DATA_FORMAT, RGB565);
+	pico_i2c_write(INPUT_RESOLUTION, resolution);
+	pico_i2c_write(INPUT_SOURCE, SPLASH_SCREEN);
+	dpp2600_flash_dma(address, size, 1, SPLASH_LUT);
+	/* turn image back on */
+	pico_i2c_write(SEQ_CONTROL, 1);
+	return 0;
+}
+
+/*
+ *  Modify contents of a 32-bit register
+ *  @param anAddr      Register address
+ *  @param aClearMask  Any bits set in this mask will be cleared
+ *  @param aSetMask    Bits to be set after the clear
+ */
+void modify_pico_register(unsigned int Addr, unsigned int ClearMask,
+			unsigned int SetMask)
+{
+	u32 val;
+	val = __raw_readl(Addr);
+	val &= ~(ClearMask);
+	val |= (SetMask);
+	__raw_writel(val, Addr);
+}
+
+/*
+ * Configure datapath for test pattern generator operation
+ *
+ * @param   pattern_select - I - color table to load
+ *
+ * @return  0 - no errors
+ *          1 - invalid pattern specified
+ */
+int dpp2600_config_tpg(int pattern_select)
+{
+	if (pattern_select > TPG_ANSI_CHECKERBOARD)
+		return 1;
+	pico_i2c_write(SEQ_CONTROL, 0);
+	pico_i2c_write(INPUT_RESOLUTION, WVGA_854_LANDSCAPE);
+	pico_i2c_write(SEQUENCE_MODE, SEQ_LOCK);
+	pico_i2c_write(TEST_PAT_SELECT, pattern_select);
+	pico_i2c_write(INPUT_SOURCE, 1);
+	pico_i2c_write(SEQ_CONTROL, 1);
+	return 0;
+}
+
+static int pico_i2c_initialize(void)
+{
+
+	mutex_init(&sd->xfer_lock);
+	mdelay(100);
+	/* pico Soft reset */
+	pico_i2c_write(SOFT_RESET, 1);
+	/*Front end reset*/
+	pico_i2c_write(DMD_PARK_TRIGGER, 1);
+	/* write the software version number to a spare register field */
+	pico_i2c_write(MISC_REG, PICO_MAJOR<<2 | PICO_MINOR);
+	pico_i2c_write(SEQ_CONTROL, 0);
+	pico_i2c_write(SEQ_VECTOR, 0x100);
+	pico_i2c_write(DMD_BLOCK_COUNT, 7);
+	pico_i2c_write(DMD_VCC_CONTROL, 0x109);
+	pico_i2c_write(DMD_PARK_PULSE_COUNT, 0xA);
+	pico_i2c_write(DMD_PARK_PULSE_WIDTH, 0xB);
+	pico_i2c_write(DMD_PARK_DELAY, 0x2ED);
+	pico_i2c_write(DMD_SHADOW_ENABLE, 0);
+	/* serial flash common config */
+	pico_i2c_write(FLASH_OPCODE, 0xB);
+	pico_i2c_write(FLASH_DUMMY_BYTES, 1);
+	pico_i2c_write(FLASH_ADDR_BYTES, 3);
+	/* configure DMA from flash to LUT */
+	dpp2600_flash_dma(CMT_LUT_0_START_ADDR, CMT_LUT_0_SIZE, 1, CMT_LUT_ALL);
+	/* SEQ and DRC look-up tables */
+	dpp2600_flash_dma(SEQUENCE_0_START_ADDR, SEQUENCE_0_SIZE, 0, SEQ_SEQ_LUT);
+	dpp2600_flash_dma(DRC_TABLE_0_START_ADDR, DRC_TABLE_0_SIZE, 0, SEQ_DRC_LUT_ALL);
+	/* frame buffer memory controller enable */
+	pico_i2c_write(SDC_ENABLE, 1);
+	/* AGC control */
+	pico_i2c_write(AGC_CTRL, 7);
+	/*CCA */
+	pico_i2c_write(CCA_C1A, 0x100);
+	pico_i2c_write(CCA_C1B, 0x000);
+	pico_i2c_write(CCA_C1C, 0x000);
+	pico_i2c_write(CCA_C2A, 0x000);
+	pico_i2c_write(CCA_C2B, 0x100);
+	pico_i2c_write(CCA_C2C, 0x000);
+	pico_i2c_write(CCA_C3A, 0x000);
+	pico_i2c_write(CCA_C3B, 0x000);
+	pico_i2c_write(CCA_C3C, 0x100);
+	pico_i2c_write(CCA_C7A, 0x100);
+	pico_i2c_write(CCA_C7B, 0x100);
+	pico_i2c_write(CCA_C7C, 0x100);
+	pico_i2c_write(CCA_ENABLE, 1);
+	/* main datapath setup */
+	pico_i2c_write(CPU_IF_MODE, 1);
+	pico_i2c_write(SHORT_FLIP, 1);
+	pico_i2c_write(CURTAIN_CONTROL, 0);
+	/* display Logo splash image */
+	dpp2600_config_splash(1);
+	pico_i2c_write(DMD_PARK_TRIGGER, 0);
+	/* LED PWM and enables */
+	pico_i2c_write(R_DRIVE_CURRENT, 0x298);
+	pico_i2c_write(G_DRIVE_CURRENT, 0x298);
+	pico_i2c_write(B_DRIVE_CURRENT, 0x298);
+	pico_i2c_write(RGB_DRIVER_ENABLE, 7);
+	mdelay(10000);
+	dpp2600_config_rgb();
+	return 0;
+
+
+}
+
+static int pico_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	printk("pico probe called");
+	sd = kzalloc(sizeof(struct pico), GFP_KERNEL);
+	if (sd == NULL)
+		return -ENOMEM;
+	i2c_set_clientdata(client, sd);
+	sd->client = client;
+	return 0;
+}
+
+static int __exit pico_remove(struct i2c_client *client)
+{
+	struct pico *sd1 = i2c_get_clientdata(client);
+	kfree(sd1);
+	i2c_set_clientdata(client, NULL);
+
+	return 0;
+}
+
+static const struct i2c_device_id pico_id[] = {
+	{ "picoDLP_i2c_driver", 0 },
+	{ },
+};
+
+
+static int picoDLP_panel_enable(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+	printk("pico DLP init is called ");
+	if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
+		r = -EINVAL;
+		return r;
+	}
+	if (dssdev->platform_enable) {
+		r = dssdev->platform_enable(dssdev);
+		if (r)
+			return r;
+	}
+	r = omapdss_dpi_display_enable(dssdev);
+	if (r) {
+		dev_err(&dssdev->dev, "failed to enable DPI\n");
+		return r;
+	}
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+	display_control_reg	= (int)dispc_base;
+	/* Specify the Display Controller Logic Clock Divisor*/
+	modify_pico_register(display_control_reg + DSI_DIV2, 0xFF |
+			(0XFF << DSI_DIV_LCD), (1 << DSI_DIV_LCD) | (4 << DSI_DIV_PCD));
+	/* LCD output Enabled */
+	modify_pico_register(display_control_reg + DSI_CONTROL2, (1<<11), 0x00000000);
+	pico_i2c_initialize();
+	return 0;
+
+}
+static void pico_get_resolution(struct omap_dss_device *dssdev,
+		u16 *xres, u16 *yres)
+{
+		*xres = dssdev->panel.timings.x_res;
+		*yres = dssdev->panel.timings.y_res;
+}
+
+static int picoDLP_panel_probe(struct omap_dss_device *dssdev)
+{
+	dssdev->panel.config &= ~((OMAP_DSS_LCD_IPC) | (OMAP_DSS_LCD_IEO));
+	dssdev->panel.config =  (OMAP_DSS_LCD_TFT) | (OMAP_DSS_LCD_ONOFF) |
+						(OMAP_DSS_LCD_IHS)  |
+						(OMAP_DSS_LCD_IVS) ;
+	dssdev->panel.acb = 0x0;
+	dssdev->panel.timings = pico_ls_timings;
+
+	return 0;
+}
+
+static void picoDLP_panel_remove(struct omap_dss_device *dssdev)
+{
+	return ;
+}
+
+static void picoDLP_panel_disable(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+	/* Turn of DLP Power */
+	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) {
+		r = -EINVAL;
+	}
+
+		omapdss_dpi_display_disable(dssdev);
+
+		if (dssdev->platform_disable)
+		dssdev->platform_disable(dssdev);
+
+		dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+
+}
+
+static int picoDLP_panel_suspend(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+	/* Turn of DLP Power */
+	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) {
+		r = -EINVAL;
+		return r;
+	}
+
+	omapdss_dpi_display_disable(dssdev);
+
+	if (dssdev->platform_disable)
+		dssdev->platform_disable(dssdev);
+
+	dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
+
+	return 0;
+}
+
+static int picoDLP_panel_resume(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+	printk("pico DLP resume is called ");
+	if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
+		r = -EINVAL;
+		return r;
+	}
+	if (dssdev->platform_enable) {
+		r = dssdev->platform_enable(dssdev);
+		if (r)
+			return r;
+	}
+	r = omapdss_dpi_display_enable(dssdev);
+	if (r) {
+		dev_err(&dssdev->dev, "failed to enable DPI\n");
+		return r;
+	}
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+	display_control_reg	= (int)dispc_base;
+	/* Specify the Display Controller Logic Clock Divisor*/
+	modify_pico_register(display_control_reg + DSI_DIV2, 0xFF |
+			(0XFF << DSI_DIV_LCD), (1 << DSI_DIV_LCD) | (4 << DSI_DIV_PCD));
+	/* LCD output Enabled */
+	modify_pico_register(display_control_reg + DSI_CONTROL2, (1<<11), 0x00000000);
+	pico_i2c_initialize();
+	return 0;
+
+}
+
+static struct omap_dss_driver picoDLP_driver = {
+	.probe		= picoDLP_panel_probe,
+	.remove		= picoDLP_panel_remove,
+	.enable		= picoDLP_panel_enable,
+	.disable	= picoDLP_panel_disable,
+	.get_resolution	= pico_get_resolution,
+	.suspend	= picoDLP_panel_suspend,
+	.resume		= picoDLP_panel_resume,
+	.driver         = {
+		.name   = "picoDLP_panel",
+	.owner  = THIS_MODULE,
+	},
+};
+
+static struct i2c_driver pico_i2c_driver = {
+	.driver = {
+		.name           = "pico_i2c_driver",
+	},
+	.probe          = pico_probe,
+	.remove         = __exit_p(pico_remove),
+	.id_table       = pico_id,
+
+};
+
+static int __init pico_i2c_init(void)
+{
+	int r;
+	r = i2c_add_driver(&pico_i2c_driver);
+	if (r < 0) {
+		printk(KERN_WARNING DRIVER_NAME
+		" driver registration failed\n");
+		return r;
+	}
+	omap_dss_register_driver(&picoDLP_driver);
+	return 0;
+}
+
+
+static void __exit pico_i2c_exit(void)
+{
+	i2c_del_driver(&pico_i2c_driver);
+	omap_dss_unregister_driver(&picoDLP_driver);
+}
+
+
+module_init(pico_i2c_init);
+module_exit(pico_i2c_exit);
+
+
+
+MODULE_DESCRIPTION("pico DLP driver");
+MODULE_LICENSE("GPL");
+
+
+
diff --git a/drivers/video/omap2/displays/panel-picodlp.h b/drivers/video/omap2/displays/panel-picodlp.h
new file mode 100644
index 000000000000..01c1b9528467
--- /dev/null
+++ b/drivers/video/omap2/displays/panel-picodlp.h
@@ -0,0 +1,281 @@
+#define MAIN_STATUS               0x03
+#define PBC_CONTROL               0x08
+#define INPUT_SOURCE              0x0B
+#define INPUT_RESOLUTION          0x0C
+#define DATA_FORMAT               0x0D
+#define IMG_ROTATION              0x0E
+#define LONG_FLIP                 0x0F
+#define SHORT_FLIP                0x10
+#define TEST_PAT_SELECT           0x11
+#define R_DRIVE_CURRENT           0x12
+#define G_DRIVE_CURRENT           0x13
+#define B_DRIVE_CURRENT           0x14
+#define READ_REG_SELECT           0x15
+#define RGB_DRIVER_ENABLE         0x16
+
+#define CPU_IF_MODE               0x18
+#define FRAME_RATE                0x19
+#define CPU_IF_SYNC_METHOD        0x1A
+#define CPU_IF_SOF                0x1B
+#define CPU_IF_EOF                0x1C
+#define CPU_IF_SLEEP              0x1D
+
+#define SEQUENCE_MODE             0x1E
+#define SOFT_RESET                0x1F
+#define FRONT_END_RESET           0x21
+#define AUTO_PWR_ENABLE           0x22
+
+#define VSYNC_LINE_DELAY          0x23
+#define CPU_PI_HORIZ_START        0x24
+#define CPU_PI_VERT_START         0x25
+#define CPU_PI_HORIZ_WIDTH        0x26
+#define CPU_PI_VERT_HEIGHT        0x27
+
+#define PIXEL_MASK_CROP           0x28
+#define CROP_FIRST_LINE           0x29
+#define CROP_LAST_LINE            0x2A
+#define CROP_FIRST_PIXEL          0x2B
+#define CROP_LAST_PIXEL           0x2C
+#define DMD_PARK_TRIGGER		  0x2D
+
+#define MISC_REG                  0x30
+
+/* AGC registers */
+#define AGC_CTRL                  0x50
+#define AGC_CLIPPED_PIXS          0x55
+#define AGC_BRIGHT_PIXS           0x56
+#define AGC_BG_PIXS               0x57
+#define AGC_SAFETY_MARGIN         0x17
+
+/* CCA registers */
+#define CCA_ENABLE                0x5E
+#define CCA_C1A                   0x5F
+#define CCA_C1B                   0x60
+#define CCA_C1C                   0x61
+#define CCA_C2A                   0x62
+#define CCA_C2B                   0x63
+#define CCA_C2C                   0x64
+#define CCA_C3A                   0x65
+#define CCA_C3B                   0x66
+#define CCA_C3C                   0x67
+#define CCA_C7A                   0x71
+#define CCA_C7B                   0x72
+#define CCA_C7C                   0x73
+
+/* registers for DMA operations from flash to DPP2600 LUTs */
+#define FLASH_ADDR_BYTES          0x74
+#define FLASH_DUMMY_BYTES         0x75
+#define FLASH_WRITE_BYTES         0x76
+#define FLASH_READ_BYTES          0x77
+#define FLASH_OPCODE              0x78
+#define FLASH_START_ADDR          0x79
+#define FLASH_DUMMY2              0x7A
+#define FLASH_WRITE_DATA          0x7B
+
+#define TEMPORAL_DITH_DISABLE     0x7E
+#define SEQ_CONTROL               0x82
+#define SEQ_VECTOR                0x83
+#define DMD_BLOCK_COUNT           0x84
+#define DMD_VCC_CONTROL           0x86
+#define DMD_PARK_PULSE_COUNT      0x87
+#define DMD_PARK_PULSE_WIDTH      0x88
+#define DMD_PARK_DELAY            0x89
+#define DMD_SHADOW_ENABLE         0x8E
+#define SEQ_STATUS                0x8F
+#define FLASH_CLOCK_CONTROL       0x98
+#define DMD_PARK                  0x2D
+
+#define SDRAM_BIST_ENABLE         0x46
+#define DDR_DRIVER_STRENGTH       0x9A
+#define SDC_ENABLE                0x9D
+#define SDC_BUFF_SWAP_DISABLE     0xA3
+#define CURTAIN_CONTROL           0xA6
+#define DDR_BUS_SWAP_ENABLE       0xA7
+#define DMD_TRC_ENABLE            0xA8
+#define DMD_BUS_SWAP_ENABLE       0xA9
+
+#define ACTGEN_ENABLE             0xAE
+#define ACTGEN_CONTROL            0xAF
+#define ACTGEN_HORIZ_BP           0xB0
+#define ACTGEN_VERT_BP            0xB1
+
+/* LUT access */
+#define CMT_SPLASH_LUT_START_ADDR   0xFA
+#define CMT_SPLASH_LUT_DEST_SELECT  0xFB
+#define CMT_SPLASH_LUT_DATA         0xFC
+#define SEQ_RESET_LUT_START_ADDR    0xFD
+#define SEQ_RESET_LUT_DEST_SELECT   0xFE
+#define SEQ_RESET_LUT_DATA          0xFF
+
+/* input source defines */
+#define PARALLEL_RGB              0
+#define INT_TEST_PATTERN          1
+#define SPLASH_SCREEN             2
+#define CPU_INTF                  3
+#define BT656                     4
+
+/* input resolution defines */
+#define QVGA_PORTRAIT             0       /* (240h*320v) */
+#define QVGA_LANDSCAPE            1       /* (320h*240v) */
+#define QWVGA_LANDSCAPE           3       /* (427h*240v) */
+#define VGA_PORTRAIT_2_3          4       /* (430h*640v) */
+#define VGA_LANDSCAPE_3_2         5       /* (640h*430v) */
+#define VGA_PORTRAIT              6       /* (480h*640v) */
+#define VGA_LANDSCAPE             7       /* (640h*480v) */
+#define WVGA_720_PORTRAIT         8       /* (480h*720v) */
+#define WVGA_720_LANDSCAPE        9       /* (720h*480v) */
+#define WVGA_752_PORTRAIT         10      /* (480h*752v) */
+#define WVGA_752_LANDSCAPE        11      /* (752h*480v) */
+#define WVGA_800_PORTRAIT         12      /* (480h*800v) */
+#define WVGA_800_LANDSCAPE        13      /* (800h*480v) */
+#define WVGA_852_PORTRAIT         14      /* (480h*852v) */
+#define WVGA_852_LANDSCAPE        15      /* (852h*480v) */
+#define WVGA_853_PORTRAIT         16      /* (480h*853v) */
+#define WVGA_853_LANDSCAPE        17      /* (853h*480v) */
+#define WVGA_854_PORTRAIT         18      /* (480h*854v) */
+#define WVGA_854_LANDSCAPE        19      /* (854h*480v) */
+#define WVGA_864_PORTRAIT         20      /* (480h*864v) */
+#define WVGA_864_LANDSCAPE        21      /* (864h*480v) */
+#define NTSC_LANDSCAPE            23      /* (720h*240v) */
+#define PAL_LANDSCAPE             25      /* (720h*288v) */
+#define VGA_DMD_OPTICAL_TEST      33      /* (456h*684v) */
+#define WVGA_DMD_OPTICAL_TEST     35      /* (608h*684v) */
+
+/* data format defines */
+#define RGB565                    0
+#define RGB666                    1
+#define RGB888                    2
+
+/* test pattern defines */
+#define TPG_CHECKERBOARD          0
+#define TPG_BLACK                 1
+#define TPG_WHITE                 2
+#define TPG_RED                   3
+#define TPG_BLUE                  4
+#define TPG_GREEN                 5
+#define TPG_VLINES_BLACK          6
+#define TPG_HLINES_BLACK          7
+#define TPG_VLINES_ALT            8
+#define TPG_HLINES_ALT            9
+#define TPG_DIAG_LINES            10
+#define TPG_GREYRAMP_VERT         11
+#define TPG_GREYRAMP_HORIZ        12
+#define TPG_ANSI_CHECKERBOARD     13
+
+/* sequence mode defines */
+#define SEQ_FREE_RUN              0
+#define SEQ_LOCK                  1
+
+/* curtain color defines */
+#define CURTAIN_BLACK             0
+#define CURTAIN_RED               1
+#define CURTAIN_GREEN             2
+#define CURTAIN_BLUE              3
+#define CURTAIN_YELLOW            4
+#define CURTAIN_MAGENTA           5
+#define CURTAIN_CYAN              6
+#define CURTAIN_WHITE             7
+
+/* LUT defines */
+#define CMT_LUT_NONE              0
+#define CMT_LUT_GREEN             1
+#define CMT_LUT_RED               2
+#define CMT_LUT_BLUE              3
+#define CMT_LUT_ALL               4
+#define SPLASH_LUT                5
+
+#define SEQ_LUT_NONE              0
+#define SEQ_DRC_LUT_0             1
+#define SEQ_DRC_LUT_1             2
+#define SEQ_DRC_LUT_2             3
+#define SEQ_DRC_LUT_3             4
+#define SEQ_SEQ_LUT               5
+#define SEQ_DRC_LUT_ALL           6
+#define WPC_PROGRAM_LUT           7
+
+/*#define DMA_STATUS                BIT8 */
+
+
+#define BITSTREAM_START_ADDR         0x00000000
+#define BITSTREAM_SIZE               0x00040000
+
+#define WPC_FW_0_START_ADDR          0x00040000
+#define WPC_FW_0_SIZE                0x00000ce8
+
+#define SEQUENCE_0_START_ADDR        0x00044000
+#define SEQUENCE_0_SIZE              0x00001000
+
+#define SEQUENCE_1_START_ADDR        0x00045000
+#define SEQUENCE_1_SIZE              0x00000d10
+
+#define SEQUENCE_2_START_ADDR        0x00046000
+#define SEQUENCE_2_SIZE              0x00000d10
+
+#define SEQUENCE_3_START_ADDR        0x00047000
+#define SEQUENCE_3_SIZE              0x00000d10
+
+#define SEQUENCE_4_START_ADDR        0x00048000
+#define SEQUENCE_4_SIZE              0x00000d10
+
+#define SEQUENCE_5_START_ADDR        0x00049000
+#define SEQUENCE_5_SIZE              0x00000d10
+
+#define SEQUENCE_6_START_ADDR        0x0004a000
+#define SEQUENCE_6_SIZE              0x00000d10
+
+#define CMT_LUT_0_START_ADDR         0x0004b200
+#define CMT_LUT_0_SIZE               0x00000600
+
+#define CMT_LUT_1_START_ADDR         0x0004b800
+#define CMT_LUT_1_SIZE               0x00000600
+
+#define CMT_LUT_2_START_ADDR         0x0004be00
+#define CMT_LUT_2_SIZE               0x00000600
+
+#define CMT_LUT_3_START_ADDR         0x0004c400
+#define CMT_LUT_3_SIZE               0x00000600
+
+#define CMT_LUT_4_START_ADDR         0x0004ca00
+#define CMT_LUT_4_SIZE               0x00000600
+
+#define CMT_LUT_5_START_ADDR         0x0004d000
+#define CMT_LUT_5_SIZE               0x00000600
+
+#define CMT_LUT_6_START_ADDR         0x0004d600
+#define CMT_LUT_6_SIZE               0x00000600
+
+#define DRC_TABLE_0_START_ADDR       0x0004dc00
+#define DRC_TABLE_0_SIZE             0x00000100
+
+#define SPLASH_0_START_ADDR          0x0004dd00
+#define SPLASH_0_SIZE                0x00032280
+
+#define SEQUENCE_7_START_ADDR        0x00080000
+#define SEQUENCE_7_SIZE              0x00000d10
+
+#define SEQUENCE_8_START_ADDR        0x00081800
+#define SEQUENCE_8_SIZE              0x00000d10
+
+#define SEQUENCE_9_START_ADDR        0x00083000
+#define SEQUENCE_9_SIZE              0x00000d10
+
+#define CMT_LUT_7_START_ADDR         0x0008e000
+#define CMT_LUT_7_SIZE               0x00000600
+
+#define CMT_LUT_8_START_ADDR         0x0008e800
+#define CMT_LUT_8_SIZE               0x00000600
+
+#define CMT_LUT_9_START_ADDR         0x0008f000
+#define CMT_LUT_9_SIZE               0x00000600
+
+#define SPLASH_1_START_ADDR          0x0009a000
+#define SPLASH_1_SIZE                0x00032280
+
+#define SPLASH_2_START_ADDR          0x000cd000
+#define SPLASH_2_SIZE                0x00032280
+
+#define SPLASH_3_START_ADDR          0x00100000
+#define SPLASH_3_SIZE                0x00032280
+
+#define OPT_SPLASH_0_START_ADDR      0x00134000
+#define OPT_SPLASH_0_SIZE            0x000cb100
diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
index 8d51a5e6341c..7d9eb2b1f5af 100644
--- a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
@@ -20,10 +20,17 @@
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/device.h>
+#include <linux/backlight.h>
+#include <linux/fb.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 
 #include <plat/display.h>
 
+struct sharp_data {
+	struct backlight_device *bl;
+};
+
 static struct omap_video_timings sharp_ls_timings = {
 	.x_res = 480,
 	.y_res = 640,
@@ -39,18 +46,89 @@ static struct omap_video_timings sharp_ls_timings = {
 	.vbp		= 1,
 };
 
+static int sharp_ls_bl_update_status(struct backlight_device *bl)
+{
+	struct omap_dss_device *dssdev = dev_get_drvdata(&bl->dev);
+	int level;
+
+	if (!dssdev->set_backlight)
+		return -EINVAL;
+
+	if (bl->props.fb_blank == FB_BLANK_UNBLANK &&
+			bl->props.power == FB_BLANK_UNBLANK)
+		level = bl->props.brightness;
+	else
+		level = 0;
+
+	return dssdev->set_backlight(dssdev, level);
+}
+
+static int sharp_ls_bl_get_brightness(struct backlight_device *bl)
+{
+	if (bl->props.fb_blank == FB_BLANK_UNBLANK &&
+			bl->props.power == FB_BLANK_UNBLANK)
+		return bl->props.brightness;
+
+	return 0;
+}
+
+static const struct backlight_ops sharp_ls_bl_ops = {
+	.get_brightness = sharp_ls_bl_get_brightness,
+	.update_status  = sharp_ls_bl_update_status,
+};
+
+
+
 static int sharp_ls_panel_probe(struct omap_dss_device *dssdev)
 {
+	struct backlight_properties props;
+	struct backlight_device *bl;
+	struct sharp_data *sd;
+	int r;
+
 	dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
 		OMAP_DSS_LCD_IHS;
 	dssdev->panel.acb = 0x28;
 	dssdev->panel.timings = sharp_ls_timings;
 
+	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
+	if (!sd)
+		return -ENOMEM;
+
+	dev_set_drvdata(&dssdev->dev, sd);
+
+	memset(&props, 0, sizeof(struct backlight_properties));
+	props.max_brightness = dssdev->max_backlight_level;
+
+	bl = backlight_device_register("sharp-ls", &dssdev->dev, dssdev,
+			&sharp_ls_bl_ops, &props);
+	if (IS_ERR(bl)) {
+		r = PTR_ERR(bl);
+		kfree(sd);
+		return r;
+	}
+	sd->bl = bl;
+
+	bl->props.fb_blank = FB_BLANK_UNBLANK;
+	bl->props.power = FB_BLANK_UNBLANK;
+	bl->props.brightness = dssdev->max_backlight_level;
+	r = sharp_ls_bl_update_status(bl);
+	if (r < 0)
+		dev_err(&dssdev->dev, "failed to set lcd brightness\n");
+
 	return 0;
 }
 
 static void sharp_ls_panel_remove(struct omap_dss_device *dssdev)
 {
+	struct sharp_data *sd = dev_get_drvdata(&dssdev->dev);
+	struct backlight_device *bl = sd->bl;
+
+	bl->props.power = FB_BLANK_POWERDOWN;
+	sharp_ls_bl_update_status(bl);
+	backlight_device_unregister(bl);
+
+	kfree(sd);
 }
 
 static int sharp_ls_power_on(struct omap_dss_device *dssdev)
diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c
index 4f3988a41082..9d4115df7782 100644
--- a/drivers/video/omap2/displays/panel-taal.c
+++ b/drivers/video/omap2/displays/panel-taal.c
@@ -31,6 +31,7 @@
 #include <linux/completion.h>
 #include <linux/workqueue.h>
 #include <linux/slab.h>
+#include <linux/mutex.h>
 
 #include <plat/display.h>
 
@@ -64,9 +65,17 @@
 /* #define TAAL_USE_ESD_CHECK */
 #define TAAL_ESD_CHECK_PERIOD	msecs_to_jiffies(5000)
 
+static bool dsi_te_sync = 1;
+module_param_named(dsi_te_sync, dsi_te_sync, bool, 0644);
+MODULE_PARM_DESC(dsi_te_sync, "enable/disable tearing");
+
 static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable);
+static int taal_update(struct omap_dss_device *dssdev,
+						u16 x, u16 y, u16 w, u16 h);
 
 struct taal_data {
+	struct mutex lock;
+
 	struct backlight_device *bldev;
 
 	unsigned long	hw_guard_end;	/* next value of jiffies when we can
@@ -113,12 +122,12 @@ static void hw_guard_wait(struct taal_data *td)
 	}
 }
 
-static int taal_dcs_read_1(u8 dcs_cmd, u8 *data)
+static int taal_dcs_read_1(enum omap_dsi_index ix, u8 dcs_cmd, u8 *data)
 {
 	int r;
 	u8 buf[1];
 
-	r = dsi_vc_dcs_read(TCH, dcs_cmd, buf, 1);
+	r = dsi_vc_dcs_read(ix, TCH, dcs_cmd, buf, 1);
 
 	if (r < 0)
 		return r;
@@ -128,20 +137,20 @@ static int taal_dcs_read_1(u8 dcs_cmd, u8 *data)
 	return 0;
 }
 
-static int taal_dcs_write_0(u8 dcs_cmd)
+static int taal_dcs_write_0(enum omap_dsi_index ix, u8 dcs_cmd)
 {
-	return dsi_vc_dcs_write(TCH, &dcs_cmd, 1);
+	return dsi_vc_dcs_write(ix, TCH, &dcs_cmd, 1);
 }
 
-static int taal_dcs_write_1(u8 dcs_cmd, u8 param)
+static int taal_dcs_write_1(enum omap_dsi_index ix, u8 dcs_cmd, u8 param)
 {
 	u8 buf[2];
 	buf[0] = dcs_cmd;
 	buf[1] = param;
-	return dsi_vc_dcs_write(TCH, buf, 2);
+	return dsi_vc_dcs_write(ix, TCH, buf, 2);
 }
 
-static int taal_sleep_in(struct taal_data *td)
+static int taal_sleep_in(enum omap_dsi_index ix, struct taal_data *td)
 
 {
 	u8 cmd;
@@ -150,7 +159,7 @@ static int taal_sleep_in(struct taal_data *td)
 	hw_guard_wait(td);
 
 	cmd = DCS_SLEEP_IN;
-	r = dsi_vc_dcs_write_nosync(TCH, &cmd, 1);
+	r = dsi_vc_dcs_write_nosync(ix, TCH, &cmd, 1);
 	if (r)
 		return r;
 
@@ -161,13 +170,13 @@ static int taal_sleep_in(struct taal_data *td)
 	return 0;
 }
 
-static int taal_sleep_out(struct taal_data *td)
+static int taal_sleep_out(enum omap_dsi_index ix, struct taal_data *td)
 {
 	int r;
 
 	hw_guard_wait(td);
 
-	r = taal_dcs_write_0(DCS_SLEEP_OUT);
+	r = taal_dcs_write_0(ix, DCS_SLEEP_OUT);
 	if (r)
 		return r;
 
@@ -178,30 +187,32 @@ static int taal_sleep_out(struct taal_data *td)
 	return 0;
 }
 
-static int taal_get_id(u8 *id1, u8 *id2, u8 *id3)
+static int taal_get_id(enum omap_dsi_index ix,
+	u8 *id1, u8 *id2, u8 *id3)
 {
 	int r;
 
-	r = taal_dcs_read_1(DCS_GET_ID1, id1);
+	r = taal_dcs_read_1(ix, DCS_GET_ID1, id1);
 	if (r)
 		return r;
-	r = taal_dcs_read_1(DCS_GET_ID2, id2);
+	r = taal_dcs_read_1(ix, DCS_GET_ID2, id2);
 	if (r)
 		return r;
-	r = taal_dcs_read_1(DCS_GET_ID3, id3);
+	r = taal_dcs_read_1(ix, DCS_GET_ID3, id3);
 	if (r)
 		return r;
 
 	return 0;
 }
 
-static int taal_set_addr_mode(u8 rotate, bool mirror)
+static int taal_set_addr_mode(enum omap_dsi_index ix,
+	u8 rotate, bool mirror)
 {
 	int r;
 	u8 mode;
 	int b5, b6, b7;
 
-	r = taal_dcs_read_1(DCS_READ_MADCTL, &mode);
+	r = taal_dcs_read_1(ix, DCS_READ_MADCTL, &mode);
 	if (r)
 		return r;
 
@@ -235,10 +246,11 @@ static int taal_set_addr_mode(u8 rotate, bool mirror)
 	mode &= ~((1<<7) | (1<<6) | (1<<5));
 	mode |= (b7 << 7) | (b6 << 6) | (b5 << 5);
 
-	return taal_dcs_write_1(DCS_MEM_ACC_CTRL, mode);
+	return taal_dcs_write_1(ix, DCS_MEM_ACC_CTRL, mode);
 }
 
-static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)
+static int taal_set_update_window(enum omap_dsi_index ix,
+	u16 x, u16 y, u16 w, u16 h)
 {
 	int r;
 	u16 x1 = x;
@@ -253,7 +265,7 @@ static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)
 	buf[3] = (x2 >> 8) & 0xff;
 	buf[4] = (x2 >> 0) & 0xff;
 
-	r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf));
+	r = dsi_vc_dcs_write_nosync(ix, TCH, buf, sizeof(buf));
 	if (r)
 		return r;
 
@@ -263,11 +275,11 @@ static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)
 	buf[3] = (y2 >> 8) & 0xff;
 	buf[4] = (y2 >> 0) & 0xff;
 
-	r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf));
+	r = dsi_vc_dcs_write_nosync(ix, TCH, buf, sizeof(buf));
 	if (r)
 		return r;
 
-	dsi_vc_send_bta_sync(TCH);
+	dsi_vc_send_bta_sync(ix, TCH);
 
 	return r;
 }
@@ -278,6 +290,12 @@ static int taal_bl_update_status(struct backlight_device *dev)
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int r;
 	int level;
+	enum omap_dsi_index ix;
+
+	if (cpu_is_omap44xx())
+		return;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
 			dev->props.power == FB_BLANK_UNBLANK)
@@ -289,9 +307,9 @@ static int taal_bl_update_status(struct backlight_device *dev)
 
 	if (td->use_dsi_bl) {
 		if (td->enabled) {
-			dsi_bus_lock();
-			r = taal_dcs_write_1(DCS_BRIGHTNESS, level);
-			dsi_bus_unlock();
+			dsi_bus_lock(ix);
+			r = taal_dcs_write_1(ix, DCS_BRIGHTNESS, level);
+			dsi_bus_unlock(ix);
 			if (r)
 				return r;
 		}
@@ -351,6 +369,15 @@ static irqreturn_t taal_te_isr(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+static irqreturn_t taal_te_isr2(int irq, void *data)
+{
+	struct omap_dss_device *dssdev = data;
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+	complete_all(&td->te_completion);
+
+	return IRQ_HANDLED;
+}
+
 static ssize_t taal_num_errors_show(struct device *dev,
 		struct device_attribute *attr, char *buf)
 {
@@ -358,11 +385,14 @@ static ssize_t taal_num_errors_show(struct device *dev,
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	u8 errors;
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	if (td->enabled) {
-		dsi_bus_lock();
-		r = taal_dcs_read_1(DCS_READ_NUM_ERRORS, &errors);
-		dsi_bus_unlock();
+		dsi_bus_lock(ix);
+		r = taal_dcs_read_1(ix, DCS_READ_NUM_ERRORS, &errors);
+		dsi_bus_unlock(ix);
 	} else {
 		r = -ENODEV;
 	}
@@ -380,11 +410,14 @@ static ssize_t taal_hw_revision_show(struct device *dev,
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	u8 id1, id2, id3;
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	if (td->enabled) {
-		dsi_bus_lock();
-		r = taal_get_id(&id1, &id2, &id3);
-		dsi_bus_unlock();
+		dsi_bus_lock(ix);
+		r = taal_get_id(ix, &id1, &id2, &id3);
+		dsi_bus_unlock(ix);
 	} else {
 		r = -ENODEV;
 	}
@@ -429,6 +462,9 @@ static ssize_t store_cabc_mode(struct device *dev,
 	struct omap_dss_device *dssdev = to_dss_device(dev);
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int i;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) {
 		if (sysfs_streq(cabc_modes[i], buf))
@@ -439,10 +475,10 @@ static ssize_t store_cabc_mode(struct device *dev,
 		return -EINVAL;
 
 	if (td->enabled) {
-		dsi_bus_lock();
+		dsi_bus_lock(ix);
 		if (!td->cabc_broken)
-			taal_dcs_write_1(DCS_WRITE_CABC, i);
-		dsi_bus_unlock();
+			taal_dcs_write_1(ix, DCS_WRITE_CABC, i);
+		dsi_bus_unlock(ix);
 	}
 
 	td->cabc_mode = i;
@@ -499,10 +535,12 @@ static int taal_probe(struct omap_dss_device *dssdev)
 
 	dev_dbg(&dssdev->dev, "probe\n");
 
-	dssdev->panel.config = OMAP_DSS_LCD_TFT;
+	dssdev->panel.config = OMAP_DSS_LCD_TFT |
+		OMAP_DSS_LCD_ONOFF | OMAP_DSS_LCD_RF;
 	dssdev->panel.timings = taal_panel_timings;
 	dssdev->ctrl.pixel_size = 24;
-
+	dssdev->panel.acbi = 0;
+	dssdev->panel.acb = 0;
 	td = kzalloc(sizeof(*td), GFP_KERNEL);
 	if (!td) {
 		r = -ENOMEM;
@@ -510,12 +548,15 @@ static int taal_probe(struct omap_dss_device *dssdev)
 	}
 	td->dssdev = dssdev;
 
+	mutex_init(&td->lock);
+
 	td->esd_wq = create_singlethread_workqueue("taal_esd");
 	if (td->esd_wq == NULL) {
 		dev_err(&dssdev->dev, "can't create ESD workqueue\n");
 		r = -ENOMEM;
 		goto err1;
 	}
+
 	INIT_DELAYED_WORK_DEFERRABLE(&td->esd_work, taal_esd_work);
 
 	dev_set_drvdata(&dssdev->dev, td);
@@ -530,8 +571,10 @@ static int taal_probe(struct omap_dss_device *dssdev)
 		props.max_brightness = 255;
 	else
 		props.max_brightness = 127;
-	bldev = backlight_device_register("taal", &dssdev->dev, dssdev,
-					  &taal_bl_ops, &props);
+
+		bldev = backlight_device_register(dssdev->name,
+			&dssdev->dev, dssdev, &taal_bl_ops, &props);
+
 	if (IS_ERR(bldev)) {
 		r = PTR_ERR(bldev);
 		goto err2;
@@ -548,8 +591,27 @@ static int taal_probe(struct omap_dss_device *dssdev)
 
 	taal_bl_update_status(bldev);
 
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
+		td->te_enabled = true;
+
 	if (dssdev->phy.dsi.ext_te) {
 		int gpio = dssdev->phy.dsi.ext_te_gpio;
+		void __iomem *phymux_base = NULL;
+		int val;
+
+		phymux_base = ioremap(0x4A100000, 0x1000);
+
+		if (dssdev->channel == OMAP_DSS_CHANNEL_LCD) {
+			val = __raw_readl(phymux_base + 0x90);
+			val = val & 0xFFFFFFE0;
+			val = val | 0x11B;
+			__raw_writel(val, phymux_base + 0x90);
+		} else {
+			val = __raw_readl(phymux_base + 0x94);
+			val = val & 0xFFFFFFE0;
+			val = val | 0x11B;
+			__raw_writel(val, phymux_base + 0x94);
+		}
 
 		r = gpio_request(gpio, "taal irq");
 		if (r) {
@@ -559,10 +621,15 @@ static int taal_probe(struct omap_dss_device *dssdev)
 
 		gpio_direction_input(gpio);
 
-		r = request_irq(gpio_to_irq(gpio), taal_te_isr,
+		if (dssdev->channel == OMAP_DSS_CHANNEL_LCD) {
+			r = request_irq(gpio_to_irq(gpio), taal_te_isr,
+					IRQF_DISABLED | IRQF_TRIGGER_RISING,
+					"taal vsync", dssdev);
+		} else {
+			r = request_irq(gpio_to_irq(gpio), taal_te_isr2,
 				IRQF_DISABLED | IRQF_TRIGGER_RISING,
-				"taal vsync", dssdev);
-
+				"taal vsync2", dssdev);
+		}
 		if (r) {
 			dev_err(&dssdev->dev, "IRQ request failed\n");
 			gpio_free(gpio);
@@ -572,6 +639,7 @@ static int taal_probe(struct omap_dss_device *dssdev)
 		init_completion(&td->te_completion);
 
 		td->use_ext_te = true;
+		iounmap(phymux_base);
 	}
 
 	r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group);
@@ -629,6 +697,9 @@ static int taal_power_on(struct omap_dss_device *dssdev)
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	u8 id1, id2, id3;
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	if (dssdev->platform_enable) {
 		r = dssdev->platform_enable(dssdev);
@@ -639,7 +710,7 @@ static int taal_power_on(struct omap_dss_device *dssdev)
 	/* it seems we have to wait a bit until taal is ready */
 	msleep(5);
 
-	dsi_bus_lock();
+	dsi_bus_lock(ix);
 
 	r = omapdss_dsi_display_enable(dssdev);
 	if (r) {
@@ -647,13 +718,13 @@ static int taal_power_on(struct omap_dss_device *dssdev)
 		goto err0;
 	}
 
-	omapdss_dsi_vc_enable_hs(TCH, false);
+	omapdss_dsi_vc_enable_hs(ix, TCH, false);
 
-	r = taal_sleep_out(td);
+	r = taal_sleep_out(ix, td);
 	if (r)
 		goto err;
 
-	r = taal_get_id(&id1, &id2, &id3);
+	r = taal_get_id(ix, &id1, &id2, &id3);
 	if (r)
 		goto err;
 
@@ -661,22 +732,23 @@ static int taal_power_on(struct omap_dss_device *dssdev)
 	if (id2 == 0x00 || id2 == 0xff || id2 == 0x81)
 		td->cabc_broken = true;
 
-	taal_dcs_write_1(DCS_BRIGHTNESS, 0xff);
-	taal_dcs_write_1(DCS_CTRL_DISPLAY, (1<<2) | (1<<5)); /* BL | BCTRL */
+	taal_dcs_write_1(ix, DCS_BRIGHTNESS, 0xff);
+	taal_dcs_write_1(ix, DCS_CTRL_DISPLAY,
+			(1<<2) | (1<<5)); /* BL | BCTRL */
 
-	taal_dcs_write_1(DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */
+	taal_dcs_write_1(ix, DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */
 
-	taal_set_addr_mode(td->rotate, td->mirror);
+	taal_set_addr_mode(ix, td->rotate, td->mirror);
 	if (!td->cabc_broken)
-		taal_dcs_write_1(DCS_WRITE_CABC, td->cabc_mode);
+		taal_dcs_write_1(ix, DCS_WRITE_CABC, td->cabc_mode);
 
-	taal_dcs_write_0(DCS_DISPLAY_ON);
+	taal_dcs_write_0(ix, DCS_DISPLAY_ON);
 
 	r = _taal_enable_te(dssdev, td->te_enabled);
 	if (r)
 		goto err;
 
-#ifdef TAAL_USE_ESD_CHECK
+#if TAAL_USE_ESD_CHECK
 	queue_delayed_work(td->esd_wq, &td->esd_work, TAAL_ESD_CHECK_PERIOD);
 #endif
 
@@ -691,16 +763,15 @@ static int taal_power_on(struct omap_dss_device *dssdev)
 		td->intro_printed = true;
 	}
 
-	omapdss_dsi_vc_enable_hs(TCH, true);
+	omapdss_dsi_vc_enable_hs(ix, TCH, true);
 
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
 
 	return 0;
 err:
-	dsi_bus_unlock();
-
 	omapdss_dsi_display_disable(dssdev);
 err0:
+	dsi_bus_unlock(ix);
 	if (dssdev->platform_disable)
 		dssdev->platform_disable(dssdev);
 
@@ -710,13 +781,16 @@ err0:
 static void taal_power_off(struct omap_dss_device *dssdev)
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
-	dsi_bus_lock();
+	dsi_bus_lock(ix);
 
 	cancel_delayed_work(&td->esd_work);
 
-	taal_dcs_write_0(DCS_DISPLAY_OFF);
-	taal_sleep_in(td);
+	taal_dcs_write_0(ix, DCS_DISPLAY_OFF);
+	taal_sleep_in(ix, td);
 
 	/* wait a bit so that the message goes through */
 	msleep(10);
@@ -728,67 +802,143 @@ static void taal_power_off(struct omap_dss_device *dssdev)
 
 	td->enabled = 0;
 
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
 }
 
 static int taal_enable(struct omap_dss_device *dssdev)
 {
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int r;
+
 	dev_dbg(&dssdev->dev, "enable\n");
 
-	if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)
-		return -EINVAL;
+	mutex_lock(&td->lock);
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
+		r = -EINVAL;
+		goto err;
+	}
 
 	r = taal_power_on(dssdev);
 	if (r)
-		return r;
+		goto err;
 
 	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
 
+	mutex_unlock(&td->lock);
+
+	/* auto update for OMAP4 */
+	if (cpu_is_omap44xx())
+		taal_update(dssdev, 0, 0, 864, 480);
+
+	return 0;
+err:
+	dev_dbg(&dssdev->dev, "enable failed\n");
+	mutex_unlock(&td->lock);
 	return r;
 }
 
 static void taal_disable(struct omap_dss_device *dssdev)
 {
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+
 	dev_dbg(&dssdev->dev, "disable\n");
 
+	mutex_lock(&td->lock);
+
 	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
 		taal_power_off(dssdev);
 
 	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+
+	mutex_unlock(&td->lock);
 }
 
 static int taal_suspend(struct omap_dss_device *dssdev)
 {
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+	int r;
+
+	if (cpu_is_omap44xx())
+		return;
 	dev_dbg(&dssdev->dev, "suspend\n");
 
-	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
-		return -EINVAL;
+	mutex_lock(&td->lock);
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) {
+		r = -EINVAL;
+		goto err;
+	}
 
 	taal_power_off(dssdev);
 	dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
 
+	mutex_unlock(&td->lock);
+
 	return 0;
+err:
+	mutex_unlock(&td->lock);
+	return r;
 }
 
 static int taal_resume(struct omap_dss_device *dssdev)
 {
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int r;
+
+	if (cpu_is_omap44xx())
+		return;
+
 	dev_dbg(&dssdev->dev, "resume\n");
 
-	if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED)
-		return -EINVAL;
+	mutex_lock(&td->lock);
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
+		r = -EINVAL;
+		goto err;
+	}
 
 	r = taal_power_on(dssdev);
 	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+	mutex_unlock(&td->lock);
+
 	return r;
+err:
+	mutex_unlock(&td->lock);
+	return r;
+}
+
+static int taal_wait_te(struct omap_dss_device *dssdev)
+{
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+	long wait = msecs_to_jiffies(500);
+
+	if (!td->use_ext_te || !td->te_enabled)
+		return 0;
+
+	INIT_COMPLETION(td->te_completion);
+	wait = wait_for_completion_timeout(&td->te_completion, wait);
+	if (wait == 0) {
+		dev_err(&dssdev->dev, "timeout waiting TE\n");
+		return -ETIME;
+	}
+
+	return 0;
 }
 
 static void taal_framedone_cb(int err, void *data)
 {
 	struct omap_dss_device *dssdev = data;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+
 	dev_dbg(&dssdev->dev, "framedone, err %d\n", err);
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	/* auto update for OMAP4 */
+	if (cpu_is_omap44xx())
+		taal_update(dssdev, 0, 0, 864, 480);
 }
 
 static int taal_update(struct omap_dss_device *dssdev,
@@ -796,10 +946,14 @@ static int taal_update(struct omap_dss_device *dssdev,
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	dev_dbg(&dssdev->dev, "update %d, %d, %d x %d\n", x, y, w, h);
 
-	dsi_bus_lock();
+	mutex_lock(&td->lock);
+	dsi_bus_lock(ix);
 
 	if (!td->enabled) {
 		r = 0;
@@ -810,28 +964,45 @@ static int taal_update(struct omap_dss_device *dssdev,
 	if (r)
 		goto err;
 
-	r = taal_set_update_window(x, y, w, h);
+	r = taal_set_update_window(ix, x, y, w, h);
 	if (r)
 		goto err;
 
-	r = omap_dsi_update(dssdev, TCH, x, y, w, h,
-			taal_framedone_cb, dssdev);
+	if (dsi_te_sync && dssdev->phy.dsi.ext_te)
+		dssdev->driver->wait_for_te(dssdev);
+
+	/* We use VC(1) for VideoPort Data and VC(0) for L4 data */
+	if (cpu_is_omap44xx())
+		r = omap_dsi_update(dssdev, 1, x, y, w, h,
+				taal_framedone_cb, dssdev);
+	else
+		r = omap_dsi_update(dssdev, TCH, x, y, w, h,
+				taal_framedone_cb, dssdev);
 	if (r)
 		goto err;
 
 	/* note: no bus_unlock here. unlock is in framedone_cb */
+	mutex_unlock(&td->lock);
 	return 0;
 err:
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 	return r;
 }
 
 static int taal_sync(struct omap_dss_device *dssdev)
 {
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+
 	dev_dbg(&dssdev->dev, "sync\n");
 
-	dsi_bus_lock();
-	dsi_bus_unlock();
+	mutex_lock(&td->lock);
+	dsi_bus_lock(ix);
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 
 	dev_dbg(&dssdev->dev, "sync done\n");
 
@@ -842,13 +1013,16 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable)
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	td->te_enabled = enable;
 
 	if (enable)
-		r = taal_dcs_write_1(DCS_TEAR_ON, 0);
+		r = taal_dcs_write_1(ix, DCS_TEAR_ON, 0);
 	else
-		r = taal_dcs_write_0(DCS_TEAR_OFF);
+		r = taal_dcs_write_0(ix, DCS_TEAR_OFF);
 
 	omapdss_dsi_enable_te(dssdev, enable);
 
@@ -861,13 +1035,19 @@ static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable)
 
 static int taal_enable_te(struct omap_dss_device *dssdev, bool enable)
 {
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
-	dsi_bus_lock();
+	mutex_lock(&td->lock);
+	dsi_bus_lock(ix);
 
 	r = _taal_enable_te(dssdev, enable);
 
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 
 	return r;
 }
@@ -875,89 +1055,126 @@ static int taal_enable_te(struct omap_dss_device *dssdev, bool enable)
 static int taal_get_te(struct omap_dss_device *dssdev)
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
-	return td->te_enabled;
+	int r;
+
+	mutex_lock(&td->lock);
+	r = td->te_enabled;
+	mutex_unlock(&td->lock);
+
+	return r;
 }
 
 static int taal_rotate(struct omap_dss_device *dssdev, u8 rotate)
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	dev_dbg(&dssdev->dev, "rotate %d\n", rotate);
 
-	dsi_bus_lock();
+	mutex_lock(&td->lock);
+	dsi_bus_lock(ix);
 
 	if (td->enabled) {
-		r = taal_set_addr_mode(rotate, td->mirror);
+		r = taal_set_addr_mode(ix, rotate, td->mirror);
 		if (r)
 			goto err;
 	}
 
 	td->rotate = rotate;
 
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 	return 0;
 err:
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 	return r;
 }
 
 static u8 taal_get_rotate(struct omap_dss_device *dssdev)
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
-	return td->rotate;
+	int r;
+
+	mutex_lock(&td->lock);
+	r = td->rotate;
+	mutex_unlock(&td->lock);
+
+	return r;
 }
 
 static int taal_mirror(struct omap_dss_device *dssdev, bool enable)
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	dev_dbg(&dssdev->dev, "mirror %d\n", enable);
 
-	dsi_bus_lock();
+	mutex_lock(&td->lock);
+	dsi_bus_lock(ix);
 	if (td->enabled) {
-		r = taal_set_addr_mode(td->rotate, enable);
+		r = taal_set_addr_mode(ix, td->rotate, enable);
 		if (r)
 			goto err;
 	}
 
 	td->mirror = enable;
 
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 	return 0;
 err:
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 	return r;
 }
 
 static bool taal_get_mirror(struct omap_dss_device *dssdev)
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
-	return td->mirror;
+	int r;
+
+	mutex_lock(&td->lock);
+	r = td->mirror;
+	mutex_unlock(&td->lock);
+
+	return r;
 }
 
 static int taal_run_test(struct omap_dss_device *dssdev, int test_num)
 {
+	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
 	u8 id1, id2, id3;
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
-	dsi_bus_lock();
+	mutex_lock(&td->lock);
+	dsi_bus_lock(ix);
 
-	r = taal_dcs_read_1(DCS_GET_ID1, &id1);
+	r = taal_dcs_read_1(ix, DCS_GET_ID1, &id1);
 	if (r)
 		goto err;
-	r = taal_dcs_read_1(DCS_GET_ID2, &id2);
+	r = taal_dcs_read_1(ix, DCS_GET_ID2, &id2);
 	if (r)
 		goto err;
-	r = taal_dcs_read_1(DCS_GET_ID3, &id3);
+	r = taal_dcs_read_1(ix, DCS_GET_ID3, &id3);
 	if (r)
 		goto err;
 
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 	return 0;
 err:
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
+	mutex_unlock(&td->lock);
 	return r;
 }
 
@@ -970,18 +1187,25 @@ static int taal_memory_read(struct omap_dss_device *dssdev,
 	int plen;
 	unsigned buf_used = 0;
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+	enum omap_dsi_index ix;
 
-	if (!td->enabled)
-		return -ENODEV;
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	if (size < w * h * 3)
 		return -ENOMEM;
 
+	mutex_lock(&td->lock);
+
+	if (!td->enabled) {
+		r = -ENODEV;
+		goto err1;
+	}
+
 	size = min(w * h * 3,
 			dssdev->panel.timings.x_res *
 			dssdev->panel.timings.y_res * 3);
 
-	dsi_bus_lock();
+	dsi_bus_lock(ix);
 
 	/* plen 1 or 2 goes into short packet. until checksum error is fixed,
 	 * use short packets. plen 32 works, but bigger packets seem to cause
@@ -991,22 +1215,22 @@ static int taal_memory_read(struct omap_dss_device *dssdev,
 	else
 		plen = 2;
 
-	taal_set_update_window(x, y, w, h);
+	taal_set_update_window(ix, x, y, w, h);
 
-	r = dsi_vc_set_max_rx_packet_size(TCH, plen);
+	r = dsi_vc_set_max_rx_packet_size(ix, TCH, plen);
 	if (r)
-		goto err0;
+		goto err2;
 
 	while (buf_used < size) {
 		u8 dcs_cmd = first ? 0x2e : 0x3e;
 		first = 0;
 
-		r = dsi_vc_dcs_read(TCH, dcs_cmd,
+		r = dsi_vc_dcs_read(ix, TCH, dcs_cmd,
 				buf + buf_used, size - buf_used);
 
 		if (r < 0) {
 			dev_err(&dssdev->dev, "read error\n");
-			goto err;
+			goto err3;
 		}
 
 		buf_used += r;
@@ -1020,16 +1244,18 @@ static int taal_memory_read(struct omap_dss_device *dssdev,
 			dev_err(&dssdev->dev, "signal pending, "
 					"aborting memory read\n");
 			r = -ERESTARTSYS;
-			goto err;
+			goto err3;
 		}
 	}
 
 	r = buf_used;
 
-err:
-	dsi_vc_set_max_rx_packet_size(TCH, 1);
-err0:
-	dsi_bus_unlock();
+err3:
+	dsi_vc_set_max_rx_packet_size(ix, TCH, 1);
+err2:
+	dsi_bus_unlock(ix);
+err1:
+	mutex_unlock(&td->lock);
 	return r;
 }
 
@@ -1040,26 +1266,32 @@ static void taal_esd_work(struct work_struct *work)
 	struct omap_dss_device *dssdev = td->dssdev;
 	u8 state1, state2;
 	int r;
+	enum omap_dsi_index ix;
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
-	if (!td->enabled)
+	mutex_lock(&td->lock);
+
+	if (!td->enabled) {
+		mutex_unlock(&td->lock);
 		return;
+	}
 
-	dsi_bus_lock();
+	dsi_bus_lock(ix);
 
-	r = taal_dcs_read_1(DCS_RDDSDR, &state1);
+	r = taal_dcs_read_1(ix, DCS_RDDSDR, &state1);
 	if (r) {
 		dev_err(&dssdev->dev, "failed to read Taal status\n");
 		goto err;
 	}
 
 	/* Run self diagnostics */
-	r = taal_sleep_out(td);
+	r = taal_sleep_out(ix, td);
 	if (r) {
 		dev_err(&dssdev->dev, "failed to run Taal self-diagnostics\n");
 		goto err;
 	}
 
-	r = taal_dcs_read_1(DCS_RDDSDR, &state2);
+	r = taal_dcs_read_1(ix, DCS_RDDSDR, &state2);
 	if (r) {
 		dev_err(&dssdev->dev, "failed to read Taal status\n");
 		goto err;
@@ -1075,31 +1307,34 @@ static void taal_esd_work(struct work_struct *work)
 	/* Self-diagnostics result is also shown on TE GPIO line. We need
 	 * to re-enable TE after self diagnostics */
 	if (td->use_ext_te && td->te_enabled) {
-		r = taal_dcs_write_1(DCS_TEAR_ON, 0);
+		r = taal_dcs_write_1(ix, DCS_TEAR_ON, 0);
 		if (r)
 			goto err;
 	}
 
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
 
 	queue_delayed_work(td->esd_wq, &td->esd_work, TAAL_ESD_CHECK_PERIOD);
 
+	mutex_unlock(&td->lock);
 	return;
 err:
 	dev_err(&dssdev->dev, "performing LCD reset\n");
 
-	taal_disable(dssdev);
-	taal_enable(dssdev);
+	taal_power_off(dssdev);
+	taal_power_on(dssdev);
 
-	dsi_bus_unlock();
+	dsi_bus_unlock(ix);
 
 	queue_delayed_work(td->esd_wq, &td->esd_work, TAAL_ESD_CHECK_PERIOD);
+
+	mutex_unlock(&td->lock);
 }
 
 static int taal_set_update_mode(struct omap_dss_device *dssdev,
 		enum omap_dss_update_mode mode)
 {
-	if (mode != OMAP_DSS_UPDATE_MANUAL)
+	if (mode != OMAP_DSS_UPDATE_AUTO)
 		return -EINVAL;
 	return 0;
 }
@@ -1107,7 +1342,7 @@ static int taal_set_update_mode(struct omap_dss_device *dssdev,
 static enum omap_dss_update_mode taal_get_update_mode(
 		struct omap_dss_device *dssdev)
 {
-	return OMAP_DSS_UPDATE_MANUAL;
+	return OMAP_DSS_UPDATE_AUTO;
 }
 
 static struct omap_dss_driver taal_driver = {
@@ -1130,7 +1365,7 @@ static struct omap_dss_driver taal_driver = {
 
 	.enable_te	= taal_enable_te,
 	.get_te		= taal_get_te,
-
+	.wait_for_te	= taal_wait_te,
 	.set_rotate	= taal_rotate,
 	.get_rotate	= taal_get_rotate,
 	.set_mirror	= taal_mirror,
@@ -1146,9 +1381,48 @@ static struct omap_dss_driver taal_driver = {
 	},
 };
 
+static struct omap_dss_driver taal2_driver = {
+	.probe		= taal_probe,
+	.remove		= taal_remove,
+
+	.enable		= taal_enable,
+	.disable	= taal_disable,
+	.suspend	= taal_suspend,
+	.resume		= taal_resume,
+
+	.set_update_mode = taal_set_update_mode,
+	.get_update_mode = taal_get_update_mode,
+
+	.update		= taal_update,
+	.sync		= taal_sync,
+
+	.get_resolution	= taal_get_resolution,
+	.get_recommended_bpp = omapdss_default_get_recommended_bpp,
+
+	.enable_te	= taal_enable_te,
+	.get_te		= taal_get_te,
+	.wait_for_te	= taal_wait_te,
+	.set_rotate	= taal_rotate,
+	.get_rotate	= taal_get_rotate,
+	.set_mirror	= taal_mirror,
+	.get_mirror	= taal_get_mirror,
+	.run_test	= taal_run_test,
+	.memory_read	= taal_memory_read,
+
+	.get_timings	= taal_get_timings,
+
+	.driver         = {
+		.name   = "taal2",
+		.owner  = THIS_MODULE,
+	},
+};
+
+
 static int __init taal_init(void)
 {
 	omap_dss_register_driver(&taal_driver);
+	if (cpu_is_omap44xx())
+		omap_dss_register_driver(&taal2_driver);
 
 	return 0;
 }
@@ -1156,6 +1430,8 @@ static int __init taal_init(void)
 static void __exit taal_exit(void)
 {
 	omap_dss_unregister_driver(&taal_driver);
+	if (cpu_is_omap44xx())
+		omap_dss_unregister_driver(&taal2_driver);
 }
 
 module_init(taal_init);
diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
index 87afb81b2c44..810586c56968 100644
--- a/drivers/video/omap2/dss/Kconfig
+++ b/drivers/video/omap2/dss/Kconfig
@@ -1,8 +1,8 @@
 menuconfig OMAP2_DSS
-        tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
+        tristate "OMAP2/3/4 Display Subsystem support (EXPERIMENTAL)"
+        depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
         help
-          OMAP2/3 Display Subsystem support.
+          OMAP2/3/4 Display Subsystem support.
 
 if OMAP2_DSS
 
@@ -36,6 +36,12 @@ config OMAP2_DSS_COLLECT_IRQ_STATS
 	  <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
 	  <debugfs>/omapdss/dsi_irq for DSI interrupts.
 
+config OMAP2_DSS_DPI
+	bool "DPI support"
+	default y
+	help
+	  DPI Interface. This is the Parallel Display Interface.
+
 config OMAP2_DSS_RFBI
 	bool "RFBI support"
         default n
@@ -54,6 +60,12 @@ config OMAP2_DSS_VENC
 	help
 	  OMAP Video Encoder support for S-Video and composite TV-out.
 
+config OMAP2_DSS_HDMI
+	bool "HDMI support"
+        default n
+	help
+	  OMAP HDMI panel support.
+
 config OMAP2_DSS_SDI
 	bool "SDI support"
 	depends on ARCH_OMAP3
@@ -66,7 +78,7 @@ config OMAP2_DSS_SDI
 
 config OMAP2_DSS_DSI
 	bool "DSI support"
-	depends on ARCH_OMAP3
+	depends on ARCH_OMAP3 || ARCH_OMAP4
         default n
 	help
 	  MIPI DSI (Display Serial Interface) support.
diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
index 980c72c2db98..c1dd777e9727 100644
--- a/drivers/video/omap2/dss/Makefile
+++ b/drivers/video/omap2/dss/Makefile
@@ -1,6 +1,8 @@
 obj-$(CONFIG_OMAP2_DSS) += omapdss.o
-omapdss-y := core.o dss.o dispc.o dpi.o display.o manager.o overlay.o
+omapdss-y := core.o dss.o dispc.o display.o manager.o overlay.o wb.o
+omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o
 omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
 omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
 omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
 omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
+omapdss-$(CONFIG_OMAP2_DSS_HDMI) += hdmi.o
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index 7ebe50b335ed..ed9f76912ae9 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -68,6 +68,11 @@ unsigned int dss_debug;
 module_param_named(debug, dss_debug, bool, 0644);
 #endif
 
+static int hdmi_code = 16;
+static int hdmi_mode = 1;
+module_param_named(hdmicode, hdmi_code, int, 0644);
+module_param_named(hdmimode, hdmi_mode, int, 0644);
+
 /* CONTEXT */
 static int dss_get_ctx_id(void)
 {
@@ -224,16 +229,19 @@ err:
 
 static void dss_put_clocks(void)
 {
+#if 0
 	if (core.dss_96m_fck)
 		clk_put(core.dss_96m_fck);
 	clk_put(core.dss_54m_fck);
 	clk_put(core.dss1_fck);
 	clk_put(core.dss2_fck);
 	clk_put(core.dss_ick);
+#endif
 }
 
 unsigned long dss_clk_get_rate(enum dss_clock clk)
 {
+#if 0
 	switch (clk) {
 	case DSS_CLK_ICK:
 		return clk_get_rate(core.dss_ick);
@@ -248,7 +256,8 @@ unsigned long dss_clk_get_rate(enum dss_clock clk)
 	}
 
 	BUG();
-	return 0;
+#endif
+	return 153600000;
 }
 
 static unsigned count_clk_bits(enum dss_clock clks)
@@ -272,7 +281,7 @@ static unsigned count_clk_bits(enum dss_clock clks)
 static void dss_clk_enable_no_ctx(enum dss_clock clks)
 {
 	unsigned num_clks = count_clk_bits(clks);
-
+#if 0
 	if (clks & DSS_CLK_ICK)
 		clk_enable(core.dss_ick);
 	if (clks & DSS_CLK_FCK1)
@@ -283,7 +292,7 @@ static void dss_clk_enable_no_ctx(enum dss_clock clks)
 		clk_enable(core.dss_54m_fck);
 	if (clks & DSS_CLK_96M)
 		clk_enable(core.dss_96m_fck);
-
+#endif
 	core.num_clks_enabled += num_clks;
 }
 
@@ -300,7 +309,7 @@ void dss_clk_enable(enum dss_clock clks)
 static void dss_clk_disable_no_ctx(enum dss_clock clks)
 {
 	unsigned num_clks = count_clk_bits(clks);
-
+#if 0
 	if (clks & DSS_CLK_ICK)
 		clk_disable(core.dss_ick);
 	if (clks & DSS_CLK_FCK1)
@@ -311,7 +320,7 @@ static void dss_clk_disable_no_ctx(enum dss_clock clks)
 		clk_disable(core.dss_54m_fck);
 	if (clks & DSS_CLK_96M)
 		clk_disable(core.dss_96m_fck);
-
+#endif
 	core.num_clks_enabled -= num_clks;
 }
 
@@ -411,7 +420,8 @@ static void dss_debug_dump_clocks(struct seq_file *s)
 	dss_dump_clocks(s);
 	dispc_dump_clocks(s);
 #ifdef CONFIG_OMAP2_DSS_DSI
-	dsi_dump_clocks(s);
+	dsi_dump_clocks(DSI1, s);
+	dsi_dump_clocks(DSI2, s);
 #endif
 }
 
@@ -489,7 +499,7 @@ static int omap_dss_probe(struct platform_device *pdev)
 {
 	struct omap_dss_board_info *pdata = pdev->dev.platform_data;
 	int skip_init = 0;
-	int r;
+	int r = 0;
 	int i;
 
 	core.pdev = pdev;
@@ -497,6 +507,10 @@ static int omap_dss_probe(struct platform_device *pdev)
 	dss_init_overlay_managers(pdev);
 	dss_init_overlays(pdev);
 
+	if (cpu_is_omap44xx())
+		dss_init_writeback(pdev); /*Write back init*/
+
+	if (!cpu_is_omap44xx())
 	r = dss_get_clocks();
 	if (r)
 		goto fail0;
@@ -526,11 +540,13 @@ static int omap_dss_probe(struct platform_device *pdev)
 	}
 #endif
 
+#ifdef CONFIG_OMAP2_DSS_DPI
 	r = dpi_init(pdev);
 	if (r) {
 		DSSERR("Failed to initialize dpi\n");
 		goto fail0;
 	}
+#endif
 
 	r = dispc_init();
 	if (r) {
@@ -552,15 +568,31 @@ static int omap_dss_probe(struct platform_device *pdev)
 			goto fail0;
 		}
 #endif
+	}
+	if (!cpu_is_omap24xx()) {
 #ifdef CONFIG_OMAP2_DSS_DSI
 		r = dsi_init(pdev);
 		if (r) {
 			DSSERR("Failed to initialize DSI\n");
 			goto fail0;
 		}
+		if (cpu_is_omap44xx()) {
+			r = dsi2_init(pdev);
+			if (r) {
+				DSSERR("Failed to initialize DSI2\n");
+				goto fail0;
+			}
+		}
 #endif
 	}
 
+#ifdef CONFIG_OMAP2_DSS_HDMI
+	r = hdmi_init(pdev, hdmi_code, hdmi_mode);
+	if (r) {
+		DSSERR("Failed to initialize hdmi\n");
+		goto fail0;
+	}
+#endif
 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 	r = dss_initialize_debugfs();
 	if (r)
@@ -600,17 +632,25 @@ static int omap_dss_remove(struct platform_device *pdev)
 #ifdef CONFIG_OMAP2_DSS_VENC
 	venc_exit();
 #endif
+#ifdef CONFIG_OMAP2_DSS_HDMI
+	hdmi_exit();
+#endif
 	dispc_exit();
+#ifdef CONFIG_OMAP2_DSS_DPI
 	dpi_exit();
+#endif
 #ifdef CONFIG_OMAP2_DSS_RFBI
 	rfbi_exit();
 #endif
-	if (cpu_is_omap34xx()) {
+	if (!cpu_is_omap24xx()) {
 #ifdef CONFIG_OMAP2_DSS_DSI
 		dsi_exit();
+		if (cpu_is_omap44xx())
+			dsi2_exit();
 #endif
 #ifdef CONFIG_OMAP2_DSS_SDI
-		sdi_exit();
+		if (cpu_is_omap34xx())
+			sdi_exit();
 #endif
 	}
 
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index e777e352dbcd..6ac09c3cfbc5 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -38,14 +38,18 @@
 #include <plat/display.h>
 
 #include "dss.h"
+#include <mach/tiler.h>
 
-/* DISPC */
-#define DISPC_BASE			0x48050400
+#ifndef CONFIG_ARCH_OMAP4
+#define DISPC_BASE		0x48050400
+#else
+#define DISPC_BASE		0x58001000
+#endif
 
-#define DISPC_SZ_REGS			SZ_1K
+#define DISPC_SZ_REGS			SZ_16K
 
 struct dispc_reg { u16 idx; };
-
+extern void __iomem  *dispc_base;
 #define DISPC_REG(idx)			((const struct dispc_reg) { idx })
 
 /* DISPC common */
@@ -67,9 +71,11 @@ struct dispc_reg { u16 idx; };
 #define DISPC_TIMING_V			DISPC_REG(0x0068)
 #define DISPC_POL_FREQ			DISPC_REG(0x006C)
 #define DISPC_DIVISOR			DISPC_REG(0x0070)
+#define DISPC_DIVISOR1			DISPC_REG(0x0804)
 #define DISPC_GLOBAL_ALPHA		DISPC_REG(0x0074)
 #define DISPC_SIZE_DIG			DISPC_REG(0x0078)
 #define DISPC_SIZE_LCD			DISPC_REG(0x007C)
+#define DISPC_GLOBAL_BUFFER		DISPC_REG(0x0800)
 
 /* DISPC GFX plane */
 #define DISPC_GFX_BA0			DISPC_REG(0x0080)
@@ -130,6 +136,118 @@ struct dispc_reg { u16 idx; };
 					 DISPC_IRQ_SYNC_LOST | \
 					 DISPC_IRQ_SYNC_LOST_DIGIT)
 
+#define DISPC_CONTROL2			 DISPC_REG(0x0238)
+
+/******** registers related to VID3 and WB pipelines ****/
+/* DISPC Video plane, n = 0 for VID3, n = 1 for WB _VID_V3_WB_ */
+#define DISPC_VID_V3_WB_REG(n, idx) DISPC_REG(0x0300 + (n)*0x200 + idx)
+
+#define DISPC_VID_V3_WB_ACCU0(n)	       DISPC_VID_V3_WB_REG(n, 0x0000)
+#define DISPC_VID_V3_WB_ACCU1(n)	       DISPC_VID_V3_WB_REG(n, 0x0004)
+
+#define DISPC_VID_V3_WB_BA0(n)	 DISPC_VID_V3_WB_REG(n, 0x0008)
+#define DISPC_VID_V3_WB_BA1(n)	 DISPC_VID_V3_WB_REG(n, 0x000C)
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+#define DISPC_VID_V3_WB_FIR_COEF_H(n, i) DISPC_REG(0x0310+(n)*0x200+(i)*0x8)
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+#define DISPC_VID_V3_WB_FIR_COEF_HV(n, i) DISPC_REG(0x0314+(n)*0x200+(i)*0x8)
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+#define DISPC_VID_V3_WB_FIR_COEF_V(n, i) DISPC_REG(0x0350+(n)*0x200+(i)*0x4)
+
+#define DISPC_VID_V3_WB_ATTRIBUTES(n)	  DISPC_VID_V3_WB_REG(n, 0x0070)
+
+/* coef index i = {0, 1, 2, 3, 4} */
+#define DISPC_VID_V3_WB_CONV_COEF(n, i)	DISPC_REG(0x0374 + (n)*0x200 + (i)*0x4)
+
+#define DISPC_VID_V3_WB_BUF_SIZE_STATUS(n)     DISPC_VID_V3_WB_REG(n, 0x0088)
+#define DISPC_VID_V3_WB_BUF_THRESHOLD(n)       DISPC_VID_V3_WB_REG(n, 0x008C)
+#define DISPC_VID_V3_WB_FIR(n)	 DISPC_VID_V3_WB_REG(n, 0x0090)
+#define DISPC_VID_V3_WB_PICTURE_SIZE(n)	DISPC_VID_V3_WB_REG(n, 0x0094)
+#define DISPC_VID_V3_WB_PIXEL_INC(n)	   DISPC_VID_V3_WB_REG(n, 0x0098)
+
+#define DISPC_VID_VID3_POSITION		DISPC_REG(0x039C)
+#define DISPC_VID_VID3_PRELOAD	 DISPC_REG(0x03A0)
+
+
+#define DISPC_VID_V3_WB_ROW_INC(n)	     DISPC_VID_V3_WB_REG(n, 0x00A4)
+#define DISPC_VID_V3_WB_SIZE(n)		DISPC_VID_V3_WB_REG(n, 0x00A8)
+
+#define DISPC_VID_V3_WB_FIR2(n)		DISPC_REG(0x0724 + (n)*0x6C)
+				       /* n=0: VID3, n=1: WB*/
+
+#define DISPC_VID_V3_WB_ACCU2_0(n)     DISPC_REG(0x0728 + (n)*0x6C)
+				       /* n=0: VID3, n=1: WB*/
+#define DISPC_VID_V3_WB_ACCU2_1(n)     DISPC_REG(0x072C + (n)*0x6C)
+				       /* n=0: VID3, n=1: WB*/
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7}  n=0: VID3, n=1: WB */
+#define DISPC_VID_V3_WB_FIR_COEF_H2(n, i) DISPC_REG(0x0730+(n)*0x6C+(i)*0x8)
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+#define DISPC_VID_V3_WB_FIR_COEF_HV2(n, i) DISPC_REG(0x0734+(n)*0x6C+(i)*0x8)
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+#define DISPC_VID_V3_WB_FIR_COEF_V2(n, i) DISPC_REG(0x0770+(n)*0x6C+(i)*0x4)
+
+
+/*********End Vid3 and WB Registers ***************/
+
+/********** OMAP4 new global registers  **/
+#define DISPC_DEFAULT_COLOR2	   DISPC_REG(0x03AC)
+#define DISPC_TRANS_COLOR2		     DISPC_REG(0x03B0)
+#define DISPC_CPR2_COEF_B		      DISPC_REG(0x03B4)
+#define DISPC_CPR2_COEF_G		      DISPC_REG(0x03B8)
+#define DISPC_CPR2_COEF_R		      DISPC_REG(0x03BC)
+#define DISPC_DATA2_CYCLE1		     DISPC_REG(0x03C0)
+#define DISPC_DATA2_CYCLE2		     DISPC_REG(0x03C4)
+#define DISPC_DATA2_CYCLE3		     DISPC_REG(0x03C8)
+#define DISPC_SIZE_LCD2				DISPC_REG(0x03CC)
+#define DISPC_TIMING_H2				DISPC_REG(0x0400)
+#define DISPC_TIMING_V2				DISPC_REG(0x0404)
+#define DISPC_POL_FREQ2				DISPC_REG(0x0408)
+#define DISPC_DIVISOR2			 DISPC_REG(0x040C)
+/* DISPC Video plane,
+	       n = 0 for VID1
+	       n = 1 for VID2
+	       and n = 2 for VID3,
+	       n = 3 for WB*/
+
+#define DISPC_VID_OMAP4_REG(n, idx) DISPC_REG(0x0600 + (n)*0x04 + idx)
+
+#define DISPC_VID_BA_UV0(n)	    DISPC_VID_OMAP4_REG((n)*2, 0x0000)
+#define DISPC_VID_BA_UV1(n)	    DISPC_VID_OMAP4_REG((n)*2, 0x0004)
+
+#define DISPC_CONFIG2		  DISPC_REG(0x0620)
+
+#define DISPC_VID_ATTRIBUTES2(n)       DISPC_VID_OMAP4_REG(n, 0x0024)
+				       /* n = {0,1,2,3} */
+#define DISPC_GAMMA_TABLE(n)	   DISPC_VID_OMAP4_REG(n, 0x0030)
+				       /* n = {0,1,2,3} */
+
+/* VID1/VID2 specific new registers */
+#define DISPC_VID_FIR2(n)	      DISPC_REG(0x063C + (n)*0x6C)
+				       /* n=0: VID1, n=1: VID2*/
+
+#define DISPC_VID_ACCU2_0(n)	   DISPC_REG(0x0640 + (n)*0x6C)
+				       /* n=0: VID1, n=1: VID2*/
+#define DISPC_VID_ACCU2_1(n)	   DISPC_REG(0x0644 + (n)*0x6C)
+				       /* n=0: VID1, n=1: VID2*/
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7}  n=0: VID1, n=1: VID2 */
+#define DISPC_VID_FIR_COEF_H2(n, i)    DISPC_REG(0x0648 + (n)*0x6C + (i)*0x8)
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+#define DISPC_VID_FIR_COEF_HV2(n, i)   DISPC_REG(0x064C + (n)*0x6C + (i)*0x8)
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+#define DISPC_VID_FIR_COEF_V2(n, i)    DISPC_REG(0x0688 + (n)*0x6C + (i)*0x4)
+/*end of VID1/VID2 specific new registers*/
+
+
+
 #define DISPC_MAX_NR_ISRS		8
 
 struct omap_dispc_isr_data {
@@ -146,7 +264,10 @@ struct omap_dispc_isr_data {
 
 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 	DISPC_VID_ATTRIBUTES(0),
-	DISPC_VID_ATTRIBUTES(1) };
+	DISPC_VID_ATTRIBUTES(1),
+	DISPC_VID_V3_WB_ATTRIBUTES(0), /* VID 3 pipeline */
+	DISPC_VID_V3_WB_ATTRIBUTES(1)};/* WB pipeline */
+
 
 struct dispc_irq_stats {
 	unsigned long last_reset;
@@ -185,6 +306,28 @@ static inline u32 dispc_read_reg(const struct dispc_reg idx)
 	return __raw_readl(dispc.base + idx.idx);
 }
 
+static inline u8 calc_tiler_orientation(u8 rotation, u8 mir)
+{
+	static u8 orientation;
+	switch (rotation) {
+	case 0:
+		orientation = (mir ? 0x2 : 0x0);
+		break;
+	case 1:
+		orientation = (mir ? 0x7 : 0x6);
+		break;
+	case 2:
+		orientation = (mir ? 0x1 : 0x3);
+		break;
+	case 3:
+		orientation = (mir ? 0x4 : 0x5);
+		break;
+	}
+	return orientation;
+}
+
+
+
 #define SR(reg) \
 	dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 #define RR(reg) \
@@ -233,6 +376,214 @@ void dispc_save_context(void)
 
 	SR(GFX_PRELOAD);
 
+	if (cpu_is_omap44xx()) {
+		SR(DIVISOR1);
+	SR(GLOBAL_BUFFER);
+	SR(CONTROL2);
+	SR(DEFAULT_COLOR2);
+	SR(TRANS_COLOR2);
+	SR(CPR2_COEF_B);
+	SR(CPR2_COEF_G);
+	SR(CPR2_COEF_R);
+	SR(DATA2_CYCLE1);
+	SR(DATA2_CYCLE2);
+	SR(DATA2_CYCLE3);
+	SR(SIZE_LCD2);
+	SR(TIMING_H2);
+	SR(TIMING_V2);
+	SR(POL_FREQ2);
+	SR(DIVISOR2);
+
+	SR(CONFIG2);
+
+	/**** VID3 ****/;
+
+	SR(VID_V3_WB_ACCU0(0));
+	SR(VID_V3_WB_ACCU1(0));
+	SR(VID_V3_WB_BA0(0));
+	SR(VID_V3_WB_BA1(0));
+
+	SR(VID_V3_WB_FIR_COEF_H(0, 0));
+	SR(VID_V3_WB_FIR_COEF_H(0, 1));
+	SR(VID_V3_WB_FIR_COEF_H(0, 2));
+	SR(VID_V3_WB_FIR_COEF_H(0, 3));
+	SR(VID_V3_WB_FIR_COEF_H(0, 4));
+	SR(VID_V3_WB_FIR_COEF_H(0, 5));
+	SR(VID_V3_WB_FIR_COEF_H(0, 6));
+	SR(VID_V3_WB_FIR_COEF_H(0, 7));
+
+	SR(VID_V3_WB_FIR_COEF_HV(0, 0));
+	SR(VID_V3_WB_FIR_COEF_HV(0, 1));
+	SR(VID_V3_WB_FIR_COEF_HV(0, 2));
+	SR(VID_V3_WB_FIR_COEF_HV(0, 3));
+	SR(VID_V3_WB_FIR_COEF_HV(0, 4));
+	SR(VID_V3_WB_FIR_COEF_HV(0, 5));
+	SR(VID_V3_WB_FIR_COEF_HV(0, 6));
+	SR(VID_V3_WB_FIR_COEF_HV(0, 7));
+
+	SR(VID_V3_WB_FIR_COEF_V(0, 0));
+	SR(VID_V3_WB_FIR_COEF_V(0, 1));
+	SR(VID_V3_WB_FIR_COEF_V(0, 2));
+	SR(VID_V3_WB_FIR_COEF_V(0, 3));
+	SR(VID_V3_WB_FIR_COEF_V(0, 4));
+	SR(VID_V3_WB_FIR_COEF_V(0, 5));
+	SR(VID_V3_WB_FIR_COEF_V(0, 6));
+	SR(VID_V3_WB_FIR_COEF_V(0, 7));
+
+	SR(VID_V3_WB_ATTRIBUTES(0));
+	SR(VID_V3_WB_CONV_COEF(0, 0));
+	SR(VID_V3_WB_CONV_COEF(0, 1));
+	SR(VID_V3_WB_CONV_COEF(0, 2));
+	SR(VID_V3_WB_CONV_COEF(0, 3));
+	SR(VID_V3_WB_CONV_COEF(0, 4));
+	SR(VID_V3_WB_CONV_COEF(0, 5));
+	SR(VID_V3_WB_CONV_COEF(0, 6));
+	SR(VID_V3_WB_CONV_COEF(0, 7));
+
+	SR(VID_V3_WB_BUF_SIZE_STATUS(0));
+	SR(VID_V3_WB_BUF_THRESHOLD(0));
+	SR(VID_V3_WB_FIR(0));
+	SR(VID_V3_WB_PICTURE_SIZE(0));
+	SR(VID_V3_WB_PIXEL_INC(0));
+	SR(VID_VID3_POSITION);
+	SR(VID_VID3_PRELOAD);
+
+	SR(VID_V3_WB_ROW_INC(0));
+	SR(VID_V3_WB_SIZE(0));
+	SR(VID_V3_WB_FIR2(0));
+	SR(VID_V3_WB_ACCU2_0(0));
+	SR(VID_V3_WB_ACCU2_1(0));
+
+	SR(VID_V3_WB_FIR_COEF_H2(0, 0));
+	SR(VID_V3_WB_FIR_COEF_H2(0, 1));
+	SR(VID_V3_WB_FIR_COEF_H2(0, 2));
+	SR(VID_V3_WB_FIR_COEF_H2(0, 3));
+	SR(VID_V3_WB_FIR_COEF_H2(0, 4));
+	SR(VID_V3_WB_FIR_COEF_H2(0, 5));
+	SR(VID_V3_WB_FIR_COEF_H2(0, 6));
+	SR(VID_V3_WB_FIR_COEF_H2(0, 7));
+
+	SR(VID_V3_WB_FIR_COEF_HV2(0, 0));
+	SR(VID_V3_WB_FIR_COEF_HV2(0, 1));
+	SR(VID_V3_WB_FIR_COEF_HV2(0, 2));
+	SR(VID_V3_WB_FIR_COEF_HV2(0, 3));
+	SR(VID_V3_WB_FIR_COEF_HV2(0, 4));
+	SR(VID_V3_WB_FIR_COEF_HV2(0, 5));
+	SR(VID_V3_WB_FIR_COEF_HV2(0, 6));
+	SR(VID_V3_WB_FIR_COEF_HV2(0, 7));
+
+	SR(VID_V3_WB_FIR_COEF_V2(0, 0));
+	SR(VID_V3_WB_FIR_COEF_V2(0, 1));
+	SR(VID_V3_WB_FIR_COEF_V2(0, 2));
+	SR(VID_V3_WB_FIR_COEF_V2(0, 3));
+	SR(VID_V3_WB_FIR_COEF_V2(0, 4));
+	SR(VID_V3_WB_FIR_COEF_V2(0, 5));
+	SR(VID_V3_WB_FIR_COEF_V2(0, 6));
+	SR(VID_V3_WB_FIR_COEF_V2(0, 7));
+
+	/******* WB Registers *********/;
+
+	SR(VID_V3_WB_ACCU0(1));
+	SR(VID_V3_WB_ACCU1(1));
+	SR(VID_V3_WB_BA0(1));
+	SR(VID_V3_WB_BA1(1));
+
+	SR(VID_V3_WB_FIR_COEF_H(1, 0));
+	SR(VID_V3_WB_FIR_COEF_H(1, 1));
+	SR(VID_V3_WB_FIR_COEF_H(1, 2));
+	SR(VID_V3_WB_FIR_COEF_H(1, 3));
+	SR(VID_V3_WB_FIR_COEF_H(1, 4));
+	SR(VID_V3_WB_FIR_COEF_H(1, 5));
+	SR(VID_V3_WB_FIR_COEF_H(1, 6));
+	SR(VID_V3_WB_FIR_COEF_H(1, 7));
+
+	SR(VID_V3_WB_FIR_COEF_HV(1, 0));
+	SR(VID_V3_WB_FIR_COEF_HV(1, 1));
+	SR(VID_V3_WB_FIR_COEF_HV(1, 2));
+	SR(VID_V3_WB_FIR_COEF_HV(1, 3));
+	SR(VID_V3_WB_FIR_COEF_HV(1, 4));
+	SR(VID_V3_WB_FIR_COEF_HV(1, 5));
+	SR(VID_V3_WB_FIR_COEF_HV(1, 6));
+	SR(VID_V3_WB_FIR_COEF_HV(1, 7));
+
+	SR(VID_V3_WB_FIR_COEF_V(1, 0));
+	SR(VID_V3_WB_FIR_COEF_V(1, 1));
+	SR(VID_V3_WB_FIR_COEF_V(1, 2));
+	SR(VID_V3_WB_FIR_COEF_V(1, 3));
+	SR(VID_V3_WB_FIR_COEF_V(1, 4));
+	SR(VID_V3_WB_FIR_COEF_V(1, 5));
+	SR(VID_V3_WB_FIR_COEF_V(1, 6));
+	SR(VID_V3_WB_FIR_COEF_V(1, 7));
+
+	SR(VID_V3_WB_ATTRIBUTES(1));
+	SR(VID_V3_WB_CONV_COEF(1, 0));
+	SR(VID_V3_WB_CONV_COEF(1, 1));
+	SR(VID_V3_WB_CONV_COEF(1, 2));
+	SR(VID_V3_WB_CONV_COEF(1, 3));
+	SR(VID_V3_WB_CONV_COEF(1, 4));
+	SR(VID_V3_WB_CONV_COEF(1, 5));
+	SR(VID_V3_WB_CONV_COEF(1, 6));
+	SR(VID_V3_WB_CONV_COEF(1, 7));
+
+	SR(VID_V3_WB_BUF_SIZE_STATUS(1));
+	SR(VID_V3_WB_BUF_THRESHOLD(1));
+	SR(VID_V3_WB_FIR(1));
+	SR(VID_V3_WB_PICTURE_SIZE(1));
+	SR(VID_V3_WB_PIXEL_INC(1));
+	SR(VID_VID3_POSITION);
+	SR(VID_VID3_PRELOAD);
+
+	SR(VID_V3_WB_ROW_INC(1));
+	SR(VID_V3_WB_SIZE(1));
+	SR(VID_V3_WB_FIR2(1));
+	SR(VID_V3_WB_ACCU2_0(1));
+	SR(VID_V3_WB_ACCU2_1(1));
+
+	SR(VID_V3_WB_FIR_COEF_H2(1, 0));
+	SR(VID_V3_WB_FIR_COEF_H2(1, 1));
+	SR(VID_V3_WB_FIR_COEF_H2(1, 2));
+	SR(VID_V3_WB_FIR_COEF_H2(1, 3));
+	SR(VID_V3_WB_FIR_COEF_H2(1, 4));
+	SR(VID_V3_WB_FIR_COEF_H2(1, 5));
+	SR(VID_V3_WB_FIR_COEF_H2(1, 6));
+	SR(VID_V3_WB_FIR_COEF_H2(1, 7));
+
+	SR(VID_V3_WB_FIR_COEF_HV2(1, 0));
+	SR(VID_V3_WB_FIR_COEF_HV2(1, 1));
+	SR(VID_V3_WB_FIR_COEF_HV2(1, 2));
+	SR(VID_V3_WB_FIR_COEF_HV2(1, 3));
+	SR(VID_V3_WB_FIR_COEF_HV2(1, 4));
+	SR(VID_V3_WB_FIR_COEF_HV2(1, 5));
+	SR(VID_V3_WB_FIR_COEF_HV2(1, 6));
+	SR(VID_V3_WB_FIR_COEF_HV2(1, 7));
+
+	SR(VID_V3_WB_FIR_COEF_V2(1, 0));
+	SR(VID_V3_WB_FIR_COEF_V2(1, 1));
+	SR(VID_V3_WB_FIR_COEF_V2(1, 2));
+	SR(VID_V3_WB_FIR_COEF_V2(1, 3));
+	SR(VID_V3_WB_FIR_COEF_V2(1, 4));
+	SR(VID_V3_WB_FIR_COEF_V2(1, 5));
+	SR(VID_V3_WB_FIR_COEF_V2(1, 6));
+	SR(VID_V3_WB_FIR_COEF_V2(1, 7));
+
+	SR(VID_BA_UV0(0));
+	SR(VID_BA_UV0(1));
+
+	SR(VID_BA_UV1(0));
+	SR(VID_BA_UV1(1));
+
+	SR(VID_ATTRIBUTES2(0));
+	SR(VID_ATTRIBUTES2(1));
+	SR(VID_ATTRIBUTES2(2));
+	SR(VID_ATTRIBUTES2(3));
+
+	SR(GAMMA_TABLE(0));
+	SR(GAMMA_TABLE(1));
+	SR(GAMMA_TABLE(2));
+	SR(GAMMA_TABLE(3));
+
+	}
+
 	/* VID1 */
 	SR(VID_BA0(0));
 	SR(VID_BA1(0));
@@ -351,6 +702,214 @@ void dispc_restore_context(void)
 	RR(SIZE_DIG);
 	RR(SIZE_LCD);
 
+	if (cpu_is_omap44xx()) {
+		RR(DIVISOR1);
+	RR(GLOBAL_BUFFER);
+	RR(CONTROL2);
+	RR(DEFAULT_COLOR2);
+	RR(TRANS_COLOR2);
+	RR(CPR2_COEF_B);
+	RR(CPR2_COEF_G);
+	RR(CPR2_COEF_R);
+	RR(DATA2_CYCLE1);
+	RR(DATA2_CYCLE2);
+	RR(DATA2_CYCLE3);
+	RR(SIZE_LCD2);
+	RR(TIMING_H2);
+	RR(TIMING_V2);
+	RR(POL_FREQ2);
+	RR(DIVISOR2);
+
+	RR(CONFIG2);
+
+	/**** VID3 ****/;
+
+	RR(VID_V3_WB_ACCU0(0));
+	RR(VID_V3_WB_ACCU1(0));
+	RR(VID_V3_WB_BA0(0));
+	RR(VID_V3_WB_BA1(0));
+
+	RR(VID_V3_WB_FIR_COEF_H(0, 0));
+	RR(VID_V3_WB_FIR_COEF_H(0, 1));
+	RR(VID_V3_WB_FIR_COEF_H(0, 2));
+	RR(VID_V3_WB_FIR_COEF_H(0, 3));
+	RR(VID_V3_WB_FIR_COEF_H(0, 4));
+	RR(VID_V3_WB_FIR_COEF_H(0, 5));
+	RR(VID_V3_WB_FIR_COEF_H(0, 6));
+	RR(VID_V3_WB_FIR_COEF_H(0, 7));
+
+	RR(VID_V3_WB_FIR_COEF_HV(0, 0));
+	RR(VID_V3_WB_FIR_COEF_HV(0, 1));
+	RR(VID_V3_WB_FIR_COEF_HV(0, 2));
+	RR(VID_V3_WB_FIR_COEF_HV(0, 3));
+	RR(VID_V3_WB_FIR_COEF_HV(0, 4));
+	RR(VID_V3_WB_FIR_COEF_HV(0, 5));
+	RR(VID_V3_WB_FIR_COEF_HV(0, 6));
+	RR(VID_V3_WB_FIR_COEF_HV(0, 7));
+
+	RR(VID_V3_WB_FIR_COEF_V(0, 0));
+	RR(VID_V3_WB_FIR_COEF_V(0, 1));
+	RR(VID_V3_WB_FIR_COEF_V(0, 2));
+	RR(VID_V3_WB_FIR_COEF_V(0, 3));
+	RR(VID_V3_WB_FIR_COEF_V(0, 4));
+	RR(VID_V3_WB_FIR_COEF_V(0, 5));
+	RR(VID_V3_WB_FIR_COEF_V(0, 6));
+	RR(VID_V3_WB_FIR_COEF_V(0, 7));
+
+	RR(VID_V3_WB_ATTRIBUTES(0));
+	RR(VID_V3_WB_CONV_COEF(0, 0));
+	RR(VID_V3_WB_CONV_COEF(0, 1));
+	RR(VID_V3_WB_CONV_COEF(0, 2));
+	RR(VID_V3_WB_CONV_COEF(0, 3));
+	RR(VID_V3_WB_CONV_COEF(0, 4));
+	RR(VID_V3_WB_CONV_COEF(0, 5));
+	RR(VID_V3_WB_CONV_COEF(0, 6));
+	RR(VID_V3_WB_CONV_COEF(0, 7));
+
+	RR(VID_V3_WB_BUF_SIZE_STATUS(0));
+	RR(VID_V3_WB_BUF_THRESHOLD(0));
+	RR(VID_V3_WB_FIR(0));
+	RR(VID_V3_WB_PICTURE_SIZE(0));
+	RR(VID_V3_WB_PIXEL_INC(0));
+	RR(VID_VID3_POSITION);
+	RR(VID_VID3_PRELOAD);
+
+	RR(VID_V3_WB_ROW_INC(0));
+	RR(VID_V3_WB_SIZE(0));
+	RR(VID_V3_WB_FIR2(0));
+	RR(VID_V3_WB_ACCU2_0(0));
+	RR(VID_V3_WB_ACCU2_1(0));
+
+	RR(VID_V3_WB_FIR_COEF_H2(0, 0));
+	RR(VID_V3_WB_FIR_COEF_H2(0, 1));
+	RR(VID_V3_WB_FIR_COEF_H2(0, 2));
+	RR(VID_V3_WB_FIR_COEF_H2(0, 3));
+	RR(VID_V3_WB_FIR_COEF_H2(0, 4));
+	RR(VID_V3_WB_FIR_COEF_H2(0, 5));
+	RR(VID_V3_WB_FIR_COEF_H2(0, 6));
+	RR(VID_V3_WB_FIR_COEF_H2(0, 7));
+
+	RR(VID_V3_WB_FIR_COEF_HV2(0, 0));
+	RR(VID_V3_WB_FIR_COEF_HV2(0, 1));
+	RR(VID_V3_WB_FIR_COEF_HV2(0, 2));
+	RR(VID_V3_WB_FIR_COEF_HV2(0, 3));
+	RR(VID_V3_WB_FIR_COEF_HV2(0, 4));
+	RR(VID_V3_WB_FIR_COEF_HV2(0, 5));
+	RR(VID_V3_WB_FIR_COEF_HV2(0, 6));
+	RR(VID_V3_WB_FIR_COEF_HV2(0, 7));
+
+	RR(VID_V3_WB_FIR_COEF_V2(0, 0));
+	RR(VID_V3_WB_FIR_COEF_V2(0, 1));
+	RR(VID_V3_WB_FIR_COEF_V2(0, 2));
+	RR(VID_V3_WB_FIR_COEF_V2(0, 3));
+	RR(VID_V3_WB_FIR_COEF_V2(0, 4));
+	RR(VID_V3_WB_FIR_COEF_V2(0, 5));
+	RR(VID_V3_WB_FIR_COEF_V2(0, 6));
+	RR(VID_V3_WB_FIR_COEF_V2(0, 7));
+
+	/******* WB Registers *********/;
+
+	RR(VID_V3_WB_ACCU0(1));
+	RR(VID_V3_WB_ACCU1(1));
+	RR(VID_V3_WB_BA0(1));
+	RR(VID_V3_WB_BA1(1));
+
+	RR(VID_V3_WB_FIR_COEF_H(1, 0));
+	RR(VID_V3_WB_FIR_COEF_H(1, 1));
+	RR(VID_V3_WB_FIR_COEF_H(1, 2));
+	RR(VID_V3_WB_FIR_COEF_H(1, 3));
+	RR(VID_V3_WB_FIR_COEF_H(1, 4));
+	RR(VID_V3_WB_FIR_COEF_H(1, 5));
+	RR(VID_V3_WB_FIR_COEF_H(1, 6));
+	RR(VID_V3_WB_FIR_COEF_H(1, 7));
+
+	RR(VID_V3_WB_FIR_COEF_HV(1, 0));
+	RR(VID_V3_WB_FIR_COEF_HV(1, 1));
+	RR(VID_V3_WB_FIR_COEF_HV(1, 2));
+	RR(VID_V3_WB_FIR_COEF_HV(1, 3));
+	RR(VID_V3_WB_FIR_COEF_HV(1, 4));
+	RR(VID_V3_WB_FIR_COEF_HV(1, 5));
+	RR(VID_V3_WB_FIR_COEF_HV(1, 6));
+	RR(VID_V3_WB_FIR_COEF_HV(1, 7));
+
+	RR(VID_V3_WB_FIR_COEF_V(1, 0));
+	RR(VID_V3_WB_FIR_COEF_V(1, 1));
+	RR(VID_V3_WB_FIR_COEF_V(1, 2));
+	RR(VID_V3_WB_FIR_COEF_V(1, 3));
+	RR(VID_V3_WB_FIR_COEF_V(1, 4));
+	RR(VID_V3_WB_FIR_COEF_V(1, 5));
+	RR(VID_V3_WB_FIR_COEF_V(1, 6));
+	RR(VID_V3_WB_FIR_COEF_V(1, 7));
+
+	RR(VID_V3_WB_ATTRIBUTES(1));
+	RR(VID_V3_WB_CONV_COEF(1, 0));
+	RR(VID_V3_WB_CONV_COEF(1, 1));
+	RR(VID_V3_WB_CONV_COEF(1, 2));
+	RR(VID_V3_WB_CONV_COEF(1, 3));
+	RR(VID_V3_WB_CONV_COEF(1, 4));
+	RR(VID_V3_WB_CONV_COEF(1, 5));
+	RR(VID_V3_WB_CONV_COEF(1, 6));
+	RR(VID_V3_WB_CONV_COEF(1, 7));
+
+	RR(VID_V3_WB_BUF_SIZE_STATUS(1));
+	RR(VID_V3_WB_BUF_THRESHOLD(1));
+	RR(VID_V3_WB_FIR(1));
+	RR(VID_V3_WB_PICTURE_SIZE(1));
+	RR(VID_V3_WB_PIXEL_INC(1));
+	RR(VID_VID3_POSITION);
+	RR(VID_VID3_PRELOAD);
+
+	RR(VID_V3_WB_ROW_INC(1));
+	RR(VID_V3_WB_SIZE(1));
+	RR(VID_V3_WB_FIR2(1));
+	RR(VID_V3_WB_ACCU2_0(1));
+	RR(VID_V3_WB_ACCU2_1(1));
+
+	RR(VID_V3_WB_FIR_COEF_H2(1, 0));
+	RR(VID_V3_WB_FIR_COEF_H2(1, 1));
+	RR(VID_V3_WB_FIR_COEF_H2(1, 2));
+	RR(VID_V3_WB_FIR_COEF_H2(1, 3));
+	RR(VID_V3_WB_FIR_COEF_H2(1, 4));
+	RR(VID_V3_WB_FIR_COEF_H2(1, 5));
+	RR(VID_V3_WB_FIR_COEF_H2(1, 6));
+	RR(VID_V3_WB_FIR_COEF_H2(1, 7));
+
+	RR(VID_V3_WB_FIR_COEF_HV2(1, 0));
+	RR(VID_V3_WB_FIR_COEF_HV2(1, 1));
+	RR(VID_V3_WB_FIR_COEF_HV2(1, 2));
+	RR(VID_V3_WB_FIR_COEF_HV2(1, 3));
+	RR(VID_V3_WB_FIR_COEF_HV2(1, 4));
+	RR(VID_V3_WB_FIR_COEF_HV2(1, 5));
+	RR(VID_V3_WB_FIR_COEF_HV2(1, 6));
+	RR(VID_V3_WB_FIR_COEF_HV2(1, 7));
+
+	RR(VID_V3_WB_FIR_COEF_V2(1, 0));
+	RR(VID_V3_WB_FIR_COEF_V2(1, 1));
+	RR(VID_V3_WB_FIR_COEF_V2(1, 2));
+	RR(VID_V3_WB_FIR_COEF_V2(1, 3));
+	RR(VID_V3_WB_FIR_COEF_V2(1, 4));
+	RR(VID_V3_WB_FIR_COEF_V2(1, 5));
+	RR(VID_V3_WB_FIR_COEF_V2(1, 6));
+	RR(VID_V3_WB_FIR_COEF_V2(1, 7));
+
+	RR(VID_BA_UV0(0));
+	RR(VID_BA_UV0(1));
+
+	RR(VID_BA_UV1(0));
+	RR(VID_BA_UV1(1));
+
+	RR(VID_ATTRIBUTES2(0));
+	RR(VID_ATTRIBUTES2(1));
+	RR(VID_ATTRIBUTES2(2));
+	RR(VID_ATTRIBUTES2(3));
+
+	RR(GAMMA_TABLE(0));
+	RR(GAMMA_TABLE(1));
+	RR(GAMMA_TABLE(2));
+	RR(GAMMA_TABLE(3));
+
+	}
+
 	RR(GFX_BA0);
 	RR(GFX_BA1);
 	RR(GFX_POSITION);
@@ -489,219 +1048,168 @@ bool dispc_go_busy(enum omap_channel channel)
 {
 	int bit;
 
-	if (channel == OMAP_DSS_CHANNEL_LCD)
+	if ((!cpu_is_omap44xx()) && (channel == OMAP_DSS_CHANNEL_LCD))
+		bit = 5; /* GOLCD */
+	else if (cpu_is_omap44xx() && (channel != OMAP_DSS_CHANNEL_DIGIT))
 		bit = 5; /* GOLCD */
 	else
 		bit = 6; /* GODIGIT */
 
-	return REG_GET(DISPC_CONTROL, bit, bit) == 1;
+	if (cpu_is_omap44xx() && (channel == OMAP_DSS_CHANNEL_LCD2))
+		return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
+	else
+		return REG_GET(DISPC_CONTROL, bit, bit) == 1;
+
 }
 
+
 void dispc_go(enum omap_channel channel)
 {
 	int bit;
 
 	enable_clocks(1);
 
-	if (channel == OMAP_DSS_CHANNEL_LCD)
+	if ((channel == OMAP_DSS_CHANNEL_LCD) ||
+			(channel == OMAP_DSS_CHANNEL_LCD2))
 		bit = 0; /* LCDENABLE */
 	else
 		bit = 1; /* DIGITALENABLE */
 
 	/* if the channel is not enabled, we don't need GO */
-	if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
-		goto end;
+	if (cpu_is_omap44xx() && (channel == OMAP_DSS_CHANNEL_LCD2)) {
+		if (REG_GET(DISPC_CONTROL2, bit, bit) == 0)
+			goto end;
+	} else {
+		if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
+			goto end;
+	}
 
-	if (channel == OMAP_DSS_CHANNEL_LCD)
+	if ((channel == OMAP_DSS_CHANNEL_LCD) ||
+			(channel == OMAP_DSS_CHANNEL_LCD2))
 		bit = 5; /* GOLCD */
 	else
 		bit = 6; /* GODIGIT */
 
-	if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
-		DSSERR("GO bit not down for channel %d\n", channel);
-		goto end;
+	if (cpu_is_omap44xx() && (channel == OMAP_DSS_CHANNEL_LCD2)) {
+		if (REG_GET(DISPC_CONTROL2, bit, bit) == 1) {
+			/* FIXME PICO DLP on Channel 2 needs GO bit to be UP
+			it will come as error so changing to DSSDBG*/
+			DSSDBG("GO bit not down for channel %d\n", channel);
+			goto end;
+		}
+	} else {
+		if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
+			DSSERR("GO bit not down for channel %d\n", channel);
+			goto end;
+		}
 	}
 
-	DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
+	DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
+		channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT");
+
+	if (cpu_is_omap44xx() && (channel == OMAP_DSS_CHANNEL_LCD2))
+		REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
+	else
+		REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 
-	REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 end:
 	enable_clocks(0);
 }
 
+
+
 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 {
 	BUG_ON(plane == OMAP_DSS_GFX);
 
-	dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
+	if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane))
+		dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
+	else if (OMAP_DSS_VIDEO3 == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_H(0, reg), value);
+	else if (OMAP_DSS_WB == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_H(1, reg), value);
 }
 
 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 {
 	BUG_ON(plane == OMAP_DSS_GFX);
 
-	dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
+	if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane))
+		dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
+	else if (OMAP_DSS_VIDEO3 == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_HV(0, reg), value);
+
+	else if (OMAP_DSS_WB == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_HV(1, reg), value);
 }
 
 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 {
 	BUG_ON(plane == OMAP_DSS_GFX);
 
-	dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
+	if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane))
+		dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
+	else if (OMAP_DSS_VIDEO3 == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_V(0, reg), value);
+	else if (OMAP_DSS_WB == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_V(1, reg), value);
 }
 
-static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
-		int vscaleup, int five_taps)
+static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 {
-	/* Coefficients for horizontal up-sampling */
-	static const u32 coef_hup[8] = {
-		0x00800000,
-		0x0D7CF800,
-		0x1E70F5FF,
-		0x335FF5FE,
-		0xF74949F7,
-		0xF55F33FB,
-		0xF5701EFE,
-		0xF87C0DFF,
-	};
-
-	/* Coefficients for horizontal down-sampling */
-	static const u32 coef_hdown[8] = {
-		0x24382400,
-		0x28371FFE,
-		0x2C361BFB,
-		0x303516F9,
-		0x11343311,
-		0x1635300C,
-		0x1B362C08,
-		0x1F372804,
-	};
+	BUG_ON(plane == OMAP_DSS_GFX);
 
-	/* Coefficients for horizontal and vertical up-sampling */
-	static const u32 coef_hvup[2][8] = {
-		{
-		0x00800000,
-		0x037B02FF,
-		0x0C6F05FE,
-		0x205907FB,
-		0x00404000,
-		0x075920FE,
-		0x056F0CFF,
-		0x027B0300,
-		},
-		{
-		0x00800000,
-		0x0D7CF8FF,
-		0x1E70F5FE,
-		0x335FF5FB,
-		0xF7404000,
-		0xF55F33FE,
-		0xF5701EFF,
-		0xF87C0D00,
-		},
-	};
+	if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane))
+		dispc_write_reg(DISPC_VID_FIR_COEF_H2(plane-1, reg), value);
+	else if (OMAP_DSS_VIDEO3 == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_H2(0, reg), value);
+	else if (OMAP_DSS_WB == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_H2(1, reg), value);
+}
 
-	/* Coefficients for horizontal and vertical down-sampling */
-	static const u32 coef_hvdown[2][8] = {
-		{
-		0x24382400,
-		0x28391F04,
-		0x2D381B08,
-		0x3237170C,
-		0x123737F7,
-		0x173732F9,
-		0x1B382DFB,
-		0x1F3928FE,
-		},
-		{
-		0x24382400,
-		0x28371F04,
-		0x2C361B08,
-		0x3035160C,
-		0x113433F7,
-		0x163530F9,
-		0x1B362CFB,
-		0x1F3728FE,
-		},
-	};
+static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
+{
+	BUG_ON(plane == OMAP_DSS_GFX);
 
-	/* Coefficients for vertical up-sampling */
-	static const u32 coef_vup[8] = {
-		0x00000000,
-		0x0000FF00,
-		0x0000FEFF,
-		0x0000FBFE,
-		0x000000F7,
-		0x0000FEFB,
-		0x0000FFFE,
-		0x000000FF,
-	};
+	if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane))
+		dispc_write_reg(DISPC_VID_FIR_COEF_HV2(plane-1, reg), value);
+	else if (OMAP_DSS_VIDEO3 == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_HV2(0, reg), value);
+	else if (OMAP_DSS_WB == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_HV2(1, reg), value);
+}
 
+static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
+{
+	BUG_ON(plane == OMAP_DSS_GFX);
 
-	/* Coefficients for vertical down-sampling */
-	static const u32 coef_vdown[8] = {
-		0x00000000,
-		0x000004FE,
-		0x000008FB,
-		0x00000CF9,
-		0x0000F711,
-		0x0000F90C,
-		0x0000FB08,
-		0x0000FE04,
-	};
+	if ((OMAP_DSS_VIDEO1 == plane) || (OMAP_DSS_VIDEO2 == plane))
+		dispc_write_reg(DISPC_VID_FIR_COEF_V2(plane-1, reg), value);
+	else if (OMAP_DSS_VIDEO3 == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_V2(0, reg), value);
+	else if (OMAP_DSS_WB == plane)
+		dispc_write_reg(DISPC_VID_V3_WB_FIR_COEF_V2(1, reg), value);
+}
 
-	const u32 *h_coef;
-	const u32 *hv_coef;
-	const u32 *hv_coef_mod;
-	const u32 *v_coef;
+static void _dispc_set_scale_coef(enum omap_plane plane, const s8 *hfir,
+				  const s8 *vfir, int three_taps)
+{
 	int i;
-
-	if (hscaleup)
-		h_coef = coef_hup;
-	else
-		h_coef = coef_hdown;
-
-	if (vscaleup) {
-		hv_coef = coef_hvup[five_taps];
-		v_coef = coef_vup;
-
-		if (hscaleup)
-			hv_coef_mod = NULL;
-		else
-			hv_coef_mod = coef_hvdown[five_taps];
-	} else {
-		hv_coef = coef_hvdown[five_taps];
-		v_coef = coef_vdown;
-
-		if (hscaleup)
-			hv_coef_mod = coef_hvup[five_taps];
-		else
-			hv_coef_mod = NULL;
-	}
-
-	for (i = 0; i < 8; i++) {
-		u32 h, hv;
-
-		h = h_coef[i];
-
-		hv = hv_coef[i];
-
-		if (hv_coef_mod) {
-			hv &= 0xffffff00;
-			hv |= (hv_coef_mod[i] & 0xff);
-		}
+	for (i = 0; i < 8; i++, hfir++, vfir++) {
+		u32 h, hv, v;
+		h = ((hfir[0] & 0xFF) | ((hfir[8] << 8) & 0xFF00) |
+		     ((hfir[16] << 16) & 0xFF0000) |
+		     ((hfir[24] << 24) & 0xFF000000));
+		hv = ((hfir[32] & 0xFF) | ((vfir[8] << 8) & 0xFF00) |
+		      ((vfir[16] << 16) & 0xFF0000) |
+		      ((vfir[24] << 24) & 0xFF000000));
+		v = ((vfir[0] & 0xFF) | ((vfir[32] << 8) & 0xFF00));
 
 		_dispc_write_firh_reg(plane, i, h);
 		_dispc_write_firhv_reg(plane, i, hv);
-	}
-
-	if (!five_taps)
-		return;
-
-	for (i = 0; i < 8; i++) {
-		u32 v;
-		v = v_coef[i];
 		_dispc_write_firv_reg(plane, i, v);
+		if (three_taps && v)
+			printk(KERN_ERR "three_tap v is %x\n", v);
 	}
 }
 
@@ -731,6 +1239,33 @@ static void _dispc_setup_color_conv_coef(void)
 	dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 	dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 	dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
+	if (cpu_is_omap44xx()) {
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(0, 0),
+			CVAL(ct->rcr, ct->ry));
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(0, 1),
+			CVAL(ct->gy,  ct->rcb));
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(0, 2),
+			CVAL(ct->gcb, ct->gcr));
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(0, 3),
+			CVAL(ct->bcr, ct->by));
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(0, 4),
+			CVAL(0, ct->bcb));
+		REG_FLD_MOD(DISPC_VID_V3_WB_ATTRIBUTES(0), ct->full_range, 11, 11);
+		/* Writeback */
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(1, 0),
+			CVAL(ct->rcr, ct->ry));
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(1, 1),
+			CVAL(ct->gy,  ct->rcb));
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(1, 2),
+			CVAL(ct->gcb, ct->gcr));
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(1, 3),
+			CVAL(ct->bcr, ct->by));
+		dispc_write_reg(DISPC_VID_V3_WB_CONV_COEF(1, 4),
+			CVAL(0,	ct->bcb));
+
+		REG_FLD_MOD(DISPC_VID_V3_WB_ATTRIBUTES(1), ct->full_range, 11, 11);
+
+	}
 
 #undef CVAL
 
@@ -741,46 +1276,93 @@ static void _dispc_setup_color_conv_coef(void)
 
 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 {
-	const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
+	struct dispc_reg ba0_reg[5] = { DISPC_GFX_BA0,
 		DISPC_VID_BA0(0),
 		DISPC_VID_BA0(1) };
+	if (cpu_is_omap44xx()) {
+		ba0_reg[3] = DISPC_VID_V3_WB_BA0(0); /* VID 3 pipeline*/
+		ba0_reg[4] = DISPC_VID_V3_WB_BA0(1); /* WB pipeline*/
+	}
 
 	dispc_write_reg(ba0_reg[plane], paddr);
 }
 
 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 {
-	const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
+	struct dispc_reg ba1_reg[5] = { DISPC_GFX_BA1,
 				      DISPC_VID_BA1(0),
 				      DISPC_VID_BA1(1) };
+	if (cpu_is_omap44xx()) {
+		ba1_reg[3] = DISPC_VID_V3_WB_BA1(0); /* VID 3 pipeline*/
+		ba1_reg[4] = DISPC_VID_V3_WB_BA1(1); /* WB pipeline*/
+	}
 
 	dispc_write_reg(ba1_reg[plane], paddr);
 }
 
+static void _dispc_set_plane_ba_uv0(enum omap_plane plane, u32 paddr)
+{
+	const struct dispc_reg ba_uv0_reg[] = { DISPC_VID_BA_UV0(0),
+				DISPC_VID_BA_UV0(1),
+				DISPC_VID_BA_UV0(2), /* VID 3 pipeline*/
+				DISPC_VID_BA_UV0(3), /* WB pipeline*/
+	};
+
+	BUG_ON(plane == OMAP_DSS_GFX);
+
+	dispc_write_reg(ba_uv0_reg[plane - 1], paddr);
+	/* plane - 1 => no UV_BA for GFX*/
+
+}
+
+static void _dispc_set_plane_ba_uv1(enum omap_plane plane, u32 paddr)
+{
+	const struct dispc_reg ba_uv1_reg[] = { DISPC_VID_BA_UV1(0),
+				DISPC_VID_BA_UV1(1),
+				DISPC_VID_BA_UV1(2)
+	};
+
+	BUG_ON(plane == OMAP_DSS_GFX);
+
+	dispc_write_reg(ba_uv1_reg[plane - 1], paddr);
+	/* plane - 1 => no UV_BA for GFX*/
+}
+
+
 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 {
-	const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
+	struct dispc_reg pos_reg[4] = { DISPC_GFX_POSITION,
 				      DISPC_VID_POSITION(0),
 				      DISPC_VID_POSITION(1) };
-
 	u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
+	if (cpu_is_omap44xx())
+		pos_reg[3] = DISPC_VID_VID3_POSITION; /* VID 3 pipeline*/
+
 	dispc_write_reg(pos_reg[plane], val);
 }
 
 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 {
-	const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
+	struct dispc_reg siz_reg[5] = { DISPC_GFX_SIZE,
 				      DISPC_VID_PICTURE_SIZE(0),
 				      DISPC_VID_PICTURE_SIZE(1) };
 	u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
+	if (cpu_is_omap44xx()) {
+		siz_reg[3] = DISPC_VID_V3_WB_PICTURE_SIZE(0); /* VID3 pipeline*/
+		siz_reg[4] = DISPC_VID_V3_WB_PICTURE_SIZE(1); /* WB pipeline*/
+	}
 	dispc_write_reg(siz_reg[plane], val);
 }
 
 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 {
 	u32 val;
-	const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
+	struct dispc_reg vsi_reg[4] = { DISPC_VID_SIZE(0),
 				      DISPC_VID_SIZE(1) };
+	if (cpu_is_omap44xx()) {
+		vsi_reg[2] = DISPC_VID_V3_WB_SIZE(0); /* VID 3 pipeline*/
+		vsi_reg[3] = DISPC_VID_V3_WB_SIZE(1); /* WB pipeline*/
+	}
 
 	BUG_ON(plane == OMAP_DSS_GFX);
 
@@ -790,8 +1372,8 @@ static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 
 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 {
-
-	BUG_ON(plane == OMAP_DSS_VIDEO1);
+	if (!cpu_is_omap44xx())
+		BUG_ON(plane == OMAP_DSS_VIDEO1);
 
 	if (cpu_is_omap24xx())
 		return;
@@ -800,22 +1382,34 @@ static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 		REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 	else if (plane == OMAP_DSS_VIDEO2)
 		REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
+	else if (plane == OMAP_DSS_VIDEO1)
+		REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 15, 8);
+	else if (plane == OMAP_DSS_VIDEO3)
+		REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 31, 24);
+
 }
 
 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 {
-	const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
+	struct dispc_reg ri_reg[5] = { DISPC_GFX_PIXEL_INC,
 				     DISPC_VID_PIXEL_INC(0),
 				     DISPC_VID_PIXEL_INC(1) };
-
+	if (cpu_is_omap44xx()) {
+		ri_reg[3] = DISPC_VID_V3_WB_PIXEL_INC(0);
+		ri_reg[4] = DISPC_VID_V3_WB_PIXEL_INC(1); /* WB pipeline*/
+	}
 	dispc_write_reg(ri_reg[plane], inc);
 }
 
 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 {
-	const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
+	struct dispc_reg ri_reg[5] = { DISPC_GFX_ROW_INC,
 				     DISPC_VID_ROW_INC(0),
-				     DISPC_VID_ROW_INC(1) };
+				     DISPC_VID_ROW_INC(1)};
+	if (cpu_is_omap44xx()) {
+		ri_reg[3] = DISPC_VID_V3_WB_ROW_INC(0);
+		ri_reg[4] = DISPC_VID_V3_WB_ROW_INC(1); /* WB pipeline*/
+	}
 
 	dispc_write_reg(ri_reg[plane], inc);
 }
@@ -824,38 +1418,74 @@ static void _dispc_set_color_mode(enum omap_plane plane,
 		enum omap_color_mode color_mode)
 {
 	u32 m = 0;
-
-	switch (color_mode) {
-	case OMAP_DSS_COLOR_CLUT1:
-		m = 0x0; break;
-	case OMAP_DSS_COLOR_CLUT2:
-		m = 0x1; break;
-	case OMAP_DSS_COLOR_CLUT4:
-		m = 0x2; break;
-	case OMAP_DSS_COLOR_CLUT8:
-		m = 0x3; break;
-	case OMAP_DSS_COLOR_RGB12U:
-		m = 0x4; break;
-	case OMAP_DSS_COLOR_ARGB16:
-		m = 0x5; break;
-	case OMAP_DSS_COLOR_RGB16:
-		m = 0x6; break;
-	case OMAP_DSS_COLOR_RGB24U:
-		m = 0x8; break;
-	case OMAP_DSS_COLOR_RGB24P:
-		m = 0x9; break;
-	case OMAP_DSS_COLOR_YUV2:
-		m = 0xa; break;
-	case OMAP_DSS_COLOR_UYVY:
-		m = 0xb; break;
-	case OMAP_DSS_COLOR_ARGB32:
-		m = 0xc; break;
-	case OMAP_DSS_COLOR_RGBA32:
-		m = 0xd; break;
-	case OMAP_DSS_COLOR_RGBX32:
-		m = 0xe; break;
-	default:
-		BUG(); break;
+	if ((!cpu_is_omap44xx()) || (OMAP_DSS_GFX == plane)) {
+		switch (color_mode) {
+		case OMAP_DSS_COLOR_CLUT1:
+			m = 0x0; break;
+		case OMAP_DSS_COLOR_CLUT2:
+			m = 0x1; break;
+		case OMAP_DSS_COLOR_CLUT4:
+			m = 0x2; break;
+		case OMAP_DSS_COLOR_CLUT8:
+			m = 0x3; break;
+		case OMAP_DSS_COLOR_RGB12U:
+			m = 0x4; break;
+		case OMAP_DSS_COLOR_ARGB16:
+			m = 0x5; break;
+		case OMAP_DSS_COLOR_RGB16:
+			m = 0x6; break;
+		case OMAP_DSS_COLOR_RGB24U:
+			m = 0x8; break;
+		case OMAP_DSS_COLOR_RGB24P:
+			m = 0x9; break;
+		case OMAP_DSS_COLOR_YUV2:
+			m = 0xa; break;
+		case OMAP_DSS_COLOR_UYVY:
+			m = 0xb; break;
+		case OMAP_DSS_COLOR_ARGB32:
+			m = 0xc; break;
+		case OMAP_DSS_COLOR_RGBA32:
+			m = 0xd; break;
+		case OMAP_DSS_COLOR_RGBX32:
+			m = 0xe; break;
+		default:
+			BUG(); break;
+		}
+	} else {
+		switch (color_mode) {
+		case OMAP_DSS_COLOR_NV12:
+			m = 0x0; break;
+		case OMAP_DSS_COLOR_RGB12U:
+			m = 0x1; break;
+		case OMAP_DSS_COLOR_RGBA12:
+			m = 0x2; break;
+		case OMAP_DSS_COLOR_XRGB12:
+			m = 0x4; break;
+		case OMAP_DSS_COLOR_ARGB16:
+			m = 0x5; break;
+		case OMAP_DSS_COLOR_RGB16:
+			m = 0x6; break;
+		case OMAP_DSS_COLOR_ARGB16_1555:
+			m = 0x7; break;
+		case OMAP_DSS_COLOR_RGB24U:
+			m = 0x8; break;
+		case OMAP_DSS_COLOR_RGB24P:
+			m = 0x9; break;
+		case OMAP_DSS_COLOR_YUV2:
+			m = 0xA; break;
+		case OMAP_DSS_COLOR_UYVY:
+			m = 0xB; break;
+		case OMAP_DSS_COLOR_ARGB32:
+			m = 0xC; break;
+		case OMAP_DSS_COLOR_RGBA32:
+			m = 0xD; break;
+		case OMAP_DSS_COLOR_RGBX24_32_ALGN:
+			m = 0xE; break;
+		case OMAP_DSS_COLOR_XRGB15:
+			m = 0xF; break;
+		default:
+			BUG(); break;
+		}
 	}
 
 	REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
@@ -866,6 +1496,7 @@ static void _dispc_set_channel_out(enum omap_plane plane,
 {
 	int shift;
 	u32 val;
+	int chan = 0, chan2 = 0;
 
 	switch (plane) {
 	case OMAP_DSS_GFX:
@@ -873,6 +1504,7 @@ static void _dispc_set_channel_out(enum omap_plane plane,
 		break;
 	case OMAP_DSS_VIDEO1:
 	case OMAP_DSS_VIDEO2:
+	case OMAP_DSS_VIDEO3:
 		shift = 16;
 		break;
 	default:
@@ -881,7 +1513,30 @@ static void _dispc_set_channel_out(enum omap_plane plane,
 	}
 
 	val = dispc_read_reg(dispc_reg_att[plane]);
-	val = FLD_MOD(val, channel, shift, shift);
+	if (cpu_is_omap44xx()) {
+		switch (channel) {
+
+		case OMAP_DSS_CHANNEL_LCD:
+			chan = 0;
+			chan2 = 0;
+			break;
+		case OMAP_DSS_CHANNEL_DIGIT:
+			chan = 1;
+			chan2 = 0;
+			break;
+		case OMAP_DSS_CHANNEL_LCD2:
+			chan = 0;
+			chan2 = 1;
+			break;
+		default:
+			BUG();
+		}
+
+		val = FLD_MOD(val, chan, shift, shift);
+		val = FLD_MOD(val, chan2, 31, 30);
+	} else {
+		val = FLD_MOD(val, channel, shift, shift);
+	}
 	dispc_write_reg(dispc_reg_att[plane], val);
 }
 
@@ -899,6 +1554,8 @@ void dispc_set_burst_size(enum omap_plane plane,
 		break;
 	case OMAP_DSS_VIDEO1:
 	case OMAP_DSS_VIDEO2:
+	case OMAP_DSS_VIDEO3:
+	case OMAP_DSS_WB: /* WB pipeline */
 		shift = 14;
 		break;
 	default:
@@ -913,6 +1570,48 @@ void dispc_set_burst_size(enum omap_plane plane,
 	enable_clocks(0);
 }
 
+void dispc_set_zorder(enum omap_plane plane,
+					enum omap_overlay_zorder zorder)
+{
+	u32 val;
+
+	BUG_ON(plane == OMAP_DSS_WB);
+	val = dispc_read_reg(dispc_reg_att[plane]);
+	val = FLD_MOD(val, zorder, 27, 26);
+	dispc_write_reg(dispc_reg_att[plane], val);
+
+}
+
+void dispc_enable_zorder(enum omap_plane plane, bool enable)
+{
+	u32 val;
+
+	BUG_ON(plane == OMAP_DSS_WB);
+	val = dispc_read_reg(dispc_reg_att[plane]);
+	val = FLD_MOD(val, enable, 25, 25);
+	dispc_write_reg(dispc_reg_att[plane], val);
+
+}
+
+
+void dispc_set_idle_mode(void)
+{
+	u32 l;
+
+	l = dispc_read_reg(DISPC_SYSCONFIG);
+	l = FLD_MOD(l, 1, 13, 12);	/* MIDLEMODE: smart standby */
+	l = FLD_MOD(l, 1, 4, 3);	/* SIDLEMODE: smart idle */
+	l = FLD_MOD(l, 0, 2, 2);	/* ENWAKEUP */
+	l = FLD_MOD(l, 0, 0, 0);	/* AUTOIDLE */
+	dispc_write_reg(DISPC_SYSCONFIG, l);
+
+}
+
+void dispc_enable_gamma_table(bool enable)
+{
+	REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
+}
+
 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 {
 	u32 val;
@@ -927,6 +1626,7 @@ static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 void dispc_enable_replication(enum omap_plane plane, bool enable)
 {
 	int bit;
+	BUG_ON(plane == OMAP_DSS_WB);
 
 	if (plane == OMAP_DSS_GFX)
 		bit = 5;
@@ -938,13 +1638,16 @@ void dispc_enable_replication(enum omap_plane plane, bool enable)
 	enable_clocks(0);
 }
 
-void dispc_set_lcd_size(u16 width, u16 height)
+void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
 {
 	u32 val;
 	BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 	val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 	enable_clocks(1);
-	dispc_write_reg(DISPC_SIZE_LCD, val);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		dispc_write_reg(DISPC_SIZE_LCD2, val);
+	else
+		dispc_write_reg(DISPC_SIZE_LCD, val);
 	enable_clocks(0);
 }
 
@@ -960,11 +1663,15 @@ void dispc_set_digit_size(u16 width, u16 height)
 
 static void dispc_read_plane_fifo_sizes(void)
 {
-	const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
+	struct dispc_reg fsz_reg[5] = { DISPC_GFX_FIFO_SIZE_STATUS,
 				      DISPC_VID_FIFO_SIZE_STATUS(0),
 				      DISPC_VID_FIFO_SIZE_STATUS(1) };
 	u32 size;
 	int plane;
+	if (cpu_is_omap44xx()) {
+		fsz_reg[3] = DISPC_VID_V3_WB_BUF_SIZE_STATUS(0);
+		fsz_reg[4] = DISPC_VID_V3_WB_BUF_SIZE_STATUS(1);	/* WB pipeline*/
+	}
 
 	enable_clocks(1);
 
@@ -973,6 +1680,8 @@ static void dispc_read_plane_fifo_sizes(void)
 			size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
 		else if (cpu_is_omap34xx())
 			size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
+		else if (cpu_is_omap44xx())
+			size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 15, 0);
 		else
 			BUG();
 
@@ -989,9 +1698,13 @@ u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 
 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 {
-	const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
+	struct dispc_reg ftrs_reg[5] = { DISPC_GFX_FIFO_THRESHOLD,
 				       DISPC_VID_FIFO_THRESHOLD(0),
 				       DISPC_VID_FIFO_THRESHOLD(1) };
+	if (cpu_is_omap44xx()) {
+		ftrs_reg[3] = DISPC_VID_V3_WB_BUF_THRESHOLD(0);
+		ftrs_reg[4] = DISPC_VID_V3_WB_BUF_THRESHOLD(1);
+	}
 	enable_clocks(1);
 
 	DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
@@ -1003,9 +1716,12 @@ void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 	if (cpu_is_omap24xx())
 		dispc_write_reg(ftrs_reg[plane],
 				FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
-	else
+	else if (cpu_is_omap34xx())
+		dispc_write_reg(ftrs_reg[plane],
+					FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
+	else /* cpu is omap44xx */
 		dispc_write_reg(ftrs_reg[plane],
-				FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
+					FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
 
 	enable_clocks(0);
 }
@@ -1023,9 +1739,12 @@ void dispc_enable_fifomerge(bool enable)
 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
 {
 	u32 val;
-	const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
+	struct dispc_reg fir_reg[4] = { DISPC_VID_FIR(0),
 				      DISPC_VID_FIR(1) };
-
+	if (cpu_is_omap44xx()) {
+		fir_reg[2] = DISPC_VID_V3_WB_FIR(0);
+		fir_reg[3] = DISPC_VID_V3_WB_FIR(1); /* WB pipeline*/
+	}
 	BUG_ON(plane == OMAP_DSS_GFX);
 
 	if (cpu_is_omap24xx())
@@ -1038,71 +1757,284 @@ static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
 {
 	u32 val;
-	const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
+	struct dispc_reg ac0_reg[4] = { DISPC_VID_ACCU0(0),
 				      DISPC_VID_ACCU0(1) };
+	if (cpu_is_omap44xx()) {
+		ac0_reg[2] = DISPC_VID_V3_WB_ACCU0(0); /* VID 3 pipeline*/
+		ac0_reg[3] = DISPC_VID_V3_WB_ACCU0(1); /* WB pipeline*/
+	}
 
 	BUG_ON(plane == OMAP_DSS_GFX);
+	if (cpu_is_omap44xx())
+		val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+	else
+		val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
 
-	val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
 	dispc_write_reg(ac0_reg[plane-1], val);
 }
 
 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
 {
 	u32 val;
-	const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
+	struct dispc_reg ac1_reg[4] = { DISPC_VID_ACCU1(0),
 				      DISPC_VID_ACCU1(1) };
+	if (cpu_is_omap44xx()) {
+		ac1_reg[2] = DISPC_VID_V3_WB_ACCU1(0); /* VID 3 pipeline*/
+		ac1_reg[3] = DISPC_VID_V3_WB_ACCU1(1); /* WB pipeline*/
+	}
+
+	BUG_ON(plane == OMAP_DSS_GFX);
+	if (cpu_is_omap44xx())
+		val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+	else
+		val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
+	dispc_write_reg(ac1_reg[plane-1], val);
+}
+
+static void _dispc_set_fir2(enum omap_plane plane, int hinc, int vinc)
+{
+	u32 val;
+	const struct dispc_reg fir_reg[] = { DISPC_VID_FIR2(0),
+						DISPC_VID_FIR2(1),
+						DISPC_VID_V3_WB_FIR2(0),
+				/* VID 3 pipeline*/
+						DISPC_VID_V3_WB_FIR2(1)
+				/* WB pipeline*/
+
+	};
+
+	BUG_ON(plane == OMAP_DSS_GFX);
+
+	val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
+
+	dispc_write_reg(fir_reg[plane-1], val);
+}
+
+static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
+{
+	u32 val;
+	const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU2_0(0),
+					DISPC_VID_ACCU2_0(1),
+					DISPC_VID_V3_WB_ACCU2_0(0),
+					DISPC_VID_V3_WB_ACCU2_0(1) /* WB */
+	};
+
+	BUG_ON(plane == OMAP_DSS_GFX);
+
+	val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+	dispc_write_reg(ac0_reg[plane-1], val);
+}
+
+static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
+{
+	u32 val;
+	const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU2_1(0),
+					DISPC_VID_ACCU2_1(1),
+					DISPC_VID_V3_WB_ACCU2_1(0),
+					DISPC_VID_V3_WB_ACCU2_1(1)
+	};
 
 	BUG_ON(plane == OMAP_DSS_GFX);
 
-	val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
+	val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
 	dispc_write_reg(ac1_reg[plane-1], val);
 }
+static const s8 fir5_zero[] = {
+	 0,    0,    0,    0,    0,    0,    0,    0,
+	 0,    0,    0,    0,    0,    0,    0,    0,
+	 0,    0,    0,    0,    0,    0,    0,    0,
+	 0,    0,    0,    0,    0,    0,    0,    0,
+	 0,    0,    0,    0,    0,    0,    0,    0,
+};
+static const s8 fir3_m8[] = {
+	 0,    0,    0,    0,    0,    0,    0,    0,
+	 0,    2,    5,    7,    64,   32,   12,   3,
+	 128,  123,  111,  89,   64,   89,   111,  123,
+	 0,    3,    12,   32,   0,    7,    5,    2,
+	 0,    0,    0,    0,    0,    0,    0,    0,
+};
+static const s8 fir5_m8[] = {
+	 17,   18,   15,   9,   -18,  -6,    5,    13,
+	-20,  -27,  -30,  -27,   81,   47,   17,  -4,
+	 134,  127,  121,  105,  81,   105,  121,  127,
+	-20,  -4,    17,   47,  -18,  -27,  -30,  -27,
+	 17,   14,   5,   -6,    2,    9,    15,   19,
+};
+static const s8 fir5_m8b[] = {
+	 0,    0,   -1,   -2,   -9,   -5,   -2,   -1,
+	 0,   -8,   -11,  -11,   73,   51,   30,   13,
+	 128,  124,  112,  95,   73,   95,   112,  124,
+	 0,    13,   30,   51,  -9,   -11,  -11,  -8,
+	 0,   -1,   -2,   -5,    0,   -2,   -1,    0,
+};
+static const s8 fir5_m9[] = {
+	 8,    14,   17,   17,  -26,  -18,  -9,    1,
+	-8,   -21,  -27,  -30,   83,   56,   30,   8,
+	 128,  126,  117,  103,  83,   103,  117,  126,
+	-8,    8,    30,   56,  -26,  -30,  -27,  -21,
+	 8,    1,   -9,   -18,   14,   17,   17,   14,
+};
+static const s8 fir5_m10[] = {
+	-2,    5,    11,   15,  -28,  -24,  -18,  -10,
+	 2,   -12,  -22,  -27,   83,   62,   41,   20,
+	 128,  125,  116,  102,  83,   102,  116,  125,
+	 2,    20,   41,   62,  -28,  -27,  -22,  -12,
+	-2,   -10,  -18,  -24,   18,   15,   11,   5,
+};
+static const s8 fir5_m11[] = {
+	-12,  -4,    3,    9,   -26,  -27,  -24,  -19,
+	 12,  -3,   -15,  -22,   83,   67,   49,   30,
+	 128,  124,  115,  101,  83,   101,  115,  124,
+	 12,   30,   49,   67,  -26,  -22,  -15,  -3,
+	-12,  -19,  -24,  -27,   14,   9,    3,   -4,
+};
+static const s8 fir5_m12[] = {
+	-19,  -12,  -6,    1,   -21,  -25,  -26,  -24,
+	 21,   6,   -7,   -16,   82,   70,   55,   38,
+	 124,  120,  112,  98,   82,   98,   112,  120,
+	 21,   38,   55,   70,  -21,  -16,  -7,    6,
+	-19,  -24,  -26,  -25,   6,    1,   -6,   -12,
+};
+static const s8 fir5_m13[] = {
+	-22,  -18,  -12,  -6,   -17,  -22,  -25,  -25,
+	 27,   13,   0,   -10,   81,   71,   58,   43,
+	 118,  115,  107,  95,   81,   95,   107,  115,
+	 27,   43,   58,   71,  -17,  -10,   0,    13,
+	-22,  -25,  -25,  -22,   0,   -6,   -12,  -18,
+};
+static const s8 fir5_m14[] = {
+	-23,  -20,  -16,  -11,  -11,  -18,  -22,  -24,
+	 32,   18,   6,   -4,    78,   70,   59,   46,
+	 110,  108,  101,  91,   78,   91,   101,  108,
+	 32,   46,   59,   70,  -11,  -4,    6,    18,
+	-23,  -24,  -22,  -18,  -6,   -11,  -16,  -20,
+};
+static const s8 fir3_m16[] = {
+	 0,    0,    0,    0,    0,    0,    0,    0,
+	 36,   31,   27,   23,   55,   50,   45,   40,
+	 56,   57,   56,   55,   55,   55,   56,   57,
+	 36,   40,   45,   50,   18,   23,   27,   31,
+	 0,    0,    0,    0,    0,    0,    0,    0,
+};
+static const s8 fir5_m16[] = {
+	-20,  -21,  -19,  -17,  -2,   -9,   -14,  -18,
+	 37,   26,   15,   6,    73,   66,   58,   48,
+	 94,   93,   88,   82,   73,   82,   88,   93,
+	 37,   48,   58,   66,  -2,    6,    15,   26,
+	-20,  -18,  -14,  -9,   -14,  -17,  -19,  -21,
+};
+static const s8 fir5_m19[] = {
+	-12,  -14,  -16,  -16,   8,    1,   -4,   -9,
+	 38,   31,   22,   15,   64,   59,   53,   47,
+	 76,   72,   73,   69,   64,   69,   73,   72,
+	 38,   47,   53,   59,   8,    15,   22,   31,
+	-12,  -8,   -4,    1,   -16,  -16,  -16,  -13,
+};
+static const s8 fir5_m22[] = {
+	-6,   -8,   -11,  -13,   13,   8,    3,   -2,
+	 37,   32,   25,   19,   58,   53,   48,   44,
+	 66,   61,   63,   61,   58,   61,   63,   61,
+	 37,   44,   48,   53,   13,   19,   25,   32,
+	-6,   -1,    3,    8,   -14,  -13,  -11,  -7,
+};
+static const s8 fir5_m26[] = {
+	 1,   -2,   -5,   -8,    18,   13,   8,    4,
+	 36,   31,   27,   22,   51,   48,   44,   40,
+	 54,   55,   54,   53,   51,   53,   54,   55,
+	 36,   40,   44,   48,   18,   22,   27,   31,
+	 1,    4,    8,    13,  -10,  -8,   -5,   -2,
+};
+static const s8 fir5_m32[] = {
+	 7,    4,    1,   -1,    21,   17,   14,   10,
+	 34,   31,   27,   24,   45,   42,   39,   37,
+	 46,   46,   46,   46,   45,   46,   46,   46,
+	 34,   37,   39,   42,   21,   24,   28,   31,
+	 7,    10,   14,   17,  -4,   -1,    1,    4,
+};
 
+static const s8 *get_scaling_coef(int orig_size, int out_size,
+			    int orig_ilaced, int out_ilaced,
+			    int three_tap)
+{
+	/* ranges from 2 to 32 */
+	int two_m = 16 * orig_size / out_size;
+
+	if (orig_size > 4 * out_size || out_size > 8 * orig_size)
+		return fir5_zero;
+
+	/* interlaced output needs at least M = 16 */
+	if (out_ilaced) {
+		if (two_m < 32)
+			two_m = 32;
+	}
 
+	if (three_tap)
+		return two_m < 24 ? fir3_m8 : fir3_m16;
+
+	return orig_size < out_size ? fir5_m8b :
+		two_m < 17 ? fir5_m8 :
+		two_m < 19 ? fir5_m9 :
+		two_m < 21 ? fir5_m10 :
+		two_m < 23 ? fir5_m11 :
+		two_m < 25 ? fir5_m12 :
+		two_m < 27 ? fir5_m13 :
+		two_m < 30 ? fir5_m14 :
+		two_m < 35 ? fir5_m16 :
+		two_m < 41 ? fir5_m19 :
+		two_m < 48 ? fir5_m22 :
+		two_m < 58 ? fir5_m26 :
+		fir5_m32;
+}
 static void _dispc_set_scaling(enum omap_plane plane,
 		u16 orig_width, u16 orig_height,
 		u16 out_width, u16 out_height,
-		bool ilace, bool five_taps,
-		bool fieldmode)
+		bool ilace, bool three_taps,
+		bool fieldmode, int scale_x, int scale_y)
 {
 	int fir_hinc;
 	int fir_vinc;
-	int hscaleup, vscaleup;
 	int accu0 = 0;
 	int accu1 = 0;
 	u32 l;
+	const s8 *hfir, *vfir;
 
 	BUG_ON(plane == OMAP_DSS_GFX);
 
-	hscaleup = orig_width <= out_width;
-	vscaleup = orig_height <= out_height;
-
-	_dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
-
-	if (!orig_width || orig_width == out_width)
+	if (scale_x) {
+		fir_hinc = 1024 * (orig_width - 1) / (out_width - 1);
+		if (fir_hinc > 4095)
+			fir_hinc = 4095;
+		hfir = get_scaling_coef(orig_width, out_width, 0, 0, 0);
+	} else {
 		fir_hinc = 0;
-	else
-		fir_hinc = 1024 * orig_width / out_width;
+		hfir = fir5_zero;
+	}
 
-	if (!orig_height || orig_height == out_height)
+	if (scale_y) {
+		fir_vinc = 1024 * (orig_height - 1) / (out_height - 1);
+		if (fir_vinc > 4095)
+			fir_vinc = 4095;
+		vfir = get_scaling_coef(orig_height, out_height, 0, 0,
+					three_taps);
+	} else {
 		fir_vinc = 0;
-	else
-		fir_vinc = 1024 * orig_height / out_height;
+		vfir = fir5_zero;
+	}
 
+	_dispc_set_scale_coef(plane, hfir, vfir, three_taps);
 	_dispc_set_fir(plane, fir_hinc, fir_vinc);
 
 	l = dispc_read_reg(dispc_reg_att[plane]);
-	l &= ~((0x0f << 5) | (0x3 << 21));
-
+	if (!cpu_is_omap44xx()) {
+		l &= ~((0x0f << 5) | (0x3 << 21));
+		l |= out_width > orig_width ? 0 : (1 << 7);
+		l |= out_height > orig_height ? 0 : (1 << 8);
+	} else
+		l &= ~((0x03 << 5) | (0x1 << 21));
 	l |= fir_hinc ? (1 << 5) : 0;
 	l |= fir_vinc ? (1 << 6) : 0;
 
-	l |= hscaleup ? 0 : (1 << 7);
-	l |= vscaleup ? 0 : (1 << 8);
-
-	l |= five_taps ? (1 << 21) : 0;
-	l |= five_taps ? (1 << 22) : 0;
+	l |= three_taps ? 0 : (1 << 21);
 
 	dispc_write_reg(dispc_reg_att[plane], l);
 
@@ -1123,54 +2055,140 @@ static void _dispc_set_scaling(enum omap_plane plane,
 	_dispc_set_vid_accu1(plane, 0, accu1);
 }
 
-static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
-		bool mirroring, enum omap_color_mode color_mode)
+static void _dispc_set_scaling_uv(enum omap_plane plane,
+		u16 orig_width, u16 orig_height,
+		u16 out_width, u16 out_height,
+		bool ilace, bool three_taps,
+		bool fieldmode, int scale_x, int scale_y)
 {
-	if (color_mode == OMAP_DSS_COLOR_YUV2 ||
-			color_mode == OMAP_DSS_COLOR_UYVY) {
-		int vidrot = 0;
+	int i;
+	int fir_hinc, fir_vinc;
+	int accu0, accu1, accuh;
+	const s8 *hfir, *vfir;
+
+	if (scale_x) {
+		fir_hinc = 1024 * (orig_width - 1) / (out_width - 1);
+		if (fir_hinc > 4095)
+			fir_hinc = 4095;
+		hfir = get_scaling_coef(orig_width, out_width, 0, 0, 0);
+	} else {
+		fir_hinc = 0;
+		hfir = fir5_zero;
+		}
 
-		if (mirroring) {
-			switch (rotation) {
-			case OMAP_DSS_ROT_0:
-				vidrot = 2;
-				break;
-			case OMAP_DSS_ROT_90:
-				vidrot = 1;
-				break;
-			case OMAP_DSS_ROT_180:
-				vidrot = 0;
-				break;
-			case OMAP_DSS_ROT_270:
-				vidrot = 3;
-				break;
-			}
-		} else {
-			switch (rotation) {
-			case OMAP_DSS_ROT_0:
-				vidrot = 0;
-				break;
-			case OMAP_DSS_ROT_90:
-				vidrot = 1;
-				break;
-			case OMAP_DSS_ROT_180:
-				vidrot = 2;
-				break;
-			case OMAP_DSS_ROT_270:
-				vidrot = 3;
-				break;
-			}
+	if (scale_y) {
+		fir_vinc = 1024 * (orig_height - 0) / (out_height - 0);
+		if (fir_vinc > 4095)
+			fir_vinc = 4095;
+		vfir = get_scaling_coef(orig_height, out_height, 0,
+					ilace, three_taps);
+	} else {
+		fir_vinc = 0;
+		vfir = fir5_zero;
 		}
 
-		REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
+	for (i = 0; i < 8; i++, hfir++, vfir++) {
+		u32 h, hv, v;
+		h = ((hfir[0] & 0xFF) | ((hfir[8] << 8) & 0xFF00) |
+		     ((hfir[16] << 16) & 0xFF0000) |
+		     ((hfir[24] << 24) & 0xFF000000));
+		hv = ((hfir[32] & 0xFF) | ((vfir[8] << 8) & 0xFF00) |
+		      ((vfir[16] << 16) & 0xFF0000) |
+		      ((vfir[24] << 24) & 0xFF000000));
+		v = ((vfir[0] & 0xFF) | ((vfir[32] << 8) & 0xFF00));
+
+		_dispc_write_firh2_reg(plane, i, h);
+		_dispc_write_firhv2_reg(plane, i, hv);
+		_dispc_write_firv2_reg(plane, i, v);
+		if (three_taps && v)
+			printk(KERN_ERR "three_tap v is %x\n", v);
+	}
 
-		if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
-			REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
-		else
-			REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
+	/* set chroma resampling */
+	REG_FLD_MOD(DISPC_VID_ATTRIBUTES2(plane - 1),
+		(fir_hinc || fir_vinc) ? 1 : 0, 8, 8);
+
+	/* set H scaling */
+	REG_FLD_MOD(dispc_reg_att[plane], fir_hinc ? 1 : 0, 6, 6);
+
+	/* set V scaling */
+	REG_FLD_MOD(dispc_reg_att[plane], fir_vinc ? 1 : 0, 5, 5);
+
+	_dispc_set_fir2(plane, fir_hinc, fir_vinc);
+
+	if (ilace) {
+		accu0 = (-3 * fir_vinc / 4) % 1024;
+		accu1 = (-fir_vinc / 4) % 1024;
 	} else {
-		REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
-		REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
+		accu0 = accu1 = (-fir_vinc / 2) % 1024;
+	}
+	accuh = (-fir_hinc / 2) % 1024;
+
+	_dispc_set_vid_accu2_0(plane, 0x80, 0);
+	_dispc_set_vid_accu2_1(plane, 0x80, 0);
+	/* _dispc_set_vid_accu2_0(plane, accuh, accu0);
+	   _dispc_set_vid_accu2_1(plane, accuh, accu1); */
+}
+static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
+		bool mirroring, enum omap_color_mode color_mode)
+{
+	BUG_ON(plane == OMAP_DSS_WB);
+	if (!cpu_is_omap44xx()) {
+		if (color_mode == OMAP_DSS_COLOR_YUV2 ||
+				color_mode == OMAP_DSS_COLOR_UYVY) {
+			int vidrot = 0;
+
+			if (mirroring) {
+				switch (rotation) {
+				case OMAP_DSS_ROT_0:
+					vidrot = 2;
+					break;
+				case OMAP_DSS_ROT_90:
+					vidrot = 1;
+					break;
+				case OMAP_DSS_ROT_180:
+					vidrot = 0;
+					break;
+				case OMAP_DSS_ROT_270:
+					vidrot = 3;
+					break;
+				}
+			} else {
+				switch (rotation) {
+				case OMAP_DSS_ROT_0:
+					vidrot = 0;
+					break;
+				case OMAP_DSS_ROT_90:
+					vidrot = 1;
+					break;
+				case OMAP_DSS_ROT_180:
+					vidrot = 2;
+					break;
+				case OMAP_DSS_ROT_270:
+					vidrot = 3;
+					break;
+				}
+			}
+
+			REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
+
+			if (rotation == OMAP_DSS_ROT_90 ||
+					rotation == OMAP_DSS_ROT_270)
+				REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
+			else
+				REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
+		} else {
+			REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
+			REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
+		}
+	} else if (plane != OMAP_DSS_GFX) {
+		if (color_mode == OMAP_DSS_COLOR_NV12) {
+			/* DOUBLESTRIDE : 0 for 90-, 270-; 1 for 0- and 180- */
+			if (rotation == 1 || rotation == 3)
+				REG_FLD_MOD(dispc_reg_att[plane], 0x0, 22, 22);
+			else
+				REG_FLD_MOD(dispc_reg_att[plane], 0x1, 22, 22);
+		}
 	}
 }
 
@@ -1215,6 +2233,69 @@ static s32 pixinc(int pixels, u8 ps)
 		BUG();
 }
 
+ static void calc_tiler_row_rotation(u8 rotation,
+		u16 width, u16 height,
+		enum omap_color_mode color_mode,
+		s32 *row_inc)
+ {
+	u8 ps = 1;
+	DSSDBG("calc_tiler_rot(%d): %dx%d\n", rotation, width, height);
+
+	switch (color_mode) {
+	case OMAP_DSS_COLOR_RGB16:
+	case OMAP_DSS_COLOR_ARGB16:
+
+	case OMAP_DSS_COLOR_YUV2:
+	case OMAP_DSS_COLOR_UYVY:
+		ps = 2;
+		break;
+
+	case OMAP_DSS_COLOR_RGB24P:
+	case OMAP_DSS_COLOR_RGB24U:
+	case OMAP_DSS_COLOR_ARGB32:
+	case OMAP_DSS_COLOR_RGBA32:
+	case OMAP_DSS_COLOR_RGBX32:
+		ps = 4;
+		break;
+
+	case OMAP_DSS_COLOR_NV12:
+		ps = 1;
+		break;
+
+	default:
+		BUG();
+		return;
+	}
+	switch (rotation) {
+	case 0:
+	case 2:
+		if (1 == ps)
+			*row_inc = 16384 + 1 - (width);
+		else
+			*row_inc = 32768 + 1 - (width * ps);
+		break;
+
+	case 1:
+	case 3:
+		if (4 == ps)
+			*row_inc = 16384 + 1 - (width * ps);
+		else
+			*row_inc = 8192 + 1 - (width * ps);
+		break;
+
+	default:
+		BUG();
+		return;
+	}
+
+	DSSDBG(" colormode: %d, rotation: %d, ps: %d, width: %d,"
+		" height: %d, row_inc:%d\n",
+		color_mode, rotation, ps, width, height, *row_inc);
+
+	return;
+ }
+
+
 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
 		u16 screen_width,
 		u16 width, u16 height,
@@ -1439,12 +2520,13 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
 	}
 }
 
-static unsigned long calc_fclk_five_taps(u16 width, u16 height,
-		u16 out_width, u16 out_height, enum omap_color_mode color_mode)
+static unsigned long calc_fclk_five_taps(enum omap_channel channel,
+		u16 width, u16 height, u16 out_width, u16 out_height,
+		enum omap_color_mode color_mode)
 {
 	u32 fclk = 0;
 	/* FIXME venc pclk? */
-	u64 tmp, pclk = dispc_pclk_rate();
+	u64 tmp, pclk = dispc_pclk_rate(channel);
 
 	if (height > out_height) {
 		/* FIXME get real display PPL */
@@ -1476,8 +2558,8 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
 	return fclk;
 }
 
-static unsigned long calc_fclk(u16 width, u16 height,
-		u16 out_width, u16 out_height)
+static unsigned long calc_fclk(enum omap_channel channel, u16 width,
+			u16 height, u16 out_width, u16 out_height)
 {
 	unsigned int hf, vf;
 
@@ -1501,7 +2583,7 @@ static unsigned long calc_fclk(u16 width, u16 height,
 		vf = 1;
 
 	/* FIXME venc pclk? */
-	return dispc_pclk_rate() * vf * hf;
+	return dispc_pclk_rate(channel) * vf * hf;
 }
 
 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
@@ -1519,11 +2601,11 @@ static int _dispc_setup_plane(enum omap_plane plane,
 		enum omap_color_mode color_mode,
 		bool ilace,
 		enum omap_dss_rotation_type rotation_type,
-		u8 rotation, int mirror,
-		u8 global_alpha)
+		u8 rotation, int mirror, enum omap_channel channel,
+		u8 global_alpha, u32 puv_addr)
 {
-	const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
-	bool five_taps = 0;
+	const int maxdownscale = (cpu_is_omap34xx() | cpu_is_omap44xx()) ? 4 : 2;
+	bool three_taps = 0;
 	bool fieldmode = 0;
 	int cconv = 0;
 	unsigned offset0, offset1;
@@ -1531,6 +2613,10 @@ static int _dispc_setup_plane(enum omap_plane plane,
 	s32 pix_inc;
 	u16 frame_height = height;
 	unsigned int field_offset = 0;
+	u8 orientation = 0;
+	struct tiler_view_orient orient;
+	unsigned long mir_x = 0, mir_y = 0;
+	unsigned long tiler_width, tiler_height;
 
 	if (paddr == 0)
 		return -EINVAL;
@@ -1558,6 +2644,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
 		case OMAP_DSS_COLOR_ARGB32:
 		case OMAP_DSS_COLOR_RGBA32:
 		case OMAP_DSS_COLOR_RGBX32:
+
 			if (cpu_is_omap24xx())
 				return -EINVAL;
 			/* fall through */
@@ -1597,12 +2684,18 @@ static int _dispc_setup_plane(enum omap_plane plane,
 		case OMAP_DSS_COLOR_ARGB16:
 		case OMAP_DSS_COLOR_ARGB32:
 		case OMAP_DSS_COLOR_RGBA32:
+		case OMAP_DSS_COLOR_RGBA12:
+		case OMAP_DSS_COLOR_XRGB12:
+		case OMAP_DSS_COLOR_ARGB16_1555:
+		case OMAP_DSS_COLOR_RGBX24_32_ALGN:
+		case OMAP_DSS_COLOR_XRGB15:
 			if (cpu_is_omap24xx())
 				return -EINVAL;
-			if (plane == OMAP_DSS_VIDEO1)
+			if (!cpu_is_omap44xx() && plane == OMAP_DSS_VIDEO1)
 				return -EINVAL;
 			break;
 
+		case OMAP_DSS_COLOR_NV12:
 		case OMAP_DSS_COLOR_YUV2:
 		case OMAP_DSS_COLOR_UYVY:
 			cconv = 1;
@@ -1612,32 +2705,36 @@ static int _dispc_setup_plane(enum omap_plane plane,
 			return -EINVAL;
 		}
 
-		/* Must use 5-tap filter? */
-		five_taps = height > out_height * 2;
+		/* Must use 3-tap filter */
+		three_taps = width > 1280;
+
+		/* Should use 3-tap filter for upscaling, but HDMI gets
+		   out of sync if using 3-tap */
+		/* if (out_height > height)
+			three_taps = 1; */
 
-		if (!five_taps) {
-			fclk = calc_fclk(width, height,
+		if (three_taps) {
+			fclk = calc_fclk(channel, width, height,
 					out_width, out_height);
 
 			/* Try 5-tap filter if 3-tap fclk is too high */
 			if (cpu_is_omap34xx() && height > out_height &&
-					fclk > dispc_fclk_rate())
-				five_taps = true;
+					fclk > dispc_fclk_rate()) {
+				printk(KERN_ERR
+					"Should use 5 tap but cannot\n");
+			}
+		} else {
+			fclk = calc_fclk_five_taps(channel, width, height,
+				out_width, out_height, color_mode);
 		}
 
-		if (width > (2048 >> five_taps)) {
-			DSSERR("failed to set up scaling, fclk too low\n");
+	if (!cpu_is_omap44xx())
+		if (width > (1024 << three_taps))
 			return -EINVAL;
-		}
-
-		if (five_taps)
-			fclk = calc_fclk_five_taps(width, height,
-					out_width, out_height, color_mode);
-
 		DSSDBG("required fclk rate = %lu Hz\n", fclk);
 		DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
 
-		if (!fclk || fclk > dispc_fclk_rate()) {
+		if (fclk > dispc_fclk_rate()) {
 			DSSERR("failed to set up scaling, "
 					"required fclk rate = %lu Hz, "
 					"current fclk rate = %lu Hz\n",
@@ -1663,18 +2760,69 @@ static int _dispc_setup_plane(enum omap_plane plane,
 	/* Fields are independent but interleaved in memory. */
 	if (fieldmode)
 		field_offset = 1;
+	pix_inc = 0x1;
+	offset0 = 0x0;
+	offset1 = 0x0;
+	/* check if tiler address; else set row_inc = 1*/
+	if ((paddr >= 0x60000000) && (paddr <= 0x7fffffff)) {
+		calc_tiler_row_rotation(rotation, width, frame_height,
+						color_mode, &row_inc);
+
+		orientation = calc_tiler_orientation(rotation, (u8)mirror);
+		/* get rotated top-left coordinate
+				(if rotation is applied before mirroring) */
+		memset(&orient, 0, sizeof(orient));
+		tiler_rotate_view(&orient, rotation * 90);
+		if (mirror) {
+			/* Horizontal mirroring */
+			if (rotation == 1 || rotation == 3)
+				mir_x = 1;
+			else
+				mir_y = 1;
+		} else {
+			mir_x = 0;
+			mir_y = 0;
+		}
+		orient.x_invert ^= mir_x;
+		orient.y_invert ^= mir_y;
+
+		DSSDBG("RYX = %d %d %d\n", orient.rotate_90,
+				orient.x_invert, orient.y_invert);
 
-	if (rotation_type == OMAP_DSS_ROT_DMA)
-		calc_dma_rotation_offset(rotation, mirror,
+		if (orient.rotate_90 & 1) {
+			tiler_height = width;
+			tiler_width = height;
+		} else {
+			tiler_height = height;
+			tiler_width = width;
+		}
+		DSSDBG("w, h = %ld %ld\n", tiler_width, tiler_height);
+
+		paddr = tiler_reorient_topleft(tiler_get_natural_addr((void *)paddr),
+				orient, tiler_width, tiler_height);
+
+		if (puv_addr)
+			puv_addr = tiler_reorient_topleft(
+					tiler_get_natural_addr((void *)puv_addr),
+					orient, tiler_width/2, tiler_height/2);
+			DSSDBG("rotated addresses: 0x%0x, 0x%0x\n",
+						paddr, puv_addr);
+			/* set BURSTTYPE if rotation is non-zero */
+			REG_FLD_MOD(dispc_reg_att[plane], 0x1, 29, 29);
+	} else
+		row_inc = 0x1;
+	if (!cpu_is_omap44xx()) {
+		if (rotation_type == OMAP_DSS_ROT_DMA)
+			calc_dma_rotation_offset(rotation, mirror,
 				screen_width, width, frame_height, color_mode,
 				fieldmode, field_offset,
 				&offset0, &offset1, &row_inc, &pix_inc);
-	else
-		calc_vrfb_rotation_offset(rotation, mirror,
+		else
+			calc_vrfb_rotation_offset(rotation, mirror,
 				screen_width, width, frame_height, color_mode,
 				fieldmode, field_offset,
 				&offset0, &offset1, &row_inc, &pix_inc);
-
+	}
 	DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
 			offset0, offset1, row_inc, pix_inc);
 
@@ -1683,6 +2831,11 @@ static int _dispc_setup_plane(enum omap_plane plane,
 	_dispc_set_plane_ba0(plane, paddr + offset0);
 	_dispc_set_plane_ba1(plane, paddr + offset1);
 
+	if (OMAP_DSS_COLOR_NV12 == color_mode) {
+		_dispc_set_plane_ba_uv0(plane, puv_addr + offset0);
+		_dispc_set_plane_ba_uv1(plane, puv_addr + offset1);
+	}
+
 	_dispc_set_row_inc(plane, row_inc);
 	_dispc_set_pix_inc(plane, pix_inc);
 
@@ -1694,16 +2847,56 @@ static int _dispc_setup_plane(enum omap_plane plane,
 	_dispc_set_pic_size(plane, width, height);
 
 	if (plane != OMAP_DSS_GFX) {
+		int scale_x = width != out_width;
+		int scale_y = height != out_height;
+		u16 out_ch_height = out_height;
+		u16 out_ch_width = out_width;
+		u16 ch_height = height;
+		u16 ch_width = width;
+		int scale_uv = 0;
+
+	if (cpu_is_omap44xx()) {
+		/* account for chroma decimation */
+		switch (color_mode) {
+		case OMAP_DSS_COLOR_NV12:
+			ch_height >>= 1; /* Y downsampled by 2 */
+		case OMAP_DSS_COLOR_YUV2:
+		case OMAP_DSS_COLOR_UYVY:
+			ch_width >>= 1; /* X downsampled by 2 */
+			/* must use FIR for YUV422 if rotated */
+			if (color_mode != OMAP_DSS_COLOR_NV12 && rotation % 4)
+				scale_x = scale_y = 1;
+			scale_uv = 1;
+			break;
+		default:
+			/* no UV scaling for RGB formats for now */
+			break;
+			}
+
+		if (out_ch_width != ch_width)
+			scale_x = true;
+		if (out_ch_height != ch_height)
+			scale_y = true;
+		/* set up UV scaling */
+		_dispc_set_scaling_uv(plane, ch_width, ch_height,
+			out_ch_width, out_ch_height, ilace,
+			three_taps, fieldmode, scale_uv && scale_x,
+			scale_uv && scale_y);
+		if (!scale_uv || (!scale_x && !scale_y))
+			/* :TRICKY: set chroma resampling for RGB formats */
+			REG_FLD_MOD(DISPC_VID_ATTRIBUTES2(plane - 1), 0, 8, 8);
+	}
 		_dispc_set_scaling(plane, width, height,
 				   out_width, out_height,
-				   ilace, five_taps, fieldmode);
+				   ilace, three_taps, fieldmode,
+				   scale_x, scale_y);
 		_dispc_set_vid_size(plane, out_width, out_height);
 		_dispc_set_vid_color_conv(plane, cconv);
 	}
 
 	_dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
 
-	if (plane != OMAP_DSS_VIDEO1)
+	if ((plane != OMAP_DSS_VIDEO1) || (cpu_is_omap44xx()))
 		_dispc_setup_global_alpha(plane, global_alpha);
 
 	return 0;
@@ -1712,6 +2905,10 @@ static int _dispc_setup_plane(enum omap_plane plane,
 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
 {
 	REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
+	if (!enable && cpu_is_omap44xx()) { /* clear out resizer related bits */
+		REG_FLD_MOD(dispc_reg_att[plane], 0x00, 6, 5);
+		REG_FLD_MOD(dispc_reg_att[plane], 0x00, 21, 21);
+	}
 }
 
 static void dispc_disable_isr(void *data, u32 mask)
@@ -1720,36 +2917,47 @@ static void dispc_disable_isr(void *data, u32 mask)
 	complete(compl);
 }
 
-static void _enable_lcd_out(bool enable)
+static void _enable_lcd_out(enum omap_channel channel, bool enable)
 {
-	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
+	else
+		REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
 }
 
-static void dispc_enable_lcd_out(bool enable)
+void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
 {
 	struct completion frame_done_completion;
 	bool is_on;
 	int r;
+	int irq;
 
 	enable_clocks(1);
 
 	/* When we disable LCD output, we need to wait until frame is done.
 	 * Otherwise the DSS is still working, and turning off the clocks
 	 * prevents DSS from going to OFF mode */
-	is_on = REG_GET(DISPC_CONTROL, 0, 0);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel) {
+		is_on = REG_GET(DISPC_CONTROL2, 0, 0);
+		irq = DISPC_IRQ_FRAMEDONE2;
+	} else {
+		is_on = REG_GET(DISPC_CONTROL, 0, 0);
+		irq = DISPC_IRQ_FRAMEDONE;
+	}
+
 
 	if (!enable && is_on) {
 		init_completion(&frame_done_completion);
 
 		r = omap_dispc_register_isr(dispc_disable_isr,
 				&frame_done_completion,
-				DISPC_IRQ_FRAMEDONE);
+				irq);
 
 		if (r)
 			DSSERR("failed to register FRAMEDONE isr\n");
 	}
 
-	_enable_lcd_out(enable);
+	_enable_lcd_out(channel, enable);
 
 	if (!enable && is_on) {
 		if (!wait_for_completion_timeout(&frame_done_completion,
@@ -1758,7 +2966,7 @@ static void dispc_enable_lcd_out(bool enable)
 
 		r = omap_dispc_unregister_isr(dispc_disable_isr,
 				&frame_done_completion,
-				DISPC_IRQ_FRAMEDONE);
+				irq);
 
 		if (r)
 			DSSERR("failed to unregister FRAMEDONE isr\n");
@@ -1772,7 +2980,7 @@ static void _enable_digit_out(bool enable)
 	REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
 }
 
-static void dispc_enable_digit_out(bool enable)
+void dispc_enable_digit_out(bool enable)
 {
 	struct completion frame_done_completion;
 	int r;
@@ -1810,13 +3018,15 @@ static void dispc_enable_digit_out(bool enable)
 	/* XXX I understand from TRM that we should only wait for the
 	 * current field to complete. But it seems we have to wait
 	 * for both fields */
-	if (!wait_for_completion_timeout(&frame_done_completion,
+	if (!cpu_is_omap44xx()) {
+		if (!wait_for_completion_timeout(&frame_done_completion,
 				msecs_to_jiffies(100)))
-		DSSERR("timeout waiting for EVSYNC\n");
+			DSSERR("timeout waiting for EVSYNC\n");
 
-	if (!wait_for_completion_timeout(&frame_done_completion,
+		if (!wait_for_completion_timeout(&frame_done_completion,
 				msecs_to_jiffies(100)))
-		DSSERR("timeout waiting for EVSYNC\n");
+			DSSERR("timeout waiting for EVSYNC\n");
+	}
 
 	r = omap_dispc_unregister_isr(dispc_disable_isr,
 			&frame_done_completion,
@@ -1848,8 +3058,9 @@ bool dispc_is_channel_enabled(enum omap_channel channel)
 
 void dispc_enable_channel(enum omap_channel channel, bool enable)
 {
-	if (channel == OMAP_DSS_CHANNEL_LCD)
-		dispc_enable_lcd_out(enable);
+	if (channel == OMAP_DSS_CHANNEL_LCD ||
+		channel == OMAP_DSS_CHANNEL_LCD2)
+		dispc_enable_lcd_out(channel, enable);
 	else if (channel == OMAP_DSS_CHANNEL_DIGIT)
 		dispc_enable_digit_out(enable);
 	else
@@ -1885,7 +3096,8 @@ void dispc_enable_fifohandcheck(bool enable)
 }
 
 
-void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
+void dispc_set_lcd_display_type(enum omap_channel channel,
+				enum omap_lcd_display_type type)
 {
 	int mode;
 
@@ -1904,7 +3116,11 @@ void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
 	}
 
 	enable_clocks(1);
-	REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
+	else
+		REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
+
 	enable_clocks(0);
 }
 
@@ -1919,8 +3135,7 @@ void dispc_set_loadmode(enum omap_dss_load_mode mode)
 void dispc_set_default_color(enum omap_channel channel, u32 color)
 {
 	const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
-				DISPC_DEFAULT_COLOR1 };
-
+				DISPC_DEFAULT_COLOR1, DISPC_DEFAULT_COLOR2 };
 	enable_clocks(1);
 	dispc_write_reg(def_reg[channel], color);
 	enable_clocks(0);
@@ -1929,11 +3144,12 @@ void dispc_set_default_color(enum omap_channel channel, u32 color)
 u32 dispc_get_default_color(enum omap_channel channel)
 {
 	const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
-				DISPC_DEFAULT_COLOR1 };
+				DISPC_DEFAULT_COLOR1, DISPC_DEFAULT_COLOR2 };
 	u32 l;
 
-	BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
-	       channel != OMAP_DSS_CHANNEL_LCD);
+	if (!cpu_is_omap44xx())
+		BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
+			channel != OMAP_DSS_CHANNEL_LCD);
 
 	enable_clocks(1);
 	l = dispc_read_reg(def_reg[channel]);
@@ -1947,10 +3163,13 @@ void dispc_set_trans_key(enum omap_channel ch,
 		u32 trans_key)
 {
 	const struct dispc_reg tr_reg[] = {
-		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
+		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1,
+		DISPC_TRANS_COLOR2};
 
 	enable_clocks(1);
-	if (ch == OMAP_DSS_CHANNEL_LCD)
+	if (ch == OMAP_DSS_CHANNEL_LCD2)
+		REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
+	else if (ch == OMAP_DSS_CHANNEL_LCD)
 		REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
 	else /* OMAP_DSS_CHANNEL_DIGIT */
 		REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
@@ -1964,11 +3183,14 @@ void dispc_get_trans_key(enum omap_channel ch,
 		u32 *trans_key)
 {
 	const struct dispc_reg tr_reg[] = {
-		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
+		DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1,
+		DISPC_TRANS_COLOR2 };
 
 	enable_clocks(1);
 	if (type) {
-		if (ch == OMAP_DSS_CHANNEL_LCD)
+		if (ch == OMAP_DSS_CHANNEL_LCD2)
+			*type = REG_GET(DISPC_CONFIG2, 11, 11);
+		else if (ch == OMAP_DSS_CHANNEL_LCD)
 			*type = REG_GET(DISPC_CONFIG, 11, 11);
 		else if (ch == OMAP_DSS_CHANNEL_DIGIT)
 			*type = REG_GET(DISPC_CONFIG, 13, 13);
@@ -1984,7 +3206,9 @@ void dispc_get_trans_key(enum omap_channel ch,
 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
 {
 	enable_clocks(1);
-	if (ch == OMAP_DSS_CHANNEL_LCD)
+	if (ch == OMAP_DSS_CHANNEL_LCD2)
+		REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
+	else if (ch == OMAP_DSS_CHANNEL_LCD)
 		REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
 	else /* OMAP_DSS_CHANNEL_DIGIT */
 		REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
@@ -2026,8 +3250,12 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
 bool dispc_trans_key_enabled(enum omap_channel ch)
 {
 	bool enabled;
+	BUG_ON(ch == OMAP_DSS_CHANNEL_LCD2);
 
 	enable_clocks(1);
+	if (ch == OMAP_DSS_CHANNEL_LCD2)
+		enabled = REG_GET(DISPC_CONFIG2, 10, 10);
+	else
 	if (ch == OMAP_DSS_CHANNEL_LCD)
 		enabled = REG_GET(DISPC_CONFIG, 10, 10);
 	else if (ch == OMAP_DSS_CHANNEL_DIGIT)
@@ -2040,7 +3268,7 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
 }
 
 
-void dispc_set_tft_data_lines(u8 data_lines)
+void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
 {
 	int code;
 
@@ -2063,11 +3291,15 @@ void dispc_set_tft_data_lines(u8 data_lines)
 	}
 
 	enable_clocks(1);
-	REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
+	if (channel == OMAP_DSS_CHANNEL_LCD2)
+		REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
+	else
+		REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
 	enable_clocks(0);
 }
 
-void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
+void dispc_set_parallel_interface_mode(enum omap_channel channel,
+				enum omap_parallel_interface_mode mode)
 {
 	u32 l;
 	int stallmode;
@@ -2097,13 +3329,18 @@ void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
 
 	enable_clocks(1);
 
-	l = dispc_read_reg(DISPC_CONTROL);
-
-	l = FLD_MOD(l, stallmode, 11, 11);
-	l = FLD_MOD(l, gpout0, 15, 15);
-	l = FLD_MOD(l, gpout1, 16, 16);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel) {
+		l = dispc_read_reg(DISPC_CONTROL2);
+		l = FLD_MOD(l, stallmode, 11, 11);
+		dispc_write_reg(DISPC_CONTROL2, l);
+	} else {
+		l = dispc_read_reg(DISPC_CONTROL);
+		l = FLD_MOD(l, stallmode, 11, 11);
+		l = FLD_MOD(l, gpout0, 15, 15);
+		l = FLD_MOD(l, gpout1, 16, 16);
 
-	dispc_write_reg(DISPC_CONTROL, l);
+		dispc_write_reg(DISPC_CONTROL, l);
+	}
 
 	enable_clocks(0);
 }
@@ -2139,8 +3376,8 @@ bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
 			timings->vfp, timings->vbp);
 }
 
-static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
-				   int vsw, int vfp, int vbp)
+static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
+			int hfp, int hbp, int vsw, int vfp, int vbp)
 {
 	u32 timing_h, timing_v;
 
@@ -2159,13 +3396,19 @@ static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
 	}
 
 	enable_clocks(1);
-	dispc_write_reg(DISPC_TIMING_H, timing_h);
-	dispc_write_reg(DISPC_TIMING_V, timing_v);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel) {
+		dispc_write_reg(DISPC_TIMING_H2, timing_h);
+		dispc_write_reg(DISPC_TIMING_V2, timing_v);
+	} else {
+		dispc_write_reg(DISPC_TIMING_H, timing_h);
+		dispc_write_reg(DISPC_TIMING_V, timing_v);
+	}
 	enable_clocks(0);
 }
 
 /* change name to mode? */
-void dispc_set_lcd_timings(struct omap_video_timings *timings)
+void dispc_set_lcd_timings(enum omap_channel channel,
+				struct omap_video_timings *timings)
 {
 	unsigned xtot, ytot;
 	unsigned long ht, vt;
@@ -2175,10 +3418,11 @@ void dispc_set_lcd_timings(struct omap_video_timings *timings)
 				timings->vfp, timings->vbp))
 		BUG();
 
-	_dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
-			timings->vsw, timings->vfp, timings->vbp);
+	_dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
+				timings->hbp, timings->vsw, timings->vfp,
+				timings->vbp);
 
-	dispc_set_lcd_size(timings->x_res, timings->y_res);
+	dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
 
 	xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
 	ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
@@ -2186,7 +3430,8 @@ void dispc_set_lcd_timings(struct omap_video_timings *timings)
 	ht = (timings->pixel_clock * 1000) / xtot;
 	vt = (timings->pixel_clock * 1000) / xtot / ytot;
 
-	DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
+	DSSDBG("channel %u xres %u yres %u\n", channel, timings->x_res,
+						timings->y_res);
 	DSSDBG("pck %u\n", timings->pixel_clock);
 	DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
 			timings->hsw, timings->hfp, timings->hbp,
@@ -2195,21 +3440,30 @@ void dispc_set_lcd_timings(struct omap_video_timings *timings)
 	DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
 }
 
-static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
+static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
+								u16 pck_div)
 {
 	BUG_ON(lck_div < 1);
 	BUG_ON(pck_div < 2);
 
 	enable_clocks(1);
-	dispc_write_reg(DISPC_DIVISOR,
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		dispc_write_reg(DISPC_DIVISOR2,
+			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
+	else
+		dispc_write_reg(DISPC_DIVISOR,
 			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
 	enable_clocks(0);
 }
 
-static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
+static void dispc_get_lcd_divisor(enum omap_channel channel,
+						int *lck_div, int *pck_div)
 {
 	u32 l;
-	l = dispc_read_reg(DISPC_DIVISOR);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		l = dispc_read_reg(DISPC_DIVISOR2);
+	else
+		l = dispc_read_reg(DISPC_DIVISOR);
 	*lck_div = FLD_GET(l, 23, 16);
 	*pck_div = FLD_GET(l, 7, 0);
 }
@@ -2222,20 +3476,22 @@ unsigned long dispc_fclk_rate(void)
 		r = dss_clk_get_rate(DSS_CLK_FCK1);
 	else
 #ifdef CONFIG_OMAP2_DSS_DSI
-		r = dsi_get_dsi1_pll_rate();
+		r = dsi_get_dsi1_pll_rate(DSI1);
 #else
 	BUG();
 #endif
 	return r;
 }
 
-unsigned long dispc_lclk_rate(void)
+unsigned long dispc_lclk_rate(enum omap_channel channel)
 {
 	int lcd;
 	unsigned long r;
 	u32 l;
-
-	l = dispc_read_reg(DISPC_DIVISOR);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		l = dispc_read_reg(DISPC_DIVISOR2);
+	else
+		l = dispc_read_reg(DISPC_DIVISOR);
 
 	lcd = FLD_GET(l, 23, 16);
 
@@ -2244,13 +3500,16 @@ unsigned long dispc_lclk_rate(void)
 	return r / lcd;
 }
 
-unsigned long dispc_pclk_rate(void)
+unsigned long dispc_pclk_rate(enum omap_channel channel)
 {
 	int lcd, pcd;
 	unsigned long r;
 	u32 l;
 
-	l = dispc_read_reg(DISPC_DIVISOR);
+	if (OMAP_DSS_CHANNEL_LCD2 == channel)
+		l = dispc_read_reg(DISPC_DIVISOR2);
+	else
+		l = dispc_read_reg(DISPC_DIVISOR);
 
 	lcd = FLD_GET(l, 23, 16);
 	pcd = FLD_GET(l, 7, 0);
@@ -2266,7 +3525,7 @@ void dispc_dump_clocks(struct seq_file *s)
 
 	enable_clocks(1);
 
-	dispc_get_lcd_divisor(&lcd, &pcd);
+	dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
 
 	seq_printf(s, "- DISPC -\n");
 
@@ -2275,8 +3534,26 @@ void dispc_dump_clocks(struct seq_file *s)
 			"dss1_alwon_fclk" : "dsi1_pll_fclk");
 
 	seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
-	seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
-	seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
+	seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
+			dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
+	seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
+			dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
+
+	if (cpu_is_omap44xx()) {
+		dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
+
+		seq_printf(s, "- DISPC - LCD 2\n");
+
+		seq_printf(s, "dispc fclk source = %s\n",
+			 dss_get_dispc_clk_source() == 0 ?
+			 "dss1_alwon_fclk" : "dsi1_pll_fclk");
+
+		seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
+		seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
+				dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
+		seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
+				dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
+	}
 
 	enable_clocks(0);
 }
@@ -2392,6 +3669,7 @@ void dispc_dump_regs(struct seq_file *s)
 	DUMPREG(DISPC_VID_POSITION(1));
 	DUMPREG(DISPC_VID_SIZE(1));
 	DUMPREG(DISPC_VID_ATTRIBUTES(1));
+	DUMPREG(DISPC_VID_V3_WB_ATTRIBUTES(1));
 	DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
 	DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
 	DUMPREG(DISPC_VID_ROW_INC(1));
@@ -2468,8 +3746,9 @@ void dispc_dump_regs(struct seq_file *s)
 #undef DUMPREG
 }
 
-static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
-				bool ihs, bool ivs, u8 acbi, u8 acb)
+static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
+				bool ieo, bool ipc, bool ihs, bool ivs,
+				u8 acbi, u8 acb)
 {
 	u32 l = 0;
 
@@ -2486,13 +3765,17 @@ static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
 	l |= FLD_VAL(acb, 7, 0);
 
 	enable_clocks(1);
-	dispc_write_reg(DISPC_POL_FREQ, l);
+	if (OMAP_DSS_CHANNEL_LCD2)
+		dispc_write_reg(DISPC_POL_FREQ2, l);
+	else
+		dispc_write_reg(DISPC_POL_FREQ, l);
 	enable_clocks(0);
 }
 
-void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
+void dispc_set_pol_freq(enum omap_channel ch, enum omap_panel_config config,
+			u8 acbi, u8 acb)
 {
-	_dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
+	_dispc_set_pol_freq(ch, (config & OMAP_DSS_LCD_ONOFF) != 0,
 			(config & OMAP_DSS_LCD_RF) != 0,
 			(config & OMAP_DSS_LCD_IEO) != 0,
 			(config & OMAP_DSS_LCD_IPC) != 0,
@@ -2561,25 +3844,31 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 	return 0;
 }
 
-int dispc_set_clock_div(struct dispc_clock_info *cinfo)
+int dispc_set_clock_div(enum omap_channel channel,
+	struct dispc_clock_info *cinfo)
 {
 	DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
 	DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
 
-	dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
+	dispc_set_lcd_divisor(channel, cinfo->lck_div,
+							cinfo->pck_div);
 
 	return 0;
 }
 
-int dispc_get_clock_div(struct dispc_clock_info *cinfo)
+int dispc_get_clock_div(enum omap_channel channel,
+	struct dispc_clock_info *cinfo)
 {
 	unsigned long fck;
 
 	fck = dispc_fclk_rate();
-
-	cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
-	cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
-
+	if (OMAP_DSS_CHANNEL_LCD2 == channel) {
+		cinfo->lck_div = REG_GET(DISPC_DIVISOR2, 23, 16);
+		cinfo->pck_div = REG_GET(DISPC_DIVISOR2, 7, 0);
+	} else {
+		cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
+		cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
+	}
 	cinfo->lck = fck / cinfo->lck_div;
 	cinfo->pck = cinfo->lck / cinfo->pck_div;
 
@@ -2857,6 +4146,23 @@ static void dispc_error_worker(struct work_struct *work)
 			}
 		}
 	}
+	if (errors & DISPC_IRQ_VID3_FIFO_UNDERFLOW) {
+		DSSERR("VID3_FIFO_UNDERFLOW, disabling VID2\n");
+		for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+			struct omap_overlay *ovl;
+			ovl = omap_dss_get_overlay(i);
+
+			if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
+				continue;
+
+			if (ovl->id == 3) {
+				dispc_enable_plane(ovl->id, 0);
+				dispc_go(ovl->manager->id);
+				mdelay(50);
+				break;
+			}
+		}
+	}
 
 	if (errors & DISPC_IRQ_SYNC_LOST) {
 		struct omap_overlay_manager *manager = NULL;
@@ -2897,7 +4203,52 @@ static void dispc_error_worker(struct work_struct *work)
 		}
 	}
 
+	if (errors & DISPC_IRQ_SYNC_LOST_2) {
+		struct omap_overlay_manager *manager = NULL;
+		bool enable = false;
+
+		DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
+
+		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
+			struct omap_overlay_manager *mgr;
+			mgr = omap_dss_get_overlay_manager(i);
+
+			if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
+				manager = mgr;
+				enable = mgr->device->state ==
+						OMAP_DSS_DISPLAY_ACTIVE;
+				mgr->device->driver->disable(mgr->device);
+				break;
+			}
+		}
+
+		if (manager) {
+			for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+				struct omap_overlay *ovl;
+				ovl = omap_dss_get_overlay(i);
+
+				if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
+					continue;
+
+				if (ovl->id != 0 && ovl->manager == manager)
+					dispc_enable_plane(ovl->id, 0);
+			}
+
+			dispc_go(manager->id);
+			mdelay(50);
+			if (enable)
+				manager->device->driver->enable(
+							manager->device);
+		}
+	}
+
+
 	if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
+
+	DSSERR("SYNC_LOST_DIGIT\n");
+/*commenting below code as with 1080P Decode we see a sync lost digit for
+first frame  as it takes long time to decode but it later recovers*/
+#if 0
 		struct omap_overlay_manager *manager = NULL;
 		bool enable = false;
 
@@ -2914,6 +4265,7 @@ static void dispc_error_worker(struct work_struct *work)
 				mgr->device->driver->disable(mgr->device);
 				break;
 			}
+
 		}
 
 		if (manager) {
@@ -2934,6 +4286,7 @@ static void dispc_error_worker(struct work_struct *work)
 			if (enable)
 				dssdev->driver->enable(dssdev);
 		}
+#endif
 	}
 
 	if (errors & DISPC_IRQ_OCP_ERR) {
@@ -3014,13 +4367,24 @@ int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 }
 
 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
-void dispc_fake_vsync_irq(void)
+void dispc_fake_vsync_irq(enum omap_dsi_index ix)
 {
 	u32 irqstatus = DISPC_IRQ_VSYNC;
 	int i;
 
 	local_irq_disable();
-
+	switch (ix) {
+	case DSI1:
+		irqstatus = DISPC_IRQ_VSYNC;
+		break;
+	case DSI2:
+		irqstatus = DISPC_IRQ_VSYNC2;
+		break;
+	default:
+		DSSERR("Invalid display id for fake vsync\n");
+		local_irq_enable();
+		return;
+	}
 	for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
 		struct omap_dispc_isr_data *isr_data;
 		isr_data = &dispc.registered_isr[i];
@@ -3077,7 +4441,8 @@ static void _omap_dispc_initial_config(void)
 	dispc_write_reg(DISPC_SYSCONFIG, l);
 
 	/* FUNCGATED */
-	REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
+	if (!cpu_is_omap44xx())
+		REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
 
 	/* L3 firewall setting: enable access to OCM RAM */
 	/* XXX this should be somewhere in plat-omap */
@@ -3104,7 +4469,7 @@ int dispc_init(void)
 
 	INIT_WORK(&dispc.error_work, dispc_error_worker);
 
-	dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
+	dispc_base = dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
 	if (!dispc.base) {
 		DSSERR("can't ioremap DISPC\n");
 		return -ENOMEM;
@@ -3151,7 +4516,8 @@ int dispc_setup_plane(enum omap_plane plane,
 		       enum omap_color_mode color_mode,
 		       bool ilace,
 		       enum omap_dss_rotation_type rotation_type,
-		       u8 rotation, bool mirror, u8 global_alpha)
+			u8 rotation, bool mirror, u8 global_alpha,
+			enum omap_channel channel, u32 puv_addr)
 {
 	int r = 0;
 
@@ -3173,9 +4539,243 @@ int dispc_setup_plane(enum omap_plane plane,
 			   color_mode, ilace,
 			   rotation_type,
 			   rotation, mirror,
-			   global_alpha);
+			   channel,
+			   global_alpha,
+			   puv_addr);
 
 	enable_clocks(0);
 
 	return r;
 }
+
+/* Writeback*/
+int dispc_setup_wb(struct writeback_cache_data *wb)
+{
+	unsigned long mir_x, mir_y;
+	unsigned long tiler_width, tiler_height;
+	u8 orientation = 0, rotation = 0, mirror = 0 ;
+	int ch_width, ch_height, out_ch_width, out_ch_height, scale_x, scale_y;
+	struct tiler_view_orient orient;
+	u32 paddr = wb->paddr;
+	u32 puv_addr = wb->puv_addr; /* relevant for NV12 format only */
+	u16 out_width = wb->width;
+	u16 out_height	= wb->height;
+	u16 width = wb->input_width;
+	u16 height = wb->input_height;
+
+	enum omap_color_mode color_mode = wb->color_mode;  /* output color */
+
+	u32 fifo_low = wb->fifo_low;
+	u32 fifo_high = wb->fifo_high;
+	enum omap_writeback_source			source = wb->source;
+
+	enum omap_plane plane = OMAP_DSS_WB;
+	enum omap_plane input_plane;
+
+	const int maxdownscale = 2;
+	bool three_taps = 0;
+	int cconv = 0;
+	s32 row_inc;
+	s32 pix_inc;
+	u16 frame_height = height;
+
+	DSSDBG("dispc_setup_wb");
+	DSSDBG("Maxds = %d", maxdownscale);
+	DSSDBG("out_width, width = %d, %d", (int) out_width, (int) width);
+	DSSDBG("out_height, height = %d, %d", (int) out_height, (int) height);
+
+	if (paddr == 0) {
+		printk("KERN_ERR dispc_setup_wb paddr NULL");
+		return -EINVAL;
+		}
+	{
+		/* validate color format and 5taps*/
+
+		if (out_width < width / maxdownscale ||
+		   out_width > width * 8){
+			printk("KERN_ERR dispc_setup_wb out_width not in range ");
+			return -EINVAL;
+		}
+		if (out_height < height / maxdownscale ||
+		   out_height > height * 8){
+			printk("KERN_ERR dispc_setup_wb out_height not in range ");
+			return -EINVAL;
+		}
+		switch (color_mode) {
+		case OMAP_DSS_COLOR_RGB16:
+		case OMAP_DSS_COLOR_RGB24P:
+		case OMAP_DSS_COLOR_RGB24U:
+		case OMAP_DSS_COLOR_ARGB16:
+		case OMAP_DSS_COLOR_ARGB32:
+		case OMAP_DSS_COLOR_RGBA32:
+		case OMAP_DSS_COLOR_RGBA12:
+		case OMAP_DSS_COLOR_XRGB12:
+		case OMAP_DSS_COLOR_ARGB16_1555:
+		case OMAP_DSS_COLOR_RGBX24_32_ALGN:
+		case OMAP_DSS_COLOR_XRGB15:
+			break;
+
+		case OMAP_DSS_COLOR_NV12:
+		case OMAP_DSS_COLOR_YUV2:
+		case OMAP_DSS_COLOR_UYVY:
+			cconv = 1;
+			break;
+
+		default:
+			return -EINVAL;
+		}
+	}
+
+	if (width > 1280)
+		three_taps = 1;
+
+/* we handle ONLY overlays as source yet, NOT Managers */
+/* TODO: remove this check once managers are accepted as source */
+	if (source > OMAP_WB_TV_MANAGER) {
+		input_plane = (source - 3);
+
+	DSSDBG("input pipeline is not an overlay manager so overlay %d is configured ", input_plane);
+	/* Set the channel out for input source: DISPC_VIDX_ATTRIBUTES[31:30] CHANNELOUT2 as WB (0x3)*/
+	REG_FLD_MOD(dispc_reg_att[input_plane], 0x3, 31, 30);
+	/* Set the channel out for input source: DISPC_VIDX_ATTRIBUTES[16] CHANNELOUT as LCD / WB (0x0)*/
+	REG_FLD_MOD(dispc_reg_att[input_plane], 0x0, 16, 16);
+
+	REG_FLD_MOD(dispc_reg_att[input_plane], 0x1, 10, 10);
+	REG_FLD_MOD(dispc_reg_att[input_plane], 0x1, 19, 19);
+	REG_FLD_MOD(dispc_reg_att[plane], source, 18, 16);
+
+	}
+
+	pix_inc = 0x1;
+	if ((paddr >= 0x60000000) && (paddr <= 0x7fffffff)) {
+		calc_tiler_row_rotation(rotation, width, frame_height,
+						color_mode, &row_inc);
+		orientation = calc_tiler_orientation(rotation, (u8)mirror);
+		/* get rotated top-left coordinate
+				(if rotation is applied before mirroring) */
+		memset(&orient, 0, sizeof(orient));
+		tiler_rotate_view(&orient, rotation * 90);
+
+		if (mirror) {
+			/* Horizontal mirroring */
+			if (rotation == 1 || rotation == 3)
+				mir_x = 1;
+			else
+				mir_y = 1;
+		} else {
+			mir_x = 0;
+			mir_y = 0;
+		}
+		orient.x_invert ^= mir_x;
+		orient.y_invert ^= mir_y;
+
+		if (orient.rotate_90 & 1) {
+			tiler_height = width;
+			tiler_width = height;
+		} else {
+			tiler_height = height;
+			tiler_width = width;
+		}
+
+		paddr = tiler_reorient_topleft(tiler_get_natural_addr((void *)paddr),
+				orient, tiler_width, tiler_height);
+
+		if (puv_addr)
+			puv_addr = tiler_reorient_topleft(
+					tiler_get_natural_addr((void *)puv_addr),
+					orient, tiler_width/2, tiler_height/2);
+			DSSDBG(
+				"rotated addresses: 0x%0x, 0x%0x\n",
+						paddr, puv_addr);
+			/* set BURSTTYPE if rotation is non-zero */
+			REG_FLD_MOD(dispc_reg_att[plane], 0x1, 8, 8);
+	} else
+	row_inc = 1;
+
+
+	_dispc_set_color_mode(plane, color_mode);
+
+	_dispc_set_plane_ba0(plane, paddr);
+	_dispc_set_plane_ba1(plane, paddr);
+	if (OMAP_DSS_COLOR_NV12 == color_mode) {
+		_dispc_set_plane_ba_uv0(plane, puv_addr);
+		_dispc_set_plane_ba_uv1(plane, puv_addr);
+	}
+	_dispc_set_row_inc(plane, row_inc);
+	_dispc_set_pix_inc(plane, pix_inc);
+
+	DSSDBG("%dx%d -> %p,%p %dx%d\n",
+	       width, height,
+	       (void *)paddr, (void *)puv_addr, out_width, out_height);
+
+	_dispc_set_pic_size(plane, width, height);
+	dispc_setup_plane_fifo(plane, fifo_low, fifo_high);
+
+	/* non interlaced */
+	ch_width = width;
+	ch_height = height;
+	out_ch_width = out_width;
+	out_ch_height = out_height;
+
+	/* account for output color decimation */
+	switch (color_mode) {
+	case OMAP_DSS_COLOR_NV12:
+		out_ch_height >>= 1;
+	case OMAP_DSS_COLOR_UYVY:
+	case OMAP_DSS_COLOR_YUV2:
+		out_ch_width >>= 1;
+	default:
+		;
+	}
+
+	/* account for input color decimation */
+	switch (wb->input_color_mode) {
+	case OMAP_DSS_COLOR_NV12:
+		ch_height >>= 1;
+	case OMAP_DSS_COLOR_UYVY:
+	case OMAP_DSS_COLOR_YUV2:
+		ch_width >>= 1;
+	default:
+		;
+	}
+
+	/* we must scale NV12 format */
+	scale_x = width != out_width || ch_width != out_ch_width;
+	scale_y = height != out_height || ch_height != out_ch_height;
+	_dispc_set_scaling(plane, width, height,
+			   out_width, out_height,
+			   0, three_taps, false, scale_x, scale_y);
+
+	if (out_ch_width != out_width) {
+		/* this is true for YUV formats */
+		_dispc_set_scaling_uv(plane, ch_width, ch_height,
+				      out_ch_width, out_ch_height, 0,
+				      three_taps, false, scale_x, scale_y);
+	} else {
+		/* set chroma resampling */
+		REG_FLD_MOD(DISPC_VID_ATTRIBUTES2(plane - 1), 0, 8, 8);
+	}
+
+	_dispc_set_vid_size(plane, out_width, out_height);
+	_dispc_set_vid_color_conv(plane, cconv);
+
+	pix_inc = dispc_read_reg(dispc_reg_att[plane]);
+	DSSDBG("vid[%d] attributes = %x\n", plane, pix_inc);
+
+	return 0;
+
+}
+
+void dispc_go_wb(void)
+{
+	enable_clocks(1);
+
+	if (REG_GET(DISPC_CONTROL2, 6, 6) == 1) {
+		DSSERR("GO bit not down for WB\n");
+		goto end;
+	}
+	REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
+    DSSDBG("dispc_go_wb\n");
+end:
+	enable_clocks(0);
+}
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
index 6a74ea116d29..05801825394e 100644
--- a/drivers/video/omap2/dss/display.c
+++ b/drivers/video/omap2/dss/display.c
@@ -29,6 +29,7 @@
 #include <linux/platform_device.h>
 
 #include <plat/display.h>
+#include <plat/cpu.h>
 #include "dss.h"
 
 static LIST_HEAD(display_list);
@@ -278,6 +279,55 @@ static ssize_t display_wss_store(struct device *dev,
 	return size;
 }
 
+static ssize_t display_edid_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct omap_dss_device *dssdev = to_dss_device(dev);
+
+
+		if (!dssdev->driver->get_edid)
+		return -ENOENT;
+	dssdev->driver->get_edid(dssdev);
+	return snprintf(buf, PAGE_SIZE, "EDID-Information");
+
+}
+static ssize_t display_custom_edid_timing_store(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct omap_dss_device *dssdev = to_dss_device(dev);
+	int val, code, mode;
+	val = simple_strtoul(buf, NULL, 0);
+	code = val / 10;
+	mode = val % 10;
+		if (!dssdev->driver->set_custom_edid_timing_code)
+			return -ENOENT;
+	dssdev->driver->set_custom_edid_timing_code(dssdev, code, mode);
+	return snprintf(buf, PAGE_SIZE, "EDID-Information %d mode % d code", mode, code);
+
+}
+
+static ssize_t display_hpd_enabled_store(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf, size_t size)
+{
+	struct omap_dss_device *dssdev = to_dss_device(dev);
+	bool enabled, r;
+
+	enabled = simple_strtoul(buf, NULL, 10);
+
+	if (enabled != (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)) {
+		if (enabled) {
+			r = dssdev->driver->hpd_enable(dssdev);
+			if (r)
+				return r;
+		} else {
+			dssdev->driver->disable(dssdev);
+		}
+	}
+
+	return size;
+}
+
 static DEVICE_ATTR(enabled, S_IRUGO|S_IWUSR,
 		display_enabled_show, display_enabled_store);
 static DEVICE_ATTR(update_mode, S_IRUGO|S_IWUSR,
@@ -292,6 +342,10 @@ static DEVICE_ATTR(mirror, S_IRUGO|S_IWUSR,
 		display_mirror_show, display_mirror_store);
 static DEVICE_ATTR(wss, S_IRUGO|S_IWUSR,
 		display_wss_show, display_wss_store);
+static DEVICE_ATTR(custom_edid_timing, S_IRUGO|S_IWUSR,
+		display_edid_show, display_custom_edid_timing_store);
+static DEVICE_ATTR(hpd_enabled, S_IRUGO|S_IWUSR,
+		NULL, display_hpd_enabled_store);
 
 static struct device_attribute *display_sysfs_attrs[] = {
 	&dev_attr_enabled,
@@ -301,6 +355,8 @@ static struct device_attribute *display_sysfs_attrs[] = {
 	&dev_attr_rotate,
 	&dev_attr_mirror,
 	&dev_attr_wss,
+	&dev_attr_custom_edid_timing,
+	&dev_attr_hpd_enabled,
 	NULL
 };
 
@@ -319,7 +375,11 @@ void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 	unsigned burst_size_bytes;
 
 	*burst_size = OMAP_DSS_BURST_16x32;
-	burst_size_bytes = 16 * 32 / 8;
+	if (cpu_is_omap44xx())
+		burst_size_bytes = 8 * 128 / 8; /* OMAP4: highest
+							burst size is 8x128*/
+	else
+		burst_size_bytes = 16 * 32 / 8;
 
 	*fifo_high = fifo_size - 1;
 	*fifo_low = fifo_size - burst_size_bytes;
@@ -342,7 +402,7 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev)
 			return 16;
 	case OMAP_DISPLAY_TYPE_VENC:
 	case OMAP_DISPLAY_TYPE_SDI:
-		return 24;
+	case OMAP_DISPLAY_TYPE_HDMI:
 		return 24;
 	default:
 		BUG();
@@ -365,6 +425,9 @@ bool dss_use_replication(struct omap_dss_device *dssdev,
 			(dssdev->panel.config & OMAP_DSS_LCD_TFT) == 0)
 		return false;
 
+	if (dssdev->type == OMAP_DISPLAY_TYPE_HDMI)
+		return false;
+
 	switch (dssdev->type) {
 	case OMAP_DISPLAY_TYPE_DPI:
 		bpp = dssdev->phy.dpi.data_lines;
@@ -392,7 +455,9 @@ void dss_init_device(struct platform_device *pdev,
 	int r;
 
 	switch (dssdev->type) {
+#ifdef CONFIG_OMAP2_DSS_DPI
 	case OMAP_DISPLAY_TYPE_DPI:
+#endif
 #ifdef CONFIG_OMAP2_DSS_RFBI
 	case OMAP_DISPLAY_TYPE_DBI:
 #endif
@@ -405,6 +470,9 @@ void dss_init_device(struct platform_device *pdev,
 #ifdef CONFIG_OMAP2_DSS_VENC
 	case OMAP_DISPLAY_TYPE_VENC:
 #endif
+#ifdef CONFIG_OMAP2_DSS_HDMI
+	case OMAP_DISPLAY_TYPE_HDMI:
+#endif
 		break;
 	default:
 		DSSERR("Support for display '%s' not compiled in.\n",
@@ -413,9 +481,11 @@ void dss_init_device(struct platform_device *pdev,
 	}
 
 	switch (dssdev->type) {
+#ifdef CONFIG_OMAP2_DSS_DPI
 	case OMAP_DISPLAY_TYPE_DPI:
 		r = dpi_init_display(dssdev);
 		break;
+#endif
 #ifdef CONFIG_OMAP2_DSS_RFBI
 	case OMAP_DISPLAY_TYPE_DBI:
 		r = rfbi_init_display(dssdev);
@@ -436,6 +506,11 @@ void dss_init_device(struct platform_device *pdev,
 		r = dsi_init_display(dssdev);
 		break;
 #endif
+#ifdef CONFIG_OMAP2_DSS_HDMI
+	case OMAP_DISPLAY_TYPE_HDMI:
+		r = hdmi_init_display(dssdev);
+		break;
+#endif
 	default:
 		BUG();
 	}
@@ -541,7 +616,10 @@ int dss_resume_all_devices(void)
 static int dss_disable_device(struct device *dev, void *data)
 {
 	struct omap_dss_device *dssdev = to_dss_device(dev);
-	dssdev->driver->disable(dssdev);
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)
+		dssdev->driver->disable(dssdev);
+
 	return 0;
 }
 
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 960e977a8bf0..971ee171a82d 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -40,25 +40,35 @@ static struct {
 } dpi;
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
+static int dpi_set_dsi_clk(int lcd_channel_ix, bool is_tft, unsigned long pck_req,
 		unsigned long *fck, int *lck_div, int *pck_div)
 {
 	struct dsi_clock_info dsi_cinfo;
 	struct dispc_clock_info dispc_cinfo;
 	int r;
-
-	r = dsi_pll_calc_clock_div_pck(is_tft, pck_req, &dsi_cinfo,
+	if (!cpu_is_omap44xx()) {
+		r = dsi_pll_calc_clock_div_pck(lcd_channel_ix, is_tft, pck_req, &dsi_cinfo,
 			&dispc_cinfo);
 	if (r)
 		return r;
-
-	r = dsi_pll_set_clock_div(&dsi_cinfo);
+	} else {
+		dispc_cinfo.lck_div = 1;
+		dispc_cinfo.pck_div = 4;
+		dsi_cinfo.regn = 19;
+		dsi_cinfo.regm = 150;
+		dsi_cinfo.regm3 = 4;
+		dsi_cinfo.regm4 = 4;
+		dsi_cinfo.use_dss2_fck = true;
+		dsi_cinfo.highfreq = 0;
+		dsi_calc_clock_rates(&dsi_cinfo);
+	}
+	r = dsi_pll_set_clock_div(lcd_channel_ix, &dsi_cinfo);
 	if (r)
 		return r;
 
 	dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
 
-	r = dispc_set_clock_div(&dispc_cinfo);
+	r = dispc_set_clock_div(lcd_channel_ix, &dispc_cinfo);
 	if (r)
 		return r;
 
@@ -69,13 +79,15 @@ static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
 	return 0;
 }
 #else
-static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
+static int dpi_set_dispc_clk(int lcd_channel_ix, bool is_tft, unsigned long pck_req,
 		unsigned long *fck, int *lck_div, int *pck_div)
 {
 	struct dss_clock_info dss_cinfo;
 	struct dispc_clock_info dispc_cinfo;
 	int r;
 
+	if (cpu_is_omap44xx()) /*TODO Check this */
+	return 0;
 	r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
 	if (r)
 		return r;
@@ -84,7 +96,7 @@ static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
 	if (r)
 		return r;
 
-	r = dispc_set_clock_div(&dispc_cinfo);
+	r = dispc_set_clock_div(lcd_channel_ix, &dispc_cinfo);
 	if (r)
 		return r;
 
@@ -103,20 +115,28 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
 	unsigned long fck;
 	unsigned long pck;
 	bool is_tft;
-	int r = 0;
+	int r = 0, lcd_channel_ix = 0;
+
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
+		lcd_channel_ix = 1;
 
 	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 
-	dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
-			dssdev->panel.acb);
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
+		dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD2, dssdev->panel.config,
+				dssdev->panel.acbi, dssdev->panel.acb);
+	else
+		dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD, dssdev->panel.config,
+				dssdev->panel.acbi, dssdev->panel.acb);
+
 
 	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-	r = dpi_set_dsi_clk(is_tft, t->pixel_clock * 1000,
+	r = dpi_set_dsi_clk(lcd_channel_ix, is_tft, t->pixel_clock * 1000,
 			&fck, &lck_div, &pck_div);
 #else
-	r = dpi_set_dispc_clk(is_tft, t->pixel_clock * 1000,
+	r = dpi_set_dispc_clk(lcd_channel_ix, is_tft, t->pixel_clock * 1000,
 			&fck, &lck_div, &pck_div);
 #endif
 	if (r)
@@ -132,8 +152,15 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
 		t->pixel_clock = pck;
 	}
 
-	dispc_set_lcd_timings(t);
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
+		dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD2, t);
+	else
+		dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD, t);
 
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
+err1:
+	dsi_pll_uninit(lcd_channel_ix);
+#endif
 err0:
 	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 	return r;
@@ -145,17 +172,51 @@ static int dpi_basic_init(struct omap_dss_device *dssdev)
 
 	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
 
-	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
-	dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
-			OMAP_DSS_LCD_DISPLAY_STN);
-	dispc_set_tft_data_lines(dssdev->phy.dpi.data_lines);
-
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) {
+		dispc_set_parallel_interface_mode(OMAP_DSS_CHANNEL_LCD2,
+				OMAP_DSS_PARALLELMODE_BYPASS);
+		dispc_set_lcd_display_type(OMAP_DSS_CHANNEL_LCD2,
+				is_tft ? OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
+		dispc_set_tft_data_lines(OMAP_DSS_CHANNEL_LCD2,
+				dssdev->phy.dpi.data_lines);
+
+	} else {
+		dispc_set_parallel_interface_mode(OMAP_DSS_CHANNEL_LCD,
+				OMAP_DSS_PARALLELMODE_BYPASS);
+		dispc_set_lcd_display_type(OMAP_DSS_CHANNEL_LCD,
+				is_tft ? OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
+		dispc_set_tft_data_lines(OMAP_DSS_CHANNEL_LCD,
+				dssdev->phy.dpi.data_lines);
+	}
 	return 0;
 }
 
+/*This one needs to be to set the ovl info to dirty*/
+static void dpi_start_auto_update(struct omap_dss_device *dssdev)
+
+{
+	int i;
+	DSSDBG("starting auto update\n");
+	for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+		struct omap_overlay *ovl;
+		ovl = omap_dss_get_overlay(i);
+		if (ovl->manager == dssdev->manager)
+			ovl->info_dirty = true;
+			printk(KERN_ERR "ovl[%d]->manager = %s", i, ovl->manager->name);
+	}
+	dssdev->manager->apply(dssdev->manager);
+}
+
 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
 {
 	int r;
+	int lcd_channel_ix = 1;
+
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) {
+		printk("Lcd channel index 1");
+		lcd_channel_ix = 1;
+	} else
+		lcd_channel_ix = 0;
 
 	r = omap_dss_start_device(dssdev);
 	if (r) {
@@ -187,13 +248,16 @@ int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
 
 	mdelay(2);
 
+	if (cpu_is_omap44xx())
+		dpi_start_auto_update(dssdev);
+
 	dssdev->manager->enable(dssdev->manager);
 
 	return 0;
 
 err4:
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-	dsi_pll_uninit();
+	dsi_pll_uninit(lcd_channel_ix);
 err3:
 	dss_clk_disable(DSS_CLK_FCK2);
 #endif
@@ -210,11 +274,16 @@ EXPORT_SYMBOL(omapdss_dpi_display_enable);
 
 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
 {
+	int lcd_channel_ix = 0;
+
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
+		lcd_channel_ix = 1;
+
 	dssdev->manager->disable(dssdev->manager);
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
 	dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
-	dsi_pll_uninit();
+	dsi_pll_uninit(lcd_channel_ix);
 	dss_clk_disable(DSS_CLK_FCK2);
 #endif
 
@@ -234,7 +303,10 @@ void dpi_set_timings(struct omap_dss_device *dssdev,
 	dssdev->panel.timings = *timings;
 	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
 		dpi_set_mode(dssdev);
-		dispc_go(OMAP_DSS_CHANNEL_LCD);
+		if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
+			dispc_go(OMAP_DSS_CHANNEL_LCD2);
+		else
+			dispc_go(OMAP_DSS_CHANNEL_LCD);
 	}
 }
 EXPORT_SYMBOL(dpi_set_timings);
@@ -243,11 +315,14 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
 			struct omap_video_timings *timings)
 {
 	bool is_tft;
-	int r;
+	int r = 0, lcd_channel_ix = 0;
 	int lck_div, pck_div;
 	unsigned long fck;
 	unsigned long pck;
 
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2)
+		lcd_channel_ix = 1;
+
 	if (!dispc_lcd_timings_ok(timings))
 		return -EINVAL;
 
@@ -260,7 +335,7 @@ int dpi_check_timings(struct omap_dss_device *dssdev,
 	{
 		struct dsi_clock_info dsi_cinfo;
 		struct dispc_clock_info dispc_cinfo;
-		r = dsi_pll_calc_clock_div_pck(is_tft,
+		r = dsi_pll_calc_clock_div_pck(lcd_channel_ix, is_tft,
 				timings->pixel_clock * 1000,
 				&dsi_cinfo, &dispc_cinfo);
 
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 3af207b2bde3..2602a6617e2f 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -42,7 +42,13 @@
 /*#define VERBOSE_IRQ*/
 #define DSI_CATCH_MISSING_TE
 
+#ifndef CONFIG_ARCH_OMAP4
 #define DSI_BASE		0x4804FC00
+#else
+#define DSI_BASE		0x58004000
+#define DSI2_BASE		0x58005000
+
+#endif
 
 struct dsi_reg { u16 idx; };
 
@@ -92,6 +98,13 @@ struct dsi_reg { u16 idx; };
 #define DSI_DSIPHY_CFG2			DSI_REG(0x200 + 0x0008)
 #define DSI_DSIPHY_CFG5			DSI_REG(0x200 + 0x0014)
 
+/* DSI Rev 3.0 Registers */
+
+#define DSI_DSIPHY_CFG8			DSI_REG(0x200 + 0x0020)
+#define DSI_DSIPHY_CFG9			DSI_REG(0x200 + 0x0024)
+#define DSI_DSIPHY_CFG12		DSI_REG(0x200 + 0x0030)
+#define DSI_DSIPHY_CFG14		DSI_REG(0x200 + 0x0038)
+
 /* DSI_PLL_CTRL_SCP */
 
 #define DSI_PLL_CONTROL			DSI_REG(0x300 + 0x0000)
@@ -100,11 +113,11 @@ struct dsi_reg { u16 idx; };
 #define DSI_PLL_CONFIGURATION1		DSI_REG(0x300 + 0x000C)
 #define DSI_PLL_CONFIGURATION2		DSI_REG(0x300 + 0x0010)
 
-#define REG_GET(idx, start, end) \
-	FLD_GET(dsi_read_reg(idx), start, end)
+#define REG_GET(no, idx, start, end) \
+	FLD_GET(dsi_read_reg(no, idx), start, end)
 
-#define REG_FLD_MOD(idx, val, start, end) \
-	dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
+#define REG_FLD_MOD(no, idx, val, start, end) \
+	dsi_write_reg(no, idx, FLD_MOD(dsi_read_reg(no, idx), val, start, end))
 
 /* Global interrupts */
 #define DSI_IRQ_VC0		(1 << 0)
@@ -212,7 +225,7 @@ struct dsi_irq_stats {
 	unsigned cio_irqs[32];
 };
 
-static struct
+static struct dsi_struct
 {
 	void __iomem	*base;
 
@@ -224,6 +237,7 @@ static struct
 		enum dsi_vc_mode mode;
 		struct omap_dss_device *dssdev;
 		enum fifo_size fifo_size;
+		int dest_per;
 	} vc[4];
 
 	struct mutex lock;
@@ -237,7 +251,7 @@ static struct
 	struct dsi_update_region update_region;
 
 	bool te_enabled;
-
+	bool use_ext_te;
 	struct work_struct framedone_work;
 	void (*framedone_callback)(int, void *);
 	void *framedone_data;
@@ -265,21 +279,29 @@ static struct
 	spinlock_t irq_stats_lock;
 	struct dsi_irq_stats irq_stats;
 #endif
-} dsi;
+} dsi1, dsi2;
 
 #ifdef DEBUG
 static unsigned int dsi_perf;
 module_param_named(dsi_perf, dsi_perf, bool, 0644);
 #endif
 
-static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
+static inline void dsi_write_reg(enum omap_dsi_index ix,
+		const struct dsi_reg idx, u32 val)
 {
-	__raw_writel(val, dsi.base + idx.idx);
+	if (ix == DSI1)
+		__raw_writel(val, dsi1.base + idx.idx);
+	else
+		__raw_writel(val, dsi2.base + idx.idx);
 }
 
-static inline u32 dsi_read_reg(const struct dsi_reg idx)
+static inline u32 dsi_read_reg(enum omap_dsi_index ix,
+		const struct dsi_reg idx)
 {
-	return __raw_readl(dsi.base + idx.idx);
+	if (ix == DSI1)
+		return __raw_readl(dsi1.base + idx.idx);
+	else
+		return __raw_readl(dsi2.base + idx.idx);
 }
 
 
@@ -291,29 +313,39 @@ void dsi_restore_context(void)
 {
 }
 
-void dsi_bus_lock(void)
+void dsi_bus_lock(enum omap_dsi_index ix)
 {
-	down(&dsi.bus_lock);
+	if (ix == DSI1)
+		down(&dsi1.bus_lock);
+	else
+		down(&dsi2.bus_lock);
 }
 EXPORT_SYMBOL(dsi_bus_lock);
 
-void dsi_bus_unlock(void)
+void dsi_bus_unlock(enum omap_dsi_index ix)
 {
-	up(&dsi.bus_lock);
+	if (ix == DSI1)
+		up(&dsi1.bus_lock);
+	else
+		up(&dsi2.bus_lock);
 }
 EXPORT_SYMBOL(dsi_bus_unlock);
 
-static bool dsi_bus_is_locked(void)
+static bool dsi_bus_is_locked(enum omap_dsi_index ix)
 {
-	return dsi.bus_lock.count == 0;
+	if (ix == DSI1)
+		return dsi1.bus_lock.count == 0;
+	else
+		return dsi2.bus_lock.count == 0;
 }
 
-static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
+static inline int wait_for_bit_change(enum omap_dsi_index ix,
+	const struct dsi_reg idx, int bitnum,
 		int value)
 {
 	int t = 100000;
 
-	while (REG_GET(idx, bitnum, bitnum) != value) {
+	while (REG_GET(ix, idx, bitnum, bitnum) != value) {
 		if (--t == 0)
 			return !value;
 	}
@@ -322,42 +354,49 @@ static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
 }
 
 #ifdef DEBUG
-static void dsi_perf_mark_setup(void)
+static void dsi_perf_mark_setup(enum omap_dsi_index ix)
 {
-	dsi.perf_setup_time = ktime_get();
+	struct dsi_struct *p_dsi;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	p_dsi->perf_setup_time = ktime_get();
 }
 
-static void dsi_perf_mark_start(void)
+static void dsi_perf_mark_start(enum omap_dsi_index ix)
 {
-	dsi.perf_start_time = ktime_get();
+	struct dsi_struct *p_dsi;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	p_dsi->perf_start_time = ktime_get();
 }
 
-static void dsi_perf_show(const char *name)
+static void dsi_perf_show(enum omap_dsi_index ix,
+	const char *name)
 {
 	ktime_t t, setup_time, trans_time;
 	u32 total_bytes;
 	u32 setup_us, trans_us, total_us;
+	struct dsi_struct *p_dsi;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
 	if (!dsi_perf)
 		return;
 
 	t = ktime_get();
 
-	setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
+	setup_time = ktime_sub(p_dsi->perf_start_time, p_dsi->perf_setup_time);
 	setup_us = (u32)ktime_to_us(setup_time);
 	if (setup_us == 0)
 		setup_us = 1;
 
-	trans_time = ktime_sub(t, dsi.perf_start_time);
+	trans_time = ktime_sub(t, p_dsi->perf_start_time);
 	trans_us = (u32)ktime_to_us(trans_time);
 	if (trans_us == 0)
 		trans_us = 1;
 
 	total_us = setup_us + trans_us;
 
-	total_bytes = dsi.update_region.w *
-		dsi.update_region.h *
-		dsi.update_region.device->ctrl.pixel_size / 8;
+	total_bytes = p_dsi->update_region.w *
+		p_dsi->update_region.h *
+		p_dsi->update_region.device->ctrl.pixel_size / 8;
 
 	printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 			"%u bytes, %u kbytes/sec\n",
@@ -370,9 +409,9 @@ static void dsi_perf_show(const char *name)
 			total_bytes * 1000 / total_us);
 }
 #else
-#define dsi_perf_mark_setup()
-#define dsi_perf_mark_start()
-#define dsi_perf_show(x)
+#define dsi_perf_mark_setup(x)
+#define dsi_perf_mark_start(x)
+#define dsi_perf_show(x, y)
 #endif
 
 static void print_irq_status(u32 status)
@@ -470,47 +509,56 @@ static void print_irq_status_cio(u32 status)
 
 static int debug_irq;
 
-/* called from dss */
-void dsi_irq_handler(void)
+/* called from dss in OMAP3, in OMAP4 there is a dedicated
+* interrupt line for DSI */
+irqreturn_t dsi_irq_handler(int irq, void *arg)
+
 {
 	u32 irqstatus, vcstatus, ciostatus;
 	int i;
+	enum omap_dsi_index ix = DSI1;
+	struct dsi_struct *p_dsi;
+
+	if (cpu_is_omap44xx() && irq == OMAP44XX_IRQ_DSS_DSI2)
+		ix = DSI2;
 
-	irqstatus = dsi_read_reg(DSI_IRQSTATUS);
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	irqstatus = dsi_read_reg(ix, DSI_IRQSTATUS);
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-	spin_lock(&dsi.irq_stats_lock);
-	dsi.irq_stats.irq_count++;
-	dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
+	spin_lock(&p_dsi->irq_stats_lock);
+	p_dsi->irq_stats.irq_count++;
+	dss_collect_irq_stats(irqstatus, p_dsi->irq_stats.dsi_irqs);
 #endif
 
 	if (irqstatus & DSI_IRQ_ERROR_MASK) {
 		DSSERR("DSI error, irqstatus %x\n", irqstatus);
 		print_irq_status(irqstatus);
-		spin_lock(&dsi.errors_lock);
-		dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
-		spin_unlock(&dsi.errors_lock);
+		spin_lock(&p_dsi->errors_lock);
+		p_dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
+		spin_unlock(&p_dsi->errors_lock);
 	} else if (debug_irq) {
 		print_irq_status(irqstatus);
 	}
 
 #ifdef DSI_CATCH_MISSING_TE
 	if (irqstatus & DSI_IRQ_TE_TRIGGER)
-		del_timer(&dsi.te_timer);
+		del_timer(&p_dsi->te_timer);
 #endif
 
 	for (i = 0; i < 4; ++i) {
 		if ((irqstatus & (1<<i)) == 0)
 			continue;
 
-		vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
+		vcstatus = dsi_read_reg(ix, DSI_VC_IRQSTATUS(i));
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-		dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
+		dss_collect_irq_stats(vcstatus, p_dsi->irq_stats.vc_irqs[i]);
 #endif
 
 		if (vcstatus & DSI_VC_IRQ_BTA)
-			complete(&dsi.bta_completion);
+			complete(&p_dsi->bta_completion);
 
 		if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
 			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
@@ -520,106 +568,110 @@ void dsi_irq_handler(void)
 			print_irq_status_vc(i, vcstatus);
 		}
 
-		dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
+		dsi_write_reg(ix, DSI_VC_IRQSTATUS(i), vcstatus);
 		/* flush posted write */
-		dsi_read_reg(DSI_VC_IRQSTATUS(i));
+		dsi_read_reg(ix, DSI_VC_IRQSTATUS(i));
 	}
 
 	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
-		ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
+		ciostatus = dsi_read_reg(ix, DSI_COMPLEXIO_IRQ_STATUS);
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-		dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
+		dss_collect_irq_stats(ciostatus, p_dsi->irq_stats.cio_irqs);
 #endif
 
-		dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
+		dsi_write_reg(ix, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 		/* flush posted write */
-		dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
+		dsi_read_reg(ix, DSI_COMPLEXIO_IRQ_STATUS);
 
 		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 		print_irq_status_cio(ciostatus);
 	}
 
-	dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
+	dsi_write_reg(ix, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 	/* flush posted write */
-	dsi_read_reg(DSI_IRQSTATUS);
+	dsi_read_reg(ix, DSI_IRQSTATUS);
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-	spin_unlock(&dsi.irq_stats_lock);
+	spin_unlock(&p_dsi->irq_stats_lock);
 #endif
+	return IRQ_HANDLED;
 }
 
-
-static void _dsi_initialize_irq(void)
+static void _dsi_initialize_irq(enum omap_dsi_index ix)
 {
 	u32 l;
 	int i;
 
 	/* disable all interrupts */
-	dsi_write_reg(DSI_IRQENABLE, 0);
+	dsi_write_reg(ix, DSI_IRQENABLE, 0);
 	for (i = 0; i < 4; ++i)
-		dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
-	dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
+		dsi_write_reg(ix, DSI_VC_IRQENABLE(i), 0);
+	dsi_write_reg(ix, DSI_COMPLEXIO_IRQ_ENABLE, 0);
 
 	/* clear interrupt status */
-	l = dsi_read_reg(DSI_IRQSTATUS);
-	dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
+	l = dsi_read_reg(ix, DSI_IRQSTATUS);
+	dsi_write_reg(ix, DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
 
 	for (i = 0; i < 4; ++i) {
-		l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
-		dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
+		l = dsi_read_reg(ix, DSI_VC_IRQSTATUS(i));
+		dsi_write_reg(ix, DSI_VC_IRQSTATUS(i), l);
 	}
 
-	l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
-	dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
+	l = dsi_read_reg(ix, DSI_COMPLEXIO_IRQ_STATUS);
+	dsi_write_reg(ix, DSI_COMPLEXIO_IRQ_STATUS, l);
 
 	/* enable error irqs */
 	l = DSI_IRQ_ERROR_MASK;
 #ifdef DSI_CATCH_MISSING_TE
 	l |= DSI_IRQ_TE_TRIGGER;
 #endif
-	dsi_write_reg(DSI_IRQENABLE, l);
+	dsi_write_reg(ix, DSI_IRQENABLE, l);
 
 	l = DSI_VC_IRQ_ERROR_MASK;
 	for (i = 0; i < 4; ++i)
-		dsi_write_reg(DSI_VC_IRQENABLE(i), l);
+		dsi_write_reg(ix, DSI_VC_IRQENABLE(i), l);
 
 	/* XXX zonda responds incorrectly, causing control error:
 	   Exit from LP-ESC mode to LP11 uses wrong transition states on the
 	   data lines LP0 and LN0. */
-	dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
+	dsi_write_reg(ix, DSI_COMPLEXIO_IRQ_ENABLE,
 			-1 & (~DSI_CIO_IRQ_ERRCONTROL2));
 }
 
-static u32 dsi_get_errors(void)
+static u32 dsi_get_errors(enum omap_dsi_index ix)
 {
 	unsigned long flags;
 	u32 e;
-	spin_lock_irqsave(&dsi.errors_lock, flags);
-	e = dsi.errors;
-	dsi.errors = 0;
-	spin_unlock_irqrestore(&dsi.errors_lock, flags);
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	spin_lock_irqsave(&p_dsi->errors_lock, flags);
+	e = p_dsi->errors;
+	p_dsi->errors = 0;
+	spin_unlock_irqrestore(&p_dsi->errors_lock, flags);
 	return e;
 }
 
-static void dsi_vc_enable_bta_irq(int channel)
+static void dsi_vc_enable_bta_irq(enum omap_dsi_index ix,
+	int channel)
 {
 	u32 l;
 
-	dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
+	dsi_write_reg(ix, DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
 
-	l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
+	l = dsi_read_reg(ix, DSI_VC_IRQENABLE(channel));
 	l |= DSI_VC_IRQ_BTA;
-	dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
+	dsi_write_reg(ix, DSI_VC_IRQENABLE(channel), l);
 }
 
-static void dsi_vc_disable_bta_irq(int channel)
+static void dsi_vc_disable_bta_irq(enum omap_dsi_index ix,
+	int channel)
 {
 	u32 l;
 
-	l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
+	l = dsi_read_reg(ix, DSI_VC_IRQENABLE(channel));
 	l &= ~DSI_VC_IRQ_BTA;
-	dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
+	dsi_write_reg(ix, DSI_VC_IRQENABLE(channel), l);
 }
 
 /* DSI func clock. this could also be DSI2_PLL_FCLK */
@@ -632,21 +684,24 @@ static inline void enable_clocks(bool enable)
 }
 
 /* source clock for DSI PLL. this could also be PCLKFREE */
-static inline void dsi_enable_pll_clock(bool enable)
+static inline void dsi_enable_pll_clock(enum omap_dsi_index ix,
+	bool enable)
 {
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
 	if (enable)
 		dss_clk_enable(DSS_CLK_FCK2);
 	else
 		dss_clk_disable(DSS_CLK_FCK2);
 
-	if (enable && dsi.pll_locked) {
-		if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
+	if (enable && p_dsi->pll_locked) {
+		if (wait_for_bit_change(ix, DSI_PLL_STATUS, 1, 1) != 1)
 			DSSERR("cannot lock PLL when enabling clocks\n");
 	}
 }
 
 #ifdef DEBUG
-static void _dsi_print_reset_status(void)
+static void _dsi_print_reset_status(enum omap_dsi_index ix)
 {
 	u32 l;
 
@@ -656,17 +711,17 @@ static void _dsi_print_reset_status(void)
 	/* A dummy read using the SCP interface to any DSIPHY register is
 	 * required after DSIPHY reset to complete the reset of the DSI complex
 	 * I/O. */
-	l = dsi_read_reg(DSI_DSIPHY_CFG5);
+	l = dsi_read_reg(ix, DSI_DSIPHY_CFG5);
 
 	printk(KERN_DEBUG "DSI resets: ");
 
-	l = dsi_read_reg(DSI_PLL_STATUS);
+	l = dsi_read_reg(ix, DSI_PLL_STATUS);
 	printk("PLL (%d) ", FLD_GET(l, 0, 0));
 
-	l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
+	l = dsi_read_reg(ix, DSI_COMPLEXIO_CFG1);
 	printk("CIO (%d) ", FLD_GET(l, 29, 29));
 
-	l = dsi_read_reg(DSI_DSIPHY_CFG5);
+	l = dsi_read_reg(ix, DSI_DSIPHY_CFG5);
 	printk("PHY (%x, %d, %d, %d)\n",
 			FLD_GET(l, 28, 26),
 			FLD_GET(l, 29, 29),
@@ -674,17 +729,18 @@ static void _dsi_print_reset_status(void)
 			FLD_GET(l, 31, 31));
 }
 #else
-#define _dsi_print_reset_status()
+#define _dsi_print_reset_status(ix)
 #endif
 
-static inline int dsi_if_enable(bool enable)
+static inline int dsi_if_enable(enum omap_dsi_index ix,
+	bool enable)
 {
 	DSSDBG("dsi_if_enable(%d)\n", enable);
 
 	enable = enable ? 1 : 0;
-	REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
+	REG_FLD_MOD(ix, DSI_CTRL, enable, 0, 0); /* IF_EN */
 
-	if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
+	if (wait_for_bit_change(ix, DSI_CTRL, 0, enable) != enable) {
 			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
 			return -EIO;
 	}
@@ -692,22 +748,25 @@ static inline int dsi_if_enable(bool enable)
 	return 0;
 }
 
-unsigned long dsi_get_dsi1_pll_rate(void)
+unsigned long dsi_get_dsi1_pll_rate(enum omap_dsi_index ix)
 {
-	return dsi.current_cinfo.dsi1_pll_fclk;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	return p_dsi->current_cinfo.dsi1_pll_fclk;
 }
 
-static unsigned long dsi_get_dsi2_pll_rate(void)
+static unsigned long dsi_get_dsi2_pll_rate(enum omap_dsi_index ix)
 {
-	return dsi.current_cinfo.dsi2_pll_fclk;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	return p_dsi->current_cinfo.dsi2_pll_fclk;
 }
 
-static unsigned long dsi_get_txbyteclkhs(void)
+static unsigned long dsi_get_txbyteclkhs(enum omap_dsi_index ix)
 {
-	return dsi.current_cinfo.clkin4ddr / 16;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	return p_dsi->current_cinfo.clkin4ddr / 16;
 }
 
-static unsigned long dsi_fclk_rate(void)
+static unsigned long dsi_fclk_rate(enum omap_dsi_index ix)
 {
 	unsigned long r;
 
@@ -716,7 +775,7 @@ static unsigned long dsi_fclk_rate(void)
 		r = dss_clk_get_rate(DSS_CLK_FCK1);
 	} else {
 		/* DSI FCLK source is DSI2_PLL_FCLK */
-		r = dsi_get_dsi2_pll_rate();
+		r = dsi_get_dsi2_pll_rate(ix);
 	}
 
 	return r;
@@ -727,23 +786,28 @@ static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
 	unsigned long dsi_fclk;
 	unsigned lp_clk_div;
 	unsigned long lp_clk;
+	struct dsi_struct *p_dsi;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
 	lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
 
 	if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
 		return -EINVAL;
 
-	dsi_fclk = dsi_fclk_rate();
+	dsi_fclk = dsi_fclk_rate(ix);
 
 	lp_clk = dsi_fclk / 2 / lp_clk_div;
 
 	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
-	dsi.current_cinfo.lp_clk = lp_clk;
-	dsi.current_cinfo.lp_clk_div = lp_clk_div;
+	p_dsi->current_cinfo.lp_clk = lp_clk;
+	p_dsi->current_cinfo.lp_clk_div = lp_clk_div;
 
-	REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0);   /* LP_CLK_DIVISOR */
+	REG_FLD_MOD(ix, DSI_CLK_CTRL, lp_clk_div, 12, 0);   /* LP_CLK_DIVISOR */
 
-	REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
+	REG_FLD_MOD(ix, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
 			21, 21);		/* LP_RX_SYNCHRO_ENABLE */
 
 	return 0;
@@ -757,14 +821,15 @@ enum dsi_pll_power_state {
 	DSI_PLL_POWER_ON_DIV	= 0x3,
 };
 
-static int dsi_pll_power(enum dsi_pll_power_state state)
+static int dsi_pll_power(enum omap_dsi_index ix,
+	enum dsi_pll_power_state state)
 {
 	int t = 0;
 
-	REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30);	/* PLL_PWR_CMD */
+	REG_FLD_MOD(ix, DSI_CLK_CTRL, state, 31, 30);	/* PLL_PWR_CMD */
 
 	/* PLL_PWR_STATUS */
-	while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
+	while (FLD_GET(dsi_read_reg(ix, DSI_CLK_CTRL), 29, 28) != state) {
 		if (++t > 1000) {
 			DSSERR("Failed to set DSI PLL power mode to %d\n",
 					state);
@@ -777,7 +842,7 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
 }
 
 /* calculate clock rates using dividers in cinfo */
-static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
+int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
 {
 	if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
 		return -EINVAL;
@@ -793,11 +858,12 @@ static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
 
 	if (cinfo->use_dss2_fck) {
 		cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
+		cinfo->clkin = 38400000;
 		/* XXX it is unclear if highfreq should be used
 		 * with DSS2_FCK source also */
 		cinfo->highfreq = 0;
 	} else {
-		cinfo->clkin = dispc_pclk_rate();
+		cinfo->clkin = dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD);
 
 		if (cinfo->clkin < 32000000)
 			cinfo->highfreq = 0;
@@ -828,7 +894,8 @@ static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
 	return 0;
 }
 
-int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
+int dsi_pll_calc_clock_div_pck(enum omap_dsi_index ix,
+		bool is_tft, unsigned long req_pck,
 		struct dsi_clock_info *dsi_cinfo,
 		struct dispc_clock_info *dispc_cinfo)
 {
@@ -837,13 +904,14 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
 	int min_fck_per_pck;
 	int match = 0;
 	unsigned long dss_clk_fck2;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
 	dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
 
-	if (req_pck == dsi.cache_req_pck &&
-			dsi.cache_cinfo.clkin == dss_clk_fck2) {
+	if (req_pck == p_dsi->cache_req_pck &&
+			p_dsi->cache_cinfo.clkin == dss_clk_fck2) {
 		DSSDBG("DSI clock info found from cache\n");
-		*dsi_cinfo = dsi.cache_cinfo;
+		*dsi_cinfo = p_dsi->cache_cinfo;
 		dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
 				dispc_cinfo);
 		return 0;
@@ -954,30 +1022,32 @@ found:
 	if (dispc_cinfo)
 		*dispc_cinfo = best_dispc;
 
-	dsi.cache_req_pck = req_pck;
-	dsi.cache_clk_freq = 0;
-	dsi.cache_cinfo = best;
+	p_dsi->cache_req_pck = req_pck;
+	p_dsi->cache_clk_freq = 0;
+	p_dsi->cache_cinfo = best;
 
 	return 0;
 }
 
-int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
+int dsi_pll_set_clock_div(enum omap_dsi_index ix,
+	struct dsi_clock_info *cinfo)
 {
 	int r = 0;
 	u32 l;
-	int f;
+	int f = 0;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
 	DSSDBGF();
 
-	dsi.current_cinfo.fint = cinfo->fint;
-	dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
-	dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
-	dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
+	p_dsi->current_cinfo.fint = cinfo->fint;
+	p_dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
+	p_dsi->current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
+	p_dsi->current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
 
-	dsi.current_cinfo.regn = cinfo->regn;
-	dsi.current_cinfo.regm = cinfo->regm;
-	dsi.current_cinfo.regm3 = cinfo->regm3;
-	dsi.current_cinfo.regm4 = cinfo->regm4;
+	p_dsi->current_cinfo.regn = cinfo->regn;
+	p_dsi->current_cinfo.regm = cinfo->regm;
+	p_dsi->current_cinfo.regm3 = cinfo->regm3;
+	p_dsi->current_cinfo.regm4 = cinfo->regm4;
 
 	DSSDBG("DSI Fint %ld\n", cinfo->fint);
 
@@ -1004,32 +1074,39 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
 	DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
 			cinfo->regm4, cinfo->dsi2_pll_fclk);
 
-	REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
+	REG_FLD_MOD(ix, DSI_PLL_CONTROL, 0,
+			0, 0); /* DSI_PLL_AUTOMODE = manual */
 
-	l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
+	l = dsi_read_reg(ix, DSI_PLL_CONFIGURATION1);
 	l = FLD_MOD(l, 1, 0, 0);		/* DSI_PLL_STOPMODE */
-	l = FLD_MOD(l, cinfo->regn - 1, 7, 1);	/* DSI_PLL_REGN */
-	l = FLD_MOD(l, cinfo->regm, 18, 8);	/* DSI_PLL_REGM */
+	l = FLD_MOD(l, cinfo->regn - 1, (cpu_is_omap44xx()) ? 8 : 7,
+			1);		/* DSI_PLL_REGN */
+	l = FLD_MOD(l, cinfo->regm, (cpu_is_omap44xx()) ? 20 : 18,
+			(cpu_is_omap44xx()) ? 9 : 8);	/* DSI_PLL_REGM */
 	l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
-			22, 19);		/* DSI_CLOCK_DIV */
+			(cpu_is_omap44xx()) ? 25 : 22,
+			(cpu_is_omap44xx()) ? 21 : 19);	/* DSI_CLOCK_DIV */
 	l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
-			26, 23);		/* DSIPROTO_CLOCK_DIV */
-	dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
+			(cpu_is_omap44xx()) ? 30 : 26,
+			(cpu_is_omap44xx()) ? 26 : 23);	/* DSIPROTO_CLOCK_DIV */
+	dsi_write_reg(ix, DSI_PLL_CONFIGURATION1, l);
 
 	BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
-	if (cinfo->fint < 1000000)
-		f = 0x3;
-	else if (cinfo->fint < 1250000)
-		f = 0x4;
-	else if (cinfo->fint < 1500000)
-		f = 0x5;
-	else if (cinfo->fint < 1750000)
-		f = 0x6;
-	else
-		f = 0x7;
-
-	l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
-	l = FLD_MOD(l, f, 4, 1);		/* DSI_PLL_FREQSEL */
+	if (!cpu_is_omap44xx()) {
+		if (cinfo->fint < 1000000)
+			f = 0x3;
+		else if (cinfo->fint < 1250000)
+			f = 0x4;
+		else if (cinfo->fint < 1500000)
+			f = 0x5;
+		else if (cinfo->fint < 1750000)
+			f = 0x6;
+		else
+			f = 0x7;
+	}
+	l = dsi_read_reg(ix, DSI_PLL_CONFIGURATION2);
+	if (!cpu_is_omap44xx())
+		l = FLD_MOD(l, f, 4, 1);		/* DSI_PLL_FREQSEL */
 	l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
 			11, 11);		/* DSI_PLL_CLKSEL */
 	l = FLD_MOD(l, cinfo->highfreq,
@@ -1037,29 +1114,32 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
 	l = FLD_MOD(l, 1, 13, 13);		/* DSI_PLL_REFEN */
 	l = FLD_MOD(l, 0, 14, 14);		/* DSIPHY_CLKINEN */
 	l = FLD_MOD(l, 1, 20, 20);		/* DSI_HSDIVBYPASS */
-	dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
+	if (cpu_is_omap44xx())
+		l = FLD_MOD(l, 3, 22, 21);	/* DSI_REF_SEL */
+	dsi_write_reg(ix, DSI_PLL_CONFIGURATION2, l);
 
-	REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0);	/* DSI_PLL_GO */
+	REG_FLD_MOD(ix, DSI_PLL_GO, 1, 0, 0);	/* DSI_PLL_GO */
 
-	if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
+	if (wait_for_bit_change(ix, DSI_PLL_GO, 0, 0) != 0) {
 		DSSERR("dsi pll go bit not going down.\n");
 		r = -EIO;
 		goto err;
 	}
 
-	if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
+	if (wait_for_bit_change(ix, DSI_PLL_STATUS, 1, 1) != 1) {
 		DSSERR("cannot lock PLL\n");
 		r = -EIO;
 		goto err;
 	}
 
-	dsi.pll_locked = 1;
+	p_dsi->pll_locked = 1;
 
-	l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
+	l = dsi_read_reg(ix, DSI_PLL_CONFIGURATION2);
 	l = FLD_MOD(l, 0, 0, 0);	/* DSI_PLL_IDLE */
 	l = FLD_MOD(l, 0, 5, 5);	/* DSI_PLL_PLLLPMODE */
 	l = FLD_MOD(l, 0, 6, 6);	/* DSI_PLL_LOWCURRSTBY */
-	l = FLD_MOD(l, 0, 7, 7);	/* DSI_PLL_TIGHTPHASELOCK */
+	if (!cpu_is_omap44xx())
+		l = FLD_MOD(l, 0, 7, 7);	/* DSI_PLL_TIGHTPHASELOCK */
 	l = FLD_MOD(l, 0, 8, 8);	/* DSI_PLL_DRIFTGUARDEN */
 	l = FLD_MOD(l, 0, 10, 9);	/* DSI_PLL_LOCKSEL */
 	l = FLD_MOD(l, 1, 13, 13);	/* DSI_PLL_REFEN */
@@ -1070,7 +1150,11 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
 	l = FLD_MOD(l, 1, 18, 18);	/* DSI_PROTO_CLOCK_EN */
 	l = FLD_MOD(l, 0, 19, 19);	/* DSI_PROTO_CLOCK_PWDN */
 	l = FLD_MOD(l, 0, 20, 20);	/* DSI_HSDIVBYPASS */
-	dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
+	if (cpu_is_omap44xx()) {
+		l = FLD_MOD(l, 0, 25, 25);	/* M7_CLOCK_EN */
+		l = FLD_MOD(l, 0, 26, 26);	/* M7_CLOCK_PWDN */
+	}
+	dsi_write_reg(ix, DSI_PLL_CONFIGURATION2, l);
 
 	DSSDBG("PLL config done\n");
 err:
@@ -1082,20 +1166,30 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
 {
 	int r = 0;
 	enum dsi_pll_power_state pwstate;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	DSSDBG("PLL init\n");
 
+	/* The SCPClk is required for PLL registers in OMAP4 */
+	if (cpu_is_omap44xx())
+		REG_FLD_MOD(ix, DSI_CLK_CTRL, 1, 14, 14);
+
 	enable_clocks(1);
-	dsi_enable_pll_clock(1);
+	dsi_enable_pll_clock(ix, 1);
 
-	r = regulator_enable(dsi.vdds_dsi_reg);
-	if (r)
-		goto err0;
+	if (!cpu_is_omap44xx()) {
+		r = regulator_enable(dsi1.vdds_dsi_reg);
+		if (r)
+			goto err0;
+	}
 
 	/* XXX PLL does not come out of reset without this... */
-	dispc_pck_free_enable(1);
+	if (!cpu_is_omap44xx())
+		dispc_pck_free_enable(1);
 
-	if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
+	if (wait_for_bit_change(ix, DSI_PLL_STATUS, 0, 1) != 1) {
 		DSSERR("PLL not coming out of reset.\n");
 		r = -ENODEV;
 		goto err1;
@@ -1103,7 +1197,8 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
 
 	/* XXX ... but if left on, we get problems when planes do not
 	 * fill the whole display. No idea about this */
-	dispc_pck_free_enable(0);
+	if (!cpu_is_omap44xx())
+		dispc_pck_free_enable(0);
 
 	if (enable_hsclk && enable_hsdiv)
 		pwstate = DSI_PLL_POWER_ON_ALL;
@@ -1114,7 +1209,7 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
 	else
 		pwstate = DSI_PLL_POWER_OFF;
 
-	r = dsi_pll_power(pwstate);
+	r = dsi_pll_power(ix, pwstate);
 
 	if (r)
 		goto err1;
@@ -1123,32 +1218,37 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
 
 	return 0;
 err1:
-	regulator_disable(dsi.vdds_dsi_reg);
+	if (!cpu_is_omap44xx())
+		regulator_disable(dsi1.vdds_dsi_reg);
 err0:
 	enable_clocks(0);
-	dsi_enable_pll_clock(0);
+	dsi_enable_pll_clock(ix, 0);
 	return r;
 }
 
-void dsi_pll_uninit(void)
+void dsi_pll_uninit(enum omap_dsi_index ix)
 {
+	struct dsi_struct *p_dsi;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
 	enable_clocks(0);
-	dsi_enable_pll_clock(0);
+	dsi_enable_pll_clock(ix, 0);
 
-	dsi.pll_locked = 0;
-	dsi_pll_power(DSI_PLL_POWER_OFF);
-	regulator_disable(dsi.vdds_dsi_reg);
+	p_dsi->pll_locked = 0;
+	dsi_pll_power(ix, DSI_PLL_POWER_OFF);
+	if (!cpu_is_omap44xx())
+		regulator_disable(dsi1.vdds_dsi_reg);
 	DSSDBG("PLL uninit done\n");
 }
 
-void dsi_dump_clocks(struct seq_file *s)
+void dsi_dump_clocks(enum omap_dsi_index ix, struct seq_file *s)
 {
 	int clksel;
-	struct dsi_clock_info *cinfo = &dsi.current_cinfo;
-
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	struct dsi_clock_info *cinfo = &p_dsi->current_cinfo;
 	enable_clocks(1);
 
-	clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
+	clksel = REG_GET(ix, DSI_PLL_CONFIGURATION2, 11, 11);
 
 	seq_printf(s,	"- DSI PLL -\n");
 
@@ -1179,36 +1279,37 @@ void dsi_dump_clocks(struct seq_file *s)
 			dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
 			"dss1_alwon_fclk" : "dsi2_pll_fclk");
 
-	seq_printf(s,	"DSI_FCLK\t%lu\n", dsi_fclk_rate());
+	seq_printf(s,	"DSI_FCLK\t%lu\n", dsi_fclk_rate(ix));
 
 	seq_printf(s,	"DDR_CLK\t\t%lu\n",
 			cinfo->clkin4ddr / 4);
 
-	seq_printf(s,	"TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
+	seq_printf(s,	"TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(ix));
 
 	seq_printf(s,	"LP_CLK\t\t%lu\n", cinfo->lp_clk);
 
 	seq_printf(s,	"VP_CLK\t\t%lu\n"
 			"VP_PCLK\t\t%lu\n",
-			dispc_lclk_rate(),
-			dispc_pclk_rate());
+			dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
+			dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
 
 	enable_clocks(0);
 }
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-void dsi_dump_irqs(struct seq_file *s)
+void dsi_dump_irqs(enum omap_dsi_index ix, struct seq_file *s)
 {
 	unsigned long flags;
 	struct dsi_irq_stats stats;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
-	spin_lock_irqsave(&dsi.irq_stats_lock, flags);
+	spin_lock_irqsave(&p_dsi->irq_stats_lock, flags);
 
-	stats = dsi.irq_stats;
-	memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
-	dsi.irq_stats.last_reset = jiffies;
+	stats = p_dsi->irq_stats;
+	memset(&p_dsi->irq_stats, 0, sizeof(p_dsi->irq_stats));
+	p_dsi->irq_stats.last_reset = jiffies;
 
-	spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
+	spin_unlock_irqrestore(&p_dsi->irq_stats_lock, flags);
 
 	seq_printf(s, "period %u ms\n",
 			jiffies_to_msecs(jiffies - stats.last_reset));
@@ -1285,81 +1386,81 @@ void dsi_dump_irqs(struct seq_file *s)
 }
 #endif
 
-void dsi_dump_regs(struct seq_file *s)
+void dsi_dump_regs(enum omap_dsi_index ix, struct seq_file *s)
 {
-#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
+#define DUMPREG(ix, r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(ix, r))
 
 	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 
-	DUMPREG(DSI_REVISION);
-	DUMPREG(DSI_SYSCONFIG);
-	DUMPREG(DSI_SYSSTATUS);
-	DUMPREG(DSI_IRQSTATUS);
-	DUMPREG(DSI_IRQENABLE);
-	DUMPREG(DSI_CTRL);
-	DUMPREG(DSI_COMPLEXIO_CFG1);
-	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
-	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
-	DUMPREG(DSI_CLK_CTRL);
-	DUMPREG(DSI_TIMING1);
-	DUMPREG(DSI_TIMING2);
-	DUMPREG(DSI_VM_TIMING1);
-	DUMPREG(DSI_VM_TIMING2);
-	DUMPREG(DSI_VM_TIMING3);
-	DUMPREG(DSI_CLK_TIMING);
-	DUMPREG(DSI_TX_FIFO_VC_SIZE);
-	DUMPREG(DSI_RX_FIFO_VC_SIZE);
-	DUMPREG(DSI_COMPLEXIO_CFG2);
-	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
-	DUMPREG(DSI_VM_TIMING4);
-	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
-	DUMPREG(DSI_VM_TIMING5);
-	DUMPREG(DSI_VM_TIMING6);
-	DUMPREG(DSI_VM_TIMING7);
-	DUMPREG(DSI_STOPCLK_TIMING);
-
-	DUMPREG(DSI_VC_CTRL(0));
-	DUMPREG(DSI_VC_TE(0));
-	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
-	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
-	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
-	DUMPREG(DSI_VC_IRQSTATUS(0));
-	DUMPREG(DSI_VC_IRQENABLE(0));
-
-	DUMPREG(DSI_VC_CTRL(1));
-	DUMPREG(DSI_VC_TE(1));
-	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
-	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
-	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
-	DUMPREG(DSI_VC_IRQSTATUS(1));
-	DUMPREG(DSI_VC_IRQENABLE(1));
-
-	DUMPREG(DSI_VC_CTRL(2));
-	DUMPREG(DSI_VC_TE(2));
-	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
-	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
-	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
-	DUMPREG(DSI_VC_IRQSTATUS(2));
-	DUMPREG(DSI_VC_IRQENABLE(2));
-
-	DUMPREG(DSI_VC_CTRL(3));
-	DUMPREG(DSI_VC_TE(3));
-	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
-	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
-	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
-	DUMPREG(DSI_VC_IRQSTATUS(3));
-	DUMPREG(DSI_VC_IRQENABLE(3));
-
-	DUMPREG(DSI_DSIPHY_CFG0);
-	DUMPREG(DSI_DSIPHY_CFG1);
-	DUMPREG(DSI_DSIPHY_CFG2);
-	DUMPREG(DSI_DSIPHY_CFG5);
-
-	DUMPREG(DSI_PLL_CONTROL);
-	DUMPREG(DSI_PLL_STATUS);
-	DUMPREG(DSI_PLL_GO);
-	DUMPREG(DSI_PLL_CONFIGURATION1);
-	DUMPREG(DSI_PLL_CONFIGURATION2);
+	DUMPREG(ix, DSI_REVISION);
+	DUMPREG(ix, DSI_SYSCONFIG);
+	DUMPREG(ix, DSI_SYSSTATUS);
+	DUMPREG(ix, DSI_IRQSTATUS);
+	DUMPREG(ix, DSI_IRQENABLE);
+	DUMPREG(ix, DSI_CTRL);
+	DUMPREG(ix, DSI_COMPLEXIO_CFG1);
+	DUMPREG(ix, DSI_COMPLEXIO_IRQ_STATUS);
+	DUMPREG(ix, DSI_COMPLEXIO_IRQ_ENABLE);
+	DUMPREG(ix, DSI_CLK_CTRL);
+	DUMPREG(ix, DSI_TIMING1);
+	DUMPREG(ix, DSI_TIMING2);
+	DUMPREG(ix, DSI_VM_TIMING1);
+	DUMPREG(ix, DSI_VM_TIMING2);
+	DUMPREG(ix, DSI_VM_TIMING3);
+	DUMPREG(ix, DSI_CLK_TIMING);
+	DUMPREG(ix, DSI_TX_FIFO_VC_SIZE);
+	DUMPREG(ix, DSI_RX_FIFO_VC_SIZE);
+	DUMPREG(ix, DSI_COMPLEXIO_CFG2);
+	DUMPREG(ix, DSI_RX_FIFO_VC_FULLNESS);
+	DUMPREG(ix, DSI_VM_TIMING4);
+	DUMPREG(ix, DSI_TX_FIFO_VC_EMPTINESS);
+	DUMPREG(ix, DSI_VM_TIMING5);
+	DUMPREG(ix, DSI_VM_TIMING6);
+	DUMPREG(ix, DSI_VM_TIMING7);
+	DUMPREG(ix, DSI_STOPCLK_TIMING);
+
+	DUMPREG(ix, DSI_VC_CTRL(0));
+	DUMPREG(ix, DSI_VC_TE(0));
+	DUMPREG(ix, DSI_VC_LONG_PACKET_HEADER(0));
+	DUMPREG(ix, DSI_VC_LONG_PACKET_PAYLOAD(0));
+	DUMPREG(ix, DSI_VC_SHORT_PACKET_HEADER(0));
+	DUMPREG(ix, DSI_VC_IRQSTATUS(0));
+	DUMPREG(ix, DSI_VC_IRQENABLE(0));
+
+	DUMPREG(ix, DSI_VC_CTRL(1));
+	DUMPREG(ix, DSI_VC_TE(1));
+	DUMPREG(ix, DSI_VC_LONG_PACKET_HEADER(1));
+	DUMPREG(ix, DSI_VC_LONG_PACKET_PAYLOAD(1));
+	DUMPREG(ix, DSI_VC_SHORT_PACKET_HEADER(1));
+	DUMPREG(ix, DSI_VC_IRQSTATUS(1));
+	DUMPREG(ix, DSI_VC_IRQENABLE(1));
+
+	DUMPREG(ix, DSI_VC_CTRL(2));
+	DUMPREG(ix, DSI_VC_TE(2));
+	DUMPREG(ix, DSI_VC_LONG_PACKET_HEADER(2));
+	DUMPREG(ix, DSI_VC_LONG_PACKET_PAYLOAD(2));
+	DUMPREG(ix, DSI_VC_SHORT_PACKET_HEADER(2));
+	DUMPREG(ix, DSI_VC_IRQSTATUS(2));
+	DUMPREG(ix, DSI_VC_IRQENABLE(2));
+
+	DUMPREG(ix, DSI_VC_CTRL(3));
+	DUMPREG(ix, DSI_VC_TE(3));
+	DUMPREG(ix, DSI_VC_LONG_PACKET_HEADER(3));
+	DUMPREG(ix, DSI_VC_LONG_PACKET_PAYLOAD(3));
+	DUMPREG(ix, DSI_VC_SHORT_PACKET_HEADER(3));
+	DUMPREG(ix, DSI_VC_IRQSTATUS(3));
+	DUMPREG(ix, DSI_VC_IRQENABLE(3));
+
+	DUMPREG(ix, DSI_DSIPHY_CFG0);
+	DUMPREG(ix, DSI_DSIPHY_CFG1);
+	DUMPREG(ix, DSI_DSIPHY_CFG2);
+	DUMPREG(ix, DSI_DSIPHY_CFG5);
+
+	DUMPREG(ix, DSI_PLL_CONTROL);
+	DUMPREG(ix, DSI_PLL_STATUS);
+	DUMPREG(ix, DSI_PLL_GO);
+	DUMPREG(ix, DSI_PLL_CONFIGURATION1);
+	DUMPREG(ix, DSI_PLL_CONFIGURATION2);
 
 	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 #undef DUMPREG
@@ -1371,15 +1472,20 @@ enum dsi_complexio_power_state {
 	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
 };
 
-static int dsi_complexio_power(enum dsi_complexio_power_state state)
+static int dsi_complexio_power(enum omap_dsi_index ix,
+	enum dsi_complexio_power_state state)
 {
 	int t = 0;
 
 	/* PWR_CMD */
-	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
+	REG_FLD_MOD(ix, DSI_COMPLEXIO_CFG1, state, 28, 27);
+
+	if (cpu_is_omap44xx())
+		/*bit 30 has to be set to 1 to GO in omap4*/
+		REG_FLD_MOD(ix, DSI_COMPLEXIO_CFG1, 1, 30, 30);
 
 	/* PWR_STATUS */
-	while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
+	while (FLD_GET(dsi_read_reg(ix, DSI_COMPLEXIO_CFG1), 26, 25) != state) {
 		if (++t > 1000) {
 			DSSERR("failed to set complexio power state to "
 					"%d\n", state);
@@ -1394,6 +1500,8 @@ static int dsi_complexio_power(enum dsi_complexio_power_state state)
 static void dsi_complexio_config(struct omap_dss_device *dssdev)
 {
 	u32 r;
+	enum omap_dsi_index ix;
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	int clk_lane   = dssdev->phy.dsi.clk_lane;
 	int data1_lane = dssdev->phy.dsi.data1_lane;
@@ -1402,14 +1510,14 @@ static void dsi_complexio_config(struct omap_dss_device *dssdev)
 	int data1_pol  = dssdev->phy.dsi.data1_pol;
 	int data2_pol  = dssdev->phy.dsi.data2_pol;
 
-	r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
+	r = dsi_read_reg(ix, DSI_COMPLEXIO_CFG1);
 	r = FLD_MOD(r, clk_lane, 2, 0);
 	r = FLD_MOD(r, clk_pol, 3, 3);
 	r = FLD_MOD(r, data1_lane, 6, 4);
 	r = FLD_MOD(r, data1_pol, 7, 7);
 	r = FLD_MOD(r, data2_lane, 10, 8);
 	r = FLD_MOD(r, data2_pol, 11, 11);
-	dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
+	dsi_write_reg(ix, DSI_COMPLEXIO_CFG1, r);
 
 	/* The configuration of the DSI complex I/O (number of data lanes,
 	   position, differential order) should not be changed while
@@ -1430,20 +1538,22 @@ static void dsi_complexio_config(struct omap_dss_device *dssdev)
 	*/
 }
 
-static inline unsigned ns2ddr(unsigned ns)
+static inline unsigned ns2ddr(enum omap_dsi_index ix, unsigned ns)
 {
 	/* convert time in ns to ddr ticks, rounding up */
-	unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	unsigned long ddr_clk = p_dsi->current_cinfo.clkin4ddr / 4;
 	return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
 }
 
-static inline unsigned ddr2ns(unsigned ddr)
+static inline unsigned ddr2ns(enum omap_dsi_index ix, unsigned ddr)
 {
-	unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	unsigned long ddr_clk = p_dsi->current_cinfo.clkin4ddr / 4;
 	return ddr * 1000 * 1000 / (ddr_clk / 1000);
 }
 
-static void dsi_complexio_timings(void)
+static void dsi_complexio_timings(enum omap_dsi_index ix)
 {
 	u32 r;
 	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
@@ -1455,80 +1565,85 @@ static void dsi_complexio_timings(void)
 	/* 1 * DDR_CLK = 2 * UI */
 
 	/* min 40ns + 4*UI	max 85ns + 6*UI */
-	ths_prepare = ns2ddr(70) + 2;
+	ths_prepare = ns2ddr(ix, 70) + 2;
 
 	/* min 145ns + 10*UI */
-	ths_prepare_ths_zero = ns2ddr(175) + 2;
+	ths_prepare_ths_zero = ns2ddr(ix, 175) + 2;
 
 	/* min max(8*UI, 60ns+4*UI) */
-	ths_trail = ns2ddr(60) + 5;
+	ths_trail = ns2ddr(ix, 60) + 5;
 
 	/* min 100ns */
-	ths_exit = ns2ddr(145);
+	ths_exit = ns2ddr(ix, 145);
 
 	/* tlpx min 50n */
-	tlpx_half = ns2ddr(25);
+	tlpx_half = ns2ddr(ix, 25);
 
 	/* min 60ns */
-	tclk_trail = ns2ddr(60) + 2;
+	tclk_trail = ns2ddr(ix, 60) + 2;
 
 	/* min 38ns, max 95ns */
-	tclk_prepare = ns2ddr(65);
+	tclk_prepare = ns2ddr(ix, 65);
 
 	/* min tclk-prepare + tclk-zero = 300ns */
-	tclk_zero = ns2ddr(260);
+	tclk_zero = ns2ddr(ix, 260);
 
 	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
-		ths_prepare, ddr2ns(ths_prepare),
-		ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
+		ths_prepare, ddr2ns(ix, ths_prepare),
+		ths_prepare_ths_zero, ddr2ns(ix, ths_prepare_ths_zero));
 	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
-			ths_trail, ddr2ns(ths_trail),
-			ths_exit, ddr2ns(ths_exit));
+			ths_trail, ddr2ns(ix, ths_trail),
+			ths_exit, ddr2ns(ix, ths_exit));
 
 	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
 			"tclk_zero %u (%uns)\n",
-			tlpx_half, ddr2ns(tlpx_half),
-			tclk_trail, ddr2ns(tclk_trail),
-			tclk_zero, ddr2ns(tclk_zero));
+			tlpx_half, ddr2ns(ix, tlpx_half),
+			tclk_trail, ddr2ns(ix, tclk_trail),
+			tclk_zero, ddr2ns(ix, tclk_zero));
 	DSSDBG("tclk_prepare %u (%uns)\n",
-			tclk_prepare, ddr2ns(tclk_prepare));
+			tclk_prepare, ddr2ns(ix, tclk_prepare));
 
 	/* program timings */
 
-	r = dsi_read_reg(DSI_DSIPHY_CFG0);
+	r = dsi_read_reg(ix, DSI_DSIPHY_CFG0);
 	r = FLD_MOD(r, ths_prepare, 31, 24);
 	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
 	r = FLD_MOD(r, ths_trail, 15, 8);
 	r = FLD_MOD(r, ths_exit, 7, 0);
-	dsi_write_reg(DSI_DSIPHY_CFG0, r);
+	dsi_write_reg(ix, DSI_DSIPHY_CFG0, r);
 
-	r = dsi_read_reg(DSI_DSIPHY_CFG1);
+	r = dsi_read_reg(ix, DSI_DSIPHY_CFG1);
 	r = FLD_MOD(r, tlpx_half, 22, 16);
 	r = FLD_MOD(r, tclk_trail, 15, 8);
 	r = FLD_MOD(r, tclk_zero, 7, 0);
-	dsi_write_reg(DSI_DSIPHY_CFG1, r);
+	dsi_write_reg(ix, DSI_DSIPHY_CFG1, r);
 
-	r = dsi_read_reg(DSI_DSIPHY_CFG2);
+	r = dsi_read_reg(ix, DSI_DSIPHY_CFG2);
 	r = FLD_MOD(r, tclk_prepare, 7, 0);
-	dsi_write_reg(DSI_DSIPHY_CFG2, r);
+	dsi_write_reg(ix, DSI_DSIPHY_CFG2, r);
 }
 
 
 static int dsi_complexio_init(struct omap_dss_device *dssdev)
 {
 	int r = 0;
+	enum omap_dsi_index ix;
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	DSSDBG("dsi_complexio_init\n");
 
 	/* CIO_CLK_ICG, enable L3 clk to CIO */
-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
+	REG_FLD_MOD(ix, DSI_CLK_CTRL, 1, 14, 14);
+
+	if (cpu_is_omap44xx())
+		REG_FLD_MOD(ix, DSI_CLK_CTRL, 1, 13, 13);
 
 	/* A dummy read using the SCP interface to any DSIPHY register is
 	 * required after DSIPHY reset to complete the reset of the DSI complex
 	 * I/O. */
-	dsi_read_reg(DSI_DSIPHY_CFG5);
+	dsi_read_reg(ix, DSI_DSIPHY_CFG5);
 
-	if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
+	if (wait_for_bit_change(ix, DSI_DSIPHY_CFG5, 30, 1) != 1) {
 		DSSERR("ComplexIO PHY not coming out of reset.\n");
 		r = -ENODEV;
 		goto err;
@@ -1536,24 +1651,26 @@ static int dsi_complexio_init(struct omap_dss_device *dssdev)
 
 	dsi_complexio_config(dssdev);
 
-	r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
+	r = dsi_complexio_power(ix, DSI_COMPLEXIO_POWER_ON);
 
 	if (r)
 		goto err;
 
-	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
+	if (wait_for_bit_change(ix, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
 		DSSERR("ComplexIO not coming out of reset.\n");
 		r = -ENODEV;
 		goto err;
 	}
 
-	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
-		DSSERR("ComplexIO LDO power down.\n");
-		r = -ENODEV;
-		goto err;
+	if (!cpu_is_omap44xx()) {
+		if (wait_for_bit_change(ix, DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
+			DSSERR("ComplexIO LDO power down.\n");
+			r = -ENODEV;
+			goto err;
+		}
 	}
 
-	dsi_complexio_timings();
+	dsi_complexio_timings(ix);
 
 	/*
 	   The configuration of the DSI complex I/O (number of data lanes,
@@ -1567,27 +1684,27 @@ static int dsi_complexio_init(struct omap_dss_device *dssdev)
 	   bit to 1. If the sequence is not followed, the DSi complex I/O
 	   configuration is undetermined.
 	   */
-	dsi_if_enable(1);
-	dsi_if_enable(0);
-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
-	dsi_if_enable(1);
-	dsi_if_enable(0);
+	dsi_if_enable(ix, 1);
+	dsi_if_enable(ix, 0);
+	REG_FLD_MOD(ix, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
+	dsi_if_enable(ix, 1);
+	dsi_if_enable(ix, 0);
 
 	DSSDBG("CIO init done\n");
 err:
 	return r;
 }
 
-static void dsi_complexio_uninit(void)
+static void dsi_complexio_uninit(enum omap_dsi_index ix)
 {
-	dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
+	dsi_complexio_power(ix, DSI_COMPLEXIO_POWER_OFF);
 }
 
-static int _dsi_wait_reset(void)
+static int _dsi_wait_reset(enum omap_dsi_index ix)
 {
 	int t = 0;
 
-	while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
+	while (REG_GET(ix, DSI_SYSSTATUS, 0, 0) == 0) {
 		if (++t > 5) {
 			DSSERR("soft reset failed\n");
 			return -ENODEV;
@@ -1598,42 +1715,44 @@ static int _dsi_wait_reset(void)
 	return 0;
 }
 
-static int _dsi_reset(void)
+static int _dsi_reset(enum omap_dsi_index ix)
 {
 	/* Soft reset */
-	REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
-	return _dsi_wait_reset();
+	REG_FLD_MOD(ix, DSI_SYSCONFIG, 1, 1, 1);
+	return _dsi_wait_reset(ix);
 }
 
-static void dsi_reset_tx_fifo(int channel)
+static void dsi_reset_tx_fifo(enum omap_dsi_index ix, int channel)
 {
 	u32 mask;
 	u32 l;
 
 	/* set fifosize of the channel to 0, then return the old size */
-	l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
+	l = dsi_read_reg(ix, DSI_TX_FIFO_VC_SIZE);
 
 	mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
-	dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
+	dsi_write_reg(ix, DSI_TX_FIFO_VC_SIZE, l & ~mask);
 
-	dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
+	dsi_write_reg(ix, DSI_TX_FIFO_VC_SIZE, l);
 }
 
-static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
-		enum fifo_size size3, enum fifo_size size4)
+static void dsi_config_tx_fifo(enum omap_dsi_index ix,
+	enum fifo_size size1, enum fifo_size size2,
+	enum fifo_size size3, enum fifo_size size4)
 {
 	u32 r = 0;
 	int add = 0;
 	int i;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
-	dsi.vc[0].fifo_size = size1;
-	dsi.vc[1].fifo_size = size2;
-	dsi.vc[2].fifo_size = size3;
-	dsi.vc[3].fifo_size = size4;
+	p_dsi->vc[0].fifo_size = size1;
+	p_dsi->vc[1].fifo_size = size2;
+	p_dsi->vc[2].fifo_size = size3;
+	p_dsi->vc[3].fifo_size = size4;
 
 	for (i = 0; i < 4; i++) {
 		u8 v;
-		int size = dsi.vc[i].fifo_size;
+		int size = p_dsi->vc[i].fifo_size;
 
 		if (add + size > 4) {
 			DSSERR("Illegal FIFO configuration\n");
@@ -1646,24 +1765,26 @@ static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
 		add += size;
 	}
 
-	dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
+	dsi_write_reg(ix, DSI_TX_FIFO_VC_SIZE, r);
 }
 
-static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
-		enum fifo_size size3, enum fifo_size size4)
+static void dsi_config_rx_fifo(enum omap_dsi_index ix,
+	enum fifo_size size1, enum fifo_size size2,
+	enum fifo_size size3, enum fifo_size size4)
 {
 	u32 r = 0;
 	int add = 0;
 	int i;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
-	dsi.vc[0].fifo_size = size1;
-	dsi.vc[1].fifo_size = size2;
-	dsi.vc[2].fifo_size = size3;
-	dsi.vc[3].fifo_size = size4;
+	p_dsi->vc[0].fifo_size = size1;
+	p_dsi->vc[1].fifo_size = size2;
+	p_dsi->vc[2].fifo_size = size3;
+	p_dsi->vc[3].fifo_size = size4;
 
 	for (i = 0; i < 4; i++) {
 		u8 v;
-		int size = dsi.vc[i].fifo_size;
+		int size = p_dsi->vc[i].fifo_size;
 
 		if (add + size > 4) {
 			DSSERR("Illegal FIFO configuration\n");
@@ -1676,18 +1797,18 @@ static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
 		add += size;
 	}
 
-	dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
+	dsi_write_reg(ix, DSI_RX_FIFO_VC_SIZE, r);
 }
 
-static int dsi_force_tx_stop_mode_io(void)
+static int dsi_force_tx_stop_mode_io(enum omap_dsi_index ix)
 {
 	u32 r;
 
-	r = dsi_read_reg(DSI_TIMING1);
+	r = dsi_read_reg(ix, DSI_TIMING1);
 	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
-	dsi_write_reg(DSI_TIMING1, r);
+	dsi_write_reg(ix, DSI_TIMING1, r);
 
-	if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
+	if (wait_for_bit_change(ix, DSI_TIMING1, 15, 0) != 0) {
 		DSSERR("TX_STOP bit not going down\n");
 		return -EIO;
 	}
@@ -1695,16 +1816,18 @@ static int dsi_force_tx_stop_mode_io(void)
 	return 0;
 }
 
-static int dsi_vc_enable(int channel, bool enable)
+static int dsi_vc_enable(enum omap_dsi_index ix,
+	int channel, bool enable)
 {
 	DSSDBG("dsi_vc_enable channel %d, enable %d\n",
 			channel, enable);
 
 	enable = enable ? 1 : 0;
 
-	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
+	REG_FLD_MOD(ix, DSI_VC_CTRL(channel), enable, 0, 0);
 
-	if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
+	if (wait_for_bit_change(ix, DSI_VC_CTRL(channel),
+			0, enable) != enable) {
 			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
 			return -EIO;
 	}
@@ -1712,13 +1835,14 @@ static int dsi_vc_enable(int channel, bool enable)
 	return 0;
 }
 
-static void dsi_vc_initial_config(int channel)
+static void dsi_vc_initial_config(enum omap_dsi_index ix, int channel)
 {
 	u32 r;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
 	DSSDBGF("%d", channel);
 
-	r = dsi_read_reg(DSI_VC_CTRL(channel));
+	r = dsi_read_reg(ix, DSI_VC_CTRL(channel));
 
 	if (FLD_GET(r, 15, 15)) /* VC_BUSY */
 		DSSERR("VC(%d) busy when trying to configure it!\n",
@@ -1731,77 +1855,112 @@ static void dsi_vc_initial_config(int channel)
 	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
 	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
 	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
-
+	if (cpu_is_omap44xx()) {
+		r = FLD_MOD(r, 3, 11, 10);
+		r = FLD_MOD(r, 3, 18, 17);
+	}
 	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
 	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
 
-	dsi_write_reg(DSI_VC_CTRL(channel), r);
+	dsi_write_reg(ix, DSI_VC_CTRL(channel), r);
 
-	dsi.vc[channel].mode = DSI_VC_MODE_L4;
+	p_dsi->vc[channel].mode = DSI_VC_MODE_L4;
 }
 
-static void dsi_vc_config_l4(int channel)
+static void dsi_vc_initial_config_vp(enum omap_dsi_index ix, int channel)
 {
-	if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
+	u32 r;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	DSSDBGF("%d", channel);
+
+	r = dsi_read_reg(ix, DSI_VC_CTRL(channel));
+	r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
+	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
+	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
+	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
+	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
+	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
+	r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
+	r = FLD_MOD(r, 1, 12, 12);	/*RGB565_ORDER*/
+	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
+	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
+	r = FLD_MOD(r, 1, 30, 30);	/* DCS_CMD_ENABLE*/
+	r = FLD_MOD(r, 0, 31, 31);	/* DCS_CMD_CODE*/
+	dsi_write_reg(ix, DSI_VC_CTRL(channel), r);
+
+	p_dsi->vc[channel].mode = DSI_VC_MODE_VP;
+}
+
+static void dsi_vc_config_l4(enum omap_dsi_index ix, int channel)
+{
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	if (p_dsi->vc[channel].mode == DSI_VC_MODE_L4)
 		return;
 
 	DSSDBGF("%d", channel);
 
-	dsi_vc_enable(channel, 0);
+	dsi_vc_enable(ix, channel, 0);
 
-	if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
+	if (REG_GET(ix, DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
 		DSSERR("vc(%d) busy when trying to config for L4\n", channel);
 
-	REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
+	REG_FLD_MOD(ix, DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
 
-	dsi_vc_enable(channel, 1);
+	dsi_vc_enable(ix, channel, 1);
 
-	dsi.vc[channel].mode = DSI_VC_MODE_L4;
+	p_dsi->vc[channel].mode = DSI_VC_MODE_L4;
 }
 
-static void dsi_vc_config_vp(int channel)
+static void dsi_vc_config_vp(enum omap_dsi_index ix, int channel)
 {
-	if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	if (p_dsi->vc[channel].mode == DSI_VC_MODE_VP)
 		return;
 
 	DSSDBGF("%d", channel);
 
-	dsi_vc_enable(channel, 0);
+	dsi_vc_enable(ix, channel, 0);
 
-	if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
+	if (REG_GET(ix, DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
 		DSSERR("vc(%d) busy when trying to config for VP\n", channel);
 
-	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
+	REG_FLD_MOD(ix, DSI_VC_CTRL(channel),
+			1, 1, 1); /* SOURCE, 1 = video port */
 
-	dsi_vc_enable(channel, 1);
+	dsi_vc_enable(ix, channel, 1);
 
-	dsi.vc[channel].mode = DSI_VC_MODE_VP;
+	p_dsi->vc[channel].mode = DSI_VC_MODE_VP;
 }
 
 
-void omapdss_dsi_vc_enable_hs(int channel, bool enable)
+void omapdss_dsi_vc_enable_hs(enum omap_dsi_index ix,
+	int channel, bool enable)
 {
 	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
 
-	WARN_ON(!dsi_bus_is_locked());
+	WARN_ON(!dsi_bus_is_locked(ix));
 
-	dsi_vc_enable(channel, 0);
-	dsi_if_enable(0);
+	dsi_vc_enable(ix, channel, 0);
+	dsi_if_enable(ix, 0);
 
-	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
+	REG_FLD_MOD(ix, DSI_VC_CTRL(channel), enable, 9, 9);
 
-	dsi_vc_enable(channel, 1);
-	dsi_if_enable(1);
+	dsi_vc_enable(ix, channel, 1);
+	dsi_if_enable(ix, 1);
 
-	dsi_force_tx_stop_mode_io();
+	dsi_force_tx_stop_mode_io(ix);
 }
 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
 
-static void dsi_vc_flush_long_data(int channel)
+static void dsi_vc_flush_long_data(enum omap_dsi_index ix,
+	int channel)
 {
-	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
+	while (REG_GET(ix, DSI_VC_CTRL(channel), 20, 20)) {
 		u32 val;
-		val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
+		val = dsi_read_reg(ix, DSI_VC_SHORT_PACKET_HEADER(channel));
 		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
 				(val >> 0) & 0xff,
 				(val >> 8) & 0xff,
@@ -1847,18 +2006,20 @@ static void dsi_show_rx_ack_with_err(u16 err)
 		DSSERR("\t\tDSI Protocol Violation\n");
 }
 
-static u16 dsi_vc_flush_receive_data(int channel)
+static u16 dsi_vc_flush_receive_data(enum omap_dsi_index ix,
+	int channel)
 {
 	/* RX_FIFO_NOT_EMPTY */
-	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
+	while (REG_GET(ix, DSI_VC_CTRL(channel), 20, 20)) {
 		u32 val;
 		u8 dt;
-		val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
+		val = dsi_read_reg(ix, DSI_VC_SHORT_PACKET_HEADER(channel));
 		DSSDBG("\trawval %#08x\n", val);
 		dt = FLD_GET(val, 5, 0);
 		if (dt == DSI_DT_RX_ACK_WITH_ERR) {
 			u16 err = FLD_GET(val, 23, 8);
-			dsi_show_rx_ack_with_err(err);
+			if (!cpu_is_omap44xx())
+				dsi_show_rx_ack_with_err(err);
 		} else if (dt == DSI_DT_RX_SHORT_READ_1) {
 			DSSDBG("\tDCS short response, 1 byte: %#x\n",
 					FLD_GET(val, 23, 8));
@@ -1868,7 +2029,7 @@ static u16 dsi_vc_flush_receive_data(int channel)
 		} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
 			DSSDBG("\tDCS long response, len %d\n",
 					FLD_GET(val, 23, 8));
-			dsi_vc_flush_long_data(channel);
+			dsi_vc_flush_long_data(ix, channel);
 		} else {
 			DSSERR("\tunknown datatype 0x%02x\n", dt);
 		}
@@ -1876,74 +2037,84 @@ static u16 dsi_vc_flush_receive_data(int channel)
 	return 0;
 }
 
-static int dsi_vc_send_bta(int channel)
+static int dsi_vc_send_bta(enum omap_dsi_index ix, int channel)
 {
-	if (dsi.debug_write || dsi.debug_read)
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	if (p_dsi->debug_write || p_dsi->debug_read)
 		DSSDBG("dsi_vc_send_bta %d\n", channel);
 
-	WARN_ON(!dsi_bus_is_locked());
+	WARN_ON(!dsi_bus_is_locked(ix));
 
-	if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {	/* RX_FIFO_NOT_EMPTY */
-		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
-		dsi_vc_flush_receive_data(channel);
+	/* RX_FIFO_NOT_EMPTY */
+	if (REG_GET(ix, DSI_VC_CTRL(channel), 20, 20)) {
+		if (!cpu_is_omap44xx())
+			DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
+		dsi_vc_flush_receive_data(ix, channel);
 	}
 
-	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
+	REG_FLD_MOD(ix, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
 
 	return 0;
 }
 
-int dsi_vc_send_bta_sync(int channel)
+int dsi_vc_send_bta_sync(enum omap_dsi_index ix,
+	int channel)
 {
 	int r = 0;
 	u32 err;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
-	INIT_COMPLETION(dsi.bta_completion);
+	INIT_COMPLETION(p_dsi->bta_completion);
 
-	dsi_vc_enable_bta_irq(channel);
+	dsi_vc_enable_bta_irq(ix, channel);
 
-	r = dsi_vc_send_bta(channel);
+	r = dsi_vc_send_bta(ix, channel);
 	if (r)
 		goto err;
 
-	if (wait_for_completion_timeout(&dsi.bta_completion,
+	if (wait_for_completion_timeout(&p_dsi->bta_completion,
 				msecs_to_jiffies(500)) == 0) {
 		DSSERR("Failed to receive BTA\n");
 		r = -EIO;
 		goto err;
 	}
 
-	err = dsi_get_errors();
+	err = dsi_get_errors(ix);
 	if (err) {
 		DSSERR("Error while sending BTA: %x\n", err);
 		r = -EIO;
 		goto err;
 	}
 err:
-	dsi_vc_disable_bta_irq(channel);
+	dsi_vc_disable_bta_irq(ix, channel);
 
 	return r;
 }
 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
 
-static inline void dsi_vc_write_long_header(int channel, u8 data_type,
+static inline void dsi_vc_write_long_header(enum omap_dsi_index ix,
+		int channel, u8 data_type,
 		u16 len, u8 ecc)
 {
 	u32 val;
 	u8 data_id;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+	WARN_ON(!dsi_bus_is_locked(ix));
 
-	WARN_ON(!dsi_bus_is_locked());
-
-	data_id = data_type | channel << 6;
+	if (cpu_is_omap44xx())
+		data_id = data_type | p_dsi->vc[channel].dest_per << 6;
+	else
+		data_id = data_type | channel << 6;
 
 	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
 		FLD_VAL(ecc, 31, 24);
 
-	dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
+	dsi_write_reg(ix, DSI_VC_LONG_PACKET_HEADER(channel), val);
 }
 
-static inline void dsi_vc_write_long_payload(int channel,
-		u8 b1, u8 b2, u8 b3, u8 b4)
+static inline void dsi_vc_write_long_payload(enum omap_dsi_index ix,
+	int channel, u8 b1, u8 b2, u8 b3, u8 b4)
 {
 	u32 val;
 
@@ -1952,10 +2123,11 @@ static inline void dsi_vc_write_long_payload(int channel,
 /*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
 			b1, b2, b3, b4, val); */
 
-	dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
+	dsi_write_reg(ix, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
 }
 
-static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
+static int dsi_vc_send_long(enum omap_dsi_index ix, int channel,
+	u8 data_type, u8 *data, u16 len,
 		u8 ecc)
 {
 	/*u32 val; */
@@ -1963,23 +2135,24 @@ static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
 	u8 *p;
 	int r = 0;
 	u8 b1, b2, b3, b4;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
-	if (dsi.debug_write)
+	if (p_dsi->debug_write)
 		DSSDBG("dsi_vc_send_long, %d bytes\n", len);
 
 	/* len + header */
-	if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
+	if (p_dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
 		DSSERR("unable to send long packet: packet too long.\n");
 		return -EINVAL;
 	}
 
-	dsi_vc_config_l4(channel);
+	dsi_vc_config_l4(ix, channel);
 
-	dsi_vc_write_long_header(channel, data_type, len, ecc);
+	dsi_vc_write_long_header(ix, channel, data_type, len, ecc);
 
 	p = data;
 	for (i = 0; i < len >> 2; i++) {
-		if (dsi.debug_write)
+		if (p_dsi->debug_write)
 			DSSDBG("\tsending full packet %d\n", i);
 
 		b1 = *p++;
@@ -1987,14 +2160,14 @@ static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
 		b3 = *p++;
 		b4 = *p++;
 
-		dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
+		dsi_vc_write_long_payload(ix, channel, b1, b2, b3, b4);
 	}
 
 	i = len % 4;
 	if (i) {
 		b1 = 0; b2 = 0; b3 = 0;
 
-		if (dsi.debug_write)
+		if (p_dsi->debug_write)
 			DSSDBG("\tsending remainder bytes %d\n", i);
 
 		switch (i) {
@@ -2012,62 +2185,68 @@ static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
 			break;
 		}
 
-		dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
+		dsi_vc_write_long_payload(ix, channel, b1, b2, b3, 0);
 	}
 
 	return r;
 }
 
-static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
+static int dsi_vc_send_short(enum omap_dsi_index ix,
+	int channel, u8 data_type, u16 data, u8 ecc)
 {
 	u32 r;
 	u8 data_id;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
-	WARN_ON(!dsi_bus_is_locked());
+	WARN_ON(!dsi_bus_is_locked(ix));
 
-	if (dsi.debug_write)
+	if (p_dsi->debug_write)
 		DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
 				channel,
 				data_type, data & 0xff, (data >> 8) & 0xff);
 
-	dsi_vc_config_l4(channel);
+	dsi_vc_config_l4(ix, channel);
 
-	if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
+	if (FLD_GET(dsi_read_reg(ix, DSI_VC_CTRL(channel)), 16, 16)) {
 		DSSERR("ERROR FIFO FULL, aborting transfer\n");
 		return -EINVAL;
 	}
 
-	data_id = data_type | channel << 6;
+	if (cpu_is_omap44xx())
+		data_id = data_type | p_dsi->vc[channel].dest_per << 6;
+	else
+		data_id = data_type | channel << 6;
 
 	r = (data_id << 0) | (data << 8) | (ecc << 24);
 
-	dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
+	dsi_write_reg(ix, DSI_VC_SHORT_PACKET_HEADER(channel), r);
 
 	return 0;
 }
 
-int dsi_vc_send_null(int channel)
+int dsi_vc_send_null(enum omap_dsi_index ix, int channel)
 {
 	u8 nullpkg[] = {0, 0, 0, 0};
-	return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
+	return dsi_vc_send_long(ix, channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
 }
 EXPORT_SYMBOL(dsi_vc_send_null);
 
-int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
+int dsi_vc_dcs_write_nosync(enum omap_dsi_index ix, int channel,
+	u8 *data, int len)
 {
 	int r;
 
 	BUG_ON(len == 0);
 
 	if (len == 1) {
-		r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
+		r = dsi_vc_send_short(ix, channel, DSI_DT_DCS_SHORT_WRITE_0,
 				data[0], 0);
 	} else if (len == 2) {
-		r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
+		r = dsi_vc_send_short(ix, channel, DSI_DT_DCS_SHORT_WRITE_1,
 				data[0] | (data[1] << 8), 0);
 	} else {
 		/* 0x39 = DCS Long Write */
-		r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
+		r = dsi_vc_send_long(ix, channel, DSI_DT_DCS_LONG_WRITE,
 				data, len, 0);
 	}
 
@@ -2075,15 +2254,16 @@ int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
 }
 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
 
-int dsi_vc_dcs_write(int channel, u8 *data, int len)
+int dsi_vc_dcs_write(enum omap_dsi_index ix, int channel,
+	u8 *data, int len)
 {
 	int r;
 
-	r = dsi_vc_dcs_write_nosync(channel, data, len);
+	r = dsi_vc_dcs_write_nosync(ix, channel, data, len);
 	if (r)
 		goto err;
 
-	r = dsi_vc_send_bta_sync(channel);
+	r = dsi_vc_send_bta_sync(ix, channel);
 	if (r)
 		goto err;
 
@@ -2095,47 +2275,51 @@ err:
 }
 EXPORT_SYMBOL(dsi_vc_dcs_write);
 
-int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
+int dsi_vc_dcs_write_0(enum omap_dsi_index ix, int channel,
+	u8 dcs_cmd)
 {
-	return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
+	return dsi_vc_dcs_write(ix, channel, &dcs_cmd, 1);
 }
 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
 
-int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
+int dsi_vc_dcs_write_1(enum omap_dsi_index ix, int channel,
+	u8 dcs_cmd, u8 param)
 {
 	u8 buf[2];
 	buf[0] = dcs_cmd;
 	buf[1] = param;
-	return dsi_vc_dcs_write(channel, buf, 2);
+	return dsi_vc_dcs_write(ix, channel, buf, 2);
 }
 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
 
-int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
+int dsi_vc_dcs_read(enum omap_dsi_index ix, int channel,
+	u8 dcs_cmd, u8 *buf, int buflen)
 {
 	u32 val;
 	u8 dt;
 	int r;
+	struct dsi_struct *p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
-	if (dsi.debug_read)
+	if (p_dsi->debug_read)
 		DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
 
-	r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
+	r = dsi_vc_send_short(ix, channel, DSI_DT_DCS_READ, dcs_cmd, 0);
 	if (r)
 		goto err;
 
-	r = dsi_vc_send_bta_sync(channel);
+	r = dsi_vc_send_bta_sync(ix, channel);
 	if (r)
 		goto err;
 
 	/* RX_FIFO_NOT_EMPTY */
-	if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
+	if (REG_GET(ix, DSI_VC_CTRL(channel), 20, 20) == 0) {
 		DSSERR("RX fifo empty when trying to read.\n");
 		r = -EIO;
 		goto err;
 	}
 
-	val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-	if (dsi.debug_read)
+	val = dsi_read_reg(ix, DSI_VC_SHORT_PACKET_HEADER(channel));
+	if (p_dsi->debug_read)
 		DSSDBG("\theader: %08x\n", val);
 	dt = FLD_GET(val, 5, 0);
 	if (dt == DSI_DT_RX_ACK_WITH_ERR) {
@@ -2146,7 +2330,7 @@ int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
 
 	} else if (dt == DSI_DT_RX_SHORT_READ_1) {
 		u8 data = FLD_GET(val, 15, 8);
-		if (dsi.debug_read)
+		if (p_dsi->debug_read)
 			DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
 
 		if (buflen < 1) {
@@ -2159,7 +2343,7 @@ int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
 		return 1;
 	} else if (dt == DSI_DT_RX_SHORT_READ_2) {
 		u16 data = FLD_GET(val, 23, 8);
-		if (dsi.debug_read)
+		if (p_dsi->debug_read)
 			DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
 
 		if (buflen < 2) {
@@ -2174,7 +2358,7 @@ int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
 	} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
 		int w;
 		int len = FLD_GET(val, 23, 8);
-		if (dsi.debug_read)
+		if (p_dsi->debug_read)
 			DSSDBG("\tDCS long response, len %d\n", len);
 
 		if (len > buflen) {
@@ -2185,8 +2369,8 @@ int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
 		/* two byte checksum ends the packet, not included in len */
 		for (w = 0; w < len + 2;) {
 			int b;
-			val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
-			if (dsi.debug_read)
+			val = dsi_read_reg(ix, DSI_VC_SHORT_PACKET_HEADER(channel));
+			if (p_dsi->debug_read)
 				DSSDBG("\t\t%02x %02x %02x %02x\n",
 						(val >> 0) & 0xff,
 						(val >> 8) & 0xff,
@@ -2217,11 +2401,12 @@ err:
 }
 EXPORT_SYMBOL(dsi_vc_dcs_read);
 
-int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
+int dsi_vc_dcs_read_1(enum omap_dsi_index ix, int channel,
+	u8 dcs_cmd, u8 *data)
 {
 	int r;
 
-	r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
+	r = dsi_vc_dcs_read(ix, channel, dcs_cmd, data, 1);
 
 	if (r < 0)
 		return r;
@@ -2233,11 +2418,12 @@ int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
 }
 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
 
-int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data)
+int dsi_vc_dcs_read_2(enum omap_dsi_index ix, int channel,
+	u8 dcs_cmd, u16 *data)
 {
 	int r;
 
-	r = dsi_vc_dcs_read(channel, dcs_cmd, (u8 *)data, 2);
+	r = dsi_vc_dcs_read(ix, channel, dcs_cmd, (u8 *)data, 2);
 
 	if (r < 0)
 		return r;
@@ -2249,22 +2435,24 @@ int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data)
 }
 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
 
-int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
+int dsi_vc_set_max_rx_packet_size(enum omap_dsi_index ix,
+	int channel, u16 len)
 {
 	int r;
-	r = dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
+	r = dsi_vc_send_short(ix, channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
 			len, 0);
 
 	if (r)
 		return r;
 
-	r = dsi_vc_send_bta_sync(channel);
+	r = dsi_vc_send_bta_sync(ix, channel);
 
 	return r;
 }
 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
 
-static void dsi_set_lp_rx_timeout(unsigned long ns)
+static void dsi_set_lp_rx_timeout(enum omap_dsi_index ix,
+	unsigned long ns)
 {
 	u32 r;
 	unsigned x4, x16;
@@ -2273,7 +2461,7 @@ static void dsi_set_lp_rx_timeout(unsigned long ns)
 
 	/* ticks in DSI_FCK */
 
-	fck = dsi_fclk_rate();
+	fck = dsi_fclk_rate(ix);
 	ticks = (fck / 1000 / 1000) * ns / 1000;
 	x4 = 0;
 	x16 = 0;
@@ -2303,12 +2491,12 @@ static void dsi_set_lp_rx_timeout(unsigned long ns)
 		x16 = 1;
 	}
 
-	r = dsi_read_reg(DSI_TIMING2);
+	r = dsi_read_reg(ix, DSI_TIMING2);
 	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
 	r = FLD_MOD(r, x16, 14, 14);	/* LP_RX_TO_X16 */
 	r = FLD_MOD(r, x4, 13, 13);	/* LP_RX_TO_X4 */
 	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
-	dsi_write_reg(DSI_TIMING2, r);
+	dsi_write_reg(ix, DSI_TIMING2, r);
 
 	DSSDBG("LP_RX_TO %lu ns (%#lx ticks%s%s)\n",
 			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
@@ -2316,7 +2504,8 @@ static void dsi_set_lp_rx_timeout(unsigned long ns)
 			ticks, x4 ? " x4" : "", x16 ? " x16" : "");
 }
 
-static void dsi_set_ta_timeout(unsigned long ns)
+static void dsi_set_ta_timeout(enum omap_dsi_index ix,
+	unsigned long ns)
 {
 	u32 r;
 	unsigned x8, x16;
@@ -2324,7 +2513,7 @@ static void dsi_set_ta_timeout(unsigned long ns)
 	unsigned long ticks;
 
 	/* ticks in DSI_FCK */
-	fck = dsi_fclk_rate();
+	fck = dsi_fclk_rate(ix);
 	ticks = (fck / 1000 / 1000) * ns / 1000;
 	x8 = 0;
 	x16 = 0;
@@ -2354,12 +2543,12 @@ static void dsi_set_ta_timeout(unsigned long ns)
 		x16 = 1;
 	}
 
-	r = dsi_read_reg(DSI_TIMING1);
+	r = dsi_read_reg(ix, DSI_TIMING1);
 	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
 	r = FLD_MOD(r, x16, 30, 30);	/* TA_TO_X16 */
 	r = FLD_MOD(r, x8, 29, 29);	/* TA_TO_X8 */
 	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
-	dsi_write_reg(DSI_TIMING1, r);
+	dsi_write_reg(ix, DSI_TIMING1, r);
 
 	DSSDBG("TA_TO %lu ns (%#lx ticks%s%s)\n",
 			(ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
@@ -2367,7 +2556,8 @@ static void dsi_set_ta_timeout(unsigned long ns)
 			ticks, x8 ? " x8" : "", x16 ? " x16" : "");
 }
 
-static void dsi_set_stop_state_counter(unsigned long ns)
+static void dsi_set_stop_state_counter(enum omap_dsi_index ix,
+	unsigned long ns)
 {
 	u32 r;
 	unsigned x4, x16;
@@ -2376,7 +2566,7 @@ static void dsi_set_stop_state_counter(unsigned long ns)
 
 	/* ticks in DSI_FCK */
 
-	fck = dsi_fclk_rate();
+	fck = dsi_fclk_rate(ix);
 	ticks = (fck / 1000 / 1000) * ns / 1000;
 	x4 = 0;
 	x16 = 0;
@@ -2407,12 +2597,12 @@ static void dsi_set_stop_state_counter(unsigned long ns)
 		x16 = 1;
 	}
 
-	r = dsi_read_reg(DSI_TIMING1);
+	r = dsi_read_reg(ix, DSI_TIMING1);
 	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
 	r = FLD_MOD(r, x16, 14, 14);	/* STOP_STATE_X16_IO */
 	r = FLD_MOD(r, x4, 13, 13);	/* STOP_STATE_X4_IO */
 	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
-	dsi_write_reg(DSI_TIMING1, r);
+	dsi_write_reg(ix, DSI_TIMING1, r);
 
 	DSSDBG("STOP_STATE_COUNTER %lu ns (%#lx ticks%s%s)\n",
 			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
@@ -2420,7 +2610,8 @@ static void dsi_set_stop_state_counter(unsigned long ns)
 			ticks, x4 ? " x4" : "", x16 ? " x16" : "");
 }
 
-static void dsi_set_hs_tx_timeout(unsigned long ns)
+static void dsi_set_hs_tx_timeout(enum omap_dsi_index ix,
+	unsigned long ns)
 {
 	u32 r;
 	unsigned x4, x16;
@@ -2429,7 +2620,7 @@ static void dsi_set_hs_tx_timeout(unsigned long ns)
 
 	/* ticks in TxByteClkHS */
 
-	fck = dsi_get_txbyteclkhs();
+	fck = dsi_get_txbyteclkhs(ix);
 	ticks = (fck / 1000 / 1000) * ns / 1000;
 	x4 = 0;
 	x16 = 0;
@@ -2459,12 +2650,12 @@ static void dsi_set_hs_tx_timeout(unsigned long ns)
 		x16 = 1;
 	}
 
-	r = dsi_read_reg(DSI_TIMING2);
+	r = dsi_read_reg(ix, DSI_TIMING2);
 	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
 	r = FLD_MOD(r, x16, 30, 30);	/* HS_TX_TO_X16 */
 	r = FLD_MOD(r, x4, 29, 29);	/* HS_TX_TO_X8 (4 really) */
 	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
-	dsi_write_reg(DSI_TIMING2, r);
+	dsi_write_reg(ix, DSI_TIMING2, r);
 
 	DSSDBG("HS_TX_TO %lu ns (%#lx ticks%s%s)\n",
 			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
@@ -2475,22 +2666,27 @@ static int dsi_proto_config(struct omap_dss_device *dssdev)
 {
 	u32 r;
 	int buswidth = 0;
+	struct dsi_struct *p_dsi;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
-	dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
+	dsi_config_tx_fifo(ix, DSI_FIFO_SIZE_32,
 			DSI_FIFO_SIZE_32,
 			DSI_FIFO_SIZE_32,
 			DSI_FIFO_SIZE_32);
 
-	dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
+	dsi_config_rx_fifo(ix, DSI_FIFO_SIZE_32,
 			DSI_FIFO_SIZE_32,
 			DSI_FIFO_SIZE_32,
 			DSI_FIFO_SIZE_32);
 
 	/* XXX what values for the timeouts? */
-	dsi_set_stop_state_counter(1000);
-	dsi_set_ta_timeout(6400000);
-	dsi_set_lp_rx_timeout(48000);
-	dsi_set_hs_tx_timeout(1000000);
+	dsi_set_stop_state_counter(ix, 1000);
+	dsi_set_ta_timeout(ix, 6400000);
+	dsi_set_lp_rx_timeout(ix, 48000);
+	dsi_set_hs_tx_timeout(ix, 1000000);
 
 	switch (dssdev->ctrl.pixel_size) {
 	case 16:
@@ -2506,26 +2702,45 @@ static int dsi_proto_config(struct omap_dss_device *dssdev)
 		BUG();
 	}
 
-	r = dsi_read_reg(DSI_CTRL);
-	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
-	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
+	r = dsi_read_reg(ix, DSI_CTRL);
+	r = FLD_MOD(r, (cpu_is_omap44xx()) ? 0 : 1,
+			1, 1);				/* CS_RX_EN */
+	r = FLD_MOD(r, (cpu_is_omap44xx()) ? 0 : 1,
+			2, 2);				/* ECC_RX_EN */
 	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
 	r = FLD_MOD(r, 1, 4, 4);	/* VP_CLK_RATIO, always 1, see errata*/
 	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
 	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
+	r = FLD_MOD(r, (cpu_is_omap44xx()) ? 1 : 0,
+			9, 9);	/*VP_DE_POL */
+	r = FLD_MOD(r, (cpu_is_omap44xx()) ? 1 : 0,
+			11, 11);			/*VP_VSYNC_POL */
 	r = FLD_MOD(r, 2, 13, 12);	/* LINE_BUFFER, 2 lines */
 	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
-	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
-	r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
-	r = FLD_MOD(r, 0, 25, 25);	/* DCS_CMD_CODE, 1=start, 0=continue */
-
-	dsi_write_reg(DSI_CTRL, r);
-
-	dsi_vc_initial_config(0);
-	dsi_vc_initial_config(1);
-	dsi_vc_initial_config(2);
-	dsi_vc_initial_config(3);
+	r = FLD_MOD(r, (cpu_is_omap44xx()) ? 0 : 1,
+			19, 19);	/* EOT_ENABLE */
+	if (cpu_is_omap34xx()) {
+		r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
+		r = FLD_MOD(r, 0, 25, 25);	/* DCS_CMD_CODE */
+	}
+	dsi_write_reg(ix, DSI_CTRL, r);
 
+	dsi_vc_initial_config(ix, 0);
+	if (cpu_is_omap44xx())
+		dsi_vc_initial_config_vp(ix, 1);
+	else
+		dsi_vc_initial_config(ix, 1);
+	dsi_vc_initial_config(ix, 2);
+	dsi_vc_initial_config(ix, 3);
+
+	/* In Present OMAP4 configuration, 2 VC's send data
+	* to the same peripheral */
+	if (cpu_is_omap44xx()) {
+		p_dsi->vc[0].dest_per = 0;
+		p_dsi->vc[1].dest_per = 0;
+		p_dsi->vc[2].dest_per = 0;
+		p_dsi->vc[3].dest_per = 0;
+	}
 	return 0;
 }
 
@@ -2539,26 +2754,29 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
 	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
 	unsigned ths_eot;
 	u32 r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
-	r = dsi_read_reg(DSI_DSIPHY_CFG0);
+	r = dsi_read_reg(ix, DSI_DSIPHY_CFG0);
 	ths_prepare = FLD_GET(r, 31, 24);
 	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
 	ths_zero = ths_prepare_ths_zero - ths_prepare;
 	ths_trail = FLD_GET(r, 15, 8);
 	ths_exit = FLD_GET(r, 7, 0);
 
-	r = dsi_read_reg(DSI_DSIPHY_CFG1);
+	r = dsi_read_reg(ix, DSI_DSIPHY_CFG1);
 	tlpx = FLD_GET(r, 22, 16) * 2;
 	tclk_trail = FLD_GET(r, 15, 8);
 	tclk_zero = FLD_GET(r, 7, 0);
 
-	r = dsi_read_reg(DSI_DSIPHY_CFG2);
+	r = dsi_read_reg(ix, DSI_DSIPHY_CFG2);
 	tclk_prepare = FLD_GET(r, 7, 0);
 
 	/* min 8*UI */
 	tclk_pre = 20;
 	/* min 60ns + 52*UI */
-	tclk_post = ns2ddr(60) + 26;
+	tclk_post = ns2ddr(ix, 60) + 26;
 
 	/* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
 	if (dssdev->phy.dsi.data1_lane != 0 &&
@@ -2574,10 +2792,10 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
 	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
 	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
 
-	r = dsi_read_reg(DSI_CLK_TIMING);
+	r = dsi_read_reg(ix, DSI_CLK_TIMING);
 	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
 	r = FLD_MOD(r, ddr_clk_post, 7, 0);
-	dsi_write_reg(DSI_CLK_TIMING, r);
+	dsi_write_reg(ix, DSI_CLK_TIMING, r);
 
 	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
 			ddr_clk_pre,
@@ -2591,7 +2809,7 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
 
 	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
 		FLD_VAL(exit_hs_mode_lat, 15, 0);
-	dsi_write_reg(DSI_VM_TIMING7, r);
+	dsi_write_reg(ix, DSI_VM_TIMING7, r);
 
 	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
 			enter_hs_mode_lat, exit_hs_mode_lat);
@@ -2601,19 +2819,19 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
 #define DSI_DECL_VARS \
 	int __dsi_cb = 0; u32 __dsi_cv = 0;
 
-#define DSI_FLUSH(ch) \
+#define DSI_FLUSH(ix, ch) \
 	if (__dsi_cb > 0) { \
 		/*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
-		dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
+		dsi_write_reg(ix, DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
 		__dsi_cb = __dsi_cv = 0; \
 	}
 
-#define DSI_PUSH(ch, data) \
+#define DSI_PUSH(ix, ch, data) \
 	do { \
 		__dsi_cv |= (data) << (__dsi_cb * 8); \
 		/*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
 		if (++__dsi_cb > 3) \
-			DSI_FLUSH(ch); \
+			DSI_FLUSH(ix, ch); \
 	} while (0)
 
 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
@@ -2633,9 +2851,14 @@ static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
 	int horiz_inc;
 	int current_x;
 	struct omap_overlay *ovl;
+	struct dsi_struct *p_dsi;
+	enum omap_dsi_index ix;
 
 	debug_irq = 0;
 
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
 	DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
 			x, y, w, h);
 
@@ -2658,7 +2881,7 @@ static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
 	 * in fifo */
 
 	/* When using CPU, max long packet size is TX buffer size */
-	max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
+	max_dsi_packet_size = p_dsi->vc[0].fifo_size * 32 * 4;
 
 	/* we seem to get better perf if we divide the tx fifo to half,
 	   and while the other half is being sent, we fill the other half
@@ -2687,12 +2910,12 @@ static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
 #if 1
 		/* using fifo not empty */
 		/* TX_FIFO_NOT_EMPTY */
-		while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
+		while (FLD_GET(dsi_read_reg(ix, DSI_VC_CTRL(0)), 5, 5)) {
 			fifo_stalls++;
 			if (fifo_stalls > 0xfffff) {
 				DSSERR("fifo stalls overflow, pixels left %d\n",
 						pixels_left);
-				dsi_if_enable(0);
+				dsi_if_enable(ix, 0);
 				return -EIO;
 			}
 			udelay(1);
@@ -2724,17 +2947,17 @@ static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
 
 		pixels_left -= pixels;
 
-		dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
+		dsi_vc_write_long_header(ix, 0, DSI_DT_DCS_LONG_WRITE,
 				1 + pixels * bytespp, 0);
 
-		DSI_PUSH(0, dcs_cmd);
+		DSI_PUSH(ix, 0, dcs_cmd);
 
 		while (pixels-- > 0) {
 			u32 pix = __raw_readl(data++);
 
-			DSI_PUSH(0, (pix >> 16) & 0xff);
-			DSI_PUSH(0, (pix >> 8) & 0xff);
-			DSI_PUSH(0, (pix >> 0) & 0xff);
+			DSI_PUSH(ix, 0, (pix >> 16) & 0xff);
+			DSI_PUSH(ix, 0, (pix >> 8) & 0xff);
+			DSI_PUSH(ix, 0, (pix >> 0) & 0xff);
 
 			current_x++;
 			if (current_x == x+w) {
@@ -2743,7 +2966,7 @@ static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
 			}
 		}
 
-		DSI_FLUSH(0);
+		DSI_FLUSH(ix, 0);
 	}
 
 	return 0;
@@ -2759,16 +2982,26 @@ static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
 	unsigned packet_payload;
 	unsigned packet_len;
 	u32 l;
-	const unsigned channel = dsi.update_channel;
+	struct dsi_struct *p_dsi;
+	enum omap_dsi_index ix;
+	unsigned channel;
+	bool use_te_trigger;
 	/* line buffer is 1024 x 24bits */
 	/* XXX: for some reason using full buffer size causes considerable TX
 	 * slowdown with update sizes that fill the whole buffer */
 	const unsigned line_buf_size = 1023 * 3;
 
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	channel = p_dsi->update_channel;
+
+	use_te_trigger = p_dsi->te_enabled && !p_dsi->use_ext_te;
+
 	DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
 			x, y, w, h);
 
-	dsi_vc_config_vp(channel);
+	dsi_vc_config_vp(ix, channel);
 
 	bytespp	= dssdev->ctrl.pixel_size / 8;
 	bytespl = w * bytespp;
@@ -2789,15 +3022,16 @@ static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
 		total_len += (bytespf % packet_payload) + 1;
 
 	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
-	dsi_write_reg(DSI_VC_TE(channel), l);
+	dsi_write_reg(ix, DSI_VC_TE(channel), l);
 
-	dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
+	dsi_vc_write_long_header(ix, channel, DSI_DT_DCS_LONG_WRITE,
+			packet_len, 0);
 
-	if (dsi.te_enabled)
+	if (use_te_trigger)
 		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
 	else
 		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
-	dsi_write_reg(DSI_VC_TE(channel), l);
+	dsi_write_reg(ix, DSI_VC_TE(channel), l);
 
 	/* We put SIDLEMODE to no-idle for the duration of the transfer,
 	 * because DSS interrupts are not capable of waking up the CPU and the
@@ -2807,22 +3041,24 @@ static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
 	 */
 	dispc_disable_sidle();
 
-	dsi_perf_mark_start();
+	dsi_perf_mark_start(ix);
 
-	schedule_delayed_work(&dsi.framedone_timeout_work,
+	schedule_delayed_work(&p_dsi->framedone_timeout_work,
 			msecs_to_jiffies(250));
 
 	dss_start_update(dssdev);
 
-	if (dsi.te_enabled) {
+	if (use_te_trigger) {
 		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
 		 * for TE is longer than the timer allows */
-		REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
-
-		dsi_vc_send_bta(channel);
+		REG_FLD_MOD(ix, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
 
+		if (cpu_is_omap44xx())
+			dsi_vc_send_bta(ix, 0);
+		else
+			dsi_vc_send_bta(ix, channel);
 #ifdef DSI_CATCH_MISSING_TE
-		mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
+		mod_timer(&p_dsi->te_timer, jiffies + msecs_to_jiffies(250));
 #endif
 	}
 }
@@ -2830,23 +3066,37 @@ static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
 #ifdef DSI_CATCH_MISSING_TE
 static void dsi_te_timeout(unsigned long arg)
 {
-	DSSERR("TE not received for 250ms!\n");
+	DSSERR("DSI TE not received for 250ms!\n");
+}
+
+static void dsi2_te_timeout(unsigned long arg)
+{
+	DSSERR("DSI2 TE not received for 250ms!\n");
 }
 #endif
 
 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
 {
 	int r;
-	const int channel = dsi.update_channel;
+	int channel;
+
+	if (!cpu_is_omap44xx())
+		channel = dsi1.update_channel;
+	else
+		channel = 0;
 
 	DSSERR("Framedone not received for 250ms!\n");
 
 	/* SIDLEMODE back to smart-idle */
 	dispc_enable_sidle();
 
-	if (dsi.te_enabled) {
+	if (cpu_is_omap44xx())
+		/* Ensures recovery of DISPC after a failed lcd_enable*/
+		dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD, 0);
+
+	if (dsi1.te_enabled) {
 		/* enable LP_RX_TO again after the TE */
-		REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
+		REG_FLD_MOD(DSI1, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
 	}
 
 	/* Send BTA after the frame. We need this for the TE to work, as TE
@@ -2858,17 +3108,63 @@ static void dsi_framedone_timeout_work_callback(struct work_struct *work)
 	 * make sure that the transfer has been completed. It would be more
 	 * optimal, but more complex, to wait only just before starting next
 	 * transfer. */
-	r = dsi_vc_send_bta_sync(channel);
+	r = dsi_vc_send_bta_sync(DSI1, channel);
 	if (r)
 		DSSERR("BTA after framedone failed\n");
 
 	/* RX_FIFO_NOT_EMPTY */
-	if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
+	if (REG_GET(DSI1, DSI_VC_CTRL(channel), 20, 20)) {
+		DSSERR("Received error during frame transfer:\n");
+		dsi_vc_flush_receive_data(DSI1, channel);
+	}
+
+	dsi1.framedone_callback(-ETIMEDOUT, dsi1.framedone_data);
+}
+
+static void dsi2_framedone_timeout_work_callback(struct work_struct *work)
+{
+	int r;
+	int channel;
+
+	if (!cpu_is_omap44xx())
+		channel = dsi2.update_channel;
+	else
+		channel = 0;
+
+	DSSERR("Framedone2 not received for 250ms!\n");
+
+	/* SIDLEMODE back to smart-idle */
+	dispc_enable_sidle();
+
+	if (cpu_is_omap44xx())
+		/* Ensures recovery of DISPC after a failed lcd_enable*/
+		dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD2, 0);
+
+	if (dsi2.te_enabled) {
+		/* enable LP_RX_TO again after the TE */
+		REG_FLD_MOD(DSI2, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
+	}
+
+	/* Send BTA after the frame. We need this for the TE to work, as TE
+	 * trigger is only sent for BTAs without preceding packet. Thus we need
+	 * to BTA after the pixel packets so that next BTA will cause TE
+	 * trigger.
+	 *
+	 * This is not needed when TE is not in use, but we do it anyway to
+	 * make sure that the transfer has been completed. It would be more
+	 * optimal, but more complex, to wait only just before starting next
+	 * transfer. */
+	r = dsi_vc_send_bta_sync(DSI2, channel);
+	if (r)
+		DSSERR("BTA after framedone2 failed\n");
+
+	/* RX_FIFO_NOT_EMPTY */
+	if (REG_GET(DSI2, DSI_VC_CTRL(channel), 20, 20)) {
 		DSSERR("Received error during frame transfer:\n");
-		dsi_vc_flush_receive_data(channel);
+		dsi_vc_flush_receive_data(DSI2, channel);
 	}
 
-	dsi.framedone_callback(-ETIMEDOUT, dsi.framedone_data);
+	dsi2.framedone_callback(-ETIMEDOUT, dsi2.framedone_data);
 }
 
 static void dsi_framedone_irq_callback(void *data, u32 mask)
@@ -2880,20 +3176,41 @@ static void dsi_framedone_irq_callback(void *data, u32 mask)
 
 	/* SIDLEMODE back to smart-idle */
 	dispc_enable_sidle();
+	schedule_work(&dsi1.framedone_work);
+}
 
-	schedule_work(&dsi.framedone_work);
+static void dsi2_framedone_irq_callback(void *data, u32 mask)
+{
+	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
+	 * turns itself off. However, DSI still has the pixels in its buffers,
+	 * and is sending the data.
+	 */
+
+	/* SIDLEMODE back to smart-idle */
+	dispc_enable_sidle();
+	schedule_work(&dsi2.framedone_work);
 }
 
-static void dsi_handle_framedone(void)
+static void dsi_handle_framedone(enum omap_dsi_index ix)
 {
 	int r;
-	const int channel = dsi.update_channel;
+	int channel;
+	struct dsi_struct *p_dsi;
+	bool use_te_trigger;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	use_te_trigger = p_dsi->te_enabled && !p_dsi->use_ext_te;
+
+	if (!cpu_is_omap44xx())
+		channel = p_dsi->update_channel;
+	else
+		channel = 0;
 
 	DSSDBG("FRAMEDONE\n");
 
-	if (dsi.te_enabled) {
+	if (use_te_trigger) {
 		/* enable LP_RX_TO again after the TE */
-		REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
+		REG_FLD_MOD(ix, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
 	}
 
 	/* Send BTA after the frame. We need this for the TE to work, as TE
@@ -2905,18 +3222,19 @@ static void dsi_handle_framedone(void)
 	 * make sure that the transfer has been completed. It would be more
 	 * optimal, but more complex, to wait only just before starting next
 	 * transfer. */
-	r = dsi_vc_send_bta_sync(channel);
+	r = dsi_vc_send_bta_sync(ix, channel);
 	if (r)
 		DSSERR("BTA after framedone failed\n");
 
 	/* RX_FIFO_NOT_EMPTY */
-	if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
-		DSSERR("Received error during frame transfer:\n");
-		dsi_vc_flush_receive_data(channel);
+	if (REG_GET(ix, DSI_VC_CTRL(channel), 20, 20)) {
+		if (!cpu_is_omap44xx())
+			DSSERR("Received error during frame transfer:\n");
+		dsi_vc_flush_receive_data(ix, channel);
 	}
 
 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
-	dispc_fake_vsync_irq();
+	dispc_fake_vsync_irq(ix);
 #endif
 }
 
@@ -2924,19 +3242,35 @@ static void dsi_framedone_work_callback(struct work_struct *work)
 {
 	DSSDBGF();
 
-	cancel_delayed_work_sync(&dsi.framedone_timeout_work);
+	cancel_delayed_work_sync(&dsi1.framedone_timeout_work);
 
-	dsi_handle_framedone();
+	dsi_handle_framedone(DSI1);
 
-	dsi_perf_show("DISPC");
+	dsi_perf_show(DSI1, "DISPC");
 
-	dsi.framedone_callback(0, dsi.framedone_data);
+	dsi1.framedone_callback(0, dsi1.framedone_data);
+}
+
+static void dsi2_framedone_work_callback(struct work_struct *work)
+{
+	DSSDBGF();
+
+	cancel_delayed_work_sync(&dsi2.framedone_timeout_work);
+
+	dsi_handle_framedone(DSI2);
+
+	dsi_perf_show(DSI2, "DISPC");
+
+	dsi2.framedone_callback(0, dsi2.framedone_data);
 }
 
 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
 				    u16 *x, u16 *y, u16 *w, u16 *h)
 {
 	u16 dw, dh;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	dssdev->driver->get_resolution(dssdev, &dw, &dh);
 
@@ -2955,11 +3289,11 @@ int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
 	if (*w == 0 || *h == 0)
 		return -EINVAL;
 
-	dsi_perf_mark_setup();
+	dsi_perf_mark_setup(ix);
 
 	if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
 		dss_setup_partial_planes(dssdev, x, y, w, h);
-		dispc_set_lcd_size(*w, *h);
+		dispc_set_lcd_size(dssdev->channel, *w, *h);
 	}
 
 	return 0;
@@ -2971,22 +3305,28 @@ int omap_dsi_update(struct omap_dss_device *dssdev,
 		u16 x, u16 y, u16 w, u16 h,
 		void (*callback)(int, void *), void *data)
 {
-	dsi.update_channel = channel;
+	struct dsi_struct *p_dsi;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	p_dsi->update_channel = channel;
 
 	if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
-		dsi.framedone_callback = callback;
-		dsi.framedone_data = data;
+		p_dsi->framedone_callback = callback;
+		p_dsi->framedone_data = data;
 
-		dsi.update_region.x = x;
-		dsi.update_region.y = y;
-		dsi.update_region.w = w;
-		dsi.update_region.h = h;
-		dsi.update_region.device = dssdev;
+		p_dsi->update_region.x = x;
+		p_dsi->update_region.y = y;
+		p_dsi->update_region.w = w;
+		p_dsi->update_region.h = h;
+		p_dsi->update_region.device = dssdev;
 
 		dsi_update_screen_dispc(dssdev, x, y, w, h);
 	} else {
 		dsi_update_screen_l4(dssdev, x, y, w, h);
-		dsi_perf_show("L4");
+		dsi_perf_show(ix, "L4");
 		callback(0, data);
 	}
 
@@ -3000,21 +3340,42 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
 {
 	int r;
 
-	r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
-			DISPC_IRQ_FRAMEDONE);
+	r = omap_dispc_register_isr((dssdev->channel == OMAP_DSS_CHANNEL_LCD) ?
+			dsi_framedone_irq_callback : dsi2_framedone_irq_callback,
+			NULL, (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ?
+			DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2);
 	if (r) {
 		DSSERR("can't get FRAMEDONE irq\n");
 		return r;
 	}
 
-	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
+	dispc_set_lcd_display_type(dssdev->channel,
+					OMAP_DSS_LCD_DISPLAY_TFT);
 
-	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
+	dispc_set_parallel_interface_mode(dssdev->channel,
+					OMAP_DSS_PARALLELMODE_DSI);
 	dispc_enable_fifohandcheck(1);
 
-	dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
+	dispc_set_tft_data_lines(dssdev->channel, dssdev->ctrl.pixel_size);
+
+	if (cpu_is_omap44xx())
+		dispc_set_pol_freq(dssdev->channel, dssdev->panel.config,
+			dssdev->panel.acbi, dssdev->panel.acb);
 
-	{
+	if (cpu_is_omap44xx()) {
+		struct omap_video_timings timings = {
+			.hsw		= 4+1,
+			.hfp		= 4+1,
+			.hbp		= 4+1,
+			.vsw		= 0+1,
+			.vfp		= 0,
+			.vbp		= 1,
+			.x_res	= 864,
+			.y_res	= 480,
+		};
+
+		dispc_set_lcd_timings(dssdev->channel, &timings);
+	} else {
 		struct omap_video_timings timings = {
 			.hsw		= 1,
 			.hfp		= 1,
@@ -3024,7 +3385,7 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
 			.vbp		= 0,
 		};
 
-		dispc_set_lcd_timings(&timings);
+		dispc_set_lcd_timings(dssdev->channel, &timings);
 	}
 
 	return 0;
@@ -3032,14 +3393,19 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
 
 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
 {
-	omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
-			DISPC_IRQ_FRAMEDONE);
+	omap_dispc_unregister_isr((dssdev->channel == OMAP_DSS_CHANNEL_LCD) ?
+			dsi_framedone_irq_callback : dsi2_framedone_irq_callback,
+			NULL, (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ?
+			DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2);
 }
 
 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
 {
 	struct dsi_clock_info cinfo;
 	int r;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
 	/* we always use DSS2_FCK as input clock */
 	cinfo.use_dss2_fck = true;
@@ -3051,7 +3417,7 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
 	if (r)
 		return r;
 
-	r = dsi_pll_set_clock_div(&cinfo);
+	r = dsi_pll_set_clock_div(ix, &cinfo);
 	if (r) {
 		DSSERR("Failed to set dsi clocks\n");
 		return r;
@@ -3065,8 +3431,11 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
 	struct dispc_clock_info dispc_cinfo;
 	int r;
 	unsigned long long fck;
+	enum omap_dsi_index ix;
 
-	fck = dsi_get_dsi1_pll_rate();
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+
+	fck = dsi_get_dsi1_pll_rate(ix);
 
 	dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
 	dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
@@ -3077,7 +3446,7 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
 		return r;
 	}
 
-	r = dispc_set_clock_div(&dispc_cinfo);
+	r = dispc_set_clock_div(dssdev->channel, &dispc_cinfo);
 	if (r) {
 		DSSERR("Failed to set dispc clocks\n");
 		return r;
@@ -3088,9 +3457,15 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
 
 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
 {
-	int r;
+	int r, l = 0;
+	struct dsi_struct *p_dsi;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
 
-	_dsi_print_reset_status();
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
+	_dsi_print_reset_status(ix);
 
 	r = dsi_pll_init(dssdev, true, true);
 	if (r)
@@ -3100,8 +3475,11 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
 	if (r)
 		goto err1;
 
-	dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
-	dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
+	if (cpu_is_omap44xx())
+		dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
+	else
+		dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
+	dss_select_dsi_clk_source(ix, DSS_SRC_DSI2_PLL_FCLK);
 
 	DSSDBG("PLL OK\n");
 
@@ -3113,58 +3491,81 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
 	if (r)
 		goto err2;
 
-	_dsi_print_reset_status();
+	_dsi_print_reset_status(ix);
 
 	dsi_proto_timings(dssdev);
 	dsi_set_lp_clk_divisor(dssdev);
 
 	if (1)
-		_dsi_print_reset_status();
+		_dsi_print_reset_status(ix);
 
 	r = dsi_proto_config(dssdev);
 	if (r)
 		goto err3;
 
 	/* enable interface */
-	dsi_vc_enable(0, 1);
-	dsi_vc_enable(1, 1);
-	dsi_vc_enable(2, 1);
-	dsi_vc_enable(3, 1);
-	dsi_if_enable(1);
-	dsi_force_tx_stop_mode_io();
+	dsi_vc_enable(ix, 0, 1);
+	dsi_vc_enable(ix, 1, 1);
+	dsi_vc_enable(ix, 2, 1);
+	dsi_vc_enable(ix, 3, 1);
+	dsi_if_enable(ix, 1);
+	dsi_force_tx_stop_mode_io(ix);
+
+	/* magic OMAP4 registers */
+	dsi_write_reg(ix, DSI_DSIPHY_CFG12, 0x58);
+
+	l = dsi_read_reg(ix, DSI_DSIPHY_CFG14);
+	l = FLD_MOD(l, 1, 31, 31);
+	l = FLD_MOD(l, 0x54, 30, 23);
+	l = FLD_MOD(l, 1, 19, 19);
+	l = FLD_MOD(l, 1, 18, 18);
+	l = FLD_MOD(l, 7, 17, 14);
+	l = FLD_MOD(l, 1, 11, 11);
+	dsi_write_reg(ix, DSI_DSIPHY_CFG14, l);
+
+	l = 0;
+	l = dsi_read_reg(ix, DSI_DSIPHY_CFG8);
+	l = FLD_MOD(l, 1, 11, 11);
+	l = FLD_MOD(l, 0x10, 10, 6);
+	l = FLD_MOD(l, 1, 5, 5);
+	l = FLD_MOD(l, 0xE, 3, 0);
+	dsi_write_reg(ix, DSI_DSIPHY_CFG8, l);
 
 	return 0;
 err3:
-	dsi_complexio_uninit();
+	dsi_complexio_uninit(ix);
 err2:
 	dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
-	dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
+	dss_select_dsi_clk_source(ix, DSS_SRC_DSS1_ALWON_FCLK);
 err1:
-	dsi_pll_uninit();
+	dsi_pll_uninit(ix);
 err0:
 	return r;
 }
 
 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
 {
+	enum omap_dsi_index ix;
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+
 	dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
-	dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
-	dsi_complexio_uninit();
-	dsi_pll_uninit();
+	dss_select_dsi_clk_source(ix, DSS_SRC_DSS1_ALWON_FCLK);
+	dsi_complexio_uninit(ix);
+	dsi_pll_uninit(ix);
 }
 
-static int dsi_core_init(void)
+static int dsi_core_init(enum omap_dsi_index ix)
 {
 	/* Autoidle */
-	REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
+	REG_FLD_MOD(ix, DSI_SYSCONFIG, 1, 0, 0);
 
 	/* ENWAKEUP */
-	REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
+	REG_FLD_MOD(ix, DSI_SYSCONFIG, 1, 2, 2);
 
 	/* SIDLEMODE smart-idle */
-	REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
+	REG_FLD_MOD(ix, DSI_SYSCONFIG, 2, 4, 3);
 
-	_dsi_initialize_irq();
+	_dsi_initialize_irq(ix);
 
 	return 0;
 }
@@ -3172,12 +3573,18 @@ static int dsi_core_init(void)
 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
 {
 	int r = 0;
+	struct dsi_struct *p_dsi;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
 
 	DSSDBG("dsi_display_enable\n");
 
-	WARN_ON(!dsi_bus_is_locked());
+	WARN_ON(!dsi_bus_is_locked(ix));
 
-	mutex_lock(&dsi.lock);
+	mutex_lock(&p_dsi->lock);
 
 	r = omap_dss_start_device(dssdev);
 	if (r) {
@@ -3186,13 +3593,17 @@ int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
 	}
 
 	enable_clocks(1);
-	dsi_enable_pll_clock(1);
+	dsi_enable_pll_clock(ix, 1);
+
+	/* DSS_PWR_DSS_DSS_CTRL */
+	if (cpu_is_omap44xx())
+		omap_writel(0x00030007, 0x4A307100);
 
-	r = _dsi_reset();
+	r = _dsi_reset(ix);
 	if (r)
 		goto err1;
 
-	dsi_core_init();
+	dsi_core_init(ix);
 
 	r = dsi_display_init_dispc(dssdev);
 	if (r)
@@ -3202,7 +3613,9 @@ int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
 	if (r)
 		goto err2;
 
-	mutex_unlock(&dsi.lock);
+	p_dsi->use_ext_te = dssdev->phy.dsi.ext_te;
+
+	mutex_unlock(&p_dsi->lock);
 
 	return 0;
 
@@ -3210,10 +3623,10 @@ err2:
 	dsi_display_uninit_dispc(dssdev);
 err1:
 	enable_clocks(0);
-	dsi_enable_pll_clock(0);
+	dsi_enable_pll_clock(ix, 0);
 	omap_dss_stop_device(dssdev);
 err0:
-	mutex_unlock(&dsi.lock);
+	mutex_unlock(&p_dsi->lock);
 	DSSDBG("dsi_display_enable FAILED\n");
 	return r;
 }
@@ -3221,28 +3634,37 @@ EXPORT_SYMBOL(omapdss_dsi_display_enable);
 
 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
 {
+	struct dsi_struct *p_dsi;
+	enum omap_dsi_index ix;
+
+	ix = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? DSI1 : DSI2;
+	p_dsi = (ix == DSI1) ? &dsi1 : &dsi2;
+
 	DSSDBG("dsi_display_disable\n");
 
-	WARN_ON(!dsi_bus_is_locked());
+	WARN_ON(!dsi_bus_is_locked(ix));
 
-	mutex_lock(&dsi.lock);
+	mutex_lock(&p_dsi->lock);
 
 	dsi_display_uninit_dispc(dssdev);
 
 	dsi_display_uninit_dsi(dssdev);
 
 	enable_clocks(0);
-	dsi_enable_pll_clock(0);
+	dsi_enable_pll_clock(ix, 0);
 
 	omap_dss_stop_device(dssdev);
 
-	mutex_unlock(&dsi.lock);
+	mutex_unlock(&p_dsi->lock);
 }
 EXPORT_SYMBOL(omapdss_dsi_display_disable);
 
 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
 {
-	dsi.te_enabled = enable;
+	struct dsi_struct *p_dsi;
+	p_dsi = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? &dsi1 : &dsi2;
+
+	p_dsi->te_enabled = enable;
 	return 0;
 }
 EXPORT_SYMBOL(omapdss_dsi_enable_te);
@@ -3262,14 +3684,18 @@ void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 
 int dsi_init_display(struct omap_dss_device *dssdev)
 {
+	struct dsi_struct *p_dsi;
+
 	DSSDBG("DSI init\n");
 
+	p_dsi = (dssdev->channel == OMAP_DSS_CHANNEL_LCD) ? &dsi1 : &dsi2;
+
 	/* XXX these should be figured out dynamically */
 	dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
 		OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
 
-	dsi.vc[0].dssdev = dssdev;
-	dsi.vc[1].dssdev = dssdev;
+	p_dsi->vc[0].dssdev = dssdev;
+	p_dsi->vc[1].dssdev = dssdev;
 
 	return 0;
 }
@@ -3278,47 +3704,56 @@ int dsi_init(struct platform_device *pdev)
 {
 	u32 rev;
 	int r;
+	enum omap_dsi_index ix = DSI1;
 
-	spin_lock_init(&dsi.errors_lock);
-	dsi.errors = 0;
+	spin_lock_init(&dsi1.errors_lock);
+	dsi1.errors = 0;
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-	spin_lock_init(&dsi.irq_stats_lock);
-	dsi.irq_stats.last_reset = jiffies;
+	spin_lock_init(&dsi1.irq_stats_lock);
+	dsi1.irq_stats.last_reset = jiffies;
 #endif
 
-	init_completion(&dsi.bta_completion);
+	init_completion(&dsi1.bta_completion);
 
-	mutex_init(&dsi.lock);
-	sema_init(&dsi.bus_lock, 1);
+	mutex_init(&dsi1.lock);
+	sema_init(&dsi1.bus_lock, 1);
 
-	INIT_WORK(&dsi.framedone_work, dsi_framedone_work_callback);
-	INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
+	INIT_WORK(&dsi1.framedone_work, dsi_framedone_work_callback);
+	INIT_DELAYED_WORK_DEFERRABLE(&dsi1.framedone_timeout_work,
 			dsi_framedone_timeout_work_callback);
 
+	if (cpu_is_omap44xx()) {
+		r = request_irq(OMAP44XX_IRQ_DSS_DSI1, dsi_irq_handler,
+				0, "OMAP DSI", (void *)0);
+		if (r)
+			goto err2;
+	}
 #ifdef DSI_CATCH_MISSING_TE
-	init_timer(&dsi.te_timer);
-	dsi.te_timer.function = dsi_te_timeout;
-	dsi.te_timer.data = 0;
+	init_timer(&dsi1.te_timer);
+	dsi1.te_timer.function = dsi_te_timeout;
+	dsi1.te_timer.data = 0;
 #endif
-	dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
-	if (!dsi.base) {
+	dsi1.base = ioremap(DSI_BASE, DSI_SZ_REGS);
+	if (!dsi1.base) {
 		DSSERR("can't ioremap DSI\n");
 		r = -ENOMEM;
 		goto err1;
 	}
 
-	dsi.vdds_dsi_reg = dss_get_vdds_dsi();
-	if (IS_ERR(dsi.vdds_dsi_reg)) {
-		iounmap(dsi.base);
-		DSSERR("can't get VDDS_DSI regulator\n");
-		r = PTR_ERR(dsi.vdds_dsi_reg);
-		goto err2;
+	if (!cpu_is_omap44xx()) {
+		dsi1.vdds_dsi_reg = dss_get_vdds_dsi();
+		if (IS_ERR(dsi1.vdds_dsi_reg)) {
+			iounmap(dsi1.base);
+			DSSERR("can't get VDDS_DSI regulator\n");
+			r = PTR_ERR(dsi1.vdds_dsi_reg);
+			goto err2;
+		}
 	}
 
 	enable_clocks(1);
 
-	rev = dsi_read_reg(DSI_REVISION);
+	rev = dsi_read_reg(ix, DSI_REVISION);
 	printk(KERN_INFO "OMAP DSI rev %d.%d\n",
 	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 
@@ -3326,15 +3761,81 @@ int dsi_init(struct platform_device *pdev)
 
 	return 0;
 err2:
-	iounmap(dsi.base);
+	iounmap(dsi1.base);
+	if (cpu_is_omap44xx())
+		free_irq(OMAP44XX_IRQ_DSS_DSI1, (void *)0);
+err1:
+	return r;
+}
+
+int dsi2_init(struct platform_device *pdev)
+{
+	u32 rev;
+	int r;
+	enum omap_dsi_index ix = DSI2;
+
+	spin_lock_init(&dsi2.errors_lock);
+	dsi2.errors = 0;
+
+#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
+	spin_lock_init(&dsi2.irq_stats_lock);
+	dsi2.irq_stats.last_reset = jiffies;
+#endif
+
+	init_completion(&dsi2.bta_completion);
+
+	mutex_init(&dsi2.lock);
+	sema_init(&dsi2.bus_lock, 1);
+
+	INIT_WORK(&dsi2.framedone_work, dsi2_framedone_work_callback);
+	INIT_DELAYED_WORK_DEFERRABLE(&dsi2.framedone_timeout_work,
+			dsi2_framedone_timeout_work_callback);
+
+	r = request_irq(OMAP44XX_IRQ_DSS_DSI2, dsi_irq_handler,
+				0, "OMAP DSI2", (void *)0);
+	if (r)
+		goto err2;
+
+#ifdef DSI_CATCH_MISSING_TE
+	init_timer(&dsi2.te_timer);
+	dsi2.te_timer.function = dsi2_te_timeout;
+	dsi2.te_timer.data = 0;
+#endif
+	dsi2.te_enabled = true;
+
+	dsi2.base = ioremap(DSI2_BASE, DSI_SZ_REGS);
+	if (!dsi2.base) {
+		DSSERR("can't ioremap DSI2\n");
+		r = -ENOMEM;
+		goto err1;
+	}
+
+	enable_clocks(1);
+
+	rev = dsi_read_reg(ix, DSI_REVISION);
+	printk(KERN_INFO "OMAP DSI2 rev %d.%d\n",
+	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
+
+	enable_clocks(0);
+
+	return 0;
+err2:
+	iounmap(dsi2.base);
+	free_irq(OMAP44XX_IRQ_DSS_DSI2, (void *)0);
 err1:
 	return r;
 }
 
 void dsi_exit(void)
 {
-	iounmap(dsi.base);
+	iounmap(dsi1.base);
 
 	DSSDBG("omap_dsi_exit\n");
 }
 
+void dsi2_exit(void)
+{
+	iounmap(dsi2.base);
+
+	DSSDBG("omap_dsi2_exit\n");
+}
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 54344184dd73..db8bc715c564 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -33,7 +33,11 @@
 #include <plat/display.h>
 #include "dss.h"
 
+#ifndef CONFIG_ARCH_OMAP4
 #define DSS_BASE			0x48050000
+#else
+#define DSS_BASE			0x58000000
+#endif
 
 #define DSS_SZ_REGS			SZ_512
 
@@ -223,7 +227,13 @@ void dss_dump_clocks(struct seq_file *s)
 
 	seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 
-	seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
+	if (cpu_is_omap3630())
+		seq_printf(s, "dss1_alwon_fclk = %lu / %lu  = %lu\n",
+			dpll4_ck_rate,
+			dpll4_ck_rate / dpll4_m4_ck_rate,
+			dss_clk_get_rate(DSS_CLK_FCK1));
+	else
+		seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
 			dpll4_ck_rate,
 			dpll4_ck_rate / dpll4_m4_ck_rate,
 			dss_clk_get_rate(DSS_CLK_FCK1));
@@ -259,12 +269,17 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
 
 	b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
 
-	REG_FLD_MOD(DSS_CONTROL, b, 0, 0);	/* DISPC_CLK_SWITCH */
+	if (!cpu_is_omap44xx()) {
+		REG_FLD_MOD(DSS_CONTROL, b, 0, 0);	/* DISPC_CLK_SWITCH */
+	} else {
+		REG_FLD_MOD(DSS_CONTROL, b, 9, 8);	/* FCK_CLK_SWITCH */
+	}
 
 	dss.dispc_clk_source = clk_src;
 }
 
-void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
+void dss_select_dsi_clk_source(enum omap_dsi_index ix,
+	enum dss_clk_source clk_src)
 {
 	int b;
 
@@ -273,7 +288,14 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
 
 	b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
 
-	REG_FLD_MOD(DSS_CONTROL, b, 1, 1);	/* DSI_CLK_SWITCH */
+	if (ix == DSI1) {
+		REG_FLD_MOD(DSS_CONTROL, b, 1, 1);	/* DSI_CLK_SWITCH */
+		if (cpu_is_omap44xx())
+			REG_FLD_MOD(DSS_CONTROL, b, 0, 0);	/* LCD1_CLK_SWITCH */
+	} else {
+		REG_FLD_MOD(DSS_CONTROL, b, 10, 10);	/* DSI2_CLK_SWITCH */
+		REG_FLD_MOD(DSS_CONTROL, b, 12, 12);	/* LCD2_CLK_SWITCH */
+	}
 
 	dss.dsi_clk_source = clk_src;
 }
@@ -293,7 +315,8 @@ int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 {
 	unsigned long prate;
 
-	if (cinfo->fck_div > 16 || cinfo->fck_div == 0)
+	if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
+						cinfo->fck_div == 0)
 		return -EINVAL;
 
 	prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
@@ -329,7 +352,10 @@ int dss_get_clock_div(struct dss_clock_info *cinfo)
 	if (cpu_is_omap34xx()) {
 		unsigned long prate;
 		prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
-		cinfo->fck_div = prate / (cinfo->fck / 2);
+		if (cpu_is_omap3630())
+			cinfo->fck_div = prate / (cinfo->fck);
+		else
+			cinfo->fck_div = prate / (cinfo->fck / 2);
 	} else {
 		cinfo->fck_div = 0;
 	}
@@ -402,10 +428,14 @@ retry:
 
 		goto found;
 	} else if (cpu_is_omap34xx()) {
-		for (fck_div = 16; fck_div > 0; --fck_div) {
+		for (fck_div = (cpu_is_omap3630() ? 32 : 16);
+					fck_div > 0; --fck_div) {
 			struct dispc_clock_info cur_dispc;
 
-			fck = prate / fck_div * 2;
+			if (cpu_is_omap3630())
+				fck = prate / fck_div;
+			else
+				fck = prate / fck_div * 2;
 
 			if (fck > DISPC_MAX_FCK)
 				continue;
@@ -480,8 +510,8 @@ static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
 	if (irqstatus & (1<<0))	/* DISPC_IRQ */
 		dispc_irq_handler();
 #ifdef CONFIG_OMAP2_DSS_DSI
-	if (irqstatus & (1<<1))	/* DSI_IRQ */
-		dsi_irq_handler();
+	if (!cpu_is_omap44xx() && (irqstatus & (1<<1)))	/* DSI_IRQ */
+		dsi_irq_handler(0, NULL);
 #endif
 
 	return IRQ_HANDLED;
@@ -529,6 +559,13 @@ void dss_set_dac_pwrdn_bgz(bool enable)
 	REG_FLD_MOD(DSS_CONTROL, enable, 5, 5);	/* DAC Power-Down Control */
 }
 
+void dss_switch_tv_hdmi(int hdmi)
+{
+	REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15);	/* 0x1 for HDMI, 0x0 TV */
+	if (hdmi)
+		REG_FLD_MOD(DSS_CONTROL, 0, 9, 8);
+}
+
 int dss_init(bool skip_init)
 {
 	int r;
@@ -570,11 +607,16 @@ int dss_init(bool skip_init)
 	REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */
 #endif
 
-	r = request_irq(INT_24XX_DSS_IRQ,
-			cpu_is_omap24xx()
-			? dss_irq_handler_omap2
-			: dss_irq_handler_omap3,
-			0, "OMAP DSS", NULL);
+	if (!cpu_is_omap44xx())
+		r = request_irq(INT_24XX_DSS_IRQ,
+				cpu_is_omap24xx()
+				? dss_irq_handler_omap2
+				: dss_irq_handler_omap3,
+				0, "OMAP DSS", NULL);
+	else
+		r = request_irq(OMAP44XX_IRQ_DSS_DISPC,
+				dss_irq_handler_omap2,
+				0, "OMAP DSS", NULL);
 
 	if (r < 0) {
 		DSSERR("omap2 dss: request_irq failed\n");
@@ -602,7 +644,8 @@ int dss_init(bool skip_init)
 	return 0;
 
 fail2:
-	free_irq(INT_24XX_DSS_IRQ, NULL);
+	if (!cpu_is_omap44xx())
+		free_irq(INT_24XX_DSS_IRQ, NULL);
 fail1:
 	iounmap(dss.base);
 fail0:
@@ -614,8 +657,8 @@ void dss_exit(void)
 	if (cpu_is_omap34xx())
 		clk_put(dss.dpll4_m4_ck);
 
-	free_irq(INT_24XX_DSS_IRQ, NULL);
-
+	if (!cpu_is_omap44xx())
+		free_irq(INT_24XX_DSS_IRQ, NULL);
 	iounmap(dss.base);
 }
 
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 24326a5fd292..02cd5aed5c87 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -20,9 +20,12 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <plat/display.h>
 #ifndef __OMAP2_DSS_H
 #define __OMAP2_DSS_H
 
+#include <linux/interrupt.h>
+
 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
 #define DEBUG
 #endif
@@ -165,6 +168,38 @@ struct dsi_clock_info {
 	bool use_dss2_fck;
 };
 
+/*TODO: Move this structure to manager.c*/
+struct writeback_cache_data {
+	/* If true, cache changed, but not written to shadow registers. Set
+	 * in apply(), cleared when registers written. */
+	bool dirty;
+	/* If true, shadow registers contain changed values not yet in real
+	 * registers. Set when writing to shadow registers, cleared at
+	 * VSYNC/EVSYNC */
+	bool shadow_dirty;
+
+	bool enabled;
+
+	u32 paddr;
+	u32 puv_addr; /* relevant for NV12 format only */
+
+	u16 width;
+	u16 height;
+	u16 input_width;
+	u16 input_height;
+
+	enum omap_color_mode 				color_mode;
+	enum omap_color_mode 				input_color_mode;
+	enum omap_writeback_capturemode 	capturemode;
+	enum omap_writeback_source_type 	source_type;
+	enum omap_writeback_source			source;
+
+	enum omap_burst_size 				burst_size;
+	u32 								fifo_low;
+	u32 								fifo_high;
+
+};
+
 struct seq_file;
 struct platform_device;
 
@@ -211,11 +246,16 @@ void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 #endif
 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
+/* Write back */
+void dss_init_writeback(struct platform_device *pdev);
+bool omap_dss_check_wb(struct writeback_cache_data *wb, int overlayId, int managerId);
 
 /* DSS */
 int dss_init(bool skip_init);
 void dss_exit(void);
 
+void dss_switch_tv_hdmi(int hdmi);
+
 void dss_save_context(void);
 void dss_restore_context(void);
 
@@ -226,7 +266,8 @@ int dss_sdi_enable(void);
 void dss_sdi_disable(void);
 
 void dss_select_dispc_clk_source(enum dss_clk_source clk_src);
-void dss_select_dsi_clk_source(enum dss_clk_source clk_src);
+void dss_select_dsi_clk_source(enum omap_dsi_index ix,
+		enum dss_clk_source clk_src);
 enum dss_clk_source dss_get_dispc_clk_source(void);
 enum dss_clk_source dss_get_dsi_clk_source(void);
 
@@ -249,27 +290,32 @@ int sdi_init_display(struct omap_dss_device *display);
 /* DSI */
 int dsi_init(struct platform_device *pdev);
 void dsi_exit(void);
+int dsi2_init(struct platform_device *pdev);
+void dsi2_exit(void);
 
-void dsi_dump_clocks(struct seq_file *s);
-void dsi_dump_irqs(struct seq_file *s);
-void dsi_dump_regs(struct seq_file *s);
+void dsi_dump_clocks(enum omap_dsi_index ix, struct seq_file *s);
+void dsi_dump_irqs(enum omap_dsi_index ix, struct seq_file *s);
+void dsi_dump_regs(enum omap_dsi_index ix, struct seq_file *s);
 
 void dsi_save_context(void);
 void dsi_restore_context(void);
 
 int dsi_init_display(struct omap_dss_device *display);
-void dsi_irq_handler(void);
-unsigned long dsi_get_dsi1_pll_rate(void);
-int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo);
-int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
+irqreturn_t dsi_irq_handler(int irq, void *arg);
+unsigned long dsi_get_dsi1_pll_rate(enum omap_dsi_index ix);
+int dsi_pll_set_clock_div(enum omap_dsi_index ix,
+		struct dsi_clock_info *cinfo);
+int dsi_pll_calc_clock_div_pck(enum omap_dsi_index ix,
+		bool is_tft, unsigned long req_pck,
 		struct dsi_clock_info *cinfo,
 		struct dispc_clock_info *dispc_cinfo);
 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
 		bool enable_hsdiv);
-void dsi_pll_uninit(void);
+void dsi_pll_uninit(enum omap_dsi_index ix);
 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 		u32 fifo_size, enum omap_burst_size *burst_size,
 		u32 *fifo_low, u32 *fifo_high);
+int dsi_calc_clock_rates(struct dsi_clock_info *cinfo);
 
 /* DPI */
 int dpi_init(struct platform_device *pdev);
@@ -283,7 +329,7 @@ void dispc_dump_clocks(struct seq_file *s);
 void dispc_dump_irqs(struct seq_file *s);
 void dispc_dump_regs(struct seq_file *s);
 void dispc_irq_handler(void);
-void dispc_fake_vsync_irq(void);
+void dispc_fake_vsync_irq(enum omap_dsi_index ix);
 
 void dispc_save_context(void);
 void dispc_restore_context(void);
@@ -295,17 +341,24 @@ void dispc_lcd_enable_signal_polarity(bool act_high);
 void dispc_lcd_enable_signal(bool enable);
 void dispc_pck_free_enable(bool enable);
 void dispc_enable_fifohandcheck(bool enable);
+void dispc_enable_lcd_out(enum omap_channel channel, bool enable);
 
-void dispc_set_lcd_size(u16 width, u16 height);
+void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 void dispc_set_digit_size(u16 width, u16 height);
 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
 void dispc_enable_fifomerge(bool enable);
 void dispc_set_burst_size(enum omap_plane plane,
 		enum omap_burst_size burst_size);
+void dispc_set_zorder(enum omap_plane plane,
+			enum omap_overlay_zorder zorder);
+void dispc_enable_zorder(enum omap_plane plane, bool enable);
 
 void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
 void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
+void dispc_enable_gamma_table(bool enable);
+void dispc_set_idle_mode(void);
+
 void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
 void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
 void dispc_set_channel_out(enum omap_plane plane,
@@ -320,18 +373,23 @@ int dispc_setup_plane(enum omap_plane plane,
 		      bool ilace,
 		      enum omap_dss_rotation_type rotation_type,
 		      u8 rotation, bool mirror,
-		      u8 global_alpha);
+		      u8 global_alpha, enum omap_channel channel,
+		      u32 puv_addr);
 
 bool dispc_go_busy(enum omap_channel channel);
 void dispc_go(enum omap_channel channel);
+void dispc_enable_digit_out(bool enable);
 void dispc_enable_channel(enum omap_channel channel, bool enable);
 bool dispc_is_channel_enabled(enum omap_channel channel);
 int dispc_enable_plane(enum omap_plane plane, bool enable);
 void dispc_enable_replication(enum omap_plane plane, bool enable);
 
-void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
-void dispc_set_tft_data_lines(u8 data_lines);
-void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
+void dispc_set_parallel_interface_mode(enum omap_channel channel,
+				enum omap_parallel_interface_mode mode);
+void dispc_set_tft_data_lines(enum omap_channel channel,
+						u8 data_lines);
+void dispc_set_lcd_display_type(enum omap_channel channel,
+				enum omap_lcd_display_type type);
 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 
 void dispc_set_default_color(enum omap_channel channel, u32 color);
@@ -348,18 +406,23 @@ bool dispc_trans_key_enabled(enum omap_channel ch);
 bool dispc_alpha_blending_enabled(enum omap_channel ch);
 
 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
-void dispc_set_lcd_timings(struct omap_video_timings *timings);
+void dispc_set_lcd_timings(enum omap_channel channel,
+				struct omap_video_timings *timings);
 unsigned long dispc_fclk_rate(void);
-unsigned long dispc_lclk_rate(void);
-unsigned long dispc_pclk_rate(void);
-void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb);
+unsigned long dispc_lclk_rate(enum omap_channel channel);
+unsigned long dispc_pclk_rate(enum omap_channel channel);
+void dispc_set_pol_freq(enum omap_channel channel,
+			enum omap_panel_config config, u8 acbi, u8 acb);
 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 		struct dispc_clock_info *cinfo);
 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 		struct dispc_clock_info *cinfo);
-int dispc_set_clock_div(struct dispc_clock_info *cinfo);
-int dispc_get_clock_div(struct dispc_clock_info *cinfo);
-
+int dispc_set_clock_div(enum omap_channel channel,
+		struct dispc_clock_info *cinfo);
+int dispc_get_clock_div(enum omap_channel channel,
+		struct dispc_clock_info *cinfo);
+void dispc_go_wb(void);
+int dispc_setup_wb(struct writeback_cache_data *wb);
 
 /* VENC */
 int venc_init(struct platform_device *pdev);
@@ -380,6 +443,12 @@ void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
 unsigned long rfbi_get_max_tx_rate(void);
 int rfbi_init_display(struct omap_dss_device *display);
 
+#ifdef CONFIG_OMAP2_DSS_HDMI
+int hdmi_init(struct platform_device *pdev, int code, int mode);
+void hdmi_exit(void);
+void hdmi_dump_regs(struct seq_file *s);
+int hdmi_init_display(struct omap_dss_device *display);
+#endif
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
new file mode 100644
index 000000000000..6a248cce7ec8
--- /dev/null
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -0,0 +1,1373 @@
+/*
+ * linux/drivers/video/omap2/dss/hdmi.c
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Author: Yong Zhi
+ *
+ * HDMI settings from TI's DSS driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ * History:
+ * Mythripk <mythripk@ti.com>  Apr 2010 Modified for EDID reading and adding OMAP
+ *                                      related timing
+ *				May 2010 Added support of Hot Plug Detect
+ *
+ */
+
+#define DSS_SUBSYS_NAME "HDMI"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/mutex.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <plat/display.h>
+#include <plat/cpu.h>
+#include <plat/hdmi_lib.h>
+#include <plat/gpio.h>
+
+#include "dss.h"
+#include "hdmi.h"
+
+#define HDMI_PLLCTRL		0x58006200
+#define HDMI_PHY		0x58006300
+
+u16 current_descriptor_addrs;
+u8		edid[HDMI_EDID_MAX_LENGTH] = {0};
+u8		edid_set = 0;
+u8		header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
+u8 hpd_mode = 0;
+/* PLL */
+#define PLLCTRL_PLL_CONTROL				0x0ul
+#define PLLCTRL_PLL_STATUS				0x4ul
+#define PLLCTRL_PLL_GO					0x8ul
+#define PLLCTRL_CFG1					0xCul
+#define PLLCTRL_CFG2					0x10ul
+#define PLLCTRL_CFG3					0x14ul
+#define PLLCTRL_CFG4					0x20ul
+
+/* HDMI PHY */
+#define HDMI_TXPHY_TX_CTRL				0x0ul
+#define HDMI_TXPHY_DIGITAL_CTRL			0x4ul
+#define HDMI_TXPHY_POWER_CTRL			0x8ul
+#define HDMI_TXPHY_PAD_CFG_CTRL			0xCul
+
+/*This is the structure which has all supported timing values that OMAP4 supports*/
+struct omap_video_timings all_timings_direct[31] = { {640, 480, 25200, 96, 16, 48, 2, 10, 33},
+						{1280, 720, 74250, 40, 440, 220, 5, 5, 20},
+						{1280, 720, 74250, 40, 110, 220, 5, 5, 20},
+						{720, 480, 27000, 62, 16, 60, 6, 9, 30},
+						{2880, 576, 108000, 256, 48, 272, 5, 5, 39},
+						{1440, 480, 27000, 124, 38, 114, 3, 4, 15},
+						{1440, 576, 27000, 126, 24, 138, 3, 2, 19},
+						{1920, 1080, 74250, 44, 528, 148, 2, 5, 15},
+						{1920, 1080, 74250, 44, 88, 148, 2, 5, 15},
+						{1920, 1080, 148500, 44, 88, 148, 5, 4, 36},
+						{720, 576, 27000, 64, 12, 68, 5, 5, 39},
+						{1440, 576, 54000, 128, 24, 136, 5, 5, 39},
+						{1920, 1080, 148500, 44, 528, 148, 5, 4, 36},
+						{2880, 480, 108000, 248, 64, 240, 6, 9, 30},
+						/*Vesa frome here*/
+						{640, 480, 25175, 96, 16, 48, 2 , 11, 31},
+						{800, 600, 40000, 128, 40, 88, 4 , 1, 23},
+						{848, 480, 33750, 112, 16, 112, 8 , 6, 23},
+						{1280, 768, 71000, 128, 64, 192, 7 , 3, 20},
+						{1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 							{1360, 768, 85500, 112, 64, 256, 6 , 3, 18},
+						{1280, 960, 108000, 112, 96, 312, 3 , 1, 36},
+						{1280, 1024, 108000, 112, 48, 248, 3 , 1, 38},
+						{1024, 768, 65000, 136, 24, 160, 6, 3, 29},
+						{1400, 1050, 121750, 144, 88, 232, 4, 3, 32},
+						{1440, 900, 106500, 152, 80, 232, 6, 3, 25},
+						{1680, 1050, 146250, 176 , 104, 280, 6, 3, 30},
+						{1366, 768, 85500, 143, 70, 213, 3, 3, 24},
+						{1920, 1080, 148500, 44, 88, 80, 5, 4, 36},
+						{1280, 768, 68250, 32, 48, 80, 7, 3, 12},
+						{1400, 1050, 101000, 32, 48, 80, 4, 3, 23},    							{1680, 1050, 119000, 32, 48, 80, 6, 3, 21} } ;
+
+/*This is a static Mapping array which maps the timing values with corresponding CEA / VESA code*/
+int code_index[31] = {1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35,
+			/* <--14 CEA 17--> vesa*/
+			4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
+			0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39};
+
+/*This is revere static mapping which maps the CEA / VESA code to the corresponding timing values*/
+int code_cea[39] = {-1, 0, 3, 3, 2, 8, 5, 5, -1, -1, -1, -1, -1, -1, -1, -1, 9,
+			10, 10, 1, 7, 6, 6 , -1, -1, -1, -1, -1, -1, 11, 11,
+			12, -1, -1, -1, 13, 13, 4, 4};
+
+int code_vesa[83] = {-1, -1, -1, -1, 14, -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
+			-1, 22, -1, -1, -1, -1, -1, 28, 17, -1, -1, -1, -1, 18,
+			-1, -1, -1, 20, -1, -1, 21, -1, -1, -1, 19, -1, 29, 23,
+			-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+			30, 25, -1, -1, -1, -1, -1, -1, -1 , -1, -1, -1, -1, -1,
+			-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 26, 27};
+
+
+
+static struct {
+	void __iomem *base_phy;
+	void __iomem *base_pll;
+	struct mutex lock;
+	int code;
+	int mode;
+	HDMI_Timing_t ti;
+} hdmi;
+
+static struct hdmi_cm {
+	int code;
+	int mode;
+};
+struct omap_video_timings edid_timings;
+
+static inline void hdmi_write_reg(u32 base, u16 idx, u32 val)
+{
+	void __iomem *b;
+
+	switch (base) {
+	case HDMI_PHY:
+	  b = hdmi.base_phy;
+	  break;
+	case HDMI_PLLCTRL:
+	  b = hdmi.base_pll;
+	  break;
+	default:
+	  BUG();
+	}
+	__raw_writel(val, b + idx);
+	/* DBG("write = 0x%x idx =0x%x\r\n", val, idx); */
+}
+
+static inline u32 hdmi_read_reg(u32 base, u16 idx)
+{
+	void __iomem *b;
+	u32 l;
+
+	switch (base) {
+	case HDMI_PHY:
+	 b = hdmi.base_phy;
+	 break;
+	case HDMI_PLLCTRL:
+	 b = hdmi.base_pll;
+	 break;
+	default:
+	 BUG();
+	}
+	l = __raw_readl(b + idx);
+
+	/* DBG("addr = 0x%p rd = 0x%x idx = 0x%x\r\n", (b+idx), l, idx); */
+	return l;
+}
+
+#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
+#define FLD_MOD(orig, val, start, end) \
+	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
+
+#define REG_FLD_MOD(b, i, v, s, e) \
+	hdmi_write_reg(b, i, FLD_MOD(hdmi_read_reg(b, i), v, s, e))
+
+/*
+ * refclk = (sys_clk/(highfreq+1))/(n+1)
+ * so refclk = 38.4/2/(n+1) = 19.2/(n+1)
+ * choose n = 15, makes refclk = 1.2
+ *
+ * m = tclk/cpf*refclk = tclk/2*1.2
+ *
+ *	for clkin = 38.2/2 = 192
+ *	    phy = 2520
+ *
+ *	m = 2520*16/2* 192 = 105;
+ *
+ *	for clkin = 38.4
+ *	    phy = 2520
+ *
+ */
+
+#define CPF			2
+
+struct hdmi_pll_info {
+	u16 regn;
+	u16 regm;
+	u32 regmf;
+	u16 regm4; /* M4_CLOCK_DIV */
+	u16 regm2;
+	u16 regsd;
+	u16 dcofreq;
+};
+
+static void compute_pll(int clkin, int phy,
+	int n, struct hdmi_pll_info *pi)
+{
+	int refclk;
+	u32 temp, mf;
+
+	if (clkin > 3200) /* 32 mHz */
+		refclk = clkin / (2 * (n + 1));
+	else
+		refclk = clkin / (n + 1);
+
+	temp = phy * 100/(CPF * refclk);
+
+	pi->regn = n;
+	pi->regm = temp/100;
+	pi->regm2 = 1;
+
+	mf = (phy - pi->regm * CPF * refclk) * 262144;
+	pi->regmf = mf/(CPF * refclk);
+
+	if (phy > 1000 * 100) {
+		pi->regm4 = phy / 10000;
+		pi->dcofreq = 1;
+		pi->regsd = ((pi->regm * 384)/((n + 1) * 250) + 5)/10;
+	} else {
+		pi->regm4 = 1;
+		pi->dcofreq = 0;
+		pi->regsd = 0;
+	}
+
+	DSSDBG("M = %d Mf = %d, m4= %d\n", pi->regm, pi->regmf, pi->regm4);
+	DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
+}
+
+static int hdmi_pll_init(int refsel, int dcofreq, struct hdmi_pll_info *fmt, u16 sd)
+{
+	u32 r;
+	unsigned t = 500000;
+	u32 pll = HDMI_PLLCTRL;
+
+	/* PLL start always use manual mode */
+	REG_FLD_MOD(pll, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
+
+	r = hdmi_read_reg(pll, PLLCTRL_CFG1);
+	r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1__PLL_REGM */
+	r = FLD_MOD(r, fmt->regn, 8, 1);  /* CFG1__PLL_REGN */
+	r = FLD_MOD(r, fmt->regm4, 25, 21); /* M4_CLOCK_DIV */
+
+	hdmi_write_reg(pll, PLLCTRL_CFG1, r);
+
+	r = hdmi_read_reg(pll, PLLCTRL_CFG2);
+
+	/* SYS w/o divide by 2 [22:21] = donot care  [11:11] = 0x0 */
+	/* SYS divide by 2     [22:21] = 0x3 [11:11] = 0x1 */
+	/* PCLK, REF1 or REF2  [22:21] = 0x0, 0x 1 or 0x2 [11:11] = 0x1 */
+	r = FLD_MOD(r, 0x0, 11, 11); /* PLL_CLKSEL 1: PLL 0: SYS*/
+	r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
+	r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
+	r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
+	r = FLD_MOD(r, 0x1, 20, 20); /* HSDIVBYPASS assert during locking */
+	r = FLD_MOD(r, refsel, 22, 21); /* REFSEL */
+	/* DPLL3  used by DISPC or HDMI itself*/
+	r = FLD_MOD(r, 0x0, 17, 17); /* M4_CLOCK_PWDN */
+	r = FLD_MOD(r, 0x1, 16, 16); /* M4_CLOCK_EN */
+
+	if (dcofreq) {
+		/* divider programming for 1080p */
+		REG_FLD_MOD(pll, PLLCTRL_CFG3, sd, 17, 10);
+		r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
+	} else
+		r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
+
+	hdmi_write_reg(pll, PLLCTRL_CFG2, r);
+
+	r = hdmi_read_reg(pll, PLLCTRL_CFG4);
+	r = FLD_MOD(r, 0, 24, 18); /* todo: M2 */
+	r = FLD_MOD(r, fmt->regmf, 17, 0);
+
+	/* go now */
+	REG_FLD_MOD(pll, PLLCTRL_PLL_GO, 0x1ul, 0, 0);
+
+	/* wait for bit change */
+	while (FLD_GET(hdmi_read_reg(pll, PLLCTRL_PLL_GO), 0, 0))
+
+	/* Wait till the lock bit is set */
+	/* read PLL status */
+	while (0 == FLD_GET(hdmi_read_reg(pll, PLLCTRL_PLL_STATUS), 1, 1)) {
+		udelay(1);
+		if (!--t) {
+			printk(KERN_WARNING "HDMI: cannot lock PLL\n");
+			DSSDBG("CFG1 0x%x\n", hdmi_read_reg(pll, PLLCTRL_CFG1));
+			DSSDBG("CFG2 0x%x\n", hdmi_read_reg(pll, PLLCTRL_CFG2));
+			DSSDBG("CFG4 0x%x\n", hdmi_read_reg(pll, PLLCTRL_CFG4));
+			return -EIO;
+		}
+	}
+
+	DSSDBG("PLL locked!\n");
+
+	r = hdmi_read_reg(pll, PLLCTRL_CFG2);
+	r = FLD_MOD(r, 0, 0, 0);	/* PLL_IDLE */
+	r = FLD_MOD(r, 0, 5, 5);	/* PLL_PLLLPMODE */
+	r = FLD_MOD(r, 0, 6, 6);	/* PLL_LOWCURRSTBY */
+	r = FLD_MOD(r, 0, 8, 8);	/* PLL_DRIFTGUARDEN */
+	r = FLD_MOD(r, 0, 10, 9);	/* PLL_LOCKSEL */
+	r = FLD_MOD(r, 1, 13, 13);	/* PLL_REFEN */
+	r = FLD_MOD(r, 1, 14, 14);	/* PHY_CLKINEN */
+	r = FLD_MOD(r, 0, 15, 15);	/* BYPASSEN */
+	r = FLD_MOD(r, 0, 20, 20);	/* HSDIVBYPASS */
+	hdmi_write_reg(pll, PLLCTRL_CFG2, r);
+
+	return 0;
+}
+
+static int hdmi_pll_reset(void)
+{
+	int t = 0;
+
+	/* SYSREEST  controled by power FSM*/
+	REG_FLD_MOD(HDMI_PLLCTRL, PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
+
+	/* READ 0x0 reset is in progress */
+	while (!FLD_GET(hdmi_read_reg(HDMI_PLLCTRL,
+			PLLCTRL_PLL_STATUS), 0, 0)) {
+		udelay(1);
+		if (t++ > 1000) {
+			ERR("Failed to sysrest PLL\n");
+			return -ENODEV;
+		}
+	}
+	return 0;
+}
+
+int hdmi_pll_program(struct hdmi_pll_info *fmt)
+{
+	u32 r;
+	int refsel;
+
+	HDMI_PllPwr_t PllPwrWaitParam;
+
+	/* wait for wrapper rest */
+	HDMI_W1_SetWaitSoftReset();
+
+	/* power off PLL */
+	PllPwrWaitParam = HDMI_PLLPWRCMD_ALLOFF;
+	r = HDMI_W1_SetWaitPllPwrState(HDMI_WP,
+				PllPwrWaitParam);
+	if (r)
+		return r;
+
+	/* power on PLL */
+	PllPwrWaitParam = HDMI_PLLPWRCMD_BOTHON_ALLCLKS;
+	r = HDMI_W1_SetWaitPllPwrState(HDMI_WP,
+				PllPwrWaitParam);
+	if (r)
+		return r;
+
+	hdmi_pll_reset();
+
+	refsel = 0x3; /* select SYSCLK reference */
+
+	r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd);
+
+	return r;
+}
+
+/* double check the order */
+static int hdmi_phy_init(u32 w1,
+		u32 phy)
+{
+	u32 count;
+	int r;
+
+	/* wait till PHY_PWR_STATUS=LDOON */
+	/* HDMI_PHYPWRCMD_LDOON = 1 */
+	r = HDMI_W1_SetWaitPhyPwrState(w1, 1);
+	if (r)
+		return r;
+
+	/* wait till PHY_PWR_STATUS=TXON */
+	r = HDMI_W1_SetWaitPhyPwrState(w1, 2);
+	if (r)
+		return r;
+
+	/* read address 0 in order to get the SCPreset done completed */
+	/* Dummy access performed to solve resetdone issue */
+	hdmi_read_reg(phy, HDMI_TXPHY_TX_CTRL);
+
+	/* write to phy address 0 to configure the clock */
+	/* use HFBITCLK write HDMI_TXPHY_TX_CONTROL__FREQOUT field */
+	REG_FLD_MOD(phy, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
+
+	/* write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
+	hdmi_write_reg(phy, HDMI_TXPHY_DIGITAL_CTRL,
+				0xF0000000);
+
+	/* setup max LDO voltage */
+	REG_FLD_MOD(phy, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
+	/*  write to phy address 3 to change the polarity control  */
+	REG_FLD_MOD(phy, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
+
+	count = 0;
+	while (count++ < 1000)
+		;
+
+	return 0;
+}
+
+static int hdmi_phy_off(u32 name)
+{
+	int r = 0;
+	u32 count;
+
+	/* wait till PHY_PWR_STATUS=OFF */
+	/* HDMI_PHYPWRCMD_OFF = 0 */
+	r = HDMI_W1_SetWaitPhyPwrState(name, 0);
+	if (r)
+		return r;
+
+	count = 0;
+	while (count++ < 200)
+		;
+
+	return 0;
+}
+
+/* driver */
+static int hdmi_panel_probe(struct omap_dss_device *dssdev)
+{
+	int code;
+	DSSDBG("ENTER hdmi_panel_probe()\n");
+
+	dssdev->panel.config = OMAP_DSS_LCD_TFT |
+			OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS;
+
+	if	(hdmi.mode == 0)
+		code = code_vesa[hdmi.code];
+	else
+		code = code_cea[hdmi.code];
+	if (code == -1)	{
+		code = 9;
+		hdmi.code = 16;
+		hdmi.mode = 1;
+	}
+
+	dssdev->panel.timings = all_timings_direct[code];
+	DSSDBG("hdmi_panel_probe x_res= %d y_res = %d", dssdev->panel.timings.x_res,
+		 dssdev->panel.timings.y_res);
+
+	return 0;
+}
+
+static void hdmi_panel_remove(struct omap_dss_device *dssdev)
+{
+
+}
+
+static int hdmi_panel_enable(struct omap_dss_device *dssdev)
+{
+	hdmi_enable_display(dssdev);
+	return 0;
+}
+
+static void hdmi_panel_disable(struct omap_dss_device *dssdev)
+{
+	hdmi_disable_display(dssdev);
+}
+
+static int hdmi_panel_suspend(struct omap_dss_device *dssdev)
+{
+	hdmi_display_suspend(dssdev);
+	return 0;
+}
+
+static int hdmi_panel_resume(struct omap_dss_device *dssdev)
+{
+	hdmi_display_resume(dssdev);
+	return 0;
+}
+
+static void hdmi_enable_clocks(int enable)
+{
+	if (enable)
+		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
+				DSS_CLK_96M);
+	else
+		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
+				DSS_CLK_96M);
+}
+
+static struct omap_dss_driver hdmi_driver = {
+	.probe		= hdmi_panel_probe,
+	.remove		= hdmi_panel_remove,
+
+	.enable		= hdmi_panel_enable,
+	.disable	= hdmi_panel_disable,
+	.suspend	= hdmi_panel_suspend,
+	.resume		= hdmi_panel_resume,
+	.get_timings	= hdmi_get_timings,
+	.set_timings	= hdmi_set_timings,
+	.check_timings	= hdmi_check_timings,
+	.get_edid	= hdmi_get_edid,
+	.set_custom_edid_timing_code	= hdmi_set_custom_edid_timing_code,
+	.hpd_enable	=	hdmi_enable_hpd,
+	.driver			= {
+		.name   = "hdmi_panel",
+		.owner  = THIS_MODULE,
+	},
+};
+/* driver end */
+
+int hdmi_init(struct platform_device *pdev, int code, int mode)
+{
+	int r = 0;
+	DSSDBG("Enter hdmi_init()\n");
+
+	mutex_init(&hdmi.lock);
+
+	hdmi.base_pll = ioremap(HDMI_PLLCTRL, 64);
+	if (!hdmi.base_pll) {
+		ERR("can't ioremap pll\n");
+		return -ENOMEM;
+	}
+	hdmi.base_phy = ioremap(HDMI_PHY, 64);
+
+	if (!hdmi.base_phy) {
+		ERR("can't ioremap phy\n");
+		return -ENOMEM;
+	}
+	hdmi.code = code;
+	hdmi.mode = mode;
+	DSSDBG("%d code %d mode", hdmi.code, hdmi.mode);
+	hdmi_enable_clocks(1);
+
+	hdmi_lib_init();
+
+	hdmi_enable_clocks(0);
+	r = request_irq(OMAP44XX_IRQ_DSS_HDMI, hdmi_irq_handler,
+			0, "OMAP HDMI", (void *)0);
+
+
+	return omap_dss_register_driver(&hdmi_driver);
+
+}
+
+void hdmi_exit(void)
+{
+	hdmi_lib_exit();
+	free_irq(OMAP44XX_IRQ_DSS_HDMI, NULL);
+	iounmap(hdmi.base_pll);
+	iounmap(hdmi.base_phy);
+}
+
+static int hdmi_power_on(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+	int code = 0;
+	struct omap_video_timings *p;
+	struct hdmi_pll_info pll_data;
+
+	int clkin, n, phy;
+
+	if (hdmi.mode == 0)
+		code = code_vesa[hdmi.code];
+	else
+		code = code_cea[hdmi.code];
+	if (code == -1)	{
+		code = 9;
+		hdmi.code = 16;
+		hdmi.mode = 1;
+	}
+
+	dssdev->panel.timings = all_timings_direct[code];
+	DSSDBG("hdmi_panel_probe x_res= %d y_res = %d", dssdev->panel.timings.x_res,
+		 dssdev->panel.timings.y_res);
+
+	hdmi_enable_clocks(1);
+
+	p = &dssdev->panel.timings;
+
+	r = hdmi_read_edid(p);
+	if (r) {
+		r = -EIO;
+		goto err;
+	}
+
+	clkin = 3840; /* 38.4 mHz */
+	n = 15; /* this is a constant for our math */
+	phy = p->pixel_clock;
+	compute_pll(clkin, phy, n, &pll_data);
+
+	HDMI_W1_StopVideoFrame(HDMI_WP);
+
+	dispc_enable_digit_out(0);
+
+	/* config the PLL and PHY first */
+	r = hdmi_pll_program(&pll_data);
+	if (r) {
+		DSSERR("Failed to lock PLL\n");
+		r = -EIO;
+		goto err;
+	}
+
+	r = hdmi_phy_init(HDMI_WP, HDMI_PHY);
+	if (r) {
+		DSSERR("Failed to start PHY\n");
+		r = -EIO;
+		goto err;
+	}
+
+	DSS_HDMI_CONFIG(hdmi.ti, hdmi.code, hdmi.mode);
+
+	/* these settings are independent of overlays */
+	dss_switch_tv_hdmi(1);
+
+	/* bypass TV gamma table*/
+	dispc_enable_gamma_table(0);
+
+	/* do not fall into any sort of idle */
+	dispc_set_idle_mode();
+
+	/* tv size */
+	dispc_set_digit_size(dssdev->panel.timings.x_res,
+			dssdev->panel.timings.y_res);
+
+	HDMI_W1_StartVideoFrame(HDMI_WP);
+
+	dispc_enable_digit_out(1);
+
+	return 0;
+err:
+	return r;
+}
+
+int hdmi_min_enable(void)
+{
+	int r;
+	DSSDBG("hdmi_min_enable");
+	r = hdmi_phy_init(HDMI_WP, HDMI_PHY);
+	if (r) {
+		DSSERR("Failed to start PHY\n");
+	}
+	DSS_HDMI_CONFIG(hdmi.ti, hdmi.code, hdmi.mode);
+	return 0;
+}
+
+static irqreturn_t hdmi_irq_handler(int irq, void *arg)
+{
+	int r = 0;
+	struct omap_dss_device *dssdev = NULL;
+	const char *buf = "hdmi";
+	int match(struct omap_dss_device *dssdev2 , void *data)
+	 {
+		const char *str = data;
+		return sysfs_streq(dssdev2->name , str);
+	 }
+	dssdev = omap_dss_find_device((void *)buf , match);
+	DSSDBG("found hdmi handle %s" , dssdev->name);
+	HDMI_W1_HPD_handler(&r);
+	DSSDBG("r = %d", r);
+
+	if ((r == 4 || r == 2) && (hpd_mode == 1)) {
+		hdmi_phy_off(HDMI_WP);
+		hdmi_enable_clocks(1);
+		hdmi_power_on(dssdev);
+		mdelay(1000);
+		printk(KERN_INFO "Display enabled");
+	}
+	if (r == 1 || r == 4) {
+		hpd_mode = 0;
+	}
+	if ((r == 3) && (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)) {
+		printk(KERN_INFO "Display disabled");
+		hdmi_power_off(dssdev);
+		hpd_mode = 1;
+
+		if (dssdev->platform_disable)
+			dssdev->platform_disable(dssdev);
+
+		hdmi_min_enable();
+	}
+
+	return IRQ_HANDLED;
+
+}
+
+static void hdmi_power_off(struct omap_dss_device *dssdev)
+{
+	HDMI_W1_StopVideoFrame(HDMI_WP);
+
+	dispc_enable_digit_out(0);
+
+	hdmi_phy_off(HDMI_WP);
+
+	HDMI_W1_SetWaitPllPwrState(HDMI_WP, HDMI_PLLPWRCMD_ALLOFF);
+
+	if (dssdev->platform_disable)
+		dssdev->platform_disable(dssdev);
+
+	edid_set = 0;
+	hdmi_enable_clocks(0);
+
+	/* reset to default */
+
+}
+
+static int hdmi_enable_display(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+	DSSDBG("ENTER hdmi_enable_display()\n");
+
+	mutex_lock(&hdmi.lock);
+
+	/* the tv overlay manager is shared*/
+	r = omap_dss_start_device(dssdev);
+	if (r) {
+		DSSERR("failed to start device\n");
+		goto err;
+	}
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
+		r = -EINVAL;
+		goto err;
+	}
+
+	free_irq(OMAP44XX_IRQ_DSS_HDMI, NULL);
+
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+	/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+	omap_writel(0x01180118, 0x4A100098);
+	/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
+	omap_writel(0x01180118 , 0x4A10009C);
+	/* CONTROL_HDMI_TX_PHY */
+	omap_writel(0x10000000, 0x4A100610);
+
+	if (dssdev->platform_enable)
+		dssdev->platform_enable(dssdev);
+
+	r = hdmi_power_on(dssdev);
+	if (r) {
+		DSSERR("failed to power on device\n");
+		goto err;
+	}
+	r = request_irq(OMAP44XX_IRQ_DSS_HDMI, hdmi_irq_handler,
+			0, "OMAP HDMI", (void *)0);
+
+err:
+	mutex_unlock(&hdmi.lock);
+	return r;
+
+}
+
+static int hdmi_enable_hpd(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+	DSSDBG("ENTER hdmi_enable_hpd()\n");
+
+	mutex_lock(&hdmi.lock);
+
+	/* the tv overlay manager is shared*/
+	r = omap_dss_start_device(dssdev);
+	if (r) {
+		DSSERR("failed to start device\n");
+		goto err;
+	}
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
+		r = -EINVAL;
+		goto err;
+	}
+
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+	/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+	omap_writel(0x01180118, 0x4A100098);
+	/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
+	omap_writel(0x01180118 , 0x4A10009C);
+	/* CONTROL_HDMI_TX_PHY */
+	omap_writel(0x10000000, 0x4A100610);
+
+	if (dssdev->platform_enable)
+		dssdev->platform_enable(dssdev);
+
+	hpd_mode = 1;
+	r = hdmi_min_enable();
+	if (r) {
+		DSSERR("failed to power on device\n");
+		goto err;
+	}
+
+err:
+	mutex_unlock(&hdmi.lock);
+	return r;
+
+}
+
+static void hdmi_disable_display(struct omap_dss_device *dssdev)
+{
+	DSSDBG("Enter hdmi_disable_display()\n");
+
+	mutex_lock(&hdmi.lock);
+	if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
+		goto end;
+
+	if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
+		/* suspended is the same as disabled with venc */
+		dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+		goto end;
+	}
+
+	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+	omap_dss_stop_device(dssdev);
+
+	hdmi_power_off(dssdev);
+
+	hdmi.code = 16;
+	hdmi.mode = 1 ; /*setting to default only in case of disable and not suspend*/
+end:
+	mutex_unlock(&hdmi.lock);
+}
+
+static int hdmi_display_suspend(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+
+	DSSDBG("hdmi_display_suspend\n");
+		mutex_lock(&hdmi.lock);
+	if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
+		goto end;
+
+	if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
+		goto end;
+
+	dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
+
+	omap_dss_stop_device(dssdev);
+
+	hdmi_power_off(dssdev);
+end:
+	mutex_unlock(&hdmi.lock);
+	return r;
+}
+
+static int hdmi_display_resume(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+
+	DSSDBG("hdmi_display_resume\n");
+	mutex_lock(&hdmi.lock);
+
+	/* the tv overlay manager is shared*/
+	r = omap_dss_start_device(dssdev);
+	if (r) {
+		DSSERR("failed to start device\n");
+		goto err;
+	}
+
+	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
+		r = -EINVAL;
+		goto err;
+	}
+
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+	/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+	omap_writel(0x01180118, 0x4A100098);
+	/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
+	omap_writel(0x01180118 , 0x4A10009C);
+	/* CONTROL_HDMI_TX_PHY */
+	omap_writel(0x10000000, 0x4A100610);
+
+	if (dssdev->platform_enable)
+		dssdev->platform_enable(dssdev);
+
+	r = hdmi_power_on(dssdev);
+	if (r) {
+		DSSERR("failed to power on device\n");
+		goto err;
+	}
+
+err:
+	mutex_unlock(&hdmi.lock);
+
+	return r;
+}
+
+static void hdmi_get_timings(struct omap_dss_device *dssdev,
+			struct omap_video_timings *timings)
+{
+	*timings = dssdev->panel.timings;
+}
+
+static void hdmi_set_timings(struct omap_dss_device *dssdev,
+			struct omap_video_timings *timings)
+{
+	DSSDBG("hdmi_set_timings\n");
+
+	dssdev->panel.timings = *timings;
+
+	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
+		/* turn the hdmi off and on to get new timings to use */
+		hdmi_disable_display(dssdev);
+		hdmi_enable_display(dssdev);
+	}
+}
+
+static void hdmi_set_custom_edid_timing_code(struct omap_dss_device *dssdev, int code , int mode)
+{
+		if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
+		/* turn the hdmi off and on to get new timings to use */
+		hdmi_disable_display(dssdev);
+		hdmi.code = code;
+		hdmi.mode = mode;
+		hdmi_enable_display(dssdev);
+	}
+}
+
+static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
+{
+	int i = 0, code = -1;
+	struct omap_video_timings temp;
+	struct hdmi_cm cm = {-1};
+	DSSDBG("hdmi_get_code");
+
+	for (i = 0; i < 31; i++) {
+		temp = all_timings_direct[i];
+
+		if (!memcmp(&temp, timing, sizeof(struct omap_video_timings))) {
+
+			code = i;
+			cm.code = code_index[i];
+			if (code < 14)
+				cm.mode = 1;
+			else
+				cm.mode = 0;
+			printk(KERN_INFO "Hdmi_code = %d mode = %d ", cm.code, cm.mode);
+			printk(KERN_INFO "Timing Info "
+			"pixel_clk 			= %d\n"
+			"Xresolution		=%d\n"
+			"yresolution		=%d\n"
+			"hfp			= %d\n"
+			"hsw			= %d\n"
+			"hbp			= %d\n"
+			"vfp			= %d\n"
+			"vsw			= %d\n"
+			"vbp			= %d\n",
+			temp.pixel_clock,
+			temp.x_res,
+			temp.y_res,
+			temp.hfp,
+			temp.hsw,
+			temp.hbp,
+			temp.vfp,
+			temp.vsw,
+			temp.vbp);
+			break;
+		 }
+
+	}
+	return cm;
+}
+
+static void hdmi_get_edid(struct omap_dss_device *dssdev)
+{
+	u8 i = 0, flag = 0;
+	int count, offset, effective_addrs;
+	if (edid_set != 1) {
+		printk(KERN_WARNING "Display doesnt seem to be enabled invalid read\n");
+	if (HDMI_CORE_DDC_READEDID(HDMI_CORE_SYS, edid) != 0) {
+		printk(KERN_WARNING "HDMI failed to read E-EDID\n");
+	}
+			for (i = 0x00; i < 0x08; i++) {
+				if (edid[i] == header[i])
+					continue;
+				else {
+					flag = 1;
+					break;
+				}
+			}
+		if (flag == 0)
+			edid_set = 1;
+	}
+
+	mdelay(1000);
+
+	printk("\nHeader:\n");
+	for (i = 0x00; i < 0x08; i++)
+		printk("%02x	", edid[i]);
+	printk("\nVendor & Product:\n");
+	for (i = 0x08; i < 0x12; i++)
+		printk("%02x	", edid[i]);
+	printk("\nEDID Structure:\n");
+	for (i = 0x12; i < 0x14; i++)
+		printk("%02x	", edid[i]);
+	printk("\nBasic Display Parameter:\n");
+	for (i = 0x14; i < 0x19; i++)
+		printk("%02x	", edid[i]);
+	printk("\nColor Characteristics:\n");
+	for (i = 0x19; i < 0x23; i++)
+		printk("%02x	", edid[i]);
+	printk("\nEstablished timings:\n");
+	for (i = 0x23; i < 0x26; i++)
+		printk("%02x	", edid[i]);
+	printk("\nStandard timings:\n");
+	for (i = 0x26; i < 0x36; i++)
+		printk("%02x	", edid[i]);
+
+	for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) {
+		current_descriptor_addrs =
+			EDID_DESCRIPTOR_BLOCK0_ADDRESS +
+			count * EDID_TIMING_DESCRIPTOR_SIZE;
+		show_horz_vert_timing_info(edid);
+		}
+	if (edid[0x7e] != 0x00) {
+		offset = edid[EDID_DESCRIPTOR_BLOCK1_ADDRESS + 2];
+		printk("\n offset %x\n", offset);
+		if (offset != 0) {
+			effective_addrs = EDID_DESCRIPTOR_BLOCK1_ADDRESS
+				+ offset;
+			/*to determine the number of descriptor blocks */
+			for (count = 0;
+			      count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR;
+			      count++) {
+			current_descriptor_addrs = effective_addrs +
+			count * EDID_TIMING_DESCRIPTOR_SIZE;
+		show_horz_vert_timing_info(edid);
+			}
+		}
+
+
+	}
+	hdmi_get_image_format();
+	hdmi_get_audio_format();
+
+}
+void show_horz_vert_timing_info(u8 *edid)
+{
+	struct omap_video_timings timings_value;
+
+	printk(KERN_INFO
+			 "EDID DTD block address	= 0x%x\n",
+			 current_descriptor_addrs
+			 );
+	/*X and Y resolution */
+	timings_value.x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) |
+			 edid[current_descriptor_addrs + 2]);
+	timings_value.y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) |
+			 edid[current_descriptor_addrs + 5]);
+	timings_value.pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) |
+					edid[current_descriptor_addrs]);
+
+	timings_value.pixel_clock = 10 * timings_value.pixel_clock;
+
+	/*HORIZONTAL FRONT PORCH */
+	timings_value.hfp = edid[current_descriptor_addrs + 8];
+	/*HORIZONTAL SYNC WIDTH */
+	timings_value.hsw = edid[current_descriptor_addrs + 9];
+	/*HORIZONTAL BACK PORCH */
+	timings_value.hbp = (((edid[current_descriptor_addrs + 4]
+					  & 0x0F) << 8) |
+					edid[current_descriptor_addrs + 3]) -
+		(timings_value.hfp + timings_value.hsw);
+	/*VERTICAL FRONT PORCH */
+	timings_value.vfp = ((edid[current_descriptor_addrs + 10] &
+				       0xF0) >> 4);
+	/*VERTICAL SYNC WIDTH */
+	timings_value.vsw = (edid[current_descriptor_addrs + 10] &
+				      0x0F);
+	/*VERTICAL BACK PORCH */
+	timings_value.vbp = (((edid[current_descriptor_addrs + 7] &
+					0x0F) << 8) |
+				      edid[current_descriptor_addrs + 6]) -
+		(timings_value.vfp + timings_value.vsw);
+
+	hdmi_get_code(&timings_value);
+
+}
+
+static int hdmi_check_timings(struct omap_dss_device *dssdev,
+			struct omap_video_timings *timings)
+{
+	DSSDBG("hdmi_check_timings\n");
+
+	if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)) == 0)
+		return 0;
+
+	return -EINVAL;
+}
+
+int hdmi_init_display(struct omap_dss_device *dssdev)
+{
+	DSSDBG("init_display\n");
+
+	return 0;
+}
+
+static int hdmi_read_edid(struct omap_video_timings *dp)
+{
+	int r = 0, i = 0 , flag = 0 , ret;
+
+	u16		horizontal_res;
+	u16		vertical_res;
+	u16		pixel_clk;
+	struct hdmi_cm cm;
+	struct omap_video_timings *tp;
+
+	memset(edid, 0, HDMI_EDID_MAX_LENGTH);
+	tp = dp;
+
+	if (edid_set != 1) {
+		ret = HDMI_CORE_DDC_READEDID(HDMI_CORE_SYS, edid);
+	}
+	if (ret != 0) {
+		printk(KERN_WARNING "HDMI failed to read E-EDID\n");
+
+	} else {
+		for (i = 0x00; i < 0x08; i++) {
+			if (edid[i] == header[i])
+				continue;
+			else {
+			flag = 1;
+			break;
+			}
+		}
+		if (flag == 0)
+			edid_set = 1;
+		edid_timings.pixel_clock = dp->pixel_clock;
+		edid_timings.x_res = dp->x_res;
+		edid_timings.y_res = dp->y_res;
+		/* search for timings of default resolution */
+		if (get_edid_timing_data(edid, &pixel_clk,
+				&horizontal_res, &vertical_res)) {
+			dp->pixel_clock = pixel_clk * 10; /* be careful */
+			tp = &edid_timings;
+		} else {
+				edid_timings.pixel_clock =
+							all_timings_direct[2].pixel_clock;
+				edid_timings.x_res = all_timings_direct[2].x_res;
+				edid_timings.y_res = all_timings_direct[2].y_res;
+				if (get_edid_timing_data(edid,
+					&pixel_clk, &horizontal_res,
+							&vertical_res)) {
+					dp->pixel_clock = pixel_clk * 10;
+					dp->x_res = horizontal_res;
+					dp->y_res = vertical_res;
+					tp = &edid_timings;
+
+		}
+	}
+
+	}
+	cm = hdmi_get_code(tp);
+	hdmi.code = cm.code;
+	hdmi.mode = cm.mode;
+	hdmi.ti.pixelPerLine = tp->x_res;
+	hdmi.ti.linePerPanel = tp->y_res;
+	hdmi.ti.horizontalBackPorch = tp->hbp;
+	hdmi.ti.horizontalFrontPorch = tp->hfp;
+	hdmi.ti.horizontalSyncPulse = tp->hsw;
+	hdmi.ti.verticalBackPorch = tp->vbp;
+	hdmi.ti.verticalFrontPorch = tp->vfp;
+	hdmi.ti.verticalSyncPulse = tp->vsw;
+
+	return r;
+}
+
+u16 current_descriptor_addrs;
+
+void get_horz_vert_timing_info(u8 *edid)
+{
+	/*HORIZONTAL FRONT PORCH */
+	edid_timings.hfp = edid[current_descriptor_addrs + 8];
+	/*HORIZONTAL SYNC WIDTH */
+	edid_timings.hsw = edid[current_descriptor_addrs + 9];
+	/*HORIZONTAL BACK PORCH */
+	edid_timings.hbp = (((edid[current_descriptor_addrs + 4]
+					  & 0x0F) << 8) |
+					edid[current_descriptor_addrs + 3]) -
+		(edid_timings.hfp + edid_timings.hsw);
+	/*VERTICAL FRONT PORCH */
+	edid_timings.vfp = ((edid[current_descriptor_addrs + 10] &
+				       0xF0) >> 4);
+	/*VERTICAL SYNC WIDTH */
+	edid_timings.vsw = (edid[current_descriptor_addrs + 10] &
+				      0x0F);
+	/*VERTICAL BACK PORCH */
+	edid_timings.vbp = (((edid[current_descriptor_addrs + 7] &
+					0x0F) << 8) |
+				      edid[current_descriptor_addrs + 6]) -
+		(edid_timings.vfp + edid_timings.vsw);
+
+	DSSDBG(KERN_INFO "hfp			= %d\n"
+			"hsw			= %d\n"
+			"hbp			= %d\n"
+			"vfp			= %d\n"
+			"vsw			= %d\n"
+			"vbp			= %d\n",
+		 edid_timings.hfp,
+		 edid_timings.hsw,
+		 edid_timings.hbp,
+		 edid_timings.vfp,
+		 edid_timings.vsw,
+		 edid_timings.vbp);
+
+}
+
+/*------------------------------------------------------------------------------
+ | Function    : get_edid_timing_data
+ +------------------------------------------------------------------------------
+ | Description : This function gets the resolution information from EDID
+ |
+ | Parameters  : void
+ |
+ | Returns     : void
+ +----------------------------------------------------------------------------*/
+static int get_edid_timing_data(u8 *edid, u16 *pixel_clk, u16 *horizontal_res,
+			  u16 *vertical_res)
+{
+	u8 offset, effective_addrs;
+	u8 count;
+	u8 flag = false;
+	/* Seach block 0, there are 4 DTDs arranged in priority order */
+	for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) {
+		current_descriptor_addrs =
+			EDID_DESCRIPTOR_BLOCK0_ADDRESS +
+			count * EDID_TIMING_DESCRIPTOR_SIZE;
+		*horizontal_res =
+			(((edid[EDID_DESCRIPTOR_BLOCK0_ADDRESS + 4 +
+			   count * EDID_TIMING_DESCRIPTOR_SIZE] & 0xF0) << 4) |
+			 edid[EDID_DESCRIPTOR_BLOCK0_ADDRESS + 2 +
+			 count * EDID_TIMING_DESCRIPTOR_SIZE]);
+		*vertical_res =
+			(((edid[EDID_DESCRIPTOR_BLOCK0_ADDRESS + 7 +
+			   count * EDID_TIMING_DESCRIPTOR_SIZE] & 0xF0) << 4) |
+			 edid[EDID_DESCRIPTOR_BLOCK0_ADDRESS + 5 +
+			 count * EDID_TIMING_DESCRIPTOR_SIZE]);
+		DSSDBG("***Block-0-Timing-descriptor[%d]***\n", count);
+#ifdef EDID_DEBUG
+		for (i = current_descriptor_addrs;
+		      i <
+		      (current_descriptor_addrs+EDID_TIMING_DESCRIPTOR_SIZE);
+		      i++)
+			DSSDBG("%d ==>		%x\n", i, edid[i]);
+
+			DSSDBG("E-EDID Buffer Index	= 0x%x\n"
+				 "horizontal_res       	= %d\n"
+				 "vertical_res		= %d\n",
+				 current_descriptor_addrs,
+				 *horizontal_res,
+				 *vertical_res
+				 );
+#endif
+		if (*horizontal_res == edid_timings.x_res &&
+		    *vertical_res == edid_timings.y_res) {
+			DSSDBG("Found EDID Data for %d x %dp\n",
+					*horizontal_res, *vertical_res);
+			flag = true;
+			break;
+			}
+	}
+
+	/*check for the 1080p in extended block CEA DTDs*/
+	if (flag != true) {
+		offset = edid[EDID_DESCRIPTOR_BLOCK1_ADDRESS + 2];
+		if (offset != 0) {
+			effective_addrs = EDID_DESCRIPTOR_BLOCK1_ADDRESS
+				+ offset;
+			/*to determine the number of descriptor blocks */
+			for (count = 0;
+			      count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR;
+			      count++) {
+				current_descriptor_addrs = effective_addrs +
+					count * EDID_TIMING_DESCRIPTOR_SIZE;
+				*horizontal_res =
+					(((edid[effective_addrs + 4 +
+					   count*EDID_TIMING_DESCRIPTOR_SIZE] &
+					   0xF0) << 4) |
+					 edid[effective_addrs + 2 +
+					 count * EDID_TIMING_DESCRIPTOR_SIZE]);
+				*vertical_res =
+					(((edid[effective_addrs + 7 +
+					   count*EDID_TIMING_DESCRIPTOR_SIZE] &
+					   0xF0) << 4) |
+					 edid[effective_addrs + 5 +
+					 count * EDID_TIMING_DESCRIPTOR_SIZE]);
+
+				DSSDBG("Block1-Timing-descriptor[%d]\n", count);
+#ifdef EDID_DEBUG
+				for (i = current_descriptor_addrs;
+				      i < (current_descriptor_addrs+
+					   EDID_TIMING_DESCRIPTOR_SIZE); i++)
+					DSSDBG("%x ==> 	%x\n",
+						   i, edid[i]);
+
+				DSSDBG("current_descriptor	= 0x%x\n"
+						"horizontal_res		= %d\n"
+						"vertical_res 		= %d\n",
+					 current_descriptor_addrs,
+					 *horizontal_res, *vertical_res);
+#endif
+				if (*horizontal_res == edid_timings.x_res &&
+				    *vertical_res == edid_timings.y_res) {
+					DSSDBG("Found EDID Data for "
+						 "%d x %dp\n",
+						 *horizontal_res,
+						 *vertical_res
+						 );
+					flag = true;
+					break;
+					}
+			}
+		}
+	}
+
+	if (flag == true) {
+		*pixel_clk = ((edid[current_descriptor_addrs + 1] << 8) |
+					edid[current_descriptor_addrs]);
+
+		edid_timings.x_res = *horizontal_res;
+		edid_timings.y_res = *vertical_res;
+		edid_timings.pixel_clock = *pixel_clk*10;
+		printk(KERN_INFO "EDID TIMING DATA FOUND\n");
+		DSSDBG("EDID DTD block address	= 0x%x\n"
+			 "pixel_clk 			= %d\n"
+			 "horizontal res		= %d\n"
+			 "vertical res			= %d\n",
+			 current_descriptor_addrs,
+			 edid_timings.pixel_clock,
+			 edid_timings.x_res,
+			 edid_timings.y_res
+			 );
+
+		get_horz_vert_timing_info(edid);
+	} else {
+
+		printk(KERN_INFO "EDID TIMING DATA supported NOT FOUND\n");
+		DSSDBG("setting default timing values\n"
+			 "pixel_clk 		= %d\n"
+			 "horizontal res	= %d\n"
+			 "vertical res		= %d\n",
+			 edid_timings.pixel_clock,
+			 edid_timings.x_res,
+			 edid_timings.y_res
+			 );
+
+		*pixel_clk = edid_timings.pixel_clock;
+		*horizontal_res = edid_timings.x_res;
+		*vertical_res = edid_timings.y_res;
+	}
+
+	return flag;
+}
+
+void hdmi_dump_regs(struct seq_file *s)
+{
+	DSSDBG("0x4a100060 x%x\n", omap_readl(0x4A100060));
+	DSSDBG("0x4A100088 x%x\n", omap_readl(0x4A100088));
+	DSSDBG("0x48055134 x%x\n", omap_readl(0x48055134));
+	DSSDBG("0x48055194 x%x\n", omap_readl(0x48055194));
+}
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h
new file mode 100644
index 000000000000..ea2228c6cdb9
--- /dev/null
+++ b/drivers/video/omap2/dss/hdmi.h
@@ -0,0 +1,245 @@
+/*
+ * drivers/media/video/omap2/dss/hdmi.h
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * hdmi driver
+ */
+#ifndef _OMAP4_HDMI_H_
+#define _OMAP4_HDMI_H_
+
+#define HDMI_EDID_DETAILED_TIMING_OFFSET  0x36 /*EDID Detailed Timing
+							Info 0 begin offset*/
+#define HDMI_EDID_PIX_CLK_OFFSET          0
+#define HDMI_EDID_H_ACTIVE_OFFSET         2
+#define HDMI_EDID_H_BLANKING_OFFSET       3
+#define HDMI_EDID_V_ACTIVE_OFFSET         5
+#define HDMI_EDID_V_BLANKING_OFFSET       6
+#define HDMI_EDID_H_SYNC_OFFSET           8
+#define HDMI_EDID_H_SYNC_PW_OFFSET        9
+#define HDMI_EDID_V_SYNC_OFFSET           10
+#define HDMI_EDID_V_SYNC_PW_OFFSET        10
+#define HDMI_EDID_H_IMAGE_SIZE_OFFSET     12
+#define HDMI_EDID_V_IMAGE_SIZE_OFFSET     13
+#define HDMI_EDID_H_BORDER_OFFSET         15
+#define HDMI_EDID_V_BORDER_OFFSET         16
+#define HDMI_EDID_FLAGS_OFFSET            17
+
+
+#define EDID_TIMING_DESCRIPTOR_SIZE 		0x12
+#define EDID_DESCRIPTOR_BLOCK0_ADDRESS  	0x36
+#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 		0x80
+#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 	4
+#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 	4
+
+/* HDMI Connected States  */
+#define HDMI_STATE_NOMONITOR    0       /* No HDMI monitor connected*/
+#define HDMI_STATE_CONNECTED    1  /* HDMI monitor connected but powered off*/
+#define HDMI_STATE_ON           2  /* HDMI monitor connected and powered on*/
+
+
+/* HDMI EDID Length  */
+#define HDMI_EDID_MAX_LENGTH    256
+
+/* HDMI EDID DTDs  */
+#define HDMI_EDID_MAX_DTDS      4
+
+/* HDMI EDID DTD Tags  */
+#define HDMI_EDID_DTD_TAG_MONITOR_NAME              0xFC
+#define HDMI_EDID_DTD_TAG_MONITOR_SERIALNUM         0xFF
+#define HDMI_EDID_DTD_TAG_MONITOR_LIMITS            0xFD
+
+
+/* HDMI EDID Extension Data Block Tags  */
+#define HDMI_EDID_EX_DATABLOCK_TAG_MASK             0xE0
+#define HDMI_EDID_EX_DATABLOCK_LEN_MASK             0x1F
+
+#define HDMI_EDID_EX_DATABLOCK_AUDIO                0x20
+#define HDMI_EDID_EX_DATABLOCK_VIDEO                0x40
+#define HDMI_EDID_EX_DATABLOCK_VENDOR               0x60
+#define HDMI_EDID_EX_DATABLOCK_SPEAKERS             0x80
+
+/* HDMI EDID Extenion Data Block Values: Video  */
+#define HDMI_EDID_EX_VIDEO_NATIVE                   0x80
+#define HDMI_EDID_EX_VIDEO_MASK                     0x7F
+#define HDMI_EDID_EX_VIDEO_MAX                      35
+
+#define HDMI_EDID_EX_VIDEO_640x480p_60Hz_4_3        1
+#define HDMI_EDID_EX_VIDEO_720x480p_60Hz_4_3        2
+#define HDMI_EDID_EX_VIDEO_720x480p_60Hz_16_9       3
+#define HDMI_EDID_EX_VIDEO_1280x720p_60Hz_16_9      4
+#define HDMI_EDID_EX_VIDEO_1920x1080i_60Hz_16_9     5
+#define HDMI_EDID_EX_VIDEO_720x480i_60Hz_4_3        6
+#define HDMI_EDID_EX_VIDEO_720x480i_60Hz_16_9       7
+#define HDMI_EDID_EX_VIDEO_720x240p_60Hz_4_3        8
+#define HDMI_EDID_EX_VIDEO_720x240p_60Hz_16_9       9
+#define HDMI_EDID_EX_VIDEO_2880x480i_60Hz_4_3       10
+#define HDMI_EDID_EX_VIDEO_2880x480i_60Hz_16_9      11
+#define HDMI_EDID_EX_VIDEO_2880x480p_60Hz_4_3       12
+#define HDMI_EDID_EX_VIDEO_2880x480p_60Hz_16_9      13
+#define HDMI_EDID_EX_VIDEO_1440x480p_60Hz_4_3       14
+#define HDMI_EDID_EX_VIDEO_1440x480p_60Hz_16_9      15
+#define HDMI_EDID_EX_VIDEO_1920x1080p_60Hz_16_9     16
+#define HDMI_EDID_EX_VIDEO_720x576p_50Hz_4_3        17
+#define HDMI_EDID_EX_VIDEO_720x576p_50Hz_16_9       18
+#define HDMI_EDID_EX_VIDEO_1280x720p_50Hz_16_9      19
+#define HDMI_EDID_EX_VIDEO_1920x1080i_50Hz_16_9     20
+#define HDMI_EDID_EX_VIDEO_720x576i_50Hz_4_3        21
+#define HDMI_EDID_EX_VIDEO_720x576i_50Hz_16_9       22
+#define HDMI_EDID_EX_VIDEO_720x288p_50Hz_4_3        23
+#define HDMI_EDID_EX_VIDEO_720x288p_50Hz_16_9       24
+#define HDMI_EDID_EX_VIDEO_2880x576i_50Hz_4_3       25
+#define HDMI_EDID_EX_VIDEO_2880x576i_50Hz_16_9      26
+#define HDMI_EDID_EX_VIDEO_2880x288p_50Hz_4_3       27
+#define HDMI_EDID_EX_VIDEO_2880x288p_50Hz_16_9      28
+#define HDMI_EDID_EX_VIDEO_1440x576p_50Hz_4_3       29
+#define HDMI_EDID_EX_VIDEO_1440x576p_50Hz_16_9      30
+#define HDMI_EDID_EX_VIDEO_1920x1080p_50Hz_16_9     31
+#define HDMI_EDID_EX_VIDEO_1920x1080p_24Hz_16_9     32
+#define HDMI_EDID_EX_VIDEO_1920x1080p_25Hz_16_9     33
+#define HDMI_EDID_EX_VIDEO_1920x1080p_30Hz_16_9     34
+
+/*---------------------------------------------------------------------  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*  Video Descriptor Block  */
+typedef struct {
+	u8   pixel_clock[2];          /* 54-55 */
+	u8   horiz_active;            /* 56 */
+	u8   horiz_blanking;          /* 57 */
+	u8   horiz_high;              /* 58 */
+	u8   vert_active;             /* 59 */
+	u8   vert_blanking;           /* 60 */
+	u8   vert_high;               /* 61 */
+	u8   horiz_sync_offset;       /* 62 */
+	u8   horiz_sync_pulse;        /* 63 */
+	u8   vert_sync_pulse;         /* 64 */
+	u8   sync_pulse_high;         /* 65 */
+	u8   horiz_image_size;        /* 66 */
+	u8   vert_image_size;	      /* 67 */
+	u8   image_size_high;         /* 68 */
+	u8   horiz_border;            /* 69 */
+	u8   vert_border;             /* 70 */
+	u8   misc_settings;           /* 71 */
+}
+HDMI_EDID_DTD_VIDEO;
+
+
+/*  Monitor Limits Descriptor Block  */
+typedef struct {
+	u8   pixel_clock[2];          	/* 54-55*/
+	u8   _reserved1;             	/* 56 */
+	u8   block_type;              	/* 57 */
+	u8   _reserved2;             	/* 58 */
+	u8   min_vert_freq;            	/* 59 */
+	u8   max_vert_freq;            	/* 60 */
+	u8   min_horiz_freq;           	/* 61 */
+	u8   max_horiz_freq;           	/* 62 */
+	u8   pixel_clock_mhz;         	/* 63 */
+
+	u8   GTF[2];                 	/* 64 -65 */
+	u8   start_horiz_freq;         	/* 66  */
+	u8   C;	                    	/* 67 */
+	u8   M[2];                   	/* 68-69 */
+	u8   K;                      	/* 70 */
+	u8   J;                      	/* 71 */
+}
+HDMI_EDID_DTD_MONITOR;
+
+
+/*  Text Descriptor Block  */
+typedef struct {
+	u8   pixel_clock[2];          	/* 54-55 */
+	u8   _reserved1;             	/* 56 */
+	u8   block_type;              	/* 57 */
+	u8   _reserved2;             	/* 58 */
+
+	u8   text[13];               	/* 59-71 */
+}
+HDMI_EDID_DTD_TEXT;
+
+
+/*  DTD Union  */
+typedef union {
+	HDMI_EDID_DTD_VIDEO     	video;
+	HDMI_EDID_DTD_TEXT      	monitor_name;
+	HDMI_EDID_DTD_TEXT      	monitor_serial_number;
+	HDMI_EDID_DTD_MONITOR   	monitor_limits;
+}
+HDMI_EDID_DTD;
+
+
+/*  EDID struct  */
+typedef struct {
+	u8   header[8];              	/* 00-07 */
+	u8   manufacturerID[2];      	/* 08-09 */
+	u8   product_id[2];           	/* 10-11 */
+	u8   serial_number[4];        	/* 12-15 */
+	u8   week_manufactured;       	/* 16 */
+	u8   year_manufactured;       	/* 17 */
+	u8   edid_version;            	/* 18 */
+	u8   edid_revision;           	/* 19 */
+
+	u8   video_in_definition;      	/* 20 */
+	u8   max_horiz_image_size;      /* 21 */
+	u8   max_vert_image_size;       /* 22 */
+	u8   display_gamma;           	/* 23 */
+	u8   power_features;          	/* 24 */
+	u8   chroma_info[10];         	/* 25-34 */
+	u8   timing_1;                	/* 35 */
+	u8   timing_2;               	/* 36 */
+	u8   timing_3;              	/* 37 */
+	u8   std_timings[16];         	/* 38-53 */
+
+	HDMI_EDID_DTD   DTD[4];         /* 72-125 */
+
+	u8   extension_edid;          	/* 126 */
+	u8   checksum;			/* 127 */
+
+	u8   extension_tag;		/* 00 (extensions follow EDID) */
+	u8   extention_rev;		/* 01 */
+	u8   offset_dtd;		/* 02 */
+	u8   num_dtd;			/* 03 */
+
+	u8   data_block[123];		/* 04 - 126 */
+	u8   extension_checksum;	/* 127 */
+ }
+HDMI_EDID;
+
+static int hdmi_enable_display(struct omap_dss_device *dssdev);
+static void hdmi_disable_display(struct omap_dss_device *dssdev);
+static int hdmi_display_suspend(struct omap_dss_device *dssdev);
+static int hdmi_display_resume(struct omap_dss_device *dssdev);
+static void hdmi_get_timings(struct omap_dss_device *dssdev,
+			struct omap_video_timings *timings);
+static void hdmi_set_timings(struct omap_dss_device *dssdev,
+			struct omap_video_timings *timings);
+static void hdmi_set_custom_edid_timing_code(struct omap_dss_device *dssdev, int code , int mode);
+static void hdmi_get_edid(struct omap_dss_device *dssdev);
+static int hdmi_check_timings(struct omap_dss_device *dssdev,
+			struct omap_video_timings *timings);
+static int hdmi_read_edid(struct omap_video_timings *);
+static int get_edid_timing_data(u8 *edid, u16 *pixel_clk, u16 *horizontal_res,
+			  u16 *vertical_res);
+void show_horz_vert_timing_info(u8 *edid);
+int hdmi_get_image_format(void);
+int hdmi_get_audio_format(void);
+static irqreturn_t hdmi_irq_handler(int irq, void *arg);
+static int hdmi_enable_hpd(struct omap_dss_device *dssdev);
+static void hdmi_power_off(struct omap_dss_device *dssdev);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index 0820986d4a68..2f32160c8375 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -34,6 +34,8 @@
 
 #include "dss.h"
 
+#define MAX_DSS_MANAGERS (cpu_is_omap44xx() ? 3 : 2)
+
 static int num_managers;
 static struct list_head manager_list;
 
@@ -415,6 +417,8 @@ struct overlay_cache_data {
 	u32 fifo_high;
 
 	bool manual_update;
+	enum omap_overlay_zorder zorder;
+	u32 p_uv_addr; /* relevent for NV12 format only */
 };
 
 struct manager_cache_data {
@@ -444,8 +448,9 @@ struct manager_cache_data {
 
 static struct {
 	spinlock_t lock;
-	struct overlay_cache_data overlay_cache[3];
-	struct manager_cache_data manager_cache[2];
+	struct overlay_cache_data overlay_cache[4];
+	struct manager_cache_data manager_cache[3];
+	struct writeback_cache_data writeback_cache;
 
 	bool irq_enabled;
 } dss_cache;
@@ -509,9 +514,20 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
 
 	if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC)
 		irq = DISPC_IRQ_EVSYNC_ODD;
-	else
-		irq = DISPC_IRQ_VSYNC;
-
+	else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI)
+		irq = DISPC_IRQ_EVSYNC_EVEN;
+	else if ((mgr->device->type == OMAP_DISPLAY_TYPE_DSI)
+			&& (mgr->device->channel == OMAP_DSS_CHANNEL_LCD))
+		irq = DISPC_IRQ_FRAMEDONE;
+	else if ((mgr->device->type == OMAP_DISPLAY_TYPE_DSI)
+			&& (mgr->device->channel == OMAP_DSS_CHANNEL_LCD2))
+		irq = DISPC_IRQ_FRAMEDONE2;
+	else if ((mgr->device->type == OMAP_DISPLAY_TYPE_DPI)
+			&& (mgr->device->channel == OMAP_DSS_CHANNEL_LCD))
+			irq = DISPC_IRQ_VSYNC;
+	else if ((mgr->device->type == OMAP_DISPLAY_TYPE_DPI)
+			&& (mgr->device->channel == OMAP_DSS_CHANNEL_LCD2))
+			irq = DISPC_IRQ_VSYNC2;
 	return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
 }
 
@@ -527,10 +543,10 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
 
 	if (!dssdev)
 		return 0;
-
-	if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
+	channel = mgr->device->channel;
+	if (dssdev->type == OMAP_DISPLAY_TYPE_VENC
+		|| dssdev->type == OMAP_DISPLAY_TYPE_HDMI) {
 		irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
-		channel = OMAP_DSS_CHANNEL_DIGIT;
 	} else {
 		if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
 			enum omap_dss_update_mode mode;
@@ -538,11 +554,16 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
 			if (mode != OMAP_DSS_UPDATE_AUTO)
 				return 0;
 
-			irq = DISPC_IRQ_FRAMEDONE;
+			irq = (channel == OMAP_DSS_CHANNEL_LCD) ?
+						  DISPC_IRQ_FRAMEDONE
+						: DISPC_IRQ_FRAMEDONE2;
+
 		} else {
-			irq = DISPC_IRQ_VSYNC;
+			irq = (channel == OMAP_DSS_CHANNEL_LCD) ?
+							DISPC_IRQ_VSYNC
+							: DISPC_IRQ_VSYNC2;
+
 		}
-		channel = OMAP_DSS_CHANNEL_LCD;
 	}
 
 	mc = &dss_cache.manager_cache[mgr->id];
@@ -600,10 +621,11 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
 		return 0;
 
 	dssdev = ovl->manager->device;
+	channel = dssdev->channel;
 
-	if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
+	if (dssdev->type == OMAP_DISPLAY_TYPE_VENC
+		|| dssdev->type == OMAP_DISPLAY_TYPE_HDMI) {
 		irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
-		channel = OMAP_DSS_CHANNEL_DIGIT;
 	} else {
 		if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
 			enum omap_dss_update_mode mode;
@@ -611,11 +633,14 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
 			if (mode != OMAP_DSS_UPDATE_AUTO)
 				return 0;
 
-			irq = DISPC_IRQ_FRAMEDONE;
+			irq = (channel == OMAP_DSS_CHANNEL_LCD) ?
+						  DISPC_IRQ_FRAMEDONE
+						: DISPC_IRQ_FRAMEDONE2;
 		} else {
-			irq = DISPC_IRQ_VSYNC;
+			irq = (channel == OMAP_DSS_CHANNEL_LCD) ?
+							DISPC_IRQ_VSYNC
+							: DISPC_IRQ_VSYNC2;
 		}
-		channel = OMAP_DSS_CHANNEL_LCD;
 	}
 
 	oc = &dss_cache.overlay_cache[ovl->id];
@@ -816,7 +841,9 @@ static int configure_overlay(enum omap_plane plane)
 			c->rotation_type,
 			c->rotation,
 			c->mirror,
-			c->global_alpha);
+			c->global_alpha,
+			c->channel,
+			c->p_uv_addr);
 
 	if (r) {
 		/* this shouldn't happen */
@@ -828,8 +855,22 @@ static int configure_overlay(enum omap_plane plane)
 	dispc_enable_replication(plane, c->replication);
 
 	dispc_set_burst_size(plane, c->burst_size);
+	dispc_set_zorder(plane, c->zorder);
+	dispc_enable_zorder(plane, 1);
 	dispc_setup_plane_fifo(plane, c->fifo_low, c->fifo_high);
-
+	if (cpu_is_omap44xx()) {
+		struct writeback_cache_data *wb;
+		wb = &dss_cache.writeback_cache;
+		/*if  writeback is enabled and input  source is the current overlay
+		set writeback values and enable wb plane before source plane*/
+		if ((wb->enabled) &&
+		(omap_dss_check_wb(wb, plane, c->channel))) {
+			/* writeback is enabled for this plane - set accordingly */
+			dispc_setup_wb(wb);
+			wb->dirty = false;
+			wb->shadow_dirty = true;
+		}
+	}
 	dispc_enable_plane(plane, 1);
 
 	return 0;
@@ -856,21 +897,25 @@ static int configure_dispc(void)
 {
 	struct overlay_cache_data *oc;
 	struct manager_cache_data *mc;
+	struct writeback_cache_data *wb;
 	const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
-	const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
+	const int num_mgrs = MAX_DSS_MANAGERS;
 	int i;
 	int r;
-	bool mgr_busy[2];
-	bool mgr_go[2];
+	bool mgr_busy[MAX_DSS_MANAGERS];
+	bool mgr_go[MAX_DSS_MANAGERS];
 	bool busy;
 
 	r = 0;
 	busy = false;
 
-	mgr_busy[0] = dispc_go_busy(0);
-	mgr_busy[1] = dispc_go_busy(1);
-	mgr_go[0] = false;
-	mgr_go[1] = false;
+	for (i = 0; i < num_mgrs; i++) {
+		mgr_busy[i] = dispc_go_busy(i);
+		mgr_go[i] = false;
+	}
+
+	if (cpu_is_omap44xx())
+		wb = &dss_cache.writeback_cache;
 
 	/* Commit overlay settings */
 	for (i = 0; i < num_ovls; ++i) {
@@ -894,7 +939,12 @@ static int configure_dispc(void)
 
 		oc->dirty = false;
 		oc->shadow_dirty = true;
+		if (!cpu_is_omap44xx())
 		mgr_go[oc->channel] = true;
+		else
+			if (!omap_dss_check_wb(wb, i, -1))
+				/*skip manager go if WB enabled*/
+				mgr_go[oc->channel] = true;
 	}
 
 	/* Commit manager settings */
@@ -917,7 +967,28 @@ static int configure_dispc(void)
 		mc->shadow_dirty = true;
 		mgr_go[i] = true;
 	}
-
+	if (cpu_is_omap44xx()) {
+		/*Enable WB plane and source plane */
+		DSSDBG("configure manager wb->shadow_dirty = %d", wb->shadow_dirty);
+		if (wb->shadow_dirty && wb->enabled) {
+			DSSDBG("dispc_go_wb_is called after enabling input plane and then WB");
+			switch (wb->source) {
+			case OMAP_WB_OVERLAY0:
+			case OMAP_WB_OVERLAY1:
+			case OMAP_WB_OVERLAY2:
+			case OMAP_WB_OVERLAY3:
+				dispc_enable_plane(wb->source - 3, 1);
+				break;
+			case OMAP_WB_LCD_1_MANAGER:
+			case OMAP_WB_LCD_2_MANAGER:
+			case OMAP_WB_TV_MANAGER:
+				;/*Do nothing As of now as we dont support Manager yet with WB*/
+			}
+			dispc_go_wb();
+			wb->shadow_dirty = false;
+			dispc_enable_plane(OMAP_DSS_WB, 1);
+		}
+	}
 	/* set GO */
 	for (i = 0; i < num_mgrs; ++i) {
 		mc = &dss_cache.manager_cache[i];
@@ -940,6 +1011,22 @@ static int configure_dispc(void)
 	return r;
 }
 
+/* Make the coordinates even. There are some strange problems with OMAP and
+ * partial DSI update when the update widths are odd. */
+static void make_even(u16 *x, u16 *w)
+{
+	u16 x1, x2;
+
+	x1 = *x;
+	x2 = *x + *w;
+
+	x1 &= ~1;
+	x2 = ALIGN(x2, 2);
+
+	*x = x1;
+	*w = x2 - x1;
+}
+
 /* Configure dispc for partial update. Return possibly modified update
  * area */
 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
@@ -968,6 +1055,8 @@ void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 		return;
 	}
 
+	make_even(&x, &w);
+
 	spin_lock_irqsave(&dss_cache.lock, flags);
 
 	/* We need to show the whole overlay if it is scaled. So look for
@@ -1029,6 +1118,8 @@ void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 		w = x2 - x1;
 		h = y2 - y1;
 
+		make_even(&x, &w);
+
 		DSSDBG("changing upd area due to ovl(%d) scaling %d,%d %dx%d\n",
 				i, x, y, w, h);
 	}
@@ -1057,7 +1148,7 @@ void dss_start_update(struct omap_dss_device *dssdev)
 	struct manager_cache_data *mc;
 	struct overlay_cache_data *oc;
 	const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
-	const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
+	const int num_mgrs = MAX_DSS_MANAGERS;
 	struct omap_overlay_manager *mgr;
 	int i;
 
@@ -1089,10 +1180,10 @@ static void dss_apply_irq_handler(void *data, u32 mask)
 	const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache);
 	const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache);
 	int i, r;
-	bool mgr_busy[2];
+	bool mgr_busy[MAX_DSS_MANAGERS];
 
-	mgr_busy[0] = dispc_go_busy(0);
-	mgr_busy[1] = dispc_go_busy(1);
+	for (i = 0; i < num_mgrs; i++)
+		mgr_busy[i] = dispc_go_busy(i);
 
 	spin_lock(&dss_cache.lock);
 
@@ -1125,7 +1216,7 @@ static void dss_apply_irq_handler(void *data, u32 mask)
 
 	omap_dispc_unregister_isr(dss_apply_irq_handler, NULL,
 			DISPC_IRQ_VSYNC	| DISPC_IRQ_EVSYNC_ODD |
-			DISPC_IRQ_EVSYNC_EVEN);
+			DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_VSYNC2);
 	dss_cache.irq_enabled = false;
 
 end:
@@ -1186,6 +1277,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 		oc->dirty = true;
 
 		oc->paddr = ovl->info.paddr;
+		oc->p_uv_addr = ovl->info.p_uv_addr;
 		oc->vaddr = ovl->info.vaddr;
 		oc->screen_width = ovl->info.screen_width;
 		oc->width = ovl->info.width;
@@ -1199,6 +1291,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 		oc->out_width = ovl->info.out_width;
 		oc->out_height = ovl->info.out_height;
 		oc->global_alpha = ovl->info.global_alpha;
+		oc->zorder = ovl->info.zorder;
 
 		oc->replication =
 			dss_use_replication(dssdev, ovl->info.color_mode);
@@ -1298,6 +1391,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 		case OMAP_DISPLAY_TYPE_DBI:
 		case OMAP_DISPLAY_TYPE_SDI:
 		case OMAP_DISPLAY_TYPE_VENC:
+		case OMAP_DISPLAY_TYPE_HDMI:
 			default_get_overlay_fifo_thresholds(ovl->id, size,
 					&oc->burst_size, &oc->fifo_low,
 					&oc->fifo_high);
@@ -1319,7 +1413,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 	if (!dss_cache.irq_enabled) {
 		r = omap_dispc_register_isr(dss_apply_irq_handler, NULL,
 				DISPC_IRQ_VSYNC	| DISPC_IRQ_EVSYNC_ODD |
-				DISPC_IRQ_EVSYNC_EVEN);
+				DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_VSYNC2);
 		dss_cache.irq_enabled = true;
 	}
 	configure_dispc();
@@ -1330,6 +1424,274 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 	return r;
 }
 
+int count_wb_manager = 0;
+void wb_irq_handler(void *data, u32 mask)
+{
+	count_wb_manager++;
+	DSSDBG("Framedone wb count = %d", count_wb_manager);
+}
+
+int omap_dss_wb_apply(struct omap_overlay_manager *mgr, struct omap_writeback *wb)
+{
+	struct overlay_cache_data *oc;
+	struct manager_cache_data *mc;
+	int i, j;
+	struct omap_overlay *ovl;
+	int num_planes_enabled = 0;
+	bool use_fifomerge;
+	unsigned long flags;
+	int r;
+	struct writeback_cache_data *wbc;
+
+	DSSDBG("omap_dss_wb_apply(%s)\n", mgr->name);
+
+	spin_lock_irqsave(&dss_cache.lock, flags);
+
+	/* Configure overlays */
+	for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+		struct omap_dss_device *dssdev;
+
+		ovl = omap_dss_get_overlay(i);
+
+		if (ovl == NULL)
+			break;
+
+		if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
+			continue;
+
+		oc = &dss_cache.overlay_cache[ovl->id];
+
+		if (!overlay_enabled(ovl)) {
+			if (oc->enabled) {
+				oc->enabled = false;
+				oc->dirty = true;
+			}
+			continue;
+		}
+		oc->enabled = true;
+
+		if (!ovl->info_dirty) {
+			if (oc->enabled)
+				++num_planes_enabled;
+			continue;
+		}
+
+		dssdev = ovl->manager->device;
+
+		if (dss_check_overlay(ovl, dssdev)) {
+			if (oc->enabled) {
+				oc->enabled = false;
+				oc->dirty = true;
+			}
+			continue;
+		}
+
+		ovl->info_dirty = false;
+		oc->dirty = true;
+
+		oc->paddr = ovl->info.paddr;
+		oc->p_uv_addr = ovl->info.p_uv_addr;
+		oc->zorder = ovl->info.zorder;
+		oc->vaddr = ovl->info.vaddr;
+		oc->screen_width = ovl->info.screen_width;
+		oc->width = ovl->info.width;
+		oc->height = ovl->info.height;
+		oc->color_mode = ovl->info.color_mode;
+		oc->rotation = ovl->info.rotation;
+		oc->rotation_type = ovl->info.rotation_type;
+		oc->mirror = ovl->info.mirror;
+		oc->pos_x = ovl->info.pos_x;
+		oc->pos_y = ovl->info.pos_y;
+		oc->out_width = ovl->info.out_width;
+		oc->out_height = ovl->info.out_height;
+		oc->global_alpha = ovl->info.global_alpha;
+
+		oc->replication =
+			dss_use_replication(dssdev, ovl->info.color_mode);
+
+		oc->ilace = dssdev->type == OMAP_DISPLAY_TYPE_VENC;
+
+		oc->channel = ovl->manager->id;
+		/* TODO: to change with dssdev->channel? */
+
+		oc->enabled = true;
+
+		oc->manual_update =
+			dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE &&
+			dssdev->driver->get_update_mode(dssdev) != OMAP_DSS_UPDATE_AUTO;
+
+		++num_planes_enabled;
+		wbc = &dss_cache.writeback_cache;
+
+		if (!wb->first_time) {
+			DSSDBG("entered wb_first time\n");
+			wbc->enabled = true;
+			wbc->source = wb->info.source;
+			wbc->source_type = wb->info.source_type;
+			wb->first_time = true;
+		}
+		DSSDBG("dss_wb_apply %d\n", wbc->enabled);
+		/* Configure Write-back - check for connect with this overlay*/
+		if ((wbc->enabled) &&
+			(omap_dss_check_wb(wbc, ovl->id , ovl->manager->id))) {
+
+			DSSDBG("dss_mgr_apply paddr = %lx", wb->info.paddr);
+			for (j = 0 ; j < 1 ; j++) {
+				if (!wb->enabled) {
+					if (wbc->enabled) {
+						wbc->enabled = false;
+						wbc->dirty = true;
+					}
+					continue;
+				}
+				if (!wb->info_dirty)
+					continue;
+
+				wb->info_dirty = false;
+				wbc->dirty = true;
+
+				wbc->color_mode = wb->info.dss_mode;
+				wbc->input_color_mode = oc->color_mode;
+				/*OMAP_DSS_COLOR_ARGB32;  */
+				wbc->width = wb->info.width;
+				wbc->height = wb->info.height;
+				wbc->input_width = ovl->info.width;
+				wbc->input_height = ovl->info.height;
+
+				wbc->paddr = wb->info.paddr;
+				wbc->puv_addr = wb->info.puv_addr;
+
+				wbc->enabled = true;
+
+				wbc->capturemode = wb->info.capturemode;
+				wbc->burst_size = OMAP_DSS_BURST_16x32; /* 8x128 - min. for OMAP4 */
+				wbc->source = wb->info.source;
+
+				/* TODO: Set fifo high, fifo low values ? */
+				wbc->fifo_high = 0x28A;
+				wbc->fifo_low = 0XFA;
+			}
+		}
+	}
+	if (count_wb_manager == 0)
+		omap_dispc_register_isr(wb_irq_handler, NULL,
+				DISPC_IRQ_FRAMEDONE_WB);
+	/* Configure managers */
+	list_for_each_entry(mgr, &manager_list, list) {
+		struct omap_dss_device *dssdev;
+
+		if (!(mgr->caps & OMAP_DSS_OVL_MGR_CAP_DISPC))
+			continue;
+
+		mc = &dss_cache.manager_cache[mgr->id];
+
+		if (mgr->device_changed) {
+			mgr->device_changed = false;
+			mgr->info_dirty  = true;
+		}
+
+		if (!mgr->info_dirty)
+			continue;
+
+		if (!mgr->device)
+			continue;
+
+		dssdev = mgr->device;
+
+		mgr->info_dirty = false;
+		mc->dirty = true;
+
+		mc->default_color = mgr->info.default_color;
+		mc->trans_key_type = mgr->info.trans_key_type;
+		mc->trans_key = mgr->info.trans_key;
+		mc->trans_enabled = mgr->info.trans_enabled;
+		mc->alpha_enabled = mgr->info.alpha_enabled;
+
+		mc->manual_upd_display =
+			dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
+
+		mc->manual_update =
+			dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE &&
+			dssdev->driver->get_update_mode(dssdev) != OMAP_DSS_UPDATE_AUTO;
+	}
+
+	/* XXX TODO: Try to get fifomerge working. The problem is that it
+	 * affects both managers, not individually but at the same time. This
+	 * means the change has to be well synchronized. I guess the proper way
+	 * is to have a two step process for fifo merge:
+	 *        fifomerge enable:
+	 *             1. disable other planes, leaving one plane enabled
+	 *             2. wait until the planes are disabled on HW
+	 *             3. config merged fifo thresholds, enable fifomerge
+	 *        fifomerge disable:
+	 *             1. config unmerged fifo thresholds, disable fifomerge
+	 *             2. wait until fifo changes are in HW
+	 *             3. enable planes
+	 */
+	use_fifomerge = false;
+
+	/* Configure overlay fifos */
+	for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+		struct omap_dss_device *dssdev;
+		u32 size;
+
+		ovl = omap_dss_get_overlay(i);
+
+		if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
+			continue;
+
+		oc = &dss_cache.overlay_cache[ovl->id];
+
+		if (!oc->enabled)
+			continue;
+
+		dssdev = ovl->manager->device;
+
+		size = dispc_get_plane_fifo_size(ovl->id);
+		if (use_fifomerge)
+			size *= 3;
+
+		switch (dssdev->type) {
+		case OMAP_DISPLAY_TYPE_DPI:
+		case OMAP_DISPLAY_TYPE_DBI:
+		case OMAP_DISPLAY_TYPE_SDI:
+		case OMAP_DISPLAY_TYPE_VENC:
+		case OMAP_DISPLAY_TYPE_HDMI:
+			default_get_overlay_fifo_thresholds(ovl->id, size,
+					&oc->burst_size, &oc->fifo_low,
+					&oc->fifo_high);
+			break;
+#ifdef CONFIG_OMAP2_DSS_DSI
+		case OMAP_DISPLAY_TYPE_DSI:
+			dsi_get_overlay_fifo_thresholds(ovl->id, size,
+					&oc->burst_size, &oc->fifo_low,
+					&oc->fifo_high);
+			break;
+#endif
+		default:
+			BUG();
+		}
+	}
+
+	r = 0;
+	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+	if (!dss_cache.irq_enabled) {
+		r = omap_dispc_register_isr(dss_apply_irq_handler, NULL,
+				DISPC_IRQ_VSYNC	| DISPC_IRQ_EVSYNC_ODD |
+				DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_VSYNC2);
+
+		dss_cache.irq_enabled = true;
+	}
+	configure_dispc();
+	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+
+	spin_unlock_irqrestore(&dss_cache.lock, flags);
+
+	return r;
+}
+
+EXPORT_SYMBOL(omap_dss_wb_apply);
+
 static int dss_check_manager(struct omap_overlay_manager *mgr)
 {
 	/* OMAP supports only graphics source transparency color key and alpha
@@ -1396,7 +1758,7 @@ int dss_init_overlay_managers(struct platform_device *pdev)
 
 	num_managers = 0;
 
-	for (i = 0; i < 2; ++i) {
+	for (i = 0; i < MAX_DSS_MANAGERS; ++i) {
 		struct omap_overlay_manager *mgr;
 		mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
 
@@ -1413,8 +1775,17 @@ int dss_init_overlay_managers(struct platform_device *pdev)
 		case 1:
 			mgr->name = "tv";
 			mgr->id = OMAP_DSS_CHANNEL_DIGIT;
-			mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
+			mgr->supported_displays =
+				OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI;
 			break;
+		case 2:
+			mgr->name = "2lcd";
+			mgr->id = OMAP_DSS_CHANNEL_LCD2;
+			mgr->supported_displays =
+				OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_SDI |
+				OMAP_DISPLAY_TYPE_DPI |	OMAP_DISPLAY_TYPE_DSI;
+			break;
+
 		}
 
 		mgr->set_device = &omap_dss_set_device;
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
index 82336583adef..2462f51a6900 100644
--- a/drivers/video/omap2/dss/overlay.c
+++ b/drivers/video/omap2/dss/overlay.c
@@ -36,6 +36,8 @@
 
 #include "dss.h"
 
+#define MAX_DSS_OVERLAYS (cpu_is_omap44xx() ? 4 : 3)
+
 static int num_overlays;
 static struct list_head overlay_list;
 
@@ -56,6 +58,7 @@ static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf,
 	int i, r;
 	struct omap_overlay_manager *mgr = NULL;
 	struct omap_overlay_manager *old_mgr;
+	struct omap_overlay_info info;
 	int len = size;
 
 	if (buf[size-1] == '\n')
@@ -81,6 +84,16 @@ static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf,
 	if (mgr == ovl->manager)
 		return size;
 
+	if (sysfs_streq(mgr->name, "tv")) {
+		ovl->get_overlay_info(ovl, &info);
+		if (mgr->device->panel.timings.x_res < info.width ||
+			mgr->device->panel.timings.y_res < info.height) {
+			printk(KERN_ERR"TV does not support downscaling"
+			"Please configure overlay to supported format");
+			return -EINVAL;
+		}
+	}
+
 	old_mgr = ovl->manager;
 
 	/* detach old manager */
@@ -166,18 +179,28 @@ static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf)
 static ssize_t overlay_output_size_store(struct omap_overlay *ovl,
 		const char *buf, size_t size)
 {
-	int r;
+	int r, out_width, out_height;
 	char *last;
 	struct omap_overlay_info info;
 
 	ovl->get_overlay_info(ovl, &info);
 
-	info.out_width = simple_strtoul(buf, &last, 10);
+	out_width = simple_strtoul(buf, &last, 10);
 	++last;
 	if (last - buf >= size)
 		return -EINVAL;
 
-	info.out_height = simple_strtoul(last, &last, 10);
+	out_height = simple_strtoul(last, &last, 10);
+
+	if (sysfs_streq(ovl->manager->name, "tv")) {
+		if (ovl->manager->device->panel.timings.x_res < out_width ||
+		ovl->manager->device->panel.timings.y_res < out_height)
+		printk(KERN_ERR"TV does not support downscaling , Wrong output size");
+		return -EINVAL;
+	}
+
+	info.out_width = out_width;
+	info.out_height = out_height;
 
 	r = ovl->set_overlay_info(ovl, &info);
 	if (r)
@@ -234,10 +257,10 @@ static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
 
 	ovl->get_overlay_info(ovl, &info);
 
-	/* Video1 plane does not support global alpha
+	/* In OMAP2/3 Video1 plane does not support global alpha
 	 * to always make it 255 completely opaque
 	 */
-	if (ovl->id == OMAP_DSS_VIDEO1)
+	if ((!cpu_is_omap44xx()) && (ovl->id == OMAP_DSS_VIDEO1))
 		info.global_alpha = 255;
 	else
 		info.global_alpha = simple_strtoul(buf, NULL, 10);
@@ -255,6 +278,35 @@ static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
 	return size;
 }
 
+static ssize_t overlay_zorder_show(struct omap_overlay *ovl, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n",
+			ovl->info.zorder);
+}
+
+static ssize_t overlay_zorder_store(struct omap_overlay *ovl,
+		const char *buf, size_t size)
+{
+	int r;
+	struct omap_overlay_info info;
+
+	ovl->get_overlay_info(ovl, &info);
+
+	info.zorder = simple_strtoul(buf, NULL, 10);
+
+	r = ovl->set_overlay_info(ovl, &info);
+	if (r)
+		return r;
+
+	if (ovl->manager) {
+		r = ovl->manager->apply(ovl->manager);
+		if (r)
+			return r;
+	}
+
+	return size;
+}
+
 struct overlay_attribute {
 	struct attribute attr;
 	ssize_t (*show)(struct omap_overlay *, char *);
@@ -278,6 +330,9 @@ static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
 		overlay_enabled_show, overlay_enabled_store);
 static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR,
 		overlay_global_alpha_show, overlay_global_alpha_store);
+static OVERLAY_ATTR(zorder, S_IRUGO|S_IWUSR,
+		overlay_zorder_show, overlay_zorder_store);
+
 
 static struct attribute *overlay_sysfs_attrs[] = {
 	&overlay_attr_name.attr,
@@ -288,6 +343,7 @@ static struct attribute *overlay_sysfs_attrs[] = {
 	&overlay_attr_output_size.attr,
 	&overlay_attr_enabled.attr,
 	&overlay_attr_global_alpha.attr,
+	&overlay_attr_zorder.attr,
 	NULL
 };
 
@@ -392,6 +448,12 @@ int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev)
 		return -EINVAL;
 	}
 
+	if ((info->zorder < OMAP_DSS_OVL_ZORDER_0) ||
+			(info->zorder > OMAP_DSS_OVL_ZORDER_3)) {
+		DSSERR("overlay doesn't support zorder %d\n", info->zorder);
+		return -EINVAL;
+	}
+
 	return 0;
 }
 
@@ -510,11 +572,11 @@ static void omap_dss_add_overlay(struct omap_overlay *overlay)
 	list_add_tail(&overlay->list, &overlay_list);
 }
 
-static struct omap_overlay *dispc_overlays[3];
+static struct omap_overlay *dispc_overlays[4];
 
 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr)
 {
-	mgr->num_overlays = 3;
+	mgr->num_overlays = MAX_DSS_OVERLAYS;
 	mgr->overlays = dispc_overlays;
 }
 
@@ -535,7 +597,7 @@ void dss_init_overlays(struct platform_device *pdev)
 
 	num_overlays = 0;
 
-	for (i = 0; i < 3; ++i) {
+	for (i = 0; i < MAX_DSS_OVERLAYS; ++i) {
 		struct omap_overlay *ovl;
 		ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
 
@@ -545,32 +607,48 @@ void dss_init_overlays(struct platform_device *pdev)
 		case 0:
 			ovl->name = "gfx";
 			ovl->id = OMAP_DSS_GFX;
-			ovl->supported_modes = cpu_is_omap34xx() ?
+			ovl->supported_modes = (cpu_is_omap44xx() |
+				cpu_is_omap34xx()) ?
 				OMAP_DSS_COLOR_GFX_OMAP3 :
 				OMAP_DSS_COLOR_GFX_OMAP2;
 			ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
 			ovl->info.global_alpha = 255;
+			ovl->info.zorder = OMAP_DSS_OVL_ZORDER_0;
 			break;
 		case 1:
 			ovl->name = "vid1";
 			ovl->id = OMAP_DSS_VIDEO1;
-			ovl->supported_modes = cpu_is_omap34xx() ?
+			ovl->supported_modes = (cpu_is_omap44xx() |
+				cpu_is_omap34xx()) ?
 				OMAP_DSS_COLOR_VID1_OMAP3 :
 				OMAP_DSS_COLOR_VID_OMAP2;
 			ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
 				OMAP_DSS_OVL_CAP_DISPC;
 			ovl->info.global_alpha = 255;
+			ovl->info.zorder = OMAP_DSS_OVL_ZORDER_3;
 			break;
 		case 2:
 			ovl->name = "vid2";
 			ovl->id = OMAP_DSS_VIDEO2;
-			ovl->supported_modes = cpu_is_omap34xx() ?
+			ovl->supported_modes = (cpu_is_omap44xx() |
+				cpu_is_omap34xx()) ?
 				OMAP_DSS_COLOR_VID2_OMAP3 :
 				OMAP_DSS_COLOR_VID_OMAP2;
 			ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
 				OMAP_DSS_OVL_CAP_DISPC;
 			ovl->info.global_alpha = 255;
+			ovl->info.zorder = OMAP_DSS_OVL_ZORDER_2;
 			break;
+		case 3:
+			ovl->name = "vid3";
+			ovl->id = OMAP_DSS_VIDEO3;
+			ovl->supported_modes = OMAP_DSS_COLOR_VID3_OMAP3;
+			ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
+				OMAP_DSS_OVL_CAP_DISPC;
+			ovl->info.global_alpha = 255;
+			ovl->info.zorder = OMAP_DSS_OVL_ZORDER_1;
+			break;
+
 		}
 
 		ovl->set_manager = &omap_dss_set_manager;
@@ -627,21 +705,35 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
 	int i;
 	struct omap_overlay_manager *lcd_mgr;
 	struct omap_overlay_manager *tv_mgr;
+	struct omap_overlay_manager *lcd2_mgr = NULL;
 	struct omap_overlay_manager *mgr = NULL;
 
 	lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
 	tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
-
-	if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) {
-		if (!lcd_mgr->device || force) {
-			if (lcd_mgr->device)
-				lcd_mgr->unset_device(lcd_mgr);
-			lcd_mgr->set_device(lcd_mgr, dssdev);
-			mgr = lcd_mgr;
+	if (cpu_is_omap44xx())
+		lcd2_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD2);
+
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD2) {
+		if (!lcd2_mgr->device || force || sysfs_streq(dssdev->name, "2lcd")) {
+			if (lcd2_mgr->device)
+				lcd2_mgr->unset_device(lcd2_mgr);
+			lcd2_mgr->set_device(lcd2_mgr, dssdev);
+			mgr = lcd2_mgr;
+		}
+	} else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC
+			&& dssdev->type != OMAP_DISPLAY_TYPE_HDMI) {
+		if (lcd2_mgr) {
+			if (!lcd_mgr->device || force) {
+				if (lcd_mgr->device)
+					lcd_mgr->unset_device(lcd_mgr);
+				lcd_mgr->set_device(lcd_mgr, dssdev);
+				mgr = lcd_mgr;
+			}
 		}
 	}
 
-	if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
+	if (dssdev->type == OMAP_DISPLAY_TYPE_VENC
+		|| dssdev->type == OMAP_DISPLAY_TYPE_HDMI) {
 		if (!tv_mgr->device || force) {
 			if (tv_mgr->device)
 				tv_mgr->unset_device(tv_mgr);
@@ -651,7 +743,7 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force)
 	}
 
 	if (mgr) {
-		for (i = 0; i < 3; i++) {
+		for (i = 0; i < MAX_DSS_OVERLAYS; i++) {
 			struct omap_overlay *ovl;
 			ovl = omap_dss_get_overlay(i);
 			if (!ovl->manager || force) {
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index cc23f53cc62d..a9fbb45ca52f 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -311,7 +311,7 @@ void rfbi_transfer_area(u16 width, u16 height,
 
 	DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
 
-	dispc_set_lcd_size(width, height);
+	dispc_set_lcd_size(OMAP_DSS_CHANNEL_LCD, width, height);
 
 	dispc_enable_channel(OMAP_DSS_CHANNEL_LCD, true);
 
@@ -1018,11 +1018,14 @@ int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
 		goto err1;
 	}
 
-	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
+	dispc_set_lcd_display_type(OMAP_DSS_CHANNEL_LCD,
+					OMAP_DSS_LCD_DISPLAY_TFT);
 
-	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
+	dispc_set_parallel_interface_mode(OMAP_DSS_CHANNEL_LCD,
+					OMAP_DSS_PARALLELMODE_RFBI);
 
-	dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
+	dispc_set_tft_data_lines(OMAP_DSS_CHANNEL_LCD,
+					dssdev->ctrl.pixel_size);
 
 	rfbi_configure(dssdev->phy.rfbi.channel,
 			       dssdev->ctrl.pixel_size,
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index 12eb4042dd82..95e6a53df75f 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -23,21 +23,26 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/regulator/consumer.h>
 
 #include <plat/display.h>
+#include <plat/cpu.h>
 #include "dss.h"
 
 static struct {
 	bool skip_init;
 	bool update_enabled;
+	struct regulator *vdds_sdi_reg;
 } sdi;
 
 static void sdi_basic_init(void)
 {
-	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
+	dispc_set_parallel_interface_mode(OMAP_DSS_CHANNEL_LCD,
+					OMAP_DSS_PARALLELMODE_BYPASS);
 
-	dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
-	dispc_set_tft_data_lines(24);
+	dispc_set_lcd_display_type(OMAP_DSS_CHANNEL_LCD,
+					OMAP_DSS_LCD_DISPLAY_TFT);
+	dispc_set_tft_data_lines(OMAP_DSS_CHANNEL_LCD, 24);
 	dispc_lcd_enable_signal_polarity(1);
 }
 
@@ -57,6 +62,10 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
 		goto err0;
 	}
 
+	r = regulator_enable(sdi.vdds_sdi_reg);
+	if (r)
+		goto err1;
+
 	/* In case of skip_init sdi_init has already enabled the clocks */
 	if (!sdi.skip_init)
 		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
@@ -66,15 +75,15 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
 	/* 15.5.9.1.2 */
 	dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
 
-	dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
-			dssdev->panel.acb);
+	dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD, dssdev->panel.config,
+				dssdev->panel.acbi, dssdev->panel.acb);
 
 	if (!sdi.skip_init) {
 		r = dss_calc_clock_div(1, t->pixel_clock * 1000,
 				&dss_cinfo, &dispc_cinfo);
 	} else {
 		r = dss_get_clock_div(&dss_cinfo);
-		r = dispc_get_clock_div(&dispc_cinfo);
+		r = dispc_get_clock_div(OMAP_DSS_CHANNEL_LCD, &dispc_cinfo);
 	}
 
 	if (r)
@@ -95,7 +104,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
 	}
 
 
-	dispc_set_lcd_timings(t);
+	dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD, t);
 
 	r = dss_set_clock_div(&dss_cinfo);
 	if (r)
@@ -115,19 +124,12 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
 
 	dssdev->manager->enable(dssdev->manager);
 
-	if (dssdev->driver->enable) {
-		r = dssdev->driver->enable(dssdev);
-		if (r)
-			goto err3;
-	}
-
 	sdi.skip_init = 0;
 
 	return 0;
-err3:
-	dssdev->manager->disable(dssdev->manager);
 err2:
 	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+	regulator_disable(sdi.vdds_sdi_reg);
 err1:
 	omap_dss_stop_device(dssdev);
 err0:
@@ -137,15 +139,14 @@ EXPORT_SYMBOL(omapdss_sdi_display_enable);
 
 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev)
 {
-	if (dssdev->driver->disable)
-		dssdev->driver->disable(dssdev);
-
 	dssdev->manager->disable(dssdev->manager);
 
 	dss_sdi_disable();
 
 	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 
+	regulator_disable(sdi.vdds_sdi_reg);
+
 	omap_dss_stop_device(dssdev);
 }
 EXPORT_SYMBOL(omapdss_sdi_display_disable);
@@ -162,6 +163,11 @@ int sdi_init(bool skip_init)
 	/* we store this for first display enable, then clear it */
 	sdi.skip_init = skip_init;
 
+	sdi.vdds_sdi_reg = dss_get_vdds_sdi();
+	if (IS_ERR(sdi.vdds_sdi_reg)) {
+		DSSERR("can't get VDDS_SDI regulator\n");
+		return PTR_ERR(sdi.vdds_sdi_reg);
+	}
 	/*
 	 * Enable clocks already here, otherwise there would be a toggle
 	 * of them until sdi_display_enable is called.
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index f0ba5732d84a..eff35050e28a 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -479,12 +479,6 @@ static int venc_panel_enable(struct omap_dss_device *dssdev)
 		goto err1;
 	}
 
-	if (dssdev->platform_enable) {
-		r = dssdev->platform_enable(dssdev);
-		if (r)
-			goto err2;
-	}
-
 	venc_power_on(dssdev);
 
 	venc.wss_data = 0;
@@ -494,13 +488,9 @@ static int venc_panel_enable(struct omap_dss_device *dssdev)
 	/* wait couple of vsyncs until enabling the LCD */
 	msleep(50);
 
-	mutex_unlock(&venc.venc_lock);
-
-	return r;
-err2:
-	venc_power_off(dssdev);
 err1:
 	mutex_unlock(&venc.venc_lock);
+
 	return r;
 }
 
@@ -524,9 +514,6 @@ static void venc_panel_disable(struct omap_dss_device *dssdev)
 	/* wait at least 5 vsyncs after disabling the LCD */
 	msleep(100);
 
-	if (dssdev->platform_disable)
-		dssdev->platform_disable(dssdev);
-
 	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
 end:
 	mutex_unlock(&venc.venc_lock);
diff --git a/drivers/video/omap2/dss/wb.c b/drivers/video/omap2/dss/wb.c
new file mode 100644
index 000000000000..02f9a7a18df1
--- /dev/null
+++ b/drivers/video/omap2/dss/wb.c
@@ -0,0 +1,179 @@
+/*
+ * linux/drivers/video/omap2/dss/wb.c
+ * Copyright (C) 2009 Texas Instruments
+ * Author: mythripk <mythripk@ti.com>
+ * Some code and ideas taken from drivers/video/omap/ driver
+ * by Imre Deak.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define DSS_SUBSYS_NAME "WRITEBACK"
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <plat/display.h>
+#include <plat/cpu.h>
+
+#include "dss.h"
+
+static struct list_head wb_list;
+
+static struct attribute *writeback_sysfs_attrs[] = {
+	NULL
+};
+
+static ssize_t writeback_attr_show(struct kobject *kobj, struct attribute *attr,
+		char *buf)
+{
+return 0;
+}
+
+static ssize_t writeback_attr_store(struct kobject *kobj, struct attribute *attr,
+		const char *buf, size_t size)
+{
+return 0;
+}
+
+static struct sysfs_ops writeback_sysfs_ops = {
+	.show = writeback_attr_show,
+	.store = writeback_attr_store,
+};
+
+static struct kobj_type writeback_ktype = {
+	.sysfs_ops = &writeback_sysfs_ops,
+	.default_attrs = writeback_sysfs_attrs,
+};
+
+bool omap_dss_check_wb(struct writeback_cache_data *wb, int overlayId, int managerId)
+{
+	bool result = false;
+	DSSDBG("ovl=%d,mgr=%d,srcty=%d(%s),src=%d",
+	   overlayId, managerId, wb->source_type,
+	   wb->source_type == OMAP_WB_SOURCE_OVERLAY ? "OMAP_WB_SOURCE_OVERLAY" :
+	   wb->source_type == OMAP_WB_SOURCE_MANAGER ? "OMAP_WB_SOURCE_MANAGER" : "???",
+	   wb->source);
+
+	if ((wb->source_type == OMAP_WB_SOURCE_OVERLAY) &&
+				((wb->source - 3) == overlayId))
+		result = true;
+	else if (wb->source_type == OMAP_WB_SOURCE_MANAGER) {
+		switch (wb->source) {
+		case OMAP_WB_LCD_1_MANAGER:
+			if (managerId == OMAP_DSS_CHANNEL_LCD)
+				result = true;
+		case OMAP_WB_LCD_2_MANAGER:
+			if (managerId == OMAP_DSS_CHANNEL_LCD2)
+				result = true;
+		case OMAP_WB_TV_MANAGER:
+			if (managerId == OMAP_DSS_CHANNEL_DIGIT)
+				result = true;
+		case OMAP_WB_OVERLAY0:
+		case OMAP_WB_OVERLAY1:
+		case OMAP_WB_OVERLAY2:
+		case OMAP_WB_OVERLAY3:
+				break;
+		}
+	}
+
+	return result;
+
+}
+
+static bool dss_check_wb(struct omap_writeback *wb)
+{
+	DSSDBG("srcty=%d(%s),src=%d", wb->info.source_type,
+	   wb->info.source_type == OMAP_WB_SOURCE_OVERLAY ? "OMAP_WB_SOURCE_OVERLAY" :
+	   wb->info.source_type == OMAP_WB_SOURCE_MANAGER ? "OMAP_WB_SOURCE_MANAGER" : "???",
+	   wb->info.source);
+
+	return 0;
+}
+
+static int omap_dss_wb_set_info(struct omap_writeback *wb,
+		struct omap_writeback_info *info)
+{
+	int r;
+	struct omap_writeback_info old_info;
+	old_info = wb->info;
+	wb->info = *info;
+
+	r = dss_check_wb(wb);
+	if (r) {
+		wb->info = old_info;
+		return r;
+	}
+
+	wb->info_dirty = true;
+
+	return 0;
+}
+
+static void omap_dss_wb_get_info(struct omap_writeback *wb,
+		struct omap_writeback_info *info)
+{
+	*info = wb->info;
+}
+
+struct omap_writeback *omap_dss_get_wb(int num)
+{
+	int i = 0;
+	struct omap_writeback *wb;
+
+	list_for_each_entry(wb, &wb_list, list) {
+		if (i++ == num)
+			return wb;
+	}
+
+	return NULL;
+}
+EXPORT_SYMBOL(omap_dss_get_wb);
+
+
+static void omap_dss_add_wb(struct omap_writeback *wb)
+{
+	list_add_tail(&wb->list, &wb_list);
+}
+
+
+void dss_init_writeback(struct platform_device *pdev)
+{
+	int r;
+	struct omap_writeback *wb;
+	INIT_LIST_HEAD(&wb_list);
+
+		wb = kzalloc(sizeof(*wb), GFP_KERNEL);
+
+		BUG_ON(wb == NULL);
+
+		wb->check_wb = &dss_check_wb;
+		wb->set_wb_info = &omap_dss_wb_set_info;
+		wb->get_wb_info = &omap_dss_wb_get_info;
+		mutex_init(&wb->lock);
+
+		omap_dss_add_wb(wb);
+
+		r = kobject_init_and_add(&wb->kobj, &writeback_ktype,
+				&pdev->dev.kobj, "writeback", 0);
+
+		if (r) {
+			DSSERR("failed to create sysfs file\n");
+		}
+
+}
diff --git a/drivers/video/omap2/omapfb/Kconfig b/drivers/video/omap2/omapfb/Kconfig
index 43496d6c377f..f186c2b6509b 100644
--- a/drivers/video/omap2/omapfb/Kconfig
+++ b/drivers/video/omap2/omapfb/Kconfig
@@ -1,17 +1,16 @@
 menuconfig FB_OMAP2
-        tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)"
+        tristate "OMAP2/3/4 frame buffer support (EXPERIMENTAL)"
         depends on FB && OMAP2_DSS
 
 	select OMAP2_VRAM
-	select OMAP2_VRFB
         select FB_CFB_FILLRECT
         select FB_CFB_COPYAREA
         select FB_CFB_IMAGEBLIT
         help
-          Frame buffer driver for OMAP2/3 based boards.
+          Frame buffer driver for OMAP2/3/4 based boards.
 
 config FB_OMAP2_DEBUG_SUPPORT
-	bool "Debug support for OMAP2/3 FB"
+	bool "Debug support for OMAP2/3/4 FB"
 	default y
 	depends on FB_OMAP2
 	help
diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
index 1ffa760b8545..9c7361871d78 100644
--- a/drivers/video/omap2/omapfb/omapfb-ioctl.c
+++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
@@ -183,13 +183,14 @@ int omapfb_update_window(struct fb_info *fbi,
 	struct omapfb2_device *fbdev = ofbi->fbdev;
 	int r;
 
+	if (!lock_fb_info(fbi))
+		return -ENODEV;
 	omapfb_lock(fbdev);
-	lock_fb_info(fbi);
 
 	r = omapfb_update_window_nolock(fbi, x, y, w, h);
 
-	unlock_fb_info(fbi);
 	omapfb_unlock(fbdev);
+	unlock_fb_info(fbi);
 
 	return r;
 }
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index 4b4506da96da..34bacdd75742 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -33,6 +33,7 @@
 #include <plat/display.h>
 #include <plat/vram.h>
 #include <plat/vrfb.h>
+#include <mach/tiler.h>
 
 #include "omapfb.h"
 
@@ -44,6 +45,7 @@
 static char *def_mode;
 static char *def_vram;
 static int def_vrfb;
+static int def_tiler;
 static int def_rotate;
 static int def_mirror;
 
@@ -621,13 +623,16 @@ void set_fb_fix(struct fb_info *fbi)
 		}
 
 		fix->smem_len = var->yres_virtual * fix->line_length;
-	} else {
+	} else if (ofbi->rotation_type != OMAP_DSS_ROT_TILER) {
 		fix->line_length =
 			(var->xres_virtual * var->bits_per_pixel) >> 3;
-		fix->smem_len = rg->size;
+
+		/* tiler line length is set during allocation, and cannot
+		   be changed */
 	}
 
 	fix->smem_start = omapfb_get_region_paddr(ofbi);
+	fix->smem_len = rg->size;
 
 	fix->type = FB_TYPE_PACKED_PIXELS;
 
@@ -853,14 +858,21 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
 	DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
 			posx, posy, outw, outh);
 
+	if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+			xres = var->xres;
+			yres = var->yres;
+	} else {
 	if (rotation == FB_ROTATE_CW || rotation == FB_ROTATE_CCW) {
 		xres = var->yres;
 		yres = var->xres;
 	} else {
 		xres = var->xres;
 		yres = var->yres;
+		}
 	}
 
+	offset = ((var->yoffset * var->xres_virtual +
+				var->xoffset) * var->bits_per_pixel) >> 3;
 
 	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
 		data_start_p = omapfb_get_region_rot_paddr(ofbi, rotation);
@@ -913,7 +925,12 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
 	info.paddr = data_start_p;
 	info.vaddr = data_start_v;
 	info.screen_width = screen_width;
+	if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+		info.width =
+			((rotation == 1) | (rotation == 3)) ? yres : xres;
+	} else {
 	info.width = xres;
+	}
 	info.height = yres;
 	info.color_mode = mode;
 	info.rotation_type = ofbi->rotation_type;
@@ -922,7 +939,12 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
 
 	info.pos_x = posx;
 	info.pos_y = posy;
+	if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+		info.out_width =
+			((rotation == 1) | (rotation == 3)) ? outh : outw;
+	} else {
 	info.out_width = outw;
+	}
 	info.out_height = outh;
 
 	r = ovl->set_overlay_info(ovl, &info);
@@ -969,6 +991,10 @@ int omapfb_apply_changes(struct fb_info *fbi, int init)
 
 		if (init || (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
 			int rotation = (var->rotate + ofbi->rotation[i]) % 4;
+			if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+					outw = var->xres;
+					outh = var->yres;
+			} else {
 			if (rotation == FB_ROTATE_CW ||
 					rotation == FB_ROTATE_CCW) {
 				outw = var->yres;
@@ -977,9 +1003,27 @@ int omapfb_apply_changes(struct fb_info *fbi, int init)
 				outw = var->xres;
 				outh = var->yres;
 			}
+			}
 		} else {
-			outw = ovl->info.out_width;
-			outh = ovl->info.out_height;
+			/*sv it comes here for vid1 on fb */
+			DBG("its vid pipeline so sclaing is enabled, still\
+				we will not scale for output size,\
+				just maintain the input size");
+			int rotation = (var->rotate + ofbi->rotation[i]) % 4;
+			if (rotation == FB_ROTATE_CW ||
+					rotation == FB_ROTATE_CCW) {
+				outw = var->yres;
+				outh = var->xres;
+			} else {
+				DBG("info.out_width = %d, info.out_height = %d\
+					take care of this for vid pipeline",
+					ovl->info.out_width,
+					ovl->info.out_height);
+				/*svoutw = ovl->info.out_width;
+				outh = ovl->info.out_height;*/
+				outw = var->xres;
+				outh = var->yres;
+			}
 		}
 
 		if (init) {
@@ -1038,7 +1082,8 @@ static int omapfb_pan_display(struct fb_var_screeninfo *var,
 		struct fb_info *fbi)
 {
 	struct fb_var_screeninfo new_var;
-	int r;
+	int r = 0;
+	struct omap_dss_device *display = fb2display(fbi);
 
 	DBG("pan_display(%d)\n", FB2OFB(fbi)->id);
 
@@ -1053,6 +1098,9 @@ static int omapfb_pan_display(struct fb_var_screeninfo *var,
 	fbi->var = new_var;
 
 	r = omapfb_apply_changes(fbi, 0);
+	/* don't call panel update for OMAP4 */
+	if (!cpu_is_omap44xx() && display && display->driver->update)
+		display->driver->update(display, 0, 0, var->xres, var->yres);
 
 	return r;
 }
@@ -1101,7 +1149,24 @@ static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
 
 	DBG("user mmap region start %lx, len %d, off %lx\n", start, len, off);
 
-	vma->vm_pgoff = off >> PAGE_SHIFT;
+	vma->vm_private_data = ofbi;
+	if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+		int k = 0, p = fix->line_length;
+
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+		vma->vm_ops = &mmap_user_ops; /* &dmm_remap_vm_ops; */
+
+		/* we need to figure out the height of the block. */
+		for (k = 0; k < len; k += p) {
+			/* map each page of the line */
+			vma->vm_pgoff = off >> PAGE_SHIFT;
+			if (remap_pfn_range(vma, vma->vm_start + k,
+				off >> PAGE_SHIFT, p, vma->vm_page_prot))
+				return -EAGAIN;
+			off += 2*64*TILER_WIDTH;
+		}
+	} else {
+		vma->vm_pgoff = off >> PAGE_SHIFT;
 	vma->vm_flags |= VM_IO | VM_RESERVED;
 	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 	vma->vm_ops = &mmap_user_ops;
@@ -1109,6 +1174,7 @@ static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
 	if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
 			     vma->vm_end - vma->vm_start, vma->vm_page_prot))
 		return -EAGAIN;
+	}
 	/* vm_ops.open won't be called for mmap itself. */
 	atomic_inc(&ofbi->map_count);
 	return 0;
@@ -1302,9 +1368,13 @@ static void omapfb_free_fbmem(struct fb_info *fbi)
 
 	rg = &ofbi->region;
 
+	if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+		tiler_free(rg->paddr);
+	} else {
 	if (rg->paddr)
 		if (omap_vram_free(rg->paddr, rg->size))
 			dev_err(fbdev->dev, "VRAM FREE failed\n");
+	}
 
 	if (rg->vaddr)
 		iounmap(rg->vaddr);
@@ -1354,6 +1424,9 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
 	struct omapfb2_mem_region *rg;
 	void __iomem *vaddr;
 	int r;
+	u16 h = 0, w = 0;
+	unsigned long pstride;
+	size_t psize;
 
 	rg = &ofbi->region;
 	memset(rg, 0, sizeof(*rg));
@@ -1362,7 +1435,19 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
 
 	if (!paddr) {
 		DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
+		if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+			int err = 0xFFFFFFFF;
+			/* get width & height from line length & size */
+			w = fbi->fix.line_length /
+				(fbi->var.bits_per_pixel >> 3);
+			h = size / fbi->fix.line_length;
+			err = tiler_alloc(TILFMT_32BIT, w, h, &paddr);
+			if (err != 0x0)
+				return -ENOMEM;
+			r = 0;
+		} else {
 		r = omap_vram_alloc(OMAP_VRAM_MEMTYPE_SDRAM, size, &paddr);
+		}
 	} else {
 		DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr,
 				ofbi->id);
@@ -1374,7 +1459,7 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
 		return -ENOMEM;
 	}
 
-	if (ofbi->rotation_type != OMAP_DSS_ROT_VRFB) {
+	if (ofbi->rotation_type ==  OMAP_DSS_ROT_DMA) {
 		vaddr = ioremap_wc(paddr, size);
 
 		if (!vaddr) {
@@ -1382,9 +1467,17 @@ static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
 			omap_vram_free(paddr, size);
 			return -ENOMEM;
 		}
+	} else if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+		pstride = tiler_stride(tiler_get_natural_addr(paddr));
+		psize = h * pstride;
+		vaddr = __arm_multi_strided_ioremap(1, &paddr, &psize,
+			&pstride, (unsigned long *) &fbi->fix.line_length,
+			MT_DEVICE_WC);
+		if (vaddr == NULL)
+			return -ENOMEM;
 
 		DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr);
-	} else {
+	} else if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
 		r = omap_vrfb_request_ctx(&rg->vrfb);
 		if (r) {
 			dev_err(fbdev->dev, "vrfb create ctx failed\n");
@@ -1428,6 +1521,10 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
 		break;
 	}
 
+	if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+		fbi->var.bits_per_pixel = 32;  /* always 32-bit for tiler */
+		bytespp = fbi->var.bits_per_pixel >> 3;
+	}
 	if (!size) {
 		u16 w, h;
 
@@ -1439,9 +1536,13 @@ static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
 
 			DBG("adjusting fb mem size for VRFB, %u -> %lu\n",
 					w * h * bytespp, size);
-		} else {
-			size = w * h * bytespp;
+		} else if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+			/* round up width to tiler size */
+			w = ALIGN(w, PAGE_SIZE / bytespp);
+			fbi->fix.line_length = w * bytespp;
 		}
+			size = w * h * bytespp;
+
 	}
 
 	if (!size)
@@ -1595,9 +1696,9 @@ static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
 	}
 
 	for (i = 0; i < fbdev->num_fbs; i++) {
-		/* allocate memory automatically only for fb0, or if
+		/* allocate memory automatically only for fb0, fb1 and fb2 , or if
 		 * excplicitly defined with vram or plat data option */
-		if (i == 0 || vram_sizes[i] != 0) {
+		if (i == 0 || i == 1 || i == 2 || vram_sizes[i] != 0) {
 			r = omapfb_alloc_fbmem_display(fbdev->fbs[i],
 					vram_sizes[i], vram_paddrs[i]);
 
@@ -1748,9 +1849,12 @@ static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
 	if (display) {
 		u16 w, h;
 		int rotation = (var->rotate + ofbi->rotation[0]) % 4;
-
 		display->driver->get_resolution(display, &w, &h);
 
+		if (ofbi->rotation_type == OMAP_DSS_ROT_TILER) {
+				var->xres = w;
+				var->yres = h;
+		} else {
 		if (rotation == FB_ROTATE_CW ||
 				rotation == FB_ROTATE_CCW) {
 			var->xres = h;
@@ -1759,7 +1863,7 @@ static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
 			var->xres = w;
 			var->yres = h;
 		}
-
+		}
 		var->xres_virtual = var->xres;
 		var->yres_virtual = var->yres;
 
@@ -1872,8 +1976,14 @@ static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
 		ofbi->id = i;
 
 		/* assign these early, so that fb alloc can use them */
-		ofbi->rotation_type = def_vrfb ? OMAP_DSS_ROT_VRFB :
-			OMAP_DSS_ROT_DMA;
+		if (def_vrfb == 1)
+			ofbi->rotation_type = OMAP_DSS_ROT_VRFB;
+		else if (def_tiler == 1)
+			ofbi->rotation_type = OMAP_DSS_ROT_TILER;
+		else
+			ofbi->rotation_type = OMAP_DSS_ROT_DMA;
+
+
 		ofbi->mirror = def_mirror;
 
 		fbdev->num_fbs++;
@@ -2210,9 +2320,11 @@ static int omapfb_probe(struct platform_device *pdev)
 			if (dssdrv->set_update_mode)
 				dssdrv->set_update_mode(def_display,
 						OMAP_DSS_UPDATE_MANUAL);
-
-			dssdrv->get_resolution(def_display, &w, &h);
-			def_display->driver->update(def_display, 0, 0, w, h);
+			/* don't call panel update for OMAP4 */
+			if (!cpu_is_omap44xx()) {
+				dssdrv->get_resolution(def_display, &w, &h);
+				def_display->driver->update(def_display, 0, 0, w, h);
+			}
 		} else {
 			if (dssdrv->set_update_mode)
 				dssdrv->set_update_mode(def_display,
@@ -2273,6 +2385,7 @@ module_param_named(mode, def_mode, charp, 0);
 module_param_named(vram, def_vram, charp, 0);
 module_param_named(rotate, def_rotate, int, 0);
 module_param_named(vrfb, def_vrfb, bool, 0);
+module_param_named(tiler, def_tiler, bool, 0);
 module_param_named(mirror, def_mirror, bool, 0);
 
 /* late_initcall to let panel/ctrl drivers loaded first.
diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
index 62bb88f5c192..5179219128bd 100644
--- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
@@ -57,7 +57,8 @@ static ssize_t store_rotate_type(struct device *dev,
 	if (rot_type != OMAP_DSS_ROT_DMA && rot_type != OMAP_DSS_ROT_VRFB)
 		return -EINVAL;
 
-	lock_fb_info(fbi);
+	if (!lock_fb_info(fbi))
+		return -ENODEV;
 
 	r = 0;
 	if (rot_type == ofbi->rotation_type)
@@ -105,7 +106,8 @@ static ssize_t store_mirror(struct device *dev,
 	if (mirror != 0 && mirror != 1)
 		return -EINVAL;
 
-	lock_fb_info(fbi);
+	if (!lock_fb_info(fbi))
+		return -ENODEV;
 
 	ofbi->mirror = mirror;
 
@@ -137,8 +139,9 @@ static ssize_t show_overlays(struct device *dev,
 	ssize_t l = 0;
 	int t;
 
+	if (!lock_fb_info(fbi))
+		return -ENODEV;
 	omapfb_lock(fbdev);
-	lock_fb_info(fbi);
 
 	for (t = 0; t < ofbi->num_overlays; t++) {
 		struct omap_overlay *ovl = ofbi->overlays[t];
@@ -154,8 +157,8 @@ static ssize_t show_overlays(struct device *dev,
 
 	l += snprintf(buf + l, PAGE_SIZE - l, "\n");
 
-	unlock_fb_info(fbi);
 	omapfb_unlock(fbdev);
+	unlock_fb_info(fbi);
 
 	return l;
 }
@@ -195,8 +198,9 @@ static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
 	if (buf[len - 1] == '\n')
 		len = len - 1;
 
+	if (!lock_fb_info(fbi))
+		return -ENODEV;
 	omapfb_lock(fbdev);
-	lock_fb_info(fbi);
 
 	if (len > 0) {
 		char *p = (char *)buf;
@@ -303,8 +307,8 @@ static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
 
 	r = count;
 out:
-	unlock_fb_info(fbi);
 	omapfb_unlock(fbdev);
+	unlock_fb_info(fbi);
 
 	return r;
 }
@@ -317,7 +321,8 @@ static ssize_t show_overlays_rotate(struct device *dev,
 	ssize_t l = 0;
 	int t;
 
-	lock_fb_info(fbi);
+	if (!lock_fb_info(fbi))
+		return -ENODEV;
 
 	for (t = 0; t < ofbi->num_overlays; t++) {
 		l += snprintf(buf + l, PAGE_SIZE - l, "%s%d",
@@ -345,7 +350,8 @@ static ssize_t store_overlays_rotate(struct device *dev,
 	if (buf[len - 1] == '\n')
 		len = len - 1;
 
-	lock_fb_info(fbi);
+	if (!lock_fb_info(fbi))
+		return -ENODEV;
 
 	if (len > 0) {
 		char *p = (char *)buf;
@@ -416,7 +422,8 @@ static ssize_t store_size(struct device *dev, struct device_attribute *attr,
 
 	size = PAGE_ALIGN(simple_strtoul(buf, NULL, 0));
 
-	lock_fb_info(fbi);
+	if (!lock_fb_info(fbi))
+		return -ENODEV;
 
 	for (i = 0; i < ofbi->num_overlays; i++) {
 		if (ofbi->overlays[i]->info.enabled) {
diff --git a/include/asm-generic/int-ll64.h b/include/asm-generic/int-ll64.h
index f394147c0739..0d806774a6ec 100644
--- a/include/asm-generic/int-ll64.h
+++ b/include/asm-generic/int-ll64.h
@@ -8,7 +8,7 @@
 #ifndef _ASM_GENERIC_INT_LL64_H
 #define _ASM_GENERIC_INT_LL64_H
 
-#include <asm/bitsperlong.h>
+#include <asm-generic/bitsperlong.h>
 
 #ifndef __ASSEMBLY__
 /*
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 2685915b6268..b93f38e8a0dc 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -616,9 +616,14 @@ struct twl4030_codec_data {
 	struct twl4030_codec_audio_data		*audio;
 	struct twl4030_codec_vibra_data		*vibra;
 
-	/* twl6030 */
-	int audpwron_gpio;      /* audio power-on gpio */
-	int naudint_irq;        /* audio interrupt */
+	/* twl6040 */
+	int audpwron_gpio;	/* audio power-on gpio */
+	int naudint_irq;	/* audio interrupt */
+
+	/* aess */
+	int (*device_enable) (struct platform_device *pdev);
+	int (*device_shutdown) (struct platform_device *pdev);
+	int (*device_idle) (struct platform_device *pdev);
 };
 
 struct twl4030_platform_data {
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 43eaf5ca5848..9f416867b459 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -208,6 +208,17 @@ struct mmc_host {
 
 	struct dentry		*debugfs_root;
 
+#ifdef CONFIG_TIWLAN_SDIO
+	struct {
+		struct sdio_cis         *cis;
+		struct sdio_embedded_func   *funcs;
+		unsigned int quirks;    /* embedded sdio card quirks */
+#define MMC_QUIRK_VDD_165_195  (1<<0)  /* do not ignore MMC_VDD_165_195 */
+#define MMC_QUIRK_LENIENT_FUNC0  (1<<1)
+	/* allow SDIO FN0 writes outside of VS CCCR */
+	} embedded_sdio_data;
+#endif
+
 	unsigned long		private[0] ____cacheline_aligned;
 };
 
@@ -216,6 +227,13 @@ extern int mmc_add_host(struct mmc_host *);
 extern void mmc_remove_host(struct mmc_host *);
 extern void mmc_free_host(struct mmc_host *);
 
+#ifdef CONFIG_TIWLAN_SDIO
+extern void mmc_set_embedded_sdio_data(struct mmc_host *host,
+       struct sdio_cis *cis,
+       struct sdio_embedded_func *funcs,
+	unsigned int quirks);
+#endif
+
 static inline void *mmc_priv(struct mmc_host *host)
 {
 	return (void *)host->private;
diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h
index c6c0cceba5fe..d522c8624778 100644
--- a/include/linux/mmc/sdio_func.h
+++ b/include/linux/mmc/sdio_func.h
@@ -22,6 +22,16 @@ struct sdio_func;
 
 typedef void (sdio_irq_handler_t)(struct sdio_func *);
 
+#ifdef CONFIG_TIWLAN_SDIO
+/*
+ * Structure used to hold embedded SDIO device data from platform layer
+ */
+struct sdio_embedded_func {
+    uint8_t f_class;
+    uint32_t f_maxblksize;
+};
+#endif
+
 /*
  * SDIO function CIS tuple (unknown to the core)
  */
diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h
index 33b2ea09a4ad..770f311fcdb9 100644
--- a/include/linux/mmc/sdio_ids.h
+++ b/include/linux/mmc/sdio_ids.h
@@ -35,6 +35,11 @@
 #define SDIO_DEVICE_ID_MARVELL_8688WLAN		0x9104
 #define SDIO_DEVICE_ID_MARVELL_8688BT		0x9105
 
+#ifdef CONFIG_TIWLAN_SDIO
+#define SDIO_VENDOR_ID_TI              0x104c
+#define SDIO_DEVICE_ID_TI_WL12xx       0x9066
+#endif
+
 #define SDIO_VENDOR_ID_SIANO			0x039a
 #define SDIO_DEVICE_ID_SIANO_NOVA_B0		0x0201
 #define SDIO_DEVICE_ID_SIANO_NICE		0x0202
diff --git a/include/linux/tty.h b/include/linux/tty.h
index 4409967db0c4..44be1fa99b2f 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -23,7 +23,7 @@
  */
 #define NR_UNIX98_PTY_DEFAULT	4096      /* Default maximum for Unix98 ptys */
 #define NR_UNIX98_PTY_MAX	(1 << MINORBITS) /* Absolute limit */
-#define NR_LDISCS		20
+#define NR_LDISCS		21
 
 /* line disciplines */
 #define N_TTY		0
@@ -48,6 +48,7 @@
 #define N_PPS		18	/* Pulse per Second */
 
 #define N_V253		19	/* Codec control over voice modem */
+#define N_SHARED	20	/* for TI connectivity chip */
 
 /*
  * This character is the same as _POSIX_VDISABLE: it cannot be used as
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 3793d168b44d..ab140f755206 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -928,6 +928,41 @@ struct v4l2_ext_controls {
 	__u32 reserved[2];
 	struct v4l2_ext_control *controls;
 };
+/* Write back device for OMAP4 */
+enum v4l2_writeback_source {
+	V4L2_WB_LCD_1_MANAGER		= 0,
+	V4L2_WB_LCD_2_MANAGER		= 1,
+	V4L2_WB_TV_MANAGER			= 2,
+	V4L2_WB_OVERLAY0			= 3,
+	V4L2_WB_OVERLAY1			= 4,
+	V4L2_WB_OVERLAY2			= 5,
+	V4L2_WB_OVERLAY3			= 6
+};
+
+enum v4l2_writeback_source_type {
+	V4L2_WB_SOURCE_OVERLAY	= 0,
+	V4L2_WB_SOURCE_MANAGER	= 1
+};
+
+enum v4l2_writeback_capturemode {
+	V4L2_WB_CAPTURE_ALL = 0x0,
+	V4L2_WB_CAPTURE_1 = 0x1,
+	V4L2_WB_CAPTURE_1_OF_2 = 0x2,
+	V4L2_WB_CAPTURE_1_OF_3 = 0x3,
+	V4L2_WB_CAPTURE_1_OF_4 = 0x4,
+	V4L2_WB_CAPTURE_1_OF_5 = 0x5,
+	V4L2_WB_CAPTURE_1_OF_6 = 0x6,
+	V4L2_WB_CAPTURE_1_OF_7 = 0x7
+};
+
+struct v4l2_writeback_ioctl_data {
+    int								enabled;
+    int								info_dirty;
+    enum v4l2_writeback_source			source;
+    enum v4l2_writeback_source_type		source_type;
+    struct v4l2_pix_format				pix;
+    enum v4l2_writeback_capturemode		capturemode;
+};
 
 /*  Values for ctrl_class field */
 #define V4L2_CTRL_CLASS_USER 0x00980000	/* Old-style 'user' controls */
@@ -1029,8 +1064,9 @@ enum v4l2_colorfx {
 
 #define V4L2_CID_ROTATE				(V4L2_CID_BASE+34)
 #define V4L2_CID_BG_COLOR			(V4L2_CID_BASE+35)
+#define V4L2_CID_WB					(V4L2_CID_BASE+36)
 /* last CID + 1 */
-#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+36)
+#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+37)
 
 /*  MPEG-class control IDs defined by V4L2 */
 #define V4L2_CID_MPEG_BASE 			(V4L2_CTRL_CLASS_MPEG | 0x900)
@@ -1756,6 +1792,10 @@ struct v4l2_dbg_chip_ident {
 #define VIDIOC_CROPCAP_OLD     	 _IOR('V', 58, struct v4l2_cropcap)
 #endif
 
+/* ioctls for Writeback Pipeline */
+#define VIDIOC_CUSTOM_G_WB     _IOWR('V', 255, struct v4l2_writeback_ioctl_data)
+#define VIDIOC_CUSTOM_S_WB     _IOW('V', 254, struct v4l2_writeback_ioctl_data)
+
 #define BASE_VIDIOC_PRIVATE	192		/* 192-255 are private */
 
 #endif /* __LINUX_VIDEODEV2_H */
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 1743d565e996..eb1d7b3e49a2 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -34,6 +34,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_TPA6130A2 if I2C
 	select SND_SOC_TLV320DAC33 if I2C
 	select SND_SOC_TWL4030 if TWL4030_CORE
+	select SND_SOC_ABE_TWL6040 if TWL4030_CORE
 	select SND_SOC_UDA134X
 	select SND_SOC_UDA1380 if I2C
 	select SND_SOC_WM2000 if I2C
@@ -164,6 +165,9 @@ config SND_SOC_TWL4030
 	select TWL4030_CODEC
 	tristate
 
+config SND_SOC_ABE_TWL6040
+	tristate
+
 config SND_SOC_UDA134X
        tristate
 
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index dd5ce6df6292..c1491b769d4a 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -21,6 +21,7 @@ snd-soc-tlv320aic26-objs := tlv320aic26.o
 snd-soc-tlv320aic3x-objs := tlv320aic3x.o
 snd-soc-tlv320dac33-objs := tlv320dac33.o
 snd-soc-twl4030-objs := twl4030.o
+snd-soc-abe-twl6040-objs := abe-twl6040.o
 snd-soc-uda134x-objs := uda134x.o
 snd-soc-uda1380-objs := uda1380.o
 snd-soc-wm8350-objs := wm8350.o
@@ -83,6 +84,7 @@ obj-$(CONFIG_SND_SOC_TLV320AIC26)	+= snd-soc-tlv320aic26.o
 obj-$(CONFIG_SND_SOC_TLV320AIC3X)	+= snd-soc-tlv320aic3x.o
 obj-$(CONFIG_SND_SOC_TLV320DAC33)	+= snd-soc-tlv320dac33.o
 obj-$(CONFIG_SND_SOC_TWL4030)	+= snd-soc-twl4030.o
+obj-$(CONFIG_SND_SOC_ABE_TWL6040)	+= snd-soc-abe-twl6040.o abe/
 obj-$(CONFIG_SND_SOC_UDA134X)	+= snd-soc-uda134x.o
 obj-$(CONFIG_SND_SOC_UDA1380)	+= snd-soc-uda1380.o
 obj-$(CONFIG_SND_SOC_WM8350)	+= snd-soc-wm8350.o
diff --git a/sound/soc/codecs/abe-twl6040.c b/sound/soc/codecs/abe-twl6040.c
new file mode 100644
index 000000000000..65027d43c9c4
--- /dev/null
+++ b/sound/soc/codecs/abe-twl6040.c
@@ -0,0 +1,2130 @@
+/*
+ * ALSA SoC ABE-TWL6040 codec driver
+ *
+ * Author:	 Misael Lopez Cruz <x0052729@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/i2c/twl.h>
+#include <linux/clk.h>
+#include <linux/pm_runtime.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "twl6040.h"
+#include "abe-twl6040.h"
+#include "abe/abe_main.h"
+
+#define ABE_FORMATS	 (SNDRV_PCM_FMTBIT_S32_LE)
+
+struct twl6040_jack_data {
+	struct snd_soc_jack *jack;
+	int report;
+};
+
+/* codec private data */
+struct twl6040_data {
+	struct snd_soc_codec codec;
+	int audpwron;
+	int naudint;
+	struct twl6040_jack_data hs_jack;
+	int codec_powered;
+	int pll;
+	int non_lp;
+	unsigned int sysclk;
+	struct snd_pcm_hw_constraint_list *sysclk_constraints;
+	struct completion ready;
+	int configure;
+	int mcpdm_dl_enable;
+	int mcpdm_ul_enable;
+	struct clk *clk;
+};
+
+/*
+ * twl6040 register cache & default register settings
+ */
+static const u8 twl6040_reg[TWL6040_CACHEREGNUM] = {
+	0x00, /* not used		0x00	*/
+	0x4B, /* TWL6040_ASICID (ro)	0x01	*/
+	0x00, /* TWL6040_ASICREV (ro)	0x02	*/
+	0x00, /* TWL6040_INTID		0x03	*/
+	0x00, /* TWL6040_INTMR		0x04	*/
+	0x00, /* TWL6040_NCPCTRL	0x05	*/
+	0x00, /* TWL6040_LDOCTL		0x06	*/
+	0x60, /* TWL6040_HPPLLCTL	0x07	*/
+	0x00, /* TWL6040_LPPLLCTL	0x08	*/
+	0x4A, /* TWL6040_LPPLLDIV	0x09	*/
+	0x00, /* TWL6040_AMICBCTL	0x0A	*/
+	0x00, /* TWL6040_DMICBCTL	0x0B	*/
+	0x18, /* TWL6040_MICLCTL	0x0C	- No input selected on Left Mic */
+	0x18, /* TWL6040_MICRCTL	0x0D	- No input selected on Right Mic */
+	0x00, /* TWL6040_MICGAIN	0x0E	*/
+	0x1B, /* TWL6040_LINEGAIN	0x0F	*/
+	0x00, /* TWL6040_HSLCTL		0x10	*/
+	0x00, /* TWL6040_HSRCTL		0x11	*/
+	0xFF, /* TWL6040_HSGAIN		0x12	*/
+	0x1E, /* TWL6040_EARCTL		0x13	*/
+	0x00, /* TWL6040_HFLCTL		0x14	*/
+	0x1D, /* TWL6040_HFLGAIN	0x15	*/
+	0x00, /* TWL6040_HFRCTL		0x16	*/
+	0x1D, /* TWL6040_HFRGAIN	0x17	*/
+	0x00, /* TWL6040_VIBCTLL	0x18	*/
+	0x00, /* TWL6040_VIBDATL	0x19	*/
+	0x00, /* TWL6040_VIBCTLR	0x1A	*/
+	0x00, /* TWL6040_VIBDATR	0x1B	*/
+	0x00, /* TWL6040_HKCTL1		0x1C	*/
+	0x00, /* TWL6040_HKCTL2		0x1D	*/
+	0x02, /* TWL6040_GPOCTL		0x1E	*/
+	0x00, /* TWL6040_ALB		0x1F	*/
+	0x00, /* TWL6040_DLB		0x20	*/
+	0x00, /* not used		0x21	*/
+	0x00, /* not used		0x22	*/
+	0x00, /* not used		0x23	*/
+	0x00, /* not used		0x24	*/
+	0x00, /* not used		0x25	*/
+	0x00, /* not used		0x26	*/
+	0x00, /* not used		0x27	*/
+	0x00, /* TWL6040_TRIM1		0x28	*/
+	0x00, /* TWL6040_TRIM2		0x29	*/
+	0x00, /* TWL6040_TRIM3		0x2A	*/
+	0x00, /* TWL6040_HSOTRIM	0x2B	*/
+	0x00, /* TWL6040_HFOTRIM	0x2C	*/
+	0x09, /* TWL6040_ACCCTL		0x2D	*/
+	0x00, /* TWL6040_STATUS (ro)	0x2E	*/
+	0x00, /* TWL6040_SHADOW		0x2F	*/
+};
+
+/*
+ * twl6040 vio/gnd registers:
+ * registers under vio/gnd supply can be accessed
+ * before the power-up sequence, after NRESPWRON goes high
+ */
+static const int twl6040_vio_reg[TWL6040_VIOREGNUM] = {
+	TWL6040_REG_ASICID,
+	TWL6040_REG_ASICREV,
+	TWL6040_REG_INTID,
+	TWL6040_REG_INTMR,
+	TWL6040_REG_NCPCTL,
+	TWL6040_REG_LDOCTL,
+	TWL6040_REG_AMICBCTL,
+	TWL6040_REG_DMICBCTL,
+	TWL6040_REG_HKCTL1,
+	TWL6040_REG_HKCTL2,
+	TWL6040_REG_GPOCTL,
+	TWL6040_REG_TRIM1,
+	TWL6040_REG_TRIM2,
+	TWL6040_REG_TRIM3,
+	TWL6040_REG_HSOTRIM,
+	TWL6040_REG_HFOTRIM,
+	TWL6040_REG_ACCCTL,
+	TWL6040_REG_STATUS,
+};
+
+/*
+ * twl6040 vdd/vss registers:
+ * registers under vdd/vss supplies can only be accessed
+ * after the power-up sequence
+ */
+static const int twl6040_vdd_reg[TWL6040_VDDREGNUM] = {
+	TWL6040_REG_HPPLLCTL,
+	TWL6040_REG_LPPLLCTL,
+	TWL6040_REG_LPPLLDIV,
+	TWL6040_REG_MICLCTL,
+	TWL6040_REG_MICRCTL,
+	TWL6040_REG_MICGAIN,
+	TWL6040_REG_LINEGAIN,
+	TWL6040_REG_HSLCTL,
+	TWL6040_REG_HSRCTL,
+	TWL6040_REG_HSGAIN,
+	TWL6040_REG_EARCTL,
+	TWL6040_REG_HFLCTL,
+	TWL6040_REG_HFLGAIN,
+	TWL6040_REG_HFRCTL,
+	TWL6040_REG_HFRGAIN,
+	TWL6040_REG_VIBCTLL,
+	TWL6040_REG_VIBDATL,
+	TWL6040_REG_VIBCTLR,
+	TWL6040_REG_VIBDATR,
+	TWL6040_REG_ALB,
+	TWL6040_REG_DLB,
+};
+
+/*
+ * read twl6040 register cache
+ */
+static inline unsigned int twl6040_read_reg_cache(struct snd_soc_codec *codec,
+						unsigned int reg)
+{
+	u8 *cache = codec->reg_cache;
+
+	if (reg >= TWL6040_CACHEREGNUM)
+		return -EIO;
+
+	return cache[reg];
+}
+
+/*
+ * write twl6040 register cache
+ */
+static inline void twl6040_write_reg_cache(struct snd_soc_codec *codec,
+						u8 reg, u8 value)
+{
+	u8 *cache = codec->reg_cache;
+
+	if (reg >= TWL6040_CACHEREGNUM)
+		return;
+	cache[reg] = value;
+}
+
+/*
+ * read from twl6040 hardware register
+ */
+static int twl6040_read_reg_volatile(struct snd_soc_codec *codec,
+			unsigned int reg)
+{
+	u8 value;
+
+	if (reg >= TWL6040_CACHEREGNUM)
+		return -EIO;
+
+	if (likely(reg < TWL6040_REG_SHADOW)) {
+		twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &value, reg);
+		twl6040_write_reg_cache(codec, reg, value);
+		return value;
+	} else {
+		return twl6040_read_reg_cache(codec, reg);
+	}
+}
+
+/*
+ * write to the twl6040 register space
+ */
+static int twl6040_write(struct snd_soc_codec *codec,
+			unsigned int reg, unsigned int value)
+{
+	if (reg >= TWL6040_CACHEREGNUM)
+		return -EIO;
+
+	twl6040_write_reg_cache(codec, reg, value);
+	 if (likely(reg < TWL6040_REG_SHADOW))
+		return twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, value, reg);
+	else
+		return 0;
+}
+
+static void twl6040_init_vio_regs(struct snd_soc_codec *codec)
+{
+	u8 *cache = codec->reg_cache;
+	int reg, i;
+
+	/* allow registers to be accessed by i2c */
+	twl6040_write(codec, TWL6040_REG_ACCCTL, cache[TWL6040_REG_ACCCTL]);
+
+	for (i = 0; i < TWL6040_VIOREGNUM; i++) {
+		reg = twl6040_vio_reg[i];
+		/* skip read-only registers (ASICID, ASICREV, STATUS) */
+		switch (reg) {
+		case TWL6040_REG_ASICID:
+		case TWL6040_REG_ASICREV:
+		case TWL6040_REG_STATUS:
+			continue;
+		default:
+			break;
+		}
+		twl6040_write(codec, reg, cache[reg]);
+	}
+}
+
+static void twl6040_init_vdd_regs(struct snd_soc_codec *codec)
+{
+	u8 *cache = codec->reg_cache;
+	int reg, i;
+
+	for (i = 0; i < TWL6040_VDDREGNUM; i++) {
+		reg = twl6040_vdd_reg[i];
+		twl6040_write(codec, reg, cache[reg]);
+	}
+}
+
+static void abe_init_chip(struct snd_soc_codec *codec,
+			struct platform_device *pdev)
+{
+	struct twl4030_codec_data *pdata = codec->dev->platform_data;
+	abe_opp_t OPP = ABE_OPP100;
+	abe_equ_t dl2_eq;
+	const abe_int32 DL2_COEF [25] =	{
+		-7554223, 708210, -708206, 7554225,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 6802833, -682266, 731554
+	};
+	dl2_eq.equ_length = 25;
+
+	/* build the coefficient parameter for the equalizer api */
+	memcpy(dl2_eq.coef.type1, DL2_COEF, sizeof(DL2_COEF));
+
+	abe_init_mem();
+	/* aess_clk has to be enabled to access hal register.
+	 * Disabel the clk after it has been used.
+	 */
+	pm_runtime_get_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+	if (pdata->device_enable)
+		pdata->device_enable(pdev);
+#endif
+
+	abe_reset_hal();
+	abe_load_fw();
+	/* Config OPP 100 for now */
+	abe_set_opp_processing(OPP);
+	/* "tick" of the audio engine */
+	abe_write_event_generator(EVENT_TIMER);
+
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2);
+	abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES);
+
+	abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_TONES);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+	abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2);
+
+	abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER);
+	abe_write_mixer(MIXSDT, GAIN_M6dB, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER);
+
+	abe_write_mixer(MIXECHO, MUTE_GAIN, RAMP_0MS, GAIN_LEFT_OFFSET);
+	abe_write_mixer(MIXECHO, MUTE_GAIN, RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_TONES);
+	abe_write_mixer(MIXAUDUL, GAIN_M6dB, RAMP_0MS, MIX_AUDUL_INPUT_UPLINK);
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_MM_DL);
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_VX_DL);
+
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_TONES);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_VX_DL);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_MM_DL);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_VX_UL);
+
+	/* load the high-pass coefficient of IHF-Right */
+	abe_write_equalizer(EQ2L, &dl2_eq);
+	/* load the high-pass coefficient of IHF-Left */
+	abe_write_equalizer(EQ2R, &dl2_eq);
+
+	/* Vx in HS, MM in HF and Tones in HF */
+	twl6040_write(codec, TWL6040_REG_SHADOW, 0x92);
+
+	pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+	if (pdata->device_idle)
+		pdata->device_idle(pdev);
+#endif
+}
+
+/* twl6040 codec manual power-up sequence */
+static void twl6040_power_up(struct snd_soc_codec *codec)
+{
+	u8 ncpctl, ldoctl, lppllctl, accctl;
+
+	ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL);
+	ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL);
+	lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
+	accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL);
+
+	/* enable reference system */
+	ldoctl |= TWL6040_REFENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	msleep(10);
+	/* enable internal oscillator */
+	ldoctl |= TWL6040_OSCENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	udelay(10);
+	/* enable high-side ldo */
+	ldoctl |= TWL6040_HSLDOENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	udelay(244);
+	/* enable negative charge pump */
+	ncpctl |= TWL6040_NCPENA | TWL6040_NCPOPEN;
+	twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl);
+	udelay(488);
+	/* enable low-side ldo */
+	ldoctl |= TWL6040_LSLDOENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	udelay(244);
+	/* enable low-power pll */
+	lppllctl |= TWL6040_LPLLENA;
+	twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+	/* reset state machine */
+	accctl |= TWL6040_RESETSPLIT;
+	twl6040_write(codec, TWL6040_REG_ACCCTL, accctl);
+	mdelay(5);
+	accctl &= ~TWL6040_RESETSPLIT;
+	twl6040_write(codec, TWL6040_REG_ACCCTL, accctl);
+	/* disable internal oscillator */
+	ldoctl &= ~TWL6040_OSCENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+}
+
+/* twl6040 codec manual power-down sequence */
+static void twl6040_power_down(struct snd_soc_codec *codec)
+{
+	u8 ncpctl, ldoctl, lppllctl, accctl;
+
+	ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL);
+	ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL);
+	lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
+	accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL);
+
+	/* enable internal oscillator */
+	ldoctl |= TWL6040_OSCENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	udelay(10);
+	/* disable low-power pll */
+	lppllctl &= ~TWL6040_LPLLENA;
+	twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+	/* disable low-side ldo */
+	ldoctl &= ~TWL6040_LSLDOENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	udelay(244);
+	/* disable negative charge pump */
+	ncpctl &= ~(TWL6040_NCPENA | TWL6040_NCPOPEN);
+	twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl);
+	udelay(488);
+	/* disable high-side ldo */
+	ldoctl &= ~TWL6040_HSLDOENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	udelay(244);
+	/* disable internal oscillator */
+	ldoctl &= ~TWL6040_OSCENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	/* disable reference system */
+	ldoctl &= ~TWL6040_REFENA;
+	twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl);
+	msleep(10);
+}
+
+/* set headset dac and driver power mode */
+static int headset_power_mode(struct snd_soc_codec *codec, int high_perf)
+{
+	int hslctl, hsrctl;
+	int mask = TWL6040_HSDRVMODEL | TWL6040_HSDACMODEL;
+
+	hslctl = twl6040_read_reg_cache(codec, TWL6040_REG_HSLCTL);
+	hsrctl = twl6040_read_reg_cache(codec, TWL6040_REG_HSRCTL);
+
+	if (high_perf) {
+		hslctl &= ~mask;
+		hsrctl &= ~mask;
+	} else {
+		hslctl |= mask;
+		hsrctl |= mask;
+	}
+
+	twl6040_write(codec, TWL6040_REG_HSLCTL, hslctl);
+	twl6040_write(codec, TWL6040_REG_HSRCTL, hsrctl);
+
+	return 0;
+}
+
+static int twl6040_hs_power_event(struct snd_soc_dapm_widget *w,
+			struct snd_kcontrol *kcontrol, int event)
+{
+	msleep(1);
+	return 0;
+}
+
+static int twl6040_power_mode_event(struct snd_soc_dapm_widget *w,
+			struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_codec *codec = w->codec;
+	struct twl6040_data *priv = codec->private_data;
+
+	if (SND_SOC_DAPM_EVENT_ON(event))
+		priv->non_lp++;
+	else
+		priv->non_lp--;
+
+	msleep(1);
+
+	return 0;
+}
+
+/* audio interrupt handler */
+static irqreturn_t twl6040_naudint_handler(int irq, void *data)
+{
+	struct snd_soc_codec *codec = data;
+	struct twl6040_data *priv = codec->private_data;
+	struct twl6040_jack_data *jack = &priv->hs_jack;
+	int report = 0;
+	u8 intid;
+
+	twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID);
+
+	switch (intid) {
+	case TWL6040_THINT:
+		dev_alert(codec->dev, "die temp over-limit detection\n");
+		break;
+	case TWL6040_PLUGINT:
+		/* Debounce */
+		msleep(200);
+		report = jack->report;
+	case TWL6040_UNPLUGINT:
+		snd_soc_jack_report(jack->jack, report, jack->report);
+		break;
+	case TWL6040_HOOKINT:
+		break;
+	case TWL6040_HFINT:
+		dev_alert(codec->dev, "hf drivers over current detection\n");
+		break;
+	case TWL6040_VIBINT:
+		dev_alert(codec->dev, "vib drivers over current detection\n");
+		break;
+	case TWL6040_READYINT:
+		complete(&priv->ready);
+		break;
+	default:
+		dev_err(codec->dev, "unknown audio interrupt %d\n", intid);
+		break;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int snd_soc_put_dl1_mixer(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+	struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
+	unsigned int shift = mc->shift;
+	int mask;
+	int err;
+	unsigned short val;
+	char *name = kcontrol->id.name;
+
+	mask = 1 << shift;
+	val = (ucontrol->value.integer.value[0] << shift);
+
+	if (strcmp(name, "DL1 Mixer Tones") == 0) {
+		if (val)
+			abe_write_mixer(MIXDL1, GAIN_M6dB,
+					RAMP_0MS, MIX_DL1_INPUT_TONES);
+		else
+			abe_write_mixer(MIXDL1, MUTE_GAIN,
+					RAMP_0MS, MIX_DL1_INPUT_TONES);
+	} else if (strcmp(name, "DL1 Mixer Voice") == 0) {
+		if (val)
+			abe_write_mixer(MIXDL1, GAIN_M6dB,
+					RAMP_1MS, MIX_DL1_INPUT_VX_DL);
+		else
+			abe_write_mixer(MIXDL1, MUTE_GAIN,
+					RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+	} else if (strcmp(name, "DL1 Mixer Multimedia") == 0) {
+		if (val)
+			abe_write_mixer(MIXDL1, GAIN_M6dB,
+					RAMP_2MS, MIX_DL1_INPUT_MM_DL);
+		else
+			abe_write_mixer(MIXDL1, MUTE_GAIN,
+					RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+	} else if (strcmp(name, "DL1 Mixer Multimedia Uplink") == 0) {
+		if (val)
+			abe_write_mixer(MIXDL1, GAIN_M6dB,
+					RAMP_5MS, MIX_DL1_INPUT_MM_UL2);
+		else
+			abe_write_mixer(MIXDL1, MUTE_GAIN,
+					RAMP_0MS, MIX_DL1_INPUT_MM_UL2);
+	}
+
+	err = snd_soc_update_bits(widget->codec, TWL6040_REG_SHADOW, mask, val);
+
+	return err;
+}
+
+static int snd_soc_put_dl2_mixer(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+	struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
+	unsigned int shift = mc->shift;
+	int mask;
+	int err;
+	unsigned short val;
+	char *name = kcontrol->id.name;
+
+	mask = 1 << shift;
+	val = (ucontrol->value.integer.value[0] << shift);
+
+	if (strcmp(name, "DL2 Mixer Tones") == 0) {
+		if (val)
+			abe_write_mixer(MIXDL2, GAIN_M6dB,
+				RAMP_0MS, MIX_DL2_INPUT_TONES);
+		else
+			abe_write_mixer(MIXDL2, MUTE_GAIN,
+				RAMP_0MS, MIX_DL2_INPUT_TONES);
+	} else if (strcmp(name, "DL2 Mixer Voice") == 0) {
+		if (val)
+			abe_write_mixer(MIXDL2, GAIN_M6dB,
+				RAMP_1MS, MIX_DL2_INPUT_VX_DL);
+		else
+			abe_write_mixer(MIXDL2, MUTE_GAIN,
+				RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+	} else if (strcmp(name, "DL2 Mixer Multimedia") == 0) {
+		if (val)
+			abe_write_mixer(MIXDL2, GAIN_M6dB,
+				RAMP_2MS, MIX_DL2_INPUT_MM_DL);
+		else
+			abe_write_mixer(MIXDL2, MUTE_GAIN,
+				RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+	} else if (strcmp(name, "DL2 Mixer Multimedia Uplink") == 0) {
+		if (val)
+			abe_write_mixer(MIXDL2, GAIN_M6dB,
+				RAMP_5MS, MIX_DL2_INPUT_MM_UL2);
+		else
+			abe_write_mixer(MIXDL2, MUTE_GAIN,
+				RAMP_0MS, MIX_DL2_INPUT_MM_UL2);
+	}
+
+	err = snd_soc_update_bits(widget->codec, TWL6040_REG_SHADOW, mask, val);
+
+	return err;
+}
+
+/*
+ * MICATT volume control:
+ * from -6 to 0 dB in 6 dB steps
+ */
+static DECLARE_TLV_DB_SCALE(mic_preamp_tlv, -600, 600, 0);
+
+/*
+ * MICGAIN volume control:
+ * from 6 to 30 dB in 6 dB steps
+ */
+static DECLARE_TLV_DB_SCALE(mic_amp_tlv, 600, 600, 0);
+
+/*
+ * AFMGAIN volume control:
+ * from 18 to 24 dB in 6 dB steps
+ */
+static DECLARE_TLV_DB_SCALE(afm_amp_tlv, 600, 600, 0);
+
+
+/*
+ * HSGAIN volume control:
+ * from -30 to 0 dB in 2 dB steps
+ */
+static DECLARE_TLV_DB_SCALE(hs_tlv, -3000, 200, 0);
+
+/*
+ * HFGAIN volume control:
+ * from -52 to 6 dB in 2 dB steps
+ */
+static DECLARE_TLV_DB_SCALE(hf_tlv, -5200, 200, 0);
+
+/*
+ * EPGAIN volume control:
+ * from -24 to 6 dB in 2 dB steps
+ */
+static DECLARE_TLV_DB_SCALE(ep_tlv, -2400, 200, 0);
+
+/* Left analog microphone selection */
+static const char *twl6040_amicl_texts[] =
+	{"Headset Mic", "Main Mic", "Aux/FM Left", "Off"};
+
+/* Right analog microphone selection */
+static const char *twl6040_amicr_texts[] =
+	{"Headset Mic", "Sub Mic", "Aux/FM Right", "Off"};
+
+static const char *twl6040_hs_texts[] =
+	{"Off", "HS DAC", "Line-In amp"};
+
+static const char *twl6040_hf_texts[] =
+	{"Off", "HF DAC", "Line-In amp"};
+
+static const struct soc_enum twl6040_enum[] = {
+	SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 4, twl6040_amicl_texts),
+	SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 4, twl6040_amicr_texts),
+	SOC_ENUM_SINGLE(TWL6040_REG_HSLCTL, 5, 3, twl6040_hs_texts),
+	SOC_ENUM_SINGLE(TWL6040_REG_HSRCTL, 5, 3, twl6040_hs_texts),
+	SOC_ENUM_SINGLE(TWL6040_REG_HFLCTL, 2, 3, twl6040_hf_texts),
+	SOC_ENUM_SINGLE(TWL6040_REG_HFRCTL, 2, 3, twl6040_hf_texts),
+};
+
+static const struct snd_kcontrol_new amicl_control =
+	SOC_DAPM_ENUM("Route", twl6040_enum[0]);
+
+static const struct snd_kcontrol_new amicr_control =
+	SOC_DAPM_ENUM("Route", twl6040_enum[1]);
+
+static const struct snd_kcontrol_new dl1_mixer_controls[] = {
+	SOC_SINGLE_EXT("Tones", TWL6040_REG_SHADOW, 0, 1, 0,
+		snd_soc_dapm_get_volsw, snd_soc_put_dl1_mixer),
+	SOC_SINGLE_EXT("Voice", TWL6040_REG_SHADOW, 1, 1, 0,
+		snd_soc_dapm_get_volsw, snd_soc_put_dl1_mixer),
+	SOC_SINGLE_EXT("Multimedia Uplink", TWL6040_REG_SHADOW, 2, 1, 0,
+		snd_soc_dapm_get_volsw, snd_soc_put_dl1_mixer),
+	SOC_SINGLE_EXT("Multimedia", TWL6040_REG_SHADOW, 3, 1, 0,
+		snd_soc_dapm_get_volsw, snd_soc_put_dl1_mixer),
+};
+
+static const struct snd_kcontrol_new dl2_mixer_controls[] = {
+	SOC_SINGLE_EXT("Tones", TWL6040_REG_SHADOW, 4, 1, 0,
+		snd_soc_dapm_get_volsw, snd_soc_put_dl2_mixer),
+	SOC_SINGLE_EXT("Voice", TWL6040_REG_SHADOW, 5, 1, 0,
+		snd_soc_dapm_get_volsw, snd_soc_put_dl2_mixer),
+	SOC_SINGLE_EXT("Multimedia Uplink", TWL6040_REG_SHADOW, 6, 1, 0,
+		snd_soc_dapm_get_volsw, snd_soc_put_dl2_mixer),
+	SOC_SINGLE_EXT("Multimedia", TWL6040_REG_SHADOW, 7, 1, 0,
+		snd_soc_dapm_get_volsw, snd_soc_put_dl2_mixer),
+};
+
+
+/* Headset DAC playback switches */
+static const struct snd_kcontrol_new hsl_mux_controls =
+	SOC_DAPM_ENUM("Route", twl6040_enum[2]);
+
+static const struct snd_kcontrol_new hsr_mux_controls =
+	SOC_DAPM_ENUM("Route", twl6040_enum[3]);
+
+/* Handsfree DAC playback switches */
+static const struct snd_kcontrol_new hfl_mux_controls =
+	SOC_DAPM_ENUM("Route", twl6040_enum[4]);
+
+static const struct snd_kcontrol_new hfr_mux_controls =
+	SOC_DAPM_ENUM("Route", twl6040_enum[5]);
+
+static const struct snd_kcontrol_new ep_driver_switch_controls =
+	SOC_DAPM_SINGLE("Switch", TWL6040_REG_EARCTL, 0, 1, 0);
+
+static const struct snd_kcontrol_new twl6040_snd_controls[] = {
+	/* Capture gains */
+	SOC_DOUBLE_TLV("Capture Preamplifier Volume",
+		TWL6040_REG_MICGAIN, 6, 7, 1, 1, mic_preamp_tlv),
+	SOC_DOUBLE_TLV("Capture Volume",
+		TWL6040_REG_MICGAIN, 0, 3, 4, 0, mic_amp_tlv),
+
+	/* AFM gains */
+	SOC_DOUBLE_TLV("Aux FM Volume",
+		TWL6040_REG_LINEGAIN, 0, 5, 0xF, 0, afm_amp_tlv),
+
+	/* Playback gains */
+	SOC_DOUBLE_TLV("Headset Playback Volume",
+		TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv),
+	SOC_DOUBLE_R_TLV("Handsfree Playback Volume",
+		TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv),
+	SOC_SINGLE_TLV("Earphone Playback Volume",
+		TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv),
+};
+
+static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = {
+	/* Inputs */
+	SND_SOC_DAPM_INPUT("MAINMIC"),
+	SND_SOC_DAPM_INPUT("HSMIC"),
+	SND_SOC_DAPM_INPUT("SUBMIC"),
+	SND_SOC_DAPM_INPUT("AFML"),
+	SND_SOC_DAPM_INPUT("AFMR"),
+
+	/* Outputs */
+	SND_SOC_DAPM_OUTPUT("HSOL"),
+	SND_SOC_DAPM_OUTPUT("HSOR"),
+	SND_SOC_DAPM_OUTPUT("HFL"),
+	SND_SOC_DAPM_OUTPUT("HFR"),
+	SND_SOC_DAPM_OUTPUT("EP"),
+
+	/* Analog input muxes for the capture amplifiers */
+	SND_SOC_DAPM_MUX("Analog Left Capture Route",
+			SND_SOC_NOPM, 0, 0, &amicl_control),
+	SND_SOC_DAPM_MUX("Analog Right Capture Route",
+			SND_SOC_NOPM, 0, 0, &amicr_control),
+
+	SND_SOC_DAPM_MIXER("DL1 Mixer",
+			SND_SOC_NOPM, 0, 0, dl1_mixer_controls,
+			ARRAY_SIZE(dl1_mixer_controls)),
+	SND_SOC_DAPM_MIXER("DL2 Mixer",
+			SND_SOC_NOPM, 0, 0, dl2_mixer_controls,
+			ARRAY_SIZE(dl2_mixer_controls)),
+
+	/* Analog capture PGAs */
+	SND_SOC_DAPM_PGA("MicAmpL",
+			TWL6040_REG_MICLCTL, 0, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("MicAmpR",
+			TWL6040_REG_MICRCTL, 0, 0, NULL, 0),
+
+	/* Auxiliary FM PGAs */
+	SND_SOC_DAPM_PGA("AFMAmpL",
+			TWL6040_REG_MICLCTL, 1, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("AFMAmpR",
+			TWL6040_REG_MICRCTL, 1, 0, NULL, 0),
+
+	/* ADCs */
+	SND_SOC_DAPM_ADC("ADC Left", "Left Front Capture",
+			TWL6040_REG_MICLCTL, 2, 0),
+	SND_SOC_DAPM_ADC("ADC Right", "Right Front Capture",
+			TWL6040_REG_MICRCTL, 2, 0),
+
+	/* Microphone bias */
+	SND_SOC_DAPM_MICBIAS("Headset Mic Bias",
+			TWL6040_REG_AMICBCTL, 0, 0),
+	SND_SOC_DAPM_MICBIAS("Main Mic Bias",
+			TWL6040_REG_AMICBCTL, 4, 0),
+	SND_SOC_DAPM_MICBIAS("Digital Mic1 Bias",
+			TWL6040_REG_DMICBCTL, 0, 0),
+	SND_SOC_DAPM_MICBIAS("Digital Mic2 Bias",
+			TWL6040_REG_DMICBCTL, 4, 0),
+
+	SND_SOC_DAPM_AIF_IN("AIFIN Tones", "Playback", 0,
+			SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_IN("AIFIN Voice", "Playback", 0,
+			SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_IN("AIFIN Multimedia Uplink", "Playback", 0,
+			SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_IN("AIFIN Multimedia", "Playback", 0,
+			SND_SOC_NOPM, 0, 0),
+
+	/* DACs */
+	SND_SOC_DAPM_DAC_E("HSDAC Left", "Headset Playback",
+			TWL6040_REG_HSLCTL, 0, 0,
+			twl6040_hs_power_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("HSDAC Right", "Headset Playback",
+			TWL6040_REG_HSRCTL, 0, 0,
+			twl6040_hs_power_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("HFDAC Left", "Handsfree Playback",
+			TWL6040_REG_HFLCTL, 0, 0,
+			twl6040_power_mode_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("HFDAC Right", "Handsfree Playback",
+			TWL6040_REG_HFRCTL, 0, 0,
+			twl6040_power_mode_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MUX("HF Left Playback",
+			SND_SOC_NOPM, 0, 0, &hfl_mux_controls),
+	SND_SOC_DAPM_MUX("HF Right Playback",
+			SND_SOC_NOPM, 0, 0, &hfr_mux_controls),
+	/* Analog playback Muxes */
+	SND_SOC_DAPM_MUX("HS Left Playback",
+			SND_SOC_NOPM, 0, 0, &hsl_mux_controls),
+	SND_SOC_DAPM_MUX("HS Right Playback",
+			SND_SOC_NOPM, 0, 0, &hsr_mux_controls),
+
+	/* Analog playback drivers */
+	SND_SOC_DAPM_PGA_E("Handsfree Left Driver",
+			TWL6040_REG_HFLCTL, 4, 0, NULL, 0,
+			twl6040_power_mode_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("Handsfree Right Driver",
+			TWL6040_REG_HFRCTL, 4, 0, NULL, 0,
+			twl6040_power_mode_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA("Headset Left Driver",
+			TWL6040_REG_HSLCTL, 2, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("Headset Right Driver",
+			TWL6040_REG_HSRCTL, 2, 0, NULL, 0),
+	SND_SOC_DAPM_SWITCH_E("Earphone Driver",
+			SND_SOC_NOPM, 0, 0, &ep_driver_switch_controls,
+			twl6040_power_mode_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+	/* Analog playback PGAs */
+	SND_SOC_DAPM_PGA("HFDAC Left PGA",
+			TWL6040_REG_HFLCTL, 1, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("HFDAC Right PGA",
+			TWL6040_REG_HFRCTL, 1, 0, NULL, 0),
+
+};
+
+static const struct snd_soc_dapm_route intercon[] = {
+	/* Capture path */
+	{"Analog Left Capture Route", "Headset Mic", "HSMIC"},
+	{"Analog Left Capture Route", "Main Mic", "MAINMIC"},
+	{"Analog Left Capture Route", "Aux/FM Left", "AFML"},
+
+	{"Analog Right Capture Route", "Headset Mic", "HSMIC"},
+	{"Analog Right Capture Route", "Sub Mic", "SUBMIC"},
+	{"Analog Right Capture Route", "Aux/FM Right", "AFMR"},
+
+	{"MicAmpL", NULL, "Analog Left Capture Route"},
+	{"MicAmpR", NULL, "Analog Right Capture Route"},
+
+	{"ADC Left", NULL, "MicAmpL"},
+	{"ADC Right", NULL, "MicAmpR"},
+
+	/* AFM path */
+	{"AFMAmpL", "NULL", "AFML"},
+	{"AFMAmpR", "NULL", "AFMR"},
+
+	/* Headset playback path */
+	{"DL1 Mixer", "Tones", "AIFIN Tones"},
+	{"DL1 Mixer", "Voice", "AIFIN Voice"},
+	{"DL1 Mixer", "Multimedia Uplink", "AIFIN Multimedia Uplink"},
+	{"DL1 Mixer", "Multimedia", "AIFIN Multimedia"},
+
+	{"HSDAC Left", NULL, "DL1 Mixer"},
+	{"HSDAC Right", NULL, "DL1 Mixer"},
+
+	{"HS Left Playback", "HS DAC", "HSDAC Left"},
+	{"HS Left Playback", "Line-In amp", "AFMAmpL"},
+
+	{"HS Right Playback", "HS DAC", "HSDAC Right"},
+	{"HS Right Playback", "Line-In amp", "AFMAmpR"},
+
+	{"Headset Left Driver", "NULL", "HS Left Playback"},
+	{"Headset Right Driver", "NULL", "HS Right Playback"},
+
+	{"HSOL", NULL, "Headset Left Driver"},
+	{"HSOR", NULL, "Headset Right Driver"},
+
+	/* Earphone playback path */
+	{"Earphone Driver", "Switch", "HSDAC Left"},
+	{"EP", NULL, "Earphone Driver"},
+
+	/* Handsfree playback path */
+	{"DL2 Mixer", "Tones", "AIFIN Tones"},
+	{"DL2 Mixer", "Voice", "AIFIN Voice"},
+	{"DL2 Mixer", "Multimedia Uplink", "AIFIN Multimedia Uplink"},
+	{"DL2 Mixer", "Multimedia", "AIFIN Multimedia"},
+
+	{"HFDAC Left", NULL, "DL2 Mixer"},
+	{"HFDAC Right", NULL, "DL2 Mixer"},
+
+	{"HF Left Playback", "HF DAC", "HFDAC Left"},
+	{"HF Left Playback", "Line-In amp", "AFMAmpL"},
+
+	{"HF Right Playback", "HF DAC", "HFDAC Right"},
+	{"HF Right Playback", "Line-In amp", "AFMAmpR"},
+
+	{"HFDAC Left PGA", NULL, "HF Left Playback"},
+	{"HFDAC Right PGA", NULL, "HF Right Playback"},
+
+	{"Handsfree Left Driver", "Switch", "HFDAC Left PGA"},
+	{"Handsfree Right Driver", "Switch", "HFDAC Right PGA"},
+
+	{"HFL", NULL, "Handsfree Left Driver"},
+	{"HFR", NULL, "Handsfree Right Driver"},
+};
+
+static int abe_twl6040_add_widgets(struct snd_soc_codec *codec)
+{
+	snd_soc_dapm_new_controls(codec, twl6040_dapm_widgets,
+				 ARRAY_SIZE(twl6040_dapm_widgets));
+
+	snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+
+	snd_soc_dapm_new_widgets(codec);
+
+	return 0;
+}
+
+static int twl6040_power_up_completion(struct snd_soc_codec *codec,
+					int naudint)
+{
+	struct twl6040_data *priv = codec->private_data;
+	int time_left;
+	u8 intid;
+
+	time_left = wait_for_completion_timeout(&priv->ready,
+				msecs_to_jiffies(48));
+
+	if (!time_left) {
+		twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid,
+							TWL6040_REG_INTID);
+		if (!(intid & TWL6040_READYINT)) {
+			dev_err(codec->dev, "timeout waiting for READYINT\n");
+			return -ETIMEDOUT;
+		}
+	}
+
+	priv->codec_powered = 1;
+
+	return 0;
+}
+
+static int abe_twl6040_set_bias_level(struct snd_soc_codec *codec,
+				enum snd_soc_bias_level level)
+{
+	struct twl6040_data *priv = codec->private_data;
+	int audpwron = priv->audpwron;
+	int naudint = priv->naudint;
+	int ret;
+
+	switch (level) {
+	case SND_SOC_BIAS_ON:
+		break;
+	case SND_SOC_BIAS_PREPARE:
+		break;
+	case SND_SOC_BIAS_STANDBY:
+		if (priv->codec_powered)
+			break;
+
+		if (gpio_is_valid(audpwron)) {
+			/* use AUDPWRON line */
+			gpio_set_value(audpwron, 1);
+
+			/* wait for power-up completion */
+			ret = twl6040_power_up_completion(codec, naudint);
+			if (ret)
+				return ret;
+
+			/* sync registers updated during power-up sequence */
+			twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL);
+			twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL);
+			twl6040_read_reg_volatile(codec, TWL6040_REG_LPPLLCTL);
+		} else {
+			/* use manual power-up sequence */
+			twl6040_power_up(codec);
+			priv->codec_powered = 1;
+		}
+
+		/* initialize vdd/vss registers with reg_cache */
+		twl6040_init_vdd_regs(codec);
+		break;
+	case SND_SOC_BIAS_OFF:
+		if (!priv->codec_powered)
+			break;
+
+		if (gpio_is_valid(audpwron)) {
+			/* use AUDPWRON line */
+			gpio_set_value(audpwron, 0);
+
+			/* power-down sequence latency */
+			udelay(500);
+
+			/* sync registers updated during power-down sequence */
+			twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL);
+			twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL);
+			twl6040_write_reg_cache(codec, TWL6040_REG_LPPLLCTL,
+						0x00);
+		} else {
+			/* use manual power-down sequence */
+			twl6040_power_down(codec);
+		}
+
+		priv->codec_powered = 0;
+		break;
+	}
+
+	codec->bias_level = level;
+
+	return 0;
+}
+
+/* set of rates for each pll: low-power and high-performance */
+
+static unsigned int lp_rates[] = {
+	44100,
+	48000,
+};
+
+static struct snd_pcm_hw_constraint_list lp_constraints = {
+	.count	= ARRAY_SIZE(lp_rates),
+	.list	= lp_rates,
+};
+
+static unsigned int hp_rates[] = {
+	8000,
+	16000,
+	48000,
+};
+
+static struct snd_pcm_hw_constraint_list hp_constraints = {
+	.count	= ARRAY_SIZE(hp_rates),
+	.list	= hp_rates,
+};
+
+static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+		int clk_id, unsigned int freq, int dir)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct twl6040_data *priv = codec->private_data;
+	u8 hppllctl, lppllctl;
+
+	hppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_HPPLLCTL);
+	lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
+
+	switch (clk_id) {
+	case TWL6040_SYSCLK_SEL_LPPLL:
+		switch (freq) {
+		case 32768:
+			/* headset dac and driver must be in low-power mode */
+			headset_power_mode(codec, 0);
+
+			/* clk32k input requires low-power pll */
+			lppllctl |= TWL6040_LPLLENA;
+			twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+			mdelay(5);
+			lppllctl &= ~TWL6040_HPLLSEL;
+			twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+			hppllctl &= ~TWL6040_HPLLENA;
+			twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl);
+			break;
+		default:
+			dev_err(codec->dev, "unknown mclk freq %d\n", freq);
+			return -EINVAL;
+		}
+
+		/* lppll divider */
+		switch (priv->sysclk) {
+		case 17640000:
+			lppllctl |= TWL6040_LPLLFIN;
+			break;
+		case 19200000:
+			lppllctl &= ~TWL6040_LPLLFIN;
+			break;
+		default:
+			/* sysclk not yet configured */
+			lppllctl &= ~TWL6040_LPLLFIN;
+			priv->sysclk = 19200000;
+			break;
+		}
+
+		twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+
+		priv->pll = TWL6040_LPPLL_ID;
+		priv->sysclk_constraints = &lp_constraints;
+		break;
+	case TWL6040_SYSCLK_SEL_HPPLL:
+		hppllctl &= ~TWL6040_MCLK_MSK;
+
+		switch (freq) {
+		case 12000000:
+			/* mclk input, pll enabled */
+			hppllctl |= TWL6040_MCLK_12000KHZ |
+				    TWL6040_HPLLSQRBP |
+				    TWL6040_HPLLENA;
+			break;
+		case 19200000:
+			/* mclk input, pll disabled */
+			hppllctl |= TWL6040_MCLK_19200KHZ |
+				    TWL6040_HPLLSQRENA |
+				    TWL6040_HPLLBP;
+			break;
+		case 26000000:
+			/* mclk input, pll enabled */
+			hppllctl |= TWL6040_MCLK_26000KHZ |
+				    TWL6040_HPLLSQRBP |
+				    TWL6040_HPLLENA;
+			break;
+		case 38400000:
+			/* clk slicer, pll disabled */
+			hppllctl |= TWL6040_MCLK_38400KHZ |
+				    TWL6040_HPLLSQRENA |
+				    TWL6040_HPLLBP;
+			break;
+		default:
+			dev_err(codec->dev, "unknown mclk freq %d\n", freq);
+			return -EINVAL;
+		}
+
+		/* headset dac and driver must be in high-performance mode */
+		headset_power_mode(codec, 1);
+
+		twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl);
+		udelay(500);
+		lppllctl |= TWL6040_HPLLSEL;
+		twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+		lppllctl &= ~TWL6040_LPLLENA;
+		twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+
+		/* high-performance pll can provide only 19.2 MHz */
+		priv->pll = TWL6040_HPPLL_ID;
+		priv->sysclk = 19200000;
+		priv->sysclk_constraints = &hp_constraints;
+		break;
+	default:
+		dev_err(codec->dev, "unknown clk_id %d\n", clk_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int abe_mm_startup(struct snd_pcm_substream *substream,
+			struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	struct twl4030_codec_data *pdata = codec->dev->platform_data;
+	struct platform_device *pdev = to_platform_device(codec->dev);
+
+	if (!priv->sysclk) {
+		dev_err(codec->dev,
+			"no mclk configured, call set_sysclk() on init\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * capture is not supported at 17.64 MHz,
+	 * it's reserved for headset low-power playback scenario
+	 */
+	if ((priv->sysclk == 17640000) && substream->stream) {
+		dev_err(codec->dev,
+			"capture mode is not supported at %dHz\n",
+			priv->sysclk);
+		return -EINVAL;
+	}
+
+	snd_pcm_hw_constraint_list(substream->runtime, 0,
+				SNDRV_PCM_HW_PARAM_RATE,
+				priv->sysclk_constraints);
+
+	if (!priv->configure++) {
+		pm_runtime_get_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+		if (pdata->device_enable)
+			pdata->device_enable(pdev);
+#endif
+
+		abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC,
+			(abe_router_t *)abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]);
+
+		abe_write_gain(GAINS_DL1, GAIN_M6dB,  RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DL1, GAIN_M6dB,  RAMP_0MS, GAIN_RIGHT_OFFSET);
+		abe_write_gain(GAINS_DL2, GAIN_M6dB,  RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DL2, GAIN_M6dB,  RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+		abe_write_gain(GAINS_AMIC, GAIN_M6dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_AMIC, GAIN_M6dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+		abe_write_gain(GAINS_SPLIT, GAIN_M6dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_SPLIT, GAIN_M6dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+	}
+	return 0;
+}
+
+static int abe_mm_hw_params(struct snd_pcm_substream *substream,
+			struct snd_pcm_hw_params *params,
+			struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	u8 lppllctl;
+	int rate;
+	int channels;
+	unsigned int sysclk;
+	abe_data_format_t format;
+	abe_dma_t dma_sink;
+
+	lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
+
+	rate = params_rate(params);
+	switch (rate) {
+	case 44100:
+		lppllctl |= TWL6040_LPLLFIN;
+		sysclk = 17640000;
+		break;
+	case 48000:
+	/* Select output frequency 19.2 MHz */
+		lppllctl &= ~TWL6040_LPLLFIN;
+		sysclk = 19200000;
+		break;
+	default:
+		dev_err(codec->dev, "unsupported rate %d\n", rate);
+		return -EINVAL;
+	}
+
+	channels = params_channels(params);
+	switch (channels) {
+	case 1:
+		format.samp_format = MONO_MSB;
+		break;
+	case 2:
+		format.samp_format = STEREO_MSB;
+		break;
+	default:
+		dev_err(codec->dev, "%d channels not supported", channels);
+		return -EINVAL;
+	}
+
+	if (priv->pll == TWL6040_LPPLL_ID) {
+		priv->sysclk = sysclk;
+		twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+	}
+
+	format.f = rate;
+	if (!substream->stream) {
+		abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink);
+		abe_enable_data_transfer(MM_DL_PORT);
+		if (!priv->mcpdm_dl_enable++) {
+			abe_enable_data_transfer(PDM_DL_PORT);
+		}
+	} else {
+		abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink);
+		abe_enable_data_transfer(MM_UL2_PORT);
+		if (!priv->mcpdm_ul_enable++)
+			abe_enable_data_transfer(PDM_UL_PORT);
+	}
+
+	return 0;
+}
+
+static int abe_mm_trigger(struct snd_pcm_substream *substream,
+			int cmd, struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	unsigned int snd_reg_shadow;
+
+	snd_reg_shadow = twl6040_read_reg_cache(codec, TWL6040_REG_SHADOW);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+		/*
+		 * low-power playback mode is restricted
+		 * for headset path only
+		 */
+		if ((priv->sysclk == 17640000) && priv->non_lp) {
+			dev_err(codec->dev,
+				"some enabled paths aren't supported at %dHz\n",
+				priv->sysclk);
+			return -EPERM;
+		}
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (!substream->stream){
+			if ((snd_reg_shadow & 0x08) == 0x08)
+				abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+
+			if ((snd_reg_shadow & 0x80) == 0x80)
+				abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+		}
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (!substream->stream){
+			if ((snd_reg_shadow & 0x08) == 0x08)
+				abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+
+			if ((snd_reg_shadow & 0x80) == 0x80)
+				abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static void abe_mm_shutdown(struct snd_pcm_substream *substream,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	struct twl4030_codec_data *pdata = codec->dev->platform_data;
+	struct platform_device *pdev = to_platform_device(codec->dev);
+
+        if (!substream->stream) {
+                abe_disable_data_transfer(MM_DL_PORT);
+		if (!--priv->mcpdm_dl_enable) {
+	                abe_disable_data_transfer(PDM_DL_PORT);
+		}
+        } else {
+                abe_disable_data_transfer(MM_UL2_PORT);
+		if (!--priv->mcpdm_ul_enable)
+	                abe_disable_data_transfer(PDM_UL_PORT);
+        }
+
+	if (!--priv->configure) {
+		pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+		if (pdata->device_idle)
+			pdata->device_idle(pdev);
+#endif
+	}
+}
+
+static int twl6040_mute(struct snd_soc_dai *dai, int mute)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct twl6040_data *priv = codec->private_data;
+
+	int hs_gain, hf_gain;
+
+	hf_gain = twl6040_read_reg_cache(codec, TWL6040_REG_HFRGAIN);
+	hs_gain = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN);
+
+	if (mute) {
+		if (priv->mcpdm_dl_enable == 1) {
+			twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, 0x1D, TWL6040_REG_HFRGAIN);
+			twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, 0x1D, TWL6040_REG_HFLGAIN);
+			twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, 0xFF, TWL6040_REG_HSGAIN);
+		}
+	} else {
+		twl6040_write(codec, TWL6040_REG_HFRGAIN, hf_gain);
+		twl6040_write(codec, TWL6040_REG_HFLGAIN, hf_gain);
+		twl6040_write(codec, TWL6040_REG_HSGAIN, hs_gain);
+	}
+
+	return 0;
+}
+
+static struct snd_soc_dai_ops abe_mm_dai_ops = {
+	.startup	= abe_mm_startup,
+	.hw_params	= abe_mm_hw_params,
+	.digital_mute	= twl6040_mute,
+	.shutdown	= abe_mm_shutdown,
+	.trigger	= abe_mm_trigger,
+	.set_sysclk	= twl6040_set_dai_sysclk,
+};
+
+static int abe_tones_hw_params(struct snd_pcm_substream *substream,
+			struct snd_pcm_hw_params *params,
+			struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	u8 lppllctl;
+	int rate;
+	int channels;
+	unsigned int sysclk;
+	abe_data_format_t format;
+	abe_dma_t dma_sink;
+
+	lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
+
+	rate = params_rate(params);
+	switch (rate) {
+	case 44100:
+		lppllctl |= TWL6040_LPLLFIN;
+		sysclk = 17640000;
+		break;
+	case 48000:
+	/* Select output frequency 19.2 MHz */
+		lppllctl &= ~TWL6040_LPLLFIN;
+		sysclk = 19200000;
+		break;
+	default:
+		dev_err(codec->dev, "unsupported rate %d\n", rate);
+		return -EINVAL;
+	}
+
+	channels = params_channels(params);
+	switch (channels) {
+	case 1:
+		format.samp_format = MONO_MSB;
+		break;
+	case 2:
+		format.samp_format = STEREO_MSB;
+		break;
+	default:
+		dev_err(codec->dev, "%d channels not supported", channels);
+		return -EINVAL;
+	}
+
+	if (priv->pll == TWL6040_LPPLL_ID) {
+		priv->sysclk = sysclk;
+		twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+	}
+
+	format.f = rate;
+	if (!substream->stream) {
+		abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format,
+							ABE_CBPR5_IDX, &dma_sink);
+		abe_enable_data_transfer(TONES_DL_PORT);
+		if (!priv->mcpdm_dl_enable++)
+			abe_enable_data_transfer(PDM_DL_PORT);
+	}
+
+	return 0;
+}
+
+static int abe_tones_trigger(struct snd_pcm_substream *substream,
+			int cmd, struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	unsigned int snd_reg_shadow;
+
+	snd_reg_shadow = twl6040_read_reg_cache(codec, TWL6040_REG_SHADOW);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+		/*
+		 * low-power playback mode is restricted
+		 * for headset path only
+		 */
+		if ((priv->sysclk == 17640000) && priv->non_lp) {
+			dev_err(codec->dev,
+				"some enabled paths aren't supported at %dHz\n",
+				priv->sysclk);
+			return -EPERM;
+		}
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (!substream->stream){
+			if ((snd_reg_shadow & 0x01) == 0x01)
+				abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_TONES);
+
+			if ((snd_reg_shadow & 0x10) == 0x10)
+				abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_TONES);
+		}
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (!substream->stream){
+			if ((snd_reg_shadow & 0x01) == 0x01)
+				abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES);
+
+			if ((snd_reg_shadow & 0x10) == 0x10)
+				abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static void abe_tones_shutdown(struct snd_pcm_substream *substream,
+                                struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_device *socdev = rtd->socdev;
+        struct snd_soc_codec *codec = socdev->card->codec;
+        struct twl6040_data *priv = codec->private_data;
+        struct twl4030_codec_data *pdata = codec->dev->platform_data;
+	struct platform_device *pdev = to_platform_device(codec->dev);
+
+        if (!substream->stream) {
+                abe_disable_data_transfer(TONES_DL_PORT);
+		if (!--priv->mcpdm_dl_enable)
+	                abe_disable_data_transfer(PDM_DL_PORT);
+        }
+
+	if (!--priv->configure) {
+		pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+		if (pdata->device_idle)
+			pdata->device_idle(pdev);
+#endif
+	}
+}
+
+static struct snd_soc_dai_ops abe_tones_dai_ops = {
+	.startup	= abe_mm_startup,
+	.hw_params	= abe_tones_hw_params,
+	.digital_mute   = twl6040_mute,
+	.shutdown       = abe_tones_shutdown,
+	.trigger	= abe_tones_trigger,
+	.set_sysclk	= twl6040_set_dai_sysclk,
+};
+
+static int abe_voice_startup(struct snd_pcm_substream *substream,
+			struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	struct twl4030_codec_data *pdata = codec->dev->platform_data;
+	struct platform_device *pdev = to_platform_device(codec->dev);
+
+	if (!priv->sysclk) {
+		dev_err(codec->dev,
+			"no mclk configured, call set_sysclk() on init\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * capture is not supported at 17.64 MHz,
+	 * it's reserved for headset low-power playback scenario
+	 */
+	if ((priv->sysclk == 17640000) && substream->stream) {
+		dev_err(codec->dev,
+			"capture mode is not supported at %dHz\n",
+			priv->sysclk);
+		return -EINVAL;
+	}
+
+	snd_pcm_hw_constraint_list(substream->runtime, 0,
+				SNDRV_PCM_HW_PARAM_RATE,
+				priv->sysclk_constraints);
+
+	if (!priv->configure++) {
+		pm_runtime_get_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+		if (pdata->device_enable)
+			pdata->device_enable(pdev);
+#endif
+
+		abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC,
+			(abe_router_t *)abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]);
+		abe_write_gain(GAINS_DL1, GAIN_M6dB,  RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DL1, GAIN_M6dB,  RAMP_0MS, GAIN_RIGHT_OFFSET);
+		abe_write_gain(GAINS_DL2, GAIN_M6dB,  RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DL2, GAIN_M6dB,  RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+                abe_write_gain(GAINS_AMIC, GAIN_M6dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+                abe_write_gain(GAINS_AMIC, GAIN_M6dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+		abe_write_gain(GAINS_SPLIT, GAIN_M6dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_SPLIT, GAIN_M6dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+	}
+	return 0;
+}
+
+static int abe_voice_hw_params(struct snd_pcm_substream *substream,
+			struct snd_pcm_hw_params *params,
+			struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	u8 lppllctl;
+	int rate;
+	int channels;
+	abe_data_format_t format;
+#ifndef CONFIG_SND_OMAP_VOICE_TEST
+	abe_dma_t dma_sink;
+#endif
+
+	rate = params_rate(params);
+	switch (rate) {
+	case 16000:
+	case 8000:
+	/* Select output frequency 19.2 MHz */
+		if (priv->pll == TWL6040_LPPLL_ID) {
+			lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL);
+			lppllctl &= ~TWL6040_LPLLFIN;
+			priv->sysclk = 19200000;
+			twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl);
+		}
+		break;
+	default:
+		dev_err(codec->dev, "unsupported rate %d\n", rate);
+		return -EINVAL;
+	}
+
+	channels = params_channels(params);
+	switch (channels) {
+		case 1:
+		format.samp_format = MONO_MSB;
+		break;
+	case 2:
+		format.samp_format = STEREO_MSB;
+		break;
+	default:
+		dev_err(codec->dev, "%d channels not supported", channels);
+		return -EINVAL;
+	}
+
+	format.f = rate;
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+	if (!substream->stream) {
+		/* Vx_DL connection to McBSP 2 ports */
+		format.f = 8000;
+		format.samp_format = STEREO_RSHIFTED_16;
+		abe_connect_serial_port(VX_DL_PORT, &format, MCBSP2_RX);
+		/* Enable downlink port */
+		abe_enable_data_transfer(VX_DL_PORT);
+		if (!priv->mcpdm_dl_enable++)
+			abe_enable_data_transfer(PDM_DL_PORT);
+	} else {
+		/* Vx_UL connection to McBSP 2 ports */
+		format.f = 8000;
+		format.samp_format = STEREO_RSHIFTED_16;
+		abe_connect_serial_port(VX_UL_PORT, &format, MCBSP2_TX);
+		/* Enable uplink port */
+		abe_enable_data_transfer(VX_UL_PORT);
+		if (!priv->mcpdm_ul_enable++)
+			abe_enable_data_transfer(PDM_UL_PORT);
+	}
+#else
+	if (!substream->stream) {
+		abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+		abe_enable_data_transfer(VX_DL_PORT);
+		if (!priv->mcpdm_dl_enable++)
+			abe_enable_data_transfer(PDM_DL_PORT);
+	} else {
+		abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+		abe_enable_data_transfer(VX_UL_PORT);
+		if (!priv->mcpdm_ul_enable++)
+			abe_enable_data_transfer(PDM_UL_PORT);
+	}
+#endif
+
+	return 0;
+}
+
+static int abe_voice_trigger(struct snd_pcm_substream *substream,
+					int cmd, struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct twl6040_data *priv = codec->private_data;
+	unsigned int snd_reg_shadow;
+
+	snd_reg_shadow = twl6040_read_reg_cache(codec, TWL6040_REG_SHADOW);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+		/*
+		 * low-power playback mode is restricted
+		 * for headset path only
+		 */
+		if ((priv->sysclk == 17640000) && priv->non_lp) {
+			dev_err(codec->dev,
+				"some enabled paths aren't supported at %dHz\n",
+				priv->sysclk);
+			return -EPERM;
+		}
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (!substream->stream){
+			if ((snd_reg_shadow & 0x02) == 0x02)
+				abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+
+			if ((snd_reg_shadow & 0x20) == 0x20)
+				abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+		}
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (!substream->stream){
+			if ((snd_reg_shadow & 0x02) == 0x02)
+				abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+
+			if ((snd_reg_shadow & 0x20) == 0x20)
+				abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static void abe_voice_shutdown(struct snd_pcm_substream *substream,
+                                struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_device *socdev = rtd->socdev;
+        struct snd_soc_codec *codec = socdev->card->codec;
+        struct twl6040_data *priv = codec->private_data;
+        struct twl4030_codec_data *pdata = codec->dev->platform_data;
+	struct platform_device *pdev = to_platform_device(codec->dev);
+
+        if (!substream->stream) {
+                abe_disable_data_transfer(VX_DL_PORT);
+                if (!--priv->mcpdm_dl_enable) {
+			abe_disable_data_transfer(PDM_DL_PORT);
+	                if (priv->mcpdm_ul_enable == 0)
+				abe_disable_data_transfer(PDM_UL_PORT);
+		}
+        } else {
+		abe_disable_data_transfer(VX_UL_PORT);
+		if (!--priv->mcpdm_ul_enable) {
+	                if (priv->mcpdm_dl_enable == 0) {
+				abe_disable_data_transfer(PDM_UL_PORT);
+			}
+		}
+	}
+
+        if(!--priv->configure) {
+		pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+		if (pdata->device_idle)
+			pdata->device_idle(pdev);
+#endif
+	}
+}
+
+static struct snd_soc_dai_ops abe_voice_dai_ops = {
+	.startup	= abe_voice_startup,
+	.hw_params	= abe_voice_hw_params,
+	.digital_mute	= twl6040_mute,
+	.shutdown	= abe_voice_shutdown,
+	.trigger	= abe_voice_trigger,
+	.set_sysclk	= twl6040_set_dai_sysclk,
+};
+
+/* Audio Backend DAIs */
+struct snd_soc_dai abe_dai[] = {
+	/* Multimedia: MM-UL2, MM-DL */
+	{
+		.name = "Multimedia",
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
+			.formats = ABE_FORMATS,
+		},
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_48000,
+			.formats = ABE_FORMATS,
+		},
+		.ops = &abe_mm_dai_ops,
+	},
+	/* Tones DL: MM-DL2 */
+	{
+		.name = "Tones DL",
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
+			.formats = ABE_FORMATS,
+		},
+		.ops = &abe_tones_dai_ops,
+	},
+	/* Voice: VX-UL, VX-DL */
+	{
+		.name = "Voice",
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+			.formats = ABE_FORMATS,
+		},
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+			.formats = ABE_FORMATS,
+		},
+		.ops = &abe_voice_dai_ops,
+	},
+	/* Digital Uplink: MM-UL */
+	{
+		.name = "Digital Uplink",
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 2,
+			.channels_max = 10,
+			.rates = SNDRV_PCM_RATE_48000,
+			.formats = ABE_FORMATS,
+		},
+	},
+	/* Vibrator: VIB-DL */
+	{
+		.name = "Vibrator",
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 2,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_48000,
+			.formats = ABE_FORMATS,
+		},
+	},
+};
+
+#ifdef CONFIG_PM
+static int abe_twl6040_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct snd_soc_codec *codec = socdev->card->codec;
+
+	abe_twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+	return 0;
+}
+
+static int abe_twl6040_resume(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct snd_soc_codec *codec = socdev->card->codec;
+
+	abe_twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+	abe_twl6040_set_bias_level(codec, codec->suspend_bias_level);
+
+	return 0;
+}
+#else
+#define abe_twl6040_suspend NULL
+#define abe_twl6040_resume NULL
+#endif
+
+void twl6040_hs_jack_detect(struct snd_soc_codec *codec,
+			    struct snd_soc_jack *jack, int report)
+{
+	struct twl6040_data *priv = codec->private_data;
+	int status;
+
+	priv->hs_jack.jack = jack;
+	priv->hs_jack.report = report;
+
+	/* Sync status */
+	status = twl6040_read_reg_volatile(codec, TWL6040_REG_STATUS);
+	if(status & TWL6040_PLUGCOMP)
+		snd_soc_jack_report(jack, report, report);
+	else
+		snd_soc_jack_report(jack, 0, report);
+}
+EXPORT_SYMBOL_GPL(twl6040_hs_jack_detect);
+
+static struct snd_soc_codec *twl6040_codec;
+
+static int abe_twl6040_probe(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct snd_soc_codec *codec;
+	int ret = 0;
+
+	BUG_ON(!twl6040_codec);
+
+	codec = twl6040_codec;
+	socdev->card->codec = codec;
+
+	/* register pcms */
+	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to create pcms\n");
+		return ret;
+	}
+
+	abe_init_chip(codec, pdev);
+	snd_soc_add_controls(codec, twl6040_snd_controls,
+				ARRAY_SIZE(twl6040_snd_controls));
+	abe_twl6040_add_widgets(codec);
+
+	return 0;
+}
+
+static int abe_twl6040_remove(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct snd_soc_codec *codec = socdev->card->codec;
+
+	abe_twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
+	snd_soc_free_pcms(socdev);
+	snd_soc_dapm_free(socdev);
+	kfree(codec);
+
+	return 0;
+}
+
+struct snd_soc_codec_device soc_codec_dev_abe_twl6040 = {
+	.probe = abe_twl6040_probe,
+	.remove = abe_twl6040_remove,
+	.suspend = abe_twl6040_suspend,
+	.resume = abe_twl6040_resume,
+};
+EXPORT_SYMBOL_GPL(soc_codec_dev_abe_twl6040);
+
+static int __devinit abe_twl6040_codec_probe(struct platform_device *pdev)
+{
+	struct twl4030_codec_data *twl_codec = pdev->dev.platform_data;
+	struct snd_soc_codec *codec;
+	struct twl6040_data *priv;
+	int audpwron, naudint;
+	int ret = 0;
+
+	priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL);
+	if (priv == NULL)
+		return -ENOMEM;
+
+	if (twl_codec) {
+		audpwron = twl_codec->audpwron_gpio;
+		naudint = twl_codec->naudint_irq;
+	} else {
+		audpwron = -EINVAL;
+		naudint = 0;
+	}
+
+	priv->audpwron = audpwron;
+	priv->naudint = naudint;
+
+	codec = &priv->codec;
+	codec->dev = &pdev->dev;
+	codec->name = "twl6040";
+	codec->owner = THIS_MODULE;
+	codec->read = twl6040_read_reg_cache;
+	codec->write = twl6040_write;
+	codec->set_bias_level = abe_twl6040_set_bias_level;
+	codec->private_data = priv;
+	codec->dai = abe_dai;
+	codec->num_dai = ARRAY_SIZE(abe_dai);
+	codec->reg_cache_size = ARRAY_SIZE(twl6040_reg);
+	codec->reg_cache = kmemdup(twl6040_reg, sizeof(twl6040_reg),
+					GFP_KERNEL);
+	if (codec->reg_cache == NULL) {
+		ret = -ENOMEM;
+		goto cache_err;
+	}
+
+	mutex_init(&codec->mutex);
+	INIT_LIST_HEAD(&codec->dapm_widgets);
+	INIT_LIST_HEAD(&codec->dapm_paths);
+	init_completion(&priv->ready);
+
+	if (gpio_is_valid(audpwron)) {
+		ret = gpio_request(audpwron, "audpwron");
+		if (ret)
+			goto gpio1_err;
+
+		ret = gpio_direction_output(audpwron, 0);
+		if (ret)
+			goto gpio2_err;
+
+		priv->codec_powered = 0;
+	}
+
+	if (naudint) {
+		/* audio interrupt */
+		ret = request_threaded_irq(naudint, NULL,
+				twl6040_naudint_handler,
+				IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+				"twl6040_codec", codec);
+		if (ret)
+			goto gpio2_err;
+	} else {
+		if (gpio_is_valid(audpwron)) {
+			/* enable only codec ready interrupt */
+			twl6040_write_reg_cache(codec, TWL6040_REG_INTMR,
+					~TWL6040_READYMSK & TWL6040_ALLINT_MSK);
+		} else {
+			/* no interrupts at all */
+			twl6040_write_reg_cache(codec, TWL6040_REG_INTMR,
+						TWL6040_ALLINT_MSK);
+		}
+	}
+
+	/* init vio registers */
+	twl6040_init_vio_regs(codec);
+
+	/* power on device */
+	ret = abe_twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+	if (ret)
+		goto irq_err;
+
+	ret = snd_soc_register_codec(codec);
+	if (ret)
+		goto reg_err;
+
+	twl6040_codec = codec;
+
+	ret = snd_soc_register_dais(abe_dai, ARRAY_SIZE(abe_dai));
+	if (ret)
+		goto dai_err;
+
+	return 0;
+
+dai_err:
+	snd_soc_unregister_codec(codec);
+	twl6040_codec = NULL;
+reg_err:
+	abe_twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
+irq_err:
+	if (naudint)
+		free_irq(naudint, codec);
+	if (gpio_is_valid(audpwron))
+		gpio_free(audpwron);
+gpio2_err:
+	pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+	if (twl_codec->device_shutdown)
+		twl_codec->device_shutdown(pdev);
+#endif
+	if (gpio_is_valid(audpwron))
+		gpio_free(audpwron);
+gpio1_err:
+	kfree(codec->reg_cache);
+cache_err:
+	kfree(priv);
+	return ret;
+}
+
+static int __devexit abe_twl6040_codec_remove(struct platform_device *pdev)
+{
+	struct twl6040_data *priv = twl6040_codec->private_data;
+	struct twl4030_codec_data *pdata = pdev->dev.platform_data;
+	int audpwron = priv->audpwron;
+	int naudint = priv->naudint;
+
+	if (gpio_is_valid(audpwron))
+		gpio_free(audpwron);
+
+	if (naudint)
+		free_irq(naudint, twl6040_codec);
+
+	pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+	if (pdata->device_shutdown)
+		pdata->device_shutdown(pdev);
+#endif
+
+	snd_soc_unregister_dais(abe_dai, ARRAY_SIZE(abe_dai));
+	snd_soc_unregister_codec(twl6040_codec);
+
+	kfree(twl6040_codec);
+	twl6040_codec = NULL;
+
+	return 0;
+}
+
+static struct platform_driver abe_twl6040_codec_driver = {
+	.driver = {
+		.name = "twl6040_codec",
+		.owner = THIS_MODULE,
+	},
+	.probe = abe_twl6040_codec_probe,
+	.remove = __devexit_p(abe_twl6040_codec_remove),
+};
+
+static int __init abe_twl6040_codec_init(void)
+{
+	return platform_driver_register(&abe_twl6040_codec_driver);
+}
+module_init(abe_twl6040_codec_init);
+
+static void __exit abe_twl6040_codec_exit(void)
+{
+	platform_driver_unregister(&abe_twl6040_codec_driver);
+}
+module_exit(abe_twl6040_codec_exit);
+
+MODULE_DESCRIPTION("ASoC ABE-TWL6040 codec driver");
+MODULE_AUTHOR("Misael Lopez Cruz");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/abe-twl6040.h b/sound/soc/codecs/abe-twl6040.h
new file mode 100644
index 000000000000..74224648cd9f
--- /dev/null
+++ b/sound/soc/codecs/abe-twl6040.h
@@ -0,0 +1,36 @@
+/*
+ * ALSA SoC ABE-TWL6040 codec driver
+ *
+ * Author:	Misael Lopez Cruz <x0052729@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __ABE_TWL6040_H__
+#define __ABE_TWL6040_H__
+
+extern struct snd_soc_dai abe_dai[];
+extern struct snd_soc_codec_device soc_codec_dev_abe_twl6040;
+
+struct twl6040_setup_data {
+	void (*codec_enable)(int enable);
+	void *jack;
+};
+
+void twl6040_hs_jack_detect(struct snd_soc_codec *codec,
+			    struct snd_soc_jack *jack, int report);
+
+#endif /* End of __ABE_TWL6040_H__ */
diff --git a/sound/soc/codecs/abe/C_ABE_FW.CM b/sound/soc/codecs/abe/C_ABE_FW.CM
new file mode 100644
index 000000000000..b4601cfd383b
--- /dev/null
+++ b/sound/soc/codecs/abe/C_ABE_FW.CM
@@ -0,0 +1,1315 @@
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+0x000003,
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+0x000003,
+0xf4b6f8,
+0x000003,
+0x08c704,
+0x000003,
+0x028e88,
+0xb46d8b,
+0x051de8,
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+0x183def,
+0x051de8,
+0xb46d8b,
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+0x9f3a1d,
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+0x07da1a,
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+0x000003,
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+0x000003,
+0x0430ab,
+0x7ff7a1,
+0x000003,
+0x0430ab,
+0x7ff7a1,
+0x000003,
+0x0430ab,
+0x7ff7a1,
+0x000003,
+0x0430ab,
+0x7ff7a1,
+0x000020,
+0x3fffe0,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x040002,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x040002,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x040002,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x269ec3,
+0x0d0ff4,
+0x051eba,
+0x640001,
+0x02f290,
+0xfdd340,
+0x02a810,
+0x02a810,
+0xfdd340,
+0x02f290,
+0x45a895,
+0xf4a186,
+0x18a312,
+0xe445b2,
+0x10419e,
+
+
+#if 0
+		/* numerator of the flat impulse response */
+	343932, 1023940, 2058156, 2784340, 2784340, 2058156, 1023940, 343932,
+
+	1636220, -7884808, 318670, -582210, 729130, -748022, 448410,
+
+#else
+
+		/* numerator of the smoothed correction for the MCPDM bug */
+	687864, 2047884, 4116312, 5568684, 5568684, 4116312, 2047884, 687864,
+
+	1636220, -7884808, 318670, -582210, 729130, -748022, 448410,
+#endif
+
+0xc1248b,
+0xfd1080,
+0xfaca4c,
+0xfab048,
+0xfdb0ac,
+0x024f54,
+0x054fb8,
+0x0535b4,
+0x02ef80,
+0x3edb77,
+0x1d92ec,
+0x962b59,
+0x0bd422,
+0xe48132,
+0x2dbdc2,
+0xc7a94a,
+0x33fbe6,
+0xdd3502,
+0x0fea26,
+
diff --git a/sound/soc/codecs/abe/C_ABE_FW.PM b/sound/soc/codecs/abe/C_ABE_FW.PM
new file mode 100644
index 000000000000..f300f53f8d79
--- /dev/null
+++ b/sound/soc/codecs/abe/C_ABE_FW.PM
@@ -0,0 +1,2048 @@
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diff --git a/sound/soc/codecs/abe/C_ABE_FW.SM32 b/sound/soc/codecs/abe/C_ABE_FW.SM32
new file mode 100644
index 000000000000..33113a3970fa
--- /dev/null
+++ b/sound/soc/codecs/abe/C_ABE_FW.SM32
@@ -0,0 +1,4464 @@
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diff --git a/sound/soc/codecs/abe/C_ABE_FW.lDM b/sound/soc/codecs/abe/C_ABE_FW.lDM
new file mode 100644
index 000000000000..5c6a615ae4fe
--- /dev/null
+++ b/sound/soc/codecs/abe/C_ABE_FW.lDM
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diff --git a/sound/soc/codecs/abe/C_ABE_FW_SIZE.h b/sound/soc/codecs/abe/C_ABE_FW_SIZE.h
new file mode 100644
index 000000000000..3221b53e9068
--- /dev/null
+++ b/sound/soc/codecs/abe/C_ABE_FW_SIZE.h
@@ -0,0 +1,6 @@
+/*
+	FW 05.10  MEMORY SIZES
+*/
+#define ABE_DMEM_SIZE_OPTIMIZED 16384
+#define ABE_SMEM_SIZE_OPTIMIZED 15360
+#define ABE_CMEM_SIZE_OPTIMIZED 6552
\ No newline at end of file
diff --git a/sound/soc/codecs/abe/Makefile b/sound/soc/codecs/abe/Makefile
new file mode 100644
index 000000000000..4dd762827518
--- /dev/null
+++ b/sound/soc/codecs/abe/Makefile
@@ -0,0 +1,10 @@
+snd-soc-abe-hal-objs += abe_api.o \
+			abe_dbg.o \
+			abe_ext.o \
+			abe_ini.o \
+			abe_irq.o \
+			abe_lib.o \
+			abe_seq.o \
+
+obj-$(CONFIG_SND_SOC_ABE_TWL6040) += snd-soc-abe-hal.o
+
diff --git a/sound/soc/codecs/abe/abe_api.c b/sound/soc/codecs/abe/abe_api.c
new file mode 100644
index 000000000000..75713ba75896
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_api.c
@@ -0,0 +1,1625 @@
+/*
+ * ==========================================================================
+ *		 Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.	All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_main.h"
+#include "abe_typedef.h"
+
+static abe_uint32 ABE_FW_PM[ABE_PMEM_SIZE / 4]	= {
+#include "C_ABE_FW.PM"
+};
+static abe_uint32 ABE_FW_CM[ABE_CMEM_SIZE / 4]  = {
+#include "C_ABE_FW.CM"
+};
+static abe_uint32 ABE_FW_DM[ABE_DMEM_SIZE / 4]  = {
+#include "C_ABE_FW.lDM"
+};
+static abe_uint32 ABE_FW_SM[ABE_SMEM_SIZE / 4]  = {
+#include "C_ABE_FW.SM32"
+};
+
+/**
+* @fn abe_reset_hal()
+*
+*  Operations : reset the HAL by reloading the static variables and default AESS registers.
+*	Called after a PRCM cold-start reset of ABE
+*
+* @see	ABE_API.h
+*/
+void abe_reset_hal(void)
+{
+	/* init hardware components */
+	abe_hw_configuration();
+}
+
+/**
+* @fn abe_load_fwl()
+*
+*  Operations :
+*      loads the Audio Engine firmware, generate a single pulse on the Event generator
+*      to let execution start, read the version number returned from this execution.
+*
+* @see	ABE_API.h
+*/
+void abe_load_fw_param(abe_uint32 *PMEM, abe_uint32 PMEM_SIZE,
+			abe_uint32 *CMEM, abe_uint32 CMEM_SIZE,
+				abe_uint32 *SMEM, abe_uint32 SMEM_SIZE,
+					abe_uint32 *DMEM, abe_uint32 DMEM_SIZE)
+{
+	static abe_uint32 warm_boot;
+	abe_uint32 event_gen;
+
+#if PC_SIMULATION
+	/* the code is loaded from the Checkers */
+#else
+	/* do not load PMEM */
+	if (warm_boot) {
+		/* Stop the event Generator */
+		event_gen = 0;
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
+				EVENT_GENERATOR_START, &event_gen, 4);
+
+		/* Now we are sure the firmware is stalled */
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, CMEM, CMEM_SIZE);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, SMEM, SMEM_SIZE);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, DMEM, DMEM_SIZE);
+
+		/* Restore the event Generator status */
+		event_gen = 1;
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
+				EVENT_GENERATOR_START, &event_gen, 4);
+	} else {
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_PMEM, 0, PMEM, PMEM_SIZE);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, CMEM, CMEM_SIZE);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, SMEM, SMEM_SIZE);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, DMEM, DMEM_SIZE);
+	}
+
+	warm_boot = 1;
+#endif
+}
+
+void abe_load_fw(void)
+{
+	abe_load_fw_param(ABE_FW_PM, sizeof (ABE_FW_PM),
+			ABE_FW_CM, sizeof(ABE_FW_CM),
+			ABE_FW_SM, sizeof(ABE_FW_SM),
+			ABE_FW_DM, sizeof(ABE_FW_DM));
+
+	abe_reset_all_ports();
+	abe_build_scheduler_table();
+	abe_reset_all_sequence();
+	abe_select_main_port(PDM_DL_PORT);
+}
+
+/*
+ *  ABE_HARDWARE_CONFIGURATION
+ *
+ *  Parameter  :
+ *  U : use-case description list (pointer)
+ *  H : pointer to the output structure
+ *
+ *  Operations :
+ *	return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC
+ *	will be upgraded in FW06
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_read_hardware_configuration(abe_use_case_id *u, abe_opp_t *o, abe_hw_config_init_t *hw)
+{
+	abe_read_use_case_opp(u, o);
+
+	hw->MCPDM_CTRL__DIV_SEL = 0;		/* 0: 96kHz   1:192kHz */
+	hw->MCPDM_CTRL__CMD_INT = 1;		/* 0: no command in the FIFO,  1: 6 data on each lines (with commands) */
+	hw->MCPDM_CTRL__PDMOUTFORMAT = 0;	/* 0:MSB aligned  1:LSB aligned */
+	hw->MCPDM_CTRL__PDM_DN5_EN = 1;
+	hw->MCPDM_CTRL__PDM_DN4_EN = 1;
+	hw->MCPDM_CTRL__PDM_DN3_EN = 1;
+	hw->MCPDM_CTRL__PDM_DN2_EN = 1;
+	hw->MCPDM_CTRL__PDM_DN1_EN = 1;
+	hw->MCPDM_CTRL__PDM_UP3_EN = 0;
+	hw->MCPDM_CTRL__PDM_UP2_EN = 1;
+	hw->MCPDM_CTRL__PDM_UP1_EN = 1;
+	hw->MCPDM_FIFO_CTRL_DN__DN_TRESH = MCPDM_DL_ITER/6; /* All the McPDM_DL FIFOs are enabled simultaneously */
+	hw->MCPDM_FIFO_CTRL_UP__UP_TRESH = MCPDM_UL_ITER/2; /* number of ATC access upon AMIC DMArequests, 2 the FIFOs channels are enabled */
+
+	hw->DMIC_CTRL__DMIC_CLK_DIV = 0;	/* 0:2.4MHz  1:3.84MHz */
+	hw->DMIC_CTRL__DMICOUTFORMAT = 0;	/* 0:MSB aligned  1:LSB aligned */
+	hw->DMIC_CTRL__DMIC_UP3_EN = 1;
+	hw->DMIC_CTRL__DMIC_UP2_EN = 1;
+	hw->DMIC_CTRL__DMIC_UP1_EN = 1;
+	hw->DMIC_FIFO_CTRL__DMIC_TRESH = DMIC_ITER/6; /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */
+
+	hw->MCBSP_SPCR1_REG__RJUST = 1;		/* 1:MSB  2:LSB aligned */
+	hw->MCBSP_THRSH2_REG_REG__XTHRESHOLD = 1;
+	hw->MCBSP_THRSH1_REG_REG__RTHRESHOLD = 1;
+
+	hw->AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE = EVENT_GENERATOR_COUNTER_DEFAULT; /* 2050 gives about 96kHz */
+	hw->AESS_EVENT_SOURCE_SELECTION__SELECTION = 1;	/* 0: DMAreq, 1:Counter */
+	hw->AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION = ABE_ATC_MCPDMDL_DMA_REQ; /* 5bits DMAreq selection */
+
+	hw->HAL_EVENT_SELECTION = EVENT_TIMER;
+}
+
+/*
+ *  ABE_DEFAULT_CONFIGURATION
+ *
+ *  Parameter  :
+ *	use-case-ID : "LP player", "voice-call" use-cases as defined in the paragraph
+ *	"programming use-case sequences"
+ *	Param 1, 2, 3, 4 used for non regression tests
+ *
+ *  Operations :
+ *	private API used during development. Loads all the necessary parameters and data
+ *	patterns to allow a stand-alone functional test without the need of.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_default_configuration(abe_uint32 use_case)
+{
+	abe_data_format_t format;
+	abe_dma_t dma_sink;
+	abe_uint32 data_sink;
+        abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0};
+        abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0};
+        abe_opp_t OPP;
+	abe_hw_config_init_t CONFIG;
+
+	abe_load_fw();
+
+	switch (use_case) {
+	/* voice ul/dl on earpiece + MM_DL on IHF */
+	case UC2_VOICE_CALL_AND_IHF_MMDL:
+		/* enable one of the preloaded and programmable routing
+		 * configuration for the uplink paths
+		 * To be added here:
+		 * - Device driver initialization following
+		 *   abe_read_hardware_configuration() returned data
+		 * McPDM_DL : 6 slots activated (5 + Commands)
+		 * DMIC : 6 microphones activated
+		 * McPDM_UL : 2 microphones activated (No status)
+		 */
+		abe_read_hardware_configuration(UC2, &OPP, &CONFIG);	/* check hw config and opp config */
+		abe_set_opp_processing(OPP);				/* sets the OPP100 on FW05.xx */
+		abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);	/* "tick" of the audio engine */
+		/* mixers' configuration = voice on earphone + music on hands-free path */
+		abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_1MS, MIX_DL1_INPUT_VX_DL);
+		abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL);
+
+		abe_enable_data_transfer(MM_UL2_PORT);
+		abe_enable_data_transfer(MM_UL_PORT);
+		abe_enable_data_transfer(MM_DL_PORT);			/* enable all the data paths */
+		abe_enable_data_transfer(VX_DL_PORT);
+		abe_enable_data_transfer(VX_UL_PORT);
+		abe_enable_data_transfer(PDM_UL_PORT);
+		abe_enable_data_transfer(DMIC_PORT);
+		abe_enable_data_transfer(PDM_DL_PORT);
+		abe_enable_data_transfer(TONES_DL_PORT);
+		break;
+	case UC5_PINGPONG_MMDL:
+		/* Ping-Pong access through MM_DL using Left/Right
+		 * 16bits/16bits data format
+		 * To be added here:
+		 * - Device driver initialization following abe_read_hardware_configuration() returned data
+		 * McPDM_DL : 6 slots activated (5 + Commands)
+		 * DMIC : 6 microphones activated
+		 * McPDM_UL : 2 microphones activated (No status)
+		 */
+		abe_read_hardware_configuration(UC5, &OPP, &CONFIG);	/* check hw config and opp config */
+		abe_set_opp_processing(OPP);				/* sets the OPP100 on FW05.xx */
+		abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);	/* "tick" of the audio engine */
+
+		/* MM_DL init: overwrite the previous default initialization made above */
+		format.f = 48000;
+		format.samp_format = MONO_MSB;
+
+		/* connect a Ping-Pong SDMA protocol to MM_DL port
+		 * with Ping-Pong 576 mono samples
+		 * (12x4 bytes for each ping & pong size)
+		 */
+		abe_connect_dmareq_ping_pong_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, (12 * 4), &dma_sink);
+
+		/* mixers' configuration = voice on earphone + music on hands-free path */
+		abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL);
+		abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL);
+
+		/* Here: connect the sDMA to "dma_sink" content */
+		abe_enable_data_transfer(MM_DL_PORT);			/* enable all the data paths */
+		abe_enable_data_transfer(PDM_DL1_PORT);
+		break;
+	case UC6_PINGPONG_MMDL_WITH_IRQ:
+		/* Ping-Pong using the IRQ instead of the sDMA	*/
+		abe_read_hardware_configuration(UC5, &OPP, &CONFIG);	/* check hw config and opp config */
+		abe_set_opp_processing(OPP);				/* sets the OPP100 on FW05.xx */
+		abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);	/* "tick" of the audio engine */
+
+		/* MM_DL init: overwrite the previous default initialization made above */
+		format.f = 48000;
+		format.samp_format = STEREO_16_16;
+
+		/* connect a Ping-Pong cache-flush protocol to MM_DL port
+		 * with 50Hz (20ms) rate
+		 */
+		abe_add_subroutine(&abe_irq_pingpong_player_id,
+			(abe_subroutine2) abe_default_irq_pingpong_player,
+								SUB_0_PARAM, (abe_uint32*)0);
+		#define N_SAMPLES_BYTES (120 *4)
+		abe_connect_irq_ping_pong_port(MM_DL_PORT, &format,
+			abe_irq_pingpong_player_id, N_SAMPLES_BYTES, &data_sink,
+							PING_PONG_WITH_MCU_IRQ);
+
+		/* mixers' configuration = voice on earphone + music on hands-free path */
+		abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL);
+		abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL);
+
+		abe_enable_data_transfer(MM_DL_PORT);			/* enable all the data paths */
+		abe_enable_data_transfer(PDM_DL1_PORT);
+		break;
+	case UC71_STOP_ALL:
+		abe_disable_data_transfer(MM_UL2_PORT);
+		abe_disable_data_transfer(MM_DL_PORT);
+		abe_disable_data_transfer(VX_DL_PORT);
+		abe_disable_data_transfer(VX_UL_PORT);
+		abe_disable_data_transfer(PDM_UL_PORT);
+		abe_disable_data_transfer(DMIC_PORT);
+		abe_disable_data_transfer(PDM_DL_PORT);
+		break;
+	case UC72_ENABLE_ALL:
+		abe_enable_data_transfer(MM_UL2_PORT);
+		abe_enable_data_transfer(MM_DL_PORT);
+		abe_enable_data_transfer(VX_DL_PORT);
+		abe_enable_data_transfer(VX_UL_PORT);
+		abe_enable_data_transfer(PDM_UL_PORT);
+		abe_enable_data_transfer(DMIC_PORT);
+		abe_enable_data_transfer(PDM_DL_PORT);
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ *	ABE_IRQ_PROCESSING
+ *
+ *	Parameter  :
+ *		No parameter
+ *
+ *	Operations :
+ *		This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" ABE interrupt
+ *		This subroutine will check the IRQ_FIFO from the AE and act accordingly.
+ *		Some IRQ source are originated for the delivery of "end of time sequenced tasks"
+ *		notifications, some are originated from the Ping-Pong protocols, some are generated from
+ *		the embedded debugger when the firmware stops on programmable break-points, etc …
+ *
+ *	Return value :
+ *		None.
+ */
+void abe_irq_processing(void)
+{
+	abe_uint32 clear_abe_irq;
+	abe_uint32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm = 0;
+	abe_irq_data_t IRQ_data;
+#define IrqFiFoMask ((D_McuIrqFifo_sizeof >> 2) - 1)
+
+	/* extract the write pointer index from CMEM memory (INITPTR format) */
+	/* CMEM address of the write pointer in bytes */
+	cmem_src = MCU_IRQ_FIFO_ptr_labelID * 4;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_CMEM, cmem_src,
+		(abe_uint32*)&abe_irq_dbg_write_ptr,
+			sizeof (abe_irq_dbg_write_ptr));
+	abe_irq_dbg_write_ptr = sm_cm >> 16;	/* AESS left-pointer index located on MSBs */
+	abe_irq_dbg_write_ptr &= 0xFF;
+
+	/* loop on the IRQ FIFO content */
+	for (i = 0; i < D_McuIrqFifo_sizeof; i++) {
+		/* stop when the FIFO is empty */
+		if (abe_irq_dbg_write_ptr == abe_irq_dbg_read_ptr)
+			break;
+		/* read the IRQ/DBG FIFO */
+		abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+			D_McuIrqFifo_ADDR + (i << 2), (abe_uint32 *)&IRQ_data,
+					sizeof (IRQ_data));
+		abe_irq_dbg_read_ptr = (abe_irq_dbg_read_ptr + 1) & IrqFiFoMask;
+
+		/* select the source of the interrupt */
+		switch (IRQ_data.tag) {
+		case IRQtag_APS:
+			abe_irq_aps(IRQ_data.data);
+			break;
+		case IRQtag_PP:
+			abe_irq_ping_pong();
+			break;
+		case IRQtag_COUNT:
+			abe_irq_check_for_sequences(IRQ_data.data);
+			break;
+		default:
+		break;
+		}
+	}
+
+	abe_monitoring();
+
+	clear_abe_irq = 1;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_MCU_IRQSTATUS,
+							     &clear_abe_irq, 4);
+}
+
+/*
+ *  ABE_SELECT_MAIN_PORT
+ *
+ *  Parameter  :
+ *      id : audio port name
+ *
+ *  Operations :
+ *	tells the FW which is the reference stream for adjusting
+ *	the processing on 23/24/25 slots
+ *
+ *  Return value:
+ *      None.
+ */
+void abe_select_main_port (abe_port_id id)
+{
+	abe_uint32 selection;
+
+	/* flow control */
+	selection = D_IOdescr_ADDR + id*sizeof(ABE_SIODescriptor) + flow_counter_;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_Slot23_ctrl_ADDR, &selection, 4);
+}
+
+/*
+ *  ABE_WRITE_EVENT_GENERATOR
+ *
+ *  Parameter  :
+ *	e: Event Generation Counter, McPDM, DMIC or default.
+ *
+ *  Operations :
+ *	load the AESS event generator hardware source. Loads the firmware parameters
+ *	accordingly. Indicates to the FW which data stream is the most important to preserve
+ *	in case all the streams are asynchronous. If the parameter is "default", let the HAL
+ *	decide which Event source is the best appropriate based on the opened ports.
+ *
+ *	When neither the DMIC and the McPDM are activated the AE will have its EVENT generator programmed
+ *	with the EVENT_COUNTER. The event counter will be tuned in order to deliver a pulse frequency higher
+ *	than 96 kHz. The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz
+ *	The ratio is (MCLK/96000)+(1<<1) = 2050
+ *	(1<<1) in order to have the same speed at 50% and 100% OPP (only 15 MSB bits are used at OPP50%)
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_write_event_generator(abe_event_id e)
+{
+	abe_uint32 event, selection, counter, start;
+
+	counter = EVENT_GENERATOR_COUNTER_DEFAULT;
+	start = EVENT_GENERATOR_ON;
+	abe_current_event_id = e;
+
+	switch (e) {
+	case EVENT_MCPDM:
+		selection = EVENT_SOURCE_DMA;
+		event = ABE_ATC_MCPDMDL_DMA_REQ;
+		break;
+	case EVENT_DMIC:
+		selection = EVENT_SOURCE_DMA;
+		event = ABE_ATC_DMIC_DMA_REQ;
+		break;
+	case EVENT_TIMER:
+		selection = EVENT_SOURCE_COUNTER;
+		event = 0;
+		break;
+	case EVENT_McBSP:
+		selection = EVENT_SOURCE_COUNTER;
+		event = 0;
+		break;
+	case EVENT_McASP:
+		selection = EVENT_SOURCE_COUNTER;
+		event = 0;
+		break;
+	case EVENT_SLIMBUS:
+		selection = EVENT_SOURCE_COUNTER;
+		event = 0;
+		break;
+	case EVENT_44100:
+		selection = EVENT_SOURCE_COUNTER;
+		event = 0;
+		counter = EVENT_GENERATOR_COUNTER_44100;
+		break;
+	case EVENT_DEFAULT:
+		selection = EVENT_SOURCE_COUNTER;
+		event = 0;
+		break;
+	default:
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
+	}
+
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, EVENT_GENERATOR_COUNTER, &counter, 4);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, EVENT_SOURCE_SELECTION, &selection, 4);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, EVENT_GENERATOR_START, &start, 4);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, AUDIO_ENGINE_SCHEDULER, &event, 4);
+
+}
+
+/**
+*  abe_read_use_case_opp() description for void abe_read_use_case_opp().
+*
+*  Operations : returns the expected min OPP for a given use_case list
+*
+*  Parameter  : No parameter
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return	error code
+*
+* @see
+*/
+void abe_read_use_case_opp(abe_use_case_id *u, abe_opp_t *o)
+{
+	abe_uint32 opp, i;
+	abe_use_case_id *ptr = u;
+
+	#define MAX_READ_USE_CASE_OPP 10	/* there is no reason to have more use_cases */
+	#define OPP_25	1
+	#define OPP_50	2
+	#define OPP_100 4
+
+	opp = i = 0;
+	do {
+		/* check for pointer errors */
+		if (i > MAX_READ_USE_CASE_OPP) {
+			abe_dbg_param |= ERR_API;
+			abe_dbg_error_log(ABE_READ_USE_CASE_OPP_ERR);
+			break;
+		}
+
+		/* check for end_of_list */
+		if (*ptr <= 0)
+			break;
+
+		/* OPP selection based on current firmware implementation */
+		switch (*ptr) {
+		case ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE:
+			opp |= OPP_25;
+			break;
+		case ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER:
+			opp |= OPP_100;
+			break;
+		case ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL:
+			opp |= OPP_100;
+			break;
+		case ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT:
+			opp |= OPP_50;
+			break;
+		case ABE_MULTIMEDIA_AUDIO_RECORDER:
+			opp |= OPP_50;
+			break;
+		case ABE_VIBRATOR_OR_HAPTICS:
+			opp |= OPP_100;
+			break;
+		case ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER:
+			opp |= OPP_100;
+			break;
+		case ABE_RINGER_TONES:
+			opp |= OPP_100;
+			break;
+		case ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER:
+			opp |= OPP_100;
+			break;
+		default:
+			break;
+		}
+
+		i++;
+		ptr++;
+	} while (*ptr != 0);
+
+	if (opp & OPP_100)
+		*o = ABE_OPP100;
+	else if (opp & OPP_50)
+		*o = ABE_OPP50;
+	else
+		*o = ABE_OPP25;
+}
+
+/*
+ *  ABE_READ_LOWEST_OPP
+ *
+ *  Parameter  :
+ *	Data pointer : returned data
+ *
+ *  Operations :
+ *	Returns the lowest possible OPP based on the current active ports
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_read_lowest_opp(abe_opp_t *o)
+{
+	abe_uint32 opp;
+	opp = OPP_25;
+
+	if (abe_port[DMIC_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[PDM_UL_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[BT_VX_UL_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[MM_UL_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[MM_UL2_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[VX_UL_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[VX_DL_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[MM_EXT_OUT_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[MM_EXT_IN_PORT].status == RUN_P)
+		opp |= OPP_50;
+	if (abe_port[VIB_DL_PORT].status == RUN_P)
+		opp |= OPP_100;
+
+	if (opp & OPP_100)
+		*o = ABE_OPP100;
+	else if (opp & OPP_50)
+		*o = ABE_OPP50;
+	else
+		*o = ABE_OPP25;
+}
+
+/*
+ *  ABE_SET_OPP_PROCESSING
+ *
+ *  Parameter  :
+ *	New processing network and OPP:
+ *	  0: Ultra Lowest power consumption audio player (no post-processing, no mixer)
+ *	  1: OPP 25% (simple multimedia features, including low-power player)
+ *	  2: OPP 50% (multimedia and voice calls)
+ *	  3: OPP100% (EANC, multimedia complex use-cases)
+ *
+ *  Operations :
+ *	Rearranges the FW task network to the corresponding OPP list of features.
+ *	The corresponding AE ports are supposed to be set/reset accordingly before this switch.
+ *
+ *  Return value :
+ *	error code when the new OPP do not corresponds the list of activated features
+ */
+void abe_set_opp_processing(abe_opp_t opp)
+{
+	abe_uint32 dOppMode32;
+
+	switch(opp){
+	case ABE_OPP25:
+		/* OPP25% */
+		dOppMode32 = DOPPMODE32_OPP25;
+		break;
+	case ABE_OPP50:
+		/* OPP50% */
+		dOppMode32 = DOPPMODE32_OPP50;
+		break;
+	default:
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
+		case ABE_OPP100:
+		/* OPP100% */
+		dOppMode32 = DOPPMODE32_OPP100;
+		break;
+	}
+
+	/* Write Multiframe inside DMEM */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+		D_maxTaskBytesInSlot_ADDR, &dOppMode32, sizeof(abe_uint32));
+}
+
+/*
+ *  ABE_SET_PING_PONG_BUFFER
+ *
+ *  Parameter  :
+ *	Port_ID :
+ *	New data
+ *
+ *  Operations :
+ *	Updates the next ping-pong buffer with "size" bytes copied from the
+ *	host processor. This API notifies the FW that the data transfer is done.
+ */
+void abe_set_ping_pong_buffer(abe_port_id port, abe_uint32 n_bytes)
+{
+	abe_uint32 sio_pp_desc_address, struct_offset, *src, n_samples, datasize, base_and_size;
+	ABE_SPingPongDescriptor desc_pp;
+
+	/* ping_pong is only supported on MM_DL */
+	if (port != MM_DL_PORT) {
+	    abe_dbg_param |= ERR_API;
+	    abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+	/* translates the number of bytes in samples */
+	/* data size in DMEM words */
+	datasize = abe_dma_port_iter_factor(&((abe_port[port]).format));
+	/* data size in bytes */
+	datasize = datasize << 2;
+	n_samples = n_bytes / datasize;
+
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_PingPongDesc_ADDR,
+					(abe_uint32 *)&desc_pp, sizeof(desc_pp));
+
+	/*
+	 * read the port SIO descriptor and extract the current pointer
+	 * address  after reading the counter
+	 */
+	if ((desc_pp.counter & 0x1) == 0) {
+		struct_offset = (abe_uint32)&(desc_pp.nextbuff0_BaseAddr) -
+							(abe_uint32)&(desc_pp);
+		base_and_size = desc_pp.nextbuff0_BaseAddr;
+	} else {
+		struct_offset = (abe_uint32)&(desc_pp.nextbuff1_BaseAddr) -
+							(abe_uint32)&(desc_pp);
+		base_and_size = desc_pp.nextbuff1_BaseAddr;
+	}
+
+	base_and_size = (base_and_size & 0xFFFFL) + ((abe_uint32)n_samples << 16);
+
+	sio_pp_desc_address = D_PingPongDesc_ADDR + struct_offset;
+	src = &base_and_size;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_pp_desc_address,
+				(abe_uint32 *)&base_and_size, sizeof(abe_uint32));
+}
+
+/*
+ *  ABE_READ_NEXT_PING_PONG_BUFFER
+ *
+ *  Parameter  :
+ *	Port_ID :
+ *	Returned address to the next buffer (byte offset from DMEM start)
+ *
+ *  Operations :
+ *	Tell the next base address of the next ping_pong Buffer and its size
+ *
+ *
+ */
+void abe_read_next_ping_pong_buffer(abe_port_id port, abe_uint32 *p, abe_uint32 *n)
+{
+	abe_uint32 sio_pp_desc_address;
+	ABE_SPingPongDescriptor desc_pp;
+
+	/* ping_pong is only supported on MM_DL */
+	if (port != MM_DL_PORT) {
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+
+	/* read the port SIO descriptor and extract the current pointer address  after reading the counter */
+	sio_pp_desc_address = D_PingPongDesc_ADDR;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address, (abe_uint32*)&desc_pp, sizeof(ABE_SPingPongDescriptor));
+
+	if ((desc_pp.counter & 0x1) == 0) {
+		(*p) = desc_pp.nextbuff0_BaseAddr;
+	} else {
+		(*p) = desc_pp.nextbuff1_BaseAddr;
+	}
+
+	/* translates the number of samples in bytes */
+	(*n) = abe_size_pingpong;
+}
+
+/*
+ *  ABE_INIT_PING_PONG_BUFFER
+ *
+ *  Parameter  :
+ *	size of the ping pong
+ *	number of buffers (2 = ping/pong)
+ *	returned address of the ping-pong list of base address (byte offset from DMEM start)
+ *
+ *  Operations :
+ *	Computes the base address of the ping_pong buffers
+ *
+ */
+void abe_init_ping_pong_buffer(abe_port_id id, abe_uint32 size_bytes, abe_uint32 n_buffers, abe_uint32 *p)
+{
+	abe_uint32 i, dmem_addr;
+
+	/* ping_pong is supported in 2 buffers configuration right now but FW is ready for ping/pong/pung/pang... */
+	if (id != MM_DL_PORT || n_buffers > MAX_PINGPONG_BUFFERS) {
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+
+	for (i = 0; i < n_buffers; i++) {
+		dmem_addr = dmem_ping_pong_buffer + (i * size_bytes);
+	    abe_base_address_pingpong [i] = dmem_addr;	 /* base addresses of the ping pong buffers in U8 unit */
+	}
+
+	abe_size_pingpong = size_bytes;	/* global data */
+	*p = (abe_uint32)dmem_ping_pong_buffer;
+}
+
+/*
+ *  ABE_PLUG_SUBROUTINE
+ *
+ *  Parameter :
+ *  id: returned sequence index after plugging a new subroutine
+ *  f : subroutine address to be inserted
+ *  n : number of parameters of this subroutine
+ *
+ *  Returned value : error code
+ *
+ *  Operations : register a list of subroutines for call-back purpose
+ *
+ */
+void abe_plug_subroutine(abe_uint32 *id, abe_subroutine2 f, abe_uint32 n, abe_uint32* params)
+{
+	/* debug trace */
+	abe_add_subroutine (id, f, n, params);
+}
+
+/*
+ *  ABE_PLUG_SEQUENCE
+ *
+ *  Parameter  :
+ *	 Id: returned sequence index after pluging a new sequence (index in the tables)
+ *	 s : sequence to be inserted
+ *
+ *  Operations :
+ *	Load a time-sequenced operations.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_plug_sequence(abe_uint32 *id, abe_sequence_t *s)
+{
+}
+
+/*
+ *  ABE_SET_SEQUENCE_TIME_ACCURACY
+ *
+ *  Parameter  :
+ *	patch bit field used to guarantee the code compatibility without conditionnal compilation
+ *	Sequence index
+ *
+ *  Operations : two counters are implemented in the firmware:
+ *  -	one "fast" counter, generating an IRQ to the HAL for sequences scheduling, the rate is in the range 1ms .. 100ms
+ *  -	one "slow" counter, generating an IRQ to the HAL for the management of ASRC drift, the rate is in the range 1s .. 100s
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_set_sequence_time_accuracy(abe_micros_t fast, abe_micros_t slow)
+{
+}
+
+/*
+ *  ABE_LAUNCH_SEQUENCE
+ *
+ *  Parameter  :
+ *	patch bit field used to guarantee the code compatibility without conditionnal compilation
+ *	Sequence index
+ *
+ *  Operations :
+ *	Launch a list a time-sequenced operations.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_launch_sequence(abe_patch_rev patch, abe_uint32 n)
+{
+	just_to_avoid_the_many_warnings_abe_patch_rev = patch;
+	just_to_avoid_the_many_warnings = n;
+}
+
+/*
+ *  ABE_LAUNCH_SEQUENCE_PARAM
+ *
+ *  Parameter  :
+ *	patch bit field used to guarantee the code compatibility without conditionnal compilation
+ *	Sequence index
+ *	Parameters to the programmable sequence
+ *
+ *  Operations :
+ *	Launch a list a time-sequenced operations.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_launch_sequence_param(abe_patch_rev patch, abe_uint32 n, abe_int32 *param1, abe_int32 *param2, abe_int32 *param3, abe_int32 *param4)
+{
+}
+
+/*
+ *  ABE_RESET_PORT
+ *
+ *  Parameters :
+ *  id: port name
+ *
+ *  Returned value : error code
+ *
+ *  Operations : stop the port activity and reload default parameters on the associated processing features.
+ *	 Clears the internal AE buffers.
+ *
+ */
+void abe_reset_port(abe_port_id id)
+{
+	abe_port[id] = ((abe_port_t *) abe_port_init) [id];
+}
+
+/*
+ *  ABE_READ_REMAINING_DATA
+ *
+ *  Parameter  :
+ *	Port_ID :
+ *	size : pointer to the remaining number of 32bits words
+ *
+ *  Operations :
+ *	computes the remaining amount of data in the buffer.
+ *
+ *  Return value :
+ *	error code
+ */
+void abe_read_remaining_data(abe_port_id port, abe_uint32 *n)
+{
+}
+
+/*
+ *  ABE_DISABLE_DATA_TRANSFER
+ *
+ *  Parameter  :
+ *	p: port indentifier
+ *
+ *  Operations :
+ *	disables the ATC descriptor and stop IO/port activities
+ *	disable the IO task (@f = 0)
+ *	clear ATC DMEM buffer, ATC enabled
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_disable_data_transfer(abe_port_id id)
+{
+	/* local host variable status= "port is running" */
+	abe_port[id].status = IDLE_P;
+	/* disable DMA requests */
+	abe_disable_dma_request(id);
+	/* disable ATC transfers */
+	abe_init_atc(id);
+	abe_clean_temporary_buffers(id);
+}
+
+/*
+ *  ABE_ENABLE_DATA_TRANSFER
+ *
+ *  Parameter  :
+ *	p: port indentifier
+ *
+ *  Operations :
+ *	enables the ATC descriptor
+ *	reset ATC pointers
+ *	enable the IO task (@f <> 0)
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_enable_data_transfer(abe_port_id id)
+{
+	abe_port_protocol_t *protocol;
+	abe_data_format_t format;
+
+	abe_clean_temporary_buffers(id);
+
+	if (id == PDM_UL_PORT) {
+		/* initializes the ABE ATC descriptors in DMEM - MCPDM_UL */
+		protocol = &(abe_port[PDM_UL_PORT].protocol);
+		format = abe_port[PDM_UL_PORT].format;
+		abe_init_atc(PDM_UL_PORT);
+		abe_init_io_tasks(PDM_UL_PORT, &format, protocol);
+	}
+	if (id == PDM_DL_PORT) {
+		/* initializes the ABE ATC descriptors in DMEM - MCPDM_DL */
+		protocol = &(abe_port[PDM_DL_PORT].protocol);
+		format = abe_port[PDM_DL_PORT].format;
+		abe_init_atc(PDM_DL_PORT);
+		abe_init_io_tasks(PDM_DL_PORT, &format, protocol);
+	}
+	if (id == DMIC_PORT) {
+		/* one DMIC port enabled = all DMICs enabled,
+		 * since there is a single DMIC path for all DMICs */
+		protocol = &(abe_port[DMIC_PORT].protocol);
+		format = abe_port[DMIC_PORT].format;
+		abe_init_atc(DMIC_PORT);
+		abe_init_io_tasks(DMIC_PORT, &format, protocol);
+	}
+
+	/* local host variable status= "port is running" */
+	abe_port[id].status = RUN_P;
+	/* enable DMA requests */
+	abe_enable_dma_request(id);
+}
+
+/*
+ *  ABE_SET_DMIC_FILTER
+ *
+ *  Parameter  :
+ *	DMIC decimation ratio : 16/25/32/40
+ *
+ *  Operations :
+ *	Loads in CMEM a specific list of coefficients depending on the DMIC sampling
+ *	frequency (2.4MHz or 3.84MHz). This table compensates the DMIC decimator roll-off at 20kHz.
+ *	The default table is loaded with the DMIC 2.4MHz recommended configuration.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_set_dmic_filter(abe_dmic_ratio_t d)
+{
+	abe_int32 *src;
+
+	switch(d) {
+	case ABE_DEC16:
+		src = (abe_int32 *)abe_dmic_16;
+		break;
+	case ABE_DEC25:
+		src = (abe_int32 *) abe_dmic_25;
+		break;
+	case ABE_DEC32:
+		src = (abe_int32 *) abe_dmic_32;
+		break;
+	default:
+	case ABE_DEC40:
+		src = (abe_int32 *) abe_dmic_40;
+		break;
+	}
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM,
+		C_98_48_LP_Coefs_ADDR,
+		(abe_uint32 *)src, C_98_48_LP_Coefs_sizeof << 2);
+}
+
+/**
+* @fn abe_connect_cbpr_dmareq_port()
+*
+*  Operations : enables the data echange between a DMA and the ABE through the
+*	CBPr registers of AESS.
+*
+*   Parameters :
+*   id: port name
+*   f : desired data format
+*   d : desired dma_request line (0..7)
+*   a : returned pointer to the base address of the CBPr register and number of
+*	samples to exchange during a DMA_request.
+*
+* @see	ABE_API.h
+*/
+void abe_connect_cbpr_dmareq_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_dma_t *returned_dma_t)
+{
+	if (f->f == 44100)
+		/* waiting for a true SRC_44_48 in ABE */
+		abe_write_event_generator(EVENT_44100);
+	abe_port[id] = ((abe_port_t *)abe_port_init)[id];
+
+	abe_port[id].format = *f;
+	abe_port[id].protocol.protocol_switch = DMAREQ_PORT_PROT;
+	abe_port[id].protocol.p.prot_dmareq.iter = abe_dma_port_iteration(f);
+	abe_port[id].protocol.p.prot_dmareq.dma_addr = ABE_DMASTATUS_RAW;
+	abe_port[id].protocol.p.prot_dmareq.dma_data = (1 << d);
+
+	abe_port[id].status = RUN_P;
+
+	/* load the micro-task parameters */
+	abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol));
+
+	/* load the dma_t with physical information from AE memory mapping */
+	abe_init_dma_t(id, &((abe_port [id]).protocol));
+
+	/* load the ATC descriptors - disabled */
+	abe_init_atc(id);
+
+	/* return the dma pointer address */
+	abe_read_port_address(id, returned_dma_t);
+}
+
+/**
+* @fn abe_connect_dmareq_port()
+*
+*  Operations : enables the data echanges between a DMA and a direct access to
+*   the DMEM memory of ABE. On each dma_request activation the DMA will exchange
+*   "iter" bytes and rewind its pointer to the base address "l3" waiting for the
+*   next activation. The scheme is used for the MM_UL and debug port
+*
+*   Parameters :
+*   id: port name
+*   f : desired data format
+*   d : desired dma_request line (0..7)
+*   a : returned pointer to the base address of the ping-pong buffer and number
+*	of samples to exchange during a DMA_request..
+*
+* @see	ABE_API.h
+*/
+void abe_connect_dmareq_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_dma_t *a)
+{
+}
+
+/**
+* @fn abe_connect_dmareq_ping_pong_port()
+*
+*  Operations : enables the data echanges between a DMA and a direct access to
+*   the DMEM memory of ABE. On each dma_request activation the DMA will exchange
+*   "s" bytes and switch to the "pong" buffer for a new buffer exchange.
+*
+*    Parameters :
+*    id: port name
+*    f : desired data format
+*    d : desired dma_request line (0..7)
+*    s : half-buffer (ping) size
+*
+*    a : returned pointer to the base address of the ping-pong buffer and number of samples to exchange during a DMA_request.
+*
+* @see	ABE_API.h
+*/
+void abe_connect_dmareq_ping_pong_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_uint32 s, abe_dma_t *returned_dma_t)
+{
+	abe_dma_t dma1;
+
+	/* ping_pong is only supported on MM_DL */
+	if (id != MM_DL_PORT)
+	{
+	    abe_dbg_param |= ERR_API;
+	    abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+
+	/* declare PP buffer and prepare the returned dma_t */
+        abe_init_ping_pong_buffer(MM_DL_PORT, s, 2, (abe_uint32 *)&(returned_dma_t->data));
+
+	abe_port [id]				   = ((abe_port_t *) abe_port_init) [id];
+
+	(abe_port [id]).format			    = (*f);
+	(abe_port [id]).protocol.protocol_switch	  = PINGPONG_PORT_PROT;
+	(abe_port [id]).protocol.p.prot_pingpong.buf_addr = dmem_ping_pong_buffer;
+	(abe_port [id]).protocol.p.prot_pingpong.buf_size = s;
+	(abe_port [id]).protocol.p.prot_pingpong.irq_addr = ABE_DMASTATUS_RAW;
+	(abe_port [id]).protocol.p.prot_pingpong.irq_data = (1 << d);
+
+	abe_port [id].status = RUN_P;
+
+	/* load the micro-task parameters DESC_IO_PP */
+	abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol));
+
+	/* load the dma_t with physical information from AE memory mapping */
+	abe_init_dma_t(id, &((abe_port [id]).protocol));
+
+	dma1.data = (abe_uint32 *)(abe_port [id].dma.data + ABE_DMEM_BASE_ADDRESS_L3);
+	dma1.iter = abe_port [id].dma.iter;
+	(*returned_dma_t) = dma1;
+}
+
+/**
+* @fn abe_connect_irq_ping_pong_port()
+*
+*  Operations : enables the data echanges between a direct access to the DMEM
+*	memory of ABE using cache flush. On each IRQ activation a subroutine
+*	registered with "abe_plug_subroutine" will be called. This subroutine
+*	will generate an amount of samples, send them to DMEM memory and call
+*	"abe_set_ping_pong_buffer" to notify the new amount of samples in the
+*	pong buffer.
+*
+*    Parameters :
+*	id: port name
+*	f : desired data format
+*	I : index of the call-back subroutine to call
+*	s : half-buffer (ping) size
+*
+*	p: returned base address of the first (ping) buffer)
+*
+* @see	ABE_API.h
+*/
+void abe_connect_irq_ping_pong_port(abe_port_id id, abe_data_format_t *f,
+			abe_uint32 subroutine_id, abe_uint32 size,
+					abe_uint32 *sink, abe_uint32 dsp_mcu_flag)
+{
+	/* ping_pong is only supported on MM_DL */
+	if (id != MM_DL_PORT) {
+	    abe_dbg_param |= ERR_API;
+	    abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+
+	abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+	(abe_port[id]).format = (*f);
+	(abe_port[id]).protocol.protocol_switch	  = PINGPONG_PORT_PROT;
+	(abe_port[id]).protocol.p.prot_pingpong.buf_addr = dmem_ping_pong_buffer;
+	(abe_port[id]).protocol.p.prot_pingpong.buf_size = size;
+	(abe_port[id]).protocol.p.prot_pingpong.irq_data = (1);
+
+	abe_init_ping_pong_buffer(MM_DL_PORT, size, 2, sink);
+
+	if (dsp_mcu_flag == PING_PONG_WITH_MCU_IRQ)
+		(abe_port [id]).protocol.p.prot_pingpong.irq_addr = ABE_MCU_IRQSTATUS_RAW;
+
+	if (dsp_mcu_flag == PING_PONG_WITH_DSP_IRQ)
+		(abe_port [id]).protocol.p.prot_pingpong.irq_addr = ABE_DSP_IRQSTATUS_RAW;
+
+	abe_port[id].status = RUN_P;
+
+	/* load the micro-task parameters */
+	abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol));
+
+	/* load the ATC descriptors - disabled */
+	abe_init_atc(id);
+
+	(*sink)= (abe_port [id]).protocol.p.prot_pingpong.buf_addr;
+}
+
+/**
+* @fn abe_connect_serial_port()
+*
+*  Operations : enables the data echanges between a McBSP and an ATC buffer in
+*   DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz
+*   voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
+*   abe_write_port API.
+*
+*   Parameters :
+*    id: port name
+*    f : data format
+*    i : peripheral ID (McBSP #1, #2, #3)
+*
+* @see	ABE_API.h
+*/
+void abe_connect_serial_port(abe_port_id id, abe_data_format_t *f, abe_mcbsp_id mcbsp_id)
+{
+	abe_port [id] = ((abe_port_t *) abe_port_init) [id];
+	(abe_port [id]).format = (*f);
+	(abe_port [id]).protocol.protocol_switch = SERIAL_PORT_PROT;
+	/* McBSP peripheral connected to ATC */
+	(abe_port [id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE;
+	/* ITERation on each DMAreq signals */
+	(abe_port [id]).protocol.p.prot_serial.iter = abe_dma_port_iteration(f);
+
+	//(abe_port [id]).protocol.p.prot_serial.buf_addr;		/* Address of ATC McBSP/McASP descriptor's in bytes */
+	//(abe_port [id]).protocol.p.prot_serial.buf_size;		/* DMEM address in bytes */
+	//(abe_port [id]).protocol.p.prot_serial.thr_flow;		/* Data threshold for flow management */
+
+	abe_port [id].status = RUN_P;
+	/* load the micro-task parameters */
+	abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol));
+	/* load the ATC descriptors - disabled */
+	abe_init_atc(id);
+}
+
+/*
+ *  ABE_READ_PORT_DESCRIPTOR
+ *
+ *  Parameter  :
+ *	id: port name
+ *	f : input pointer to the data format
+ *	p : input pointer to the protocol description
+ *	dma : output pointer to the DMA iteration and data destination pointer :
+ *
+ *  Operations :
+ *	returns the port parameters from the HAL internal buffer.
+ *
+ *  Return value :
+ *	error code in case the Port_id is not compatible with the current OPP value
+ */
+void abe_read_port_descriptor(abe_port_id port, abe_data_format_t *f, abe_port_protocol_t *p)
+{
+	(*f)	= (abe_port[port]).format;
+	(*p)	= (abe_port[port]).protocol;
+}
+
+/*
+ *  ABE_READ_APS_ENERGY
+ *
+ *  Parameter  :
+ *	Port_ID : port ID supporting APS
+ *	APS data struct pointer
+ *
+ *  Operations :
+ *	Returns the estimated amount of energy
+ *
+ *  Return value :
+ *	error code when the Port is not activated.
+ */
+void abe_read_aps_energy(abe_port_id *p, abe_gain_t *a)
+{
+	just_to_avoid_the_many_warnings_abe_port_id = *p;
+	just_to_avoid_the_many_warnings_abe_gain_t = *a;
+}
+
+/*
+ *  ABE_READ_PORT_ADDRESS
+ *
+ *  Parameter  :
+ *	dma : output pointer to the DMA iteration and data destination pointer
+ *
+ *  Operations :
+ *	This API returns the address of the DMA register used on this audio port.
+ *	Depending on the protocol being used, adds the base address offset L3 (DMA) or MPU (ARM)
+ *
+ *  Return value :
+ */
+void abe_read_port_address(abe_port_id port, abe_dma_t *dma2)
+{
+	abe_dma_t_offset dma1;
+	abe_uint32 protocol_switch;
+
+	dma1  = (abe_port[port]).dma;
+	protocol_switch = abe_port[port].protocol.protocol_switch;
+
+	switch (protocol_switch) {
+	case PINGPONG_PORT_PROT:
+		/* return the base address of the ping buffer in L3 and L4 spaces */
+		(*dma2).data = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3);
+		(*dma2).l3_dmem = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3);
+		(*dma2).l4_dmem = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L4);
+		break;
+	case DMAREQ_PORT_PROT:
+		/* return the CBPr(L3), DMEM(L3), DMEM(L4) address */
+		(*dma2).data = (void *)(dma1.data + ABE_ATC_BASE_ADDRESS_L3);
+		(*dma2).l3_dmem =
+			(void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
+					ABE_DMEM_BASE_ADDRESS_L3);
+		(*dma2).l4_dmem = (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr + ABE_DMEM_BASE_ADDRESS_L4);
+		break;
+	default:
+		break;
+	}
+
+	(*dma2).iter  = (dma1.iter);
+}
+
+/*
+ *  ABE_WRITE_EQUALIZER
+ *
+ *  Parameter  :
+ *	Id  : name of the equalizer
+ *	Param : equalizer coefficients
+ *
+ *  Operations :
+ *	Load the coefficients in CMEM. This API can be called when the corresponding equalizer
+ *	is not activated. After reloading the firmware the default coefficients corresponds to
+ *	"no equalizer feature". Loading all coefficients with zeroes disables the feature.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_write_equalizer(abe_equ_id id, abe_equ_t *param)
+{
+	abe_uint32 eq_offset, length, *src;
+
+	switch(id) {
+	default:
+	case EQ1:
+		eq_offset = C_DL1_Coefs_ADDR;
+		break;
+	case EQ2L:
+		eq_offset = C_DL2_L_Coefs_ADDR;
+		break;
+	case EQ2R:
+		eq_offset = C_DL2_R_Coefs_ADDR;
+		break;
+	case EQSDT:
+		eq_offset = C_SDT_Coefs_ADDR;
+		break;
+	case EQMIC:
+		eq_offset = C_98_48_LP_Coefs_ADDR;
+		break;
+	case APS1:
+		eq_offset = C_APS_DL1_coeffs1_ADDR;
+		break;
+	case APS2L:
+		eq_offset = C_APS_DL2_L_coeffs1_ADDR;
+		break;
+	case APS2R:
+		eq_offset = C_APS_DL2_R_coeffs1_ADDR;
+		break;
+	}
+
+	length = param->equ_length;
+	src = (abe_uint32 *)((param->coef).type1);
+
+	eq_offset <<=2;	/* translate in bytes */
+	length <<=2;	/* translate in bytes */
+
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, eq_offset, src, length);
+}
+
+/*
+ * ABE_SET_ASRC_DRIFT_CONTROL
+ *
+ *  Parameter  :
+ *	Id  : name of the asrc
+ *	f: flag which enables (1) the automatic computation of drift parameters
+ *
+ *  Operations :
+ *	When an audio port is connected to an hardware peripheral (MM_DL connected to a McBSP for
+ *	example), the drift compensation can be managed in "forced mode" (f=0) or "adaptive mode"
+ *	(f=1). In the first case the drift is managed with the usage of the API "abe_write_asrc".
+ *	In the second case the firmware will generate on periodic basis an information about the
+ *	observed drift, the HAL will reload the drift parameter based on those observations.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_set_asrc_drift_control(abe_asrc_id id, abe_uint32 f)
+{
+}
+
+/*
+ * ABE_WRITE_ASRC
+ *
+ *  Parameter  :
+ *	Id  : name of the asrc
+ *	param : drift value t compensate
+ *
+ *  Operations :
+ *	Load the drift coefficients in FW memory. This API can be called when the corresponding
+ *	ASRC is not activated. After reloading the firmware the default coefficients corresponds
+ *	to "no ASRC activated". Loading the drift value with zero disables the feature.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_write_asrc(abe_asrc_id id, abe_drift_t dppm)
+{
+#if 0
+	abe_int32 dtempvalue, adppm, alpha_current, beta_current, asrc_params;
+	abe_int32 atempvalue32[8];
+	/*
+	 * x = ppm
+	 *	 - 1000000/x must be multiple of 16
+	 *	 - deltaalpha = round(2^20*x*16/1000000)=round(2^18/5^6*x) on 22 bits. then shifted by 2bits
+	 *	 - minusdeltaalpha
+	 *	 - oneminusepsilon = 1-deltaalpha/2.
+	 *	 ppm = 250
+	 *	 - 1000000/250=4000
+	 *	 - deltaalpha = 4194.3 ~ 4195 => 0x00418c
+	 */
+	 /* examples for -6250 ppm */
+	 // atempvalue32[0] = 4;		  /* d_constalmost0 */
+	 // atempvalue32[1] = -1;		   /* d_driftsign */
+	 // atempvalue32[2] = 15;		  /* d_subblock */
+	 // atempvalue32[3] = 0x00066668; /* d_deltaalpha */
+	 // atempvalue32[4] = 0xfff99998; /* d_minusdeltaalpha */
+	 // atempvalue32[5] = 0x003ccccc; /* d_oneminusepsilon */
+	 // atempvalue32[6] = 0x00000000; /* d_alphazero */
+	 // atempvalue32[7] = 0x00400000; /* d_betaone */
+
+	/* compute new value for the ppm */
+	if (dppm > 0){
+		atempvalue32[1] = 1;		   /* d_driftsign */
+		adppm = dppm;
+	} else {
+		atempvalue32[1] = -1;		   /* d_driftsign */
+		adppm = (-1*dppm);
+	}
+
+	dtempvalue =  (adppm << 4) +  adppm - ((adppm * 3481L)/15625L);
+	atempvalue32[3] = dtempvalue<<2;
+	atempvalue32[4] = (-dtempvalue)<<2;
+	atempvalue32[5] = (0x00100000-(dtempvalue/2))<<2;
+
+	switch (id) {
+	case ASRC2:		/* asynchronous sample-rate-converter for the uplink voice path */
+		alpha_current = C_AlphaCurrent_UL_VX_ADDR;
+		beta_current  = C_BetaCurrent_UL_VX_ADDR;
+		asrc_params   = D_AsrcVars_UL_VX_ADDR;
+		break;
+	case ASRC1:		/* asynchronous sample-rate-converter for the downlink voice path */
+		alpha_current = C_AlphaCurrent_DL_VX_ADDR;
+		beta_current  = C_BetaCurrent_DL_VX_ADDR;
+		asrc_params   = D_AsrcVars_DL_VX_ADDR;
+		break;
+	default:
+	case ASRC3:		/* asynchronous sample-rate-converter for the multimedia player */
+		alpha_current = C_AlphaCurrent_DL_MM_ADDR;
+		beta_current  = C_BetaCurrent_DL_MM_ADDR;
+		asrc_params   = D_AsrcVars_DL_MM_ADDR;
+		break;
+	}
+
+	dtempvalue = 0x00000000;
+	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, alpha_current,(abe_uint32 *)&dtempvalue, 4);
+	dtempvalue = 0x00400000;
+	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, beta_current, (abe_uint32 *)&dtempvalue, 4);
+	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, asrc_params , (abe_uint32 *)&atempvalue32, sizeof(atempvalue32));
+#endif
+}
+
+/*
+ *  ABE_WRITE_APS
+ *
+ *  Parameter  :
+ *	Id  : name of the aps filter
+ *	param : table of filter coefficients
+ *
+ *  Operations :
+ *	Load the filters and thresholds coefficients in FW memory. This API can be called when
+ *	the corresponding APS is not activated. After reloading the firmware the default coefficients
+ *	corresponds to "no APS activated". Loading all the coefficients value with zero disables
+ *	the feature.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_write_aps(abe_aps_id id, abe_aps_t *param)
+{
+}
+
+/*
+ *  ABE_WRITE_MIXER
+ *
+ *  Parameter  :
+ *  Id	: name of the mixer
+ *  param : list of input gains of the mixer
+ *  p : list of port corresponding to the above gains
+ *
+ *  Operations :
+ *	Load the gain coefficients in FW memory. This API can be called when the corresponding
+ *	MIXER is not activated. After reloading the firmware the default coefficients corresponds
+ *	to "all input and output mixer's gain in mute state". A mixer is disabled with a network
+ *	reconfiguration corresponding to an OPP value.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_write_gain(abe_gain_id id, abe_gain_t f_g, abe_ramp_t f_ramp, abe_port_id p)
+{
+	abe_uint32 lin_g, mixer_target, mixer_offset;
+	abe_int32 gain_index;
+
+	gain_index = ((f_g - min_mdb) / 100);
+	gain_index = maximum(gain_index, 0);
+	gain_index = minimum(gain_index, sizeof_db2lin_table);
+
+	lin_g = abe_db2lin_table [gain_index];
+
+	switch(id) {
+	default:
+	case GAINS_DMIC1:
+		mixer_offset = dmic1_gains_offset;
+		break;
+	case GAINS_DMIC2:
+		mixer_offset = dmic2_gains_offset;
+		break;
+	case GAINS_DMIC3:
+		mixer_offset = dmic3_gains_offset;
+		break;
+	case GAINS_AMIC:
+		mixer_offset = amic_gains_offset;
+		break;
+	case GAINS_DL1:
+		mixer_offset = dl1_gains_offset;
+		break;
+	case GAINS_DL2:
+		mixer_offset = dl2_gains_offset;
+		break;
+	case GAINS_SPLIT:
+		mixer_offset = splitters_gains_offset;
+		break;
+	case MIXDL1:
+		mixer_offset = mixer_dl1_offset;
+		break;
+	case MIXDL2:
+		mixer_offset = mixer_dl2_offset;
+		break;
+	case MIXECHO:
+		mixer_offset = mixer_echo_offset;
+		break;
+	case MIXSDT:
+		mixer_offset = mixer_sdt_offset;
+		break;
+	case MIXVXREC:
+		mixer_offset = mixer_vxrec_offset;
+		break;
+	case MIXAUDUL:
+		mixer_offset = mixer_audul_offset;
+		break;
+	}
+
+	mixer_target = (smem_target_gain_base << 1);/* SMEM word32 address */
+	mixer_target += mixer_offset;
+	mixer_target += p;
+	mixer_target <<= 2; /* translate coef address in Bytes */
+
+	/* load the S_G_Target SMEM table */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, mixer_target,
+				(abe_uint32*)&lin_g, sizeof(lin_g));
+}
+
+void abe_write_mixer(abe_mixer_id id, abe_gain_t f_g, abe_ramp_t f_ramp, abe_port_id p)
+{
+	abe_write_gain((abe_gain_id)id, f_g, f_ramp, p);
+}
+
+/*
+ *  ABE_SET_ROUTER_CONFIGURATION
+ *
+ *  Parameter  :
+ *	Id  : name of the router
+ *	Conf : id of the configuration
+ *	param : list of output index of the route
+ *
+ *  Operations :
+ *	The uplink router takes its input from DMIC (6 samples), AMIC (2 samples) and
+ *	PORT1/2 (2 stereo ports). Each sample will be individually stored in an intermediate
+ *	table of 10 elements. The intermediate table is used to route the samples to
+ *	three directions : REC1 mixer, 2 EANC DMIC source of filtering and MM recording audio path.
+ *	For example, a use case consisting in AMIC used for uplink voice communication, DMIC 0,1,2,3
+ *	used for multimedia recording, , DMIC 5 used for EANC filter, DMIC 4 used for the feedback channel,
+ *	will be implemented with the following routing table index list :
+ *	[3, 2 , 1, 0, 0, 0 (two dummy indexes to data that will not be on MM_UL), 4, 5, 7, 6]
+ *  example
+ *      abe_set_router_configuration (UPROUTE, UPROUTE_CONFIG_AMIC, abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]);
+ *  Return value :
+ *	None.
+ */
+void abe_set_router_configuration(abe_router_id id, abe_uint32 configuration, abe_router_t *param)
+{
+	abe_uint8 aUplinkMuxing[16], n, i;
+
+	n = D_aUplinkRouting_ADDR_END - D_aUplinkRouting_ADDR + 1;
+
+	for(i=0; i < n; i++)
+		aUplinkMuxing[i] = (abe_uint8) (param [i]);
+
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_aUplinkRouting_ADDR, (abe_uint32 *)aUplinkMuxing, sizeof (aUplinkMuxing));
+}
+
+/*
+ *  ABE_READ_DEBUG_TRACE
+ *
+ *  Parameter  :
+ *	data destination pointer
+ *	max number of data read
+ *
+ *  Operations :
+ *	reads the AE circular data pointer holding pairs of debug data+timestamps, and store
+ *	the pairs in linear addressing to the parameter pointer. Stops the copy when the max
+ *	parameter is reached or when the FIFO is empty.
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_read_debug_trace(abe_uint32 *data, abe_uint32 *n)
+{
+	just_to_avoid_the_many_warnings = (*data);
+	just_to_avoid_the_many_warnings = (*n);
+}
+
+/*
+ *  ABE_SET_DEBUG_TRACE
+ *
+ *  Parameter  :
+ *	debug ID from a list to be defined
+ *
+ *  Operations :
+ *	load a mask which filters the debug trace to dedicated types of data
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_set_debug_trace(abe_dbg_t debug)
+{
+}
+
+/*
+ *  ABE_REMOTE_DEBUGGER_INTERFACE
+ *
+ *  Parameter  :
+ *
+ *  Operations :
+ *	interpretation of the UART stream from the remote debugger commands.
+ *	The commands consist in setting break points, loading parameter
+ *
+ *  Return value :
+ *	None.
+ */
+void abe_remote_debugger_interface(abe_uint32 n, abe_uint8 *p)
+{
+}
diff --git a/sound/soc/codecs/abe/abe_api.h b/sound/soc/codecs/abe/abe_api.h
new file mode 100644
index 000000000000..5a30d8bc306f
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_api.h
@@ -0,0 +1,708 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_API_H_
+#define _ABE_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * External API
+ */
+#if PC_SIMULATION
+extern void target_server_read_pmem(abe_uint32 address,	 abe_uint32 *data, abe_uint32 nb_words_32bits);
+extern void target_server_write_pmem(abe_uint32 address,	 abe_uint32 *data, abe_uint32 nb_words_32bits);
+extern void target_server_read_cmem(abe_uint32 address,	 abe_uint32 *data, abe_uint32 nb_words_32bits);
+extern void target_server_write_cmem(abe_uint32 address,	 abe_uint32 *data, abe_uint32 nb_words_32bits);
+extern void target_server_read_atc(abe_uint32 address,	 abe_uint32 *data, abe_uint32 nb_words_32bits);
+extern void target_server_write_atc(abe_uint32 address,        abe_uint32 *data, abe_uint32 nb_words_32bits);
+extern void target_server_read_smem(abe_uint32 address_48bits, abe_uint32 *data, abe_uint32 nb_words_48bits);
+extern void target_server_write_smem(abe_uint32 address_48bits, abe_uint32 *data, abe_uint32 nb_words_48bits);
+extern void target_server_read_dmem(abe_uint32 address_byte,   abe_uint32 *data, abe_uint32 nb_byte);
+extern void target_server_write_dmem(abe_uint32 address_byte,   abe_uint32 *data, abe_uint32 nb_byte);
+
+extern void target_server_activate_mcpdm_ul(void);
+extern void target_server_activate_mcpdm_dl(void);
+extern void target_server_activate_dmic(void);
+extern void target_server_set_voice_sampling(int dVirtAudioVoiceMode, int dVirtAudioVoiceSampleFrequency);
+extern void target_server_set_dVirtAudioMultimediaMode(int dVirtAudioMultimediaMode);
+#endif
+
+/*
+ * Internal API
+ */
+
+/**
+* abe_read_sys_clock() description for void abe_read_sys_clock().
+*
+*  Operations : returns the current time indication for the LOG
+*
+*  Parameter  : No parameter
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_read_sys_clock(abe_micros_t *time);
+
+/**
+* abe_fprintf() description for void abe_fprintf().
+*
+*  Operations : returns the current time indication for the LOG
+*
+*  Parameter  : No parameter
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+//void abe_fprintf(char *line);
+
+/*
+ * API as part of the HAL paper documentation
+ */
+
+/**
+* abe_reset_hal() description for void abe_reset_hal().
+*
+*  Operations : reset the HAL by reloading the static variables and default AESS registers.
+*	Called after a PRCM cold-start reset of ABE
+*
+*  Parameter  : No parameter
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_reset_hal(void);
+
+/**
+*  abe_read_use_case_opp() description for void abe_read_use_case_opp().
+*
+*  Operations : returns the expected min OPP for a given use_case list
+*
+*  Parameter  : No parameter
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_read_use_case_opp(abe_use_case_id *u, abe_opp_t *o);
+
+/**
+* abe_load_fw() description for void abe_load_fw().
+*
+*  Operations :
+*      loads the Audio Engine firmware, generate a single pulse on the Event generator
+*      to let execution start, read the version number returned from this execution.
+*
+*  Parameter  : No parameter
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code in case the firmware does not start.
+*
+* @see
+*/
+void abe_load_fw(void);
+
+/**
+* abe_read_port_address() description for void abe_read_port_address().
+*
+*  Operations :
+*      This API returns the address of the DMA register used on this audio port.
+*
+*  Parameter  : No parameter
+* @param	dma : output pointer to the DMA iteration and data destination pointer
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_read_port_address(abe_port_id port, abe_dma_t *dma);
+
+/**
+* abe_default_configuration() description for void abe_default_configuration().
+*
+*  Parameter  :
+*      use-case-ID : "LP player", "voice-call" use-cases as defined in the paragraph
+*      "programming use-case sequences"
+*      param1, 2, 3, 4 : two parameters to be used later during FW06 integration
+*
+*  Operations :
+*      private API used during development. Loads all the necessary parameters and data
+*      patterns to allow a stand-alone functional test without the need of.
+*
+*  Parameter  : No parameter
+* @param	dma : output pointer to the DMA iteration and data destination pointer
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_default_configuration(abe_uint32 use_case);
+
+/**
+* abe_irq_processing() description for void abe_irq_processing().
+*
+*  Parameter  :
+*      No parameter
+*
+*  Operations :
+*      This subroutine will check the IRQ_FIFO from the AE and act accordingly.
+*      Some IRQ source are originated for the delivery of "end of time sequenced tasks"
+*      notifications, some are originated from the Ping-Pong protocols, some are generated from
+*      the embedded debugger when the firmware stops on programmable break-points, etc …
+*
+* @param	dma : output pointer to the DMA iteration and data destination pointer
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_irq_processing(void);
+
+/**
+* abe_write_event_generator () description for void abe_event_generator_switch().
+*
+*  Operations :
+*      load the AESS event generator hardware source. Loads the firmware parameters
+*      accordingly. Indicates to the FW which data stream is the most important to preserve
+*      in case all the streams are asynchronous. If the parameter is "default", let the HAL
+*      decide which Event source is the best appropriate based on the opened ports.
+*
+* @param	e: Event Generation Counter, McPDM, DMIC or default.
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_write_event_generator(abe_event_id e);
+
+/**
+* abe_read_lowest_opp() description for void abe_read_lowest_opp().
+*
+*  Operations :
+*      Returns the lowest possible OPP based on the current active ports.
+*
+* @param	o: returned data
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_read_lowest_opp(abe_opp_t *o);
+
+/**
+* abe_set_opp_processing() description for void abe_set_opp_processing().
+*
+*  Parameter  :
+*      New processing network and OPP:
+*	  0: Ultra Lowest power consumption audio player (no post-processing, no mixer);
+*	  1: OPP 25% (simple multimedia features, including low-power player);
+*	  2: OPP 50% (multimedia and voice calls);
+*	  3: OPP100% (EANC, multimedia complex use-cases);
+*
+*  Operations :
+*      Rearranges the FW task network to the corresponding OPP list of features.
+*      The corresponding AE ports are supposed to be set/reset accordingly before this switch.
+*
+* @param	o: desired opp
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_set_opp_processing(abe_opp_t opp);
+
+/**
+* abe_set_ping_pong_bufferg() description for void abe_set_ping_pong_buffer().
+*
+*  Parameter  :
+*      Port_ID :
+*      Pointer name : Read or Write pointer
+*      New data
+*
+*  Operations :
+*      Updates the ping-pong read/write pointer with the input data.
+*
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_set_ping_pong_buffer(abe_port_id port, abe_uint32 n);
+
+/**
+* @fn abe_connect_irq_ping_pong_port()
+*
+*  Operations : enables the data echanges between a direct access to the DMEM
+*       memory of ABE using cache flush. On each IRQ activation a subroutine
+*       registered with "abe_plug_subroutine" will be called. This subroutine
+*       will generate an amount of samples, send them to DMEM memory and call
+*       "abe_set_ping_pong_buffer" to notify the new amount of samples in the
+*       pong buffer.
+*
+*    Parameters :
+*       id: port name
+*       f : desired data format
+*       I : index of the call-back subroutine to call
+*       s : half-buffer (ping) size
+*
+*       p: returned base address of the first (ping) buffer)
+*
+* @see	ABE_API.h
+*/
+void abe_connect_irq_ping_pong_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d,
+				abe_uint32 s, abe_uint32 *p, abe_uint32 dsp_mcu_flag);
+
+/**
+* abe_plug_subroutine() description for void abe_plug_subroutine().
+*
+* Parameter :
+*  id: returned sequence index after plugging a new subroutine
+*  f : subroutine address to be inserted
+*
+*  Operations :
+*      register a list of subroutines for call-back purpose.
+*
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_plug_subroutine(abe_uint32 *id, abe_subroutine2 f, abe_uint32 n, abe_uint32 *params);
+
+/**
+* abe_plug_sequence() description for void abe_plug_sequence().
+*
+ *  Parameter  :
+ *       Id: returned sequence index after pluging a new sequence (index in the tables);
+ *       s : sequence to be inserted
+ *
+ *  Operations :
+ *      Load a list a time-sequenced operations.
+*
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_plug_sequence(abe_uint32 *id, abe_sequence_t *s);
+
+/**
+* abe_launch_sequence() description for void abe_launch_sequence().
+*
+*  Parameter  :
+*      Sequence index
+*
+*  Operations :
+*      Launch a list a time-sequenced operations.
+*
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_launch_sequence(abe_patch_rev patch, abe_uint32 n);
+
+/**
+* abe_launch_sequence_param() description for void abe_launch_sequence_param().
+*
+*  Parameter  :
+*      Sequence index
+*      Parameters to the programmable sequence
+*
+*  Operations :
+*      Launch a list a time-sequenced operations.
+*
+* @param
+*
+* @pre	  no pre-condition
+*
+* @post
+*
+* @return       error code
+*
+* @see
+*/
+void abe_launch_sequence_param(abe_patch_rev patch, abe_uint32 n, abe_int32 *param1, abe_int32 *param2, abe_int32 *param3, abe_int32 *param4);;
+
+/*
+ *  ABE_RESET_PORT
+ *
+ *  Parameters :
+ *  id: port name
+ *
+ *  Returned value : error code
+ *
+ *  Operations : stop the port activity and reload default parameters on the associated processing features.
+ *
+ */
+void abe_reset_port(abe_port_id id);
+
+/*
+ *  ABE_READ_REMAINING_DATA
+ *
+ *  Parameter  :
+ *      Port_ID :
+ *      size : pointer to the remaining number of 32bits words
+ *
+ *  Operations :
+ *      computes the remaining amount of data in the buffer.
+ *
+ *  Return value :
+ *      error code
+ */
+void abe_read_remaining_data(abe_port_id port, abe_uint32 *n);
+
+/*
+ *  ABE_DISABLE_DATA_TRANSFER
+ *
+ *  Parameter  :
+ *      p: port indentifier
+ *
+ *  Operations :
+ *      disables the ATC descriptor
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_disable_data_transfer (abe_port_id p);
+
+/*
+ *  ABE_ENABLE_DATA_TRANSFER
+ *
+ *  Parameter  :
+ *      p: port indentifier
+ *
+ *  Operations :
+ *      enables the ATC descriptor
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_enable_data_transfer(abe_port_id p);
+
+/*
+ *  ABE_SET_DMIC_FILTER
+ *
+ *  Parameter  :
+ *      DMIC decimation ratio : 16/25/32/40
+ *
+ *  Operations :
+ *      Loads in CMEM a specific list of coefficients depending on the DMIC sampling
+ *      frequency (2.4MHz or 3.84MHz);. This table compensates the DMIC decimator roll-off at 20kHz.
+ *      The default table is loaded with the DMIC 2.4MHz recommended configuration.
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_set_dmic_filter(abe_dmic_ratio_t d);
+
+/**
+* @fn abe_connect_cbpr_dmareq_port()
+*
+*  Operations : enables the data echange between a DMA and the ABE through the
+*       CBPr registers of AESS.
+*
+*   Parameters :
+*   id: port name
+*   f : desired data format
+*   d : desired dma_request line (0..7)
+*   a : returned pointer to the base address of the CBPr register and number of
+*       samples to exchange during a DMA_request.
+*
+* @see	ABE_API.h
+*/
+void abe_connect_cbpr_dmareq_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_dma_t *a);
+
+/**
+* @fn abe_connect_dmareq_port()
+*
+*  Operations : enables the data echange between a DMA and the ABE through the
+*       CBPr registers of AESS.
+*
+*   Parameters :
+*   id: port name
+*   f : desired data format
+*   d : desired dma_request line (0..7)
+*   a : returned pointer to the base address of the ping-pong buffer and number
+*       of samples to exchange during a DMA_request..
+*
+* @see	ABE_API.h
+*/
+void abe_connect_dmareq_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_dma_t *a);
+
+/**
+* @fn abe_connect_dmareq_ping_pong_port()
+*
+*  Operations : enables the data echanges between a DMA and a direct access to the
+*       DMEM memory of ABE. On each dma_request activation the DMA will exchange "s"
+*       bytes and switch to the "pong" buffer for a new buffer exchange.ABE
+*
+*    Parameters :
+*    id: port name
+*    f : desired data format
+*    d : desired dma_request line (0..7)
+*    s : half-buffer (ping) size
+*
+*    a : returned pointer to the base address of the ping-pong buffer and number of samples to exchange during a DMA_request.
+*
+* @see	ABE_API.h
+*/
+void abe_connect_dmareq_ping_pong_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_uint32 s, abe_dma_t *a);
+
+/**
+* @fn abe_connect_serial_port()
+*
+*  Operations : enables the data echanges between a McBSP and an ATC buffer in
+*   DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz
+*   voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
+*   abe_write_port API.
+*
+*   Parameters :
+*    id: port name
+*    f : data format
+*    i : peripheral ID (McBSP #1, #2, #3)
+*
+* @see	ABE_API.h
+*/
+void abe_connect_serial_port(abe_port_id id, abe_data_format_t *f, abe_mcbsp_id i);
+
+/*
+ *  ABE_WRITE_GAIN
+ *
+ *  Parameter  :
+ *      port : name of the port (VX_DL_PORT, MM_DL_PORT, MM_EXT_DL_PORT, TONES_DL_PORT, …);
+ *      dig_gain_port pointer to returned port gain and time constant
+ *
+ *  Operations :
+ *      saves the gain data in the local HAL-L0 table of gains in native format.
+ *      Translate the gain to the AE-FW format and load it in CMEM
+ *
+ *  Return value :
+ *      error code in case the gain_id is not compatible with the current OPP value.
+ */
+
+void abe_write_gain(abe_gain_id id, abe_gain_t f_g, abe_ramp_t f_ramp, abe_port_id p);
+
+/*
+ *  ABE_WRITE_EQUALIZER
+ *
+ *  Parameter  :
+ *      Id  : name of the equalizer
+ *      Param : equalizer coefficients
+ *
+ *  Operations :
+ *      Load the coefficients in CMEM. This API can be called when the corresponding equalizer
+ *      is not activated. After reloading the firmware the default coefficients corresponds to
+ *      "no equalizer feature". Loading all coefficients with zeroes disables the feature.
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_write_equalizer(abe_equ_id id, abe_equ_t *param);
+
+/*
+ * ABE_SELECT_MAIN_PORT
+ *
+ * Parameter  :
+ * id : audio port name
+ * Operations :
+ * tells the FW which is the reference stream for adjusting the processing on 23/24/25 slots
+ *
+ * Return value :
+ * None.
+ */
+void abe_select_main_port(abe_port_id id);
+
+/*
+ * ABE_WRITE_ASRC
+ *
+ *  Parameter  :
+ *      Id  : name of the asrc
+ *      param : drift value t compensate
+ *
+ *  Operations :
+ *      Load the drift coefficients in FW memory. This API can be called when the corresponding
+ *      ASRC is not activated. After reloading the firmware the default coefficients corresponds
+ *      to "no ASRC activated". Loading the drift value with zero disables the feature.
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_write_asrc(abe_asrc_id id, abe_drift_t param);
+void abe_set_asrc_drift_control(abe_asrc_id id, abe_uint32 f);
+
+/*
+ *  ABE_WRITE_APS
+ *
+ *  Parameter  :
+ *      Id  : name of the aps filter
+ *      param : table of filter coefficients
+ *
+ *  Operations :
+ *      Load the filters and thresholds coefficients in FW memory. This API can be called when
+ *      the corresponding APS is not activated. After reloading the firmware the default coefficients
+ *      corresponds to "no APS activated". Loading all the coefficients value with zero disables
+ *      the feature.
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_write_aps(abe_aps_id id, abe_aps_t *param);
+
+/*
+ *  ABE_WRITE_MIXER
+ *
+ *  Parameter  :
+ *  Id  : name of the mixer
+ *  param : list of input gains of the mixer
+ *  p : list of ports corresponding to the above gains
+ *
+ *  Operations :
+ *      Load the gain coefficients in FW memory. This API can be called when the corresponding
+ *      MIXER is not activated. After reloading the firmware the default coefficients corresponds
+ *      to "all input and output mixer's gain in mute state". A mixer is disabled with a network
+ *      reconfiguration corresponding to an OPP value.
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_write_mixer(abe_mixer_id id, abe_gain_t g, abe_ramp_t ramp, abe_port_id p);
+
+/*
+ *  ABE_SET_ROUTER_CONFIGURATION
+ *
+ *  Parameter  :
+ *      Id  : name of the router
+ *      Conf : id of the configuration
+ *      param : list of output index of the route
+ *
+ *  Operations :
+ *      The uplink router takes its input from DMIC (6 samples), AMIC (2 samples) and
+ *      PORT1/2 (2 stereo ports). Each sample will be individually stored in an intermediate
+ *      table of 10 elements. The intermediate table is used to route the samples to
+ *      three directions : REC1 mixer, 2 EANC DMIC source of filtering and MM recording audio path.
+ *      For example, a use case consisting in AMIC used for uplink voice communication, DMIC 0,1,2,3
+ *      used for multimedia recording, , DMIC 5 used for EANC filter, DMIC 4 used for the feedback channel,
+ *      will be implemented with the following routing table index list :
+ *      [3, 2 , 1, 0, 0, 0 (two dummy indexes to data that will not be on MM_UL), 4, 5, 7, 6]
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_set_router_configuration(abe_router_id id, abe_uint32 configuration, abe_router_t *param);
+
+/*
+ *  ABE_READ_DEBUG_TRACE
+ *
+ *  Parameter  :
+ *      data destination pointer
+ *      max number of data read
+ *
+ *  Operations :
+ *      reads the AE circular data pointer holding pairs of debug data+timestamps, and store
+ *      the pairs in linear addressing to the parameter pointer. Stops the copy when the max
+ *	parameter is reached or when the FIFO is empty.
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_read_debug_trace(abe_uint32 *data, abe_uint32 *n);
+
+/*
+ *  ABE_SET_DEBUG_TRACE
+ *
+ *  Parameter  :
+ *      debug ID from a list to be defined
+ *
+ *  Operations :
+ *      load a mask which filters the debug trace to dedicated types of data
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_set_debug_trace(abe_dbg_t debug);
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _ABE_API_H_ */
diff --git a/sound/soc/codecs/abe/abe_cm_addr.h b/sound/soc/codecs/abe/abe_cm_addr.h
new file mode 100644
index 000000000000..2f56b3dcc1c7
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_cm_addr.h
@@ -0,0 +1,346 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_CM_ADDR_H_
+#define _ABE_CM_ADDR_H_
+
+#define init_CM_ADDR			0
+#define init_CM_ADDR_END		284
+#define init_CM_sizeof			285
+
+#define C_Data_LSB_2_ADDR		285
+#define C_Data_LSB_2_ADDR_END		285
+#define C_Data_LSB_2_sizeof		1
+
+#define C_1_Alpha_ADDR			286
+#define C_1_Alpha_ADDR_END		303
+#define C_1_Alpha_sizeof		18
+
+#define C_Alpha_ADDR			304
+#define C_Alpha_ADDR_END		321
+#define C_Alpha_sizeof			18
+
+#define C_GainsWRamp_ADDR		322
+#define C_GainsWRamp_ADDR_END		335
+#define C_GainsWRamp_sizeof		14
+
+#define C_Gains_DL1M_ADDR		336
+#define C_Gains_DL1M_ADDR_END		339
+#define C_Gains_DL1M_sizeof		4
+
+#define C_Gains_DL2M_ADDR		340
+#define C_Gains_DL2M_ADDR_END		343
+#define C_Gains_DL2M_sizeof		4
+
+#define C_Gains_EchoM_ADDR		344
+#define C_Gains_EchoM_ADDR_END		345
+#define C_Gains_EchoM_sizeof		2
+
+#define C_Gains_SDTM_ADDR		346
+#define C_Gains_SDTM_ADDR_END		347
+#define C_Gains_SDTM_sizeof		2
+
+#define C_Gains_VxRecM_ADDR		348
+#define C_Gains_VxRecM_ADDR_END		351
+#define C_Gains_VxRecM_sizeof		4
+
+#define C_Gains_ULM_ADDR		352
+#define C_Gains_ULM_ADDR_END		355
+#define C_Gains_ULM_sizeof		4
+
+#define C_Gains_unused_ADDR		356
+#define C_Gains_unused_ADDR_END		357
+#define C_Gains_unused_sizeof		2
+
+#define C_SDT_Coefs_ADDR		358
+#define C_SDT_Coefs_ADDR_END		366
+#define C_SDT_Coefs_sizeof		9
+
+#define C_CoefASRC1_VX_ADDR		367
+#define C_CoefASRC1_VX_ADDR_END		385
+#define C_CoefASRC1_VX_sizeof		19
+
+#define C_CoefASRC2_VX_ADDR		386
+#define C_CoefASRC2_VX_ADDR_END		404
+#define C_CoefASRC2_VX_sizeof		19
+
+#define C_CoefASRC3_VX_ADDR		405
+#define C_CoefASRC3_VX_ADDR_END		423
+#define C_CoefASRC3_VX_sizeof		19
+
+#define C_CoefASRC4_VX_ADDR		424
+#define C_CoefASRC4_VX_ADDR_END		442
+#define C_CoefASRC4_VX_sizeof		19
+
+#define C_CoefASRC5_VX_ADDR		443
+#define C_CoefASRC5_VX_ADDR_END		461
+#define C_CoefASRC5_VX_sizeof		19
+
+#define C_CoefASRC6_VX_ADDR		462
+#define C_CoefASRC6_VX_ADDR_END		480
+#define C_CoefASRC6_VX_sizeof		19
+
+#define C_CoefASRC7_VX_ADDR		481
+#define C_CoefASRC7_VX_ADDR_END		499
+#define C_CoefASRC7_VX_sizeof		19
+
+#define C_CoefASRC8_VX_ADDR		500
+#define C_CoefASRC8_VX_ADDR_END		518
+#define C_CoefASRC8_VX_sizeof		19
+
+#define C_CoefASRC9_VX_ADDR		519
+#define C_CoefASRC9_VX_ADDR_END		537
+#define C_CoefASRC9_VX_sizeof		19
+
+#define C_CoefASRC10_VX_ADDR		538
+#define C_CoefASRC10_VX_ADDR_END	556
+#define C_CoefASRC10_VX_sizeof		19
+
+#define C_CoefASRC11_VX_ADDR		557
+#define C_CoefASRC11_VX_ADDR_END	575
+#define C_CoefASRC11_VX_sizeof		19
+
+#define C_CoefASRC12_VX_ADDR		576
+#define C_CoefASRC12_VX_ADDR_END	594
+#define C_CoefASRC12_VX_sizeof		19
+
+#define C_CoefASRC13_VX_ADDR		595
+#define C_CoefASRC13_VX_ADDR_END	613
+#define C_CoefASRC13_VX_sizeof		19
+
+#define C_CoefASRC14_VX_ADDR		614
+#define C_CoefASRC14_VX_ADDR_END	632
+#define C_CoefASRC14_VX_sizeof		19
+
+#define C_CoefASRC15_VX_ADDR		633
+#define C_CoefASRC15_VX_ADDR_END	651
+#define C_CoefASRC15_VX_sizeof		19
+
+#define C_CoefASRC16_VX_ADDR		652
+#define C_CoefASRC16_VX_ADDR_END	670
+#define C_CoefASRC16_VX_sizeof		19
+
+#define C_AlphaCurrent_UL_VX_ADDR	671
+#define C_AlphaCurrent_UL_VX_ADDR_END	671
+#define C_AlphaCurrent_UL_VX_sizeof	1
+
+#define C_BetaCurrent_UL_VX_ADDR	672
+#define C_BetaCurrent_UL_VX_ADDR_END	672
+#define C_BetaCurrent_UL_VX_sizeof	1
+
+#define C_AlphaCurrent_DL_VX_ADDR	673
+#define C_AlphaCurrent_DL_VX_ADDR_END	673
+#define C_AlphaCurrent_DL_VX_sizeof	1
+
+#define C_BetaCurrent_DL_VX_ADDR	674
+#define C_BetaCurrent_DL_VX_ADDR_END	674
+#define C_BetaCurrent_DL_VX_sizeof	1
+
+#define C_CoefASRC1_DL_MM_ADDR		675
+#define C_CoefASRC1_DL_MM_ADDR_END	692
+#define C_CoefASRC1_DL_MM_sizeof	18
+
+#define C_CoefASRC2_DL_MM_ADDR		693
+#define C_CoefASRC2_DL_MM_ADDR_END	710
+#define C_CoefASRC2_DL_MM_sizeof	18
+
+#define C_CoefASRC3_DL_MM_ADDR		711
+#define C_CoefASRC3_DL_MM_ADDR_END	728
+#define C_CoefASRC3_DL_MM_sizeof	18
+
+#define C_CoefASRC4_DL_MM_ADDR		729
+#define C_CoefASRC4_DL_MM_ADDR_END	746
+#define C_CoefASRC4_DL_MM_sizeof	18
+
+#define C_CoefASRC5_DL_MM_ADDR		747
+#define C_CoefASRC5_DL_MM_ADDR_END	764
+#define C_CoefASRC5_DL_MM_sizeof	18
+
+#define C_CoefASRC6_DL_MM_ADDR		765
+#define C_CoefASRC6_DL_MM_ADDR_END	782
+#define C_CoefASRC6_DL_MM_sizeof	18
+
+#define C_CoefASRC7_DL_MM_ADDR		783
+#define C_CoefASRC7_DL_MM_ADDR_END	800
+#define C_CoefASRC7_DL_MM_sizeof	18
+
+#define C_CoefASRC8_DL_MM_ADDR		801
+#define C_CoefASRC8_DL_MM_ADDR_END	818
+#define C_CoefASRC8_DL_MM_sizeof	18
+
+#define C_CoefASRC9_DL_MM_ADDR		819
+#define C_CoefASRC9_DL_MM_ADDR_END	836
+#define C_CoefASRC9_DL_MM_sizeof	18
+
+#define C_CoefASRC10_DL_MM_ADDR		837
+#define C_CoefASRC10_DL_MM_ADDR_END	854
+#define C_CoefASRC10_DL_MM_sizeof	18
+
+#define C_CoefASRC11_DL_MM_ADDR		855
+#define C_CoefASRC11_DL_MM_ADDR_END	872
+#define C_CoefASRC11_DL_MM_sizeof	18
+
+#define C_CoefASRC12_DL_MM_ADDR		873
+#define C_CoefASRC12_DL_MM_ADDR_END	890
+#define C_CoefASRC12_DL_MM_sizeof	18
+
+#define C_CoefASRC13_DL_MM_ADDR		891
+#define C_CoefASRC13_DL_MM_ADDR_END	908
+#define C_CoefASRC13_DL_MM_sizeof	18
+
+#define C_CoefASRC14_DL_MM_ADDR		909
+#define C_CoefASRC14_DL_MM_ADDR_END	926
+#define C_CoefASRC14_DL_MM_sizeof	18
+
+#define C_CoefASRC15_DL_MM_ADDR		927
+#define C_CoefASRC15_DL_MM_ADDR_END	944
+#define C_CoefASRC15_DL_MM_sizeof	18
+
+#define C_CoefASRC16_DL_MM_ADDR		945
+#define C_CoefASRC16_DL_MM_ADDR_END	962
+#define C_CoefASRC16_DL_MM_sizeof	18
+
+#define C_AlphaCurrent_DL_MM_ADDR	963
+#define C_AlphaCurrent_DL_MM_ADDR_END	963
+#define C_AlphaCurrent_DL_MM_sizeof	1
+
+#define C_BetaCurrent_DL_MM_ADDR	964
+#define C_BetaCurrent_DL_MM_ADDR_END	964
+#define C_BetaCurrent_DL_MM_sizeof	1
+
+#define C_DL2_L_Coefs_ADDR		965
+#define C_DL2_L_Coefs_ADDR_END		989
+#define C_DL2_L_Coefs_sizeof		25
+
+#define C_DL2_R_Coefs_ADDR		990
+#define C_DL2_R_Coefs_ADDR_END		1014
+#define C_DL2_R_Coefs_sizeof		25
+
+#define C_DL1_Coefs_ADDR		1015
+#define C_DL1_Coefs_ADDR_END		1039
+#define C_DL1_Coefs_sizeof		25
+
+#define C_VX_8_48_BP_Coefs_ADDR		1040
+#define C_VX_8_48_BP_Coefs_ADDR_END	1052
+#define C_VX_8_48_BP_Coefs_sizeof	13
+
+#define C_VX_8_48_LP_Coefs_ADDR		1053
+#define C_VX_8_48_LP_Coefs_ADDR_END	1065
+#define C_VX_8_48_LP_Coefs_sizeof	13
+
+#define C_VX_48_8_LP_Coefs_ADDR		1066
+#define C_VX_48_8_LP_Coefs_ADDR_END	1078
+#define C_VX_48_8_LP_Coefs_sizeof	13
+
+#define C_VX_16_48_HP_Coefs_ADDR	1079
+#define C_VX_16_48_HP_Coefs_ADDR_END	1085
+#define C_VX_16_48_HP_Coefs_sizeof	7
+
+#define C_VX_16_48_LP_Coefs_ADDR	1086
+#define C_VX_16_48_LP_Coefs_ADDR_END	1098
+#define C_VX_16_48_LP_Coefs_sizeof	13
+
+#define C_VX_48_16_LP_Coefs_ADDR	1099
+#define C_VX_48_16_LP_Coefs_ADDR_END	1111
+#define C_VX_48_16_LP_Coefs_sizeof	13
+
+#define C_EANC_WarpCoeffs_ADDR		1112
+#define C_EANC_WarpCoeffs_ADDR_END	1113
+#define C_EANC_WarpCoeffs_sizeof	2
+
+#define C_EANC_FIRcoeffs_ADDR		1114
+#define C_EANC_FIRcoeffs_ADDR_END	1134
+#define C_EANC_FIRcoeffs_sizeof		21
+
+#define C_EANC_IIRcoeffs_ADDR		1135
+#define C_EANC_IIRcoeffs_ADDR_END	1151
+#define C_EANC_IIRcoeffs_sizeof		17
+
+#define C_EANC_FIRcoeffs_2nd_ADDR	1152
+#define C_EANC_FIRcoeffs_2nd_ADDR_END	1172
+#define C_EANC_FIRcoeffs_2nd_sizeof	21
+
+#define C_EANC_IIRcoeffs_2nd_ADDR	1173
+#define C_EANC_IIRcoeffs_2nd_ADDR_END	1189
+#define C_EANC_IIRcoeffs_2nd_sizeof	17
+
+#define C_APS_DL1_coeffs1_ADDR		1190
+#define C_APS_DL1_coeffs1_ADDR_END	1198
+#define C_APS_DL1_coeffs1_sizeof	9
+
+#define C_APS_DL1_M_coeffs2_ADDR	1199
+#define C_APS_DL1_M_coeffs2_ADDR_END	1201
+#define C_APS_DL1_M_coeffs2_sizeof	3
+
+#define C_APS_DL1_C_coeffs2_ADDR	1202
+#define C_APS_DL1_C_coeffs2_ADDR_END	1204
+#define C_APS_DL1_C_coeffs2_sizeof	3
+
+#define C_APS_DL2_L_coeffs1_ADDR	1205
+#define C_APS_DL2_L_coeffs1_ADDR_END	1213
+#define C_APS_DL2_L_coeffs1_sizeof	9
+
+#define C_APS_DL2_R_coeffs1_ADDR	1214
+#define C_APS_DL2_R_coeffs1_ADDR_END	1222
+#define C_APS_DL2_R_coeffs1_sizeof	9
+
+#define C_APS_DL2_L_M_coeffs2_ADDR		1223
+#define C_APS_DL2_L_M_coeffs2_ADDR_END		1225
+#define C_APS_DL2_L_M_coeffs2_sizeof		3
+
+#define C_APS_DL2_R_M_coeffs2_ADDR		1226
+#define C_APS_DL2_R_M_coeffs2_ADDR_END		1228
+#define C_APS_DL2_R_M_coeffs2_sizeof		3
+
+#define C_APS_DL2_L_C_coeffs2_ADDR		1229
+#define C_APS_DL2_L_C_coeffs2_ADDR_END		1231
+#define C_APS_DL2_L_C_coeffs2_sizeof		3
+
+#define C_APS_DL2_R_C_coeffs2_ADDR		1232
+#define C_APS_DL2_R_C_coeffs2_ADDR_END		1234
+#define C_APS_DL2_R_C_coeffs2_sizeof		3
+
+#define C_AlphaCurrent_ECHO_REF_ADDR		1235
+#define C_AlphaCurrent_ECHO_REF_ADDR_END	1235
+#define C_AlphaCurrent_ECHO_REF_sizeof		1
+
+#define C_BetaCurrent_ECHO_REF_ADDR		1236
+#define C_BetaCurrent_ECHO_REF_ADDR_END		1236
+#define C_BetaCurrent_ECHO_REF_sizeof		1
+
+#define C_APS_DL1_EQ_ADDR			1237
+#define C_APS_DL1_EQ_ADDR_END			1245
+#define C_APS_DL1_EQ_sizeof			9
+
+#define C_APS_DL2_L_EQ_ADDR			1246
+#define C_APS_DL2_L_EQ_ADDR_END			1254
+#define C_APS_DL2_L_EQ_sizeof			9
+
+#define C_APS_DL2_R_EQ_ADDR			1255
+#define C_APS_DL2_R_EQ_ADDR_END			1263
+#define C_APS_DL2_R_EQ_sizeof			9
+
+#define C_Vibra2_consts_ADDR			1264
+#define C_Vibra2_consts_ADDR_END		1267
+#define C_Vibra2_consts_sizeof			4
+
+#define C_Vibra1_coeffs_ADDR			1268
+#define C_Vibra1_coeffs_ADDR_END		1278
+#define C_Vibra1_coeffs_sizeof			11
+
+#define C_48_96_LP_Coefs_ADDR			1279
+#define C_48_96_LP_Coefs_ADDR_END		1293
+#define C_48_96_LP_Coefs_sizeof			15
+
+#define C_98_48_LP_Coefs_ADDR			1294
+#define C_98_48_LP_Coefs_ADDR_END		1312
+#define C_98_48_LP_Coefs_sizeof			19
+
+#endif /* _ABECM_ADDR_H_ */
diff --git a/sound/soc/codecs/abe/abe_cof.h b/sound/soc/codecs/abe/abe_cof.h
new file mode 100644
index 000000000000..322b9ccae138
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_cof.h
@@ -0,0 +1,32 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+const abe_int32 abe_dmic_40[C_98_48_LP_Coefs_sizeof] = {
+	-4119413, -192384, -341428, -348088, -151380, 151380,
+	348088, 341428, 192384, 4119415, 1938156, -6935719,
+	775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982
+	};
+
+const abe_int32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof] = {
+	 -4119413, -192384, -341428, -348088, -151380, 151380,
+	348088, 341428, 192384, 4119415, 1938156, -6935719,
+	775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982
+	};
+
+const abe_int32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof] = {
+	-4119413, -192384, -341428, -348088, -151380, 151380,
+	348088, 341428, 192384, 4119415, 1938156, -6935719,
+	775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982
+	};
+const abe_int32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof] = {
+	-4119413, -192384, -341428, -348088, -151380, 151380,
+	348088, 341428, 192384, 4119415, 1938156, -6935719,
+	775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982
+	};
+
diff --git a/sound/soc/codecs/abe/abe_dat.h b/sound/soc/codecs/abe/abe_dat.h
new file mode 100644
index 000000000000..ab2ef4217f2e
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_dat.h
@@ -0,0 +1,1300 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_DAT_H_
+#define _ABE_DAT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Callbacks
+ */
+abe_subroutine2 callbacks[MAXCALLBACK];	/* 2 parameters subroutine pointers */
+
+abe_port_t abe_port[MAXNBABEPORTS];	/* list of ABE ports */
+
+const abe_port_t abe_port_init[MAXNBABEPORTS] = {
+/* status, data format, drift, callback, io-task buffer 1, io-task buffer 2,
+ * protocol, dma offset, features, name
+ * - Features reseted at start
+ */
+
+	/* DMIC */
+	{
+		IDLE_P,
+		{96000, SIX_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		0,
+		0,
+		{
+			SNK_P,
+			DMIC_PORT_PROT,
+			{{
+				dmem_dmic,
+				dmem_dmic_size,
+				DMIC_ITER
+			}},
+		},
+		{0, 0},
+		{EQMIC, 0},
+		"DMIC",
+	},
+	/* PDM_UL */
+	{
+		IDLE_P,
+		{96000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_amic,
+		0,
+		{
+			SNK_P,
+			MCPDMUL_PORT_PROT,
+			{{
+				dmem_amic,
+				dmem_amic_size,
+				MCPDM_UL_ITER,
+			}},
+		},
+		{0, 0},
+		{EQMIC, 0},
+		"PDM_UL",
+	},
+	/* BT_VX_UL */
+	{
+		IDLE_P,
+		{8000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_bt_vx_ul,
+		0,
+		{
+			SNK_P,
+			SERIAL_PORT_PROT,
+			{{
+				MCBSP1_DMA_TX * ATC_SIZE,
+				dmem_bt_vx_ul,
+				dmem_bt_vx_ul_size,
+				1 * SCHED_LOOP_8kHz,
+			}},
+		},
+		{0, 0},
+		{0},
+		"BT_VX_UL",
+	},
+	/* MM_UL */
+	{
+		IDLE_P,
+		{48000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_mm_ul,
+		0,
+		{
+			SRC_P,
+			DMAREQ_PORT_PROT,
+			{{
+				CBPr_DMA_RTX3 * ATC_SIZE,
+				dmem_mm_ul,
+				dmem_mm_ul_size,
+				10 * SCHED_LOOP_48kHz,
+				ABE_DMASTATUS_RAW,
+				1 << 3,
+			}},
+		},
+		{CIRCULAR_BUFFER_PERIPHERAL_R__3, 120},
+		{UPROUTE, 0},
+		"MM_UL",
+	},
+	/* MM_UL2 */
+	{
+		IDLE_P,
+		{48000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_mm_ul2,
+		0,
+		{
+			SRC_P,
+			DMAREQ_PORT_PROT,
+			{{
+				CBPr_DMA_RTX4 * ATC_SIZE,
+				dmem_mm_ul2,
+				dmem_mm_ul2_size,
+				2 * SCHED_LOOP_48kHz,
+				ABE_DMASTATUS_RAW,
+				1 << 4,
+			}},
+		},
+		{CIRCULAR_BUFFER_PERIPHERAL_R__4, 24},
+		{UPROUTE, 0},
+		"MM_UL2",
+	},
+	/* VX_UL */
+	{
+		IDLE_P,
+		{8000, MONO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_vx_ul,
+		0,
+		{
+			SRC_P,
+			DMAREQ_PORT_PROT,
+			{{
+				CBPr_DMA_RTX2*ATC_SIZE,
+				dmem_vx_ul,
+				dmem_vx_ul_size / 2,
+				1 * SCHED_LOOP_8kHz,
+				ABE_DMASTATUS_RAW,
+				1 << 2,
+			}},
+		},
+		{CIRCULAR_BUFFER_PERIPHERAL_R__2, 2},
+		{ASRC2, 0},
+		"VX_UL",
+	},
+	/* MM_DL */
+	{
+		IDLE_P,
+		{48000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_mm_dl_opp100,
+		0,
+		{
+			SNK_P,
+			PINGPONG_PORT_PROT,
+			{{
+				CBPr_DMA_RTX0 * ATC_SIZE,
+				dmem_mm_dl,
+				dmem_mm_dl_size,
+				2 * SCHED_LOOP_48kHz,
+				ABE_DMASTATUS_RAW,
+				1 << 0,
+			}},
+		},
+		{CIRCULAR_BUFFER_PERIPHERAL_R__0, 24},
+		{ASRC3, 0},
+		"MM_DL",
+	},
+	/* VX_DL */
+	{
+		IDLE_P,
+		{8000, MONO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_vx_dl,
+		0,
+		{
+			SNK_P,
+			DMAREQ_PORT_PROT,
+			{{
+				CBPr_DMA_RTX1 * ATC_SIZE,
+				dmem_vx_dl,
+				dmem_vx_dl_size,
+				1 * SCHED_LOOP_8kHz,
+				ABE_DMASTATUS_RAW,
+				1 << 1,
+			}},
+		},
+		{CIRCULAR_BUFFER_PERIPHERAL_R__1, 2},
+		{ASRC1, 0},
+		"VX_DL",
+	},
+	/* TONES_DL */
+	{
+		IDLE_P,
+		{48000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_tones_dl,
+		0,
+		{
+			SNK_P,
+			DMAREQ_PORT_PROT,
+			{{
+				CBPr_DMA_RTX5 * ATC_SIZE,
+				dmem_tones_dl,
+				dmem_tones_dl_size,
+				2 * SCHED_LOOP_48kHz,
+				ABE_DMASTATUS_RAW,
+				1 << 5,
+			}},
+		},
+		{CIRCULAR_BUFFER_PERIPHERAL_R__5, 24},
+		{0},
+		"TONES_DL",
+	},
+	/* VIB_DL */
+	{
+		IDLE_P,
+		{24000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_vib,
+		0,
+		{
+			SNK_P,
+			DMAREQ_PORT_PROT,
+			{{
+				CBPr_DMA_RTX6 * ATC_SIZE,
+				dmem_vib_dl,
+				dmem_vib_dl_size,
+				2 * SCHED_LOOP_24kHz,
+				ABE_DMASTATUS_RAW,
+				1 << 6,
+			}},
+		},
+		{CIRCULAR_BUFFER_PERIPHERAL_R__6, 12},
+		{0},
+		"VIB_DL",
+	},
+	/* BT_VX_DL */
+	{
+		IDLE_P,
+		{8000, MONO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_bt_vx_dl,
+		0,
+		{
+			SRC_P,
+			SERIAL_PORT_PROT,
+			{{
+				MCBSP1_DMA_RX * ATC_SIZE,
+				dmem_bt_vx_dl,
+				dmem_bt_vx_dl_size,
+				1 * SCHED_LOOP_8kHz,
+			}},
+		},
+		{0, 0},
+		{0},
+		"BT_VX_DL",
+	},
+	/* PDM_DL1 */
+	{
+		IDLE_P,
+		{96000, SIX_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		0,
+		0,
+		{
+			SRC_P,
+			MCPDMDL_PORT_PROT,
+			{{
+				dmem_mcpdm,
+				dmem_mcpdm_size,
+			}},
+		},
+		{0, 0},
+		{MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R, 0},
+		"PDM_DL",
+	},
+	/* MM_EXT_OUT */
+	{
+		IDLE_P,
+		{48000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_mm_ext_out,
+		0,
+		{
+			SRC_P,
+			SERIAL_PORT_PROT,
+			{{
+				MCBSP1_DMA_TX * ATC_SIZE,
+				dmem_mm_ext_out,
+				dmem_mm_ext_out_size,
+				2 * SCHED_LOOP_48kHz,
+			}},
+		},
+		{0, 0},
+		{0},
+		"MM_EXT_OUT",
+	},
+	/* MM_EXT_IN */
+	{
+		IDLE_P,
+		{48000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_mm_ext_in,
+		0,
+		{
+			SRC_P,
+			SERIAL_PORT_PROT,
+			{{
+				MCBSP1_DMA_RX * ATC_SIZE,
+				dmem_mm_ext_in,
+				dmem_mm_ext_in_size,
+				2 * SCHED_LOOP_48kHz,
+			}},
+		},
+		{0, 0},
+		{0},
+		"MM_EXT_IN",
+	},
+#if 0
+	/* SCHD_DBG_PORT */
+	{
+		IDLE_P,
+		{48000, STEREO_MSB},
+		NODRIFT,
+		NOCALLBACK,
+		smem_mm_trace,
+		0,
+		{
+			SRC_P,
+			DMAREQ_PORT_PROT,
+			{{
+				CBPr_DMA_RTX7 * ATC_SIZE,
+				dmem_mm_trace,
+				dmem_mm_trace_size,
+				2 * SCHED_LOOP_48kHz,
+				DEFAULT_THR_WRITE,
+				ABE_DMASTATUS_RAW,
+				1 << 4,
+			}},
+		},
+		{CIRCULAR_BUFFER_PERIPHERAL_R__7, 24},
+		{SEQUENCE, CONTROL, GAINS, 0},
+		"SCHD_DBG",
+	},
+#endif
+};
+
+const	abe_port_info_t abe_port_info[MAXNBABEPORTS] = {
+	/* DMIC */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* PDM_UL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* BT_VX_UL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* MM_UL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* MM_UL2 */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* VX_UL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* MM_DL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_MIXER, {MM_DL_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* VX_DL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* TONES_DL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* VIB_DL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* BT_VX_DL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* PDM_DL */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* MM_EXT_OUT */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/* MM_EXT_IN */
+	{
+		ABE_OPP50,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	/*
+	SCHD_DBG_PORT
+	{
+		ABE_OPP25,
+		{SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}},
+		{0, {0, 0, 0, 0}}
+	},
+	*/
+};
+
+/*
+ * Firmware features
+ */
+abe_feature_t all_feature[MAXNBFEATURE];
+
+const abe_feature_t all_feature_init[] = {
+/* on_reset, off, read, write, status, input, output, slots, opp, name */
+	/* EQ1: equalizer downlink path headset + earphone */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq1,
+		c_write_eq1,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP25,
+		"  DLEQ1",
+	},
+	/* EQ2L: equalizer downlink path integrated handsfree left */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq2,
+		c_write_eq2,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP100,
+		"  DLEQ2L",
+	},
+	/* EQ2R: equalizer downlink path integrated handsfree right */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP100,
+		"  DLEQ2R",
+	},
+	/* EQSDT: equalizer downlink path side-tone */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  EQSDT",
+	},
+	/* EQDMIC1: SRC+equalizer uplink DMIC 1st pair */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  EQDMIC1",
+	},
+	/* EQDMIC2: SRC+equalizer uplink DMIC 2nd pair */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  EQDMIC2",
+	},
+	/* EQDMIC3: SRC+equalizer uplink DMIC 3rd pair */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  EQDMIC3",
+	},
+	/* EQAMIC: SRC+equalizer uplink AMIC */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  EQAMIC",
+	},
+	/* APS1: Acoustic protection for headset */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP25,
+		"  APS1",
+	},
+	/* APS2: acoustic protection high-pass filter for handsfree left */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP100,
+		"  APS2",
+	},
+	/* APS3: acoustic protection high-pass filter for handsfree right */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP100,
+		"  APS3",
+	},
+	/* ASRC1: asynchronous sample-rate-converter for the downlink voice path */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  ASRC_VXDL"
+	},
+	/* ASRC2: asynchronous sample-rate-converter for the uplink voice path */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  ASRC_VXUL",
+	},
+	/* ASRC3: asynchronous sample-rate-converter for the multimedia player */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP100,
+		"  ASRC_MMDL",
+	},
+	/* ASRC4: asynchronous sample-rate-converter for the echo reference */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  ASRC_ECHO",
+	},
+	/* MXDL1: mixer of the headset and earphone path */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP25,
+		"  MIX_DL1",
+	},
+	/* MXDL2: mixer of the hands-free path */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP100,
+		"  MIX_DL2",
+	},
+	/* MXAUDUL: mixer for uplink tone mixer */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  MXSAUDUL",
+	},
+	/* MXVXREC: mixer for voice recording */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  MXVXREC",
+	},
+	/* MXSDT: mixer for side-tone */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  MIX_SDT",
+	},
+	/* MXECHO: mixer for echo reference */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  MIX_ECHO",
+	},
+	/* UPROUTE: router of the uplink path */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP50,
+		"  DLEQ3",
+	},
+	/* GAINS: all gains */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP25,
+		"  DLEQ3",
+	},
+	/* EANC: active noise canceller */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP100,
+		"  DLEQ3",
+	},
+	/* SEQ: sequencing queue of micro tasks */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP25,
+		"  DLEQ3",
+	},
+	/* CTL: Phoenix control queue through McPDM */
+	{
+		c_feat_init_eq,
+		c_feat_init_eq,
+		c_feat_read_eq3,
+		c_write_eq3,
+		0,
+		0x1000,
+		0x1010,
+		2,
+		0,
+		ABE_OPP25,
+		"  DLEQ3",
+	},
+};
+
+/*
+ * Memory mapping of DMEM FIFOs
+ */
+abe_uint32 abe_map_dmem[LAST_PORT_ID];			/* DMEM port map */
+abe_uint32 abe_map_dmem_secondary[LAST_PORT_ID];
+abe_uint32 abe_map_dmem_size[LAST_PORT_ID];		/* DMEM port buffer sizes */
+
+/*
+ * AESS/ATC destination and source address translation
+ * (except McASPs) from the original 64bits words address
+ */
+const abe_uint32 abe_atc_dstid[ABE_ATC_DESC_SIZE >> 3] = {
+	/* DMA_0 DMIC  PDM_DL  PDM_UL  McB1TX  McB1RX  McB2TX  McB2RX  0-7 */
+	0,      0,      12,     0,      1,      0,      2,      0,
+	/* McB3TX  McB3RX  SLIMT0  SLIMT1  SLIMT2  SLIMT3  SLIMT4  SLIMT5	 8-15 */
+	3,      0,      4,      5,      6,      7,      8,      9,
+	/* SLIMT6  SLIMT7  SLIMR0  SLIMR1  SLIMR2  SLIMR3  SLIMR4  SLIMR5	16-23 */
+	10,     11,     0,      0,      0,      0,      0,      0,
+	/* SLIMR6  SLIMR7  McASP1X ------  ------  McASP1R -----   ------  24-31 */
+	0,      0,      14,     0,      0,      0,      0,      0,
+	/* CBPrT0  CBPrT1  CBPrT2  CBPrT3  CBPrT4  CBPrT5  CBPrT6  CBPrT7  32-39 */
+	63,     63,     63,     63,     63,     63,     63,     63,
+	/* CBP_T0  CBP_T1  CBP_T2  CBP_T3  CBP_T4  CBP_T5  CBP_T6  CBP_T7	40-47 */
+	0,      0,      0,      0,      0,      0,      0,      0,
+	/* CBP_T8  CBP_T9  CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 CBP_T15	48-63 */
+	0,      0,      0,      0,      0,      0,      0,      0,
+};
+
+const abe_uint32 abe_atc_srcid[ABE_ATC_DESC_SIZE >> 3] = {
+	/* DMA_0   DMIC    PDM_DL  PDM_UL  McB1TX  McB1RX  McB2TX  McB2RX   0-7 */
+	0,      12,     0,      13,     0,      1,      0,      2,
+	/* McB3TX  McB3RX  SLIMT0  SLIMT1  SLIMT2  SLIMT3  SLIMT4  SLIMT5   8-15 */
+	0,      3,      0,      0,      0,      0,      0,      0,
+	/* SLIMT6  SLIMT7  SLIMR0  SLIMR1  SLIMR2  SLIMR3  SLIMR4  SLIMR5  16-23 */
+	0,      0,      4,      5,      6,      7,      8,      9,
+	/* SLIMR6  SLIMR7  McASP1X ------  ------  McASP1R ------  ------  24-31 */
+	10,     11,     0,      0,      0,      14,     0,      0,
+	/* CBPrT0  CBPrT1  CBPrT2  CBPrT3  CBPrT4  CBPrT5  CBPrT6  CBPrT7  32-39 */
+	63,     63,     63,     63,     63,     63,     63,     63,
+	/* CBP_T0  CBP_T1  CBP_T2  CBP_T3  CBP_T4  CBP_T5  CBP_T6  CBP_T7  40-47 */
+	0,      0,      0,      0,      0,      0,      0,      0,
+	/* CBP_T8  CBP_T9  CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 CBP_T15 48-63 */
+	0,      0,      0,      0,      0,      0,      0,      0,
+};
+
+/*
+ * Router tables
+ */
+const abe_router_t abe_router_ul_table_preset[NBROUTE_CONFIG][NBROUTE_UL] = {
+	/* Voice uplink with Phoenix microphones - Uproute config_dmic1 */
+	{
+		/* 0  .. 9   = MM_UL */
+		DMIC1_L_labelID,
+		DMIC1_R_labelID,
+		DMIC2_L_labelID,
+		DMIC2_R_labelID,
+		DMIC3_L_labelID,
+		DMIC3_R_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		/* 10 .. 11  = MM_UL2 */
+		AMIC_L_labelID,
+		AMIC_R_labelID,
+		/* 12 .. 13  = VX_UL */
+		AMIC_L_labelID,
+		AMIC_R_labelID,
+		/* 14 .. 15  = RESERVED */
+		ZERO_labelID,
+		ZERO_labelID,
+	},
+	/* Voice uplink with the first DMIC pair - Uproute config_dmic2 */
+	{
+		/* 0  .. 9   = MM_UL */
+		DMIC2_L_labelID,
+		DMIC2_R_labelID,
+		DMIC3_L_labelID,
+		DMIC3_R_labelID,
+		DMIC1_L_labelID,
+		DMIC1_R_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		/* 10 .. 11  = MM_UL2 */
+		DMIC1_L_labelID,
+		DMIC1_R_labelID,
+		/* 12 .. 13  = VX_UL */
+		DMIC1_L_labelID,
+		DMIC1_R_labelID,
+		/* 14 .. 15  = RESERVED */
+		ZERO_labelID,
+		ZERO_labelID,
+	},
+	/* Voice uplink with the second DMIC pair - Uproute config_dmic3 */
+	{
+		/* 0  .. 9   = MM_UL */
+		DMIC3_L_labelID,
+		DMIC3_R_labelID,
+		DMIC1_L_labelID,
+		DMIC1_R_labelID,
+		DMIC2_L_labelID,
+		DMIC2_R_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		/* 10 .. 11  = MM_UL2 */
+		DMIC2_L_labelID,
+		DMIC2_R_labelID,
+		/* 12 .. 13  = VX_UL */
+		DMIC2_L_labelID,
+		DMIC2_R_labelID,
+		/* 14 .. 15  = RESERVED */
+		ZERO_labelID,
+		ZERO_labelID,
+	},
+	/* VOICE UPLINK WITH THE LAST DMIC PAIR - UPROUTE_CONFIG_DMIC3 */
+	{
+		AMIC_L_labelID,	/* 0  .. 9 = MM_UL */
+		AMIC_R_labelID,
+		DMIC2_L_labelID,
+		DMIC2_R_labelID,
+		DMIC3_L_labelID,
+		DMIC3_R_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		DMIC3_L_labelID,
+		DMIC3_R_labelID,	/* 10 .. 11  = MM_UL2 */
+		DMIC3_L_labelID,
+		DMIC3_R_labelID,	/* 12 .. 13  = VX_UL */
+		ZERO_labelID,
+		ZERO_labelID,		/* 14 .. 15  = RESERVED */
+	},
+	/* VOICE UPLINK WITH THE BT - UPROUTE_CONFIG_BT */
+	{
+		BT_UL_L_labelID,
+		BT_UL_R_labelID,
+		DMIC2_L_labelID,
+		DMIC2_R_labelID,	/* 0  .. 9	 = MM_UL */
+		DMIC3_L_labelID,
+		DMIC3_R_labelID,
+		DMIC1_L_labelID,
+		DMIC1_R_labelID,
+		ZERO_labelID,
+		ZERO_labelID,
+		AMIC_L_labelID,
+		AMIC_R_labelID,		/* 10 .. 11  = MM_UL2 */
+		BT_UL_L_labelID,
+		BT_UL_R_labelID,	/* 12 .. 13  = VX_UL */
+		ZERO_labelID,
+		ZERO_labelID,		/* 14 .. 15  = RESERVED */
+	},
+};
+
+/* all default routing configurations */
+abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL];
+
+/*
+ * ABE_GLOBAL DATA
+ */
+/* flag, indicates the allowed control of Phoenix through McPDM slot 6 */
+abe_uint32 abe_global_mcpdm_control;
+abe_event_id abe_current_event_id;
+
+/*
+ * ABE SUBROUTINES AND SEQUENCES
+ */
+
+/*
+const abe_seq_t abe_seq_array [MAXNBSEQUENCE] [MAXSEQUENCESTEPS] =
+	   {{0,      0,      0,      0}, {-1, 0, 0, 0}},
+	   {{0,      0,      0,      0}, {-1, 0, 0, 0}},
+const seq_t setup_hw_sequence2 [ ] = { 0, C_AE_FUNC1,  0, 0, 0, 0,
+				      -1, C_CALLBACK1, 0, 0, 0, 0 };
+
+const abe_subroutine2 abe_sub_array [MAXNBSUBROUTINE] =
+	    abe_init_atc,   0,      0,
+	    abe_init_atc,   0,      0,
+
+ typedef double (*PtrFun) (double);
+PtrFun pFun;
+pFun = sin;
+y = (* pFun) (x);
+*/
+
+const abe_sequence_t seq_null =	{
+	NOMASK,
+	{
+		CL_M1,
+		0,
+		{0, 0, 0, 0},
+		0,
+	},
+	{
+		CL_M1,
+		0,
+		{0, 0, 0, 0},
+		0,
+	},
+};
+
+/* table of new subroutines called in the sequence */
+abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE];
+/* number of parameters per calls */
+abe_uint32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE];
+/* index of the subroutine */
+abe_uint32 abe_subroutine_id[MAXNBSUBROUTINE];
+abe_uint32* abe_all_subroutine_params[MAXNBSUBROUTINE];
+abe_uint32 abe_subroutine_write_pointer;
+
+/* table of all sequences */
+abe_sequence_t abe_all_sequence[MAXNBSEQUENCE];
+
+abe_uint32 abe_sequence_write_pointer;
+
+/* current number of pending sequences (avoids to look in the table) */
+abe_uint32 abe_nb_pending_sequences;
+
+/* pending sequences due to ressource collision */
+abe_uint32 abe_pending_sequences[MAXNBSEQUENCE];
+
+/* mask of unsharable ressources among other sequences */
+abe_uint32 abe_global_sequence_mask;
+
+/* table of active sequences */
+abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS];
+
+/* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */
+abe_uint32 abe_irq_pingpong_player_id;
+/* index of the plugged subroutine doing acoustics protection adaptation */
+abe_uint32 abe_irq_aps_adaptation_id;
+
+/* base addresses of the ping pong buffers in bytes addresses */
+abe_uint32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS];
+
+/* size of each ping/pong buffers */
+abe_uint32 abe_size_pingpong;
+
+/* number of ping/pong buffer being used */
+abe_uint32 abe_nb_pingpong;
+
+/*
+ * ABE CONST AREA FOR PARAMETERS TRANSLATION
+ */
+const abe_uint32 abe_db2lin_table [sizeof_db2lin_table] = {
+	0x00000000,	/* SMEM coding of -120 dB */
+	0x00000000,	/* SMEM coding of -119 dB */
+	0x00000000,	/* SMEM coding of -118 dB */
+	0x00000000,	/* SMEM coding of -117 dB */
+	0x00000000,	/* SMEM coding of -116 dB */
+	0x00000000,	/* SMEM coding of -115 dB */
+	0x00000000,	/* SMEM coding of -114 dB */
+	0x00000000,	/* SMEM coding of -113 dB */
+	0x00000000,	/* SMEM coding of -112 dB */
+	0x00000000,	/* SMEM coding of -111 dB */
+	0x00000000,	/* SMEM coding of -110 dB */
+	0x00000000,	/* SMEM coding of -109 dB */
+	0x00000001,	/* SMEM coding of -108 dB */
+	0x00000001,	/* SMEM coding of -107 dB */
+	0x00000001,	/* SMEM coding of -106 dB */
+	0x00000001,	/* SMEM coding of -105 dB */
+	0x00000001,	/* SMEM coding of -104 dB */
+	0x00000001,	/* SMEM coding of -103 dB */
+	0x00000002,	/* SMEM coding of -102 dB */
+	0x00000002,	/* SMEM coding of -101 dB */
+	0x00000002,	/* SMEM coding of -100 dB */
+	0x00000002,	/* SMEM coding of  -99 dB */
+	0x00000003,	/* SMEM coding of  -98 dB */
+	0x00000003,	/* SMEM coding of  -97 dB */
+	0x00000004,	/* SMEM coding of  -96 dB */
+	0x00000004,	/* SMEM coding of  -95 dB */
+	0x00000005,	/* SMEM coding of  -94 dB */
+	0x00000005,	/* SMEM coding of  -93 dB */
+	0x00000006,	/* SMEM coding of  -92 dB */
+	0x00000007,	/* SMEM coding of  -91 dB */
+	0x00000008,	/* SMEM coding of  -90 dB */
+	0x00000009,	/* SMEM coding of  -89 dB */
+	0x0000000A,	/* SMEM coding of  -88 dB */
+	0x0000000B,	/* SMEM coding of  -87 dB */
+	0x0000000D,	/* SMEM coding of  -86 dB */
+	0x0000000E,	/* SMEM coding of  -85 dB */
+	0x00000010,	/* SMEM coding of  -84 dB */
+	0x00000012,	/* SMEM coding of  -83 dB */
+	0x00000014,	/* SMEM coding of  -82 dB */
+	0x00000017,	/* SMEM coding of  -81 dB */
+	0x0000001A,	/* SMEM coding of  -80 dB */
+	0x0000001D,	/* SMEM coding of  -79 dB */
+	0x00000021,	/* SMEM coding of  -78 dB */
+	0x00000025,	/* SMEM coding of  -77 dB */
+	0x00000029,	/* SMEM coding of  -76 dB */
+	0x0000002E,	/* SMEM coding of  -75 dB */
+	0x00000034,	/* SMEM coding of  -74 dB */
+	0x0000003A,	/* SMEM coding of  -73 dB */
+	0x00000041,	/* SMEM coding of  -72 dB */
+	0x00000049,	/* SMEM coding of  -71 dB */
+	0x00000052,	/* SMEM coding of  -70 dB */
+	0x0000005D,	/* SMEM coding of  -69 dB */
+	0x00000068,	/* SMEM coding of  -68 dB */
+	0x00000075,	/* SMEM coding of  -67 dB */
+	0x00000083,	/* SMEM coding of  -66 dB */
+	0x00000093,	/* SMEM coding of  -65 dB */
+	0x000000A5,	/* SMEM coding of  -64 dB */
+	0x000000B9,	/* SMEM coding of  -63 dB */
+	0x000000D0,	/* SMEM coding of  -62 dB */
+	0x000000E9,	/* SMEM coding of  -61 dB */
+	0x00000106,	/* SMEM coding of  -60 dB */
+	0x00000126,	/* SMEM coding of  -59 dB */
+	0x0000014A,	/* SMEM coding of  -58 dB */
+	0x00000172,	/* SMEM coding of  -57 dB */
+	0x0000019F,	/* SMEM coding of  -56 dB */
+	0x000001D2,	/* SMEM coding of  -55 dB */
+	0x0000020B,	/* SMEM coding of  -54 dB */
+	0x0000024A,	/* SMEM coding of  -53 dB */
+	0x00000292,	/* SMEM coding of  -52 dB */
+	0x000002E2,	/* SMEM coding of  -51 dB */
+	0x0000033C,	/* SMEM coding of  -50 dB */
+	0x000003A2,	/* SMEM coding of  -49 dB */
+	0x00000413,	/* SMEM coding of  -48 dB */
+	0x00000492,	/* SMEM coding of  -47 dB */
+	0x00000521,	/* SMEM coding of  -46 dB */
+	0x000005C2,	/* SMEM coding of  -45 dB */
+	0x00000676,	/* SMEM coding of  -44 dB */
+	0x0000073F,	/* SMEM coding of  -43 dB */
+	0x00000822,	/* SMEM coding of  -42 dB */
+	0x00000920,	/* SMEM coding of  -41 dB */
+	0x00000A3D,	/* SMEM coding of  -40 dB */
+	0x00000B7D,	/* SMEM coding of  -39 dB */
+	0x00000CE4,	/* SMEM coding of  -38 dB */
+	0x00000E76,	/* SMEM coding of  -37 dB */
+	0x0000103A,	/* SMEM coding of  -36 dB */
+	0x00001235,	/* SMEM coding of  -35 dB */
+	0x0000146E,	/* SMEM coding of  -34 dB */
+	0x000016EC,	/* SMEM coding of  -33 dB */
+	0x000019B8,	/* SMEM coding of  -32 dB */
+	0x00001CDC,	/* SMEM coding of  -31 dB */
+	0x00002061,	/* SMEM coding of  -30 dB */
+	0x00002455,	/* SMEM coding of  -29 dB */
+	0x000028C4,	/* SMEM coding of  -28 dB */
+	0x00002DBD,	/* SMEM coding of  -27 dB */
+	0x00003352,	/* SMEM coding of  -26 dB */
+	0x00003995,	/* SMEM coding of  -25 dB */
+	0x0000409C,	/* SMEM coding of  -24 dB */
+	0x0000487E,	/* SMEM coding of  -23 dB */
+	0x00005156,	/* SMEM coding of  -22 dB */
+	0x00005B43,	/* SMEM coding of  -21 dB */
+	0x00006666,	/* SMEM coding of  -20 dB */
+	0x000072E5,	/* SMEM coding of  -19 dB */
+	0x000080E9,	/* SMEM coding of  -18 dB */
+	0x000090A4,	/* SMEM coding of  -17 dB */
+	0x0000A24B,	/* SMEM coding of  -16 dB */
+	0x0000B618,	/* SMEM coding of  -15 dB */
+	0x0000CC50,	/* SMEM coding of  -14 dB */
+	0x0000E53E,	/* SMEM coding of  -13 dB */
+	0x00010137,	/* SMEM coding of  -12 dB */
+	0x0001209A,	/* SMEM coding of  -11 dB */
+	0x000143D1,	/* SMEM coding of  -10 dB */
+	0x00016B54,	/* SMEM coding of   -9 dB */
+	0x000197A9,	/* SMEM coding of   -8 dB */
+	0x0001C967,	/* SMEM coding of   -7 dB */
+	0x00020137,	/* SMEM coding of   -6 dB */
+	0x00023FD6,	/* SMEM coding of   -5 dB */
+	0x00028619,	/* SMEM coding of   -4 dB */
+	0x0002D4EF,	/* SMEM coding of   -3 dB */
+	0x00032D64,	/* SMEM coding of   -2 dB */
+	0x000390A4,	/* SMEM coding of   -1 dB */
+	0x00040000,	/* SMEM coding of    0 dB */
+	0x00047CF2,	/* SMEM coding of    1 dB */
+	0x00050923,	/* SMEM coding of    2 dB */
+	0x0005A670,	/* SMEM coding of    3 dB */
+	0x000656EE,	/* SMEM coding of    4 dB */
+	0x00071CF5,	/* SMEM coding of    5 dB */
+	0x0007FB26,	/* SMEM coding of    6 dB */
+	0x0008F473,	/* SMEM coding of    7 dB */
+	0x000A0C2B,	/* SMEM coding of    8 dB */
+	0x000B4606,	/* SMEM coding of    9 dB */
+	0x000CA62C,	/* SMEM coding of   10 dB */
+	0x000E314A,	/* SMEM coding of   11 dB */
+	0x000FEC9E,	/* SMEM coding of   12 dB */
+	0x0011DE0A,	/* SMEM coding of   13 dB */
+	0x00140C28,	/* SMEM coding of   14 dB */
+	0x00167E60,	/* SMEM coding of   15 dB */
+	0x00193D00,	/* SMEM coding of   16 dB */
+	0x001C515D,	/* SMEM coding of   17 dB */
+	0x001FC5EB,	/* SMEM coding of   18 dB */
+	0x0023A668,	/* SMEM coding of   19 dB */
+	0x00280000,	/* SMEM coding of   20 dB */
+	0x002CE178,	/* SMEM coding of   21 dB */
+	0x00325B65,	/* SMEM coding of   22 dB */
+	0x00388062,	/* SMEM coding of   23 dB */
+	0x003F654E,	/* SMEM coding of   24 dB */
+	0x00472194,	/* SMEM coding of   25 dB */
+	0x004FCF7C,	/* SMEM coding of   26 dB */
+	0x00598C81,	/* SMEM coding of   27 dB */
+	0x006479B7,	/* SMEM coding of   28 dB */
+	0x0070BC3D,	/* SMEM coding of   29 dB */
+	0x007E7DB9,	/* SMEM coding of   30 dB */
+};
+
+
+const abe_uint32 abe_sin_table [] = { 0 };
+/*
+ * ABE_DEBUG DATA
+ */
+
+/*
+ * IRQ and trace pointer in DMEM:
+ * FW updates a write pointer at "MCU_IRQ_FIFO_ptr_labelID", the read pointer is in HAL
+ */
+abe_uint32 abe_irq_dbg_read_ptr;
+
+/* General circular buffer used to trace APIs calls and AE activity */
+abe_uint32 abe_dbg_activity_log[DBG_LOG_SIZE];
+abe_uint32 abe_dbg_activity_log_write_pointer;
+abe_uint32 abe_dbg_mask;
+
+/* Global variable holding parameter errors */
+abe_uint32 abe_dbg_param;
+
+/* Output of messages selector */
+abe_uint32 abe_dbg_output;
+
+/* Last parameters */
+#define SIZE_PARAM      10
+
+abe_uint32 param1[SIZE_PARAM];
+abe_uint32 param2[SIZE_PARAM];
+abe_uint32 param3[SIZE_PARAM];
+abe_uint32 param4[SIZE_PARAM];
+abe_uint32 param5[SIZE_PARAM];
+
+volatile abe_uint32 just_to_avoid_the_many_warnings;
+volatile abe_gain_t just_to_avoid_the_many_warnings_abe_gain_t;
+volatile abe_ramp_t just_to_avoid_the_many_warnings_abe_ramp_t;
+volatile abe_dma_t just_to_avoid_the_many_warnings_abe_dma_t;
+volatile abe_port_id just_to_avoid_the_many_warnings_abe_port_id;
+volatile abe_millis_t just_to_avoid_the_many_warnings_abe_millis_t;
+volatile abe_micros_t just_to_avoid_the_many_warnings_abe_micros_t;
+volatile abe_patch_rev just_to_avoid_the_many_warnings_abe_patch_rev;
+volatile abe_sequence_t just_to_avoid_the_many_warnings_abe_sequence_t;
+volatile abe_ana_port_id just_to_avoid_the_many_warnings_abe_ana_port_id;
+volatile abe_time_stamp_t just_to_avoid_the_many_warnings_abe_time_stamp_t;
+volatile abe_data_format_t just_to_avoid_the_many_warnings_abe_data_format_t;
+volatile abe_port_protocol_t just_to_avoid_the_many_warnings_abe_port_protocol_t;
+volatile abe_router_t just_to_avoid_the_many_warnings_abe_router_t;
+volatile abe_router_id just_to_avoid_the_many_warnings_abe_router_id;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _ABE_DAT_H_ */
diff --git a/sound/soc/codecs/abe/abe_dbg.c b/sound/soc/codecs/abe/abe_dbg.c
new file mode 100644
index 000000000000..130bc067f290
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_dbg.c
@@ -0,0 +1,259 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_main.h"
+
+/*
+ *  ABE_DBG_LOG
+ *
+ *  Parameter  :
+ *      x : data to be logged
+ *
+ *      abe_dbg_activity_log : global circular buffer holding the data
+ *      abe_dbg_activity_log_write_pointer : circular write pointer
+ *
+ *  Operations :
+ *      saves data in the log file
+ *
+ *  Return value :
+ *      none
+ */
+void abe_dbg_log_copy(abe_uint32 x)
+{
+	abe_dbg_activity_log[abe_dbg_activity_log_write_pointer] = x;
+
+	if (abe_dbg_activity_log_write_pointer == (DBG_LOG_SIZE - 1))
+		abe_dbg_activity_log_write_pointer = 0;
+	else
+		abe_dbg_activity_log_write_pointer ++;
+}
+
+void abe_dbg_log(abe_uint32 x)
+{
+	abe_time_stamp_t t = 0;
+	abe_millis_t m = 0;
+	abe_micros_t time;
+
+	abe_read_sys_clock(&time);	/* extract system timer */
+
+	abe_dbg_log_copy(x);		/* dump data */
+	abe_dbg_log_copy(time);
+	abe_dbg_log_copy(t);
+	abe_dbg_log_copy(m);
+}
+
+/*
+ *  ABE_DEBUG_OUTPUT_PINS
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *      set the debug output pins of AESS
+ *
+ *  Return value :
+ *
+ */
+void abe_debug_output_pins(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+
+
+/*
+ *  ABE_DBG_ERROR_LOG
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *      log the error codes
+ *
+ *  Return value :
+ *
+ */
+void abe_dbg_error_log(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+
+/*
+ *  ABE_DEBUGGER
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_debugger(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+/*
+ *	S = power (2, 31) * 0.25;
+ *	N =  4; B = 2; F=[1/N 1/N]; gen_and_save('dbg_8k_2.txt',	B, F, N, S);
+ * 	N =  8; B = 2; F=[1/N 2/N]; gen_and_save('dbg_16k_2.txt', B, F, N, S);
+ * 	N = 12; B = 2; F=[1/N 2/N]; gen_and_save('dbg_48k_2.txt', B, F, N, S);
+ * 	N = 60; B = 2; F=[4/N 8/N]; gen_and_save('dbg_amic.txt', B, F, N, S);
+ * 	N = 10; B = 6; F=[1/N 2/N 3/N 1/N 2/N 3/N]; gen_and_save('dbg_dmic.txt', B, F, N, S);
+ */
+void abe_load_embeddded_patterns (void)
+{
+	abe_uint32 i;
+#if 0
+#define patterns_dmic_len 60
+const long patterns_dmic[patterns_dmic_len] = {	// 9.6kHZ
+	315564800, 510594560, 510594560, 315564800, 510594560, 510594560,
+	510594560, 315564800, -315565056, 510594560, 315564800, -315565056,
+	510594560, -315565056, -315565056, 510594560, -315565056, -315565056,
+	315564800, -510594816, 510594560, 315564800, -510594816, 510594560,
+	0,	-256, 0, 0, -256, 0,
+	-315565056, 510594560, -510594816, -315565056, 510594560, -510594816,
+	-510594816, 315564800, 315564800, -510594816, 315564800, 315564800,
+	-510594816, -315565056, 315564800, -510594816, -315565056, 315564800,
+	-315565056, -510594816, -510594816, -315565056, -510594816, -510594816,
+	-256, -256, -256, -256, -256, -256,
+};
+#endif
+#define patterns_mcpdm_len (6*12)
+const long patterns_mcpdm[patterns_mcpdm_len] = {
+	268435200, 464943616, 536870912, 536870912, 464943616, 268435200,
+	464943616, 464943616,0, 0, 464943616, 464943616,
+	536870912, 	0, -536870912, -536870912, 0,536870912,
+	464943616, -464943872, -256, -256, -464943872, 464943616,
+	268435456, -464943872, 536870912, 536870912, -464943872, 268435456,
+		0, -256, 0, 0, -256, 0,
+	-268435456, 464943616, -536870912, -536870912, 464943616, -268435456,
+	-464943872, 464943616, -256, -256, 464943616, -464943872,
+	-536870912, 0, 536870912, 536870912, 0, -536870912,
+	-464943872, -464943872, 0, 0, -464943872, -464943872,
+	-268435712, -464943872, -536870912, -536870912, -464943872, -268435712,
+	-256, -256, -256, -256, -256, -256,
+};
+#if 0
+#define patterns_amic_len 120
+const long patterns_amic[patterns_amic_len] = { // 6 / 12kHz
+	218364928,	398972672,
+	398972672,	533929728,
+	510594560,	315564800,
+	533929728,	-111621888,
+	464943616,	-464943872,
+	315564800,	-510594816,
+	111621632,	-218365184,
+	-111621888,	218364928,
+	-315565056,	510594560,
+	-464943872,	464943616,
+	-533929984,	111621632,
+	-510594816,	-315565056,
+	-398972928,	-533929984,
+	-218365184,	-398972928,
+	-256,			-256,
+	218364928,	398972672,
+	398972672,	533929728,
+	510594560,	315564800,
+	533929728,	-111621888,
+	464943616,	-464943872,
+	315564800,	-510594816,
+	111621632,	-218365184,
+	-111621888,	218364928,
+	-315565056,	510594560,
+	-464943872,	464943616,
+	-533929984,	111621632,
+	-510594816,	-315565056,
+	-398972928,	-533929984,
+	-218365184,	-398972928,
+	-256,			-256,
+	218364928,	398972672,
+	398972672,	533929728,
+	510594560,	315564800,
+	533929728,	-111621888,
+	464943616,	-464943872,
+	315564800,	-510594816,
+	111621632,	-218365184,
+	-111621888,	218364928,
+	-315565056,	510594560,
+	-464943872,	464943616,
+	-533929984,	111621632,
+	-510594816,	-315565056,
+	-398972928,	-533929984,
+	-218365184,	-398972928,
+	-256,			-256,
+	218364928,	398972672,
+	398972672,	533929728,
+	510594560,	315564800,
+	533929728,	-111621888,
+	464943616,	-464943872,
+	315564800,	-510594816,
+	111621632,	-218365184,
+	-111621888,	218364928,
+	-315565056,	510594560,
+	-464943872,	464943616,
+	-533929984,	111621632,
+	-510594816,	-315565056,
+	-398972928,	-533929984,
+	-218365184,	-398972928,
+	-256,			-256,
+};
+#endif
+#define patterns_48k_len 24
+const long patterns_48k[patterns_48k_len] = {	// 4kHz 8kHZ
+	268435200,	464943616,
+	464943616,	464943616,
+	536870912,		0,
+	464943616,	-464943872,
+	268435456,	-464943872,
+		0,	-256,
+	-268435456,	464943616,
+	-464943872,	464943616,
+	-536870912,		0,
+	-464943872,	-464943872,
+	-268435712,	-464943872,
+	-256,			-256,
+};
+#define patterns_16k_len 16
+const long patterns_16k[patterns_16k_len] = {	// 2kHz / 4kHz
+	379624960,	536870912,
+	536870912, 		0,
+	379624960,	-536870912,
+		0,		-256,
+	-379625216,	536870912,
+	-536870912,		0,
+	-379625216,	-536870912,
+	-256,			-256,
+};
+#define patterns_8k_len 8
+const long patterns_8k[patterns_8k_len] = { // 2kHz
+	536870912,	536870912,
+		0,		0,
+	-536870912,	-536870912,
+	-256,			-256,
+};
+
+	for(i = 0; i < patterns_mcpdm_len; i++)
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+				S_DBG_MCPDM_PATTERN_ADDR *8,
+					(abe_uint32 *)(&(patterns_mcpdm[i])), 4);
+	for(i = 0; i < patterns_16k_len; i++)
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+				S_DBG_16K_PATTERN_ADDR *8,
+					(abe_uint32 *)(&(patterns_16k[i])), 4);
+	for(i = 0; i < patterns_8k_len; i++)
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+				S_DBG_8K_PATTERN_ADDR *8,
+					(abe_uint32 *)(&(patterns_8k[i])), 4);
+	for (i = 0; i < patterns_48k_len; i++)
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+				S_DBG_48K_PATTERN_ADDR *8,
+					(abe_uint32 *)(&(patterns_48k[i])), 4);
+}
diff --git a/sound/soc/codecs/abe/abe_dbg.h b/sound/soc/codecs/abe/abe_dbg.h
new file mode 100644
index 000000000000..daecd9a7c374
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_dbg.h
@@ -0,0 +1,167 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_main.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * DEFINE
+ */
+#define NO_OUTPUT		0
+#define TERMINAL_OUTPUT		1
+#define LINE_OUTPUT		2
+#define DEBUG_TRACE_OUTPUT	3
+
+#define DBG_LOG_SIZE		1000
+
+#define DBG_BITFIELD_OFFSET	8
+
+#define DBG_API_CALLS		0
+#define DBG_MAPI		(1L << (DBG_API_CALLS + DBG_BITFIELD_OFFSET))
+
+#define DBG_EXT_DATA_ACCESS	1
+#define DBG_MDATA		(1L << (DBG_EXT_DATA_ACCESS + DBG_BITFIELD_OFFSET))
+
+#define DBG_ERR_CODES		2
+#define DBG_MERR		(1L << (DBG_API_CALLS + DBG_BITFIELD_OFFSET))
+
+/*
+ * IDs used for traces
+ */
+#define ID_RESET_HAL			(1 + DBG_MAPI)
+#define ID_LOAD_FW			(2 + DBG_MAPI)
+#define ID_DEFAULT_CONFIGURATION	(3 + DBG_MAPI)
+#define ID_IRQ_PROCESSING		(4 + DBG_MAPI)
+#define ID_EVENT_GENERATOR_SWITCH	(5 + DBG_MAPI)
+#define ID_SET_MEMORY_CONFIG		(6 + DBG_MAPI)
+#define ID_READ_LOWEST_OPP		(7 + DBG_MAPI)
+#define ID_SET_OPP_PROCESSING		(8 + DBG_MAPI)
+#define ID_SET_PING_PONG_BUFFER		(9 + DBG_MAPI)
+#define ID_PLUG_SUBROUTINE		(10 + DBG_MAPI)
+#define ID_UNPLUG_SUBROUTINE		(11 + DBG_MAPI)
+#define ID_PLUG_SEQUENCE		(12 + DBG_MAPI)
+#define ID_LAUNCH_SEQUENCE		(13 + DBG_MAPI)
+#define ID_LAUNCH_SEQUENCE_PARAM	(14 + DBG_MAPI)
+#define ID_SET_ANALOG_CONTROL		(15 + DBG_MAPI)
+#define ID_READ_ANALOG_GAIN_DL		(16 + DBG_MAPI)
+#define ID_READ_ANALOG_GAIN_UL		(17 + DBG_MAPI)
+#define ID_ENABLE_DYN_UL_GAIN		(18 + DBG_MAPI)
+#define ID_DISABLE_DYN_UL_GAIN		(19 + DBG_MAPI)
+#define ID_ENABLE_DYN_EXTENSION		(20 + DBG_MAPI)
+#define ID_DISABLE_DYN_EXTENSION	(21 + DBG_MAPI)
+#define ID_NOTIFY_ANALOG_GAIN_CHANGED	(22 + DBG_MAPI)
+#define ID_RESET_PORT			(23 + DBG_MAPI)
+#define ID_READ_REMAINING_DATA		(24 + DBG_MAPI)
+#define ID_DISABLE_DATA_TRANSFER	(25 + DBG_MAPI)
+#define ID_ENABLE_DATA_TRANSFER		(26 + DBG_MAPI)
+#define ID_READ_GLOBAL_COUNTER		(27 + DBG_MAPI)
+#define ID_SET_DMIC_FILTER		(28 + DBG_MAPI)
+#define ID_WRITE_PORT_DESCRIPTOR	(29 + DBG_MAPI)
+#define ID_READ_PORT_DESCRIPTOR		(30 + DBG_MAPI)
+#define ID_READ_PORT_ADDRESS		(31 + DBG_MAPI)
+#define ID_WRITE_PORT_GAIN		(32 + DBG_MAPI)
+#define ID_WRITE_HEADSET_OFFSET		(33 + DBG_MAPI)
+#define ID_READ_GAIN_RANGES		(34 + DBG_MAPI)
+#define ID_WRITE_EQUALIZER		(35 + DBG_MAPI)
+#define ID_WRITE_ASRC			(36 + DBG_MAPI)
+#define ID_WRITE_APS			(37 + DBG_MAPI)
+#define ID_WRITE_MIXER			(38 + DBG_MAPI)
+#define ID_WRITE_EANC			(39 + DBG_MAPI)
+#define ID_WRITE_ROUTER			(40 + DBG_MAPI)
+#define ID_READ_PORT_GAIN		(41 + DBG_MAPI)
+#define ID_READ_ASRC			(42 + DBG_MAPI)
+#define ID_READ_APS			(43 + DBG_MAPI)
+#define ID_READ_APS_ENERGY		(44 + DBG_MAPI)
+#define ID_READ_MIXER			(45 + DBG_MAPI)
+#define ID_READ_EANC			(46 + DBG_MAPI)
+#define ID_READ_ROUTER			(47 + DBG_MAPI)
+#define ID_READ_DEBUG_TRACE		(48 + DBG_MAPI)
+#define ID_SET_DEBUG_TRACE		(49 + DBG_MAPI)
+#define ID_SET_DEBUG_PINS		(50 + DBG_MAPI)
+#define ID_CALL_SUBROUTINE		(51 + DBG_MAPI)
+
+/*
+ * IDs used for error codes
+ */
+#define NOERR				0
+#define ABE_SET_MEMORY_CONFIG_ERR	(1 + DBG_MERR)
+#define ABE_BLOCK_COPY_ERR		(2 + DBG_MERR)
+#define ABE_SEQTOOLONG			(3 + DBG_MERR)
+#define ABE_BADSAMPFORMAT		(4 + DBG_MERR)
+#define ABE_SET_ATC_MEMORY_CONFIG_ERR	(5 + DBG_MERR)
+#define ABE_PROTOCOL_ERROR		(6 + DBG_MERR)
+#define ABE_PARAMETER_ERROR		(7 + DBG_MERR)
+#define ABE_PORT_REPROGRAMMING		(8 + DBG_MERR)	/* port programmed while still running */
+#define ABE_READ_USE_CASE_OPP_ERR	(9 + DBG_MERR)
+#define ABE_PARAMETER_OVERFLOW		(10 + DBG_MERR)
+
+/*
+ * IDs used for error codes
+ */
+#define ERR_LIB		(1 << 1)	/* error in the LIB.C file */
+#define ERR_API		(1 << 2)	/* error in the API.C file */
+#define ERR_INI		(1 << 3)	/* error in the INI.C file */
+#define ERR_SEQ		(1 << 4)	/* error in the SEQ.C file */
+#define ERR_DBG		(1 << 5)	/* error in the DBG.C file */
+#define ERR_EXT		(1 << 6)	/* error in the EXT.C file */
+
+/*
+ * MACROS
+ */
+#ifdef HAL_TIME_STAMP
+#define _log(x) ((x&abe_dbg_mask)?abe_dbg_log(x);   \
+		 abe_dbg_time_stamp(x);	     \
+		 abe_dbg_printf(x);		 \
+		)
+#else
+#define _log(x) {if(x&abe_dbg_mask)abe_dbg_log(x);}
+#endif
+
+/*
+ * PROTOTYPES
+ */
+
+/*
+ *  ABE_DBG_LOG
+ *
+ *  Parameter  :
+ *      x : data to be logged
+ *
+ *      abe_dbg_activity_log : global circular buffer holding the data
+ *      abe_dbg_activity_log_write_pointer : circular write pointer
+ *
+ *  Operations :
+ *      saves data in the log file
+ *
+ *  Return value :
+ *      none
+ */
+void abe_dbg_log(abe_uint32 x);
+
+/*
+ *  ABE_DBG_ERROR_LOG
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *      log the error codes
+ *
+ *  Return value :
+ *
+ */
+void abe_dbg_error_log(abe_uint32 x);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/sound/soc/codecs/abe/abe_def.h b/sound/soc/codecs/abe/abe_def.h
new file mode 100644
index 000000000000..3f7d8a5eb420
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_def.h
@@ -0,0 +1,303 @@
+/*
+ * ==========================================================================
+ *		 Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.	All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_DEF_H_
+#define _ABE_DEF_H_
+
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+
+#define ABE_DMAREQ_REGISTER(desc)	(abe_uint32 *)((desc/8) + CIRCULAR_BUFFER_PERIPHERAL_R__0)
+
+//#define ABE_SEND_DMAREQ(dma)	(*((abe_uint32 *)(ABE_ATC_BASE_ADDRESS_MPU+ABE_DMASTATUS_RAW)) = (dma))
+
+#define ABE_CBPR0_IDX		0	/* MM_DL */
+#define ABE_CBPR1_IDX		1	/* VX_DL */
+#define ABE_CBPR2_IDX		2	/* VX_UL */
+#define ABE_CBPR3_IDX		3	/* MM_UL */
+#define ABE_CBPR4_IDX		4	/* MM_UL2 */
+#define ABE_CBPR5_IDX		5	/* TONES */
+#define ABE_CBPR6_IDX		6	/* VIB */
+#define ABE_CBPR7_IDX		7	/* DEBUG/CTL */
+
+#define CIRCULAR_BUFFER_PERIPHERAL_R__0	(0x100 + ABE_CBPR0_IDX * 4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__1	(CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR1_IDX * 4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__2	(CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR2_IDX * 4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__3	(CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR3_IDX * 4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__4	(CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR4_IDX * 4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__5	(CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR5_IDX * 4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__6	(CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR6_IDX * 4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__7	(CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR7_IDX * 4)
+
+/*
+ * cache-flush mechanism
+ */
+#define NB_BYTES_CACHELINE_SHFT	4
+#define NB_BYTES_IN_CACHE_LINE	(1<<NB_BYTES_CACHELINE_SHFT) /* there are 16 bytes in each cache lines	*/
+
+/*
+ * DEFINITIONS SHARED WITH VIRTAUDIO
+ */
+
+#define UC1_LP			1	/* MP3 low-power player use-case */
+#define UC2_VOICE_CALL_AND_IHF_MMDL 2	/* enables voice ul/dl on earpiece + MM_DL on IHF */
+#define UC5_PINGPONG_MMDL	5	/* Test MM_DL with Ping-Pong */
+#define UC6_PINGPONG_MMDL_WITH_IRQ 6	/* ping-pong with IRQ instead of sDMA */
+
+#define UC31_VOICE_CALL_8KMONO		31
+#define UC32_VOICE_CALL_8KSTEREO	32
+#define UC33_VOICE_CALL_16KMONO		33
+#define UC34_VOICE_CALL_16KSTEREO	34
+#define UC35_MMDL_MONO			35
+#define UC36_MMDL_STEREO		36
+#define UC37_MMUL2_MONO			37
+#define UC38_MMUL2_STEREO		38
+
+#define UC41_____		40
+#define UC71_STOP_ALL		71	/* stop all activities */
+#define UC72_ENABLE_ALL		72	/* stop all activities */
+#define UC81_ROUTE_AMIC		81
+#define UC82_ROUTE_DMIC01	82
+#define UC83_ROUTE_DMIC23	83
+#define UC84_ROUTE_DMIC45	84
+
+#define UC91_ASRC_DRIFT1	91
+#define UC92_ASRC_DRIFT2	92
+#define UC93_EANC		93
+
+#define PING_PONG_WITH_MCU_IRQ	1
+#define PING_PONG_WITH_DSP_IRQ	2
+
+#define HAL_RESET_HAL		10	/* abe_reset_hal () */
+#define HAL_WRITE_MIXER		11	/* abe_write_mixer () */
+
+#define COPY_FROM_ABE_TO_HOST	1	/* ID used for LIB memory copy subroutines */
+#define COPY_FROM_HOST_TO_ABE	2
+
+/*
+ * INTERNAL DEFINITIONS
+ */
+
+#define CC_M1			0xFF	/* unsigned version of (-1) */
+#define CS_M1			0xFFFF	/* unsigned version of (-1) */
+#define CL_M1			0xFFFFFFFFL /* unsigned version of (-1) */
+
+#define NBEANC1			20	/* 20 Q6.26 coef for the FIR	*/
+#define NBEANC2			16	/* 16 Q6.26 coef for the IIR	*/
+
+#define NBEQ1			25	/* 24 Q6.26 coefficients	*/
+#define NBEQ2			13	/* 2x12 Q6.26 coefficients	 */
+
+#define NBAPS1			10	/* TBD APS first set of parameters	*/
+#define NBAPS2			10	/* TBD APS second set of parameters	 */
+
+#define NBMIX_AUDIO_UL		2	/* Mixer used for sending tones to the uplink voice path */
+#define NBMIX_DL1		4	/* Main downlink mixer */
+#define NBMIX_DL2		4	/* Handsfree downlink mixer */
+#define NBMIX_SDT		2	/* Side-tone mixer */
+#define NBMIX_ECHO		2	/* Echo reference mixer */
+#define NBMIX_VXREC		4	/* Voice record mixer */
+	/*
+	Mixer ID		Input port ID	Comments
+	DL1_MIXER		0		MMDL path
+				1		MMUL2 path
+				2		VXDL path
+				3		TONES path
+
+	SDT_MIXER		0		Uplink path
+				1		Downlink path
+
+	ECHO_MIXER		0		DL1_MIXER  path
+				1		DL2_MIXER path
+
+	AUDUL_MIXER		0		TONES_DL path
+				1		Uplink path
+				2		MM_DL path
+
+	VXREC_MIXER		0		TONES_DL path
+				1		VX_DL path
+				2		MM_DL path
+				3		VX_UL path
+	*/
+#define MIX_VXUL_INPUT_MM_DL	(abe_port_id)0
+#define MIX_VXUL_INPUT_TONES	(abe_port_id)1
+#define MIX_VXUL_INPUT_VX_UL	(abe_port_id)2
+#define MIX_VXUL_INPUT_VX_DL	(abe_port_id)3
+
+#define MIX_DL1_INPUT_MM_DL	(abe_port_id)0
+#define MIX_DL1_INPUT_MM_UL2	(abe_port_id)1
+#define MIX_DL1_INPUT_VX_DL	(abe_port_id)2
+#define MIX_DL1_INPUT_TONES	(abe_port_id)3
+
+#define MIX_DL2_INPUT_MM_DL	(abe_port_id)0
+#define MIX_DL2_INPUT_MM_UL2	(abe_port_id)1
+#define MIX_DL2_INPUT_VX_DL	(abe_port_id)2
+#define MIX_DL2_INPUT_TONES	(abe_port_id)3
+
+#define MIX_SDT_INPUT_UP_MIXER	(abe_port_id)0
+#define MIX_SDT_INPUT_DL1_MIXER (abe_port_id)1
+
+#define MIX_AUDUL_INPUT_MM_DL	(abe_port_id)0
+#define MIX_AUDUL_INPUT_TONES	(abe_port_id)1
+#define MIX_AUDUL_INPUT_UPLINK	(abe_port_id)2
+#define MIX_AUDUL_INPUT_VX_DL	(abe_port_id)3
+
+#define MIX_VXREC_INPUT_MM_DL	(abe_port_id)0
+#define MIX_VXREC_INPUT_TONES	(abe_port_id)1
+#define MIX_VXREC_INPUT_VX_UL	(abe_port_id)2
+#define MIX_VXREC_INPUT_VX_DL	(abe_port_id)3
+
+#define NBROUTE_UL		16	/* nb of samples to route */
+#define NBROUTE_CONFIG_MAX	10	/* 10 routing tables max */
+
+#define NBROUTE_CONFIG		5	/* 5 pre-computed routing tables */
+#define UPROUTE_CONFIG_AMIC	0	/* AMIC on VX_UL */
+#define UPROUTE_CONFIG_DMIC1	1	/* DMIC first pair on VX_UL */
+#define UPROUTE_CONFIG_DMIC2	2	/* DMIC second pair on VX_UL */
+#define UPROUTE_CONFIG_DMIC3	3	/* DMIC last pair on VX_UL */
+#define UPROUTE_CONFIG_BT	4	/* BT_UL on VX_UL */
+
+#define ABE_PMEM		1
+#define ABE_CMEM		2
+#define ABE_SMEM		3
+#define ABE_DMEM		4
+#define ABE_ATC			5
+
+#define MAXCALLBACK		100	/* call-back indexes */
+#define MAXNBSUBROUTINE		100	/* subroutines */
+
+#define MAXNBSEQUENCE		20	/* time controlled sequenced */
+#define MAXACTIVESEQUENCE	20	/* maximum simultaneous active sequences */
+#define MAXSEQUENCESTEPS	2	/* max number of steps in the sequences */
+#define MAXFEATUREPORT		12	/* max number of feature associated to a port */
+#define SUB_0_PARAM		0
+#define SUB_1_PARAM		1	/* number of parameters per sequence calls */
+#define SUB_2_PARAM		2
+#define SUB_3_PARAM		3
+#define SUB_4_PARAM		4
+
+#define FREE_LINE		0	/* active sequence mask = 0 means the line is free */
+#define NOMASK			(1 << 0) /* no ask for collision protection */
+#define MASK_PDM_OFF		(1 << 1) /* do not allow a PDM OFF during the execution of this sequence */
+#define MASK_PDM_ON		(1 << 2) /* do not allow a PDM ON during the execution of this sequence */
+
+#define NBCHARFEATURENAME	16	/* explicit name of the feature */
+#define NBCHARPORTNAME		16	/* explicit name of the port */
+#define MAXNBABEPORTS		LAST_PORT_ID /* number	of sink+source ports of the ABE */
+#define MAX_MAP_DMEM		LAST_PORT_ID
+
+#define SNK_P			ABE_ATC_DIRECTION_IN	/* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */
+#define SRC_P			ABE_ATC_DIRECTION_OUT	/* source / ouptut port */
+
+#define NODRIFT			0	/* no ASRC applied */
+#define FORCED_DRIFT_CONTROL	1	/* for abe_set_asrc_drift_control */
+#define ADPATIVE_DRIFT_CONTROL	2	/* for abe_set_asrc_drift_control */
+
+#define DOPPMODE32_OPP100	(0x00000010 | (0x00000000<<16))
+#define DOPPMODE32_OPP50	(0x0000000C | (0x0000004<<16))
+#define DOPPMODE32_OPP25	(0x0000004 | (0x0000000C<<16))
+
+/*
+ * ABE CONST AREA FOR PARAMETERS TRANSLATION
+ */
+#define min_mdb (-12000)
+#define max_mdb (  3000)
+#define sizeof_db2lin_table (1+ ((max_mdb - min_mdb)/100))
+
+#define GAIN_MAXIMUM	(abe_gain_t)3000L
+#define GAIN_24dB	(abe_gain_t)2400L
+#define GAIN_18dB		   (abe_gain_t)1800L
+#define GAIN_12dB		   (abe_gain_t)1200L
+#define GAIN_6dB		    (abe_gain_t)600L
+#define GAIN_0dB		     (abe_gain_t) 0L	    /* default gain = 1 */
+#define GAIN_M6dB		   (abe_gain_t)-600L
+#define GAIN_M12dB		  (abe_gain_t)-1200L
+#define GAIN_M18dB		  (abe_gain_t)-1800L
+#define GAIN_M24dB		  (abe_gain_t)-2400L
+#define GAIN_M30dB		  (abe_gain_t)-3000L
+#define GAIN_M40dB		  (abe_gain_t)-4000L
+#define GAIN_M50dB		  (abe_gain_t)-5000L
+#define MUTE_GAIN		 (abe_gain_t)-12000L
+
+#define RAMP_0MS	(abe_ramp_t)0L           /* ramp_t is in milli- seconds */
+#define RAMP_1MS	(abe_ramp_t)1L
+#define RAMP_2MS	(abe_ramp_t)2L
+#define RAMP_5MS        (abe_ramp_t)5L
+#define RAMP_10MS       (abe_ramp_t)10L
+#define RAMP_20MS       (abe_ramp_t)20L
+#define RAMP_50MS       (abe_ramp_t)50L
+#define RAMP_100MS      (abe_ramp_t)100L
+#define RAMP_200MS      (abe_ramp_t) 200L
+#define RAMP_500MS      (abe_ramp_t) 500L
+#define RAMP_1000MS     (abe_ramp_t) 1000L
+#define RAMP_MAXLENGTH  (abe_ramp_t) 10000L
+
+#define LINABE_TO_DECIBELS	1	/* for abe_translate_gain_format */
+#define DECIBELS_TO_LINABE	2
+#define IIRABE_TO_MICROS	1	/* for abe_translate_ramp_format */
+#define MICROS_TO_IIABE		2
+
+#define IDLE_P			1	/* port idled */
+#define RUN_P			2	/* port running */
+#define NOCALLBACK		0
+#define NOPARAMETER		0
+					/* HAL 06: those numbers may be x4 */
+#define MCPDM_UL_ITER		2	/* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */
+#define MCPDM_DL_ITER		6	/* All the McPDM FIFOs are enabled simultaneously */
+#define DMIC_ITER		6	/* All the DMIC FIFOs are enabled simultaneously */
+
+#define DEFAULT_THR_READ	1	/* port / flow management */
+#define DEFAULT_THR_WRITE	1	/* port / flow management */
+
+#define DEFAULT_CONTROL_MCPDMDL 1	/* allows control on the PDM line */
+
+#define MAX_PINGPONG_BUFFERS	2	/* TBD later if needed */
+
+/*
+ * Indexes to the subroutines
+ */
+#define SUB_WRITE_MIXER		1
+#define SUB_WRITE_PORT_GAIN	2
+
+/* OLD WAY */
+#define c_feat_init_eq		1
+#define c_feat_read_eq1		2
+#define c_write_eq1		3
+#define c_feat_read_eq2		4
+#define c_write_eq2		5
+#define c_feat_read_eq3		6
+#define c_write_eq3		7
+
+/*
+ * MACROS
+ */
+
+#define LOAD_ABEREG(reg,data)	{abe_uint32 *ocp_addr = (abe_uint32 *)((reg)+ABE_ATC_BASE_ADDRESS_MPU); *ocp_addr= (data);}
+
+#define maximum(a,b)		(((a)<(b))?(b):(a))
+#define minimum(a,b)		(((a)>(b))?(b):(a))
+#define absolute(a)		( ((a)>0) ? (a):((-1)*(a)) )
+
+// Gives 1% errors
+//#define abe_power_of_two(x) (abe_float)(1 + x*(0.69315 + x*(0.24022 + x*(0.056614 + x*(0.00975 )))))	 /* for x = [-1..+1] */
+//#define abe_log_of_two(i)   (abe_float)(-2.4983 + i*(4.0321 + i*(-2.0843 + i*(0.63 + i*(-0.0793)))))	 /* for i = [+1..+2[ */
+// Gives 0.1% errors
+//#define abe_power_of_two(xx) (abe_float)(1 + xx*(0.69314718055995 + xx*(0.24022650695909 + xx*(0.05661419083812 + xx*(0.0096258236109 )))))	/* for x = [-1..+1] */
+//#define abe_log_of_two(i)   (abe_float)(-3.02985297173966 + i*(6.07170945221999 + i*(-5.27332161514862 + i*(3.22638187067771 + i*(-1.23767101624897 + i*(0.26766043958616 + i*(-0.02490211314987)))))))   /* for i = [+1..+2[ */
+
+#if 0
+#define abe_power_of_two(xx) (abe_float)(0.9999999924494 + xx*(0.69314847688495 + xx*(0.24022677604481 + xx*(0.05549256818679 + xx*(0.00961666477618 + xx*(0.0013584351075 + xx*(0.00015654359307)))))))	/* for x = [-1..+1] */
+#define abe_log_of_two(xx)   (abe_float)(-3.02985297175803 + xx*(6.07170945229365 + xx*(-5.27332161527062 + xx*(3.22638187078450 + xx*(-1.23767101630110 + xx*(0.26766043959961 + xx*(-0.02490211315130)))))))	/* for x = [+1..+2] */
+#define abe_sine(xx)	 (abe_float)(-0.000000389441 + xx*(6.283360925789 + xx*(-0.011140658372 + xx*(-41.073653348384 + xx*(-3.121196875959 + xx*(100.619954580736 + xx*( -59.133359355846)))))))	  /* for x = [0 .. pi/2] */
+#define abe_sqrt(xx)	 (abe_float)(0.32298238417665 + xx*(0.93621865220393 + xx*(-0.36276443369703 + xx*(0.13008602653101+ xx*(-0.03017833169073 + xx*(0.00393731964847 + xx*-0.00021858629159 ))))))     /* for x = [1 .. 4] */
+#endif
+
+#endif	/* _ABE_DEF_H_ */
diff --git a/sound/soc/codecs/abe/abe_define.h b/sound/soc/codecs/abe/abe_define.h
new file mode 100644
index 000000000000..95889f84ee7b
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_define.h
@@ -0,0 +1,47 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_DEFINE_H_
+#define _ABE_DEFINE_H_
+
+#define ATC_DESCRIPTOR_NUMBER	64
+#define PROCESSING_SLOTS	25
+#define TASK_POOL_LENGTH	128
+#define MCU_IRQ			0x24
+#define DMA_REQ			0x84
+#define DSP_IRQ			0x4c
+#define IRQtag_APS		0x000a
+#define IRQtag_COUNT		0x000c
+#define IRQtag_PP		0x000d
+#define DMAreq_7		0x0080
+#define IRQ_FIFO_LENGTH		16
+#define SDT_EQ_ORDER		4
+#define DL_EQ_ORDER		12
+#define MIC_FILTER_ORDER	4
+#define GAINS_WITH_RAMP1	14
+#define GAINS_WITH_RAMP2	22
+#define GAINS_WITH_RAMP_TOTAL	36
+#define EANC_FIR_TAPS		21
+#define EANC_IIR_ORDER		8
+#define ASRC_MEMLENGTH		40
+#define ASRC_UL_VX_FIR_L	19
+#define ASRC_DL_VX_FIR_L	19
+#define ASRC_DL_MM_FIR_L	18
+#define ASRC_N_8k		2
+#define ASRC_N_16k		4
+#define ASRC_N_48k		12
+#define VIBRA_N			5
+#define VIBRA1_IIR_MEMSIZE	11
+#define SAMP_LOOP_96K		24
+#define SAMP_LOOP_48K		12
+#define SAMP_LOOP_16K		4
+#define SAMP_LOOP_8K		2
+
+#endif	/* _ABE_DEFINE_H_ */
diff --git a/sound/soc/codecs/abe/abe_dm_addr.h b/sound/soc/codecs/abe/abe_dm_addr.h
new file mode 100644
index 000000000000..17601716380d
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_dm_addr.h
@@ -0,0 +1,322 @@
+/*
+ * ==========================================================================
+ *		 Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.	All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_DM_ADDR_H_
+#define _ABE_DM_ADDR_H_
+
+#define D_atcDescriptors_ADDR				0
+#define D_atcDescriptors_ADDR_END			511
+#define D_atcDescriptors_sizeof				512
+
+#define stack_ADDR					512
+#define stack_ADDR_END					623
+#define stack_sizeof					112
+
+#define D_version_ADDR					624
+#define D_version_ADDR_END				627
+#define D_version_sizeof				4
+
+#define D_BT_DL_FIFO_ADDR				1024
+#define D_BT_DL_FIFO_ADDR_END				1503
+#define D_BT_DL_FIFO_sizeof				480
+
+#define D_BT_UL_FIFO_ADDR				1536
+#define D_BT_UL_FIFO_ADDR_END				2015
+#define D_BT_UL_FIFO_sizeof				480
+
+#define D_MM_EXT_OUT_FIFO_ADDR				2048
+#define D_MM_EXT_OUT_FIFO_ADDR_END			2527
+#define D_MM_EXT_OUT_FIFO_sizeof			480
+
+#define D_MM_EXT_IN_FIFO_ADDR				2560
+#define D_MM_EXT_IN_FIFO_ADDR_END			3039
+#define D_MM_EXT_IN_FIFO_sizeof				480
+
+#define D_MM_UL2_FIFO_ADDR				3072
+#define D_MM_UL2_FIFO_ADDR_END				3551
+#define D_MM_UL2_FIFO_sizeof				480
+
+#define D_VX_UL_FIFO_ADDR				3584
+#define D_VX_UL_FIFO_ADDR_END				4063
+#define D_VX_UL_FIFO_sizeof				480
+
+#define D_VX_DL_FIFO_ADDR				4096
+#define D_VX_DL_FIFO_ADDR_END				4575
+#define D_VX_DL_FIFO_sizeof				480
+
+#define D_DMIC_UL_FIFO_ADDR				4608
+#define D_DMIC_UL_FIFO_ADDR_END				5087
+#define D_DMIC_UL_FIFO_sizeof				480
+
+#define D_MM_UL_FIFO_ADDR				5120
+#define D_MM_UL_FIFO_ADDR_END				5599
+#define D_MM_UL_FIFO_sizeof				480
+
+#define D_MM_DL_FIFO_ADDR				5632
+#define D_MM_DL_FIFO_ADDR_END				6111
+#define D_MM_DL_FIFO_sizeof				480
+
+#define D_TONES_DL_FIFO_ADDR				6144
+#define D_TONES_DL_FIFO_ADDR_END			6623
+#define D_TONES_DL_FIFO_sizeof				480
+
+#define D_VIB_DL_FIFO_ADDR				6656
+#define D_VIB_DL_FIFO_ADDR_END				7135
+#define D_VIB_DL_FIFO_sizeof				480
+
+#define D_McPDM_DL_FIFO_ADDR				7168
+#define D_McPDM_DL_FIFO_ADDR_END			7647
+#define D_McPDM_DL_FIFO_sizeof				480
+
+#define D_McPDM_UL_FIFO_ADDR				7680
+#define D_McPDM_UL_FIFO_ADDR_END			8159
+#define D_McPDM_UL_FIFO_sizeof				480
+
+#define D_IOdescr_ADDR					8160
+#define D_IOdescr_ADDR_END				8719
+#define D_IOdescr_sizeof				560
+
+#define D_debugATCptrs_ADDR				8720
+#define D_debugATCptrs_ADDR_END				8783
+#define D_debugATCptrs_sizeof				64
+
+#define d_zero_ADDR					8784
+#define d_zero_ADDR_END					8784
+#define d_zero_sizeof					1
+
+#define dbg_trace1_ADDR					8785
+#define dbg_trace1_ADDR_END				8785
+#define dbg_trace1_sizeof				1
+
+#define dbg_trace2_ADDR					8786
+#define dbg_trace2_ADDR_END				8786
+#define dbg_trace2_sizeof				1
+
+#define dbg_trace3_ADDR					8787
+#define dbg_trace3_ADDR_END				8787
+#define dbg_trace3_sizeof				1
+
+#define D_multiFrame_ADDR				8788
+#define D_multiFrame_ADDR_END				9187
+#define D_multiFrame_sizeof				400
+
+#define D_tasksList_ADDR				9188
+#define D_tasksList_ADDR_END				11235
+#define D_tasksList_sizeof				2048
+
+#define D_idleTask_ADDR					11236
+#define D_idleTask_ADDR_END				11237
+#define D_idleTask_sizeof				2
+
+#define D_typeLengthCheck_ADDR				11238
+#define D_typeLengthCheck_ADDR_END			11239
+#define D_typeLengthCheck_sizeof			2
+
+#define D_maxTaskBytesInSlot_ADDR			11240
+#define D_maxTaskBytesInSlot_ADDR_END			11241
+#define D_maxTaskBytesInSlot_sizeof			2
+
+#define D_rewindTaskBytes_ADDR				11242
+#define D_rewindTaskBytes_ADDR_END			11243
+#define D_rewindTaskBytes_sizeof			2
+
+#define D_pCurrentTask_ADDR				11244
+#define D_pCurrentTask_ADDR_END				11245
+#define D_pCurrentTask_sizeof				2
+
+#define D_pFastLoopBack_ADDR				11246
+#define D_pFastLoopBack_ADDR_END			11247
+#define D_pFastLoopBack_sizeof				2
+
+#define D_pNextFastLoopBack_ADDR			11248
+#define D_pNextFastLoopBack_ADDR_END			11251
+#define D_pNextFastLoopBack_sizeof			4
+
+#define D_ppCurrentTask_ADDR				11252
+#define D_ppCurrentTask_ADDR_END			11253
+#define D_ppCurrentTask_sizeof				2
+
+#define D_slotCounter_ADDR				11256
+#define D_slotCounter_ADDR_END				11257
+#define D_slotCounter_sizeof				2
+
+#define D_loopCounter_ADDR				11260
+#define D_loopCounter_ADDR_END				11261
+#define D_loopCounter_sizeof				2
+
+#define D_RewindFlag_ADDR				11262
+#define D_RewindFlag_ADDR_END				11263
+#define D_RewindFlag_sizeof				2
+
+#define D_Slot23_ctrl_ADDR				11264
+#define D_Slot23_ctrl_ADDR_END				11267
+#define D_Slot23_ctrl_sizeof				4
+
+#define D_McuIrqFifo_ADDR				11268
+#define D_McuIrqFifo_ADDR_END				11331
+#define D_McuIrqFifo_sizeof				64
+
+#define D_PingPongDesc_ADDR				11332
+#define D_PingPongDesc_ADDR_END				11379
+#define D_PingPongDesc_sizeof				48
+
+#define D_PP_MCU_IRQ_ADDR				11380
+#define D_PP_MCU_IRQ_ADDR_END				11381
+#define D_PP_MCU_IRQ_sizeof				2
+
+#define D_ctrlPortFifo_ADDR				11392
+#define D_ctrlPortFifo_ADDR_END				11407
+#define D_ctrlPortFifo_sizeof				16
+
+#define D_Idle_State_ADDR				11408
+#define D_Idle_State_ADDR_END				11411
+#define D_Idle_State_sizeof				4
+
+#define D_Stop_Request_ADDR				11412
+#define D_Stop_Request_ADDR_END				11415
+#define D_Stop_Request_sizeof				4
+
+#define D_Ref0_ADDR					11416
+#define D_Ref0_ADDR_END					11417
+#define D_Ref0_sizeof					2
+
+#define D_DebugRegister_ADDR				11420
+#define D_DebugRegister_ADDR_END			11559
+#define D_DebugRegister_sizeof				140
+
+#define D_Gcount_ADDR					11560
+#define D_Gcount_ADDR_END				11561
+#define D_Gcount_sizeof					2
+
+#define D_DCcounter_ADDR				11564
+#define D_DCcounter_ADDR_END				11567
+#define D_DCcounter_sizeof				4
+
+#define D_DCsum_ADDR					11568
+#define D_DCsum_ADDR_END				11575
+#define D_DCsum_sizeof					8
+
+#define D_fastCounter_ADDR				11576
+#define D_fastCounter_ADDR_END				11579
+#define D_fastCounter_sizeof				4
+
+#define D_slowCounter_ADDR				11580
+#define D_slowCounter_ADDR_END				11583
+#define D_slowCounter_sizeof				4
+
+#define D_aUplinkRouting_ADDR				11584
+#define D_aUplinkRouting_ADDR_END			11599
+#define D_aUplinkRouting_sizeof				16
+
+#define D_VirtAudioLoop_ADDR				11600
+#define D_VirtAudioLoop_ADDR_END			11603
+#define D_VirtAudioLoop_sizeof				4
+
+#define D_AsrcVars_DL_VX_ADDR				11604
+#define D_AsrcVars_DL_VX_ADDR_END			11635
+#define D_AsrcVars_DL_VX_sizeof				32
+
+#define D_AsrcVars_UL_VX_ADDR				11636
+#define D_AsrcVars_UL_VX_ADDR_END			11667
+#define D_AsrcVars_UL_VX_sizeof				32
+
+#define D_CoefAddresses_VX_ADDR				11668
+#define D_CoefAddresses_VX_ADDR_END			11699
+#define D_CoefAddresses_VX_sizeof			32
+
+#define D_AsrcVars_DL_MM_ADDR				11700
+#define D_AsrcVars_DL_MM_ADDR_END			11731
+#define D_AsrcVars_DL_MM_sizeof				32
+
+#define D_CoefAddresses_DL_MM_ADDR			11732
+#define D_CoefAddresses_DL_MM_ADDR_END			11763
+#define D_CoefAddresses_DL_MM_sizeof			32
+
+#define D_APS_DL1_M_thresholds_ADDR			11764
+#define D_APS_DL1_M_thresholds_ADDR_END			11771
+#define D_APS_DL1_M_thresholds_sizeof			8
+
+#define D_APS_DL1_M_IRQ_ADDR				11772
+#define D_APS_DL1_M_IRQ_ADDR_END			11773
+#define D_APS_DL1_M_IRQ_sizeof				2
+
+#define D_APS_DL1_C_IRQ_ADDR				11774
+#define D_APS_DL1_C_IRQ_ADDR_END			11775
+#define D_APS_DL1_C_IRQ_sizeof				2
+
+#define D_TraceBufAdr_ADDR				11776
+#define D_TraceBufAdr_ADDR_END				11777
+#define D_TraceBufAdr_sizeof				2
+
+#define D_TraceBufOffset_ADDR				11778
+#define D_TraceBufOffset_ADDR_END			11779
+#define D_TraceBufOffset_sizeof				2
+
+#define D_TraceBufLength_ADDR				11780
+#define D_TraceBufLength_ADDR_END			11781
+#define D_TraceBufLength_sizeof				2
+
+#define D_AsrcVars_ECHO_REF_ADDR			11784
+#define D_AsrcVars_ECHO_REF_ADDR_END			11815
+#define D_AsrcVars_ECHO_REF_sizeof			32
+
+#define D_Pempty_ADDR					11816
+#define D_Pempty_ADDR_END				11819
+#define D_Pempty_sizeof					4
+
+#define D_APS_DL2_L_M_IRQ_ADDR				11820
+#define D_APS_DL2_L_M_IRQ_ADDR_END			11821
+#define D_APS_DL2_L_M_IRQ_sizeof			2
+
+#define D_APS_DL2_L_C_IRQ_ADDR				11822
+#define D_APS_DL2_L_C_IRQ_ADDR_END			11823
+#define D_APS_DL2_L_C_IRQ_sizeof			2
+
+#define D_APS_DL2_R_M_IRQ_ADDR				11824
+#define D_APS_DL2_R_M_IRQ_ADDR_END			11825
+#define D_APS_DL2_R_M_IRQ_sizeof			2
+
+#define D_APS_DL2_R_C_IRQ_ADDR				11826
+#define D_APS_DL2_R_C_IRQ_ADDR_END			11827
+#define D_APS_DL2_R_C_IRQ_sizeof			2
+
+#define D_APS_DL1_C_thresholds_ADDR			11828
+#define D_APS_DL1_C_thresholds_ADDR_END			11835
+#define D_APS_DL1_C_thresholds_sizeof			8
+
+#define D_APS_DL2_L_M_thresholds_ADDR			11836
+#define D_APS_DL2_L_M_thresholds_ADDR_END		11843
+#define D_APS_DL2_L_M_thresholds_sizeof			8
+
+#define D_APS_DL2_L_C_thresholds_ADDR			11844
+#define D_APS_DL2_L_C_thresholds_ADDR_END		11851
+#define D_APS_DL2_L_C_thresholds_sizeof			8
+
+#define D_APS_DL2_R_M_thresholds_ADDR			11852
+#define D_APS_DL2_R_M_thresholds_ADDR_END		11859
+#define D_APS_DL2_R_M_thresholds_sizeof			8
+
+#define D_APS_DL2_R_C_thresholds_ADDR			11860
+#define D_APS_DL2_R_C_thresholds_ADDR_END		11867
+#define D_APS_DL2_R_C_thresholds_sizeof			8
+
+#define D_nextMultiFrame_ADDR				11868
+#define D_nextMultiFrame_ADDR_END			11875
+#define D_nextMultiFrame_sizeof				8
+
+#define D_PING_ADDR					16384
+#define D_PING_ADDR_END					40959
+#define D_PING_sizeof					24576
+
+#define D_PONG_ADDR					40960
+#define D_PONG_ADDR_END					65535
+#define D_PONG_sizeof					24576
+
+#endif	/* _ABE_DM_ADDR_H_ */
diff --git a/sound/soc/codecs/abe/abe_ext.c b/sound/soc/codecs/abe/abe_ext.c
new file mode 100644
index 000000000000..0ca6cd1b257b
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_ext.c
@@ -0,0 +1,174 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_main.h"
+
+/*
+ *  ABE_DEFAULT_IRQ_PINGPONG_PLAYER
+ *
+ *
+ *  Operations :
+ *      generates data for the cache-flush buffer MODE 16+16
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_default_irq_pingpong_player(void)
+{
+	/* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */
+	#define N_SAMPLES_MAX ((int)(1024))
+
+	static abe_int32 idx;
+	abe_uint32 i, dst, n_samples, n_bytes;
+	abe_int32 temp [N_SAMPLES_MAX], audio_sample;
+#define DATA_SIZE 20
+	const abe_int32 audio_pattern [DATA_SIZE] =
+	{
+		0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, 9630,
+		5063, 0, -5063, -9630, -13254, -15581, -16383, -15581,
+		-13254, -9630, -5063
+	};
+
+	/* read the address of the Pong buffer */
+	abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes);
+
+	n_samples = n_bytes / 4;
+	/* generate a test pattern */
+	for (i = 0; i < n_samples; i++) {
+		audio_sample = audio_pattern [idx];
+		idx = (idx >= (DATA_SIZE-1))? 0: (idx+1);
+		temp[i] = ((audio_sample << 16) + audio_sample);
+	}
+
+	/* copy the pattern (flush it) to DMEM pointer update
+	 * not necessary here because the buffer size do not
+	 * change from one ping to the other pong
+	 */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, (abe_uint32 *)&(temp[0]), n_samples * 4);
+	abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes);
+}
+
+/*
+ * ABE_DEFAULT_IRQ_PINGPONG_PLAYER_32BITS
+ *
+ * Operations:
+ * generates data for the cache-flush buffer  MODE 32 BITS
+ * Return value:
+ * None.
+ */
+void abe_default_irq_pingpong_player_32bits(void)
+{
+/* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */
+#define N_SAMPLES_MAX ((int)(1024))
+	static abe_int32 idx;
+	abe_uint32 i, dst, n_samples, n_bytes;
+	abe_int32 temp[N_SAMPLES_MAX], audio_sample;
+#define DATA_SIZE 20 /*  t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */
+        const abe_int32 audio_pattern [DATA_SIZE] =
+	{
+		0, 5063, 9630, 13254, 15581, 16383, 15581, 13254,
+		9630, 5063, 0, -5063, -9630, -13254, -15581, -16383,
+		-15581, -13254, -9630, -5063
+	};
+
+	/* read the address of the Pong buffer */
+	abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes);
+	n_samples = n_bytes / 8;	/* each stereo sample weights 8 bytes (format 32|32) */
+
+	/* generate a test pattern */
+	for (i = 0; i < n_samples; i++) {
+		/* circular addressing */
+		audio_sample = audio_pattern[idx];
+		idx = (idx >= (DATA_SIZE-1))? 0: (idx+1);
+		temp[i*2 +0] = (audio_sample << 16);
+		temp[i*2 +1] = (audio_sample << 16);
+	}
+
+	/* copy the pattern (flush it) to DMEM pointer update
+	 * not necessary here because the buffer size do not
+	 * change from one ping to the other pong
+	 */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst,
+			(abe_uint32 *)&(temp[0]), n_samples * 4 *2);
+
+	abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes);
+}
+/*
+ * ABE_DEFAULT_IRQ_APS_ADAPTATION
+ *
+ * Operations :
+ * updates the APS filter and gain
+ *
+ * Return value :
+ * None.
+ */
+void abe_default_irq_aps_adaptation(void)
+{
+}
+
+/*
+ *  ABE_READ_SYS_CLOCK
+ *
+ *  Parameter  :
+ *      pointer to the system clock
+ *
+ *  Operations :
+ *      returns the current time indication for the LOG
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_read_sys_clock(abe_micros_t *time)
+{
+	static abe_micros_t clock;
+
+	*time = clock;
+	clock ++;
+}
+
+/*
+ *  ABE_APS_TUNING
+ *
+ *  Parameter  :
+ *
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_aps_tuning(void)
+{
+}
+
+/**
+* @fn abe_lock_executione()
+*
+*  Operations : set a spin-lock and wait in case of collision
+*
+*
+* @see	ABE_API.h
+*/
+void abe_lock_execution(void)
+{
+}
+
+/**
+* @fn abe_unlock_executione()
+*
+*  Operations : reset a spin-lock (end of subroutine)
+*
+*
+* @see	ABE_API.h
+*/
+void abe_unlock_execution(void)
+{
+}
diff --git a/sound/soc/codecs/abe/abe_ext.h b/sound/soc/codecs/abe/abe_ext.h
new file mode 100644
index 000000000000..510e707d43f6
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_ext.h
@@ -0,0 +1,165 @@
+/*
+ * ==========================================================================
+ *		 Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.	All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_EXT_H_
+#define _ABE_EXT_H_
+
+#include <linux/io.h>
+#define PC_SIMULATION		0	/* Tuning is done on PC ? */
+
+/*
+ * OS DEPENDENT MMU CONFIGURATION
+ */
+#define ABE_ATC_BASE_ADDRESS_L3		0x490F1000L	/* base address used for L3/DMA access */
+#define ABE_ATC_BASE_ADDRESS_L4		0x401F1000L	/* base address used for L4/MCU access */
+#define ABE_DMEM_BASE_ADDRESS_L3	0x49080000L	/* 64kB as seen from DMA access */
+#define ABE_DMEM_BASE_ADDRESS_L4	0x40180000L	/* 64kB as seen from MCU access */
+
+
+#if 0
+#define ABE_PMEM_BASE_ADDRESS_MPU	0x401E0000L	/*  8kB  as seen from MPU access */
+#define ABE_CMEM_BASE_ADDRESS_MPU	0x401A0000L	/*  8kB  +++++++++++++++++++++++ */
+#define ABE_SMEM_BASE_ADDRESS_MPU	0x401C0000L	/* 24kB				 */
+#define ABE_DMEM_BASE_ADDRESS_MPU	0x40180000L	/* 64kB				 */
+#define ABE_ATC_BASE_ADDRESS_MPU	0x401F1000L
+#else
+#define ABE_PMEM_BASE_ADDRESS_MPU	0x490E0000L	/* 8kB	as seen from MPU access */
+#define ABE_CMEM_BASE_ADDRESS_MPU	0x490A0000L	/* 8kB	+++++++++++++++++++++++ */
+#define ABE_SMEM_BASE_ADDRESS_MPU	0x490C0000L	/* 24kB */
+#define ABE_DMEM_BASE_ADDRESS_MPU	0x49080000L	/* 64kB */
+#define ABE_ATC_BASE_ADDRESS_MPU	0x490F1000L
+#endif
+
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+
+#define ABE_PMEM_SIZE			8192		/* PMEM SIZE in bytes (1024 words of 64 bits: : #32bits words x 4)*/
+#define ABE_CMEM_SIZE			8192		/* CMEM SIZE in bytes (2048 coeff :		#32bits words x 4)*/
+#define ABE_SMEM_SIZE			24576		/* SMEM SIZE in bytes (3072 stereo samples :	#32bits words x 4)*/
+#define ABE_DMEM_SIZE			65536L		/* DMEM SIZE in bytes */
+#define ABE_ATC_DESC_SIZE		512		/* ATC REGISTERS SIZE in bytes */
+
+
+#define ABE_MCU_IRQSTATUS_RAW		0x24		/* holds the MCU Irq signal */
+#define ABE_MCU_IRQSTATUS		0x28		/* status : clear the IRQ */
+#define ABE_DSP_IRQSTATUS_RAW		0x4C		/* holds the DSP Irq signal */
+#define ABE_DMASTATUS_RAW		0x84		/* holds the DMA req lines to the sDMA	*/
+
+
+#define EVENT_GENERATOR_COUNTER		0x68
+#define EVENT_GENERATOR_COUNTER_DEFAULT 2048	/* PLL output/desired sampling rate = (32768 * 6000)/96000 */
+#define EVENT_GENERATOR_COUNTER_44100	2229	/* PLL output/desired sampling rate = (32768 * 6000)/88400 */
+
+#define EVENT_GENERATOR_START		0x6C	/* start / stop the EVENT generator */
+#define EVENT_GENERATOR_ON		1
+#define EVENT_GENERATOR_OFF		0
+
+#define EVENT_SOURCE_SELECTION		0x70	/* selection of the EVENT generator source */
+#define EVENT_SOURCE_DMA		0
+#define EVENT_SOURCE_COUNTER		1
+
+#define AUDIO_ENGINE_SCHEDULER		0x74	/* selection of the ABE DMA req line from ATC */
+#define ABE_ATC_DMIC_DMA_REQ		1
+#define ABE_ATC_MCPDMDL_DMA_REQ		2
+#define ABE_ATC_MCPDMUL_DMA_REQ		3
+#define ABE_ATC_DIRECTION_IN		0	/* Direction=0 means input from ABE point of view */
+#define ABE_ATC_DIRECTION_OUT		1	/* Direction=1 means output from ABE point of view */
+
+/*
+ *  * DMA requests
+ *   */
+#define External_DMA_0		0	//Internal connection doesn't connect at ABE boundary
+#define DMIC_DMA_REQ		1	//Transmit request digital microphone
+#define McPDM_DMA_DL		2	//Multichannel PDM downlink
+#define McPDM_DMA_UP		3	//Multichannel PDM uplink
+#define MCBSP1_DMA_TX		4	//MCBSP module 1 - transmit request
+#define MCBSP1_DMA_RX		5	//MCBSP module 1 - receive request
+#define MCBSP2_DMA_TX		6	//MCBSP module 2 - transmit request
+#define MCBSP2_DMA_RX		7	//MCBSP module 2 - receive request
+#define MCBSP3_DMA_TX		8	//MCBSP module 3 - transmit request
+#define MCBSP3_DMA_RX		9	//MCBSP module 3 - receive request
+#define SLIMBUS1_DMA_TX0	10	//SLIMBUS module 1 - transmit request channel 0
+#define SLIMBUS1_DMA_TX1	11	//SLIMBUS module 1 - transmit request channel 1
+#define SLIMBUS1_DMA_TX2	12	//SLIMBUS module 1 - transmit request channel 2
+#define SLIMBUS1_DMA_TX3	13	//SLIMBUS module 1 - transmit request channel 3
+#define SLIMBUS1_DMA_TX4	14	//SLIMBUS module 1 - transmit request channel 4
+#define SLIMBUS1_DMA_TX5	15	//SLIMBUS module 1 - transmit request channel 5
+#define SLIMBUS1_DMA_TX6	16	//SLIMBUS module 1 - transmit request channel 6
+#define SLIMBUS1_DMA_TX7	17	//SLIMBUS module 1 - transmit request channel 7
+#define SLIMBUS1_DMA_RX0	18	//SLIMBUS module 1 - receive request channel 0
+#define SLIMBUS1_DMA_RX1	19	//SLIMBUS module 1 - receive request channel 1
+#define SLIMBUS1_DMA_RX2	20	//SLIMBUS module 1 - receive request channel 2
+#define SLIMBUS1_DMA_RX3	21	//SLIMBUS module 1 - receive request channel 3
+#define SLIMBUS1_DMA_RX4	22	//SLIMBUS module 1 - receive request channel 4
+#define SLIMBUS1_DMA_RX5	23	//SLIMBUS module 1 - receive request channel 5
+#define SLIMBUS1_DMA_RX6	24	//SLIMBUS module 1 - receive request channel 6
+#define SLIMBUS1_DMA_RX7	25	//SLIMBUS module 1 - receive request channel 7
+#define McASP1_AXEVT		26	//McASP  - Data transmit DMA request line
+#define McASP1_AREVT		29	//McASP  - Data receive DMA request line
+#define CBPr_DMA_RTX0		32	//DMA of the Circular buffer peripheral 0
+#define CBPr_DMA_RTX1		33	//DMA of the Circular buffer peripheral 1
+#define CBPr_DMA_RTX2		34	//DMA of the Circular buffer peripheral 2
+#define CBPr_DMA_RTX3		35	//DMA of the Circular buffer peripheral 3
+#define CBPr_DMA_RTX4		36	//DMA of the Circular buffer peripheral 4
+#define CBPr_DMA_RTX5		37	//DMA of the Circular buffer peripheral 5
+#define CBPr_DMA_RTX6		38	//DMA of the Circular buffer peripheral 6
+#define CBPr_DMA_RTX7		39	//DMA of the Circular buffer peripheral 7
+
+/*
+ *  * ATC DESCRIPTORS - DESTINATIONS
+ *   */
+#define DEST_DMEM_access	0x00
+#define DEST_MCBSP1_TX		0x01
+#define DEST_MCBSP2_TX		0x02
+#define DEST_MCBSP3_TX		0x03
+#define DEST_SLIMBUS1_TX0	0x04
+#define DEST_SLIMBUS1_TX1	0x05
+#define DEST_SLIMBUS1_TX2	0x06
+#define DEST_SLIMBUS1_TX3	0x07
+#define DEST_SLIMBUS1_TX4	0x08
+#define DEST_SLIMBUS1_TX5	0x09
+#define DEST_SLIMBUS1_TX6	0x0A
+#define DEST_SLIMBUS1_TX7	0x0B
+#define DEST_MCPDM_DL		0x0C
+#define DEST_MCASP_TX0		0x0D
+#define DEST_MCASP_TX1		0x0E
+#define DEST_MCASP_TX2		0x0F
+#define DEST_MCASP_TX3		0x10
+#define DEST_EXTPORT0		0x11
+#define DEST_EXTPORT1		0x12
+#define DEST_EXTPORT2		0x13
+#define DEST_EXTPORT3		0x14
+#define DEST_MCPDM_ON		0x15
+#define DEST_CBP_CBPr		0x3F
+
+/*
+ *  * ATC DESCRIPTORS - SOURCES
+ *   */
+#define SRC_DMEM_access		0x0
+#define SRC_MCBSP1_RX		0x01
+#define SRC_MCBSP2_RX		0x02
+#define SRC_MCBSP3_RX		0x03
+#define SRC_SLIMBUS1_RX0	0x04
+#define SRC_SLIMBUS1_RX1	0x05
+#define SRC_SLIMBUS1_RX2	0x06
+#define SRC_SLIMBUS1_RX3	0x07
+#define SRC_SLIMBUS1_RX4	0x08
+#define SRC_SLIMBUS1_RX5	0x09
+#define SRC_SLIMBUS1_RX6	0x0A
+#define SRC_SLIMBUS1_RX7	0x0B
+#define SRC_DMIC_UP		0x0C
+#define SRC_MCPDM_UP		0x0D
+#define SRC_MCASP_RX0		0x0E
+#define SRC_MCASP_RX1		0x0F
+#define SRC_MCASP_RX2		0x10
+#define SRC_MCASP_RX3		0x11
+#define SRC_CBP_CBPr		0x3F
+#endif	/* _ABE_EXT_H_ */
diff --git a/sound/soc/codecs/abe/abe_functionsId.h b/sound/soc/codecs/abe/abe_functionsId.h
new file mode 100644
index 000000000000..ffb8072c0ddb
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_functionsId.h
@@ -0,0 +1,80 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_FUNCTIONSID_H_
+#define _ABE_FUNCTIONSID_H_
+
+/*
+ * TASK function ID definitions
+ */
+#define C_ABE_FW_FUNCTION_IIR					0
+#define C_ABE_FW_FUNCTION_monoToStereoPack			1
+#define C_ABE_FW_FUNCTION_stereoToMonoSplit			2
+#define C_ABE_FW_FUNCTION_decimator				3
+#define C_ABE_FW_FUNCTION_OS0Fill				4
+#define C_ABE_FW_FUNCTION_mixer2				5
+#define C_ABE_FW_FUNCTION_mixer4				6
+#define C_ABE_FW_FUNCTION_inplaceGain				7
+#define C_ABE_FW_FUNCTION_EANC					8
+#define C_ABE_FW_FUNCTION_StreamRouting				9
+#define C_ABE_FW_FUNCTION_VIBRA2				10
+#define C_ABE_FW_FUNCTION_VIBRA1				11
+#define C_ABE_FW_FUNCTION_APS_core				12
+#define C_ABE_FW_FUNCTION_ASRC_DL_wrapper			13
+#define C_ABE_FW_FUNCTION_ASRC_UL_wrapper			14
+#define C_ABE_FW_FUNCTION_gainConverge				15
+#define C_ABE_FW_FUNCTION_dualIir				16
+#define C_ABE_FW_FUNCTION_EANC_wrapper				17
+#define C_ABE_FW_FUNCTION_DCoffset				18
+#define C_ABE_FW_FUNCTION_DCoffset2				19
+#define C_ABE_FW_FUNCTION_IO_DL_pp				20
+#define C_ABE_FW_FUNCTION_EANCUpdateOutSample			21
+#define C_ABE_FW_FUNCTION_VX_DL_8_48_wrapper			22
+#define C_ABE_FW_FUNCTION_VX_UL_48_8_wrapper			23
+#define C_ABE_FW_FUNCTION_VX_DL_16_48_wrapper			24
+#define C_ABE_FW_FUNCTION_VX_UL_48_16_wrapper			25
+#define C_ABE_FW_FUNCTION_BT_UL_8_48_wrapper			26
+#define C_ABE_FW_FUNCTION_BT_DL_48_8_wrapper			27
+#define C_ABE_FW_FUNCTION_BT_UL_16_48_wrapper			28
+#define C_ABE_FW_FUNCTION_BT_DL_48_16_wrapper			29
+#define C_ABE_FW_FUNCTION_ECHO_REF_48_8_wrapper			30
+#define C_ABE_FW_FUNCTION_ECHO_REF_48_16_wrapper		31
+#define C_ABE_FW_FUNCTION_IO_generic2				32
+#define C_ABE_FW_FUNCTION_irq_fifo_debug			33
+#define C_ABE_FW_FUNCTION_synchronize_pointers			34
+#define C_ABE_FW_FUNCTION_IIR_SRC_MIC				35
+#define C_ABE_FW_FUNCTION_APS_FEEDBACK_DL1_wrapper		36
+#define C_ABE_FW_FUNCTION_APS_FEEDBACK_DL2_L_wrapper		37
+#define C_ABE_FW_FUNCTION_APS_FEEDBACK_DL2_R_wrapper		38
+
+/*
+ * COPY function ID definitions
+ */
+#define NULL_COPY_CFPID			0
+#define COPY_D2S_LR_CFPID		1
+#define COPY_D2S_2_CFPID		2
+#define COPY_D2S_MONO_CFPID		3
+#define COPY_S1D_MONO_CFPID		4
+#define COPY_S2D_MONO_CFPID		5
+#define COPY_S2D_2_CFPID		6
+#define COPY_DMIC_CFPID			7
+#define COPY_MCPDM_DL_CFPID		8
+#define COPY_MM_UL_CFPID		9
+#define SPLIT_SMEM_CFPID		10
+#define MERGE_SMEM_CFPID		11
+#define SPLIT_TDM_12_CFPID		12
+#define MERGE_TDM_12_CFPID		13
+#define ROUTE_MM_UL_CFPID		14
+#define IO_DMAREQ_CFPID			15
+#define IO_IP_CFPID			16
+#define COPY_S2D_MONOS16_CFPID		17
+#define COPY_S2D_2S16_CFPID		18
+
+#endif	/* _ABE_FUNCTIONSID_H_ */
diff --git a/sound/soc/codecs/abe/abe_fw.h b/sound/soc/codecs/abe/abe_fw.h
new file mode 100644
index 000000000000..f13975300584
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_fw.h
@@ -0,0 +1,454 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_cm_addr.h"
+#include "abe_sm_addr.h"
+#include "abe_dm_addr.h"
+#include "abe_typedef.h"
+
+/*
+ * GLOBAL DEFINITION
+ */
+#define FW_SCHED_LOOP_FREQ		4000	/* one scheduler loop = 4kHz = 12 samples at 48kHz */
+#define EVENT_FREQUENCY			96000
+#define SLOTS_IN_SCHED_LOOP		(96000/FW_SCHED_LOOP_FREQ)
+
+#define SCHED_LOOP_8kHz			( 8000/FW_SCHED_LOOP_FREQ)
+#define SCHED_LOOP_16kHz		(16000/FW_SCHED_LOOP_FREQ)
+#define SCHED_LOOP_24kHz		(24000/FW_SCHED_LOOP_FREQ)
+#define SCHED_LOOP_48kHz		(48000/FW_SCHED_LOOP_FREQ)
+
+#define TASKS_IN_SLOT			8
+/*
+ * DMEM AREA - SCHEDULER
+ */
+#define smem_mm_trace			0
+#define dmem_mm_trace			D_debugATCptrs_ADDR
+#define dmem_mm_trace_size		((D_debugATCptrs_ADDR_END-D_debugATCptrs_ADDR+1)/4)
+
+
+#define ATC_SIZE			8   /* 8 bytes per descriptors */
+
+typedef struct {
+	unsigned rdpt:7;	/* first 32bits word of the descriptor */
+	unsigned reserved0:1;
+	unsigned cbsize:7;
+	unsigned irqdest:1;
+	unsigned cberr:1;
+	unsigned reserved1:5;
+	unsigned cbdir:1;
+	unsigned nw:1;
+	unsigned wrpt:7;
+	unsigned reserved2:1;
+	unsigned badd:12;	/* second 32bits word of the descriptor */
+	unsigned iter:7;	/*  iteration field overlaps the 16 bits boundary */
+	unsigned srcid:6;
+	unsigned destid:6;
+	unsigned desen:1;
+} abe_satcdescriptor_aess;
+
+/*
+ *  table of scheduler tasks :
+ *  char scheduler_table[24 x 4] : four bytes used at OPP100%
+ */
+#define dmem_scheduler_table		D_multiFrame_ADDR
+
+#define dmem_eanc_task_pointer		D_pFastLoopBack_ADDR
+
+/*
+ *  OPP value :
+ *  pointer increment steps in the scheduler table
+ */
+#define dmem_scheduler_table_step	D_taskStep_ADDR
+
+/*
+ *  table of scheduler tasks (max 64) :
+ *  char task_descriptors[64 x 8] : eight bytes per task
+ *     TASK INDEX, INITPTR 1,2,3, INITREG, Loop Counter, Reserved 1,2
+ */
+#define dmem_task_descriptor		D_tasksList_ADDR
+
+/*
+ *  table of task function addresses:
+ *  short task_function_descriptors[32 x 1] : 16bits addresses to PMEM using TASK_INDEX above
+ */
+
+/*
+ *  IDs of the micro tasks
+ */
+
+// from ABE_FunctionsId.h
+/*#define id_		copyMultiFrame_TFID
+#define id_		inplaceGain_TFID
+#define id_		mixer_TFID
+#define id_		IIR_TFID
+#define id_		gainConverge_TFID
+#define id_		sinGen_TFID
+#define id_		OSR0Fill_TFID
+#define id_		IOtask_TFID
+
+#define id_mixer
+#define id_eq
+#define id_upsample_src
+#define id_downsample_src
+#define id_asrc
+#define id_gain_update
+#define id_aps_hs
+#define id_aps_ihf
+#define id_dither
+#define id_eanc
+#define id_io
+#define id_router
+#define id_dynamic_dl
+#define id_dynamic_ul
+#define id_sequence_reader
+#define id_ ..
+*/
+
+/*
+ *  I/O DESCRIPTORS
+ */
+#define dmem_port_descriptors		D_IOdescr_ADDR
+
+/* ping_pong_t descriptors table
+ *   structure of 8 bytes:
+ *       uint16 base_address1
+ *       uint16 size1       (16bits address format)
+ *       uint16 base_address2
+ *       uint16 size2
+ *   } ping_pong_t
+ *  ping_pong_t dmem_ping_pong_t [8]
+ */
+#define dmem_ping_pong_buffer		D_PING_ADDR	/* U8 address */
+
+/*
+ *  IRQ mask used with ports with IRQ (DMA or host)
+ *  uint32 dmem_irq_masks [8]
+ */
+#define dmem_irq_masks			D_IRQMask_ADDR
+
+/*
+ *  tables of to the 8 FIFO sequences (delayed commands) holding 12bytes tasks in the format
+ *  structure {
+ *       1) Down counter delay on 16bits, decremented on each scheduler period
+ *       2) Code on 8 bits for the type of operation to execute : call or data move.
+ *       3) Three 16bits parameters (for data move example example : source/destination/counter)
+ *       4) Three bytes reserved
+ *      } seq_fw_task_t
+ *
+ *  structure {
+ *      uint32 : base address(MSB) + read pointer(LSB)
+ *      uint32 : max address (MSB) + write pointer (LSB)
+ *      } FIFO_generic;
+ *      seq_fw_task_t FIFO_CONTENT [8]; 96 bytes
+ *
+ *   FIFO_SEQ dmem_fifo_sequences [8]; all FIFO sequences
+ */
+#define dmem_fifo_sequences		D_DCFifo_ADDR
+#define dmem_fifo_sequences_descriptors	D_DCFifoDesc_ADDR
+
+/*
+ *  IRQ FIFOs
+ *
+ *  structure {
+ *      uint32 : base address(MSB) + read pointer(LSB)
+ *      uint32 : max address (MSB) + write pointer (LSB)
+ *      uint32 IRQ_CODES [6];
+ *      } dmem_fifo_irq_mcu;  32 bytes
+ *      } dmem_fifo_irq_dsp;  32 bytes
+ */
+#define dmem_fifo_irq_mcu_descriptor	D_McuIrqFifoDesc_ADDR
+#define dmem_fifo_irq_dsp_descriptor	D_DspIrqFifoDesc_ADDR
+#define dmem_fifo_irq_mcu		D_McuIrqFifo_ADDR
+#define dmem_fifo_irq_dsp		D_DspIrqFifo_ADDR
+
+/*
+ *  remote debugger exchange buffer
+ *  uint32 dmem_debug_ae2hal [32]
+ *  uint32 dmem_debug_hal2ae [32]
+ */
+#define dmem_debug_ae2hal		D_DebugAbe2hal_ADDR
+#define dmem_debug_hal2ae		D_Debug_hal2abe_ADDR
+
+/*
+ *  DMEM address of the ASRC ppm drift parameter for ASRCs (voice and multimedia paths)
+ *  uint32 smem_asrc(x)_drift
+ */
+#define dmem_asrc1_drift		D_ASRC1drift_ADDR
+#define dmem_asrc2_drift		D_ASRC2drift_ADDR
+
+/*
+ *  DMEM indexes of the router uplink paths
+ *  uint8 dmem_router_index [8]
+ */
+// OC: TBD ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+//#define dmem_router_index
+
+/*
+ *  analog control circular buffer commands to Phoenix
+ *  structure {
+ *      uint32 : base address(MSB) + read pointer(LSB)
+ *      uint32 : max address (MSB) + write pointer (LSB)
+ *      uint32 FIFO_CONTENT [6];
+ *      } dmem_commands_to_phoenix;     32 bytes
+ */
+#define dmem_commands_to_phoenix		D_Cmd2PhenixFifo_ADDR
+#define dmem_commands_to_phoenix_descriptor	D_Cmd2PhenixFifoDesc_ADDR
+
+/*
+ *  analog control circular buffer commands from Phoenix (status line)
+ *  structure {
+ *      uint32 : base address(MSB) + read pointer(LSB)
+ *      uint32 : max address (MSB) + write pointer (LSB)
+ *      uint32 FIFO_CONTENT [6];
+ *      } dmem_commands_to_phoenix;     32 bytes
+ */
+#define dmem_commands_from_phoenix		D_StatusFromPhenixFifo_ADDR
+#define dmem_commands_from_phoenix_descriptor	D_StatusFromPhenixFifoDesc_ADDR
+
+/*
+ *  DEBUG mask
+ *  uint16 dmem_debug_trace_mask
+ *  each bit of this word enables a type a trace in the debug circular buffer
+ */
+
+// OC: TBD ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+//#define dmem_debug_trace_mask
+
+/*
+ *  DEBUG circular buffer
+ *  structure {
+ *      uint32 : base address(MSB) + read pointer(LSB)
+ *      uint32 : max address (MSB) + write pointer (LSB)
+ *      uint32 FIFO_CONTENT [14];  = TIMESTAMP + CODE
+ *      } dmem_debug_trace_buffer;     64 bytes
+ *  should be much larger (depends on the DMEM mapping...)
+ */
+#define dmem_debug_trace_buffer
+#define dmem_debug_trace_fifo		D_debugFifo_ADDR
+#define dmem_debug_trace_descriptor	D_debugFifoDesc_ADDR
+
+/*
+ *  Infinite counter incremented on each sheduler periods (~250 us)
+ *  uint16 dmem_debug_time_stamp
+ */
+#define dmem_debug_time_stamp		D_loopCounter_ADDR
+
+/*
+ *  ATC BUFFERS + IO TASKS SMEM buffers
+ */
+#define dmem_dmic			D_DMIC_UL_FIFO_ADDR
+#define dmem_dmic_size			((D_DMIC_UL_FIFO_ADDR_END-D_DMIC_UL_FIFO_ADDR+1)/4)
+#define smem_dmic1			DMIC0_96_labelID
+#define smem_dmic2			DMIC1_96_labelID
+#define smem_dmic3			DMIC2_96_labelID
+
+#define dmem_amic			D_McPDM_UL_FIFO_ADDR
+#define dmem_amic_size			((D_McPDM_UL_FIFO_ADDR_END-D_McPDM_UL_FIFO_ADDR+1)/4)
+#define smem_amic			AMIC_96_labelID
+
+#define dmem_mcpdm			D_McPDM_DL_FIFO_ADDR
+#define dmem_mcpdm_size			((D_McPDM_DL_FIFO_ADDR_END-D_McPDM_DL_FIFO_ADDR+1)/4)
+
+#define dmem_mm_ul			D_MM_UL_FIFO_ADDR
+#define dmem_mm_ul_size			((D_MM_UL_FIFO_ADDR_END-D_MM_UL_FIFO_ADDR+1)/4)
+#define smem_mm_ul			MM_UL_labelID	/* managed directly by the router */
+
+#define dmem_mm_ul2			D_MM_UL2_FIFO_ADDR
+#define dmem_mm_ul2_size		((D_MM_UL2_FIFO_ADDR_END-D_MM_UL2_FIFO_ADDR+1)/4)
+#define smem_mm_ul2			MM_UL2_labelID /* managed directly by the router */
+
+#define dmem_mm_dl			D_MM_DL_FIFO_ADDR
+#define dmem_mm_dl_size			((D_MM_DL_FIFO_ADDR_END-D_MM_DL_FIFO_ADDR+1)/4)
+#define smem_mm_dl_opp100		MM_DL_labelID
+#define smem_mm_dl_opp25			MM_DL_labelID		/* @@@ at OPP 25/50 or without ASRC */
+
+#define dmem_vx_dl			D_VX_DL_FIFO_ADDR
+#define dmem_vx_dl_size			((D_VX_DL_FIFO_ADDR_END-D_VX_DL_FIFO_ADDR+1)/4)
+#define smem_vx_dl			Voice_16k_DL_labelID	/* ASRC input buffer, size 40 */
+
+#define dmem_vx_ul			D_VX_UL_FIFO_ADDR
+#define dmem_vx_ul_size			((D_VX_UL_FIFO_ADDR_END-D_VX_UL_FIFO_ADDR+1)/4)
+#define smem_vx_ul			Voice_16k_UL_labelID
+
+#define dmem_tones_dl			D_TONES_DL_FIFO_ADDR
+#define dmem_tones_dl_size		((D_TONES_DL_FIFO_ADDR_END-D_TONES_DL_FIFO_ADDR+1)/4)
+#define smem_tones_dl			Tones_labelID
+
+#define dmem_vib_dl			D_VIB_DL_FIFO_ADDR
+#define dmem_vib_dl_size		((D_VIB_DL_FIFO_ADDR_END-D_VIB_DL_FIFO_ADDR+1)/4)
+#define smem_vib			IO_VIBRA_DL_labelID
+
+#define dmem_mm_ext_out			D_MM_EXT_OUT_FIFO_ADDR
+#define dmem_mm_ext_out_size		((D_MM_EXT_OUT_FIFO_ADDR_END-D_MM_EXT_OUT_FIFO_ADDR+1)/4)
+#define smem_mm_ext_out			DL1_M_labelID
+
+#define dmem_mm_ext_in			D_MM_EXT_IN_FIFO_ADDR
+#define dmem_mm_ext_in_size		((D_MM_EXT_IN_FIFO_ADDR_END-D_MM_EXT_IN_FIFO_ADDR+1)/4)
+#define smem_mm_ext_in			AMIC_labelID
+
+#define dmem_bt_vx_dl			D_BT_DL_FIFO_ADDR
+#define dmem_bt_vx_dl_size		((D_BT_DL_FIFO_ADDR_END-D_BT_DL_FIFO_ADDR+1)/4)
+#define smem_bt_vx_dl			AMIC_labelID
+
+#define dmem_bt_vx_ul			D_BT_UL_FIFO_ADDR
+#define dmem_bt_vx_ul_size		((D_BT_UL_FIFO_ADDR_END-D_BT_UL_FIFO_ADDR+1)/4)
+#define smem_bt_vx_ul			SDT_M_labelID
+
+/*
+ * INITPTR / INITREG AREA
+ */
+
+/*
+ *  POINTER - used for the port descriptor programming
+ *  corresponds to 8bits addresses to the INITPTR area
+ *
+ * List  from ABE_INITxxx_labels.h
+ */
+#define ptr_ul_rec
+#define ptr_vx_dl
+#define ptr_mm_dl
+#define ptr_mm_ext
+#define ptr_tones
+#define ptr_vibra2
+
+/*
+ * SMEM AREA
+ */
+
+/*
+ *  PHOENIX OFFSET in SMEM
+ *  used to subtract a DC offset on the headset path (power consumption optimization)
+ */
+
+/* OC: exact usage to be detailled */
+#define smem_phoenix_offset		S_PhoenixOffset_ADDR
+
+/*
+ *  EQUALIZERS Z AREA
+ *  used to reset the filter memory - IIR-8 (max)
+ *  int24 stereo smem_equ(x) [8x2 + 1]
+ */
+#define smem_equ1		S_EQU1_data_ADDR
+#define smem_equ2		S_EQU2_data_ADDR
+#define smem_equ3		S_EQU3_data_ADDR
+#define smem_equ4		S_EQU4_data_ADDR
+#define smem_sdt		S_SDT_data_ADDR
+
+/*
+ *  GAIN SMEM on PORT
+ *  int32 smem_G0 [18] : desired gain on the ports
+ *  format of G0 = 6 bits left shifted desired gain in linear 24bits format
+ *  int24 stereo G0 [18] = G0
+ *  int24 stereo GI [18] current value of the gain in the same format of G0
+ *  List of smoothed gains :
+ *  6 DMIC 0 1 2 3 4 5
+ *  2 AMIC L R
+ *  4 PORT1/2_RX L R
+ *  2 MM_EXT L R
+ *  2 MM_VX_DL L R
+ *  2 IHF L R
+ * ---------------
+ * 18 = TOTAL
+ */
+//#define smem_g0			S_GTarget_ADDR	/* [9] 2 gains in 1 SM address */
+//#define smem_g1			S_GCurrent_ADDR	/* [9] 2 gains in 1 SM address */
+
+/*
+ * COEFFICIENTS AREA
+ */
+
+/*
+ *  delay coefficients used in the IIR-1 filters
+ *  int24 cmem_gain_delay_iir1[9 x 2]  (a, (1-a))
+ *
+ *  3 for 6 DMIC 0 1 2 3 4 5
+ *  1 for 2 AMIC L R
+ *  2 for 4 PORT1/2_RX L R
+ *  1 for 2 MM_EXT L R
+ *  1 for 2 MM_VX_DL L R
+ *  1 for 2 IHF L R
+ */
+
+#define cmem_gain_alpha		C_Alpha_ADDR	/* [9] */
+#define cmem_gain_1_alpha	C_1_Alpha_ADDR
+
+/*
+ * gain controls
+ */
+#define GAIN_LEFT_OFFSET	(abe_port_id)0
+#define GAIN_RIGHT_OFFSET	(abe_port_id)1
+
+#define cmem_gains_base		C_GainsWRamp_ADDR
+#define smem_target_gain_base	S_GTarget1_ADDR
+#define cmem_1_Alpha_base	C_1_Alpha_ADDR
+#define cmem_Alpha_base		C_Alpha_ADDR
+
+#define dmic1_gains_offset	0	/* stereo gains */
+#define dmic2_gains_offset	2	/* stereo gains */
+#define dmic3_gains_offset	4	/* stereo gains */
+#define amic_gains_offset	6	/* stereo gains */
+#define dl1_gains_offset	8	/* stereo gains */
+#define dl2_gains_offset	10	/* stereo gains */
+#define splitters_gains_offset	12	/* stereo gains */
+
+#define mixer_dl1_offset	14
+#define mixer_dl2_offset	18
+#define mixer_echo_offset	22
+#define mixer_sdt_offset	24
+#define mixer_vxrec_offset	26
+#define mixer_audul_offset	30
+#define gain_unused_offset	34
+
+/*
+ *  DMIC SRC 96->48
+ *  the filter is changed depending on the decimatio ratio used (16/25/32/40)
+ *  int32 cmem_src2_dmic [6]   IIR with 2 coefs in the recursive part and 4 coefs in the direct part
+ */
+#define cmem_src2_dmic
+
+/*
+ *  EANC coefficients
+ *  structure of :
+ *      20 Q6.26 coef for the FIR
+ *      16 Q6.26 coef for the IIR
+ *      1 Q6.26 coef for Lambda
+ */
+#define cmem_eanc_coef_fir
+#define cmem_eanc_coef_iir
+#define cmem_eanc_coef_lambda
+
+/*
+ *  EQUALIZERS - SDT - COEF AREA
+ *  int24  cmem_equ(x) [8x2+1]
+ */
+#define cmem_equ1		C_EQU1_data_ADDR
+#define cmem_equ2		C_EQU2_data_ADDR
+#define cmem_equ3		C_EQU3_data_ADDR
+#define cmem_equ4		C_EQU4_data_ADDR
+#define cmem_sdt		C_SDT_data_ADDR
+
+/*
+ *  APS - COEF AREA
+ *  int24  cmem_aps(x) [16]
+ */
+#define cmem_aps1
+#define cmem_aps2
+#define cmem_aps3
+
+/*
+ *  DITHER - COEF AREA
+ *  int24  cmem_dither(x) [4]
+ */
+#define cmem_dither
+
+//#ifdef __cplusplus
+//}
+//#endif
diff --git a/sound/soc/codecs/abe/abe_ini.c b/sound/soc/codecs/abe/abe_ini.c
new file mode 100644
index 000000000000..5beeb465aa71
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_ini.c
@@ -0,0 +1,1145 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_main.h"
+#include "abe_dat.h" /* data declaration */
+#include "abe_cof.h"
+/*
+ *  initialize the default values for call-backs to subroutines
+ *      - FIFO IRQ call-backs for sequenced tasks
+ *      - FIFO IRQ call-backs for audio player/recorders (ping-pong protocols)
+ *      - Remote debugger interface
+ *      - Error monitoring
+ *      - Activity Tracing
+ */
+
+/*
+ *  ABE_HW_CONFIGURATION
+ *
+ *  Parameter  :
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_hw_configuration()
+{
+	abe_uint32 atc_reg;
+
+	/* enables the DMAreq from AESS  AESS_DMAENABLE_SET = 255 */
+	atc_reg = 0xFF;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x60, &atc_reg, 4);
+}
+
+/*
+ *  ABE_BUILD_SCHEDULER_TABLE
+ *
+ *  Parameter  :
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_build_scheduler_table()
+{
+	short MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT];
+	abe_uint16 i, n;
+	abe_uint8 *ptr;
+	char aUplinkMuxing[16];
+
+	/* LOAD OF THE TASKS' MULTIFRAME */
+	/* WARNING ON THE LOCATION OF IO_MM_DL WHICH IS PATCHED IN "abe_init_io_tasks" */
+
+	for (ptr = (abe_uint8 *)&(MultiFrame[0][0]), i=0; i < sizeof (MultiFrame); i++)
+		*ptr++ = 0;
+
+	//MultiFrame[0][0] = 0;
+	//MultiFrame[0][1] = 0;
+	MultiFrame[0][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_VX_DL;
+	//MultiFrame[0][3] = 0;
+	//MultiFrame[0][4] = 0;
+	//MultiFrame[0][5] = 0;
+	//@@@ MultiFrame[0][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_MM_DL; No ASRC
+	//MultiFrame[0][7] = 0;
+	//MultiFrame[1][0] = 0;
+	//MultiFrame[1][1] = 0;
+#define TASK_ASRC_VX_DL_SLT 1
+#define TASK_ASRC_VX_DL_IDX 2
+	//MultiFrame[1][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_DL_16;
+#define TASK_VX_DL_SLT 1
+#define TASK_VX_DL_IDX 3
+	MultiFrame[1][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_DL_16_48;
+	//MultiFrame[1][4] = 0;
+	//MultiFrame[1][5] = 0;
+	MultiFrame[1][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2Mixer;
+	MultiFrame[1][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_VIB_DL;
+	MultiFrame[2][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1Mixer;
+	//MultiFrame[2][1] = 0;
+	MultiFrame[2][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_SideTone;
+	//MultiFrame[2][3] = 0;
+	MultiFrame[2][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_SDTMixer;
+	MultiFrame[2][5] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_DMIC;
+	//MultiFrame[2][6] = 0;
+	//MultiFrame[2][7] = 0;
+
+	MultiFrame[3][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_EQ;
+	//MultiFrame[3][1] = 0;
+	MultiFrame[3][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EchoMixer;
+	//MultiFrame[3][3] = 0;
+	//MultiFrame[3][4] = 0;
+	//MultiFrame[3][5] = 0;
+	MultiFrame[3][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_EQ;
+	MultiFrame[3][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VIBRA_SPLIT;
+	MultiFrame[4][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_APS_EQ;
+	MultiFrame[4][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_GAIN;
+	MultiFrame[4][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VXRECMixer;
+	MultiFrame[4][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VXREC_SPLIT;
+	//MultiFrame[4][4] = 0;
+	//MultiFrame[4][5] = 0;
+	MultiFrame[4][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VIBRA1;
+	MultiFrame[4][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VIBRA2;
+
+	MultiFrame[5][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EARP_48_96_0SR;
+	MultiFrame[5][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EARP_48_96_LP;
+	MultiFrame[5][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_PDM_UL;
+	//MultiFrame[5][3] = 0;
+	//MultiFrame[5][4] = 0;
+	//MultiFrame[5][5] = 0;
+	MultiFrame[5][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_APS_EQ;
+	MultiFrame[5][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_GAIN;
+
+	MultiFrame[6][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EARP_48_96_LP;
+	MultiFrame[6][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_PDM_DL;
+	//MultiFrame[6][2] = 0;
+	//MultiFrame[6][3] = 0;
+	//MultiFrame[6][4] = 0;
+	//MultiFrame[6][5] = 0;
+	MultiFrame[6][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_APS_SPLIT;
+	//MultiFrame[6][7] = 0;
+
+	//MultiFrame[7][0] = 0;
+	//MultiFrame[7][1] = 0;
+	MultiFrame[7][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_UL_SPLIT;
+	MultiFrame[7][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DBG_SYNC;
+	//MultiFrame[7][4] = 0;
+	//MultiFrame[7][5] = 0;
+	MultiFrame[7][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_R_APS_CORE;
+	MultiFrame[7][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_L_APS_CORE;
+
+	//MultiFrame[8][0] = 0;
+	//MultiFrame[8][1] = 0;
+	MultiFrame[8][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC1_96_48_LP;
+	//MultiFrame[8][3] = 0;
+	MultiFrame[8][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC1_SPLIT;
+	//MultiFrame[8][5] = 0;
+	//MultiFrame[8][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EANC_FBK_96_48;
+	//MultiFrame[8][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EANC_FBK_SPLIT;
+
+	//MultiFrame[9][0] = 0;
+	//MultiFrame[9][1] = 0;
+	MultiFrame[9][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC2_96_48_LP;
+	//MultiFrame[9][3] = 0;
+	MultiFrame[9][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC2_SPLIT;
+	//MultiFrame[9][5] = 0;
+	MultiFrame[9][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IHF_48_96_0SR;
+	MultiFrame[9][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IHF_48_96_LP;
+
+	//MultiFrame[10][0] = 0;
+	//MultiFrame[10][1] = 0;
+	MultiFrame[10][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC3_96_48_LP;
+	//MultiFrame[10][3] = 0;
+	MultiFrame[10][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC3_SPLIT;
+	//MultiFrame[10][5] = 0;
+	//MultiFrame[10][6] = 0; // D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EANC_COPY; // NEW: copy EANC coefs to working CMEM areas
+	MultiFrame[10][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IHF_48_96_LP;
+
+	//MultiFrame[11][0] = 0;
+	//MultiFrame[11][1] = 0;
+	MultiFrame[11][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_AMIC_96_48_LP;
+	//MultiFrame[11][3] = 0;
+	MultiFrame[11][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_AMIC_SPLIT;
+	//MultiFrame[11][5] = 0;
+	//MultiFrame[11][6] = 0;
+	MultiFrame[11][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VIBRA_PACK;
+
+	//MultiFrame[12][0] = 0;
+	//MultiFrame[12][1] = 0;
+	MultiFrame[12][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_BT_VX_DL;
+	MultiFrame[12][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_UL_ROUTING;
+	MultiFrame[12][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ULMixer;
+#define TASK_VX_UL_SLT 12
+#define TASK_VX_UL_IDX 5
+	MultiFrame[12][5] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_UL_48_16;
+	//MultiFrame[12][6] = 0;
+	//MultiFrame[12][7] = 0;
+	//MultiFrame[13][0] = 0;
+	//MultiFrame[13][1] = 0;
+	MultiFrame[13][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_MM_UL2_ROUTING;
+	//MultiFrame[13][3] = 0;
+	MultiFrame[13][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_UL;
+	//MultiFrame[13][5] = 0;
+	//MultiFrame[13][6] = 0;
+	//MultiFrame[13][7] = 0;
+
+	//MultiFrame[14][0] = 0;
+	//MultiFrame[14][1] = 0;
+	//MultiFrame[14][2] = 0;
+	MultiFrame[14][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_DMIC;
+#define TASK_BT_DL_48_8_SLT	14
+#define	TASK_BT_DL_48_8_IDX	4
+	MultiFrame[14][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_DL_48_8;
+	//MultiFrame[14][5] = 0;
+#define TASK_ECHO_SLT 14
+#define TASK_ECHO_IDX 6
+	MultiFrame[14][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ECHO_REF_48_16;
+	//MultiFrame[14][7] = 0;
+
+	MultiFrame[15][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_APS_IIR;
+	MultiFrame[15][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_APS_CORE;
+	//MultiFrame[15][2] = 0;
+	MultiFrame[15][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_BT_VX_UL;
+	//MultiFrame[15][4] = 0;
+	//MultiFrame[15][5] = 0;
+	//MultiFrame[15][6] = 0;
+#define TASK_ASRC_ECHO_SLT 15
+#define TASK_ASRC_ECHO_IDX 7
+	//@@@	MultiFrame[15][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_ECHO_REF_16;
+
+	//MultiFrame[16][0] = 0;
+	//MultiFrame[16][1] = 0;
+#define TASK_ASRC_VX_UL_SLT 16
+#define TASK_ASRC_VX_UL_IDX 2
+	//@@@  MultiFrame[16][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_UL_16;
+	MultiFrame[16][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_VX_UL; // USING ECHO REF MERGED
+	//MultiFrame[16][4] = 0;
+	//MultiFrame[16][5] = 0;
+	//MultiFrame[16][6] = 0;
+	//MultiFrame[16][7] = 0;
+
+	//MultiFrame[17][0] = 0;
+	//MultiFrame[17][1] = 0;
+#define TASK_BT_UL_8_48_SLT	17
+#define TASK_BT_UL_8_48_IDX	2
+	MultiFrame[17][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_UL_8_48;
+	MultiFrame[17][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_UL2;
+	//MultiFrame[17][4] = 0;
+	//MultiFrame[17][5] = 0;
+	//MultiFrame[17][6] = 0;
+	//MultiFrame[17][7] = 0;
+
+	MultiFrame[18][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_PDM_DL;
+	//MultiFrame[18][1] = 0;
+	//MultiFrame[18][2] = 0;
+	//MultiFrame[18][3] = 0;
+	//MultiFrame[18][4] = 0;
+	//MultiFrame[18][5] = 0;
+	//MultiFrame[18][6] = 0;
+	//MultiFrame[18][7] = 0;
+
+#define TASK_IO_MM_DL_SLT 19
+#define TASK_IO_MM_DL_IDX 0
+	MultiFrame[19][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_DL;
+	//MultiFrame[19][1] = 0
+	//MultiFrame[19][2] = 0;
+	//MultiFrame[19][3] = 0;
+	//MultiFrame[19][4] = 0;
+	//MultiFrame[19][5] = 0;
+	//MultiFrame[19][6] = 0;
+	//MultiFrame[19][7] = 0;
+
+	MultiFrame[20][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_TONES_DL;
+	MultiFrame[20][1] = 0;
+	MultiFrame[20][2] = 0;
+	//MultiFrame[20][3] = 0;
+	//MultiFrame[20][4] = 0;
+	//MultiFrame[20][5] = 0;
+	//MultiFrame[20][6] = 0;
+	//MultiFrame[20][7] = 0;
+
+	//MultiFrame[21][0] = 0;
+	//MultiFrame[21][1] = 0;
+	//MultiFrame[21][2] = 0;
+	//MultiFrame[21][3] = 0;
+	//MultiFrame[21][4] = 0;
+	//MultiFrame[21][5] = 0;
+	//MultiFrame[21][6] = 0;
+	//MultiFrame[21][7] = 0;
+
+	MultiFrame[22][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DEBUG_IRQFIFO;	// MUST STAY ON SLOT 22
+	//MultiFrame[22][1] = 0;
+	MultiFrame[22][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_EXT_OUT;
+	MultiFrame[22][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_EXT_IN;
+	//MultiFrame[22][4] = 0;
+	//MultiFrame[22][5] = 0;
+	//MultiFrame[22][6] = 0;
+	//MultiFrame[22][7] = 0;
+
+	MultiFrame[23][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_GAIN_UPDATE;
+	//MultiFrame[23][1] = 0;
+	//MultiFrame[23][2] = 0;
+	//MultiFrame[23][3] = 0;
+	//MultiFrame[23][4] = 0;
+	//MultiFrame[23][5] = 0;
+	//MultiFrame[23][6] = 0;
+	//MultiFrame[23][7] = 0;
+
+	//MultiFrame[24][0] = 0;
+	//MultiFrame[24][1] = 0;
+	//MultiFrame[24][2] = 0;
+	//MultiFrame[24][3] = 0;
+	//MultiFrame[24][4] = 0;
+	//MultiFrame[24][5] = 0;
+	//MultiFrame[24][6] = 0;
+	//MultiFrame[24][7] = 0;
+
+	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame));
+
+	// EANC Fast Loopback
+	// dFastLoopback = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EANC_WRAP2;
+	// abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_pFastLoopBack_ADDR, (abe_uint32*)&dFastLoopback, sizeof (dFastLoopback));
+
+	/* reset the uplink router */
+	n = D_aUplinkRouting_ADDR_END - D_aUplinkRouting_ADDR + 1;
+	for(i = 0; i < n; i++)
+		aUplinkMuxing[i] = ZERO_labelID;
+
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_aUplinkRouting_ADDR, (abe_uint32 *)aUplinkMuxing, sizeof(aUplinkMuxing));
+}
+
+/*
+ *  ABE_INIT_ATC
+ *
+ *  Parameter  :
+ *      prot : protocol being used
+ *
+ *  Operations :
+ *      load the DMEM ATC/AESS descriptors
+ *
+ *  Return value :
+ *
+ */
+void abe_init_atc(abe_port_id id)
+{
+	abe_satcdescriptor_aess desc;
+	abe_uint8 iter;
+	abe_int32 datasize;
+
+	// load default values of the descriptor
+	desc.rdpt = desc.wrpt = desc.irqdest = desc.cberr = desc.desen = desc.nw =0;
+	desc.reserved0 = desc.reserved1 = desc.reserved2 = 0;
+	desc.srcid = desc.destid = desc.badd = desc.iter = desc.cbsize = 0;
+
+	datasize = abe_dma_port_iter_factor (&((abe_port[id]).format));
+	iter = (abe_uint8) abe_dma_port_iteration (&((abe_port[id]).format));
+
+	if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) // IN from AESS point of view
+		if (iter + 2*datasize > 126)
+			desc.wrpt = (iter >>1) + (2*datasize);
+		else
+			desc.wrpt = iter + 2*datasize;
+	else
+		desc.wrpt = 0 + 2*datasize;
+
+	switch ((abe_port[id]).protocol.protocol_switch) {
+	case SLIMBUS_PORT_PROT:
+		desc.cbdir = (abe_port[id]).protocol.direction;
+		desc.cbsize = (abe_port[id]).protocol.p.prot_slimbus.buf_size;
+		desc.badd = ((abe_port[id]).protocol.p.prot_slimbus.buf_addr1) >> 4;
+		desc.iter = (abe_port[id]).protocol.p.prot_slimbus.iter;
+		desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p.prot_slimbus.desc_addr1 >> 3];
+
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				(abe_port[id]).protocol.p.prot_slimbus.desc_addr1,
+							(abe_uint32*)&desc, sizeof(desc));
+
+		desc.badd = (abe_port[id]).protocol.p.prot_slimbus.buf_addr2;
+		desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p.prot_slimbus.desc_addr2 >> 3];
+
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				(abe_port[id]).protocol.p.prot_slimbus.desc_addr2,
+							(abe_uint32*)&desc, sizeof(desc));
+		break;
+	case SERIAL_PORT_PROT:
+		desc.cbdir = (abe_port[id]).protocol.direction;
+		desc.cbsize = (abe_port[id]).protocol.p.prot_serial.buf_size;
+		desc.badd = ((abe_port[id]).protocol.p.prot_serial.buf_addr) >> 4;
+		desc.iter = (abe_port[id]).protocol.p.prot_serial.iter;
+		desc.srcid = abe_atc_srcid[(abe_port[id]).protocol.p.prot_serial.desc_addr >> 3];
+		desc.destid = abe_atc_dstid[(abe_port[id]).protocol.p.prot_serial.desc_addr >> 3];
+
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				(abe_port[id]).protocol.p.prot_serial.desc_addr,
+							(abe_uint32*)&desc, sizeof(desc));
+		break;
+	case DMIC_PORT_PROT:
+		desc.cbdir = ABE_ATC_DIRECTION_IN;
+		desc.cbsize = (abe_port[id]).protocol.p.prot_dmic.buf_size;
+		desc.badd = ((abe_port[id]).protocol.p.prot_dmic.buf_addr) >> 4;
+		desc.iter = DMIC_ITER;
+		desc.srcid = abe_atc_srcid[ABE_ATC_DMIC_DMA_REQ];
+
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				ABE_ATC_DMIC_DMA_REQ * ATC_SIZE, (abe_uint32*)&desc, sizeof(desc));
+		break;
+	case MCPDMDL_PORT_PROT:
+		abe_global_mcpdm_control = abe_port[id].protocol.p.prot_mcpdmdl.control;	/* Control allowed on McPDM DL */
+		desc.cbdir = ABE_ATC_DIRECTION_OUT;
+		desc.cbsize = (abe_port[id]).protocol.p.prot_mcpdmdl.buf_size;
+		desc.badd = ((abe_port[id]).protocol.p.prot_mcpdmdl.buf_addr) >> 4;
+		desc.iter = MCPDM_DL_ITER;
+		desc.destid = abe_atc_dstid[ABE_ATC_MCPDMDL_DMA_REQ];
+
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				ABE_ATC_MCPDMDL_DMA_REQ * ATC_SIZE, (abe_uint32*)&desc, sizeof(desc));
+		break;
+	case MCPDMUL_PORT_PROT:
+		desc.cbdir = ABE_ATC_DIRECTION_IN;
+		desc.cbsize = (abe_port[id]).protocol.p.prot_mcpdmul.buf_size;
+		desc.badd = ((abe_port[id]).protocol.p.prot_mcpdmul.buf_addr) >> 4;
+		desc.iter = MCPDM_UL_ITER;
+		desc.srcid = abe_atc_srcid[ABE_ATC_MCPDMUL_DMA_REQ];
+
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				ABE_ATC_MCPDMUL_DMA_REQ * ATC_SIZE, (abe_uint32*)&desc, sizeof(desc));
+		break;
+	case PINGPONG_PORT_PROT:
+		/* software protocol, nothing to do on ATC */
+		break;
+	case DMAREQ_PORT_PROT:
+		desc.cbdir = (abe_port[id]).protocol.direction;
+		desc.cbsize = (abe_port[id]).protocol.p.prot_dmareq.buf_size;
+		desc.badd = ((abe_port[id]).protocol.p.prot_dmareq.buf_addr) >> 4;
+		desc.iter = 1; /* CBPr needs ITER=1. this is the eDMA job to do the iterations */
+		/* input from ABE point of view */
+		if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) {
+			desc.rdpt = 127;
+			desc.wrpt = 0;
+			desc.srcid = abe_atc_srcid[(abe_port[id]).protocol.p.prot_dmareq.desc_addr >> 3];
+		} else {
+			desc.rdpt = 0;
+			desc.wrpt = 127;
+			desc.destid = abe_atc_dstid[(abe_port[id]).protocol.p.prot_dmareq.desc_addr >> 3];
+		}
+
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			(abe_port[id]).protocol.p.prot_dmareq.desc_addr, (abe_uint32*)&desc, sizeof (desc));
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ *
+ * ABE_INIT_DMA_T
+ *  Parameter  :
+ *      prot : protocol being used
+ *
+ *  Operations :
+ *      load the dma_t with physical information from AE memory mapping
+ *
+ *  Return value :
+ *
+ */
+void abe_init_dma_t(abe_port_id id, abe_port_protocol_t *prot)
+{
+	abe_dma_t_offset dma;
+	abe_uint32 idx;
+
+	dma.data = 0;	/* default dma_t points to address 0000... */
+	dma.iter = 0;
+
+	switch (prot->protocol_switch) {
+	case PINGPONG_PORT_PROT:
+		for (idx = 0; idx < 32; idx++) {
+			if (((prot->p).prot_pingpong.irq_data) == (abe_uint32)(1 << idx))
+				break;
+		}
+		(prot->p).prot_dmareq.desc_addr = (CBPr_DMA_RTX0+idx)*ATC_SIZE;
+		dma.data = (prot->p).prot_pingpong.buf_addr >> 2;
+		dma.iter = (prot->p).prot_pingpong.buf_size >> 2;
+		break;
+	case DMAREQ_PORT_PROT:
+		for (idx = 0; idx < 32; idx++) {
+			if (((prot->p).prot_dmareq.dma_data) == (abe_uint32)(1 << idx))
+				break;
+		}
+		dma.data = (CIRCULAR_BUFFER_PERIPHERAL_R__0 + idx*4);
+		dma.iter = (prot->p).prot_dmareq.iter;
+		(prot->p).prot_dmareq.desc_addr = (CBPr_DMA_RTX0+idx)*ATC_SIZE;
+		break;
+	case SLIMBUS_PORT_PROT:
+	case SERIAL_PORT_PROT:
+	case DMIC_PORT_PROT:
+	case MCPDMDL_PORT_PROT:
+	case MCPDMUL_PORT_PROT:
+	default:
+		break;
+	}
+
+	/* upload the dma type */
+	abe_port [id].dma = dma;
+}
+
+/*
+ * ABE_DISENABLE_DMA_REQUEST
+ * Parameter:
+ * Operations:
+ * Return value:
+ */
+void abe_disable_enable_dma_request(abe_port_id id, abe_uint32 on_off)
+{
+	ABE_SIODescriptor desc;
+	ABE_SPingPongDescriptor desc_pp;
+	abe_uint8 desc_third_word[4], irq_dmareq_field;
+	abe_uint32 sio_desc_address;
+	abe_uint32 struct_offset;
+
+	if (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) {
+		irq_dmareq_field = (abe_uint8)(on_off * abe_port[id].protocol.p.prot_pingpong.irq_data);
+		sio_desc_address = D_PingPongDesc_ADDR;
+		struct_offset = (abe_uint32)&(desc_pp.data_size) - (abe_uint32)&(desc_pp);
+
+		abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address + struct_offset, (abe_uint32 *)desc_third_word, 4);
+		desc_third_word[2] = irq_dmareq_field;
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address + struct_offset, (abe_uint32 *)desc_third_word, 4);
+	} else {
+		sio_desc_address = dmem_port_descriptors + (id * sizeof(ABE_SIODescriptor));
+		abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, (abe_uint32*)&desc, sizeof (desc));
+
+		if (on_off) {
+			desc.atc_irq_data = (abe_uint8) abe_port[id].protocol.p.prot_dmareq.dma_data;
+			desc.on_off = 0x80;
+		} else {
+			desc.atc_irq_data = 0;
+			desc.on_off = 0;
+		}
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address,
+						(abe_uint32*)&desc, sizeof (desc));
+	}
+}
+
+void abe_enable_dma_request(abe_port_id id)
+{
+	abe_disable_enable_dma_request(id, 1);
+}
+
+/*
+ * ABE_DISABLE_DMA_REQUEST
+ *
+ * Parameter:
+ * Operations:
+ * Return value:
+ *
+ */
+void abe_disable_dma_request(abe_port_id id)
+{
+	abe_disable_enable_dma_request(id, 0);
+}
+
+
+/*
+ * ABE_ENABLE_ATC
+ * Parameter:
+ * Operations:
+ * Return value:
+ */
+void abe_enable_atc(abe_port_id id)
+{
+	just_to_avoid_the_many_warnings = (abe_port_id)id;
+#if 0
+	abe_satcdescriptor_aess desc;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+		(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+				(abe_uint32*)&desc, sizeof (desc));
+	desc.desen = 1;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+		(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+				(abe_uint32*)&desc, sizeof (desc));
+#endif
+}
+
+
+/*
+ * ABE_DISABLE_ATC
+ * Parameter:
+ * Operations:
+ * Return value:
+ */
+void abe_disable_atc(abe_port_id id)
+{
+	abe_satcdescriptor_aess desc;
+
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+		(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+				(abe_uint32*)&desc, sizeof (desc));
+	desc.desen = 0;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+		(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+				(abe_uint32*)&desc, sizeof (desc));
+}
+
+/*
+ *   ABE_INIT_IO_TASKS
+ *
+ *  Parameter  :
+ *  prot : protocol being used
+ *
+ *  Operations :
+ *      load the micro-task parameters doing to DMEM <==> SMEM data moves
+ *
+ *       I/O descriptors input parameters :
+ *	 For Read from DMEM usually THR1/THR2 = X+1/X-1
+ *	 For Write to DMEM usually  THR1/THR2 = 2/0
+ *	 UP_1/2 =X+1/X-1
+ *
+ *  Return value :
+ *
+ */
+void abe_init_io_tasks(abe_port_id id, abe_data_format_t *format, abe_port_protocol_t *prot)
+{
+	ABE_SIODescriptor desc;
+	ABE_SPingPongDescriptor desc_pp;
+	abe_uint32 x_io, direction, iter_samples, smem1, smem2, smem3, io_sub_id;
+	abe_uint32 copy_func_index, before_func_index, after_func_index;
+	abe_uint32 dmareq_addr, dmareq_field;
+	abe_uint32 sio_desc_address, datasize, iter, nsamp, datasize2, dOppMode32;
+	abe_uint32 atc_ptr_saved, atc_ptr_saved2, copy_func_index1;
+	abe_uint32 copy_func_index2, atc_desc_address1, atc_desc_address2;
+	short MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT];
+
+	if (prot->protocol_switch == PINGPONG_PORT_PROT) {
+		if (MM_DL_PORT == id) {
+			// @@@@  reset local memory
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+				D_multiFrame_ADDR,
+					(abe_uint32*)MultiFrame,
+						sizeof (MultiFrame));
+			MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] =
+				D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_PING_PONG;
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				D_multiFrame_ADDR, (abe_uint32*)MultiFrame,
+						sizeof (MultiFrame));
+		} else {
+			abe_dbg_param |= ERR_API;
+			abe_dbg_error_log (ABE_PARAMETER_ERROR);
+		}
+
+		smem1 = (abe_uint8) abe_port[id].smem_buffer1;
+		copy_func_index = (abe_uint8) abe_dma_port_copy_subroutine_id (id);
+		dmareq_addr  = abe_port[id].protocol.p.prot_pingpong.irq_addr;
+		dmareq_field = abe_port[id].protocol.p.prot_pingpong.irq_data;
+		datasize = abe_dma_port_iter_factor (format);
+		iter = abe_dma_port_iteration (format);
+		iter_samples = (iter / datasize);	  /* number of "samples" either mono or stereo */
+
+		/* load the IO descriptor */
+		desc_pp.drift_ASRC = 0; /* no drift  */
+		desc_pp.drift_io = 0; /* no drift  */
+		desc_pp.hw_ctrl_addr = (abe_uint16) dmareq_addr;
+		desc_pp.copy_func_index = (abe_uint8) copy_func_index;
+		desc_pp.smem_addr = (abe_uint8) smem1;
+		desc_pp.atc_irq_data = (abe_uint8) dmareq_field; /* DMA req 0 is used for CBPr0 */
+		desc_pp.x_io = (abe_uint8) iter_samples; /* size of block transfer */
+		desc_pp.data_size = (abe_uint8) datasize;
+		desc_pp.workbuff_BaseAddr = (abe_uint16) (abe_base_address_pingpong [0]);			 /* address comunicated in Bytes */
+		desc_pp.workbuff_Samples = (abe_uint16) iter_samples; /* size comunicated in XIO sample */
+		desc_pp.nextbuff0_BaseAddr = (abe_uint16) (abe_base_address_pingpong [0]);
+		desc_pp.nextbuff0_Samples = (abe_uint16) ((abe_size_pingpong >> 2)/datasize);
+		desc_pp.nextbuff1_BaseAddr = (abe_uint16) (abe_base_address_pingpong [1]);
+		desc_pp.nextbuff1_Samples = (abe_uint16) ((abe_size_pingpong >> 2)/datasize);
+		desc_pp.counter = 1;
+
+		/* send a DMA req to fill B0 with N samples
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_DMASTATUS_RAW, &(abe_port[id].protocol.p.prot_pingpong.irq_data), 4); */
+
+		sio_desc_address = D_PingPongDesc_ADDR;
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address,
+				(abe_uint32*)&desc_pp, sizeof (desc_pp));
+	} else {
+		io_sub_id = dmareq_addr = ABE_DMASTATUS_RAW;
+		dmareq_field = 0;
+		atc_desc_address1 = atc_desc_address2 = 0;
+
+		datasize2=datasize = abe_dma_port_iter_factor(format);
+		x_io = (abe_uint8) abe_dma_port_iteration(format);
+		nsamp = (x_io / datasize);
+
+		atc_ptr_saved2=atc_ptr_saved = DMIC_ATC_PTR_labelID + id;
+
+		smem1 = abe_port[id].smem_buffer1;
+		smem3 = smem2 = abe_port[id].smem_buffer2;
+
+		copy_func_index1 = (abe_uint8) abe_dma_port_copy_subroutine_id(id);
+		before_func_index = after_func_index = copy_func_index2 = NULL_COPY_CFPID;
+
+		/* MM_DL managed in non-ping-pong mode */
+		if (MM_DL_PORT == id) {
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR,
+				(abe_uint32*)MultiFrame, sizeof (MultiFrame));
+			MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = D_tasksList_ADDR +
+							sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_DL;
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR,
+							(abe_uint32 *)MultiFrame, sizeof (MultiFrame));
+		}
+
+		switch (prot->protocol_switch) {
+		case DMIC_PORT_PROT:
+			/* DMIC port is read in two steps */
+			x_io = x_io >> 1;
+			nsamp = nsamp >> 1;
+			atc_desc_address1 = ABE_ATC_DMIC_DMA_REQ*ATC_SIZE;
+			io_sub_id = IO_IP_CFPID;
+			break;
+		case MCPDMDL_PORT_PROT:
+			/* PDMDL port is written to  in two steps */
+			x_io = x_io >> 1;
+			atc_desc_address1 = ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE;
+			io_sub_id = IO_IP_CFPID;
+			break;
+		case MCPDMUL_PORT_PROT:
+			atc_desc_address1 = ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE;
+			io_sub_id = IO_IP_CFPID;
+			break;
+		case SLIMBUS_PORT_PROT:
+			atc_desc_address1 = abe_port[id].protocol.p.prot_slimbus.desc_addr1;
+			atc_desc_address2 = abe_port[id].protocol.p.prot_slimbus.desc_addr2;
+			copy_func_index2 = NULL_COPY_CFPID;
+/* @@@@@@
+#define SPLIT_SMEM_CFPID	9
+#define MERGE_SMEM_CFPID	10
+#define SPLIT_TDM_12_CFPID	11
+#define MERGE_TDM_12_CFPID	12
+*/
+				io_sub_id = IO_IP_CFPID;
+		case SERIAL_PORT_PROT: /* McBSP/McASP */
+			atc_desc_address1  = (abe_int16) abe_port[id].protocol.p.prot_serial.desc_addr;
+				io_sub_id = IO_IP_CFPID;
+			break;
+		case DMAREQ_PORT_PROT: /* DMA w/wo CBPr */
+			dmareq_addr = abe_port[id].protocol.p.prot_dmareq.dma_addr;
+			dmareq_field = 0;
+			atc_desc_address1 = abe_port[id].protocol.p.prot_dmareq.desc_addr;
+			io_sub_id = IO_DMAREQ_CFPID;
+			break;
+		default:
+			break;
+		}
+
+		/* special situation of the PING_PONG protocol which has its own SIO descriptor format */
+		/* Sequence of operations on ping-pong buffers B0/B1
+		 * ---------- time --------------------------------------------->>>>
+		 * Host Application  is ready to send data from DDR to B0
+		 * SDMA is initialized from "abe_connect_irq_ping_pong_port" to B0
+		 * ABE HAL init FW to B0
+		 * send DMAreq to fill B0
+		 * FIRMWARE starts sending B1 data, sends DMAreq v
+		 * continue with B0, sends DMAreq v   continue with B1
+		 * DMAreq v (direct access from HAL to AESS regs)
+		 * v (from ABE_FW) v (from ABE_FW)
+		 * SDMA | fills B0 | fills B1...| fills B0...
+		 */
+
+		if (MM_UL_PORT == id) {
+			copy_func_index1 = COPY_MM_UL_CFPID;
+			before_func_index = ROUTE_MM_UL_CFPID;
+		}
+
+		/* check for 8kHz/16kHz */
+		if (VX_DL_PORT == id) {
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR,
+				(abe_uint32*)MultiFrame, sizeof (MultiFrame));
+			if (abe_port[id].format.f == 8000) {
+				//@@@ MultiFrame[TASK_ASRC_VX_DL_SLT][TASK_ASRC_VX_DL_IDX]  = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_DL_8;
+				MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] =
+						D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_DL_8_48;
+				smem1 = Voice_8k_DL_labelID; //@@@ IO_VX_DL_ASRC_labelID
+			} else {
+				//@@@ MultiFrame[TASK_ASRC_VX_DL_SLT][TASK_ASRC_VX_DL_IDX]  = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_DL_16;
+				MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_DL_16_48;
+				smem1 = Voice_16k_DL_labelID; //@@@ IO_VX_DL_ASRC_labelID
+			}
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR,
+				(abe_uint32*)MultiFrame, sizeof (MultiFrame));
+		}
+		/* check for 8kHz/16kHz */
+		if (VX_UL_PORT == id) {
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof(MultiFrame));
+			if (abe_port[id].format.f == 8000) {
+				//@@@ MultiFrame[TASK_ASRC_VX_UL_SLT][TASK_ASRC_VX_UL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_UL_8;
+				MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_UL_48_8;
+				//@@@ MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ECHO_REF_48_8;
+				//@@@ MultiFrame[TASK_ASRC_ECHO_SLT][TASK_ASRC_ECHO_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_ECHO_REF_8;
+				smem1 = Voice_8k_UL_labelID; //@@@ XinASRC_UL_VX_labelID
+			} else {
+				//@@@ MultiFrame[TASK_ASRC_VX_UL_SLT][TASK_ASRC_VX_UL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_UL_16;
+				MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_UL_48_16;
+				//@@@ MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ECHO_REF_48_16;
+				//@@@ MultiFrame[TASK_ASRC_ECHO_SLT][TASK_ASRC_ECHO_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_ECHO_REF_16;
+				smem1 = Voice_16k_UL_labelID; //@@@ XinASRC_UL_VX_labelID
+			}
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof(MultiFrame));
+		}
+
+		/* check for 8kHz/16kHz */
+		if (BT_VX_DL_PORT == id) {
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+					D_multiFrame_ADDR,
+						(abe_uint32*)MultiFrame,
+							sizeof (MultiFrame));
+			if (abe_port[id].format.f == 8000) {
+				MultiFrame[TASK_BT_DL_48_8_SLT][TASK_BT_DL_48_8_IDX] =
+					D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_DL_48_8;
+				smem1 = BT_DL_8k_labelID;
+			} else {
+				MultiFrame[TASK_BT_DL_48_8_SLT][TASK_BT_DL_48_8_IDX] =
+					D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_DL_48_16;
+				smem1 = BT_DL_16k_labelID;
+			}
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				D_multiFrame_ADDR, (abe_uint32*)MultiFrame,
+							sizeof (MultiFrame));
+		}
+
+		/* check for 8kHz/16kHz */
+		if (BT_VX_UL_PORT == id) {
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR,
+				(abe_uint32*)MultiFrame, sizeof (MultiFrame));
+			if (abe_port[id].format.f == 8000) {
+				MultiFrame[TASK_BT_UL_8_48_SLT][TASK_BT_UL_8_48_IDX] =
+					D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_UL_8_48;
+				smem1 = BT_UL_8k_labelID;
+			} else {
+				MultiFrame[TASK_BT_UL_8_48_SLT][TASK_BT_UL_8_48_IDX] =
+					D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_UL_16_48;
+				smem1 = BT_UL_16k_labelID;
+			}
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				D_multiFrame_ADDR, (abe_uint32*)MultiFrame,
+							sizeof (MultiFrame));
+		}
+
+		if (MM_DL_PORT == id) {
+			//@@@ abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame));
+			//@@@ MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO2_MM_DL;
+			//@@@ abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame));
+			/* set the SMEM buffer @@@@@ programming sequence : OPP must be set before channel is defined */
+			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_maxTaskBytesInSlot_ADDR, &dOppMode32, sizeof(abe_uint32));
+			if (dOppMode32 == DOPPMODE32_OPP100)
+				smem1 = smem_mm_dl_opp100; /* ASRC input buffer, size 40 */
+			else
+				smem1 = smem_mm_dl_opp25; /* at OPP 25/50 or without ASRC  */
+		}
+		/* MM_EXT_IN takes the PDM_UL path */
+		if (MM_EXT_IN_PORT == id) {
+			/* set the PDM_UL SMEM buffer to /nul */
+			sio_desc_address = dmem_port_descriptors + (PDM_UL_PORT * sizeof(ABE_SIODescriptor));
+			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, (abe_uint32*)&desc, sizeof(desc));
+			desc.smem_addr1 = (abe_uint16) Dummy_AM_labelID;
+			abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, (abe_uint32*)&desc, sizeof(desc));
+		}
+
+		if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
+			direction = 0;
+		else
+			direction = 3; /* offset of the write pointer in the ATC descriptor */
+
+		desc.drift_ASRC = 0;
+		desc.drift_io = 0;
+		desc.io_type_idx = (abe_uint8) io_sub_id;
+		desc.samp_size = (abe_uint8) datasize;
+		//desc.unused1 = (abe_uint8)0;
+		//desc.unused2 = (abe_uint8)0;
+
+		desc.hw_ctrl_addr = (abe_uint16) (dmareq_addr << 2);
+		desc.atc_irq_data = (abe_uint8) dmareq_field;
+		desc.flow_counter = (abe_uint16) 0;
+
+		desc.direction_rw = (abe_uint8) direction;
+		desc.nsamp = (abe_uint8) nsamp;
+		desc.x_io = (abe_uint8) x_io;
+		desc.on_off = 0x80; // set ATC ON
+
+		desc.split_addr1 = (abe_uint16) smem1;
+		desc.split_addr2 = (abe_uint16) smem2;
+		desc.split_addr3 = (abe_uint16) smem3;
+		desc.before_f_index = (abe_uint8) before_func_index;
+		desc.after_f_index = (abe_uint8) after_func_index;
+
+		desc.smem_addr1 = (abe_uint16) smem1;
+		desc.atc_address1 = (abe_uint16) atc_desc_address1;
+		desc.atc_pointer_saved1 = (abe_uint16) atc_ptr_saved;
+		desc.data_size1 = (abe_uint8) datasize;
+		desc.copy_f_index1 = (abe_uint8) copy_func_index1;
+
+		desc.smem_addr2 = (abe_uint16) smem2;
+		desc.atc_address2 = (abe_uint16) atc_desc_address2;
+		desc.atc_pointer_saved2 = (abe_uint16) atc_ptr_saved2;
+		desc.data_size2 = (abe_uint8) datasize2;
+		desc.copy_f_index2 = (abe_uint8) copy_func_index2;
+
+		sio_desc_address = dmem_port_descriptors + (id * sizeof(ABE_SIODescriptor));
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			sio_desc_address, (abe_uint32*)&desc, sizeof(desc));
+	}
+}
+
+/*
+ *  ABE_INIT_DMIC
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_init_dmic(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+
+/*
+ *  ABE_INIT_MCPDM
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_init_mcpdm(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+
+/*
+ *  ABE_RESET_FEATURE
+ *
+ *  Parameter  :
+ *      x : index of the feature to be initialized
+ *
+ *  Operations :
+ *      reload the configuration
+ *
+ *  Return value :
+ *
+ */
+void abe_reset_one_feature(abe_uint32 x)
+{
+	all_feature[x] = all_feature_init[x];	/* load default fields */
+	/* abe_call_subroutine ((all_feature[x]).disable_feature, NOPARAMETER, NOPARAMETER, NOPARAMETER, NOPARAMETER);  */
+}
+
+/*
+ *  ABE_RESET_ALL_FEATURE
+ *
+ *  Parameter  :
+ *      none
+ *
+ *  Operations :
+ *      load default configuration for all features
+ *	 struct {
+ *		uint16 load_default_data;
+ *		uint16 read_parameter;
+ *		uint16 write_parameter;
+ *		uint16 running_status;
+ *		uint16 fw_input_buffer_address;
+ *		uint16 fw_output_buffer_address;
+ *		uint16 fw_scheduler_slot_position;
+ *		uint16 fw_scheduler_subslot_position;
+ *		uint16 min_opp;
+ *		char name[NBCHARFEATURENAME];
+ *	} abe_feature_t;
+ *
+ *  Return value :
+ *
+ */
+void abe_reset_all_features(void)
+{
+	abe_uint16 i;
+
+	for (i = 0; i < FEAT_GAINS_DMIC1; i++)
+		abe_reset_one_feature(i);
+}
+
+/*
+ *  ABE_RESET_ALL_PORTS
+ *
+ *  Parameter  :
+ *      none
+ *
+ *  Operations :
+ *      load default configuration for all features
+ *
+ *  Return value :
+ *
+ */
+void abe_reset_all_ports(void)
+{
+	abe_uint16 i;
+
+	for (i = 0; i < MAXNBABEPORTS; i++)
+		abe_reset_port(i);
+
+	/* mixers' configuration */
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_DL);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_UL2);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_VX_DL);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_TONES);
+
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_TONES);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_VX_DL);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_DL);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_UL2);
+
+	abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_100MS, MIX_SDT_INPUT_UP_MIXER);
+	abe_write_mixer(MIXSDT, GAIN_0dB , RAMP_100MS, MIX_SDT_INPUT_DL1_MIXER);
+
+	abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_MM_DL);
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_TONES);
+	abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_100MS, MIX_AUDUL_INPUT_UPLINK);
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_VX_DL);
+
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_TONES);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_DL);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_MM_DL);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_UL);
+
+	abe_write_gain(GAINS_DMIC1,GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DMIC1,GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_DMIC2,GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DMIC2,GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_DMIC3,GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DMIC3,GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_AMIC,GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+
+	abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	//abe_write_gain(GAINS_EANC ,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
+	//abe_write_gain(GAINS_EANC, GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
+
+	/*@@@Gain set to -6dB due to McPDM Limitation*/
+	/* cf CDDS  00635*/
+	abe_write_gain(GAINS_DL1, GAIN_M6dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DL1, GAIN_M6dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_DL2, GAIN_M6dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DL2, GAIN_M6dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+}
+
+/*
+ *	ABE_CLEAN_TEMPORARY_BUFFERS
+ *
+ *	Parameter  :
+ *	none
+ *
+ *	Operations :
+ *	clear temporary buffers
+ *
+ *	Return value :
+ *
+ */
+void abe_clean_temporary_buffers(abe_port_id id)
+{
+	switch (id) {
+	case DMIC_PORT:
+		abe_reset_mem(ABE_DMEM, D_DMIC_UL_FIFO_ADDR,D_DMIC_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_DMIC0_96_48_data_ADDR << 3, S_DMIC0_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_DMIC1_96_48_data_ADDR << 3, S_DMIC1_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3, S_DMIC1_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR+dmic1_gains_offset) << 2, 6 << 2); /* reset current gains */
+		abe_reset_mem(ABE_SMEM, (S_GCurrent_ADDR+dmic1_gains_offset) << 3, 6 << 3);
+		break;
+	case PDM_UL_PORT:
+		abe_reset_mem(ABE_DMEM, D_McPDM_UL_FIFO_ADDR, D_McPDM_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_AMIC_96_48_data_ADDR << 3, S_AMIC_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR+amic_gains_offset) << 2, 2 << 2); /* reset current gains */
+		abe_reset_mem(ABE_SMEM, (S_GCurrent_ADDR+amic_gains_offset) << 3, 6 << 3);
+		break;
+	case BT_VX_UL_PORT:	// ABE <-- BT (8/16kHz)
+		abe_reset_mem(ABE_DMEM, D_BT_UL_FIFO_ADDR, D_BT_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3);
+		break;
+	case MM_UL_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_UL_FIFO_ADDR, D_MM_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_MM_UL_ADDR << 3, S_MM_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_MM_UL2_ADDR << 3, D_MM_UL2_FIFO_sizeof << 3);
+		break;
+	case MM_UL2_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_UL2_FIFO_ADDR, D_MM_UL2_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_MM_UL2_ADDR << 3, S_MM_UL2_sizeof << 3);
+		break;
+	case VX_UL_PORT:
+		abe_reset_mem(ABE_DMEM, D_VX_UL_FIFO_ADDR, D_VX_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_ADDR << 3, S_VX_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_48_8_BP_data_ADDR << 3, S_VX_UL_48_8_BP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_48_8_LP_data_ADDR << 3, S_VX_UL_48_8_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_48_16_HP_data_ADDR << 3, S_VX_UL_48_16_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_48_16_LP_data_ADDR << 3, S_VX_UL_48_16_LP_data_sizeof << 3);
+		break;
+	case MM_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_DL_FIFO_ADDR, D_MM_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_MM_DL_ADDR << 3,  S_MM_DL_sizeof << 3);
+		break;
+	case VX_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_VX_DL_FIFO_ADDR, D_VX_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_ADDR << 3, S_VX_DL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_8_48_BP_data_ADDR << 3, S_VX_DL_8_48_BP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_8_48_LP_data_ADDR << 3, S_VX_DL_8_48_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_16_48_HP_data_ADDR << 3, S_VX_DL_16_48_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_16_48_LP_data_ADDR << 3, S_VX_DL_16_48_LP_data_sizeof << 3);
+		break;
+	case TONES_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_TONES_DL_FIFO_ADDR, D_TONES_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_Tones_ADDR << 3, S_Tones_sizeof << 3);
+		break;
+	case VIB_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_VIB_DL_FIFO_ADDR, D_VIB_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_VIBRA_ADDR << 3, S_VIBRA_sizeof << 3);
+		break;
+	case BT_VX_DL_PORT:// ABE --> BT (8/16kHz)
+		abe_reset_mem(ABE_DMEM, D_BT_DL_FIFO_ADDR, D_BT_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_BT_DL_ADDR << 3, S_BT_DL_sizeof << 3);
+		break;
+	case PDM_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_McPDM_DL_FIFO_ADDR, D_McPDM_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3, S_DMIC1_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_DL2_M_LR_EQ_data_ADDR << 3, S_DL2_M_LR_EQ_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_DL1_M_EQ_data_ADDR << 3, S_DL1_M_EQ_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_EARP_48_96_LP_data_ADDR << 3, S_EARP_48_96_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_IHF_48_96_LP_data_ADDR << 3, S_IHF_48_96_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_APS_DL1_EQ_data_ADDR << 3, S_APS_DL1_EQ_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_APS_DL2_EQ_data_ADDR << 3, S_APS_DL2_EQ_data_sizeof << 3);
+		break;
+	case MM_EXT_OUT_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_EXT_OUT_FIFO_ADDR, D_MM_EXT_OUT_FIFO_sizeof);
+		break;
+	case MM_EXT_IN_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_EXT_IN_FIFO_ADDR, D_MM_EXT_IN_FIFO_sizeof);
+		break;
+	default:
+		break;
+	}
+}
diff --git a/sound/soc/codecs/abe/abe_initxxx_labels.h b/sound/soc/codecs/abe/abe_initxxx_labels.h
new file mode 100644
index 000000000000..d18907dbf6a6
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_initxxx_labels.h
@@ -0,0 +1,293 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_INITXXX_LABELS_H_
+#define _ABE_INITXXX_LABELS_H_
+
+#define Dummy_Regs_labelID			0
+#define Dummy_AM_labelID			1
+#define Voice_8k_UL_labelID			2
+#define Voice_8k_DL_labelID			3
+#define ECHO_REF_8K_labelID			4
+#define Voice_16k_UL_labelID			5
+#define Voice_16k_DL_labelID			6
+#define ECHO_REF_16K_labelID			7
+#define MM_DL_labelID				8
+#define IO_VX_DL_ASRC_labelID			9
+#define IO_MM_DL_ASRC_labelID			10
+#define IO_VIBRA_DL_labelID			11
+#define ZERO_labelID				12
+#define GTarget_labelID				13
+#define GCurrent_labelID			14
+#define Gr_1_labelID				15
+#define Gr_2_labelID				16
+#define Gr_Regs_labelID				17
+#define DMIC0_Gain_labelID			18
+#define DMIC1_Gain_labelID			19
+#define DMIC2_Gain_labelID			20
+#define DMIC3_Gain_labelID			21
+#define AMIC_Gain_labelID			22
+#define DL1_Gain_labelID			23
+#define DL2_Gain_labelID			24
+#define DEFAULT_Gain_labelID			25
+#define DL1_M_G_Tones_labelID			26
+#define DL2_M_G_Tones_labelID			27
+#define Echo_M_G_labelID			28
+#define SDT_M_G_labelID				29
+#define VXREC_M_G_VX_DL_labelID			30
+#define UL_M_G_VX_DL_labelID			31
+#define DL1_M_labelID				32
+#define DL2_M_labelID				33
+#define MM_UL2_labelID				34
+#define VX_DL_labelID				35
+#define Tones_labelID				36
+#define DL_M_MM_UL2_VX_DL_labelID		37
+#define Echo_M_labelID				38
+#define VX_UL_labelID				39
+#define VX_UL_M_labelID				40
+#define SDT_F_labelID				41
+#define SDT_F_data_labelID			42
+#define SDT_Coef_labelID			43
+#define SDT_Regs_labelID			44
+#define SDT_M_labelID				45
+#define DL1_labelID				46
+#define DMIC1_labelID				47
+#define DMIC1_L_labelID				48
+#define DMIC1_R_labelID				49
+#define DMIC2_labelID				50
+#define DMIC2_L_labelID				51
+#define DMIC2_R_labelID				52
+#define DMIC3_labelID				53
+#define DMIC3_L_labelID				54
+#define DMIC3_R_labelID				55
+#define BT_UL_L_labelID				56
+#define BT_UL_R_labelID				57
+#define AMIC_labelID				58
+#define AMIC_L_labelID				59
+#define AMIC_R_labelID				60
+#define EANC_FBK_In_labelID			61
+#define EANC_FBK_Out_labelID			62
+#define EANC_FBK_L_labelID			63
+#define EANC_FBK_R_labelID			64
+#define EchoRef_L_labelID			65
+#define EchoRef_R_labelID			66
+#define MM_DL_L_labelID				67
+#define MM_DL_R_labelID				68
+#define MM_UL_labelID				69
+#define AMIC_96_labelID				70
+#define DMIC0_96_labelID			71
+#define DMIC1_96_labelID			72
+#define DMIC2_96_labelID			73
+#define DMIC_desc_labelID			74
+#define UL_MIC_48K_labelID			75
+#define EQ_DL_48K_labelID			76
+#define EQ_48K_labelID				77
+#define UP_DOWN_8_48_labelID			78
+#define McPDM_Out1_labelID			79
+#define McPDM_Out2_labelID			80
+#define McPDM_Out3_labelID			81
+#define VX_UL_MUX_labelID			82
+#define MM_UL2_MUX_labelID			83
+#define MM_UL_MUX_labelID			84
+#define XinASRC_DL_VX_labelID			85
+#define ASRC_DL_VX_Coefs_labelID		86
+#define ASRC_DL_VX_Alpha_labelID		87
+#define ASRC_DL_VX_VarsBeta_labelID		88
+#define ASRC_DL_VX_8k_Regs_labelID		89
+#define XinASRC_UL_VX_labelID			90
+#define ASRC_UL_VX_Coefs_labelID		91
+#define ASRC_UL_VX_Alpha_labelID		92
+#define ASRC_UL_VX_VarsBeta_labelID		93
+#define ASRC_UL_VX_8k_Regs_labelID		94
+#define UL_48_8_DEC_labelID			95
+#define UP_DOWN_16_48_labelID			96
+#define ASRC_DL_VX_16k_Regs_labelID		97
+#define ASRC_UL_VX_16k_Regs_labelID		98
+#define UL_48_16_DEC_labelID			99
+#define XinASRC_DL_MM_labelID			100
+#define ASRC_DL_MM_Coefs_labelID		101
+#define ASRC_DL_MM_Alpha_labelID		102
+#define ASRC_DL_MM_VarsBeta_labelID		103
+#define ASRC_DL_MM_Regs_labelID			104
+#define VX_REC_labelID				105
+#define VXREC_UL_M_Tones_VX_UL_labelID		106
+#define VX_REC_L_labelID			107
+#define VX_REC_R_labelID			108
+#define DL2_M_L_labelID				109
+#define DL2_M_R_labelID				110
+#define DL1_M_data_labelID			111
+#define DL1_M_Coefs_labelID			112
+#define DL2_M_LR_data_labelID			113
+#define DL2_M_LR_Coefs_labelID			114
+#define VX_DL_8_48_LP_COEFS_labelID		115
+#define VX_DL_8_48_BP_COEFS_labelID		116
+#define VX_DL_8_48_BP_DATA_labelID		117
+#define VX_DL_8_48_LP_DATA_labelID		118
+#define SRC_BP_8K_48K_labelID			119
+#define SRC_HP_16K_48K_labelID			120
+#define SRC_LP_48K_labelID			121
+#define EARP_48_96_LP_DATA_labelID		122
+#define SRC_48_96_LP_labelID			123
+#define IHF_48_96_LP_DATA_labelID		124
+#define VX_DL_16_48_HP_COEFS_labelID		125
+#define VX_DL_16_48_LP_COEFS_labelID		126
+#define VX_DL_16_48_HP_DATA_labelID		127
+#define VX_DL_16_48_LP_DATA_labelID		128
+#define VX_UL_48_8_LP_COEFS_labelID		129
+#define VX_UL_48_8_BP_DATA_labelID		130
+#define VX_UL_48_8_LP_DATA_labelID		131
+#define VX_UL_8_TEMP_labelID			132
+#define VX_UL_48_16_LP_COEFS_labelID		133
+#define VX_UL_48_16_HP_DATA_labelID		134
+#define VX_UL_48_16_LP_DATA_labelID		135
+#define EQ_VX_UL_16K_labelID			136
+#define VX_UL_16_TEMP_labelID			137
+#define pAPS_iir1_p23_labelID			138
+#define pAPS_iir1_p45_labelID			139
+#define APS_IIR_Regs_labelID			140
+#define pAPS_core_DL1_p1_labelID		141
+#define pAPS_core_DL1_p23_labelID		142
+#define pAPS_core_DL1_p45_labelID		143
+#define pAPS_core_DL1_r_labelID			144
+#define pAPS_DL2L_core_r_labelID		145
+#define pAPS_DL2R_core_r_labelID		146
+#define pAPS_COIL_core_DL1_p1_labelID		147
+#define pAPS_COIL_core_DL1_p23_labelID		148
+#define pAPS_COIL_core_DL1_p45_labelID		149
+#define pAPS_COIL_core_DL1_r_labelID		150
+#define XinASRC_ECHO_REF_labelID		151
+#define ASRC_ECHO_REF_Coefs_labelID		152
+#define ASRC_ECHO_REF_Alpha_labelID		153
+#define ASRC_ECHO_REF_VarsBeta_labelID		154
+#define ASRC_ECHO_REF_8k_Regs_labelID		155
+#define ASRC_ECHO_REF_16k_Regs_labelID		156
+#define DL2_L_APS_IIR_p23_labelID		157
+#define DL2_R_APS_IIR_p23_labelID		158
+#define DL2_L_APS_IIR_p45_labelID		159
+#define DL2_R_APS_IIR_p45_labelID		160
+#define DL2_L_APS_CORE_p1_labelID		161
+#define DL2_L_APS_CORE_p23_labelID		162
+#define DL2_L_APS_CORE_p45_labelID		163
+#define DL2_R_APS_CORE_p1_labelID		164
+#define DL2_R_APS_CORE_p23_labelID		165
+#define DL2_R_APS_CORE_p45_labelID		166
+#define DL2_L_APS_COIL_CORE_p1_labelID		167
+#define DL2_L_APS_COIL_CORE_p23_labelID		168
+#define DL2_L_APS_COIL_CORE_p45_labelID		169
+#define pAPS_COIL_DL2L_core_r_labelID		170
+#define DL2_R_APS_COIL_CORE_p1_labelID		171
+#define DL2_R_APS_COIL_CORE_p23_labelID		172
+#define DL2_R_APS_COIL_CORE_p45_labelID		173
+#define pAPS_COIL_DL2R_core_r_labelID		174
+#define DL1_APS_labelID				175
+#define DL2_L_APS_labelID			176
+#define DL2_R_APS_labelID			177
+#define ECHO_REF_48_16_HP_DATA_labelID		178
+#define ECHO_REF_48_16_LP_DATA_labelID		179
+#define ECHO_REF_48_8_BP_DATA_labelID		180
+#define ECHO_REF_48_8_LP_DATA_labelID		181
+#define ECHO_REF_DEC_labelID			182
+#define pEANC_p0_labelID			183
+#define pEANC_p1_labelID			184
+#define pEANC_p23_labelID			185
+#define pEANC_p45_labelID			186
+#define pEANC_reg1_labelID			187
+#define pEANC_reg2_labelID			188
+#define pEANC_reg3_labelID			189
+#define pEANC_r_labelID				190
+#define DL1_APS_EQ_p23_labelID			191
+#define DL1_APS_EQ_p45_labelID			192
+#define DL2_APS_EQ_p23_labelID			193
+#define DL2_APS_EQ_p45_labelID			194
+#define pDC_EANC_p23_labelID			195
+#define pDC_EANC_r_labelID			196
+#define pVIBRA1_p0_labelID			197
+#define pVIBRA1_p1_labelID			198
+#define pVIBRA1_p23_labelID			199
+#define pVIBRA1_p45_labelID			200
+#define pVibra1_pR1_labelID			201
+#define pVibra1_pR2_labelID			202
+#define pVibra1_pR3_labelID			203
+#define pVIBRA1_r_labelID			204
+#define pVIBRA2_p0_labelID			205
+#define pVIBRA2_p1_labelID			206
+#define pVIBRA2_p23_labelID			207
+#define pVIBRA2_p45_labelID			208
+#define pCtrl_p67_labelID			209
+#define pVIBRA2_r_labelID			210
+#define VIBRA_labelID				211
+#define PING_labelID				212
+#define PING_Regs_labelID			213
+#define UP_48_96_LP_COEFS_labelID		214
+#define AMIC_96_48_data_labelID			215
+#define DOWN_96_48_Coefs_labelID		216
+#define DOWN_96_48_Regs_labelID			217
+#define DMIC0_96_48_data_labelID		218
+#define DMIC1_96_48_data_labelID		219
+#define DMIC2_96_48_data_labelID		220
+#define EANC_FBK_96_48_data_labelID		221
+#define pDC_EANC_r2_labelID			222
+#define SIO_DMIC_labelID			223
+#define SIO_PDM_UL_labelID			224
+#define SIO_BT_VX_UL_labelID			225
+#define SIO_MM_UL_labelID			226
+#define SIO_MM_UL2_labelID			227
+#define SIO_VX_UL_labelID			228
+#define SIO_MM_DL_labelID			229
+#define SIO_VX_DL_labelID			230
+#define SIO_TONES_DL_labelID			231
+#define SIO_VIB_DL_labelID			232
+#define SIO_BT_VX_DL_labelID			233
+#define SIO_PDM_DL_labelID			234
+#define SIO_MM_EXT_OUT_labelID			235
+#define SIO_MM_EXT_IN_labelID			236
+#define DMIC_ATC_PTR_labelID			237
+#define MCPDM_UL_ATC_PTR_labelID		238
+#define BT_VX_UL_ATC_PTR_labelID		239
+#define MM_UL_ATC_PTR_labelID			240
+#define MM_UL2_ATC_PTR_labelID			241
+#define VX_UL_ATC_PTR_labelID			242
+#define MM_DL_ATC_PTR_labelID			243
+#define VX_DL_ATC_PTR_labelID			244
+#define TONES_DL_ATC_PTR_labelID		245
+#define VIB_DL_ATC_PTR_labelID			246
+#define BT_VX_DL_ATC_PTR_labelID		247
+#define PDM_DL_ATC_PTR_labelID			248
+#define MM_EXT_OUT_ATC_PTR_labelID		249
+#define MM_EXT_IN_ATC_PTR_labelID		250
+#define MCU_IRQ_FIFO_ptr_labelID		251
+#define DEBUG_ATC_ptrs_labelID			252
+#define DEBUG_IRQ_FIFO_reg_labelID		253
+#define UP_DOWN_48_96_labelID			254
+#define OSR96_2_labelID				255
+#define DEBUG_GAINS_labelID			256
+#define DBG_8K_PATTERN_labelID			257
+#define DBG_16K_PATTERN_labelID			258
+#define DBG_48K_PATTERN_labelID			259
+#define DBG_MCPDM_PATTERN_labelID		260
+#define SMEM_TEST_PATTERN_labelID		261
+#define UL_VX_UL_48_8K_labelID			262
+#define UL_VX_UL_48_16K_labelID			263
+#define BT_UL_8_48_BP_DATA_labelID		264
+#define BT_UL_8_48_LP_DATA_labelID		265
+#define BT_UL_16_48_HP_DATA_labelID		266
+#define BT_UL_16_48_LP_DATA_labelID		267
+#define BT_DL_48_8_BP_DATA_labelID		268
+#define BT_DL_48_8_LP_DATA_labelID		269
+#define BT_DL_48_16_HP_DATA_labelID		270
+#define BT_DL_48_16_LP_DATA_labelID		271
+#define BT_DL_labelID				272
+#define BT_UL_labelID				273
+#define BT_DL_8k_labelID			274
+#define BT_DL_16k_labelID			275
+#define BT_UL_8k_labelID			276
+#define BT_UL_16k_labelID			277
+
+#endif	/* _ABE_INITXXXX_LABELS_H_ */
diff --git a/sound/soc/codecs/abe/abe_irq.c b/sound/soc/codecs/abe/abe_irq.c
new file mode 100644
index 000000000000..61bd1263c0da
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_irq.c
@@ -0,0 +1,71 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_main.h"
+
+/*
+ *  initialize the default values for call-backs to subroutines
+ *      - FIFO IRQ call-backs for sequenced tasks
+ *      - FIFO IRQ call-backs for audio player/recorders (ping-pong protocols)
+ *      - Remote debugger interface
+ *      - Error monitoring
+ *      - Activity Tracing
+ */
+
+/*
+ * ABE_IRQ_PING_PONG
+ * Parameter  :
+ * No parameter
+ *
+ * Operations :
+ * Call the respective subroutine depending on the IRQ FIFO content:
+ * APS interrupts : IRQtag_APS to [31:28], APS_IRQs to [27:16], loopCounter to [15:0]
+ * SEQ interrupts : IRQtag_COUNT to [31:28], Count_IRQs to [27:16], loopCounter to [15:0]
+ * Ping-Pong Interrupts : IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], loopCounter to [15:0]
+ * Check for ping-pong subroutines (low-power players)
+ *
+ * Return value :
+ * None.
+ */
+void abe_irq_ping_pong(void)
+{
+	abe_call_subroutine(abe_irq_pingpong_player_id, NOPARAMETER, NOPARAMETER, NOPARAMETER, NOPARAMETER);
+}
+
+/*
+ * ABE_IRQ_CHECK_FOR_SEQUENCES
+ * Parameter  :
+ * No parameter
+ *
+ * Operations :
+ * check the active sequence list
+ *
+ * Return value :
+ * None.
+ */
+void abe_irq_check_for_sequences(abe_uint32 i)
+{
+}
+
+/*
+ * ABE_IRQ_APS
+ * Parameter  :
+ * No parameter
+ *
+ * Operations :
+ * call the application subroutines that updates the acoustics protection filters
+ *
+ * Return value :
+ * None.
+ */
+void abe_irq_aps(abe_uint32 aps_info)
+{
+	abe_call_subroutine(abe_irq_aps_adaptation_id, NOPARAMETER, NOPARAMETER, NOPARAMETER, NOPARAMETER);
+}
diff --git a/sound/soc/codecs/abe/abe_lib.c b/sound/soc/codecs/abe/abe_lib.c
new file mode 100644
index 000000000000..a7f44fcc5799
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_lib.c
@@ -0,0 +1,719 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_main.h"
+#include <linux/io.h>
+
+void __iomem *io_base;
+
+void abe_init_mem()
+{
+	io_base = ioremap(L4_ABE_44XX_PHYS, SZ_1M);
+}
+
+#define ABE_PMEM_BASE_OFFSET_MPU	0xe0000
+#define ABE_CMEM_BASE_OFFSET_MPU	0xa0000
+#define ABE_SMEM_BASE_OFFSET_MPU	0xc0000
+#define ABE_DMEM_BASE_OFFSET_MPU	0x80000
+#define ABE_ATC_BASE_OFFSET_MPU		0xf1000
+
+#if 0
+/*
+ *  ABE_TRANSLATE_TO_XMEM_FORMAT
+ *
+ *  Parameter  :
+ *  Operations :
+ *      translates a floating point data to the cmem/smem/dmem data format
+ *  Return value :
+ *      None.
+ */
+void abe_translate_to_xmem_format(abe_int32 memory_bank, abe_float fc, abe_uint32 *c)
+{
+	abe_int32 l;
+	abe_float afc;
+
+	l = 0;
+	afc = absolute(fc);
+
+	switch (memory_bank) {
+	case ABE_CMEM:
+		if (afc >= 1.0 && afc < 32.0) {
+			/* ALU post shifter +6 */
+			l = (abe_int32)(fc * (1 << 16));
+			l = (l << 2) + 2;
+		} else if (afc >= 0.5 && afc < 1.0) {
+			/* ALU post shifter +1 */
+			l = (abe_int32)(fc * (1 << 21));
+			l = (l << 2) + 1;
+		} else if (afc >= 0.25 && afc < 0.5) {
+			/* ALU post shifter 0 */
+			l = (abe_int32)(fc * (1 << 22));
+			l = (l << 2) + 0;
+		} else if (afc < 0.25) {
+			/* ALU post shifter -6 */
+			l = (abe_int32)(fc * (1 << 28));
+			l = (l << 2) + 3;
+		}
+		break;
+	case ABE_SMEM:
+		/* Q23 data format */
+		l = (abe_int32)(fc * (1 << 23));
+		break;
+	case ABE_DMEM:
+		/* Q31 data format (1<<31)=0 */
+		l = (abe_int32)(fc * 2* (1 << 30));
+		break;
+	default: /* ABE_PMEM */
+		/* Q31 data format */
+		l = (abe_int32)(2 * fc * 2* (1 << 30));
+		break;
+	}
+
+	*c = l;
+}
+
+/*
+ *  ABE_TRANSLATE_GAIN_FORMAT
+ *
+ *  Parameter  :
+ *  Operations :
+ *    f: original format name for gain or frequency.
+ *       1=linear ABE => decibels
+ *       2=decibels  => linear ABE firmware format
+ *
+ *      lin = power(2, decibel/602); lin = [0.0001 .. 30.0]
+ *      decibel = 6.02 * log2(lin), decibel = [-70 .. +30]
+ *
+ *    g1: pointer to the original data
+ *    g2: pointer to the translated gain data
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_translate_gain_format(abe_uint32 f, abe_float g1, abe_float *g2)
+{
+	abe_float g, frac_part, gg1, gg2;
+	abe_int32 int_part, i;
+
+	#define C_20LOG2 ((abe_float)6.020599913)
+
+	gg1 = (g1);
+	int_part = 0;
+	frac_part = gg2 = 0;
+
+	switch (f) {
+	case DECIBELS_TO_LINABE:
+		g = gg1 / C_20LOG2;
+		int_part = (abe_int32) g;
+		frac_part = g - int_part;
+
+		gg2 = abe_power_of_two(frac_part);
+
+		if (int_part > 0)
+			gg2 = gg2 * (1 << int_part);
+		else
+			gg2 = gg2 / (1 << (-int_part));
+
+		break;
+	case LINABE_TO_DECIBELS:
+		if (gg1 == 1.0) {
+			gg2 = 0.0;
+			return;
+		}
+
+		/* find the power of 2 by iteration */
+		if (gg1 > 1.0) {
+			for (i = 0; i < 63; i++) {
+				if ((1 << i) > gg1) {
+					int_part = (i-1);
+					frac_part = gg1 / (1 << int_part);
+					break;
+				}
+			}
+			gg2 = C_20LOG2 * (int_part + abe_log_of_two(frac_part));
+		} else {
+			for (i = 0; i < 63; i++) {
+				if (((1 << i) * gg1) > 1) {
+					int_part = i;
+					frac_part = gg1 * (1 << int_part);
+					break;
+				}
+			}
+			/* compute the dB using polynomial
+			 * interpolation in the [1..2] range
+			 */
+			gg2 = C_20LOG2 * (((-1)*int_part) + abe_log_of_two(frac_part));}
+		break;
+	}
+
+	*g2 = gg2;
+ }
+
+/*
+ *  ABE_TRANSLATE_RAMP_FORMAT
+ *
+ *  Parameter  :
+ *  Operations :
+ *    f: original format name for gain or frequency.
+ *       1=ABE IIR coef => microseconds
+ *       2=microseconds => ABE IIR coef
+ *
+ *    g1: pointer to the original data
+ *    g2: pointer to the translated gain data
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_translate_ramp_format(abe_float ramp, abe_float *ramp_iir1)
+{
+	*ramp_iir1   = 0.125;
+}
+
+/*
+ *  ABE_TRANSLATE_EQU_FORMAT
+ *
+ *  Parameter  :
+ *  Operations :
+ *     Translate
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_translate_equ_format(abe_equ_t *p, abe_float *iir, abe_uint32 n)
+{
+#if 0
+	switch (p->type
+typedef struct {
+		abe_iir_t equ_param1;	   /* type of filter */
+		abe_uint32 equ_param2;	  /* filter length */
+		union {			 /* parameters are the direct and recursive coefficients in */
+		       abe_int32 type1 [NBEQ1];     /* Q6.26 integer fixed-point format. */
+		       struct {
+		       abe_int32 freq [NBEQ2];      /* parameters are the frequency (type "freq") and Q factors */
+		       abe_int32 gain [NBEQ2];      /* (type "gain") of each band. */
+		       } type2;
+		} coef;
+		abe_int32 equ_param3;
+	} abe_equ_t;
+
+	Fs = 48000;
+	f0 = 19000;
+	Q = sqrt(0.5)
+	dBgain = -40
+
+
+	A = sqrt (power (10, dBgain/20));
+	w0 = 2*pi*f0/Fs
+	alpha = sin(w0) / (2*Q);
+
+	%PeakingEQ ==========================================
+	b_peak = print_ABE_data ([1+alpha*A -2*cos(w0) 1-alpha*A],3);
+	a_peak = print_ABE_data ([1+alpha/A -2*cos(w0) 1-alpha/A],3);
+
+#endif
+}
+#endif
+
+/*
+ *  ABE_FPRINTF
+ *
+ *  Parameter  :
+ *      character line to be printed
+ *
+ *  Operations :
+ *
+ *  Return value :
+ *      None.
+ */
+#if 0
+void abe_fprintf(char *line)
+{
+	switch (abe_dbg_output) {
+	case NO_OUTPUT:
+		break;
+	case TERMINAL_OUTPUT:
+		break;
+	case LINE_OUTPUT:
+		break;
+	case DEBUG_TRACE_OUTPUT:
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
+/*
+ *  ABE_READ_FEATURE_FROM_PORT
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_read_feature_from_port(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+
+/*
+ *  ABE_WRITE_FEATURE_TO_PORT
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_write_feature_to_port(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+
+/*
+ *  ABE_READ_FIFO
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_read_fifo(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+
+/*
+ *  ABE_WRITE_FIFO
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_write_fifo(abe_uint32 x)
+{
+	just_to_avoid_the_many_warnings = x;
+}
+
+/*
+ *  ABE_BLOCK_COPY
+ *
+ *  Parameter  :
+ *      direction of the data move (Read/Write)
+ *      memory bank among PMEM, DMEM, CMEM, SMEM, ATC/IO
+ *      address of the memory copy (byte addressing)
+ *      long pointer to the data
+ *      number of data to move
+ *
+ *  Operations :
+ *      block data move
+ *
+ *  Return value :
+ *      none
+ */
+void abe_block_copy(abe_int32 direction, abe_int32 memory_bank, abe_int32 address, abe_uint32 *data, abe_uint32 nb_bytes)
+{
+#if PC_SIMULATION
+	abe_uint32 *smem_tmp, smem_offset, smem_base, nb_words48;
+
+	if (direction == COPY_FROM_HOST_TO_ABE) {
+		switch (memory_bank) {
+		case ABE_PMEM:
+			target_server_write_pmem(address/4, data, nb_bytes/4);
+			break;
+		case ABE_CMEM:
+			target_server_write_cmem(address/4, data, nb_bytes/4);
+			break;
+		case ABE_ATC:
+			target_server_write_atc(address/4, data, nb_bytes/4);
+			break;
+		case ABE_SMEM:
+			nb_words48 = (nb_bytes +7)>>3;
+			/* temporary buffer manages the OCP access to 32bits boundaries */
+			smem_tmp = malloc(nb_bytes + 64);
+			/* address is on SMEM 48bits lines boundary */
+			smem_base = address - (address & 7);
+			target_server_read_smem(smem_base/8, smem_tmp, 2 + nb_words48);
+			smem_offset = address & 7;
+			memcpy(&(smem_tmp[smem_offset>>2]), data, nb_bytes);
+			target_server_write_smem(smem_base/8, smem_tmp, 2 + nb_words48);
+			free(smem_tmp);
+			break;
+		case ABE_DMEM:
+			target_server_write_dmem(address, data, nb_bytes);
+			break;
+		default:
+			abe_dbg_param |= ERR_LIB;
+			abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
+			break;
+		}
+	} else {
+		switch (memory_bank) {
+		case ABE_PMEM:
+			target_server_read_pmem(address/4, data, nb_bytes/4);
+			break;
+		case ABE_CMEM:
+			target_server_read_cmem(address/4, data, nb_bytes/4);
+			break;
+		case ABE_ATC:
+			target_server_read_atc(address/4, data, nb_bytes/4);
+			break;
+		case ABE_SMEM:
+			nb_words48 = (nb_bytes +7)>>3;
+			/* temporary buffer manages the OCP access to 32bits boundaries */
+			smem_tmp = malloc(nb_bytes + 64);
+			/* address is on SMEM 48bits lines boundary */
+			smem_base = address - (address & 7);
+			target_server_read_smem(smem_base/8, smem_tmp, 2 + nb_words48);
+			smem_offset = address & 7;
+			memcpy(data, &(smem_tmp[smem_offset>>2]), nb_bytes);
+			free(smem_tmp);
+			break;
+		case ABE_DMEM:
+			target_server_read_dmem(address, data, nb_bytes);
+			break;
+		default:
+			abe_dbg_param |= ERR_LIB;
+			abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
+			break;
+		}
+	}
+#else
+	abe_uint32 i;
+	abe_uint32 base_address = 0, *src_ptr, *dst_ptr, n;
+
+	switch (memory_bank) {
+	case ABE_PMEM:
+		base_address = (abe_uint32) io_base + ABE_PMEM_BASE_OFFSET_MPU;
+		break;
+	case ABE_CMEM:
+		base_address = (abe_uint32) io_base + ABE_CMEM_BASE_OFFSET_MPU;
+		break;
+	case ABE_SMEM:
+		base_address = (abe_uint32) io_base + ABE_SMEM_BASE_OFFSET_MPU;
+		break;
+	case ABE_DMEM:
+		base_address = (abe_uint32) io_base + ABE_DMEM_BASE_OFFSET_MPU;
+		break;
+	case ABE_ATC:
+		base_address = (abe_uint32) io_base + ABE_ATC_BASE_OFFSET_MPU;
+		break;
+	default:
+		base_address = (abe_uint32) io_base + ABE_SMEM_BASE_OFFSET_MPU;
+		abe_dbg_param |= ERR_LIB;
+		abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
+		break;
+	}
+
+	if (direction == COPY_FROM_HOST_TO_ABE) {
+		dst_ptr = (abe_uint32 *)(base_address + address);
+		src_ptr = (abe_uint32 *)data;
+	} else {
+		dst_ptr = (abe_uint32 *)data;
+		src_ptr = (abe_uint32 *)(base_address + address);
+	}
+
+	n = (nb_bytes/4);
+
+	for (i = 0; i < n; i++)
+		*dst_ptr++ = *src_ptr++;
+
+#endif
+}
+/*
+ *	ABE_RESET_MEM
+ *
+ *	Parameter  :
+ *	memory bank among DMEM, SMEM
+ *	address of the memory copy (byte addressing)
+ *	number of data to move
+ *
+ *	Operations :
+ *	reset memory
+ *
+ *	Return value :
+ *	none
+ */
+
+void  abe_reset_mem(abe_int32 memory_bank, abe_int32 address, abe_uint32 nb_bytes)
+{
+#if PC_SIMULATION
+	extern void target_server_write_smem(abe_uint32 address_48bits, abe_uint32 *data, abe_uint32 nb_words_48bits);
+	extern void target_server_write_dmem(abe_uint32 address_byte, abe_uint32 *data, abe_uint32 nb_byte);
+
+	abe_uint32 *smem_tmp, *data, smem_offset, smem_base, nb_words48;
+
+	data = calloc(nb_bytes, 1);
+
+	switch (memory_bank) {
+	case ABE_SMEM:
+		nb_words48 = (nb_bytes +7)>>3;
+		/* temporary buffer manages the OCP access to 32bits boundaries */
+		smem_tmp = malloc (nb_bytes + 64);
+		/* address is on SMEM 48bits lines boundary */
+		smem_base = address - (address & 7);
+		target_server_read_smem (smem_base/8, smem_tmp, 2 + nb_words48);
+		smem_offset = address & 7;
+		memcpy (&(smem_tmp[smem_offset>>2]), data, nb_bytes);
+		target_server_write_smem (smem_base/8, smem_tmp, 2 + nb_words48);
+		free (smem_tmp);
+		break;
+	case ABE_DMEM:
+		target_server_write_dmem(address, data, nb_bytes);
+		break;
+	default:
+		abe_dbg_param |= ERR_LIB;
+		abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
+	}
+	free(data);
+#else
+	abe_uint32 i;
+	abe_uint32 *dst_ptr, n;
+	abe_uint32 base_address = 0;
+
+	switch (memory_bank) {
+	case ABE_SMEM:
+		base_address = (abe_uint32) io_base + ABE_SMEM_BASE_OFFSET_MPU;
+		break;
+	case ABE_DMEM:
+		base_address = (abe_uint32) io_base + ABE_DMEM_BASE_OFFSET_MPU;
+		break;
+	case ABE_CMEM:
+		base_address = (abe_uint32) io_base + ABE_CMEM_BASE_OFFSET_MPU;
+		break;
+	}
+
+	dst_ptr = (abe_uint32 *) (base_address + address);
+
+	n = (nb_bytes/4);
+
+	for (i = 0; i < n; i++)
+		*dst_ptr++ = 0;
+#endif
+}
+
+/*
+ *  ABE_MONITORING
+ *
+ *  Parameter  :
+ *
+ *  Operations :
+ *      checks the internal status of ABE and HAL
+ *
+ *  Return value :
+ *      Call Backs on Errors
+ */
+void abe_monitoring(void)
+{
+	abe_dbg_param = 0;
+}
+
+/*
+ *  ABE_FORMAT_SWITCH
+ *
+ *  Parameter  :
+ *
+ *  Operations :
+ *      translates the sampling and data length to ITER number for the DMA
+ *      and the multiplier factor to apply during data move with DMEM
+ *
+ *  Return value :
+ *      Call Backs on Errors
+ */
+void abe_format_switch(abe_data_format_t *f, abe_uint32 *iter, abe_uint32 *mulfac)
+{
+	abe_uint32 n_freq;
+
+#if FW_SCHED_LOOP_FREQ==4000
+	switch (f->f) {
+	/* nb of samples processed by scheduling loop */
+	case  8000: n_freq = 2;  break;
+	case 16000: n_freq = 4;  break;
+	case 24000: n_freq = 6;  break;
+	case 44100: n_freq = 12; break;
+	case 96000: n_freq = 24; break;
+	default /*case 48000*/: n_freq = 12; break;
+	}
+#else
+	n_freq = 0;	/* erroneous cases */
+#endif
+	switch (f->samp_format) {
+	case MONO_MSB:
+		*mulfac = 1;
+		break;
+	case STEREO_16_16:
+		*mulfac = 1;
+		break;
+	case STEREO_MSB:
+		*mulfac = 2;
+		break;
+	case THREE_MSB:
+		*mulfac = 3;
+		break;
+	case FOUR_MSB:
+		*mulfac = 4;
+		break;
+	case FIVE_MSB:
+		*mulfac = 5;
+		break;
+	case SIX_MSB:
+		*mulfac = 6;
+		break;
+	case SEVEN_MSB:
+		*mulfac = 7;
+		break;
+	case EIGHT_MSB:
+		*mulfac = 8;
+		break;
+	case NINE_MSB:
+		*mulfac = 9;
+		break;
+	default:
+		*mulfac = 1;
+		break;
+	}
+
+	*iter = (n_freq * (*mulfac));
+}
+
+/*
+ *  ABE_DMA_PORT_ITERATION
+ *
+ *  Parameter  :
+ *
+ *  Operations :
+ *      translates the sampling and data length to ITER number for the DMA
+ *
+ *  Return value :
+ *      Call Backs on Errors
+ */
+abe_uint32 abe_dma_port_iteration(abe_data_format_t *f)
+{
+	abe_uint32 iter, mulfac;
+
+	abe_format_switch(f, &iter, &mulfac);
+
+	return iter;
+}
+
+/*
+ *  ABE_DMA_PORT_ITER_FACTOR
+ *
+ *  Parameter  :
+ *
+ *  Operations :
+ *      returns the multiplier factor to apply during data move with DMEM
+ *
+ *  Return value :
+ *      Call Backs on Errors
+ */
+abe_uint32 abe_dma_port_iter_factor(abe_data_format_t *f)
+{
+	abe_uint32 iter, mulfac;
+
+	abe_format_switch(f, &iter, &mulfac);
+
+	return mulfac;
+}
+
+/*
+ *  ABE_DMA_PORT_COPY_SUBROUTINE_ID
+ *
+ *  Parameter  :
+ *
+ *  Operations :
+ *      returns the index of the function doing the copy in I/O tasks
+ *
+ *  Return value :
+ *      Call Backs on Errors
+ */
+abe_uint32 abe_dma_port_copy_subroutine_id(abe_port_id port_id)
+{
+	abe_uint32 sub_id;
+	if (abe_port[port_id].protocol.direction == ABE_ATC_DIRECTION_IN) {
+		switch (abe_port[port_id].format.samp_format) {
+		case MONO_MSB:
+			sub_id = COPY_D2S_MONO_CFPID;
+			break;	/* VX_DL */
+		case STEREO_16_16:
+			sub_id = COPY_D2S_LR_CFPID;
+			break;	/* MM_DL */
+		case STEREO_MSB:
+			sub_id = COPY_D2S_2_CFPID; break;	/* AMIC, MM_DL, VIB */
+		case SIX_MSB:
+			if (port_id == DMIC_PORT) {
+				sub_id = COPY_DMIC_CFPID;
+				break;
+			}
+		case THREE_MSB:
+		case FOUR_MSB:
+		case FIVE_MSB:
+		case SEVEN_MSB:
+		case EIGHT_MSB:
+		case NINE_MSB:
+		default:
+			sub_id = NULL_COPY_CFPID;
+			break;
+		}
+	} else {
+		switch (abe_port[port_id].format.samp_format) {
+		case MONO_MSB:
+			sub_id = COPY_S2D_MONO_CFPID;
+			break; /* VX_UL */
+		case MONO_RSHIFTED_16:
+			sub_id = COPY_S2D_MONOS16_CFPID;
+			break;	/* McBSP_TX Mono */
+		case STEREO_RSHIFTED_16:
+			sub_id = COPY_S2D_2S16_CFPID;
+			break;	/* McBSP_TX Stereo */
+		case STEREO_MSB:
+			sub_id = COPY_S2D_2_CFPID;
+			break;	/* MM_UL2 */
+		case SIX_MSB:
+			if (port_id == PDM_DL_PORT) {
+				sub_id = COPY_MCPDM_DL_CFPID;
+				break;
+			}
+			if (port_id == MM_UL_PORT) {
+				sub_id = COPY_MM_UL_CFPID;
+				break;
+			}
+		case THREE_MSB:
+		case FOUR_MSB:
+		case FIVE_MSB:
+		case SEVEN_MSB:
+		case EIGHT_MSB:
+		case NINE_MSB:
+			sub_id = COPY_MM_UL_CFPID;
+			break;
+		case STEREO_16_16:
+		default:
+			sub_id = NULL_COPY_CFPID;
+			break;
+		}
+	}
+	return sub_id;
+}
diff --git a/sound/soc/codecs/abe/abe_lib.h b/sound/soc/codecs/abe/abe_lib.h
new file mode 100644
index 000000000000..9dd64ce62d11
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_lib.h
@@ -0,0 +1,124 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void abe_init_mem(void);
+void abe_translate_gain_format(abe_uint32 f, abe_float g1, abe_float *g2);
+void abe_translate_ramp_format(abe_float g1, abe_float *g2);
+
+/*
+ *  ABE_FPRINTF
+ *
+ *  Parameter  :
+ *      character line to be printed
+ *
+ *  Operations :
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_fprintf(char *line);
+
+/*
+ *  ABE_READ_FEATURE_FROM_PORT
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_read_feature_from_port(abe_uint32 x);
+
+/*
+ *  ABE_WRITE_FEATURE_TO_PORT
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_write_feature_to_port(abe_uint32 x);
+
+/*
+ *  ABE_READ_FIFO
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_read_fifo(abe_uint32 x);
+
+/*
+ *  ABE_WRITE_FIFO
+ *
+ *  Parameter  :
+ *      x : d
+ *
+ *  Operations :
+ *
+ *
+ *  Return value :
+ *
+ */
+void abe_write_fifo(abe_uint32 x);
+
+/*
+ *  ABE_BLOCK_COPY
+ *
+ *  Parameter  :
+ *      direction of the data move (Read/Write)
+ *      memory bank among PMEM, DMEM, CMEM, SMEM, ATC/IO
+ *      address of the memory copy (byte addressing)
+ *      long pointer to the data
+ *      number of data to move
+ *
+ *  Operations :
+ *      block data move
+ *
+ *  Return value :
+ *      none
+ */
+void abe_block_copy(abe_int32 direction, abe_int32 memory_bank, abe_int32 address, abe_uint32 *data, abe_uint32 nb);
+
+/*
+ * ABE_RESET_MEM
+ *
+ *Parameter:
+ * memory bank among DMEM, SMEM
+ * address of the memory copy (byte addressing)
+ * number of data to move
+ *
+ * Operations:
+ * reset memory
+ *
+ * Return value:
+ * none
+ */
+void abe_reset_mem(abe_int32 memory_bank, abe_int32 address, abe_uint32 nb_bytes);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/sound/soc/codecs/abe/abe_main.c b/sound/soc/codecs/abe/abe_main.c
new file mode 100644
index 000000000000..3423fe62e50a
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_main.c
@@ -0,0 +1,99 @@
+/* =============================================================================
+*	     Texas Instruments OMAP(TM) Platform Software
+*  (c) Copyright 2009 Texas Instruments Incorporated.  All Rights Reserved.
+*
+*  Use of this software is controlled by the terms and conditions found
+*  in the license agreement under which this software has been supplied.
+* =========================================================================== */
+/**
+ * @file  ABE_MAIN.C
+ *
+ * 'ABEMAIN.C' dummy main of the HAL
+ *
+ * @path
+ * @rev     01.00
+ */
+/* ----------------------------------------------------------------------------
+*!
+*! Revision History
+*! ===================================
+*! 27-Nov-2008 Original (LLF)
+*! 05-Jun-2009 V05 release
+* =========================================================================== */
+
+
+#if !PC_SIMULATION
+
+
+#include "abe_main.h"
+#include "abe_test.h"
+
+void main (void)
+{
+
+	abe_dma_t dma_sink, dma_source;
+	abe_data_format_t format;
+	abe_uint32 base_address;
+
+	abe_auto_check_data_format_translation();
+	abe_reset_hal();
+	abe_check_opp();
+	abe_check_dma();
+
+	/*
+		To be added here :
+		Device driver initialization:
+		McPDM_DL : threshold=1, 6 slots activated
+		DMIC : threshold=1, 6 microphones activated
+		McPDM_UL : threshold=1, two microphones activated
+	*/
+
+
+	/*  MM_DL INIT
+		connect a DMA channel to MM_DL port (ATC FIFO)
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink);
+
+		connect a Ping-Pong SDMA protocol to MM_DL port with Ping-Pong 576 stereo samples
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_dmareq_ping_pong_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, (576 * 4), &dma_sink);
+
+		connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate
+	*/
+	abe_add_subroutine(&abe_irq_pingpong_player_id,
+		(abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0 );
+	format.f = 48000;
+	format.samp_format = STEREO_MSB;
+/* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */
+#define N_SAMPLES ((int)(48000 * 0.020))
+	abe_connect_irq_ping_pong_port(MM_DL_PORT, &format, abe_irq_pingpong_player_id,
+				N_SAMPLES, &base_address, PING_PONG_WITH_MCU_IRQ);
+
+	/*  VX_DL INIT
+		connect a DMA channel to VX_DL port (ATC FIFO)
+	*/
+	format.f = 8000;
+	format.samp_format = MONO_MSB;
+	abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+
+	/*  VX_UL INIT
+	    connect a DMA channel to VX_UL port (ATC FIFO)
+	*/
+	format.f = 8000;
+	format.samp_format = MONO_MSB;
+	abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_source);
+
+	/* make the AE waking event to be the McPDM DMA requests */
+	abe_write_event_generator(EVENT_MCPDM);
+
+	abe_enable_data_transfer(MM_DL_PORT );
+	abe_enable_data_transfer(VX_DL_PORT );
+	abe_enable_data_transfer(VX_UL_PORT );
+	abe_enable_data_transfer(PDM_UL_PORT);
+	abe_enable_data_transfer(PDM_DL1_PORT);
+
+}
+
+#endif
diff --git a/sound/soc/codecs/abe/abe_main.h b/sound/soc/codecs/abe/abe_main.h
new file mode 100644
index 000000000000..8ccfd48daf45
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_main.h
@@ -0,0 +1,55 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_MAIN_H_
+#define _ABE_MAIN_H_
+
+#include "abe_dm_addr.h"
+#include "abe_cm_addr.h"
+#include "abe_def.h"
+#include "abe_typ.h"
+#include "abe_dbg.h"
+#include "abe_ext.h"
+#include "abe_lib.h"
+#include "abe_ref.h"
+#include "abe_api.h"
+//#include "ABE_DAT.h"
+
+#include "abe_typedef.h"
+#include "abe_functionsId.h"
+#include "abe_taskId.h"
+#include "abe_dm_addr.h"
+#include "abe_sm_addr.h"
+#include "abe_cm_addr.h"
+#include "abe_initxxx_labels.h"
+
+#include "abe_fw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ABE_HAL_VERSION		0x00000002L
+#define ABE_FW_VERSION		0x00000000L
+#define ABE_HW_VERSION		0x00000000L
+
+#define HAL_TIME_STAMP		0	/* generates the time-stamps used for the AESS verification */
+
+#define ABE_DEBUG_CHECKERS	0	/* pipe connection to the TARGET simulator */
+#define ABE_DEBUG_HWFILE	0	/* simulator data extracted from a text-file */
+#define ABE_DEBUG_LL_LOG	0	/* low-level log files */
+
+#define ABE_DEBUG (ABE_DEBUG_CHECKERS | ABE_DEBUG_HWFILE | ABE_DEBUG_LL_LOG)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _ABE_MAIN_H_ */
diff --git a/sound/soc/codecs/abe/abe_ref.h b/sound/soc/codecs/abe/abe_ref.h
new file mode 100644
index 000000000000..2af9b213e559
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_ref.h
@@ -0,0 +1,140 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_REF_H_
+#define _ABE_REF_H_
+
+/*
+ *  'ABE_PRO.H' all non-API prototypes for INI, IRQ, SEQ ...
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * HAL EXTERNAL API
+ */
+
+/*
+ * HAL INTERNAL API
+ */
+void abe_load_embedded_patterns(void);
+void abe_build_scheduler_table(void);
+void abe_reset_all_features(void);
+void abe_reset_one_port(abe_uint32 x);
+void abe_reset_all_ports(void);
+void abe_reset_all_fifo(void);
+void abe_reset_all_sequence(void);
+abe_uint32 abe_dma_port_iteration(abe_data_format_t *format);
+void abe_read_sys_clock(abe_micros_t *time);
+void abe_enable_dma_request(abe_port_id id);
+void abe_disable_dma_request(abe_port_id id);
+void abe_enable_atc(abe_port_id id);
+void abe_disable_atc(abe_port_id id);
+void abe_init_atc(abe_port_id id);
+void abe_init_io_tasks(abe_port_id id, abe_data_format_t *format, abe_port_protocol_t *prot);
+void abe_init_dma_t(abe_port_id id, abe_port_protocol_t *prot);
+abe_uint32 abe_dma_port_iter_factor(abe_data_format_t *f);
+abe_uint32 abe_dma_port_copy_subroutine_id(abe_port_id i);
+void abe_call_subroutine(abe_uint32 idx, abe_uint32 p1, abe_uint32 p2, abe_uint32 p3, abe_uint32 p4);
+void abe_monitoring(void);
+void abe_lock_execution(void);
+void abe_unlock_execution(void);
+void abe_hw_configuration(void);
+void abe_add_subroutine(abe_uint32 *id, abe_subroutine2 f, abe_uint32 nparam, abe_uint32* params);
+void abe_read_next_ping_pong_buffer(abe_port_id port, abe_uint32 *p, abe_uint32 *n);
+void abe_irq_ping_pong(void);
+void abe_irq_check_for_sequences(abe_uint32 seq_info);
+void abe_default_irq_pingpong_player(void);
+void abe_default_irq_pingping_player_32bits(void);
+void abe_default_irq_aps_adaptation(void);
+void abe_read_hardware_configuration(abe_use_case_id *u, abe_opp_t *o, abe_hw_config_init_t *hw);
+void abe_irq_aps(abe_uint32 aps_info);
+void abe_clean_temporary_buffers(abe_port_id id);
+
+void abe_translate_to_xmem_format(abe_int32 memory_bank, float fc, abe_uint32 *c);
+
+/*
+ * HAL INTERNAL DATA
+ */
+
+extern abe_port_t abe_port[];
+extern abe_feature_t feature[];
+extern abe_subroutine2 callbacks[];
+
+extern abe_port_t abe_port[];
+extern const abe_port_t abe_port_init[];
+
+extern abe_feature_t all_feature[];
+extern const abe_feature_t all_feature_init[];
+
+extern abe_seq_t all_sequence[];
+extern const abe_seq_t all_sequence_init[];
+
+extern const abe_router_t abe_router_ul_table_preset[NBROUTE_CONFIG][NBROUTE_UL];
+extern abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL];
+
+extern abe_uint32 abe_dbg_output;
+extern abe_uint32 abe_dbg_mask;
+extern abe_uint32 abe_dbg_activity_log[DBG_LOG_SIZE];
+extern abe_uint32 abe_dbg_activity_log_write_pointer;
+extern abe_uint32 abe_dbg_param;
+
+extern abe_uint32 abe_global_mcpdm_control;
+extern abe_event_id abe_current_event_id;
+
+extern const abe_sequence_t seq_null;
+extern abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE];	/* table of new subroutines called in the sequence */
+extern abe_uint32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE]; /* number of parameters per calls */
+extern abe_uint32 abe_subroutine_id[MAXNBSUBROUTINE];
+extern abe_uint32* abe_all_subroutine_params[MAXNBSUBROUTINE];
+extern abe_uint32 abe_subroutine_write_pointer;
+extern abe_sequence_t abe_all_sequence[MAXNBSEQUENCE]; /* table of all sequences */
+extern abe_uint32 abe_sequence_write_pointer;
+extern abe_uint32 abe_nb_pending_sequences;	/* current number of pending sequences (avoids to look in the table) */
+extern abe_uint32 abe_pending_sequences[MAXNBSEQUENCE]; /* pending sequences due to ressource collision */
+extern abe_uint32 abe_global_sequence_mask;	/* mask of unsharable ressources among other sequences */
+extern abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS]; /* table of active sequences */
+extern abe_uint32 abe_irq_pingpong_player_id;	/* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */
+extern abe_uint32 abe_irq_aps_adaptation_id;
+extern abe_uint32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS]; /* base addresses of the ping pong buffers */
+extern abe_uint32 abe_size_pingpong;		/* size of each ping/pong buffers */
+extern abe_uint32 abe_nb_pingpong;		/* number of ping/pong buffer being used */
+
+extern abe_uint32 abe_irq_dbg_read_ptr;
+
+extern volatile abe_uint32		just_to_avoid_the_many_warnings;
+extern volatile abe_gain_t		just_to_avoid_the_many_warnings_abe_gain_t;
+extern volatile abe_ramp_t		just_to_avoid_the_many_warnings_abe_ramp_t;
+extern volatile abe_dma_t		just_to_avoid_the_many_warnings_abe_dma_t;
+extern volatile abe_port_id		just_to_avoid_the_many_warnings_abe_port_id;
+extern volatile abe_millis_t		just_to_avoid_the_many_warnings_abe_millis_t;
+extern volatile abe_micros_t		just_to_avoid_the_many_warnings_abe_micros_t;
+extern volatile abe_patch_rev		just_to_avoid_the_many_warnings_abe_patch_rev;
+extern volatile abe_sequence_t		just_to_avoid_the_many_warnings_abe_sequence_t;
+extern volatile abe_ana_port_id		just_to_avoid_the_many_warnings_abe_ana_port_id;
+extern volatile abe_time_stamp_t	just_to_avoid_the_many_warnings_abe_time_stamp_t;
+extern volatile abe_data_format_t	just_to_avoid_the_many_warnings_abe_data_format_t;
+extern volatile abe_port_protocol_t	just_to_avoid_the_many_warnings_abe_port_protocol_t;
+extern volatile abe_router_t		just_to_avoid_the_many_warnings_abe_router_t;
+extern volatile abe_router_id		just_to_avoid_the_many_warnings_abe_router_id;
+
+extern const abe_int32 abe_dmic_40[C_98_48_LP_Coefs_sizeof];
+extern const abe_int32 abe_dmic_32[C_98_48_LP_Coefs_sizeof];
+extern const abe_int32 abe_dmic_25[C_98_48_LP_Coefs_sizeof];
+extern const abe_int32 abe_dmic_16[C_98_48_LP_Coefs_sizeof];
+
+extern const abe_uint32 abe_db2lin_table [];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _ABE_REF_H_ */
diff --git a/sound/soc/codecs/abe/abe_seq.c b/sound/soc/codecs/abe/abe_seq.c
new file mode 100644
index 000000000000..e042fb317eec
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_seq.c
@@ -0,0 +1,284 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_main.h"
+
+/*
+ *      SEQUENCES
+ *      struct {
+ *      micros_t time;	  Waiting time before executing next line
+ *      seq_code_t code	 Subroutine index interpreted in the HAL and translated to
+ *				FW subroutine codes in case of ABE tasks
+ *      int32 param[2]	  Two parameters
+ *      char param_tag[2]       Flags used for parameters when launching the sequences
+ *      } seq_t
+ *
+ */
+
+/*
+ *  ABE_NULL_SUBROUTINE
+ *
+ *  Operations : nothing
+ */
+void abe_null_subroutine_0(void) { }
+void abe_null_subroutine_2 (abe_uint32 a, abe_uint32 b) {
+	just_to_avoid_the_many_warnings = a;
+	just_to_avoid_the_many_warnings = b;
+}
+void abe_null_subroutine_4 (abe_uint32 a, abe_uint32 b, abe_uint32 c, abe_uint32 d) {
+	just_to_avoid_the_many_warnings = a;
+	just_to_avoid_the_many_warnings = b;
+	just_to_avoid_the_many_warnings = c;
+	just_to_avoid_the_many_warnings = d;
+}
+/*
+ *  abe_init_subroutine_table
+ *
+ *  parameter  :
+ *      none
+ *
+ *  operations :
+ *      initializes the default table of pointers to subroutines
+ *
+ *  return value :
+ *
+ */
+void abe_init_subroutine_table(void)
+{
+	abe_uint32 id;
+
+	/* reset the table's pointers */
+	abe_subroutine_write_pointer = 0;
+	/* the first index is the NULL task */
+	abe_add_subroutine(&id,(abe_subroutine2) abe_null_subroutine_2, SUB_0_PARAM, (abe_uint32*)0);
+	/* write mixer has 3 parameters  @@@ TBD*/
+	abe_add_subroutine(&(abe_subroutine_id[SUB_WRITE_MIXER]), (abe_subroutine2) abe_write_mixer, SUB_4_PARAM, (abe_uint32*)0);
+	/* ping-pong player IRQ */
+	abe_add_subroutine(&abe_irq_pingpong_player_id,(abe_subroutine2) abe_null_subroutine_0, SUB_0_PARAM, (abe_uint32*)0);
+	abe_add_subroutine(&abe_irq_aps_adaptation_id,(abe_subroutine2) abe_default_irq_aps_adaptation, SUB_0_PARAM, (abe_uint32*)0);
+}
+
+/*
+ *  ABE_ADD_SUBROUTINE
+ *
+ *  Parameter  :
+ *      port id
+ *      pointer to the subroutines
+ *      number of parameters to push on the stack before call
+ *
+ *  Operations :
+ *      add one function pointer more and returns the index to it
+ *
+ *  Return value :
+ *
+ */
+void abe_add_subroutine (abe_uint32 *id, abe_subroutine2 f, abe_uint32 nparam, abe_uint32* params)
+{
+	abe_uint32 i, i_found;
+
+	if ((abe_subroutine_write_pointer >= MAXNBSUBROUTINE) || ((abe_uint32)f == 0)) {
+		abe_dbg_param |= ERR_SEQ;
+		abe_dbg_error_log(ABE_PARAMETER_OVERFLOW);
+	} else {
+		/* search if this subroutine address was not already
+		 * declared, then return the previous index
+		 */
+		for (i_found = abe_subroutine_write_pointer, i = 0; i < abe_subroutine_write_pointer; i++) {
+			if (f == abe_all_subsubroutine[i])
+				i_found = i;
+		}
+
+		if (i_found == abe_subroutine_write_pointer) {
+			*id = abe_subroutine_write_pointer;
+			abe_all_subsubroutine[abe_subroutine_write_pointer] = (f);
+			abe_all_subroutine_params[abe_subroutine_write_pointer] = params;
+			abe_all_subsubroutine_nparam[abe_subroutine_write_pointer] = nparam;
+			abe_subroutine_write_pointer++;
+		} else {
+			abe_all_subroutine_params[i_found] = params;
+			*id = i_found;
+		}
+	}
+}
+
+/*
+ *  ABE_ADD_SEQUENCE
+ *
+ *  Parameter  :
+ *       Id: returned sequence index after pluging a new sequence (index in the tables)
+ *       s : sequence to be inserted
+ *
+ *  Operations :
+ *      Load a time-sequenced operations.
+ *
+ *  Return value :
+ *      None.
+ */
+
+void abe_add_sequence(abe_uint32 *id, abe_sequence_t *s)
+{
+	abe_seq_t *seq_src, *seq_dst;
+	abe_uint32 i, no_end_of_sequence_found;
+
+	seq_src = &(s->seq1);
+	seq_dst = &((abe_all_sequence[abe_sequence_write_pointer]).seq1);
+
+	if ((abe_sequence_write_pointer >= MAXNBSEQUENCE) || ((abe_uint32)s == 0)) {
+		abe_dbg_param |= ERR_SEQ;
+		abe_dbg_error_log(ABE_PARAMETER_OVERFLOW);
+	} else {
+		*id = abe_subroutine_write_pointer;
+		(abe_all_sequence[abe_sequence_write_pointer]).mask = s->mask;	/* copy the mask */
+
+		for (no_end_of_sequence_found = 1, i = 0; i < MAXSEQUENCESTEPS; i++, seq_src++, seq_dst++) {
+			(*seq_dst) = (*seq_src);	/* sequence copied line by line */
+
+			if ((*(abe_int32 *)seq_src) == -1) {
+				/* stop when the line start with time=(-1) */
+				no_end_of_sequence_found = 0;
+				break;
+			}
+		}
+		abe_subroutine_write_pointer++;
+
+		if (no_end_of_sequence_found)
+			abe_dbg_error_log(ABE_SEQTOOLONG);
+	}
+}
+
+/*
+ *  ABE_RESET_ONE_SEQUENCE
+ *
+ *  Parameter  :
+ *      sequence ID
+ *
+ *  Operations :
+ *      load default configuration for that sequence
+ *      kill running activities
+ *
+ *  Return value :
+ *
+ */
+void abe_reset_one_sequence(abe_uint32 id)
+{
+	just_to_avoid_the_many_warnings = id;
+}
+
+/*
+ *  ABE_RESET_ALL_SEQUENCE
+ *
+ *  Parameter  :
+ *      none
+ *
+ *  Operations :
+ *      load default configuration for all sequences
+ *      kill any running activities
+ *
+ *  Return value :
+ *
+ */
+void abe_reset_all_sequence(void)
+{
+	abe_uint32 i;
+
+	abe_init_subroutine_table();
+
+	/* arrange to have the first sequence index=0 to the NULL operation sequence */
+	abe_add_sequence(&i, (abe_sequence_t *)&seq_null);
+
+	/* reset the the collision protection mask */
+	abe_global_sequence_mask = 0;
+
+	/* reset the pending sequences list */
+	for (abe_nb_pending_sequences = i = 0; i < MAXNBSEQUENCE; i++)
+		abe_pending_sequences[i] = 0;
+}
+
+/*
+ *  ABE_CALL_SUBROUTINE
+ *
+ *  Parameter  :
+ *      index to the table of all registered Call-backs and subroutines
+ *
+ *  Operations :
+ *      run and log a subroutine
+ *
+ *  Return value :
+ *      None.
+ */
+void abe_call_subroutine(abe_uint32 idx, abe_uint32 p1, abe_uint32 p2, abe_uint32 p3, abe_uint32 p4)
+{
+	abe_subroutine0 f0;
+	abe_subroutine1 f1;
+	abe_subroutine2 f2;
+	abe_subroutine3 f3;
+	abe_subroutine4 f4;
+	abe_uint32* params;
+
+	if (idx >= MAXNBSUBROUTINE)
+		return;
+
+	switch (idx) {
+#if 0
+	/* call the subroutines defined at compilation time (const .. sequences) */
+	case SUB_WRITE_MIXER_DL1 :
+		/@@@@ abe_write_mixer_dl1 (p1, p2, p3)
+		abe_fprintf ("write_mixer");
+		break;
+#endif
+	/* call the subroutines defined at execution time (dynamic sequences) */
+	default :
+		switch(abe_all_subsubroutine_nparam[idx]) {
+		case SUB_0_PARAM:
+			f0 = (abe_subroutine0)abe_all_subsubroutine[idx];
+			(*f0)();
+			break;
+		case SUB_1_PARAM:
+			f1 = (abe_subroutine1) abe_all_subsubroutine[idx];
+			params = abe_all_subroutine_params[abe_irq_pingpong_player_id];
+			if (params != (abe_uint32*)0)
+				p1 = params[0];
+			(*f1) (p1);
+			break;
+		case SUB_2_PARAM:
+			f2 = abe_all_subsubroutine[idx];
+			params = abe_all_subroutine_params[abe_irq_pingpong_player_id];
+			if (params != (abe_uint32*)0) {
+				p1 = params[0];
+				p2 = params[1];
+			}
+			(*f2) (p1, p2);
+			break;
+		case SUB_3_PARAM:
+			f3 = (abe_subroutine3) abe_all_subsubroutine[idx];
+			params = abe_all_subroutine_params[abe_irq_pingpong_player_id];
+			if (params != (abe_uint32*)0) {
+				p1 = params[0];
+				p2 = params[1];
+				p3 = params[2];
+			}
+			(*f3) (p1, p2, p3);
+			break;
+		case SUB_4_PARAM:
+			f4 = (abe_subroutine4) abe_all_subsubroutine[idx];
+			params = abe_all_subroutine_params[abe_irq_pingpong_player_id];
+			if (params != (abe_uint32*)0) {
+				p1 = params[0];
+				p2 = params[1];
+				p3 = params[2];
+				p4 = params[3];
+			}
+			(*f4) (p1, p2, p3, p4);
+			break;
+		default:
+			break;
+		}
+	}
+}
diff --git a/sound/soc/codecs/abe/abe_seq.h b/sound/soc/codecs/abe/abe_seq.h
new file mode 100644
index 000000000000..6e15531e920e
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_seq.h
@@ -0,0 +1,127 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+void abe_init_subroutine_table(void);
+
+/*
+ * Register Programming Examples
+ *
+ * 1. Power on sequence
+ *
+ * The modules HSLDO, NCP, LSLDO, LPPLL are enabled/disabled automatically by the TWL6040 power state machine after pin AUDPWRON transitions from 0 ' 1. No register writes are necessary.
+ *
+ * For the purposes of test it is possible to bypass the power state machine and manually enable these modules in the same order as described in Fig 2-XX. This can be done after VIO comes up and I2C register writes are possible.
+ *
+ * The manual sequence could be as follows
+ * LDOCTL = 0x04 (Enable HSLDO)
+ * NCPCTL = 0x03 (Enable NCP in auto mode)
+ * LDOCTL = 0x05 (Enable LSLDO)
+ * LPPLLCTL = 0x09 (Enable LPPLL with output frequency = 19.2MHz)
+ *
+ * Please see Fig 2-64 for details on details to be maintained between successive I2C register writes.
+ *
+ * Further if the system MCLK is active the HPPLL could be enabled instead of the LPPLL.
+ * (a) For a square wave where slicer is not required
+ * HPPLLCTL = 0x11 (Select HPPLL output, Enable HPPLL)
+ * (a) For a sine wave where slicer is required
+ * HPPLLCTL = 0x19 (Select HPPLL output, Enable Slicer, Enable HPPLL)
+ *
+ */
+
+/*
+ * 2. Setting up a stereo UPLINK path through MICAMPL, MICAMPR input amplifiers
+ * AMICBCTL = 0x10
+ * MICGAIN = 0x0F (Gain to 24 dB for L and R)
+ * HPPLLCTL = 0x19 (Select HPPLL output, Enable Slicer, Enable HPPLL)
+ * MICLCTL = 0x0D (Select MMIC input, Enable ADC)
+ * MICRCTL = 0x0D (Select SMIC input, Enable ADC)
+ *
+ */
+
+/*
+ * 3. Setting up a stereo headset MP3 playback DNLINK path
+ * Please see section 2.3.1.1 for details
+ *
+ * (b) HP
+ * HSGAIN = 0x22 (-4 dB gain on L and R amplifiers)
+ * HSLCTL = 0x01 (Enable HSDAC L, HP mode)
+ * HSRCTL = 0x01 (Enable HSDAC R, HP mode)
+ * Wait 80us
+ * HSLCTL = 0x05 (Enable HSLDRV, HP mode)
+ * HSRCTL = 0x05 (Enable HSRDRV, HP mode)
+ * Wait 2ms
+ * HSLCTL = 0x25 (Close HSDACL switch)
+ * HSRCTL = 0x25 (Close HSDACR switch)
+ *
+ */
+
+/*
+ * (a) LP
+ * HSGAIN = 0x22 (-4 dB gain on L and R amplifiers)
+ * HSLCTL = 0x03 (Enable HSDAC L, LP mode)
+ * HSRCTL = 0x03 (Enable HSDAC R, LP mode)
+ * Wait 80us
+ * HSLCTL = 0x0F (Enable HSLDRV, LP mode)
+ * HSRCTL = 0x0F (Enable HSRDRV, LP mode)
+ * Wait 2ms
+ * HSLCTL = 0x2F (Close HSDACL switch)
+ * HSRCTL = 0x2F (Close HSDACR switch)
+ *
+ */
+
+/*
+ * 4. Setting up a stereo FM playback path on headset
+ * (a) HP
+ * LINEGAIN = 0x1B (0dB gain on L and R inputs)
+ * MICLCTL = 0x02 (Enable Left LINEAMP)
+ * MICRCTL = 0x02 (Enable Right LINEAMP)
+ * HSGAIN = 0x22 (-4 dB gain on L and R amplifiers)
+ * HSLCTL = 0x04 (Enable HSLDRV in HP mode)
+ * HSRCTL = 0x04 (Enable HSRDRV in HP mode)
+ * Wait 2ms
+ * HSLCTL = 0x44 (Close FMLOOP switch)
+ * HSRCTL = 0x44 (Close FMLOOP switch)
+ *
+ *
+ */
+
+/*
+ * (b) LP
+ * LINEGAIN = 0x1B (0dB gain on L and R inputs)
+ * MICLCTL = 0x02 (Enable Left LINEAMP)
+ * MICRCTL = 0x02 (Enable Right LINEAMP)
+ * HSGAIN = 0x22 (-4 dB gain on L and R amplifiers)
+ * HSLCTL = 0x0C (Enable HSLDRV in LP mode)
+ * HSRCTL = 0x0C (Enable HSRDRV in LP mode)
+ * Wait 2ms
+ * HSLCTL = 0x4C (Close FMLOOP switch)
+ * HSRCTL = 0x4C (Close FMLOOP switch)
+ *
+ */
+
+
+/*
+ * 5. Setting up a handset call
+ *
+ * UPLINK
+ *
+ * AMICBCTL = 0x10
+ * MICGAIN = 0x0F (Gain to 24 dB for L and R)
+ * HPPLLCTL = 0x19 (Select HPPLL output, Enable Slicer, Enable HPPLL)
+ * MICLCTL = 0x0D (Select MMIC input, Enable ADC)
+ * MICRCTL = 0x0D (Select SMIC input, Enable ADC)
+ *
+ * DNLINK
+ *
+ * HSLCTL = 0x01 (Enable HSDACL, HP mode)
+ * Wait 80us
+ * EARCTL = 0x03 (Enable EAR, Gain = min, by default enabling EAR connects HSDACL output to EAR)
+ *
+ */
diff --git a/sound/soc/codecs/abe/abe_sm_addr.h b/sound/soc/codecs/abe/abe_sm_addr.h
new file mode 100644
index 000000000000..ce5c9eef7ca2
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_sm_addr.h
@@ -0,0 +1,630 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_SM_ADDR_H_
+#define _ABE_SM_ADDR_H_
+
+#define init_SM_ADDR						0
+#define init_SM_ADDR_END					284
+#define init_SM_sizeof						285
+
+#define S_Data0_ADDR						285
+#define S_Data0_ADDR_END					285
+#define S_Data0_sizeof						1
+
+#define S_Temp_ADDR						286
+#define S_Temp_ADDR_END						286
+#define S_Temp_sizeof						1
+
+#define S_PhoenixOffset_ADDR					287
+#define S_PhoenixOffset_ADDR_END				287
+#define S_PhoenixOffset_sizeof					1
+
+#define S_GTarget1_ADDR						288
+#define S_GTarget1_ADDR_END					294
+#define S_GTarget1_sizeof					7
+
+#define S_Gtarget_DL1_ADDR					295
+#define S_Gtarget_DL1_ADDR_END					296
+#define S_Gtarget_DL1_sizeof					2
+
+#define S_Gtarget_DL2_ADDR					297
+#define S_Gtarget_DL2_ADDR_END					298
+#define S_Gtarget_DL2_sizeof					2
+
+#define S_Gtarget_Echo_ADDR					299
+#define S_Gtarget_Echo_ADDR_END					299
+#define S_Gtarget_Echo_sizeof					1
+
+#define S_Gtarget_SDT_ADDR					300
+#define S_Gtarget_SDT_ADDR_END					300
+#define S_Gtarget_SDT_sizeof					1
+
+#define S_Gtarget_VxRec_ADDR					301
+#define S_Gtarget_VxRec_ADDR_END				302
+#define S_Gtarget_VxRec_sizeof					2
+
+#define S_Gtarget_UL_ADDR					303
+#define S_Gtarget_UL_ADDR_END					304
+#define S_Gtarget_UL_sizeof					2
+
+#define S_Gtarget_unused_ADDR					305
+#define S_Gtarget_unused_ADDR_END				305
+#define S_Gtarget_unused_sizeof					1
+
+#define S_GCurrent_ADDR						306
+#define S_GCurrent_ADDR_END					323
+#define S_GCurrent_sizeof					18
+
+#define S_GAIN_ONE_ADDR						324
+#define S_GAIN_ONE_ADDR_END					324
+#define S_GAIN_ONE_sizeof					1
+
+#define S_Tones_ADDR						325
+#define S_Tones_ADDR_END					336
+#define S_Tones_sizeof						12
+
+#define S_VX_DL_ADDR						337
+#define S_VX_DL_ADDR_END					348
+#define S_VX_DL_sizeof						12
+
+#define S_MM_UL2_ADDR						349
+#define S_MM_UL2_ADDR_END					360
+#define S_MM_UL2_sizeof						12
+
+#define S_MM_DL_ADDR						361
+#define S_MM_DL_ADDR_END					372
+#define S_MM_DL_sizeof						12
+
+#define S_DL1_M_Out_ADDR					373
+#define S_DL1_M_Out_ADDR_END					384
+#define S_DL1_M_Out_sizeof					12
+
+#define S_DL2_M_Out_ADDR					385
+#define S_DL2_M_Out_ADDR_END					396
+#define S_DL2_M_Out_sizeof					12
+
+#define S_Echo_M_Out_ADDR					397
+#define S_Echo_M_Out_ADDR_END					408
+#define S_Echo_M_Out_sizeof					12
+
+#define S_SDT_M_Out_ADDR					409
+#define S_SDT_M_Out_ADDR_END					420
+#define S_SDT_M_Out_sizeof					12
+
+#define S_VX_UL_ADDR						421
+#define S_VX_UL_ADDR_END					432
+#define S_VX_UL_sizeof						12
+
+#define S_VX_UL_M_ADDR						433
+#define S_VX_UL_M_ADDR_END					444
+#define S_VX_UL_M_sizeof					12
+
+#define S_BT_DL_ADDR						445
+#define S_BT_DL_ADDR_END					456
+#define S_BT_DL_sizeof						12
+
+#define S_BT_UL_ADDR						457
+#define S_BT_UL_ADDR_END					468
+#define S_BT_UL_sizeof						12
+
+#define S_BT_DL_8k_ADDR						469
+#define S_BT_DL_8k_ADDR_END					470
+#define S_BT_DL_8k_sizeof					2
+
+#define S_BT_DL_16k_ADDR					471
+#define S_BT_DL_16k_ADDR_END					474
+#define S_BT_DL_16k_sizeof					4
+
+#define S_BT_UL_8k_ADDR						475
+#define S_BT_UL_8k_ADDR_END					476
+#define S_BT_UL_8k_sizeof					2
+
+#define S_BT_UL_16k_ADDR					477
+#define S_BT_UL_16k_ADDR_END					480
+#define S_BT_UL_16k_sizeof					4
+
+#define S_BT_UL_8_48_BP_data_ADDR				481
+#define S_BT_UL_8_48_BP_data_ADDR_END				493
+#define S_BT_UL_8_48_BP_data_sizeof				13
+
+#define S_BT_UL_8_48_LP_data_ADDR				494
+#define S_BT_UL_8_48_LP_data_ADDR_END				506
+#define S_BT_UL_8_48_LP_data_sizeof				13
+
+#define S_BT_UL_16_48_HP_data_ADDR				507
+#define S_BT_UL_16_48_HP_data_ADDR_END				513
+#define S_BT_UL_16_48_HP_data_sizeof				7
+
+#define S_BT_UL_16_48_LP_data_ADDR				514
+#define S_BT_UL_16_48_LP_data_ADDR_END				526
+#define S_BT_UL_16_48_LP_data_sizeof				13
+
+#define S_BT_DL_48_8_BP_data_ADDR				527
+#define S_BT_DL_48_8_BP_data_ADDR_END				539
+#define S_BT_DL_48_8_BP_data_sizeof				13
+
+#define S_BT_DL_48_8_LP_data_ADDR				540
+#define S_BT_DL_48_8_LP_data_ADDR_END				552
+#define S_BT_DL_48_8_LP_data_sizeof				13
+
+#define S_BT_DL_48_16_HP_data_ADDR				553
+#define S_BT_DL_48_16_HP_data_ADDR_END				559
+#define S_BT_DL_48_16_HP_data_sizeof				7
+
+#define S_BT_DL_48_16_LP_data_ADDR				560
+#define S_BT_DL_48_16_LP_data_ADDR_END				572
+#define S_BT_DL_48_16_LP_data_sizeof				13
+
+#define S_SDT_F_ADDR						573
+#define S_SDT_F_ADDR_END					584
+#define S_SDT_F_sizeof						12
+
+#define S_SDT_F_data_ADDR					585
+#define S_SDT_F_data_ADDR_END					593
+#define S_SDT_F_data_sizeof					9
+
+#define S_MM_DL_OSR_ADDR					594
+#define S_MM_DL_OSR_ADDR_END					617
+#define S_MM_DL_OSR_sizeof					24
+
+#define S_24_zeros_ADDR						618
+#define S_24_zeros_ADDR_END					641
+#define S_24_zeros_sizeof					24
+
+#define S_DMIC1_ADDR						642
+#define S_DMIC1_ADDR_END					653
+#define S_DMIC1_sizeof						12
+
+#define S_DMIC2_ADDR						654
+#define S_DMIC2_ADDR_END					665
+#define S_DMIC2_sizeof						12
+
+#define S_DMIC3_ADDR						666
+#define S_DMIC3_ADDR_END					677
+#define S_DMIC3_sizeof						12
+
+#define S_AMIC_ADDR						678
+#define S_AMIC_ADDR_END						689
+#define S_AMIC_sizeof						12
+
+#define S_EANC_FBK_in_ADDR					690
+#define S_EANC_FBK_in_ADDR_END					713
+#define S_EANC_FBK_in_sizeof					24
+
+#define S_EANC_FBK_out_ADDR					714
+#define S_EANC_FBK_out_ADDR_END					725
+#define S_EANC_FBK_out_sizeof					12
+
+#define S_DMIC1_L_ADDR						726
+#define S_DMIC1_L_ADDR_END					737
+#define S_DMIC1_L_sizeof					12
+
+#define S_DMIC1_R_ADDR						738
+#define S_DMIC1_R_ADDR_END					749
+#define S_DMIC1_R_sizeof					12
+
+#define S_DMIC2_L_ADDR						750
+#define S_DMIC2_L_ADDR_END					761
+#define S_DMIC2_L_sizeof					12
+
+#define S_DMIC2_R_ADDR						762
+#define S_DMIC2_R_ADDR_END					773
+#define S_DMIC2_R_sizeof					12
+
+#define S_DMIC3_L_ADDR						774
+#define S_DMIC3_L_ADDR_END					785
+#define S_DMIC3_L_sizeof					12
+
+#define S_DMIC3_R_ADDR						786
+#define S_DMIC3_R_ADDR_END					797
+#define S_DMIC3_R_sizeof					12
+
+#define S_BT_UL_L_ADDR						798
+#define S_BT_UL_L_ADDR_END					809
+#define S_BT_UL_L_sizeof					12
+
+#define S_BT_UL_R_ADDR						810
+#define S_BT_UL_R_ADDR_END					821
+#define S_BT_UL_R_sizeof					12
+
+#define S_AMIC_L_ADDR						822
+#define S_AMIC_L_ADDR_END					833
+#define S_AMIC_L_sizeof						12
+
+#define S_AMIC_R_ADDR						834
+#define S_AMIC_R_ADDR_END					845
+#define S_AMIC_R_sizeof						12
+
+#define S_EANC_FBK_L_ADDR					846
+#define S_EANC_FBK_L_ADDR_END					857
+#define S_EANC_FBK_L_sizeof					12
+
+#define S_EANC_FBK_R_ADDR					858
+#define S_EANC_FBK_R_ADDR_END					869
+#define S_EANC_FBK_R_sizeof					12
+
+#define S_EchoRef_L_ADDR					870
+#define S_EchoRef_L_ADDR_END					881
+#define S_EchoRef_L_sizeof					12
+
+#define S_EchoRef_R_ADDR					882
+#define S_EchoRef_R_ADDR_END					893
+#define S_EchoRef_R_sizeof					12
+
+#define S_MM_DL_L_ADDR						894
+#define S_MM_DL_L_ADDR_END					905
+#define S_MM_DL_L_sizeof					12
+
+#define S_MM_DL_R_ADDR						906
+#define S_MM_DL_R_ADDR_END					917
+#define S_MM_DL_R_sizeof					12
+
+#define S_MM_UL_ADDR						918
+#define S_MM_UL_ADDR_END					1037
+#define S_MM_UL_sizeof						120
+
+#define S_AMIC_96k_ADDR						1038
+#define S_AMIC_96k_ADDR_END					1061
+#define S_AMIC_96k_sizeof					24
+
+#define S_DMIC0_96k_ADDR					1062
+#define S_DMIC0_96k_ADDR_END					1085
+#define S_DMIC0_96k_sizeof					24
+
+#define S_DMIC1_96k_ADDR					1086
+#define S_DMIC1_96k_ADDR_END					1109
+#define S_DMIC1_96k_sizeof					24
+
+#define S_DMIC2_96k_ADDR					1110
+#define S_DMIC2_96k_ADDR_END					1133
+#define S_DMIC2_96k_sizeof					24
+
+#define S_UL_VX_UL_48_8K_ADDR					1134
+#define S_UL_VX_UL_48_8K_ADDR_END				1145
+#define S_UL_VX_UL_48_8K_sizeof					12
+
+#define S_UL_VX_UL_48_16K_ADDR					1146
+#define S_UL_VX_UL_48_16K_ADDR_END				1157
+#define S_UL_VX_UL_48_16K_sizeof				12
+
+#define S_UL_MIC_48K_ADDR					1158
+#define S_UL_MIC_48K_ADDR_END					1169
+#define S_UL_MIC_48K_sizeof					12
+
+#define S_Voice_8k_UL_ADDR					1170
+#define S_Voice_8k_UL_ADDR_END					1172
+#define S_Voice_8k_UL_sizeof					3
+
+#define S_Voice_8k_DL_ADDR					1173
+#define S_Voice_8k_DL_ADDR_END					1174
+#define S_Voice_8k_DL_sizeof					2
+
+#define S_McPDM_Out1_ADDR					1175
+#define S_McPDM_Out1_ADDR_END					1198
+#define S_McPDM_Out1_sizeof					24
+
+#define S_McPDM_Out2_ADDR					1199
+#define S_McPDM_Out2_ADDR_END					1222
+#define S_McPDM_Out2_sizeof					24
+
+#define S_McPDM_Out3_ADDR					1223
+#define S_McPDM_Out3_ADDR_END					1246
+#define S_McPDM_Out3_sizeof					24
+
+#define S_Voice_16k_UL_ADDR					1247
+#define S_Voice_16k_UL_ADDR_END					1251
+#define S_Voice_16k_UL_sizeof					5
+
+#define S_Voice_16k_DL_ADDR					1252
+#define S_Voice_16k_DL_ADDR_END					1255
+#define S_Voice_16k_DL_sizeof					4
+
+#define S_XinASRC_DL_VX_ADDR					1256
+#define S_XinASRC_DL_VX_ADDR_END				1295
+#define S_XinASRC_DL_VX_sizeof					40
+
+#define S_XinASRC_UL_VX_ADDR					1296
+#define S_XinASRC_UL_VX_ADDR_END				1335
+#define S_XinASRC_UL_VX_sizeof					40
+
+#define S_XinASRC_DL_MM_ADDR					1336
+#define S_XinASRC_DL_MM_ADDR_END				1375
+#define S_XinASRC_DL_MM_sizeof					40
+
+#define S_VX_REC_ADDR						1376
+#define S_VX_REC_ADDR_END					1387
+#define S_VX_REC_sizeof						12
+
+#define S_VX_REC_L_ADDR						1388
+#define S_VX_REC_L_ADDR_END					1399
+#define S_VX_REC_L_sizeof					12
+
+#define S_VX_REC_R_ADDR						1400
+#define S_VX_REC_R_ADDR_END					1411
+#define S_VX_REC_R_sizeof					12
+
+#define S_DL2_M_L_ADDR						1412
+#define S_DL2_M_L_ADDR_END					1423
+#define S_DL2_M_L_sizeof					12
+
+#define S_DL2_M_R_ADDR						1424
+#define S_DL2_M_R_ADDR_END					1435
+#define S_DL2_M_R_sizeof					12
+
+#define S_DL2_M_LR_EQ_data_ADDR					1436
+#define S_DL2_M_LR_EQ_data_ADDR_END				1460
+#define S_DL2_M_LR_EQ_data_sizeof				25
+
+#define S_DL1_M_EQ_data_ADDR					1461
+#define S_DL1_M_EQ_data_ADDR_END				1485
+#define S_DL1_M_EQ_data_sizeof					25
+
+#define S_VX_DL_8_48_BP_data_ADDR				1486
+#define S_VX_DL_8_48_BP_data_ADDR_END				1498
+#define S_VX_DL_8_48_BP_data_sizeof				13
+
+#define S_VX_DL_8_48_LP_data_ADDR				1499
+#define S_VX_DL_8_48_LP_data_ADDR_END				1511
+#define S_VX_DL_8_48_LP_data_sizeof				13
+
+#define S_EARP_48_96_LP_data_ADDR				1512
+#define S_EARP_48_96_LP_data_ADDR_END				1526
+#define S_EARP_48_96_LP_data_sizeof				15
+
+#define S_IHF_48_96_LP_data_ADDR				1527
+#define S_IHF_48_96_LP_data_ADDR_END				1541
+#define S_IHF_48_96_LP_data_sizeof				15
+
+#define S_VX_DL_16_48_HP_data_ADDR				1542
+#define S_VX_DL_16_48_HP_data_ADDR_END				1548
+#define S_VX_DL_16_48_HP_data_sizeof				7
+
+#define S_VX_DL_16_48_LP_data_ADDR				1549
+#define S_VX_DL_16_48_LP_data_ADDR_END				1561
+#define S_VX_DL_16_48_LP_data_sizeof				13
+
+#define S_VX_UL_48_8_BP_data_ADDR				1562
+#define S_VX_UL_48_8_BP_data_ADDR_END				1574
+#define S_VX_UL_48_8_BP_data_sizeof				13
+
+#define S_VX_UL_48_8_LP_data_ADDR				1575
+#define S_VX_UL_48_8_LP_data_ADDR_END				1587
+#define S_VX_UL_48_8_LP_data_sizeof				13
+
+#define S_VX_UL_8_TEMP_ADDR					1588
+#define S_VX_UL_8_TEMP_ADDR_END					1589
+#define S_VX_UL_8_TEMP_sizeof					2
+
+#define S_VX_UL_48_16_HP_data_ADDR				1590
+#define S_VX_UL_48_16_HP_data_ADDR_END				1596
+#define S_VX_UL_48_16_HP_data_sizeof				7
+
+#define S_VX_UL_48_16_LP_data_ADDR				1597
+#define S_VX_UL_48_16_LP_data_ADDR_END				1609
+#define S_VX_UL_48_16_LP_data_sizeof				13
+
+#define S_VX_UL_16_TEMP_ADDR					1610
+#define S_VX_UL_16_TEMP_ADDR_END				1613
+#define S_VX_UL_16_TEMP_sizeof					4
+
+#define S_EANC_IIR_data_ADDR					1614
+#define S_EANC_IIR_data_ADDR_END				1630
+#define S_EANC_IIR_data_sizeof					17
+
+#define S_EANC_SignalTemp_ADDR					1631
+#define S_EANC_SignalTemp_ADDR_END				1651
+#define S_EANC_SignalTemp_sizeof				21
+
+#define S_EANC_Input_ADDR					1652
+#define S_EANC_Input_ADDR_END					1652
+#define S_EANC_Input_sizeof					1
+
+#define S_EANC_Output_ADDR					1653
+#define S_EANC_Output_ADDR_END					1653
+#define S_EANC_Output_sizeof					1
+
+#define S_APS_IIRmem1_ADDR					1654
+#define S_APS_IIRmem1_ADDR_END					1662
+#define S_APS_IIRmem1_sizeof					9
+
+#define S_APS_M_IIRmem2_ADDR					1663
+#define S_APS_M_IIRmem2_ADDR_END				1665
+#define S_APS_M_IIRmem2_sizeof					3
+
+#define S_APS_C_IIRmem2_ADDR					1666
+#define S_APS_C_IIRmem2_ADDR_END				1668
+#define S_APS_C_IIRmem2_sizeof					3
+
+#define S_APS_DL1_OutSamples_ADDR				1669
+#define S_APS_DL1_OutSamples_ADDR_END				1670
+#define S_APS_DL1_OutSamples_sizeof				2
+
+#define S_APS_DL1_COIL_OutSamples_ADDR				1671
+#define S_APS_DL1_COIL_OutSamples_ADDR_END			1672
+#define S_APS_DL1_COIL_OutSamples_sizeof			2
+
+#define S_APS_DL2_L_OutSamples_ADDR				1673
+#define S_APS_DL2_L_OutSamples_ADDR_END				1674
+#define S_APS_DL2_L_OutSamples_sizeof				2
+
+#define S_APS_DL2_L_COIL_OutSamples_ADDR			1675
+#define S_APS_DL2_L_COIL_OutSamples_ADDR_END			1676
+#define S_APS_DL2_L_COIL_OutSamples_sizeof			2
+
+#define S_APS_DL2_R_OutSamples_ADDR				1677
+#define S_APS_DL2_R_OutSamples_ADDR_END				1678
+#define S_APS_DL2_R_OutSamples_sizeof				2
+
+#define S_APS_DL2_R_COIL_OutSamples_ADDR			1679
+#define S_APS_DL2_R_COIL_OutSamples_ADDR_END			1680
+#define S_APS_DL2_R_COIL_OutSamples_sizeof			2
+
+#define S_XinASRC_ECHO_REF_ADDR					1681
+#define S_XinASRC_ECHO_REF_ADDR_END				1720
+#define S_XinASRC_ECHO_REF_sizeof				40
+
+#define S_ECHO_REF_16K_ADDR					1721
+#define S_ECHO_REF_16K_ADDR_END					1725
+#define S_ECHO_REF_16K_sizeof					5
+
+#define S_ECHO_REF_8K_ADDR					1726
+#define S_ECHO_REF_8K_ADDR_END					1728
+#define S_ECHO_REF_8K_sizeof					3
+
+#define S_DL1_ADDR						1729
+#define S_DL1_ADDR_END						1740
+#define S_DL1_sizeof						12
+
+#define S_APS_DL2_L_IIRmem1_ADDR				1741
+#define S_APS_DL2_L_IIRmem1_ADDR_END				1749
+#define S_APS_DL2_L_IIRmem1_sizeof				9
+
+#define S_APS_DL2_R_IIRmem1_ADDR				1750
+#define S_APS_DL2_R_IIRmem1_ADDR_END				1758
+#define S_APS_DL2_R_IIRmem1_sizeof				9
+
+#define S_APS_DL2_L_M_IIRmem2_ADDR				1759
+#define S_APS_DL2_L_M_IIRmem2_ADDR_END				1761
+#define S_APS_DL2_L_M_IIRmem2_sizeof				3
+
+#define S_APS_DL2_R_M_IIRmem2_ADDR				1762
+#define S_APS_DL2_R_M_IIRmem2_ADDR_END				1764
+#define S_APS_DL2_R_M_IIRmem2_sizeof				3
+
+#define S_APS_DL2_L_C_IIRmem2_ADDR				1765
+#define S_APS_DL2_L_C_IIRmem2_ADDR_END				1767
+#define S_APS_DL2_L_C_IIRmem2_sizeof				3
+
+#define S_APS_DL2_R_C_IIRmem2_ADDR				1768
+#define S_APS_DL2_R_C_IIRmem2_ADDR_END				1770
+#define S_APS_DL2_R_C_IIRmem2_sizeof				3
+
+#define S_DL1_APS_ADDR						1771
+#define S_DL1_APS_ADDR_END					1782
+#define S_DL1_APS_sizeof					12
+
+#define S_DL2_L_APS_ADDR					1783
+#define S_DL2_L_APS_ADDR_END					1794
+#define S_DL2_L_APS_sizeof					12
+
+#define S_DL2_R_APS_ADDR					1795
+#define S_DL2_R_APS_ADDR_END					1806
+#define S_DL2_R_APS_sizeof					12
+
+#define S_ECHO_REF_48_8_BP_data_ADDR				1807
+#define S_ECHO_REF_48_8_BP_data_ADDR_END			1819
+#define S_ECHO_REF_48_8_BP_data_sizeof				13
+
+#define S_ECHO_REF_48_8_LP_data_ADDR				1820
+#define S_ECHO_REF_48_8_LP_data_ADDR_END			1832
+#define S_ECHO_REF_48_8_LP_data_sizeof				13
+
+#define S_ECHO_REF_48_16_HP_data_ADDR				1833
+#define S_ECHO_REF_48_16_HP_data_ADDR_END			1839
+#define S_ECHO_REF_48_16_HP_data_sizeof				7
+
+#define S_ECHO_REF_48_16_LP_data_ADDR				1840
+#define S_ECHO_REF_48_16_LP_data_ADDR_END			1852
+#define S_ECHO_REF_48_16_LP_data_sizeof				13
+
+#define S_APS_DL1_EQ_data_ADDR					1853
+#define S_APS_DL1_EQ_data_ADDR_END				1861
+#define S_APS_DL1_EQ_data_sizeof				9
+
+#define S_APS_DL2_EQ_data_ADDR					1862
+#define S_APS_DL2_EQ_data_ADDR_END				1870
+#define S_APS_DL2_EQ_data_sizeof				9
+
+#define S_DC_DCvalue_ADDR					1871
+#define S_DC_DCvalue_ADDR_END					1871
+#define S_DC_DCvalue_sizeof					1
+
+#define S_VIBRA_ADDR						1872
+#define S_VIBRA_ADDR_END					1877
+#define S_VIBRA_sizeof						6
+
+#define S_Vibra2_in_ADDR					1878
+#define S_Vibra2_in_ADDR_END					1883
+#define S_Vibra2_in_sizeof					6
+
+#define S_Vibra2_addr_ADDR					1884
+#define S_Vibra2_addr_ADDR_END					1884
+#define S_Vibra2_addr_sizeof					1
+
+#define S_VibraCtrl_forRightSM_ADDR				1885
+#define S_VibraCtrl_forRightSM_ADDR_END				1908
+#define S_VibraCtrl_forRightSM_sizeof				24
+
+#define S_Rnoise_mem_ADDR					1909
+#define S_Rnoise_mem_ADDR_END					1909
+#define S_Rnoise_mem_sizeof					1
+
+#define S_Ctrl_ADDR						1910
+#define S_Ctrl_ADDR_END						1927
+#define S_Ctrl_sizeof						18
+
+#define S_Vibra1_in_ADDR					1928
+#define S_Vibra1_in_ADDR_END					1933
+#define S_Vibra1_in_sizeof					6
+
+#define S_Vibra1_temp_ADDR					1934
+#define S_Vibra1_temp_ADDR_END					1957
+#define S_Vibra1_temp_sizeof					24
+
+#define S_VibraCtrl_forLeftSM_ADDR				1958
+#define S_VibraCtrl_forLeftSM_ADDR_END				1981
+#define S_VibraCtrl_forLeftSM_sizeof				24
+
+#define S_Vibra1_mem_ADDR					1982
+#define S_Vibra1_mem_ADDR_END					1992
+#define S_Vibra1_mem_sizeof					11
+
+#define S_VibraCtrl_Stereo_ADDR					1993
+#define S_VibraCtrl_Stereo_ADDR_END				2016
+#define S_VibraCtrl_Stereo_sizeof				24
+
+#define S_AMIC_96_48_data_ADDR					2017
+#define S_AMIC_96_48_data_ADDR_END				2035
+#define S_AMIC_96_48_data_sizeof				19
+
+#define S_DMIC0_96_48_data_ADDR					2036
+#define S_DMIC0_96_48_data_ADDR_END				2054
+#define S_DMIC0_96_48_data_sizeof				19
+
+#define S_DMIC1_96_48_data_ADDR					2055
+#define S_DMIC1_96_48_data_ADDR_END				2073
+#define S_DMIC1_96_48_data_sizeof				19
+
+#define S_DMIC2_96_48_data_ADDR					2074
+#define S_DMIC2_96_48_data_ADDR_END				2092
+#define S_DMIC2_96_48_data_sizeof				19
+
+#define S_EANC_FBK_96_48_data_ADDR				2093
+#define S_EANC_FBK_96_48_data_ADDR_END				2111
+#define S_EANC_FBK_96_48_data_sizeof				19
+
+#define S_DBG_8K_PATTERN_ADDR					2112
+#define S_DBG_8K_PATTERN_ADDR_END				2119
+#define S_DBG_8K_PATTERN_sizeof					8
+
+#define S_DBG_16K_PATTERN_ADDR					2120
+#define S_DBG_16K_PATTERN_ADDR_END				2135
+#define S_DBG_16K_PATTERN_sizeof				16
+
+#define S_DBG_48K_PATTERN_ADDR					2136
+#define S_DBG_48K_PATTERN_ADDR_END				2159
+#define S_DBG_48K_PATTERN_sizeof				24
+
+#define S_DBG_MCPDM_PATTERN_ADDR				2160
+#define S_DBG_MCPDM_PATTERN_ADDR_END				2231
+#define S_DBG_MCPDM_PATTERN_sizeof				72
+
+#endif /* _ABESM_ADDR_H_ */
diff --git a/sound/soc/codecs/abe/abe_sys.h b/sound/soc/codecs/abe/abe_sys.h
new file mode 100644
index 000000000000..f4d50d2132ff
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_sys.h
@@ -0,0 +1,9 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
diff --git a/sound/soc/codecs/abe/abe_taskId.h b/sound/soc/codecs/abe/abe_taskId.h
new file mode 100644
index 000000000000..4f6ace57a021
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_taskId.h
@@ -0,0 +1,129 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_TASKID_H_
+#define _ABE_TASKID_H_
+
+#define C_ABE_FW_TASK_DL1_APS_CORE		0
+#define C_ABE_FW_TASK_DL1_APS_COIL_CORE		1
+#define C_ABE_FW_TASK_DL2_L_APS_CORE		2
+#define C_ABE_FW_TASK_DL2_L_APS_COIL_CORE	3
+#define C_ABE_FW_TASK_DL2_R_APS_CORE		4
+#define C_ABE_FW_TASK_DL2_R_APS_COIL_CORE	5
+#define C_ABE_FW_TASK_ASRC_VX_DL_8		6
+#define C_ABE_FW_TASK_ASRC_VX_DL_16		7
+#define C_ABE_FW_TASK_ASRC_MM_DL		8
+#define C_ABE_FW_TASK_ASRC_VX_UL_8		9
+#define C_ABE_FW_TASK_ASRC_VX_UL_16		10
+#define C_ABE_FW_TASK_ASRC_ECHO_REF_8		11
+#define C_ABE_FW_TASK_ASRC_ECHO_REF_16		12
+#define C_ABE_FW_TASK_DC_REMOVAL2		13
+#define C_ABE_FW_TASK_VX_UL_48_8_DEC		14
+#define C_ABE_FW_TASK_VX_UL_48_16_DEC		15
+#define C_ABE_FW_TASK_BT_DL_48_8_DEC		16
+#define C_ABE_FW_TASK_BT_DL_48_16_DEC		17
+#define C_ABE_FW_TASK_ECHO_REF_48_8_DEC		18
+#define C_ABE_FW_TASK_ECHO_REF_48_16_DEC	19
+#define C_ABE_FW_TASK_DL2_EQ			20
+#define C_ABE_FW_TASK_DL2_L_APS_IIR		21
+#define C_ABE_FW_TASK_DL2_R_APS_IIR		22
+#define C_ABE_FW_TASK_DL2_APS_EQ		23
+#define C_ABE_FW_TASK_ECHO_REF_48_16		24
+#define C_ABE_FW_TASK_ECHO_REF_48_8		25
+#define C_ABE_FW_TASK_GAIN_UPDATE		26
+#define C_ABE_FW_TASK_SideTone			27
+#define C_ABE_FW_TASK_VX_DL_8_48_BP		28
+#define C_ABE_FW_TASK_VX_DL_8_48_LP		29
+#define C_ABE_FW_TASK_VX_DL_16_48_HP		30
+#define C_ABE_FW_TASK_VX_DL_16_48_LP		31
+#define C_ABE_FW_TASK_VX_UL_48_8_LP		32
+#define C_ABE_FW_TASK_VX_UL_48_8_BP		33
+#define C_ABE_FW_TASK_VX_UL_48_16_LP		34
+#define C_ABE_FW_TASK_VX_UL_48_16_HP		35
+#define C_ABE_FW_TASK_BT_UL_8_48_BP		36
+#define C_ABE_FW_TASK_BT_UL_8_48_LP		37
+#define C_ABE_FW_TASK_BT_UL_16_48_HP		38
+#define C_ABE_FW_TASK_BT_UL_16_48_LP		39
+#define C_ABE_FW_TASK_BT_DL_48_8_LP		40
+#define C_ABE_FW_TASK_BT_DL_48_8_BP		41
+#define C_ABE_FW_TASK_BT_DL_48_16_LP		42
+#define C_ABE_FW_TASK_BT_DL_48_16_HP		43
+#define C_ABE_FW_TASK_DL1_EQ			44
+#define C_ABE_FW_TASK_DL1_APS_IIR		45
+#define C_ABE_FW_TASK_ECHO_REF_48_8_LP		46
+#define C_ABE_FW_TASK_ECHO_REF_48_8_BP		47
+#define C_ABE_FW_TASK_ECHO_REF_48_16_LP		48
+#define C_ABE_FW_TASK_ECHO_REF_48_16_HP		49
+#define C_ABE_FW_TASK_DL1_APS_EQ		50
+#define C_ABE_FW_TASK_IHF_48_96_LP		51
+#define C_ABE_FW_TASK_EARP_48_96_LP		52
+#define C_ABE_FW_TASK_DL1_GAIN			53
+#define C_ABE_FW_TASK_DL2_GAIN			54
+#define C_ABE_FW_TASK_IO_PING_PONG		55
+#define C_ABE_FW_TASK_IO_DMIC			56
+#define C_ABE_FW_TASK_IO_PDM_UL			57
+#define C_ABE_FW_TASK_IO_BT_VX_UL		58
+#define C_ABE_FW_TASK_IO_MM_UL			59
+#define C_ABE_FW_TASK_IO_MM_UL2			60
+#define C_ABE_FW_TASK_IO_VX_UL			61
+#define C_ABE_FW_TASK_IO_MM_DL			62
+#define C_ABE_FW_TASK_IO_VX_DL			63
+#define C_ABE_FW_TASK_IO_TONES_DL		64
+#define C_ABE_FW_TASK_IO_VIB_DL			65
+#define C_ABE_FW_TASK_IO_BT_VX_DL		66
+#define C_ABE_FW_TASK_IO_PDM_DL			67
+#define C_ABE_FW_TASK_IO_MM_EXT_OUT		68
+#define C_ABE_FW_TASK_IO_MM_EXT_IN		69
+#define C_ABE_FW_TASK_DEBUG_IRQFIFO		70
+#define C_ABE_FW_TASK_EchoMixer			71
+#define C_ABE_FW_TASK_SDTMixer			72
+#define C_ABE_FW_TASK_DL1Mixer			73
+#define C_ABE_FW_TASK_DL2Mixer			74
+#define C_ABE_FW_TASK_VXRECMixer		75
+#define C_ABE_FW_TASK_ULMixer			76
+#define C_ABE_FW_TASK_VIBRA_PACK		77
+#define C_ABE_FW_TASK_VX_DL_8_48_0SR		78
+#define C_ABE_FW_TASK_VX_DL_16_48_0SR		79
+#define C_ABE_FW_TASK_BT_UL_8_48_0SR		80
+#define C_ABE_FW_TASK_BT_UL_16_48_0SR		81
+#define C_ABE_FW_TASK_IHF_48_96_0SR		82
+#define C_ABE_FW_TASK_EARP_48_96_0SR		83
+#define C_ABE_FW_TASK_AMIC_SPLIT		84
+#define C_ABE_FW_TASK_DMIC1_SPLIT		85
+#define C_ABE_FW_TASK_DMIC2_SPLIT		86
+#define C_ABE_FW_TASK_DMIC3_SPLIT		87
+#define C_ABE_FW_TASK_VXREC_SPLIT		88
+#define C_ABE_FW_TASK_BT_UL_SPLIT		89
+#define C_ABE_FW_TASK_MM_SPLIT			90
+#define C_ABE_FW_TASK_DL2_APS_SPLIT		91
+#define C_ABE_FW_TASK_VIBRA_SPLIT		92
+#define C_ABE_FW_TASK_EANC_FBK_SPLIT		93
+#define C_ABE_FW_TASK_VX_UL_ROUTING		94
+#define C_ABE_FW_TASK_MM_UL2_ROUTING		95
+#define C_ABE_FW_TASK_VIBRA1			96
+#define C_ABE_FW_TASK_VIBRA2			97
+#define C_ABE_FW_TASK_BT_UL_16_48		98
+#define C_ABE_FW_TASK_BT_UL_8_48		99
+#define C_ABE_FW_TASK_BT_DL_48_16		100
+#define C_ABE_FW_TASK_BT_DL_48_8		101
+#define C_ABE_FW_TASK_VX_DL_16_48		102
+#define C_ABE_FW_TASK_VX_DL_8_48		103
+#define C_ABE_FW_TASK_VX_UL_48_16		104
+#define C_ABE_FW_TASK_VX_UL_48_8		105
+#define C_ABE_FW_TASK_DBG_SYNC			106
+#define C_ABE_FW_TASK_APS_DL1_IRQs		107
+#define C_ABE_FW_TASK_APS_DL2_L_IRQs		108
+#define C_ABE_FW_TASK_APS_DL2_R_IRQs		109
+#define C_ABE_FW_TASK_AMIC_96_48_LP		110
+#define C_ABE_FW_TASK_DMIC1_96_48_LP		111
+#define C_ABE_FW_TASK_DMIC2_96_48_LP		112
+#define C_ABE_FW_TASK_DMIC3_96_48_LP		113
+
+#endif	/* _ABE_TASKID_H_ */
diff --git a/sound/soc/codecs/abe/abe_test.c b/sound/soc/codecs/abe/abe_test.c
new file mode 100644
index 000000000000..4c7ea4a338fd
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_test.c
@@ -0,0 +1,866 @@
+/*
+ * ==========================================================================
+ *				 Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.	All Rights Reserved.
+ *
+ *	Use of this firmware is controlled by the terms and conditions found
+ *	in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+#include "ABE_MAIN.h"
+#include "ABE_DEF.h"
+
+void abe_test_scenario_1(void);
+void abe_test_scenario_2(void);
+void abe_test_scenario_3(void);
+void abe_test_scenario_4(void);
+
+/*
+* @fn ABE_TEST_SCENARIO()
+*/
+void abe_test_scenario(abe_int32 scenario_id)
+{
+	switch (scenario_id) {
+	case 1:
+		abe_test_scenario_1();
+		break;
+	case 2:
+		abe_test_scenario_2();
+		break;
+	case 3:
+		abe_test_scenario_3();
+		break;
+	case 4:
+		abe_test_scenario_4();
+		break;
+	}
+}
+
+/*
+* @fn abe_test_read_time ()
+*/
+abe_uint32 abe_test_read_time(void)
+{
+	abe_uint32 time;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_slotCounter_ADDR,
+						(abe_uint32*)&time, sizeof (time));
+	return (time & 0xFFFF);
+}
+
+/*
+* @fn ABE_TEST_SCENARIO_1 ()
+*
+*	DMA AUDIO PLAYER + DMA VOICE CALL 16kHz
+*/
+void abe_test_scenario_1(void)
+{
+	static abe_int32 time_offset, state;
+	abe_data_format_t format;
+	abe_dma_t dma_sink;
+	abe_uint32 current_time;
+	abe_use_case_id UC2[] = {
+		ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE,
+		ABE_RINGER_TONES,
+		(abe_use_case_id)0
+	};
+	// abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0};
+	abe_opp_t OPP;
+	abe_hw_config_init_t CONFIG;
+
+	/* Scenario 1- 16kHz first */
+	switch (state) {
+	case 0:
+		state ++;
+		time_offset = abe_test_read_time();
+		abe_reset_hal();
+		abe_load_fw();
+
+		/* check HW config and OPP config */
+		abe_read_hardware_configuration(UC2, &OPP, &CONFIG);
+		/* sets the OPP100 on FW05.xx */
+		abe_set_opp_processing(OPP);
+		/* "tick" of the audio engine */
+		abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);
+
+		abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC,
+				(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_BT]);
+
+		format.f = 48000;
+		format.samp_format = SIX_MSB;
+		abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink);
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink);
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+		/* enable all DMIC aquisition */
+		abe_enable_data_transfer(MM_UL_PORT);
+		/* enable large-band DMIC aquisition */
+		abe_enable_data_transfer(MM_UL2_PORT);
+		abe_enable_data_transfer(VX_UL_PORT);
+
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink);
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink);
+		format.f = 24000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(VIB_DL_PORT, &format, ABE_CBPR6_IDX, &dma_sink);
+		abe_enable_data_transfer(TONES_DL_PORT);
+		abe_enable_data_transfer(VX_DL_PORT);
+		/* enable all the data paths */
+		abe_enable_data_transfer(MM_DL_PORT);
+		abe_enable_data_transfer(VIB_DL_PORT);
+
+		/* SERIAL PORTS TEST */
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_serial_port(BT_VX_UL_PORT, &format, MCBSP1_RX);
+		format.f = 8000;
+		format.samp_format = MONO_RSHIFTED_16;
+		abe_connect_serial_port(BT_VX_DL_PORT, &format, MCBSP1_TX);
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_serial_port(MM_EXT_IN_PORT, &format, MCBSP2_RX);
+		format.f = 48000;
+		format.samp_format = MONO_RSHIFTED_16;
+		abe_connect_serial_port(MM_EXT_OUT_PORT, &format, MCBSP2_TX);
+		abe_enable_data_transfer(BT_VX_UL_PORT);
+		abe_enable_data_transfer(BT_VX_DL_PORT);
+		abe_enable_data_transfer(MM_EXT_IN_PORT);
+		abe_enable_data_transfer(MM_EXT_OUT_PORT);
+
+		/* DMIC ATC can be enabled even if the DMIC */
+		abe_enable_data_transfer(DMIC_PORT);
+		abe_enable_data_transfer(PDM_DL_PORT);
+		abe_enable_data_transfer(PDM_UL_PORT);
+
+		/* mixers' configuration = voice on earphone + music on hands-free path */
+		abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+		abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2);
+		abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+		abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES);
+
+		abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_TONES);
+		abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+		abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+		abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2);
+
+		abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER);
+		abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER);
+
+		abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_MM_DL);
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_TONES);
+		abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_0MS, MIX_AUDUL_INPUT_UPLINK);
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_VX_DL);
+
+		abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_TONES);
+		abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_DL);
+		abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_MM_DL);
+		abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_UL);
+		break;
+	case 1:
+		current_time = abe_test_read_time();
+		if ((current_time - time_offset) < 100)
+			break;
+		else
+			state ++;
+		break;
+	case 2:
+		current_time = abe_test_read_time();
+		if ((current_time - time_offset) < 100000)
+			break;
+		else
+			state ++; // Internal buffer analysis
+		break;
+	default:
+		state = 0;
+		break;
+	}
+}
+
+/*
+* @fn ABE_TEST_SCENARIO_2 ()
+*
+*	DMA AUDIO PLAYER + DMA VOICE CALL 8kHz
+*/
+void abe_test_scenario_2 (void)
+{
+	static abe_int32 time_offset, state;
+	abe_data_format_t format;
+	abe_dma_t dma_sink;
+	abe_uint32 current_time;
+	abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0};
+	abe_opp_t OPP;
+	abe_hw_config_init_t CONFIG;
+
+	/* Scenario 1- 16kHz first */
+	switch (state)
+	{
+	case 0:
+		state ++;
+
+		time_offset = abe_test_read_time();
+		abe_reset_hal();
+		abe_load_fw();
+
+		/* check HW config and OPP config */
+		abe_read_hardware_configuration(UC2, &OPP,  &CONFIG);
+		abe_set_opp_processing(OPP); /* sets the OPP100 on FW05.xx */
+		/* "tick" of the audio engine */
+		abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);
+
+		abe_set_router_configuration(UPROUTE,
+			UPROUTE_CONFIG_AMIC,
+			(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]);
+
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink);
+
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink);
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+		abe_enable_data_transfer(MM_UL_PORT); /* enable all DMIC aquisition */
+		abe_enable_data_transfer(MM_UL2_PORT); /* enable large-band DMIC aquisition */
+		abe_enable_data_transfer(VX_UL_PORT);
+
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink);
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink);
+		format.f = 24000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(VIB_DL_PORT,&format, ABE_CBPR6_IDX, &dma_sink);
+		abe_enable_data_transfer(TONES_DL_PORT);
+		abe_enable_data_transfer(VX_DL_PORT);
+		abe_enable_data_transfer(MM_DL_PORT); /* enable all the data paths */
+		abe_enable_data_transfer(VIB_DL_PORT);
+
+		abe_enable_data_transfer(DMIC_PORT);	/* DMIC ATC can be enabled even if the DMIC */
+		abe_enable_data_transfer(PDM_DL_PORT);
+		abe_enable_data_transfer(PDM_UL_PORT);
+
+		/* mixers' configuration = voice on earphone + music on hands-free path */
+		abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES);
+		abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+		abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+		abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2);
+
+		abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES);
+		abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+		abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+		abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2);
+
+		abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER);
+		abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER);
+
+		abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_TONES);
+		abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_0MS, MIX_AUDUL_INPUT_UPLINK);
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_MM_DL);
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_VX_DL);
+
+		abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_TONES);
+		abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_DL);
+		abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_MM_DL);
+		abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_UL);
+		break;
+	case 1:
+		current_time = abe_test_read_time();
+		if ((current_time - time_offset) < 100)
+			break;
+		else
+			state ++;
+		break;
+	case 2:
+		current_time = abe_test_read_time();
+		if ((current_time - time_offset) < 100000)
+			break;
+		else
+			state ++;
+		break;
+	default:
+		state = 0;
+		break;
+	}
+}
+/**
+*	@fn ABE_TEST_SCENARIO_3 ()
+*
+*	IRQ AUDIO PLAYER 44100Hz  OPP 25%
+*/
+void abe_test_scenario_3 (void)
+{
+	static abe_int32 time_offset, state, gain=0x040000, i;
+	abe_data_format_t format;
+	abe_uint32 data_sink;
+	abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0};
+	// abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0};
+	abe_opp_t OPP;
+	abe_hw_config_init_t CONFIG;
+
+	/* Scenario 1- 16kHz first */
+	switch (state) {
+	case 0:
+		state ++;
+		time_offset = abe_test_read_time();
+		abe_reset_hal();
+		abe_load_fw();
+
+		abe_read_hardware_configuration(UC2, &OPP,  &CONFIG); /* check HW config and OPP config */
+		abe_set_opp_processing(ABE_OPP25);	/* sets the OPP25 on FW05.xx */
+		abe_write_event_generator(EVENT_44100);	/* "tick" of the audio engine */
+
+		/* connect a Ping-Pong cache-flush protocol to MM_DL port */
+#define N_SAMPLES_BYTES (25 *8)				/* half-buffer size in bytes, 32/32 data format */
+		format.f = 44100;
+		format.samp_format = STEREO_MSB;
+		abe_add_subroutine(&abe_irq_pingpong_player_id,
+			(abe_subroutine2) abe_default_irq_pingpong_player_32bits,
+			SUB_0_PARAM, (abe_uint32*)0);
+
+		abe_connect_irq_ping_pong_port(MM_DL_PORT, &format,
+			abe_irq_pingpong_player_id, N_SAMPLES_BYTES,
+			&data_sink, PING_PONG_WITH_MCU_IRQ);
+
+		abe_enable_data_transfer(MM_DL_PORT);	/* enable all the data paths */
+		abe_enable_data_transfer(PDM_DL_PORT);
+
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_serial_port(MM_EXT_OUT_PORT, &format, MCBSP2_TX);
+		abe_enable_data_transfer(MM_EXT_OUT_PORT);
+
+		/* mixers' configuration */
+		abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_TONES);
+		abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+		break;
+	}
+}
+/**
+* @fn ABE_TEST_SCENARIO_4 ()
+*
+*	DMA AUDIO PLAYER + DMA VOICE CALL 8kHz OPP 50%
+*/
+void abe_test_scenario_4 (void)
+{
+	static abe_int32 time_offset, state;
+	abe_data_format_t format;
+	abe_dma_t dma_sink;
+	abe_uint32 current_time;
+	abe_use_case_id UC2[] = {
+		ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE,
+		ABE_RINGER_TONES,
+		(abe_use_case_id)0
+	};
+	// abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0};
+	abe_opp_t OPP;
+	abe_hw_config_init_t CONFIG;
+
+	/* Scenario 1- 16kHz first */
+	switch (state) {
+	case 0:
+		state ++;
+		time_offset = abe_test_read_time();
+
+		/* check HW config and OPP config */
+		abe_read_hardware_configuration(UC2, &OPP, &CONFIG);
+		/* sets the OPP100 on FW05.xx */
+		abe_set_opp_processing(OPP);
+		/* "tick" of the audio engine */
+		abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);
+
+		abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC,
+			(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]);
+
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink);
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink);
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+		/* enable all DMIC aquisition */
+		abe_enable_data_transfer(MM_UL_PORT);
+		/* enable large-band DMIC aquisition */
+		abe_enable_data_transfer(MM_UL2_PORT);
+		abe_enable_data_transfer(VX_UL_PORT);
+
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink);
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink);
+		format.f = 24000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(VIB_DL_PORT, &format, ABE_CBPR6_IDX, &dma_sink);
+		abe_enable_data_transfer(TONES_DL_PORT);
+		abe_enable_data_transfer(VX_DL_PORT);
+		/* enable all the data paths */
+		abe_enable_data_transfer(MM_DL_PORT);
+		abe_enable_data_transfer(VIB_DL_PORT);
+
+		/* DMIC ATC can be enabled even if the DMIC */
+		abe_enable_data_transfer(DMIC_PORT);
+		abe_enable_data_transfer(PDM_DL_PORT);
+		abe_enable_data_transfer(PDM_UL_PORT);
+
+		/* mixers' configuration = voice on earphone + music on hands-free path */
+		abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES);
+		abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+		abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+		abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2);
+
+		abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES);
+		abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+		abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+		abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2);
+
+		abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER);
+		abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER);
+
+		abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_TONES);
+		abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_0MS, MIX_AUDUL_INPUT_UPLINK);
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_MM_DL);
+		abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_VX_DL);
+
+		abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_TONES);
+		abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_DL);
+		abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_MM_DL);
+		abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_UL);
+
+		abe_write_gain(GAINS_DMIC1, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DMIC1, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+		abe_write_gain(GAINS_DMIC2, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DMIC2, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+		abe_write_gain(GAINS_DMIC3, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DMIC3, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+		abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+
+		abe_write_gain(GAINS_SPLIT , GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_SPLIT,  GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+		//abe_write_gain(GAINS_EANC , GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		//abe_write_gain(GAINS_EANC,  GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+		abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+		abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET);
+		abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET);
+		break;
+		case 1:
+			current_time = abe_test_read_time();
+			if ((current_time - time_offset) < 100)
+				break;
+			else
+				state ++; /* Gains switch */
+			break;
+		case 2:
+			current_time = abe_test_read_time();
+			if ((current_time - time_offset) < 100000)
+				break;
+			else
+				state ++; /* Internal buffer analysis */
+			break;
+		default:
+			state = 0;
+			break;
+		}
+}
+
+#if 0
+
+	/*
+	 *		build the default uplink router configurations
+	 */
+	abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC,
+		(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]);
+#if 0
+	abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1,
+		(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]);
+	abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC2,
+		(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC2]);
+	abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC3,
+		(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC3]);
+#endif
+	/* meaningful other microphone configuration can be added here */
+	/* init hardware components */
+	abe_hw_configuration();
+
+	/* enable the VX_UL path with Analog microphones from Phoenix */
+	/*	MM_DL INIT
+		connect a DMA channel to MM_DL port (ATC FIFO) */
+	format.f = 48000;
+	format.samp_format = STEREO_MSB;
+	abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink);
+
+	/*	VX_DL INIT
+		connect a DMA channel to VX_DL port (ATC FIFO) */
+	format.f = 16000;
+	format.samp_format = STEREO_MSB;
+	abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+
+	/*	VX_UL INIT
+		connect a DMA channel to VX_UL port (ATC FIFO) */
+	format.f = 16000;
+	format.samp_format = STEREO_MSB;
+	abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+
+	/*	MM_UL2 INIT
+		connect a DMA channel to MM_UL2 port (ATC FIFO) */
+	format.f = 48000;
+	format.samp_format = STEREO_MSB;
+	abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink);
+
+	/*	MM_UL INIT
+		connect a DMA channel to MM_UL port (ATC FIFO) */
+	format.f = 48000;
+	format.samp_format = STEREO_MSB;
+	abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink);
+
+	/*	TONES INIT
+		connect a DMA channel to TONES port (ATC FIFO) */
+	format.f = 48000;
+	format.samp_format = STEREO_MSB;
+	abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink);
+
+	/*	VIBRA/HAPTICS INIT
+		connect a DMA channel to VIBRA/HAPTICS port (ATC FIFO) */
+	format.f = 24000;
+	format.samp_format = STEREO_MSB;
+	abe_connect_cbpr_dmareq_port(VIB_DL_PORT, &format, ABE_CBPR6_IDX, &dma_sink);
+
+	/* mixers' default configuration = voice on earphone + music on hands-free path */
+	case 2:
+	/* Scenario 2-	8kHz first */
+		switch (time10us) {
+		case 1:
+			/* check HW config and OPP config */
+			abe_read_hardware_configuration(UC2, &OPP,	&CONFIG);
+			/* sets the OPP100 on FW05.xx */
+			abe_set_opp_processing(OPP);
+			/* "tick" of the audio engine */
+			abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);
+			// enables VOICECALL-MMDL-MMUL-8/16kHz-ROUTING
+			abe_reset_hal();
+			format.f = 8000;
+			format.samp_format = MONO_MSB;
+			abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+			format.f = 8000;
+			format.samp_format = MONO_MSB;
+			abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+
+			abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_1MS, MIX_DL1_INPUT_VX_DL);
+			abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL);
+
+			/* enable large-band DMIC aquisition */
+			abe_enable_data_transfer(MM_UL2_PORT);
+			/* enable all DMIC aquisition */
+			abe_enable_data_transfer(MM_UL_PORT);
+			/* enable all the data paths */
+			abe_enable_data_transfer(MM_DL_PORT);
+			abe_enable_data_transfer(VX_DL_PORT);
+			abe_enable_data_transfer(VX_UL_PORT);
+			abe_enable_data_transfer(PDM_UL_PORT);
+			/* DMIC ATC can be enabled even if the DMIC */
+			abe_enable_data_transfer(DMIC_PORT);
+			abe_enable_data_transfer(PDM_DL_PORT);
+			abe_enable_data_transfer(TONES_DL_PORT);
+			break;
+		case 100:
+			abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_TONES);
+			abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_1MS, MIX_DL1_INPUT_VX_DL);
+			abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL);
+			abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_5MS, MIX_DL1_INPUT_MM_UL2);
+			break;
+		case 1200:
+			abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1,
+				(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]);
+			break;
+		case 8000:		// end
+			fcloseall();
+			exit(-2);
+		}
+	 /* case scenario_id ==2 */
+	break;
+	case 3:
+		/* Scenario 3 PING-PONG DMAreq */
+		switch (time10us) {
+		case 1:
+			/* Ping-Pong access through MM_DL using Left/Right 16bits/16bits data format */
+			/* To be added here :  Device driver initialization following
+					abe_read_hardware_configuration() returned data
+					McPDM_DL : 6 slots activated (5 + Commands)
+					DMIC : 6 microphones activated
+					McPDM_UL : 2 microphones activated (No status)
+			*/
+			abe_read_hardware_configuration(UC5, &OPP, &CONFIG);
+			abe_set_opp_processing(OPP);
+			abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);
+
+			/* MM_DL INIT (overwrite the previous default initialization made above  */
+			format.f = 48000;
+			format.samp_format = MONO_MSB;
+
+			/* connect a Ping-Pong SDMA protocol to MM_DL port with Ping-Pong 12 mono
+			 * samples (12x4 bytes for each ping & pong size)*/
+			abe_connect_dmareq_ping_pong_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, (12 * 4), &dma_sink);
+
+			/* mixers' configuration = voice on earphone + music on hands-free path */
+			abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL);
+			abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL);
+
+			/* Here : connect the sDMA to "dma_sink" content */
+			/* enable all the data paths */
+			abe_enable_data_transfer(MM_DL_PORT);
+			abe_enable_data_transfer(PDM_DL_PORT);
+			break;
+		case 8000:		// end
+			fcloseall();
+			exit(-3);
+		}
+	/* case scenario_id ==3 */
+	break;
+	case 40:
+		 /* Scenario 4.0	PING_PONG+ IRQ TO MCU */
+		switch (time10us) {
+		case 1:
+			/* check HW config and OPP config */
+			abe_read_hardware_configuration(UC5, &OPP,	&CONFIG);
+			/* sets the OPP100 on FW05.xx */
+			abe_set_opp_processing(OPP);
+			/* "tick" of the audio engine */
+			abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);
+
+			/* MM_DL INIT (overwrite the previous default initialization made above  */
+			format.f = 48000;
+			format.samp_format = STEREO_16_16;
+
+			/* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */
+			abe_add_subroutine(&abe_irq_pingpong_player_id,
+				(abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0);
+
+			#define N_SAMPLES_BYTES (24 *4)		  // @@@@ to be tuned
+			abe_connect_irq_ping_pong_port(MM_DL_PORT, &format,
+				abe_irq_pingpong_player_id, N_SAMPLES_BYTES, &data_sink, PING_PONG_WITH_MCU_IRQ);
+
+			abe_write_mixer(MIXDL1,	GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_TONES);
+			abe_write_mixer(MIXDL1,	GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+			abe_write_mixer(MIXDL1,	GAIN_0dB,  RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+			abe_write_mixer(MIXDL1,	GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_UL2);
+			abe_write_mixer(MIXDL2,	GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_TONES);
+			abe_write_mixer(MIXDL2,	GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+			abe_write_mixer(MIXDL2,	GAIN_0dB,  RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+			abe_write_mixer(MIXDL2,	GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_MM_UL2);
+
+			abe_write_mixer(MIXSDT,	GAIN_0dB,  RAMP_0MS, MIX_SDT_INPUT_UP_MIXER);
+			abe_write_mixer(MIXSDT,	MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER);
+
+			/* enable all the data paths */
+			abe_enable_data_transfer(MM_DL_PORT);
+			abe_enable_data_transfer(PDM_DL_PORT);
+			break;
+		case 1200:
+			abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1,
+				(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]);
+			break;
+		case 2400:		// end
+			fcloseall();
+			exit(-4);
+		}
+	 /* case scenario_id ==4 */
+	break;
+	case 41:
+		/* Scenario 4.1   PING_PONG+ IRQ TO MCU 32BITS */
+		switch (time10us) {
+		case 1:
+			/* check HW config and OPP config */
+			abe_read_hardware_configuration(UC5, &OPP, &CONFIG);
+			/* sets the OPP100 on FW05.xx */
+			abe_set_opp_processing(OPP);
+			/* "tick" of the audio engine */
+			abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);
+
+			/* MM_DL INIT(overwrite the previous default initialization made above	*/
+			format.f = 48000;
+			format.samp_format = STEREO_MSB;
+
+			/* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */
+			abe_add_subroutine(&abe_irq_pingpong_player_id,
+				(abe_subroutine2) abe_default_irq_pingpong_player_32bits, SUB_0_PARAM, (abe_uint32*)0);
+
+			#define N_SAMPLES_BYTES (24 * 4)	   // @@@@ to be tuned
+			abe_connect_irq_ping_pong_port(MM_DL_PORT, &format,
+				abe_irq_pingpong_player_id, N_SAMPLES_BYTES, &data_sink, PING_PONG_WITH_MCU_IRQ);
+
+			abe_write_mixer(MIXDL1,	MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES);
+			abe_write_mixer(MIXDL1,	MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_VX_DL);
+			abe_write_mixer(MIXDL1,	GAIN_0dB,  RAMP_0MS, MIX_DL1_INPUT_MM_DL);
+			abe_write_mixer(MIXDL1,	MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2);
+
+			abe_write_mixer(MIXDL2,	MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES);
+			abe_write_mixer(MIXDL2,	MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_VX_DL);
+			abe_write_mixer(MIXDL2,	GAIN_0dB,  RAMP_0MS, MIX_DL2_INPUT_MM_DL);
+			abe_write_mixer(MIXDL2,	MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2);
+
+			abe_write_mixer(MIXSDT,	GAIN_0dB,  RAMP_0MS, MIX_SDT_INPUT_UP_MIXER);
+			abe_write_mixer(MIXSDT,	MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER);
+
+			/* enable all the data paths */
+			abe_enable_data_transfer(MM_DL_PORT );
+			abe_enable_data_transfer(PDM_DL_PORT);
+
+			break;
+		case 1200:
+			abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1,
+				(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]);
+			break;
+
+		case 2400:		// end
+			fcloseall();
+			exit(-4);
+		}
+	 /* case scenario_id ==4 */
+	break;
+
+	case 5:
+		/* Scenario 5	  CHECK APS ADAPTATION ALGO */
+		switch (time10us) {
+		case 1:
+			/* check HW config and OPP config */
+			abe_read_hardware_configuration(UC5, &OPP,	&CONFIG);
+			/* sets the OPP100 on FW05.xx */
+			abe_set_opp_processing(OPP);
+			/* "tick" of the audio engine */
+			abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION);
+
+			/* MM_DL INIT(overwrite the previous default initialization made above	*/
+			format.f = 48000;
+			format.samp_format = STEREO_16_16;
+
+			/* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */
+			abe_add_subroutine(&abe_irq_pingpong_player_id,
+				(abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0);
+
+			#define N_SAMPLES_BYTES (24 *4)		  // @@@@ to be tuned
+			abe_connect_irq_ping_pong_port(MM_DL_PORT,
+				&format, abe_irq_pingpong_player_id, N_SAMPLES_BYTES,
+							&data_sink, PING_PONG_WITH_MCU_IRQ);
+
+			/* mixers' configuration = voice on earphone + music on hands-free path */
+			abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL);
+			abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL);
+
+			/* enable all the data paths */
+			abe_enable_data_transfer(MM_DL_PORT);
+			abe_enable_data_transfer(PDM_DL_PORT);
+
+			/* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */
+			abe_add_subroutine(&abe_irq_aps_adaptation_id,
+			(abe_subroutine2) abe_default_irq_aps_adaptation, SUB_0_PARAM, (abe_uint32*)0);
+			break;
+		} /* case scenario_id ==5 */
+
+	abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC,
+			(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]);
+	abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1,
+			(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]);
+	abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC2,
+			(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC2]);
+	abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC3,
+			(abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC3]);
+	case UC31_VOICE_CALL_8KMONO:
+		abe_disable_data_transfer(VX_DL_PORT);
+		abe_disable_data_transfer(VX_UL_PORT);
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+		format.f = 8000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+		abe_enable_data_transfer(VX_DL_PORT);
+		abe_enable_data_transfer(VX_UL_PORT);
+	case UC32_VOICE_CALL_8KSTEREO:
+		format.f = 8000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+		format.f = 8000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+	case UC33_VOICE_CALL_16KMONO:
+		format.f = 16000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+		format.f = 16000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+	case UC34_VOICE_CALL_16KSTEREO:
+		format.f = 16000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink);
+		format.f = 16000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink);
+	case UC35_MMDL_MONO:
+		format.f = 48000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink);
+	case UC36_MMDL_STEREO:
+		format.f = 48000;
+		format.samp_format = STEREO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink);
+	case UC37_MMUL2_MONO:
+		format.f = 48000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink);
+	case UC38_MMUL2_STEREO:
+		format.f = 48000;
+		format.samp_format = MONO_MSB;
+		abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink);
+	case UC91_ASRC_DRIFT1:
+		abe_set_asrc_drift_control(VX_UL_PORT, FORCED_DRIFT_CONTROL);
+		abe_write_asrc(VX_UL_PORT, 100);
+		abe_set_asrc_drift_control(VX_DL_PORT, FORCED_DRIFT_CONTROL);
+		abe_write_asrc(VX_DL_PORT, 200);
+		abe_set_asrc_drift_control(MM_DL_PORT, FORCED_DRIFT_CONTROL);
+		abe_write_asrc(MM_DL_PORT, 300);
+	case UC92_ASRC_DRIFT2:
+		abe_set_asrc_drift_control(VX_UL_PORT, FORCED_DRIFT_CONTROL);
+		abe_write_asrc(VX_UL_PORT, -100);
+		abe_set_asrc_drift_control(VX_DL_PORT, FORCED_DRIFT_CONTROL);
+		abe_write_asrc(VX_DL_PORT, -200);
+		abe_set_asrc_drift_control(MM_DL_PORT, FORCED_DRIFT_CONTROL);
+		abe_write_asrc(MM_DL_PORT, -300);
+#endif
diff --git a/sound/soc/codecs/abe/abe_test.h b/sound/soc/codecs/abe/abe_test.h
new file mode 100644
index 000000000000..b84ee3dafcde
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_test.h
@@ -0,0 +1,28 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_TEST_H_
+#define _ABE_TEST_H_
+
+/*
+ * HAL test API
+ */
+void abe_auto_check_data_format_translation(void);
+void abe_check_opp(void);
+void abe_check_dma(void);
+void abe_debug_and_non_regression(void);
+void abe_check_mixers_gain_update(void);
+void abe_test_scenario(abe_int32 scenario_id);
+
+/*
+ * HAL test DATA
+ */
+
+#endif	/* _ABE_TEST_H_ */
diff --git a/sound/soc/codecs/abe/abe_typ.h b/sound/soc/codecs/abe/abe_typ.h
new file mode 100644
index 000000000000..73c45ae3ed9a
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_typ.h
@@ -0,0 +1,661 @@
+/*
+ * ==========================================================================
+ *               Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
+ *
+ *  Use of this firmware is controlled by the terms and conditions found
+ *  in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#include "abe_def.h"
+#include "abe_ext.h"
+#ifndef _ABE_TYP_H_
+#define _ABE_TYP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * BASIC TYPES
+ */
+
+typedef char	    abe_flag;
+typedef unsigned char   abe_uint8;
+typedef char	    abe_int8;
+typedef unsigned short  abe_uint16;
+typedef short	   abe_int16;
+typedef unsigned long   abe_uint32;
+typedef long	    abe_int32;
+typedef float	   abe_float;
+typedef double	  abe_double;
+
+typedef abe_uint32 abe_errc_t;
+typedef abe_int32  abe_millibel;
+
+//typedef abe_uint32  abe_millisecond;
+//typedef abe_uint32  abe_milliHertz;
+//typedef abe_uint32  abe_millimeter;
+//typedef abe_uint32  abe_millidegree;
+//typedef abe_uint32  abe_permille;
+//typedef abe_uint32  abe_microsecond;
+
+typedef abe_uint32  abe_result;
+typedef abe_millibel abe_gain_t;	/* smoothed gain amplitude and ramp */
+typedef abe_uint32  abe_ramp_t;
+
+typedef abe_uint32  abe_freq_t;		 /* 4 bytes	millihertz	      */
+typedef abe_uint32  abe_millis_t;	       /* 4 bytes	milliseconds	    */
+typedef abe_uint32  abe_micros_t;	       /* 4 bytes	microseconds	    */
+
+typedef abe_uint32  abe_dbg_mask_t;	     /* 4 bytes	Bit field indicating the type of informations to be traced */
+typedef abe_uint32  abe_time_stamp_t;	   /* 4 bytes	infinite loop 32bits counter incremented on each firmware loop */
+						/* scheduling task loops (250us / 272us with respectively 48kHz / 44.1kHz on Phoenix). */
+typedef abe_uint32   abe_dbg_t;		 /* debug filter */
+
+typedef abe_uint32  abe_seq_code_t;	     /* Index to the table of sequences */
+typedef abe_uint32  abe_sub_code_t;	     /* Index to the table of subroutines called in the sequence */
+
+typedef void (* abe_subroutine0)(void);					    /* subroutine with no parameter */
+typedef void (* abe_subroutine1)(abe_uint32);				      /* subroutine with one parameter */
+typedef void (* abe_subroutine2)(abe_uint32, abe_uint32);			  /* subroutine with two parameters */
+typedef void (* abe_subroutine3)(abe_uint32, abe_uint32, abe_uint32);	      /* subroutine with three parameters */
+typedef void (* abe_subroutine4)(abe_uint32, abe_uint32, abe_uint32, abe_uint32);  /* subroutine with four parameters */
+
+/*
+ *      CODE PORTABILITY - FUTURE PATCHES
+ *
+ *      32bits field for having the code compatible with future revisions of the hardware (audio integration)
+ *      or evolution of the software partitionning. Used for the highest level APIs (launch_sequences)
+ */
+typedef abe_uint32 abe_patch_rev;
+
+/*
+ * ENUMS
+ */
+
+/*
+ *      MEMORY CONFIG TYPE
+ *
+ *	 0: Ultra Lowest power consumption audio player
+ *	 1: OPP 25% (simple multimedia features)
+ *	 2: OPP 50% (multimedia and voice calls)
+ *	 3: OPP100% (EANC, multimedia complex use-cases)
+ */
+typedef enum {
+	ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE = 1,
+	ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER,
+	ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL,
+	ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT,
+	ABE_MULTIMEDIA_AUDIO_RECORDER,
+	ABE_VIBRATOR_OR_HAPTICS,
+	ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER,
+	ABE_RINGER_TONES,
+	ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER,
+
+	ABE_LAST_USE_CASE
+} abe_use_case_id;
+
+/*
+ *      OPP TYPE
+ *
+ *	 0: Ultra Lowest power consumption audio player
+ *	 1: OPP 25% (simple multimedia features)
+ *	 2: OPP 50% (multimedia and voice calls)
+ *	 3: OPP100% (EANC, multimedia complex use-cases)
+ */
+typedef enum {
+	ABE_OPP0 = 0,
+	ABE_OPP25, ABE_OPP50, ABE_OPP100
+} abe_opp_t;
+
+/*
+ *      IIR TYPE
+ *
+ *	 0: Ultra Lowest power consumption audio player
+ *	 1: OPP 25% (simple multimedia features)
+ */
+typedef enum {
+	ABE_IIR_TYPE_1 = 0,
+	ABE_IIR_TYPE_2
+} abe_iir_t;
+
+/*
+ *      DMIC DECIMATION RATIO
+ *
+ */
+typedef enum {
+	ABE_DEC16 = 16,
+	ABE_DEC25 = 25,
+	ABE_DEC32 = 32,
+	ABE_DEC40 = 40
+} abe_dmic_ratio_t;
+
+/*
+ *      SAMPLES TYPE
+ *
+ *	mono 16bits sample LSB aligned, 16 MSB bits are unused
+ *	mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP TX purpose.
+ *	mono sample MSB aligned (16/24/32bits)
+ *      two successive mono samples in one 32bits container
+ *	Two L/R 16bits samples in a 32bits container,
+ *	Two channels defined with two MSB aligned samples
+ *	Three channels defined with three MSB aligned samples (MIC)
+ *	Four channels defined with four MSB aligned samples (MIC)
+ *      . . .
+ *	Eight channels defined with six MSB aligned samples (MIC)
+ */
+typedef enum {
+	MONO_MSB = 1,
+	MONO_RSHIFTED_16, STEREO_RSHIFTED_16,  /* only used for McBSP_TX */
+	STEREO_16_16,
+	STEREO_MSB, THREE_MSB, FOUR_MSB, FIVE_MSB, SIX_MSB, SEVEN_MSB, EIGHT_MSB, NINE_MSB, TEN_MSB,
+} abe_samp_t;
+
+/*
+ *      PORT PROTOCOL TYPE
+ */
+typedef enum {
+	SLIMBUS_PORT_PROT = 1,
+	SERIAL_PORT_PROT,
+	DMIC_PORT_PROT,
+	MCPDMDL_PORT_PROT,
+	MCPDMUL_PORT_PROT,
+	PINGPONG_PORT_PROT,
+	DMAREQ_PORT_PROT,
+	FIFO_PORT_PROT,
+} abe_port_protocol_switch_id;
+
+/*
+ * PORT IDs, this list is aligned with the FW data mapping
+ */
+typedef enum {
+	DMIC_PORT = 0,
+	PDM_UL_PORT,	    /* analog MICs */
+	BT_VX_UL_PORT,	  /* BT uplink (8/16 kHz)*/
+
+	/* AE source ports - Uplink */
+	MM_UL_PORT,	     /* up to 5 stereo channels */
+	MM_UL2_PORT,	    /* stereo FM record path (4) */
+	VX_UL_PORT,	     /* stereo FM record path */
+
+	/* AE sink ports - Downlink */
+	MM_DL_PORT,	     /* multimedia player audio path */
+	VX_DL_PORT,
+	TONES_DL_PORT, /* 8 */
+	VIB_DL_PORT,
+
+	/* AE source ports - Downlink */
+	BT_VX_DL_PORT,
+	PDM_DL_PORT,	/* ABE --> BT (8/16kHz) */
+	MM_EXT_OUT_PORT, /* 12 */
+	MM_EXT_IN_PORT,
+
+	LAST_PORT_ID /* dummy port used to declare the other tasks of the scheduler */
+} abe_port_id;
+
+/*
+ * Definition for the compatibility with HAL05xx
+ */
+#define PDM_DL1_PORT PDM_DL_PORT
+#define PDM_DL2_PORT PDM_DL_PORT
+#define PDM_VIB_PORT PDM_DL_PORT
+#define DMIC_PORT1 DMIC_PORT
+#define DMIC_PORT2 DMIC_PORT
+#define DMIC_PORT3 DMIC_PORT
+
+/*
+ *      ANA_PORT_ID     Analog companion audio port
+ */
+typedef enum {
+	EAR_PHOENIX = 1,
+	HS_L,   HS_R,
+	IHF_L,  IHF_R,
+	VIBRA1, VIBRA2
+} abe_ana_port_id ;
+
+typedef abe_int32 headset_offset_t;   /* Calibration data from the analog companion */
+
+/*
+ *      Signal processing module names - EQ APS MIX ROUT
+ */
+#define FEAT_EQ1	1		/* equalizer downlink path headset + earphone */
+#define FEAT_EQ2L	FEAT_EQ1+1	/* equalizer downlink path integrated handsfree LEFT */
+#define FEAT_EQ2R	FEAT_EQ2L+1	/* equalizer downlink path integrated handsfree RIGHT */
+#define FEAT_EQSDT	FEAT_EQ2R+1	/* equalizer downlink path side-tone */
+#define FEAT_EQMIC	FEAT_EQSDT+1	/* equalizer uplink path first DMIC pair */
+#define FEAT_APS1	FEAT_EQMIC+1	/* Acoustic protection for headset */
+#define FEAT_APS2	FEAT_APS1+1	/* acoustic protection high-pass filter for handsfree "Left" */
+#define FEAT_APS3	FEAT_APS2+1	/* acoustic protection high-pass filter for handsfree "Right" */
+#define FEAT_ASRC1	FEAT_APS3+1	/* asynchronous sample-rate-converter for the downlink voice path */
+#define FEAT_ASRC2	FEAT_ASRC1+1	/* asynchronous sample-rate-converter for the uplink voice path */
+#define FEAT_ASRC3	FEAT_ASRC2+1	/* asynchronous sample-rate-converter for the multimedia player */
+#define FEAT_ASRC4	FEAT_ASRC3+1	/* asynchronous sample-rate-converter for the echo reference */
+#define FEAT_MIXDL1	FEAT_ASRC4+1	/* mixer of the headset and earphone path */
+#define FEAT_MIXDL2	FEAT_MIXDL1+1	/* mixer of the hands-free path */
+#define FEAT_MIXAUDUL	FEAT_MIXDL2+1	/* mixer for audio being sent on the voice_ul path */
+#define FEAT_MIXVXREC	FEAT_MIXAUDUL+1	/* mixer for voice communication recording */
+#define FEAT_MIXSDT	FEAT_MIXVXREC+1	/* mixer for side-tone */
+#define FEAT_MIXECHO	FEAT_MIXSDT+1	/* mixer for echo reference */
+#define FEAT_UPROUTE	FEAT_MIXECHO+1	/* router of the uplink path */
+#define FEAT_GAINS	FEAT_UPROUTE+1	/* all gains */
+#define FEAT_GAINS_DMIC1 FEAT_GAINS+1
+#define FEAT_GAINS_DMIC2 FEAT_GAINS_DMIC1+1
+#define FEAT_GAINS_DMIC3 FEAT_GAINS_DMIC2+1
+#define FEAT_GAINS_AMIC FEAT_GAINS_DMIC3+1
+#define FEAT_GAINS_SPLIT	FEAT_GAINS_AMIC+1
+#define FEAT_GAINS_DL1	FEAT_GAINS_SPLIT+1
+#define FEAT_GAINS_DL2	FEAT_GAINS_DL1+1
+#define FEAT_GAIN_EANC	FEAT_GAINS_DL2+1 /* active noise canceller */
+#define FEAT_SEQ	FEAT_GAIN_EANC+1	/* sequencing queue of micro tasks */
+#define FEAT_CTL	FEAT_SEQ+1	/* Phoenix control queue through McPDM */
+
+#define MAXNBFEATURE	FEAT_CTL	/* list of features of the firmware */
+
+typedef enum {
+	EQ1 =   FEAT_EQ1,	/* equalizer downlink path headset + earphone */
+	EQ2L =  FEAT_EQ2L,	/* equalizer downlink path integrated handsfree LEFT */
+	EQ2R =  FEAT_EQ2R,
+	EQSDT = FEAT_EQSDT,	/* equalizer downlink path side-tone */
+	EQMIC = FEAT_EQMIC,
+} abe_equ_id;
+
+typedef enum {
+	APS1 = FEAT_APS1,	/* Acoustic protection for headset */
+	APS2L = FEAT_APS2,
+	APS2R = FEAT_APS3
+} abe_aps_id;
+
+typedef enum {
+	ASRC1 = FEAT_ASRC1,	/* asynchronous sample-rate-converter for the downlink voice path */
+	ASRC2 = FEAT_ASRC2,	/* asynchronous sample-rate-converter for the uplink voice path */
+	ASRC3 = FEAT_ASRC3,	/* asynchronous sample-rate-converter for the multimedia player */
+	ASRC4 = FEAT_ASRC4,	/* asynchronous sample-rate-converter for the voice uplink echo_reference */
+} abe_asrc_id;
+
+typedef enum {
+	MIXDL1 = FEAT_MIXDL1,
+	MIXDL2 = FEAT_MIXDL2,
+	MIXSDT = FEAT_MIXSDT,
+	MIXECHO = FEAT_MIXECHO,
+	MIXEANC = FEAT_GAIN_EANC,
+	MIXAUDUL = FEAT_MIXAUDUL,
+	MIXVXREC = FEAT_MIXVXREC,
+} abe_mixer_id;
+
+typedef enum {
+	UPROUTE = FEAT_UPROUTE,	/* there is only one router up to now */
+} abe_router_id;
+
+typedef enum {
+	GAINS = FEAT_GAINS,	/* Misc tasks of the scheduler */
+	SEQUENCE = FEAT_SEQ,
+	CONTROL = FEAT_CTL
+} abe_schd_id;
+
+/*
+ * GAIN IDs
+ */
+typedef enum {
+	GAINS_DMIC1 = FEAT_GAINS_DMIC1,
+	GAINS_DMIC2 = FEAT_GAINS_DMIC2,
+	GAINS_DMIC3 = FEAT_GAINS_DMIC3,
+	GAINS_AMIC = FEAT_GAINS_AMIC,
+	GAINS_SPLIT = FEAT_GAINS_SPLIT,
+	GAINS_DL1 = FEAT_GAINS_DL1,
+	GAINS_DL2 = FEAT_GAINS_DL2,
+	GAINS_EANC = FEAT_GAIN_EANC,
+} abe_gain_id;
+
+#if 0
+typedef enum {
+	VX_DL_IN_GAIN = 1,	/* mixer's gain */
+	MM_DL_IN_GAIN,
+	TONES_DL_IN_GAIN,
+	MM_VX_DL_IN_GAIN,
+	MM_IHF_DL_IN_GAIN,	/* mixer's gain */
+	MM_HS_DL_OUT_GAIN,	/* Output Left gain */
+	MM_IHF_L_DL_OUT_GAIN,	/* Output Left gain */
+	MM_IHF_R_DL_OUT_GAIN,	/* Output Right gain */
+	MM_VIB1_DL_GAIN,
+	MM_VIB2_DL_GAIN,	/* no gain in fact */
+	DMIC_UL_IN_GAIN_0,
+	DMIC_UL_IN_GAIN_1,	/* today = same GAIN on DMIC pairs */
+	DMIC_UL_IN_GAIN_2,
+	DMIC_UL_IN_GAIN_3,
+	DMIC_UL_IN_GAIN_4,
+	DMIC_UL_IN_GAIN_5,
+	AMIC_UL_IN_GAIN_L,
+	AMIC_UL_IN_GAIN_R,	/* today = same gain on AMIC pair */
+	ECHO_REF_GAIN,
+	BT_VX_DL_OUT_GAIN,
+	BT_VX_UL_IN_GAIN,
+} abe_gain_id;
+#endif
+
+/*
+ * EVENT GENERATORS
+ */
+typedef enum {
+	EVENT_MCPDM = 1,
+	EVENT_DMIC, EVENT_TIMER,
+	EVENT_McBSP, EVENT_McASP, EVENT_SLIMBUS, EVENT_44100, EVENT_DEFAULT,
+} abe_event_id;
+
+/*
+ * SERIAL PORTS IDs
+ */
+typedef enum {
+	MCBSP1_TX = MCBSP1_DMA_TX,
+	MCBSP1_RX = MCBSP1_DMA_RX,
+	MCBSP2_TX = MCBSP2_DMA_TX,
+	MCBSP2_RX = MCBSP2_DMA_RX,
+	MCBSP3_TX = MCBSP3_DMA_TX,
+	MCBSP3_RX = MCBSP3_DMA_RX,
+} abe_mcbsp_id;
+
+
+/*
+ * TYPES USED FOR APIS
+ */
+
+/*
+ * HARDWARE CONFIG TYPE
+ */
+typedef struct {
+	abe_uint32 AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE; /* EVENT_GENERATOR_COUNTER_DEFAULT gives about 96kHz */
+	abe_uint32 AESS_EVENT_SOURCE_SELECTION__SELECTION; /* 0: DMAreq, 1:Counter */
+	abe_uint32 AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION; /* 5bits DMAreq selection */
+	abe_event_id HAL_EVENT_SELECTION;
+
+	abe_uint32 MCPDM_CTRL__DIV_SEL;	 /* 0: 96kHz   1:192kHz */
+	abe_uint32 MCPDM_CTRL__CMD_INT;	 /* 0: no command in the FIFO,  1: 6 data on each lines (with commands) */
+	abe_uint32 MCPDM_CTRL__PDMOUTFORMAT;    /* 0:MSB aligned  1:LSB aligned */
+	abe_uint32 MCPDM_CTRL__PDM_DN5_EN;
+	abe_uint32 MCPDM_CTRL__PDM_DN4_EN;
+	abe_uint32 MCPDM_CTRL__PDM_DN3_EN;
+	abe_uint32 MCPDM_CTRL__PDM_DN2_EN;
+	abe_uint32 MCPDM_CTRL__PDM_DN1_EN;
+	abe_uint32 MCPDM_CTRL__PDM_UP3_EN;
+	abe_uint32 MCPDM_CTRL__PDM_UP2_EN;
+	abe_uint32 MCPDM_CTRL__PDM_UP1_EN;
+	abe_uint32 MCPDM_FIFO_CTRL_DN__DN_TRESH;
+	abe_uint32 MCPDM_FIFO_CTRL_UP__UP_TRESH;
+
+	abe_uint32 DMIC_CTRL__DMIC_CLK_DIV;     /* 0:2.4MHz  1:3.84MHz */
+	abe_uint32 DMIC_CTRL__DMICOUTFORMAT;    /* 0:MSB aligned  1:LSB aligned */
+	abe_uint32 DMIC_CTRL__DMIC_UP3_EN;
+	abe_uint32 DMIC_CTRL__DMIC_UP2_EN;
+	abe_uint32 DMIC_CTRL__DMIC_UP1_EN;
+	abe_uint32 DMIC_FIFO_CTRL__DMIC_TRESH;  /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */
+
+	abe_uint32 MCBSP_SPCR1_REG__RJUST;      /* 1:MSB  2:LSB aligned */
+	abe_uint32 MCBSP_THRSH2_REG_REG__XTHRESHOLD;
+	abe_uint32 MCBSP_THRSH1_REG_REG__RTHRESHOLD;
+} abe_hw_config_init_t;
+
+/*
+ * EANC_T
+ *
+ * TBD : coefficients of the EANC
+ */
+typedef struct {
+	abe_int32 dmic_index;
+	abe_int32 fir_coef[NBEANC1];
+	abe_int32 lambda;
+	abe_int32 iir_filter[NBEANC2];
+	abe_int32 loop_gain;
+} abe_eanc_t;
+
+/*
+ * EQU_T
+ *
+ * coefficients of the equalizer
+ */
+typedef struct {
+	abe_iir_t equ_type;	/* type of filter */
+	abe_uint32 equ_length;	/* filter length */
+	union {			/* parameters are the direct and recursive coefficients in */
+	       abe_int32 type1[NBEQ1];		/* Q6.26 integer fixed-point format. */
+	       struct {
+			abe_int32 freq [NBEQ2];		/* center frequency of the band [Hz] */
+			abe_int32 gain [NBEQ2];		/* gain of each band. [dB]*/
+			abe_int32 q    [NBEQ2];		/* Q factor of this band [dB] */
+	       } type2;
+	} coef;
+	abe_int32 equ_param3;
+} abe_equ_t;
+
+/*
+ * APS_T
+ *
+ * coefficients of the Acoustics Protection and Safety
+ */
+typedef struct {
+	abe_int32 coef1[NBAPS1];
+	abe_int32 coef2[NBAPS2];
+} abe_aps_t;
+
+typedef struct {
+		abe_millibel e1;	/* structure of two energy_t estimation for coil and membrane */
+		abe_millibel e2;
+} abe_aps_energy_t;
+
+/*
+ * ROUTER_T
+ *
+ * table of indexes in unsigned bytes
+ */
+typedef abe_uint32 abe_router_t;
+
+/*
+ * DATA_FORMAT_T
+ *
+ * used in port declaration
+ */
+typedef struct {
+	abe_freq_t f;	       /* Sampling frequency of the stream */
+	abe_samp_t samp_format;     /* Sample format type  */
+} abe_data_format_t;
+
+/*
+ * PORT_PROTOCOL_T
+ *
+ * port declaration
+ */
+typedef struct {
+	abe_uint32 direction;		       /* Direction=0 means input from AESS point of view */
+	abe_port_protocol_switch_id protocol_switch; /* Protocol type (switch) during the data transfers */
+	union {
+		struct {			/* Slimbus peripheral connected to ATC */
+			abe_uint32 desc_addr1;	/* Address of ATC Slimbus descriptor's index */
+			abe_uint32 desc_addr2;	/* Second ATC index for SlimBus reception (or NULL) */
+			abe_uint32 buf_addr1;	/* DMEM address 1 in bytes */
+			abe_uint32 buf_addr2;	/* DMEM address 2 in bytes */
+			abe_uint32 buf_size;	/* DMEM buffer size size in bytes */
+			abe_uint32 iter;	/* ITERation on each DMAreq signals */
+		} prot_slimbus;
+
+		struct {
+			abe_uint32 desc_addr;	/* McBSP/McASP peripheral connected to ATC */
+			abe_uint32 buf_addr;	/* Address of ATC McBSP/McASP descriptor's in bytes */
+			abe_uint32 buf_size;	/* DMEM address in bytes */
+			abe_uint32 iter;	/* ITERation on each DMAreq signals */
+		} prot_serial;
+
+		struct {			/* DMIC peripheral connected to ATC */
+			abe_uint32 buf_addr;	/* DMEM address in bytes */
+			abe_uint32 buf_size;	/* DMEM buffer size in bytes */
+			abe_uint32 nbchan;	/* Number of activated DMIC */
+		} prot_dmic;
+
+		struct {			/* McPDMDL peripheral connected to ATC */
+			abe_uint32 buf_addr;	/* DMEM address in bytes */
+			abe_uint32 buf_size;	/* DMEM size in bytes */
+			abe_uint32 control;	/* Control allowed on McPDM DL */
+		} prot_mcpdmdl;
+
+		struct {			/* McPDMUL peripheral connected to ATC */
+			abe_uint32 buf_addr;	/* DMEM address size in bytes */
+			abe_uint32 buf_size;	/* DMEM buffer size size in bytes */
+		} prot_mcpdmul;
+
+		struct {			/* Ping-Pong interface to the Host using cache-flush */
+			abe_uint32 desc_addr;	/* Address of ATC descriptor's */
+			abe_uint32 buf_addr;	/* DMEM buffer base address in bytes */
+			abe_uint32 buf_size;	/* DMEM size in bytes for each ping and pong buffers */
+			abe_uint32 irq_addr;	/* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
+			abe_uint32 irq_data;	/* IRQ data content loaded in the AESS IRQ register */
+			abe_uint32 callback;	/* Call-back function upon IRQ reception */
+		} prot_pingpong;
+
+		struct {			/* DMAreq line to CBPr */
+			abe_uint32 desc_addr;   /* Address of ATC descriptor's */
+			abe_uint32 buf_addr;	/* DMEM buffer address in bytes */
+			abe_uint32 buf_size;	/* DMEM buffer size size in bytes */
+			abe_uint32 iter;	/* ITERation on each DMAreq signals */
+			abe_uint32 dma_addr;	/* DMAreq address */
+			abe_uint32 dma_data;	/* DMA/AESS = 1 << #DMA */
+		} prot_dmareq;
+
+		struct {			/* Circular buffer - direct addressing to DMEM */
+			abe_uint32 buf_addr;	/* DMEM buffer base address in bytes */
+			abe_uint32 buf_size;	/* DMEM buffer size in bytes */
+			abe_uint32 dma_addr;	/* DMAreq address */
+			abe_uint32 dma_data;	/* DMA/AESS = 1 << #DMA */
+		} prot_circular_buffer;
+	}p;
+} abe_port_protocol_t;
+
+/*
+ * DMA_T
+ *
+ * dma structure for easing programming
+ */
+typedef struct {
+	void *data;		/* OCP L3 pointer to the first address of the */
+				/* destination buffer (either DMA or Ping-Pong read/write pointers). */
+	void *l3_dmem;		/* address L3 when addressing the DMEM buffer instead of CBPr */
+	void *l4_dmem;		/* address L3 translated to L4 the ARM memory space */
+	abe_uint32 iter;	/* number of iterations for the DMA data moves. */
+} abe_dma_t;
+
+typedef struct {
+	abe_uint32 data;	/* Offset to the first address of the */
+	abe_uint32 iter;	/* number of iterations for the DMA data moves. */
+} abe_dma_t_offset;
+
+/*
+ *  SEQ_T
+ *
+ *      struct {
+ *      micros_t time;	  Waiting time before executing next line
+ *      seq_code_t code	 Subroutine index interpreted in the HAL and translated to
+ *				FW subroutine codes in case of ABE tasks
+ *      int32 param[2]	  Two parameters
+ *      } seq_t
+ *
+ */
+typedef struct {
+	abe_micros_t delta_time;
+	abe_sub_code_t code;
+	abe_uint32 param[4];
+	abe_uint8  tag;
+} abe_seq_t;
+
+typedef struct {
+	abe_uint32 mask;
+	abe_seq_t seq1;
+	abe_seq_t seq2;
+} abe_sequence_t;
+
+/*
+ * DRIFT_T
+ *
+ * ASRC drift parameter in [ppm] value
+ */
+typedef abe_int32 abe_drift_t;
+
+/*
+ * INTERNAL DATA TYPES
+ */
+
+/*
+ * ABE_IRQ_DATA_T
+ *
+ * IRQ FIFO content declaration
+ * APS interrupts:
+ * 	IRQtag_APS to [31:28], APS_IRQs to [27:16], loopCounter to [15:0]
+ * SEQ interrupts:
+ * 	 IRQtag_COUNT to [31:28], Count_IRQs to [27:16], loopCounter to [15:0]
+ * Ping-Pong Interrupts:
+ * 	 IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], loopCounter to [15:0]
+ */
+typedef struct {
+	unsigned int counter: 16;
+	unsigned int data: 12;
+	unsigned int tag: 4;
+} abe_irq_data_t;
+
+/*
+ * ABE_PORT_T status / format / sampling / protocol(call_back) / features / gain / name ..
+ *
+ */
+typedef struct {
+	abe_uint16  status;			/* running / idled */
+	abe_data_format_t format;		/* Sample format type  */
+	abe_drift_t drift;			/* API : for ASRC */
+	abe_uint16 callback;			/* optionnal call-back index for errors and ack */
+	abe_uint16 smem_buffer1;		/* IO tasks buffers */
+	abe_uint16 smem_buffer2;
+	abe_port_protocol_t protocol;
+	abe_dma_t_offset dma;			/* pointer and iteration counter of the xDMA */
+	abe_uint16 feature_index [MAXFEATUREPORT]; /* list of features associated to a port (EQ, APS, ... , ends with 0) */
+	 // abe_millibel gain_calibration;	/* gain tuning, default=0dB */
+	char name[NBCHARPORTNAME];
+} abe_port_t;
+
+/*
+ * ABE_SUBROUTINE_T
+ *
+ */
+typedef struct {
+	abe_uint32 sub_id;
+	abe_int32 param[4];
+} abe_subroutine_t;
+
+/*
+ * ABE_PORT_INFO_T
+ *
+ * OPP, subroutines to call on reset
+ */
+typedef struct {
+	abe_opp_t  min_opp;
+	abe_subroutine_t sub1;
+	abe_subroutine_t sub2;
+} abe_port_info_t;
+
+/*
+ * ABE_FEATURE_T
+ *
+ */
+typedef struct {
+	abe_uint16 enable_with_default_data;
+	abe_uint16 disable_feature;
+	abe_uint16 read_parameter;
+	abe_uint16 write_parameter;
+	abe_uint16 running_status;
+	abe_uint16 fw_input_buffer_address;
+	abe_uint16 fw_output_buffer_address;
+	abe_uint16 fw_scheduler_slot_position;
+	abe_uint16 fw_scheduler_subslot_position;
+	abe_opp_t  min_opp;
+	char name[NBCHARFEATURENAME];
+} abe_feature_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _ABE_TYP_H_ */
diff --git a/sound/soc/codecs/abe/abe_typedef.h b/sound/soc/codecs/abe/abe_typedef.h
new file mode 100644
index 000000000000..a3877ddbd936
--- /dev/null
+++ b/sound/soc/codecs/abe/abe_typedef.h
@@ -0,0 +1,187 @@
+/*
+ * ==========================================================================
+ *		 Texas Instruments OMAP(TM) Platform Firmware
+ * (c) Copyright 2009, Texas Instruments Incorporated.	All Rights Reserved.
+ *
+ *	Use of this firmware is controlled by the terms and conditions found
+ *	in the license agreement under which this firmware has been supplied.
+ * ==========================================================================
+ */
+
+#ifndef _ABE_TYPEDEF_H_
+#define _ABE_TYPEDEF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "abe_define.h"
+
+/*
+ * Basic types definition
+*/
+typedef unsigned char ABE_uchar;
+typedef char ABE_char;
+typedef unsigned short ABE_uint16;
+typedef short ABE_int16;
+typedef long ABE_int32;
+typedef unsigned long ABE_uint32;
+
+typedef ABE_uchar* pABE_uchar;
+typedef ABE_char* pABE_char;
+typedef ABE_uint16* pABE_uint16;
+typedef ABE_int16* pABE_int16;
+typedef ABE_int32* pABE_int32;
+typedef ABE_uint32* pABE_uint32;
+
+/*
+ * Hard-coded data generated in the XLS sheet (to be removed later@@@@)
+ */
+#ifdef __chess__
+typedef struct abeatcdescTag {
+	unsigned long a;
+	unsigned long b;
+} ABE_SAtcDescriptor;
+typedef void (*pABE_voidFunction)()clobbers(R0, R1, R2, R3, R4, R5, R6, R7, R13);
+typedef void (*pABE_voidFunctionsList[])()clobbers(R0, R1, R2, R3, R4, R5, R6, R7, R13);
+typedef void (*pABE_cmdFunction)() clobbers(R0, R1, R2, R3, R4, R5, R6, R7, R13);
+typedef void (*pABE_cmdFunctionsList[])() clobbers(R0, R1, R2, R3, R4, R5, R6, R7, R13);
+typedef void (*pABE_copyFunction)(ABE_uint16 chess_storage(R13))clobbers(R13);
+typedef void (*pABE_copyFunctionsList[])(ABE_uint16 chess_storage(R13))clobbers(R13);
+#endif
+/*
+ * Commonly used structures
+ */
+
+typedef struct abetaskTag{
+	ABE_uint16 iF;	/* 0 Index of called function */
+	ABE_uint16 A0;	/* 2 for INITPTR  of A0 */
+	ABE_uint16 A1;	/* 4 for INITPTR  of A1 */
+	ABE_uint16 A2_3;	/* 6 for INITPTR  of A2 & A3 */
+	ABE_uint16 A4_5;	/* 8 for INITPTR  of A4 & A5 */
+	ABE_uint16 R;	/* 10 for INITREG of R0, R1, R2, R3 */
+	ABE_uint16 misc0;	/* 12 */
+	ABE_uint16 misc1;	/* 14 */
+} ABE_STask;
+typedef ABE_STask* pABE_STask;
+typedef ABE_STask** ppABE_STask;
+
+typedef struct {
+	ABE_uint16 drift_ASRC;	/* 0 */
+	ABE_uint16 drift_io;	/* 2 */
+	ABE_uchar io_type_idx;	/* 4 */
+	ABE_uchar samp_size;	/* 5 */
+	ABE_uchar unused1;	/* 6 */
+	ABE_uchar unused2;	/* 7 */
+
+	ABE_uint16 hw_ctrl_addr;	/* 8 */
+	ABE_uchar atc_irq_data;		/* 10 */
+	ABE_uchar direction_rw;		/* 11 */
+	ABE_uchar flow_counter;		/* 12 */
+	ABE_uchar nsamp;		/* 13 */
+	ABE_uchar x_io;			/* 14 */
+	ABE_uchar on_off;		/* 15 */
+
+	ABE_uint16 split_addr1;		/* 16 */
+	ABE_uint16 split_addr2;		/* 18 */
+	ABE_uint16 split_addr3;		/* 20 */
+	ABE_uchar before_f_index;	/* 22 */
+	ABE_uchar after_f_index;	/* 23 */
+
+	ABE_uint16 smem_addr1;		/* 24 */
+	ABE_uint16 atc_address1;	/* 26 */
+	ABE_uint16 atc_pointer_saved1;	/* 28 */
+	ABE_uchar data_size1;		/* 30 */
+	ABE_uchar copy_f_index1;	/* 31 */
+
+	ABE_uint16 smem_addr2;		/* 32 */
+	ABE_uint16 atc_address2;	/* 34 */
+	ABE_uint16 atc_pointer_saved2;	/* 36 */
+	ABE_uchar data_size2;		/* 38 */
+	ABE_uchar copy_f_index2;	/* 39 */
+
+} ABE_SIODescriptor;
+
+
+#define drift_asrc_	0	/* [w] asrc output used for the next asrc call (+/- 1 / 0) */
+#define drift_io_	2	/* [w] asrc output used for controlling the number of samples to be exchanged (+/- 1 / 0) */
+#define io_type_idx_	4	/* address of the IO subroutine */
+#define samp_size_	5
+#define unused1		6
+#define unused2		7
+#define hw_ctrl_addr_	8	/* dmareq address or host irq buffer address (atc address) */
+#define atc_irq_data_	10	/* data content to be loaded to "hw_ctrl_addr" */
+#define direction_rw_	11	/* read dmem =0, write dmem =3 (atc offset of the access pointer) */
+#define flow_counter_	12	/* flow error counter */
+#define nsamp_		13	/* number of samples (either mono stereo...) */
+#define x_io_		14	/* x number of raw DMEM data moved */
+#define on_off_		15
+
+#define split_addr1_	16	/* internal smem buffer initptr pointer index */
+#define split_addr2_	18	/* internal smem buffer initptr pointer index */
+#define split_addr3_	20	/* internal smem buffer initptr pointer index */
+#define before_f_index_	22	/* index of the copy subroutine */
+#define after_f_index_	23	/* index of the copy subroutine */
+
+#define minidesc1_	24
+#define rel_smem_	0	/* internal smem buffer initptr pointer index */
+#define rel_atc_	2	/* atc descriptor address (byte address x4) */
+#define rel_atc_saved	4	/* location of the saved ATC pointer (+debug info) */
+#define rel_size_	6	/* size of each sample (1:mono/1616 2:stereo ) */
+#define rel_f_		7	/* index of the copy subroutine */
+
+#define s_mem_mm_ul	24
+#define s_mm_ul_size	30
+
+#define minidesc2_	32
+#define Struct_Size	40
+
+typedef ABE_SIODescriptor* pABE_SIODescriptor;
+typedef ABE_SIODescriptor** ppABE_SIODescriptor;
+
+typedef struct abepingpongdescriptorTag{
+	ABE_uint16 drift_ASRC;	/* 0 [W] asrc output used for the next ASRC call (+/- 1 / 0)*/
+	ABE_uint16 drift_io;	/* 2 [W] asrc output used for controlling the number of samples to be exchanged (+/- 1 / 0) */
+	ABE_uint16 hw_ctrl_addr;	/* 4 DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */
+	ABE_uchar  copy_func_index;	/* 6 index of the copy subroutine */
+	ABE_uchar x_io;			/* 7 X number of SMEM samples to move */
+	ABE_uchar data_size;	/* 8 0 for mono data, 1 for stereo data */
+	ABE_uchar smem_addr;	/* 9 internal SMEM buffer INITPTR pointer index */
+	ABE_uchar atc_irq_data;	/* 10 data content to be loaded to "hw_ctrl_addr" */
+	ABE_uchar counter;	/* 11 ping/pong buffer flag */
+	ABE_uint16 workbuff_BaseAddr;	/* 12 current Base address of the working buffer */
+	ABE_uint16 workbuff_Samples;	/* 14 samples left in the working buffer */
+	ABE_uint16 nextbuff0_BaseAddr;	/* 6 Base address of the ping/pong buffer 0 */
+	ABE_uint16 nextbuff0_Samples;	/* 18 samples available in the ping/pong buffer 0 */
+	ABE_uint16 nextbuff1_BaseAddr;	/* 20 Base address of the ping/pong buffer 1 */
+	ABE_uint16 nextbuff1_Samples;	/* 22 samples available in the ping/pong buffer 1 */
+} ABE_SPingPongDescriptor;
+
+typedef ABE_SPingPongDescriptor* pABE_SPingPongDescriptor;
+
+#ifdef __chess__
+#define drift_ASRC	0	/* [W] asrc output used for the next ASRC call (+/- 1 / 0)*/
+#define drift_io	2	/* [W] asrc output used for controlling the number of samples to be exchanged (+/- 1 / 0) */
+#define hw_ctrl_addr	4	/* DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */
+#define copy_func_index 6	/* index of the copy subroutine */
+#define x_io		7	/* X number of SMEM samples to move */
+#define data_size	8	/* 0 for mono data, 1 for stereo data */
+#define smem_addr	9	/* internal SMEM buffer INITPTR pointer index */
+#define atc_irq_data	10	/* data content to be loaded to "hw_ctrl_addr"	*/
+#define atc_address	11	/* ATC descriptor address */
+#define threshold_1	12	/* THR1; For stereo data, THR1 is provided by HAL as THR1<<1 */
+#define threshold_2	13	/* THR2; For stereo data, THR2 is provided by HAL as THR2<<1 */
+#define update_1	14	/* UP_1; For stereo data, UP_1 is provided by HAL as UP_1<<1 */
+#define update_2	15	/* UP_2; For stereo data, UP_2 is provided by HAL as UP_2<<1 */
+#define flow_counter	16	/* Flow error counter */
+#define direction_rw	17	/* Read DMEM =0, Write DMEM =3 (ATC offset of the access pointer) */
+#define counter		11	/* ping/pong buffer flag */
+#define workbuff_BaseAddr	12	/* current Base address of the working buffer */
+#define workbuff_Samples	14	/* samples left in the working buffer */
+#define nextbuff0_BaseAddr	16	/* Base address of the ping/pong buffer 0 */
+#define nextbuff0_Samples	18	/* samples available in the ping/pong buffer 0 */
+#define nextbuff1_BaseAddr	20	/* Base address of the ping/pong buffer 1 */
+#define nextbuff1_Samples	22	/* samples available in the ping/pong buffer 1 */
+#endif
+
+#endif	/* _ABE_TYPEDEF_H_ */
diff --git a/sound/soc/codecs/abe/abehal.dsp b/sound/soc/codecs/abe/abehal.dsp
new file mode 100644
index 000000000000..e350f139a678
--- /dev/null
+++ b/sound/soc/codecs/abe/abehal.dsp
@@ -0,0 +1,242 @@
+# Microsoft Developer Studio Project File - Name="ABEHAL" - Package Owner=<4>
+# Microsoft Developer Studio Generated Build File, Format Version 6.00
+# ** DO NOT EDIT **
+
+# TARGTYPE "Win32 (x86) Console Application" 0x0103
+
+CFG=ABEHAL - Win32 Debug
+!MESSAGE This is not a valid makefile. To build this project using NMAKE,
+!MESSAGE use the Export Makefile command and run
+!MESSAGE
+!MESSAGE NMAKE /f "ABEHAL.mak".
+!MESSAGE
+!MESSAGE You can specify a configuration when running NMAKE
+!MESSAGE by defining the macro CFG on the command line. For example:
+!MESSAGE
+!MESSAGE NMAKE /f "ABEHAL.mak" CFG="ABEHAL - Win32 Debug"
+!MESSAGE
+!MESSAGE Possible choices for configuration are:
+!MESSAGE
+!MESSAGE "ABEHAL - Win32 Release" (based on "Win32 (x86) Console Application")
+!MESSAGE "ABEHAL - Win32 Debug" (based on "Win32 (x86) Console Application")
+!MESSAGE
+
+# Begin Project
+# PROP AllowPerConfigDependencies 0
+# PROP Scc_ProjName "ABEHAL"
+# PROP Scc_LocalPath "m:\a0918484_L1doc\ABE_Firmware\HAL\src"
+CPP=cl.exe
+RSC=rc.exe
+
+!IF  "$(CFG)" == "ABEHAL - Win32 Release"
+
+# PROP BASE Use_MFC 0
+# PROP BASE Use_Debug_Libraries 0
+# PROP BASE Output_Dir "Release"
+# PROP BASE Intermediate_Dir "Release"
+# PROP BASE Target_Dir ""
+# PROP Use_MFC 0
+# PROP Use_Debug_Libraries 0
+# PROP Output_Dir "Release"
+# PROP Intermediate_Dir "Release"
+# PROP Ignore_Export_Lib 0
+# PROP Target_Dir ""
+# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c
+# ADD CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c
+# ADD BASE RSC /l 0x3009 /d "NDEBUG"
+# ADD RSC /l 0x3009 /d "NDEBUG"
+BSC32=bscmake.exe
+# ADD BASE BSC32 /nologo
+# ADD BSC32 /nologo
+LINK32=link.exe
+# ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /machine:I386
+# ADD LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /machine:I386
+
+!ELSEIF  "$(CFG)" == "ABEHAL - Win32 Debug"
+
+# PROP BASE Use_MFC 0
+# PROP BASE Use_Debug_Libraries 1
+# PROP BASE Output_Dir "Debug"
+# PROP BASE Intermediate_Dir "Debug"
+# PROP BASE Target_Dir ""
+# PROP Use_MFC 0
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+# PROP Output_Dir "Debug"
+# PROP Intermediate_Dir "Debug"
+# PROP Ignore_Export_Lib 0
+# PROP Target_Dir ""
+# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c
+# ADD CPP /nologo /W4 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /FR /YX /FD /GZ /c
+# ADD BASE RSC /l 0x3009 /d "_DEBUG"
+# ADD RSC /l 0x3009 /d "_DEBUG"
+BSC32=bscmake.exe
+# ADD BASE BSC32 /nologo
+# ADD BSC32 /nologo
+LINK32=link.exe
+# ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /debug /machine:I386 /pdbtype:sept
+# ADD LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /debug /machine:I386 /pdbtype:sept
+
+!ENDIF
+
+# Begin Target
+
+# Name "ABEHAL - Win32 Release"
+# Name "ABEHAL - Win32 Debug"
+# Begin Group "Source Files"
+
+# PROP Default_Filter "cpp;c;cxx;rc;def;r;odl;idl;hpj;bat"
+# Begin Source File
+
+SOURCE=.\ABE_API.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_DBG.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_EXT.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_INI.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_IRQ.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_LIB.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_MAIN.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_SEQ.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_TEST.C
+# End Source File
+# End Group
+# Begin Group "Header Files"
+
+# PROP Default_Filter "h;hpp;hxx;hm;inl"
+# Begin Source File
+
+SOURCE=.\ABE_API.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_CM_ADDR.h
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_COF.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_DAT.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_DBG.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_DEF.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_define.h
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_DM_ADDR.h
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_EXT.h
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_functionsId.h
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_FW.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_INITxxx_labels.h
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_LIB.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_MAIN.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_REF.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_SEQ.H
+# End Source File
+# Begin Source File
+
+SOURCE=.\ABE_SM_ADDR.h
+# End Source File
+# Begin Source File
+
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+# End Source File
+# Begin Source File
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+# End Source File
+# Begin Source File
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+# End Source File
+# Begin Source File
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+# End Source File
+# Begin Source File
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+# End Source File
+# Begin Source File
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+SOURCE=.\C_ABE_FW.CM
+# End Source File
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+# End Source File
+# Begin Source File
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+# End Source File
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+SOURCE=.\C_ABE_FW.SM32
+# End Source File
+# Begin Source File
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+SOURCE=.\CodingStyle.txt
+# End Source File
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+
+# PROP Default_Filter "ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe"
+# End Group
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+# End Project
diff --git a/sound/soc/codecs/abe/abehal.dsw b/sound/soc/codecs/abe/abehal.dsw
new file mode 100644
index 000000000000..f28cce8c49d5
--- /dev/null
+++ b/sound/soc/codecs/abe/abehal.dsw
@@ -0,0 +1,33 @@
+Microsoft Developer Studio Workspace File, Format Version 6.00
+# WARNING: DO NOT EDIT OR DELETE THIS WORKSPACE FILE!
+
+###############################################################################
+
+Project: "ABEHAL"=.\ABEHAL.dsp - Package Owner=<4>
+
+Package=<5>
+{{{
+    begin source code control
+    ABEHAL
+    m:\a0918484_L1doc\ABE_Firmware\HAL\src
+    end source code control
+}}}
+
+Package=<4>
+{{{
+}}}
+
+###############################################################################
+
+Global:
+
+Package=<5>
+{{{
+}}}
+
+Package=<3>
+{{{
+}}}
+
+###############################################################################
+
diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h
new file mode 100644
index 000000000000..42f3f56286ff
--- /dev/null
+++ b/sound/soc/codecs/twl6040.h
@@ -0,0 +1,143 @@
+/*
+ * ALSA SoC TWL6040 codec driver
+ *
+ * Author:	Misael Lopez Cruz <x0052729@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __TWL6040_H__
+#define __TWL6040_H__
+
+#define TWL6040_REG_ASICID		0x01
+#define TWL6040_REG_ASICREV		0x02
+#define TWL6040_REG_INTID		0x03
+#define TWL6040_REG_INTMR		0x04
+#define TWL6040_REG_NCPCTL		0x05
+#define TWL6040_REG_LDOCTL		0x06
+#define TWL6040_REG_HPPLLCTL		0x07
+#define TWL6040_REG_LPPLLCTL		0x08
+#define TWL6040_REG_LPPLLDIV		0x09
+#define TWL6040_REG_AMICBCTL		0x0A
+#define TWL6040_REG_DMICBCTL		0x0B
+#define TWL6040_REG_MICLCTL		0x0C
+#define TWL6040_REG_MICRCTL		0x0D
+#define TWL6040_REG_MICGAIN		0x0E
+#define TWL6040_REG_LINEGAIN		0x0F
+#define TWL6040_REG_HSLCTL		0x10
+#define TWL6040_REG_HSRCTL		0x11
+#define TWL6040_REG_HSGAIN		0x12
+#define TWL6040_REG_EARCTL		0x13
+#define TWL6040_REG_HFLCTL		0x14
+#define TWL6040_REG_HFLGAIN		0x15
+#define TWL6040_REG_HFRCTL		0x16
+#define TWL6040_REG_HFRGAIN		0x17
+#define TWL6040_REG_VIBCTLL		0x18
+#define TWL6040_REG_VIBDATL		0x19
+#define TWL6040_REG_VIBCTLR		0x1A
+#define TWL6040_REG_VIBDATR		0x1B
+#define TWL6040_REG_HKCTL1		0x1C
+#define TWL6040_REG_HKCTL2		0x1D
+#define TWL6040_REG_GPOCTL		0x1E
+#define TWL6040_REG_ALB			0x1F
+#define TWL6040_REG_DLB			0x20
+#define TWL6040_REG_TRIM1		0x28
+#define TWL6040_REG_TRIM2		0x29
+#define TWL6040_REG_TRIM3		0x2A
+#define TWL6040_REG_HSOTRIM		0x2B
+#define TWL6040_REG_HFOTRIM		0x2C
+#define TWL6040_REG_ACCCTL		0x2D
+#define TWL6040_REG_STATUS		0x2E
+#define TWL6040_REG_SHADOW		0x2F
+
+#define TWL6040_CACHEREGNUM		(TWL6040_REG_SHADOW + 1)
+
+#define TWL6040_VIOREGNUM		18
+#define TWL6040_VDDREGNUM		21
+
+/* INTID (0x03) fields */
+
+#define TWL6040_THINT			0x01
+#define TWL6040_PLUGINT			0x02
+#define TWL6040_UNPLUGINT		0x04
+#define TWL6040_HOOKINT			0x08
+#define TWL6040_HFINT			0x10
+#define TWL6040_VIBINT			0x20
+#define TWL6040_READYINT		0x40
+
+/* INTMR (0x04) fields */
+
+#define TWL6040_READYMSK		0x40
+#define TWL6040_ALLINT_MSK		0x7B
+
+/* NCPCTL (0x05) fields */
+
+#define TWL6040_NCPENA			0x01
+#define TWL6040_NCPOPEN			0x40
+
+/* LDOCTL (0x06) fields */
+
+#define TWL6040_LSLDOENA		0x01
+#define TWL6040_HSLDOENA		0x04
+#define TWL6040_REFENA			0x40
+#define TWL6040_OSCENA			0x80
+
+/* HPPLLCTL (0x07) fields */
+
+#define TWL6040_HPLLENA			0x01
+#define TWL6040_HPLLRST			0x02
+#define TWL6040_HPLLBP			0x04
+#define TWL6040_HPLLSQRENA		0x08
+#define TWL6040_HPLLSQRBP		0x10
+#define TWL6040_MCLK_12000KHZ		(0 << 5)
+#define TWL6040_MCLK_19200KHZ		(1 << 5)
+#define TWL6040_MCLK_26000KHZ		(2 << 5)
+#define TWL6040_MCLK_38400KHZ		(3 << 5)
+#define TWL6040_MCLK_MSK		0x60
+
+/* LPPLLCTL (0x08) fields */
+
+#define TWL6040_LPLLENA			0x01
+#define TWL6040_LPLLRST			0x02
+#define TWL6040_LPLLSEL			0x04
+#define TWL6040_LPLLFIN			0x08
+#define TWL6040_HPLLSEL			0x10
+
+/* HSLCTL (0x10) fields */
+
+#define TWL6040_HSDACMODEL		0x02
+#define TWL6040_HSDRVMODEL		0x08
+
+/* HSRCTL (0x11) fields */
+
+#define TWL6040_HSDACMODER		0x02
+#define TWL6040_HSDRVMODER		0x08
+
+/* ACCCTL (0x2D) fields */
+
+#define TWL6040_RESETSPLIT		0x04
+
+#define TWL6040_SYSCLK_SEL_LPPLL	1
+#define TWL6040_SYSCLK_SEL_HPPLL	2
+
+#define TWL6040_HPPLL_ID		1
+#define TWL6040_LPPLL_ID		2
+
+/* STATUS (0x2E) fields */
+
+#define TWL6040_PLUGCOMP		0x02
+
+#endif /* End of __TWL6040_H__ */
diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index f11963c21873..a82127abce76 100644
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
@@ -6,9 +6,13 @@ config SND_OMAP_SOC_MCBSP
 	tristate
 	select OMAP_MCBSP
 
-config SND_OMAP_SOC_MCPDM
+config OMAP_MCPDM
 	tristate
 
+config SND_OMAP_SOC_ABE
+	tristate
+	select OMAP_MCPDM
+
 config SND_OMAP_SOC_N810
 	tristate "SoC Audio support for Nokia N810"
 	depends on SND_OMAP_SOC && MACH_NOKIA_N810 && I2C
@@ -88,6 +92,28 @@ config SND_OMAP_SOC_SDP3430
 	  Say Y if you want to add support for SoC audio on Texas Instruments
 	  SDP3430.
 
+config SND_OMAP_SOC_SDP4430
+	tristate "SoC Audio support for Texas Instruments SDP4430"
+	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP_4430SDP
+	select SND_OMAP_SOC_ABE
+	select SND_SOC_ABE_TWL6040
+	select SND_OMAP_SOC_MCBSP
+	help
+	  Say Y if you want to add support for SoC audio on Texas Instruments
+	  SDP4430.
+
+config SND_OMAP_SOC_HDMI
+	tristate "SoC Audio support for HDMI interface on SDP4430"
+	depends on SND_OMAP_SOC_SDP4430 && OMAP2_DSS_HDMI
+	help
+	  Say Y if you want to add support for HDMI interface on SDP4430
+
+config SND_OMAP_VOICE_TEST
+	bool "SoC Audio support for test Voice Call"
+	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP_4430SDP
+	help
+	 Say Y if you want to test modem voice call
+
 config SND_OMAP_SOC_OMAP3_PANDORA
 	tristate "SoC Audio support for OMAP3 Pandora"
 	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP3_PANDORA
diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
index 0bc00ca14b37..f3390dcac31e 100644
--- a/sound/soc/omap/Makefile
+++ b/sound/soc/omap/Makefile
@@ -1,11 +1,13 @@
 # OMAP Platform Support
 snd-soc-omap-objs := omap-pcm.o
 snd-soc-omap-mcbsp-objs := omap-mcbsp.o
-snd-soc-omap-mcpdm-objs := omap-mcpdm.o mcpdm.o
+snd-soc-omap-abe-objs := omap-abe.o mcpdm.o
+snd-soc-omap-hdmi-objs:= omap-hdmi.o
 
 obj-$(CONFIG_SND_OMAP_SOC) += snd-soc-omap.o
 obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o
-obj-$(CONFIG_SND_OMAP_SOC_MCPDM) += snd-soc-omap-mcpdm.o
+obj-$(CONFIG_SND_OMAP_SOC_ABE) += snd-soc-omap-abe.o
+obj-$(CONFIG_SND_OMAP_SOC_HDMI) += snd-soc-omap-hdmi.o
 
 # OMAP Machine Support
 snd-soc-n810-objs := n810.o
@@ -16,6 +18,7 @@ snd-soc-omap2evm-objs := omap2evm.o
 snd-soc-omap3evm-objs := omap3evm.o
 snd-soc-am3517evm-objs := am3517evm.o
 snd-soc-sdp3430-objs := sdp3430.o
+snd-soc-sdp4430-objs := sdp4430.o
 snd-soc-omap3pandora-objs := omap3pandora.o
 snd-soc-omap3beagle-objs := omap3beagle.o
 snd-soc-zoom2-objs := zoom2.o
@@ -29,6 +32,7 @@ obj-$(CONFIG_SND_OMAP_SOC_OMAP2EVM) += snd-soc-omap2evm.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o
 obj-$(CONFIG_SND_OMAP_SOC_AM3517EVM) += snd-soc-am3517evm.o
 obj-$(CONFIG_SND_OMAP_SOC_SDP3430) += snd-soc-sdp3430.o
+obj-$(CONFIG_SND_OMAP_SOC_SDP4430) += snd-soc-sdp4430.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
 obj-$(CONFIG_SND_OMAP_SOC_ZOOM2) += snd-soc-zoom2.o
diff --git a/sound/soc/omap/mcpdm.c b/sound/soc/omap/mcpdm.c
index 1dab4c14874d..d2bb50adca75 100644
--- a/sound/soc/omap/mcpdm.c
+++ b/sound/soc/omap/mcpdm.c
@@ -1,5 +1,5 @@
 /*
- * mcpdm.c  --  McPDM interface driver
+ * mcpdm.c  --	McPDM interface driver
  *
  * Author: Jorge Eduardo Candelaria <x0107209@ti.com>
  * Copyright (C) 2009 - Texas Instruments, Inc.
@@ -28,10 +28,10 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/err.h>
-#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/pm_runtime.h>
 
 #include "mcpdm.h"
 
@@ -39,47 +39,49 @@ static struct omap_mcpdm *mcpdm;
 
 static inline void omap_mcpdm_write(u16 reg, u32 val)
 {
-       __raw_writel(val, mcpdm->io_base + reg);
+	__raw_writel(val, mcpdm->io_base + reg);
 }
 
 static inline int omap_mcpdm_read(u16 reg)
 {
-       return __raw_readl(mcpdm->io_base + reg);
+	return __raw_readl(mcpdm->io_base + reg);
 }
 
+#ifdef MCPDM_DEBUG
 static void omap_mcpdm_reg_dump(void)
 {
-       dev_dbg(mcpdm->dev, "***********************\n");
-       dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_IRQSTATUS_RAW));
-       dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_IRQSTATUS));
-       dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_IRQENABLE_SET));
-       dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_IRQENABLE_CLR));
-       dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
-                       omap_mcpdm_read(MCPDM_IRQWAKE_EN));
-       dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
-                       omap_mcpdm_read(MCPDM_DMAENABLE_SET));
-       dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_DMAENABLE_CLR));
-       dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_DMAWAKEEN));
-       dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_CTRL));
-       dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_DN_DATA));
-       dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
-                       omap_mcpdm_read(MCPDM_UP_DATA));
-       dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
-                       omap_mcpdm_read(MCPDM_FIFO_CTRL_DN));
-       dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_FIFO_CTRL_UP));
-       dev_dbg(mcpdm->dev, "DN_OFFSET:  0x%04x\n",
-                       omap_mcpdm_read(MCPDM_DN_OFFSET));
-       dev_dbg(mcpdm->dev, "***********************\n");
+	dev_dbg(mcpdm->dev, "***********************\n");
+	dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQSTATUS_RAW));
+	dev_dbg(mcpdm->dev, "IRQSTATUS:	0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQSTATUS));
+	dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQENABLE_SET));
+	dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQENABLE_CLR));
+	dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
+			omap_mcpdm_read(MCPDM_IRQWAKE_EN));
+	dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
+			omap_mcpdm_read(MCPDM_DMAENABLE_SET));
+	dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_DMAENABLE_CLR));
+	dev_dbg(mcpdm->dev, "DMAWAKEEN:	0x%04x\n",
+			omap_mcpdm_read(MCPDM_DMAWAKEEN));
+	dev_dbg(mcpdm->dev, "CTRL:	0x%04x\n",
+			omap_mcpdm_read(MCPDM_CTRL));
+	dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_DN_DATA));
+	dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
+			omap_mcpdm_read(MCPDM_UP_DATA));
+	dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
+			omap_mcpdm_read(MCPDM_FIFO_CTRL_DN));
+	dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
+			omap_mcpdm_read(MCPDM_FIFO_CTRL_UP));
+	dev_dbg(mcpdm->dev, "DN_OFFSET:	0x%04x\n",
+			omap_mcpdm_read(MCPDM_DN_OFFSET));
+	dev_dbg(mcpdm->dev, "***********************\n");
 }
+#endif
 
 /*
  * Takes the McPDM module in and out of reset state.
@@ -87,26 +89,26 @@ static void omap_mcpdm_reg_dump(void)
  */
 static void omap_mcpdm_reset_capture(int reset)
 {
-       int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+	int ctrl = omap_mcpdm_read(MCPDM_CTRL);
 
-       if (reset)
-               ctrl |= SW_UP_RST;
-       else
-               ctrl &= ~SW_UP_RST;
+	if (reset)
+		ctrl |= SW_UP_RST;
+	else
+		ctrl &= ~SW_UP_RST;
 
-       omap_mcpdm_write(MCPDM_CTRL, ctrl);
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
 }
 
 static void omap_mcpdm_reset_playback(int reset)
 {
-       int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+	int ctrl = omap_mcpdm_read(MCPDM_CTRL);
 
-       if (reset)
-               ctrl |= SW_DN_RST;
-       else
-               ctrl &= ~SW_DN_RST;
+	if (reset)
+		ctrl |= SW_DN_RST;
+	else
+		ctrl &= ~SW_DN_RST;
 
-       omap_mcpdm_write(MCPDM_CTRL, ctrl);
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
 }
 
 /*
@@ -115,14 +117,14 @@ static void omap_mcpdm_reset_playback(int reset)
  */
 void omap_mcpdm_start(int stream)
 {
-       int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+	int ctrl = omap_mcpdm_read(MCPDM_CTRL);
 
-       if (stream)
-               ctrl |= mcpdm->up_channels;
-       else
-               ctrl |= mcpdm->dn_channels;
+	if (stream)
+		ctrl |= mcpdm->up_channels;
+	else
+		ctrl |= mcpdm->dn_channels;
 
-       omap_mcpdm_write(MCPDM_CTRL, ctrl);
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
 }
 
 /*
@@ -131,14 +133,14 @@ void omap_mcpdm_start(int stream)
  */
 void omap_mcpdm_stop(int stream)
 {
-       int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+	int ctrl = omap_mcpdm_read(MCPDM_CTRL);
 
-       if (stream)
-               ctrl &= ~mcpdm->up_channels;
-       else
-               ctrl &= ~mcpdm->dn_channels;
+	if (stream)
+		ctrl &= ~mcpdm->up_channels;
+	else
+		ctrl &= ~mcpdm->dn_channels;
 
-       omap_mcpdm_write(MCPDM_CTRL, ctrl);
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
 }
 
 /*
@@ -147,38 +149,38 @@ void omap_mcpdm_stop(int stream)
  */
 int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink)
 {
-       int irq_mask = 0;
-       int ctrl;
+	int irq_mask = 0;
+	int ctrl;
 
-       if (!uplink)
-               return -EINVAL;
+	if (!uplink)
+		return -EINVAL;
 
-       mcpdm->uplink = uplink;
+	mcpdm->uplink = uplink;
 
-       /* Enable irq request generation */
-       irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
-       omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
+	/* Enable irq request generation */
+	irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
+	omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
 
-       /* Configure uplink threshold */
-       if (uplink->threshold > UP_THRES_MAX)
-               uplink->threshold = UP_THRES_MAX;
+	/* Configure uplink threshold */
+	if (uplink->threshold > UP_THRES_MAX)
+		uplink->threshold = UP_THRES_MAX;
 
-       omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
+	omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
 
-       /* Configure DMA controller */
-       omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
+	/* Configure DMA controller */
+	omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
 
-       /* Set pdm out format */
-       ctrl = omap_mcpdm_read(MCPDM_CTRL);
-       ctrl &= ~PDMOUTFORMAT;
-       ctrl |= uplink->format & PDMOUTFORMAT;
+	/* Set pdm out format */
+	ctrl = omap_mcpdm_read(MCPDM_CTRL);
+	ctrl &= ~PDMOUTFORMAT;
+	ctrl |= uplink->format & PDMOUTFORMAT;
 
-       /* Uplink channels */
-       mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK);
+	/* Uplink channels */
+	mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK);
 
-       omap_mcpdm_write(MCPDM_CTRL, ctrl);
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
 
-       return 0;
+	return 0;
 }
 
 /*
@@ -187,38 +189,38 @@ int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink)
  */
 int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink)
 {
-       int irq_mask = 0;
-       int ctrl;
+	int irq_mask = 0;
+	int ctrl;
 
-       if (!downlink)
-               return -EINVAL;
+	if (!downlink)
+		return -EINVAL;
 
-       mcpdm->downlink = downlink;
+	mcpdm->downlink = downlink;
 
-       /* Enable irq request generation */
-       irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
-       omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
+	/* Enable irq request generation */
+	irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
+	omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
 
-       /* Configure uplink threshold */
-       if (downlink->threshold > DN_THRES_MAX)
-               downlink->threshold = DN_THRES_MAX;
+	/* Configure uplink threshold */
+	if (downlink->threshold > DN_THRES_MAX)
+		downlink->threshold = DN_THRES_MAX;
 
-       omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
+	omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
 
-       /* Enable DMA request generation */
-       omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
+	/* Enable DMA request generation */
+	omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
 
-       /* Set pdm out format */
-       ctrl = omap_mcpdm_read(MCPDM_CTRL);
-       ctrl &= ~PDMOUTFORMAT;
-       ctrl |= downlink->format & PDMOUTFORMAT;
+	/* Set pdm out format */
+	ctrl = omap_mcpdm_read(MCPDM_CTRL);
+	ctrl &= ~PDMOUTFORMAT;
+	ctrl |= downlink->format & PDMOUTFORMAT;
 
-       /* Downlink channels */
-       mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK);
+	/* Downlink channels */
+	mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK);
 
-       omap_mcpdm_write(MCPDM_CTRL, ctrl);
+	omap_mcpdm_write(MCPDM_CTRL, ctrl);
 
-       return 0;
+	return 0;
 }
 
 /*
@@ -227,24 +229,24 @@ int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink)
  */
 int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink)
 {
-       int irq_mask = 0;
+	int irq_mask = 0;
 
-       if (!uplink)
-               return -EINVAL;
+	if (!uplink)
+		return -EINVAL;
 
-       /* Disable irq request generation */
-       irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
-       omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
+	/* Disable irq request generation */
+	irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
+	omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
 
-       /* Disable DMA request generation */
-       omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE);
+	/* Disable DMA request generation */
+	omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE);
 
-       /* Clear Downlink channels */
-       mcpdm->up_channels = 0;
+	/* Clear Downlink channels */
+	mcpdm->up_channels = 0;
 
-       mcpdm->uplink = NULL;
+	mcpdm->uplink = NULL;
 
-       return 0;
+	return 0;
 }
 
 /*
@@ -253,124 +255,146 @@ int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink)
  */
 int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink)
 {
-       int irq_mask = 0;
+	int irq_mask = 0;
 
-       if (!downlink)
-               return -EINVAL;
+	if (!downlink)
+		return -EINVAL;
 
-       /* Disable irq request generation */
-       irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
-       omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
+	/* Disable irq request generation */
+	irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
+	omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
 
-       /* Disable DMA request generation */
-       omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE);
+	/* Disable DMA request generation */
+	omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE);
 
-       /* clear Downlink channels */
-       mcpdm->dn_channels = 0;
+	/* clear Downlink channels */
+	mcpdm->dn_channels = 0;
 
-       mcpdm->downlink = NULL;
+	mcpdm->downlink = NULL;
 
-       return 0;
+	return 0;
 }
 
 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
 {
-       struct omap_mcpdm *mcpdm_irq = dev_id;
-       int irq_status;
-
-       irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS);
-
-       /* Acknowledge irq event */
-       omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
-
-       if (irq & MCPDM_DN_IRQ_FULL) {
-               dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
-               omap_mcpdm_reset_playback(1);
-               omap_mcpdm_playback_open(mcpdm_irq->downlink);
-               omap_mcpdm_reset_playback(0);
-       }
-
-       if (irq & MCPDM_DN_IRQ_EMPTY) {
-               dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
-               omap_mcpdm_reset_playback(1);
-               omap_mcpdm_playback_open(mcpdm_irq->downlink);
-               omap_mcpdm_reset_playback(0);
-       }
-
-       if (irq & MCPDM_DN_IRQ) {
-               dev_dbg(mcpdm_irq->dev, "DN write request\n");
-       }
-
-       if (irq & MCPDM_UP_IRQ_FULL) {
-               dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
-               omap_mcpdm_reset_capture(1);
-               omap_mcpdm_capture_open(mcpdm_irq->uplink);
-               omap_mcpdm_reset_capture(0);
-       }
-
-       if (irq & MCPDM_UP_IRQ_EMPTY) {
-               dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
-               omap_mcpdm_reset_capture(1);
-               omap_mcpdm_capture_open(mcpdm_irq->uplink);
-               omap_mcpdm_reset_capture(0);
-       }
-
-       if (irq & MCPDM_UP_IRQ) {
-               dev_dbg(mcpdm_irq->dev, "UP write request\n");
-       }
-
-       return IRQ_HANDLED;
+	struct omap_mcpdm *mcpdm_irq = dev_id;
+	int irq_status;
+
+	irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS);
+
+	/* Acknowledge irq event */
+	omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
+
+	if (irq & MCPDM_DN_IRQ_FULL) {
+		dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
+		omap_mcpdm_reset_playback(1);
+		omap_mcpdm_playback_open(mcpdm_irq->downlink);
+		omap_mcpdm_reset_playback(0);
+	}
+
+	if (irq & MCPDM_DN_IRQ_EMPTY) {
+		dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
+		omap_mcpdm_reset_playback(1);
+		omap_mcpdm_playback_open(mcpdm_irq->downlink);
+		omap_mcpdm_reset_playback(0);
+	}
+
+	if (irq & MCPDM_DN_IRQ) {
+		dev_dbg(mcpdm_irq->dev, "DN write request\n");
+	}
+
+	if (irq & MCPDM_UP_IRQ_FULL) {
+		dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
+		omap_mcpdm_reset_capture(1);
+		omap_mcpdm_capture_open(mcpdm_irq->uplink);
+		omap_mcpdm_reset_capture(0);
+	}
+
+	if (irq & MCPDM_UP_IRQ_EMPTY) {
+		dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
+		omap_mcpdm_reset_capture(1);
+		omap_mcpdm_capture_open(mcpdm_irq->uplink);
+		omap_mcpdm_reset_capture(0);
+	}
+
+	if (irq & MCPDM_UP_IRQ) {
+		dev_dbg(mcpdm_irq->dev, "UP write request\n");
+	}
+
+	return IRQ_HANDLED;
 }
 
 int omap_mcpdm_request(void)
 {
-       int ret;
-
-       clk_enable(mcpdm->clk);
-
-       spin_lock(&mcpdm->lock);
-
-       if (!mcpdm->free) {
-               dev_err(mcpdm->dev, "McPDM interface is in use\n");
-               spin_unlock(&mcpdm->lock);
-               ret = -EBUSY;
-               goto err;
-       }
-       mcpdm->free = 0;
-
-       spin_unlock(&mcpdm->lock);
-
-       /* Disable lines while request is ongoing */
-       omap_mcpdm_write(MCPDM_CTRL, 0x00);
-
-       ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
-                               0, "McPDM", (void *)mcpdm);
-       if (ret) {
-               dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n");
-               goto err;
-       }
-
-       return 0;
+	struct platform_device *pdev;
+	struct omap_mcpdm_platform_data *pdata;
+	int ret;
+
+	pdev = to_platform_device(mcpdm->dev);
+	pdata = pdev->dev.platform_data;
+
+	pm_runtime_get_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+	if (pdata->device_enable)
+		pdata->device_enable(pdev);
+#endif
+	spin_lock(&mcpdm->lock);
+
+	if (!mcpdm->free) {
+		dev_err(mcpdm->dev, "McPDM interface is in use\n");
+		spin_unlock(&mcpdm->lock);
+		ret = -EBUSY;
+		goto err;
+	}
+	mcpdm->free = 0;
+
+	spin_unlock(&mcpdm->lock);
+
+	/* Disable lines while request is ongoing */
+	omap_mcpdm_write(MCPDM_CTRL, 0x00);
+
+	ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
+				0, "McPDM", (void *)mcpdm);
+	if (ret) {
+		dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n");
+		goto err;
+	}
+
+	return 0;
 
 err:
-       clk_disable(mcpdm->clk);
-       return ret;
+	pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+	if (pdata->device_idle)
+		pdata->device_idle(pdev);
+#endif
+	return ret;
 }
 
 void omap_mcpdm_free(void)
 {
-       spin_lock(&mcpdm->lock);
-       if (mcpdm->free) {
-               dev_err(mcpdm->dev, "McPDM interface is already free\n");
-               spin_unlock(&mcpdm->lock);
-               return;
-       }
-       mcpdm->free = 1;
-       spin_unlock(&mcpdm->lock);
-
-       clk_disable(mcpdm->clk);
-
-       free_irq(mcpdm->irq, (void *)mcpdm);
+	struct platform_device *pdev;
+	struct omap_mcpdm_platform_data *pdata;
+
+	pdev = to_platform_device(mcpdm->dev);
+	pdata = pdev->dev.platform_data;
+
+	spin_lock(&mcpdm->lock);
+	if (mcpdm->free) {
+		dev_err(mcpdm->dev, "McPDM interface is already free\n");
+		spin_unlock(&mcpdm->lock);
+		return;
+	}
+	mcpdm->free = 1;
+	spin_unlock(&mcpdm->lock);
+
+	pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+	if (pdata->device_idle)
+		pdata->device_idle(pdev);
+#endif
+
+	free_irq(mcpdm->irq, (void *)mcpdm);
 }
 
 /* Enable/disable DC offset cancelation for the analog
@@ -378,108 +402,107 @@ void omap_mcpdm_free(void)
  */
 int omap_mcpdm_set_offset(int offset1, int offset2)
 {
-       int offset;
+	int offset;
 
-       if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX))
-               return -EINVAL;
+	if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX))
+		return -EINVAL;
 
-       offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2);
+	offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2);
 
-       /* offset cancellation for channel 1 */
-       if (offset1)
-               offset |= DN_OFST_RX1_EN;
-       else
-               offset &= ~DN_OFST_RX1_EN;
+	/* offset cancellation for channel 1 */
+	if (offset1)
+		offset |= DN_OFST_RX1_EN;
+	else
+		offset &= ~DN_OFST_RX1_EN;
 
-       /* offset cancellation for channel 2 */
-       if (offset2)
-               offset |= DN_OFST_RX2_EN;
-       else
-               offset &= ~DN_OFST_RX2_EN;
+	/* offset cancellation for channel 2 */
+	if (offset2)
+		offset |= DN_OFST_RX2_EN;
+	else
+		offset &= ~DN_OFST_RX2_EN;
 
-       omap_mcpdm_write(MCPDM_DN_OFFSET, offset);
+	omap_mcpdm_write(MCPDM_DN_OFFSET, offset);
 
-       return 0;
+	return 0;
 }
 
 static int __devinit omap_mcpdm_probe(struct platform_device *pdev)
 {
-       struct resource *res;
-       int ret = 0;
-
-       mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
-       if (!mcpdm) {
-               ret = -ENOMEM;
-               goto exit;
-       }
-
-       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       if (res == NULL) {
-               dev_err(&pdev->dev, "no resource\n");
-               goto err_resource;
-       }
-
-       spin_lock_init(&mcpdm->lock);
-       mcpdm->free = 1;
-       mcpdm->io_base = ioremap(res->start, resource_size(res));
-       if (!mcpdm->io_base) {
-               ret = -ENOMEM;
-               goto err_resource;
-       }
-
-       mcpdm->irq = platform_get_irq(pdev, 0);
-
-       mcpdm->clk = clk_get(&pdev->dev, "pdm_ck");
-       if (IS_ERR(mcpdm->clk)) {
-               ret = PTR_ERR(mcpdm->clk);
-               dev_err(&pdev->dev, "unable to get pdm_ck: %d\n", ret);
-               goto err_clk;
-       }
-
-       mcpdm->dev = &pdev->dev;
-       platform_set_drvdata(pdev, mcpdm);
-
-       return 0;
-
-err_clk:
-       iounmap(mcpdm->io_base);
+	struct resource *res;
+	int ret = 0;
+
+	mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
+	if (!mcpdm) {
+		ret = -ENOMEM;
+		goto exit;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "no resource\n");
+		goto err_resource;
+	}
+
+	spin_lock_init(&mcpdm->lock);
+	mcpdm->free = 1;
+
+	mcpdm->io_base = ioremap(res->start, resource_size(res));
+	if (!mcpdm->io_base) {
+		ret = -ENOMEM;
+		goto err_resource;
+	}
+
+	mcpdm->irq = platform_get_irq(pdev, 0);
+	if (!mcpdm->irq) {
+		ret = -EINVAL;
+		goto err_irq;
+	}
+
+	mcpdm->dev = &pdev->dev;
+	platform_set_drvdata(pdev, mcpdm);
+
+	return 0;
+
+err_irq:
+	iounmap(mcpdm->io_base);
 err_resource:
-       kfree(mcpdm);
+	kfree(mcpdm);
 exit:
-       return ret;
+	return ret;
 }
 
 static int __devexit omap_mcpdm_remove(struct platform_device *pdev)
 {
-       struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev);
+	struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev);
+	struct omap_mcpdm_platform_data *pdata = pdev->dev.platform_data;
 
-       platform_set_drvdata(pdev, NULL);
+	platform_set_drvdata(pdev, NULL);
 
-       clk_put(mcpdm_ptr->clk);
+	pm_runtime_put_sync(&pdev->dev);
+#ifndef CONFIG_PM_RUNTIME
+	if (pdata->device_shutdown)
+		pdata->device_shutdown(pdev);
+#endif
+	iounmap(mcpdm_ptr->io_base);
 
-       iounmap(mcpdm_ptr->io_base);
+	mcpdm_ptr->free = 0;
+	mcpdm_ptr->dev = NULL;
 
-       mcpdm_ptr->clk = NULL;
-       mcpdm_ptr->free = 0;
-       mcpdm_ptr->dev = NULL;
+	kfree(mcpdm_ptr);
 
-       kfree(mcpdm_ptr);
-
-       return 0;
+	return 0;
 }
 
 static struct platform_driver omap_mcpdm_driver = {
-       .probe = omap_mcpdm_probe,
-       .remove = __devexit_p(omap_mcpdm_remove),
-       .driver = {
-               .name = "omap-mcpdm",
-       },
+	.probe = omap_mcpdm_probe,
+	.remove = __devexit_p(omap_mcpdm_remove),
+	.driver = {
+		.name = "omap-mcpdm",
+	},
 };
 
-static struct platform_device *omap_mcpdm_device;
-
 static int __init omap_mcpdm_init(void)
 {
-       return platform_driver_register(&omap_mcpdm_driver);
+	return platform_driver_register(&omap_mcpdm_driver);
 }
 arch_initcall(omap_mcpdm_init);
diff --git a/sound/soc/omap/mcpdm.h b/sound/soc/omap/mcpdm.h
index 7bb326ef0886..ab649ab970b8 100644
--- a/sound/soc/omap/mcpdm.h
+++ b/sound/soc/omap/mcpdm.h
@@ -21,123 +21,126 @@
 
 /* McPDM registers */
 
-#define MCPDM_REVISION         0x00
-#define MCPDM_SYSCONFIG                0x10
-#define MCPDM_IRQSTATUS_RAW    0x24
-#define MCPDM_IRQSTATUS                0x28
-#define MCPDM_IRQENABLE_SET    0x2C
-#define MCPDM_IRQENABLE_CLR    0x30
-#define MCPDM_IRQWAKE_EN       0x34
-#define MCPDM_DMAENABLE_SET    0x38
-#define MCPDM_DMAENABLE_CLR    0x3C
-#define MCPDM_DMAWAKEEN                0x40
-#define MCPDM_CTRL             0x44
-#define MCPDM_DN_DATA          0x48
-#define MCPDM_UP_DATA          0x4C
-#define MCPDM_FIFO_CTRL_DN     0x50
-#define MCPDM_FIFO_CTRL_UP     0x54
-#define MCPDM_DN_OFFSET                0x58
+#define MCPDM_REVISION		0x00
+#define MCPDM_SYSCONFIG		0x10
+#define MCPDM_IRQSTATUS_RAW	0x24
+#define MCPDM_IRQSTATUS		0x28
+#define MCPDM_IRQENABLE_SET	0x2C
+#define MCPDM_IRQENABLE_CLR	0x30
+#define MCPDM_IRQWAKE_EN	0x34
+#define MCPDM_DMAENABLE_SET	0x38
+#define MCPDM_DMAENABLE_CLR	0x3C
+#define MCPDM_DMAWAKEEN		0x40
+#define MCPDM_CTRL		0x44
+#define MCPDM_DN_DATA		0x48
+#define MCPDM_UP_DATA		0x4C
+#define MCPDM_FIFO_CTRL_DN	0x50
+#define MCPDM_FIFO_CTRL_UP	0x54
+#define MCPDM_DN_OFFSET		0x58
 
 /*
  * MCPDM_IRQ bit fields
  * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
  */
 
-#define MCPDM_DN_IRQ                   (1 << 0)
-#define MCPDM_DN_IRQ_EMPTY             (1 << 1)
-#define MCPDM_DN_IRQ_ALMST_EMPTY       (1 << 2)
-#define MCPDM_DN_IRQ_FULL              (1 << 3)
+#define MCPDM_DN_IRQ			(1 << 0)
+#define MCPDM_DN_IRQ_EMPTY		(1 << 1)
+#define MCPDM_DN_IRQ_ALMST_EMPTY	(1 << 2)
+#define MCPDM_DN_IRQ_FULL		(1 << 3)
 
-#define MCPDM_UP_IRQ                   (1 << 8)
-#define MCPDM_UP_IRQ_EMPTY             (1 << 9)
-#define MCPDM_UP_IRQ_ALMST_FULL                (1 << 10)
-#define MCPDM_UP_IRQ_FULL              (1 << 11)
+#define MCPDM_UP_IRQ			(1 << 8)
+#define MCPDM_UP_IRQ_EMPTY		(1 << 9)
+#define MCPDM_UP_IRQ_ALMST_FULL		(1 << 10)
+#define MCPDM_UP_IRQ_FULL		(1 << 11)
 
-#define MCPDM_DOWNLINK_IRQ_MASK                0x00F
-#define MCPDM_UPLINK_IRQ_MASK          0xF00
+#define MCPDM_DOWNLINK_IRQ_MASK		0x00F
+#define MCPDM_UPLINK_IRQ_MASK		0xF00
 
 /*
  * MCPDM_DMAENABLE bit fields
  */
 
-#define DMA_DN_ENABLE          0x1
-#define DMA_UP_ENABLE          0x2
+#define DMA_DN_ENABLE		0x1
+#define DMA_UP_ENABLE		0x2
 
 /*
  * MCPDM_CTRL bit fields
  */
 
-#define PDM_UP1_EN             0x0001
-#define PDM_UP2_EN             0x0002
-#define PDM_UP3_EN             0x0004
-#define PDM_DN1_EN             0x0008
-#define PDM_DN2_EN             0x0010
-#define PDM_DN3_EN             0x0020
-#define PDM_DN4_EN             0x0040
-#define PDM_DN5_EN             0x0080
-#define PDMOUTFORMAT           0x0100
-#define CMD_INT                        0x0200
-#define STATUS_INT             0x0400
-#define SW_UP_RST              0x0800
-#define SW_DN_RST              0x1000
-#define PDM_UP_MASK            0x007
-#define PDM_DN_MASK            0x0F8
-#define PDM_CMD_MASK           0x200
-#define PDM_STATUS_MASK                0x400
-
-
-#define PDMOUTFORMAT_LJUST     (0 << 8)
-#define PDMOUTFORMAT_RJUST     (1 << 8)
+#define PDM_UP1_EN		0x0001
+#define PDM_UP2_EN		0x0002
+#define PDM_UP3_EN		0x0004
+#define PDM_DN1_EN		0x0008
+#define PDM_DN2_EN		0x0010
+#define PDM_DN3_EN		0x0020
+#define PDM_DN4_EN		0x0040
+#define PDM_DN5_EN		0x0080
+#define PDMOUTFORMAT		0x0100
+#define CMD_INT			0x0200
+#define STATUS_INT		0x0400
+#define SW_UP_RST		0x0800
+#define SW_DN_RST		0x1000
+#define PDM_UP_MASK		0x007
+#define PDM_DN_MASK		0x0F8
+#define PDM_CMD_MASK		0x200
+#define PDM_STATUS_MASK		0x400
+
+
+#define PDMOUTFORMAT_LJUST	(0 << 8)
+#define PDMOUTFORMAT_RJUST	(1 << 8)
 
 /*
  * MCPDM_FIFO_CTRL bit fields
  */
 
-#define UP_THRES_MAX           0xF
-#define DN_THRES_MAX           0xF
+#define UP_THRES_MAX		0xF
+#define DN_THRES_MAX		0xF
 
 /*
  * MCPDM_DN_OFFSET bit fields
  */
 
-#define DN_OFST_RX1_EN         0x0001
-#define DN_OFST_RX2_EN         0x0100
+#define DN_OFST_RX1_EN		0x0001
+#define DN_OFST_RX2_EN		0x0100
 
-#define DN_OFST_RX1            1
-#define DN_OFST_RX2            9
-#define DN_OFST_MAX            0x1F
+#define DN_OFST_RX1		1
+#define DN_OFST_RX2		9
+#define DN_OFST_MAX		0x1F
 
-#define MCPDM_UPLINK           1
-#define MCPDM_DOWNLINK         2
+#define MCPDM_UPLINK		1
+#define MCPDM_DOWNLINK		2
 
 struct omap_mcpdm_link {
-       int irq_mask;
-       int threshold;
-       int format;
-       int channels;
+	int irq_mask;
+	int threshold;
+	int format;
+	int channels;
 };
 
 struct omap_mcpdm_platform_data {
-       unsigned long phys_base;
-       u16 irq;
+	unsigned long phys_base;
+	u16 irq;
+
+	int (*device_enable) (struct platform_device *pdev);
+	int (*device_shutdown) (struct platform_device *pdev);
+	int (*device_idle) (struct platform_device *pdev);
 };
 
 struct omap_mcpdm {
-       struct device *dev;
-       unsigned long phys_base;
-       void __iomem *io_base;
-       u8 free;
-       int irq;
-
-       spinlock_t lock;
-       struct omap_mcpdm_platform_data *pdata;
-       struct clk *clk;
-       struct omap_mcpdm_link *downlink;
-       struct omap_mcpdm_link *uplink;
-       struct completion irq_completion;
-
-       int dn_channels;
-       int up_channels;
+	struct device *dev;
+	unsigned long phys_base;
+	void __iomem *io_base;
+	u8 free;
+	int irq;
+
+	spinlock_t lock;
+	struct omap_mcpdm_platform_data *pdata;
+	struct omap_mcpdm_link *downlink;
+	struct omap_mcpdm_link *uplink;
+	struct completion irq_completion;
+
+	int dn_channels;
+	int up_channels;
 };
 
 extern void omap_mcpdm_start(int stream);
diff --git a/sound/soc/omap/omap-abe.c b/sound/soc/omap/omap-abe.c
new file mode 100644
index 000000000000..63e97a8a873b
--- /dev/null
+++ b/sound/soc/omap/omap-abe.c
@@ -0,0 +1,780 @@
+/*
+ * omap-abe.c  --  OMAP ALSA SoC DAI driver using Audio Backend
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Contact: Misael Lopez Cruz <x0052729@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <plat/control.h>
+#include <plat/dma-44xx.h>
+#include <plat/dma.h>
+#include "mcpdm.h"
+#include "omap-pcm.h"
+#include "omap-abe.h"
+#include "../codecs/abe/abe_main.h"
+
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+#include "omap-mcbsp.h"
+#include <plat/mcbsp.h>
+#endif
+
+#define OMAP_ABE_FORMATS	(SNDRV_PCM_FMTBIT_S32_LE)
+
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
+
+static const int omap44xx_dma_reqs[][2] = {
+	{ OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX },
+	{ OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX },
+	{ OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX },
+	{ OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX },
+};
+
+static const unsigned long omap44xx_mcbsp_port[][2] = {
+	{ OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
+	  OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
+	{ OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
+	  OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
+	{ OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
+	  OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
+	{ OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
+	  OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
+};
+#endif
+struct omap_mcpdm_data {
+	struct omap_mcpdm_link *links;
+	int active[2];
+	int requested;
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+	int mcbsp_requested;
+	struct omap_mcbsp_reg_cfg	regs;
+	unsigned int fmt;
+	unsigned int in_freq;
+	int clk_div;
+#endif
+};
+
+static struct omap_mcpdm_link omap_mcpdm_links[] = {
+	/* downlink */
+	{
+		.irq_mask = MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL,
+		.threshold = 1,
+		.format = PDMOUTFORMAT_LJUST,
+		.channels = PDM_DN_MASK | PDM_CMD_MASK,
+	},
+	/* uplink */
+	{
+		.irq_mask = MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL,
+		.threshold = 1,
+		.format = PDMOUTFORMAT_LJUST,
+		.channels = PDM_UP1_EN | PDM_UP2_EN |
+				PDM_DN_MASK | PDM_CMD_MASK,
+	},
+};
+
+static struct omap_mcpdm_data mcpdm_data = {
+	.links = omap_mcpdm_links,
+	.active = {0},
+	.requested = 0,
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+	.mcbsp_requested = 0,
+	.clk_div = 0,
+#endif
+};
+
+/*
+ * Stream DMA parameters
+ */
+static struct omap_pcm_dma_data omap_abe_dai_dma_params[] = {
+	{
+		.name = "Audio playback",
+		.dma_req = OMAP44XX_DMA_ABE_REQ_0,
+		.data_type = OMAP_DMA_DATA_TYPE_S32,
+		.sync_mode = OMAP_DMA_SYNC_PACKET,
+	},
+	{
+		.name = "Audio capture",
+		.dma_req = OMAP44XX_DMA_ABE_REQ_2,
+		.data_type = OMAP_DMA_DATA_TYPE_S32,
+		.sync_mode = OMAP_DMA_SYNC_PACKET,
+	},
+};
+
+static int omap_abe_dai_startup(struct snd_pcm_substream *substream,
+				  struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	int err = 0;
+
+	if (!mcpdm_priv->requested++)
+		err = omap_mcpdm_request();
+
+	return err;
+}
+
+static int omap_abe_dai_trigger(struct snd_pcm_substream *substream, int cmd,
+				  struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcpdm_link *mcpdm_links = mcpdm_priv->links;
+	int stream = substream->stream;
+	int err = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream) {
+			if (!mcpdm_priv->active[stream]++) {
+				err = omap_mcpdm_capture_open(&mcpdm_links[stream]);
+				omap_mcpdm_start(stream);
+			}
+		}
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		break;
+	default:
+		err = -EINVAL;
+	}
+
+	return err;
+}
+
+static void omap_abe_dai_shutdown(struct snd_pcm_substream *substream,
+				    struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+
+	if (!--mcpdm_priv->requested)
+		omap_mcpdm_free();
+}
+
+static int omap_abe_dai_hw_params(struct snd_pcm_substream *substream,
+				    struct snd_pcm_hw_params *params,
+				    struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcpdm_link *mcpdm_links = mcpdm_priv->links;
+	int err=0, stream = substream->stream, dma_req;
+	abe_dma_t dma_params;
+
+	/* get abe dma data */
+	switch (cpu_dai->id) {
+	case OMAP_ABE_MM_DAI:
+		if (stream == SNDRV_PCM_STREAM_CAPTURE) {
+			abe_read_port_address(MM_UL2_PORT, &dma_params);
+			dma_req = OMAP44XX_DMA_ABE_REQ_4;
+		} else {
+			abe_read_port_address(MM_DL_PORT, &dma_params);
+			dma_req = OMAP44XX_DMA_ABE_REQ_0;
+		}
+		break;
+	case OMAP_ABE_TONES_DL_DAI:
+		if (stream == SNDRV_PCM_STREAM_CAPTURE) {
+			return -EINVAL;
+		} else {
+			abe_read_port_address(TONES_DL_PORT, &dma_params);
+			dma_req = OMAP44XX_DMA_ABE_REQ_5;
+		}
+		break;
+	case OMAP_ABE_VOICE_DAI:
+		if (stream == SNDRV_PCM_STREAM_CAPTURE) {
+			abe_read_port_address(VX_UL_PORT, &dma_params);
+			dma_req = OMAP44XX_DMA_ABE_REQ_2;
+		} else {
+			abe_read_port_address(VX_DL_PORT, &dma_params);
+			dma_req = OMAP44XX_DMA_ABE_REQ_1;
+		}
+		break;
+	case OMAP_ABE_DIG_UPLINK_DAI:
+		if (stream == SNDRV_PCM_STREAM_CAPTURE) {
+			abe_read_port_address(MM_UL_PORT, &dma_params);
+			dma_req = OMAP44XX_DMA_ABE_REQ_3;
+
+		} else {
+			return -EINVAL;
+		}
+		break;
+	case OMAP_ABE_VIB_DAI:
+		if (stream == SNDRV_PCM_STREAM_CAPTURE) {
+			return -EINVAL;
+		} else {
+			abe_read_port_address(VIB_DL_PORT, &dma_params);
+                        dma_req = OMAP44XX_DMA_ABE_REQ_6;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	omap_abe_dai_dma_params[stream].dma_req = dma_req;
+	omap_abe_dai_dma_params[stream].port_addr =
+					(unsigned long)dma_params.data;
+	omap_abe_dai_dma_params[stream].packet_size = dma_params.iter;
+	snd_soc_dai_set_dma_data(cpu_dai, substream,
+				 &omap_abe_dai_dma_params[stream]);
+
+	if (!substream->stream) {
+		if (!mcpdm_priv->active[stream]++) {
+			err = omap_mcpdm_playback_open(&mcpdm_links[stream]);
+			msleep(5);
+			omap_mcpdm_start(stream);
+		}
+		/* Increment by 2 because 2 calls of HW free */
+		mcpdm_priv->active[stream]++;
+	}
+
+	return err;
+}
+
+static int omap_abe_dai_hw_free(struct snd_pcm_substream *substream,
+				  struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcpdm_link *mcpdm_links = mcpdm_priv->links;
+	int stream = substream->stream;
+	int err = 0;
+
+	if (mcpdm_priv->active[stream] == 1) {
+		if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			err = omap_mcpdm_playback_close(&mcpdm_links[stream]);
+			if (mcpdm_priv->active[0] == 0)
+				err = omap_mcpdm_capture_close(&mcpdm_links[stream]);
+		}
+		else {
+			if (mcpdm_priv->active[1] == 0)
+				err = omap_mcpdm_capture_close(&mcpdm_links[stream]);
+		}
+		omap_mcpdm_stop(stream);
+		mcpdm_priv->active[stream] = 0;
+	} else if (mcpdm_priv->active[stream] != 0) {
+		mcpdm_priv->active[stream]--;
+	}
+
+	return err;
+}
+
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+static int omap_abe_vx_dai_startup(struct snd_pcm_substream *substream,
+					struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	int err = 0, bus_id = 1, max_period, dma_op_mode;
+
+	if (!mcpdm_priv->requested++) {
+		err = omap_mcpdm_request();
+	}
+	if (!mcpdm_priv->mcbsp_requested++) {
+		omap_mcbsp_request(bus_id);
+
+		dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
+
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
+		else
+			max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
+
+		max_period++;
+		max_period <<= 1;
+
+		if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
+			snd_pcm_hw_constraint_minmax(substream->runtime,
+				SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
+							32, max_period);
+	}
+
+	return err;
+}
+
+static void omap_abe_vx_dai_shutdown(struct snd_pcm_substream *substream,
+				    struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	int bus_id = 1;
+
+	if (!--mcpdm_priv->requested)
+		omap_mcpdm_free();
+
+	if (!--mcpdm_priv->mcbsp_requested)
+		omap_mcbsp_free(bus_id);
+}
+
+static int omap_abe_vx_dai_trigger(struct snd_pcm_substream *substream, int cmd,
+				  struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcpdm_link *mcpdm_links = mcpdm_priv->links;
+	int stream = substream->stream, bus_id = 1;
+	int err = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream) {
+			if (!mcpdm_priv->active[stream]++) {
+				err = omap_mcpdm_capture_open(&mcpdm_links[stream]);
+				omap_mcpdm_start(stream);
+			}
+			omap_mcbsp_start(bus_id, stream, !stream);
+		}
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		break;
+	default:
+		err = -EINVAL;
+	}
+
+	return err;
+}
+
+static int omap_abe_vx_dai_hw_params(struct snd_pcm_substream *substream,
+				    struct snd_pcm_hw_params *params,
+				    struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcpdm_link *mcpdm_links = mcpdm_priv->links;
+	int err = 0, stream = substream->stream, dma_req, dma, bus_id = 1, id = 1;
+	int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
+	unsigned long port;
+	abe_dma_t dma_params;
+	struct omap_mcbsp_reg_cfg *regs = &mcpdm_priv->regs;
+	unsigned int format, framesize, master, div;
+
+	/* get abe dma data */
+	switch (cpu_dai->id) {
+	case OMAP_ABE_VOICE_DAI:
+		if (stream == SNDRV_PCM_STREAM_CAPTURE) {
+			abe_read_port_address(VX_UL_PORT, &dma_params);
+			dma_req = OMAP44XX_DMA_ABE_REQ_2;
+		} else {
+			abe_read_port_address(VX_DL_PORT, &dma_params);
+			dma_req = OMAP44XX_DMA_ABE_REQ_1;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	omap_abe_dai_dma_params[stream].dma_req = dma_req;
+	omap_abe_dai_dma_params[stream].port_addr =
+					(unsigned long)dma_params.data;
+	omap_abe_dai_dma_params[stream].packet_size = dma_params.iter;
+	snd_soc_dai_set_dma_data(cpu_dai, substream,
+				 &omap_abe_dai_dma_params[stream]);
+
+	dma = omap44xx_dma_reqs[bus_id][substream->stream];
+	port = omap44xx_mcbsp_port[bus_id][substream->stream];
+
+	omap_mcbsp_dai_dma_params[id][substream->stream].name =
+	substream->stream ? "Audio Capture" : "Audio Playback";
+	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
+	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
+	omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
+	omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
+							OMAP_DMA_DATA_TYPE_S16;
+
+	format = mcpdm_priv->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
+
+	/* FIX-ME: Using mono format per default */
+	wpf = channels = 1;
+	if (channels == 2 && format == SND_SOC_DAIFMT_I2S) {
+		/* Use dual-phase frames */
+		regs->rcr2	|= RPHASE;
+		regs->xcr2	|= XPHASE;
+		/* Set 1 word per (McBSP) frame for phase1 and phase2 */
+		wpf--;
+		regs->rcr2	|= RFRLEN2(wpf - 1);
+		regs->xcr2	|= XFRLEN2(wpf - 1);
+	}
+
+	regs->rcr1	|= RFRLEN1(wpf - 1);
+	regs->xcr1	|= XFRLEN1(wpf - 1);
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+	case SNDRV_PCM_FORMAT_S32_LE:
+		/* Set word lengths */
+		wlen = 16;
+		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);
+		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);
+		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);
+		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);
+		break;
+	default:
+		/* Unsupported PCM format */
+		return -EINVAL;
+	}
+
+	/* In McBSP master modes, FRAME (i.e. sample rate) is generated
+	 * by _counting_ BCLKs. Calculate frame size in BCLKs */
+	master = mcpdm_priv->fmt & SND_SOC_DAIFMT_MASTER_MASK;
+	if (master == SND_SOC_DAIFMT_CBS_CFS) {
+		div = mcpdm_priv->clk_div ? mcpdm_priv->clk_div : 1;
+		framesize = (mcpdm_priv->in_freq / div) / params_rate(params);
+
+		if (framesize < wlen * channels) {
+			printk(KERN_ERR "%s: not enough bandwidth for desired rate and"
+				"channels\n", __func__);
+			return -EINVAL;
+		}
+	} else {
+		framesize = wlen * channels;
+	}
+
+	/* Set FS period and length in terms of bit clock periods */
+	switch (format) {
+	case SND_SOC_DAIFMT_I2S:
+		regs->srgr2	|= FPER(framesize - 1);
+		regs->srgr1	|= FWID((framesize >> 1) - 1);
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+	case SND_SOC_DAIFMT_DSP_B:
+		regs->srgr2	|= FPER(framesize - 1);
+		regs->srgr1	|= FWID(0);
+		break;
+	}
+
+	omap_mcbsp_config(bus_id, &mcpdm_priv->regs);
+	if (!substream->stream) {
+		if (!mcpdm_priv->active[stream]++) {
+			err = omap_mcpdm_playback_open(&mcpdm_links[stream]);
+			msleep(5);
+			omap_mcpdm_start(stream);
+		}
+		omap_mcbsp_start(bus_id, stream, !stream);
+		/* Increment by 2 because 2 calls of HW free */
+		mcpdm_priv->active[stream]++;
+	}
+
+	return err;
+}
+
+static int omap_abe_vx_dai_hw_free(struct snd_pcm_substream *substream,
+				  struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcpdm_link *mcpdm_links = mcpdm_priv->links;
+	int stream = substream->stream;
+	int err=0, bus_id = 1;
+
+	if (mcpdm_priv->active[stream] == 1) {
+		if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			err = omap_mcpdm_playback_close(&mcpdm_links[stream]);
+			if (mcpdm_priv->active[0] == 0)
+				err = omap_mcpdm_capture_close(&mcpdm_links[stream]);
+		}
+		else {
+			if (mcpdm_priv->active[1] == 0)
+				err = omap_mcpdm_capture_close(&mcpdm_links[stream]);
+		}
+		omap_mcpdm_stop(stream);
+		/* Stop McBSP */
+		omap_mcbsp_stop(bus_id, !stream, stream);
+		mcpdm_priv->active[stream] = 0;
+	} else if (mcpdm_priv->active[stream] != 0) {
+		mcpdm_priv->active[stream]--;
+	}
+
+	return err;
+}
+
+/*
+ * This must be called before _set_clkdiv and _set_sysclk since McBSP register
+ * cache is initialized here
+ */
+static int omap_abe_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
+				      unsigned int fmt)
+{
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcbsp_reg_cfg *regs = &mcpdm_priv->regs;
+	unsigned int temp_fmt = fmt;
+
+	mcpdm_priv->fmt = fmt;
+	memset(regs, 0, sizeof(*regs));
+	/* Generic McBSP register settings */
+	regs->spcr2	|= XINTM(3) | FREE;
+	regs->spcr1	|= RINTM(3);
+
+	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+		regs->xccr = DXENDLY(1) | XDMAEN;
+		regs->rccr = RFULL_CYCLE | RDMAEN;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		/* 1-bit data delay */
+		regs->rcr2	|= RDATDLY(1);
+		regs->xcr2	|= XDATDLY(1);
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+		/* 1-bit data delay */
+		regs->rcr2      |= RDATDLY(1);
+		regs->xcr2      |= XDATDLY(1);
+		/* Invert FS polarity configuration */
+		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
+		break;
+	case SND_SOC_DAIFMT_DSP_B:
+		/* 0-bit data delay */
+		regs->rcr2      |= RDATDLY(0);
+		regs->xcr2      |= XDATDLY(0);
+		/* Invert FS polarity configuration */
+		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
+		break;
+	default:
+		/* Unsupported data format */
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBS_CFS:
+		/* McBSP master. Set FS and bit clocks as outputs */
+		regs->pcr0	|= FSXM | FSRM |
+				   CLKXM | CLKRM;
+		/* Sample rate generator drives the FS */
+		regs->srgr2	|= FSGM;
+		break;
+	case SND_SOC_DAIFMT_CBM_CFM:
+		/* McBSP slave */
+		break;
+	default:
+		/* Unsupported master/slave configuration */
+		return -EINVAL;
+	}
+
+	/* Set bit clock (CLKX/CLKR) and FS polarities */
+	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		/*
+		 * Normal BCLK + FS.
+		 * FS active low. TX data driven on falling edge of bit clock
+		 * and RX data sampled on rising edge of bit clock.
+		 */
+		regs->pcr0	|= FSXP | FSRP |
+				   CLKXP | CLKRP;
+		break;
+	case SND_SOC_DAIFMT_NB_IF:
+		regs->pcr0	|= CLKXP | CLKRP;
+		break;
+	case SND_SOC_DAIFMT_IB_NF:
+		regs->pcr0	|= FSXP | FSRP;
+		break;
+	case SND_SOC_DAIFMT_IB_IF:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int omap_abe_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
+					 int clk_id, unsigned int freq,
+					 int dir)
+{
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcbsp_reg_cfg *regs = &mcpdm_priv->regs;
+	int err = 0;
+
+	mcpdm_priv->in_freq = freq;
+	switch (clk_id) {
+	case OMAP_MCBSP_SYSCLK_CLK:
+		regs->srgr2	|= CLKSM;
+		break;
+	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
+		if (cpu_is_omap44xx()) {
+			regs->srgr2     |= CLKSM;
+			break;
+		}
+	default:
+		err = -ENODEV;
+	}
+
+	return err;
+}
+
+static int omap_abe_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
+						int div_id, int div)
+{
+	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
+	struct omap_mcbsp_reg_cfg *regs = &mcpdm_priv->regs;
+
+	if (div_id != OMAP_MCBSP_CLKGDV)
+		return -ENODEV;
+
+	regs->srgr1 |= CLKGDV(div - 1);
+
+	return 0;
+}
+#endif
+
+static struct snd_soc_dai_ops omap_abe_dai_ops = {
+	.startup	= omap_abe_dai_startup,
+	.shutdown	= omap_abe_dai_shutdown,
+	.trigger        = omap_abe_dai_trigger,
+	.hw_params	= omap_abe_dai_hw_params,
+	.hw_free	= omap_abe_dai_hw_free,
+};
+
+static struct snd_soc_dai_ops omap_abe_vx_dai_ops = {
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+	.startup	= omap_abe_vx_dai_startup,
+	.shutdown	= omap_abe_vx_dai_shutdown,
+	.hw_params	= omap_abe_vx_dai_hw_params,
+	.hw_free	= omap_abe_vx_dai_hw_free,
+	.trigger	= omap_abe_vx_dai_trigger,
+	.set_fmt	= omap_abe_mcbsp_dai_set_dai_fmt,
+	.set_sysclk	= omap_abe_mcbsp_dai_set_dai_sysclk,
+	.set_clkdiv	= omap_abe_mcbsp_dai_set_clkdiv,
+#else
+        .startup        = omap_abe_dai_startup,
+        .shutdown       = omap_abe_dai_shutdown,
+	.trigger        = omap_abe_dai_trigger,
+        .hw_params      = omap_abe_dai_hw_params,
+        .hw_free        = omap_abe_dai_hw_free,
+#endif
+};
+
+struct snd_soc_dai omap_abe_dai[] = {
+	{
+		.name = "omap-abe-mm",
+		.id = OMAP_ABE_MM_DAI,
+		.playback = {
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
+			.formats = OMAP_ABE_FORMATS,
+		},
+		.capture = {
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_48000,
+			.formats = OMAP_ABE_FORMATS,
+		},
+		.ops = &omap_abe_dai_ops,
+		.private_data = &mcpdm_data,
+	},
+	{
+		.name = "omap-abe-tone-dl",
+		.id = OMAP_ABE_TONES_DL_DAI,
+		.playback = {
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
+			.formats = OMAP_ABE_FORMATS,
+		},
+		.ops = &omap_abe_dai_ops,
+		.private_data = &mcpdm_data,
+	},
+	{
+		.name = "omap-abe-voice",
+		.id = OMAP_ABE_VOICE_DAI,
+		.playback = {
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+			.formats = OMAP_ABE_FORMATS,
+		},
+		.capture = {
+			.channels_min = 2,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+			.formats = OMAP_ABE_FORMATS,
+		},
+		.ops = &omap_abe_vx_dai_ops,
+		.private_data = &mcpdm_data,
+	},
+	{
+		.name = "omap-abe-dig-ul",
+		.id = OMAP_ABE_DIG_UPLINK_DAI,
+		.capture = {
+			.channels_min = 2,
+			.channels_max = 8,
+			.rates = SNDRV_PCM_RATE_48000,
+			.formats = OMAP_ABE_FORMATS,
+		},
+		.ops = &omap_abe_dai_ops,
+		.private_data = &mcpdm_data,
+	},
+	{
+		.name = "omap-abe-vib",
+		.id = OMAP_ABE_VIB_DAI,
+		.playback = {
+			.channels_min = 2,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_48000,
+			.formats = OMAP_ABE_FORMATS,
+		},
+		.ops = &omap_abe_dai_ops,
+		.private_data = &mcpdm_data,
+	},
+};
+EXPORT_SYMBOL_GPL(omap_abe_dai);
+
+static int __init snd_omap_abe_init(void)
+{
+	return snd_soc_register_dais(omap_abe_dai, ARRAY_SIZE(omap_abe_dai));
+}
+module_init(snd_omap_abe_init);
+
+static void __exit snd_omap_abe_exit(void)
+{
+	snd_soc_unregister_dais(omap_abe_dai, ARRAY_SIZE(omap_abe_dai));
+}
+module_exit(snd_omap_abe_exit);
+
+MODULE_AUTHOR("Misael Lopez Cruz <x0052729@ti.com>");
+MODULE_DESCRIPTION("OMAP ABE SoC Interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/omap-abe.h b/sound/soc/omap/omap-abe.h
new file mode 100644
index 000000000000..44f23940601f
--- /dev/null
+++ b/sound/soc/omap/omap-abe.h
@@ -0,0 +1,35 @@
+/*
+ * omap-abe.h
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Contact: Misael Lopez Cruz <x0052729@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __OMAP_MCPDM_H__
+#define __OMAP_MCPDM_H__
+
+#define OMAP_ABE_MM_DAI			0
+#define OMAP_ABE_TONES_DL_DAI		1
+#define OMAP_ABE_VOICE_DAI		2
+#define OMAP_ABE_DIG_UPLINK_DAI		3
+#define OMAP_ABE_VIB_DAI		4
+
+extern struct snd_soc_dai omap_abe_dai[];
+
+#endif	/* End of __OMAP_MCPDM_H__ */
diff --git a/sound/soc/omap/omap-hdmi.c b/sound/soc/omap/omap-hdmi.c
new file mode 100644
index 000000000000..e7b39ac685ba
--- /dev/null
+++ b/sound/soc/omap/omap-hdmi.c
@@ -0,0 +1,241 @@
+/*
+ * omap-hdmi.c  --  OMAP ALSA SoC DAI driver for HDMI audio
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Contact: Jorge Candelaria <x0107209@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <plat/control.h>
+#include <plat/dma.h>
+#include "omap-pcm.h"
+#include "omap-hdmi.h"
+
+#define CONFIG_HDMI_NO_IP_MODULE
+#define OMAP_HDMI_RATES	(SNDRV_PCM_RATE_48000)
+
+/* Currently, we support only 16b samples at HDMI */
+#define OMAP_HDMI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
+
+#ifdef CONFIG_HDMI_NO_IP_MODULE
+#include <plat/hdmi_lib.h>
+#else
+struct hdmi_ip_driver hdmi_audio_core;
+#endif
+
+static struct omap_pcm_dma_data omap_hdmi_dai_dma_params = {
+	.name = "HDMI playback",
+	.dma_req = OMAP44XX_DMA_DSS_HDMI_REQ,
+	.port_addr = HDMI_WP + HDMI_WP_AUDIO_DATA,
+	.sync_mode = OMAP_DMA_SYNC_PACKET,
+};
+
+static int omap_hdmi_dai_startup(struct snd_pcm_substream *substream,
+				  struct snd_soc_dai *dai)
+{
+	int err = 0;
+#ifdef CONFIG_HDMI_NO_IP_MODULE
+	err = hdmi_w1_wrapper_enable(HDMI_WP);
+#else
+	if (hdmi_audio_core.module_loaded)
+		err = hdmi_audio_core.wrapper_enable(HDMI_WP);
+	else
+		printk(KERN_WARNING "Warning: hdmi_core.ko is not enabled");
+#endif
+	return err;
+}
+
+static void omap_hdmi_dai_shutdown(struct snd_pcm_substream *substream,
+				    struct snd_soc_dai *dai)
+{
+	int err = 0;
+#ifdef CONFIG_HDMI_NO_IP_MODULE
+	err = hdmi_w1_wrapper_disable(HDMI_WP);
+#else
+	if (hdmi_audio_core.module_loaded)
+		err = hdmi_audio_core.wrapper_disable(HDMI_WP);
+	else
+		printk(KERN_WARNING "Warning: hdmi_core.ko is not enabled");
+#endif
+	return err;
+}
+
+static int omap_hdmi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
+				  struct snd_soc_dai *dai)
+{
+	int err = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+#ifdef CONFIG_HDMI_NO_IP_MODULE
+		err = hdmi_w1_start_audio_transfer(HDMI_WP);
+#else
+		if (hdmi_audio_core.module_loaded)
+			err = hdmi_audio_core.start_audio(HDMI_WP);
+		else
+			printk(KERN_WARNING "Warning: hdmi_core.ko is "
+							"not enabled");
+#endif
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+#ifdef CONFIG_HDMI_NO_IP_MODULE
+		err = hdmi_w1_stop_audio_transfer(HDMI_WP);
+#else
+		if (hdmi_audio_core.module_loaded)
+			err = hdmi_audio_core.stop_audio(HDMI_WP);
+		else
+			printk(KERN_WARNING "Warning: hdmi_core.ko is "
+							"not enabled");
+#endif
+		break;
+	default:
+		err = -EINVAL;
+	}
+
+	return err;
+}
+
+static int omap_hdmi_dai_hw_params(struct snd_pcm_substream *substream,
+				    struct snd_pcm_hw_params *params,
+				    struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	int err = 0;
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+	case SNDRV_PCM_FORMAT_S32_LE:
+		omap_hdmi_dai_dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
+		break;
+
+	default:
+		err = -EINVAL;
+	}
+	omap_hdmi_dai_dma_params.packet_size = 0x20;
+
+	snd_soc_dai_set_dma_data(cpu_dai, substream,
+				 &omap_hdmi_dai_dma_params);
+
+	return err;
+}
+
+static struct snd_soc_dai_ops omap_hdmi_dai_ops = {
+	.startup	= omap_hdmi_dai_startup,
+	.shutdown	= omap_hdmi_dai_shutdown,
+	.trigger	= omap_hdmi_dai_trigger,
+	.hw_params	= omap_hdmi_dai_hw_params,
+};
+
+struct snd_soc_dai omap_hdmi_dai = {
+	.name = "omap-hdmi-dai",
+	.id = -1,
+	.playback = {
+		.channels_min = 2,
+		/* currently we support only stereo HDMI */
+		.channels_max = 2,
+		.rates = OMAP_HDMI_RATES,
+		.formats = OMAP_HDMI_FORMATS,
+	},
+	.ops = &omap_hdmi_dai_ops,
+};
+EXPORT_SYMBOL_GPL(omap_hdmi_dai);
+
+static int __init snd_omap_hdmi_init(void)
+{
+#ifdef CONFIG_HDMI_NO_IP_MODULE
+	hdmi_lib_init();
+#else
+	hdmi_audio_core_stub_init();
+#endif
+	return snd_soc_register_dai(&omap_hdmi_dai);
+}
+module_init(snd_omap_hdmi_init);
+
+static void __exit snd_omap_hdmi_exit(void)
+{
+	snd_soc_unregister_dai(&omap_hdmi_dai);
+}
+module_exit(snd_omap_hdmi_exit);
+
+#ifndef CONFIG_HDMI_NO_IP_MODULE
+
+/* stub */
+int audio_stub_lib_init(void)
+{
+	printk(KERN_WARNING "ERR: please install HDMI IP kernel module\n");
+	return -1;
+}
+void audio_stub_lib_exit(void)
+{
+	printk(KERN_WARNING "HDMI module does not exist!\n");
+}
+
+#define EXPORT_SYMTAB
+
+/* HDMI panel driver */
+void hdmi_audio_core_stub_init(void)
+{
+	hdmi_audio_core.stop_video = NULL;
+	hdmi_audio_core.start_video = NULL;
+	hdmi_audio_core.wrapper_enable = NULL;
+	hdmi_audio_core.wrapper_disable = NULL;
+	hdmi_audio_core.stop_audio = NULL;
+	hdmi_audio_core.start_audio = NULL;
+	hdmi_audio_core.config_video = NULL;
+	hdmi_audio_core.set_wait_pll = NULL;
+	hdmi_audio_core.set_wait_pwr = NULL;
+	hdmi_audio_core.set_wait_srst = NULL;
+	hdmi_audio_core.read_edid = NULL;
+	hdmi_audio_core.ip_init = audio_stub_lib_init;
+	hdmi_audio_core.ip_exit = audio_stub_lib_exit;
+	hdmi_audio_core.module_loaded = 0;
+}
+
+void hdmi_audio_core_lib_set(struct hdmi_ip_driver *ipc)
+{
+	hdmi_audio_core.module_loaded = ipc->module_loaded;
+	if (ipc->module_loaded) {
+		hdmi_audio_core.wrapper_enable = ipc->wrapper_enable;
+		hdmi_audio_core.wrapper_disable = ipc->wrapper_disable;
+		hdmi_audio_core.start_audio = ipc->start_audio;
+		hdmi_audio_core.stop_audio = ipc->stop_audio;
+	}
+}
+EXPORT_SYMBOL(hdmi_audio_core_lib_set);
+
+#endif
+
+
+MODULE_AUTHOR("Jorge Candelaria <x0107209@ti.com");
+MODULE_DESCRIPTION("OMAP HDMI SoC Interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/omap-hdmi.h b/sound/soc/omap/omap-hdmi.h
new file mode 100644
index 000000000000..34142c9a551e
--- /dev/null
+++ b/sound/soc/omap/omap-hdmi.h
@@ -0,0 +1,54 @@
+/*
+ * omap-hdmi.h
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Contact: Jorge Candelaria <x0107209@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __OMAP_HDMI_H__
+#define __OMAP_HDMI_H__
+
+extern struct snd_soc_dai omap_hdmi_dai;
+
+#ifndef CONFIG_HDMI_NO_IP_MODULE
+
+#define HDMI_WP 		0x58006000
+#define HDMI_WP_AUDIO_DATA 	0x8Cul
+
+struct hdmi_ip_driver {
+	int (*stop_video)(u32);
+	int (*start_video)(u32);
+	int (*wrapper_enable)(u32);
+	int (*wrapper_disable)(u32);
+	int (*stop_audio)(u32);
+	int (*start_audio)(u32);
+	int (*config_video)(struct hdmi_timing_t, u32, u32);
+	int (*set_wait_pll)(u32, enum hdmi_pllpwr_cmd);
+	int (*set_wait_pwr)(u32, enum hdmi_phypwr_cmd);
+	int (*set_wait_srst)(void);
+	int (*read_edid)(u32, u8 *d);
+	int (*ip_init)(void);
+	void (*ip_exit)(void);
+	int module_loaded;
+};
+
+extern void hdmi_audio_core_stub_init(void);
+#endif
+
+#endif	/* End of __OMAP_HDMI_H__ */
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 8ad9dc901007..4ae59353eb8e 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -104,6 +104,17 @@ static const int omap24xx_dma_reqs[][2] = {
 static const int omap24xx_dma_reqs[][2] = {};
 #endif
 
+#if defined(CONFIG_ARCH_OMAP4)
+static const int omap44xx_dma_reqs[][2] = {
+	{ OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX },
+	{ OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX },
+	{ OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX },
+	{ OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX },
+};
+#else
+static const int omap44xx_dma_reqs[][2] = {};
+#endif
+
 #if defined(CONFIG_ARCH_OMAP2420)
 static const unsigned long omap2420_mcbsp_port[][2] = {
 	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
@@ -170,6 +181,21 @@ static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 		omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
 }
 
+#if defined(CONFIG_ARCH_OMAP4)
+static const unsigned long omap44xx_mcbsp_port[][2] = {
+	{ OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
+	  OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
+	{ OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
+	  OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
+	{ OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
+	  OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
+	{ OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
+	  OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
+};
+#else
+static const unsigned long omap44xx_mcbsp_port[][2] = {};
+#endif
+
 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 				  struct snd_soc_dai *dai)
 {
@@ -182,7 +208,7 @@ static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 	if (!cpu_dai->active)
 		err = omap_mcbsp_request(bus_id);
 
-	if (cpu_is_omap343x()) {
+	if (cpu_is_omap343x() || cpu_is_omap44xx()) {
 		int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
 		int max_period;
 
@@ -287,6 +313,9 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 		if (omap_mcbsp_get_dma_op_mode(bus_id) ==
 						MCBSP_DMA_MODE_THRESHOLD)
 			sync_mode = OMAP_DMA_SYNC_FRAME;
+	} else if (cpu_is_omap44xx()) {
+		dma = omap44xx_dma_reqs[bus_id][substream->stream];
+		port = omap44xx_mcbsp_port[bus_id][substream->stream];
 	} else {
 		return -ENODEV;
 	}
@@ -295,8 +324,18 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 	omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
-	omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
-							OMAP_DMA_DATA_TYPE_S16;
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
+			 OMAP_DMA_DATA_TYPE_S16;
+		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
+			 OMAP_DMA_DATA_TYPE_S32;
+		break;
+	default:
+		return -EINVAL;
+	}
 
 	snd_soc_dai_set_dma_data(cpu_dai, substream,
 		&omap_mcbsp_dai_dma_params[id][substream->stream]);
@@ -330,6 +369,14 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);
 		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);
 		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		/* Set word lengths */
+		wlen = 32;
+		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_32);
+		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_32);
+		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_32);
+		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_32);
+		break;
 	default:
 		/* Unsupported PCM format */
 		return -EINVAL;
@@ -389,11 +436,11 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 	regs->spcr2	|= XINTM(3) | FREE;
 	regs->spcr1	|= RINTM(3);
 	/* RFIG and XFIG are not defined in 34xx */
-	if (!cpu_is_omap34xx()) {
+	if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
 		regs->rcr2	|= RFIG;
 		regs->xcr2	|= XFIG;
 	}
-	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 		regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 		regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 	}
@@ -582,6 +629,10 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 		regs->srgr2	|= CLKSM;
 		break;
 	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
+		if (cpu_is_omap44xx()) {
+			regs->srgr2     |= CLKSM;
+			break;
+		}
 	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 		err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 		break;
@@ -623,13 +674,15 @@ static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
 		.channels_min = 1,				\
 		.channels_max = 16,				\
 		.rates = OMAP_MCBSP_RATES,			\
-		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
+		.formats = SNDRV_PCM_FMTBIT_S16_LE |		\
+			   SNDRV_PCM_FMTBIT_S32_LE,		\
 	},							\
 	.capture = {						\
 		.channels_min = 1,				\
 		.channels_max = 16,				\
 		.rates = OMAP_MCBSP_RATES,			\
-		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
+		.formats = SNDRV_PCM_FMTBIT_S16_LE |		\
+			   SNDRV_PCM_FMTBIT_S32_LE,		\
 	},							\
 	.ops = &omap_mcbsp_dai_ops,				\
 	.private_data = &mcbsp_data[(link_id)].bus_id,		\
@@ -641,8 +694,10 @@ struct snd_soc_dai omap_mcbsp_dai[] = {
 #if NUM_LINKS >= 3
 	OMAP_MCBSP_DAI_BUILDER(2),
 #endif
-#if NUM_LINKS == 5
+#if NUM_LINKS >= 4
 	OMAP_MCBSP_DAI_BUILDER(3),
+#endif
+#if NUM_LINKS == 5
 	OMAP_MCBSP_DAI_BUILDER(4),
 #endif
 };
diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
index 6c363e5f4387..178c7c73d05f 100644
--- a/sound/soc/omap/omap-mcbsp.h
+++ b/sound/soc/omap/omap-mcbsp.h
@@ -50,6 +50,10 @@ enum omap_mcbsp_div {
 #undef  NUM_LINKS
 #define NUM_LINKS	3
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+#undef  NUM_LINKS
+#define NUM_LINKS	4
+#endif
 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 #undef  NUM_LINKS
 #define NUM_LINKS	5
diff --git a/sound/soc/omap/omap-mcpdm.c b/sound/soc/omap/omap-mcpdm.c
index b7f4f7e015f3..1fe5a2ad6bb5 100644
--- a/sound/soc/omap/omap-mcpdm.c
+++ b/sound/soc/omap/omap-mcpdm.c
@@ -109,36 +109,6 @@ static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
 		omap_mcpdm_free();
 }
 
-static int omap_mcpdm_dai_trigger(struct snd_pcm_substream *substream, int cmd,
-				  struct snd_soc_dai *dai)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
-	struct omap_mcpdm_data *mcpdm_priv = cpu_dai->private_data;
-	int stream = substream->stream;
-	int err = 0;
-
-	switch (cmd) {
-	case SNDRV_PCM_TRIGGER_START:
-	case SNDRV_PCM_TRIGGER_RESUME:
-	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-		if (!mcpdm_priv->active++)
-			omap_mcpdm_start(stream);
-		break;
-
-	case SNDRV_PCM_TRIGGER_STOP:
-	case SNDRV_PCM_TRIGGER_SUSPEND:
-	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-		if (!--mcpdm_priv->active)
-			omap_mcpdm_stop(stream);
-		break;
-	default:
-		err = -EINVAL;
-	}
-
-	return err;
-}
-
 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
 				    struct snd_pcm_hw_params *params,
 				    struct snd_soc_dai *dai)
@@ -183,6 +153,8 @@ static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
 		err = omap_mcpdm_capture_open(&mcpdm_links[stream]);
 	}
 
+	omap_mcpdm_start(stream);
+
 	return err;
 }
 
@@ -201,13 +173,14 @@ static int omap_mcpdm_dai_hw_free(struct snd_pcm_substream *substream,
 	else
 		err = omap_mcpdm_capture_close(&mcpdm_links[stream]);
 
+	omap_mcpdm_stop(stream);
+
 	return err;
 }
 
 static struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
 	.startup	= omap_mcpdm_dai_startup,
 	.shutdown	= omap_mcpdm_dai_shutdown,
-	.trigger	= omap_mcpdm_dai_trigger,
 	.hw_params	= omap_mcpdm_dai_hw_params,
 	.hw_free	= omap_mcpdm_dai_hw_free,
 };
diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/omap-pcm.c
index 1e521904ea64..995c963fa17e 100644
--- a/sound/soc/omap/omap-pcm.c
+++ b/sound/soc/omap/omap-pcm.c
@@ -233,6 +233,11 @@ static int omap_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		prtd->period_index = -1;
 		omap_stop_dma(prtd->dma_ch);
+		/* Since we are using self linking, there is a
+		   chance that the DMA as re-enabled the channel
+		   just after disabling it */
+		while (omap_get_dma_active_status(prtd->dma_ch))
+			omap_stop_dma(prtd->dma_ch);
 		break;
 	default:
 		ret = -EINVAL;
@@ -279,6 +284,14 @@ static int omap_pcm_open(struct snd_pcm_substream *substream)
 	if (ret < 0)
 		goto out;
 
+	/* ABE needs a step of 24 * 4 data bits, and HDMI 32 * 4
+	* Ensure buffer size satisfies both constraints.
+	*/
+	ret = snd_pcm_hw_constraint_step(runtime, 0,
+					 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 384);
+	if (ret < 0)
+		goto out;
+
 	prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
 	if (prtd == NULL) {
 		ret = -ENOMEM;
diff --git a/sound/soc/omap/sdp4430.c b/sound/soc/omap/sdp4430.c
new file mode 100644
index 000000000000..1373a9164217
--- /dev/null
+++ b/sound/soc/omap/sdp4430.c
@@ -0,0 +1,400 @@
+/*
+ * sdp4430.c  --  SoC audio for TI OMAP4430 SDP
+ *
+ * Author: Misael Lopez Cruz <x0052729@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/jack.h>
+
+#include <asm/mach-types.h>
+#include <plat/hardware.h>
+#include <plat/mux.h>
+
+#include "mcpdm.h"
+#include "omap-abe.h"
+#include "omap-pcm.h"
+#include "omap-mcbsp.h"
+#include "../codecs/twl6040.h"
+#include "../codecs/abe-twl6040.h"
+
+#ifdef CONFIG_SND_OMAP_SOC_HDMI
+#include "omap-hdmi.h"
+#endif
+
+static int twl6040_power_mode;
+static struct snd_soc_card snd_soc_sdp4430;
+
+static int sdp4430_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+	int clk_id, freq;
+	int ret;
+
+	if (twl6040_power_mode) {
+		clk_id = TWL6040_SYSCLK_SEL_HPPLL;
+		freq = 38400000;
+	} else {
+		clk_id = TWL6040_SYSCLK_SEL_LPPLL;
+		freq = 32768;
+	}
+
+	/* set the codec mclk */
+	ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, freq,
+				SND_SOC_CLOCK_IN);
+	if (ret) {
+		printk(KERN_ERR "can't set codec system clock\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static struct snd_soc_ops sdp4430_ops = {
+	.hw_params = sdp4430_hw_params,
+};
+
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+static int sdp4430_voice_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	int clk_id, freq;
+	int ret;
+
+	if (twl6040_power_mode) {
+		clk_id = TWL6040_SYSCLK_SEL_HPPLL;
+		freq = 38400000;
+	} else {
+		clk_id = TWL6040_SYSCLK_SEL_LPPLL;
+		freq = 32768;
+	}
+
+	/* set the codec mclk */
+	ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, freq,
+				SND_SOC_CLOCK_IN);
+	if (ret) {
+		printk(KERN_ERR "can't set codec system clock\n");
+		return ret;
+	}
+
+	/* Set cpu DAI configuration */
+	ret = snd_soc_dai_set_fmt(cpu_dai,
+				  SND_SOC_DAIFMT_I2S |
+				  SND_SOC_DAIFMT_NB_NF |
+				  SND_SOC_DAIFMT_CBM_CFM);
+	if (ret < 0) {
+		printk(KERN_ERR "can't set cpu DAI configuration\n");
+		return ret;
+	}
+
+	/* Set McBSP clock to external */
+	ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_FCLK,
+				     64 * params_rate(params),
+				     SND_SOC_CLOCK_IN);
+	if (ret < 0) {
+		printk(KERN_ERR "can't set cpu system clock\n");
+		return ret;
+	}
+
+	ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, 193);
+	if (ret < 0) {
+		printk(KERN_ERR "can't set cpu clock div\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static struct snd_soc_ops sdp4430_voice_ops = {
+	.hw_params = sdp4430_voice_hw_params,
+};
+#endif
+
+/* Headset jack */
+static struct snd_soc_jack hs_jack;
+
+/*Headset jack detection DAPM pins */
+static struct snd_soc_jack_pin hs_jack_pins[] = {
+	{
+		.pin = "Headset Mic",
+		.mask = SND_JACK_MICROPHONE,
+	},
+	{
+		.pin = "Headset Stereophone",
+		.mask = SND_JACK_HEADPHONE,
+	},
+};
+
+static int sdp4430_get_power_mode(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.integer.value[0] = twl6040_power_mode;
+	return 0;
+}
+
+static int sdp4430_set_power_mode(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	if (twl6040_power_mode == ucontrol->value.integer.value[0])
+		return 0;
+
+	twl6040_power_mode = ucontrol->value.integer.value[0];
+
+	return 1;
+}
+
+static const char *power_texts[] = {"Low-Power", "High-Performance"};
+
+static const struct soc_enum sdp4430_enum[] = {
+	SOC_ENUM_SINGLE_EXT(2, power_texts),
+};
+
+static const struct snd_kcontrol_new sdp4430_controls[] = {
+	SOC_ENUM_EXT("TWL6040 Power Mode", sdp4430_enum[0],
+		sdp4430_get_power_mode, sdp4430_set_power_mode),
+};
+
+/* SDP4430 machine DAPM */
+static const struct snd_soc_dapm_widget sdp4430_twl6040_dapm_widgets[] = {
+	SND_SOC_DAPM_MIC("Ext Mic", NULL),
+	SND_SOC_DAPM_SPK("Ext Spk", NULL),
+	SND_SOC_DAPM_MIC("Headset Mic", NULL),
+	SND_SOC_DAPM_HP("Headset Stereophone", NULL),
+	SND_SOC_DAPM_SPK("Earphone Spk", NULL),
+	SND_SOC_DAPM_INPUT("Aux/FM Stereo In"),
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+	/* External Mics: MAINMIC, SUBMIC with bias*/
+	{"MAINMIC", NULL, "Main Mic Bias"},
+	{"SUBMIC", NULL, "Main Mic Bias"},
+	{"Main Mic Bias", NULL, "Ext Mic"},
+
+	/* External Speakers: HFL, HFR */
+	{"Ext Spk", NULL, "HFL"},
+	{"Ext Spk", NULL, "HFR"},
+
+	/* Headset Mic: HSMIC with bias */
+	{"HSMIC", NULL, "Headset Mic Bias"},
+	{"Headset Mic Bias", NULL, "Headset Mic"},
+
+	/* Headset Stereophone (Headphone): HSOL, HSOR */
+	{"Headset Stereophone", NULL, "HSOL"},
+	{"Headset Stereophone", NULL, "HSOR"},
+
+	/* Earphone speaker */
+	{"Earphone Spk", NULL, "EP"},
+
+	/* Aux/FM Stereo In: AFML, AFMR */
+	{"AFML", NULL, "Aux/FM Stereo In"},
+	{"AFMR", NULL, "Aux/FM Stereo In"},
+};
+
+static int sdp4430_twl6040_init(struct snd_soc_codec *codec)
+{
+	int ret;
+
+	/* Add SDP4430 specific controls */
+	ret = snd_soc_add_controls(codec, sdp4430_controls,
+				ARRAY_SIZE(sdp4430_controls));
+	if (ret)
+		return ret;
+
+	/* Add SDP4430 specific widgets */
+	ret = snd_soc_dapm_new_controls(codec, sdp4430_twl6040_dapm_widgets,
+				ARRAY_SIZE(sdp4430_twl6040_dapm_widgets));
+	if (ret)
+		return ret;
+
+	/* Set up SDP4430 specific audio path audio_map */
+	snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+
+	/* SDP4430 connected pins */
+	snd_soc_dapm_enable_pin(codec, "Ext Mic");
+	snd_soc_dapm_enable_pin(codec, "Ext Spk");
+	snd_soc_dapm_enable_pin(codec, "AFML");
+	snd_soc_dapm_enable_pin(codec, "AFMR");
+	snd_soc_dapm_disable_pin(codec, "Headset Mic");
+	snd_soc_dapm_disable_pin(codec, "Headset Stereophone");
+
+	ret = snd_soc_dapm_sync(codec);
+	if (ret)
+		return ret;
+
+	/*Headset jack detection */
+	ret = snd_soc_jack_new(&snd_soc_sdp4430, "Headset Jack",
+				SND_JACK_HEADSET, &hs_jack);
+	if (ret)
+		return ret;
+
+	ret = snd_soc_jack_add_pins(&hs_jack, ARRAY_SIZE(hs_jack_pins),
+				hs_jack_pins);
+
+	twl6040_hs_jack_detect(codec, &hs_jack, SND_JACK_HEADSET);
+
+	return ret;
+}
+
+#ifdef CONFIG_SND_OMAP_SOC_HDMI
+struct snd_soc_dai null_dai = {
+	.name = "null",
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 2,
+		.channels_max = 8,
+		.rates = SNDRV_PCM_RATE_48000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
+	},
+};
+#endif
+
+/* Digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link sdp4430_dai[] = {
+	{
+		.name = "abe-twl6040",
+		.stream_name = "Multimedia",
+		.cpu_dai = &omap_abe_dai[OMAP_ABE_MM_DAI],
+		.codec_dai = &abe_dai[0],
+		.init = sdp4430_twl6040_init,
+		.ops = &sdp4430_ops,
+	},
+	{
+		.name = "abe-twl6040",
+		.stream_name = "Tones DL",
+		.cpu_dai = &omap_abe_dai[OMAP_ABE_TONES_DL_DAI],
+		.codec_dai = &abe_dai[1],
+		.ops = &sdp4430_ops,
+	},
+	{
+		.name = "abe-twl6040",
+		.stream_name = "Voice",
+		.cpu_dai = &omap_abe_dai[OMAP_ABE_VOICE_DAI],
+		.codec_dai = &abe_dai[2],
+#ifdef CONFIG_SND_OMAP_VOICE_TEST
+		.ops = &sdp4430_voice_ops,
+#else
+		.ops = &sdp4430_ops,
+#endif
+	},
+	{
+		.name = "abe-twl6040",
+		.stream_name = "Digital Uplink",
+		.cpu_dai = &omap_abe_dai[OMAP_ABE_DIG_UPLINK_DAI],
+		.codec_dai = &abe_dai[3],
+		.ops = &sdp4430_ops,
+	},
+	{
+		.name = "abe-twl6040",
+		.stream_name = "Vibrator",
+		.cpu_dai = &omap_abe_dai[OMAP_ABE_VIB_DAI],
+		.codec_dai = &abe_dai[4],
+		.ops = &sdp4430_ops,
+	},
+#ifdef CONFIG_SND_OMAP_SOC_HDMI
+	{
+		.name = "hdmi",
+		.stream_name = "HDMI",
+		.cpu_dai = &omap_hdmi_dai,
+		.codec_dai = &null_dai,
+	},
+#endif
+};
+
+/* Audio machine driver */
+static struct snd_soc_card snd_soc_sdp4430 = {
+	.name = "SDP4430",
+	.platform = &omap_soc_platform,
+	.dai_link = sdp4430_dai,
+	.num_links = ARRAY_SIZE(sdp4430_dai),
+};
+
+/* Audio subsystem */
+static struct snd_soc_device sdp4430_snd_devdata = {
+	.card = &snd_soc_sdp4430,
+	.codec_dev = &soc_codec_dev_abe_twl6040,
+};
+
+static struct platform_device *sdp4430_snd_device;
+
+static int __init sdp4430_soc_init(void)
+{
+	int ret;
+
+	if (!machine_is_omap_4430sdp()) {
+		pr_debug("Not SDP4430!\n");
+		return -ENODEV;
+	}
+	printk(KERN_INFO "SDP4430 SoC init\n");
+
+#ifdef CONFIG_SND_OMAP_SOC_HDMI
+	snd_soc_register_dais(&null_dai, 1);
+#endif
+
+	sdp4430_snd_device = platform_device_alloc("soc-audio", -1);
+	if (!sdp4430_snd_device) {
+		printk(KERN_ERR "Platform device allocation failed\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(sdp4430_snd_device, &sdp4430_snd_devdata);
+	sdp4430_snd_devdata.dev = &sdp4430_snd_device->dev;
+
+	ret = platform_device_add(sdp4430_snd_device);
+	if (ret)
+		goto err;
+
+	ret = snd_soc_dai_set_sysclk(sdp4430_dai[0].codec_dai,
+				TWL6040_SYSCLK_SEL_HPPLL, 38400000,
+				SND_SOC_CLOCK_IN);
+	if (ret) {
+		printk(KERN_ERR "can't set codec system clock\n");
+		goto err;
+	}
+
+	/* Codec starts in HP mode */
+	twl6040_power_mode = 1;
+
+	return 0;
+
+err:
+	printk(KERN_ERR "Unable to add platform device\n");
+	platform_device_put(sdp4430_snd_device);
+	return ret;
+}
+module_init(sdp4430_soc_init);
+
+static void __exit sdp4430_soc_exit(void)
+{
+	platform_device_unregister(sdp4430_snd_device);
+}
+module_exit(sdp4430_soc_exit);
+
+MODULE_AUTHOR("Misael Lopez Cruz <x0052729@ti.com>");
+MODULE_DESCRIPTION("ALSA SoC SDP4430");
+MODULE_LICENSE("GPL");
+
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index ad7f9528d751..9cf39cecfb3e 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -566,16 +566,18 @@ static int soc_codec_close(struct snd_pcm_substream *substream)
 		platform->pcm_ops->close(substream);
 	cpu_dai->runtime = NULL;
 
-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		/* start delayed pop wq here for playback streams */
-		codec_dai->pop_wait = 1;
-		schedule_delayed_work(&card->delayed_work,
-			msecs_to_jiffies(card->pmdown_time));
-	} else {
-		/* capture streams can be powered down now */
-		snd_soc_dapm_stream_event(codec,
-			codec_dai->capture.stream_name,
-			SND_SOC_DAPM_STREAM_STOP);
+	if (!codec->active) {
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			/* start delayed pop wq here for playback streams */
+			codec_dai->pop_wait = 1;
+			schedule_delayed_work(&card->delayed_work,
+				msecs_to_jiffies(card->pmdown_time));
+		} else {
+			/* capture streams can be powered down now */
+			snd_soc_dapm_stream_event(codec,
+				codec_dai->capture.stream_name,
+				SND_SOC_DAPM_STREAM_STOP);
+		}
 	}
 
 	mutex_unlock(&pcm_mutex);
@@ -749,8 +751,8 @@ static int soc_pcm_hw_free(struct snd_pcm_substream *substream)
 	mutex_lock(&pcm_mutex);
 
 	/* apply codec digital mute */
-	if (!codec->active)
-		snd_soc_dai_digital_mute(codec_dai, 1);
+	/* Codec to take of no active stream */
+	snd_soc_dai_digital_mute(codec_dai, 1);
 
 	/* free any machine hw params */
 	if (machine->ops && machine->ops->hw_free)