diff options
95 files changed, 3443 insertions, 1541 deletions
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt new file mode 100644 index 000000000000..f8d405897a94 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -0,0 +1,221 @@ +* Marvell EBU PCIe interfaces + +Mandatory properties: +- compatible: one of the following values: + marvell,armada-370-pcie + marvell,armada-xp-pcie + marvell,kirkwood-pcie +- #address-cells, set to <3> +- #size-cells, set to <2> +- #interrupt-cells, set to <1> +- bus-range: PCI bus numbers covered +- device_type, set to "pci" +- ranges: ranges for the PCI memory and I/O regions, as well as the + MMIO registers to control the PCIe interfaces. + +In addition, the Device Tree node must have sub-nodes describing each +PCIe interface, having the following mandatory properties: +- reg: used only for interrupt mapping, so only the first four bytes + are used to refer to the correct bus number and device number. +- assigned-addresses: reference to the MMIO registers used to control + this PCIe interface. +- clocks: the clock associated to this PCIe interface +- marvell,pcie-port: the physical PCIe port number +- status: either "disabled" or "okay" +- device_type, set to "pci" +- #address-cells, set to <3> +- #size-cells, set to <2> +- #interrupt-cells, set to <1> +- ranges, empty property. +- interrupt-map-mask and interrupt-map, standard PCI properties to + define the mapping of the PCIe interface to interrupt numbers. + +and the following optional properties: +- marvell,pcie-lane: the physical PCIe lane number, for ports having + multiple lanes. If this property is not found, we assume that the + value is 0. + +Example: + +pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + }; + + pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + }; + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; +}; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5543d36c2834..20bb83fca873 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -502,6 +502,7 @@ config ARCH_DOVE config ARCH_KIRKWOOD bool "Marvell Kirkwood" + select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select CPU_FEROCEON select GENERIC_CLOCKEVENTS diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 80a4603857bb..9f0144f34f0e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -64,6 +64,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ + kirkwood-db-88f6281.dtb \ + kirkwood-db-88f6282.dtb \ kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ @@ -84,6 +86,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-ns2max.dtb \ kirkwood-ns2mini.dtb \ kirkwood-nsa310.dtb \ + kirkwood-sheevaplug.dtb \ + kirkwood-sheevaplug-esata.dtb \ kirkwood-topkick.dtb \ kirkwood-ts219-6281.dtb \ kirkwood-ts219-6282.dtb \ diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 2353b1f13704..beee1699d49e 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -74,6 +74,7 @@ */ status = "disabled"; /* No CD or WP GPIOs */ + broken-cd; }; usb@50000 { diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 14e36e19d515..45b107763e3b 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -99,6 +99,7 @@ * No CD or WP GPIOs: SDIO interface used for * Wifi/Bluetooth chip */ + broken-cd; }; usb@50000 { diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 130f8390a7e4..89c21106cfa9 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -64,6 +64,7 @@ pinctrl-names = "default"; status = "okay"; /* No CD or WP GPIOs */ + broken-cd; }; usb@50000 { diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 550eb772c30e..8f3d7bc07b93 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -80,7 +80,7 @@ sata@a0000 { compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; + reg = <0xa0000 0x5000>; interrupts = <55>; clocks = <&gateclk 15>, <&gateclk 30>; clock-names = "0", "1"; @@ -96,7 +96,7 @@ ethernet@70000 { compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x2500>; + reg = <0x70000 0x4000>; interrupts = <8>; clocks = <&gateclk 4>; status = "disabled"; @@ -104,7 +104,7 @@ ethernet@74000 { compatible = "marvell,armada-370-neta"; - reg = <0x74000 0x2500>; + reg = <0x74000 0x4000>; interrupts = <10>; clocks = <&gateclk 3>; status = "disabled"; @@ -143,6 +143,10 @@ reg = <0xd4000 0x200>; interrupts = <54>; clocks = <&gateclk 17>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index d6cc8bf8272e..f5fc1a3868a2 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -30,6 +30,9 @@ }; soc { + ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ + 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ + internal-regs { serial@12000 { clock-frequency = <250000000>; @@ -97,6 +100,7 @@ pinctrl-names = "default"; status = "okay"; /* No CD or WP GPIOs */ + broken-cd; }; usb@50000 { @@ -155,6 +159,35 @@ status = "okay"; }; }; + + devbus-bootcs@10400 { + status = "okay"; + ranges = <0 0xf0000000 0x1000000>; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 3ee63d128e27..0a040705a72d 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -104,6 +104,16 @@ phy-mode = "rgmii-id"; }; + /* Front-side USB slot */ + usb@50000 { + status = "okay"; + }; + + /* Back-side USB slot */ + usb@51000 { + status = "okay"; + }; + spi0: spi@10600 { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 6ab56bd35de9..488ca5eb9a55 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -107,7 +107,7 @@ ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x2500>; + reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 46b785064dd8..685ee7a282e3 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -137,13 +137,22 @@ nr-ports = <2>; status = "okay"; }; + + /* Front side USB 0 */ usb@50000 { status = "okay"; }; + + /* Front side USB 1 */ usb@51000 { status = "okay"; }; + /* USB interface in the mini-PCIe connector */ + usb@52000 { + status = "okay"; + }; + devbus-bootcs@10400 { status = "okay"; ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 5b902f9a3af2..1ee8540b0eba 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -88,7 +88,7 @@ ethernet@30000 { compatible = "marvell,armada-370-neta"; - reg = <0x30000 0x2500>; + reg = <0x30000 0x4000>; interrupts = <12>; clocks = <&gateclk 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 7e3065abd751..5cae2ab69762 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -44,11 +44,60 @@ gpio = <&gpio0 1 0>; }; }; + + clocks { + /* 25MHz reference crystal */ + ref25: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; }; &uart0 { status = "okay"; }; &sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + si5351: clock-generator { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* connect xtal input to 25MHz reference */ + clocks = <&ref25>; + + /* connect xtal input as source of pll0 and pll1 */ + silabs,pll-source = <0 0>, <1 0>; + + clkout0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + }; + + clkout1 { + reg = <1>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + silabs,pll-master; + }; + + clkout2 { + reg = <2>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + }; + }; +}; &sdio0 { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index d6c9d65cbaeb..c40b779f54f4 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -40,5 +40,64 @@ marvell,function = "sdio"; }; }; + + rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + status = "disabled"; + }; + + mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 23991e45bc55..a63a11137262 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -49,6 +49,34 @@ }; }; + rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + status = "disabled"; + }; + + mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + thermal@10078 { compatible = "marvell,kirkwood-thermal"; reg = <0x10078 0x4>; @@ -65,5 +93,53 @@ clocks = <&gate_clk 7>; status = "disabled"; }; + + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 10>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 18>; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 5f21d4e427b0..00c48d26de68 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -18,10 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_spi &pmx_uart0 - &pmx_cloudbox_sata0 >; - pinctrl-names = "default"; - pmx_cloudbox_sata0: pmx-cloudbox-sata0 { marvell,pins = "mpp15"; marvell,function = "sata0"; @@ -29,16 +25,22 @@ }; serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; clock-frequency = <166666667>; status = "okay"; }; sata@80000 { + pinctrl-0 = <&pmx_cloudbox_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; spi@10600 { + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts new file mode 100644 index 000000000000..9d777edd1f36 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -0,0 +1,30 @@ +/* + * Marvell DB-88F6281-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "kirkwood-db.dtsi" +/include/ "kirkwood-6281.dtsi" + +/ { + model = "Marvell DB-88F6281-BP Development Board"; + compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts new file mode 100644 index 000000000000..f4c852886d23 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -0,0 +1,34 @@ +/* + * Marvell DB-88F6282-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "kirkwood-db.dtsi" +/include/ "kirkwood-6282.dtsi" + +/ { + model = "Marvell DB-88F6282-BP Development Board"; + compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + ocp@f1000000 { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie@2,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi new file mode 100644 index 000000000000..c87cfb816120 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -0,0 +1,89 @@ +/* + * Marvell DB-{88F6281,88F6282}-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common between the 6281 + * and 6282 variants of the Marvell Kirkwood Development Board. + */ + +/include/ "kirkwood.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + pinctrl@10000 { + pmx_sdio_gpios: pmx-sdio-gpios { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x1fb00000>; + }; + }; + + sata@80000 { + nr-ports = <2>; + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio_gpios>; + pinctrl-names = "default"; + wp-gpios = <&gpio1 5 0>; + cd-gpios = <&gpio1 6 0>; + status = "okay"; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index c9c44b2f62d7..14d4ceea3057 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -17,6 +17,11 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320 + &pmx_led_red_left_hdd &pmx_led_red_right_hdd + &pmx_led_white_usb>; + pinctrl-names = "default"; + blue-power { label = "dns320:blue:power"; gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ @@ -46,6 +51,8 @@ }; serial@12100 { + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index e4e4930dc5cf..63872570e6ce 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts @@ -17,6 +17,11 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 + &pmx_led_red_left_hdd &pmx_led_red_right_hdd + &pmx_led_white_usb>; + pinctrl-names = "default"; + white-power { label = "dns325:white:power"; gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 6875ac00c174..0afe1d07c803 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -9,6 +9,10 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_power &pmx_button_unmount + &pmx_button_reset>; + pinctrl-names = "default"; + button@1 { label = "Power button"; linux,code = <116>; @@ -29,6 +33,8 @@ gpio_fan { /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; + pinctrl-names = "default"; gpios = <&gpio1 14 1 &gpio1 13 1>; gpio-fan,speed-map = <0 0 @@ -38,27 +44,17 @@ gpio_poweroff { compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; gpios = <&gpio1 4 0>; }; ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_nand &pmx_uart1 - &pmx_sata0 &pmx_sata1 - &pmx_led_power - &pmx_led_red_right_hdd - &pmx_led_red_left_hdd - &pmx_led_red_usb_325 - &pmx_button_power - &pmx_led_red_usb_320 - &pmx_power_off &pmx_power_back_on - &pmx_power_sata0 &pmx_power_sata1 - &pmx_present_sata0 &pmx_present_sata1 - &pmx_led_white_usb &pmx_fan_tacho - &pmx_fan_high_speed &pmx_fan_low_speed - &pmx_button_unmount &pmx_button_reset - &pmx_temp_alarm >; + pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 + &pmx_present_sata1 &pmx_fan_tacho + &pmx_temp_alarm>; pinctrl-names = "default"; pmx_sata0: pmx-sata0 { @@ -147,11 +143,15 @@ }; }; sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; status = "okay"; nr-ports = <2>; }; nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; status = "okay"; chip-delay = <35>; @@ -192,6 +192,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; + pinctrl-names = "default"; sata0_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 0196cf6b0ef2..7714742bb8d8 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -18,11 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_usb_power_enable - &pmx_led_green &pmx_led_orange >; - pinctrl-names = "default"; - pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; marvell,function = "gpio"; @@ -62,6 +57,8 @@ }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_green &pmx_led_orange>; + pinctrl-names = "default"; health { label = "status:green:health"; @@ -77,6 +74,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; usb_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 289e51d86372..36c7ba38d500 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -18,12 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_spi - &pmx_led_bluetooth &pmx_led_wifi - &pmx_led_wifi_ap >; - pinctrl-names = "default"; - pmx_led_bluetooth: pmx-led-bluetooth { marvell,pins = "mpp47"; marvell,function = "gpio"; @@ -43,6 +37,8 @@ spi@10600 { status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; m25p40@0 { #address-cells = <1>; @@ -79,11 +75,15 @@ pinctrl-names = "default"; status = "okay"; /* No CD or WP GPIOs */ + broken-cd; }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi + &pmx_led_wifi_ap >; + pinctrl-names = "default"; bluetooth { label = "dreamplug:blue:bluetooth"; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index c3573be7b92c..31caa6405065 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -18,15 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange - &pmx_led_left_cap_0 &pmx_led_left_cap_1 - &pmx_led_left_cap_2 &pmx_led_left_cap_3 - &pmx_led_right_cap_0 &pmx_led_right_cap_1 - &pmx_led_right_cap_2 &pmx_led_right_cap_3 - >; - pinctrl-names = "default"; - pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; marvell,function = "gpio"; @@ -109,6 +100,13 @@ }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_orange + &pmx_led_left_cap_0 &pmx_led_left_cap_1 + &pmx_led_left_cap_2 &pmx_led_left_cap_3 + &pmx_led_right_cap_0 &pmx_led_right_cap_1 + &pmx_led_right_cap_2 &pmx_led_right_cap_3 + >; + pinctrl-names = "default"; health { label = "status:green:health"; @@ -156,6 +154,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; usb_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 44fd97dfc1f3..1e642f39b154 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -18,11 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g - &pmx_led_wmode_r &pmx_led_wmode_g >; - pinctrl-names = "default"; - pmx_led_health_r: pmx-led-health-r { marvell,pins = "mpp46"; marvell,function = "gpio"; @@ -72,11 +67,16 @@ mvsdio@90000 { status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g + &pmx_led_wmode_r &pmx_led_wmode_g >; + pinctrl-names = "default"; health-r { label = "guruplug:red:health"; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 5335b1aa8601..20c4b081f420 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -18,13 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_nand - &pmx_led_os_red &pmx_power_off - &pmx_led_os_green &pmx_led_usb_transfer - &pmx_button_reset &pmx_button_usb_copy >; - pinctrl-names = "default"; - pmx_led_os_red: pmx-led-os-red { marvell,pins = "mpp22"; marvell,function = "gpio"; @@ -61,6 +54,8 @@ nand@3000000 { status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; partition@0 { label = "u-boot"; @@ -84,6 +79,9 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; + pinctrl-names = "default"; + button@1 { label = "USB Copy"; linux,code = <133>; @@ -97,6 +95,9 @@ }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green + &pmx_led_usb_transfer>; + pinctrl-names = "default"; green-os { label = "ib62x0:green:os"; @@ -114,6 +115,8 @@ }; gpio_poweroff { compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_power_off>; + pinctrl-names = "default"; gpios = <&gpio0 24 0>; }; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 12ccf74ac3c4..441204e8abc6 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -20,51 +20,43 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35 - &pmx_gpio_41 &pmx_gpio_42 - &pmx_gpio_43 &pmx_gpio_44 - &pmx_gpio_45 &pmx_gpio_46 - &pmx_gpio_47 &pmx_gpio_48 >; - pinctrl-names = "default"; - - pmx_gpio_12: pmx-gpio-12 { + pmx_button_reset: pmx-button-reset { marvell,pins = "mpp12"; marvell,function = "gpio"; }; - pmx_gpio_35: pmx-gpio-35 { + pmx_button_otb: pmx-button-otb { marvell,pins = "mpp35"; marvell,function = "gpio"; }; - pmx_gpio_41: pmx-gpio-41 { + pmx_led_level: pmx-led-level { marvell,pins = "mpp41"; marvell,function = "gpio"; }; - pmx_gpio_42: pmx-gpio-42 { + pmx_led_power_blue: pmx-led-power-blue { marvell,pins = "mpp42"; marvell,function = "gpio"; }; - pmx_gpio_43: pmx-gpio-43 { + pmx_led_power_red: pmx-power-red { marvell,pins = "mpp43"; marvell,function = "gpio"; }; - pmx_gpio_44: pmx-gpio-44 { + pmx_led_usb1: pmx-led-usb1 { marvell,pins = "mpp44"; marvell,function = "gpio"; }; - pmx_gpio_45: pmx-gpio-45 { + pmx_led_usb2: pmx-led-usb2 { marvell,pins = "mpp45"; marvell,function = "gpio"; }; - pmx_gpio_46: pmx-gpio-46 { + pmx_led_usb3: pmx-led-usb3 { marvell,pins = "mpp46"; marvell,function = "gpio"; }; - pmx_gpio_47: pmx-gpio-47 { + pmx_led_usb4: pmx-led-usb4 { marvell,pins = "mpp47"; marvell,function = "gpio"; }; - pmx_gpio_48: pmx-gpio-48 { + pmx_led_otb: pmx-led-otb { marvell,pins = "mpp48"; marvell,function = "gpio"; }; @@ -109,10 +101,23 @@ reg = <0x980000 0x1f400000>; }; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_level &pmx_led_power_blue + &pmx_led_power_red &pmx_led_usb1 + &pmx_led_usb2 &pmx_led_usb3 + &pmx_led_usb4 &pmx_led_otb >; + pinctrl-names = "default"; led-level { label = "led_level"; @@ -154,6 +159,9 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; + pinctrl-names = "default"; + button@1 { label = "OTB Button"; linux,code = <133>; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 3694e94f6e99..00a7bfe5e83b 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -18,12 +18,7 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_button_reset &pmx_button_power - &pmx_led_backup &pmx_led_power - &pmx_button_otb &pmx_led_rebuild - &pmx_led_health - &pmx_led_sata_brt_ctrl_1 + pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 &pmx_led_sata_brt_ctrl_2 &pmx_led_backup_brt_ctrl_1 &pmx_led_backup_brt_ctrl_2 @@ -151,6 +146,9 @@ }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_backup &pmx_led_power + &pmx_led_rebuild &pmx_led_health >; + pinctrl-names = "default"; power_led { label = "status:white:power_led"; @@ -174,6 +172,11 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_reset &pmx_button_power + &pmx_button_otb>; + pinctrl-names = "default"; + + Power { label = "Power Button"; linux,code = <116>; diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts index 0bdce0ad7277..c3f036b86cca 100644 --- a/arch/arm/boot/dts/kirkwood-is2.dts +++ b/arch/arm/boot/dts/kirkwood-is2.dts @@ -13,6 +13,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 5bbd0542cdd3..5d9f5ea78700 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -18,9 +18,7 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda - &pmx_i2c_gpio_scl >; + pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; pinctrl-names = "default"; pmx_i2c_gpio_sda: pmx-gpio-sda { @@ -38,8 +36,17 @@ }; nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; status = "ok"; chip-delay = <25>; }; }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = < &gpio0 8 0 /* sda */ + &gpio0 9 0 >; /* scl */ + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + }; }; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 37d45c4f88fb..31b17f5b9d28 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -8,16 +8,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus - &pmx_fan_low &pmx_fan_high - &pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_fan_lock &pmx_button_function - &pmx_power_switch &pmx_power_auto_switch - &pmx_led_function_blue >; - pinctrl-names = "default"; - pmx_power_hdd: pmx-power-hdd { marvell,pins = "mpp10"; marvell,function = "gpo"; @@ -112,6 +102,10 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_function &pmx_power_switch + &pmx_power_auto_switch>; + pinctrl-names = "default"; + button@1 { label = "Function Button"; linux,code = <357>; @@ -133,6 +127,10 @@ gpio_leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm + &pmx_led_info &pmx_led_power + &pmx_led_function_blue>; + pinctrl-names = "default"; led@1 { label = "lsxl:blue:func"; @@ -163,6 +161,8 @@ gpio_fan { compatible = "gpio-fan"; + pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; + pinctrl-names = "default"; gpios = <&gpio0 19 1 &gpio0 18 1>; gpio-fan,speed-map = <0 3 @@ -172,10 +172,16 @@ alarm-gpios = <&gpio1 8 0>; }; + restart_poweroff { + compatible = "restart-poweroff"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; + pinctrl-names = "default"; usb_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 758824118a9a..6179333fd71f 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -18,16 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_nand &pmx_uart0 - &pmx_led_health - &pmx_sata0 &pmx_sata1 - &pmx_led_user1o - &pmx_led_user1g &pmx_led_user0o - &pmx_led_user0g &pmx_led_misc - >; - pinctrl-names = "default"; - pmx_led_health: pmx-led-health { marvell,pins = "mpp7"; marvell,function = "gpo"; @@ -91,9 +81,13 @@ serial@12000 { status = "ok"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; }; nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; status = "okay"; partition@0 { @@ -127,22 +121,37 @@ }; sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; nr-ports = <2>; status = "okay"; - }; mvsdio@90000 { pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; pinctrl-names = "default"; status = "okay"; - cd-gpios = <&gpio1 15 0>; + cd-gpios = <&gpio1 15 1>; /* No WP GPIO */ }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_health + &pmx_led_user1o + &pmx_led_user1g &pmx_led_user0o + &pmx_led_user0g &pmx_led_misc + >; + pinctrl-names = "default"; health { label = "status:green:health"; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 1ca66ab83ad6..b79ea8cebf4c 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -18,18 +18,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - - pinctrl-0 = < &pmx_uart0 - &pmx_button_power - &pmx_button_backup - &pmx_button_reset - &pmx_led_blue_power - &pmx_led_blue_activity - &pmx_led_blue_disk1 - &pmx_led_blue_disk2 - &pmx_led_blue_backup >; - pinctrl-names = "default"; - pmx_button_power: pmx-button-power { marvell,pins = "mpp47"; marvell,function = "gpio"; @@ -74,6 +62,8 @@ }; serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; status = "okay"; }; @@ -115,6 +105,10 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity + &pmx_led_blue_disk1 &pmx_led_blue_disk2 + &pmx_led_blue_backup >; + pinctrl-names = "default"; power_led { label = "status:blue:power_led"; @@ -143,6 +137,10 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_button_power &pmx_button_backup + &pmx_button_reset>; + pinctrl-names = "default"; + button@1 { label = "Power Button"; linux,code = <116>; /* KEY_POWER */ diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 6affd924fe11..2afac0405816 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -8,10 +8,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0 - &pmx_ns2_sata0 &pmx_ns2_sata1>; - pinctrl-names = "default"; - pmx_ns2_sata0: pmx-ns2-sata0 { marvell,pins = "mpp21"; marvell,function = "sata0"; @@ -23,10 +19,14 @@ }; serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; status = "okay"; }; spi@10600 { + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; status = "okay"; flash@0 { @@ -45,6 +45,8 @@ }; i2c@11000 { + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; status = "okay"; eeprom@50 { diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts index f2d36ecf36d8..b50e93d7796c 100644 --- a/arch/arm/boot/dts/kirkwood-ns2.dts +++ b/arch/arm/boot/dts/kirkwood-ns2.dts @@ -13,6 +13,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts index b02eb4ea1bb4..af8259fe8955 100644 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts @@ -13,6 +13,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts index bcec4d6cada7..85f24d227e17 100644 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ b/arch/arm/boot/dts/kirkwood-ns2max.dts @@ -13,6 +13,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; + pinctrl-names = "default"; status = "okay"; nr-ports = <2>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts index adab1ab25733..329e530bffe7 100644 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts @@ -14,6 +14,8 @@ ocp@f1000000 { sata@80000 { + pinctrl-0 = <&pmx_ns2_sata0>; + pinctrl-names = "default"; status = "okay"; nr-ports = <1>; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index a7412b937a8a..69003598f5fa 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { model = "ZyXEL NSA310"; @@ -17,22 +18,7 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_led_esata_green - &pmx_led_esata_red - &pmx_led_usb_green - &pmx_led_usb_red - &pmx_usb_power_off - &pmx_led_sys_green - &pmx_led_sys_red - &pmx_btn_reset - &pmx_btn_copy - &pmx_led_copy_green - &pmx_led_copy_red - &pmx_led_hdd_green - &pmx_led_hdd_red - &pmx_unknown - &pmx_btn_power - &pmx_pwr_off >; + pinctrl-0 = <&pmx_unknown>; pinctrl-names = "default"; pmx_led_esata_green: pmx-led-esata-green { @@ -176,12 +162,22 @@ reg = <0x5040000 0x2fc0000>; }; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; + pinctrl-names = "default"; button@1 { label = "Power Button"; @@ -202,6 +198,12 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red + &pmx_led_usb_green &pmx_led_usb_red + &pmx_led_sys_green &pmx_led_sys_red + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd_green &pmx_led_hdd_red>; + pinctrl-names = "default"; green-sys { label = "nsa310:green:sys"; @@ -247,6 +249,8 @@ gpio_poweroff { compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_pwr_off>; + pinctrl-names = "default"; gpios = <&gpio1 16 0>; }; @@ -254,6 +258,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_off>; + pinctrl-names = "default"; usb0_power_off: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index d27f7245f8e7..38dc8517d777 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -19,15 +19,21 @@ ocp@f1000000 { serial@12000 { status = "ok"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; }; serial@12100 { status = "ok"; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; }; nand@3000000 { chip-delay = <25>; status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; partition@0 { label = "uboot"; @@ -67,6 +73,8 @@ i2c@11100 { status = "okay"; + pinctrl-0 = <&pmx_twsi1>; + pinctrl-names = "default"; s35390a: s35390a@30 { compatible = "s35390a"; @@ -75,16 +83,7 @@ }; pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_nand &pmx_uart0 - &pmx_uart1 &pmx_twsi1 - &pmx_dip_sw0 &pmx_dip_sw1 - &pmx_dip_sw2 &pmx_dip_sw3 - &pmx_gpio_0 &pmx_gpio_1 - &pmx_gpio_2 &pmx_gpio_3 - &pmx_gpio_4 &pmx_gpio_5 - &pmx_gpio_6 &pmx_gpio_7 - &pmx_led_red &pmx_led_green - &pmx_led_yellow >; + pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; pinctrl-names = "default"; pmx_uart0: pmx-uart0 { @@ -104,63 +103,14 @@ marvell,function = "sysrst"; }; - pmx_dip_sw0: pmx-dip-sw0 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_dip_sw1: pmx-dip-sw1 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_dip_sw2: pmx-dip-sw2 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_dip_sw3: pmx-dip-sw3 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp26"; + pmx_dip_switches: pmx-dip-switches { + marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23"; marvell,function = "gpio"; }; - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp31"; + pmx_gpio_header: pmx-gpio-header { + marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27", + "mpp28", "mpp29", "mpp30", "mpp31"; marvell,function = "gpio"; }; @@ -174,18 +124,8 @@ marvell,function = "gpio"; }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_led_yellow: pmx-led-yellow { - marvell,pins = "mpp43"; + pmx_leds: pmx-leds { + marvell,pins = "mpp41", "mpp42", "mpp43"; marvell,function = "gpio"; }; }; @@ -193,6 +133,8 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; led-red { label = "obsa6:red:stat"; @@ -209,4 +151,18 @@ gpios = <&gpio1 11 1>; }; }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_gpio_init>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + label = "Init Button"; + linux,code = <116>; + gpios = <&gpio1 6 0>; + }; + }; }; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi new file mode 100644 index 000000000000..9d5947599694 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -0,0 +1,97 @@ +/* + * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs + * + * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> + * + * Licensed under GPLv2 + */ + +/include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_led_red: pmx-led-red { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + pmx_led_blue: pmx-led-blue { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_sdio_wp: pmx-sdio-wp { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "okay"; + }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x0500000 0x1fb00000>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 0>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + health { + label = "sheevaplug:blue:health"; + gpios = <&gpio1 17 1>; + linux,default-trigger = "default-on"; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts new file mode 100644 index 000000000000..1c6946a62aa9 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts @@ -0,0 +1,40 @@ +/* + * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug + * + * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> + * + * Licensed under GPLv2 + */ + +/dts-v1/; + +/include/ "kirkwood-sheevaplug-common.dtsi" + +/ { + model = "Globalscale Technologies eSATA SheevaPlug"; + compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_nand &pmx_uart0 + &pmx_usb_power_enable + &pmx_led_blue>; + pinctrl-names = "default"; + + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio1 12 1>; + wp-gpios = <&gpio1 15 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts new file mode 100644 index 000000000000..f7684066f0ce --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts @@ -0,0 +1,45 @@ +/* + * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug + * + * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> + * + * Licensed under GPLv2 + */ + +/dts-v1/; + +/include/ "kirkwood-sheevaplug-common.dtsi" + +/ { + model = "Globalscale Technologies SheevaPlug"; + compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pinctrl-0 = < &pmx_nand &pmx_uart0 + &pmx_usb_power_enable + &pmx_led_red + &pmx_led_blue>; + pinctrl-names = "default"; + + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; + status = "okay"; + /* No CD or WP GPIOs */ + broken-cd; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + misc { + label = "sheevaplug:red:misc"; + gpios = <&gpio1 14 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 66eb45b00b25..f2052d7bc10f 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -19,18 +19,6 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { /* - * GPIO LED layout - * - * /-SYS_LED(2) - * | - * | /-DISK_LED - * | | - * | | /-WLAN_LED(2) - * | | | - * [SW] [*] [*] [*] - */ - - /* * Switch positions * * /-SW_LEFT(2) @@ -41,19 +29,8 @@ * | | | * PS [L] [I] [R] LEDS */ - pinctrl-0 = < &pmx_led_disk_yellow - &pmx_sata0_pwr_enable - &pmx_led_sys_red - &pmx_led_sys_blue - &pmx_led_wifi_green - &pmx_sw_left - &pmx_sw_right - &pmx_sw_idle - &pmx_sw_left2 - &pmx_led_wifi_yellow - &pmx_uart0 - &pmx_nand - &pmx_twsi0 >; + pinctrl-0 = <&pmx_sw_left &pmx_sw_right + &pmx_sw_idle &pmx_sw_left2>; pinctrl-names = "default"; pmx_led_disk_yellow: pmx-led-disk-yellow { @@ -109,10 +86,14 @@ serial@12000 { status = "ok"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; }; nand@3000000 { status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; partition@0 { label = "u-boot"; @@ -147,6 +128,8 @@ i2c@11000 { status = "ok"; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; }; mvsdio@90000 { @@ -154,11 +137,28 @@ pinctrl-names = "default"; status = "okay"; /* No CD or WP GPIOs */ + broken-cd; }; }; gpio-leds { + /* + * GPIO LED layout + * + * /-SYS_LED(2) + * | + * | /-DISK_LED + * | | + * | | /-WLAN_LED(2) + * | | | + * [SW] [*] [*] [*] + */ + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red + &pmx_led_sys_blue &pmx_led_wifi_green + &pmx_led_wifi_yellow>; + pinctrl-names = "default"; disk { label = "topkick:yellow:disk"; @@ -187,6 +187,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_sata0_pwr_enable>; + pinctrl-names = "default"; sata0_power: regulator@1 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index 8295c833887f..6dd1038e4de4 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -1,16 +1,14 @@ /dts-v1/; -/include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood.dtsi" /include/ "kirkwood-6281.dtsi" +/include/ "kirkwood-ts219.dtsi" / { ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi - &pmx_twsi0 &pmx_sata0 &pmx_sata1 - &pmx_ram_size &pmx_reset_button - &pmx_USB_copy_button &pmx_board_id>; + pinctrl-0 = <&pmx_ram_size &pmx_board_id>; pinctrl-names = "default"; pmx_ram_size: pmx-ram-size { @@ -38,6 +36,9 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; + pinctrl-names = "default"; + button@1 { label = "USB Copy"; linux,code = <133>; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index df3f95dfba33..aba435d4e0e5 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -1,16 +1,14 @@ /dts-v1/; -/include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood.dtsi" /include/ "kirkwood-6282.dtsi" +/include/ "kirkwood-ts219.dtsi" / { ocp@f1000000 { pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi - &pmx_twsi0 &pmx_sata0 &pmx_sata1 - &pmx_ram_size &pmx_reset_button - &pmx_USB_copy_button &pmx_board_id>; + pinctrl-0 = <&pmx_ram_size &pmx_board_id>; pinctrl-names = "default"; pmx_ram_size: pmx-ram-size { @@ -38,6 +36,9 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; + pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; + pinctrl-names = "default"; + button@1 { label = "USB Copy"; linux,code = <133>; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 64ea27cb3298..0c9a94cd666c 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -1,5 +1,3 @@ -/include/ "kirkwood.dtsi" - / { model = "QNAP TS219 family"; compatible = "qnap,ts219", "marvell,kirkwood"; @@ -17,6 +15,8 @@ i2c@11000 { status = "okay"; clock-frequency = <400000>; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; s35390a: s35390a@30 { compatible = "s35390a"; @@ -26,13 +26,24 @@ serial@12000 { clock-frequency = <200000000>; status = "okay"; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; }; serial@12100 { clock-frequency = <200000000>; status = "okay"; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + }; + poweroff@12100 { + compatible = "qnap,power-off"; + reg = <0x12000 0x100>; + clocks = <&gate_clk 7>; }; spi@10600 { status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; m25p128@0 { #address-cells = <1>; @@ -71,8 +82,17 @@ }; }; sata@80000 { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; status = "okay"; nr-ports = <2>; }; + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index fada7e6d24d8..b5f66bf4608a 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -19,6 +19,7 @@ ocp@f1000000 { compatible = "simple-bus"; ranges = <0x00000000 0xf1000000 0x4000000 + 0xe0000000 0xe0000000 0x8100000 /* PCIE */ 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; @@ -71,13 +72,6 @@ status = "disabled"; }; - rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - spi@10600 { compatible = "marvell,orion-spi"; #address-cells = <1>; @@ -151,15 +145,6 @@ status = "okay"; }; - sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - status = "disabled"; - }; - nand@3000000 { #address-cells = <1>; #size-cells = <1>; @@ -194,13 +179,5 @@ clocks = <&gate_clk 17>; status = "okay"; }; - - mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index a1d8252e9ec7..0f2aa61911a3 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -31,6 +30,7 @@ CONFIG_MACH_T5325=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y CONFIG_MACH_CLOUDBOX_DT=y +CONFIG_MACH_DB88F628X_BP_DT=y CONFIG_MACH_DLINK_KIRKWOOD_DT=y CONFIG_MACH_DOCKSTAR_DT=y CONFIG_MACH_DREAMPLUG_DT=y @@ -50,14 +50,19 @@ CONFIG_MACH_NETSPACE_V2_DT=y CONFIG_MACH_NSA310_DT=y CONFIG_MACH_OPENBLOCKS_A6_DT=y CONFIG_MACH_READYNAS_DT=y +CONFIG_MACH_SHEEVAPLUG_DT=y CONFIG_MACH_TOPKICK_DT=y CONFIG_MACH_TS219_DT=y # CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_PCI_MVEBU=y CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_IDLE=y CONFIG_NET=y CONFIG_PACKET=y @@ -68,14 +73,12 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set -CONFIG_NET_DSA=y CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -140,6 +143,7 @@ CONFIG_HID_TOPSEED=y CONFIG_HID_THRUSTMASTER=y CONFIG_HID_ZEROPLUS=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_PRINTER=m diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index f3e8ae001ff1..804b1dae4330 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_XP=y # CONFIG_CACHE_L2X0 is not set # CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y CONFIG_SMP=y CONFIG_AEABI=y CONFIG_HIGHMEM=y @@ -60,6 +62,8 @@ CONFIG_USB_SUPPORT=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_STORAGE=y +CONFIG_USB_XHCI_HCD=y CONFIG_MMC=y CONFIG_MMC_MVSDIO=y CONFIG_NEW_LEDS=y diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 36469d813951..dff7b2fd4e20 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -22,8 +22,7 @@ config MACH_CM_A510 config MACH_DOVE_DT bool "Marvell Dove Flattened Device Tree" - select MVEBU_CLK_CORE - select MVEBU_CLK_GATING + select DOVE_CLK select REGULATOR select REGULATOR_FIXED_VOLTAGE select USE_OF diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index 0b142803b2e1..f3755ac81148 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c @@ -10,7 +10,6 @@ #include <linux/init.h> #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_data/usb-ehci-orion.h> @@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void) static void __init dove_of_clk_init(void) { - mvebu_clocks_init(); + of_clk_init(NULL); dove_legacy_clk_init(); } diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index e2b5da031f96..2a9443d04d92 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -9,7 +9,6 @@ */ #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/dma-mapping.h> #include <linux/init.h> #include <linux/of.h> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 7509a89af967..b634f9650a7b 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -8,12 +8,6 @@ config MACH_D2NET_V2 Say 'Y' here if you want your kernel to support the LaCie d2 Network v2 NAS. -config MACH_DB88F6281_BP - bool "Marvell DB-88F6281-BP Development Board" - help - Say 'Y' here if you want your kernel to support the - Marvell DB-88F6281-BP Development Board. - config MACH_DOCKSTAR bool "Seagate FreeAgent DockStar" help @@ -134,13 +128,12 @@ comment "Device tree entries" config ARCH_KIRKWOOD_DT bool "Marvell Kirkwood Flattened Device Tree" + select KIRKWOOD_CLK select POWER_SUPPLY select POWER_RESET select POWER_RESET_GPIO select REGULATOR select REGULATOR_FIXED_VOLTAGE - select MVEBU_CLK_CORE - select MVEBU_CLK_GATING select USE_OF help Say 'Y' here if you want your kernel to support the @@ -153,6 +146,13 @@ config MACH_CLOUDBOX_DT Say 'Y' here if you want your kernel to support the LaCie CloudBox NAS, using Flattened Device Tree. +config MACH_DB88F628X_BP_DT + bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)" + help + Say 'Y' here if you want your kernel to support the Marvell + DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened + Device Tree). + config MACH_DLINK_KIRKWOOD_DT bool "D-Link Kirkwood-based NAS (Flattened Device Tree)" select ARCH_KIRKWOOD_DT @@ -227,6 +227,7 @@ config MACH_KM_KIRKWOOD_DT config MACH_LSXL_DT bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)" select ARCH_KIRKWOOD_DT + select POWER_RESET_RESTART help Say 'Y' here if you want your kernel to support the Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using @@ -272,14 +273,6 @@ config MACH_NETSPACE_V2_DT Say 'Y' here if you want your kernel to support the LaCie Network Space v2 NAS, using Flattened Device Tree. -config MACH_NSA310_DT - bool "ZyXEL NSA-310 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - select ARM_ATAG_DTB_COMPAT - help - Say 'Y' here if you want your kernel to support the - ZyXEL NSA-310 board (Flattened Device Tree). - config MACH_OPENBLOCKS_A6_DT bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)" select ARCH_KIRKWOOD_DT @@ -296,6 +289,13 @@ config MACH_READYNAS_DT Say 'Y' here if you want your kernel to support the NETGEAR ReadyNAS Duo v2 using Fattened Device Tree. +config MACH_SHEEVAPLUG_DT + bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)" + select ARCH_KIRKWOOD_DT + help + Say 'Y' here if you want your kernel to support the + Marvell (eSATA) SheevaPlug (Flattened Device Tree). + config MACH_TOPKICK_DT bool "USI Topkick (Flattened Device Tree)" select ARCH_KIRKWOOD_DT @@ -308,6 +308,7 @@ config MACH_TS219_DT select ARCH_KIRKWOOD_DT select ARM_APPENDED_DTB select ARM_ATAG_DTB_COMPAT + select POWER_RESET_QNAP help Say 'Y' here if you want your kernel to support the QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index e1f3735d3415..ac4cd75dd499 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -1,7 +1,6 @@ obj-y += common.o irq.o pcie.o mpp.o obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o @@ -21,6 +20,7 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o obj-$(CONFIG_MACH_CLOUDBOX_DT) += board-ns2.o +obj-$(CONFIG_MACH_DB88F628X_BP_DT) += board-db88f628x-bp.o obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o @@ -37,8 +37,8 @@ obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o -obj-$(CONFIG_MACH_NSA310_DT) += board-nsa310.o obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o obj-$(CONFIG_MACH_READYNAS_DT) += board-readynas.o +obj-$(CONFIG_MACH_SHEEVAPLUG_DT) += board-sheevaplug.o obj-$(CONFIG_MACH_TOPKICK_DT) += board-usi_topkick.o obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c new file mode 100644 index 000000000000..2f574bc8ed40 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-db88f628x-bp.c @@ -0,0 +1,24 @@ +/* + * Saeed Bishara <saeed@marvell.com> + * + * Marvell DB-88F628{1,2}-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/mv643xx_eth.h> +#include "common.h" + +static struct mv643xx_eth_platform_data db88f628x_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +void __init db88f628x_init(void) +{ + kirkwood_ge00_init(&db88f628x_ge00_data); +} diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index e9647b80cb59..6e122ed3282f 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -15,7 +15,6 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/kexec.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -25,11 +24,6 @@ #include <plat/common.h> #include "common.h" -static struct of_device_id kirkwood_dt_match_table[] __initdata = { - { .compatible = "simple-bus", }, - { } -}; - /* * There are still devices that doesn't know about DT yet. Get clock * gates here and add a clock lookup alias, so that old platform @@ -77,7 +71,7 @@ static void __init kirkwood_legacy_clk_init(void) static void __init kirkwood_of_clk_init(void) { - mvebu_clocks_init(); + of_clk_init(NULL); kirkwood_legacy_clk_init(); } @@ -97,6 +91,8 @@ static void __init kirkwood_dt_init(void) kirkwood_l2_init(); + kirkwood_cpufreq_init(); + /* Setup root of clk tree */ kirkwood_of_clk_init(); @@ -112,6 +108,9 @@ static void __init kirkwood_dt_init(void) if (of_machine_is_compatible("globalscale,guruplug")) guruplug_dt_init(); + if (of_machine_is_compatible("globalscale,sheevaplug")) + sheevaplug_dt_init(); + if (of_machine_is_compatible("dlink,dns-kirkwood")) dnskw_init(); @@ -147,6 +146,10 @@ static void __init kirkwood_dt_init(void) of_machine_is_compatible("lacie,netspace_v2")) ns2_init(); + if (of_machine_is_compatible("marvell,db-88f6281-bp") || + of_machine_is_compatible("marvell,db-88f6282-bp")) + db88f628x_init(); + if (of_machine_is_compatible("mpl,cec4")) mplcec4_init(); @@ -159,12 +162,13 @@ static void __init kirkwood_dt_init(void) if (of_machine_is_compatible("usi,topkick")) usi_topkick_init(); - of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char * const kirkwood_dt_board_compat[] = { "globalscale,dreamplug", "globalscale,guruplug", + "globalscale,sheevaplug", "dlink,dns-320", "dlink,dns-325", "iom,iconnect", @@ -181,6 +185,8 @@ static const char * const kirkwood_dt_board_compat[] = { "lacie,netspace_max_v2", "lacie,netspace_mini_v2", "lacie,netspace_v2", + "marvell,db-88f6281-bp", + "marvell,db-88f6282-bp", "mpl,cec4", "netgear,readynas-duo-v2", "plathome,openblocks-a6", diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c index c8ebde4919e2..98b5ad1bba90 100644 --- a/arch/arm/mach-kirkwood/board-iconnect.c +++ b/arch/arm/mach-kirkwood/board-iconnect.c @@ -22,11 +22,3 @@ void __init iconnect_init(void) { kirkwood_ge00_init(&iconnect_ge00_data); } - -static int __init iconnect_pci_init(void) -{ - if (of_machine_is_compatible("iom,iconnect")) - kirkwood_pcie_init(KW_PCIE0); - return 0; -} -subsys_initcall(iconnect_pci_init); diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c index 4ec8b7ae784a..348395238df6 100644 --- a/arch/arm/mach-kirkwood/board-lsxl.c +++ b/arch/arm/mach-kirkwood/board-lsxl.c @@ -25,19 +25,6 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -/* - * On the LS-XHL/LS-CHLv2, the shutdown process is following: - * - Userland monitors key events until the power switch goes to off position - * - The board reboots - * - U-boot starts and goes into an idle mode waiting for the user - * to move the switch to ON position - * - */ -static void lsxl_power_off(void) -{ - kirkwood_restart('h', NULL); -} - void __init lsxl_init(void) { /* @@ -46,7 +33,4 @@ void __init lsxl_init(void) kirkwood_ge00_init(&lsxl_ge00_data); kirkwood_ge01_init(&lsxl_ge01_data); - - /* register power-off method */ - pm_power_off = lsxl_power_off; } diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c index 7d6dc669e17f..938712e248f1 100644 --- a/arch/arm/mach-kirkwood/board-mplcec4.c +++ b/arch/arm/mach-kirkwood/board-mplcec4.c @@ -29,7 +29,6 @@ void __init mplcec4_init(void) */ kirkwood_ge00_init(&mplcec4_ge00_data); kirkwood_ge01_init(&mplcec4_ge01_data); - kirkwood_pcie_init(KW_PCIE0); } diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c deleted file mode 100644 index 55ade93b93bf..000000000000 --- a/arch/arm/mach-kirkwood/board-nsa310.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-kirkwood/nsa-310-setup.c - * - * ZyXEL NSA-310 Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <mach/kirkwood.h> -#include <linux/of.h> -#include "common.h" - -static int __init nsa310_pci_init(void) -{ - if (of_machine_is_compatible("zyxel,nsa310")) - kirkwood_pcie_init(KW_PCIE0); - - return 0; -} - -subsys_initcall(nsa310_pci_init); diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c new file mode 100644 index 000000000000..fa389373ca74 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-sheevaplug.c @@ -0,0 +1,27 @@ +/* + * arch/arm/mach-kirkwood/board-sheevaplug.c + * + * Marvell Sheevaplug Reference Board Init for drivers not converted to + * flattened device tree yet. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mv643xx_eth.h> +#include "common.h" + +static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +void __init sheevaplug_dt_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_ge00_init(&sheevaplug_ge00_data); +} diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c index acb0187c7ee1..860f44ab457d 100644 --- a/arch/arm/mach-kirkwood/board-ts219.c +++ b/arch/arm/mach-kirkwood/board-ts219.c @@ -23,7 +23,6 @@ #include <asm/mach/arch.h> #include <mach/kirkwood.h> #include "common.h" -#include "tsx1x-common.h" static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), @@ -38,16 +37,4 @@ void __init qnap_dt_ts219_init(void) qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); kirkwood_ge00_init(&qnap_ts219_ge00_data); - - pm_power_off = qnap_tsx1x_power_off; -} - -/* FIXME: Will not work with DT. Maybe use MPP40_GPIO? */ -static int __init ts219_pci_init(void) -{ - if (machine_is_ts219()) - kirkwood_pcie_init(KW_PCIE0); - - return 0; } -subsys_initcall(ts219_pci_init); diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f38922897563..7c72c725b711 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -598,6 +598,29 @@ void __init kirkwood_audio_init(void) } /***************************************************************************** + * CPU Frequency + ****************************************************************************/ +static struct resource kirkwood_cpufreq_resources[] = { + [0] = { + .start = CPU_CONTROL_PHYS, + .end = CPU_CONTROL_PHYS + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device kirkwood_cpufreq_device = { + .name = "kirkwood-cpufreq", + .id = -1, + .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources), + .resource = kirkwood_cpufreq_resources, +}; + +void __init kirkwood_cpufreq_init(void) +{ + platform_device_register(&kirkwood_cpufreq_device); +} + +/***************************************************************************** * General ****************************************************************************/ /* @@ -648,30 +671,6 @@ char * __init kirkwood_id(void) void __init kirkwood_setup_wins(void) { - /* - * The PCIe windows will no longer be statically allocated - * here once Kirkwood is migrated to the pci-mvebu driver. - */ - mvebu_mbus_add_window_remap_flags("pcie0.0", - KIRKWOOD_PCIE_IO_PHYS_BASE, - KIRKWOOD_PCIE_IO_SIZE, - KIRKWOOD_PCIE_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie0.0", - KIRKWOOD_PCIE_MEM_PHYS_BASE, - KIRKWOOD_PCIE_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window_remap_flags("pcie1.0", - KIRKWOOD_PCIE1_IO_PHYS_BASE, - KIRKWOOD_PCIE1_IO_SIZE, - KIRKWOOD_PCIE1_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie1.0", - KIRKWOOD_PCIE1_MEM_PHYS_BASE, - KIRKWOOD_PCIE1_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE); mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 21da3b1ebd7b..1c09f3f93fbb 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -51,6 +51,8 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); void kirkwood_audio_init(void); void kirkwood_cpuidle_init(void); +void kirkwood_cpufreq_init(void); + void kirkwood_restart(char, const char *); void kirkwood_clk_init(void); @@ -65,6 +67,11 @@ void guruplug_dt_init(void); #else static inline void guruplug_dt_init(void) {}; #endif +#ifdef CONFIG_MACH_SHEEVAPLUG_DT +void sheevaplug_dt_init(void); +#else +static inline void sheevaplug_dt_init(void) {}; +#endif #ifdef CONFIG_MACH_TS219_DT void qnap_dt_ts219_init(void); #else @@ -119,6 +126,12 @@ void km_kirkwood_init(void); static inline void km_kirkwood_init(void) {}; #endif +#ifdef CONFIG_MACH_DB88F628X_BP_DT +void db88f628x_init(void); +#else +static inline void db88f628x_init(void) {}; +#endif + #ifdef CONFIG_MACH_MPLCEC4_DT void mplcec4_init(void); #else diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c deleted file mode 100644 index 5a369fe74754..000000000000 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * arch/arm/mach-kirkwood/db88f6281-bp-setup.c - * - * Marvell DB-88F6281-BP Development Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/sizes.h> -#include <linux/platform_device.h> -#include <linux/mtd/partitions.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include <linux/platform_data/mmc-mvsdio.h> -#include "common.h" -#include "mpp.h" - -static struct mtd_partition db88f6281_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data db88f6281_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv_sata_platform_data db88f6281_sata_data = { - .n_ports = 2, -}; - -static struct mvsdio_platform_data db88f6281_mvsdio_data = { - .gpio_write_protect = 37, - .gpio_card_detect = 38, -}; - -static unsigned int db88f6281_mpp_config[] __initdata = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP37_GPIO, - MPP38_GPIO, - 0 -}; - -static void __init db88f6281_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(db88f6281_mpp_config); - - kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25); - kirkwood_ehci_init(); - kirkwood_ge00_init(&db88f6281_ge00_data); - kirkwood_sata_init(&db88f6281_sata_data); - kirkwood_uart0_init(); - kirkwood_sdio_init(&db88f6281_mvsdio_data); -} - -static int __init db88f6281_pci_init(void) -{ - if (machine_is_db88f6281_bp()) { - u32 dev, rev; - - kirkwood_pcie_id(&dev, &rev); - if (dev == MV88F6282_DEV_ID) - kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0); - else - kirkwood_pcie_init(KW_PCIE0); - } - return 0; -} -subsys_initcall(db88f6281_pci_init); - -MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") - /* Maintainer: Saeed Bishara <saeed@marvell.com> */ - .atag_offset = 0x100, - .init_machine = db88f6281_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 5c82b7dce4e2..d4cbe5e81bb4 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -17,6 +17,7 @@ #define CPU_CONFIG_ERROR_PROP 0x00000004 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) +#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104) #define CPU_RESET 0x00000002 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) @@ -69,6 +70,7 @@ #define CGC_RUNIT (1 << 7) #define CGC_XOR0 (1 << 8) #define CGC_AUDIO (1 << 9) +#define CGC_POWERSAVE (1 << 11) #define CGC_SATA0 (1 << 14) #define CGC_SATA1 (1 << 15) #define CGC_XOR1 (1 << 16) diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 7f43e6c2f8c0..ddcb09f5bdd3 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -12,6 +12,7 @@ #include <linux/pci.h> #include <linux/slab.h> #include <linux/clk.h> +#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> @@ -253,6 +254,27 @@ static void __init add_pcie_port(int index, void __iomem *base) void __init kirkwood_pcie_init(unsigned int portmask) { + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_IO_PHYS_BASE, + KIRKWOOD_PCIE_IO_SIZE, + KIRKWOOD_PCIE_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_MEM_PHYS_BASE, + KIRKWOOD_PCIE_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_IO_PHYS_BASE, + KIRKWOOD_PCIE1_IO_SIZE, + KIRKWOOD_PCIE1_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_MEM_PHYS_BASE, + KIRKWOOD_PCIE1_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; if (portmask & KW_PCIE0) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 80a8bcacd9d5..9eb63d724602 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -10,12 +10,11 @@ config ARCH_MVEBU select PLAT_ORION select SPARSE_IRQ select CLKDEV_LOOKUP - select MVEBU_CLK_CORE - select MVEBU_CLK_CPU - select MVEBU_CLK_GATING select MVEBU_MBUS select ZONE_DMA if ARM_LPAE select ARCH_REQUIRE_GPIOLIB + select MIGHT_HAVE_PCI + select PCI_QUIRKS if PCI if ARCH_MVEBU @@ -30,6 +29,7 @@ config MACH_ARMADA_370_XP config MACH_ARMADA_370 bool "Marvell Armada 370 boards" + select ARMADA_370_CLK select MACH_ARMADA_370_XP select PINCTRL_ARMADA_370 help @@ -38,6 +38,7 @@ config MACH_ARMADA_370 config MACH_ARMADA_XP bool "Marvell Armada XP boards" + select ARMADA_XP_CLK select MACH_ARMADA_370_XP select PINCTRL_ARMADA_XP help diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 1c48890bb72b..8721e2d26066 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -14,13 +14,12 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/clk-provider.h> #include <linux/of_platform.h> #include <linux/io.h> #include <linux/time-armada-370-xp.h> -#include <linux/clk/mvebu.h> #include <linux/dma-mapping.h> #include <linux/mbus.h> -#include <linux/irqchip.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -38,18 +37,18 @@ static struct map_desc armada_370_xp_io_desc[] __initdata = { }, }; -void __init armada_370_xp_map_io(void) +static void __init armada_370_xp_map_io(void) { iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc)); } -void __init armada_370_xp_timer_and_clk_init(void) +static void __init armada_370_xp_timer_and_clk_init(void) { - mvebu_clocks_init(); + of_clk_init(NULL); armada_370_xp_timer_init(); } -void __init armada_370_xp_init_early(void) +static void __init armada_370_xp_init_early(void) { char *mbus_soc_name; @@ -89,7 +88,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") .init_machine = armada_370_xp_dt_init, .map_io = armada_370_xp_map_io, .init_early = armada_370_xp_init_early, - .init_irq = irqchip_init, .init_time = armada_370_xp_timer_and_clk_init, .restart = mvebu_restart, .dt_compat = armada_370_xp_dt_compat, diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index 53e8391192cd..5476669ba905 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent) /* Add CPU to SMP group - Atomic */ add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET - ldr r2, [r3] +1: + ldrex r2, [r3] orr r2, r2, r1 - str r2, [r3] + strex r0, r2, [r3] + cmp r0, #0 + bne 1b /* Enable coherency on CPU - Atomic */ - add r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET - ldr r2, [r3] + add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET +1: + ldrex r2, [r3] orr r2, r2, r1 - str r2, [r3] + strex r0, r2, [r3] + cmp r0, #0 + bne 1b dsb diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig index 57323fd15ec9..0b0f3e729cf7 100644 --- a/drivers/clk/mvebu/Kconfig +++ b/drivers/clk/mvebu/Kconfig @@ -1,8 +1,23 @@ -config MVEBU_CLK_CORE - bool +config MVEBU_CLK_COMMON + bool config MVEBU_CLK_CPU - bool + bool -config MVEBU_CLK_GATING - bool +config ARMADA_370_CLK + bool + select MVEBU_CLK_COMMON + select MVEBU_CLK_CPU + +config ARMADA_XP_CLK + bool + select MVEBU_CLK_COMMON + select MVEBU_CLK_CPU + +config DOVE_CLK + bool + select MVEBU_CLK_COMMON + +config KIRKWOOD_CLK + bool + select MVEBU_CLK_COMMON diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile index 58df3dc49363..1c7e70c63fb2 100644 --- a/drivers/clk/mvebu/Makefile +++ b/drivers/clk/mvebu/Makefile @@ -1,3 +1,7 @@ -obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o +obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o -obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o + +obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o +obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o +obj-$(CONFIG_DOVE_CLK) += dove.o +obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c new file mode 100644 index 000000000000..079960e7c304 --- /dev/null +++ b/drivers/clk/mvebu/armada-370.c @@ -0,0 +1,176 @@ +/* + * Marvell Armada 370 SoC clocks + * + * Copyright (C) 2012 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/of.h> +#include "common.h" + +/* + * Core Clocks + */ + +#define SARL 0 /* Low part [0:31] */ +#define SARL_A370_PCLK_FREQ_OPT 11 +#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF +#define SARL_A370_FAB_FREQ_OPT 15 +#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F +#define SARL_A370_TCLK_FREQ_OPT 20 +#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1 + +enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK }; + +static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = { + { .id = A370_CPU_TO_NBCLK, .name = "nbclk" }, + { .id = A370_CPU_TO_HCLK, .name = "hclk" }, + { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" }, +}; + +static const u32 __initconst a370_tclk_freqs[] = { + 16600000, + 20000000, +}; + +static u32 __init a370_get_tclk_freq(void __iomem *sar) +{ + u8 tclk_freq_select = 0; + + tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & + SARL_A370_TCLK_FREQ_OPT_MASK); + return a370_tclk_freqs[tclk_freq_select]; +} + +static const u32 __initconst a370_cpu_freqs[] = { + 400000000, + 533000000, + 667000000, + 800000000, + 1000000000, + 1067000000, + 1200000000, +}; + +static u32 __init a370_get_cpu_freq(void __iomem *sar) +{ + u32 cpu_freq; + u8 cpu_freq_select = 0; + + cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & + SARL_A370_PCLK_FREQ_OPT_MASK); + if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) { + pr_err("CPU freq select unsupported %d\n", cpu_freq_select); + cpu_freq = 0; + } else + cpu_freq = a370_cpu_freqs[cpu_freq_select]; + + return cpu_freq; +} + +static const int __initconst a370_nbclk_ratios[32][2] = { + {0, 1}, {1, 2}, {2, 2}, {2, 2}, + {1, 2}, {1, 2}, {1, 1}, {2, 3}, + {0, 1}, {1, 2}, {2, 4}, {0, 1}, + {1, 2}, {0, 1}, {0, 1}, {2, 2}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {2, 3}, {0, 1}, {0, 1}, {0, 1}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {0, 1}, {0, 1}, {0, 1}, {0, 1}, +}; + +static const int __initconst a370_hclk_ratios[32][2] = { + {0, 1}, {1, 2}, {2, 6}, {2, 3}, + {1, 3}, {1, 4}, {1, 2}, {2, 6}, + {0, 1}, {1, 6}, {2, 10}, {0, 1}, + {1, 4}, {0, 1}, {0, 1}, {2, 5}, + {0, 1}, {0, 1}, {0, 1}, {1, 2}, + {2, 6}, {0, 1}, {0, 1}, {0, 1}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {0, 1}, {0, 1}, {0, 1}, {0, 1}, +}; + +static const int __initconst a370_dramclk_ratios[32][2] = { + {0, 1}, {1, 2}, {2, 3}, {2, 3}, + {1, 3}, {1, 2}, {1, 2}, {2, 6}, + {0, 1}, {1, 3}, {2, 5}, {0, 1}, + {1, 4}, {0, 1}, {0, 1}, {2, 5}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {2, 3}, {0, 1}, {0, 1}, {0, 1}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {0, 1}, {0, 1}, {0, 1}, {0, 1}, +}; + +static void __init a370_get_clk_ratio( + void __iomem *sar, int id, int *mult, int *div) +{ + u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & + SARL_A370_FAB_FREQ_OPT_MASK); + + switch (id) { + case A370_CPU_TO_NBCLK: + *mult = a370_nbclk_ratios[opt][0]; + *div = a370_nbclk_ratios[opt][1]; + break; + case A370_CPU_TO_HCLK: + *mult = a370_hclk_ratios[opt][0]; + *div = a370_hclk_ratios[opt][1]; + break; + case A370_CPU_TO_DRAMCLK: + *mult = a370_dramclk_ratios[opt][0]; + *div = a370_dramclk_ratios[opt][1]; + break; + } +} + +static const struct coreclk_soc_desc a370_coreclks = { + .get_tclk_freq = a370_get_tclk_freq, + .get_cpu_freq = a370_get_cpu_freq, + .get_clk_ratio = a370_get_clk_ratio, + .ratios = a370_coreclk_ratios, + .num_ratios = ARRAY_SIZE(a370_coreclk_ratios), +}; + +static void __init a370_coreclk_init(struct device_node *np) +{ + mvebu_coreclk_setup(np, &a370_coreclks); +} +CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock", + a370_coreclk_init); + +/* + * Clock Gating Control + */ + +static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = { + { "audio", NULL, 0, 0 }, + { "pex0_en", NULL, 1, 0 }, + { "pex1_en", NULL, 2, 0 }, + { "ge1", NULL, 3, 0 }, + { "ge0", NULL, 4, 0 }, + { "pex0", "pex0_en", 5, 0 }, + { "pex1", "pex1_en", 9, 0 }, + { "sata0", NULL, 15, 0 }, + { "sdio", NULL, 17, 0 }, + { "tdm", NULL, 25, 0 }, + { "ddr", NULL, 28, CLK_IGNORE_UNUSED }, + { "sata1", NULL, 30, 0 }, + { } +}; + +static void __init a370_clk_gating_init(struct device_node *np) +{ + mvebu_clk_gating_setup(np, a370_gating_desc); +} +CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock", + a370_clk_gating_init); diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c new file mode 100644 index 000000000000..13b62ceb3407 --- /dev/null +++ b/drivers/clk/mvebu/armada-xp.c @@ -0,0 +1,210 @@ +/* + * Marvell Armada XP SoC clocks + * + * Copyright (C) 2012 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/of.h> +#include "common.h" + +/* + * Core Clocks + * + * Armada XP Sample At Reset is a 64 bit bitfiled split in two + * register of 32 bits + */ + +#define SARL 0 /* Low part [0:31] */ +#define SARL_AXP_PCLK_FREQ_OPT 21 +#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7 +#define SARL_AXP_FAB_FREQ_OPT 24 +#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF +#define SARH 4 /* High part [32:63] */ +#define SARH_AXP_PCLK_FREQ_OPT (52-32) +#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1 +#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3 +#define SARH_AXP_FAB_FREQ_OPT (51-32) +#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1 +#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4 + +enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK }; + +static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = { + { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" }, + { .id = AXP_CPU_TO_HCLK, .name = "hclk" }, + { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" }, +}; + +/* Armada XP TCLK frequency is fixed to 250MHz */ +static u32 __init axp_get_tclk_freq(void __iomem *sar) +{ + return 250000000; +} + +static const u32 __initconst axp_cpu_freqs[] = { + 1000000000, + 1066000000, + 1200000000, + 1333000000, + 1500000000, + 1666000000, + 1800000000, + 2000000000, + 667000000, + 0, + 800000000, + 1600000000, +}; + +static u32 __init axp_get_cpu_freq(void __iomem *sar) +{ + u32 cpu_freq; + u8 cpu_freq_select = 0; + + cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) & + SARL_AXP_PCLK_FREQ_OPT_MASK); + /* + * The upper bit is not contiguous to the other ones and + * located in the high part of the SAR registers + */ + cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) & + SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT); + if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) { + pr_err("CPU freq select unsupported: %d\n", cpu_freq_select); + cpu_freq = 0; + } else + cpu_freq = axp_cpu_freqs[cpu_freq_select]; + + return cpu_freq; +} + +static const int __initconst axp_nbclk_ratios[32][2] = { + {0, 1}, {1, 2}, {2, 2}, {2, 2}, + {1, 2}, {1, 2}, {1, 1}, {2, 3}, + {0, 1}, {1, 2}, {2, 4}, {0, 1}, + {1, 2}, {0, 1}, {0, 1}, {2, 2}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {2, 3}, {0, 1}, {0, 1}, {0, 1}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {0, 1}, {0, 1}, {0, 1}, {0, 1}, +}; + +static const int __initconst axp_hclk_ratios[32][2] = { + {0, 1}, {1, 2}, {2, 6}, {2, 3}, + {1, 3}, {1, 4}, {1, 2}, {2, 6}, + {0, 1}, {1, 6}, {2, 10}, {0, 1}, + {1, 4}, {0, 1}, {0, 1}, {2, 5}, + {0, 1}, {0, 1}, {0, 1}, {1, 2}, + {2, 6}, {0, 1}, {0, 1}, {0, 1}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {0, 1}, {0, 1}, {0, 1}, {0, 1}, +}; + +static const int __initconst axp_dramclk_ratios[32][2] = { + {0, 1}, {1, 2}, {2, 3}, {2, 3}, + {1, 3}, {1, 2}, {1, 2}, {2, 6}, + {0, 1}, {1, 3}, {2, 5}, {0, 1}, + {1, 4}, {0, 1}, {0, 1}, {2, 5}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {2, 3}, {0, 1}, {0, 1}, {0, 1}, + {0, 1}, {0, 1}, {0, 1}, {1, 1}, + {0, 1}, {0, 1}, {0, 1}, {0, 1}, +}; + +static void __init axp_get_clk_ratio( + void __iomem *sar, int id, int *mult, int *div) +{ + u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) & + SARL_AXP_FAB_FREQ_OPT_MASK); + /* + * The upper bit is not contiguous to the other ones and + * located in the high part of the SAR registers + */ + opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) & + SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT); + + switch (id) { + case AXP_CPU_TO_NBCLK: + *mult = axp_nbclk_ratios[opt][0]; + *div = axp_nbclk_ratios[opt][1]; + break; + case AXP_CPU_TO_HCLK: + *mult = axp_hclk_ratios[opt][0]; + *div = axp_hclk_ratios[opt][1]; + break; + case AXP_CPU_TO_DRAMCLK: + *mult = axp_dramclk_ratios[opt][0]; + *div = axp_dramclk_ratios[opt][1]; + break; + } +} + +static const struct coreclk_soc_desc axp_coreclks = { + .get_tclk_freq = axp_get_tclk_freq, + .get_cpu_freq = axp_get_cpu_freq, + .get_clk_ratio = axp_get_clk_ratio, + .ratios = axp_coreclk_ratios, + .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), +}; + +static void __init axp_coreclk_init(struct device_node *np) +{ + mvebu_coreclk_setup(np, &axp_coreclks); +} +CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock", + axp_coreclk_init); + +/* + * Clock Gating Control + */ + +static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = { + { "audio", NULL, 0, 0 }, + { "ge3", NULL, 1, 0 }, + { "ge2", NULL, 2, 0 }, + { "ge1", NULL, 3, 0 }, + { "ge0", NULL, 4, 0 }, + { "pex00", NULL, 5, 0 }, + { "pex01", NULL, 6, 0 }, + { "pex02", NULL, 7, 0 }, + { "pex03", NULL, 8, 0 }, + { "pex10", NULL, 9, 0 }, + { "pex11", NULL, 10, 0 }, + { "pex12", NULL, 11, 0 }, + { "pex13", NULL, 12, 0 }, + { "bp", NULL, 13, 0 }, + { "sata0lnk", NULL, 14, 0 }, + { "sata0", "sata0lnk", 15, 0 }, + { "lcd", NULL, 16, 0 }, + { "sdio", NULL, 17, 0 }, + { "usb0", NULL, 18, 0 }, + { "usb1", NULL, 19, 0 }, + { "usb2", NULL, 20, 0 }, + { "xor0", NULL, 22, 0 }, + { "crypto", NULL, 23, 0 }, + { "tdm", NULL, 25, 0 }, + { "pex20", NULL, 26, 0 }, + { "pex30", NULL, 27, 0 }, + { "xor1", NULL, 28, 0 }, + { "sata1lnk", NULL, 29, 0 }, + { "sata1", "sata1lnk", 30, 0 }, + { } +}; + +static void __init axp_clk_gating_init(struct device_node *np) +{ + mvebu_clk_gating_setup(np, axp_gating_desc); +} +CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock", + axp_clk_gating_init); diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c deleted file mode 100644 index 0a53edbae8b8..000000000000 --- a/drivers/clk/mvebu/clk-core.c +++ /dev/null @@ -1,675 +0,0 @@ -/* - * Marvell EBU clock core handling defined at reset - * - * Copyright (C) 2012 Marvell - * - * Gregory CLEMENT <gregory.clement@free-electrons.com> - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/clk-provider.h> -#include <linux/of_address.h> -#include <linux/io.h> -#include <linux/of.h> -#include "clk-core.h" - -struct core_ratio { - int id; - const char *name; -}; - -struct core_clocks { - u32 (*get_tclk_freq)(void __iomem *sar); - u32 (*get_cpu_freq)(void __iomem *sar); - void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); - const struct core_ratio *ratios; - int num_ratios; -}; - -static struct clk_onecell_data clk_data; - -static void __init mvebu_clk_core_setup(struct device_node *np, - struct core_clocks *coreclk) -{ - const char *tclk_name = "tclk"; - const char *cpuclk_name = "cpuclk"; - void __iomem *base; - unsigned long rate; - int n; - - base = of_iomap(np, 0); - if (WARN_ON(!base)) - return; - - /* - * Allocate struct for TCLK, cpu clk, and core ratio clocks - */ - clk_data.clk_num = 2 + coreclk->num_ratios; - clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), - GFP_KERNEL); - if (WARN_ON(!clk_data.clks)) - return; - - /* - * Register TCLK - */ - of_property_read_string_index(np, "clock-output-names", 0, - &tclk_name); - rate = coreclk->get_tclk_freq(base); - clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, - CLK_IS_ROOT, rate); - WARN_ON(IS_ERR(clk_data.clks[0])); - - /* - * Register CPU clock - */ - of_property_read_string_index(np, "clock-output-names", 1, - &cpuclk_name); - rate = coreclk->get_cpu_freq(base); - clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, - CLK_IS_ROOT, rate); - WARN_ON(IS_ERR(clk_data.clks[1])); - - /* - * Register fixed-factor clocks derived from CPU clock - */ - for (n = 0; n < coreclk->num_ratios; n++) { - const char *rclk_name = coreclk->ratios[n].name; - int mult, div; - - of_property_read_string_index(np, "clock-output-names", - 2+n, &rclk_name); - coreclk->get_clk_ratio(base, coreclk->ratios[n].id, - &mult, &div); - clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name, - cpuclk_name, 0, mult, div); - WARN_ON(IS_ERR(clk_data.clks[2+n])); - }; - - /* - * SAR register isn't needed anymore - */ - iounmap(base); - - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -} - -#ifdef CONFIG_MACH_ARMADA_370_XP -/* - * Armada 370/XP Sample At Reset is a 64 bit bitfiled split in two - * register of 32 bits - */ - -#define SARL 0 /* Low part [0:31] */ -#define SARL_AXP_PCLK_FREQ_OPT 21 -#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7 -#define SARL_A370_PCLK_FREQ_OPT 11 -#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF -#define SARL_AXP_FAB_FREQ_OPT 24 -#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF -#define SARL_A370_FAB_FREQ_OPT 15 -#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F -#define SARL_A370_TCLK_FREQ_OPT 20 -#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1 -#define SARH 4 /* High part [32:63] */ -#define SARH_AXP_PCLK_FREQ_OPT (52-32) -#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1 -#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3 -#define SARH_AXP_FAB_FREQ_OPT (51-32) -#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1 -#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4 - -static const u32 __initconst armada_370_tclk_frequencies[] = { - 16600000, - 20000000, -}; - -static u32 __init armada_370_get_tclk_freq(void __iomem *sar) -{ - u8 tclk_freq_select = 0; - - tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & - SARL_A370_TCLK_FREQ_OPT_MASK); - return armada_370_tclk_frequencies[tclk_freq_select]; -} - -static const u32 __initconst armada_370_cpu_frequencies[] = { - 400000000, - 533000000, - 667000000, - 800000000, - 1000000000, - 1067000000, - 1200000000, -}; - -static u32 __init armada_370_get_cpu_freq(void __iomem *sar) -{ - u32 cpu_freq; - u8 cpu_freq_select = 0; - - cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & - SARL_A370_PCLK_FREQ_OPT_MASK); - if (cpu_freq_select >= ARRAY_SIZE(armada_370_cpu_frequencies)) { - pr_err("CPU freq select unsupported %d\n", cpu_freq_select); - cpu_freq = 0; - } else - cpu_freq = armada_370_cpu_frequencies[cpu_freq_select]; - - return cpu_freq; -} - -enum { A370_XP_NBCLK, A370_XP_HCLK, A370_XP_DRAMCLK }; - -static const struct core_ratio __initconst armada_370_xp_core_ratios[] = { - { .id = A370_XP_NBCLK, .name = "nbclk" }, - { .id = A370_XP_HCLK, .name = "hclk" }, - { .id = A370_XP_DRAMCLK, .name = "dramclk" }, -}; - -static const int __initconst armada_370_xp_nbclk_ratios[32][2] = { - {0, 1}, {1, 2}, {2, 2}, {2, 2}, - {1, 2}, {1, 2}, {1, 1}, {2, 3}, - {0, 1}, {1, 2}, {2, 4}, {0, 1}, - {1, 2}, {0, 1}, {0, 1}, {2, 2}, - {0, 1}, {0, 1}, {0, 1}, {1, 1}, - {2, 3}, {0, 1}, {0, 1}, {0, 1}, - {0, 1}, {0, 1}, {0, 1}, {1, 1}, - {0, 1}, {0, 1}, {0, 1}, {0, 1}, -}; - -static const int __initconst armada_370_xp_hclk_ratios[32][2] = { - {0, 1}, {1, 2}, {2, 6}, {2, 3}, - {1, 3}, {1, 4}, {1, 2}, {2, 6}, - {0, 1}, {1, 6}, {2, 10}, {0, 1}, - {1, 4}, {0, 1}, {0, 1}, {2, 5}, - {0, 1}, {0, 1}, {0, 1}, {1, 2}, - {2, 6}, {0, 1}, {0, 1}, {0, 1}, - {0, 1}, {0, 1}, {0, 1}, {1, 1}, - {0, 1}, {0, 1}, {0, 1}, {0, 1}, -}; - -static const int __initconst armada_370_xp_dramclk_ratios[32][2] = { - {0, 1}, {1, 2}, {2, 3}, {2, 3}, - {1, 3}, {1, 2}, {1, 2}, {2, 6}, - {0, 1}, {1, 3}, {2, 5}, {0, 1}, - {1, 4}, {0, 1}, {0, 1}, {2, 5}, - {0, 1}, {0, 1}, {0, 1}, {1, 1}, - {2, 3}, {0, 1}, {0, 1}, {0, 1}, - {0, 1}, {0, 1}, {0, 1}, {1, 1}, - {0, 1}, {0, 1}, {0, 1}, {0, 1}, -}; - -static void __init armada_370_xp_get_clk_ratio(u32 opt, - void __iomem *sar, int id, int *mult, int *div) -{ - switch (id) { - case A370_XP_NBCLK: - *mult = armada_370_xp_nbclk_ratios[opt][0]; - *div = armada_370_xp_nbclk_ratios[opt][1]; - break; - case A370_XP_HCLK: - *mult = armada_370_xp_hclk_ratios[opt][0]; - *div = armada_370_xp_hclk_ratios[opt][1]; - break; - case A370_XP_DRAMCLK: - *mult = armada_370_xp_dramclk_ratios[opt][0]; - *div = armada_370_xp_dramclk_ratios[opt][1]; - break; - } -} - -static void __init armada_370_get_clk_ratio( - void __iomem *sar, int id, int *mult, int *div) -{ - u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & - SARL_A370_FAB_FREQ_OPT_MASK); - - armada_370_xp_get_clk_ratio(opt, sar, id, mult, div); -} - - -static const struct core_clocks armada_370_core_clocks = { - .get_tclk_freq = armada_370_get_tclk_freq, - .get_cpu_freq = armada_370_get_cpu_freq, - .get_clk_ratio = armada_370_get_clk_ratio, - .ratios = armada_370_xp_core_ratios, - .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios), -}; - -static const u32 __initconst armada_xp_cpu_frequencies[] = { - 1000000000, - 1066000000, - 1200000000, - 1333000000, - 1500000000, - 1666000000, - 1800000000, - 2000000000, - 667000000, - 0, - 800000000, - 1600000000, -}; - -/* For Armada XP TCLK frequency is fix: 250MHz */ -static u32 __init armada_xp_get_tclk_freq(void __iomem *sar) -{ - return 250 * 1000 * 1000; -} - -static u32 __init armada_xp_get_cpu_freq(void __iomem *sar) -{ - u32 cpu_freq; - u8 cpu_freq_select = 0; - - cpu_freq_select = ((readl(sar) >> SARL_AXP_PCLK_FREQ_OPT) & - SARL_AXP_PCLK_FREQ_OPT_MASK); - /* - * The upper bit is not contiguous to the other ones and - * located in the high part of the SAR registers - */ - cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) & - SARH_AXP_PCLK_FREQ_OPT_MASK) - << SARH_AXP_PCLK_FREQ_OPT_SHIFT); - if (cpu_freq_select >= ARRAY_SIZE(armada_xp_cpu_frequencies)) { - pr_err("CPU freq select unsupported: %d\n", cpu_freq_select); - cpu_freq = 0; - } else - cpu_freq = armada_xp_cpu_frequencies[cpu_freq_select]; - - return cpu_freq; -} - -static void __init armada_xp_get_clk_ratio( - void __iomem *sar, int id, int *mult, int *div) -{ - - u32 opt = ((readl(sar) >> SARL_AXP_FAB_FREQ_OPT) & - SARL_AXP_FAB_FREQ_OPT_MASK); - /* - * The upper bit is not contiguous to the other ones and - * located in the high part of the SAR registers - */ - opt |= (((readl(sar+4) >> SARH_AXP_FAB_FREQ_OPT) & - SARH_AXP_FAB_FREQ_OPT_MASK) - << SARH_AXP_FAB_FREQ_OPT_SHIFT); - - armada_370_xp_get_clk_ratio(opt, sar, id, mult, div); -} - -static const struct core_clocks armada_xp_core_clocks = { - .get_tclk_freq = armada_xp_get_tclk_freq, - .get_cpu_freq = armada_xp_get_cpu_freq, - .get_clk_ratio = armada_xp_get_clk_ratio, - .ratios = armada_370_xp_core_ratios, - .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios), -}; - -#endif /* CONFIG_MACH_ARMADA_370_XP */ - -/* - * Dove PLL sample-at-reset configuration - * - * SAR0[8:5] : CPU frequency - * 5 = 1000 MHz - * 6 = 933 MHz - * 7 = 933 MHz - * 8 = 800 MHz - * 9 = 800 MHz - * 10 = 800 MHz - * 11 = 1067 MHz - * 12 = 667 MHz - * 13 = 533 MHz - * 14 = 400 MHz - * 15 = 333 MHz - * others reserved. - * - * SAR0[11:9] : CPU to L2 Clock divider ratio - * 0 = (1/1) * CPU - * 2 = (1/2) * CPU - * 4 = (1/3) * CPU - * 6 = (1/4) * CPU - * others reserved. - * - * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio - * 0 = (1/1) * CPU - * 2 = (1/2) * CPU - * 3 = (2/5) * CPU - * 4 = (1/3) * CPU - * 6 = (1/4) * CPU - * 8 = (1/5) * CPU - * 10 = (1/6) * CPU - * 12 = (1/7) * CPU - * 14 = (1/8) * CPU - * 15 = (1/10) * CPU - * others reserved. - * - * SAR0[24:23] : TCLK frequency - * 0 = 166 MHz - * 1 = 125 MHz - * others reserved. - */ -#ifdef CONFIG_ARCH_DOVE -#define SAR_DOVE_CPU_FREQ 5 -#define SAR_DOVE_CPU_FREQ_MASK 0xf -#define SAR_DOVE_L2_RATIO 9 -#define SAR_DOVE_L2_RATIO_MASK 0x7 -#define SAR_DOVE_DDR_RATIO 12 -#define SAR_DOVE_DDR_RATIO_MASK 0xf -#define SAR_DOVE_TCLK_FREQ 23 -#define SAR_DOVE_TCLK_FREQ_MASK 0x3 - -static const u32 __initconst dove_tclk_frequencies[] = { - 166666667, - 125000000, - 0, 0 -}; - -static u32 __init dove_get_tclk_freq(void __iomem *sar) -{ - u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & - SAR_DOVE_TCLK_FREQ_MASK; - return dove_tclk_frequencies[opt]; -} - -static const u32 __initconst dove_cpu_frequencies[] = { - 0, 0, 0, 0, 0, - 1000000000, - 933333333, 933333333, - 800000000, 800000000, 800000000, - 1066666667, - 666666667, - 533333333, - 400000000, - 333333333 -}; - -static u32 __init dove_get_cpu_freq(void __iomem *sar) -{ - u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & - SAR_DOVE_CPU_FREQ_MASK; - return dove_cpu_frequencies[opt]; -} - -enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR }; - -static const struct core_ratio __initconst dove_core_ratios[] = { - { .id = DOVE_CPU_TO_L2, .name = "l2clk", }, - { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", } -}; - -static const int __initconst dove_cpu_l2_ratios[8][2] = { - { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, - { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 } -}; - -static const int __initconst dove_cpu_ddr_ratios[16][2] = { - { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 }, - { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }, - { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 }, - { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 } -}; - -static void __init dove_get_clk_ratio( - void __iomem *sar, int id, int *mult, int *div) -{ - switch (id) { - case DOVE_CPU_TO_L2: - { - u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & - SAR_DOVE_L2_RATIO_MASK; - *mult = dove_cpu_l2_ratios[opt][0]; - *div = dove_cpu_l2_ratios[opt][1]; - break; - } - case DOVE_CPU_TO_DDR: - { - u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & - SAR_DOVE_DDR_RATIO_MASK; - *mult = dove_cpu_ddr_ratios[opt][0]; - *div = dove_cpu_ddr_ratios[opt][1]; - break; - } - } -} - -static const struct core_clocks dove_core_clocks = { - .get_tclk_freq = dove_get_tclk_freq, - .get_cpu_freq = dove_get_cpu_freq, - .get_clk_ratio = dove_get_clk_ratio, - .ratios = dove_core_ratios, - .num_ratios = ARRAY_SIZE(dove_core_ratios), -}; -#endif /* CONFIG_ARCH_DOVE */ - -/* - * Kirkwood PLL sample-at-reset configuration - * (6180 has different SAR layout than other Kirkwood SoCs) - * - * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282) - * 4 = 600 MHz - * 6 = 800 MHz - * 7 = 1000 MHz - * 9 = 1200 MHz - * 12 = 1500 MHz - * 13 = 1600 MHz - * 14 = 1800 MHz - * 15 = 2000 MHz - * others reserved. - * - * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282) - * 1 = (1/2) * CPU - * 3 = (1/3) * CPU - * 5 = (1/4) * CPU - * others reserved. - * - * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282) - * 2 = (1/2) * CPU - * 4 = (1/3) * CPU - * 6 = (1/4) * CPU - * 7 = (2/9) * CPU - * 8 = (1/5) * CPU - * 9 = (1/6) * CPU - * others reserved. - * - * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only) - * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU] - * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU] - * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU] - * others reserved. - * - * SAR0[21] : TCLK frequency - * 0 = 200 MHz - * 1 = 166 MHz - * others reserved. - */ -#ifdef CONFIG_ARCH_KIRKWOOD -#define SAR_KIRKWOOD_CPU_FREQ(x) \ - (((x & (1 << 1)) >> 1) | \ - ((x & (1 << 22)) >> 21) | \ - ((x & (3 << 3)) >> 1)) -#define SAR_KIRKWOOD_L2_RATIO(x) \ - (((x & (3 << 9)) >> 9) | \ - (((x & (1 << 19)) >> 17))) -#define SAR_KIRKWOOD_DDR_RATIO 5 -#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf -#define SAR_MV88F6180_CLK 2 -#define SAR_MV88F6180_CLK_MASK 0x7 -#define SAR_KIRKWOOD_TCLK_FREQ 21 -#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1 - -enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR }; - -static const struct core_ratio __initconst kirkwood_core_ratios[] = { - { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", }, - { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", } -}; - -static u32 __init kirkwood_get_tclk_freq(void __iomem *sar) -{ - u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & - SAR_KIRKWOOD_TCLK_FREQ_MASK; - return (opt) ? 166666667 : 200000000; -} - -static const u32 __initconst kirkwood_cpu_frequencies[] = { - 0, 0, 0, 0, - 600000000, - 0, - 800000000, - 1000000000, - 0, - 1200000000, - 0, 0, - 1500000000, - 1600000000, - 1800000000, - 2000000000 -}; - -static u32 __init kirkwood_get_cpu_freq(void __iomem *sar) -{ - u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); - return kirkwood_cpu_frequencies[opt]; -} - -static const int __initconst kirkwood_cpu_l2_ratios[8][2] = { - { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 }, - { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 } -}; - -static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = { - { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, - { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 }, - { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } -}; - -static void __init kirkwood_get_clk_ratio( - void __iomem *sar, int id, int *mult, int *div) -{ - switch (id) { - case KIRKWOOD_CPU_TO_L2: - { - u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); - *mult = kirkwood_cpu_l2_ratios[opt][0]; - *div = kirkwood_cpu_l2_ratios[opt][1]; - break; - } - case KIRKWOOD_CPU_TO_DDR: - { - u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & - SAR_KIRKWOOD_DDR_RATIO_MASK; - *mult = kirkwood_cpu_ddr_ratios[opt][0]; - *div = kirkwood_cpu_ddr_ratios[opt][1]; - break; - } - } -} - -static const struct core_clocks kirkwood_core_clocks = { - .get_tclk_freq = kirkwood_get_tclk_freq, - .get_cpu_freq = kirkwood_get_cpu_freq, - .get_clk_ratio = kirkwood_get_clk_ratio, - .ratios = kirkwood_core_ratios, - .num_ratios = ARRAY_SIZE(kirkwood_core_ratios), -}; - -static const u32 __initconst mv88f6180_cpu_frequencies[] = { - 0, 0, 0, 0, 0, - 600000000, - 800000000, - 1000000000 -}; - -static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar) -{ - u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK; - return mv88f6180_cpu_frequencies[opt]; -} - -static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = { - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 } -}; - -static void __init mv88f6180_get_clk_ratio( - void __iomem *sar, int id, int *mult, int *div) -{ - switch (id) { - case KIRKWOOD_CPU_TO_L2: - { - /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */ - *mult = 1; - *div = 2; - break; - } - case KIRKWOOD_CPU_TO_DDR: - { - u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & - SAR_MV88F6180_CLK_MASK; - *mult = mv88f6180_cpu_ddr_ratios[opt][0]; - *div = mv88f6180_cpu_ddr_ratios[opt][1]; - break; - } - } -} - -static const struct core_clocks mv88f6180_core_clocks = { - .get_tclk_freq = kirkwood_get_tclk_freq, - .get_cpu_freq = mv88f6180_get_cpu_freq, - .get_clk_ratio = mv88f6180_get_clk_ratio, - .ratios = kirkwood_core_ratios, - .num_ratios = ARRAY_SIZE(kirkwood_core_ratios), -}; -#endif /* CONFIG_ARCH_KIRKWOOD */ - -static const __initdata struct of_device_id clk_core_match[] = { -#ifdef CONFIG_MACH_ARMADA_370_XP - { - .compatible = "marvell,armada-370-core-clock", - .data = &armada_370_core_clocks, - }, - { - .compatible = "marvell,armada-xp-core-clock", - .data = &armada_xp_core_clocks, - }, -#endif -#ifdef CONFIG_ARCH_DOVE - { - .compatible = "marvell,dove-core-clock", - .data = &dove_core_clocks, - }, -#endif - -#ifdef CONFIG_ARCH_KIRKWOOD - { - .compatible = "marvell,kirkwood-core-clock", - .data = &kirkwood_core_clocks, - }, - { - .compatible = "marvell,mv88f6180-core-clock", - .data = &mv88f6180_core_clocks, - }, -#endif - - { } -}; - -void __init mvebu_core_clk_init(void) -{ - struct device_node *np; - - for_each_matching_node(np, clk_core_match) { - const struct of_device_id *match = - of_match_node(clk_core_match, np); - mvebu_clk_core_setup(np, (struct core_clocks *)match->data); - } -} diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h deleted file mode 100644 index 28b5e02e9885..000000000000 --- a/drivers/clk/mvebu/clk-core.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * * Marvell EBU clock core handling defined at reset - * - * Copyright (C) 2012 Marvell - * - * Gregory CLEMENT <gregory.clement@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MVEBU_CLK_CORE_H -#define __MVEBU_CLK_CORE_H - -void __init mvebu_core_clk_init(void); - -#endif diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c deleted file mode 100644 index ebf141d4374b..000000000000 --- a/drivers/clk/mvebu/clk-gating-ctrl.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Marvell MVEBU clock gating control. - * - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * Andrew Lunn <andrew@lunn.ch> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/kernel.h> -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> -#include <linux/of.h> -#include <linux/of_address.h> - -struct mvebu_gating_ctrl { - spinlock_t lock; - struct clk **gates; - int num_gates; -}; - -struct mvebu_soc_descr { - const char *name; - const char *parent; - int bit_idx; -}; - -#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) - -static struct clk *mvebu_clk_gating_get_src( - struct of_phandle_args *clkspec, void *data) -{ - struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data; - int n; - - if (clkspec->args_count < 1) - return ERR_PTR(-EINVAL); - - for (n = 0; n < ctrl->num_gates; n++) { - struct clk_gate *gate = - to_clk_gate(__clk_get_hw(ctrl->gates[n])); - if (clkspec->args[0] == gate->bit_idx) - return ctrl->gates[n]; - } - return ERR_PTR(-ENODEV); -} - -static void __init mvebu_clk_gating_setup( - struct device_node *np, const struct mvebu_soc_descr *descr) -{ - struct mvebu_gating_ctrl *ctrl; - struct clk *clk; - void __iomem *base; - const char *default_parent = NULL; - int n; - - base = of_iomap(np, 0); - - clk = of_clk_get(np, 0); - if (!IS_ERR(clk)) { - default_parent = __clk_get_name(clk); - clk_put(clk); - } - - ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL); - if (WARN_ON(!ctrl)) - return; - - spin_lock_init(&ctrl->lock); - - /* - * Count, allocate, and register clock gates - */ - for (n = 0; descr[n].name;) - n++; - - ctrl->num_gates = n; - ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), - GFP_KERNEL); - if (WARN_ON(!ctrl->gates)) { - kfree(ctrl); - return; - } - - for (n = 0; n < ctrl->num_gates; n++) { - u8 flags = 0; - const char *parent = - (descr[n].parent) ? descr[n].parent : default_parent; - - /* - * On Armada 370, the DDR clock is a special case: it - * isn't taken by any driver, but should anyway be - * kept enabled, so we mark it as IGNORE_UNUSED for - * now. - */ - if (!strcmp(descr[n].name, "ddr")) - flags |= CLK_IGNORE_UNUSED; - - ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent, - flags, base, descr[n].bit_idx, 0, &ctrl->lock); - WARN_ON(IS_ERR(ctrl->gates[n])); - } - of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl); -} - -/* - * SoC specific clock gating control - */ - -#ifdef CONFIG_MACH_ARMADA_370 -static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = { - { "audio", NULL, 0 }, - { "pex0_en", NULL, 1 }, - { "pex1_en", NULL, 2 }, - { "ge1", NULL, 3 }, - { "ge0", NULL, 4 }, - { "pex0", NULL, 5 }, - { "pex1", NULL, 9 }, - { "sata0", NULL, 15 }, - { "sdio", NULL, 17 }, - { "tdm", NULL, 25 }, - { "ddr", NULL, 28 }, - { "sata1", NULL, 30 }, - { } -}; -#endif - -#ifdef CONFIG_MACH_ARMADA_XP -static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = { - { "audio", NULL, 0 }, - { "ge3", NULL, 1 }, - { "ge2", NULL, 2 }, - { "ge1", NULL, 3 }, - { "ge0", NULL, 4 }, - { "pex0", NULL, 5 }, - { "pex1", NULL, 6 }, - { "pex2", NULL, 7 }, - { "pex3", NULL, 8 }, - { "bp", NULL, 13 }, - { "sata0lnk", NULL, 14 }, - { "sata0", "sata0lnk", 15 }, - { "lcd", NULL, 16 }, - { "sdio", NULL, 17 }, - { "usb0", NULL, 18 }, - { "usb1", NULL, 19 }, - { "usb2", NULL, 20 }, - { "xor0", NULL, 22 }, - { "crypto", NULL, 23 }, - { "tdm", NULL, 25 }, - { "xor1", NULL, 28 }, - { "sata1lnk", NULL, 29 }, - { "sata1", "sata1lnk", 30 }, - { } -}; -#endif - -#ifdef CONFIG_ARCH_DOVE -static const struct mvebu_soc_descr __initconst dove_gating_descr[] = { - { "usb0", NULL, 0 }, - { "usb1", NULL, 1 }, - { "ge", "gephy", 2 }, - { "sata", NULL, 3 }, - { "pex0", NULL, 4 }, - { "pex1", NULL, 5 }, - { "sdio0", NULL, 8 }, - { "sdio1", NULL, 9 }, - { "nand", NULL, 10 }, - { "camera", NULL, 11 }, - { "i2s0", NULL, 12 }, - { "i2s1", NULL, 13 }, - { "crypto", NULL, 15 }, - { "ac97", NULL, 21 }, - { "pdma", NULL, 22 }, - { "xor0", NULL, 23 }, - { "xor1", NULL, 24 }, - { "gephy", NULL, 30 }, - { } -}; -#endif - -#ifdef CONFIG_ARCH_KIRKWOOD -static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = { - { "ge0", NULL, 0 }, - { "pex0", NULL, 2 }, - { "usb0", NULL, 3 }, - { "sdio", NULL, 4 }, - { "tsu", NULL, 5 }, - { "runit", NULL, 7 }, - { "xor0", NULL, 8 }, - { "audio", NULL, 9 }, - { "powersave", "cpuclk", 11 }, - { "sata0", NULL, 14 }, - { "sata1", NULL, 15 }, - { "xor1", NULL, 16 }, - { "crypto", NULL, 17 }, - { "pex1", NULL, 18 }, - { "ge1", NULL, 19 }, - { "tdm", NULL, 20 }, - { } -}; -#endif - -static const __initdata struct of_device_id clk_gating_match[] = { -#ifdef CONFIG_MACH_ARMADA_370 - { - .compatible = "marvell,armada-370-gating-clock", - .data = armada_370_gating_descr, - }, -#endif - -#ifdef CONFIG_MACH_ARMADA_XP - { - .compatible = "marvell,armada-xp-gating-clock", - .data = armada_xp_gating_descr, - }, -#endif - -#ifdef CONFIG_ARCH_DOVE - { - .compatible = "marvell,dove-gating-clock", - .data = dove_gating_descr, - }, -#endif - -#ifdef CONFIG_ARCH_KIRKWOOD - { - .compatible = "marvell,kirkwood-gating-clock", - .data = kirkwood_gating_descr, - }, -#endif - - { } -}; - -void __init mvebu_gating_clk_init(void) -{ - struct device_node *np; - - for_each_matching_node(np, clk_gating_match) { - const struct of_device_id *match = - of_match_node(clk_gating_match, np); - mvebu_clk_gating_setup(np, - (const struct mvebu_soc_descr *)match->data); - } -} diff --git a/drivers/clk/mvebu/clk-gating-ctrl.h b/drivers/clk/mvebu/clk-gating-ctrl.h deleted file mode 100644 index 9275d1e51f1b..000000000000 --- a/drivers/clk/mvebu/clk-gating-ctrl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Marvell EBU gating clock handling - * - * Copyright (C) 2012 Marvell - * - * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MVEBU_CLK_GATING_H -#define __MVEBU_CLK_GATING_H - -#ifdef CONFIG_MVEBU_CLK_GATING -void __init mvebu_gating_clk_init(void); -#else -void mvebu_gating_clk_init(void) {} -#endif - -#endif diff --git a/drivers/clk/mvebu/clk.c b/drivers/clk/mvebu/clk.c deleted file mode 100644 index 29f10fb3006c..000000000000 --- a/drivers/clk/mvebu/clk.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Marvell EBU SoC clock handling. - * - * Copyright (C) 2012 Marvell - * - * Gregory CLEMENT <gregory.clement@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/kernel.h> -#include <linux/clk-provider.h> -#include <linux/of.h> -#include "clk-core.h" -#include "clk-gating-ctrl.h" - -void __init mvebu_clocks_init(void) -{ - mvebu_core_clk_init(); - mvebu_gating_clk_init(); - of_clk_init(NULL); -} diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c new file mode 100644 index 000000000000..adaa4a1821b8 --- /dev/null +++ b/drivers/clk/mvebu/common.c @@ -0,0 +1,163 @@ +/* + * Marvell EBU SoC common clock handling + * + * Copyright (C) 2012 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#include "common.h" + +/* + * Core Clocks + */ + +static struct clk_onecell_data clk_data; + +void __init mvebu_coreclk_setup(struct device_node *np, + const struct coreclk_soc_desc *desc) +{ + const char *tclk_name = "tclk"; + const char *cpuclk_name = "cpuclk"; + void __iomem *base; + unsigned long rate; + int n; + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + + /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ + clk_data.clk_num = 2 + desc->num_ratios; + clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), + GFP_KERNEL); + if (WARN_ON(!clk_data.clks)) + return; + + /* Register TCLK */ + of_property_read_string_index(np, "clock-output-names", 0, + &tclk_name); + rate = desc->get_tclk_freq(base); + clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, + CLK_IS_ROOT, rate); + WARN_ON(IS_ERR(clk_data.clks[0])); + + /* Register CPU clock */ + of_property_read_string_index(np, "clock-output-names", 1, + &cpuclk_name); + rate = desc->get_cpu_freq(base); + clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, + CLK_IS_ROOT, rate); + WARN_ON(IS_ERR(clk_data.clks[1])); + + /* Register fixed-factor clocks derived from CPU clock */ + for (n = 0; n < desc->num_ratios; n++) { + const char *rclk_name = desc->ratios[n].name; + int mult, div; + + of_property_read_string_index(np, "clock-output-names", + 2+n, &rclk_name); + desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); + clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name, + cpuclk_name, 0, mult, div); + WARN_ON(IS_ERR(clk_data.clks[2+n])); + }; + + /* SAR register isn't needed anymore */ + iounmap(base); + + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} + +/* + * Clock Gating Control + */ + +struct clk_gating_ctrl { + spinlock_t lock; + struct clk **gates; + int num_gates; +}; + +#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) + +static struct clk *clk_gating_get_src( + struct of_phandle_args *clkspec, void *data) +{ + struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data; + int n; + + if (clkspec->args_count < 1) + return ERR_PTR(-EINVAL); + + for (n = 0; n < ctrl->num_gates; n++) { + struct clk_gate *gate = + to_clk_gate(__clk_get_hw(ctrl->gates[n])); + if (clkspec->args[0] == gate->bit_idx) + return ctrl->gates[n]; + } + return ERR_PTR(-ENODEV); +} + +void __init mvebu_clk_gating_setup(struct device_node *np, + const struct clk_gating_soc_desc *desc) +{ + struct clk_gating_ctrl *ctrl; + struct clk *clk; + void __iomem *base; + const char *default_parent = NULL; + int n; + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + + clk = of_clk_get(np, 0); + if (!IS_ERR(clk)) { + default_parent = __clk_get_name(clk); + clk_put(clk); + } + + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); + if (WARN_ON(!ctrl)) + return; + + spin_lock_init(&ctrl->lock); + + /* Count, allocate, and register clock gates */ + for (n = 0; desc[n].name;) + n++; + + ctrl->num_gates = n; + ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), + GFP_KERNEL); + if (WARN_ON(!ctrl->gates)) { + kfree(ctrl); + return; + } + + for (n = 0; n < ctrl->num_gates; n++) { + const char *parent = + (desc[n].parent) ? desc[n].parent : default_parent; + ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, + desc[n].flags, base, desc[n].bit_idx, + 0, &ctrl->lock); + WARN_ON(IS_ERR(ctrl->gates[n])); + } + + of_clk_add_provider(np, clk_gating_get_src, ctrl); +} diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h new file mode 100644 index 000000000000..f968b4d9df92 --- /dev/null +++ b/drivers/clk/mvebu/common.h @@ -0,0 +1,48 @@ +/* + * Marvell EBU SoC common clock handling + * + * Copyright (C) 2012 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __CLK_MVEBU_COMMON_H_ +#define __CLK_MVEBU_COMMON_H_ + +#include <linux/kernel.h> + +struct device_node; + +struct coreclk_ratio { + int id; + const char *name; +}; + +struct coreclk_soc_desc { + u32 (*get_tclk_freq)(void __iomem *sar); + u32 (*get_cpu_freq)(void __iomem *sar); + void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); + const struct coreclk_ratio *ratios; + int num_ratios; +}; + +struct clk_gating_soc_desc { + const char *name; + const char *parent; + int bit_idx; + unsigned long flags; +}; + +void __init mvebu_coreclk_setup(struct device_node *np, + const struct coreclk_soc_desc *desc); + +void __init mvebu_clk_gating_setup(struct device_node *np, + const struct clk_gating_soc_desc *desc); + +#endif diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c new file mode 100644 index 000000000000..79d7aedf03fb --- /dev/null +++ b/drivers/clk/mvebu/dove.c @@ -0,0 +1,194 @@ +/* + * Marvell Dove SoC clocks + * + * Copyright (C) 2012 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/of.h> +#include "common.h" + +/* + * Core Clocks + * + * Dove PLL sample-at-reset configuration + * + * SAR0[8:5] : CPU frequency + * 5 = 1000 MHz + * 6 = 933 MHz + * 7 = 933 MHz + * 8 = 800 MHz + * 9 = 800 MHz + * 10 = 800 MHz + * 11 = 1067 MHz + * 12 = 667 MHz + * 13 = 533 MHz + * 14 = 400 MHz + * 15 = 333 MHz + * others reserved. + * + * SAR0[11:9] : CPU to L2 Clock divider ratio + * 0 = (1/1) * CPU + * 2 = (1/2) * CPU + * 4 = (1/3) * CPU + * 6 = (1/4) * CPU + * others reserved. + * + * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio + * 0 = (1/1) * CPU + * 2 = (1/2) * CPU + * 3 = (2/5) * CPU + * 4 = (1/3) * CPU + * 6 = (1/4) * CPU + * 8 = (1/5) * CPU + * 10 = (1/6) * CPU + * 12 = (1/7) * CPU + * 14 = (1/8) * CPU + * 15 = (1/10) * CPU + * others reserved. + * + * SAR0[24:23] : TCLK frequency + * 0 = 166 MHz + * 1 = 125 MHz + * others reserved. + */ + +#define SAR_DOVE_CPU_FREQ 5 +#define SAR_DOVE_CPU_FREQ_MASK 0xf +#define SAR_DOVE_L2_RATIO 9 +#define SAR_DOVE_L2_RATIO_MASK 0x7 +#define SAR_DOVE_DDR_RATIO 12 +#define SAR_DOVE_DDR_RATIO_MASK 0xf +#define SAR_DOVE_TCLK_FREQ 23 +#define SAR_DOVE_TCLK_FREQ_MASK 0x3 + +enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR }; + +static const struct coreclk_ratio __initconst dove_coreclk_ratios[] = { + { .id = DOVE_CPU_TO_L2, .name = "l2clk", }, + { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", } +}; + +static const u32 __initconst dove_tclk_freqs[] = { + 166666667, + 125000000, + 0, 0 +}; + +static u32 __init dove_get_tclk_freq(void __iomem *sar) +{ + u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & + SAR_DOVE_TCLK_FREQ_MASK; + return dove_tclk_freqs[opt]; +} + +static const u32 __initconst dove_cpu_freqs[] = { + 0, 0, 0, 0, 0, + 1000000000, + 933333333, 933333333, + 800000000, 800000000, 800000000, + 1066666667, + 666666667, + 533333333, + 400000000, + 333333333 +}; + +static u32 __init dove_get_cpu_freq(void __iomem *sar) +{ + u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & + SAR_DOVE_CPU_FREQ_MASK; + return dove_cpu_freqs[opt]; +} + +static const int __initconst dove_cpu_l2_ratios[8][2] = { + { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, + { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 } +}; + +static const int __initconst dove_cpu_ddr_ratios[16][2] = { + { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 }, + { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }, + { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 }, + { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 } +}; + +static void __init dove_get_clk_ratio( + void __iomem *sar, int id, int *mult, int *div) +{ + switch (id) { + case DOVE_CPU_TO_L2: + { + u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & + SAR_DOVE_L2_RATIO_MASK; + *mult = dove_cpu_l2_ratios[opt][0]; + *div = dove_cpu_l2_ratios[opt][1]; + break; + } + case DOVE_CPU_TO_DDR: + { + u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & + SAR_DOVE_DDR_RATIO_MASK; + *mult = dove_cpu_ddr_ratios[opt][0]; + *div = dove_cpu_ddr_ratios[opt][1]; + break; + } + } +} + +static const struct coreclk_soc_desc dove_coreclks = { + .get_tclk_freq = dove_get_tclk_freq, + .get_cpu_freq = dove_get_cpu_freq, + .get_clk_ratio = dove_get_clk_ratio, + .ratios = dove_coreclk_ratios, + .num_ratios = ARRAY_SIZE(dove_coreclk_ratios), +}; + +static void __init dove_coreclk_init(struct device_node *np) +{ + mvebu_coreclk_setup(np, &dove_coreclks); +} +CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init); + +/* + * Clock Gating Control + */ + +static const struct clk_gating_soc_desc __initconst dove_gating_desc[] = { + { "usb0", NULL, 0, 0 }, + { "usb1", NULL, 1, 0 }, + { "ge", "gephy", 2, 0 }, + { "sata", NULL, 3, 0 }, + { "pex0", NULL, 4, 0 }, + { "pex1", NULL, 5, 0 }, + { "sdio0", NULL, 8, 0 }, + { "sdio1", NULL, 9, 0 }, + { "nand", NULL, 10, 0 }, + { "camera", NULL, 11, 0 }, + { "i2s0", NULL, 12, 0 }, + { "i2s1", NULL, 13, 0 }, + { "crypto", NULL, 15, 0 }, + { "ac97", NULL, 21, 0 }, + { "pdma", NULL, 22, 0 }, + { "xor0", NULL, 23, 0 }, + { "xor1", NULL, 24, 0 }, + { "gephy", NULL, 30, 0 }, + { } +}; + +static void __init dove_clk_gating_init(struct device_node *np) +{ + mvebu_clk_gating_setup(np, dove_gating_desc); +} +CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock", + dove_clk_gating_init); diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c new file mode 100644 index 000000000000..71d24619ccdb --- /dev/null +++ b/drivers/clk/mvebu/kirkwood.c @@ -0,0 +1,247 @@ +/* + * Marvell Kirkwood SoC clocks + * + * Copyright (C) 2012 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/of.h> +#include "common.h" + +/* + * Core Clocks + * + * Kirkwood PLL sample-at-reset configuration + * (6180 has different SAR layout than other Kirkwood SoCs) + * + * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282) + * 4 = 600 MHz + * 6 = 800 MHz + * 7 = 1000 MHz + * 9 = 1200 MHz + * 12 = 1500 MHz + * 13 = 1600 MHz + * 14 = 1800 MHz + * 15 = 2000 MHz + * others reserved. + * + * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282) + * 1 = (1/2) * CPU + * 3 = (1/3) * CPU + * 5 = (1/4) * CPU + * others reserved. + * + * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282) + * 2 = (1/2) * CPU + * 4 = (1/3) * CPU + * 6 = (1/4) * CPU + * 7 = (2/9) * CPU + * 8 = (1/5) * CPU + * 9 = (1/6) * CPU + * others reserved. + * + * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only) + * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU] + * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU] + * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU] + * others reserved. + * + * SAR0[21] : TCLK frequency + * 0 = 200 MHz + * 1 = 166 MHz + * others reserved. + */ + +#define SAR_KIRKWOOD_CPU_FREQ(x) \ + (((x & (1 << 1)) >> 1) | \ + ((x & (1 << 22)) >> 21) | \ + ((x & (3 << 3)) >> 1)) +#define SAR_KIRKWOOD_L2_RATIO(x) \ + (((x & (3 << 9)) >> 9) | \ + (((x & (1 << 19)) >> 17))) +#define SAR_KIRKWOOD_DDR_RATIO 5 +#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf +#define SAR_MV88F6180_CLK 2 +#define SAR_MV88F6180_CLK_MASK 0x7 +#define SAR_KIRKWOOD_TCLK_FREQ 21 +#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1 + +enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR }; + +static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = { + { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", }, + { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", } +}; + +static u32 __init kirkwood_get_tclk_freq(void __iomem *sar) +{ + u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & + SAR_KIRKWOOD_TCLK_FREQ_MASK; + return (opt) ? 166666667 : 200000000; +} + +static const u32 __initconst kirkwood_cpu_freqs[] = { + 0, 0, 0, 0, + 600000000, + 0, + 800000000, + 1000000000, + 0, + 1200000000, + 0, 0, + 1500000000, + 1600000000, + 1800000000, + 2000000000 +}; + +static u32 __init kirkwood_get_cpu_freq(void __iomem *sar) +{ + u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); + return kirkwood_cpu_freqs[opt]; +} + +static const int __initconst kirkwood_cpu_l2_ratios[8][2] = { + { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 }, + { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 } +}; + +static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = { + { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, + { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 }, + { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } +}; + +static void __init kirkwood_get_clk_ratio( + void __iomem *sar, int id, int *mult, int *div) +{ + switch (id) { + case KIRKWOOD_CPU_TO_L2: + { + u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); + *mult = kirkwood_cpu_l2_ratios[opt][0]; + *div = kirkwood_cpu_l2_ratios[opt][1]; + break; + } + case KIRKWOOD_CPU_TO_DDR: + { + u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & + SAR_KIRKWOOD_DDR_RATIO_MASK; + *mult = kirkwood_cpu_ddr_ratios[opt][0]; + *div = kirkwood_cpu_ddr_ratios[opt][1]; + break; + } + } +} + +static const u32 __initconst mv88f6180_cpu_freqs[] = { + 0, 0, 0, 0, 0, + 600000000, + 800000000, + 1000000000 +}; + +static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar) +{ + u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK; + return mv88f6180_cpu_freqs[opt]; +} + +static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = { + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 } +}; + +static void __init mv88f6180_get_clk_ratio( + void __iomem *sar, int id, int *mult, int *div) +{ + switch (id) { + case KIRKWOOD_CPU_TO_L2: + { + /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */ + *mult = 1; + *div = 2; + break; + } + case KIRKWOOD_CPU_TO_DDR: + { + u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & + SAR_MV88F6180_CLK_MASK; + *mult = mv88f6180_cpu_ddr_ratios[opt][0]; + *div = mv88f6180_cpu_ddr_ratios[opt][1]; + break; + } + } +} + +static const struct coreclk_soc_desc kirkwood_coreclks = { + .get_tclk_freq = kirkwood_get_tclk_freq, + .get_cpu_freq = kirkwood_get_cpu_freq, + .get_clk_ratio = kirkwood_get_clk_ratio, + .ratios = kirkwood_coreclk_ratios, + .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios), +}; + +static void __init kirkwood_coreclk_init(struct device_node *np) +{ + mvebu_coreclk_setup(np, &kirkwood_coreclks); +} +CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock", + kirkwood_coreclk_init); + +static const struct coreclk_soc_desc mv88f6180_coreclks = { + .get_tclk_freq = kirkwood_get_tclk_freq, + .get_cpu_freq = mv88f6180_get_cpu_freq, + .get_clk_ratio = mv88f6180_get_clk_ratio, + .ratios = kirkwood_coreclk_ratios, + .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios), +}; + +static void __init mv88f6180_coreclk_init(struct device_node *np) +{ + mvebu_coreclk_setup(np, &mv88f6180_coreclks); +} +CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock", + mv88f6180_coreclk_init); + +/* + * Clock Gating Control + */ + +static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = { + { "ge0", NULL, 0, 0 }, + { "pex0", NULL, 2, 0 }, + { "usb0", NULL, 3, 0 }, + { "sdio", NULL, 4, 0 }, + { "tsu", NULL, 5, 0 }, + { "runit", NULL, 7, 0 }, + { "xor0", NULL, 8, 0 }, + { "audio", NULL, 9, 0 }, + { "powersave", "cpuclk", 11, 0 }, + { "sata0", NULL, 14, 0 }, + { "sata1", NULL, 15, 0 }, + { "xor1", NULL, 16, 0 }, + { "crypto", NULL, 17, 0 }, + { "pex1", NULL, 18, 0 }, + { "ge1", NULL, 19, 0 }, + { "tdm", NULL, 20, 0 }, + { } +}; + +static void __init kirkwood_clk_gating_init(struct device_node *np) +{ + mvebu_clk_gating_setup(np, kirkwood_gating_desc); +} +CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock", + kirkwood_clk_gating_init); diff --git a/drivers/of/address.c b/drivers/of/address.c index 04da786c84d2..fdd0636a987d 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -227,6 +227,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar, return __of_address_to_resource(dev, addrp, size, flags, NULL, r); } EXPORT_SYMBOL_GPL(of_pci_address_to_resource); + +int of_pci_range_parser_init(struct of_pci_range_parser *parser, + struct device_node *node) +{ + const int na = 3, ns = 2; + int rlen; + + parser->node = node; + parser->pna = of_n_addr_cells(node); + parser->np = parser->pna + na + ns; + + parser->range = of_get_property(node, "ranges", &rlen); + if (parser->range == NULL) + return -ENOENT; + + parser->end = parser->range + rlen / sizeof(__be32); + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_range_parser_init); + +struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, + struct of_pci_range *range) +{ + const int na = 3, ns = 2; + + if (!range) + return NULL; + + if (!parser->range || parser->range + parser->np > parser->end) + return NULL; + + range->pci_space = parser->range[0]; + range->flags = of_bus_pci_get_flags(parser->range); + range->pci_addr = of_read_number(parser->range + 1, ns); + range->cpu_addr = of_translate_address(parser->node, + parser->range + na); + range->size = of_read_number(parser->range + parser->pna + na, ns); + + parser->range += parser->np; + + /* Now consume following elements while they are contiguous */ + while (parser->range + parser->np <= parser->end) { + u32 flags, pci_space; + u64 pci_addr, cpu_addr, size; + + pci_space = be32_to_cpup(parser->range); + flags = of_bus_pci_get_flags(parser->range); + pci_addr = of_read_number(parser->range + 1, ns); + cpu_addr = of_translate_address(parser->node, + parser->range + na); + size = of_read_number(parser->range + parser->pna + na, ns); + + if (flags != range->flags) + break; + if (pci_addr != range->pci_addr + range->size || + cpu_addr != range->cpu_addr + range->size) + break; + + range->size += size; + parser->range += parser->np; + } + + return range; +} +EXPORT_SYMBOL_GPL(of_pci_range_parser_one); + #endif /* CONFIG_PCI */ /* diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c index 13e37e2d8ec1..42c687a820ac 100644 --- a/drivers/of/of_pci.c +++ b/drivers/of/of_pci.c @@ -5,14 +5,15 @@ #include <asm/prom.h> static inline int __of_pci_pci_compare(struct device_node *node, - unsigned int devfn) + unsigned int data) { - unsigned int size; - const __be32 *reg = of_get_property(node, "reg", &size); + int devfn; - if (!reg || size < 5 * sizeof(__be32)) + devfn = of_pci_get_devfn(node); + if (devfn < 0) return 0; - return ((be32_to_cpup(®[0]) >> 8) & 0xff) == devfn; + + return devfn == data; } struct device_node *of_pci_find_child_device(struct device_node *parent, @@ -40,3 +41,51 @@ struct device_node *of_pci_find_child_device(struct device_node *parent, return NULL; } EXPORT_SYMBOL_GPL(of_pci_find_child_device); + +/** + * of_pci_get_devfn() - Get device and function numbers for a device node + * @np: device node + * + * Parses a standard 5-cell PCI resource and returns an 8-bit value that can + * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device + * and function numbers respectively. On error a negative error code is + * returned. + */ +int of_pci_get_devfn(struct device_node *np) +{ + unsigned int size; + const __be32 *reg; + + reg = of_get_property(np, "reg", &size); + + if (!reg || size < 5 * sizeof(__be32)) + return -EINVAL; + + return (be32_to_cpup(reg) >> 8) & 0xff; +} +EXPORT_SYMBOL_GPL(of_pci_get_devfn); + +/** + * of_pci_parse_bus_range() - parse the bus-range property of a PCI device + * @node: device node + * @res: address to a struct resource to return the bus-range + * + * Returns 0 on success or a negative error-code on failure. + */ +int of_pci_parse_bus_range(struct device_node *node, struct resource *res) +{ + const __be32 *values; + int len; + + values = of_get_property(node, "bus-range", &len); + if (!values || len < sizeof(*values) * 2) + return -EINVAL; + + res->name = node->name; + res->start = be32_to_cpup(values++); + res->end = be32_to_cpup(values); + res->flags = IORESOURCE_BUS; + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_parse_bus_range); diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 6d51aa68ec7a..ac45398ebb8e 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -119,3 +119,5 @@ config PCI_IOAPIC config PCI_LABEL def_bool y if (DMI || ACPI) select NLS + +source "drivers/pci/host/Kconfig" diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 0c3efcffa83b..6ebf5bf8e7a7 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o obj-$(CONFIG_OF) += of.o ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG + +# PCI host controller drivers +obj-y += host/ diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig new file mode 100644 index 000000000000..1f1d67fec8b2 --- /dev/null +++ b/drivers/pci/host/Kconfig @@ -0,0 +1,8 @@ +menu "PCI host controller drivers" + depends on PCI + +config PCI_MVEBU + bool "Marvell EBU PCIe controller" + depends on ARCH_MVEBU || ARCH_KIRKWOOD + +endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile new file mode 100644 index 000000000000..5ea2d8bf013a --- /dev/null +++ b/drivers/pci/host/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c new file mode 100644 index 000000000000..13a633b1612e --- /dev/null +++ b/drivers/pci/host/pci-mvebu.c @@ -0,0 +1,914 @@ +/* + * PCIe driver for Marvell Armada 370 and Armada XP SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/mbus.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/of_address.h> +#include <linux/of_pci.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> + +/* + * PCIe unit register offsets. + */ +#define PCIE_DEV_ID_OFF 0x0000 +#define PCIE_CMD_OFF 0x0004 +#define PCIE_DEV_REV_OFF 0x0008 +#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) +#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) +#define PCIE_HEADER_LOG_4_OFF 0x0128 +#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) +#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) +#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) +#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) +#define PCIE_WIN5_CTRL_OFF 0x1880 +#define PCIE_WIN5_BASE_OFF 0x1884 +#define PCIE_WIN5_REMAP_OFF 0x188c +#define PCIE_CONF_ADDR_OFF 0x18f8 +#define PCIE_CONF_ADDR_EN 0x80000000 +#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) +#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) +#define PCIE_CONF_ADDR(bus, devfn, where) \ + (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ + PCIE_CONF_ADDR_EN) +#define PCIE_CONF_DATA_OFF 0x18fc +#define PCIE_MASK_OFF 0x1910 +#define PCIE_MASK_ENABLE_INTS 0x0f000000 +#define PCIE_CTRL_OFF 0x1a00 +#define PCIE_CTRL_X1_MODE 0x0001 +#define PCIE_STAT_OFF 0x1a04 +#define PCIE_STAT_BUS 0xff00 +#define PCIE_STAT_DEV 0x1f0000 +#define PCIE_STAT_LINK_DOWN BIT(0) +#define PCIE_DEBUG_CTRL 0x1a60 +#define PCIE_DEBUG_SOFT_RESET BIT(20) + +/* + * This product ID is registered by Marvell, and used when the Marvell + * SoC is not the root complex, but an endpoint on the PCIe bus. It is + * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI + * bridge. + */ +#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846 + +/* PCI configuration space of a PCI-to-PCI bridge */ +struct mvebu_sw_pci_bridge { + u16 vendor; + u16 device; + u16 command; + u16 class; + u8 interface; + u8 revision; + u8 bist; + u8 header_type; + u8 latency_timer; + u8 cache_line_size; + u32 bar[2]; + u8 primary_bus; + u8 secondary_bus; + u8 subordinate_bus; + u8 secondary_latency_timer; + u8 iobase; + u8 iolimit; + u16 secondary_status; + u16 membase; + u16 memlimit; + u16 prefmembase; + u16 prefmemlimit; + u32 prefbaseupper; + u32 preflimitupper; + u16 iobaseupper; + u16 iolimitupper; + u8 cappointer; + u8 reserved1; + u16 reserved2; + u32 romaddr; + u8 intline; + u8 intpin; + u16 bridgectrl; +}; + +struct mvebu_pcie_port; + +/* Structure representing all PCIe interfaces */ +struct mvebu_pcie { + struct platform_device *pdev; + struct mvebu_pcie_port *ports; + struct resource io; + struct resource realio; + struct resource mem; + struct resource busn; + int nports; +}; + +/* Structure representing one PCIe interface */ +struct mvebu_pcie_port { + char *name; + void __iomem *base; + spinlock_t conf_lock; + int haslink; + u32 port; + u32 lane; + int devfn; + struct clk *clk; + struct mvebu_sw_pci_bridge bridge; + struct device_node *dn; + struct mvebu_pcie *pcie; + phys_addr_t memwin_base; + size_t memwin_size; + phys_addr_t iowin_base; + size_t iowin_size; +}; + +static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) +{ + return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); +} + +static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) +{ + u32 stat; + + stat = readl(port->base + PCIE_STAT_OFF); + stat &= ~PCIE_STAT_BUS; + stat |= nr << 8; + writel(stat, port->base + PCIE_STAT_OFF); +} + +static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) +{ + u32 stat; + + stat = readl(port->base + PCIE_STAT_OFF); + stat &= ~PCIE_STAT_DEV; + stat |= nr << 16; + writel(stat, port->base + PCIE_STAT_OFF); +} + +/* + * Setup PCIE BARs and Address Decode Wins: + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks + * WIN[0-3] -> DRAM bank[0-3] + */ +static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) +{ + const struct mbus_dram_target_info *dram; + u32 size; + int i; + + dram = mv_mbus_dram_info(); + + /* First, disable and clear BARs and windows. */ + for (i = 1; i < 3; i++) { + writel(0, port->base + PCIE_BAR_CTRL_OFF(i)); + writel(0, port->base + PCIE_BAR_LO_OFF(i)); + writel(0, port->base + PCIE_BAR_HI_OFF(i)); + } + + for (i = 0; i < 5; i++) { + writel(0, port->base + PCIE_WIN04_CTRL_OFF(i)); + writel(0, port->base + PCIE_WIN04_BASE_OFF(i)); + writel(0, port->base + PCIE_WIN04_REMAP_OFF(i)); + } + + writel(0, port->base + PCIE_WIN5_CTRL_OFF); + writel(0, port->base + PCIE_WIN5_BASE_OFF); + writel(0, port->base + PCIE_WIN5_REMAP_OFF); + + /* Setup windows for DDR banks. Count total DDR size on the fly. */ + size = 0; + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + writel(cs->base & 0xffff0000, + port->base + PCIE_WIN04_BASE_OFF(i)); + writel(0, port->base + PCIE_WIN04_REMAP_OFF(i)); + writel(((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + port->base + PCIE_WIN04_CTRL_OFF(i)); + + size += cs->size; + } + + /* Round up 'size' to the nearest power of two. */ + if ((size & (size - 1)) != 0) + size = 1 << fls(size); + + /* Setup BAR[1] to all DRAM banks. */ + writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1)); + writel(0, port->base + PCIE_BAR_HI_OFF(1)); + writel(((size - 1) & 0xffff0000) | 1, + port->base + PCIE_BAR_CTRL_OFF(1)); +} + +static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) +{ + u16 cmd; + u32 mask; + + /* Point PCIe unit MBUS decode windows to DRAM space. */ + mvebu_pcie_setup_wins(port); + + /* Master + slave enable. */ + cmd = readw(port->base + PCIE_CMD_OFF); + cmd |= PCI_COMMAND_IO; + cmd |= PCI_COMMAND_MEMORY; + cmd |= PCI_COMMAND_MASTER; + writew(cmd, port->base + PCIE_CMD_OFF); + + /* Enable interrupt lines A-D. */ + mask = readl(port->base + PCIE_MASK_OFF); + mask |= PCIE_MASK_ENABLE_INTS; + writel(mask, port->base + PCIE_MASK_OFF); +} + +static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, + struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + writel(PCIE_CONF_ADDR(bus->number, devfn, where), + port->base + PCIE_CONF_ADDR_OFF); + + *val = readl(port->base + PCIE_CONF_DATA_OFF); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, + struct pci_bus *bus, + u32 devfn, int where, int size, u32 val) +{ + int ret = PCIBIOS_SUCCESSFUL; + + writel(PCIE_CONF_ADDR(bus->number, devfn, where), + port->base + PCIE_CONF_ADDR_OFF); + + if (size == 4) + writel(val, port->base + PCIE_CONF_DATA_OFF); + else if (size == 2) + writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3)); + else if (size == 1) + writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3)); + else + ret = PCIBIOS_BAD_REGISTER_NUMBER; + + return ret; +} + +static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) +{ + phys_addr_t iobase; + + /* Are the new iobase/iolimit values invalid? */ + if (port->bridge.iolimit < port->bridge.iobase || + port->bridge.iolimitupper < port->bridge.iobaseupper) { + + /* If a window was configured, remove it */ + if (port->iowin_base) { + mvebu_mbus_del_window(port->iowin_base, + port->iowin_size); + port->iowin_base = 0; + port->iowin_size = 0; + } + + return; + } + + /* + * We read the PCI-to-PCI bridge emulated registers, and + * calculate the base address and size of the address decoding + * window to setup, according to the PCI-to-PCI bridge + * specifications. iobase is the bus address, port->iowin_base + * is the CPU address. + */ + iobase = ((port->bridge.iobase & 0xF0) << 8) | + (port->bridge.iobaseupper << 16); + port->iowin_base = port->pcie->io.start + iobase; + port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | + (port->bridge.iolimitupper << 16)) - + iobase); + + mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base, + port->iowin_size, + iobase, + MVEBU_MBUS_PCI_IO); + + pci_ioremap_io(iobase, port->iowin_base); +} + +static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) +{ + /* Are the new membase/memlimit values invalid? */ + if (port->bridge.memlimit < port->bridge.membase) { + + /* If a window was configured, remove it */ + if (port->memwin_base) { + mvebu_mbus_del_window(port->memwin_base, + port->memwin_size); + port->memwin_base = 0; + port->memwin_size = 0; + } + + return; + } + + /* + * We read the PCI-to-PCI bridge emulated registers, and + * calculate the base address and size of the address decoding + * window to setup, according to the PCI-to-PCI bridge + * specifications. + */ + port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); + port->memwin_size = + (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - + port->memwin_base; + + mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base, + port->memwin_size, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); +} + +/* + * Initialize the configuration space of the PCI-to-PCI bridge + * associated with the given PCIe interface. + */ +static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) +{ + struct mvebu_sw_pci_bridge *bridge = &port->bridge; + + memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); + + bridge->class = PCI_CLASS_BRIDGE_PCI; + bridge->vendor = PCI_VENDOR_ID_MARVELL; + bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID; + bridge->header_type = PCI_HEADER_TYPE_BRIDGE; + bridge->cache_line_size = 0x10; + + /* We support 32 bits I/O addressing */ + bridge->iobase = PCI_IO_RANGE_TYPE_32; + bridge->iolimit = PCI_IO_RANGE_TYPE_32; +} + +/* + * Read the configuration space of the PCI-to-PCI bridge associated to + * the given PCIe interface. + */ +static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, + unsigned int where, int size, u32 *value) +{ + struct mvebu_sw_pci_bridge *bridge = &port->bridge; + + switch (where & ~3) { + case PCI_VENDOR_ID: + *value = bridge->device << 16 | bridge->vendor; + break; + + case PCI_COMMAND: + *value = bridge->command; + break; + + case PCI_CLASS_REVISION: + *value = bridge->class << 16 | bridge->interface << 8 | + bridge->revision; + break; + + case PCI_CACHE_LINE_SIZE: + *value = bridge->bist << 24 | bridge->header_type << 16 | + bridge->latency_timer << 8 | bridge->cache_line_size; + break; + + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: + *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; + break; + + case PCI_PRIMARY_BUS: + *value = (bridge->secondary_latency_timer << 24 | + bridge->subordinate_bus << 16 | + bridge->secondary_bus << 8 | + bridge->primary_bus); + break; + + case PCI_IO_BASE: + *value = (bridge->secondary_status << 16 | + bridge->iolimit << 8 | + bridge->iobase); + break; + + case PCI_MEMORY_BASE: + *value = (bridge->memlimit << 16 | bridge->membase); + break; + + case PCI_PREF_MEMORY_BASE: + *value = (bridge->prefmemlimit << 16 | bridge->prefmembase); + break; + + case PCI_PREF_BASE_UPPER32: + *value = bridge->prefbaseupper; + break; + + case PCI_PREF_LIMIT_UPPER32: + *value = bridge->preflimitupper; + break; + + case PCI_IO_BASE_UPPER16: + *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); + break; + + case PCI_ROM_ADDRESS1: + *value = 0; + break; + + default: + *value = 0xffffffff; + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + if (size == 2) + *value = (*value >> (8 * (where & 3))) & 0xffff; + else if (size == 1) + *value = (*value >> (8 * (where & 3))) & 0xff; + + return PCIBIOS_SUCCESSFUL; +} + +/* Write to the PCI-to-PCI bridge configuration space */ +static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, + unsigned int where, int size, u32 value) +{ + struct mvebu_sw_pci_bridge *bridge = &port->bridge; + u32 mask, reg; + int err; + + if (size == 4) + mask = 0x0; + else if (size == 2) + mask = ~(0xffff << ((where & 3) * 8)); + else if (size == 1) + mask = ~(0xff << ((where & 3) * 8)); + else + return PCIBIOS_BAD_REGISTER_NUMBER; + + err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); + if (err) + return err; + + value = (reg & mask) | value << ((where & 3) * 8); + + switch (where & ~3) { + case PCI_COMMAND: + bridge->command = value & 0xffff; + break; + + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: + bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; + break; + + case PCI_IO_BASE: + /* + * We also keep bit 1 set, it is a read-only bit that + * indicates we support 32 bits addressing for the + * I/O + */ + bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; + bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; + bridge->secondary_status = value >> 16; + mvebu_pcie_handle_iobase_change(port); + break; + + case PCI_MEMORY_BASE: + bridge->membase = value & 0xffff; + bridge->memlimit = value >> 16; + mvebu_pcie_handle_membase_change(port); + break; + + case PCI_PREF_MEMORY_BASE: + bridge->prefmembase = value & 0xffff; + bridge->prefmemlimit = value >> 16; + break; + + case PCI_PREF_BASE_UPPER32: + bridge->prefbaseupper = value; + break; + + case PCI_PREF_LIMIT_UPPER32: + bridge->preflimitupper = value; + break; + + case PCI_IO_BASE_UPPER16: + bridge->iobaseupper = value & 0xffff; + bridge->iolimitupper = value >> 16; + mvebu_pcie_handle_iobase_change(port); + break; + + case PCI_PRIMARY_BUS: + bridge->primary_bus = value & 0xff; + bridge->secondary_bus = (value >> 8) & 0xff; + bridge->subordinate_bus = (value >> 16) & 0xff; + bridge->secondary_latency_timer = (value >> 24) & 0xff; + mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); + break; + + default: + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) +{ + return sys->private_data; +} + +static struct mvebu_pcie_port * +mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus, + int devfn) +{ + int i; + + for (i = 0; i < pcie->nports; i++) { + struct mvebu_pcie_port *port = &pcie->ports[i]; + if (bus->number == 0 && port->devfn == devfn) + return port; + if (bus->number != 0 && + bus->number >= port->bridge.secondary_bus && + bus->number <= port->bridge.subordinate_bus) + return port; + } + + return NULL; +} + +/* PCI configuration space write function */ +static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); + struct mvebu_pcie_port *port; + unsigned long flags; + int ret; + + port = mvebu_pcie_find_port(pcie, bus, devfn); + if (!port) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Access the emulated PCI-to-PCI bridge */ + if (bus->number == 0) + return mvebu_sw_pci_bridge_write(port, where, size, val); + + if (!port->haslink) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* + * On the secondary bus, we don't want to expose any other + * device than the device physically connected in the PCIe + * slot, visible in slot 0. In slot 1, there's a special + * Marvell device that only makes sense when the Armada is + * used as a PCIe endpoint. + */ + if (bus->number == port->bridge.secondary_bus && + PCI_SLOT(devfn) != 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Access the real PCIe interface */ + spin_lock_irqsave(&port->conf_lock, flags); + ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, + where, size, val); + spin_unlock_irqrestore(&port->conf_lock, flags); + + return ret; +} + +/* PCI configuration space read function */ +static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); + struct mvebu_pcie_port *port; + unsigned long flags; + int ret; + + port = mvebu_pcie_find_port(pcie, bus, devfn); + if (!port) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + /* Access the emulated PCI-to-PCI bridge */ + if (bus->number == 0) + return mvebu_sw_pci_bridge_read(port, where, size, val); + + if (!port->haslink) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + /* + * On the secondary bus, we don't want to expose any other + * device than the device physically connected in the PCIe + * slot, visible in slot 0. In slot 1, there's a special + * Marvell device that only makes sense when the Armada is + * used as a PCIe endpoint. + */ + if (bus->number == port->bridge.secondary_bus && + PCI_SLOT(devfn) != 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + /* Access the real PCIe interface */ + spin_lock_irqsave(&port->conf_lock, flags); + ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, + where, size, val); + spin_unlock_irqrestore(&port->conf_lock, flags); + + return ret; +} + +static struct pci_ops mvebu_pcie_ops = { + .read = mvebu_pcie_rd_conf, + .write = mvebu_pcie_wr_conf, +}; + +static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys) +{ + struct mvebu_pcie *pcie = sys_to_pcie(sys); + int i; + + pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset); + pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); + pci_add_resource(&sys->resources, &pcie->busn); + + for (i = 0; i < pcie->nports; i++) { + struct mvebu_pcie_port *port = &pcie->ports[i]; + mvebu_pcie_setup_hw(port); + } + + return 1; +} + +static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct of_irq oirq; + int ret; + + ret = of_irq_map_pci(dev, &oirq); + if (ret) + return ret; + + return irq_create_of_mapping(oirq.controller, oirq.specifier, + oirq.size); +} + +static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct mvebu_pcie *pcie = sys_to_pcie(sys); + struct pci_bus *bus; + + bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr, + &mvebu_pcie_ops, sys, &sys->resources); + if (!bus) + return NULL; + + pci_scan_child_bus(bus); + + return bus; +} + +resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, + const struct resource *res, + resource_size_t start, + resource_size_t size, + resource_size_t align) +{ + if (dev->bus->number != 0) + return start; + + /* + * On the PCI-to-PCI bridge side, the I/O windows must have at + * least a 64 KB size and be aligned on their size, and the + * memory windows must have at least a 1 MB size and be + * aligned on their size + */ + if (res->flags & IORESOURCE_IO) + return round_up(start, max((resource_size_t)SZ_64K, size)); + else if (res->flags & IORESOURCE_MEM) + return round_up(start, max((resource_size_t)SZ_1M, size)); + else + return start; +} + +static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie) +{ + struct hw_pci hw; + + memset(&hw, 0, sizeof(hw)); + + hw.nr_controllers = 1; + hw.private_data = (void **)&pcie; + hw.setup = mvebu_pcie_setup; + hw.scan = mvebu_pcie_scan_bus; + hw.map_irq = mvebu_pcie_map_irq; + hw.ops = &mvebu_pcie_ops; + hw.align_resource = mvebu_pcie_align_resource; + + pci_common_init(&hw); +} + +/* + * Looks up the list of register addresses encoded into the reg = + * <...> property for one that matches the given port/lane. Once + * found, maps it. + */ +static void __iomem * __init +mvebu_pcie_map_registers(struct platform_device *pdev, + struct device_node *np, + struct mvebu_pcie_port *port) +{ + struct resource regs; + int ret = 0; + + ret = of_address_to_resource(np, 0, ®s); + if (ret) + return NULL; + + return devm_request_and_ioremap(&pdev->dev, ®s); +} + +static int __init mvebu_pcie_probe(struct platform_device *pdev) +{ + struct mvebu_pcie *pcie; + struct device_node *np = pdev->dev.of_node; + struct of_pci_range range; + struct of_pci_range_parser parser; + struct device_node *child; + int i, ret; + + pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie), + GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->pdev = pdev; + + if (of_pci_range_parser_init(&parser, np)) + return -EINVAL; + + /* Get the I/O and memory ranges from DT */ + for_each_of_pci_range(&parser, &range) { + unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; + if (restype == IORESOURCE_IO) { + of_pci_range_to_resource(&range, np, &pcie->io); + of_pci_range_to_resource(&range, np, &pcie->realio); + pcie->io.name = "I/O"; + pcie->realio.start = max_t(resource_size_t, + PCIBIOS_MIN_IO, + range.pci_addr); + pcie->realio.end = min_t(resource_size_t, + IO_SPACE_LIMIT, + range.pci_addr + range.size); + } + if (restype == IORESOURCE_MEM) { + of_pci_range_to_resource(&range, np, &pcie->mem); + pcie->mem.name = "MEM"; + } + } + + /* Get the bus range */ + ret = of_pci_parse_bus_range(np, &pcie->busn); + if (ret) { + dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", + ret); + return ret; + } + + for_each_child_of_node(pdev->dev.of_node, child) { + if (!of_device_is_available(child)) + continue; + pcie->nports++; + } + + pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports * + sizeof(struct mvebu_pcie_port), + GFP_KERNEL); + if (!pcie->ports) + return -ENOMEM; + + i = 0; + for_each_child_of_node(pdev->dev.of_node, child) { + struct mvebu_pcie_port *port = &pcie->ports[i]; + + if (!of_device_is_available(child)) + continue; + + port->pcie = pcie; + + if (of_property_read_u32(child, "marvell,pcie-port", + &port->port)) { + dev_warn(&pdev->dev, + "ignoring PCIe DT node, missing pcie-port property\n"); + continue; + } + + if (of_property_read_u32(child, "marvell,pcie-lane", + &port->lane)) + port->lane = 0; + + port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", + port->port, port->lane); + + port->devfn = of_pci_get_devfn(child); + if (port->devfn < 0) + continue; + + port->base = mvebu_pcie_map_registers(pdev, child, port); + if (!port->base) { + dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n", + port->port, port->lane); + continue; + } + + mvebu_pcie_set_local_dev_nr(port, 1); + + if (mvebu_pcie_link_up(port)) { + port->haslink = 1; + dev_info(&pdev->dev, "PCIe%d.%d: link up\n", + port->port, port->lane); + } else { + port->haslink = 0; + dev_info(&pdev->dev, "PCIe%d.%d: link down\n", + port->port, port->lane); + } + + port->clk = of_clk_get_by_name(child, NULL); + if (IS_ERR(port->clk)) { + dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n", + port->port, port->lane); + iounmap(port->base); + port->haslink = 0; + continue; + } + + port->dn = child; + + clk_prepare_enable(port->clk); + spin_lock_init(&port->conf_lock); + + mvebu_sw_pci_bridge_init(port); + + i++; + } + + mvebu_pcie_enable(pcie); + + return 0; +} + +static const struct of_device_id mvebu_pcie_of_match_table[] = { + { .compatible = "marvell,armada-xp-pcie", }, + { .compatible = "marvell,armada-370-pcie", }, + { .compatible = "marvell,kirkwood-pcie", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); + +static struct platform_driver mvebu_pcie_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mvebu-pcie", + .of_match_table = + of_match_ptr(mvebu_pcie_of_match_table), + }, +}; + +static int __init mvebu_pcie_init(void) +{ + return platform_driver_probe(&mvebu_pcie_driver, + mvebu_pcie_probe); +} + +subsys_initcall(mvebu_pcie_init); + +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell EBU PCIe driver"); +MODULE_LICENSE("GPLv2"); diff --git a/include/linux/clk/mvebu.h b/include/linux/clk/mvebu.h deleted file mode 100644 index 8c4ae713b063..000000000000 --- a/include/linux/clk/mvebu.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __CLK_MVEBU_H_ -#define __CLK_MVEBU_H_ - -void __init mvebu_clocks_init(void); - -#endif diff --git a/include/linux/of_address.h b/include/linux/of_address.h index 0506eb53519b..4c2e6f26432c 100644 --- a/include/linux/of_address.h +++ b/include/linux/of_address.h @@ -4,6 +4,36 @@ #include <linux/errno.h> #include <linux/of.h> +struct of_pci_range_parser { + struct device_node *node; + const __be32 *range; + const __be32 *end; + int np; + int pna; +}; + +struct of_pci_range { + u32 pci_space; + u64 pci_addr; + u64 cpu_addr; + u64 size; + u32 flags; +}; + +#define for_each_of_pci_range(parser, range) \ + for (; of_pci_range_parser_one(parser, range);) + +static inline void of_pci_range_to_resource(struct of_pci_range *range, + struct device_node *np, + struct resource *res) +{ + res->flags = range->flags; + res->start = range->cpu_addr; + res->end = range->cpu_addr + range->size - 1; + res->parent = res->child = res->sibling = NULL; + res->name = np->full_name; +} + #ifdef CONFIG_OF_ADDRESS extern u64 of_translate_address(struct device_node *np, const __be32 *addr); extern bool of_can_translate_address(struct device_node *dev); @@ -27,6 +57,11 @@ static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } #define pci_address_to_pio pci_address_to_pio #endif +extern int of_pci_range_parser_init(struct of_pci_range_parser *parser, + struct device_node *node); +extern struct of_pci_range *of_pci_range_parser_one( + struct of_pci_range_parser *parser, + struct of_pci_range *range); #else /* CONFIG_OF_ADDRESS */ #ifndef of_address_to_resource static inline int of_address_to_resource(struct device_node *dev, int index, @@ -53,6 +88,19 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index, { return NULL; } + +static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser, + struct device_node *node) +{ + return -1; +} + +static inline struct of_pci_range *of_pci_range_parser_one( + struct of_pci_range_parser *parser, + struct of_pci_range *range) +{ + return NULL; +} #endif /* CONFIG_OF_ADDRESS */ diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index bb115deb7612..7a04826018c0 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h @@ -10,5 +10,7 @@ int of_irq_map_pci(const struct pci_dev *pdev, struct of_irq *out_irq); struct device_node; struct device_node *of_pci_find_child_device(struct device_node *parent, unsigned int devfn); +int of_pci_get_devfn(struct device_node *np); +int of_pci_parse_bus_range(struct device_node *node, struct resource *res); #endif |