diff options
37 files changed, 2630 insertions, 83 deletions
diff --git a/Documentation/ABI/testing/sysfs-class-power-mp2629 b/Documentation/ABI/testing/sysfs-class-power-mp2629 new file mode 100644 index 000000000000..327a07e22805 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-power-mp2629 @@ -0,0 +1,8 @@ +What: /sys/class/power_supply/mp2629_battery/batt_impedance_compen +Date: April 2020 +KernelVersion: 5.7 +Description: + Represents a battery impedance compensation to accelerate charging. + + Access: Read, Write + Valid values: Represented in milli-ohms. Valid range is [0, 140]. diff --git a/Documentation/devicetree/bindings/mfd/mps,mp2629.yaml b/Documentation/devicetree/bindings/mfd/mps,mp2629.yaml new file mode 100644 index 000000000000..f91acc42d652 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/mps,mp2629.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mps,mp2629.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MP2629 Battery Charger PMIC from Monolithic Power System. + +maintainers: + - Saravanan Sekar <sravanhome@gmail.com> + +description: | + MP2629 is a PMIC providing battery charging and power supply for smartphones, + wireless camera and portable devices. Chip is controlled over I2C. + + The battery charge management device handles battery charger controller and + ADC IIO device for battery, system voltage + +properties: + compatible: + const: mps,mp2629 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger type. + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/input/linux-event-codes.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@4b { + compatible = "mps,mp2629"; + reg = <0x4b>; + + interrupt-controller; + interrupt-parent = <&gpio2>; + #interrupt-cells = <2>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt index a9b105ac00a8..2661775a3825 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -18,24 +18,30 @@ See the following for pwarp node definitions: This document describes the binding for MFD device and its sub module. Required properties: -compatible: "mediatek,mt6397" or "mediatek,mt6323" +compatible: + "mediatek,mt6323" for PMIC MT6323 + "mediatek,mt6358" for PMIC MT6358 + "mediatek,mt6397" for PMIC MT6397 Optional subnodes: - rtc Required properties: Should be one of follows - compatible: "mediatek,mt6323-rtc" + - compatible: "mediatek,mt6358-rtc" - compatible: "mediatek,mt6397-rtc" For details, see ../rtc/rtc-mt6397.txt - regulators Required properties: - - compatible: "mediatek,mt6397-regulator" - see ../regulator/mt6397-regulator.txt - compatible: "mediatek,mt6323-regulator" see ../regulator/mt6323-regulator.txt + - compatible: "mediatek,mt6358-regulator" + see ../regulator/mt6358-regulator.txt + - compatible: "mediatek,mt6397-regulator" + see ../regulator/mt6397-regulator.txt - codec Required properties: - - compatible: "mediatek,mt6397-codec" + - compatible: "mediatek,mt6397-codec" or "mediatek,mt6358-sound" - clk Required properties: - compatible: "mediatek,mt6397-clk" @@ -54,6 +60,11 @@ Optional subnodes: - compatible: "mediatek,mt6323-pwrc" For details, see ../power/reset/mt6323-poweroff.txt +- pin-controller + Required properties: + - compatible: "mediatek,mt6397-pinctrl" + For details, see ../pinctrl/pinctrl-mt65xx.txt + Example: pwrap: pwrap@1000f000 { compatible = "mediatek,mt8135-pwrap"; diff --git a/MAINTAINERS b/MAINTAINERS index ddc1dc7e535e..9f7fb09a0140 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11474,10 +11474,15 @@ F: kernel/module.c MONOLITHIC POWER SYSTEM PMIC DRIVER M: Saravanan Sekar <sravanhome@gmail.com> S: Maintained +F: Documentation/devicetree/bindings/mfd/mps,mp2629.yaml F: Documentation/devicetree/bindings/regulator/mps,mp*.yaml +F: drivers/iio/adc/mp2629_adc.c +F: drivers/mfd/mp2629.c +F: drivers/power/supply/mp2629_charger.c F: drivers/regulator/mp5416.c F: drivers/regulator/mpq7920.c F: drivers/regulator/mpq7920.h +F: include/linux/mfd/mp2629.h MOTION EYE VAIO PICTUREBOOK CAMERA DRIVER S: Orphan diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 12bb8b7ca1ff..a864ede98114 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -692,6 +692,16 @@ config MESON_SARADC To compile this driver as a module, choose M here: the module will be called meson_saradc. +config MP2629_ADC + tristate "Monolithic MP2629 ADC driver" + depends on MFD_MP2629 + help + Say yes to have support for battery charger IC MP2629 ADC device + accessed over I2C. + + This driver provides ADC conversion of system, input power supply + and battery voltage & current information. + config NAU7802 tristate "Nuvoton NAU7802 ADC driver" depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 637807861112..78a1963a14f3 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_MCP3911) += mcp3911.o obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o obj-$(CONFIG_MESON_SARADC) += meson_saradc.o +obj-$(CONFIG_MP2629_ADC) += mp2629_adc.o obj-$(CONFIG_MXS_LRADC_ADC) += mxs-lradc-adc.o obj-$(CONFIG_NAU7802) += nau7802.o obj-$(CONFIG_NPCM_ADC) += npcm_adc.o diff --git a/drivers/iio/adc/mp2629_adc.c b/drivers/iio/adc/mp2629_adc.c new file mode 100644 index 000000000000..331a9a728217 --- /dev/null +++ b/drivers/iio/adc/mp2629_adc.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * MP2629 Driver for ADC + * + * Copyright 2020 Monolithic Power Systems, Inc + * + * Author: Saravanan Sekar <sravanhome@gmail.com> + */ + +#include <linux/iio/driver.h> +#include <linux/iio/iio.h> +#include <linux/iio/machine.h> +#include <linux/mfd/mp2629.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define MP2629_REG_ADC_CTRL 0x03 +#define MP2629_REG_BATT_VOLT 0x0e +#define MP2629_REG_SYSTEM_VOLT 0x0f +#define MP2629_REG_INPUT_VOLT 0x11 +#define MP2629_REG_BATT_CURRENT 0x12 +#define MP2629_REG_INPUT_CURRENT 0x13 + +#define MP2629_ADC_START BIT(7) +#define MP2629_ADC_CONTINUOUS BIT(6) + +#define MP2629_MAP(_mp, _mpc) IIO_MAP(#_mp, "mp2629_charger", "mp2629-"_mpc) + +#define MP2629_ADC_CHAN(_ch, _type) { \ + .type = _type, \ + .indexed = 1, \ + .datasheet_name = #_ch, \ + .channel = MP2629_ ## _ch, \ + .address = MP2629_REG_ ## _ch, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ +} + +struct mp2629_adc { + struct regmap *regmap; + struct device *dev; +}; + +static struct iio_chan_spec mp2629_channels[] = { + MP2629_ADC_CHAN(BATT_VOLT, IIO_VOLTAGE), + MP2629_ADC_CHAN(SYSTEM_VOLT, IIO_VOLTAGE), + MP2629_ADC_CHAN(INPUT_VOLT, IIO_VOLTAGE), + MP2629_ADC_CHAN(BATT_CURRENT, IIO_CURRENT), + MP2629_ADC_CHAN(INPUT_CURRENT, IIO_CURRENT) +}; + +static struct iio_map mp2629_adc_maps[] = { + MP2629_MAP(BATT_VOLT, "batt-volt"), + MP2629_MAP(SYSTEM_VOLT, "system-volt"), + MP2629_MAP(INPUT_VOLT, "input-volt"), + MP2629_MAP(BATT_CURRENT, "batt-current"), + MP2629_MAP(INPUT_CURRENT, "input-current") +}; + +static int mp2629_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct mp2629_adc *info = iio_priv(indio_dev); + unsigned int rval; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = regmap_read(info->regmap, chan->address, &rval); + if (ret) + return ret; + + if (chan->address == MP2629_INPUT_VOLT) + rval &= GENMASK(6, 0); + *val = rval; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + switch (chan->channel) { + case MP2629_BATT_VOLT: + case MP2629_SYSTEM_VOLT: + *val = 20; + return IIO_VAL_INT; + + case MP2629_INPUT_VOLT: + *val = 60; + return IIO_VAL_INT; + + case MP2629_BATT_CURRENT: + *val = 175; + *val2 = 10; + return IIO_VAL_FRACTIONAL; + + case MP2629_INPUT_CURRENT: + *val = 133; + *val2 = 10; + return IIO_VAL_FRACTIONAL; + + default: + return -EINVAL; + } + + default: + return -EINVAL; + } +} + +static const struct iio_info mp2629_adc_info = { + .read_raw = &mp2629_read_raw, +}; + +static int mp2629_adc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mp2629_data *ddata = dev_get_drvdata(dev->parent); + struct mp2629_adc *info; + struct iio_dev *indio_dev; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*info)); + if (!indio_dev) + return -ENOMEM; + + info = iio_priv(indio_dev); + info->regmap = ddata->regmap; + info->dev = dev; + platform_set_drvdata(pdev, indio_dev); + + ret = regmap_update_bits(info->regmap, MP2629_REG_ADC_CTRL, + MP2629_ADC_START | MP2629_ADC_CONTINUOUS, + MP2629_ADC_START | MP2629_ADC_CONTINUOUS); + if (ret) { + dev_err(dev, "adc enable fail: %d\n", ret); + return ret; + } + + ret = iio_map_array_register(indio_dev, mp2629_adc_maps); + if (ret) { + dev_err(dev, "IIO maps register fail: %d\n", ret); + goto fail_disable; + } + + indio_dev->name = "mp2629-adc"; + indio_dev->dev.parent = dev; + indio_dev->channels = mp2629_channels; + indio_dev->num_channels = ARRAY_SIZE(mp2629_channels); + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &mp2629_adc_info; + + ret = iio_device_register(indio_dev); + if (ret) { + dev_err(dev, "IIO device register fail: %d\n", ret); + goto fail_map_unregister; + } + + return 0; + +fail_map_unregister: + iio_map_array_unregister(indio_dev); + +fail_disable: + regmap_update_bits(info->regmap, MP2629_REG_ADC_CTRL, + MP2629_ADC_CONTINUOUS, 0); + regmap_update_bits(info->regmap, MP2629_REG_ADC_CTRL, + MP2629_ADC_START, 0); + + return ret; +} + +static int mp2629_adc_remove(struct platform_device *pdev) +{ + struct iio_dev *indio_dev = platform_get_drvdata(pdev); + struct mp2629_adc *info = iio_priv(indio_dev); + + iio_device_unregister(indio_dev); + + iio_map_array_unregister(indio_dev); + + regmap_update_bits(info->regmap, MP2629_REG_ADC_CTRL, + MP2629_ADC_CONTINUOUS, 0); + regmap_update_bits(info->regmap, MP2629_REG_ADC_CTRL, + MP2629_ADC_START, 0); + + return 0; +} + +static const struct of_device_id mp2629_adc_of_match[] = { + { .compatible = "mps,mp2629_adc"}, + {} +}; +MODULE_DEVICE_TABLE(of, mp2629_adc_of_match); + +static struct platform_driver mp2629_adc_driver = { + .driver = { + .name = "mp2629_adc", + .of_match_table = mp2629_adc_of_match, + }, + .probe = mp2629_adc_probe, + .remove = mp2629_adc_remove, +}; +module_platform_driver(mp2629_adc_driver); + +MODULE_AUTHOR("Saravanan Sekar <sravanhome@gmail.com>"); +MODULE_DESCRIPTION("MP2629 ADC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 687e9c848053..2df22de1e8d4 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -449,6 +449,15 @@ config MFD_MC13XXX_I2C help Select this if your MC13xxx is connected via an I2C bus. +config MFD_MP2629 + tristate "Monolithic Power Systems MP2629 ADC and Battery charger" + depends on I2C + select REGMAP_I2C + help + Select this option to enable support for Monolithic Power Systems + battery charger. This provides ADC, thermal and battery charger power + management functions. + config MFD_MXS_LRADC tristate "Freescale i.MX23/i.MX28 LRADC" depends on ARCH_MXS || COMPILE_TEST @@ -899,6 +908,18 @@ config MFD_MAX8998 additional drivers must be enabled in order to use the functionality of the device. +config MFD_MT6360 + tristate "Mediatek MT6360 SubPMIC" + select MFD_CORE + select REGMAP_I2C + select REGMAP_IRQ + depends on I2C + help + Say Y here to enable MT6360 PMU/PMIC/LDO functional support. + PMU part includes Charger, Flashlight, RGB LED + PMIC part includes 2-channel BUCKs and 2-channel LDOs + LDO part includes 4-channel LDOs + config MFD_MT6397 tristate "MediaTek MT6397 PMIC Support" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index bea2be419822..9367a92f795a 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -171,6 +171,8 @@ obj-$(CONFIG_MFD_MAX8925) += max8925.o obj-$(CONFIG_MFD_MAX8997) += max8997.o max8997-irq.o obj-$(CONFIG_MFD_MAX8998) += max8998.o max8998-irq.o +obj-$(CONFIG_MFD_MP2629) += mp2629.o + pcf50633-objs := pcf50633-core.o pcf50633-irq.o obj-$(CONFIG_MFD_PCF50633) += pcf50633.o obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o @@ -241,7 +243,8 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o -mt6397-objs := mt6397-core.o mt6397-irq.o +obj-$(CONFIG_MFD_MT6360) += mt6360-core.o +mt6397-objs := mt6397-core.o mt6397-irq.o mt6358-irq.o obj-$(CONFIG_MFD_MT6397) += mt6397.o obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD) += intel_soc_pmic_mrfld.o diff --git a/drivers/mfd/htc-i2cpld.c b/drivers/mfd/htc-i2cpld.c index 8ad6768bd7a2..247f9849e54a 100644 --- a/drivers/mfd/htc-i2cpld.c +++ b/drivers/mfd/htc-i2cpld.c @@ -355,12 +355,12 @@ static int htcpld_register_chip_i2c( info.platform_data = chip; /* Add the I2C device. This calls the probe() function. */ - client = i2c_new_device(adapter, &info); - if (!client) { + client = i2c_new_client_device(adapter, &info); + if (IS_ERR(client)) { /* I2C device registration failed, contineu with the next */ dev_warn(dev, "Unable to add I2C device for 0x%x\n", plat_chip_data->addr); - return -ENODEV; + return PTR_ERR(client); } i2c_set_clientdata(client, chip); diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c index 7fc0c5d4edff..046222684b8b 100644 --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c @@ -250,9 +250,9 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { { PCI_VDEVICE(INTEL, 0x4da9), (kernel_ulong_t)&spt_uart_info }, { PCI_VDEVICE(INTEL, 0x4daa), (kernel_ulong_t)&spt_info }, { PCI_VDEVICE(INTEL, 0x4dab), (kernel_ulong_t)&spt_info }, - { PCI_VDEVICE(INTEL, 0x4daf), (kernel_ulong_t)&spt_uart_info }, { PCI_VDEVICE(INTEL, 0x4dc5), (kernel_ulong_t)&bxt_i2c_info }, { PCI_VDEVICE(INTEL, 0x4dc6), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x4dc7), (kernel_ulong_t)&spt_uart_info }, { PCI_VDEVICE(INTEL, 0x4de8), (kernel_ulong_t)&bxt_i2c_info }, { PCI_VDEVICE(INTEL, 0x4de9), (kernel_ulong_t)&bxt_i2c_info }, { PCI_VDEVICE(INTEL, 0x4dea), (kernel_ulong_t)&bxt_i2c_info }, diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c index c7ed5c353553..fec2096474ad 100644 --- a/drivers/mfd/max77620.c +++ b/drivers/mfd/max77620.c @@ -177,6 +177,7 @@ static const struct regmap_config max77620_regmap_config = { .rd_table = &max77620_readable_table, .wr_table = &max77620_writable_table, .volatile_table = &max77620_volatile_table, + .use_single_write = true, }; static const struct regmap_config max20024_regmap_config = { diff --git a/drivers/mfd/mp2629.c b/drivers/mfd/mp2629.c new file mode 100644 index 000000000000..16840ec5fd1c --- /dev/null +++ b/drivers/mfd/mp2629.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MP2629 parent driver for ADC and battery charger + * + * Copyright 2020 Monolithic Power Systems, Inc + * + * Author: Saravanan Sekar <sravanhome@gmail.com> + */ + +#include <linux/i2c.h> +#include <linux/kernel.h> +#include <linux/mfd/core.h> +#include <linux/mfd/mp2629.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +static const struct mfd_cell mp2629_cell[] = { + { + .name = "mp2629_adc", + .of_compatible = "mps,mp2629_adc", + }, + { + .name = "mp2629_charger", + .of_compatible = "mps,mp2629_charger", + } +}; + +static const struct regmap_config mp2629_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0x17, +}; + +static int mp2629_probe(struct i2c_client *client) +{ + struct mp2629_data *ddata; + int ret; + + ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->dev = &client->dev; + i2c_set_clientdata(client, ddata); + + ddata->regmap = devm_regmap_init_i2c(client, &mp2629_regmap_config); + if (IS_ERR(ddata->regmap)) { + dev_err(ddata->dev, "Failed to allocate regmap\n"); + return PTR_ERR(ddata->regmap); + } + + ret = devm_mfd_add_devices(ddata->dev, PLATFORM_DEVID_AUTO, mp2629_cell, + ARRAY_SIZE(mp2629_cell), NULL, 0, NULL); + if (ret) + dev_err(ddata->dev, "Failed to register sub-devices %d\n", ret); + + return ret; +} + +static const struct of_device_id mp2629_of_match[] = { + { .compatible = "mps,mp2629"}, + { } +}; +MODULE_DEVICE_TABLE(of, mp2629_of_match); + +static struct i2c_driver mp2629_driver = { + .driver = { + .name = "mp2629", + .of_match_table = mp2629_of_match, + }, + .probe_new = mp2629_probe, +}; +module_i2c_driver(mp2629_driver); + +MODULE_AUTHOR("Saravanan Sekar <sravanhome@gmail.com>"); +MODULE_DESCRIPTION("MP2629 Battery charger parent driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c new file mode 100644 index 000000000000..db734f2831ff --- /dev/null +++ b/drivers/mfd/mt6358-irq.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/interrupt.h> +#include <linux/mfd/mt6358/core.h> +#include <linux/mfd/mt6358/registers.h> +#include <linux/mfd/mt6397/core.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +static struct irq_top_t mt6358_ints[] = { + MT6358_TOP_GEN(BUCK), + MT6358_TOP_GEN(LDO), + MT6358_TOP_GEN(PSC), + MT6358_TOP_GEN(SCK), + MT6358_TOP_GEN(BM), + MT6358_TOP_GEN(HK), + MT6358_TOP_GEN(AUD), + MT6358_TOP_GEN(MISC), +}; + +static void pmic_irq_enable(struct irq_data *data) +{ + unsigned int hwirq = irqd_to_hwirq(data); + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); + struct pmic_irq_data *irqd = chip->irq_data; + + irqd->enable_hwirq[hwirq] = true; +} + +static void pmic_irq_disable(struct irq_data *data) +{ + unsigned int hwirq = irqd_to_hwirq(data); + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); + struct pmic_irq_data *irqd = chip->irq_data; + + irqd->enable_hwirq[hwirq] = false; +} + +static void pmic_irq_lock(struct irq_data *data) +{ + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); + + mutex_lock(&chip->irqlock); +} + +static void pmic_irq_sync_unlock(struct irq_data *data) +{ + unsigned int i, top_gp, gp_offset, en_reg, int_regs, shift; + struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); + struct pmic_irq_data *irqd = chip->irq_data; + + for (i = 0; i < irqd->num_pmic_irqs; i++) { + if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i]) + continue; + + /* Find out the IRQ group */ + top_gp = 0; + while ((top_gp + 1) < irqd->num_top && + i >= mt6358_ints[top_gp + 1].hwirq_base) + top_gp++; + + /* Find the IRQ registers */ + gp_offset = i - mt6358_ints[top_gp].hwirq_base; + int_regs = gp_offset / MT6358_REG_WIDTH; + shift = gp_offset % MT6358_REG_WIDTH; + en_reg = mt6358_ints[top_gp].en_reg + + (mt6358_ints[top_gp].en_reg_shift * int_regs); + + regmap_update_bits(chip->regmap, en_reg, BIT(shift), + irqd->enable_hwirq[i] << shift); + + irqd->cache_hwirq[i] = irqd->enable_hwirq[i]; + } + mutex_unlock(&chip->irqlock); +} + +static struct irq_chip mt6358_irq_chip = { + .name = "mt6358-irq", + .flags = IRQCHIP_SKIP_SET_WAKE, + .irq_enable = pmic_irq_enable, + .irq_disable = pmic_irq_disable, + .irq_bus_lock = pmic_irq_lock, + .irq_bus_sync_unlock = pmic_irq_sync_unlock, +}; + +static void mt6358_irq_sp_handler(struct mt6397_chip *chip, + unsigned int top_gp) +{ + unsigned int irq_status, sta_reg, status; + unsigned int hwirq, virq; + int i, j, ret; + + for (i = 0; i < mt6358_ints[top_gp].num_int_regs; i++) { + sta_reg = mt6358_ints[top_gp].sta_reg + + mt6358_ints[top_gp].sta_reg_shift * i; + + ret = regmap_read(chip->regmap, sta_reg, &irq_status); + if (ret) { + dev_err(chip->dev, + "Failed to read IRQ status, ret=%d\n", ret); + return; + } + + if (!irq_status) + continue; + + status = irq_status; + do { + j = __ffs(status); + + hwirq = mt6358_ints[top_gp].hwirq_base + + MT6358_REG_WIDTH * i + j; + + virq = irq_find_mapping(chip->irq_domain, hwirq); + if (virq) + handle_nested_irq(virq); + + status &= ~BIT(j); + } while (status); + + regmap_write(chip->regmap, sta_reg, irq_status); + } +} + +static irqreturn_t mt6358_irq_handler(int irq, void *data) +{ + struct mt6397_chip *chip = data; + struct pmic_irq_data *mt6358_irq_data = chip->irq_data; + unsigned int bit, i, top_irq_status = 0; + int ret; + + ret = regmap_read(chip->regmap, + mt6358_irq_data->top_int_status_reg, + &top_irq_status); + if (ret) { + dev_err(chip->dev, + "Failed to read status from the device, ret=%d\n", ret); + return IRQ_NONE; + } + + for (i = 0; i < mt6358_irq_data->num_top; i++) { + bit = BIT(mt6358_ints[i].top_offset); + if (top_irq_status & bit) { + mt6358_irq_sp_handler(chip, i); + top_irq_status &= ~bit; + if (!top_irq_status) + break; + } + } + + return IRQ_HANDLED; +} + +static int pmic_irq_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) +{ + struct mt6397_chip *mt6397 = d->host_data; + + irq_set_chip_data(irq, mt6397); + irq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq); + irq_set_nested_thread(irq, 1); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops mt6358_irq_domain_ops = { + .map = pmic_irq_domain_map, + .xlate = irq_domain_xlate_twocell, +}; + +int mt6358_irq_init(struct mt6397_chip *chip) +{ + int i, j, ret; + struct pmic_irq_data *irqd; + + irqd = devm_kzalloc(chip->dev, sizeof(*irqd), GFP_KERNEL); + if (!irqd) + return -ENOMEM; + + chip->irq_data = irqd; + + mutex_init(&chip->irqlock); + irqd->top_int_status_reg = MT6358_TOP_INT_STATUS0; + irqd->num_pmic_irqs = MT6358_IRQ_NR; + irqd->num_top = ARRAY_SIZE(mt6358_ints); + + irqd->enable_hwirq = devm_kcalloc(chip->dev, + irqd->num_pmic_irqs, + sizeof(*irqd->enable_hwirq), + GFP_KERNEL); + if (!irqd->enable_hwirq) + return -ENOMEM; + + irqd->cache_hwirq = devm_kcalloc(chip->dev, + irqd->num_pmic_irqs, + sizeof(*irqd->cache_hwirq), + GFP_KERNEL); + if (!irqd->cache_hwirq) + return -ENOMEM; + + /* Disable all interrupts for initializing */ + for (i = 0; i < irqd->num_top; i++) { + for (j = 0; j < mt6358_ints[i].num_int_regs; j++) + regmap_write(chip->regmap, + mt6358_ints[i].en_reg + + mt6358_ints[i].en_reg_shift * j, 0); + } + + chip->irq_domain = irq_domain_add_linear(chip->dev->of_node, + irqd->num_pmic_irqs, + &mt6358_irq_domain_ops, chip); + if (!chip->irq_domain) { + dev_err(chip->dev, "Could not create IRQ domain\n"); + return -ENODEV; + } + + ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL, + mt6358_irq_handler, IRQF_ONESHOT, + mt6358_irq_chip.name, chip); + if (ret) { + dev_err(chip->dev, "Failed to register IRQ=%d, ret=%d\n", + chip->irq, ret); + return ret; + } + + enable_irq_wake(chip->irq); + return ret; +} diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c new file mode 100644 index 000000000000..db8cdf5272c1 --- /dev/null +++ b/drivers/mfd/mt6360-core.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + * + * Author: Gene Chen <gene_chen@richtek.com> + */ + +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/mfd/core.h> +#include <linux/module.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/version.h> + +#include <linux/mfd/mt6360.h> + +/* reg 0 -> 0 ~ 7 */ +#define MT6360_CHG_TREG_EVT (4) +#define MT6360_CHG_AICR_EVT (5) +#define MT6360_CHG_MIVR_EVT (6) +#define MT6360_PWR_RDY_EVT (7) +/* REG 1 -> 8 ~ 15 */ +#define MT6360_CHG_BATSYSUV_EVT (9) +#define MT6360_FLED_CHG_VINOVP_EVT (11) +#define MT6360_CHG_VSYSUV_EVT (12) +#define MT6360_CHG_VSYSOV_EVT (13) +#define MT6360_CHG_VBATOV_EVT (14) +#define MT6360_CHG_VBUSOV_EVT (15) +/* REG 2 -> 16 ~ 23 */ +/* REG 3 -> 24 ~ 31 */ +#define MT6360_WD_PMU_DET (25) +#define MT6360_WD_PMU_DONE (26) +#define MT6360_CHG_TMRI (27) +#define MT6360_CHG_ADPBADI (29) +#define MT6360_CHG_RVPI (30) +#define MT6360_OTPI (31) +/* REG 4 -> 32 ~ 39 */ +#define MT6360_CHG_AICCMEASL (32) +#define MT6360_CHGDET_DONEI (34) +#define MT6360_WDTMRI (35) +#define MT6360_SSFINISHI (36) +#define MT6360_CHG_RECHGI (37) +#define MT6360_CHG_TERMI (38) +#define MT6360_CHG_IEOCI (39) +/* REG 5 -> 40 ~ 47 */ +#define MT6360_PUMPX_DONEI (40) +#define MT6360_BAT_OVP_ADC_EVT (41) +#define MT6360_TYPEC_OTP_EVT (42) +#define MT6360_ADC_WAKEUP_EVT (43) +#define MT6360_ADC_DONEI (44) +#define MT6360_BST_BATUVI (45) +#define MT6360_BST_VBUSOVI (46) +#define MT6360_BST_OLPI (47) +/* REG 6 -> 48 ~ 55 */ +#define MT6360_ATTACH_I (48) +#define MT6360_DETACH_I (49) +#define MT6360_QC30_STPDONE (51) +#define MT6360_QC_VBUSDET_DONE (52) +#define MT6360_HVDCP_DET (53) +#define MT6360_CHGDETI (54) +#define MT6360_DCDTI (55) +/* REG 7 -> 56 ~ 63 */ +#define MT6360_FOD_DONE_EVT (56) +#define MT6360_FOD_OV_EVT (57) +#define MT6360_CHRDET_UVP_EVT (58) +#define MT6360_CHRDET_OVP_EVT (59) +#define MT6360_CHRDET_EXT_EVT (60) +#define MT6360_FOD_LR_EVT (61) +#define MT6360_FOD_HR_EVT (62) +#define MT6360_FOD_DISCHG_FAIL_EVT (63) +/* REG 8 -> 64 ~ 71 */ +#define MT6360_USBID_EVT (64) +#define MT6360_APWDTRST_EVT (65) +#define MT6360_EN_EVT (66) +#define MT6360_QONB_RST_EVT (67) +#define MT6360_MRSTB_EVT (68) +#define MT6360_OTP_EVT (69) +#define MT6360_VDDAOV_EVT (70) +#define MT6360_SYSUV_EVT (71) +/* REG 9 -> 72 ~ 79 */ +#define MT6360_FLED_STRBPIN_EVT (72) +#define MT6360_FLED_TORPIN_EVT (73) +#define MT6360_FLED_TX_EVT (74) +#define MT6360_FLED_LVF_EVT (75) +#define MT6360_FLED2_SHORT_EVT (78) +#define MT6360_FLED1_SHORT_EVT (79) +/* REG 10 -> 80 ~ 87 */ +#define MT6360_FLED2_STRB_EVT (80) +#define MT6360_FLED1_STRB_EVT (81) +#define MT6360_FLED2_STRB_TO_EVT (82) +#define MT6360_FLED1_STRB_TO_EVT (83) +#define MT6360_FLED2_TOR_EVT (84) +#define MT6360_FLED1_TOR_EVT (85) +/* REG 11 -> 88 ~ 95 */ +/* REG 12 -> 96 ~ 103 */ +#define MT6360_BUCK1_PGB_EVT (96) +#define MT6360_BUCK1_OC_EVT (100) +#define MT6360_BUCK1_OV_EVT (101) +#define MT6360_BUCK1_UV_EVT (102) +/* REG 13 -> 104 ~ 111 */ +#define MT6360_BUCK2_PGB_EVT (104) +#define MT6360_BUCK2_OC_EVT (108) +#define MT6360_BUCK2_OV_EVT (109) +#define MT6360_BUCK2_UV_EVT (110) +/* REG 14 -> 112 ~ 119 */ +#define MT6360_LDO1_OC_EVT (113) +#define MT6360_LDO2_OC_EVT (114) +#define MT6360_LDO3_OC_EVT (115) +#define MT6360_LDO5_OC_EVT (117) +#define MT6360_LDO6_OC_EVT (118) +#define MT6360_LDO7_OC_EVT (119) +/* REG 15 -> 120 ~ 127 */ +#define MT6360_LDO1_PGB_EVT (121) +#define MT6360_LDO2_PGB_EVT (122) +#define MT6360_LDO3_PGB_EVT (123) +#define MT6360_LDO5_PGB_EVT (125) +#define MT6360_LDO6_PGB_EVT (126) +#define MT6360_LDO7_PGB_EVT (127) + +static const struct regmap_irq mt6360_pmu_irqs[] = { + REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_AICR_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_MIVR_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_PWR_RDY_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_BATSYSUV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED_CHG_VINOVP_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSUV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSOV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_VBATOV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_VBUSOV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DET, 8), + REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DONE, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_TMRI, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_ADPBADI, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_RVPI, 8), + REGMAP_IRQ_REG_LINE(MT6360_OTPI, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_AICCMEASL, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHGDET_DONEI, 8), + REGMAP_IRQ_REG_LINE(MT6360_WDTMRI, 8), + REGMAP_IRQ_REG_LINE(MT6360_SSFINISHI, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_RECHGI, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_TERMI, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHG_IEOCI, 8), + REGMAP_IRQ_REG_LINE(MT6360_PUMPX_DONEI, 8), + REGMAP_IRQ_REG_LINE(MT6360_BAT_OVP_ADC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_TYPEC_OTP_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_ADC_WAKEUP_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_ADC_DONEI, 8), + REGMAP_IRQ_REG_LINE(MT6360_BST_BATUVI, 8), + REGMAP_IRQ_REG_LINE(MT6360_BST_VBUSOVI, 8), + REGMAP_IRQ_REG_LINE(MT6360_BST_OLPI, 8), + REGMAP_IRQ_REG_LINE(MT6360_ATTACH_I, 8), + REGMAP_IRQ_REG_LINE(MT6360_DETACH_I, 8), + REGMAP_IRQ_REG_LINE(MT6360_QC30_STPDONE, 8), + REGMAP_IRQ_REG_LINE(MT6360_QC_VBUSDET_DONE, 8), + REGMAP_IRQ_REG_LINE(MT6360_HVDCP_DET, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHGDETI, 8), + REGMAP_IRQ_REG_LINE(MT6360_DCDTI, 8), + REGMAP_IRQ_REG_LINE(MT6360_FOD_DONE_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FOD_OV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHRDET_UVP_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHRDET_OVP_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_CHRDET_EXT_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FOD_LR_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FOD_HR_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FOD_DISCHG_FAIL_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_USBID_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_APWDTRST_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_EN_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_QONB_RST_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_MRSTB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_OTP_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_VDDAOV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_SYSUV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED_STRBPIN_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED_TORPIN_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED_TX_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED_LVF_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED2_SHORT_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED1_SHORT_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_TO_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_TO_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED2_TOR_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_FLED1_TOR_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_BUCK1_PGB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_BUCK1_UV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_BUCK2_PGB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_BUCK2_UV_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO1_OC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO2_OC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO3_OC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO5_OC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO6_OC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO7_OC_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO1_PGB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO2_PGB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO3_PGB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO5_PGB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO6_PGB_EVT, 8), + REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8), +}; + +static int mt6360_pmu_handle_post_irq(void *irq_drv_data) +{ + struct mt6360_pmu_data *mpd = irq_drv_data; + + return regmap_update_bits(mpd->regmap, + MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, MT6360_IRQ_RETRIG); +} + +static struct regmap_irq_chip mt6360_pmu_irq_chip = { + .irqs = mt6360_pmu_irqs, + .num_irqs = ARRAY_SIZE(mt6360_pmu_irqs), + .num_regs = MT6360_PMU_IRQ_REGNUM, + .mask_base = MT6360_PMU_CHG_MASK1, + .status_base = MT6360_PMU_CHG_IRQ1, + .ack_base = MT6360_PMU_CHG_IRQ1, + .init_ack_masked = true, + .use_ack = true, + .handle_post_irq = mt6360_pmu_handle_post_irq, +}; + +static const struct regmap_config mt6360_pmu_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = MT6360_PMU_MAXREG, +}; + +static const struct resource mt6360_adc_resources[] = { + DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"), +}; + +static const struct resource mt6360_chg_resources[] = { + DEFINE_RES_IRQ_NAMED(MT6360_CHG_TREG_EVT, "chg_treg_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_PWR_RDY_EVT, "pwr_rdy_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_BATSYSUV_EVT, "chg_batsysuv_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSUV_EVT, "chg_vsysuv_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSOV_EVT, "chg_vsysov_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBATOV_EVT, "chg_vbatov_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBUSOV_EVT, "chg_vbusov_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_AICCMEASL, "chg_aiccmeasl"), + DEFINE_RES_IRQ_NAMED(MT6360_WDTMRI, "wdtmri"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_RECHGI, "chg_rechgi"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_TERMI, "chg_termi"), + DEFINE_RES_IRQ_NAMED(MT6360_CHG_IEOCI, "chg_ieoci"), + DEFINE_RES_IRQ_NAMED(MT6360_PUMPX_DONEI, "pumpx_donei"), + DEFINE_RES_IRQ_NAMED(MT6360_ATTACH_I, "attach_i"), + DEFINE_RES_IRQ_NAMED(MT6360_CHRDET_EXT_EVT, "chrdet_ext_evt"), +}; + +static const struct resource mt6360_led_resources[] = { + DEFINE_RES_IRQ_NAMED(MT6360_FLED_CHG_VINOVP_EVT, "fled_chg_vinovp_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_FLED_LVF_EVT, "fled_lvf_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_FLED2_SHORT_EVT, "fled2_short_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_FLED1_SHORT_EVT, "fled1_short_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_FLED2_STRB_TO_EVT, "fled2_strb_to_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"), +}; + +static const struct resource mt6360_pmic_resources[] = { + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_UV_EVT, "buck1_uv_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_PGB_EVT, "buck2_pgb_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), +}; + +static const struct resource mt6360_ldo_resources[] = { + DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"), +}; + +static const struct mfd_cell mt6360_devs[] = { + OF_MFD_CELL("mt6360_adc", mt6360_adc_resources, + NULL, 0, 0, "mediatek,mt6360_adc"), + OF_MFD_CELL("mt6360_chg", mt6360_chg_resources, + NULL, 0, 0, "mediatek,mt6360_chg"), + OF_MFD_CELL("mt6360_led", mt6360_led_resources, + NULL, 0, 0, "mediatek,mt6360_led"), + OF_MFD_CELL("mt6360_pmic", mt6360_pmic_resources, + NULL, 0, 0, "mediatek,mt6360_pmic"), + OF_MFD_CELL("mt6360_ldo", mt6360_ldo_resources, + NULL, 0, 0, "mediatek,mt6360_ldo"), + OF_MFD_CELL("mt6360_tcpc", NULL, + NULL, 0, 0, "mediatek,mt6360_tcpc"), +}; + +static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { + MT6360_PMU_SLAVEID, + MT6360_PMIC_SLAVEID, + MT6360_LDO_SLAVEID, + MT6360_TCPC_SLAVEID, +}; + +static int mt6360_pmu_probe(struct i2c_client *client) +{ + struct mt6360_pmu_data *mpd; + unsigned int reg_data; + int i, ret; + + mpd = devm_kzalloc(&client->dev, sizeof(*mpd), GFP_KERNEL); + if (!mpd) + return -ENOMEM; + + mpd->dev = &client->dev; + i2c_set_clientdata(client, mpd); + + mpd->regmap = devm_regmap_init_i2c(client, &mt6360_pmu_regmap_config); + if (IS_ERR(mpd->regmap)) { + dev_err(&client->dev, "Failed to register regmap\n"); + return PTR_ERR(mpd->regmap); + } + + ret = regmap_read(mpd->regmap, MT6360_PMU_DEV_INFO, ®_data); + if (ret) { + dev_err(&client->dev, "Device not found\n"); + return ret; + } + + mpd->chip_rev = reg_data & CHIP_REV_MASK; + if (mpd->chip_rev != CHIP_VEN_MT6360) { + dev_err(&client->dev, "Device not supported\n"); + return -ENODEV; + } + + mt6360_pmu_irq_chip.irq_drv_data = mpd; + ret = devm_regmap_add_irq_chip(&client->dev, mpd->regmap, client->irq, + IRQF_TRIGGER_FALLING, 0, + &mt6360_pmu_irq_chip, &mpd->irq_data); + if (ret) { + dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); + return ret; + } + + mpd->i2c[0] = client; + for (i = 1; i < MT6360_SLAVE_MAX; i++) { + mpd->i2c[i] = devm_i2c_new_dummy_device(&client->dev, + client->adapter, + mt6360_slave_addr[i]); + if (IS_ERR(mpd->i2c[i])) { + dev_err(&client->dev, + "Failed to get new dummy I2C device for address 0x%x", + mt6360_slave_addr[i]); + return PTR_ERR(mpd->i2c[i]); + } + i2c_set_clientdata(mpd->i2c[i], mpd); + } + + ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, + mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL, + 0, regmap_irq_get_domain(mpd->irq_data)); + if (ret) { + dev_err(&client->dev, + "Failed to register subordinate devices\n"); + return ret; + } + + return 0; +} + +static int __maybe_unused mt6360_pmu_suspend(struct device *dev) +{ + struct i2c_client *i2c = to_i2c_client(dev); + + if (device_may_wakeup(dev)) + enable_irq_wake(i2c->irq); + + return 0; +} + +static int __maybe_unused mt6360_pmu_resume(struct device *dev) +{ + + struct i2c_client *i2c = to_i2c_client(dev); + + if (device_may_wakeup(dev)) + disable_irq_wake(i2c->irq); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(mt6360_pmu_pm_ops, + mt6360_pmu_suspend, mt6360_pmu_resume); + +static const struct of_device_id __maybe_unused mt6360_pmu_of_id[] = { + { .compatible = "mediatek,mt6360_pmu", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mt6360_pmu_of_id); + +static struct i2c_driver mt6360_pmu_driver = { + .driver = { + .pm = &mt6360_pmu_pm_ops, + .of_match_table = of_match_ptr(mt6360_pmu_of_id), + }, + .probe_new = mt6360_pmu_probe, +}; +module_i2c_driver(mt6360_pmu_driver); + +MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>"); +MODULE_DESCRIPTION("MT6360 PMU I2C Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c index 0437c858d115..f6cd8a660602 100644 --- a/drivers/mfd/mt6397-core.c +++ b/drivers/mfd/mt6397-core.c @@ -12,13 +12,18 @@ #include <linux/regmap.h> #include <linux/mfd/core.h> #include <linux/mfd/mt6323/core.h> +#include <linux/mfd/mt6358/core.h> #include <linux/mfd/mt6397/core.h> #include <linux/mfd/mt6323/registers.h> +#include <linux/mfd/mt6358/registers.h> #include <linux/mfd/mt6397/registers.h> #define MT6323_RTC_BASE 0x8000 #define MT6323_RTC_SIZE 0x40 +#define MT6358_RTC_BASE 0x0588 +#define MT6358_RTC_SIZE 0x3c + #define MT6397_RTC_BASE 0xe000 #define MT6397_RTC_SIZE 0x3e @@ -30,6 +35,11 @@ static const struct resource mt6323_rtc_resources[] = { DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC), }; +static const struct resource mt6358_rtc_resources[] = { + DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE), + DEFINE_RES_IRQ(MT6358_IRQ_RTC), +}; + static const struct resource mt6397_rtc_resources[] = { DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE), DEFINE_RES_IRQ(MT6397_IRQ_RTC), @@ -74,6 +84,21 @@ static const struct mfd_cell mt6323_devs[] = { }, }; +static const struct mfd_cell mt6358_devs[] = { + { + .name = "mt6358-regulator", + .of_compatible = "mediatek,mt6358-regulator" + }, { + .name = "mt6358-rtc", + .num_resources = ARRAY_SIZE(mt6358_rtc_resources), + .resources = mt6358_rtc_resources, + .of_compatible = "mediatek,mt6358-rtc", + }, { + .name = "mt6358-sound", + .of_compatible = "mediatek,mt6358-sound" + }, +}; + static const struct mfd_cell mt6397_devs[] = { { .name = "mt6397-rtc", @@ -100,54 +125,42 @@ static const struct mfd_cell mt6397_devs[] = { } }; -#ifdef CONFIG_PM_SLEEP -static int mt6397_irq_suspend(struct device *dev) -{ - struct mt6397_chip *chip = dev_get_drvdata(dev); - - regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]); - regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]); - - enable_irq_wake(chip->irq); - - return 0; -} - -static int mt6397_irq_resume(struct device *dev) -{ - struct mt6397_chip *chip = dev_get_drvdata(dev); - - regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]); - regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]); - - disable_irq_wake(chip->irq); - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend, - mt6397_irq_resume); - struct chip_data { u32 cid_addr; u32 cid_shift; + const struct mfd_cell *cells; + int cell_size; + int (*irq_init)(struct mt6397_chip *chip); }; static const struct chip_data mt6323_core = { .cid_addr = MT6323_CID, .cid_shift = 0, + .cells = mt6323_devs, + .cell_size = ARRAY_SIZE(mt6323_devs), + .irq_init = mt6397_irq_init, +}; + +static const struct chip_data mt6358_core = { + .cid_addr = MT6358_SWCID, + .cid_shift = 8, + .cells = mt6358_devs, + .cell_size = ARRAY_SIZE(mt6358_devs), + .irq_init = mt6358_irq_init, }; static const struct chip_data mt6397_core = { .cid_addr = MT6397_CID, .cid_shift = 0, + .cells = mt6397_devs, + .cell_size = ARRAY_SIZE(mt6397_devs), + .irq_init = mt6397_irq_init, }; static int mt6397_probe(struct platform_device *pdev) { int ret; - unsigned int id; + unsigned int id = 0; struct mt6397_chip *pmic; const struct chip_data *pmic_core; @@ -183,29 +196,13 @@ static int mt6397_probe(struct platform_device *pdev) if (pmic->irq <= 0) return pmic->irq; - ret = mt6397_irq_init(pmic); + ret = pmic_core->irq_init(pmic); if (ret) return ret; - switch (pmic->chip_id) { - case MT6323_CHIP_ID: - ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, - mt6323_devs, ARRAY_SIZE(mt6323_devs), - NULL, 0, pmic->irq_domain); - break; - - case MT6391_CHIP_ID: - case MT6397_CHIP_ID: - ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, - mt6397_devs, ARRAY_SIZE(mt6397_devs), - NULL, 0, pmic->irq_domain); - break; - - default: - dev_err(&pdev->dev, "unsupported chip: %d\n", pmic->chip_id); - return -ENODEV; - } - + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, + pmic_core->cells, pmic_core->cell_size, + NULL, 0, pmic->irq_domain); if (ret) { irq_domain_remove(pmic->irq_domain); dev_err(&pdev->dev, "failed to add child devices: %d\n", ret); @@ -219,6 +216,9 @@ static const struct of_device_id mt6397_of_match[] = { .compatible = "mediatek,mt6323", .data = &mt6323_core, }, { + .compatible = "mediatek,mt6358", + .data = &mt6358_core, + }, { .compatible = "mediatek,mt6397", .data = &mt6397_core, }, { @@ -238,7 +238,6 @@ static struct platform_driver mt6397_driver = { .driver = { .name = "mt6397", .of_match_table = of_match_ptr(mt6397_of_match), - .pm = &mt6397_pm_ops, }, .id_table = mt6397_id, }; diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c index b2d3ce1f3115..2924919da991 100644 --- a/drivers/mfd/mt6397-irq.c +++ b/drivers/mfd/mt6397-irq.c @@ -9,6 +9,7 @@ #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/suspend.h> #include <linux/mfd/mt6323/core.h> #include <linux/mfd/mt6323/registers.h> #include <linux/mfd/mt6397/core.h> @@ -81,7 +82,7 @@ static struct irq_chip mt6397_irq_chip = { static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg, int irqbase) { - unsigned int status; + unsigned int status = 0; int i, irq, ret; ret = regmap_read(mt6397->regmap, reg, &status); @@ -128,6 +129,36 @@ static const struct irq_domain_ops mt6397_irq_domain_ops = { .map = mt6397_irq_domain_map, }; +static int mt6397_irq_pm_notifier(struct notifier_block *notifier, + unsigned long pm_event, void *unused) +{ + struct mt6397_chip *chip = + container_of(notifier, struct mt6397_chip, pm_nb); + + switch (pm_event) { + case PM_SUSPEND_PREPARE: + regmap_write(chip->regmap, + chip->int_con[0], chip->wake_mask[0]); + regmap_write(chip->regmap, + chip->int_con[1], chip->wake_mask[1]); + enable_irq_wake(chip->irq); + break; + + case PM_POST_SUSPEND: + regmap_write(chip->regmap, + chip->int_con[0], chip->irq_masks_cur[0]); + regmap_write(chip->regmap, + chip->int_con[1], chip->irq_masks_cur[1]); + disable_irq_wake(chip->irq); + break; + + default: + break; + } + + return NOTIFY_DONE; +} + int mt6397_irq_init(struct mt6397_chip *chip) { int ret; @@ -159,6 +190,7 @@ int mt6397_irq_init(struct mt6397_chip *chip) regmap_write(chip->regmap, chip->int_con[0], 0x0); regmap_write(chip->regmap, chip->int_con[1], 0x0); + chip->pm_nb.notifier_call = mt6397_irq_pm_notifier; chip->irq_domain = irq_domain_add_linear(chip->dev->of_node, MT6397_IRQ_NR, &mt6397_irq_domain_ops, @@ -177,5 +209,6 @@ int mt6397_irq_init(struct mt6397_chip *chip) return ret; } + register_pm_notifier(&chip->pm_nb); return 0; } diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c index ebdf2f11ae28..33336cde4724 100644 --- a/drivers/mfd/sprd-sc27xx-spi.c +++ b/drivers/mfd/sprd-sc27xx-spi.c @@ -284,7 +284,6 @@ MODULE_DEVICE_TABLE(of, sprd_pmic_match); static struct spi_driver sprd_pmic_driver = { .driver = { .name = "sc27xx-pmic", - .bus = &spi_bus_type, .of_match_table = sprd_pmic_match, }, .probe = sprd_pmic_probe, diff --git a/drivers/mfd/stm32-timers.c b/drivers/mfd/stm32-timers.c index efcd4b980c94..add603359124 100644 --- a/drivers/mfd/stm32-timers.c +++ b/drivers/mfd/stm32-timers.c @@ -167,10 +167,11 @@ static void stm32_timers_get_arr_size(struct stm32_timers *ddata) regmap_write(ddata->regmap, TIM_ARR, 0x0); } -static void stm32_timers_dma_probe(struct device *dev, +static int stm32_timers_dma_probe(struct device *dev, struct stm32_timers *ddata) { int i; + int ret = 0; char name[4]; init_completion(&ddata->dma.completion); @@ -179,14 +180,23 @@ static void stm32_timers_dma_probe(struct device *dev, /* Optional DMA support: get valid DMA channel(s) or NULL */ for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) { snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1); - ddata->dma.chans[i] = dma_request_slave_channel(dev, name); + ddata->dma.chans[i] = dma_request_chan(dev, name); } - ddata->dma.chans[STM32_TIMERS_DMA_UP] = - dma_request_slave_channel(dev, "up"); - ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = - dma_request_slave_channel(dev, "trig"); - ddata->dma.chans[STM32_TIMERS_DMA_COM] = - dma_request_slave_channel(dev, "com"); + ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up"); + ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig"); + ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com"); + + for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) { + if (IS_ERR(ddata->dma.chans[i])) { + /* Save the first error code to return */ + if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret) + ret = PTR_ERR(ddata->dma.chans[i]); + + ddata->dma.chans[i] = NULL; + } + } + + return ret; } static void stm32_timers_dma_remove(struct device *dev, @@ -230,7 +240,11 @@ static int stm32_timers_probe(struct platform_device *pdev) stm32_timers_get_arr_size(ddata); - stm32_timers_dma_probe(dev, ddata); + ret = stm32_timers_dma_probe(dev, ddata); + if (ret) { + stm32_timers_dma_remove(dev, ddata); + return ret; + } platform_set_drvdata(pdev, ddata); diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c index 857991cb3cbb..711979afd90a 100644 --- a/drivers/mfd/stmfx.c +++ b/drivers/mfd/stmfx.c @@ -287,14 +287,21 @@ static int stmfx_irq_init(struct i2c_client *client) ret = regmap_write(stmfx->map, STMFX_REG_IRQ_OUT_PIN, irqoutpin); if (ret) - return ret; + goto irq_exit; ret = devm_request_threaded_irq(stmfx->dev, client->irq, NULL, stmfx_irq_handler, irqtrigger | IRQF_ONESHOT, "stmfx", stmfx); if (ret) - stmfx_irq_exit(client); + goto irq_exit; + + stmfx->irq = client->irq; + + return 0; + +irq_exit: + stmfx_irq_exit(client); return ret; } @@ -481,6 +488,8 @@ static int stmfx_suspend(struct device *dev) if (ret) return ret; + disable_irq(stmfx->irq); + if (stmfx->vdd) return regulator_disable(stmfx->vdd); @@ -501,6 +510,13 @@ static int stmfx_resume(struct device *dev) } } + /* Reset STMFX - supply has been stopped during suspend */ + ret = stmfx_chip_reset(stmfx); + if (ret) { + dev_err(stmfx->dev, "Failed to reset chip: %d\n", ret); + return ret; + } + ret = regmap_raw_write(stmfx->map, STMFX_REG_SYS_CTRL, &stmfx->bkp_sysctrl, sizeof(stmfx->bkp_sysctrl)); if (ret) @@ -517,6 +533,8 @@ static int stmfx_resume(struct device *dev) if (ret) return ret; + enable_irq(stmfx->irq); + return 0; } #endif diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c index 7dfbe8906cb8..eb3da558c3fb 100644 --- a/drivers/mfd/stpmic1.c +++ b/drivers/mfd/stpmic1.c @@ -59,7 +59,7 @@ static const struct regmap_access_table stpmic1_volatile_table = { .n_yes_ranges = ARRAY_SIZE(stpmic1_volatile_ranges), }; -const struct regmap_config stpmic1_regmap_config = { +static const struct regmap_config stpmic1_regmap_config = { .reg_bits = 8, .val_bits = 8, .cache_type = REGCACHE_RBTREE, diff --git a/drivers/mfd/tqmx86.c b/drivers/mfd/tqmx86.c index b9f48e588d95..ddddf08b6a4c 100644 --- a/drivers/mfd/tqmx86.c +++ b/drivers/mfd/tqmx86.c @@ -274,7 +274,7 @@ static int __init tqmx86_init(void) module_init(tqmx86_init); -MODULE_DESCRIPTION("TQx86 PLD Core Driver"); +MODULE_DESCRIPTION("TQMx86 PLD Core Driver"); MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:tqmx86"); diff --git a/drivers/mfd/wcd934x.c b/drivers/mfd/wcd934x.c index 90341f3c6810..da910302d51a 100644 --- a/drivers/mfd/wcd934x.c +++ b/drivers/mfd/wcd934x.c @@ -280,7 +280,6 @@ static void wcd934x_slim_remove(struct slim_device *sdev) regulator_bulk_disable(WCD934X_MAX_SUPPLY, ddata->supplies); mfd_remove_devices(&sdev->dev); - kfree(ddata); } static const struct slim_device_id wcd934x_slim_id[] = { diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c index 1e9fe7d92597..3b2b93c5bbcb 100644 --- a/drivers/mfd/wm8994-core.c +++ b/drivers/mfd/wm8994-core.c @@ -393,7 +393,9 @@ static int wm8994_device_init(struct wm8994 *wm8994, int irq) ret = regulator_bulk_get(wm8994->dev, wm8994->num_supplies, wm8994->supplies); if (ret != 0) { - dev_err(wm8994->dev, "Failed to get supplies: %d\n", ret); + if (ret != -EPROBE_DEFER) + dev_err(wm8994->dev, "Failed to get supplies: %d\n", + ret); goto err; } @@ -584,6 +586,7 @@ static int wm8994_device_init(struct wm8994 *wm8994, int irq) goto err_irq; } + pm_runtime_set_active(wm8994->dev); pm_runtime_enable(wm8994->dev); pm_runtime_idle(wm8994->dev); @@ -603,7 +606,9 @@ err: static void wm8994_device_exit(struct wm8994 *wm8994) { + pm_runtime_get_sync(wm8994->dev); pm_runtime_disable(wm8994->dev); + pm_runtime_put_noidle(wm8994->dev); wm8994_irq_exit(wm8994); regulator_bulk_disable(wm8994->num_supplies, wm8994->supplies); regulator_bulk_free(wm8994->num_supplies, wm8994->supplies); @@ -690,3 +695,4 @@ module_i2c_driver(wm8994_i2c_driver); MODULE_DESCRIPTION("Core support for the WM8994 audio CODEC"); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); +MODULE_SOFTDEP("pre: wm8994_regulator"); diff --git a/drivers/power/reset/mt6323-poweroff.c b/drivers/power/reset/mt6323-poweroff.c index 1caf43d9e46d..0532803e6cbc 100644 --- a/drivers/power/reset/mt6323-poweroff.c +++ b/drivers/power/reset/mt6323-poweroff.c @@ -30,7 +30,7 @@ static void mt6323_do_pwroff(void) int ret; regmap_write(pwrc->regmap, pwrc->base + RTC_BBPU, RTC_BBPU_KEY); - regmap_write(pwrc->regmap, pwrc->base + RTC_WRTGR, 1); + regmap_write(pwrc->regmap, pwrc->base + RTC_WRTGR_MT6323, 1); ret = regmap_read_poll_timeout(pwrc->regmap, pwrc->base + RTC_BBPU, val, diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index f3424fdce341..a46643f5e2fb 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -541,6 +541,16 @@ config CHARGER_MAX8998 Say Y to enable support for the battery charger control sysfs and platform data of MAX8998/LP3974 PMICs. +config CHARGER_MP2629 + tristate "Monolithic power system MP2629 Battery charger" + depends on MFD_MP2629 + depends on MP2629_ADC + depends on IIO + help + Select this option to enable support for Monolithic power system + Battery charger. This driver provides Battery charger power management + functions on the systems. + config CHARGER_QCOM_SMBB tristate "Qualcomm Switch-Mode Battery Charger and Boost" depends on MFD_SPMI_PMIC || COMPILE_TEST diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile index 6c7da920ea83..41cb64f09e49 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_CHARGER_MAX77650) += max77650-charger.o obj-$(CONFIG_CHARGER_MAX77693) += max77693_charger.o obj-$(CONFIG_CHARGER_MAX8997) += max8997_charger.o obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o +obj-$(CONFIG_CHARGER_MP2629) += mp2629_charger.o obj-$(CONFIG_CHARGER_QCOM_SMBB) += qcom_smbb.o obj-$(CONFIG_CHARGER_BQ2415X) += bq2415x_charger.o obj-$(CONFIG_CHARGER_BQ24190) += bq24190_charger.o diff --git a/drivers/power/supply/mp2629_charger.c b/drivers/power/supply/mp2629_charger.c new file mode 100644 index 000000000000..bdf924b73e47 --- /dev/null +++ b/drivers/power/supply/mp2629_charger.c @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * MP2629 battery charger driver + * + * Copyright 2020 Monolithic Power Systems, Inc + * + * Author: Saravanan Sekar <sravanhome@gmail.com> + */ + +#include <linux/bits.h> +#include <linux/iio/consumer.h> +#include <linux/iio/types.h> +#include <linux/interrupt.h> +#include <linux/mfd/mp2629.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> +#include <linux/power_supply.h> +#include <linux/regmap.h> + +#define MP2629_REG_INPUT_ILIM 0x00 +#define MP2629_REG_INPUT_VLIM 0x01 +#define MP2629_REG_CHARGE_CTRL 0x04 +#define MP2629_REG_CHARGE_ILIM 0x05 +#define MP2629_REG_PRECHARGE 0x06 +#define MP2629_REG_TERM_CURRENT 0x06 +#define MP2629_REG_CHARGE_VLIM 0x07 +#define MP2629_REG_TIMER_CTRL 0x08 +#define MP2629_REG_IMPEDANCE_COMP 0x09 +#define MP2629_REG_INTERRUPT 0x0b +#define MP2629_REG_STATUS 0x0c +#define MP2629_REG_FAULT 0x0d + +#define MP2629_MASK_INPUT_TYPE GENMASK(7, 5) +#define MP2629_MASK_CHARGE_TYPE GENMASK(4, 3) +#define MP2629_MASK_CHARGE_CTRL GENMASK(5, 4) +#define MP2629_MASK_WDOG_CTRL GENMASK(5, 4) +#define MP2629_MASK_IMPEDANCE GENMASK(7, 4) + +#define MP2629_INPUTSOURCE_CHANGE GENMASK(7, 5) +#define MP2629_CHARGING_CHANGE GENMASK(4, 3) +#define MP2629_FAULT_BATTERY BIT(3) +#define MP2629_FAULT_THERMAL BIT(4) +#define MP2629_FAULT_INPUT BIT(5) +#define MP2629_FAULT_OTG BIT(6) + +#define MP2629_MAX_BATT_CAPACITY 100 + +#define MP2629_PROPS(_idx, _min, _max, _step) \ + [_idx] = { \ + .min = _min, \ + .max = _max, \ + .step = _step, \ +} + +enum mp2629_source_type { + MP2629_SOURCE_TYPE_NO_INPUT, + MP2629_SOURCE_TYPE_NON_STD, + MP2629_SOURCE_TYPE_SDP, + MP2629_SOURCE_TYPE_CDP, + MP2629_SOURCE_TYPE_DCP, + MP2629_SOURCE_TYPE_OTG = 7, +}; + +enum mp2629_field { + INPUT_ILIM, + INPUT_VLIM, + CHARGE_ILIM, + CHARGE_VLIM, + PRECHARGE, + TERM_CURRENT, + MP2629_MAX_FIELD +}; + +struct mp2629_charger { + struct device *dev; + int status; + int fault; + + struct regmap *regmap; + struct regmap_field *regmap_fields[MP2629_MAX_FIELD]; + struct mutex lock; + struct power_supply *usb; + struct power_supply *battery; + struct iio_channel *iiochan[MP2629_ADC_CHAN_END]; +}; + +struct mp2629_prop { + int reg; + int mask; + int min; + int max; + int step; + int shift; +}; + +static enum power_supply_usb_type mp2629_usb_types[] = { + POWER_SUPPLY_USB_TYPE_SDP, + POWER_SUPPLY_USB_TYPE_DCP, + POWER_SUPPLY_USB_TYPE_CDP, + POWER_SUPPLY_USB_TYPE_PD_DRP, + POWER_SUPPLY_USB_TYPE_UNKNOWN +}; + +static enum power_supply_property mp2629_charger_usb_props[] = { + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_USB_TYPE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT, +}; + +static enum power_supply_property mp2629_charger_bat_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_CHARGE_TYPE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_PRECHARGE_CURRENT, + POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX, +}; + +static struct mp2629_prop props[] = { + MP2629_PROPS(INPUT_ILIM, 100000, 3250000, 50000), + MP2629_PROPS(INPUT_VLIM, 3800000, 5300000, 100000), + MP2629_PROPS(CHARGE_ILIM, 320000, 4520000, 40000), + MP2629_PROPS(CHARGE_VLIM, 3400000, 4670000, 10000), + MP2629_PROPS(PRECHARGE, 120000, 720000, 40000), + MP2629_PROPS(TERM_CURRENT, 80000, 680000, 40000), +}; + +static const struct reg_field mp2629_reg_fields[] = { + [INPUT_ILIM] = REG_FIELD(MP2629_REG_INPUT_ILIM, 0, 5), + [INPUT_VLIM] = REG_FIELD(MP2629_REG_INPUT_VLIM, 0, 3), + [CHARGE_ILIM] = REG_FIELD(MP2629_REG_CHARGE_ILIM, 0, 6), + [CHARGE_VLIM] = REG_FIELD(MP2629_REG_CHARGE_VLIM, 1, 7), + [PRECHARGE] = REG_FIELD(MP2629_REG_PRECHARGE, 4, 7), + [TERM_CURRENT] = REG_FIELD(MP2629_REG_TERM_CURRENT, 0, 3), +}; + +static char *adc_chan_name[] = { + "mp2629-batt-volt", + "mp2629-system-volt", + "mp2629-input-volt", + "mp2629-batt-current", + "mp2629-input-current", +}; + +static int mp2629_read_adc(struct mp2629_charger *charger, + enum mp2629_adc_chan ch, + union power_supply_propval *val) +{ + int ret; + int chval; + + ret = iio_read_channel_processed(charger->iiochan[ch], &chval); + if (ret) + return ret; + + val->intval = chval * 1000; + + return 0; +} + +static int mp2629_get_prop(struct mp2629_charger *charger, + enum mp2629_field fld, + union power_supply_propval *val) +{ + int ret; + unsigned int rval; + + ret = regmap_field_read(charger->regmap_fields[fld], &rval); + if (ret) + return ret; + + val->intval = rval * props[fld].step + props[fld].min; + + return 0; +} + +static int mp2629_set_prop(struct mp2629_charger *charger, + enum mp2629_field fld, + const union power_supply_propval *val) +{ + unsigned int rval; + + if (val->intval < props[fld].min || val->intval > props[fld].max) + return -EINVAL; + + rval = (val->intval - props[fld].min) / props[fld].step; + return regmap_field_write(charger->regmap_fields[fld], rval); +} + +static int mp2629_get_battery_capacity(struct mp2629_charger *charger, + union power_supply_propval *val) +{ + union power_supply_propval vnow, vlim; + int ret; + + ret = mp2629_read_adc(charger, MP2629_BATT_VOLT, &vnow); + if (ret) + return ret; + + ret = mp2629_get_prop(charger, CHARGE_VLIM, &vlim); + if (ret) + return ret; + + val->intval = (vnow.intval * 100) / vlim.intval; + val->intval = min(val->intval, MP2629_MAX_BATT_CAPACITY); + + return 0; +} + +static int mp2629_charger_battery_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct mp2629_charger *charger = dev_get_drvdata(psy->dev.parent); + unsigned int rval; + int ret = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + ret = mp2629_read_adc(charger, MP2629_BATT_VOLT, val); + break; + + case POWER_SUPPLY_PROP_CURRENT_NOW: + ret = mp2629_read_adc(charger, MP2629_BATT_CURRENT, val); + break; + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: + val->intval = 4520000; + break; + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX: + val->intval = 4670000; + break; + + case POWER_SUPPLY_PROP_CAPACITY: + ret = mp2629_get_battery_capacity(charger, val); + break; + + case POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT: + ret = mp2629_get_prop(charger, TERM_CURRENT, val); + break; + + case POWER_SUPPLY_PROP_PRECHARGE_CURRENT: + ret = mp2629_get_prop(charger, PRECHARGE, val); + break; + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: + ret = mp2629_get_prop(charger, CHARGE_VLIM, val); + break; + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT: + ret = mp2629_get_prop(charger, CHARGE_ILIM, val); + break; + + case POWER_SUPPLY_PROP_HEALTH: + if (!charger->fault) + val->intval = POWER_SUPPLY_HEALTH_GOOD; + if (MP2629_FAULT_BATTERY & charger->fault) + val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; + else if (MP2629_FAULT_THERMAL & charger->fault) + val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; + else if (MP2629_FAULT_INPUT & charger->fault) + val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; + break; + + case POWER_SUPPLY_PROP_STATUS: + ret = regmap_read(charger->regmap, MP2629_REG_STATUS, &rval); + if (ret) + break; + + rval = (rval & MP2629_MASK_CHARGE_TYPE) >> 3; + switch (rval) { + case 0x00: + val->intval = POWER_SUPPLY_STATUS_DISCHARGING; + break; + case 0x01: + case 0x10: + val->intval = POWER_SUPPLY_STATUS_CHARGING; + break; + case 0x11: + val->intval = POWER_SUPPLY_STATUS_FULL; + } + break; + + case POWER_SUPPLY_PROP_CHARGE_TYPE: + ret = regmap_read(charger->regmap, MP2629_REG_STATUS, &rval); + if (ret) + break; + + rval = (rval & MP2629_MASK_CHARGE_TYPE) >> 3; + switch (rval) { + case 0x00: + val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; + break; + case 0x01: + val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; + break; + case 0x10: + val->intval = POWER_SUPPLY_CHARGE_TYPE_STANDARD; + break; + default: + val->intval = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN; + } + break; + + default: + return -EINVAL; + } + + return ret; +} + +static int mp2629_charger_battery_set_prop(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct mp2629_charger *charger = dev_get_drvdata(psy->dev.parent); + + switch (psp) { + case POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT: + return mp2629_set_prop(charger, TERM_CURRENT, val); + + case POWER_SUPPLY_PROP_PRECHARGE_CURRENT: + return mp2629_set_prop(charger, PRECHARGE, val); + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: + return mp2629_set_prop(charger, CHARGE_VLIM, val); + + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT: + return mp2629_set_prop(charger, CHARGE_ILIM, val); + + default: + return -EINVAL; + } +} + +static int mp2629_charger_usb_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct mp2629_charger *charger = dev_get_drvdata(psy->dev.parent); + unsigned int rval; + int ret; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + ret = regmap_read(charger->regmap, MP2629_REG_STATUS, &rval); + if (ret) + break; + + val->intval = !!(rval & MP2629_MASK_INPUT_TYPE); + break; + + case POWER_SUPPLY_PROP_USB_TYPE: + ret = regmap_read(charger->regmap, MP2629_REG_STATUS, &rval); + if (ret) + break; + + rval = (rval & MP2629_MASK_INPUT_TYPE) >> 5; + switch (rval) { + case MP2629_SOURCE_TYPE_SDP: + val->intval = POWER_SUPPLY_USB_TYPE_SDP; + break; + case MP2629_SOURCE_TYPE_CDP: + val->intval = POWER_SUPPLY_USB_TYPE_CDP; + break; + case MP2629_SOURCE_TYPE_DCP: + val->intval = POWER_SUPPLY_USB_TYPE_DCP; + break; + case MP2629_SOURCE_TYPE_OTG: + val->intval = POWER_SUPPLY_USB_TYPE_PD_DRP; + break; + default: + val->intval = POWER_SUPPLY_USB_TYPE_UNKNOWN; + break; + } + break; + + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + ret = mp2629_read_adc(charger, MP2629_INPUT_VOLT, val); + break; + + case POWER_SUPPLY_PROP_CURRENT_NOW: + ret = mp2629_read_adc(charger, MP2629_INPUT_CURRENT, val); + break; + + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT: + ret = mp2629_get_prop(charger, INPUT_VLIM, val); + break; + + case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: + ret = mp2629_get_prop(charger, INPUT_ILIM, val); + break; + + default: + return -EINVAL; + } + + return ret; +} + +static int mp2629_charger_usb_set_prop(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct mp2629_charger *charger = dev_get_drvdata(psy->dev.parent); + + switch (psp) { + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT: + return mp2629_set_prop(charger, INPUT_VLIM, val); + + case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: + return mp2629_set_prop(charger, INPUT_ILIM, val); + + default: + return -EINVAL; + } +} + +static int mp2629_charger_battery_prop_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + return (psp == POWER_SUPPLY_PROP_PRECHARGE_CURRENT) || + (psp == POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT) || + (psp == POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT) || + (psp == POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE); +} + +static int mp2629_charger_usb_prop_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + return (psp == POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT) || + (psp == POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT); +} + +static irqreturn_t mp2629_irq_handler(int irq, void *dev_id) +{ + struct mp2629_charger *charger = dev_id; + unsigned int rval; + int ret; + + mutex_lock(&charger->lock); + + ret = regmap_read(charger->regmap, MP2629_REG_FAULT, &rval); + if (ret) + goto unlock; + + if (rval) { + charger->fault = rval; + if (MP2629_FAULT_BATTERY & rval) + dev_err(charger->dev, "Battery fault OVP\n"); + else if (MP2629_FAULT_THERMAL & rval) + dev_err(charger->dev, "Thermal shutdown fault\n"); + else if (MP2629_FAULT_INPUT & rval) + dev_err(charger->dev, "no input or input OVP\n"); + else if (MP2629_FAULT_OTG & rval) + dev_err(charger->dev, "VIN overloaded\n"); + + goto unlock; + } + + ret = regmap_read(charger->regmap, MP2629_REG_STATUS, &rval); + if (ret) + goto unlock; + + if (rval & MP2629_INPUTSOURCE_CHANGE) + power_supply_changed(charger->usb); + else if (rval & MP2629_CHARGING_CHANGE) + power_supply_changed(charger->battery); + +unlock: + mutex_unlock(&charger->lock); + + return IRQ_HANDLED; +} + +static const struct power_supply_desc mp2629_usb_desc = { + .name = "mp2629_usb", + .type = POWER_SUPPLY_TYPE_USB, + .usb_types = mp2629_usb_types, + .num_usb_types = ARRAY_SIZE(mp2629_usb_types), + .properties = mp2629_charger_usb_props, + .num_properties = ARRAY_SIZE(mp2629_charger_usb_props), + .get_property = mp2629_charger_usb_get_prop, + .set_property = mp2629_charger_usb_set_prop, + .property_is_writeable = mp2629_charger_usb_prop_writeable, +}; + +static const struct power_supply_desc mp2629_battery_desc = { + .name = "mp2629_battery", + .type = POWER_SUPPLY_TYPE_BATTERY, + .properties = mp2629_charger_bat_props, + .num_properties = ARRAY_SIZE(mp2629_charger_bat_props), + .get_property = mp2629_charger_battery_get_prop, + .set_property = mp2629_charger_battery_set_prop, + .property_is_writeable = mp2629_charger_battery_prop_writeable, +}; + +static ssize_t batt_impedance_compensation_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct mp2629_charger *charger = dev_get_drvdata(dev->parent); + unsigned int rval; + int ret; + + ret = regmap_read(charger->regmap, MP2629_REG_IMPEDANCE_COMP, &rval); + if (ret) + return ret; + + rval = (rval >> 4) * 10; + return sprintf(buf, "%d mohm\n", rval); +} + +static ssize_t batt_impedance_compensation_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct mp2629_charger *charger = dev_get_drvdata(dev->parent); + unsigned int val; + int ret; + + ret = kstrtouint(buf, 10, &val); + if (ret) + return ret; + + if (val > 140) + return -ERANGE; + + /* multiples of 10 mohm so round off */ + val = val / 10; + ret = regmap_update_bits(charger->regmap, MP2629_REG_IMPEDANCE_COMP, + MP2629_MASK_IMPEDANCE, val << 4); + if (ret) + return ret; + + return count; +} + +static DEVICE_ATTR_RW(batt_impedance_compensation); + +static struct attribute *mp2629_charger_sysfs_attrs[] = { + &dev_attr_batt_impedance_compensation.attr, + NULL +}; +ATTRIBUTE_GROUPS(mp2629_charger_sysfs); + +static void mp2629_charger_disable(void *data) +{ + struct mp2629_charger *charger = data; + + regmap_update_bits(charger->regmap, MP2629_REG_CHARGE_CTRL, + MP2629_MASK_CHARGE_CTRL, 0); +} + +static int mp2629_charger_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mp2629_data *ddata = dev_get_drvdata(dev->parent); + struct mp2629_charger *charger; + struct power_supply_config psy_cfg = {}; + int ret, i, irq; + + charger = devm_kzalloc(dev, sizeof(*charger), GFP_KERNEL); + if (!charger) + return -ENOMEM; + + charger->regmap = ddata->regmap; + charger->dev = dev; + platform_set_drvdata(pdev, charger); + + irq = platform_get_irq_optional(to_platform_device(dev->parent), 0); + if (irq < 0) { + dev_err(dev, "get irq fail: %d\n", irq); + return irq; + } + + for (i = 0; i < MP2629_MAX_FIELD; i++) { + charger->regmap_fields[i] = devm_regmap_field_alloc(dev, + charger->regmap, mp2629_reg_fields[i]); + if (IS_ERR(charger->regmap_fields[i])) { + dev_err(dev, "regmap field alloc fail %d\n", i); + return PTR_ERR(charger->regmap_fields[i]); + } + } + + for (i = 0; i < MP2629_ADC_CHAN_END; i++) { + charger->iiochan[i] = devm_iio_channel_get(dev, + adc_chan_name[i]); + if (IS_ERR(charger->iiochan[i])) { + dev_err(dev, "iio chan get %s err\n", adc_chan_name[i]); + return PTR_ERR(charger->iiochan[i]); + } + } + + ret = devm_add_action_or_reset(dev, mp2629_charger_disable, charger); + if (ret) + return ret; + + charger->usb = devm_power_supply_register(dev, &mp2629_usb_desc, NULL); + if (IS_ERR(charger->usb)) { + dev_err(dev, "power supply register usb failed\n"); + return PTR_ERR(charger->usb); + } + + psy_cfg.drv_data = charger; + psy_cfg.attr_grp = mp2629_charger_sysfs_groups; + charger->battery = devm_power_supply_register(dev, + &mp2629_battery_desc, &psy_cfg); + if (IS_ERR(charger->battery)) { + dev_err(dev, "power supply register battery failed\n"); + return PTR_ERR(charger->battery); + } + + ret = regmap_update_bits(charger->regmap, MP2629_REG_CHARGE_CTRL, + MP2629_MASK_CHARGE_CTRL, BIT(4)); + if (ret) { + dev_err(dev, "enable charge fail: %d\n", ret); + return ret; + } + + regmap_update_bits(charger->regmap, MP2629_REG_TIMER_CTRL, + MP2629_MASK_WDOG_CTRL, 0); + + mutex_init(&charger->lock); + + ret = devm_request_threaded_irq(dev, irq, NULL, mp2629_irq_handler, + IRQF_ONESHOT | IRQF_TRIGGER_RISING, + "mp2629-charger", charger); + if (ret) { + dev_err(dev, "failed to request gpio IRQ\n"); + return ret; + } + + regmap_update_bits(charger->regmap, MP2629_REG_INTERRUPT, + GENMASK(6, 5), BIT(6) | BIT(5)); + + return 0; +} + +static const struct of_device_id mp2629_charger_of_match[] = { + { .compatible = "mps,mp2629_charger"}, + {} +}; +MODULE_DEVICE_TABLE(of, mp2629_charger_of_match); + +static struct platform_driver mp2629_charger_driver = { + .driver = { + .name = "mp2629_charger", + .of_match_table = mp2629_charger_of_match, + }, + .probe = mp2629_charger_probe, +}; +module_platform_driver(mp2629_charger_driver); + +MODULE_AUTHOR("Saravanan Sekar <sravanhome@gmail.com>"); +MODULE_DESCRIPTION("MP2629 Charger driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c index cda238dfe69b..f8b1353777ba 100644 --- a/drivers/rtc/rtc-mt6397.c +++ b/drivers/rtc/rtc-mt6397.c @@ -9,6 +9,7 @@ #include <linux/mfd/mt6397/core.h> #include <linux/module.h> #include <linux/mutex.h> +#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/rtc.h> @@ -20,7 +21,7 @@ static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) int ret; u32 data; - ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1); + ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1); if (ret < 0) return ret; @@ -269,6 +270,8 @@ static int mtk_rtc_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); rtc->addr_base = res->start; + rtc->data = of_device_get_match_data(&pdev->dev); + rtc->irq = platform_get_irq(pdev, 0); if (rtc->irq < 0) return rtc->irq; @@ -325,9 +328,18 @@ static int mt6397_rtc_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend, mt6397_rtc_resume); +static const struct mtk_rtc_data mt6358_rtc_data = { + .wrtgr = RTC_WRTGR_MT6358, +}; + +static const struct mtk_rtc_data mt6397_rtc_data = { + .wrtgr = RTC_WRTGR_MT6397, +}; + static const struct of_device_id mt6397_rtc_of_match[] = { - { .compatible = "mediatek,mt6323-rtc", }, - { .compatible = "mediatek,mt6397-rtc", }, + { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data }, + { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data }, + { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data }, { } }; MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match); diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index d01d1299e49d..7e5ac3c00891 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h @@ -70,7 +70,7 @@ struct mfd_cell { size_t pdata_size; /* device properties passed to the sub devices drivers */ - struct property_entry *properties; + const struct property_entry *properties; /* * Device Tree compatible string diff --git a/include/linux/mfd/mp2629.h b/include/linux/mfd/mp2629.h new file mode 100644 index 000000000000..89b706900b57 --- /dev/null +++ b/include/linux/mfd/mp2629.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Monolithic Power Systems, Inc + */ + +#ifndef __MP2629_H__ +#define __MP2629_H__ + +#include <linux/device.h> +#include <linux/regmap.h> + +struct mp2629_data { + struct device *dev; + struct regmap *regmap; +}; + +enum mp2629_adc_chan { + MP2629_BATT_VOLT, + MP2629_SYSTEM_VOLT, + MP2629_INPUT_VOLT, + MP2629_BATT_CURRENT, + MP2629_INPUT_CURRENT, + MP2629_ADC_CHAN_END +}; + +#endif diff --git a/include/linux/mfd/mt6358/core.h b/include/linux/mfd/mt6358/core.h new file mode 100644 index 000000000000..c5a11b7458d4 --- /dev/null +++ b/include/linux/mfd/mt6358/core.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef __MFD_MT6358_CORE_H__ +#define __MFD_MT6358_CORE_H__ + +#define MT6358_REG_WIDTH 16 + +struct irq_top_t { + int hwirq_base; + unsigned int num_int_regs; + unsigned int num_int_bits; + unsigned int en_reg; + unsigned int en_reg_shift; + unsigned int sta_reg; + unsigned int sta_reg_shift; + unsigned int top_offset; +}; + +struct pmic_irq_data { + unsigned int num_top; + unsigned int num_pmic_irqs; + unsigned short top_int_status_reg; + bool *enable_hwirq; + bool *cache_hwirq; +}; + +enum mt6358_irq_top_status_shift { + MT6358_BUCK_TOP = 0, + MT6358_LDO_TOP, + MT6358_PSC_TOP, + MT6358_SCK_TOP, + MT6358_BM_TOP, + MT6358_HK_TOP, + MT6358_AUD_TOP, + MT6358_MISC_TOP, +}; + +enum mt6358_irq_numbers { + MT6358_IRQ_VPROC11_OC = 0, + MT6358_IRQ_VPROC12_OC, + MT6358_IRQ_VCORE_OC, + MT6358_IRQ_VGPU_OC, + MT6358_IRQ_VMODEM_OC, + MT6358_IRQ_VDRAM1_OC, + MT6358_IRQ_VS1_OC, + MT6358_IRQ_VS2_OC, + MT6358_IRQ_VPA_OC, + MT6358_IRQ_VCORE_PREOC, + MT6358_IRQ_VFE28_OC = 16, + MT6358_IRQ_VXO22_OC, + MT6358_IRQ_VRF18_OC, + MT6358_IRQ_VRF12_OC, + MT6358_IRQ_VEFUSE_OC, + MT6358_IRQ_VCN33_OC, + MT6358_IRQ_VCN28_OC, + MT6358_IRQ_VCN18_OC, + MT6358_IRQ_VCAMA1_OC, + MT6358_IRQ_VCAMA2_OC, + MT6358_IRQ_VCAMD_OC, + MT6358_IRQ_VCAMIO_OC, + MT6358_IRQ_VLDO28_OC, + MT6358_IRQ_VA12_OC, + MT6358_IRQ_VAUX18_OC, + MT6358_IRQ_VAUD28_OC, + MT6358_IRQ_VIO28_OC, + MT6358_IRQ_VIO18_OC, + MT6358_IRQ_VSRAM_PROC11_OC, + MT6358_IRQ_VSRAM_PROC12_OC, + MT6358_IRQ_VSRAM_OTHERS_OC, + MT6358_IRQ_VSRAM_GPU_OC, + MT6358_IRQ_VDRAM2_OC, + MT6358_IRQ_VMC_OC, + MT6358_IRQ_VMCH_OC, + MT6358_IRQ_VEMC_OC, + MT6358_IRQ_VSIM1_OC, + MT6358_IRQ_VSIM2_OC, + MT6358_IRQ_VIBR_OC, + MT6358_IRQ_VUSB_OC, + MT6358_IRQ_VBIF28_OC, + MT6358_IRQ_PWRKEY = 48, + MT6358_IRQ_HOMEKEY, + MT6358_IRQ_PWRKEY_R, + MT6358_IRQ_HOMEKEY_R, + MT6358_IRQ_NI_LBAT_INT, + MT6358_IRQ_CHRDET, + MT6358_IRQ_CHRDET_EDGE, + MT6358_IRQ_VCDT_HV_DET, + MT6358_IRQ_RTC = 64, + MT6358_IRQ_FG_BAT0_H = 80, + MT6358_IRQ_FG_BAT0_L, + MT6358_IRQ_FG_CUR_H, + MT6358_IRQ_FG_CUR_L, + MT6358_IRQ_FG_ZCV, + MT6358_IRQ_FG_BAT1_H, + MT6358_IRQ_FG_BAT1_L, + MT6358_IRQ_FG_N_CHARGE_L, + MT6358_IRQ_FG_IAVG_H, + MT6358_IRQ_FG_IAVG_L, + MT6358_IRQ_FG_TIME_H, + MT6358_IRQ_FG_DISCHARGE, + MT6358_IRQ_FG_CHARGE, + MT6358_IRQ_BATON_LV = 96, + MT6358_IRQ_BATON_HT, + MT6358_IRQ_BATON_BAT_IN, + MT6358_IRQ_BATON_BAT_OUT, + MT6358_IRQ_BIF, + MT6358_IRQ_BAT_H = 112, + MT6358_IRQ_BAT_L, + MT6358_IRQ_BAT2_H, + MT6358_IRQ_BAT2_L, + MT6358_IRQ_BAT_TEMP_H, + MT6358_IRQ_BAT_TEMP_L, + MT6358_IRQ_AUXADC_IMP, + MT6358_IRQ_NAG_C_DLTV, + MT6358_IRQ_AUDIO = 128, + MT6358_IRQ_ACCDET = 133, + MT6358_IRQ_ACCDET_EINT0, + MT6358_IRQ_ACCDET_EINT1, + MT6358_IRQ_SPI_CMD_ALERT = 144, + MT6358_IRQ_NR, +}; + +#define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC +#define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC +#define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY +#define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC +#define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H +#define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H +#define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO +#define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT + +#define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1) +#define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1) +#define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1) +#define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1) +#define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1) +#define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1) +#define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1) +#define MT6358_IRQ_MISC_BITS \ + (MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1) + +#define MT6358_TOP_GEN(sp) \ +{ \ + .hwirq_base = MT6358_IRQ_##sp##_BASE, \ + .num_int_regs = \ + ((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1, \ + .num_int_bits = MT6358_IRQ_##sp##_BITS, \ + .en_reg = MT6358_##sp##_TOP_INT_CON0, \ + .en_reg_shift = 0x6, \ + .sta_reg = MT6358_##sp##_TOP_INT_STATUS0, \ + .sta_reg_shift = 0x2, \ + .top_offset = MT6358_##sp##_TOP, \ +} + +#endif /* __MFD_MT6358_CORE_H__ */ diff --git a/include/linux/mfd/mt6358/registers.h b/include/linux/mfd/mt6358/registers.h new file mode 100644 index 000000000000..2ad0b312aa28 --- /dev/null +++ b/include/linux/mfd/mt6358/registers.h @@ -0,0 +1,282 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef __MFD_MT6358_REGISTERS_H__ +#define __MFD_MT6358_REGISTERS_H__ + +/* PMIC Registers */ +#define MT6358_SWCID 0xa +#define MT6358_MISC_TOP_INT_CON0 0x188 +#define MT6358_MISC_TOP_INT_STATUS0 0x194 +#define MT6358_TOP_INT_STATUS0 0x19e +#define MT6358_SCK_TOP_INT_CON0 0x52e +#define MT6358_SCK_TOP_INT_STATUS0 0x53a +#define MT6358_EOSC_CALI_CON0 0x540 +#define MT6358_EOSC_CALI_CON1 0x542 +#define MT6358_RTC_MIX_CON0 0x544 +#define MT6358_RTC_MIX_CON1 0x546 +#define MT6358_RTC_MIX_CON2 0x548 +#define MT6358_RTC_DSN_ID 0x580 +#define MT6358_RTC_DSN_REV0 0x582 +#define MT6358_RTC_DBI 0x584 +#define MT6358_RTC_DXI 0x586 +#define MT6358_RTC_BBPU 0x588 +#define MT6358_RTC_IRQ_STA 0x58a +#define MT6358_RTC_IRQ_EN 0x58c +#define MT6358_RTC_CII_EN 0x58e +#define MT6358_RTC_AL_MASK 0x590 +#define MT6358_RTC_TC_SEC 0x592 +#define MT6358_RTC_TC_MIN 0x594 +#define MT6358_RTC_TC_HOU 0x596 +#define MT6358_RTC_TC_DOM 0x598 +#define MT6358_RTC_TC_DOW 0x59a +#define MT6358_RTC_TC_MTH 0x59c +#define MT6358_RTC_TC_YEA 0x59e +#define MT6358_RTC_AL_SEC 0x5a0 +#define MT6358_RTC_AL_MIN 0x5a2 +#define MT6358_RTC_AL_HOU 0x5a4 +#define MT6358_RTC_AL_DOM 0x5a6 +#define MT6358_RTC_AL_DOW 0x5a8 +#define MT6358_RTC_AL_MTH 0x5aa +#define MT6358_RTC_AL_YEA 0x5ac +#define MT6358_RTC_OSC32CON 0x5ae +#define MT6358_RTC_POWERKEY1 0x5b0 +#define MT6358_RTC_POWERKEY2 0x5b2 +#define MT6358_RTC_PDN1 0x5b4 +#define MT6358_RTC_PDN2 0x5b6 +#define MT6358_RTC_SPAR0 0x5b8 +#define MT6358_RTC_SPAR1 0x5ba +#define MT6358_RTC_PROT 0x5bc +#define MT6358_RTC_DIFF 0x5be +#define MT6358_RTC_CALI 0x5c0 +#define MT6358_RTC_WRTGR 0x5c2 +#define MT6358_RTC_CON 0x5c4 +#define MT6358_RTC_SEC_CTRL 0x5c6 +#define MT6358_RTC_INT_CNT 0x5c8 +#define MT6358_RTC_SEC_DAT0 0x5ca +#define MT6358_RTC_SEC_DAT1 0x5cc +#define MT6358_RTC_SEC_DAT2 0x5ce +#define MT6358_RTC_SEC_DSN_ID 0x600 +#define MT6358_RTC_SEC_DSN_REV0 0x602 +#define MT6358_RTC_SEC_DBI 0x604 +#define MT6358_RTC_SEC_DXI 0x606 +#define MT6358_RTC_TC_SEC_SEC 0x608 +#define MT6358_RTC_TC_MIN_SEC 0x60a +#define MT6358_RTC_TC_HOU_SEC 0x60c +#define MT6358_RTC_TC_DOM_SEC 0x60e +#define MT6358_RTC_TC_DOW_SEC 0x610 +#define MT6358_RTC_TC_MTH_SEC 0x612 +#define MT6358_RTC_TC_YEA_SEC 0x614 +#define MT6358_RTC_SEC_CK_PDN 0x616 +#define MT6358_RTC_SEC_WRTGR 0x618 +#define MT6358_PSC_TOP_INT_CON0 0x910 +#define MT6358_PSC_TOP_INT_STATUS0 0x91c +#define MT6358_BM_TOP_INT_CON0 0xc32 +#define MT6358_BM_TOP_INT_CON1 0xc38 +#define MT6358_BM_TOP_INT_STATUS0 0xc4a +#define MT6358_BM_TOP_INT_STATUS1 0xc4c +#define MT6358_HK_TOP_INT_CON0 0xf92 +#define MT6358_HK_TOP_INT_STATUS0 0xf9e +#define MT6358_BUCK_TOP_INT_CON0 0x1318 +#define MT6358_BUCK_TOP_INT_STATUS0 0x1324 +#define MT6358_BUCK_VPROC11_CON0 0x1388 +#define MT6358_BUCK_VPROC11_DBG0 0x139e +#define MT6358_BUCK_VPROC11_DBG1 0x13a0 +#define MT6358_BUCK_VPROC11_ELR0 0x13a6 +#define MT6358_BUCK_VPROC12_CON0 0x1408 +#define MT6358_BUCK_VPROC12_DBG0 0x141e +#define MT6358_BUCK_VPROC12_DBG1 0x1420 +#define MT6358_BUCK_VPROC12_ELR0 0x1426 +#define MT6358_BUCK_VCORE_CON0 0x1488 +#define MT6358_BUCK_VCORE_DBG0 0x149e +#define MT6358_BUCK_VCORE_DBG1 0x14a0 +#define MT6358_BUCK_VCORE_ELR0 0x14aa +#define MT6358_BUCK_VGPU_CON0 0x1508 +#define MT6358_BUCK_VGPU_DBG0 0x151e +#define MT6358_BUCK_VGPU_DBG1 0x1520 +#define MT6358_BUCK_VGPU_ELR0 0x1526 +#define MT6358_BUCK_VMODEM_CON0 0x1588 +#define MT6358_BUCK_VMODEM_DBG0 0x159e +#define MT6358_BUCK_VMODEM_DBG1 0x15a0 +#define MT6358_BUCK_VMODEM_ELR0 0x15a6 +#define MT6358_BUCK_VDRAM1_CON0 0x1608 +#define MT6358_BUCK_VDRAM1_DBG0 0x161e +#define MT6358_BUCK_VDRAM1_DBG1 0x1620 +#define MT6358_BUCK_VDRAM1_ELR0 0x1626 +#define MT6358_BUCK_VS1_CON0 0x1688 +#define MT6358_BUCK_VS1_DBG0 0x169e +#define MT6358_BUCK_VS1_DBG1 0x16a0 +#define MT6358_BUCK_VS1_ELR0 0x16ae +#define MT6358_BUCK_VS2_CON0 0x1708 +#define MT6358_BUCK_VS2_DBG0 0x171e +#define MT6358_BUCK_VS2_DBG1 0x1720 +#define MT6358_BUCK_VS2_ELR0 0x172e +#define MT6358_BUCK_VPA_CON0 0x1788 +#define MT6358_BUCK_VPA_CON1 0x178a +#define MT6358_BUCK_VPA_ELR0 MT6358_BUCK_VPA_CON1 +#define MT6358_BUCK_VPA_DBG0 0x1792 +#define MT6358_BUCK_VPA_DBG1 0x1794 +#define MT6358_VPROC_ANA_CON0 0x180c +#define MT6358_VCORE_VGPU_ANA_CON0 0x1828 +#define MT6358_VMODEM_ANA_CON0 0x1888 +#define MT6358_VDRAM1_ANA_CON0 0x1896 +#define MT6358_VS1_ANA_CON0 0x18a2 +#define MT6358_VS2_ANA_CON0 0x18ae +#define MT6358_VPA_ANA_CON0 0x18ba +#define MT6358_LDO_TOP_INT_CON0 0x1a50 +#define MT6358_LDO_TOP_INT_CON1 0x1a56 +#define MT6358_LDO_TOP_INT_STATUS0 0x1a68 +#define MT6358_LDO_TOP_INT_STATUS1 0x1a6a +#define MT6358_LDO_VXO22_CON0 0x1a88 +#define MT6358_LDO_VXO22_CON1 0x1a96 +#define MT6358_LDO_VA12_CON0 0x1a9c +#define MT6358_LDO_VA12_CON1 0x1aaa +#define MT6358_LDO_VAUX18_CON0 0x1ab0 +#define MT6358_LDO_VAUX18_CON1 0x1abe +#define MT6358_LDO_VAUD28_CON0 0x1ac4 +#define MT6358_LDO_VAUD28_CON1 0x1ad2 +#define MT6358_LDO_VIO28_CON0 0x1ad8 +#define MT6358_LDO_VIO28_CON1 0x1ae6 +#define MT6358_LDO_VIO18_CON0 0x1aec +#define MT6358_LDO_VIO18_CON1 0x1afa +#define MT6358_LDO_VDRAM2_CON0 0x1b08 +#define MT6358_LDO_VDRAM2_CON1 0x1b16 +#define MT6358_LDO_VEMC_CON0 0x1b1c +#define MT6358_LDO_VEMC_CON1 0x1b2a +#define MT6358_LDO_VUSB_CON0_0 0x1b30 +#define MT6358_LDO_VUSB_CON1 0x1b40 +#define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46 +#define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60 +#define MT6358_LDO_VSRAM_PROC11_DBG1 0x1b62 +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON0 0x1b64 +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON1 0x1b66 +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON2 0x1b68 +#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON3 0x1b6a +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON0 0x1b6c +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON1 0x1b6e +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON2 0x1b70 +#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON3 0x1b72 +#define MT6358_LDO_VSRAM_WAKEUP_CON0 0x1b74 +#define MT6358_LDO_GON1_ELR_NUM 0x1b76 +#define MT6358_LDO_VDRAM2_ELR0 0x1b78 +#define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88 +#define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2 +#define MT6358_LDO_VSRAM_PROC12_DBG1 0x1ba4 +#define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6 +#define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0 +#define MT6358_LDO_VSRAM_OTHERS_DBG1 0x1bc2 +#define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8 +#define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2 +#define MT6358_LDO_VSRAM_GPU_DBG1 0x1be4 +#define MT6358_LDO_VSRAM_CON0 0x1bee +#define MT6358_LDO_VSRAM_CON1 0x1bf0 +#define MT6358_LDO_VSRAM_CON2 0x1bf2 +#define MT6358_LDO_VSRAM_CON3 0x1bf4 +#define MT6358_LDO_VFE28_CON0 0x1c08 +#define MT6358_LDO_VFE28_CON1 0x1c16 +#define MT6358_LDO_VFE28_CON2 0x1c18 +#define MT6358_LDO_VFE28_CON3 0x1c1a +#define MT6358_LDO_VRF18_CON0 0x1c1c +#define MT6358_LDO_VRF18_CON1 0x1c2a +#define MT6358_LDO_VRF18_CON2 0x1c2c +#define MT6358_LDO_VRF18_CON3 0x1c2e +#define MT6358_LDO_VRF12_CON0 0x1c30 +#define MT6358_LDO_VRF12_CON1 0x1c3e +#define MT6358_LDO_VRF12_CON2 0x1c40 +#define MT6358_LDO_VRF12_CON3 0x1c42 +#define MT6358_LDO_VEFUSE_CON0 0x1c44 +#define MT6358_LDO_VEFUSE_CON1 0x1c52 +#define MT6358_LDO_VEFUSE_CON2 0x1c54 +#define MT6358_LDO_VEFUSE_CON3 0x1c56 +#define MT6358_LDO_VCN18_CON0 0x1c58 +#define MT6358_LDO_VCN18_CON1 0x1c66 +#define MT6358_LDO_VCN18_CON2 0x1c68 +#define MT6358_LDO_VCN18_CON3 0x1c6a +#define MT6358_LDO_VCAMA1_CON0 0x1c6c +#define MT6358_LDO_VCAMA1_CON1 0x1c7a +#define MT6358_LDO_VCAMA1_CON2 0x1c7c +#define MT6358_LDO_VCAMA1_CON3 0x1c7e +#define MT6358_LDO_VCAMA2_CON0 0x1c88 +#define MT6358_LDO_VCAMA2_CON1 0x1c96 +#define MT6358_LDO_VCAMA2_CON2 0x1c98 +#define MT6358_LDO_VCAMA2_CON3 0x1c9a +#define MT6358_LDO_VCAMD_CON0 0x1c9c +#define MT6358_LDO_VCAMD_CON1 0x1caa +#define MT6358_LDO_VCAMD_CON2 0x1cac +#define MT6358_LDO_VCAMD_CON3 0x1cae +#define MT6358_LDO_VCAMIO_CON0 0x1cb0 +#define MT6358_LDO_VCAMIO_CON1 0x1cbe +#define MT6358_LDO_VCAMIO_CON2 0x1cc0 +#define MT6358_LDO_VCAMIO_CON3 0x1cc2 +#define MT6358_LDO_VMC_CON0 0x1cc4 +#define MT6358_LDO_VMC_CON1 0x1cd2 +#define MT6358_LDO_VMC_CON2 0x1cd4 +#define MT6358_LDO_VMC_CON3 0x1cd6 +#define MT6358_LDO_VMCH_CON0 0x1cd8 +#define MT6358_LDO_VMCH_CON1 0x1ce6 +#define MT6358_LDO_VMCH_CON2 0x1ce8 +#define MT6358_LDO_VMCH_CON3 0x1cea +#define MT6358_LDO_VIBR_CON0 0x1d08 +#define MT6358_LDO_VIBR_CON1 0x1d16 +#define MT6358_LDO_VIBR_CON2 0x1d18 +#define MT6358_LDO_VIBR_CON3 0x1d1a +#define MT6358_LDO_VCN33_CON0_0 0x1d1c +#define MT6358_LDO_VCN33_CON0_1 0x1d2a +#define MT6358_LDO_VCN33_CON1 0x1d2c +#define MT6358_LDO_VCN33_BT_CON1 MT6358_LDO_VCN33_CON1 +#define MT6358_LDO_VCN33_WIFI_CON1 MT6358_LDO_VCN33_CON1 +#define MT6358_LDO_VCN33_CON2 0x1d2e +#define MT6358_LDO_VCN33_CON3 0x1d30 +#define MT6358_LDO_VLDO28_CON0_0 0x1d32 +#define MT6358_LDO_VLDO28_CON0_1 0x1d40 +#define MT6358_LDO_VLDO28_CON1 0x1d42 +#define MT6358_LDO_VLDO28_CON2 0x1d44 +#define MT6358_LDO_VLDO28_CON3 0x1d46 +#define MT6358_LDO_VSIM1_CON0 0x1d48 +#define MT6358_LDO_VSIM1_CON1 0x1d56 +#define MT6358_LDO_VSIM1_CON2 0x1d58 +#define MT6358_LDO_VSIM1_CON3 0x1d5a +#define MT6358_LDO_VSIM2_CON0 0x1d5c +#define MT6358_LDO_VSIM2_CON1 0x1d6a +#define MT6358_LDO_VSIM2_CON2 0x1d6c +#define MT6358_LDO_VSIM2_CON3 0x1d6e +#define MT6358_LDO_VCN28_CON0 0x1d88 +#define MT6358_LDO_VCN28_CON1 0x1d96 +#define MT6358_LDO_VCN28_CON2 0x1d98 +#define MT6358_LDO_VCN28_CON3 0x1d9a +#define MT6358_VRTC28_CON0 0x1d9c +#define MT6358_LDO_VBIF28_CON0 0x1d9e +#define MT6358_LDO_VBIF28_CON1 0x1dac +#define MT6358_LDO_VBIF28_CON2 0x1dae +#define MT6358_LDO_VBIF28_CON3 0x1db0 +#define MT6358_VCAMA1_ANA_CON0 0x1e08 +#define MT6358_VCAMA2_ANA_CON0 0x1e0c +#define MT6358_VCN33_ANA_CON0 0x1e28 +#define MT6358_VSIM1_ANA_CON0 0x1e2c +#define MT6358_VSIM2_ANA_CON0 0x1e30 +#define MT6358_VUSB_ANA_CON0 0x1e34 +#define MT6358_VEMC_ANA_CON0 0x1e38 +#define MT6358_VLDO28_ANA_CON0 0x1e3c +#define MT6358_VIO28_ANA_CON0 0x1e40 +#define MT6358_VIBR_ANA_CON0 0x1e44 +#define MT6358_VMCH_ANA_CON0 0x1e48 +#define MT6358_VMC_ANA_CON0 0x1e4c +#define MT6358_VRF18_ANA_CON0 0x1e88 +#define MT6358_VCN18_ANA_CON0 0x1e8c +#define MT6358_VCAMIO_ANA_CON0 0x1e90 +#define MT6358_VIO18_ANA_CON0 0x1e94 +#define MT6358_VEFUSE_ANA_CON0 0x1e98 +#define MT6358_VRF12_ANA_CON0 0x1e9c +#define MT6358_VSRAM_PROC11_ANA_CON0 0x1ea0 +#define MT6358_VSRAM_PROC12_ANA_CON0 0x1ea4 +#define MT6358_VSRAM_OTHERS_ANA_CON0 0x1ea6 +#define MT6358_VSRAM_GPU_ANA_CON0 0x1ea8 +#define MT6358_VDRAM2_ANA_CON0 0x1eaa +#define MT6358_VCAMD_ANA_CON0 0x1eae +#define MT6358_VA12_ANA_CON0 0x1eb2 +#define MT6358_AUD_TOP_INT_CON0 0x2228 +#define MT6358_AUD_TOP_INT_STATUS0 0x2234 + +#endif /* __MFD_MT6358_REGISTERS_H__ */ diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h new file mode 100644 index 000000000000..ea1304035d4d --- /dev/null +++ b/include/linux/mfd/mt6360.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef __MT6360_H__ +#define __MT6360_H__ + +#include <linux/regmap.h> + +enum { + MT6360_SLAVE_PMU = 0, + MT6360_SLAVE_PMIC, + MT6360_SLAVE_LDO, + MT6360_SLAVE_TCPC, + MT6360_SLAVE_MAX, +}; + +#define MT6360_PMU_SLAVEID (0x34) +#define MT6360_PMIC_SLAVEID (0x1A) +#define MT6360_LDO_SLAVEID (0x64) +#define MT6360_TCPC_SLAVEID (0x4E) + +struct mt6360_pmu_data { + struct i2c_client *i2c[MT6360_SLAVE_MAX]; + struct device *dev; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data; + unsigned int chip_rev; +}; + +/* PMU register defininition */ +#define MT6360_PMU_DEV_INFO (0x00) +#define MT6360_PMU_CORE_CTRL1 (0x01) +#define MT6360_PMU_RST1 (0x02) +#define MT6360_PMU_CRCEN (0x03) +#define MT6360_PMU_RST_PAS_CODE1 (0x04) +#define MT6360_PMU_RST_PAS_CODE2 (0x05) +#define MT6360_PMU_CORE_CTRL2 (0x06) +#define MT6360_PMU_TM_PAS_CODE1 (0x07) +#define MT6360_PMU_TM_PAS_CODE2 (0x08) +#define MT6360_PMU_TM_PAS_CODE3 (0x09) +#define MT6360_PMU_TM_PAS_CODE4 (0x0A) +#define MT6360_PMU_IRQ_IND (0x0B) +#define MT6360_PMU_IRQ_MASK (0x0C) +#define MT6360_PMU_IRQ_SET (0x0D) +#define MT6360_PMU_SHDN_CTRL (0x0E) +#define MT6360_PMU_TM_INF (0x0F) +#define MT6360_PMU_I2C_CTRL (0x10) +#define MT6360_PMU_CHG_CTRL1 (0x11) +#define MT6360_PMU_CHG_CTRL2 (0x12) +#define MT6360_PMU_CHG_CTRL3 (0x13) +#define MT6360_PMU_CHG_CTRL4 (0x14) +#define MT6360_PMU_CHG_CTRL5 (0x15) +#define MT6360_PMU_CHG_CTRL6 (0x16) +#define MT6360_PMU_CHG_CTRL7 (0x17) +#define MT6360_PMU_CHG_CTRL8 (0x18) +#define MT6360_PMU_CHG_CTRL9 (0x19) +#define MT6360_PMU_CHG_CTRL10 (0x1A) +#define MT6360_PMU_CHG_CTRL11 (0x1B) +#define MT6360_PMU_CHG_CTRL12 (0x1C) +#define MT6360_PMU_CHG_CTRL13 (0x1D) +#define MT6360_PMU_CHG_CTRL14 (0x1E) +#define MT6360_PMU_CHG_CTRL15 (0x1F) +#define MT6360_PMU_CHG_CTRL16 (0x20) +#define MT6360_PMU_CHG_AICC_RESULT (0x21) +#define MT6360_PMU_DEVICE_TYPE (0x22) +#define MT6360_PMU_QC_CONTROL1 (0x23) +#define MT6360_PMU_QC_CONTROL2 (0x24) +#define MT6360_PMU_QC30_CONTROL1 (0x25) +#define MT6360_PMU_QC30_CONTROL2 (0x26) +#define MT6360_PMU_USB_STATUS1 (0x27) +#define MT6360_PMU_QC_STATUS1 (0x28) +#define MT6360_PMU_QC_STATUS2 (0x29) +#define MT6360_PMU_CHG_PUMP (0x2A) +#define MT6360_PMU_CHG_CTRL17 (0x2B) +#define MT6360_PMU_CHG_CTRL18 (0x2C) +#define MT6360_PMU_CHRDET_CTRL1 (0x2D) +#define MT6360_PMU_CHRDET_CTRL2 (0x2E) +#define MT6360_PMU_DPDN_CTRL (0x2F) +#define MT6360_PMU_CHG_HIDDEN_CTRL1 (0x30) +#define MT6360_PMU_CHG_HIDDEN_CTRL2 (0x31) +#define MT6360_PMU_CHG_HIDDEN_CTRL3 (0x32) +#define MT6360_PMU_CHG_HIDDEN_CTRL4 (0x33) +#define MT6360_PMU_CHG_HIDDEN_CTRL5 (0x34) +#define MT6360_PMU_CHG_HIDDEN_CTRL6 (0x35) +#define MT6360_PMU_CHG_HIDDEN_CTRL7 (0x36) +#define MT6360_PMU_CHG_HIDDEN_CTRL8 (0x37) +#define MT6360_PMU_CHG_HIDDEN_CTRL9 (0x38) +#define MT6360_PMU_CHG_HIDDEN_CTRL10 (0x39) +#define MT6360_PMU_CHG_HIDDEN_CTRL11 (0x3A) +#define MT6360_PMU_CHG_HIDDEN_CTRL12 (0x3B) +#define MT6360_PMU_CHG_HIDDEN_CTRL13 (0x3C) +#define MT6360_PMU_CHG_HIDDEN_CTRL14 (0x3D) +#define MT6360_PMU_CHG_HIDDEN_CTRL15 (0x3E) +#define MT6360_PMU_CHG_HIDDEN_CTRL16 (0x3F) +#define MT6360_PMU_CHG_HIDDEN_CTRL17 (0x40) +#define MT6360_PMU_CHG_HIDDEN_CTRL18 (0x41) +#define MT6360_PMU_CHG_HIDDEN_CTRL19 (0x42) +#define MT6360_PMU_CHG_HIDDEN_CTRL20 (0x43) +#define MT6360_PMU_CHG_HIDDEN_CTRL21 (0x44) +#define MT6360_PMU_CHG_HIDDEN_CTRL22 (0x45) +#define MT6360_PMU_CHG_HIDDEN_CTRL23 (0x46) +#define MT6360_PMU_CHG_HIDDEN_CTRL24 (0x47) +#define MT6360_PMU_CHG_HIDDEN_CTRL25 (0x48) +#define MT6360_PMU_BC12_CTRL (0x49) +#define MT6360_PMU_CHG_STAT (0x4A) +#define MT6360_PMU_RESV1 (0x4B) +#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH (0x4E) +#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL (0x4F) +#define MT6360_PMU_TYPEC_OTP_HYST_TH (0x50) +#define MT6360_PMU_TYPEC_OTP_CTRL (0x51) +#define MT6360_PMU_ADC_BAT_DATA_H (0x52) +#define MT6360_PMU_ADC_BAT_DATA_L (0x53) +#define MT6360_PMU_IMID_BACKBST_ON (0x54) +#define MT6360_PMU_IMID_BACKBST_OFF (0x55) +#define MT6360_PMU_ADC_CONFIG (0x56) +#define MT6360_PMU_ADC_EN2 (0x57) +#define MT6360_PMU_ADC_IDLE_T (0x58) +#define MT6360_PMU_ADC_RPT_1 (0x5A) +#define MT6360_PMU_ADC_RPT_2 (0x5B) +#define MT6360_PMU_ADC_RPT_3 (0x5C) +#define MT6360_PMU_ADC_RPT_ORG1 (0x5D) +#define MT6360_PMU_ADC_RPT_ORG2 (0x5E) +#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH (0x5F) +#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL (0x60) +#define MT6360_PMU_CHG_CTRL19 (0x61) +#define MT6360_PMU_VDDASUPPLY (0x62) +#define MT6360_PMU_BC12_MANUAL (0x63) +#define MT6360_PMU_CHGDET_FUNC (0x64) +#define MT6360_PMU_FOD_CTRL (0x65) +#define MT6360_PMU_CHG_CTRL20 (0x66) +#define MT6360_PMU_CHG_HIDDEN_CTRL26 (0x67) +#define MT6360_PMU_CHG_HIDDEN_CTRL27 (0x68) +#define MT6360_PMU_RESV2 (0x69) +#define MT6360_PMU_USBID_CTRL1 (0x6D) +#define MT6360_PMU_USBID_CTRL2 (0x6E) +#define MT6360_PMU_USBID_CTRL3 (0x6F) +#define MT6360_PMU_FLED_CFG (0x70) +#define MT6360_PMU_RESV3 (0x71) +#define MT6360_PMU_FLED1_CTRL (0x72) +#define MT6360_PMU_FLED_STRB_CTRL (0x73) +#define MT6360_PMU_FLED1_STRB_CTRL2 (0x74) +#define MT6360_PMU_FLED1_TOR_CTRL (0x75) +#define MT6360_PMU_FLED2_CTRL (0x76) +#define MT6360_PMU_RESV4 (0x77) +#define MT6360_PMU_FLED2_STRB_CTRL2 (0x78) +#define MT6360_PMU_FLED2_TOR_CTRL (0x79) +#define MT6360_PMU_FLED_VMIDTRK_CTRL1 (0x7A) +#define MT6360_PMU_FLED_VMID_RTM (0x7B) +#define MT6360_PMU_FLED_VMIDTRK_CTRL2 (0x7C) +#define MT6360_PMU_FLED_PWSEL (0x7D) +#define MT6360_PMU_FLED_EN (0x7E) +#define MT6360_PMU_FLED_Hidden1 (0x7F) +#define MT6360_PMU_RGB_EN (0x80) +#define MT6360_PMU_RGB1_ISNK (0x81) +#define MT6360_PMU_RGB2_ISNK (0x82) +#define MT6360_PMU_RGB3_ISNK (0x83) +#define MT6360_PMU_RGB_ML_ISNK (0x84) +#define MT6360_PMU_RGB1_DIM (0x85) +#define MT6360_PMU_RGB2_DIM (0x86) +#define MT6360_PMU_RGB3_DIM (0x87) +#define MT6360_PMU_RESV5 (0x88) +#define MT6360_PMU_RGB12_Freq (0x89) +#define MT6360_PMU_RGB34_Freq (0x8A) +#define MT6360_PMU_RGB1_Tr (0x8B) +#define MT6360_PMU_RGB1_Tf (0x8C) +#define MT6360_PMU_RGB1_TON_TOFF (0x8D) +#define MT6360_PMU_RGB2_Tr (0x8E) +#define MT6360_PMU_RGB2_Tf (0x8F) +#define MT6360_PMU_RGB2_TON_TOFF (0x90) +#define MT6360_PMU_RGB3_Tr (0x91) +#define MT6360_PMU_RGB3_Tf (0x92) +#define MT6360_PMU_RGB3_TON_TOFF (0x93) +#define MT6360_PMU_RGB_Hidden_CTRL1 (0x94) +#define MT6360_PMU_RGB_Hidden_CTRL2 (0x95) +#define MT6360_PMU_RESV6 (0x97) +#define MT6360_PMU_SPARE1 (0x9A) +#define MT6360_PMU_SPARE2 (0xA0) +#define MT6360_PMU_SPARE3 (0xB0) +#define MT6360_PMU_SPARE4 (0xC0) +#define MT6360_PMU_CHG_IRQ1 (0xD0) +#define MT6360_PMU_CHG_IRQ2 (0xD1) +#define MT6360_PMU_CHG_IRQ3 (0xD2) +#define MT6360_PMU_CHG_IRQ4 (0xD3) +#define MT6360_PMU_CHG_IRQ5 (0xD4) +#define MT6360_PMU_CHG_IRQ6 (0xD5) +#define MT6360_PMU_QC_IRQ (0xD6) +#define MT6360_PMU_FOD_IRQ (0xD7) +#define MT6360_PMU_BASE_IRQ (0xD8) +#define MT6360_PMU_FLED_IRQ1 (0xD9) +#define MT6360_PMU_FLED_IRQ2 (0xDA) +#define MT6360_PMU_RGB_IRQ (0xDB) +#define MT6360_PMU_BUCK1_IRQ (0xDC) +#define MT6360_PMU_BUCK2_IRQ (0xDD) +#define MT6360_PMU_LDO_IRQ1 (0xDE) +#define MT6360_PMU_LDO_IRQ2 (0xDF) +#define MT6360_PMU_CHG_STAT1 (0xE0) +#define MT6360_PMU_CHG_STAT2 (0xE1) +#define MT6360_PMU_CHG_STAT3 (0xE2) +#define MT6360_PMU_CHG_STAT4 (0xE3) +#define MT6360_PMU_CHG_STAT5 (0xE4) +#define MT6360_PMU_CHG_STAT6 (0xE5) +#define MT6360_PMU_QC_STAT (0xE6) +#define MT6360_PMU_FOD_STAT (0xE7) +#define MT6360_PMU_BASE_STAT (0xE8) +#define MT6360_PMU_FLED_STAT1 (0xE9) +#define MT6360_PMU_FLED_STAT2 (0xEA) +#define MT6360_PMU_RGB_STAT (0xEB) +#define MT6360_PMU_BUCK1_STAT (0xEC) +#define MT6360_PMU_BUCK2_STAT (0xED) +#define MT6360_PMU_LDO_STAT1 (0xEE) +#define MT6360_PMU_LDO_STAT2 (0xEF) +#define MT6360_PMU_CHG_MASK1 (0xF0) +#define MT6360_PMU_CHG_MASK2 (0xF1) +#define MT6360_PMU_CHG_MASK3 (0xF2) +#define MT6360_PMU_CHG_MASK4 (0xF3) +#define MT6360_PMU_CHG_MASK5 (0xF4) +#define MT6360_PMU_CHG_MASK6 (0xF5) +#define MT6360_PMU_QC_MASK (0xF6) +#define MT6360_PMU_FOD_MASK (0xF7) +#define MT6360_PMU_BASE_MASK (0xF8) +#define MT6360_PMU_FLED_MASK1 (0xF9) +#define MT6360_PMU_FLED_MASK2 (0xFA) +#define MT6360_PMU_FAULTB_MASK (0xFB) +#define MT6360_PMU_BUCK1_MASK (0xFC) +#define MT6360_PMU_BUCK2_MASK (0xFD) +#define MT6360_PMU_LDO_MASK1 (0xFE) +#define MT6360_PMU_LDO_MASK2 (0xFF) +#define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2) + +/* MT6360_PMU_IRQ_SET */ +#define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - MT6360_PMU_CHG_IRQ1 + 1) +#define MT6360_IRQ_RETRIG BIT(2) + +#define CHIP_VEN_MASK (0xF0) +#define CHIP_VEN_MT6360 (0x50) +#define CHIP_REV_MASK (0x0F) + +#endif /* __MT6360_H__ */ diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h index fc88d315bdde..949268581b36 100644 --- a/include/linux/mfd/mt6397/core.h +++ b/include/linux/mfd/mt6397/core.h @@ -8,9 +8,11 @@ #define __MFD_MT6397_CORE_H__ #include <linux/mutex.h> +#include <linux/notifier.h> enum chip_id { MT6323_CHIP_ID = 0x23, + MT6358_CHIP_ID = 0x58, MT6391_CHIP_ID = 0x91, MT6397_CHIP_ID = 0x97, }; @@ -54,6 +56,7 @@ enum mt6397_irq_numbers { struct mt6397_chip { struct device *dev; struct regmap *regmap; + struct notifier_block pm_nb; int irq; struct irq_domain *irq_domain; struct mutex irqlock; @@ -63,8 +66,10 @@ struct mt6397_chip { u16 int_con[2]; u16 int_status[2]; u16 chip_id; + void *irq_data; }; +int mt6358_irq_init(struct mt6397_chip *chip); int mt6397_irq_init(struct mt6397_chip *chip); #endif /* __MFD_MT6397_CORE_H__ */ diff --git a/include/linux/mfd/mt6397/rtc.h b/include/linux/mfd/mt6397/rtc.h index 7dfb63b81373..66989a16221a 100644 --- a/include/linux/mfd/mt6397/rtc.h +++ b/include/linux/mfd/mt6397/rtc.h @@ -18,7 +18,9 @@ #define RTC_BBPU_CBUSY BIT(6) #define RTC_BBPU_KEY (0x43 << 8) -#define RTC_WRTGR 0x003c +#define RTC_WRTGR_MT6358 0x003a +#define RTC_WRTGR_MT6397 0x003c +#define RTC_WRTGR_MT6323 RTC_WRTGR_MT6397 #define RTC_IRQ_STA 0x0002 #define RTC_IRQ_STA_AL BIT(0) @@ -65,6 +67,10 @@ #define MTK_RTC_POLL_DELAY_US 10 #define MTK_RTC_POLL_TIMEOUT (jiffies_to_usecs(HZ)) +struct mtk_rtc_data { + u32 wrtgr; +}; + struct mt6397_rtc { struct device *dev; struct rtc_device *rtc_dev; @@ -74,6 +80,7 @@ struct mt6397_rtc { struct regmap *regmap; int irq; u32 addr_base; + const struct mtk_rtc_data *data; }; #endif /* _LINUX_MFD_MT6397_RTC_H_ */ diff --git a/include/linux/mfd/stmfx.h b/include/linux/mfd/stmfx.h index 3c67983678ec..744dce63946e 100644 --- a/include/linux/mfd/stmfx.h +++ b/include/linux/mfd/stmfx.h @@ -109,6 +109,7 @@ struct stmfx { struct device *dev; struct regmap *map; struct regulator *vdd; + int irq; struct irq_domain *irq_domain; struct mutex lock; /* IRQ bus lock */ u8 irq_src; |