diff options
299 files changed, 7367 insertions, 2548 deletions
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index f084af0cb8e0..8dd7248508a9 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1974,15 +1974,18 @@ and is between 256 and 4096 characters. It is defined in the file force Enable ASPM even on devices that claim not to support it. WARNING: Forcing ASPM on may cause system lockups. + pcie_ports= [PCIE] PCIe ports handling: + auto Ask the BIOS whether or not to use native PCIe services + associated with PCIe ports (PME, hot-plug, AER). Use + them only if that is allowed by the BIOS. + native Use native PCIe services associated with PCIe ports + unconditionally. + compat Treat PCIe ports as PCI-to-PCI bridges, disable the PCIe + ports driver. + pcie_pme= [PCIE,PM] Native PCIe PME signaling options: - Format: {auto|force}[,nomsi] - auto Use native PCIe PME signaling if the BIOS allows the - kernel to control PCIe config registers of root ports. - force Use native PCIe PME signaling even if the BIOS refuses - to allow the kernel to control the relevant PCIe config - registers. nomsi Do not use MSI for native PCIe PME signaling (this makes - all PCIe root ports use INTx for everything). + all PCIe root ports use INTx for all services). pcmv= [HW,PCMCIA] BadgePAD 4 diff --git a/MAINTAINERS b/MAINTAINERS index c36f5d76e1a2..01b8eef230a0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4604,7 +4604,7 @@ F: include/linux/preempt.h PRISM54 WIRELESS DRIVER M: "Luis R. Rodriguez" <mcgrof@gmail.com> L: linux-wireless@vger.kernel.org -W: http://prism54.org +W: http://wireless.kernel.org/en/users/Drivers/p54 S: Obsolete F: drivers/net/wireless/prism54/ @@ -5234,8 +5234,8 @@ F: drivers/*/*s3c2410* F: drivers/*/*/*s3c2410* TI DAVINCI MACHINE SUPPORT -P: Kevin Hilman -M: davinci-linux-open-source@linux.davincidsp.com +M: Kevin Hilman <khilman@deeprootsystems.com> +L: davinci-linux-open-source@linux.davincidsp.com (subscribers-only) Q: http://patchwork.kernel.org/project/linux-davinci/list/ S: Supported F: arch/arm/mach-davinci diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h index 48837e6d8887..b5799a3b7117 100644 --- a/arch/arm/include/asm/perf_event.h +++ b/arch/arm/include/asm/perf_event.h @@ -17,7 +17,7 @@ * counter interrupts are regular interrupts and not an NMI. This * means that when we receive the interrupt we can call * perf_event_do_pending() that handles all of the work with - * interrupts enabled. + * interrupts disabled. */ static inline void set_perf_event_pending(void) diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index d02cfb683487..c891eb76c0e3 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -393,6 +393,9 @@ #define __NR_perf_event_open (__NR_SYSCALL_BASE+364) #define __NR_recvmmsg (__NR_SYSCALL_BASE+365) #define __NR_accept4 (__NR_SYSCALL_BASE+366) +#define __NR_fanotify_init (__NR_SYSCALL_BASE+367) +#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) +#define __NR_prlimit64 (__NR_SYSCALL_BASE+369) /* * The following SWIs are ARM private. diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index afeb71fa72cb..5c26eccef998 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -376,6 +376,9 @@ CALL(sys_perf_event_open) /* 365 */ CALL(sys_recvmmsg) CALL(sys_accept4) + CALL(sys_fanotify_init) + CALL(sys_fanotify_mark) + CALL(sys_prlimit64) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 417c392ddf1c..e2139256524e 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -1041,8 +1041,8 @@ armv6pmu_handle_irq(int irq_num, /* * Handle the pending perf events. * - * Note: this call *must* be run with interrupts enabled. For - * platforms that can have the PMU interrupts raised as a PMI, this + * Note: this call *must* be run with interrupts disabled. For + * platforms that can have the PMU interrupts raised as an NMI, this * will not work. */ perf_event_do_pending(); @@ -2017,8 +2017,8 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) /* * Handle the pending perf events. * - * Note: this call *must* be run with interrupts enabled. For - * platforms that can have the PMU interrupts raised as a PMI, this + * Note: this call *must* be run with interrupts disabled. For + * platforms that can have the PMU interrupts raised as an NMI, this * will not work. */ perf_event_do_pending(); diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f864748..2bf03e95505f 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -20,23 +20,23 @@ config ARCH_DAVINCI_DM644x select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM355 - bool "DaVinci 355 based system" + bool "DaVinci 355 based system" select AINTC select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM646x - bool "DaVinci 646x based system" + bool "DaVinci 646x based system" select AINTC select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DA830 - bool "DA830/OMAP-L137 based system" + bool "DA830/OMAP-L137/AM17x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 config ARCH_DAVINCI_DA850 - bool "DA850/OMAP-L138 based system" + bool "DA850/OMAP-L138/AM18x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ @@ -115,21 +115,21 @@ config MACH_DAVINCI_DM365_EVM for development is a DM365 EVM config MACH_DAVINCI_DA830_EVM - bool "TI DA830/OMAP-L137 Reference Platform" + bool "TI DA830/OMAP-L137/AM17x Reference Platform" default ARCH_DAVINCI_DA830 depends on ARCH_DAVINCI_DA830 select GPIO_PCF857X help - Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. + Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. choice - prompt "Select DA830/OMAP-L137 UI board peripheral" + prompt "Select DA830/OMAP-L137/AM17x UI board peripheral" depends on MACH_DAVINCI_DA830_EVM help - The presence of UI card on the DA830/OMAP-L137 EVM is detected - automatically based on successful probe of the I2C based GPIO - expander on that board. This option selected in this menu has - an effect only in case of a successful UI card detection. + The presence of UI card on the DA830/OMAP-L137/AM17x EVM is + detected automatically based on successful probe of the I2C + based GPIO expander on that board. This option selected in this + menu has an effect only in case of a successful UI card detection. config DA830_UI_LCD bool "LCD" @@ -140,23 +140,23 @@ config DA830_UI_LCD config DA830_UI_NAND bool "NAND flash" help - Say Y here to use the NAND flash. Do not forget to setup + Say Y here to use the NAND flash. Do not forget to setup the switch correctly. endchoice config MACH_DAVINCI_DA850_EVM - bool "TI DA850/OMAP-L138 Reference Platform" + bool "TI DA850/OMAP-L138/AM18x Reference Platform" default ARCH_DAVINCI_DA850 depends on ARCH_DAVINCI_DA850 select GPIO_PCA953X help - Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. + Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. choice prompt "Select peripherals connected to expander on UI board" depends on MACH_DAVINCI_DA850_EVM help - The presence of User Interface (UI) card on the DA850/OMAP-L138 + The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x EVM is detected automatically based on successful probe of the I2C based GPIO expander on that card. This option selected in this menu has an effect only in case of a successful UI card detection. @@ -165,13 +165,13 @@ config DA850_UI_NONE bool "No peripheral is enabled" help Say Y if you do not want to enable any of the peripherals connected - to TCA6416 expander on DA850/OMAP-L138 EVM UI card + to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card config DA850_UI_RMII bool "RMII Ethernet PHY" help - Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM. - This PHY is found on the UI daughter card that is supplied with + Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x + EVM. This PHY is found on the UI daughter card that is supplied with the EVM. NOTE: Please take care while choosing this option, MII PHY will not be functional if RMII mode is selected. @@ -195,20 +195,20 @@ config DAVINCI_MUX say Y. config DAVINCI_MUX_DEBUG - bool "Multiplexing debug output" - depends on DAVINCI_MUX - help - Makes the multiplexing functions print out a lot of debug info. - This is useful if you want to find out the correct values of the - multiplexing registers. + bool "Multiplexing debug output" + depends on DAVINCI_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. config DAVINCI_MUX_WARNINGS - bool "Warn about pins the bootloader didn't set up" - depends on DAVINCI_MUX - help - Choose Y here to warn whenever driver initialization logic needs - to change the pin multiplexing setup. When there are no warnings - printed, it's safe to deselect DAVINCI_MUX for your product. + bool "Warn about pins the bootloader didn't set up" + depends on DAVINCI_MUX + help + Choose Y here to warn whenever driver initialization logic needs + to change the pin multiplexing setup. When there are no warnings + printed, it's safe to deselect DAVINCI_MUX for your product. config DAVINCI_RESET_CLOCKS bool "Reset unused clocks during boot" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0fd667a..77a0f71b2aa2 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,7 +5,7 @@ # Common objects obj-y := time.o clock.o serial.o io.o psc.o \ - gpio.o dma.o usb.o common.o sram.o + gpio.o dma.o usb.o common.o sram.o aemif.o obj-$(CONFIG_DAVINCI_MUX) += mux.o diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c new file mode 100644 index 000000000000..9c3f500fc12f --- /dev/null +++ b/arch/arm/mach-davinci/aemif.c @@ -0,0 +1,133 @@ +/* + * AEMIF support for DaVinci SoCs + * + * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/time.h> + +#include <mach/aemif.h> + +/* Timing value configuration */ + +#define TA(x) ((x) << 2) +#define RHOLD(x) ((x) << 4) +#define RSTROBE(x) ((x) << 7) +#define RSETUP(x) ((x) << 13) +#define WHOLD(x) ((x) << 17) +#define WSTROBE(x) ((x) << 20) +#define WSETUP(x) ((x) << 26) + +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX 0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX 0x3f +#define WSETUP_MAX 0xf + +#define TIMING_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +/* + * aemif_calc_rate - calculate timing data. + * @wanted: The cycle time needed in nanoseconds. + * @clk: The input clock rate in kHz. + * @max: The maximum divider value that can be programmed. + * + * On success, returns the calculated timing value minus 1 for easy + * programming into AEMIF timing registers, else negative errno. + */ +static int aemif_calc_rate(int wanted, unsigned long clk, int max) +{ + int result; + + result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1; + + pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted); + + /* It is generally OK to have a more relaxed timing than requested... */ + if (result < 0) + result = 0; + + /* ... But configuring tighter timings is not an option. */ + else if (result > max) + result = -EINVAL; + + return result; +} + +/** + * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface + * @t: timing values to be progammed + * @base: The virtual base address of the AEMIF interface + * @cs: chip-select to program the timing values for + * + * This function programs the given timing values (in real clock) into the + * AEMIF registers taking the AEMIF clock into account. + * + * This function does not use any locking while programming the AEMIF + * because it is expected that there is only one user of a given + * chip-select. + * + * Returns 0 on success, else negative errno. + */ +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs) +{ + unsigned set, val; + unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; + unsigned offset = A1CR_OFFSET + cs * 4; + struct clk *aemif_clk; + unsigned long clkrate; + + if (!t) + return 0; /* Nothing to do */ + + aemif_clk = clk_get(NULL, "aemif"); + if (IS_ERR(aemif_clk)) + return PTR_ERR(aemif_clk); + + clkrate = clk_get_rate(aemif_clk); + + clkrate /= 1000; /* turn clock into kHz for ease of use */ + + ta = aemif_calc_rate(t->ta, clkrate, TA_MAX); + rhold = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX); + rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX); + rsetup = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX); + whold = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX); + wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX); + wsetup = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX); + + if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || + whold < 0 || wstrobe < 0 || wsetup < 0) { + pr_err("%s: cannot get suitable timings\n", __func__); + return -EINVAL; + } + + set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | + WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + + val = __raw_readl(base + offset); + val &= ~TIMING_MASK; + val |= set; + __raw_writel(val, base + offset); + + return 0; +} +EXPORT_SYMBOL(davinci_aemif_setup_timing); diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index c3994f341e49..de82739c00ec 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -29,6 +29,7 @@ #include <mach/nand.h> #include <mach/da8xx.h> #include <mach/usb.h> +#include <mach/aemif.h> #define DA830_EVM_PHY_MASK 0x0 #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ @@ -360,6 +361,16 @@ static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = { .pattern = da830_evm_nand_mirror_pattern }; +static struct davinci_aemif_timing da830_evm_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + static struct davinci_nand_pdata da830_evm_nand_pdata = { .parts = da830_evm_nand_partitions, .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), @@ -368,6 +379,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = { .options = NAND_USE_FLASH_BBT, .bbt_td = &da830_evm_nand_bbt_main_descr, .bbt_md = &da830_evm_nand_bbt_mirror_descr, + .timing = &da830_evm_nandflash_timing, }; static struct resource da830_evm_nand_resources[] = { @@ -596,7 +608,7 @@ static void __init da830_evm_map_io(void) da830_init(); } -MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM") +MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index fdc2cc500fc6..c1d45d7ac45b 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -36,6 +36,7 @@ #include <mach/da8xx.h> #include <mach/nand.h> #include <mach/mux.h> +#include <mach/aemif.h> #define DA850_EVM_PHY_MASK 0x1 #define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ @@ -110,7 +111,7 @@ static struct platform_device da850_pm_device = { * to boot, using TI's tools to install the secondary boot loader * (UBL) and U-Boot. */ -struct mtd_partition da850_evm_nandflash_partition[] = { +static struct mtd_partition da850_evm_nandflash_partition[] = { { .name = "u-boot env", .offset = 0, @@ -143,12 +144,23 @@ struct mtd_partition da850_evm_nandflash_partition[] = { }, }; +static struct davinci_aemif_timing da850_evm_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + static struct davinci_nand_pdata da850_evm_nandflash_data = { .parts = da850_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, .ecc_bits = 4, .options = NAND_USE_FLASH_BBT, + .timing = &da850_evm_nandflash_timing, }; static struct resource da850_evm_nandflash_resource[] = { @@ -196,6 +208,30 @@ static void __init da850_evm_init_nor(void) iounmap(aemif_addr); } +static const short da850_evm_nand_pins[] = { + DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, + DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, + DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, + DA850_NEMA_WE, DA850_NEMA_OE, + -1 +}; + +static const short da850_evm_nor_pins[] = { + DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, + DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, + DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, + DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, + DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, + DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, + DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, + DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, + DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, + DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, + DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, + DA850_EMA_A_22, DA850_EMA_A_23, + -1 +}; + static u32 ui_card_detected; #if defined(CONFIG_MMC_DAVINCI) || \ @@ -205,17 +241,17 @@ static u32 ui_card_detected; #define HAS_MMC 0 #endif -static __init void da850_evm_setup_nor_nand(void) +static inline void da850_evm_setup_nor_nand(void) { int ret = 0; if (ui_card_detected & !HAS_MMC) { - ret = davinci_cfg_reg_list(da850_nand_pins); + ret = davinci_cfg_reg_list(da850_evm_nand_pins); if (ret) pr_warning("da850_evm_init: nand mux setup failed: " "%d\n", ret); - ret = davinci_cfg_reg_list(da850_nor_pins); + ret = davinci_cfg_reg_list(da850_evm_nor_pins); if (ret) pr_warning("da850_evm_init: nor mux setup failed: %d\n", ret); @@ -406,7 +442,7 @@ static int da850_lcd_hw_init(void) /* TPS65070 voltage regulator support */ /* 3.3V */ -struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { { .supply = "usb0_vdda33", }, @@ -416,7 +452,7 @@ struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { }; /* 3.3V or 1.8V */ -struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { { .supply = "dvdd3318_a", }, @@ -429,14 +465,14 @@ struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { }; /* 1.2V */ -struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { { .supply = "cvdd", }, }; /* 1.8V LDO */ -struct regulator_consumer_supply tps65070_ldo1_consumers[] = { +static struct regulator_consumer_supply tps65070_ldo1_consumers[] = { { .supply = "sata_vddr", }, @@ -452,7 +488,7 @@ struct regulator_consumer_supply tps65070_ldo1_consumers[] = { }; /* 1.2V LDO */ -struct regulator_consumer_supply tps65070_ldo2_consumers[] = { +static struct regulator_consumer_supply tps65070_ldo2_consumers[] = { { .supply = "sata_vdd", }, @@ -475,7 +511,7 @@ static struct tps6507x_reg_platform_data tps6507x_platform_data = { .defdcdc_default = true, }; -struct regulator_init_data tps65070_regulator_data[] = { +static struct regulator_init_data tps65070_regulator_data[] = { /* dcdc1 */ { .constraints = { @@ -576,6 +612,23 @@ static const short da850_evm_lcdc_pins[] = { -1 }; +static const short da850_evm_mii_pins[] = { + DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, + DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, + DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, + DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +static const short da850_evm_rmii_pins[] = { + DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, + DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, + DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + static int __init da850_evm_config_emac(void) { void __iomem *cfg_chip3_base; @@ -593,12 +646,12 @@ static int __init da850_evm_config_emac(void) if (rmii_en) { val |= BIT(8); - ret = davinci_cfg_reg_list(da850_rmii_pins); + ret = davinci_cfg_reg_list(da850_evm_rmii_pins); pr_info("EMAC: RMII PHY configured, MII PHY will not be" " functional\n"); } else { val &= ~BIT(8); - ret = davinci_cfg_reg_list(da850_cpgmac_pins); + ret = davinci_cfg_reg_list(da850_evm_mii_pins); pr_info("EMAC: MII PHY configured, RMII PHY will not be" " functional\n"); } @@ -787,7 +840,7 @@ static __init void da850_evm_init(void) if (ret) pr_warning("da850_evm_init: rtc setup failed: %d\n", ret); - ret = da850_register_cpufreq(); + ret = da850_register_cpufreq("pll0_sysclk3"); if (ret) pr_warning("da850_evm_init: cpufreq registration failed: %d\n", ret); @@ -816,7 +869,7 @@ static void __init da850_evm_map_io(void) da850_init(); } -MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") +MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 84acef1d0b3d..bdea2da0b203 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -175,7 +175,9 @@ static struct at24_platform_data eeprom_info = { .context = (void *)0x7f00, }; -static struct snd_platform_data dm365_evm_snd_data; +static struct snd_platform_data dm365_evm_snd_data = { + .asp_chan_q = EVENTQ_3, +}; static struct i2c_board_info i2c_info[] = { { diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 34c8b418cd72..65bb94064feb 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -37,6 +37,7 @@ #include <mach/nand.h> #include <mach/mmc.h> #include <mach/usb.h> +#include <mach/aemif.h> #define DM644X_EVM_PHY_MASK (0x2) #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ @@ -137,11 +138,22 @@ static struct mtd_partition davinci_evm_nandflash_partition[] = { */ }; +static struct davinci_aemif_timing davinci_evm_nandflash_timing = { + .wsetup = 20, + .wstrobe = 40, + .whold = 20, + .rsetup = 10, + .rstrobe = 40, + .rhold = 10, + .ta = 40, +}; + static struct davinci_nand_pdata davinci_evm_nandflash_data = { .parts = davinci_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, .options = NAND_USE_FLASH_BBT, + .timing = &davinci_evm_nandflash_timing, }; static struct resource davinci_evm_nandflash_resource[] = { diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 4502f346b2b0..5a29955b2f5c 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -42,6 +42,7 @@ #include <mach/nand.h> #include <mach/clock.h> #include <mach/cdce949.h> +#include <mach/aemif.h> #include "clock.h" @@ -71,6 +72,16 @@ static struct mtd_partition davinci_nand_partitions[] = { } }; +static struct davinci_aemif_timing dm6467tevm_nandflash_timing = { + .wsetup = 29, + .wstrobe = 24, + .whold = 14, + .rsetup = 19, + .rstrobe = 33, + .rhold = 0, + .ta = 29, +}; + static struct davinci_nand_pdata davinci_nand_data = { .mask_cle = 0x80000, .mask_ale = 0x40000, @@ -763,6 +774,9 @@ static __init void evm_init(void) dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); + if (machine_is_davinci_dm6467tevm()) + davinci_nand_data.timing = &dm6467tevm_nandflash_timing; + platform_device_register(&davinci_nand_device); dm646x_init_edma(dm646x_edma_rsv); diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 054c303caead..01ba080433db 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -236,7 +236,7 @@ static int __init clk_disable_unused(void) if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) continue; - pr_info("Clocks: disable unused %s\n", ck->name); + pr_debug("Clocks: disable unused %s\n", ck->name); davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, (ck->flags & PSC_SWRSTDISABLE) ? @@ -287,6 +287,79 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) return rate; } +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) +{ + unsigned v; + struct pll_data *pll; + unsigned long input; + unsigned ratio = 0; + + /* If this is the PLL base clock, wrong function to call */ + if (clk->pll_data) + return -EINVAL; + + /* There must be a parent... */ + if (WARN_ON(!clk->parent)) + return -EINVAL; + + /* ... the parent must be a PLL... */ + if (WARN_ON(!clk->parent->pll_data)) + return -EINVAL; + + /* ... and this clock must have a divider. */ + if (WARN_ON(!clk->div_reg)) + return -EINVAL; + + pll = clk->parent->pll_data; + + input = clk->parent->rate; + + /* If pre-PLL, source clock is before the multiplier and divider(s) */ + if (clk->flags & PRE_PLL) + input = pll->input_rate; + + if (input > rate) { + /* + * Can afford to provide an output little higher than requested + * only if maximum rate supported by hardware on this sysclk + * is known. + */ + if (clk->maxrate) { + ratio = DIV_ROUND_CLOSEST(input, rate); + if (input / ratio > clk->maxrate) + ratio = 0; + } + + if (ratio == 0) + ratio = DIV_ROUND_UP(input, rate); + + ratio--; + } + + if (ratio > PLLDIV_RATIO_MASK) + return -EINVAL; + + do { + v = __raw_readl(pll->base + PLLSTAT); + } while (v & PLLSTAT_GOSTAT); + + v = __raw_readl(pll->base + clk->div_reg); + v &= ~PLLDIV_RATIO_MASK; + v |= ratio | PLLDIV_EN; + __raw_writel(v, pll->base + clk->div_reg); + + v = __raw_readl(pll->base + PLLCMD); + v |= PLLCMD_GOSET; + __raw_writel(v, pll->base + PLLCMD); + + do { + v = __raw_readl(pll->base + PLLSTAT); + } while (v & PLLSTAT_GOSTAT); + + return 0; +} +EXPORT_SYMBOL(davinci_set_sysclk_rate); + static unsigned long clk_leafclk_recalc(struct clk *clk) { if (WARN_ON(!clk->parent)) diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 01e36483ac3d..11099980b58b 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -70,6 +70,9 @@ #include <linux/list.h> #include <asm/clkdev.h> +#define PLLSTAT_GOSTAT BIT(0) +#define PLLCMD_GOSET BIT(0) + struct pll_data { u32 phys_base; void __iomem *base; @@ -86,6 +89,7 @@ struct clk { struct module *owner; const char *name; unsigned long rate; + unsigned long maxrate; /* H/W supported max rate */ u8 usecount; u8 lpsc; u8 gpsc; @@ -118,6 +122,7 @@ struct clk { int davinci_clk_init(struct clk_lookup *clocks); int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv); +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index d3fa6de1e20f..343de73161fa 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -34,6 +34,8 @@ struct davinci_cpufreq { struct device *dev; struct clk *armclk; + struct clk *asyncclk; + unsigned long asyncrate; }; static struct davinci_cpufreq cpufreq; @@ -104,15 +106,27 @@ static int davinci_target(struct cpufreq_policy *policy, cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); /* if moving to higher frequency, up the voltage beforehand */ - if (pdata->set_voltage && freqs.new > freqs.old) - pdata->set_voltage(idx); + if (pdata->set_voltage && freqs.new > freqs.old) { + ret = pdata->set_voltage(idx); + if (ret) + goto out; + } ret = clk_set_rate(armclk, idx); + if (ret) + goto out; + + if (cpufreq.asyncclk) { + ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate); + if (ret) + goto out; + } /* if moving to lower freq, lower the voltage after lowering freq */ if (pdata->set_voltage && freqs.new < freqs.old) pdata->set_voltage(idx); +out: cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); return ret; @@ -185,6 +199,7 @@ static struct cpufreq_driver davinci_driver = { static int __init davinci_cpufreq_probe(struct platform_device *pdev) { struct davinci_cpufreq_config *pdata = pdev->dev.platform_data; + struct clk *asyncclk; if (!pdata) return -EINVAL; @@ -199,6 +214,12 @@ static int __init davinci_cpufreq_probe(struct platform_device *pdev) return PTR_ERR(cpufreq.armclk); } + asyncclk = clk_get(cpufreq.dev, "async"); + if (!IS_ERR(asyncclk)) { + cpufreq.asyncclk = asyncclk; + cpufreq.asyncrate = clk_get_rate(asyncclk); + } + return cpufreq_register_driver(&davinci_driver); } @@ -206,6 +227,9 @@ static int __exit davinci_cpufreq_remove(struct platform_device *pdev) { clk_put(cpufreq.armclk); + if (cpufreq.asyncclk) + clk_put(cpufreq.asyncclk); + return cpufreq_unregister_driver(&davinci_driver); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 68ed58a48252..63916b902760 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -86,6 +86,8 @@ static struct clk pll0_sysclk3 = { .parent = &pll0_clk, .flags = CLK_PLL, .div_reg = PLLDIV3, + .set_rate = davinci_set_sysclk_rate, + .maxrate = 100000000, }; static struct clk pll0_sysclk4 = { @@ -323,12 +325,19 @@ static struct clk lcdc_clk = { .gpsc = 1, }; -static struct clk mmcsd_clk = { - .name = "mmcsd", +static struct clk mmcsd0_clk = { + .name = "mmcsd0", .parent = &pll0_sysclk2, .lpsc = DA8XX_LPSC0_MMC_SD, }; +static struct clk mmcsd1_clk = { + .name = "mmcsd1", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_MMC_SD1, + .gpsc = 1, +}; + static struct clk aemif_clk = { .name = "aemif", .parent = &pll0_sysclk3, @@ -375,7 +384,8 @@ static struct clk_lookup da850_clks[] = { CLK("davinci_emac.1", NULL, &emac_clk), CLK("davinci-mcasp.0", NULL, &mcasp_clk), CLK("da8xx_lcdc.0", NULL, &lcdc_clk), - CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK("davinci_mmc.0", NULL, &mmcsd0_clk), + CLK("davinci_mmc.1", NULL, &mmcsd1_clk), CLK(NULL, "aemif", &aemif_clk), CLK(NULL, NULL, NULL), }; @@ -572,15 +582,9 @@ const short da850_cpgmac_pins[] __initdata = { DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -const short da850_rmii_pins[] __initdata = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, + DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, + DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER, + DA850_RMII_MHZ_50_CLK, -1 }; @@ -607,27 +611,19 @@ const short da850_mmcsd0_pins[] __initdata = { -1 }; -const short da850_nand_pins[] __initdata = { - DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4, - DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0, - DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, - DA850_NEMA_WE, DA850_NEMA_OE, - -1 -}; - -const short da850_nor_pins[] __initdata = { +const short da850_emif25_pins[] __initdata = { DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, - DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, - DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, - DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, - DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, - DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, - DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, - DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, - DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, - DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, - DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, - DA850_EMA_A_22, DA850_EMA_A_23, + DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE, + DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, + DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, + DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, + DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, + DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3, + DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7, + DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11, + DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15, + DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19, + DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23, -1 }; @@ -851,7 +847,7 @@ static const struct da850_opp da850_opp_300 = { .prediv = 1, .mult = 25, .postdiv = 2, - .cvdd_min = 1140000, + .cvdd_min = 1200000, .cvdd_max = 1320000, }; @@ -860,7 +856,7 @@ static const struct da850_opp da850_opp_200 = { .prediv = 1, .mult = 25, .postdiv = 3, - .cvdd_min = 1050000, + .cvdd_min = 1100000, .cvdd_max = 1160000, }; @@ -869,7 +865,7 @@ static const struct da850_opp da850_opp_96 = { .prediv = 1, .mult = 20, .postdiv = 5, - .cvdd_min = 950000, + .cvdd_min = 1000000, .cvdd_max = 1050000, }; @@ -929,10 +925,16 @@ static struct platform_device da850_cpufreq_device = { .dev = { .platform_data = &cpufreq_info, }, + .id = -1, }; -int __init da850_register_cpufreq(void) +int __init da850_register_cpufreq(char *async_clk) { + /* cpufreq driver can help keep an "async" clock constant */ + if (async_clk) + clk_add_alias("async", da850_cpufreq_device.name, + async_clk, NULL); + return platform_device_register(&da850_cpufreq_device); } @@ -983,7 +985,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index) return 0; } #else -int __init da850_register_cpufreq(void) +int __init da850_register_cpufreq(char *async_clk) { return 0; } diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 52bc7b1c6ca3..caeb7f4a3a6d 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -24,6 +24,7 @@ #include "clock.h" #define DA8XX_TPCC_BASE 0x01c00000 +#define DA850_MMCSD1_BASE 0x01e1b000 #define DA850_TPCC1_BASE 0x01e30000 #define DA8XX_TPTC0_BASE 0x01c08000 #define DA8XX_TPTC1_BASE 0x01c08400 @@ -566,6 +567,44 @@ int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) return platform_device_register(&da8xx_mmcsd0_device); } +#ifdef CONFIG_ARCH_DAVINCI_DA850 +static struct resource da850_mmcsd1_resources[] = { + { /* registers */ + .start = DA850_MMCSD1_BASE, + .end = DA850_MMCSD1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* interrupt */ + .start = IRQ_DA850_MMCSDINT0_1, + .end = IRQ_DA850_MMCSDINT0_1, + .flags = IORESOURCE_IRQ, + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(1, 28), + .end = EDMA_CTLR_CHAN(1, 28), + .flags = IORESOURCE_DMA, + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(1, 29), + .end = EDMA_CTLR_CHAN(1, 29), + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da850_mmcsd1_device = { + .name = "davinci_mmc", + .id = 1, + .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), + .resource = da850_mmcsd1_resources, +}; + +int __init da850_register_mmcsd1(struct davinci_mmc_config *config) +{ + da850_mmcsd1_device.dev.platform_data = config; + return platform_device_register(&da850_mmcsd1_device); +} +#endif + static struct resource da8xx_rtc_resources[] = { { .start = DA8XX_RTC_BASE, diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 8b7201e4c79c..2a9a252327d8 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -213,7 +213,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); /* Configure pull down control */ - __raw_writel((__raw_readl(pupdctl1) & ~0x400), + __raw_writel((__raw_readl(pupdctl1) & ~0xfc0), pupdctl1); mmcsd1_resources[0].start = DM365_MMCSD1_BASE; diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 2ede598b77dd..6b9669869c46 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -354,10 +354,12 @@ static int irq2ctlr(int irq) static irqreturn_t dma_irq_handler(int irq, void *data) { int i; - unsigned ctlr; + int ctlr; unsigned int cnt = 0; ctlr = irq2ctlr(irq); + if (ctlr < 0) + return IRQ_NONE; dev_dbg(data, "dma_irq_handler\n"); @@ -408,10 +410,12 @@ static irqreturn_t dma_irq_handler(int irq, void *data) static irqreturn_t dma_ccerr_handler(int irq, void *data) { int i; - unsigned ctlr; + int ctlr; unsigned int cnt = 0; ctlr = irq2ctlr(irq); + if (ctlr < 0) + return IRQ_NONE; dev_dbg(data, "dma_ccerr_handler\n"); diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h new file mode 100644 index 000000000000..05b293443097 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/aemif.h @@ -0,0 +1,36 @@ +/* + * TI DaVinci AEMIF support + * + * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef _MACH_DAVINCI_AEMIF_H +#define _MACH_DAVINCI_AEMIF_H + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET 0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASK BIT(30) +#define ACR_SS_MASK BIT(31) + +/* All timings in nanoseconds */ +struct davinci_aemif_timing { + u8 wsetup; + u8 wstrobe; + u8 whold; + + u8 rsetup; + u8 rstrobe; + u8 rhold; + + u8 ta; +}; + +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs); +#endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 3c07059f526e..4247b3f53b33 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -76,9 +76,10 @@ int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); int da8xx_register_emac(void); int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); int da8xx_register_mmcsd0(struct davinci_mmc_config *config); +int da850_register_mmcsd1(struct davinci_mmc_config *config); void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); -int da850_register_cpufreq(void); +int da850_register_cpufreq(char *async_clk); int da8xx_register_cpuidle(void); void __iomem * __init da8xx_get_mem_ctlr(void); int da850_register_pm(struct platform_device *pdev); @@ -121,11 +122,9 @@ extern const short da850_uart2_pins[]; extern const short da850_i2c0_pins[]; extern const short da850_i2c1_pins[]; extern const short da850_cpgmac_pins[]; -extern const short da850_rmii_pins[]; extern const short da850_mcasp_pins[]; extern const short da850_lcdcntl_pins[]; extern const short da850_mmcsd0_pins[]; -extern const short da850_nand_pins[]; -extern const short da850_nor_pins[]; +extern const short da850_emif25_pins[]; #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index b2ad8090bd10..025151049f05 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -30,9 +30,6 @@ #include <linux/mtd/nand.h> -#define NRCSR_OFFSET 0x00 -#define AWCCR_OFFSET 0x04 -#define A1CR_OFFSET 0x10 #define NANDFCR_OFFSET 0x60 #define NANDFSR_OFFSET 0x64 #define NANDF1ECC_OFFSET 0x70 @@ -83,6 +80,9 @@ struct davinci_nand_pdata { /* platform_data */ /* Main and mirror bbt descriptor overrides */ struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; + + /* Access timings */ + struct davinci_aemif_timing *timing; }; #endif /* __ARCH_ARM_DAVINCI_NAND_H */ diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 983da6e4554c..62b0858f68ca 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -172,6 +172,7 @@ #define DA8XX_LPSC1_UART2 13 #define DA8XX_LPSC1_LCDC 16 #define DA8XX_LPSC1_PWM 17 +#define DA850_LPSC1_MMC_SD1 18 #define DA8XX_LPSC1_ECAP 20 #define DA830_LPSC1_EQEP 21 #define DA850_LPSC1_TPTC2 21 diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index 864e60482c53..06d2ac9dcf3d 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -104,7 +104,7 @@ static u32 pll_ext_freq[] = { }; /* PSC control registers */ -static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE }; +static u32 psc_regs[] = { TNETV107X_PSC_BASE }; /* Host map for interrupt controller */ static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c5c0369bb481..19ed16d0017e 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -163,6 +163,15 @@ config MACH_MX27_3DS Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. +config MACH_IMX27_VISSTRIM_M10 + bool "Vista Silicon i.MX27 Visstrim_m10" + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for Visstrim_m10 platform and its different variants. + This includes specific configurations for the board and its + peripherals. + config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" select IMX_HAVE_PLATFORM_IMX_UART diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 46a9fdfbbd15..5582692bb176 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o +obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_PCA100) += mach-pca100.o diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c new file mode 100644 index 000000000000..6dad632b83d6 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -0,0 +1,263 @@ +/* + * mach-imx27_visstrim_m10.c + * + * Copyright 2010 Javier Martin <javier.martin@vista-silicon.com> + * + * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/i2c.h> +#include <linux/i2c/pca953x.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <mach/common.h> +#include <mach/mmc.h> +#include <mach/iomux.h> +#include <mach/mxc_ehci.h> + +#include "devices-imx27.h" +#include "devices.h" + +#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) +#define SDHC1_IRQ IRQ_GPIOB(25) + +static int visstrim_m10_pins[] = { + /* UART1 (console) */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + /* SDHC1 */ + PE18_PF_SD1_D0, + PE19_PF_SD1_D1, + PE20_PF_SD1_D2, + PE21_PF_SD1_D3, + PE22_PF_SD1_CMD, + PE23_PF_SD1_CLK, + /* Both I2Cs */ + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, + PC5_PF_I2C2_SDA, + PC6_PF_I2C2_SCL, + /* USB OTG */ + OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, + PC9_PF_USBOTG_DATA0, + PC11_PF_USBOTG_DATA1, + PC10_PF_USBOTG_DATA2, + PC13_PF_USBOTG_DATA3, + PC12_PF_USBOTG_DATA4, + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PE25_PF_USBOTG_DATA7, + PE24_PF_USBOTG_CLK, + PE2_PF_USBOTG_DIR, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PB23_PF_USB_PWR, + PB24_PF_USB_OC, +}; + +/* GPIOs used as events for applications */ +static struct gpio_keys_button visstrim_gpio_keys[] = { + { + .type = EV_KEY, + .code = KEY_RESTART, + .gpio = (GPIO_PORTC + 15), + .desc = "Default config", + .active_low = 0, + .wakeup = 1, + }, + { + .type = EV_KEY, + .code = KEY_RECORD, + .gpio = (GPIO_PORTF + 14), + .desc = "Record", + .active_low = 0, + .wakeup = 1, + }, + { + .type = EV_KEY, + .code = KEY_STOP, + .gpio = (GPIO_PORTF + 13), + .desc = "Stop", + .active_low = 0, + .wakeup = 1, + } +}; + +static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = { + .buttons = visstrim_gpio_keys, + .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), +}; + +static struct platform_device visstrim_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &visstrim_gpio_keys_platform_data, + }, +}; + +/* Visstrim_SM10 has a microSD slot connected to sdhc1 */ +static int visstrim_m10_sdhc1_init(struct device *dev, + irq_handler_t detect_irq, void *data) +{ + int ret; + + ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING, + "mmc-detect", data); + return ret; +} + +static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) +{ + free_irq(SDHC1_IRQ, data); +} + +static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = { + .init = visstrim_m10_sdhc1_init, + .exit = visstrim_m10_sdhc1_exit, +}; + +/* Visstrim_SM10 NOR flash */ +static struct physmap_flash_data visstrim_m10_flash_data = { + .width = 2, +}; + +static struct resource visstrim_m10_flash_resource = { + .start = 0xc0000000, + .end = 0xc0000000 + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device visstrim_m10_nor_mtd_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &visstrim_m10_flash_data, + }, + .num_resources = 1, + .resource = &visstrim_m10_flash_resource, +}; + +static struct platform_device *platform_devices[] __initdata = { + &visstrim_gpio_keys_device, + &visstrim_m10_nor_mtd_device, + &mxc_fec_device, +}; + +/* Visstrim_M10 uses UART0 as console */ +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +/* I2C */ +static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = { + .bitrate = 100000, +}; + +static struct pca953x_platform_data visstrim_m10_pca9555_pdata = { + .gpio_base = 240, /* After MX27 internal GPIOs */ + .invert = 0, +}; + +static struct i2c_board_info visstrim_m10_i2c_devices[] = { + { + I2C_BOARD_INFO("pca9555", 0x20), + .platform_data = &visstrim_m10_pca9555_pdata, + }, +}; + +/* USB OTG */ +static int otg_phy_init(struct platform_device *pdev) +{ + gpio_set_value(OTG_PHY_CS_GPIO, 0); + return 0; +} + +static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = { + .init = otg_phy_init, + .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; + +static void __init visstrim_m10_board_init(void) +{ + int ret; + + ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins, + ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10"); + if (ret) + pr_err("Failed to setup pins (%d)\n", ret); + + imx27_add_imx_uart0(&uart_pdata); + + i2c_register_board_info(0, visstrim_m10_i2c_devices, + ARRAY_SIZE(visstrim_m10_i2c_devices)); + imx27_add_i2c_imx0(&visstrim_m10_i2c_data); + imx27_add_i2c_imx1(&visstrim_m10_i2c_data); + mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata); + mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} + +static void __init visstrim_m10_timer_init(void) +{ + mx27_clocks_init((unsigned long)25000000); +} + +static struct sys_timer visstrim_m10_timer = { + .init = visstrim_m10_timer_init, +}; + +MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_irq = mx27_init_irq, + .init_machine = visstrim_m10_board_init, + .timer = &visstrim_m10_timer, +MACHINE_END diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 85beece802aa..5cee1a5c4bd2 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -9,6 +9,7 @@ config ARCH_MX35 bool select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 + select HAVE_EPIT comment "MX3 platforms:" @@ -140,6 +141,7 @@ config MACH_MX35_3DS bool "Support MX35PDK platform" select ARCH_MX35 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND default n help Include support for MX35PDK platform. This includes specific diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index d3af0fdf8475..ff0de316f9e0 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -343,8 +343,8 @@ DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL); DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL); DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL); DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL); -DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL); -DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL); +DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg, NULL); +DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg, NULL); DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL); DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL); DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL); @@ -435,8 +435,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "ect", ect_clk) _REGISTER_CLOCK(NULL, "edio", edio_clk) _REGISTER_CLOCK(NULL, "emi", emi_clk) - _REGISTER_CLOCK(NULL, "epit", epit1_clk) - _REGISTER_CLOCK(NULL, "epit", epit2_clk) + _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk) + _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk) _REGISTER_CLOCK(NULL, "esai", esai_clk) _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk) _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk) @@ -502,8 +502,13 @@ int __init mx35_clocks_init() __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); __raw_writel(0, CCM_BASE + CCM_CGR3); +#ifdef CONFIG_MXC_USE_EPIT + epit_timer_init(&epit1_clk, + MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); +#else mxc_timer_init(&gpt_clk, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); +#endif return 0; } diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index 1c30d7212f17..1dd7baae4507 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -1,5 +1,6 @@ /* * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix * * Author: Fabio Estevam <fabio.estevam@freescale.com> * @@ -27,6 +28,8 @@ #include <linux/gpio.h> #include <linux/fsl_devices.h> +#include <linux/mtd/physmap.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> @@ -35,6 +38,7 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/iomux-mx35.h> +#include <mach/mxc_ehci.h> #include "devices-imx35.h" #include "devices.h" @@ -43,8 +47,35 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static struct physmap_flash_data mx35pdk_flash_data = { + .width = 2, +}; + +static struct resource mx35pdk_flash_resource = { + .start = MX35_CS0_BASE_ADDR, + .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device mx35pdk_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &mx35pdk_flash_data, + }, + .resource = &mx35pdk_flash_resource, + .num_resources = 1, +}; + +static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + static struct platform_device *devices[] __initdata = { &mxc_fec_device, + &mx35pdk_flash, }; static struct pad_desc mx35pdk_pads[] = { @@ -75,14 +106,24 @@ static struct pad_desc mx35pdk_pads[] = { /* USBOTG */ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, + /* USBH1 */ + MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, + MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, }; /* OTG config */ -static struct fsl_usb2_platform_data usb_pdata = { +static struct fsl_usb2_platform_data usb_otg_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; +/* USB HOST config */ +static struct mxc_usbh_platform_data usb_host_pdata = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | + MXC_EHCI_INTERNAL_PHY, +}; + /* * Board specific initialization. */ @@ -94,7 +135,11 @@ static void __init mxc_board_init(void) imx35_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata); + + mxc_register_device(&mxc_usbh1, &usb_host_pdata); + + imx35_add_mxc_nand(&mx35pdk_nand_board_info); } static void __init mx35pdk_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 6e384d92e625..10d2f6bde172 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -17,6 +17,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/fsl_devices.h> +#include <linux/fec.h> #include <mach/common.h> #include <mach/hardware.h> @@ -35,7 +36,8 @@ #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ -#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */ +#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ +#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ /* USB_CTRL_1 */ #define MX51_USB_CTRL_1_OFFSET 0x10 @@ -93,6 +95,28 @@ static struct pad_desc mx51babbage_pads[] = { /* USB HUB reset line*/ MX51_PAD_GPIO_1_7__GPIO_1_7, + + /* FEC */ + MX51_PAD_EIM_EB2__FEC_MDIO, + MX51_PAD_EIM_EB3__FEC_RDAT1, + MX51_PAD_EIM_CS2__FEC_RDAT2, + MX51_PAD_EIM_CS3__FEC_RDAT3, + MX51_PAD_EIM_CS4__FEC_RX_ER, + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_NANDF_RB2__FEC_COL, + MX51_PAD_NANDF_RB3__FEC_RXCLK, + MX51_PAD_NANDF_RB6__FEC_RDAT0, + MX51_PAD_NANDF_RB7__FEC_TDAT0, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_NANDF_CS3__FEC_MDC, + MX51_PAD_NANDF_CS4__FEC_TDAT1, + MX51_PAD_NANDF_CS5__FEC_TDAT2, + MX51_PAD_NANDF_CS6__FEC_TDAT3, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + + /* FEC PHY reset line */ + MX51_PAD_EIM_A20__GPIO_2_14, }; /* Serial ports */ @@ -171,6 +195,22 @@ static inline void babbage_usbhub_reset(void) gpio_set_value(BABBAGE_USB_HUB_RESET, 1); } +static inline void babbage_fec_reset(void) +{ + int ret; + + /* reset FEC PHY */ + ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); + return; + } + gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); + gpio_set_value(BABBAGE_FEC_PHY_RESET, 0); + msleep(1); + gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); +} + /* This function is board specific as the bit mask for the plldiv will also be different for other Freescale SoCs, thus a common bitmask is not possible and cannot get place in /plat-mxc/ehci.c.*/ @@ -250,6 +290,7 @@ static void __init mxc_board_init(void) mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, ARRAY_SIZE(mx51babbage_pads)); mxc_init_imx_uart(); + babbage_fec_reset(); platform_add_devices(devices, ARRAY_SIZE(devices)); mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data); diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index a3e2b49aa39f..8fd226989b25 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -20,6 +20,7 @@ #include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/usb/musb.h> +#include <sound/tlv320aic3x.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -614,29 +615,35 @@ static int n8x0_menelaus_late_init(struct device *dev) return 0; } -static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { +#else +static int n8x0_menelaus_late_init(struct device *dev) +{ + return 0; +} +#endif + +static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { + .late_init = n8x0_menelaus_late_init, +}; + +static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { { I2C_BOARD_INFO("menelaus", 0x72), .irq = INT_24XX_SYS_NIRQ, + .platform_data = &n8x0_menelaus_platform_data, }, }; -static struct menelaus_platform_data n8x0_menelaus_platform_data = { - .late_init = n8x0_menelaus_late_init, +static struct aic3x_pdata n810_aic33_data __initdata = { + .gpio_reset = 118, }; -static void __init n8x0_menelaus_init(void) -{ - n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data; - omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, - ARRAY_SIZE(n8x0_i2c_board_info_1)); -} - -#else -static inline void __init n8x0_menelaus_init(void) -{ -} -#endif +static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { + { + I2C_BOARD_INFO("tlv320aic3x", 0x18), + .platform_data = &n810_aic33_data, + }, +}; static void __init n8x0_map_io(void) { @@ -653,6 +660,11 @@ static void __init n8x0_init_irq(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* I2S codec port pins for McBSP block */ + OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -665,9 +677,14 @@ static void __init n8x0_init_machine(void) /* FIXME: add n810 spi devices */ spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); + omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, + ARRAY_SIZE(n8x0_i2c_board_info_1)); + omap_register_i2c_bus(2, 400, NULL, 0); + if (machine_is_nokia_n810()) + i2c_register_board_info(2, n810_i2c_board_info_2, + ARRAY_SIZE(n810_i2c_board_info_2)); omap_serial_init(); - n8x0_menelaus_init(); n8x0_onenand_init(); n8x0_mmc_init(); n8x0_usb_init(); diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index c03d1d56db56..96f5bbb73b6f 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -274,8 +274,6 @@ static int __init omap4_panda_i2c_init(void) } static void __init omap4_panda_init(void) { - int status; - omap4_panda_i2c_init(); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index ab403b2ed26b..6c2f8f0c0edb 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -87,7 +87,7 @@ static char *omap_mux_options; int __init omap_mux_init_gpio(int gpio, int val) { struct omap_mux_entry *e; - struct omap_mux *gpio_mux; + struct omap_mux *gpio_mux = NULL; u16 old_mode; u16 mux_mode; int found = 0; diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index f5a1aad1a5c0..bb8c01da6578 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -35,7 +35,6 @@ static struct iommu_device omap3_devices[] = { .clk_name = "cam_ick", }, }, -#if defined(CONFIG_MPU_BRIDGE_IOMMU) { .base = 0x5d000000, .irq = 28, @@ -45,7 +44,6 @@ static struct iommu_device omap3_devices[] = { .clk_name = "iva2_ck", }, }, -#endif }; #define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices) static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 2fa38df28414..07c08151dfe6 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -259,6 +259,7 @@ struct mmci_platform_data realview_mmc0_plat_data = { .status = realview_mmc_status, .gpio_wp = 17, .gpio_cd = 16, + .cd_invert = true, }; struct mmci_platform_data realview_mmc1_plat_data = { @@ -266,6 +267,7 @@ struct mmci_platform_data realview_mmc1_plat_data = { .status = realview_mmc_status, .gpio_wp = 19, .gpio_cd = 18, + .cd_invert = true, }; /* diff --git a/arch/arm/mach-s3c64xx/dev-ts.c b/arch/arm/mach-s3c64xx/dev-ts.c new file mode 100644 index 000000000000..17cc7934afbe --- /dev/null +++ b/arch/arm/mach-s3c64xx/dev-ts.c @@ -0,0 +1,61 @@ +/* linux/arch/arm/mach-s3c64xx/dev-ts.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> + * + * Adapted by Maurus Cuelenaere for s3c64xx + * + * S3C64XX series device definition for touchscreen device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +#include <plat/devs.h> +#include <plat/ts.h> + +static struct resource s3c_ts_resource[] = { + [0] = { + .start = S3C64XX_PA_ADC, + .end = S3C64XX_PA_ADC + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TC, + .end = IRQ_TC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_ts = { + .name = "s3c64xx-ts", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_ts_resource), + .resource = s3c_ts_resource, +}; + +void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) +{ + struct s3c2410_ts_mach_info *npd; + + if (!pd) { + printk(KERN_ERR "%s: no platform data\n", __func__); + return; + } + + npd = kmemdup(pd, sizeof(struct s3c2410_ts_mach_info), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + + s3c_device_ts.dev.platform_data = npd; +} +EXPORT_SYMBOL(s3c24xx_ts_set_platdata); diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index d498219fff1b..c0f46e046f90 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -69,6 +69,7 @@ #include <plat/adc.h> #include <plat/ts.h> #include <plat/keypad.h> +#include <plat/audio.h> #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB @@ -283,6 +284,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { &s3c_device_fb, &s3c_device_ohci, &s3c_device_usb_hsotg, + &s3c64xx_device_ac97, &s3c64xx_device_iisv4, &samsung_device_keypad, @@ -699,6 +701,9 @@ static void __init smdk6410_machine_init(void) s3c_ide_set_platdata(&smdk6410_ide_pdata); + /* Board defualt with CFG2.1 off */ + s3c64xx_ac97_setup_gpio(S3C64XX_AC97_GPD); + platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); } diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index d3a38955c741..5315fec3db86 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -53,11 +53,6 @@ config S5PV210_SETUP_SDHCI_GPIO help Common setup code for SDHCI gpio. -config S5PC110_DEV_ONENAND - bool - help - Compile in platform device definition for OneNAND1 controller - menu "S5PC110 Machines" config MACH_AQUILA @@ -71,7 +66,7 @@ config MACH_AQUILA select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 - select S5PC110_DEV_ONENAND + select S5P_DEV_ONENAND select S5PV210_SETUP_FB_24BPP select S5PV210_SETUP_SDHCI help @@ -88,7 +83,7 @@ config MACH_GONI select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 - select S5PC110_DEV_ONENAND + select S5P_DEV_ONENAND select S5PV210_SETUP_FB_24BPP select S5PV210_SETUP_SDHCI help diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 05048c5aa4c6..704548912408 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_GONI) += mach-goni.o obj-y += dev-audio.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o -obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index af91fefef2c6..825b8681fbb3 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -357,7 +357,7 @@ static struct clk init_clocks_disable[] = { .id = 1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<8), + .ctrlbit = (1 << 10), }, { .name = "i2c", .id = 2, diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index b9f4d677cf55..77f456c91ad3 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -47,7 +47,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = { { .virtual = (unsigned long)S5P_VA_SYSTIMER, .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER), - .length = SZ_1M, + .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = (unsigned long)VA_VIC2, diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index e1c020e5a49b..cdb8ae415124 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -109,7 +109,7 @@ #define IRQ_IPC S5P_IRQ_VIC3(0) #define IRQ_HOSTIF S5P_IRQ_VIC3(1) -#define IRQ_MMC3 S5P_IRQ_VIC3(2) +#define IRQ_HSMMC3 S5P_IRQ_VIC3(2) #define IRQ_CEC S5P_IRQ_VIC3(3) #define IRQ_TSI S5P_IRQ_VIC3(4) #define IRQ_MDNIE0 S5P_IRQ_VIC3(5) diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index dd4fb6bf14b5..aa19d2f8dadb 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -17,7 +17,10 @@ #include <plat/map-s5p.h> #define S5PC110_PA_ONENAND (0xB0000000) +#define S5P_PA_ONENAND S5PC110_PA_ONENAND + #define S5PC110_PA_ONENAND_DMA (0xB0600000) +#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA #define S5PV210_PA_CHIPID (0xE0000000) #define S5P_PA_CHIPID S5PV210_PA_CHIPID diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index 0dda8012d6b2..bf772de6b0c3 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -477,7 +477,7 @@ static struct platform_device *aquila_devices[] __initdata = { &aquila_i2c_gpio_pmic, &aquila_device_gpiokeys, &s3c_device_fb, - &s5pc110_device_onenand, + &s5p_device_onenand, &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 53754d7d364e..fdc5cca4eb41 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -456,7 +456,7 @@ static void goni_setup_sdhci(void) static struct platform_device *goni_devices[] __initdata = { &s3c_device_fb, - &s5pc110_device_onenand, + &s5p_device_onenand, &goni_i2c_gpio_pmic, &goni_device_gpiokeys, &s5p_device_fimc0, diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 331b5bd97aba..9ac29fed44dc 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -27,12 +27,15 @@ config S5PV310_SETUP_I2C2 # machine support -config MACH_SMDKV310 - bool "SMDKV310" +menu "S5PC210 Machines" + +config MACH_SMDKC210 + bool "SMDKC210" select CPU_S5PV310 select ARCH_SPARSEMEM_ENABLE help - Machine support for Samsung SMDKV310 + Machine support for Samsung SMDKC210 + S5PC210(MCP) is one of package option of S5PV310 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" @@ -42,4 +45,17 @@ config MACH_UNIVERSAL_C210 Machine support for Samsung Mobile Universal S5PC210 Reference Board. S5PC210(MCP) is one of package option of S5PV310 +endmenu + +menu "S5PV310 Machines" + +config MACH_SMDKV310 + bool "SMDKV310" + select CPU_S5PV310 + select ARCH_SPARSEMEM_ENABLE + help + Machine support for Samsung SMDKV310 + +endmenu + endif diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile index d5b51c72340f..aefb14f23b8a 100644 --- a/arch/arm/mach-s5pv310/Makefile +++ b/arch/arm/mach-s5pv310/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o # machine support +obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c new file mode 100644 index 000000000000..03652c3605f6 --- /dev/null +++ b/arch/arm/mach-s5pv310/hotplug.c @@ -0,0 +1,144 @@ +/* linux arch/arm/mach-s5pv310/hotplug.c + * + * Cloned from linux/arch/arm/mach-realview/hotplug.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> +#include <linux/completion.h> + +#include <asm/cacheflush.h> + +extern volatile int pen_release; + +static DECLARE_COMPLETION(cpu_killed); + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0) + : "cc"); +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : + : "cc"); +} + +static inline void platform_do_lowpower(unsigned int cpu) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) { + /* + * here's the WFI + */ + asm(".word 0xe320f003\n" + : + : + : "memory", "cc"); + + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * The trouble is, letting people know about this is not really + * possible, since we are currently running incoherently, and + * therefore cannot safely call printk() or anything else + */ +#ifdef DEBUG + printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu); +#endif + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return wait_for_completion_timeout(&cpu_killed, 5000); +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ +#ifdef DEBUG + unsigned int this_cpu = hard_smp_processor_id(); + + if (cpu != this_cpu) { + printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", + this_cpu, cpu); + BUG(); + } +#endif + + printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); + complete(&cpu_killed); + + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index 4cdedda6e652..7b4b09fb7cc9 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -68,6 +68,13 @@ #define IRQ_IIC COMBINER_IRQ(27, 0) +#define IRQ_HSMMC0 COMBINER_IRQ(29, 0) +#define IRQ_HSMMC1 COMBINER_IRQ(29, 1) +#define IRQ_HSMMC2 COMBINER_IRQ(29, 2) +#define IRQ_HSMMC3 COMBINER_IRQ(29, 3) + +#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) + /* Set the default NR_IRQS */ #define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index 213e1101a3b3..204f386a3b6b 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -25,6 +25,12 @@ #define S5PV310_PA_SYSRAM (0x02025000) +#define S5PC210_PA_ONENAND (0x0C000000) +#define S5P_PA_ONENAND S5PC210_PA_ONENAND + +#define S5PC210_PA_ONENAND_DMA (0x0C600000) +#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA + #define S5PV310_PA_CHIPID (0x10000000) #define S5P_PA_CHIPID S5PV310_PA_CHIPID diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c new file mode 100644 index 000000000000..71a3becee3f1 --- /dev/null +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -0,0 +1,91 @@ +/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/serial_core.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <asm/hardware/cache-l2x0.h> + +#include <plat/regs-serial.h> +#include <plat/s5pv310.h> +#include <plat/cpu.h> + +#include <mach/map.h> + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, +}; + +static void __init smdkc210_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs)); +} + +static void __init smdkc210_machine_init(void) +{ +#ifdef CONFIG_CACHE_L2X0 + l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); +#endif +} + +MACHINE_START(SMDKC210, "SMDKC210") + /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5pv310_init_irq, + .map_io = smdkc210_map_io, + .init_machine = smdkc210_machine_init, + .timer = &s5pv310_timer, +MACHINE_END diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c index 2388cb947936..b57efaeb295f 100644 --- a/arch/arm/mach-s5pv310/mach-universal_c210.c +++ b/arch/arm/mach-s5pv310/mach-universal_c210.c @@ -7,7 +7,11 @@ * published by the Free Software Foundation. */ +#include <linux/platform_device.h> #include <linux/serial_core.h> +#include <linux/input.h> +#include <linux/gpio_keys.h> +#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -60,6 +64,61 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = { }, }; +static struct gpio_keys_button universal_gpio_keys_tables[] = { + { + .code = KEY_VOLUMEUP, + .gpio = S5PV310_GPX2(0), /* XEINT16 */ + .desc = "gpio-keys: KEY_VOLUMEUP", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, { + .code = KEY_VOLUMEDOWN, + .gpio = S5PV310_GPX2(1), /* XEINT17 */ + .desc = "gpio-keys: KEY_VOLUMEDOWN", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, { + .code = KEY_CONFIG, + .gpio = S5PV310_GPX2(2), /* XEINT18 */ + .desc = "gpio-keys: KEY_CONFIG", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, { + .code = KEY_CAMERA, + .gpio = S5PV310_GPX2(3), /* XEINT19 */ + .desc = "gpio-keys: KEY_CAMERA", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, { + .code = KEY_OK, + .gpio = S5PV310_GPX3(5), /* XEINT29 */ + .desc = "gpio-keys: KEY_OK", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data universal_gpio_keys_data = { + .buttons = universal_gpio_keys_tables, + .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables), +}; + +static struct platform_device universal_gpio_keys = { + .name = "gpio-keys", + .dev = { + .platform_data = &universal_gpio_keys_data, + }, +}; + +static struct platform_device *universal_devices[] __initdata = { + &universal_gpio_keys, +}; + static void __init universal_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -72,6 +131,9 @@ static void __init universal_machine_init(void) #ifdef CONFIG_CACHE_L2X0 l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); #endif + + /* Last */ + platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); } MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 5e16b4c69222..ae416fe7daf2 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -3,7 +3,7 @@ # # Common objects -obj-y := timer.o console.o clock.o +obj-y := timer.o console.o clock.o pm_runtime.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 23d472f9525e..95935c83c306 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -25,6 +25,7 @@ #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/mfd/sh_mobile_sdhi.h> +#include <linux/mfd/tmio.h> #include <linux/mmc/host.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> @@ -39,6 +40,7 @@ #include <linux/sh_clk.h> #include <linux/gpio.h> #include <linux/input.h> +#include <linux/leds.h> #include <linux/input/sh_keysc.h> #include <linux/usb/r8a66597.h> @@ -307,6 +309,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, .tmio_ocr_mask = MMC_VDD_165_195, + .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, }; static struct resource sdhi1_resources[] = { @@ -558,7 +561,7 @@ static struct resource fsi_resources[] = { static struct platform_device fsi_device = { .name = "sh_fsi2", - .id = 0, + .id = -1, .num_resources = ARRAY_SIZE(fsi_resources), .resource = fsi_resources, .dev = { @@ -650,7 +653,44 @@ static struct platform_device hdmi_device = { }, }; +static struct gpio_led ap4evb_leds[] = { + { + .name = "led4", + .gpio = GPIO_PORT185, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "led2", + .gpio = GPIO_PORT186, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "led3", + .gpio = GPIO_PORT187, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "led1", + .gpio = GPIO_PORT188, + .default_state = LEDS_GPIO_DEFSTATE_ON, + } +}; + +static struct gpio_led_platform_data ap4evb_leds_pdata = { + .num_leds = ARRAY_SIZE(ap4evb_leds), + .leds = ap4evb_leds, +}; + +static struct platform_device leds_device = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &ap4evb_leds_pdata, + }, +}; + static struct platform_device *ap4evb_devices[] __initdata = { + &leds_device, &nor_flash_device, &smc911x_device, &sdhi0_device, @@ -840,20 +880,6 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_CS5A, NULL); gpio_request(GPIO_FN_IRQ6_39, NULL); - /* enable LED 1 - 4 */ - gpio_request(GPIO_PORT185, NULL); - gpio_request(GPIO_PORT186, NULL); - gpio_request(GPIO_PORT187, NULL); - gpio_request(GPIO_PORT188, NULL); - gpio_direction_output(GPIO_PORT185, 1); - gpio_direction_output(GPIO_PORT186, 1); - gpio_direction_output(GPIO_PORT187, 1); - gpio_direction_output(GPIO_PORT188, 1); - gpio_export(GPIO_PORT185, 0); - gpio_export(GPIO_PORT186, 0); - gpio_export(GPIO_PORT187, 0); - gpio_export(GPIO_PORT188, 0); - /* enable Debug switch (S6) */ gpio_request(GPIO_PORT32, NULL); gpio_request(GPIO_PORT33, NULL); diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index fb4e9b1d788e..759468992ad2 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -286,7 +286,6 @@ static struct clk_ops pllc2_clk_ops = { struct clk pllc2_clk = { .ops = &pllc2_clk_ops, - .flags = CLK_ENABLE_ON_INIT, .parent = &extal1_div2_clk, .freq_table = pllc2_freq_table, .parent_table = pllc2_parent, @@ -395,7 +394,7 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { enum { MSTP001, MSTP131, MSTP130, - MSTP129, MSTP128, + MSTP129, MSTP128, MSTP127, MSTP126, MSTP118, MSTP117, MSTP116, MSTP106, MSTP101, MSTP100, MSTP223, @@ -413,6 +412,8 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ + [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */ + [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */ [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */ [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ @@ -428,7 +429,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ - [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, CLK_ENABLE_ON_INIT), /* FSIA */ + [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */ [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ @@ -498,6 +499,8 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */ CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */ CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */ + CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */ + CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */ CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */ CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */ CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index b7c705a213a2..6b7c7c42bc8f 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -1,8 +1,10 @@ /* - * SH-Mobile Timer + * SH-Mobile Clock Framework * * Copyright (C) 2010 Magnus Damm * + * Used together with arch/arm/common/clkdev.c and drivers/sh/clk.c. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c new file mode 100644 index 000000000000..94912d3944d3 --- /dev/null +++ b/arch/arm/mach-shmobile/pm_runtime.c @@ -0,0 +1,169 @@ +/* + * arch/arm/mach-shmobile/pm_runtime.c + * + * Runtime PM support code for SuperH Mobile ARM + * + * Copyright (C) 2009-2010 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/pm_runtime.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/sh_clk.h> +#include <linux/bitmap.h> + +#ifdef CONFIG_PM_RUNTIME +#define BIT_ONCE 0 +#define BIT_ACTIVE 1 +#define BIT_CLK_ENABLED 2 + +struct pm_runtime_data { + unsigned long flags; + struct clk *clk; +}; + +static void __devres_release(struct device *dev, void *res) +{ + struct pm_runtime_data *prd = res; + + dev_dbg(dev, "__devres_release()\n"); + + if (test_bit(BIT_CLK_ENABLED, &prd->flags)) + clk_disable(prd->clk); + + if (test_bit(BIT_ACTIVE, &prd->flags)) + clk_put(prd->clk); +} + +static struct pm_runtime_data *__to_prd(struct device *dev) +{ + return devres_find(dev, __devres_release, NULL, NULL); +} + +static void platform_pm_runtime_init(struct device *dev, + struct pm_runtime_data *prd) +{ + if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) { + prd->clk = clk_get(dev, NULL); + if (!IS_ERR(prd->clk)) { + set_bit(BIT_ACTIVE, &prd->flags); + dev_info(dev, "clocks managed by runtime pm\n"); + } + } +} + +static void platform_pm_runtime_bug(struct device *dev, + struct pm_runtime_data *prd) +{ + if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) + dev_err(dev, "runtime pm suspend before resume\n"); +} + +int platform_pm_runtime_suspend(struct device *dev) +{ + struct pm_runtime_data *prd = __to_prd(dev); + + dev_dbg(dev, "platform_pm_runtime_suspend()\n"); + + platform_pm_runtime_bug(dev, prd); + + if (prd && test_bit(BIT_ACTIVE, &prd->flags)) { + clk_disable(prd->clk); + clear_bit(BIT_CLK_ENABLED, &prd->flags); + } + + return 0; +} + +int platform_pm_runtime_resume(struct device *dev) +{ + struct pm_runtime_data *prd = __to_prd(dev); + + dev_dbg(dev, "platform_pm_runtime_resume()\n"); + + platform_pm_runtime_init(dev, prd); + + if (prd && test_bit(BIT_ACTIVE, &prd->flags)) { + clk_enable(prd->clk); + set_bit(BIT_CLK_ENABLED, &prd->flags); + } + + return 0; +} + +int platform_pm_runtime_idle(struct device *dev) +{ + /* suspend synchronously to disable clocks immediately */ + return pm_runtime_suspend(dev); +} + +static int platform_bus_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct device *dev = data; + struct pm_runtime_data *prd; + + dev_dbg(dev, "platform_bus_notify() %ld !\n", action); + + if (action == BUS_NOTIFY_BIND_DRIVER) { + prd = devres_alloc(__devres_release, sizeof(*prd), GFP_KERNEL); + if (prd) + devres_add(dev, prd); + else + dev_err(dev, "unable to alloc memory for runtime pm\n"); + } + + return 0; +} + +#else /* CONFIG_PM_RUNTIME */ + +static int platform_bus_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct device *dev = data; + struct clk *clk; + + dev_dbg(dev, "platform_bus_notify() %ld !\n", action); + + switch (action) { + case BUS_NOTIFY_BIND_DRIVER: + clk = clk_get(dev, NULL); + if (!IS_ERR(clk)) { + clk_enable(clk); + clk_put(clk); + dev_info(dev, "runtime pm disabled, clock forced on\n"); + } + break; + case BUS_NOTIFY_UNBOUND_DRIVER: + clk = clk_get(dev, NULL); + if (!IS_ERR(clk)) { + clk_disable(clk); + clk_put(clk); + dev_info(dev, "runtime pm disabled, clock forced off\n"); + } + break; + } + + return 0; +} + +#endif /* CONFIG_PM_RUNTIME */ + +static struct notifier_block platform_bus_notifier = { + .notifier_call = platform_bus_notify +}; + +static int __init sh_pm_runtime_init(void) +{ + bus_register_notifier(&platform_bus_type, &platform_bus_notifier); + return 0; +} +core_initcall(sh_pm_runtime_init); diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 0527e65318f4..448098bce216 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -91,6 +91,18 @@ config MXC_DEBUG_BOARD data/address de-multiplexing and decode, signal level shift, interrupt control and various board functions. +config HAVE_EPIT + bool + +config MXC_USE_EPIT + bool "Use EPIT instead of GPT" + depends on HAVE_EPIT + help + Use EPIT as the system timer on systems that have it. Normally you + don't have a reason to do so as the EPIT has the same features and + uses the same clocks as the GPT. Anyway, on some systems the GPT + may be in use for other purposes. + config MXC_ULPI bool diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 78d405ed8616..bb3443f9751a 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o +obj-$(CONFIG_MXC_USE_EPIT) += epit.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c new file mode 100644 index 000000000000..ee9582f4972e --- /dev/null +++ b/arch/arm/plat-mxc/epit.c @@ -0,0 +1,242 @@ +/* + * linux/arch/arm/plat-mxc/epit.c + * + * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#define EPITCR 0x00 +#define EPITSR 0x04 +#define EPITLR 0x08 +#define EPITCMPR 0x0c +#define EPITCNR 0x10 + +#define EPITCR_EN (1 << 0) +#define EPITCR_ENMOD (1 << 1) +#define EPITCR_OCIEN (1 << 2) +#define EPITCR_RLD (1 << 3) +#define EPITCR_PRESC(x) (((x) & 0xfff) << 4) +#define EPITCR_SWR (1 << 16) +#define EPITCR_IOVW (1 << 17) +#define EPITCR_DBGEN (1 << 18) +#define EPITCR_WAITEN (1 << 19) +#define EPITCR_RES (1 << 20) +#define EPITCR_STOPEN (1 << 21) +#define EPITCR_OM_DISCON (0 << 22) +#define EPITCR_OM_TOGGLE (1 << 22) +#define EPITCR_OM_CLEAR (2 << 22) +#define EPITCR_OM_SET (3 << 22) +#define EPITCR_CLKSRC_OFF (0 << 24) +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24) +#define EPITCR_CLKSRC_REF_HIGH (1 << 24) +#define EPITCR_CLKSRC_REF_LOW (3 << 24) + +#define EPITSR_OCIF (1 << 0) + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clockchips.h> +#include <linux/clk.h> + +#include <mach/hardware.h> +#include <asm/mach/time.h> +#include <mach/common.h> + +static struct clock_event_device clockevent_epit; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +static void __iomem *timer_base; + +static inline void epit_irq_disable(void) +{ + u32 val; + + val = __raw_readl(timer_base + EPITCR); + val &= ~EPITCR_OCIEN; + __raw_writel(val, timer_base + EPITCR); +} + +static inline void epit_irq_enable(void) +{ + u32 val; + + val = __raw_readl(timer_base + EPITCR); + val |= EPITCR_OCIEN; + __raw_writel(val, timer_base + EPITCR); +} + +static void epit_irq_acknowledge(void) +{ + __raw_writel(EPITSR_OCIF, timer_base + EPITSR); +} + +static cycle_t epit_read(struct clocksource *cs) +{ + return 0 - __raw_readl(timer_base + EPITCNR); +} + +static struct clocksource clocksource_epit = { + .name = "epit", + .rating = 200, + .read = epit_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init epit_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + clocksource_epit.mult = clocksource_hz2mult(c, + clocksource_epit.shift); + clocksource_register(&clocksource_epit); + + return 0; +} + +/* clock event */ + +static int epit_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = __raw_readl(timer_base + EPITCNR); + + __raw_writel(tcmp - evt, timer_base + EPITCMPR); + + return 0; +} + +static void epit_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call epit_set_next_event() + */ + local_irq_save(flags); + + /* Disable interrupt in GPT module */ + epit_irq_disable(); + + if (mode != clockevent_mode) { + /* Set event time into far-far future */ + + /* Clear pending interrupt */ + epit_irq_acknowledge(); + } + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + printk(KERN_ERR "epit_set_mode: Periodic mode is not " + "supported for i.MX EPIT\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * epit_set_next_event(), the core has about 4 minutes + * to call epit_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + epit_irq_enable(); + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } +} + +/* + * IRQ handler for the timer + */ +static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_epit; + + epit_irq_acknowledge(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction epit_timer_irq = { + .name = "i.MX EPIT Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = epit_timer_interrupt, +}; + +static struct clock_event_device clockevent_epit = { + .name = "epit", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = epit_set_mode, + .set_next_event = epit_set_next_event, + .rating = 200, +}; + +static int __init epit_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + clockevent_epit.mult = div_sc(c, NSEC_PER_SEC, + clockevent_epit.shift); + clockevent_epit.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_epit); + clockevent_epit.min_delta_ns = + clockevent_delta2ns(0x800, &clockevent_epit); + + clockevent_epit.cpumask = cpumask_of(0); + + clockevents_register_device(&clockevent_epit); + + return 0; +} + +void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) +{ + clk_enable(timer_clk); + + timer_base = base; + + /* + * Initialise to a known state (all timers off, and timing reset) + */ + __raw_writel(0x0, timer_base + EPITCR); + + __raw_writel(0xffffffff, timer_base + EPITLR); + __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, + timer_base + EPITCR); + + /* init and register the timer to the framework */ + epit_clocksource_init(timer_clk); + epit_clockevent_init(timer_clk); + + /* Make irqs happen */ + setup_irq(irq, &epit_timer_irq); +} diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 2941472582d2..7a1e1f89ff09 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -32,6 +32,7 @@ extern void mx31_init_irq(void); extern void mx35_init_irq(void); extern void mx51_init_irq(void); extern void mxc91231_init_irq(void); +extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 21bfa46785bb..0d77be3a2374 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -46,6 +46,13 @@ typedef enum iomux_config { #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ PAD_CTL_SRE_FAST) +#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + /* * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> @@ -106,14 +113,20 @@ typedef enum iomux_config { #define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) #define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) @@ -126,17 +139,28 @@ typedef enum iomux_config { #define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) #define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 7951eefe1a0e..2c0d3c38b01f 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -2084,7 +2084,7 @@ void omap2_gpio_prepare_for_idle(int power_state) for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l1, l2; + u32 l1 = 0, l2 = 0; if (bank->dbck_enable_mask) clk_disable(bank->dbck); @@ -2151,7 +2151,7 @@ void omap2_gpio_resume_after_idle(void) min = 1; for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l, gen, gen0, gen1; + u32 l = 0, gen, gen0, gen1; if (bank->dbck_enable_mask) clk_enable(bank->dbck); diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index c6a855db2fb6..407e3236809d 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -46,3 +46,8 @@ config S5P_DEV_FIMC2 bool help Compile in platform device definitions for FIMC controller 2 + +config S5P_DEV_ONENAND + bool + help + Compile in platform device definition for OneNAND controller diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index b2e029673950..f3e917e27da8 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -24,3 +24,4 @@ obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o +obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/plat-s5p/dev-onenand.c index f8ede33ee82b..6db926202caa 100644 --- a/arch/arm/mach-s5pv210/dev-onenand.c +++ b/arch/arm/plat-s5p/dev-onenand.c @@ -1,10 +1,12 @@ -/* - * linux/arch/arm/mach-s5pv210/dev-onenand.c +/* linux/arch/arm/plat-s5p/dev-onenand.c + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com * * Copyright (c) 2008-2010 Samsung Electronics * Kyungmin Park <kyungmin.park@samsung.com> * - * S5PC110 series device definition for OneNAND devices + * S5P series device definition for OneNAND devices * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -19,15 +21,15 @@ #include <mach/irqs.h> #include <mach/map.h> -static struct resource s5pc110_onenand_resources[] = { +static struct resource s5p_onenand_resources[] = { [0] = { - .start = S5PC110_PA_ONENAND, - .end = S5PC110_PA_ONENAND + SZ_128K - 1, + .start = S5P_PA_ONENAND, + .end = S5P_PA_ONENAND + SZ_128K - 1, .flags = IORESOURCE_MEM, }, [1] = { - .start = S5PC110_PA_ONENAND_DMA, - .end = S5PC110_PA_ONENAND_DMA + SZ_8K - 1, + .start = S5P_PA_ONENAND_DMA, + .end = S5P_PA_ONENAND_DMA + SZ_8K - 1, .flags = IORESOURCE_MEM, }, [2] = { @@ -37,19 +39,19 @@ static struct resource s5pc110_onenand_resources[] = { }, }; -struct platform_device s5pc110_device_onenand = { +struct platform_device s5p_device_onenand = { .name = "s5pc110-onenand", .id = -1, - .num_resources = ARRAY_SIZE(s5pc110_onenand_resources), - .resource = s5pc110_onenand_resources, + .num_resources = ARRAY_SIZE(s5p_onenand_resources), + .resource = s5p_onenand_resources, }; -void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata) +void s5p_onenand_set_platdata(struct onenand_platform_data *pdata) { struct onenand_platform_data *pd; pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); if (!pd) printk(KERN_ERR "%s: no memory for platform data\n", __func__); - s5pc110_device_onenand.dev.platform_data = pd; + s5p_device_onenand.dev.platform_data = pd; } diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c index 85aaf0f2842f..335bc35044d3 100644 --- a/arch/arm/plat-samsung/dev-hsmmc3.c +++ b/arch/arm/plat-samsung/dev-hsmmc3.c @@ -33,8 +33,8 @@ static struct resource s3c_hsmmc3_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_MMC3, - .end = IRQ_MMC3, + .start = IRQ_HSMMC3, + .end = IRQ_HSMMC3, .flags = IORESOURCE_IRQ, } }; diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 85f6f23a510f..cb12102fcdce 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -73,7 +73,7 @@ extern struct platform_device s3c_device_hwmon; extern struct platform_device s3c_device_nand; extern struct platform_device s3c_device_onenand; extern struct platform_device s3c64xx_device_onenand1; -extern struct platform_device s5pc110_device_onenand; +extern struct platform_device s5p_device_onenand; extern struct platform_device s3c_device_usbgadget; extern struct platform_device s3c_device_usb_hsotg; diff --git a/arch/m68k/include/asm/system_mm.h b/arch/m68k/include/asm/system_mm.h index dbb6515ffd5b..485daecb350b 100644 --- a/arch/m68k/include/asm/system_mm.h +++ b/arch/m68k/include/asm/system_mm.h @@ -205,9 +205,7 @@ static inline unsigned long __cmpxchg(volatile void *p, unsigned long old, ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ (unsigned long)(n), sizeof(*(ptr)))) -#ifndef CONFIG_SMP #include <asm-generic/cmpxchg.h> -#endif #endif diff --git a/arch/m68k/include/asm/system_no.h b/arch/m68k/include/asm/system_no.h index 3c0718d74398..08f31bdba36d 100644 --- a/arch/m68k/include/asm/system_no.h +++ b/arch/m68k/include/asm/system_no.h @@ -106,17 +106,10 @@ asmlinkage void resume(void); #define wmb() asm volatile ("" : : :"memory") #define set_mb(var, value) ({ (var) = (value); wmb(); }) -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#else #define smp_mb() barrier() #define smp_rmb() barrier() #define smp_wmb() barrier() #define smp_read_barrier_depends() do { } while(0) -#endif #define read_barrier_depends() ((void)0) @@ -199,9 +192,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz (unsigned long)(n), sizeof(*(ptr)))) #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) -#ifndef CONFIG_SMP #include <asm-generic/cmpxchg.h> -#endif #define arch_align_stack(x) (x) diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h index 60b15d0aa072..b43b36beafe3 100644 --- a/arch/m68k/include/asm/unistd.h +++ b/arch/m68k/include/asm/unistd.h @@ -340,10 +340,13 @@ #define __NR_set_thread_area 334 #define __NR_atomic_cmpxchg_32 335 #define __NR_atomic_barrier 336 +#define __NR_fanotify_init 337 +#define __NR_fanotify_mark 338 +#define __NR_prlimit64 339 #ifdef __KERNEL__ -#define NR_syscalls 337 +#define NR_syscalls 340 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c index 73e5e581245b..78e59b82ebc3 100644 --- a/arch/m68k/kernel/asm-offsets.c +++ b/arch/m68k/kernel/asm-offsets.c @@ -22,13 +22,9 @@ int main(void) { /* offsets into the task struct */ - DEFINE(TASK_STATE, offsetof(struct task_struct, state)); - DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags)); - DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace)); DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info)); DEFINE(TASK_MM, offsetof(struct task_struct, mm)); - DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); #ifdef CONFIG_MMU DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info)); #endif @@ -64,14 +60,6 @@ int main(void) /* bitfields are a bit difficult */ DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4); - /* offsets into the irq_handler struct */ - DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler)); - DEFINE(IRQ_DEVID, offsetof(struct irq_node, dev_id)); - DEFINE(IRQ_NEXT, offsetof(struct irq_node, next)); - - /* offsets into the kernel_stat struct */ - DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs)); - /* offsets into the irq_cpustat_t struct */ DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S index 2391bdff0996..6360c437dcf5 100644 --- a/arch/m68k/kernel/entry.S +++ b/arch/m68k/kernel/entry.S @@ -765,4 +765,7 @@ sys_call_table: .long sys_set_thread_area .long sys_atomic_cmpxchg_32 /* 335 */ .long sys_atomic_barrier + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c index 4926b3856c15..06438dac08ff 100644 --- a/arch/m68k/kernel/time.c +++ b/arch/m68k/kernel/time.c @@ -42,9 +42,7 @@ static inline int set_rtc_mmss(unsigned long nowtime) static irqreturn_t timer_interrupt(int irq, void *dummy) { do_timer(1); -#ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); -#endif profile_tick(CPU_PROFILING); #ifdef CONFIG_HEARTBEAT diff --git a/arch/m68k/sun3/sun3ints.c b/arch/m68k/sun3/sun3ints.c index ad90393a3361..606ff4deb320 100644 --- a/arch/m68k/sun3/sun3ints.c +++ b/arch/m68k/sun3/sun3ints.c @@ -66,12 +66,10 @@ static irqreturn_t sun3_int5(int irq, void *dev_id) #ifdef CONFIG_SUN3 intersil_clear(); #endif - do_timer(1); -#ifndef CONFIG_SMP + do_timer(1); update_process_times(user_mode(get_irq_regs())); -#endif - if (!(kstat_cpu(0).irqs[irq] % 20)) - sun3_leds(led_pattern[(kstat_cpu(0).irqs[irq] % 160) / 20]); + if (!(kstat_cpu(0).irqs[irq] % 20)) + sun3_leds(led_pattern[(kstat_cpu(0).irqs[irq] % 160) / 20]); return IRQ_HANDLED; } diff --git a/arch/m68knommu/kernel/asm-offsets.c b/arch/m68knommu/kernel/asm-offsets.c index 9a8876f715d8..eca508c48a08 100644 --- a/arch/m68knommu/kernel/asm-offsets.c +++ b/arch/m68knommu/kernel/asm-offsets.c @@ -21,14 +21,8 @@ int main(void) { /* offsets into the task struct */ - DEFINE(TASK_STATE, offsetof(struct task_struct, state)); - DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags)); - DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace)); - DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked)); DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); - DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack)); DEFINE(TASK_MM, offsetof(struct task_struct, mm)); - DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); /* offsets into the irq_cpustat_t struct */ DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); @@ -77,11 +71,8 @@ int main(void) DEFINE(THREAD_SIZE, THREAD_SIZE); /* Offsets in thread_info structure */ - DEFINE(TI_TASK, offsetof(struct thread_info, task)); - DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain)); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_PREEMPTCOUNT, offsetof(struct thread_info, preempt_count)); - DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); return 0; } diff --git a/arch/m68knommu/kernel/ptrace.c b/arch/m68knommu/kernel/ptrace.c index f6be1248d216..a32e2de78295 100644 --- a/arch/m68knommu/kernel/ptrace.c +++ b/arch/m68knommu/kernel/ptrace.c @@ -134,14 +134,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) tmp >>= 16; } else if (addr >= 21 && addr < 49) { tmp = child->thread.fp[addr - 21]; -#ifdef CONFIG_M68KFPU_EMU - /* Convert internal fpu reg representation - * into long double format - */ - if (FPU_IS_EMU && (addr < 45) && !(addr % 3)) - tmp = ((tmp & 0xffff0000) << 15) | - ((tmp & 0x0000ffff) << 16); -#endif } else if (addr == 49) { tmp = child->mm->start_code; } else if (addr == 50) { @@ -175,16 +167,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) } if (addr >= 21 && addr < 48) { -#ifdef CONFIG_M68KFPU_EMU - /* Convert long double format - * into internal fpu reg representation - */ - if (FPU_IS_EMU && (addr < 45) && !(addr % 3)) { - data = (unsigned long)data << 15; - data = (data & 0xffff0000) | - ((data & 0x0000ffff) >> 1); - } -#endif child->thread.fp[addr - 21] = data; ret = 0; } diff --git a/arch/m68knommu/kernel/setup.c b/arch/m68knommu/kernel/setup.c index ba92b90d5fbc..c684adf5dc40 100644 --- a/arch/m68knommu/kernel/setup.c +++ b/arch/m68knommu/kernel/setup.c @@ -54,9 +54,6 @@ void (*mach_reset)(void); void (*mach_halt)(void); void (*mach_power_off)(void); -#ifdef CONFIG_M68000 - #define CPU "MC68000" -#endif #ifdef CONFIG_M68328 #define CPU "MC68328" #endif diff --git a/arch/m68knommu/kernel/syscalltable.S b/arch/m68knommu/kernel/syscalltable.S index b30b3eb197a5..79b1ed198c07 100644 --- a/arch/m68knommu/kernel/syscalltable.S +++ b/arch/m68knommu/kernel/syscalltable.S @@ -355,6 +355,9 @@ ENTRY(sys_call_table) .long sys_set_thread_area .long sys_atomic_cmpxchg_32 /* 335 */ .long sys_atomic_barrier + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 .rept NR_syscalls-(.-sys_call_table)/4 .long sys_ni_syscall diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c index a90acf5b0cde..d6ac2a43453c 100644 --- a/arch/m68knommu/kernel/time.c +++ b/arch/m68knommu/kernel/time.c @@ -50,9 +50,8 @@ irqreturn_t arch_timer_interrupt(int irq, void *dummy) write_sequnlock(&xtime_lock); -#ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); -#endif + return(IRQ_HANDLED); } #endif @@ -61,13 +60,16 @@ static unsigned long read_rtc_mmss(void) { unsigned int year, mon, day, hour, min, sec; - if (mach_gettod) + if (mach_gettod) { mach_gettod(&year, &mon, &day, &hour, &min, &sec); - else - year = mon = day = hour = min = sec = 0; + if ((year += 1900) < 1970) + year += 100; + } else { + year = 1970; + mon = day = 1; + hour = min = sec = 0; + } - if ((year += 1900) < 1970) - year += 100; return mktime(year, mon, day, hour, min, sec); } diff --git a/arch/m68knommu/kernel/traps.c b/arch/m68knommu/kernel/traps.c index 3739c8f657d7..e8b813d2d0e4 100644 --- a/arch/m68knommu/kernel/traps.c +++ b/arch/m68knommu/kernel/traps.c @@ -360,16 +360,3 @@ void show_stack(struct task_struct *task, unsigned long *stack) else __show_stack(task, stack); } - -#ifdef CONFIG_M68KFPU_EMU -asmlinkage void fpemu_signal(int signal, int code, void *addr) -{ - siginfo_t info; - - info.si_signo = signal; - info.si_errno = 0; - info.si_code = code; - info.si_addr = addr; - force_sig_info(signal, &info, current); -} -#endif diff --git a/arch/m68knommu/platform/68328/entry.S b/arch/m68knommu/platform/68328/entry.S index 9d80d2c42866..74229f73449e 100644 --- a/arch/m68knommu/platform/68328/entry.S +++ b/arch/m68knommu/platform/68328/entry.S @@ -43,7 +43,7 @@ badsys: jra ret_from_exception do_trace: - movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ + movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ subql #4,%sp SAVE_SWITCH_STACK jbsr syscall_trace @@ -57,7 +57,7 @@ do_trace: lea sys_call_table, %a0 jbsr %a0@(%d1) -1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ +1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ subql #4,%sp /* dummy return address */ SAVE_SWITCH_STACK jbsr syscall_trace @@ -71,16 +71,16 @@ ENTRY(system_call) SAVE_ALL /* save top of frame*/ - pea %sp@ - jbsr set_esp0 - addql #4,%sp + pea %sp@ + jbsr set_esp0 + addql #4,%sp movel %sp@(PT_OFF_ORIG_D0),%d0 movel %sp,%d1 /* get thread_info pointer */ andl #-THREAD_SIZE,%d1 movel %d1,%a2 - btst #TIF_SYSCALL_TRACE,%a2@(TI_FLAGS) + btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8) jne do_trace cmpl #NR_syscalls,%d0 jcc badsys @@ -88,10 +88,10 @@ ENTRY(system_call) lea sys_call_table,%a0 movel %a0@(%d0), %a0 jbsr %a0@ - movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ + movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ ret_from_exception: - btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/ + btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/ jeq Luser_return /* if so, skip resched, signals*/ Lkernel_return: diff --git a/arch/m68knommu/platform/68328/head-de2.S b/arch/m68knommu/platform/68328/head-de2.S index 92d96456d363..f632fdcb93e9 100644 --- a/arch/m68knommu/platform/68328/head-de2.S +++ b/arch/m68knommu/platform/68328/head-de2.S @@ -1,11 +1,5 @@ -#if defined(CONFIG_RAM32MB) -#define MEM_END 0x02000000 /* Memory size 32Mb */ -#elif defined(CONFIG_RAM16MB) -#define MEM_END 0x01000000 /* Memory size 16Mb */ -#else #define MEM_END 0x00800000 /* Memory size 8Mb */ -#endif #undef CRT_DEBUG diff --git a/arch/m68knommu/platform/68328/head-ram.S b/arch/m68knommu/platform/68328/head-ram.S index 252b80b02038..7f1aeeacb219 100644 --- a/arch/m68knommu/platform/68328/head-ram.S +++ b/arch/m68knommu/platform/68328/head-ram.S @@ -67,33 +67,6 @@ pclp1: beq pclp1 #endif /* DEBUG */ -#ifdef CONFIG_RELOCATE - /* Copy me to RAM */ - moveal #__rom_start, %a0 - moveal #_stext, %a1 - moveal #_edata, %a2 - - /* Copy %a0 to %a1 until %a1 == %a2 */ -LD1: - movel %a0@+, %d0 - movel %d0, %a1@+ - cmpal %a1, %a2 - bhi LD1 - -#ifdef DEBUG - moveq #74, %d7 /* 'J' */ - moveb %d7,0xfffff907 /* No absolute addresses */ -pclp2: - movew 0xfffff906, %d7 - andw #0x2000, %d7 - beq pclp2 -#endif /* DEBUG */ - /* jump into the RAM copy */ - jmp ram_jump -ram_jump: - -#endif /* CONFIG_RELOCATE */ - #ifdef DEBUG moveq #82, %d7 /* 'R' */ moveb %d7,0xfffff907 /* No absolute addresses */ diff --git a/arch/m68knommu/platform/68360/entry.S b/arch/m68knommu/platform/68360/entry.S index 6d3460a39cac..d5ad4080f553 100644 --- a/arch/m68knommu/platform/68360/entry.S +++ b/arch/m68knommu/platform/68360/entry.S @@ -71,7 +71,12 @@ ENTRY(system_call) jbsr set_esp0 addql #4,%sp - btst #PF_TRACESYS_BIT,%a2@(TASK_FLAGS+PF_TRACESYS_OFF) + movel %sp@(PT_OFF_ORIG_D0),%d0 + + movel %sp,%d1 /* get thread_info pointer */ + andl #-THREAD_SIZE,%d1 + movel %d1,%a2 + btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8) jne do_trace cmpl #NR_syscalls,%d0 jcc badsys diff --git a/arch/m68knommu/platform/68VZ328/config.c b/arch/m68knommu/platform/68VZ328/config.c index fc5c63054e98..eabaabe8af36 100644 --- a/arch/m68knommu/platform/68VZ328/config.c +++ b/arch/m68knommu/platform/68VZ328/config.c @@ -90,11 +90,6 @@ static void init_hardware(char *command, int size) PDIQEG &= ~PD(1); PDIRQEN |= PD(1); /* IRQ enabled */ -#ifdef CONFIG_68328_SERIAL_UART2 - /* Enable RXD TXD port bits to enable UART2 */ - PJSEL &= ~(PJ(5) | PJ(4)); -#endif - #ifdef CONFIG_INIT_LCD /* initialize LCD controller */ LSSA = (long) screen_bits; diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c index 5598c8b8661f..a0c72ec8e6b5 100644 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ b/arch/m68knommu/platform/coldfire/intc-2.c @@ -1,5 +1,9 @@ /* - * intc-1.c + * intc-2.c + * + * General interrupt controller code for the many ColdFire version 2 cores + * that use the two region INTC interrupt controller. This includes the + * 523x family, 5270, 5271, 5274, 5275, and the 528x families. * * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> * diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c index 1b01e79c2f63..8435ced33ac4 100644 --- a/arch/m68knommu/platform/coldfire/intc-simr.c +++ b/arch/m68knommu/platform/coldfire/intc-simr.c @@ -1,6 +1,8 @@ /* * intc-simr.c * + * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts. + * * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> * * This file is subject to the terms and conditions of the GNU General Public diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 692fdfce2a23..dad40fc2bef8 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -121,6 +121,23 @@ config CMDLINE_FORCE Set this to have arguments from the default kernel command string override those passed by the boot loader. +config SECCOMP + bool "Enable seccomp to safely compute untrusted bytecode" + depends on PROC_FS + default y + help + This kernel feature is useful for number crunching applications + that may need to compute untrusted bytecode during their + execution. By using pipes or other transports made available to + the process as file descriptors supporting the read/write + syscalls, it's possible to isolate those applications in + their own address space using seccomp. Once seccomp is + enabled via /proc/<pid>/seccomp, it cannot be disabled + and the task is only allowed to execute a few safe syscalls + defined by each seccomp mode. + + If unsure, say Y. Only embedded should say N here. + endmenu menu "Advanced setup" diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h index cf377d91da71..ed9d0f6e2cdb 100644 --- a/arch/microblaze/include/asm/page.h +++ b/arch/microblaze/include/asm/page.h @@ -205,9 +205,6 @@ extern int page_is_ram(unsigned long pfn); #define TOPHYS(addr) __virt_to_phys(addr) #ifdef CONFIG_MMU -#ifdef CONFIG_CONTIGUOUS_PAGE_ALLOC -#define WANT_PAGE_VIRTUAL 1 /* page alloc 2 relies on this */ -#endif #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h index 101fa098f62a..5012b222e1df 100644 --- a/arch/microblaze/include/asm/prom.h +++ b/arch/microblaze/include/asm/prom.h @@ -22,6 +22,7 @@ #include <linux/types.h> #include <asm/irq.h> #include <asm/atomic.h> +#include <linux/of_address.h> #define HAVE_ARCH_DEVTREE_FIXUPS diff --git a/arch/microblaze/include/asm/seccomp.h b/arch/microblaze/include/asm/seccomp.h new file mode 100644 index 000000000000..0d912758a0d7 --- /dev/null +++ b/arch/microblaze/include/asm/seccomp.h @@ -0,0 +1,16 @@ +#ifndef _ASM_MICROBLAZE_SECCOMP_H +#define _ASM_MICROBLAZE_SECCOMP_H + +#include <linux/unistd.h> + +#define __NR_seccomp_read __NR_read +#define __NR_seccomp_write __NR_write +#define __NR_seccomp_exit __NR_exit +#define __NR_seccomp_sigreturn __NR_sigreturn + +#define __NR_seccomp_read_32 __NR_read +#define __NR_seccomp_write_32 __NR_write +#define __NR_seccomp_exit_32 __NR_exit +#define __NR_seccomp_sigreturn_32 __NR_sigreturn + +#endif /* _ASM_MICROBLAZE_SECCOMP_H */ diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h index 782b5c89248e..5f910ebe0325 100644 --- a/arch/microblaze/include/asm/setup.h +++ b/arch/microblaze/include/asm/setup.h @@ -25,6 +25,12 @@ void early_printk(const char *fmt, ...); int setup_early_printk(char *opt); void disable_early_printk(void); +#if defined(CONFIG_EARLY_PRINTK) && defined(CONFIG_SERIAL_UARTLITE_CONSOLE) +#define eprintk early_printk +#else +#define eprintk printk +#endif + void heartbeat(void); void setup_heartbeat(void); diff --git a/arch/microblaze/include/asm/thread_info.h b/arch/microblaze/include/asm/thread_info.h index 8a8e9fc6e0c0..b73da2ac21b3 100644 --- a/arch/microblaze/include/asm/thread_info.h +++ b/arch/microblaze/include/asm/thread_info.h @@ -127,23 +127,19 @@ static inline struct thread_info *current_thread_info(void) #define TIF_SECCOMP 10 /* secure computing */ #define TIF_FREEZE 14 /* Freezing for suspend */ -/* FIXME change in entry.S */ -#define TIF_KERNEL_TRACE 8 /* kernel trace active */ - /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define TIF_POLLING_NRFLAG 16 -#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) -#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) -#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) -#define _TIF_IRET (1<<TIF_IRET) -#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) -#define _TIF_FREEZE (1<<TIF_FREEZE) +#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) +#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) +#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) +#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) +#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) +#define _TIF_IRET (1 << TIF_IRET) +#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) +#define _TIF_FREEZE (1 << TIF_FREEZE) #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) -#define _TIF_KERNEL_TRACE (1 << TIF_KERNEL_TRACE) /* work to do in syscall trace */ #define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S index 304882e56459..a2a7e1e20e4c 100644 --- a/arch/microblaze/kernel/entry.S +++ b/arch/microblaze/kernel/entry.S @@ -186,6 +186,8 @@ swi r13, r1, PTO+PT_R13; /* Save SDA2 */ \ swi r14, r1, PTO+PT_PC; /* PC, before IRQ/trap */ \ swi r15, r1, PTO+PT_R15; /* Save LP */ \ + swi r16, r1, PTO+PT_R16; \ + swi r17, r1, PTO+PT_R17; \ swi r18, r1, PTO+PT_R18; /* Save asm scratch reg */ \ swi r19, r1, PTO+PT_R19; \ swi r20, r1, PTO+PT_R20; \ @@ -220,6 +222,8 @@ lwi r13, r1, PTO+PT_R13; /* restore SDA2 */ \ lwi r14, r1, PTO+PT_PC; /* RESTORE_LINK PC, before IRQ/trap */\ lwi r15, r1, PTO+PT_R15; /* restore LP */ \ + lwi r16, r1, PTO+PT_R16; \ + lwi r17, r1, PTO+PT_R17; \ lwi r18, r1, PTO+PT_R18; /* restore asm scratch reg */ \ lwi r19, r1, PTO+PT_R19; \ lwi r20, r1, PTO+PT_R20; \ @@ -295,6 +299,8 @@ C_ENTRY(_user_exception): /* addik r1, r1, -STATE_SAVE_SIZE; */ addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; SAVE_REGS + swi r0, r1, PTO + PT_R3 + swi r0, r1, PTO + PT_R4 lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); swi r11, r1, PTO+PT_R1; /* Store user SP. */ @@ -319,8 +325,6 @@ C_ENTRY(_user_exception): andi r11, r11, _TIF_WORK_SYSCALL_MASK beqi r11, 4f - addik r3, r0, -ENOSYS - swi r3, r1, PTO + PT_R3 brlid r15, do_syscall_trace_enter addik r5, r1, PTO + PT_R0 @@ -458,14 +462,8 @@ C_ENTRY(sys_execve): addik r8, r1, PTO; /* add user context as 4th arg */ C_ENTRY(sys_rt_sigreturn_wrapper): - swi r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */ - swi r4, r1, PTO+PT_R4; - brlid r15, sys_rt_sigreturn /* Do real work */ + brid sys_rt_sigreturn /* Do real work */ addik r5, r1, PTO; /* add user context as 1st arg */ - lwi r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */ - lwi r4, r1, PTO+PT_R4; - bri ret_from_trap /* fall through will not work here due to align */ - nop; /* * HW EXCEPTION rutine start @@ -765,9 +763,7 @@ C_ENTRY(_debug_exception): /* save all regs to pt_reg structure */ swi r0, r1, PTO+PT_R0; /* R0 must be saved too */ swi r14, r1, PTO+PT_R14 /* rewrite saved R14 value */ - swi r16, r1, PTO+PT_R16 swi r16, r1, PTO+PT_PC; /* PC and r16 are the same */ - swi r17, r1, PTO+PT_R17 /* save special purpose registers to pt_regs */ mfs r11, rear; swi r11, r1, PTO+PT_EAR; @@ -801,8 +797,6 @@ C_ENTRY(_debug_exception): addik r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */ SAVE_REGS; - swi r17, r1, PTO+PT_R17; - swi r16, r1, PTO+PT_R16; swi r16, r1, PTO+PT_PC; /* Save LP */ swi r0, r1, PTO + PT_MODE; /* Was in user-mode. */ lwi r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); @@ -848,8 +842,6 @@ dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */ tophys(r1,r1); /* MS: Restore all regs */ RESTORE_REGS - lwi r17, r1, PTO+PT_R17; - lwi r16, r1, PTO+PT_R16; addik r1, r1, STATE_SAVE_SIZE /* Clean up stack space */ lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer */ DBTRAP_return_user: /* MS: Make global symbol for debugging */ @@ -863,7 +855,6 @@ DBTRAP_return_user: /* MS: Make global symbol for debugging */ RESTORE_REGS lwi r14, r1, PTO+PT_R14; lwi r16, r1, PTO+PT_PC; - lwi r17, r1, PTO+PT_R17; addik r1, r1, STATE_SAVE_SIZE; /* MS: Clean up stack space */ tovirt(r1,r1); DBTRAP_return_kernel: /* MS: Make global symbol for debugging */ diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c index b98ee8d0c1cd..7fce4ee4644c 100644 --- a/arch/microblaze/kernel/exceptions.c +++ b/arch/microblaze/kernel/exceptions.c @@ -148,13 +148,7 @@ asmlinkage void full_exception(struct pt_regs *regs, unsigned int type, #ifdef CONFIG_MMU case MICROBLAZE_PRIVILEGED_EXCEPTION: pr_debug(KERN_WARNING "Privileged exception\n"); - /* "brk r0,r0" - used as debug breakpoint - old toolchain */ - if (get_user(code, (unsigned long *)regs->pc) == 0 - && code == 0x980c0000) { - _exception(SIGTRAP, regs, TRAP_BRKPT, addr); - } else { - _exception(SIGILL, regs, ILL_PRVOPC, addr); - } + _exception(SIGILL, regs, ILL_PRVOPC, addr); break; #endif default: diff --git a/arch/microblaze/kernel/kgdb.c b/arch/microblaze/kernel/kgdb.c index bfc006b7f2d8..9b5a817605ec 100644 --- a/arch/microblaze/kernel/kgdb.c +++ b/arch/microblaze/kernel/kgdb.c @@ -80,7 +80,7 @@ void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) void microblaze_kgdb_break(struct pt_regs *regs) { if (kgdb_handle_exception(1, SIGTRAP, 0, regs) != 0) - return 0; + return; /* Jump over the first arch_kgdb_breakpoint which is barrier to * get kgdb work. The same solution is used for powerpc */ @@ -114,7 +114,6 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code, { char *ptr; unsigned long address; - int cpu = smp_processor_id(); switch (remcom_in_buffer[0]) { case 'c': diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c index f5f768842354..bb1558e4b283 100644 --- a/arch/microblaze/kernel/setup.c +++ b/arch/microblaze/kernel/setup.c @@ -92,12 +92,6 @@ inline unsigned get_romfs_len(unsigned *addr) } #endif /* CONFIG_MTD_UCLINUX_EBSS */ -#if defined(CONFIG_EARLY_PRINTK) && defined(CONFIG_SERIAL_UARTLITE_CONSOLE) -#define eprintk early_printk -#else -#define eprintk printk -#endif - void __init machine_early_init(const char *cmdline, unsigned int ram, unsigned int fdt, unsigned int msr) { diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c index b1380ae93ae1..ec7df67006ba 100644 --- a/arch/microblaze/kernel/timer.c +++ b/arch/microblaze/kernel/timer.c @@ -278,7 +278,7 @@ void __init time_init(void) timer_num = *(int *) of_get_property(timer, "xlnx,one-timer-only", NULL); if (timer_num) { - printk(KERN_EMERG "Please enable two timers in HW\n"); + eprintk(KERN_EMERG "Please enable two timers in HW\n"); BUG(); } diff --git a/arch/microblaze/platform/generic/system.dts b/arch/microblaze/platform/generic/system.dts index 2d5c41767cd0..544a6f232012 100644 --- a/arch/microblaze/platform/generic/system.dts +++ b/arch/microblaze/platform/generic/system.dts @@ -218,6 +218,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,compound"; + ranges ; ethernet@81c00000 { compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a"; device_type = "network"; diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 4d6681dce816..c571cd3c1453 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -575,13 +575,19 @@ __secondary_start: /* Initialize the kernel stack. Just a repeat for iSeries. */ LOAD_REG_ADDR(r3, current_set) sldi r28,r24,3 /* get current_set[cpu#] */ - ldx r1,r3,r28 - addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD - std r1,PACAKSAVE(r13) + ldx r14,r3,r28 + addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD + std r14,PACAKSAVE(r13) /* Do early setup for that CPU (stab, slb, hash table pointer) */ bl .early_setup_secondary + /* + * setup the new stack pointer, but *don't* use this until + * translation is on. + */ + mr r1, r14 + /* Clear backchain so we get nice backtraces */ li r7,0 mtlr r7 diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 6bbd7a604d24..a7a570dcdd57 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -810,6 +810,9 @@ relocate_new_kernel: isync sync + mfspr r3, SPRN_PIR /* current core we are running on */ + mr r4, r5 /* load physical address of chunk called */ + /* jump to the entry point, usually the setup routine */ mtlr r5 blrl diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index ce53dfa7130d..8533b3b83f5d 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -577,20 +577,11 @@ void timer_interrupt(struct pt_regs * regs) * some CPUs will continuue to take decrementer exceptions */ set_dec(DECREMENTER_MAX); -#ifdef CONFIG_PPC32 +#if defined(CONFIG_PPC32) && defined(CONFIG_PMAC) if (atomic_read(&ppc_n_lost_interrupts) != 0) do_IRQ(regs); #endif - now = get_tb_or_rtc(); - if (now < decrementer->next_tb) { - /* not time for this event yet */ - now = decrementer->next_tb - now; - if (now <= DECREMENTER_MAX) - set_dec((int)now); - trace_timer_interrupt_exit(regs); - return; - } old_regs = set_irq_regs(regs); irq_enter(); @@ -606,8 +597,16 @@ void timer_interrupt(struct pt_regs * regs) get_lppaca()->int_dword.fields.decr_int = 0; #endif - if (evt->event_handler) - evt->event_handler(evt); + now = get_tb_or_rtc(); + if (now >= decrementer->next_tb) { + decrementer->next_tb = ~(u64)0; + if (evt->event_handler) + evt->event_handler(evt); + } else { + now = decrementer->next_tb - now; + if (now <= DECREMENTER_MAX) + set_dec((int)now); + } #ifdef CONFIG_PPC_ISERIES if (firmware_has_feature(FW_FEATURE_ISERIES) && hvlpevent_is_pending()) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index da64be19d099..2af07a6c8274 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -357,6 +357,7 @@ static void __init mpc85xx_mds_setup_arch(void) { #ifdef CONFIG_PCI struct pci_controller *hose; + struct device_node *np = NULL; #endif dma_addr_t max = 0xffffffff; diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 87991d3abbab..20cdcd2b0eed 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c @@ -24,6 +24,7 @@ #include <asm/ppc-pci.h> #include <asm/mpic.h> #include "fsl_msi.h" +#include "fsl_pci.h" LIST_HEAD(msi_head); @@ -125,13 +126,11 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, { struct fsl_msi *msi_data = fsl_msi_data; struct pci_controller *hose = pci_bus_to_host(pdev->bus); - u32 base = 0; + u64 base = fsl_pci_immrbar_base(hose); - pci_bus_read_config_dword(hose->bus, - PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); + msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base); + msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base); - msg->address_lo = msi_data->msi_addr_lo + base; - msg->address_hi = msi_data->msi_addr_hi; msg->data = hwirq; pr_debug("%s: allocated srs: %d, ibs: %d\n", diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 209384b6e039..d83f1b0f773f 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -1,7 +1,7 @@ /* * MPC83xx/85xx/86xx PCI/PCIE support routing. * - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * Copyright 2008-2009 MontaVista Software, Inc. * * Initial author: Xianghua Xiao <x.xiao@freescale.com> @@ -310,6 +310,16 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus) } } +u64 fsl_pci_immrbar_base(struct pci_controller *hose) +{ + u32 base; + + pci_bus_read_config_dword(hose->bus, + PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); + + return base; +} + int __init fsl_add_bridge(struct device_node *dev, int is_primary) { int len; @@ -428,6 +438,13 @@ struct mpc83xx_pcie_priv { u32 dev_base; }; +struct pex_inbound_window { + u32 ar; + u32 tar; + u32 barl; + u32 barh; +}; + /* * With the convention of u-boot, the PCIE outbound window 0 serves * as configuration transactions outbound. @@ -435,6 +452,8 @@ struct mpc83xx_pcie_priv { #define PEX_OUTWIN0_BAR 0xCA4 #define PEX_OUTWIN0_TAL 0xCA8 #define PEX_OUTWIN0_TAH 0xCAC +#define PEX_RC_INWIN_BASE 0xE60 +#define PEX_RCIWARn_EN 0x1 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) { @@ -461,6 +480,28 @@ static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) return PCIBIOS_SUCCESSFUL; } +/* Walk the Root Complex Inbound windows to match IMMR base */ +u64 fsl_pci_immrbar_base(struct pci_controller *hose) +{ + struct mpc83xx_pcie_priv *pcie = hose->dn->data; + struct pex_inbound_window *in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; + int i; + + for (i = 0; i < 4; i++) { + /* not enabled, skip */ + if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN) + continue; + + if (get_immrbase() == in_le32(&in[i].tar)) + return (u64)in_le32(&in[i].barh) << 32 | + in_le32(&in[i].barl); + } + + printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); + + return 0; +} + static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, unsigned int devfn, int offset) { diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index a9d8bbebed80..8ad72a11f77b 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -88,6 +88,7 @@ struct ccsr_pci { extern int fsl_add_bridge(struct device_node *dev, int is_primary); extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); extern int mpc83xx_add_bridge(struct device_node *dev); +u64 fsl_pci_immrbar_base(struct pci_controller *hose); #endif /* __POWERPC_FSL_PCI_H */ #endif /* __KERNEL__ */ diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 3157441ee1da..22a294571000 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -46,11 +46,27 @@ extern void vmem_map_init(void); #define update_mmu_cache(vma, address, ptep) do { } while (0) /* - * ZERO_PAGE is a global shared page that is always zero: used + * ZERO_PAGE is a global shared page that is always zero; used * for zero-mapped memory areas etc.. */ -extern char empty_zero_page[PAGE_SIZE]; -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) + +extern unsigned long empty_zero_page; +extern unsigned long zero_page_mask; + +#define ZERO_PAGE(vaddr) \ + (virt_to_page((void *)(empty_zero_page + \ + (((unsigned long)(vaddr)) &zero_page_mask)))) + +#define is_zero_pfn is_zero_pfn +static inline int is_zero_pfn(unsigned long pfn) +{ + extern unsigned long zero_pfn; + unsigned long offset_from_zero_pfn = pfn - zero_pfn; + return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); +} + +#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) + #endif /* !__ASSEMBLY__ */ /* diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c index 30eb6d02ddb8..6ee1dd92fe39 100644 --- a/arch/s390/mm/init.c +++ b/arch/s390/mm/init.c @@ -42,9 +42,52 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__((__aligned__(PAGE_SIZE))); -char empty_zero_page[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE))); +unsigned long empty_zero_page, zero_page_mask; EXPORT_SYMBOL(empty_zero_page); +static unsigned long setup_zero_pages(void) +{ + struct cpuid cpu_id; + unsigned int order; + unsigned long size; + struct page *page; + int i; + + get_cpu_id(&cpu_id); + switch (cpu_id.machine) { + case 0x9672: /* g5 */ + case 0x2064: /* z900 */ + case 0x2066: /* z900 */ + case 0x2084: /* z990 */ + case 0x2086: /* z990 */ + case 0x2094: /* z9-109 */ + case 0x2096: /* z9-109 */ + order = 0; + break; + case 0x2097: /* z10 */ + case 0x2098: /* z10 */ + default: + order = 2; + break; + } + + empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order); + if (!empty_zero_page) + panic("Out of memory in setup_zero_pages"); + + page = virt_to_page((void *) empty_zero_page); + split_page(page, order); + for (i = 1 << order; i > 0; i--) { + SetPageReserved(page); + page++; + } + + size = PAGE_SIZE << order; + zero_page_mask = (size - 1) & PAGE_MASK; + + return 1UL << order; +} + /* * paging_init() sets up the page tables */ @@ -93,14 +136,12 @@ void __init mem_init(void) max_mapnr = num_physpages = max_low_pfn; high_memory = (void *) __va(max_low_pfn * PAGE_SIZE); - /* clear the zero-page */ - memset(empty_zero_page, 0, PAGE_SIZE); - /* Setup guest page hinting */ cmma_init(); /* this will put all low memory onto the freelists */ totalram_pages += free_all_bootmem(); + totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */ reservedpages = 0; diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 33990fa95af0..2284215981ed 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -23,6 +23,7 @@ config SUPERH select HAVE_KERNEL_LZMA select HAVE_KERNEL_LZO select HAVE_SYSCALL_TRACEPOINTS + select HAVE_REGS_AND_STACK_ACCESS_API select RTC_LIB select GENERIC_ATOMIC64 help @@ -45,7 +46,7 @@ config SUPERH32 select HAVE_ARCH_KGDB select HAVE_HW_BREAKPOINT select HAVE_MIXED_BREAKPOINTS_REGS - select PERF_EVENTS if HAVE_HW_BREAKPOINT + select PERF_EVENTS select ARCH_HIBERNATION_POSSIBLE if MMU config SUPERH64 @@ -569,7 +570,7 @@ config SH_CLK_CPG config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ - !CPU_SUBTYPE_SH7786 + !CPU_SUBTYPE_SH7786 && !CPU_SUBTYPE_SH7757 config SH_CLK_MD int "CPU Mode Pin Setting" diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 07b35ca2f644..90ed1ec6921d 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -165,6 +165,11 @@ config SH_HIGHLANDER select SYS_SUPPORTS_PCI select IO_TRAPPED if MMU +config SH_SH7757LCR + bool "SH7757LCR" + depends on CPU_SUBTYPE_SH7757 + select ARCH_REQUIRE_GPIOLIB + config SH_SH7785LCR bool "SH7785LCR" depends on CPU_SUBTYPE_SH7785 @@ -309,6 +314,17 @@ config SH_POLARIS help Select if configuring for an SMSC Polaris development board +config SH_SH2007 + bool "SH-2007 board" + select NO_IOPORT + depends on CPU_SUBTYPE_SH7780 + help + SH-2007 is a single-board computer based around SH7780 chip + intended for embedded applications. + It has an Ethernet interface (SMC9118), direct connected + Compact Flash socket, two serial ports and PC-104 bus. + More information at <http://sh2000.sh-linux.org>. + endmenu source "arch/sh/boards/mach-r2d/Kconfig" diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile index 4f90f9b7a922..38ef655cc0f0 100644 --- a/arch/sh/boards/Makefile +++ b/arch/sh/boards/Makefile @@ -2,6 +2,7 @@ # Specific board support, not covered by a mach group. # obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o +obj-$(CONFIG_SH_SH2007) += board-sh2007.o obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o obj-$(CONFIG_SH_URQUELL) += board-urquell.o obj-$(CONFIG_SH_SHMIN) += board-shmin.o @@ -9,3 +10,4 @@ obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o obj-$(CONFIG_SH_ESPT) += board-espt.o obj-$(CONFIG_SH_POLARIS) += board-polaris.o obj-$(CONFIG_SH_TITAN) += board-titan.o +obj-$(CONFIG_SH_SH7757LCR) += board-sh7757lcr.o diff --git a/arch/sh/boards/board-sh2007.c b/arch/sh/boards/board-sh2007.c new file mode 100644 index 000000000000..b90b78f6a829 --- /dev/null +++ b/arch/sh/boards/board-sh2007.c @@ -0,0 +1,133 @@ +/* + * SH-2007 board support. + * + * Copyright (C) 2003, 2004 SUGIOKA Toshinobu + * Copyright (C) 2010 Hitoshi Mitake <mitake@dcl.info.waseda.ac.jp> + */ +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/smsc911x.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/io.h> +#include <asm/machvec.h> +#include <mach/sh2007.h> + +struct smsc911x_platform_config smc911x_info = { + .flags = SMSC911X_USE_32BIT, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct resource smsc9118_0_resources[] = { + [0] = { + .start = SMC0_BASE, + .end = SMC0_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x240), + .end = evt2irq(0x240), + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource smsc9118_1_resources[] = { + [0] = { + .start = SMC1_BASE, + .end = SMC1_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x280), + .end = evt2irq(0x280), + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smsc9118_0_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc9118_0_resources), + .resource = smsc9118_0_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct platform_device smsc9118_1_device = { + .name = "smsc911x", + .id = 1, + .num_resources = ARRAY_SIZE(smsc9118_1_resources), + .resource = smsc9118_1_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct resource cf_resources[] = { + [0] = { + .start = CF_BASE + CF_OFFSET, + .end = CF_BASE + CF_OFFSET + 0x0f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CF_BASE + CF_OFFSET + 0x206, + .end = CF_BASE + CF_OFFSET + 0x20f, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = evt2irq(0x2c0), + .end = evt2irq(0x2c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_device = { + .name = "pata_platform", + .id = 0, + .num_resources = ARRAY_SIZE(cf_resources), + .resource = cf_resources, +}; + +static struct platform_device *sh2007_devices[] __initdata = { + &smsc9118_0_device, + &smsc9118_1_device, + &cf_device, +}; + +static int __init sh2007_io_init(void) +{ + platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices)); + return 0; +} +subsys_initcall(sh2007_io_init); + +static void __init sh2007_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +/* + * Initialize the board + */ +static void __init sh2007_setup(char **cmdline_p) +{ + printk(KERN_INFO "SH-2007 Setup..."); + + /* setup wait control registers for area 5 */ + __raw_writel(CS5BCR_D, CS5BCR); + __raw_writel(CS5WCR_D, CS5WCR); + __raw_writel(CS5PCR_D, CS5PCR); + + printk(KERN_INFO " done.\n"); +} + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_sh2007 __initmv = { + .mv_setup = sh2007_setup, + .mv_name = "sh2007", + .mv_init_irq = sh2007_init_irq, +}; diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c new file mode 100644 index 000000000000..c475f1056ab4 --- /dev/null +++ b/arch/sh/boards/board-sh7757lcr.c @@ -0,0 +1,374 @@ +/* + * Renesas R0P7757LC0012RL Support. + * + * Copyright (C) 2009 - 2010 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/io.h> +#include <cpu/sh7757.h> +#include <asm/sh_eth.h> +#include <asm/heartbeat.h> + +static struct resource heartbeat_resource = { + .start = 0xffec005c, /* PUDR */ + .end = 0xffec005c, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), + .flags = HEARTBEAT_INVERTED, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* Fast Ethernet */ +static struct resource sh_eth0_resources[] = { + { + .start = 0xfef00000, + .end = 0xfef001ff, + .flags = IORESOURCE_MEM, + }, { + .start = 84, + .end = 84, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth0_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +}; + +static struct platform_device sh7757_eth0_device = { + .name = "sh-eth", + .resource = sh_eth0_resources, + .id = 0, + .num_resources = ARRAY_SIZE(sh_eth0_resources), + .dev = { + .platform_data = &sh7757_eth0_pdata, + }, +}; + +static struct resource sh_eth1_resources[] = { + { + .start = 0xfef00800, + .end = 0xfef009ff, + .flags = IORESOURCE_MEM, + }, { + .start = 84, + .end = 84, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth1_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +}; + +static struct platform_device sh7757_eth1_device = { + .name = "sh-eth", + .resource = sh_eth1_resources, + .id = 1, + .num_resources = ARRAY_SIZE(sh_eth1_resources), + .dev = { + .platform_data = &sh7757_eth1_pdata, + }, +}; + +static struct platform_device *sh7757lcr_devices[] __initdata = { + &heartbeat_device, + &sh7757_eth0_device, + &sh7757_eth1_device, +}; + +static int __init sh7757lcr_devices_setup(void) +{ + /* RGMII (PTA) */ + gpio_request(GPIO_FN_ET0_MDC, NULL); + gpio_request(GPIO_FN_ET0_MDIO, NULL); + gpio_request(GPIO_FN_ET1_MDC, NULL); + gpio_request(GPIO_FN_ET1_MDIO, NULL); + + /* ONFI (PTB, PTZ) */ + gpio_request(GPIO_FN_ON_NRE, NULL); + gpio_request(GPIO_FN_ON_NWE, NULL); + gpio_request(GPIO_FN_ON_NWP, NULL); + gpio_request(GPIO_FN_ON_NCE0, NULL); + gpio_request(GPIO_FN_ON_R_B0, NULL); + gpio_request(GPIO_FN_ON_ALE, NULL); + gpio_request(GPIO_FN_ON_CLE, NULL); + + gpio_request(GPIO_FN_ON_DQ7, NULL); + gpio_request(GPIO_FN_ON_DQ6, NULL); + gpio_request(GPIO_FN_ON_DQ5, NULL); + gpio_request(GPIO_FN_ON_DQ4, NULL); + gpio_request(GPIO_FN_ON_DQ3, NULL); + gpio_request(GPIO_FN_ON_DQ2, NULL); + gpio_request(GPIO_FN_ON_DQ1, NULL); + gpio_request(GPIO_FN_ON_DQ0, NULL); + + /* IRQ8 to 0 (PTB, PTC) */ + gpio_request(GPIO_FN_IRQ8, NULL); + gpio_request(GPIO_FN_IRQ7, NULL); + gpio_request(GPIO_FN_IRQ6, NULL); + gpio_request(GPIO_FN_IRQ5, NULL); + gpio_request(GPIO_FN_IRQ4, NULL); + gpio_request(GPIO_FN_IRQ3, NULL); + gpio_request(GPIO_FN_IRQ2, NULL); + gpio_request(GPIO_FN_IRQ1, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + /* SPI0 (PTD) */ + gpio_request(GPIO_FN_SP0_MOSI, NULL); + gpio_request(GPIO_FN_SP0_MISO, NULL); + gpio_request(GPIO_FN_SP0_SCK, NULL); + gpio_request(GPIO_FN_SP0_SCK_FB, NULL); + gpio_request(GPIO_FN_SP0_SS0, NULL); + gpio_request(GPIO_FN_SP0_SS1, NULL); + gpio_request(GPIO_FN_SP0_SS2, NULL); + gpio_request(GPIO_FN_SP0_SS3, NULL); + + /* RMII 0/1 (PTE, PTF) */ + gpio_request(GPIO_FN_RMII0_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII0_TXD1, NULL); + gpio_request(GPIO_FN_RMII0_TXD0, NULL); + gpio_request(GPIO_FN_RMII0_TXEN, NULL); + gpio_request(GPIO_FN_RMII0_REFCLK, NULL); + gpio_request(GPIO_FN_RMII0_RXD1, NULL); + gpio_request(GPIO_FN_RMII0_RXD0, NULL); + gpio_request(GPIO_FN_RMII0_RX_ER, NULL); + gpio_request(GPIO_FN_RMII1_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII1_TXD1, NULL); + gpio_request(GPIO_FN_RMII1_TXD0, NULL); + gpio_request(GPIO_FN_RMII1_TXEN, NULL); + gpio_request(GPIO_FN_RMII1_REFCLK, NULL); + gpio_request(GPIO_FN_RMII1_RXD1, NULL); + gpio_request(GPIO_FN_RMII1_RXD0, NULL); + gpio_request(GPIO_FN_RMII1_RX_ER, NULL); + + /* eMMC (PTG) */ + gpio_request(GPIO_FN_MMCCLK, NULL); + gpio_request(GPIO_FN_MMCCMD, NULL); + gpio_request(GPIO_FN_MMCDAT7, NULL); + gpio_request(GPIO_FN_MMCDAT6, NULL); + gpio_request(GPIO_FN_MMCDAT5, NULL); + gpio_request(GPIO_FN_MMCDAT4, NULL); + gpio_request(GPIO_FN_MMCDAT3, NULL); + gpio_request(GPIO_FN_MMCDAT2, NULL); + gpio_request(GPIO_FN_MMCDAT1, NULL); + gpio_request(GPIO_FN_MMCDAT0, NULL); + + /* LPC (PTG, PTH, PTQ, PTU) */ + gpio_request(GPIO_FN_SERIRQ, NULL); + gpio_request(GPIO_FN_LPCPD, NULL); + gpio_request(GPIO_FN_LDRQ, NULL); + gpio_request(GPIO_FN_WP, NULL); + gpio_request(GPIO_FN_FMS0, NULL); + gpio_request(GPIO_FN_LAD3, NULL); + gpio_request(GPIO_FN_LAD2, NULL); + gpio_request(GPIO_FN_LAD1, NULL); + gpio_request(GPIO_FN_LAD0, NULL); + gpio_request(GPIO_FN_LFRAME, NULL); + gpio_request(GPIO_FN_LRESET, NULL); + gpio_request(GPIO_FN_LCLK, NULL); + gpio_request(GPIO_FN_LGPIO7, NULL); + gpio_request(GPIO_FN_LGPIO6, NULL); + gpio_request(GPIO_FN_LGPIO5, NULL); + gpio_request(GPIO_FN_LGPIO4, NULL); + + /* SPI1 (PTH) */ + gpio_request(GPIO_FN_SP1_MOSI, NULL); + gpio_request(GPIO_FN_SP1_MISO, NULL); + gpio_request(GPIO_FN_SP1_SCK, NULL); + gpio_request(GPIO_FN_SP1_SCK_FB, NULL); + gpio_request(GPIO_FN_SP1_SS0, NULL); + gpio_request(GPIO_FN_SP1_SS1, NULL); + + /* SDHI (PTI) */ + gpio_request(GPIO_FN_SD_WP, NULL); + gpio_request(GPIO_FN_SD_CD, NULL); + gpio_request(GPIO_FN_SD_CLK, NULL); + gpio_request(GPIO_FN_SD_CMD, NULL); + gpio_request(GPIO_FN_SD_D3, NULL); + gpio_request(GPIO_FN_SD_D2, NULL); + gpio_request(GPIO_FN_SD_D1, NULL); + gpio_request(GPIO_FN_SD_D0, NULL); + + /* SCIF3/4 (PTJ, PTW) */ + gpio_request(GPIO_FN_RTS3, NULL); + gpio_request(GPIO_FN_CTS3, NULL); + gpio_request(GPIO_FN_TXD3, NULL); + gpio_request(GPIO_FN_RXD3, NULL); + gpio_request(GPIO_FN_RTS4, NULL); + gpio_request(GPIO_FN_RXD4, NULL); + gpio_request(GPIO_FN_TXD4, NULL); + gpio_request(GPIO_FN_CTS4, NULL); + + /* SERMUX (PTK, PTL, PTO, PTV) */ + gpio_request(GPIO_FN_COM2_TXD, NULL); + gpio_request(GPIO_FN_COM2_RXD, NULL); + gpio_request(GPIO_FN_COM2_RTS, NULL); + gpio_request(GPIO_FN_COM2_CTS, NULL); + gpio_request(GPIO_FN_COM2_DTR, NULL); + gpio_request(GPIO_FN_COM2_DSR, NULL); + gpio_request(GPIO_FN_COM2_DCD, NULL); + gpio_request(GPIO_FN_COM2_RI, NULL); + gpio_request(GPIO_FN_RAC_RXD, NULL); + gpio_request(GPIO_FN_RAC_RTS, NULL); + gpio_request(GPIO_FN_RAC_CTS, NULL); + gpio_request(GPIO_FN_RAC_DTR, NULL); + gpio_request(GPIO_FN_RAC_DSR, NULL); + gpio_request(GPIO_FN_RAC_DCD, NULL); + gpio_request(GPIO_FN_RAC_TXD, NULL); + gpio_request(GPIO_FN_COM1_TXD, NULL); + gpio_request(GPIO_FN_COM1_RXD, NULL); + gpio_request(GPIO_FN_COM1_RTS, NULL); + gpio_request(GPIO_FN_COM1_CTS, NULL); + + writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */ + + /* IIC (PTM, PTR, PTS) */ + gpio_request(GPIO_FN_SDA7, NULL); + gpio_request(GPIO_FN_SCL7, NULL); + gpio_request(GPIO_FN_SDA6, NULL); + gpio_request(GPIO_FN_SCL6, NULL); + gpio_request(GPIO_FN_SDA5, NULL); + gpio_request(GPIO_FN_SCL5, NULL); + gpio_request(GPIO_FN_SDA4, NULL); + gpio_request(GPIO_FN_SCL4, NULL); + gpio_request(GPIO_FN_SDA3, NULL); + gpio_request(GPIO_FN_SCL3, NULL); + gpio_request(GPIO_FN_SDA2, NULL); + gpio_request(GPIO_FN_SCL2, NULL); + gpio_request(GPIO_FN_SDA1, NULL); + gpio_request(GPIO_FN_SCL1, NULL); + gpio_request(GPIO_FN_SDA0, NULL); + gpio_request(GPIO_FN_SCL0, NULL); + + /* USB (PTN) */ + gpio_request(GPIO_FN_VBUS_EN, NULL); + gpio_request(GPIO_FN_VBUS_OC, NULL); + + /* SGPIO1/0 (PTN, PTO) */ + gpio_request(GPIO_FN_SGPIO1_CLK, NULL); + gpio_request(GPIO_FN_SGPIO1_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO1_DI, NULL); + gpio_request(GPIO_FN_SGPIO1_DO, NULL); + gpio_request(GPIO_FN_SGPIO0_CLK, NULL); + gpio_request(GPIO_FN_SGPIO0_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO0_DI, NULL); + gpio_request(GPIO_FN_SGPIO0_DO, NULL); + + /* WDT (PTN) */ + gpio_request(GPIO_FN_SUB_CLKIN, NULL); + + /* System (PTT) */ + gpio_request(GPIO_FN_STATUS1, NULL); + gpio_request(GPIO_FN_STATUS0, NULL); + + /* PWMX (PTT) */ + gpio_request(GPIO_FN_PWMX1, NULL); + gpio_request(GPIO_FN_PWMX0, NULL); + + /* R-SPI (PTV) */ + gpio_request(GPIO_FN_R_SPI_MOSI, NULL); + gpio_request(GPIO_FN_R_SPI_MISO, NULL); + gpio_request(GPIO_FN_R_SPI_RSPCK, NULL); + gpio_request(GPIO_FN_R_SPI_SSL0, NULL); + gpio_request(GPIO_FN_R_SPI_SSL1, NULL); + + /* EVC (PTV, PTW) */ + gpio_request(GPIO_FN_EVENT7, NULL); + gpio_request(GPIO_FN_EVENT6, NULL); + gpio_request(GPIO_FN_EVENT5, NULL); + gpio_request(GPIO_FN_EVENT4, NULL); + gpio_request(GPIO_FN_EVENT3, NULL); + gpio_request(GPIO_FN_EVENT2, NULL); + gpio_request(GPIO_FN_EVENT1, NULL); + gpio_request(GPIO_FN_EVENT0, NULL); + + /* LED for heartbeat */ + gpio_request(GPIO_PTU3, NULL); + gpio_direction_output(GPIO_PTU3, 1); + gpio_request(GPIO_PTU2, NULL); + gpio_direction_output(GPIO_PTU2, 1); + gpio_request(GPIO_PTU1, NULL); + gpio_direction_output(GPIO_PTU1, 1); + gpio_request(GPIO_PTU0, NULL); + gpio_direction_output(GPIO_PTU0, 1); + + /* control for MDIO of Gigabit Ethernet */ + gpio_request(GPIO_PTT4, NULL); + gpio_direction_output(GPIO_PTT4, 1); + + /* control for eMMC */ + gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */ + gpio_direction_output(GPIO_PTT7, 0); + gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */ + gpio_direction_output(GPIO_PTT6, 0); + gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ + gpio_direction_output(GPIO_PTT5, 1); + + /* General platform */ + return platform_add_devices(sh7757lcr_devices, + ARRAY_SIZE(sh7757lcr_devices)); +} +arch_initcall(sh7757lcr_devices_setup); + +/* Initialize IRQ setting */ +void __init init_sh7757lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +/* Initialize the board */ +static void __init sh7757lcr_setup(char **cmdline_p) +{ + printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n"); +} + +static int sh7757lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S3 (Low active). + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN0; /* Clock Mode: 1 */ + + return value; +} + +/* The Machine Vector */ +static struct sh_machine_vector mv_sh7757lcr __initmv = { + .mv_name = "SH7757LCR", + .mv_setup = sh7757lcr_setup, + .mv_init_irq = init_sh7757lcr_IRQ, + .mv_mode_pins = sh7757lcr_mode_pins, +}; + diff --git a/arch/sh/configs/sh2007_defconfig b/arch/sh/configs/sh2007_defconfig new file mode 100644 index 000000000000..c4927962538d --- /dev/null +++ b/arch/sh/configs/sh2007_defconfig @@ -0,0 +1,213 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_IKCONFIG=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_SLAB=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_CPU_SUBTYPE_SH7780=y +CONFIG_MEMORY_SIZE=0x08000000 +# CONFIG_VSYSCALL is not set +CONFIG_FLATMEM_MANUAL=y +CONFIG_SH_SH2007=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SH_DMA=y +CONFIG_SH_DMA_API=y +CONFIG_NR_DMA_CHANNELS_BOOL=y +CONFIG_HZ_100=y +CONFIG_CMDLINE_OVERWRITE=y +CONFIG_CMDLINE="console=ttySC1,115200 ip=dhcp root=/dev/nfs rw nfsroot=/nfs/rootfs,rsize=1024,wsize=1024 earlyprintk=sh-sci.1" +CONFIG_PCCARD=y +CONFIG_BINFMT_MISC=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NET_IPIP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PKTGEN=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=y +# CONFIG_MISC_DEVICES is not set +CONFIG_RAID_ATTRS=y +CONFIG_SCSI=y +CONFIG_SCSI_TGT=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_SCSI_FC_ATTRS=y +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_SCSI_SRP_ATTRS=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +CONFIG_EQUALIZER=y +CONFIG_TUN=y +CONFIG_VETH=y +CONFIG_NET_ETHERNET=y +CONFIG_SMSC911X=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_SH_WDT=y +CONFIG_SSB=y +CONFIG_FB=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_MON=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_DMADEVICES=y +CONFIG_TIMB_DMA=y +CONFIG_EXT3_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=932 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_INFO=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SH_STANDARD_BIOS=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_FCRYPT=y +CONFIG_CRYPTO_KHAZAD=y +CONFIG_CRYPTO_SEED=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_LIBCRC32C=y diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig new file mode 100644 index 000000000000..273f3fa198f7 --- /dev/null +++ b/arch/sh/configs/sh7757lcr_defconfig @@ -0,0 +1,85 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_CPU_SUBTYPE_SH7757=y +CONFIG_MEMORY_START=0x40000000 +CONFIG_MEMORY_SIZE=0x0f000000 +CONFIG_PMB=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_SH_SH7757LCR=y +CONFIG_HEARTBEAT=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE_OVERWRITE=y +CONFIG_CMDLINE="console=ttySC2,115200 root=/dev/nfs ip=dhcp" +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FW_LOADER is not set +CONFIG_BLK_DEV_RAM=y +# CONFIG_MISC_DEVICES is not set +CONFIG_NETDEVICES=y +CONFIG_PHYLIB=y +CONFIG_VITESSE_PHY=y +CONFIG_MDIO_BITBANG=y +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=3 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_INOTIFY=y +CONFIG_ISO9660_FS=y +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_SQUASHFS=y +CONFIG_MINIX_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_ISO8859_1=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_FTRACE is not set +# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/sh/drivers/dma/dma-api.c b/arch/sh/drivers/dma/dma-api.c index 4a277224a871..f46848f088e4 100644 --- a/arch/sh/drivers/dma/dma-api.c +++ b/arch/sh/drivers/dma/dma-api.c @@ -412,8 +412,8 @@ EXPORT_SYMBOL(unregister_dmac); static int __init dma_api_init(void) { printk(KERN_NOTICE "DMA: Registering DMA API.\n"); - create_proc_read_entry("dma", 0, 0, dma_read_proc, 0); - return 0; + return create_proc_read_entry("dma", 0, 0, dma_read_proc, 0) + ? 0 : -ENOMEM; } subsys_initcall(dma_api_init); diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c index 48f594b9582b..79a5ddae733d 100644 --- a/arch/sh/drivers/pci/ops-sh7786.c +++ b/arch/sh/drivers/pci/ops-sh7786.c @@ -1,7 +1,7 @@ /* * Generic SH7786 PCI-Express operations. * - * Copyright (C) 2009 Paul Mundt + * Copyright (C) 2009 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License v2. See the file "COPYING" in the main directory of this archive @@ -25,32 +25,39 @@ static int sh7786_pcie_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 *data) { struct pci_channel *chan = bus->sysdata; - int dev, func; + int dev, func, type; dev = PCI_SLOT(devfn); func = PCI_FUNC(devfn); + type = !!bus->parent; if (bus->number > 255 || dev > 31 || func > 7) return PCIBIOS_FUNC_NOT_SUPPORTED; - if (devfn) + if (bus->parent == NULL && dev) return PCIBIOS_DEVICE_NOT_FOUND; + /* Clear errors */ + pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR); + /* Set the PIO address */ pci_write_reg(chan, (bus->number << 24) | (dev << 19) | (func << 16) | (where & ~3), SH4A_PCIEPAR); /* Enable the configuration access */ - pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR); + pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR); + + /* Check for errors */ + if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10) + return PCIBIOS_DEVICE_NOT_FOUND; + /* Check for master and target aborts */ + if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28))) + return PCIBIOS_DEVICE_NOT_FOUND; if (access_type == PCI_ACCESS_READ) *data = pci_read_reg(chan, SH4A_PCIEPDR); else pci_write_reg(chan, *data, SH4A_PCIEPDR); - /* Check for master and target aborts */ - if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28))) - return PCIBIOS_DEVICE_NOT_FOUND; - return PCIBIOS_SUCCESSFUL; } @@ -69,8 +76,10 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn, spin_lock_irqsave(&sh7786_pcie_lock, flags); ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (ret != PCIBIOS_SUCCESSFUL) + if (ret != PCIBIOS_SUCCESSFUL) { + *val = 0xffffffff; goto out; + } if (size == 1) *val = (data >> ((where & 3) << 3)) & 0xff; diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c index f98141b3b7d7..86adb1e235cd 100644 --- a/arch/sh/drivers/pci/pci-sh7751.c +++ b/arch/sh/drivers/pci/pci-sh7751.c @@ -81,7 +81,7 @@ static int __init sh7751_pci_init(void) unsigned int id; u32 word, reg; - printk(KERN_NOTICE "PCI: Starting intialization.\n"); + printk(KERN_NOTICE "PCI: Starting initialization.\n"); chan->reg_base = 0xfe200000; diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c index ffdcbf10b95e..edb7cca14882 100644 --- a/arch/sh/drivers/pci/pci-sh7780.c +++ b/arch/sh/drivers/pci/pci-sh7780.c @@ -246,7 +246,7 @@ static int __init sh7780_pci_init(void) const char *type; int ret, i; - printk(KERN_NOTICE "PCI: Starting intialization.\n"); + printk(KERN_NOTICE "PCI: Starting initialization.\n"); chan->reg_base = 0xfe040000; diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 68cb9b0ac9d2..d053ffca8196 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -148,16 +148,11 @@ static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) static void phy_write_reg(struct pci_channel *chan, unsigned int addr, unsigned int lane, unsigned int data) { - unsigned long phyaddr, ctrl; + unsigned long phyaddr; phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + ((addr & 0xff) << BITS_ADR); - /* Enable clock */ - ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); - ctrl |= (1 << BITS_CKE); - pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); - /* Set write data */ pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); @@ -165,20 +160,22 @@ static void phy_write_reg(struct pci_channel *chan, unsigned int addr, phy_wait_for_ack(chan); /* Clear command */ + pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR); pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); phy_wait_for_ack(chan); - - /* Disable clock */ - ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); - ctrl &= ~(1 << BITS_CKE); - pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); } static int phy_init(struct pci_channel *chan) { + unsigned long ctrl; unsigned int timeout = 100; + /* Enable clock */ + ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); + ctrl |= (1 << BITS_CKE); + pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); + /* Initialize the phy */ phy_write_reg(chan, 0x60, 0xf, 0x004b008b); phy_write_reg(chan, 0x61, 0xf, 0x00007b41); @@ -187,9 +184,15 @@ static int phy_init(struct pci_channel *chan) phy_write_reg(chan, 0x66, 0xf, 0x00000010); phy_write_reg(chan, 0x74, 0xf, 0x0007001c); phy_write_reg(chan, 0x79, 0xf, 0x01fc000d); + phy_write_reg(chan, 0xb0, 0xf, 0x00000610); /* Deassert Standby */ - phy_write_reg(chan, 0x67, 0xf, 0x00000400); + phy_write_reg(chan, 0x67, 0x1, 0x00000400); + + /* Disable clock */ + ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); + ctrl &= ~(1 << BITS_CKE); + pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); while (timeout--) { if (pci_read_reg(chan, SH4A_PCIEPHYSR)) @@ -287,6 +290,9 @@ static int pcie_init(struct sh7786_pcie_port *port) __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0); __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0); + __raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4); + __raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5); + /* Finish initialization */ data = pci_read_reg(chan, SH4A_PCIETCTLR); data |= 0x1; @@ -392,7 +398,7 @@ static int __init sh7786_pcie_init(void) { int ret = 0, i; - printk(KERN_NOTICE "PCI: Starting intialization.\n"); + printk(KERN_NOTICE "PCI: Starting initialization.\n"); sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops; diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild index 0eed47b236ab..7beb42322f60 100644 --- a/arch/sh/include/asm/Kbuild +++ b/arch/sh/include/asm/Kbuild @@ -5,5 +5,7 @@ header-y += cpu-features.h header-y += hw_breakpoint.h header-y += posix_types_32.h header-y += posix_types_64.h +header-y += ptrace_32.h +header-y += ptrace_64.h header-y += unistd_32.h header-y += unistd_64.h diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h index ce830faeebbf..f38112be67d2 100644 --- a/arch/sh/include/asm/elf.h +++ b/arch/sh/include/asm/elf.h @@ -50,25 +50,14 @@ #define R_SH_GOTPC 167 /* FDPIC relocs */ -#define R_SH_GOT20 70 -#define R_SH_GOTOFF20 71 -#define R_SH_GOTFUNCDESC 72 -#define R_SH_GOTFUNCDESC20 73 -#define R_SH_GOTOFFFUNCDESC 74 -#define R_SH_GOTOFFFUNCDESC20 75 -#define R_SH_FUNCDESC 76 -#define R_SH_FUNCDESC_VALUE 77 - -#if 0 /* XXX - later .. */ -#define R_SH_GOT20 198 -#define R_SH_GOTOFF20 199 -#define R_SH_GOTFUNCDESC 200 -#define R_SH_GOTFUNCDESC20 201 -#define R_SH_GOTOFFFUNCDESC 202 -#define R_SH_GOTOFFFUNCDESC20 203 -#define R_SH_FUNCDESC 204 -#define R_SH_FUNCDESC_VALUE 205 -#endif +#define R_SH_GOT20 201 +#define R_SH_GOTOFF20 202 +#define R_SH_GOTFUNCDESC 203 +#define R_SH_GOTFUNCDESC20 204 +#define R_SH_GOTOFFFUNCDESC 205 +#define R_SH_GOTOFFFUNCDESC20 206 +#define R_SH_FUNCDESC 207 +#define R_SH_FUNCDESC_VALUE 208 /* SHmedia relocs */ #define R_SH_IMM_LOW16 246 diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h index 6e7cea453895..bd7e79a12653 100644 --- a/arch/sh/include/asm/fixmap.h +++ b/arch/sh/include/asm/fixmap.h @@ -58,7 +58,7 @@ enum fixed_addresses { #ifdef CONFIG_HIGHMEM FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ - FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, + FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1, #endif #ifdef CONFIG_IOREMAP_FIXED @@ -69,7 +69,7 @@ enum fixed_addresses { */ #define FIX_N_IOREMAPS 32 FIX_IOREMAP_BEGIN, - FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS, + FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS - 1, #endif __end_of_fixed_addresses diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h index 02c2f0102cfa..45d08b6a5ef7 100644 --- a/arch/sh/include/asm/irq.h +++ b/arch/sh/include/asm/irq.h @@ -9,7 +9,7 @@ * advised to cap this at the hard limit that they're interested in * through the machvec. */ -#define NR_IRQS 256 +#define NR_IRQS 512 #define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */ /* diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h index 036c3311233c..134f3980e44a 100644 --- a/arch/sh/include/asm/kprobes.h +++ b/arch/sh/include/asm/kprobes.h @@ -16,7 +16,6 @@ typedef insn_size_t kprobe_opcode_t; ? (MAX_STACK_SIZE) \ : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) -#define regs_return_value(_regs) ((_regs)->regs[0]) #define flush_insn_slot(p) do { } while (0) #define kretprobe_blacklist_size 0 diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h index 61a445d2d02a..46d5179c9f49 100644 --- a/arch/sh/include/asm/processor_32.h +++ b/arch/sh/include/asm/processor_32.h @@ -13,7 +13,6 @@ #include <linux/linkage.h> #include <asm/page.h> #include <asm/types.h> -#include <asm/ptrace.h> #include <asm/hw_breakpoint.h> /* @@ -194,8 +193,6 @@ extern unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15]) -#define user_stack_pointer(_regs) ((_regs)->regs[15]) - #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4) #define PREFETCH_STRIDE L1_CACHE_BYTES #define ARCH_HAS_PREFETCH diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h index 621bc4618c6b..2a541ddb5a1b 100644 --- a/arch/sh/include/asm/processor_64.h +++ b/arch/sh/include/asm/processor_64.h @@ -17,7 +17,6 @@ #include <linux/compiler.h> #include <asm/page.h> #include <asm/types.h> -#include <asm/ptrace.h> #include <cpu/registers.h> /* @@ -231,7 +230,5 @@ extern unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) ((tsk)->thread.pc) #define KSTK_ESP(tsk) ((tsk)->thread.sp) -#define user_stack_pointer(_regs) ((_regs)->regs[15]) - #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_PROCESSOR_64_H */ diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h index 2168fde25611..f6edc10aa0d3 100644 --- a/arch/sh/include/asm/ptrace.h +++ b/arch/sh/include/asm/ptrace.h @@ -3,90 +3,7 @@ /* * Copyright (C) 1999, 2000 Niibe Yutaka - * - */ -#if defined(__SH5__) -struct pt_regs { - unsigned long long pc; - unsigned long long sr; - long long syscall_nr; - unsigned long long regs[63]; - unsigned long long tregs[8]; - unsigned long long pad[2]; -}; -#else -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 15 are integer registers - * 17 - 22 are control/special registers - * 24 - 39 fp registers - * 40 - 47 xd registers - * 48 - fpscr register - * ----------------------------- - * - * We follows above, except: - * 16 --- program counter (PC) - * 22 --- syscall # - * 23 --- floating point communication register */ -#define REG_REG0 0 -#define REG_REG15 15 - -#define REG_PC 16 - -#define REG_PR 17 -#define REG_SR 18 -#define REG_GBR 19 -#define REG_MACH 20 -#define REG_MACL 21 - -#define REG_SYSCALL 22 - -#define REG_FPREG0 23 -#define REG_FPREG15 38 -#define REG_XFREG0 39 -#define REG_XFREG15 54 - -#define REG_FPSCR 55 -#define REG_FPUL 56 - -/* - * This struct defines the way the registers are stored on the - * kernel stack during a system call or other kernel entry. - */ -struct pt_regs { - unsigned long regs[16]; - unsigned long pc; - unsigned long pr; - unsigned long sr; - unsigned long gbr; - unsigned long mach; - unsigned long macl; - long tra; -}; - -/* - * This struct defines the way the DSP registers are stored on the - * kernel stack during a system call or other kernel entry. - */ -struct pt_dspregs { - unsigned long a1; - unsigned long a0g; - unsigned long a1g; - unsigned long m0; - unsigned long m1; - unsigned long a0; - unsigned long x0; - unsigned long x1; - unsigned long y0; - unsigned long y1; - unsigned long dsr; - unsigned long rs; - unsigned long re; - unsigned long mod; -}; -#endif #define PTRACE_GETREGS 12 /* General registers */ #define PTRACE_SETREGS 13 @@ -107,22 +24,102 @@ struct pt_dspregs { #define PT_DATA_ADDR 248 /* &(struct user)->start_data */ #define PT_TEXT_LEN 252 +#if defined(__SH5__) || defined(CONFIG_CPU_SH5) +#include "ptrace_64.h" +#else +#include "ptrace_32.h" +#endif + #ifdef __KERNEL__ + +#include <linux/stringify.h> +#include <linux/stddef.h> +#include <linux/thread_info.h> #include <asm/addrspace.h> #include <asm/page.h> #include <asm/system.h> #define user_mode(regs) (((regs)->sr & 0x40000000)==0) +#define user_stack_pointer(regs) ((unsigned long)(regs)->regs[15]) +#define kernel_stack_pointer(regs) ((unsigned long)(regs)->regs[15]) #define instruction_pointer(regs) ((unsigned long)(regs)->pc) extern void show_regs(struct pt_regs *); +#define arch_has_single_step() (1) + /* - * These are defined as per linux/ptrace.h. + * kprobe-based event tracer support */ -struct task_struct; +struct pt_regs_offset { + const char *name; + int offset; +}; -#define arch_has_single_step() (1) +#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} +#define REGS_OFFSET_NAME(num) \ + {.name = __stringify(r##num), .offset = offsetof(struct pt_regs, regs[num])} +#define TREGS_OFFSET_NAME(num) \ + {.name = __stringify(tr##num), .offset = offsetof(struct pt_regs, tregs[num])} +#define REG_OFFSET_END {.name = NULL, .offset = 0} + +/* Query offset/name of register from its name/offset */ +extern int regs_query_register_offset(const char *name); +extern const char *regs_query_register_name(unsigned int offset); + +extern const struct pt_regs_offset regoffset_table[]; + +/** + * regs_get_register() - get register value from its offset + * @regs: pt_regs from which register value is gotten. + * @offset: offset number of the register. + * + * regs_get_register returns the value of a register. The @offset is the + * offset of the register in struct pt_regs address which specified by @regs. + * If @offset is bigger than MAX_REG_OFFSET, this returns 0. + */ +static inline unsigned long regs_get_register(struct pt_regs *regs, + unsigned int offset) +{ + if (unlikely(offset > MAX_REG_OFFSET)) + return 0; + return *(unsigned long *)((unsigned long)regs + offset); +} + +/** + * regs_within_kernel_stack() - check the address in the stack + * @regs: pt_regs which contains kernel stack pointer. + * @addr: address which is checked. + * + * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). + * If @addr is within the kernel stack, it returns true. If not, returns false. + */ +static inline int regs_within_kernel_stack(struct pt_regs *regs, + unsigned long addr) +{ + return ((addr & ~(THREAD_SIZE - 1)) == + (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); +} + +/** + * regs_get_kernel_stack_nth() - get Nth entry of the stack + * @regs: pt_regs which contains kernel stack pointer. + * @n: stack entry number. + * + * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which + * is specified by @regs. If the @n th entry is NOT in the kernel stack, + * this returns 0. + */ +static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, + unsigned int n) +{ + unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); + addr += n; + if (regs_within_kernel_stack(regs, (unsigned long)addr)) + return *addr; + else + return 0; +} struct perf_event; struct perf_sample_data; diff --git a/arch/sh/include/asm/ptrace_32.h b/arch/sh/include/asm/ptrace_32.h new file mode 100644 index 000000000000..35d9e257558c --- /dev/null +++ b/arch/sh/include/asm/ptrace_32.h @@ -0,0 +1,83 @@ +#ifndef __ASM_SH_PTRACE_32_H +#define __ASM_SH_PTRACE_32_H + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 15 are integer registers + * 17 - 22 are control/special registers + * 24 - 39 fp registers + * 40 - 47 xd registers + * 48 - fpscr register + * ----------------------------- + * + * We follows above, except: + * 16 --- program counter (PC) + * 22 --- syscall # + * 23 --- floating point communication register + */ +#define REG_REG0 0 +#define REG_REG15 15 + +#define REG_PC 16 + +#define REG_PR 17 +#define REG_SR 18 +#define REG_GBR 19 +#define REG_MACH 20 +#define REG_MACL 21 + +#define REG_SYSCALL 22 + +#define REG_FPREG0 23 +#define REG_FPREG15 38 +#define REG_XFREG0 39 +#define REG_XFREG15 54 + +#define REG_FPSCR 55 +#define REG_FPUL 56 + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_regs { + unsigned long regs[16]; + unsigned long pc; + unsigned long pr; + unsigned long sr; + unsigned long gbr; + unsigned long mach; + unsigned long macl; + long tra; +}; + +/* + * This struct defines the way the DSP registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_dspregs { + unsigned long a1; + unsigned long a0g; + unsigned long a1g; + unsigned long m0; + unsigned long m1; + unsigned long a0; + unsigned long x0; + unsigned long x1; + unsigned long y0; + unsigned long y1; + unsigned long dsr; + unsigned long rs; + unsigned long re; + unsigned long mod; +}; + +#ifdef __KERNEL__ + +#define MAX_REG_OFFSET offsetof(struct pt_regs, tra) +#define regs_return_value(regs) ((regs)->regs[0]) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_PTRACE_32_H */ diff --git a/arch/sh/include/asm/ptrace_64.h b/arch/sh/include/asm/ptrace_64.h new file mode 100644 index 000000000000..d43c1cb0bbe7 --- /dev/null +++ b/arch/sh/include/asm/ptrace_64.h @@ -0,0 +1,20 @@ +#ifndef __ASM_SH_PTRACE_64_H +#define __ASM_SH_PTRACE_64_H + +struct pt_regs { + unsigned long long pc; + unsigned long long sr; + long long syscall_nr; + unsigned long long regs[63]; + unsigned long long tregs[8]; + unsigned long long pad[2]; +}; + +#ifdef __KERNEL__ + +#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7]) +#define regs_return_value(regs) ((regs)->regs[3]) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_PTRACE_64_H */ diff --git a/arch/sh/include/asm/syscalls_32.h b/arch/sh/include/asm/syscalls_32.h index be201fdc97aa..ae717e3c26d6 100644 --- a/arch/sh/include/asm/syscalls_32.h +++ b/arch/sh/include/asm/syscalls_32.h @@ -19,9 +19,10 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp, asmlinkage int sys_vfork(unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7, struct pt_regs __regs); -asmlinkage int sys_execve(const char __user *ufilename, char __user * __user *uargv, - char __user * __user *uenvp, unsigned long r7, - struct pt_regs __regs); +asmlinkage int sys_execve(const char __user *ufilename, + const char __user *const __user *uargv, + const char __user *const __user *uenvp, + unsigned long r7, struct pt_regs __regs); asmlinkage int sys_sigsuspend(old_sigset_t mask, unsigned long r5, unsigned long r6, unsigned long r7, struct pt_regs __regs); diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h index 51296b36770e..9bd2684f908e 100644 --- a/arch/sh/include/asm/system_32.h +++ b/arch/sh/include/asm/system_32.h @@ -216,13 +216,12 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, static inline void trigger_address_error(void) { - if (__in_29bit_mode()) - __asm__ __volatile__ ( - "ldc %0, sr\n\t" - "mov.l @%1, %0" - : - : "r" (0x10000000), "r" (0x80000001) - ); + __asm__ __volatile__ ( + "ldc %0, sr\n\t" + "mov.l @%1, %0" + : + : "r" (0x10000000), "r" (0x80000001) + ); } asmlinkage void do_address_error(struct pt_regs *regs, diff --git a/arch/sh/include/asm/tlbflush.h b/arch/sh/include/asm/tlbflush.h index e0ac97221ae6..0df66f0c7284 100644 --- a/arch/sh/include/asm/tlbflush.h +++ b/arch/sh/include/asm/tlbflush.h @@ -21,6 +21,8 @@ extern void local_flush_tlb_kernel_range(unsigned long start, unsigned long end); extern void local_flush_tlb_one(unsigned long asid, unsigned long page); +extern void __flush_tlb_global(void); + #ifdef CONFIG_SMP extern void flush_tlb_all(void); diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h index 0e7f0fc8f086..01183add5687 100644 --- a/arch/sh/include/asm/unistd_32.h +++ b/arch/sh/include/asm/unistd_32.h @@ -345,8 +345,11 @@ #define __NR_pwritev 334 #define __NR_rt_tgsigqueueinfo 335 #define __NR_perf_event_open 336 +#define __NR_fanotify_init 337 +#define __NR_fanotify_mark 338 +#define __NR_prlimit64 339 -#define NR_syscalls 337 +#define NR_syscalls 340 #ifdef __KERNEL__ diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h index 0580c33a1e04..09aa93f9eb70 100644 --- a/arch/sh/include/asm/unistd_64.h +++ b/arch/sh/include/asm/unistd_64.h @@ -387,10 +387,13 @@ #define __NR_perf_event_open 364 #define __NR_recvmmsg 365 #define __NR_accept4 366 +#define __NR_fanotify_init 367 +#define __NR_fanotify_mark 368 +#define __NR_prlimit64 369 #ifdef __KERNEL__ -#define NR_syscalls 367 +#define NR_syscalls 370 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h index f4d267efad71..15f3de11c55a 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7757.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h @@ -3,241 +3,252 @@ enum { /* PTA */ - GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, - GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0, + GPIO_PTA0, GPIO_PTA1, GPIO_PTA2, GPIO_PTA3, + GPIO_PTA4, GPIO_PTA5, GPIO_PTA6, GPIO_PTA7, /* PTB */ - GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4, - GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0, + GPIO_PTB0, GPIO_PTB1, GPIO_PTB2, GPIO_PTB3, + GPIO_PTB4, GPIO_PTB5, GPIO_PTB6, GPIO_PTB7, /* PTC */ - GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4, - GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0, + GPIO_PTC0, GPIO_PTC1, GPIO_PTC2, GPIO_PTC3, + GPIO_PTC4, GPIO_PTC5, GPIO_PTC6, GPIO_PTC7, /* PTD */ - GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4, - GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0, + GPIO_PTD0, GPIO_PTD1, GPIO_PTD2, GPIO_PTD3, + GPIO_PTD4, GPIO_PTD5, GPIO_PTD6, GPIO_PTD7, /* PTE */ - GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, - GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0, + GPIO_PTE0, GPIO_PTE1, GPIO_PTE2, GPIO_PTE3, + GPIO_PTE4, GPIO_PTE5, GPIO_PTE6, GPIO_PTE7, /* PTF */ - GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, - GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, + GPIO_PTF0, GPIO_PTF1, GPIO_PTF2, GPIO_PTF3, + GPIO_PTF4, GPIO_PTF5, GPIO_PTF6, GPIO_PTF7, /* PTG */ - GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4, - GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0, + GPIO_PTG0, GPIO_PTG1, GPIO_PTG2, GPIO_PTG3, + GPIO_PTG4, GPIO_PTG5, GPIO_PTG6, GPIO_PTG7, /* PTH */ - GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, - GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0, + GPIO_PTH0, GPIO_PTH1, GPIO_PTH2, GPIO_PTH3, + GPIO_PTH4, GPIO_PTH5, GPIO_PTH6, GPIO_PTH7, /* PTI */ - GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4, - GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0, + GPIO_PTI0, GPIO_PTI1, GPIO_PTI2, GPIO_PTI3, + GPIO_PTI4, GPIO_PTI5, GPIO_PTI6, GPIO_PTI7, /* PTJ */ - GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4, - GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0, + GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3, + GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6, GPIO_PTJ7_RESV, /* PTK */ - GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4, - GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0, + GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3, + GPIO_PTK4, GPIO_PTK5, GPIO_PTK6, GPIO_PTK7, /* PTL */ - GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, - GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0, + GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3, + GPIO_PTL4, GPIO_PTL5, GPIO_PTL6, GPIO_PTL7_RESV, /* PTM */ - GPIO_PTM6, GPIO_PTM5, GPIO_PTM4, - GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0, + GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3, + GPIO_PTM4, GPIO_PTM5, GPIO_PTM6, GPIO_PTM7, /* PTN */ - GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4, - GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0, + GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3, + GPIO_PTN4, GPIO_PTN5, GPIO_PTN6, GPIO_PTN7_RESV, /* PTO */ - GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4, - GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0, + GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3, + GPIO_PTO4, GPIO_PTO5, GPIO_PTO6, GPIO_PTO7, /* PTP */ - GPIO_PTP6, GPIO_PTP5, GPIO_PTP4, - GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0, + GPIO_PTP0, GPIO_PTP1, GPIO_PTP2, GPIO_PTP3, + GPIO_PTP4, GPIO_PTP5, GPIO_PTP6, GPIO_PTP7, /* PTQ */ - GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4, - GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0, + GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3, + GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6, GPIO_PTQ7_RESV, /* PTR */ - GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4, - GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0, + GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3, + GPIO_PTR4, GPIO_PTR5, GPIO_PTR6, GPIO_PTR7, /* PTS */ - GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4, - GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0, + GPIO_PTS0, GPIO_PTS1, GPIO_PTS2, GPIO_PTS3, + GPIO_PTS4, GPIO_PTS5, GPIO_PTS6, GPIO_PTS7, /* PTT */ - GPIO_PTT5, GPIO_PTT4, - GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0, + GPIO_PTT0, GPIO_PTT1, GPIO_PTT2, GPIO_PTT3, + GPIO_PTT4, GPIO_PTT5, GPIO_PTT6, GPIO_PTT7, /* PTU */ - GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4, - GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0, + GPIO_PTU0, GPIO_PTU1, GPIO_PTU2, GPIO_PTU3, + GPIO_PTU4, GPIO_PTU5, GPIO_PTU6, GPIO_PTU7, /* PTV */ - GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4, - GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0, + GPIO_PTV0, GPIO_PTV1, GPIO_PTV2, GPIO_PTV3, + GPIO_PTV4, GPIO_PTV5, GPIO_PTV6, GPIO_PTV7, /* PTW */ - GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4, - GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0, + GPIO_PTW0, GPIO_PTW1, GPIO_PTW2, GPIO_PTW3, + GPIO_PTW4, GPIO_PTW5, GPIO_PTW6, GPIO_PTW7, /* PTX */ - GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4, - GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0, + GPIO_PTX0, GPIO_PTX1, GPIO_PTX2, GPIO_PTX3, + GPIO_PTX4, GPIO_PTX5, GPIO_PTX6, GPIO_PTX7, /* PTY */ - GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4, - GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0, + GPIO_PTY0, GPIO_PTY1, GPIO_PTY2, GPIO_PTY3, + GPIO_PTY4, GPIO_PTY5, GPIO_PTY6, GPIO_PTY7, /* PTZ */ - GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4, - GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0, + GPIO_PTZ0, GPIO_PTZ1, GPIO_PTZ2, GPIO_PTZ3, + GPIO_PTZ4, GPIO_PTZ5, GPIO_PTZ6, GPIO_PTZ7, - /* PTA (mobule: LBSC, CPG, LPC) */ + /* PTA (mobule: LBSC, RGMII) */ GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY, - GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8, - GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4, - GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0, - - /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ - GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, - GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, - GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO, - GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO, - GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST, - GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ, - GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL, + GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO, + GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO, - /* PTC (mobule: SD) */ - GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD, - GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0, + /* PTB (mobule: INTC, ONFI, TMU) */ + GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12, + GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8, + GPIO_FN_ON_NRE, GPIO_FN_ON_NWE, GPIO_FN_ON_NWP, GPIO_FN_ON_NCE0, + GPIO_FN_ON_R_B0, GPIO_FN_ON_ALE, GPIO_FN_ON_CLE, + GPIO_FN_TCLK, - /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + /* PTC (mobule: IRQ, PWMU) */ GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4, GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0, - GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2, - GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0, - - /* PTE (mobule: EtherC) */ - GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1, - GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN, - GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1, - GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER, - - /* PTF (mobule: EtherC) */ - GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1, - GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN, - GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1, - GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER, - - /* PTG (mobule: SYSTEM, PWMX, LPC) */ - GPIO_FN_STATUS0, GPIO_FN_STATUS1, - GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3, - GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ, - - /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ - GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4, + GPIO_FN_PWMU0, GPIO_FN_PWMU1, GPIO_FN_PWMU2, GPIO_FN_PWMU3, + GPIO_FN_PWMU4, GPIO_FN_PWMU5, + + /* PTD (mobule: SPI0, DMAC) */ + GPIO_FN_SP0_MOSI, GPIO_FN_SP0_MISO, GPIO_FN_SP0_SCK, + GPIO_FN_SP0_SCK_FB, GPIO_FN_SP0_SS0, GPIO_FN_SP0_SS1, + GPIO_FN_SP0_SS2, GPIO_FN_SP0_SS3, GPIO_FN_DREQ0, + GPIO_FN_DACK0, GPIO_FN_TEND0, + + /* PTE (mobule: RMII) */ + GPIO_FN_RMII0_CRS_DV, GPIO_FN_RMII0_TXD1, GPIO_FN_RMII0_TXD0, + GPIO_FN_RMII0_TXEN, GPIO_FN_RMII0_REFCLK, GPIO_FN_RMII0_RXD1, + GPIO_FN_RMII0_RXD0, GPIO_FN_RMII0_RX_ER, + + /* PTF (mobule: RMII, SerMux) */ + GPIO_FN_RMII1_CRS_DV, GPIO_FN_RMII1_TXD1, GPIO_FN_RMII1_TXD0, + GPIO_FN_RMII1_TXEN, GPIO_FN_RMII1_REFCLK, GPIO_FN_RMII1_RXD1, + GPIO_FN_RMII1_RXD0, GPIO_FN_RMII1_RX_ER, GPIO_FN_RAC_RI, + + /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ + GPIO_FN_BOOTFMS, GPIO_FN_BOOTWP, + GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_SERIRQ, GPIO_FN_WDTOVF, + GPIO_FN_LPCPD, GPIO_FN_LDRQ, GPIO_FN_MMCCLK, GPIO_FN_MMCCMD, + + /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO, GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB, GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1, - GPIO_FN_SP0_SS1, - - /* PTI (mobule: INTC) */ - GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12, - GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8, - - /* PTJ (mobule: SCIF234, SERMUX) */ - GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2, - GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD, - GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS, - - /* PTK (mobule: SERMUX) */ - GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, - GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS, - GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR, - GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI, + GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_TEND1, GPIO_FN_DREQ1, + GPIO_FN_DACK1, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0, - /* PTL (mobule: SERMUX) */ - GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD, - GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS, - GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, - GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI, + /* PTI (mobule: LBSC, SDHI) */ + GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, + GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, + GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD, + GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0, - /* PTM (mobule: IIC, LPC) */ + /* PTJ (mobule: SCIF234) */ + GPIO_FN_RTS3, GPIO_FN_CTS3, GPIO_FN_TXD3, GPIO_FN_RXD3, + GPIO_FN_RTS4, GPIO_FN_RXD4, GPIO_FN_TXD4, + + /* PTK (mobule: SERMUX, LBSC, SCIF) */ + GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, GPIO_FN_COM2_RTS, + GPIO_FN_COM2_CTS, GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR, + GPIO_FN_COM2_DCD, GPIO_FN_CLKOUT, + GPIO_FN_SCK2, GPIO_FN_SCK4, GPIO_FN_SCK3, + + /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ + GPIO_FN_RAC_RXD, GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS, + GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, GPIO_FN_RAC_DCD, + GPIO_FN_RAC_TXD, GPIO_FN_RXD2, GPIO_FN_CS5, + GPIO_FN_CS6, GPIO_FN_AUDSYNC, GPIO_FN_AUDCK, + GPIO_FN_TXD2, + + /* PTM (mobule: LBSC, IIC) */ + GPIO_FN_CS4, GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_CS0, GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7, - GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1, - - /* PTN (mobule: SCIF234, EVC) */ - GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2, - GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2, - GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4, - GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0, - /* PTO (mobule: SGPIO) */ - GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, - GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO, - GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, - GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO, + /* PTN (mobule: USB, JMC, SGPIO, WDT) */ + GPIO_FN_VBUS_EN, GPIO_FN_VBUS_OC, GPIO_FN_JMCTCK, + GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI, + GPIO_FN_JMCTRST, + GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, GPIO_FN_SGPIO1_DI, + GPIO_FN_SGPIO1_DO, GPIO_FN_SUB_CLKIN, - /* PTP (mobule: JMC, SCIF234) */ - GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI, - GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3, + /* PTO (mobule: SGPIO, SerMux) */ + GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, GPIO_FN_SGPIO0_DI, + GPIO_FN_SGPIO0_DO, GPIO_FN_SGPIO2_CLK, GPIO_FN_SGPIO2_LOAD, + GPIO_FN_SGPIO2_DI, GPIO_FN_SGPIO2_DO, GPIO_FN_COM1_TXD, + GPIO_FN_COM1_RXD, GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS, /* PTQ (mobule: LPC) */ GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0, GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK, /* PTR (mobule: GRA, IIC) */ - GPIO_FN_DDC3, GPIO_FN_DDC2, - GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2, + GPIO_FN_DDC3, GPIO_FN_DDC2, GPIO_FN_SDA2, GPIO_FN_SCL2, GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0, + GPIO_FN_SDA8, GPIO_FN_SCL8, /* PTS (mobule: GRA, IIC) */ - GPIO_FN_DDC1, GPIO_FN_DDC0, - GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5, + GPIO_FN_DDC1, GPIO_FN_DDC0, GPIO_FN_SDA5, GPIO_FN_SCL5, GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3, + GPIO_FN_SDA9, GPIO_FN_SCL9, - /* PTT (mobule: SYSTEM, PWMX) */ - GPIO_FN_AUDSYNC, GPIO_FN_AUDCK, - GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, - GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, - GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4, + /* PTT (mobule: PWMX, AUD) */ + GPIO_FN_PWMX7, GPIO_FN_PWMX6, GPIO_FN_PWMX5, GPIO_FN_PWMX4, + GPIO_FN_PWMX3, GPIO_FN_PWMX2, GPIO_FN_PWMX1, GPIO_FN_PWMX0, + GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, + GPIO_FN_AUDATA0, GPIO_FN_STATUS1, GPIO_FN_STATUS0, - /* PTU (mobule: LBSC, DMAC) */ - GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0, - GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24, - GPIO_FN_DREQ0, GPIO_FN_DACK0, + /* PTU (mobule: LPC, APM) */ + GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4, + GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0, + GPIO_FN_APMONCTL_O, GPIO_FN_APMPWBTOUT_O, GPIO_FN_APMSCI_O, + GPIO_FN_APMVDDON, GPIO_FN_APMSLPBTN, GPIO_FN_APMPWRBTN, + GPIO_FN_APMS5N, GPIO_FN_APMS3N, - /* PTV (mobule: LBSC, DMAC) */ + /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, - GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1, + GPIO_FN_COM2_RI, GPIO_FN_R_SPI_MOSI, GPIO_FN_R_SPI_MISO, + GPIO_FN_R_SPI_RSPCK, GPIO_FN_R_SPI_SSL0, GPIO_FN_R_SPI_SSL1, + GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_VBIOS_DI, + GPIO_FN_VBIOS_DO, GPIO_FN_VBIOS_CLK, GPIO_FN_VBIOS_CS, - /* PTW (mobule: LBSC) */ + /* PTW (mobule: LBSC, EVC, SCIF) */ GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, + GPIO_FN_EVENT5, GPIO_FN_EVENT4, GPIO_FN_EVENT3, GPIO_FN_EVENT2, + GPIO_FN_EVENT1, GPIO_FN_EVENT0, GPIO_FN_CTS4, GPIO_FN_CTS2, - /* PTX (mobule: LBSC) */ + /* PTX (mobule: LBSC, SCIF, SIM) */ GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, + GPIO_FN_RTS2, GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST, /* PTY (mobule: LBSC) */ GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, + + /* PTZ (mobule: eMMC, ONFI) */ + GPIO_FN_MMCDAT7, GPIO_FN_MMCDAT6, GPIO_FN_MMCDAT5, + GPIO_FN_MMCDAT4, GPIO_FN_MMCDAT3, GPIO_FN_MMCDAT2, + GPIO_FN_MMCDAT1, GPIO_FN_MMCDAT0, + GPIO_FN_ON_DQ7, GPIO_FN_ON_DQ6, GPIO_FN_ON_DQ5, GPIO_FN_ON_DQ4, + GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0, }; #endif /* __ASM_SH7757_H__ */ diff --git a/arch/sh/include/mach-common/mach/sh2007.h b/arch/sh/include/mach-common/mach/sh2007.h new file mode 100644 index 000000000000..48180b9aa03d --- /dev/null +++ b/arch/sh/include/mach-common/mach/sh2007.h @@ -0,0 +1,117 @@ +#ifndef __MACH_SH2007_H +#define __MACH_SH2007_H + +#define CS5BCR 0xff802050 +#define CS5WCR 0xff802058 +#define CS5PCR 0xff802070 + +#define BUS_SZ8 1 +#define BUS_SZ16 2 +#define BUS_SZ32 3 + +#define PCMCIA_IODYN 1 +#define PCMCIA_ATA 0 +#define PCMCIA_IO8 2 +#define PCMCIA_IO16 3 +#define PCMCIA_COMM8 4 +#define PCMCIA_COMM16 5 +#define PCMCIA_ATTR8 6 +#define PCMCIA_ATTR16 7 + +#define TYPE_SRAM 0 +#define TYPE_PCMCIA 4 + +/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWW5 0 +#define IWW6 3 +/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWRWD5 2 +#define IWRWD6 2 +/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWRWS5 2 +#define IWRWS6 2 +/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWRRD5 2 +#define IWRRD6 2 +/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWRRS5 0 +#define IWRRS6 2 +/* burst count (0-3:4,8,16,32) */ +#define BST5 0 +#define BST6 0 +/* bus size */ +#define SZ5 BUS_SZ16 +#define SZ6 BUS_SZ16 +/* RD hold for SRAM (0-1:0,1) */ +#define RDSPL5 0 +#define RDSPL6 0 +/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */ +#define BW5 0 +#define BW6 0 +/* Multiplex (0-1:0,1) */ +#define MPX5 0 +#define MPX6 0 +/* device type */ +#define TYPE5 TYPE_PCMCIA +#define TYPE6 TYPE_PCMCIA +/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define ADS5 0 +#define ADS6 0 +/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define ADH5 0 +#define ADH6 0 +/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define RDS5 0 +#define RDS6 0 +/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define RDH5 0 +#define RDH6 0 +/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define WTS5 0 +#define WTS6 0 +/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define WTH5 0 +#define WTH6 0 +/* BS hold (0-1:1,2) */ +#define BSH5 0 +#define BSH6 0 +/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ +#define IW5 6 /* 60ns PIO mode 4 */ +#define IW6 15 /* 250ns */ + +#define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */ +#define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */ +#define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */ +#define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */ +/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ +#define PCIW5 12 +/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */ +#define TEDA5 2 +/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */ +#define TEDB5 4 +/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */ +#define TEHA5 2 +/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */ +#define TEHB5 3 + +#define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \ + (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \ + (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5) +#define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \ + (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5) +#define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \ + (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \ + (TEDB5<<8)|(TEHA5<<4)|TEHB5) + +#define SMC0_BASE 0xb0800000 /* eth0 */ +#define SMC1_BASE 0xb0900000 /* eth1 */ +#define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */ +#define IDE_BASE 0xb4000000 /* IDE */ +#define PC104_IO_BASE 0xb8000000 +#define PC104_MEM_BASE 0xba000000 +#define SMC_IO_SIZE 0x100 + +#define CF_OFFSET 0x1f0 +#define IDE_OFFSET 0x170 + +#endif /* __MACH_SH2007_H */ diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile index e25f3c69525d..1086ba1abdab 100644 --- a/arch/sh/kernel/Makefile +++ b/arch/sh/kernel/Makefile @@ -14,7 +14,7 @@ CFLAGS_REMOVE_return_address.o = -pg obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \ idle.o io.o irq.o \ irq_$(BITS).o machvec.o nmi_debug.o process.o \ - process_$(BITS).o ptrace_$(BITS).o \ + process_$(BITS).o ptrace.o ptrace_$(BITS).o \ reboot.o return_address.o \ setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o \ syscalls_$(BITS).o time.o topology.o traps.o \ diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index d180f16281ed..b93458f33b74 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -150,7 +150,7 @@ void __cpuinit cpu_probe(void) boot_cpu_data.type = CPU_SH7724; boot_cpu_data.flags |= CPU_HAS_L2_CACHE; break; - case 0x50: + case 0x10: boot_cpu_data.type = CPU_SH7757; break; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c index 0a752bd324ac..ce39a2ae8c6c 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c @@ -3,7 +3,7 @@ * * SH7757 support for the clock framework * - * Copyright (C) 2009 Renesas Solutions Corp. + * Copyright (C) 2009-2010 Renesas Solutions Corp. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -16,124 +16,147 @@ #include <asm/clock.h> #include <asm/freq.h> -static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, - 16, 1, 1, 32, 1, 1, 1, 1 }; -static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, - 16, 1, 1, 32, 1, 1, 1, 1 }; -static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, - 16, 1, 1, 32, 1, 1, 1, 1 }; -static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, - 16, 1, 1, 32, 1, 1, 1, 1 }; +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .rate = 48000000, +}; -static void master_clk_init(struct clk *clk) +static unsigned long pll_recalc(struct clk *clk) { - clk->rate = CONFIG_SH_PCLK_FREQ * 16; -} + int multiplier; -static struct clk_ops sh7757_master_clk_ops = { - .init = master_clk_init, -}; + multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16; -static void module_clk_recalc(struct clk *clk) -{ - int idx = __raw_readl(FRQCR) & 0x0000000f; - clk->rate = clk->parent->rate / p1fc_divisors[idx]; + return clk->parent->rate * multiplier; } -static struct clk_ops sh7757_module_clk_ops = { - .recalc = module_clk_recalc, +static struct clk_ops pll_clk_ops = { + .recalc = pll_recalc, }; -static void bus_clk_recalc(struct clk *clk) -{ - int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f; - clk->rate = clk->parent->rate / bfc_divisors[idx]; -} +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; -static struct clk_ops sh7757_bus_clk_ops = { - .recalc = bus_clk_recalc, +static struct clk *clks[] = { + &extal_clk, + &pll_clk, }; -static void cpu_clk_recalc(struct clk *clk) -{ - int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f; - clk->rate = clk->parent->rate / ifc_divisors[idx]; -} +static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6, + 1, 1, 1, 16, 1, 24, 1, 1 }; -static struct clk_ops sh7757_cpu_clk_ops = { - .recalc = cpu_clk_recalc, +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), }; -static struct clk_ops *sh7757_clk_ops[] = { - &sh7757_master_clk_ops, - &sh7757_module_clk_ops, - &sh7757_bus_clk_ops, - &sh7757_cpu_clk_ops, +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) -{ - if (idx < ARRAY_SIZE(sh7757_clk_ops)) - *ops = sh7757_clk_ops[idx]; -} +enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; -static void shyway_clk_recalc(struct clk *clk) -{ - int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f; - clk->rate = clk->parent->rate / sfc_divisors[idx]; -} - -static struct clk_ops sh7757_shyway_clk_ops = { - .recalc = shyway_clk_recalc, -}; +#define DIV4(_bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) -static struct clk sh7757_shyway_clk = { - .flags = CLK_ENABLE_ON_INIT, - .ops = &sh7757_shyway_clk_ops, +struct clk div4_clks[DIV4_NR] = { + /* + * P clock is always enable, because some P clock modules is used + * by Host PC. + */ + [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT), + [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT), }; -/* - * Additional sh7757-specific on-chip clocks that aren't already part of the - * clock framework - */ -static struct clk *sh7757_onchip_clocks[] = { - &sh7757_shyway_clk, +#define MSTPCR0 0xffc80030 +#define MSTPCR1 0xffc80034 + +enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112, + MSTP111, MSTP110, MSTP103, MSTP102, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + /* MSTPCR0 */ + [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), + [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), + + /* MSTPCR1 */ + [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), + [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0), + [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0), + [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), + [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), + [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), + [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0), }; #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } static struct clk_lookup lookups[] = { /* main clocks */ - CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + + /* MSTP32 clocks */ + CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]), + CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]), + { + /* TMU0 */ + .dev_id = "sh_tmu.0", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP113], + }, { + /* TMU1 */ + .dev_id = "sh_tmu.1", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP114], + }, + { + /* SCIF4 (But, ID is 2) */ + .dev_id = "sh-sci.2", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP112], + }, { + /* SCIF3 */ + .dev_id = "sh-sci.1", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP111], + }, { + /* SCIF2 */ + .dev_id = "sh-sci.0", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP110], + }, + CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]), }; -static int __init sh7757_clk_init(void) +int __init arch_clk_init(void) { - struct clk *clk = clk_get(NULL, "master_clk"); - int i; - - for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) { - struct clk *clkp = sh7757_onchip_clocks[i]; + int i, ret = 0; - clkp->parent = clk; - clk_register(clkp); - clk_enable(clkp); - } + for (i = 0; i < ARRAY_SIZE(clks); i++) + ret |= clk_register(clks[i]); + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); - /* - * Now that we have the rest of the clocks registered, we need to - * force the parent clock to propagate so that these clocks will - * automatically figure out their rate. We cheat by handing the - * parent clock its current rate and forcing child propagation. - */ - clk_set_rate(clk, clk_get_rate(clk)); + if (!ret) + ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), + &div4_table); + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); - clk_put(clk); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - return 0; + return ret; } -arch_initcall(sh7757_clk_init); - diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c index ed23b155c097..4c74bd04bba4 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c @@ -1,11 +1,11 @@ /* - * SH7757 (A0 step) Pinmux + * SH7757 (B0 step) Pinmux * - * Copyright (C) 2009 Renesas Solutions Corp. + * Copyright (C) 2009-2010 Renesas Solutions Corp. * * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> * - * Based on SH7757 Pinmux + * Based on SH7723 Pinmux * Copyright (C) 2008 Magnus Damm * * This file is subject to the terms and conditions of the GNU General Public @@ -40,27 +40,27 @@ enum { PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA, PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA, - PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, + PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL6_DATA, PTL5_DATA, PTL4_DATA, PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, - PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + PTN6_DATA, PTN5_DATA, PTN4_DATA, PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA, PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA, - PTP6_DATA, PTP5_DATA, PTP4_DATA, + PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA, PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA, - PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, + PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, - PTT5_DATA, PTT4_DATA, + PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, @@ -95,27 +95,27 @@ enum { PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN, PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN, - PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN, + PTJ6_IN, PTJ5_IN, PTJ4_IN, PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN, PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, - PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, + PTL6_IN, PTL5_IN, PTL4_IN, PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, - PTM6_IN, PTM5_IN, PTM4_IN, + PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, - PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, + PTN6_IN, PTN5_IN, PTN4_IN, PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN, PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN, - PTP6_IN, PTP5_IN, PTP4_IN, + PTP7_IN, PTP6_IN, PTP5_IN, PTP4_IN, PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN, - PTQ6_IN, PTQ5_IN, PTQ4_IN, + PTQ6_IN, PTQ5_IN, PTQ4_IN, PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN, PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN, PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, - PTT5_IN, PTT4_IN, + PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, @@ -132,16 +132,43 @@ enum { PINMUX_INPUT_END, PINMUX_INPUT_PULLUP_BEGIN, + PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, + PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, + PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, + PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, + PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU, + PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, + PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU, + PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU, + PTG7_IN_PU, PTG6_IN_PU, PTG4_IN_PU, + PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, + PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, + PTI7_IN_PU, PTI6_IN_PU, PTI4_IN_PU, + PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU, + PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU, + PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, + PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU, + PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, + PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, + PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU, + PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, + PTN4_IN_PU, + PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU, + PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU, + PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU, + PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU, + PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, - PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, - PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU, - PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU, + PTV3_IN_PU, PTV2_IN_PU, + PTW1_IN_PU, PTW0_IN_PU, PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, + PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU, + PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU, PINMUX_INPUT_PULLUP_END, PINMUX_OUTPUT_BEGIN, @@ -163,27 +190,27 @@ enum { PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT, PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT, - PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT, + PTJ6_OUT, PTJ5_OUT, PTJ4_OUT, PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT, PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, - PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, + PTL6_OUT, PTL5_OUT, PTL4_OUT, PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, - PTM6_OUT, PTM5_OUT, PTM4_OUT, + PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, - PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, + PTN6_OUT, PTN5_OUT, PTN4_OUT, PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT, PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT, - PTP6_OUT, PTP5_OUT, PTP4_OUT, + PTP7_OUT, PTP6_OUT, PTP5_OUT, PTP4_OUT, PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT, - PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, + PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT, PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT, PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, - PTT5_OUT, PTT4_OUT, + PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, @@ -218,27 +245,27 @@ enum { PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN, PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN, - PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN, + PTJ6_FN, PTJ5_FN, PTJ4_FN, PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN, PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, - PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, + PTL6_FN, PTL5_FN, PTL4_FN, PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN, - PTM6_FN, PTM5_FN, PTM4_FN, + PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN, PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, - PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN, + PTN6_FN, PTN5_FN, PTN4_FN, PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN, PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN, PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN, - PTP6_FN, PTP5_FN, PTP4_FN, + PTP7_FN, PTP6_FN, PTP5_FN, PTP4_FN, PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN, - PTQ6_FN, PTQ5_FN, PTQ4_FN, + PTQ6_FN, PTQ5_FN, PTQ4_FN, PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN, PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN, PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, - PTT5_FN, PTT4_FN, + PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, @@ -253,181 +280,248 @@ enum { PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, - PS0_15_FN1, PS0_15_FN3, - PS0_14_FN1, PS0_14_FN3, - PS0_13_FN1, PS0_13_FN3, - PS0_12_FN1, PS0_12_FN3, + PS0_15_FN1, PS0_15_FN2, + PS0_14_FN1, PS0_14_FN2, + PS0_13_FN1, PS0_13_FN2, + PS0_12_FN1, PS0_12_FN2, + PS0_11_FN1, PS0_11_FN2, + PS0_10_FN1, PS0_10_FN2, + PS0_9_FN1, PS0_9_FN2, + PS0_8_FN1, PS0_8_FN2, PS0_7_FN1, PS0_7_FN2, PS0_6_FN1, PS0_6_FN2, PS0_5_FN1, PS0_5_FN2, PS0_4_FN1, PS0_4_FN2, PS0_3_FN1, PS0_3_FN2, PS0_2_FN1, PS0_2_FN2, - PS0_1_FN1, PS0_1_FN2, - PS1_7_FN1, PS1_7_FN3, - PS1_6_FN1, PS1_6_FN3, + PS1_10_FN1, PS1_10_FN2, + PS1_9_FN1, PS1_9_FN2, + PS1_8_FN1, PS1_8_FN2, + PS1_2_FN1, PS1_2_FN2, + + PS2_13_FN1, PS2_13_FN2, + PS2_12_FN1, PS2_12_FN2, + PS2_7_FN1, PS2_7_FN2, + PS2_6_FN1, PS2_6_FN2, + PS2_5_FN1, PS2_5_FN2, + PS2_4_FN1, PS2_4_FN2, + PS2_2_FN1, PS2_2_FN2, + + PS3_15_FN1, PS3_15_FN2, + PS3_14_FN1, PS3_14_FN2, + PS3_13_FN1, PS3_13_FN2, + PS3_12_FN1, PS3_12_FN2, + PS3_11_FN1, PS3_11_FN2, + PS3_10_FN1, PS3_10_FN2, + PS3_9_FN1, PS3_9_FN2, + PS3_8_FN1, PS3_8_FN2, + PS3_7_FN1, PS3_7_FN2, + PS3_2_FN1, PS3_2_FN2, + PS3_1_FN1, PS3_1_FN2, - PS2_13_FN1, PS2_13_FN3, - PS2_12_FN1, PS2_12_FN3, - PS2_1_FN1, PS2_1_FN2, - PS2_0_FN1, PS2_0_FN2, - - PS4_15_FN1, PS4_15_FN2, PS4_14_FN1, PS4_14_FN2, PS4_13_FN1, PS4_13_FN2, PS4_12_FN1, PS4_12_FN2, - PS4_11_FN1, PS4_11_FN2, PS4_10_FN1, PS4_10_FN2, PS4_9_FN1, PS4_9_FN2, + PS4_8_FN1, PS4_8_FN2, + PS4_4_FN1, PS4_4_FN2, PS4_3_FN1, PS4_3_FN2, PS4_2_FN1, PS4_2_FN2, PS4_1_FN1, PS4_1_FN2, PS4_0_FN1, PS4_0_FN2, + PS5_11_FN1, PS5_11_FN2, + PS5_10_FN1, PS5_10_FN2, PS5_9_FN1, PS5_9_FN2, PS5_8_FN1, PS5_8_FN2, PS5_7_FN1, PS5_7_FN2, PS5_6_FN1, PS5_6_FN2, PS5_5_FN1, PS5_5_FN2, PS5_4_FN1, PS5_4_FN2, - - /* AN15 to 8 : EVENT15 to 8 */ - PS6_7_FN_AN, PS6_7_FN_EV, - PS6_6_FN_AN, PS6_6_FN_EV, - PS6_5_FN_AN, PS6_5_FN_EV, - PS6_4_FN_AN, PS6_4_FN_EV, - PS6_3_FN_AN, PS6_3_FN_EV, - PS6_2_FN_AN, PS6_2_FN_EV, - PS6_1_FN_AN, PS6_1_FN_EV, - PS6_0_FN_AN, PS6_0_FN_EV, - + PS5_3_FN1, PS5_3_FN2, + PS5_2_FN1, PS5_2_FN2, + + PS6_15_FN1, PS6_15_FN2, + PS6_14_FN1, PS6_14_FN2, + PS6_13_FN1, PS6_13_FN2, + PS6_12_FN1, PS6_12_FN2, + PS6_11_FN1, PS6_11_FN2, + PS6_10_FN1, PS6_10_FN2, + PS6_9_FN1, PS6_9_FN2, + PS6_8_FN1, PS6_8_FN2, + PS6_7_FN1, PS6_7_FN2, + PS6_6_FN1, PS6_6_FN2, + PS6_5_FN1, PS6_5_FN2, + PS6_4_FN1, PS6_4_FN2, + PS6_3_FN1, PS6_3_FN2, + PS6_2_FN1, PS6_2_FN2, + PS6_1_FN1, PS6_1_FN2, + PS6_0_FN1, PS6_0_FN2, + + PS7_15_FN1, PS7_15_FN2, + PS7_14_FN1, PS7_14_FN2, + PS7_13_FN1, PS7_13_FN2, + PS7_12_FN1, PS7_12_FN2, + PS7_11_FN1, PS7_11_FN2, + PS7_10_FN1, PS7_10_FN2, + PS7_9_FN1, PS7_9_FN2, + PS7_8_FN1, PS7_8_FN2, + PS7_7_FN1, PS7_7_FN2, + PS7_6_FN1, PS7_6_FN2, + PS7_5_FN1, PS7_5_FN2, + PS7_4_FN1, PS7_4_FN2, + + PS8_15_FN1, PS8_15_FN2, + PS8_14_FN1, PS8_14_FN2, + PS8_13_FN1, PS8_13_FN2, + PS8_12_FN1, PS8_12_FN2, + PS8_11_FN1, PS8_11_FN2, + PS8_10_FN1, PS8_10_FN2, + PS8_9_FN1, PS8_9_FN2, + PS8_8_FN1, PS8_8_FN2, PINMUX_FUNCTION_END, PINMUX_MARK_BEGIN, - /* PTA (mobule: LBSC, CPG, LPC) */ + /* PTA (mobule: LBSC, RGMII) */ BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK, - MD10_MARK, MD9_MARK, MD8_MARK, - LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK, - LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK, - - /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ - D15_MARK, D14_MARK, D13_MARK, D12_MARK, - D11_MARK, D10_MARK, D9_MARK, D8_MARK, ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK, - SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, - WPSZ1_MARK, WPSZ0_MARK, FWID_MARK, FLSHSZ_MARK, - LPC_SPIEN_MARK, BASEL_MARK, - /* PTC (mobule: SD) */ - SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK, - SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK, + /* PTB (mobule: INTC, ONFI, TMU) */ + IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK, + IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK, + ON_NRE_MARK, ON_NWE_MARK, ON_NWP_MARK, ON_NCE0_MARK, + ON_R_B0_MARK, ON_ALE_MARK, ON_CLE_MARK, TCLK_MARK, - /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + /* PTC (mobule: IRQ, PWMU) */ IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK, IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK, - MD6_MARK, MD5_MARK, MD3_MARK, MD2_MARK, - MD1_MARK, MD0_MARK, ADTRG1_MARK, ADTRG0_MARK, - - /* PTE (mobule: EtherC) */ - ET0_CRS_DV_MARK, ET0_TXD1_MARK, - ET0_TXD0_MARK, ET0_TX_EN_MARK, - ET0_REF_CLK_MARK, ET0_RXD1_MARK, - ET0_RXD0_MARK, ET0_RX_ER_MARK, - - /* PTF (mobule: EtherC) */ - ET1_CRS_DV_MARK, ET1_TXD1_MARK, - ET1_TXD0_MARK, ET1_TX_EN_MARK, - ET1_REF_CLK_MARK, ET1_RXD1_MARK, - ET1_RXD0_MARK, ET1_RX_ER_MARK, - - /* PTG (mobule: SYSTEM, PWMX, LPC) */ - STATUS0_MARK, STATUS1_MARK, - PWX0_MARK, PWX1_MARK, PWX2_MARK, PWX3_MARK, - SERIRQ_MARK, CLKRUN_MARK, LPCPD_MARK, LDRQ_MARK, - - /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ - TCLK_MARK, RXD4_MARK, TXD4_MARK, + PWMU0_MARK, PWMU1_MARK, PWMU2_MARK, PWMU3_MARK, + PWMU4_MARK, PWMU5_MARK, + + /* PTD (mobule: SPI0, DMAC) */ + SP0_MOSI_MARK, SP0_MISO_MARK, SP0_SCK_MARK, SP0_SCK_FB_MARK, + SP0_SS0_MARK, SP0_SS1_MARK, SP0_SS2_MARK, SP0_SS3_MARK, + DREQ0_MARK, DACK0_MARK, TEND0_MARK, + + /* PTE (mobule: RMII) */ + RMII0_CRS_DV_MARK, RMII0_TXD1_MARK, + RMII0_TXD0_MARK, RMII0_TXEN_MARK, + RMII0_REFCLK_MARK, RMII0_RXD1_MARK, + RMII0_RXD0_MARK, RMII0_RX_ER_MARK, + + /* PTF (mobule: RMII, SerMux) */ + RMII1_CRS_DV_MARK, RMII1_TXD1_MARK, + RMII1_TXD0_MARK, RMII1_TXEN_MARK, + RMII1_REFCLK_MARK, RMII1_RXD1_MARK, + RMII1_RXD0_MARK, RMII1_RX_ER_MARK, + RAC_RI_MARK, + + /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ + BOOTFMS_MARK, BOOTWP_MARK, A25_MARK, A24_MARK, + SERIRQ_MARK, WDTOVF_MARK, LPCPD_MARK, LDRQ_MARK, + MMCCLK_MARK, MMCCMD_MARK, + + /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK, - SP1_SS0_MARK, SP1_SS1_MARK, SP0_SS1_MARK, + SP1_SS0_MARK, SP1_SS1_MARK, WP_MARK, FMS0_MARK, + TEND1_MARK, DREQ1_MARK, DACK1_MARK, ADTRG1_MARK, + ADTRG0_MARK, - /* PTI (mobule: INTC) */ - IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK, - IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK, + /* PTI (mobule: LBSC, SDHI) */ + D15_MARK, D14_MARK, D13_MARK, D12_MARK, + D11_MARK, D10_MARK, D9_MARK, D8_MARK, + SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK, + SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK, - /* PTJ (mobule: SCIF234, SERMUX) */ - RXD3_MARK, TXD3_MARK, RXD2_MARK, TXD2_MARK, - COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK, + /* PTJ (mobule: SCIF234) */ + RTS3_MARK, CTS3_MARK, TXD3_MARK, RXD3_MARK, + RTS4_MARK, RXD4_MARK, TXD4_MARK, - /* PTK (mobule: SERMUX) */ + /* PTK (mobule: SERMUX, LBSC, SCIF) */ COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK, - COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, COM2_RI_MARK, + COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, CLKOUT_MARK, + SCK2_MARK, SCK4_MARK, SCK3_MARK, - /* PTL (mobule: SERMUX) */ - RAC_TXD_MARK, RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, - RAC_DTR_MARK, RAC_DSR_MARK, RAC_DCD_MARK, RAC_RI_MARK, + /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ + RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, RAC_DTR_MARK, + RAC_DSR_MARK, RAC_DCD_MARK, RAC_TXD_MARK, RXD2_MARK, + CS5_MARK, CS6_MARK, AUDSYNC_MARK, AUDCK_MARK, + TXD2_MARK, - /* PTM (mobule: IIC, LPC) */ + /* PTM (mobule: LBSC, IIC) */ + CS4_MARK, RD_MARK, WE0_MARK, CS0_MARK, SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK, - WP_MARK, FMS0_MARK, FMS1_MARK, - /* PTN (mobule: SCIF234, EVC) */ - SCK2_MARK, RTS4_MARK, RTS3_MARK, RTS2_MARK, - CTS4_MARK, CTS3_MARK, CTS2_MARK, - EVENT7_MARK, EVENT6_MARK, EVENT5_MARK, EVENT4_MARK, - EVENT3_MARK, EVENT2_MARK, EVENT1_MARK, EVENT0_MARK, + /* PTN (mobule: USB, JMC, SGPIO, WDT) */ + VBUS_EN_MARK, VBUS_OC_MARK, JMCTCK_MARK, JMCTMS_MARK, + JMCTDO_MARK, JMCTDI_MARK, JMCTRST_MARK, + SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, SGPIO1_DI_MARK, + SGPIO1_DO_MARK, SUB_CLKIN_MARK, - /* PTO (mobule: SGPIO) */ - SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, - SGPIO0_DI_MARK, SGPIO0_DO_MARK, - SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, - SGPIO1_DI_MARK, SGPIO1_DO_MARK, - - /* PTP (mobule: JMC, SCIF234) */ - JMCTCK_MARK, JMCTMS_MARK, JMCTDO_MARK, JMCTDI_MARK, - JMCRST_MARK, SCK4_MARK, SCK3_MARK, + /* PTO (mobule: SGPIO, SerMux) */ + SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, SGPIO0_DI_MARK, + SGPIO0_DO_MARK, SGPIO2_CLK_MARK, SGPIO2_LOAD_MARK, + SGPIO2_DI_MARK, SGPIO2_DO_MARK, + COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK, /* PTQ (mobule: LPC) */ LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK, LFRAME_MARK, LRESET_MARK, LCLK_MARK, /* PTR (mobule: GRA, IIC) */ - DDC3_MARK, DDC2_MARK, - SDA8_MARK, SCL8_MARK, SDA2_MARK, SCL2_MARK, + DDC3_MARK, DDC2_MARK, SDA2_MARK, SCL2_MARK, SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK, + SDA8_MARK, SCL8_MARK, /* PTS (mobule: GRA, IIC) */ - DDC1_MARK, DDC0_MARK, - SDA9_MARK, SCL9_MARK, SDA5_MARK, SCL5_MARK, + DDC1_MARK, DDC0_MARK, SDA5_MARK, SCL5_MARK, SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK, + SDA9_MARK, SCL9_MARK, - /* PTT (mobule: SYSTEM, PWMX) */ - AUDSYNC_MARK, AUDCK_MARK, - AUDATA3_MARK, AUDATA2_MARK, - AUDATA1_MARK, AUDATA0_MARK, - PWX7_MARK, PWX6_MARK, PWX5_MARK, PWX4_MARK, + /* PTT (mobule: PWMX, AUD) */ + PWMX7_MARK, PWMX6_MARK, PWMX5_MARK, PWMX4_MARK, + PWMX3_MARK, PWMX2_MARK, PWMX1_MARK, PWMX0_MARK, + AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK, + STATUS1_MARK, STATUS0_MARK, - /* PTU (mobule: LBSC, DMAC) */ - CS6_MARK, CS5_MARK, CS4_MARK, CS0_MARK, - RD_MARK, WE0_MARK, A25_MARK, A24_MARK, - DREQ0_MARK, DACK0_MARK, + /* PTU (mobule: LPC, APM) */ + LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK, + LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK, + APMONCTL_O_MARK, APMPWBTOUT_O_MARK, APMSCI_O_MARK, + APMVDDON_MARK, APMSLPBTN_MARK, APMPWRBTN_MARK, APMS5N_MARK, + APMS3N_MARK, - /* PTV (mobule: LBSC, DMAC) */ + /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ A23_MARK, A22_MARK, A21_MARK, A20_MARK, A19_MARK, A18_MARK, A17_MARK, A16_MARK, - TEND0_MARK, DREQ1_MARK, DACK1_MARK, TEND1_MARK, + COM2_RI_MARK, R_SPI_MOSI_MARK, R_SPI_MISO_MARK, + R_SPI_RSPCK_MARK, R_SPI_SSL0_MARK, R_SPI_SSL1_MARK, + EVENT7_MARK, EVENT6_MARK, VBIOS_DI_MARK, VBIOS_DO_MARK, + VBIOS_CLK_MARK, VBIOS_CS_MARK, - /* PTW (mobule: LBSC) */ + /* PTW (mobule: LBSC, EVC, SCIF) */ A15_MARK, A14_MARK, A13_MARK, A12_MARK, A11_MARK, A10_MARK, A9_MARK, A8_MARK, + EVENT5_MARK, EVENT4_MARK, EVENT3_MARK, EVENT2_MARK, + EVENT1_MARK, EVENT0_MARK, CTS4_MARK, CTS2_MARK, - /* PTX (mobule: LBSC) */ + /* PTX (mobule: LBSC, SCIF, SIM) */ A7_MARK, A6_MARK, A5_MARK, A4_MARK, A3_MARK, A2_MARK, A1_MARK, A0_MARK, + RTS2_MARK, SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, /* PTY (mobule: LBSC) */ D7_MARK, D6_MARK, D5_MARK, D4_MARK, D3_MARK, D2_MARK, D1_MARK, D0_MARK, + + /* PTZ (mobule: eMMC, ONFI) */ + MMCDAT7_MARK, MMCDAT6_MARK, MMCDAT5_MARK, MMCDAT4_MARK, + MMCDAT3_MARK, MMCDAT2_MARK, MMCDAT1_MARK, MMCDAT0_MARK, + ON_DQ7_MARK, ON_DQ6_MARK, ON_DQ5_MARK, ON_DQ4_MARK, + ON_DQ3_MARK, ON_DQ2_MARK, ON_DQ1_MARK, ON_DQ0_MARK, + PINMUX_MARK_END, }; @@ -473,6 +567,8 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), /* PTE GPIO */ + PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT), + PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT), PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), @@ -521,7 +617,6 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT), /* PTJ GPIO */ - PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT), PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT), PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT), PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT), @@ -541,7 +636,6 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), /* PTL GPIO */ - PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), @@ -560,7 +654,6 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), /* PTN GPIO */ - PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT), PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), @@ -609,6 +702,8 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), /* PTT GPIO */ + PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT), + PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT), PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), @@ -677,186 +772,204 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), /* PTA FN */ - PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN), - PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN), - PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN), - PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN), - PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN), - PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN), - PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN), - PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN), - PINMUX_DATA(LGPIO3_MARK, PTA3_FN), - PINMUX_DATA(LGPIO2_MARK, PTA2_FN), - PINMUX_DATA(LGPIO1_MARK, PTA1_FN), - PINMUX_DATA(LGPIO0_MARK, PTA0_FN), + PINMUX_DATA(BS_MARK, PTA7_FN), + PINMUX_DATA(RDWR_MARK, PTA6_FN), + PINMUX_DATA(WE1_MARK, PTA5_FN), + PINMUX_DATA(RDY_MARK, PTA4_FN), + PINMUX_DATA(ET0_MDC_MARK, PTA3_FN), + PINMUX_DATA(ET0_MDIO_MARK, PTA2_FN), + PINMUX_DATA(ET1_MDC_MARK, PTA1_FN), + PINMUX_DATA(ET1_MDIO_MARK, PTA0_FN), /* PTB FN */ - PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN), - PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN), - PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN), - PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN), - PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN), - PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN), - PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN), - PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN), - PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN), - PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN), - PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN), - PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN), - PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN), - PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN), - PINMUX_DATA(D8_MARK, PTB0_FN), + PINMUX_DATA(IRQ15_MARK, PS0_15_FN1, PTB7_FN), + PINMUX_DATA(ON_NRE_MARK, PS0_15_FN2, PTB7_FN), + PINMUX_DATA(IRQ14_MARK, PS0_14_FN1, PTB6_FN), + PINMUX_DATA(ON_NWE_MARK, PS0_14_FN2, PTB6_FN), + PINMUX_DATA(IRQ13_MARK, PS0_13_FN1, PTB5_FN), + PINMUX_DATA(ON_NWP_MARK, PS0_13_FN2, PTB5_FN), + PINMUX_DATA(IRQ12_MARK, PS0_12_FN1, PTB4_FN), + PINMUX_DATA(ON_NCE0_MARK, PS0_12_FN2, PTB4_FN), + PINMUX_DATA(IRQ11_MARK, PS0_11_FN1, PTB3_FN), + PINMUX_DATA(ON_R_B0_MARK, PS0_11_FN2, PTB3_FN), + PINMUX_DATA(IRQ10_MARK, PS0_10_FN1, PTB2_FN), + PINMUX_DATA(ON_ALE_MARK, PS0_10_FN2, PTB2_FN), + PINMUX_DATA(IRQ9_MARK, PS0_9_FN1, PTB1_FN), + PINMUX_DATA(ON_CLE_MARK, PS0_9_FN2, PTB1_FN), + PINMUX_DATA(IRQ8_MARK, PS0_8_FN1, PTB0_FN), + PINMUX_DATA(TCLK_MARK, PS0_8_FN2, PTB0_FN), /* PTC FN */ - PINMUX_DATA(SD_WP_MARK, PTC7_FN), - PINMUX_DATA(SD_CD_MARK, PTC6_FN), - PINMUX_DATA(SD_CLK_MARK, PTC5_FN), - PINMUX_DATA(SD_CMD_MARK, PTC4_FN), - PINMUX_DATA(SD_D3_MARK, PTC3_FN), - PINMUX_DATA(SD_D2_MARK, PTC2_FN), - PINMUX_DATA(SD_D1_MARK, PTC1_FN), - PINMUX_DATA(SD_D0_MARK, PTC0_FN), + PINMUX_DATA(IRQ7_MARK, PS0_7_FN1, PTC7_FN), + PINMUX_DATA(PWMU0_MARK, PS0_7_FN2, PTC7_FN), + PINMUX_DATA(IRQ6_MARK, PS0_6_FN1, PTC6_FN), + PINMUX_DATA(PWMU1_MARK, PS0_6_FN2, PTC6_FN), + PINMUX_DATA(IRQ5_MARK, PS0_5_FN1, PTC5_FN), + PINMUX_DATA(PWMU2_MARK, PS0_5_FN2, PTC5_FN), + PINMUX_DATA(IRQ4_MARK, PS0_4_FN1, PTC5_FN), + PINMUX_DATA(PWMU3_MARK, PS0_4_FN2, PTC4_FN), + PINMUX_DATA(IRQ3_MARK, PS0_3_FN1, PTC3_FN), + PINMUX_DATA(PWMU4_MARK, PS0_3_FN2, PTC3_FN), + PINMUX_DATA(IRQ2_MARK, PS0_2_FN1, PTC2_FN), + PINMUX_DATA(PWMU5_MARK, PS0_2_FN2, PTC2_FN), + PINMUX_DATA(IRQ1_MARK, PTC1_FN), + PINMUX_DATA(IRQ0_MARK, PTC0_FN), /* PTD FN */ - PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN), - PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN), - PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN), - PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN), - PINMUX_DATA(IRQ5_MARK, PTD5_FN), - PINMUX_DATA(IRQ4_MARK, PTD4_FN), - PINMUX_DATA(IRQ3_MARK, PTD3_FN), - PINMUX_DATA(IRQ2_MARK, PTD2_FN), - PINMUX_DATA(IRQ1_MARK, PTD1_FN), - PINMUX_DATA(IRQ0_MARK, PTD0_FN), + PINMUX_DATA(SP0_MOSI_MARK, PTD7_FN), + PINMUX_DATA(SP0_MISO_MARK, PTD6_FN), + PINMUX_DATA(SP0_SCK_MARK, PTD5_FN), + PINMUX_DATA(SP0_SCK_FB_MARK, PTD4_FN), + PINMUX_DATA(SP0_SS0_MARK, PTD3_FN), + PINMUX_DATA(SP0_SS1_MARK, PS1_10_FN1, PTD2_FN), + PINMUX_DATA(DREQ0_MARK, PS1_10_FN2, PTD2_FN), + PINMUX_DATA(SP0_SS2_MARK, PS1_9_FN1, PTD1_FN), + PINMUX_DATA(DACK0_MARK, PS1_9_FN2, PTD1_FN), + PINMUX_DATA(SP0_SS3_MARK, PS1_8_FN1, PTD0_FN), + PINMUX_DATA(TEND0_MARK, PS1_8_FN2, PTD0_FN), /* PTE FN */ - PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN), - PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN), - PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN), - PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN), - PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN), - PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN), - PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN), - PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN), + PINMUX_DATA(RMII0_CRS_DV_MARK, PTE7_FN), + PINMUX_DATA(RMII0_TXD1_MARK, PTE6_FN), + PINMUX_DATA(RMII0_TXD0_MARK, PTE5_FN), + PINMUX_DATA(RMII0_TXEN_MARK, PTE4_FN), + PINMUX_DATA(RMII0_REFCLK_MARK, PTE3_FN), + PINMUX_DATA(RMII0_RXD1_MARK, PTE2_FN), + PINMUX_DATA(RMII0_RXD0_MARK, PTE1_FN), + PINMUX_DATA(RMII0_RX_ER_MARK, PTE0_FN), /* PTF FN */ - PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN), - PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN), - PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN), - PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN), - PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN), - PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN), - PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN), - PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN), + PINMUX_DATA(RMII1_CRS_DV_MARK, PTF7_FN), + PINMUX_DATA(RMII1_TXD1_MARK, PTF6_FN), + PINMUX_DATA(RMII1_TXD0_MARK, PTF5_FN), + PINMUX_DATA(RMII1_TXEN_MARK, PTF4_FN), + PINMUX_DATA(RMII1_REFCLK_MARK, PTF3_FN), + PINMUX_DATA(RMII1_RXD1_MARK, PS1_2_FN1, PTF2_FN), + PINMUX_DATA(RAC_RI_MARK, PS1_2_FN2, PTF2_FN), + PINMUX_DATA(RMII1_RXD0_MARK, PTF1_FN), + PINMUX_DATA(RMII1_RX_ER_MARK, PTF0_FN), /* PTG FN */ - PINMUX_DATA(PWX0_MARK, PTG7_FN), - PINMUX_DATA(PWX1_MARK, PTG6_FN), - PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN), - PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN), - PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN), - PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN), + PINMUX_DATA(BOOTFMS_MARK, PTG7_FN), + PINMUX_DATA(BOOTWP_MARK, PTG6_FN), + PINMUX_DATA(A25_MARK, PS2_13_FN1, PTG5_FN), + PINMUX_DATA(MMCCLK_MARK, PS2_13_FN2, PTG5_FN), + PINMUX_DATA(A24_MARK, PS2_12_FN1, PTG4_FN), + PINMUX_DATA(MMCCMD_MARK, PS2_12_FN2, PTG4_FN), PINMUX_DATA(SERIRQ_MARK, PTG3_FN), - PINMUX_DATA(CLKRUN_MARK, PTG2_FN), + PINMUX_DATA(WDTOVF_MARK, PTG2_FN), PINMUX_DATA(LPCPD_MARK, PTG1_FN), PINMUX_DATA(LDRQ_MARK, PTG0_FN), /* PTH FN */ - PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN), - PINMUX_DATA(SP1_MISO_MARK, PTH6_FN), - PINMUX_DATA(SP1_SCK_MARK, PTH5_FN), - PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN), + PINMUX_DATA(SP1_MOSI_MARK, PS2_7_FN1, PTH7_FN), + PINMUX_DATA(TEND1_MARK, PS2_7_FN2, PTH7_FN), + PINMUX_DATA(SP1_MISO_MARK, PS2_6_FN1, PTH6_FN), + PINMUX_DATA(DREQ1_MARK, PS2_6_FN2, PTH6_FN), + PINMUX_DATA(SP1_SCK_MARK, PS2_5_FN1, PTH5_FN), + PINMUX_DATA(DACK1_MARK, PS2_5_FN2, PTH5_FN), + PINMUX_DATA(SP1_SCK_FB_MARK, PS2_4_FN1, PTH4_FN), + PINMUX_DATA(ADTRG1_MARK, PS2_4_FN2, PTH4_FN), PINMUX_DATA(SP1_SS0_MARK, PTH3_FN), - PINMUX_DATA(TCLK_MARK, PTH2_FN), - PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN), - PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN), - PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN), - PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN), + PINMUX_DATA(SP1_SS1_MARK, PS2_2_FN1, PTH2_FN), + PINMUX_DATA(ADTRG0_MARK, PS2_2_FN2, PTH2_FN), + PINMUX_DATA(WP_MARK, PTH1_FN), + PINMUX_DATA(FMS0_MARK, PTH0_FN), /* PTI FN */ - PINMUX_DATA(IRQ15_MARK, PTI7_FN), - PINMUX_DATA(IRQ14_MARK, PTI6_FN), - PINMUX_DATA(IRQ13_MARK, PTI5_FN), - PINMUX_DATA(IRQ12_MARK, PTI4_FN), - PINMUX_DATA(IRQ11_MARK, PTI3_FN), - PINMUX_DATA(IRQ10_MARK, PTI2_FN), - PINMUX_DATA(IRQ9_MARK, PTI1_FN), - PINMUX_DATA(IRQ8_MARK, PTI0_FN), + PINMUX_DATA(D15_MARK, PS3_15_FN1, PTI7_FN), + PINMUX_DATA(SD_WP_MARK, PS3_15_FN2, PTI7_FN), + PINMUX_DATA(D14_MARK, PS3_14_FN1, PTI6_FN), + PINMUX_DATA(SD_CD_MARK, PS3_14_FN2, PTI6_FN), + PINMUX_DATA(D13_MARK, PS3_13_FN1, PTI5_FN), + PINMUX_DATA(SD_CLK_MARK, PS3_13_FN2, PTI5_FN), + PINMUX_DATA(D12_MARK, PS3_12_FN1, PTI4_FN), + PINMUX_DATA(SD_CMD_MARK, PS3_12_FN2, PTI4_FN), + PINMUX_DATA(D11_MARK, PS3_11_FN1, PTI3_FN), + PINMUX_DATA(SD_D3_MARK, PS3_11_FN2, PTI3_FN), + PINMUX_DATA(D10_MARK, PS3_10_FN1, PTI2_FN), + PINMUX_DATA(SD_D2_MARK, PS3_10_FN2, PTI2_FN), + PINMUX_DATA(D9_MARK, PS3_9_FN1, PTI1_FN), + PINMUX_DATA(SD_D1_MARK, PS3_9_FN2, PTI1_FN), + PINMUX_DATA(D8_MARK, PS3_8_FN1, PTI0_FN), + PINMUX_DATA(SD_D0_MARK, PS3_8_FN2, PTI0_FN), /* PTJ FN */ - PINMUX_DATA(RXD3_MARK, PTJ7_FN), - PINMUX_DATA(TXD3_MARK, PTJ6_FN), - PINMUX_DATA(RXD2_MARK, PTJ5_FN), - PINMUX_DATA(TXD2_MARK, PTJ4_FN), - PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN), - PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN), - PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN), - PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN), + PINMUX_DATA(RTS3_MARK, PTJ6_FN), + PINMUX_DATA(CTS3_MARK, PTJ5_FN), + PINMUX_DATA(TXD3_MARK, PTJ4_FN), + PINMUX_DATA(RXD3_MARK, PTJ3_FN), + PINMUX_DATA(RTS4_MARK, PTJ2_FN), + PINMUX_DATA(RXD4_MARK, PTJ1_FN), + PINMUX_DATA(TXD4_MARK, PTJ0_FN), /* PTK FN */ - PINMUX_DATA(COM2_TXD_MARK, PTK7_FN), + PINMUX_DATA(COM2_TXD_MARK, PS3_7_FN1, PTK7_FN), + PINMUX_DATA(SCK2_MARK, PS3_7_FN2, PTK7_FN), PINMUX_DATA(COM2_RXD_MARK, PTK6_FN), PINMUX_DATA(COM2_RTS_MARK, PTK5_FN), PINMUX_DATA(COM2_CTS_MARK, PTK4_FN), PINMUX_DATA(COM2_DTR_MARK, PTK3_FN), - PINMUX_DATA(COM2_DSR_MARK, PTK2_FN), - PINMUX_DATA(COM2_DCD_MARK, PTK1_FN), - PINMUX_DATA(COM2_RI_MARK, PTK0_FN), + PINMUX_DATA(COM2_DSR_MARK, PS3_2_FN1, PTK2_FN), + PINMUX_DATA(SCK4_MARK, PS3_2_FN2, PTK2_FN), + PINMUX_DATA(COM2_DCD_MARK, PS3_1_FN1, PTK1_FN), + PINMUX_DATA(SCK3_MARK, PS3_1_FN2, PTK1_FN), + PINMUX_DATA(CLKOUT_MARK, PTK0_FN), /* PTL FN */ - PINMUX_DATA(RAC_TXD_MARK, PTL7_FN), - PINMUX_DATA(RAC_RXD_MARK, PTL6_FN), - PINMUX_DATA(RAC_RTS_MARK, PTL5_FN), - PINMUX_DATA(RAC_CTS_MARK, PTL4_FN), + PINMUX_DATA(RAC_RXD_MARK, PS4_14_FN1, PTL6_FN), + PINMUX_DATA(RXD2_MARK, PS4_14_FN2, PTL6_FN), + PINMUX_DATA(RAC_RTS_MARK, PS4_13_FN1, PTL5_FN), + PINMUX_DATA(CS5_MARK, PS4_13_FN2, PTL5_FN), + PINMUX_DATA(RAC_CTS_MARK, PS4_12_FN1, PTL4_FN), + PINMUX_DATA(CS6_MARK, PS4_12_FN2, PTL4_FN), PINMUX_DATA(RAC_DTR_MARK, PTL3_FN), - PINMUX_DATA(RAC_DSR_MARK, PTL2_FN), - PINMUX_DATA(RAC_DCD_MARK, PTL1_FN), - PINMUX_DATA(RAC_RI_MARK, PTL0_FN), + PINMUX_DATA(RAC_DSR_MARK, PS4_10_FN1, PTL2_FN), + PINMUX_DATA(AUDSYNC_MARK, PS4_10_FN2, PTL2_FN), + PINMUX_DATA(RAC_DCD_MARK, PS4_9_FN1, PTL1_FN), + PINMUX_DATA(AUDCK_MARK, PS4_9_FN2, PTL1_FN), + PINMUX_DATA(RAC_TXD_MARK, PS4_8_FN1, PTL0_FN), + PINMUX_DATA(TXD2_MARK, PS4_8_FN1, PTL0_FN), /* PTM FN */ - PINMUX_DATA(WP_MARK, PTM6_FN), - PINMUX_DATA(FMS0_MARK, PTM5_FN), - PINMUX_DATA(FMS1_MARK, PTM4_FN), + PINMUX_DATA(CS4_MARK, PTM7_FN), + PINMUX_DATA(RD_MARK, PTM6_FN), + PINMUX_DATA(WE0_MARK, PTM7_FN), + PINMUX_DATA(CS0_MARK, PTM4_FN), PINMUX_DATA(SDA6_MARK, PTM3_FN), PINMUX_DATA(SCL6_MARK, PTM2_FN), PINMUX_DATA(SDA7_MARK, PTM1_FN), PINMUX_DATA(SCL7_MARK, PTM0_FN), /* PTN FN */ - PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN), - PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN), - PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN), - PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN), - PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN), - PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN), - PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN), - PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN), - PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN), - PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN), - PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN), - PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN), - PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN), - PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN), - PINMUX_DATA(EVENT0_MARK, PTN0_FN), + PINMUX_DATA(VBUS_EN_MARK, PTN6_FN), + PINMUX_DATA(VBUS_OC_MARK, PTN5_FN), + PINMUX_DATA(JMCTCK_MARK, PS4_4_FN1, PTN4_FN), + PINMUX_DATA(SGPIO1_CLK_MARK, PS4_4_FN2, PTN4_FN), + PINMUX_DATA(JMCTMS_MARK, PS4_3_FN1, PTN5_FN), + PINMUX_DATA(SGPIO1_LOAD_MARK, PS4_3_FN2, PTN5_FN), + PINMUX_DATA(JMCTDO_MARK, PS4_2_FN1, PTN2_FN), + PINMUX_DATA(SGPIO1_DO_MARK, PS4_2_FN2, PTN2_FN), + PINMUX_DATA(JMCTDI_MARK, PS4_1_FN1, PTN1_FN), + PINMUX_DATA(SGPIO1_DI_MARK, PS4_1_FN2, PTN1_FN), + PINMUX_DATA(JMCTRST_MARK, PS4_0_FN1, PTN0_FN), + PINMUX_DATA(SUB_CLKIN_MARK, PS4_0_FN2, PTN0_FN), /* PTO FN */ PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN), PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN), PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN), PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN), - PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN), - PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN), - PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN), - PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN), + PINMUX_DATA(SGPIO2_CLK_MARK, PS5_11_FN1, PTO3_FN), + PINMUX_DATA(COM1_TXD_MARK, PS5_11_FN2, PTO3_FN), + PINMUX_DATA(SGPIO2_LOAD_MARK, PS5_10_FN1, PTO2_FN), + PINMUX_DATA(COM1_RXD_MARK, PS5_10_FN2, PTO2_FN), + PINMUX_DATA(SGPIO2_DI_MARK, PS5_9_FN1, PTO1_FN), + PINMUX_DATA(COM1_RTS_MARK, PS5_9_FN2, PTO1_FN), + PINMUX_DATA(SGPIO2_DO_MARK, PS5_8_FN1, PTO0_FN), + PINMUX_DATA(COM1_CTS_MARK, PS5_8_FN2, PTO0_FN), /* PTP FN */ - PINMUX_DATA(JMCTCK_MARK, PTP6_FN), - PINMUX_DATA(JMCTMS_MARK, PTP5_FN), - PINMUX_DATA(JMCTDO_MARK, PTP4_FN), - PINMUX_DATA(JMCTDI_MARK, PTP3_FN), - PINMUX_DATA(JMCRST_MARK, PTP2_FN), - PINMUX_DATA(SCK4_MARK, PTP1_FN), - PINMUX_DATA(SCK3_MARK, PTP0_FN), /* PTQ FN */ PINMUX_DATA(LAD3_MARK, PTQ6_FN), @@ -864,8 +977,8 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(LAD1_MARK, PTQ4_FN), PINMUX_DATA(LAD0_MARK, PTQ3_FN), PINMUX_DATA(LFRAME_MARK, PTQ2_FN), - PINMUX_DATA(SCK4_MARK, PTQ1_FN), - PINMUX_DATA(SCK3_MARK, PTQ0_FN), + PINMUX_DATA(LRESET_MARK, PTQ1_FN), + PINMUX_DATA(LCLK_MARK, PTQ0_FN), /* PTR FN */ PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */ @@ -888,58 +1001,84 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SCL3_MARK, PTS0_FN), /* PTT FN */ - PINMUX_DATA(AUDSYNC_MARK, PTS5_FN), - PINMUX_DATA(AUDCK_MARK, PTS4_FN), - PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN), - PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN), - PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN), - PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN), - PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN), - PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN), - PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN), - PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN), + PINMUX_DATA(PWMX7_MARK, PS5_7_FN1, PTT7_FN), + PINMUX_DATA(AUDATA3_MARK, PS5_7_FN2, PTT7_FN), + PINMUX_DATA(PWMX6_MARK, PS5_6_FN1, PTT6_FN), + PINMUX_DATA(AUDATA2_MARK, PS5_6_FN2, PTT6_FN), + PINMUX_DATA(PWMX5_MARK, PS5_5_FN1, PTT5_FN), + PINMUX_DATA(AUDATA1_MARK, PS5_5_FN2, PTT5_FN), + PINMUX_DATA(PWMX4_MARK, PS5_4_FN1, PTT4_FN), + PINMUX_DATA(AUDATA0_MARK, PS5_4_FN2, PTT4_FN), + PINMUX_DATA(PWMX3_MARK, PS5_3_FN1, PTT3_FN), + PINMUX_DATA(STATUS1_MARK, PS5_3_FN2, PTT3_FN), + PINMUX_DATA(PWMX2_MARK, PS5_2_FN1, PTT2_FN), + PINMUX_DATA(STATUS0_MARK, PS5_2_FN2, PTT2_FN), + PINMUX_DATA(PWMX1_MARK, PTT1_FN), + PINMUX_DATA(PWMX0_MARK, PTT0_FN), /* PTU FN */ - PINMUX_DATA(CS6_MARK, PTU7_FN), - PINMUX_DATA(CS5_MARK, PTU6_FN), - PINMUX_DATA(CS4_MARK, PTU5_FN), - PINMUX_DATA(CS0_MARK, PTU4_FN), - PINMUX_DATA(RD_MARK, PTU3_FN), - PINMUX_DATA(WE0_MARK, PTU2_FN), - PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN), - PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN), - PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN), - PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN), + PINMUX_DATA(LGPIO7_MARK, PS6_15_FN1, PTU7_FN), + PINMUX_DATA(APMONCTL_O_MARK, PS6_15_FN2, PTU7_FN), + PINMUX_DATA(LGPIO6_MARK, PS6_14_FN1, PTU6_FN), + PINMUX_DATA(APMPWBTOUT_O_MARK, PS6_14_FN2, PTU6_FN), + PINMUX_DATA(LGPIO5_MARK, PS6_13_FN1, PTU5_FN), + PINMUX_DATA(APMSCI_O_MARK, PS6_13_FN2, PTU5_FN), + PINMUX_DATA(LGPIO4_MARK, PS6_12_FN1, PTU4_FN), + PINMUX_DATA(APMVDDON_MARK, PS6_12_FN2, PTU4_FN), + PINMUX_DATA(LGPIO3_MARK, PS6_11_FN1, PTU3_FN), + PINMUX_DATA(APMSLPBTN_MARK, PS6_11_FN2, PTU3_FN), + PINMUX_DATA(LGPIO2_MARK, PS6_10_FN1, PTU2_FN), + PINMUX_DATA(APMPWRBTN_MARK, PS6_10_FN2, PTU2_FN), + PINMUX_DATA(LGPIO1_MARK, PS6_9_FN1, PTU1_FN), + PINMUX_DATA(APMS5N_MARK, PS6_9_FN2, PTU1_FN), + PINMUX_DATA(LGPIO0_MARK, PS6_8_FN1, PTU0_FN), + PINMUX_DATA(APMS3N_MARK, PS6_8_FN2, PTU0_FN), /* PTV FN */ - PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN), - PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN), - PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN), - PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN), - PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN), - PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN), - PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN), - PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN), - PINMUX_DATA(A19_MARK, PTV3_FN), - PINMUX_DATA(A18_MARK, PTV2_FN), - PINMUX_DATA(A17_MARK, PTV1_FN), - PINMUX_DATA(A16_MARK, PTV0_FN), + PINMUX_DATA(A23_MARK, PS6_7_FN1, PTV7_FN), + PINMUX_DATA(COM2_RI_MARK, PS6_7_FN2, PTV7_FN), + PINMUX_DATA(A22_MARK, PS6_6_FN1, PTV6_FN), + PINMUX_DATA(R_SPI_MOSI_MARK, PS6_6_FN2, PTV6_FN), + PINMUX_DATA(A21_MARK, PS6_5_FN1, PTV5_FN), + PINMUX_DATA(R_SPI_MISO_MARK, PS6_5_FN2, PTV5_FN), + PINMUX_DATA(A20_MARK, PS6_4_FN1, PTV4_FN), + PINMUX_DATA(R_SPI_RSPCK_MARK, PS6_4_FN2, PTV4_FN), + PINMUX_DATA(A19_MARK, PS6_3_FN1, PTV3_FN), + PINMUX_DATA(R_SPI_SSL0_MARK, PS6_3_FN2, PTV3_FN), + PINMUX_DATA(A18_MARK, PS6_2_FN1, PTV2_FN), + PINMUX_DATA(R_SPI_SSL1_MARK, PS6_2_FN2, PTV2_FN), + PINMUX_DATA(A17_MARK, PS6_1_FN1, PTV1_FN), + PINMUX_DATA(EVENT7_MARK, PS6_1_FN2, PTV1_FN), + PINMUX_DATA(A16_MARK, PS6_0_FN1, PTV0_FN), + PINMUX_DATA(EVENT6_MARK, PS6_0_FN1, PTV0_FN), /* PTW FN */ - PINMUX_DATA(A15_MARK, PTW7_FN), - PINMUX_DATA(A14_MARK, PTW6_FN), - PINMUX_DATA(A13_MARK, PTW5_FN), - PINMUX_DATA(A12_MARK, PTW4_FN), - PINMUX_DATA(A11_MARK, PTW3_FN), - PINMUX_DATA(A10_MARK, PTW2_FN), - PINMUX_DATA(A9_MARK, PTW1_FN), - PINMUX_DATA(A8_MARK, PTW0_FN), + PINMUX_DATA(A15_MARK, PS7_15_FN1, PTW7_FN), + PINMUX_DATA(EVENT5_MARK, PS7_15_FN2, PTW7_FN), + PINMUX_DATA(A14_MARK, PS7_14_FN1, PTW6_FN), + PINMUX_DATA(EVENT4_MARK, PS7_14_FN2, PTW6_FN), + PINMUX_DATA(A13_MARK, PS7_13_FN1, PTW5_FN), + PINMUX_DATA(EVENT3_MARK, PS7_13_FN2, PTW5_FN), + PINMUX_DATA(A12_MARK, PS7_12_FN1, PTW4_FN), + PINMUX_DATA(EVENT2_MARK, PS7_12_FN2, PTW4_FN), + PINMUX_DATA(A11_MARK, PS7_11_FN1, PTW3_FN), + PINMUX_DATA(EVENT1_MARK, PS7_11_FN2, PTW3_FN), + PINMUX_DATA(A10_MARK, PS7_10_FN1, PTW2_FN), + PINMUX_DATA(EVENT0_MARK, PS7_10_FN2, PTW2_FN), + PINMUX_DATA(A9_MARK, PS7_9_FN1, PTW1_FN), + PINMUX_DATA(CTS4_MARK, PS7_9_FN2, PTW1_FN), + PINMUX_DATA(A8_MARK, PS7_8_FN1, PTW0_FN), + PINMUX_DATA(CTS2_MARK, PS7_8_FN2, PTW0_FN), /* PTX FN */ - PINMUX_DATA(A7_MARK, PTX7_FN), - PINMUX_DATA(A6_MARK, PTX6_FN), - PINMUX_DATA(A5_MARK, PTX5_FN), - PINMUX_DATA(A4_MARK, PTX4_FN), + PINMUX_DATA(A7_MARK, PS7_7_FN1, PTX7_FN), + PINMUX_DATA(RTS2_MARK, PS7_7_FN2, PTX7_FN), + PINMUX_DATA(A6_MARK, PS7_6_FN1, PTX6_FN), + PINMUX_DATA(SIM_D_MARK, PS7_6_FN2, PTX6_FN), + PINMUX_DATA(A5_MARK, PS7_5_FN1, PTX5_FN), + PINMUX_DATA(SIM_CLK_MARK, PS7_5_FN2, PTX5_FN), + PINMUX_DATA(A4_MARK, PS7_4_FN1, PTX4_FN), + PINMUX_DATA(SIM_RST_MARK, PS7_4_FN2, PTX4_FN), PINMUX_DATA(A3_MARK, PTX3_FN), PINMUX_DATA(A2_MARK, PTX2_FN), PINMUX_DATA(A1_MARK, PTX1_FN), @@ -954,6 +1093,24 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(D2_MARK, PTY2_FN), PINMUX_DATA(D1_MARK, PTY1_FN), PINMUX_DATA(D0_MARK, PTY0_FN), + + /* PTZ FN */ + PINMUX_DATA(MMCDAT7_MARK, PS8_15_FN1, PTZ7_FN), + PINMUX_DATA(ON_DQ7_MARK, PS8_15_FN2, PTZ7_FN), + PINMUX_DATA(MMCDAT6_MARK, PS8_14_FN1, PTZ6_FN), + PINMUX_DATA(ON_DQ6_MARK, PS8_14_FN2, PTZ6_FN), + PINMUX_DATA(MMCDAT5_MARK, PS8_13_FN1, PTZ5_FN), + PINMUX_DATA(ON_DQ5_MARK, PS8_13_FN2, PTZ5_FN), + PINMUX_DATA(MMCDAT4_MARK, PS8_12_FN1, PTZ4_FN), + PINMUX_DATA(ON_DQ4_MARK, PS8_12_FN2, PTZ4_FN), + PINMUX_DATA(MMCDAT3_MARK, PS8_11_FN1, PTZ3_FN), + PINMUX_DATA(ON_DQ3_MARK, PS8_11_FN2, PTZ3_FN), + PINMUX_DATA(MMCDAT2_MARK, PS8_10_FN1, PTZ2_FN), + PINMUX_DATA(ON_DQ2_MARK, PS8_10_FN2, PTZ2_FN), + PINMUX_DATA(MMCDAT1_MARK, PS8_9_FN1, PTZ1_FN), + PINMUX_DATA(ON_DQ1_MARK, PS8_9_FN2, PTZ1_FN), + PINMUX_DATA(MMCDAT0_MARK, PS8_8_FN1, PTZ0_FN), + PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), }; static struct pinmux_gpio pinmux_gpios[] = { @@ -1048,7 +1205,6 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTI0, PTI0_DATA), /* PTJ */ - PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), @@ -1068,7 +1224,6 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), @@ -1078,6 +1233,7 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), /* PTM */ + PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), @@ -1087,7 +1243,6 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), /* PTN */ - PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), @@ -1107,6 +1262,7 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTO0, PTO0_DATA), /* PTP */ + PINMUX_GPIO(GPIO_PTP7, PTP7_DATA), PINMUX_GPIO(GPIO_PTP6, PTP6_DATA), PINMUX_GPIO(GPIO_PTP5, PTP5_DATA), PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), @@ -1145,6 +1301,8 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), /* PTT */ + PINMUX_GPIO(GPIO_PTT7, PTT7_DATA), + PINMUX_GPIO(GPIO_PTT6, PTT6_DATA), PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), @@ -1212,54 +1370,35 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), - /* PTA (mobule: LBSC, CPG, LPC) */ + /* PTA (mobule: LBSC, RGMII) */ PINMUX_GPIO(GPIO_FN_BS, BS_MARK), PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), - PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK), - PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK), - PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), - - /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), - PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), + PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDC_MARK), PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), - PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), - PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK), - PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK), - PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK), - PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK), - PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK), - PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK), - - /* PTC (mobule: SD) */ - PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), - PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), - PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), - PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), - PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), - PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), - PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), + PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDC_MARK), - /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + /* PTB (mobule: INTC, ONFI, TMU) */ + PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), + PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), + PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), + PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), + PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), + PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), + PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), + PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), + PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK), + PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK), + PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK), + PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK), + PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK), + PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK), + PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK), + PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), + + /* PTC (mobule: IRQ, PWMU) */ PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), @@ -1268,80 +1407,102 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK), - PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK), - PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK), - PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK), - PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK), - PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), + PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK), + PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK), + PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK), + PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK), + PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK), + PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK), + + /* PTD (mobule: SPI0, DMAC) */ + PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK), + PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), - /* PTE (mobule: EtherC) */ - PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK), - PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK), - - /* PTF (mobule: EtherC) */ - PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK), - PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK), - - /* PTG (mobule: SYSTEM, PWMX, LPC) */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK), - PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK), - PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK), - PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK), + /* PTE (mobule: RMII) */ + PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK), + + /* PTF (mobule: RMII, SerMux) */ + PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK), + PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), + + /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ + PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK), + PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), - PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK), + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), + PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), + PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), - /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), - PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), - PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), + PINMUX_GPIO(GPIO_FN_WP, WP_MARK), + PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), - /* PTI (mobule: INTC) */ - PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), - PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), - PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), - PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), - PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), - PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), - PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), - PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), + /* PTI (mobule: LBSC, SDHI) */ + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), + PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), + PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), + PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), + PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), + PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), + PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), /* PTJ (mobule: SCIF234, SERMUX) */ - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), + PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), + PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), + PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), - /* PTK (mobule: SERMUX) */ + /* PTK (mobule: SERMUX, LBSC, SCIF) */ PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), @@ -1349,62 +1510,65 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), - PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), + PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), - /* PTL (mobule: SERMUX) */ - PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), + /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), - PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), + PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), + PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - /* PTM (mobule: IIC, LPC) */ + /* PTM (mobule: LBSC, IIC) */ + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_RD, RD_MARK), + PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), + PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), - PINMUX_GPIO(GPIO_FN_WP, WP_MARK), - PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), - PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK), - /* PTN (mobule: SCIF234, EVC) */ - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), - PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), - PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), - PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), - PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), - PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), - PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), - PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), - PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), - PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), - PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), - PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), - PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), - PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), + /* PTN (mobule: USB, JMC, SGPIO, WDT) */ + PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK), + PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK), + PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), + PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), + PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), + PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), + PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), + PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK), - /* PTO (mobule: SGPIO) */ + /* PTO (mobule: SGPIO, SerMux) */ PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK), + PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), + PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), - /* PTP (mobule: JMC, SCIF234) */ - PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), - PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), - PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), - PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), - PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK), - PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + /* PTP (mobule: EVC, ADC) */ /* PTQ (mobule: LPC) */ PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), @@ -1439,31 +1603,41 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), - /* PTT (mobule: SYSTEM, PWMX) */ - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + /* PTT (mobule: PWMX, AUD) */ + PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK), + PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK), + PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK), + PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK), + PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK), + PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK), + PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK), + PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK), PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK), - PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK), - PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK), - PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK), - - /* PTU (mobule: LBSC, DMAC) */ - PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), - PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), - PINMUX_GPIO(GPIO_FN_RD, RD_MARK), - PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - /* PTV (mobule: LBSC, DMAC) */ + /* PTU (mobule: LPC, APM) */ + PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), + PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK), + PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK), + PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK), + PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK), + PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK), + PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK), + PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK), + PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK), + + /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ PINMUX_GPIO(GPIO_FN_A23, A23_MARK), PINMUX_GPIO(GPIO_FN_A22, A22_MARK), PINMUX_GPIO(GPIO_FN_A21, A21_MARK), @@ -1472,12 +1646,20 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_A18, A18_MARK), PINMUX_GPIO(GPIO_FN_A17, A17_MARK), PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK), + PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), + PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK), - /* PTW (mobule: LBSC) */ + /* PTW (mobule: LBSC, EVC, SCIF) */ PINMUX_GPIO(GPIO_FN_A16, A16_MARK), PINMUX_GPIO(GPIO_FN_A15, A15_MARK), PINMUX_GPIO(GPIO_FN_A14, A14_MARK), @@ -1487,6 +1669,14 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_A10, A10_MARK), PINMUX_GPIO(GPIO_FN_A9, A9_MARK), PINMUX_GPIO(GPIO_FN_A8, A8_MARK), + PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), + PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), + PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), + PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), + PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), + PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), + PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), + PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), /* PTX (mobule: LBSC) */ PINMUX_GPIO(GPIO_FN_A7, A7_MARK), @@ -1497,6 +1687,10 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_A2, A2_MARK), PINMUX_GPIO(GPIO_FN_A1, A1_MARK), PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), + PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), + PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), /* PTY (mobule: LBSC) */ PINMUX_GPIO(GPIO_FN_D7, D7_MARK), @@ -1507,18 +1701,36 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_D2, D2_MARK), PINMUX_GPIO(GPIO_FN_D1, D1_MARK), PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + + /* PTZ (mobule: eMMC, ONFI) */ + PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { - PTA7_FN, PTA7_OUT, PTA7_IN, 0, - PTA6_FN, PTA6_OUT, PTA6_IN, 0, - PTA5_FN, PTA5_OUT, PTA5_IN, 0, - PTA4_FN, PTA4_OUT, PTA4_IN, 0, - PTA3_FN, PTA3_OUT, PTA3_IN, 0, - PTA2_FN, PTA2_OUT, PTA2_IN, 0, - PTA1_FN, PTA1_OUT, PTA1_IN, 0, - PTA0_FN, PTA0_OUT, PTA0_IN, 0 } + PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU, + PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU, + PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU, + PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU, + PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU, + PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU, + PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU, + PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU } }, { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) { PTB7_FN, PTB7_OUT, PTB7_IN, 0, @@ -1541,125 +1753,126 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTC0_FN, PTC0_OUT, PTC0_IN, 0 } }, { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) { - PTD7_FN, PTD7_OUT, PTD7_IN, 0, - PTD6_FN, PTD6_OUT, PTD6_IN, 0, - PTD5_FN, PTD5_OUT, PTD5_IN, 0, - PTD4_FN, PTD4_OUT, PTD4_IN, 0, - PTD3_FN, PTD3_OUT, PTD3_IN, 0, - PTD2_FN, PTD2_OUT, PTD2_IN, 0, - PTD1_FN, PTD1_OUT, PTD1_IN, 0, - PTD0_FN, PTD0_OUT, PTD0_IN, 0 } + PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU, + PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU, + PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU, + PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU, + PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU, + PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU, + PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU, + PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU } }, { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) { - PTE7_FN, PTE7_OUT, PTE7_IN, 0, - PTE6_FN, PTE6_OUT, PTE6_IN, 0, - PTE5_FN, PTE5_OUT, PTE5_IN, 0, - PTE4_FN, PTE4_OUT, PTE4_IN, 0, - PTE3_FN, PTE3_OUT, PTE3_IN, 0, - PTE2_FN, PTE2_OUT, PTE2_IN, 0, - PTE1_FN, PTE1_OUT, PTE1_IN, 0, - PTE0_FN, PTE0_OUT, PTE0_IN, 0 } + PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU, + PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU, + PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU, + PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU, + PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU, + PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU, + PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU, + PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU } }, { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) { - PTF7_FN, PTF7_OUT, PTF7_IN, 0, - PTF6_FN, PTF6_OUT, PTF6_IN, 0, - PTF5_FN, PTF5_OUT, PTF5_IN, 0, - PTF4_FN, PTF4_OUT, PTF4_IN, 0, - PTF3_FN, PTF3_OUT, PTF3_IN, 0, - PTF2_FN, PTF2_OUT, PTF2_IN, 0, - PTF1_FN, PTF1_OUT, PTF1_IN, 0, - PTF0_FN, PTF0_OUT, PTF0_IN, 0 } + PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU, + PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU, + PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU, + PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU, + PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU, + PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU, + PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU, + PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU } }, { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) { - PTG7_FN, PTG7_OUT, PTG7_IN, 0, - PTG6_FN, PTG6_OUT, PTG6_IN, 0, + PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU , + PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU , PTG5_FN, PTG5_OUT, PTG5_IN, 0, - PTG4_FN, PTG4_OUT, PTG4_IN, 0, + PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU , PTG3_FN, PTG3_OUT, PTG3_IN, 0, PTG2_FN, PTG2_OUT, PTG2_IN, 0, PTG1_FN, PTG1_OUT, PTG1_IN, 0, PTG0_FN, PTG0_OUT, PTG0_IN, 0 } }, { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) { - PTH7_FN, PTH7_OUT, PTH7_IN, 0, - PTH6_FN, PTH6_OUT, PTH6_IN, 0, - PTH5_FN, PTH5_OUT, PTH5_IN, 0, - PTH4_FN, PTH4_OUT, PTH4_IN, 0, - PTH3_FN, PTH3_OUT, PTH3_IN, 0, - PTH2_FN, PTH2_OUT, PTH2_IN, 0, - PTH1_FN, PTH1_OUT, PTH1_IN, 0, - PTH0_FN, PTH0_OUT, PTH0_IN, 0 } + PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU, + PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU, + PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU, + PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU, + PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU, + PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU, + PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU, + PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU } }, { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) { - PTI7_FN, PTI7_OUT, PTI7_IN, 0, - PTI6_FN, PTI6_OUT, PTI6_IN, 0, + PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU, + PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU, PTI5_FN, PTI5_OUT, PTI5_IN, 0, - PTI4_FN, PTI4_OUT, PTI4_IN, 0, - PTI3_FN, PTI3_OUT, PTI3_IN, 0, - PTI2_FN, PTI2_OUT, PTI2_IN, 0, - PTI1_FN, PTI1_OUT, PTI1_IN, 0, - PTI0_FN, PTI0_OUT, PTI0_IN, 0 } + PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU, + PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU, + PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU, + PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU, + PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU } }, { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) { - PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0, - PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0, - PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0, - PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0, - PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0, - PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0, - PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0, - PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 } + 0, 0, 0, 0, /* reserved: always set 1 */ + PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU, + PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU, + PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU, + PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU, + PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU, + PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU, + PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU } }, { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) { - PTK7_FN, PTK7_OUT, PTK7_IN, 0, - PTK6_FN, PTK6_OUT, PTK6_IN, 0, - PTK5_FN, PTK5_OUT, PTK5_IN, 0, - PTK4_FN, PTK4_OUT, PTK4_IN, 0, - PTK3_FN, PTK3_OUT, PTK3_IN, 0, - PTK2_FN, PTK2_OUT, PTK2_IN, 0, - PTK1_FN, PTK1_OUT, PTK1_IN, 0, - PTK0_FN, PTK0_OUT, PTK0_IN, 0 } + PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU, + PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU, + PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU, + PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU, + PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU, + PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU, + PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU, + PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU } }, { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) { - PTL7_FN, PTL7_OUT, PTL7_IN, 0, - PTL6_FN, PTL6_OUT, PTL6_IN, 0, - PTL5_FN, PTL5_OUT, PTL5_IN, 0, - PTL4_FN, PTL4_OUT, PTL4_IN, 0, - PTL3_FN, PTL3_OUT, PTL3_IN, 0, - PTL2_FN, PTL2_OUT, PTL2_IN, 0, - PTL1_FN, PTL1_OUT, PTL1_IN, 0, - PTL0_FN, PTL0_OUT, PTL0_IN, 0 } + 0, 0, 0, 0, /* reserved: always set 1 */ + PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU, + PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU, + PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU, + PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU, + PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU, + PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU, + PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU } }, { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) { - 0, 0, 0, 0, /* reserved: always set 1 */ - PTM6_FN, PTM6_OUT, PTM6_IN, 0, - PTM5_FN, PTM5_OUT, PTM5_IN, 0, - PTM4_FN, PTM4_OUT, PTM4_IN, 0, + PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU, + PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU, + PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU, + PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU, PTM3_FN, PTM3_OUT, PTM3_IN, 0, PTM2_FN, PTM2_OUT, PTM2_IN, 0, PTM1_FN, PTM1_OUT, PTM1_IN, 0, PTM0_FN, PTM0_OUT, PTM0_IN, 0 } }, { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) { - PTN7_FN, PTN7_OUT, PTN7_IN, 0, + 0, 0, 0, 0, /* reserved: always set 1 */ PTN6_FN, PTN6_OUT, PTN6_IN, 0, PTN5_FN, PTN5_OUT, PTN5_IN, 0, - PTN4_FN, PTN4_OUT, PTN4_IN, 0, - PTN3_FN, PTN3_OUT, PTN3_IN, 0, - PTN2_FN, PTN2_OUT, PTN2_IN, 0, - PTN1_FN, PTN1_OUT, PTN1_IN, 0, - PTN0_FN, PTN0_OUT, PTN0_IN, 0 } + PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU, + PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU, + PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU, + PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU, + PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU } }, { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) { - PTO7_FN, PTO7_OUT, PTO7_IN, 0, - PTO6_FN, PTO6_OUT, PTO6_IN, 0, - PTO5_FN, PTO5_OUT, PTO5_IN, 0, - PTO4_FN, PTO4_OUT, PTO4_IN, 0, - PTO3_FN, PTO3_OUT, PTO3_IN, 0, - PTO2_FN, PTO2_OUT, PTO2_IN, 0, - PTO1_FN, PTO1_OUT, PTO1_IN, 0, - PTO0_FN, PTO0_OUT, PTO0_IN, 0 } + PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU, + PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU, + PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU, + PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU, + PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU, + PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU, + PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU, + PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU } }, +#if 0 /* FIXME: Remove it? */ { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) { 0, 0, 0, 0, /* reserved: always set 1 */ PTP6_FN, PTP6_OUT, PTP6_IN, 0, @@ -1670,6 +1883,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTP1_FN, PTP1_OUT, PTP1_IN, 0, PTP0_FN, PTP0_OUT, PTP0_IN, 0 } }, +#endif { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) { 0, 0, 0, 0, /* reserved: always set 1 */ PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0, @@ -1701,14 +1915,14 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTS0_FN, PTS0_OUT, PTS0_IN, 0 } }, { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) { - 0, 0, 0, 0, /* reserved: always set 1 */ - 0, 0, 0, 0, /* reserved: always set 1 */ - PTT5_FN, PTT5_OUT, PTT5_IN, 0, - PTT4_FN, PTT4_OUT, PTT4_IN, 0, - PTT3_FN, PTT3_OUT, PTT3_IN, 0, - PTT2_FN, PTT2_OUT, PTT2_IN, 0, - PTT1_FN, PTT1_OUT, PTT1_IN, 0, - PTT0_FN, PTT0_OUT, PTT0_IN, 0 } + PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU, + PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU, + PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU, + PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU, + PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU, + PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU, + PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU, + PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU } }, { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) { PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU, @@ -1727,16 +1941,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU, PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU, PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU, - PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU, - PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU } + PTV1_FN, PTV1_OUT, PTV1_IN, 0, + PTV0_FN, PTV0_OUT, PTV0_IN, 0 } }, { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) { - PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU, - PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU, - PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU, - PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU, - PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU, - PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU, + PTW7_FN, PTW7_OUT, PTW7_IN, 0, + PTW6_FN, PTW6_OUT, PTW6_IN, 0, + PTW5_FN, PTW5_OUT, PTW5_IN, 0, + PTW4_FN, PTW4_OUT, PTW4_IN, 0, + PTW3_FN, PTW3_OUT, PTW3_IN, 0, + PTW2_FN, PTW2_OUT, PTW2_IN, 0, PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU, PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU } }, @@ -1761,32 +1975,32 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU } }, { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) { - 0, PTZ7_OUT, PTZ7_IN, 0, - 0, PTZ6_OUT, PTZ6_IN, 0, - 0, PTZ5_OUT, PTZ5_IN, 0, - 0, PTZ4_OUT, PTZ4_IN, 0, - 0, PTZ3_OUT, PTZ3_IN, 0, - 0, PTZ2_OUT, PTZ2_IN, 0, - 0, PTZ1_OUT, PTZ1_IN, 0, - 0, PTZ0_OUT, PTZ0_IN, 0 } + PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0, + PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0, + PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0, + PTZ4_FN, PTZ4_OUT, PTZ4_IN, 0, + PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0, + PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0, + PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0, + PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 } }, { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) { - PS0_15_FN3, PS0_15_FN1, - PS0_14_FN3, PS0_14_FN1, - PS0_13_FN3, PS0_13_FN1, - PS0_12_FN3, PS0_12_FN1, - 0, 0, - 0, 0, + PS0_15_FN1, PS0_15_FN2, + PS0_14_FN1, PS0_14_FN2, + PS0_13_FN1, PS0_13_FN2, + PS0_12_FN1, PS0_12_FN2, + PS0_11_FN1, PS0_11_FN2, + PS0_10_FN1, PS0_10_FN2, + PS0_9_FN1, PS0_9_FN2, + PS0_8_FN1, PS0_8_FN2, + PS0_7_FN1, PS0_7_FN2, + PS0_6_FN1, PS0_6_FN2, + PS0_5_FN1, PS0_5_FN2, + PS0_4_FN1, PS0_4_FN2, + PS0_3_FN1, PS0_3_FN2, + PS0_2_FN1, PS0_2_FN2, 0, 0, - 0, 0, - PS0_7_FN2, PS0_7_FN1, - PS0_6_FN2, PS0_6_FN1, - PS0_5_FN2, PS0_5_FN1, - PS0_4_FN2, PS0_4_FN1, - PS0_3_FN2, PS0_3_FN1, - PS0_2_FN2, PS0_2_FN1, - PS0_1_FN2, PS0_1_FN1, 0, 0, } }, { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) { @@ -1795,73 +2009,136 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, + PS1_10_FN1, PS1_10_FN2, + PS1_9_FN1, PS1_9_FN2, + PS1_8_FN1, PS1_8_FN2, 0, 0, 0, 0, 0, 0, - PS1_7_FN1, PS1_7_FN3, - PS1_6_FN1, PS1_6_FN3, - 0, 0, - 0, 0, 0, 0, 0, 0, + PS1_2_FN1, PS1_2_FN2, 0, 0, 0, 0, } }, { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) { 0, 0, 0, 0, - PS2_13_FN3, PS2_13_FN1, - PS2_12_FN3, PS2_12_FN1, + PS2_13_FN1, PS2_13_FN2, + PS2_12_FN1, PS2_12_FN2, 0, 0, 0, 0, 0, 0, 0, 0, + PS2_7_FN1, PS2_7_FN2, + PS2_6_FN1, PS2_6_FN2, + PS2_5_FN1, PS2_5_FN2, + PS2_4_FN1, PS2_4_FN2, 0, 0, + PS2_2_FN1, PS2_2_FN2, 0, 0, + 0, 0, } + }, + { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) { + PS3_15_FN1, PS3_15_FN2, + PS3_14_FN1, PS3_14_FN2, + PS3_13_FN1, PS3_13_FN2, + PS3_12_FN1, PS3_12_FN2, + PS3_11_FN1, PS3_11_FN2, + PS3_10_FN1, PS3_10_FN2, + PS3_9_FN1, PS3_9_FN2, + PS3_8_FN1, PS3_8_FN2, + PS3_7_FN1, PS3_7_FN2, 0, 0, 0, 0, 0, 0, 0, 0, - PS2_1_FN1, PS2_1_FN2, - PS2_0_FN1, PS2_0_FN2, } + PS3_2_FN1, PS3_2_FN2, + PS3_1_FN1, PS3_1_FN2, + 0, 0, } }, + { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) { - PS4_15_FN2, PS4_15_FN1, - PS4_14_FN2, PS4_14_FN1, - PS4_13_FN2, PS4_13_FN1, - PS4_12_FN2, PS4_12_FN1, - PS4_11_FN2, PS4_11_FN1, - PS4_10_FN2, PS4_10_FN1, - PS4_9_FN2, PS4_9_FN1, 0, 0, + PS4_14_FN1, PS4_14_FN2, + PS4_13_FN1, PS4_13_FN2, + PS4_12_FN1, PS4_12_FN2, 0, 0, + PS4_10_FN1, PS4_10_FN2, + PS4_9_FN1, PS4_9_FN2, + PS4_8_FN1, PS4_8_FN2, 0, 0, 0, 0, 0, 0, - PS4_3_FN2, PS4_3_FN1, - PS4_2_FN2, PS4_2_FN1, - PS4_1_FN2, PS4_1_FN1, - PS4_0_FN2, PS4_0_FN1, } + PS4_4_FN1, PS4_4_FN2, + PS4_3_FN1, PS4_3_FN2, + PS4_2_FN1, PS4_2_FN2, + PS4_1_FN1, PS4_1_FN2, + PS4_0_FN1, PS4_0_FN2, } }, { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, - 0, 0, + PS5_11_FN1, PS5_11_FN2, + PS5_10_FN1, PS5_10_FN2, PS5_9_FN1, PS5_9_FN2, PS5_8_FN1, PS5_8_FN2, PS5_7_FN1, PS5_7_FN2, PS5_6_FN1, PS5_6_FN2, PS5_5_FN1, PS5_5_FN2, + PS5_4_FN1, PS5_4_FN2, + PS5_3_FN1, PS5_3_FN2, + PS5_2_FN1, PS5_2_FN2, + 0, 0, + 0, 0, } + }, + { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) { + PS6_15_FN1, PS6_15_FN2, + PS6_14_FN1, PS6_14_FN2, + PS6_13_FN1, PS6_13_FN2, + PS6_12_FN1, PS6_12_FN2, + PS6_11_FN1, PS6_11_FN2, + PS6_10_FN1, PS6_10_FN2, + PS6_9_FN1, PS6_9_FN2, + PS6_8_FN1, PS6_8_FN2, + PS6_7_FN1, PS6_7_FN2, + PS6_6_FN1, PS6_6_FN2, + PS6_5_FN1, PS6_5_FN2, + PS6_4_FN1, PS6_4_FN2, + PS6_3_FN1, PS6_3_FN2, + PS6_2_FN1, PS6_2_FN2, + PS6_1_FN1, PS6_1_FN2, + PS6_0_FN1, PS6_0_FN2, } + }, + { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) { + PS7_15_FN1, PS7_15_FN2, + PS7_14_FN1, PS7_14_FN2, + PS7_13_FN1, PS7_13_FN2, + PS7_12_FN1, PS7_12_FN2, + PS7_11_FN1, PS7_11_FN2, + PS7_10_FN1, PS7_10_FN2, + PS7_9_FN1, PS7_9_FN2, + PS7_8_FN1, PS7_8_FN2, + PS7_7_FN1, PS7_7_FN2, + PS7_6_FN1, PS7_6_FN2, + PS7_5_FN1, PS7_5_FN2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, } }, - { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) { + { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) { + PS8_15_FN1, PS8_15_FN2, + PS8_14_FN1, PS8_14_FN2, + PS8_13_FN1, PS8_13_FN2, + PS8_12_FN1, PS8_12_FN2, + PS8_11_FN1, PS8_11_FN2, + PS8_10_FN1, PS8_10_FN2, + PS8_9_FN1, PS8_9_FN2, + PS8_8_FN1, PS8_8_FN2, 0, 0, 0, 0, 0, 0, @@ -1869,15 +2146,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - 0, 0, - PS6_7_FN_AN, PS6_7_FN_EV, - PS6_6_FN_AN, PS6_6_FN_EV, - PS6_5_FN_AN, PS6_5_FN_EV, - PS6_4_FN_AN, PS6_4_FN_EV, - PS6_3_FN_AN, PS6_3_FN_EV, - PS6_2_FN_AN, PS6_2_FN_EV, - PS6_1_FN_AN, PS6_1_FN_EV, - PS6_0_FN_AN, PS6_0_FN_EV, } + 0, 0, } }, {} }; @@ -1920,7 +2189,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA } }, { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) { - PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, + 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } }, { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) { @@ -1928,15 +2197,15 @@ static struct pinmux_data_reg pinmux_data_regs[] = { PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } }, { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) { - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + 0, PTL6_DATA, PTL5_DATA, PTL4_DATA, PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } }, { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) { - 0, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } }, { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) { - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + 0, PTN6_DATA, PTN5_DATA, PTN4_DATA, PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } }, { PINMUX_DATA_REG("PODR", 0xffec0050, 8) { @@ -1944,7 +2213,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA } }, { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) { - 0, PTP6_DATA, PTP5_DATA, PTP4_DATA, + PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA, PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA } }, { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) { @@ -1960,7 +2229,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } }, { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) { - 0, 0, PTT5_DATA, PTT4_DATA, + PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } }, { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) { @@ -2000,8 +2269,8 @@ static struct pinmux_info sh7757_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_D0, + .first_gpio = GPIO_PTA0, + .last_gpio = GPIO_FN_ON_DQ0, .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, @@ -2015,5 +2284,4 @@ static int __init plat_pinmux_setup(void) { return register_pinmux(&sh7757_pinmux_info); } - arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 79c556e56262..828c9657eb52 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -524,6 +524,70 @@ static struct platform_device veu1_device = { }, }; +/* BEU0 */ +static struct uio_info beu0_platform_data = { + .name = "BEU0", + .version = "0", + .irq = evt2irq(0x8A0), +}; + +static struct resource beu0_resources[] = { + [0] = { + .name = "BEU0", + .start = 0xfe930000, + .end = 0xfe933400, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device beu0_device = { + .name = "uio_pdrv_genirq", + .id = 6, + .dev = { + .platform_data = &beu0_platform_data, + }, + .resource = beu0_resources, + .num_resources = ARRAY_SIZE(beu0_resources), + .archdata = { + .hwblk_id = HWBLK_BEU0, + }, +}; + +/* BEU1 */ +static struct uio_info beu1_platform_data = { + .name = "BEU1", + .version = "0", + .irq = evt2irq(0xA00), +}; + +static struct resource beu1_resources[] = { + [0] = { + .name = "BEU1", + .start = 0xfe940000, + .end = 0xfe943400, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device beu1_device = { + .name = "uio_pdrv_genirq", + .id = 7, + .dev = { + .platform_data = &beu1_platform_data, + }, + .resource = beu1_resources, + .num_resources = ARRAY_SIZE(beu1_resources), + .archdata = { + .hwblk_id = HWBLK_BEU1, + }, +}; + static struct sh_timer_config cmt_platform_data = { .channel_offset = 0x60, .timer_bit = 5, @@ -857,6 +921,8 @@ static struct platform_device *sh7724_devices[] __initdata = { &vpu_device, &veu0_device, &veu1_device, + &beu0_device, + &beu1_device, &jpu_device, &spu0_device, &spu1_device, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index 444aca95b20d..749c6388d5a5 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -26,7 +26,7 @@ static struct plat_sci_port scif2_platform_data = { static struct platform_device scif2_device = { .name = "sh-sci", - .id = 2, + .id = 0, .dev = { .platform_data = &scif2_platform_data, }, @@ -41,7 +41,7 @@ static struct plat_sci_port scif3_platform_data = { static struct platform_device scif3_device = { .name = "sh-sci", - .id = 3, + .id = 1, .dev = { .platform_data = &scif3_platform_data, }, @@ -56,7 +56,7 @@ static struct plat_sci_port scif4_platform_data = { static struct platform_device scif4_device = { .name = "sh-sci", - .id = 4, + .id = 2, .dev = { .platform_data = &scif4_platform_data, }, @@ -163,39 +163,23 @@ enum { IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, - SDHI, - DVC, - IRQ8, IRQ9, IRQ10, - WDT0, - TMU0, TMU1, TMU2, TMU2_TICPI, + SDHI, DVC, + IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15, + TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, HUDI, - ARC4, - DMAC0, - IRQ11, - SCIF2, - DMAC1_6, - USB0, - IRQ12, + DMAC0_5, DMAC6_7, DMAC8_11, + SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, + USB0, USB1, JMC, - SPI1, - IRQ13, IRQ14, - USB1, + SPI0, SPI1, TMR01, TMR23, TMR45, - WDT1, FRT, - LPC, - SCIF0, SCIF1, SCIF3, - PECI0I, PECI1I, PECI2I, - IRQ15, + LPC, LPC5, LPC6, LPC7, LPC8, + PECI0, PECI1, PECI2, PECI3, PECI4, PECI5, ETHERC, - SPI0, - ADC1, - DMAC1_8, + ADC0, ADC1, SIM, - TMU3, TMU4, TMU5, - ADC0, - SCIF4, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC1_0, IIC1_1, IIC1_2, IIC1_3, IIC2_0, IIC2_1, IIC2_2, IIC2_3, @@ -206,9 +190,23 @@ enum { IIC7_0, IIC7_1, IIC7_2, IIC7_3, IIC8_0, IIC8_1, IIC8_2, IIC8_3, IIC9_0, IIC9_1, IIC9_2, IIC9_3, - PCIINTA, - PCIE, + ONFICTL, + MMC1, MMC2, + ECCU, + PCIC, + G200, + RSPI, SGPIO, + DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19, + DMINT20, DMINT21, DMINT22, DMINT23, + DDRECC, + TSIP, + PCIE_BRIDGE, + WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B, + GETHER0, GETHER1, GETHER2, + PBIA, PBIB, PBIC, + DMAE2, DMAE3, + SERMUX2, SERMUX3, /* interrupt groups */ @@ -221,19 +219,18 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(DVC, 0x4e0), INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), INTC_VECT(IRQ10, 0x540), - INTC_VECT(WDT0, 0x560), INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), INTC_VECT(ARC4, 0x620), - INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), - INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), - INTC_VECT(DMAC0, 0x6c0), + INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660), + INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0), + INTC_VECT(DMAC0_5, 0x6c0), INTC_VECT(IRQ11, 0x6e0), INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), - INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), - INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0), + INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0), + INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0), INTC_VECT(USB0, 0x840), INTC_VECT(IRQ12, 0x880), INTC_VECT(JMC, 0x8a0), @@ -242,7 +239,6 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(USB1, 0x920), INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), INTC_VECT(TMR45, 0xa40), - INTC_VECT(WDT1, 0xa60), INTC_VECT(FRT, 0xa80), INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), @@ -250,14 +246,14 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), - INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20), - INTC_VECT(PECI2I, 0xc40), + INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20), + INTC_VECT(PECI2, 0xc40), INTC_VECT(IRQ15, 0xc60), INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), INTC_VECT(SPI0, 0xcc0), INTC_VECT(ADC1, 0xce0), - INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20), - INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60), + INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20), + INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60), INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), @@ -278,17 +274,47 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), - INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980), + INTC_VECT(IIC6_2, 0x1920), + INTC_VECT(ONFICTL, 0x1960), + INTC_VECT(IIC6_3, 0x1980), INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), - INTC_VECT(PCIINTA, 0x1ce0), - INTC_VECT(PCIE, 0x1e00), - INTC_VECT(SGPIO, 0x1f80), - INTC_VECT(SGPIO, 0x1fa0), + INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80), + INTC_VECT(ECCU, 0x1cc0), + INTC_VECT(PCIC, 0x1ce0), + INTC_VECT(G200, 0x1d00), + INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0), + INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0), + INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0), + INTC_VECT(PECI5, 0x1f00), + INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0), + INTC_VECT(SGPIO, 0x1fc0), + INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420), + INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460), + INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0), + INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520), + INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560), + INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600), + INTC_VECT(DDRECC, 0x2620), + INTC_VECT(TSIP, 0x2640), + INTC_VECT(PCIE_BRIDGE, 0x27c0), + INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820), + INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860), + INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0), + INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0), + INTC_VECT(WDT8B, 0x2900), + INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980), + INTC_VECT(GETHER2, 0x29a0), + INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20), + INTC_VECT(PBIC, 0x2a40), + INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80), + INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40), + INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80), + INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20), }; static struct intc_group groups[] __initdata = { @@ -312,31 +338,45 @@ static struct intc_mask_reg mask_registers[] __initdata = { { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45, - TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0, - HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012 + 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45, + TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5, + HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012 } }, { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, - ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I, + ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1, ARC4, 0, SPI1, JMC, 0, 0, 0, DVC } }, { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ - { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0, - 0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, + { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0, + 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, - IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2 + IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2 } }, - { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */ - { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0, + { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */ + { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2, IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, - PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3, + PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3, IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 } }, + + { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */ + { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0, + 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC, + PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP, + DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22 + } }, + + { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */ + { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0, + DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0, + 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8, + DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17 + } }, }; #define INTPRI 0xffd00010 @@ -372,6 +412,22 @@ static struct intc_mask_reg mask_registers[] __initdata = { #define INT2PRI29 0xffd100b4 #define INT2PRI30 0xffd100b8 #define INT2PRI31 0xffd100bc +#define INT2PRI32 0xffd20000 +#define INT2PRI33 0xffd20004 +#define INT2PRI34 0xffd20008 +#define INT2PRI35 0xffd2000c +#define INT2PRI36 0xffd20010 +#define INT2PRI37 0xffd20014 +#define INT2PRI38 0xffd20018 +#define INT2PRI39 0xffd2001c +#define INT2PRI40 0xffd200a0 +#define INT2PRI41 0xffd200a4 +#define INT2PRI42 0xffd200a8 +#define INT2PRI43 0xffd200ac +#define INT2PRI44 0xffd200b0 +#define INT2PRI45 0xffd200b4 +#define INT2PRI46 0xffd200b8 +#define INT2PRI47 0xffd200bc static struct intc_prio_reg prio_registers[] __initdata = { { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, @@ -379,39 +435,61 @@ static struct intc_prio_reg prio_registers[] __initdata = { { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, - { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } }, - { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } }, + { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } }, + { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } }, { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, - { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } }, - { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } }, + { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } }, + { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } }, { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, - { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } }, - { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } }, + { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } }, + { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } }, { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, - { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } }, + { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } }, { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, - { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } }, - { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } }, - { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } }, + { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } }, + { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } }, + { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } }, { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, - { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } }, - { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } }, - { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } }, + { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } }, + { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } }, + { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } }, { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, - { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } }, + { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } }, { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, + { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } }, + { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } }, + { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } }, + { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } }, + { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } }, + { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } }, + { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } }, + { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } }, + { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } }, + { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } }, + { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } }, + { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } }, + { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } }, + { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } }, + { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } }, + { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } }, +}; + +static struct intc_sense_reg sense_registers_irq8to15[] __initdata = { + { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12, + IRQ11, IRQ10, IRQ9, IRQ8 } }, }; static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, - mask_registers, prio_registers, NULL); + mask_registers, prio_registers, + sense_registers_irq8to15); /* Support for external interrupt pins in IRQ mode */ static struct intc_vect vectors_irq0123[] __initdata = { diff --git a/arch/sh/kernel/kprobes.c b/arch/sh/kernel/kprobes.c index 4049d99f76e1..1208b09e95c3 100644 --- a/arch/sh/kernel/kprobes.c +++ b/arch/sh/kernel/kprobes.c @@ -20,9 +20,9 @@ DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL; DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); -static struct kprobe saved_current_opcode; -static struct kprobe saved_next_opcode; -static struct kprobe saved_next_opcode2; +static DEFINE_PER_CPU(struct kprobe, saved_current_opcode); +static DEFINE_PER_CPU(struct kprobe, saved_next_opcode); +static DEFINE_PER_CPU(struct kprobe, saved_next_opcode2); #define OPCODE_JMP(x) (((x) & 0xF0FF) == 0x402b) #define OPCODE_JSR(x) (((x) & 0xF0FF) == 0x400b) @@ -102,16 +102,21 @@ int __kprobes kprobe_handle_illslot(unsigned long pc) void __kprobes arch_remove_kprobe(struct kprobe *p) { - if (saved_next_opcode.addr != 0x0) { + struct kprobe *saved = &__get_cpu_var(saved_next_opcode); + + if (saved->addr) { arch_disarm_kprobe(p); - arch_disarm_kprobe(&saved_next_opcode); - saved_next_opcode.addr = 0x0; - saved_next_opcode.opcode = 0x0; - - if (saved_next_opcode2.addr != 0x0) { - arch_disarm_kprobe(&saved_next_opcode2); - saved_next_opcode2.addr = 0x0; - saved_next_opcode2.opcode = 0x0; + arch_disarm_kprobe(saved); + + saved->addr = NULL; + saved->opcode = 0; + + saved = &__get_cpu_var(saved_next_opcode2); + if (saved->addr) { + arch_disarm_kprobe(saved); + + saved->addr = NULL; + saved->opcode = 0; } } } @@ -141,57 +146,59 @@ static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs, */ static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs) { - kprobe_opcode_t *addr = NULL; - saved_current_opcode.addr = (kprobe_opcode_t *) (regs->pc); - addr = saved_current_opcode.addr; + __get_cpu_var(saved_current_opcode).addr = (kprobe_opcode_t *)regs->pc; if (p != NULL) { + struct kprobe *op1, *op2; + arch_disarm_kprobe(p); + op1 = &__get_cpu_var(saved_next_opcode); + op2 = &__get_cpu_var(saved_next_opcode2); + if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) { unsigned int reg_nr = ((p->opcode >> 8) & 0x000F); - saved_next_opcode.addr = - (kprobe_opcode_t *) regs->regs[reg_nr]; + op1->addr = (kprobe_opcode_t *) regs->regs[reg_nr]; } else if (OPCODE_BRA(p->opcode) || OPCODE_BSR(p->opcode)) { unsigned long disp = (p->opcode & 0x0FFF); - saved_next_opcode.addr = + op1->addr = (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); } else if (OPCODE_BRAF(p->opcode) || OPCODE_BSRF(p->opcode)) { unsigned int reg_nr = ((p->opcode >> 8) & 0x000F); - saved_next_opcode.addr = + op1->addr = (kprobe_opcode_t *) (regs->pc + 4 + regs->regs[reg_nr]); } else if (OPCODE_RTS(p->opcode)) { - saved_next_opcode.addr = (kprobe_opcode_t *) regs->pr; + op1->addr = (kprobe_opcode_t *) regs->pr; } else if (OPCODE_BF(p->opcode) || OPCODE_BT(p->opcode)) { unsigned long disp = (p->opcode & 0x00FF); /* case 1 */ - saved_next_opcode.addr = p->addr + 1; + op1->addr = p->addr + 1; /* case 2 */ - saved_next_opcode2.addr = + op2->addr = (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); - saved_next_opcode2.opcode = *(saved_next_opcode2.addr); - arch_arm_kprobe(&saved_next_opcode2); + op2->opcode = *(op2->addr); + arch_arm_kprobe(op2); } else if (OPCODE_BF_S(p->opcode) || OPCODE_BT_S(p->opcode)) { unsigned long disp = (p->opcode & 0x00FF); /* case 1 */ - saved_next_opcode.addr = p->addr + 2; + op1->addr = p->addr + 2; /* case 2 */ - saved_next_opcode2.addr = + op2->addr = (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); - saved_next_opcode2.opcode = *(saved_next_opcode2.addr); - arch_arm_kprobe(&saved_next_opcode2); + op2->opcode = *(op2->addr); + arch_arm_kprobe(op2); } else { - saved_next_opcode.addr = p->addr + 1; + op1->addr = p->addr + 1; } - saved_next_opcode.opcode = *(saved_next_opcode.addr); - arch_arm_kprobe(&saved_next_opcode); + op1->opcode = *(op1->addr); + arch_arm_kprobe(op1); } } @@ -376,21 +383,23 @@ static int __kprobes post_kprobe_handler(struct pt_regs *regs) cur->post_handler(cur, regs, 0); } - if (saved_next_opcode.addr != 0x0) { - arch_disarm_kprobe(&saved_next_opcode); - saved_next_opcode.addr = 0x0; - saved_next_opcode.opcode = 0x0; + p = &__get_cpu_var(saved_next_opcode); + if (p->addr) { + arch_disarm_kprobe(p); + p->addr = NULL; + p->opcode = 0; - addr = saved_current_opcode.addr; - saved_current_opcode.addr = 0x0; + addr = __get_cpu_var(saved_current_opcode).addr; + __get_cpu_var(saved_current_opcode).addr = NULL; p = get_kprobe(addr); arch_arm_kprobe(p); - if (saved_next_opcode2.addr != 0x0) { - arch_disarm_kprobe(&saved_next_opcode2); - saved_next_opcode2.addr = 0x0; - saved_next_opcode2.opcode = 0x0; + p = &__get_cpu_var(saved_next_opcode2); + if (p->addr) { + arch_disarm_kprobe(p); + p->addr = NULL; + p->opcode = 0; } } @@ -572,14 +581,5 @@ static struct kprobe trampoline_p = { int __init arch_init_kprobes(void) { - saved_next_opcode.addr = 0x0; - saved_next_opcode.opcode = 0x0; - - saved_current_opcode.addr = 0x0; - saved_current_opcode.opcode = 0x0; - - saved_next_opcode2.addr = 0x0; - saved_next_opcode2.opcode = 0x0; - return register_kprobe(&trampoline_p); } diff --git a/arch/sh/kernel/ptrace.c b/arch/sh/kernel/ptrace.c new file mode 100644 index 000000000000..0a05983633ca --- /dev/null +++ b/arch/sh/kernel/ptrace.c @@ -0,0 +1,33 @@ +#include <linux/ptrace.h> + +/** + * regs_query_register_offset() - query register offset from its name + * @name: the name of a register + * + * regs_query_register_offset() returns the offset of a register in struct + * pt_regs from its name. If the name is invalid, this returns -EINVAL; + */ +int regs_query_register_offset(const char *name) +{ + const struct pt_regs_offset *roff; + for (roff = regoffset_table; roff->name != NULL; roff++) + if (!strcmp(roff->name, name)) + return roff->offset; + return -EINVAL; +} + +/** + * regs_query_register_name() - query register name from its offset + * @offset: the offset of a register in struct pt_regs. + * + * regs_query_register_name() returns the name of a register from its + * offset in struct pt_regs. If the @offset is invalid, this returns NULL; + */ +const char *regs_query_register_name(unsigned int offset) +{ + const struct pt_regs_offset *roff; + for (roff = regoffset_table; roff->name != NULL; roff++) + if (roff->offset == offset) + return roff->name; + return NULL; +} diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c index 6c4bbba2a675..2cd42b58cb20 100644 --- a/arch/sh/kernel/ptrace_32.c +++ b/arch/sh/kernel/ptrace_32.c @@ -274,6 +274,33 @@ static int dspregs_active(struct task_struct *target, } #endif +const struct pt_regs_offset regoffset_table[] = { + REGS_OFFSET_NAME(0), + REGS_OFFSET_NAME(1), + REGS_OFFSET_NAME(2), + REGS_OFFSET_NAME(3), + REGS_OFFSET_NAME(4), + REGS_OFFSET_NAME(5), + REGS_OFFSET_NAME(6), + REGS_OFFSET_NAME(7), + REGS_OFFSET_NAME(8), + REGS_OFFSET_NAME(9), + REGS_OFFSET_NAME(10), + REGS_OFFSET_NAME(11), + REGS_OFFSET_NAME(12), + REGS_OFFSET_NAME(13), + REGS_OFFSET_NAME(14), + REGS_OFFSET_NAME(15), + REG_OFFSET_NAME(pc), + REG_OFFSET_NAME(pr), + REG_OFFSET_NAME(sr), + REG_OFFSET_NAME(gbr), + REG_OFFSET_NAME(mach), + REG_OFFSET_NAME(macl), + REG_OFFSET_NAME(tra), + REG_OFFSET_END, +}; + /* * These are our native regset flavours. */ diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c index 5fd644da7f02..b97817016b6a 100644 --- a/arch/sh/kernel/ptrace_64.c +++ b/arch/sh/kernel/ptrace_64.c @@ -252,6 +252,85 @@ static int fpregs_active(struct task_struct *target, } #endif +const struct pt_regs_offset regoffset_table[] = { + REG_OFFSET_NAME(pc), + REG_OFFSET_NAME(sr), + REG_OFFSET_NAME(syscall_nr), + REGS_OFFSET_NAME(0), + REGS_OFFSET_NAME(1), + REGS_OFFSET_NAME(2), + REGS_OFFSET_NAME(3), + REGS_OFFSET_NAME(4), + REGS_OFFSET_NAME(5), + REGS_OFFSET_NAME(6), + REGS_OFFSET_NAME(7), + REGS_OFFSET_NAME(8), + REGS_OFFSET_NAME(9), + REGS_OFFSET_NAME(10), + REGS_OFFSET_NAME(11), + REGS_OFFSET_NAME(12), + REGS_OFFSET_NAME(13), + REGS_OFFSET_NAME(14), + REGS_OFFSET_NAME(15), + REGS_OFFSET_NAME(16), + REGS_OFFSET_NAME(17), + REGS_OFFSET_NAME(18), + REGS_OFFSET_NAME(19), + REGS_OFFSET_NAME(20), + REGS_OFFSET_NAME(21), + REGS_OFFSET_NAME(22), + REGS_OFFSET_NAME(23), + REGS_OFFSET_NAME(24), + REGS_OFFSET_NAME(25), + REGS_OFFSET_NAME(26), + REGS_OFFSET_NAME(27), + REGS_OFFSET_NAME(28), + REGS_OFFSET_NAME(29), + REGS_OFFSET_NAME(30), + REGS_OFFSET_NAME(31), + REGS_OFFSET_NAME(32), + REGS_OFFSET_NAME(33), + REGS_OFFSET_NAME(34), + REGS_OFFSET_NAME(35), + REGS_OFFSET_NAME(36), + REGS_OFFSET_NAME(37), + REGS_OFFSET_NAME(38), + REGS_OFFSET_NAME(39), + REGS_OFFSET_NAME(40), + REGS_OFFSET_NAME(41), + REGS_OFFSET_NAME(42), + REGS_OFFSET_NAME(43), + REGS_OFFSET_NAME(44), + REGS_OFFSET_NAME(45), + REGS_OFFSET_NAME(46), + REGS_OFFSET_NAME(47), + REGS_OFFSET_NAME(48), + REGS_OFFSET_NAME(49), + REGS_OFFSET_NAME(50), + REGS_OFFSET_NAME(51), + REGS_OFFSET_NAME(52), + REGS_OFFSET_NAME(53), + REGS_OFFSET_NAME(54), + REGS_OFFSET_NAME(55), + REGS_OFFSET_NAME(56), + REGS_OFFSET_NAME(57), + REGS_OFFSET_NAME(58), + REGS_OFFSET_NAME(59), + REGS_OFFSET_NAME(60), + REGS_OFFSET_NAME(61), + REGS_OFFSET_NAME(62), + REGS_OFFSET_NAME(63), + TREGS_OFFSET_NAME(0), + TREGS_OFFSET_NAME(1), + TREGS_OFFSET_NAME(2), + TREGS_OFFSET_NAME(3), + TREGS_OFFSET_NAME(4), + TREGS_OFFSET_NAME(5), + TREGS_OFFSET_NAME(6), + TREGS_OFFSET_NAME(7), + REG_OFFSET_END, +}; + /* * These are our native regset flavours. */ diff --git a/arch/sh/kernel/reboot.c b/arch/sh/kernel/reboot.c index b1fca66bb92e..ca6a5ca64015 100644 --- a/arch/sh/kernel/reboot.c +++ b/arch/sh/kernel/reboot.c @@ -9,6 +9,7 @@ #include <asm/addrspace.h> #include <asm/reboot.h> #include <asm/system.h> +#include <asm/tlbflush.h> void (*pm_power_off)(void); EXPORT_SYMBOL(pm_power_off); @@ -25,6 +26,9 @@ static void native_machine_restart(char * __unused) { local_irq_disable(); + /* Destroy all of the TLBs in preparation for reset by MMU */ + __flush_tlb_global(); + /* Address error with SR.BL=1 first. */ trigger_address_error(); diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S index 19fd11dd9871..3c6d669740a7 100644 --- a/arch/sh/kernel/syscalls_32.S +++ b/arch/sh/kernel/syscalls_32.S @@ -353,3 +353,6 @@ ENTRY(sys_call_table) .long sys_pwritev .long sys_rt_tgsigqueueinfo /* 335 */ .long sys_perf_event_open + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S index 2048a20d7c80..66585708ce90 100644 --- a/arch/sh/kernel/syscalls_64.S +++ b/arch/sh/kernel/syscalls_64.S @@ -393,3 +393,6 @@ sys_call_table: .long sys_perf_event_open .long sys_recvmmsg /* 365 */ .long sys_accept4 + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c index c86a08540258..038793286990 100644 --- a/arch/sh/mm/consistent.c +++ b/arch/sh/mm/consistent.c @@ -38,11 +38,12 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size, void *ret, *ret_nocache; int order = get_order(size); + gfp |= __GFP_ZERO; + ret = (void *)__get_free_pages(gfp, order); if (!ret) return NULL; - memset(ret, 0, size); /* * Pages from the page allocator may have data present in * cache. So flush the cache before using uncached memory. diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index d0e249100e98..105f559d946d 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -47,7 +47,6 @@ static pte_t *__get_pte_phys(unsigned long addr) pgd_t *pgd; pud_t *pud; pmd_t *pmd; - pte_t *pte; pgd = pgd_offset_k(addr); if (pgd_none(*pgd)) { @@ -67,8 +66,7 @@ static pte_t *__get_pte_phys(unsigned long addr) return NULL; } - pte = pte_offset_kernel(pmd, addr); - return pte; + return pte_offset_kernel(pmd, addr); } static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) @@ -125,13 +123,45 @@ void __clear_fixmap(enum fixed_addresses idx, pgprot_t prot) clear_pte_phys(address, prot); } +static pmd_t * __init one_md_table_init(pud_t *pud) +{ + if (pud_none(*pud)) { + pmd_t *pmd; + + pmd = alloc_bootmem_pages(PAGE_SIZE); + pud_populate(&init_mm, pud, pmd); + BUG_ON(pmd != pmd_offset(pud, 0)); + } + + return pmd_offset(pud, 0); +} + +static pte_t * __init one_page_table_init(pmd_t *pmd) +{ + if (pmd_none(*pmd)) { + pte_t *pte; + + pte = alloc_bootmem_pages(PAGE_SIZE); + pmd_populate_kernel(&init_mm, pmd, pte); + BUG_ON(pte != pte_offset_kernel(pmd, 0)); + } + + return pte_offset_kernel(pmd, 0); +} + +static pte_t * __init page_table_kmap_check(pte_t *pte, pmd_t *pmd, + unsigned long vaddr, pte_t *lastpte) +{ + return pte; +} + void __init page_table_range_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { pgd_t *pgd; pud_t *pud; pmd_t *pmd; - pte_t *pte; + pte_t *pte = NULL; int i, j, k; unsigned long vaddr; @@ -144,19 +174,13 @@ void __init page_table_range_init(unsigned long start, unsigned long end, for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { pud = (pud_t *)pgd; for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) { -#ifdef __PAGETABLE_PMD_FOLDED - pmd = (pmd_t *)pud; -#else - pmd = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE); - pud_populate(&init_mm, pud, pmd); + pmd = one_md_table_init(pud); +#ifndef __PAGETABLE_PMD_FOLDED pmd += k; #endif for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { - if (pmd_none(*pmd)) { - pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); - pmd_populate_kernel(&init_mm, pmd, pte); - BUG_ON(pte != pte_offset_kernel(pmd, 0)); - } + pte = page_table_kmap_check(one_page_table_init(pmd), + pmd, vaddr, pte); vaddr += PMD_SIZE; } k = 0; diff --git a/arch/sh/mm/nommu.c b/arch/sh/mm/nommu.c index 7694f50c9034..36312d254faf 100644 --- a/arch/sh/mm/nommu.c +++ b/arch/sh/mm/nommu.c @@ -67,6 +67,10 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) BUG(); } +void __flush_tlb_global(void) +{ +} + void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) { } diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c index 3fbe03ce8fe3..a6a20d6de4c0 100644 --- a/arch/sh/mm/tlbflush_32.c +++ b/arch/sh/mm/tlbflush_32.c @@ -119,3 +119,19 @@ void local_flush_tlb_mm(struct mm_struct *mm) local_irq_restore(flags); } } + +void __flush_tlb_global(void) +{ + unsigned long flags; + + local_irq_save(flags); + + /* + * This is the most destructive of the TLB flushing options, + * and will tear down all of the UTLB/ITLB mappings, including + * wired entries. + */ + __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR); + + local_irq_restore(flags); +} diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 03db41cc1268..7f5810f5dfdc 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -455,6 +455,11 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) flush_tlb_all(); } +void __flush_tlb_global(void) +{ + flush_tlb_all(); +} + void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) { } diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index b25aa554ee5e..9f56eb978024 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -52,6 +52,8 @@ MIGOR SH_MIGOR RSK7201 SH_RSK7201 RSK7203 SH_RSK7203 AP325RXA SH_AP325RXA +SH2007 SH_SH2007 +SH7757LCR SH_SH7757LCR SH7763RDP SH_SH7763RDP SH7785LCR SH_SH7785LCR SH7785LCR_PT SH_SH7785LCR_PT diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 404a880ea325..d395540ff894 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -27,6 +27,9 @@ extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node); extern struct pci_bus *pci_scan_bus_with_sysdata(int busno); +#ifdef CONFIG_PCI + +#ifdef CONFIG_PCI_DOMAINS static inline int pci_domain_nr(struct pci_bus *bus) { struct pci_sysdata *sd = bus->sysdata; @@ -37,13 +40,12 @@ static inline int pci_proc_domain(struct pci_bus *bus) { return pci_domain_nr(bus); } - +#endif /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */ -#ifdef CONFIG_PCI extern unsigned int pcibios_assign_all_busses(void); extern int pci_legacy_init(void); # ifdef CONFIG_ACPI diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 0859bfd8ae93..d88d09bd619e 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -81,10 +81,10 @@ config XTENSA_VARIANT_S6000 endchoice config XTENSA_UNALIGNED_USER - bool "Unaligned memory access in use space" + bool "Unaligned memory access in user space" help - The Xtensa architecture currently does not handle unaligned - memory accesses in hardware but through an exception handler. + Xtensa processors are often not configured to handle unaligned + memory accesses in hardware, but rather through an exception handler. Per default, unaligned memory accesses are disabled in user space. Say Y here to enable unaligned memory access in user space. @@ -154,8 +154,15 @@ config XTENSA_PLATFORM_ISS config XTENSA_PLATFORM_XT2000 bool "XT2000" help - XT2000 is the name of Tensilica's feature-rich emulation platform. - This hardware is capable of running a full Linux distribution. + XT2000 is the name of Tensilica's older emulation platform. + +config XTENSA_PLATFORM_XTAVNET + bool "XTAVNET" + select XTENSA_CALIBRATE_CCOUNT + select ETHOC + help + Selects support for the Tensilica-configured Avnet emulation boards. + These include the LX60 (XT-AV60), LX200 (XT-AV200), and LX110 (XT-AV110). config XTENSA_PLATFORM_S6105 bool "S6105" diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile index 7608559de93a..34d8427622eb 100644 --- a/arch/xtensa/Makefile +++ b/arch/xtensa/Makefile @@ -24,6 +24,7 @@ export VARIANT # Platform configuration platform-$(CONFIG_XTENSA_PLATFORM_XT2000) := xt2000 +platform-$(CONFIG_XTENSA_PLATFORM_XTAVNET) := xtavnet platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss platform-$(CONFIG_XTENSA_PLATFORM_S6105) := s6105 @@ -61,7 +62,9 @@ ifneq ($(VARIANT),) ifneq ($(COMPILE_ARCH), xtensa) ifndef CROSS_COMPILE - CROSS_COMPILE = xtensa_$(VARIANT)- + CROSS_COMPILE := $(call cc-cross-prefix, xtensa_$(VARIANT)- \ + xtensa-linux-uclibc- xtensa_$(VARIANT)-linux-uclibc- \ + xtensa-linux-gnu- xtensa_$(VARIANT)-linux-gnu-) endif endif endif diff --git a/arch/xtensa/boot/Makefile b/arch/xtensa/boot/Makefile index 40aa55b485be..8657c62fc78b 100644 --- a/arch/xtensa/boot/Makefile +++ b/arch/xtensa/boot/Makefile @@ -23,6 +23,7 @@ subdir-y := lib bootdir-$(CONFIG_XTENSA_PLATFORM_ISS) += boot-elf bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf +bootdir-$(CONFIG_XTENSA_PLATFORM_XTAVNET) += boot-redboot boot-elf zImage zImage.initrd Image Image.initrd: $(bootdir-y) diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/asm/coprocessor.h index 75c94a1658b0..42da613d1623 100644 --- a/arch/xtensa/include/asm/coprocessor.h +++ b/arch/xtensa/include/asm/coprocessor.h @@ -1,11 +1,11 @@ /* - * include/asm-xtensa/coprocessor.h + * arch/xtensa/include/asm/coprocessor.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003 - 2007 Tensilica Inc. + * Copyright (C) 2003-2010 Tensilica Inc. */ @@ -15,9 +15,10 @@ #include <linux/stringify.h> #include <variant/core.h> #include <variant/tie.h> +#include <variant/core.h> #include <asm/types.h> -#ifdef __ASSEMBLY__ +#if defined(__ASSEMBLY__) && !defined(LINKER_SCRIPT) # include <variant/tie-asm.h> .macro xchal_sa_start a b @@ -70,7 +71,7 @@ -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ && !LINKER_SCRIPT */ /* * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured. diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h index d04cd3a625fa..145db5cc6191 100644 --- a/arch/xtensa/include/asm/io.h +++ b/arch/xtensa/include/asm/io.h @@ -1,11 +1,11 @@ /* - * include/asm-xtensa/io.h + * arch/xtensa/include/asm/io.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 - 2005 Tensilica Inc. + * Copyright (C) 2001-2010 Tensilica Inc. */ #ifndef _XTENSA_IO_H @@ -63,40 +63,33 @@ static inline void * phys_to_virt(unsigned long address) #define bus_to_virt(x) phys_to_virt(x) /* - * Return the virtual (cached) address for the specified bus memory. + * Return the virtual (uncached) address for the specified bus memory + * (which is, for now, simply a physical address). * Note that we currently don't support any address outside the KIO segment. + * See also arch/mips/include/asm/io.h for nice comments. */ -static inline void *ioremap(unsigned long offset, unsigned long size) +static inline void __iomem *__ioremap(unsigned long offset, unsigned long size) { #ifdef CONFIG_MMU if (offset >= XCHAL_KIO_PADDR - && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE) - return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR); + && offset <= XCHAL_KIO_PADDR + XCHAL_KIO_SIZE - 1) + return (void __iomem *)(offset - XCHAL_KIO_PADDR + XCHAL_KIO_BYPASS_VADDR); else BUG(); #else - return (void *)offset; + return (void __iomem *)offset; #endif } -static inline void *ioremap_nocache(unsigned long offset, unsigned long size) -{ -#ifdef CONFIG_MMU - if (offset >= XCHAL_KIO_PADDR - && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE) - return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR); - else - BUG(); -#else - return (void *)offset; -#endif -} +#define ioremap(offset, size) __ioremap(offset, size) +#define ioremap_nocache(offset, size) __ioremap(offset, size) -static inline void iounmap(void *addr) +static inline void iounmap(void __iomem *addr) { } + /* * Generic I/O */ @@ -191,6 +184,13 @@ extern void outsl (unsigned long port, const void *src, unsigned long count); #endif +#ifndef CONFIG_GENERIC_IOMAP +/* Partial Simple MMIO */ +#define ioread32(a) __raw_readl(a) +#define iowrite32(v,a) __raw_writel((v),(a)) +#endif + + /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem access */ diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h index 4c0ccc9c4f4c..6af436f4429d 100644 --- a/arch/xtensa/include/asm/irq.h +++ b/arch/xtensa/include/asm/irq.h @@ -1,11 +1,11 @@ /* - * include/asm-xtensa/irq.h + * arch/xtensa/include/asm/irq.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 - 2005 Tensilica Inc. + * Copyright (C) 2001-2010 Tensilica Inc. */ #ifndef _XTENSA_IRQ_H @@ -22,6 +22,9 @@ static inline void variant_irq_enable(unsigned int irq) { } static inline void variant_irq_disable(unsigned int irq) { } #endif +/* This number is used when no interrupt has been assigned. */ +#define NO_IRQ (-1) + #ifndef VARIANT_NR_IRQS # define VARIANT_NR_IRQS 0 #endif diff --git a/arch/xtensa/include/asm/serial.h b/arch/xtensa/include/asm/serial.h index a8a2493260f6..c55a0e2b47ca 100644 --- a/arch/xtensa/include/asm/serial.h +++ b/arch/xtensa/include/asm/serial.h @@ -1,5 +1,5 @@ /* - * include/asm-xtensa/serial.h + * arch/xtensa/include/asm/serial.h * * Configuration details for 8250, 16450, 16550, etc. serial ports * @@ -7,12 +7,20 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 - 2005 Tensilica Inc. + * Copyright (C) 2001-2010 Tensilica Inc. */ #ifndef _XTENSA_SERIAL_H #define _XTENSA_SERIAL_H +#include <asm/irq.h> #include <platform/serial.h> +/* The 8250 driver treats IRQ 0 as absent. For the Xtensa architecture, + interrupt 0 is valid, must compare against NO_IRQ instead. */ +#ifdef is_real_interrupt +#undef is_real_interrupt +#define is_real_interrupt(irq) ((irq) != NO_IRQ) +#endif + #endif /* _XTENSA_SERIAL_H */ diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile index 2d2728b3e862..e426a4ec7f22 100644 --- a/arch/xtensa/kernel/Makefile +++ b/arch/xtensa/kernel/Makefile @@ -27,8 +27,8 @@ sed-y = -e 's/\*(\(\.[a-z]*it\|\.ref\|\)\.text)/*(\1.literal \1.text)/g' \ -e 's/\*(\(\.text\.[a-z]*\))/*(\1.literal \1)/g' quiet_cmd__cpp_lds_S = LDS $@ - cmd__cpp_lds_S = $(CPP) $(cpp_flags) -P -C -Uxtensa -D__ASSEMBLY__ $< \ - | sed $(sed-y) >$@ + cmd__cpp_lds_S = $(CPP) $(cpp_flags) -P -C -Uxtensa -D__ASSEMBLY__ \ + -DLINKER_SCRIPT $< | sed $(sed-y) >$@ $(obj)/vmlinux.lds: $(src)/vmlinux.lds.S FORCE $(call if_changed_dep,_cpp_lds_S) diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c index 19df764f6399..88ba96e2df25 100644 --- a/arch/xtensa/kernel/time.c +++ b/arch/xtensa/kernel/time.c @@ -31,7 +31,7 @@ unsigned long ccount_per_jiffy; /* per 1/HZ */ unsigned long nsec_per_ccount; /* nsec per ccount increment */ #endif -static cycle_t ccount_read(void) +static cycle_t ccount_read(struct clocksource *cs) { return (cycle_t)get_ccount(); } diff --git a/arch/xtensa/platforms/xtavnet/Makefile b/arch/xtensa/platforms/xtavnet/Makefile new file mode 100644 index 000000000000..06b120b40015 --- /dev/null +++ b/arch/xtensa/platforms/xtavnet/Makefile @@ -0,0 +1,10 @@ +# Makefile for the Tensilica Avnet-based Emulation Boards +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# +# Note 2! The CFLAGS definitions are in the main makefile... + +obj-y = setup.o lcd.o + diff --git a/arch/xtensa/platforms/xtavnet/include/platform/hardware.h b/arch/xtensa/platforms/xtavnet/include/platform/hardware.h new file mode 100644 index 000000000000..5301be745113 --- /dev/null +++ b/arch/xtensa/platforms/xtavnet/include/platform/hardware.h @@ -0,0 +1,85 @@ +/* + * arch/xtensa/platforms/xtavnet/include/platform/hardware.h + * + * This file contains the hardware configuration of Tensilica Avnet boards + * (XT-AV60, XT-AV110, XT-AV200, derived from Avnet LX60, LX110, LX200 + * boards respectively). + * + * Copyright (C) 2006-2010 Tensilica Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __XTAVNET_HARDWARE_H +#define __XTAVNET_HARDWARE_H + +#include <variant/core.h> + +/* Memory configuration. */ + +#define PLATFORM_DEFAULT_MEM_START 0x00000000 +#define PLATFORM_DEFAULT_MEM_SIZE 0x04000000 + +/* Interrupt configuration. */ + +#define PLATFORM_NR_IRQS 2 + +/* + * Default assignment of XTAVnet devices to external interrupts. + * + * CONFIG_ARCH_HAS_SMP means the hardware supports SMP, ie. is Xtensa MX. + * + * Systems with SMP support (MX) have an External Interrupt Distributor + * between external interrupts and the core's interrupts. The first three + * core interrupts are used for IPI (interprocessor interrupts), so + * external (board device) interrupts end up shifted up by 3. + */ + +/* UART interrupt: */ +#ifdef CONFIG_ARCH_HAS_SMP +#define UART_INTNUM XCHAL_EXTINT3_NUM +#else +#define UART_INTNUM XCHAL_EXTINT0_NUM +#endif + +/* Ethernet interrupt: */ +#ifdef CONFIG_ARCH_HAS_SMP +#define OETH_IRQ XCHAL_EXTINT4_NUM +#else +#define OETH_IRQ XCHAL_EXTINT1_NUM +#endif + +/* + * Device addresses and parameters. + */ + +/* UART */ +#define UART_PADDR 0xFD050020 + +/* LCD instruction and data virt. addresses. */ +#define LCD_INSTR_ADDR (char*)(0xFD040000) +#define LCD_DATA_ADDR (char*)(0xFD040004) + +/* Misc. */ +#define XTAVNET_FPGAREGS_VADDR 0xFD020000 +/* Clock frequency in Hz (read-only): */ +#define XTAVNET_CLKFRQ_VADDR (XTAVNET_FPGAREGS_VADDR + 0x04) +/* Setting of 8 DIP switches: */ +#define DIP_SWITCHES_VADDR (XTAVNET_FPGAREGS_VADDR + 0x0C) +/* Software reset (write 0xdead): */ +#define XTAVNET_SWRST_VADDR (XTAVNET_FPGAREGS_VADDR + 0x10) + +/* OpenCores Ethernet controller: */ +#define OETH_REGS_PADDR IOADDR(0xD030000) /* regs + RX/TX descriptors */ +#define OETH_REGS_VADDR 0xFD030000 +#define OETH_REGS_SIZE 0x1000 +#define OETH_SRAMBUFF_PADDR 0xFD800000 +#define OETH_SRAMBUFF_SIZE (5*0x600 + 5*0x600) /* 5*rx buffs + 5*tx buffs */ +/*#define OETH_SRAMBUFF_SIZE 0x3C00*/ /* probably 0x4000 ? */ +/* The MAC address for these boards is 00:50:c2:13:6f:xx. + The last byte (here as zero) is read from the DIP switches on the board. */ +#define OETH_MACADDR 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 + +#endif /* __XTAVNET_HARDWARE_H */ diff --git a/arch/xtensa/platforms/xtavnet/include/platform/lcd.h b/arch/xtensa/platforms/xtavnet/include/platform/lcd.h new file mode 100644 index 000000000000..67de96acb2f9 --- /dev/null +++ b/arch/xtensa/platforms/xtavnet/include/platform/lcd.h @@ -0,0 +1,22 @@ +/* + * arch/xtensa/platforms/xtavnet/include/platform/lcd.h + * + * Copyright (C) 2001-2006 Tensilica Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __XTAVNET_LCD_H +#define __XTAVNET_LCD_H + +/* Display string STR at position POS on the LCD. */ +void lcd_disp_at_pos(char *str, unsigned char pos); + +/* Shift the contents of the LCD display left or right. */ +void lcd_shiftleft(void); +void lcd_shiftright(void); + +#endif + diff --git a/arch/xtensa/platforms/xtavnet/include/platform/serial.h b/arch/xtensa/platforms/xtavnet/include/platform/serial.h new file mode 100644 index 000000000000..a0cb0caff152 --- /dev/null +++ b/arch/xtensa/platforms/xtavnet/include/platform/serial.h @@ -0,0 +1 @@ +#include <asm-generic/serial.h> diff --git a/arch/xtensa/platforms/xtavnet/lcd.c b/arch/xtensa/platforms/xtavnet/lcd.c new file mode 100644 index 000000000000..283986f158ad --- /dev/null +++ b/arch/xtensa/platforms/xtavnet/lcd.c @@ -0,0 +1,79 @@ +/* + * Driver for the LCD display on the Tensilica LX60 Board. + * This code has no effect on the LX200 board. (LX110: TBD) + * + * Copyright (C) 2001-2006 Tensilica Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +/* + * + * FIXME: this code is from the examples from the LX60 user guide. + * + * The lcd_pause function does busy waiting, which is probably not + * great. Maybe the code could be changed to use kernel timers, or + * change the hardware to not need to wait. + */ + +#include <linux/init.h> + +#include <platform/hardware.h> +#include <asm/processor.h> +#include <platform/lcd.h> +#include <linux/delay.h> + +#define LCD_PAUSE_ITERATIONS 4000 +#define LCD_CLEAR 0x1 +#define LCD_DISPLAY_ON 0xc + +/* 8bit and 2 lines display */ +#define LCD_DISPLAY_MODE8BIT 0x38 +#define LCD_DISPLAY_POS 0x80 +#define LCD_SHIFT_LEFT 0x18 +#define LCD_SHIFT_RIGHT 0x1c + +static int __init lcd_init(void) +{ + *LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT; + mdelay(5); + *LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT; + udelay(200); + *LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT; + udelay(50); + *LCD_INSTR_ADDR = LCD_DISPLAY_ON; + udelay(50); + *LCD_INSTR_ADDR = LCD_CLEAR; + mdelay(10); + lcd_disp_at_pos("XTENSA LINUX", 0); + + return 0; +} + +void lcd_disp_at_pos (char *str, unsigned char pos) +{ + *LCD_INSTR_ADDR = LCD_DISPLAY_POS | pos; + udelay(100); + while (*str != 0){ + *LCD_DATA_ADDR = *str; + udelay(200); + str++; + } +} + +void lcd_shiftleft(void) +{ + *LCD_INSTR_ADDR = LCD_SHIFT_LEFT; + udelay(50); +} + +void lcd_shiftright(void) +{ + *LCD_INSTR_ADDR = LCD_SHIFT_RIGHT; + udelay(50); +} + +arch_initcall(lcd_init); + diff --git a/arch/xtensa/platforms/xtavnet/setup.c b/arch/xtensa/platforms/xtavnet/setup.c new file mode 100644 index 000000000000..256fcb2b2af4 --- /dev/null +++ b/arch/xtensa/platforms/xtavnet/setup.c @@ -0,0 +1,269 @@ +/* + * arch/xtensa/platform-xtavnet/setup.c + * + * Setup/initialization for Tensilica Avnet boards (XT-AV60, XT-AV110, XT-AV200, + * derived from Avnet LX60, LX110, LX200 boards respectively). + * For details, see "Tensilica Avnet LX### (XT-AV###) Board User's Guide" + * (where ### is 60, 110, or 200). + * + * Authors: Chris Zankel <chris@zankel.net> + * Joe Taylor <joe@tensilica.com> + * Pete Delaney <piet@tensilica.com> + * Marc Gauthier <marc@tensilica.com> <marc@alumni.uwaterloo.ca> + * + * Copyright 2001-2010 Tensilica Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License, version 2. See the file "COPYING" in the main directory of this + * archive for more details. + */ + +#include <linux/stddef.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/reboot.h> +#include <linux/kdev_t.h> +#include <linux/types.h> +#include <linux/major.h> +#include <linux/console.h> +#include <linux/delay.h> +#include <linux/stringify.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <asm/timex.h> + +#include <linux/etherdevice.h> +#include <net/ethoc.h> + +#include <asm/processor.h> +#include <asm/platform.h> +#include <asm/bootparam.h> +#include <platform/lcd.h> +#include <platform/hardware.h> +#include <variant/core.h> + +/* For doing extra init. beyond what the ethoc driver does. */ +struct oeth_regs { + unsigned moder; /* Mode Register */ + unsigned int_src; /* Interrupt Source Register */ + unsigned int_mask; /* Interrupt Mask Register */ + unsigned ipgt; /* Back to Bak Inter Packet Gap Register */ + unsigned ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */ + unsigned ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */ + unsigned packet_len; /* Packet Length Register (min. and max.) */ + unsigned collconf; /* Collision and Retry Configuration Register */ + unsigned tx_bd_num; /* Transmit Buffer Descriptor Number Register */ + unsigned ctrlmoder; /* Control Module Mode Register */ + unsigned miimoder; /* MII Mode Register */ + unsigned miicommand; /* MII Command Register */ + unsigned miiaddress; /* MII Address Register */ + unsigned miitx_data; /* MII Transmit Data Register */ + unsigned miirx_data; /* MII Receive Data Register */ + unsigned miistatus; /* MII Status Register */ + unsigned mac_addr0; /* MAC Individual Address Register 0 */ + unsigned mac_addr1; /* MAC Individual Address Register 1 */ + unsigned hash_addr0; /* Hash Register 0 */ + unsigned hash_addr1; /* Hash Register 1 */ +}; +/* MODER Register */ +#define OETH_MODER_RST 0x00000800 /* Reset MAC */ +/* MII Mode Register */ +#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */ + + + +void platform_halt(void) +{ + /* Just display HALT on LCD display, and loop. */ + lcd_disp_at_pos(" HALT ", 0); + local_irq_disable(); + while (1); +} + +void platform_power_off(void) +{ + /* No software-controlled power-off, just display POWEROFF and loop. */ + lcd_disp_at_pos ("POWEROFF", 0); + local_irq_disable(); + while (1); +} + +void platform_restart(void) +{ + /* Software-initiated board reset. */ + *(volatile unsigned *)XTAVNET_SWRST_VADDR = 0xdead; +} + +void platform_heartbeat(void) +{ + /* Executes every timer tick. */ +} + + +/* + * Called from time_init(). "Calibrating" is a misnomer, here we just read + * the clock rate from the board specific FPGA registers. + */ +void platform_calibrate_ccount(void) +{ + long clk_freq = *(long *)XTAVNET_CLKFRQ_VADDR; + + ccount_per_jiffy = clk_freq / HZ; + nsec_per_ccount = 1000000000UL / clk_freq; +} + + +/*---------------------------------------------------------------------------- + * Ethernet -- OpenCores Ethernet MAC (ethoc driver) + */ + +static struct resource ethoc_res[] = { + [0] = { /* register space */ + .start = OETH_REGS_PADDR, + .end = OETH_REGS_PADDR + OETH_REGS_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { /* buffer space */ + .start = OETH_SRAMBUFF_PADDR, + .end = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { /* IRQ number */ + .start = OETH_IRQ, + .end = OETH_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct ethoc_platform_data ethoc_pdata = { + .hwaddr = { OETH_MACADDR }, /* last byte written in setup below */ + .phy_id = -1, +}; + +static struct platform_device ethoc_device = { + .name = "ethoc", + .id = -1, + .num_resources = ARRAY_SIZE(ethoc_res), + .resource = ethoc_res, + .dev = { + .platform_data = ðoc_pdata, + }, +}; + + +/*---------------------------------------------------------------------------- + * UART + */ + +static struct resource serial_resource = { + .start = UART_PADDR, + .end = UART_PADDR + 0x1f, + .flags = IORESOURCE_MEM, +}; + +static struct plat_serial8250_port serial_platform_data[] = { + [0] = { + .mapbase = UART_PADDR, + .irq = UART_INTNUM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, + .iotype = UPIO_MEM32, + .regshift = 2, + .uartclk = 0, /* set in xtavnet_init() */ + }, + { }, +}; + +static struct platform_device xtavnet_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, + .num_resources = 1, + .resource = &serial_resource, +}; + + +/*---------------------------------------------------------------------------- + */ + +/* platform devices */ +static struct platform_device *platform_devices[] = { + ðoc_device, + &xtavnet_uart, +}; + + + +/* very early init */ +void __init platform_setup(char **cmdline) +{ + if (cmdline) { + if (cmdline[0]) + printk("XTAVnet: platform_setup(cmdline[0]:'%s')\n", cmdline[0]); + else + printk("XTAVnet: platform_setup(cmdline[0]:<null>)\n"); + } +} + +/* early initialization, before secondary cpu's have been brought up */ + +void platform_init(bp_tag_t *bootparams) +{ + printk("\n"); + if( bootparams ) + printk("XTAVnet: platform_init(bootparams:0x%x)\n", (unsigned)bootparams); +} + +static int xtavnet_init(void) +{ + volatile struct oeth_regs *regs = (volatile struct oeth_regs*)OETH_REGS_VADDR; + + /* + * Do some of the initialization missing in the ETHOC driver. + * (Perhaps not all necessary, but was in a previously used driver.) + */ + + /* Reset the controller. */ + regs->moder = OETH_MODER_RST; /* Reset ON */ + regs->moder &= ~OETH_MODER_RST; /* Reset OFF */ + + regs->packet_len = (64 << 16) | 1536; + regs->ipgr1 = 0x0000000c; + regs->ipgr2 = 0x00000012; + regs->collconf = 0x000f003f; + regs->ctrlmoder = 0; + regs->miimoder = (OETH_MIIMODER_CLKDIV & 0x2); + + /* + * Setup dynamic info in platform device init structures. + */ + + /* Ethernet MAC address. */ + ethoc_pdata.hwaddr[5] = *(u32*)DIP_SWITCHES_VADDR; + + /* Clock rate varies among FPGA bitstreams; board specific FPGA register + * reports the actual clock rate. */ + serial_platform_data[0].uartclk = *(long *)XTAVNET_CLKFRQ_VADDR; + + + /* register platform devices */ + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + + /* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user + knows whether they set it correctly on the DIP switches. */ + printk("XTAVnet: Ethernet MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + ethoc_pdata.hwaddr[0], ethoc_pdata.hwaddr[1], ethoc_pdata.hwaddr[2], + ethoc_pdata.hwaddr[3], ethoc_pdata.hwaddr[4], ethoc_pdata.hwaddr[5]); + + return 0; +} + + +/* + * Register to be done during do_initcalls(). + */ +arch_initcall(xtavnet_init); + + diff --git a/crypto/Kconfig b/crypto/Kconfig index 1cd497d7a15a..e573077f1672 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -101,13 +101,13 @@ config CRYPTO_MANAGER2 select CRYPTO_BLKCIPHER2 select CRYPTO_PCOMP2 -config CRYPTO_MANAGER_TESTS - bool "Run algolithms' self-tests" +config CRYPTO_MANAGER_DISABLE_TESTS + bool "Disable run-time self tests" default y depends on CRYPTO_MANAGER2 help - Run cryptomanager's tests for the new crypto algorithms being - registered. + Disable run-time self tests that normally take place at + algorithm registration. config CRYPTO_GF128MUL tristate "GF(2^128) multiplication functions (EXPERIMENTAL)" diff --git a/crypto/ahash.c b/crypto/ahash.c index b8c59b889c6e..f669822a7a44 100644 --- a/crypto/ahash.c +++ b/crypto/ahash.c @@ -47,8 +47,11 @@ static int hash_walk_next(struct crypto_hash_walk *walk) walk->data = crypto_kmap(walk->pg, 0); walk->data += offset; - if (offset & alignmask) - nbytes = alignmask + 1 - (offset & alignmask); + if (offset & alignmask) { + unsigned int unaligned = alignmask + 1 - (offset & alignmask); + if (nbytes > unaligned) + nbytes = unaligned; + } walk->entrylen -= nbytes; return nbytes; diff --git a/crypto/algboss.c b/crypto/algboss.c index 40bd391f34d9..791d194958fa 100644 --- a/crypto/algboss.c +++ b/crypto/algboss.c @@ -206,13 +206,16 @@ err: return NOTIFY_OK; } -#ifdef CONFIG_CRYPTO_MANAGER_TESTS static int cryptomgr_test(void *data) { struct crypto_test_param *param = data; u32 type = param->type; int err = 0; +#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS + goto skiptest; +#endif + if (type & CRYPTO_ALG_TESTED) goto skiptest; @@ -267,7 +270,6 @@ err_put_module: err: return NOTIFY_OK; } -#endif /* CONFIG_CRYPTO_MANAGER_TESTS */ static int cryptomgr_notify(struct notifier_block *this, unsigned long msg, void *data) @@ -275,10 +277,8 @@ static int cryptomgr_notify(struct notifier_block *this, unsigned long msg, switch (msg) { case CRYPTO_MSG_ALG_REQUEST: return cryptomgr_schedule_probe(data); -#ifdef CONFIG_CRYPTO_MANAGER_TESTS case CRYPTO_MSG_ALG_REGISTER: return cryptomgr_schedule_test(data); -#endif } return NOTIFY_DONE; diff --git a/crypto/testmgr.c b/crypto/testmgr.c index abd980c729eb..fa8c8f78c8d4 100644 --- a/crypto/testmgr.c +++ b/crypto/testmgr.c @@ -23,7 +23,7 @@ #include "internal.h" -#ifndef CONFIG_CRYPTO_MANAGER_TESTS +#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS /* a perfect nop */ int alg_test(const char *driver, const char *alg, u32 type, u32 mask) @@ -2542,6 +2542,6 @@ non_fips_alg: return -EINVAL; } -#endif /* CONFIG_CRYPTO_MANAGER_TESTS */ +#endif /* CONFIG_CRYPTO_MANAGER_DISABLE_TESTS */ EXPORT_SYMBOL_GPL(alg_test); diff --git a/drivers/Makefile b/drivers/Makefile index ae473445ad6d..0861aa554dfd 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_EISA) += eisa/ obj-y += lguest/ obj-$(CONFIG_CPU_FREQ) += cpufreq/ obj-$(CONFIG_CPU_IDLE) += cpuidle/ +obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_MMC) += mmc/ obj-$(CONFIG_MEMSTICK) += memstick/ obj-$(CONFIG_NEW_LEDS) += leds/ @@ -104,7 +105,6 @@ obj-$(CONFIG_ARCH_SHMOBILE) += sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET obj-y += clocksource/ endif -obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 1f67057af2a5..3ba8d1f44a73 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -33,7 +33,6 @@ #include <linux/pm_runtime.h> #include <linux/pci.h> #include <linux/pci-acpi.h> -#include <linux/pci-aspm.h> #include <linux/acpi.h> #include <linux/slab.h> #include <acpi/acpi_bus.h> @@ -226,22 +225,31 @@ static acpi_status acpi_pci_run_osc(acpi_handle handle, return status; } -static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 flags) +static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, + u32 support, + u32 *control) { acpi_status status; - u32 support_set, result, capbuf[3]; + u32 result, capbuf[3]; + + support &= OSC_PCI_SUPPORT_MASKS; + support |= root->osc_support_set; - /* do _OSC query for all possible controls */ - support_set = root->osc_support_set | (flags & OSC_PCI_SUPPORT_MASKS); capbuf[OSC_QUERY_TYPE] = OSC_QUERY_ENABLE; - capbuf[OSC_SUPPORT_TYPE] = support_set; - capbuf[OSC_CONTROL_TYPE] = OSC_PCI_CONTROL_MASKS; + capbuf[OSC_SUPPORT_TYPE] = support; + if (control) { + *control &= OSC_PCI_CONTROL_MASKS; + capbuf[OSC_CONTROL_TYPE] = *control | root->osc_control_set; + } else { + /* Run _OSC query for all possible controls. */ + capbuf[OSC_CONTROL_TYPE] = OSC_PCI_CONTROL_MASKS; + } status = acpi_pci_run_osc(root->device->handle, capbuf, &result); if (ACPI_SUCCESS(status)) { - root->osc_support_set = support_set; - root->osc_control_qry = result; - root->osc_queried = 1; + root->osc_support_set = support; + if (control) + *control = result; } return status; } @@ -255,7 +263,7 @@ static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags) if (ACPI_FAILURE(status)) return status; mutex_lock(&osc_lock); - status = acpi_pci_query_osc(root, flags); + status = acpi_pci_query_osc(root, flags, NULL); mutex_unlock(&osc_lock); return status; } @@ -365,55 +373,70 @@ out: EXPORT_SYMBOL_GPL(acpi_get_pci_dev); /** - * acpi_pci_osc_control_set - commit requested control to Firmware - * @handle: acpi_handle for the target ACPI object - * @flags: driver's requested control bits + * acpi_pci_osc_control_set - Request control of PCI root _OSC features. + * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex). + * @mask: Mask of _OSC bits to request control of, place to store control mask. + * @req: Mask of _OSC bits the control of is essential to the caller. + * + * Run _OSC query for @mask and if that is successful, compare the returned + * mask of control bits with @req. If all of the @req bits are set in the + * returned mask, run _OSC request for it. * - * Attempt to take control from Firmware on requested control bits. + * The variable at the @mask address may be modified regardless of whether or + * not the function returns success. On success it will contain the mask of + * _OSC bits the BIOS has granted control of, but its contents are meaningless + * on failure. **/ -acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 flags) +acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req) { + struct acpi_pci_root *root; acpi_status status; - u32 control_req, result, capbuf[3]; + u32 ctrl, capbuf[3]; acpi_handle tmp; - struct acpi_pci_root *root; - status = acpi_get_handle(handle, "_OSC", &tmp); - if (ACPI_FAILURE(status)) - return status; + if (!mask) + return AE_BAD_PARAMETER; - control_req = (flags & OSC_PCI_CONTROL_MASKS); - if (!control_req) + ctrl = *mask & OSC_PCI_CONTROL_MASKS; + if ((ctrl & req) != req) return AE_TYPE; root = acpi_pci_find_root(handle); if (!root) return AE_NOT_EXIST; + status = acpi_get_handle(handle, "_OSC", &tmp); + if (ACPI_FAILURE(status)) + return status; + mutex_lock(&osc_lock); + + *mask = ctrl | root->osc_control_set; /* No need to evaluate _OSC if the control was already granted. */ - if ((root->osc_control_set & control_req) == control_req) + if ((root->osc_control_set & ctrl) == ctrl) goto out; - /* Need to query controls first before requesting them */ - if (!root->osc_queried) { - status = acpi_pci_query_osc(root, root->osc_support_set); + /* Need to check the available controls bits before requesting them. */ + while (*mask) { + status = acpi_pci_query_osc(root, root->osc_support_set, mask); if (ACPI_FAILURE(status)) goto out; + if (ctrl == *mask) + break; + ctrl = *mask; } - if ((root->osc_control_qry & control_req) != control_req) { - printk(KERN_DEBUG - "Firmware did not grant requested _OSC control\n"); + + if ((ctrl & req) != req) { status = AE_SUPPORT; goto out; } capbuf[OSC_QUERY_TYPE] = 0; capbuf[OSC_SUPPORT_TYPE] = root->osc_support_set; - capbuf[OSC_CONTROL_TYPE] = root->osc_control_set | control_req; - status = acpi_pci_run_osc(handle, capbuf, &result); + capbuf[OSC_CONTROL_TYPE] = ctrl; + status = acpi_pci_run_osc(handle, capbuf, mask); if (ACPI_SUCCESS(status)) - root->osc_control_set = result; + root->osc_control_set = *mask; out: mutex_unlock(&osc_lock); return status; @@ -544,14 +567,6 @@ static int __devinit acpi_pci_root_add(struct acpi_device *device) if (flags != base_flags) acpi_pci_osc_support(root, flags); - status = acpi_pci_osc_control_set(root->device->handle, - OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); - - if (ACPI_FAILURE(status)) { - printk(KERN_INFO "Unable to assume PCIe control: Disabling ASPM\n"); - pcie_no_aspm(); - } - pci_acpi_add_bus_pm_notifier(device, root->bus); if (device->wakeup.flags.run_wake) device_set_run_wake(root->bus->bridge, true); diff --git a/drivers/char/hw_random/n2-drv.c b/drivers/char/hw_random/n2-drv.c index 1acdb2509511..a3f5e381e746 100644 --- a/drivers/char/hw_random/n2-drv.c +++ b/drivers/char/hw_random/n2-drv.c @@ -387,7 +387,7 @@ static int n2rng_init_control(struct n2rng *np) static int n2rng_data_read(struct hwrng *rng, u32 *data) { - struct n2rng *np = rng->priv; + struct n2rng *np = (struct n2rng *) rng->priv; unsigned long ra = __pa(&np->test_data); int len; diff --git a/drivers/char/vt_ioctl.c b/drivers/char/vt_ioctl.c index 2bbeaaea46e9..38df8c19e74c 100644 --- a/drivers/char/vt_ioctl.c +++ b/drivers/char/vt_ioctl.c @@ -533,11 +533,14 @@ int vt_ioctl(struct tty_struct *tty, struct file * file, case KIOCSOUND: if (!perm) goto eperm; - /* FIXME: This is an old broken API but we need to keep it - supported and somehow separate the historic advertised - tick rate from any real one */ + /* + * The use of PIT_TICK_RATE is historic, it used to be + * the platform-dependent CLOCK_TICK_RATE between 2.6.12 + * and 2.6.36, which was a minor but unfortunate ABI + * change. + */ if (arg) - arg = CLOCK_TICK_RATE / arg; + arg = PIT_TICK_RATE / arg; kd_mksound(arg, 0); break; @@ -553,11 +556,8 @@ int vt_ioctl(struct tty_struct *tty, struct file * file, */ ticks = HZ * ((arg >> 16) & 0xffff) / 1000; count = ticks ? (arg & 0xffff) : 0; - /* FIXME: This is an old broken API but we need to keep it - supported and somehow separate the historic advertised - tick rate from any real one */ if (count) - count = CLOCK_TICK_RATE / count; + count = PIT_TICK_RATE / count; kd_mksound(count, ticks); break; } diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 717305d30444..a44611652282 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -308,7 +308,7 @@ static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) * isr before we end up here. */ if (p->flags & FLAG_CLOCKSOURCE) - p->total_cycles += p->match_value; + p->total_cycles += p->match_value + 1; if (!(p->flags & FLAG_REPROGRAM)) p->next_match_value = p->max_match_value; @@ -403,7 +403,7 @@ static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) raw = sh_cmt_get_counter(p, &has_wrapped); if (unlikely(has_wrapped)) - raw += p->match_value; + raw += p->match_value + 1; spin_unlock_irqrestore(&p->lock, flags); return value + raw; @@ -445,7 +445,7 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p, /* clk_get_rate() needs an enabled clock */ clk_enable(p->clk); - p->rate = clk_get_rate(p->clk) / (p->width == 16) ? 512 : 8; + p->rate = clk_get_rate(p->clk) / ((p->width == 16) ? 512 : 8); clk_disable(p->clk); /* TODO: calculate good shift from rate and counter bit width */ @@ -478,7 +478,7 @@ static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic) ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); if (periodic) - sh_cmt_set_next(p, (p->rate + HZ/2) / HZ); + sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1); else sh_cmt_set_next(p, p->max_match_value); } @@ -523,9 +523,9 @@ static int sh_cmt_clock_event_next(unsigned long delta, BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); if (likely(p->flags & FLAG_IRQCONTEXT)) - p->next_match_value = delta; + p->next_match_value = delta - 1; else - sh_cmt_set_next(p, delta); + sh_cmt_set_next(p, delta - 1); return 0; } diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c index 598c49acaeb5..2707f5e17158 100644 --- a/drivers/i2c/busses/i2c-sh_mobile.c +++ b/drivers/i2c/busses/i2c-sh_mobile.c @@ -538,15 +538,17 @@ static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook) { struct resource *res; int ret = -ENXIO; - int q, m; - int k = 0; - int n = 0; + int n, k = 0; while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { for (n = res->start; hook && n <= res->end; n++) { if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED, - dev_name(&dev->dev), dev)) + dev_name(&dev->dev), dev)) { + for (n--; n >= res->start; n--) + free_irq(n, dev); + goto rollback; + } } k++; } @@ -554,16 +556,17 @@ static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook) if (hook) return k > 0 ? 0 : -ENOENT; - k--; ret = 0; rollback: - for (q = k; k >= 0; k--) { - for (m = n; m >= res->start; m--) - free_irq(m, dev); + k--; + + while (k >= 0) { + res = platform_get_resource(dev, IORESOURCE_IRQ, k); + for (n = res->start; n <= res->end; n++) + free_irq(n, dev); - res = platform_get_resource(dev, IORESOURCE_IRQ, k - 1); - m = res->end; + k--; } return ret; diff --git a/drivers/input/input.c b/drivers/input/input.c index a9b025f4147a..ab6982056518 100644 --- a/drivers/input/input.c +++ b/drivers/input/input.c @@ -1599,11 +1599,14 @@ EXPORT_SYMBOL(input_free_device); * @dev: input device supporting MT events and finger tracking * @num_slots: number of slots used by the device * - * This function allocates all necessary memory for MT slot handling - * in the input device, and adds ABS_MT_SLOT to the device capabilities. + * This function allocates all necessary memory for MT slot handling in the + * input device, and adds ABS_MT_SLOT to the device capabilities. All slots + * are initially marked as unused iby setting ABS_MT_TRACKING_ID to -1. */ int input_mt_create_slots(struct input_dev *dev, unsigned int num_slots) { + int i; + if (!num_slots) return 0; @@ -1614,6 +1617,10 @@ int input_mt_create_slots(struct input_dev *dev, unsigned int num_slots) dev->mtsize = num_slots; input_set_abs_params(dev, ABS_MT_SLOT, 0, num_slots - 1, 0, 0); + /* Mark slots as 'unused' */ + for (i = 0; i < num_slots; i++) + dev->mt[i].abs[ABS_MT_TRACKING_ID - ABS_MT_FIRST] = -1; + return 0; } EXPORT_SYMBOL(input_mt_create_slots); diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c index 40d77ba8fdc1..6e29badb969e 100644 --- a/drivers/input/tablet/wacom_wac.c +++ b/drivers/input/tablet/wacom_wac.c @@ -243,10 +243,10 @@ static int wacom_graphire_irq(struct wacom_wac *wacom) if (features->type == WACOM_G4 || features->type == WACOM_MO) { input_report_abs(input, ABS_DISTANCE, data[6] & 0x3f); - rw = (signed)(data[7] & 0x04) - (data[7] & 0x03); + rw = (data[7] & 0x04) - (data[7] & 0x03); } else { input_report_abs(input, ABS_DISTANCE, data[7] & 0x3f); - rw = -(signed)data[6]; + rw = -(signed char)data[6]; } input_report_rel(input, REL_WHEEL, rw); } diff --git a/drivers/md/.gitignore b/drivers/md/.gitignore deleted file mode 100644 index a7afec6b19c6..000000000000 --- a/drivers/md/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -mktables -raid6altivec*.c -raid6int*.c -raid6tables.c diff --git a/drivers/md/bitmap.c b/drivers/md/bitmap.c index 1ba1e122e948..ed4900ade93a 100644 --- a/drivers/md/bitmap.c +++ b/drivers/md/bitmap.c @@ -1542,8 +1542,7 @@ void bitmap_cond_end_sync(struct bitmap *bitmap, sector_t sector) atomic_read(&bitmap->mddev->recovery_active) == 0); bitmap->mddev->curr_resync_completed = bitmap->mddev->curr_resync; - if (bitmap->mddev->persistent) - set_bit(MD_CHANGE_CLEAN, &bitmap->mddev->flags); + set_bit(MD_CHANGE_CLEAN, &bitmap->mddev->flags); sector &= ~((1ULL << CHUNK_BLOCK_SHIFT(bitmap)) - 1); s = 0; while (s < sector && s < bitmap->mddev->resync_max_sectors) { diff --git a/drivers/md/md.c b/drivers/md/md.c index c148b6302154..43cf9cc9c1df 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -2167,9 +2167,9 @@ repeat: rdev->recovery_offset = mddev->curr_resync_completed; } - if (mddev->external || !mddev->persistent) { - clear_bit(MD_CHANGE_DEVS, &mddev->flags); + if (!mddev->persistent) { clear_bit(MD_CHANGE_CLEAN, &mddev->flags); + clear_bit(MD_CHANGE_DEVS, &mddev->flags); wake_up(&mddev->sb_wait); return; } @@ -2178,7 +2178,6 @@ repeat: mddev->utime = get_seconds(); - set_bit(MD_CHANGE_PENDING, &mddev->flags); if (test_and_clear_bit(MD_CHANGE_DEVS, &mddev->flags)) force_change = 1; if (test_and_clear_bit(MD_CHANGE_CLEAN, &mddev->flags)) @@ -3371,7 +3370,7 @@ array_state_show(mddev_t *mddev, char *page) case 0: if (mddev->in_sync) st = clean; - else if (test_bit(MD_CHANGE_CLEAN, &mddev->flags)) + else if (test_bit(MD_CHANGE_PENDING, &mddev->flags)) st = write_pending; else if (mddev->safemode) st = active_idle; @@ -3452,9 +3451,7 @@ array_state_store(mddev_t *mddev, const char *buf, size_t len) mddev->in_sync = 1; if (mddev->safemode == 1) mddev->safemode = 0; - if (mddev->persistent) - set_bit(MD_CHANGE_CLEAN, - &mddev->flags); + set_bit(MD_CHANGE_CLEAN, &mddev->flags); } err = 0; } else @@ -3466,8 +3463,7 @@ array_state_store(mddev_t *mddev, const char *buf, size_t len) case active: if (mddev->pers) { restart_array(mddev); - if (mddev->external) - clear_bit(MD_CHANGE_CLEAN, &mddev->flags); + clear_bit(MD_CHANGE_PENDING, &mddev->flags); wake_up(&mddev->sb_wait); err = 0; } else { @@ -6572,6 +6568,7 @@ void md_write_start(mddev_t *mddev, struct bio *bi) if (mddev->in_sync) { mddev->in_sync = 0; set_bit(MD_CHANGE_CLEAN, &mddev->flags); + set_bit(MD_CHANGE_PENDING, &mddev->flags); md_wakeup_thread(mddev->thread); did_change = 1; } @@ -6580,7 +6577,6 @@ void md_write_start(mddev_t *mddev, struct bio *bi) if (did_change) sysfs_notify_dirent_safe(mddev->sysfs_state); wait_event(mddev->sb_wait, - !test_bit(MD_CHANGE_CLEAN, &mddev->flags) && !test_bit(MD_CHANGE_PENDING, &mddev->flags)); } @@ -6616,6 +6612,7 @@ int md_allow_write(mddev_t *mddev) if (mddev->in_sync) { mddev->in_sync = 0; set_bit(MD_CHANGE_CLEAN, &mddev->flags); + set_bit(MD_CHANGE_PENDING, &mddev->flags); if (mddev->safemode_delay && mddev->safemode == 0) mddev->safemode = 1; @@ -6625,7 +6622,7 @@ int md_allow_write(mddev_t *mddev) } else spin_unlock_irq(&mddev->write_lock); - if (test_bit(MD_CHANGE_CLEAN, &mddev->flags)) + if (test_bit(MD_CHANGE_PENDING, &mddev->flags)) return -EAGAIN; else return 0; @@ -6823,8 +6820,7 @@ void md_do_sync(mddev_t *mddev) atomic_read(&mddev->recovery_active) == 0); mddev->curr_resync_completed = mddev->curr_resync; - if (mddev->persistent) - set_bit(MD_CHANGE_CLEAN, &mddev->flags); + set_bit(MD_CHANGE_CLEAN, &mddev->flags); sysfs_notify(&mddev->kobj, NULL, "sync_completed"); } @@ -7103,8 +7099,7 @@ void md_check_recovery(mddev_t *mddev) mddev->recovery_cp == MaxSector) { mddev->in_sync = 1; did_change = 1; - if (mddev->persistent) - set_bit(MD_CHANGE_CLEAN, &mddev->flags); + set_bit(MD_CHANGE_CLEAN, &mddev->flags); } if (mddev->safemode == 1) mddev->safemode = 0; diff --git a/drivers/md/md.h b/drivers/md/md.h index a953fe2808ae..3931299788dc 100644 --- a/drivers/md/md.h +++ b/drivers/md/md.h @@ -140,7 +140,7 @@ struct mddev_s unsigned long flags; #define MD_CHANGE_DEVS 0 /* Some device status has changed */ #define MD_CHANGE_CLEAN 1 /* transition to or from 'clean' */ -#define MD_CHANGE_PENDING 2 /* superblock update in progress */ +#define MD_CHANGE_PENDING 2 /* switch from 'clean' to 'active' in progress */ int suspended; atomic_t active_io; diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 840b301b5671..1932e9cc8f52 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -41,23 +41,35 @@ static unsigned int fmax = 515633; * @clkreg: default value for MCICLOCK register * @clkreg_enable: enable value for MMCICLOCK register * @datalength_bits: number of bits in the MMCIDATALENGTH register + * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY + * is asserted (likewise for RX) + * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY + * is asserted (likewise for RX) */ struct variant_data { unsigned int clkreg; unsigned int clkreg_enable; unsigned int datalength_bits; + unsigned int fifosize; + unsigned int fifohalfsize; }; static struct variant_data variant_arm = { + .fifosize = 16 * 4, + .fifohalfsize = 8 * 4, .datalength_bits = 16, }; static struct variant_data variant_u300 = { + .fifosize = 16 * 4, + .fifohalfsize = 8 * 4, .clkreg_enable = 1 << 13, /* HWFCEN */ .datalength_bits = 16, }; static struct variant_data variant_ux500 = { + .fifosize = 30 * 4, + .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = 1 << 14, /* HWFCEN */ .datalength_bits = 24, @@ -138,6 +150,7 @@ static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) { + struct variant_data *variant = host->variant; unsigned int datactrl, timeout, irqmask; unsigned long long clks; void __iomem *base; @@ -173,7 +186,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) * If we have less than a FIFOSIZE of bytes to transfer, * trigger a PIO interrupt as soon as any data is available. */ - if (host->size < MCI_FIFOSIZE) + if (host->size < variant->fifosize) irqmask |= MCI_RXDATAAVLBLMASK; } else { /* @@ -332,13 +345,15 @@ static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int rema static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) { + struct variant_data *variant = host->variant; void __iomem *base = host->base; char *ptr = buffer; do { unsigned int count, maxcnt; - maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; + maxcnt = status & MCI_TXFIFOEMPTY ? + variant->fifosize : variant->fifohalfsize; count = min(remain, maxcnt); writesl(base + MMCIFIFO, ptr, count >> 2); @@ -362,6 +377,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id) { struct mmci_host *host = dev_id; struct sg_mapping_iter *sg_miter = &host->sg_miter; + struct variant_data *variant = host->variant; void __iomem *base = host->base; unsigned long flags; u32 status; @@ -420,7 +436,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id) * If we're nearing the end of the read, switch to * "any data available" mode. */ - if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) + if (status & MCI_RXACTIVE && host->size < variant->fifosize) writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); /* @@ -570,12 +586,13 @@ static int mmci_get_ro(struct mmc_host *mmc) static int mmci_get_cd(struct mmc_host *mmc) { struct mmci_host *host = mmc_priv(mmc); + struct mmci_platform_data *plat = host->plat; unsigned int status; if (host->gpio_cd == -ENOSYS) - status = host->plat->status(mmc_dev(host->mmc)); + status = plat->status(mmc_dev(host->mmc)); else - status = !gpio_get_value(host->gpio_cd); + status = !!gpio_get_value(host->gpio_cd) ^ plat->cd_invert; /* * Use positive logic throughout - status is zero for no card, diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 68970cfb81e1..4e18f5403f48 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -133,13 +133,6 @@ MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK) -/* - * The size of the FIFO in bytes. - */ -#define MCI_FIFOSIZE (16*4) - -#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2) - #define NR_SG 16 struct clk; diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 2ac7367afe77..8beb0d0233b5 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -35,6 +35,7 @@ #include <linux/slab.h> #include <mach/nand.h> +#include <mach/aemif.h> #include <asm/mach-types.h> @@ -74,6 +75,8 @@ struct davinci_nand_info { uint32_t mask_cle; uint32_t core_chipsel; + + struct davinci_aemif_timing *timing; }; static DEFINE_SPINLOCK(davinci_nand_lock); @@ -478,36 +481,6 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd) return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); } -static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info) -{ - uint32_t regval, a1cr; - - /* - * NAND FLASH timings @ PLL1 == 459 MHz - * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz - * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns - */ - regval = 0 - | (0 << 31) /* selectStrobe */ - | (0 << 30) /* extWait (never with NAND) */ - | (1 << 26) /* writeSetup 10 ns */ - | (3 << 20) /* writeStrobe 40 ns */ - | (1 << 17) /* writeHold 10 ns */ - | (0 << 13) /* readSetup 10 ns */ - | (3 << 7) /* readStrobe 60 ns */ - | (0 << 4) /* readHold 10 ns */ - | (3 << 2) /* turnAround ?? ns */ - | (0 << 0) /* asyncSize 8-bit bus */ - ; - a1cr = davinci_nand_readl(info, A1CR_OFFSET); - if (a1cr != regval) { - dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \ - "reg to 0x%08x, was 0x%08x, should be done by " \ - "bootloader.\n", regval, a1cr); - davinci_nand_writel(info, A1CR_OFFSET, regval); - } -} - /*----------------------------------------------------------------------*/ /* An ECC layout for using 4-bit ECC with small-page flash, storing @@ -611,6 +584,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev) info->chip.options = pdata->options; info->chip.bbt_td = pdata->bbt_td; info->chip.bbt_md = pdata->bbt_md; + info->timing = pdata->timing; info->ioaddr = (uint32_t __force) vaddr; @@ -688,15 +662,25 @@ static int __init nand_davinci_probe(struct platform_device *pdev) goto err_clk_enable; } - /* EMIF timings should normally be set by the boot loader, - * especially after boot-from-NAND. The *only* reason to - * have this special casing for the DM6446 EVM is to work - * with boot-from-NOR ... with CS0 manually re-jumpered - * (after startup) so it addresses the NAND flash, not NOR. - * Even for dev boards, that's unusually rude... + /* + * Setup Async configuration register in case we did not boot from + * NAND and so bootloader did not bother to set it up. */ - if (machine_is_davinci_evm()) - nand_dm6446evm_flash_init(info); + val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4); + + /* Extended Wait is not valid and Select Strobe mode is not used */ + val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK); + if (info->chip.options & NAND_BUSWIDTH_16) + val |= 0x1; + + davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val); + + ret = davinci_aemif_setup_timing(info->timing, info->base, + info->core_chipsel); + if (ret < 0) { + dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); + goto err_timing; + } spin_lock_irq(&davinci_nand_lock); @@ -809,6 +793,7 @@ syndrome_done: return 0; err_scan: +err_timing: clk_disable(info->clk); err_clk_enable: diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c index c3edfe4c2651..49279b0ee526 100644 --- a/drivers/net/pcmcia/pcnet_cs.c +++ b/drivers/net/pcmcia/pcnet_cs.c @@ -1637,6 +1637,7 @@ static struct pcmcia_device_id pcnet_ids[] = { PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCETTX", 0x547e66dc, 0x6fc5459b), PCMCIA_DEVICE_PROD_ID12("iPort", "10/100 Ethernet Card", 0x56c538d2, 0x11b0ffc0), PCMCIA_DEVICE_PROD_ID12("KANSAI ELECTRIC CO.,LTD", "KLA-PCM/T", 0xb18dc3b4, 0xcc51a956), + PCMCIA_DEVICE_PROD_ID12("KENTRONICS", "KEP-230", 0xaf8144c9, 0x868f6616), PCMCIA_DEVICE_PROD_ID12("KCI", "PE520 PCMCIA Ethernet Adapter", 0xa89b87d3, 0x1eb88e64), PCMCIA_DEVICE_PROD_ID12("KINGMAX", "EN10T2T", 0x7bcb459a, 0xa5c81fa5), PCMCIA_DEVICE_PROD_ID12("Kingston", "KNE-PC2", 0x1128e633, 0xce2a89b3), diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c index 373dcfec689c..d77ce9906b6c 100644 --- a/drivers/net/wireless/ath/ath5k/base.c +++ b/drivers/net/wireless/ath/ath5k/base.c @@ -1327,6 +1327,10 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, PCI_DMA_TODEVICE); rate = ieee80211_get_tx_rate(sc->hw, info); + if (!rate) { + ret = -EINVAL; + goto err_unmap; + } if (info->flags & IEEE80211_TX_CTL_NO_ACK) flags |= AR5K_TXDESC_NOACK; diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index b883b174385b..057fb69ddf7f 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c @@ -797,7 +797,7 @@ static bool ar9300_uncompress_block(struct ath_hw *ah, length = block[it+1]; length &= 0xff; - if (length > 0 && spot >= 0 && spot+length < mdataSize) { + if (length > 0 && spot >= 0 && spot+length <= mdataSize) { ath_print(common, ATH_DBG_EEPROM, "Restore at %d: spot=%d " "offset=%d length=%d\n", diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h index 7f48df1e2903..0b09db0f8e7d 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom.h +++ b/drivers/net/wireless/ath/ath9k/eeprom.h @@ -62,7 +62,7 @@ #define SD_NO_CTL 0xE0 #define NO_CTL 0xff -#define CTL_MODE_M 7 +#define CTL_MODE_M 0xf #define CTL_11A 0 #define CTL_11B 1 #define CTL_11G 2 diff --git a/drivers/net/wireless/ath/regd.h b/drivers/net/wireless/ath/regd.h index a1c39526161a..345dd9721b41 100644 --- a/drivers/net/wireless/ath/regd.h +++ b/drivers/net/wireless/ath/regd.h @@ -31,7 +31,6 @@ enum ctl_group { #define NO_CTL 0xff #define SD_NO_CTL 0xE0 #define NO_CTL 0xff -#define CTL_MODE_M 7 #define CTL_11A 0 #define CTL_11B 1 #define CTL_11G 2 diff --git a/drivers/net/wireless/libertas/if_sdio.c b/drivers/net/wireless/libertas/if_sdio.c index ba854c70ab94..87b634978b35 100644 --- a/drivers/net/wireless/libertas/if_sdio.c +++ b/drivers/net/wireless/libertas/if_sdio.c @@ -128,7 +128,7 @@ struct if_sdio_card { bool helper_allocated; bool firmware_allocated; - u8 buffer[65536]; + u8 buffer[65536] __attribute__((aligned(4))); spinlock_t lock; struct if_sdio_packet *packets; diff --git a/drivers/net/wireless/p54/txrx.c b/drivers/net/wireless/p54/txrx.c index 173aec3d6e7e..0e937dc0c9c4 100644 --- a/drivers/net/wireless/p54/txrx.c +++ b/drivers/net/wireless/p54/txrx.c @@ -446,7 +446,7 @@ static void p54_rx_frame_sent(struct p54_common *priv, struct sk_buff *skb) } if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && - (!payload->status)) + !(payload->status & P54_TX_FAILED)) info->flags |= IEEE80211_TX_STAT_ACK; if (payload->status & P54_TX_PSM_CANCELLED) info->flags |= IEEE80211_TX_STAT_TX_FILTERED; diff --git a/drivers/pci/hotplug/acpi_pcihp.c b/drivers/pci/hotplug/acpi_pcihp.c index 45fcc1e96df9..3bc72d18b121 100644 --- a/drivers/pci/hotplug/acpi_pcihp.c +++ b/drivers/pci/hotplug/acpi_pcihp.c @@ -338,9 +338,7 @@ int acpi_get_hp_hw_control_from_firmware(struct pci_dev *pdev, u32 flags) acpi_handle chandle, handle; struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; - flags &= (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | - OSC_SHPC_NATIVE_HP_CONTROL | - OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); + flags &= OSC_SHPC_NATIVE_HP_CONTROL; if (!flags) { err("Invalid flags %u specified!\n", flags); return -EINVAL; @@ -360,7 +358,7 @@ int acpi_get_hp_hw_control_from_firmware(struct pci_dev *pdev, u32 flags) acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); dbg("Trying to get hotplug control for %s\n", (char *)string.pointer); - status = acpi_pci_osc_control_set(handle, flags); + status = acpi_pci_osc_control_set(handle, &flags, flags); if (ACPI_SUCCESS(status)) goto got_one; if (status == AE_SUPPORT) diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index 4ed76b47b6dc..73d513989263 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -176,19 +176,11 @@ static inline void pciehp_firmware_init(void) { pciehp_acpi_slot_detection_init(); } - -static inline int pciehp_get_hp_hw_control_from_firmware(struct pci_dev *dev) -{ - int retval; - u32 flags = (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | - OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); - retval = acpi_get_hp_hw_control_from_firmware(dev, flags); - if (retval) - return retval; - return pciehp_acpi_slot_detection_check(dev); -} #else #define pciehp_firmware_init() do {} while (0) -#define pciehp_get_hp_hw_control_from_firmware(dev) 0 +static inline int pciehp_acpi_slot_detection_check(struct pci_dev *dev) +{ + return 0; +} #endif /* CONFIG_ACPI */ #endif /* _PCIEHP_H */ diff --git a/drivers/pci/hotplug/pciehp_acpi.c b/drivers/pci/hotplug/pciehp_acpi.c index 1f4000a5a108..2574700db461 100644 --- a/drivers/pci/hotplug/pciehp_acpi.c +++ b/drivers/pci/hotplug/pciehp_acpi.c @@ -85,9 +85,7 @@ static int __init dummy_probe(struct pcie_device *dev) acpi_handle handle; struct dummy_slot *slot, *tmp; struct pci_dev *pdev = dev->port; - /* Note: pciehp_detect_mode != PCIEHP_DETECT_ACPI here */ - if (pciehp_get_hp_hw_control_from_firmware(pdev)) - return -ENODEV; + pos = pci_pcie_cap(pdev); if (!pos) return -ENODEV; diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c index 3588ea61b0dd..aa5f3ff629ff 100644 --- a/drivers/pci/hotplug/pciehp_core.c +++ b/drivers/pci/hotplug/pciehp_core.c @@ -59,7 +59,7 @@ module_param(pciehp_force, bool, 0644); MODULE_PARM_DESC(pciehp_debug, "Debugging mode enabled or not"); MODULE_PARM_DESC(pciehp_poll_mode, "Using polling mechanism for hot-plug events or not"); MODULE_PARM_DESC(pciehp_poll_time, "Polling mechanism frequency, in seconds"); -MODULE_PARM_DESC(pciehp_force, "Force pciehp, even if _OSC and OSHP are missing"); +MODULE_PARM_DESC(pciehp_force, "Force pciehp, even if OSHP is missing"); #define PCIE_MODULE_NAME "pciehp" @@ -235,7 +235,7 @@ static int pciehp_probe(struct pcie_device *dev) dev_info(&dev->device, "Bypassing BIOS check for pciehp use on %s\n", pci_name(dev->port)); - else if (pciehp_get_hp_hw_control_from_firmware(dev->port)) + else if (pciehp_acpi_slot_detection_check(dev->port)) goto err_out_none; ctrl = pcie_init(dev); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 679c39de6a89..7754a678ab15 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -140,8 +140,10 @@ static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { } #ifdef CONFIG_PCIEAER void pci_no_aer(void); +bool pci_aer_available(void); #else static inline void pci_no_aer(void) { } +static inline bool pci_aer_available(void) { return false; } #endif static inline int pci_no_d1d2(struct pci_dev *dev) diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index ea654545e7c4..00c62df5a9fc 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -6,10 +6,11 @@ obj-$(CONFIG_PCIEASPM) += aspm.o pcieportdrv-y := portdrv_core.o portdrv_pci.o portdrv_bus.o +pcieportdrv-$(CONFIG_ACPI) += portdrv_acpi.o obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o # Build PCI Express AER if needed obj-$(CONFIG_PCIEAER) += aer/ -obj-$(CONFIG_PCIE_PME) += pme/ +obj-$(CONFIG_PCIE_PME) += pme.o diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index 484cc55194b8..f409948e1a9b 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -72,6 +72,11 @@ void pci_no_aer(void) pcie_aer_disable = 1; /* has priority over 'forceload' */ } +bool pci_aer_available(void) +{ + return !pcie_aer_disable && pci_msi_enabled(); +} + static int set_device_error_reporting(struct pci_dev *dev, void *data) { bool enable = *((bool *)data); @@ -411,9 +416,7 @@ static void aer_error_resume(struct pci_dev *dev) */ static int __init aer_service_init(void) { - if (pcie_aer_disable) - return -ENXIO; - if (!pci_msi_enabled()) + if (!pci_aer_available()) return -ENXIO; return pcie_port_service_register(&aerdriver); } diff --git a/drivers/pci/pcie/aer/aerdrv_acpi.c b/drivers/pci/pcie/aer/aerdrv_acpi.c index f278d7b0d95d..2bb9b8972211 100644 --- a/drivers/pci/pcie/aer/aerdrv_acpi.c +++ b/drivers/pci/pcie/aer/aerdrv_acpi.c @@ -19,42 +19,6 @@ #include <acpi/apei.h> #include "aerdrv.h" -/** - * aer_osc_setup - run ACPI _OSC method - * @pciedev: pcie_device which AER is being enabled on - * - * @return: Zero on success. Nonzero otherwise. - * - * Invoked when PCIe bus loads AER service driver. To avoid conflict with - * BIOS AER support requires BIOS to yield AER control to OS native driver. - **/ -int aer_osc_setup(struct pcie_device *pciedev) -{ - acpi_status status = AE_NOT_FOUND; - struct pci_dev *pdev = pciedev->port; - acpi_handle handle = NULL; - - if (acpi_pci_disabled) - return -1; - - handle = acpi_find_root_bridge_handle(pdev); - if (handle) { - status = acpi_pci_osc_control_set(handle, - OSC_PCI_EXPRESS_AER_CONTROL | - OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); - } - - if (ACPI_FAILURE(status)) { - dev_printk(KERN_DEBUG, &pciedev->device, "AER service couldn't " - "init device: %s\n", - (status == AE_SUPPORT || status == AE_NOT_FOUND) ? - "no _OSC support" : "_OSC failed"); - return -1; - } - - return 0; -} - #ifdef CONFIG_ACPI_APEI static inline int hest_match_pci(struct acpi_hest_aer_common *p, struct pci_dev *pci) diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index fc0b5a93e1de..29e268fadf14 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -772,22 +772,10 @@ void aer_isr(struct work_struct *work) */ int aer_init(struct pcie_device *dev) { - if (pcie_aer_get_firmware_first(dev->port)) { - dev_printk(KERN_DEBUG, &dev->device, - "PCIe errors handled by platform firmware.\n"); - goto out; - } - - if (aer_osc_setup(dev)) - goto out; - - return 0; -out: if (forceload) { dev_printk(KERN_DEBUG, &dev->device, "aerdrv forceload requested.\n"); pcie_aer_force_firmware_first(dev->port, 0); - return 0; } - return -ENXIO; + return 0; } diff --git a/drivers/pci/pcie/pme/pcie_pme.c b/drivers/pci/pcie/pme.c index bbdea18693d9..2f3c90407227 100644 --- a/drivers/pci/pcie/pme/pcie_pme.c +++ b/drivers/pci/pcie/pme.c @@ -23,38 +23,13 @@ #include <linux/pci-acpi.h> #include <linux/pm_runtime.h> -#include "../../pci.h" -#include "pcie_pme.h" +#include "../pci.h" +#include "portdrv.h" #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ /* - * If set, this switch will prevent the PCIe root port PME service driver from - * being registered. Consequently, the interrupt-based PCIe PME signaling will - * not be used by any PCIe root ports in that case. - */ -static bool pcie_pme_disabled = true; - -/* - * The PCI Express Base Specification 2.0, Section 6.1.8, states the following: - * "In order to maintain compatibility with non-PCI Express-aware system - * software, system power management logic must be configured by firmware to use - * the legacy mechanism of signaling PME by default. PCI Express-aware system - * software must notify the firmware prior to enabling native, interrupt-based - * PME signaling." However, if the platform doesn't provide us with a suitable - * notification mechanism or the notification fails, it is not clear whether or - * not we are supposed to use the interrupt-based PCIe PME signaling. The - * switch below can be used to indicate the desired behaviour. When set, it - * will make the kernel use the interrupt-based PCIe PME signaling regardless of - * the platform notification status, although the kernel will attempt to notify - * the platform anyway. When unset, it will prevent the kernel from using the - * the interrupt-based PCIe PME signaling if the platform notification fails, - * which is the default. - */ -static bool pcie_pme_force_enable; - -/* * If this switch is set, MSI will not be used for PCIe PME signaling. This * causes the PCIe port driver to use INTx interrupts only, but it turns out * that using MSI for PCIe PME signaling doesn't play well with PCIe PME-based @@ -64,38 +39,13 @@ bool pcie_pme_msi_disabled; static int __init pcie_pme_setup(char *str) { - if (!strncmp(str, "auto", 4)) - pcie_pme_disabled = false; - else if (!strncmp(str, "force", 5)) - pcie_pme_force_enable = true; - - str = strchr(str, ','); - if (str) { - str++; - str += strspn(str, " \t"); - if (*str && !strcmp(str, "nomsi")) - pcie_pme_msi_disabled = true; - } + if (!strncmp(str, "nomsi", 5)) + pcie_pme_msi_disabled = true; return 1; } __setup("pcie_pme=", pcie_pme_setup); -/** - * pcie_pme_platform_setup - Ensure that the kernel controls the PCIe PME. - * @srv: PCIe PME root port service to use for carrying out the check. - * - * Notify the platform that the native PCIe PME is going to be used and return - * 'true' if the control of the PCIe PME registers has been acquired from the - * platform. - */ -static bool pcie_pme_platform_setup(struct pcie_device *srv) -{ - if (!pcie_pme_platform_notify(srv)) - return true; - return pcie_pme_force_enable; -} - struct pcie_pme_service_data { spinlock_t lock; struct pcie_device *srv; @@ -108,7 +58,7 @@ struct pcie_pme_service_data { * @dev: PCIe root port or event collector. * @enable: Enable or disable the interrupt. */ -static void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable) +void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable) { int rtctl_pos; u16 rtctl; @@ -417,9 +367,6 @@ static int pcie_pme_probe(struct pcie_device *srv) struct pcie_pme_service_data *data; int ret; - if (!pcie_pme_platform_setup(srv)) - return -EACCES; - data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; @@ -509,8 +456,7 @@ static struct pcie_port_service_driver pcie_pme_driver = { */ static int __init pcie_pme_service_init(void) { - return pcie_pme_disabled ? - -ENODEV : pcie_port_service_register(&pcie_pme_driver); + return pcie_port_service_register(&pcie_pme_driver); } module_init(pcie_pme_service_init); diff --git a/drivers/pci/pcie/pme/Makefile b/drivers/pci/pcie/pme/Makefile deleted file mode 100644 index 8b9238053080..000000000000 --- a/drivers/pci/pcie/pme/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for PCI-Express Root Port PME signaling driver -# - -obj-$(CONFIG_PCIE_PME) += pmedriver.o - -pmedriver-objs := pcie_pme.o -pmedriver-$(CONFIG_ACPI) += pcie_pme_acpi.o diff --git a/drivers/pci/pcie/pme/pcie_pme.h b/drivers/pci/pcie/pme/pcie_pme.h deleted file mode 100644 index b30d2b7c9775..000000000000 --- a/drivers/pci/pcie/pme/pcie_pme.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * drivers/pci/pcie/pme/pcie_pme.h - * - * PCI Express Root Port PME signaling support - * - * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc. - */ - -#ifndef _PCIE_PME_H_ -#define _PCIE_PME_H_ - -struct pcie_device; - -#ifdef CONFIG_ACPI -extern int pcie_pme_acpi_setup(struct pcie_device *srv); - -static inline int pcie_pme_platform_notify(struct pcie_device *srv) -{ - return pcie_pme_acpi_setup(srv); -} -#else /* !CONFIG_ACPI */ -static inline int pcie_pme_platform_notify(struct pcie_device *srv) -{ - return 0; -} -#endif /* !CONFIG_ACPI */ - -#endif diff --git a/drivers/pci/pcie/pme/pcie_pme_acpi.c b/drivers/pci/pcie/pme/pcie_pme_acpi.c deleted file mode 100644 index 83ab2287ae3f..000000000000 --- a/drivers/pci/pcie/pme/pcie_pme_acpi.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * PCIe Native PME support, ACPI-related part - * - * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc. - * - * This file is subject to the terms and conditions of the GNU General Public - * License V2. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/acpi.h> -#include <linux/pci-acpi.h> -#include <linux/pcieport_if.h> - -/** - * pcie_pme_acpi_setup - Request the ACPI BIOS to release control over PCIe PME. - * @srv - PCIe PME service for a root port or event collector. - * - * Invoked when the PCIe bus type loads PCIe PME service driver. To avoid - * conflict with the BIOS PCIe support requires the BIOS to yield PCIe PME - * control to the kernel. - */ -int pcie_pme_acpi_setup(struct pcie_device *srv) -{ - acpi_status status = AE_NOT_FOUND; - struct pci_dev *port = srv->port; - acpi_handle handle; - int error = 0; - - if (acpi_pci_disabled) - return -ENOSYS; - - dev_info(&port->dev, "Requesting control of PCIe PME from ACPI BIOS\n"); - - handle = acpi_find_root_bridge_handle(port); - if (!handle) - return -EINVAL; - - status = acpi_pci_osc_control_set(handle, - OSC_PCI_EXPRESS_PME_CONTROL | - OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); - if (ACPI_FAILURE(status)) { - dev_info(&port->dev, - "Failed to receive control of PCIe PME service: %s\n", - (status == AE_SUPPORT || status == AE_NOT_FOUND) ? - "no _OSC support" : "ACPI _OSC failed"); - error = -ENODEV; - } - - return error; -} diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 813a5c3427b6..7b5aba0a3291 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -20,6 +20,9 @@ #define get_descriptor_id(type, service) (((type - 4) << 4) | service) +extern bool pcie_ports_disabled; +extern bool pcie_ports_auto; + extern struct bus_type pcie_port_bus_type; extern int pcie_port_device_register(struct pci_dev *dev); #ifdef CONFIG_PM @@ -30,6 +33,8 @@ extern void pcie_port_device_remove(struct pci_dev *dev); extern int __must_check pcie_port_bus_register(void); extern void pcie_port_bus_unregister(void); +struct pci_dev; + #ifdef CONFIG_PCIE_PME extern bool pcie_pme_msi_disabled; @@ -42,9 +47,26 @@ static inline bool pcie_pme_no_msi(void) { return pcie_pme_msi_disabled; } + +extern void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable); #else /* !CONFIG_PCIE_PME */ static inline void pcie_pme_disable_msi(void) {} static inline bool pcie_pme_no_msi(void) { return false; } +static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {} #endif /* !CONFIG_PCIE_PME */ +#ifdef CONFIG_ACPI +extern int pcie_port_acpi_setup(struct pci_dev *port, int *mask); + +static inline int pcie_port_platform_notify(struct pci_dev *port, int *mask) +{ + return pcie_port_acpi_setup(port, mask); +} +#else /* !CONFIG_ACPI */ +static inline int pcie_port_platform_notify(struct pci_dev *port, int *mask) +{ + return 0; +} +#endif /* !CONFIG_ACPI */ + #endif /* _PORTDRV_H_ */ diff --git a/drivers/pci/pcie/portdrv_acpi.c b/drivers/pci/pcie/portdrv_acpi.c new file mode 100644 index 000000000000..b7c4cb1ccb23 --- /dev/null +++ b/drivers/pci/pcie/portdrv_acpi.c @@ -0,0 +1,77 @@ +/* + * PCIe Port Native Services Support, ACPI-Related Part + * + * Copyright (C) 2010 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License V2. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/acpi.h> +#include <linux/pci-acpi.h> +#include <linux/pcieport_if.h> + +#include "aer/aerdrv.h" +#include "../pci.h" + +/** + * pcie_port_acpi_setup - Request the BIOS to release control of PCIe services. + * @port: PCIe Port service for a root port or event collector. + * @srv_mask: Bit mask of services that can be enabled for @port. + * + * Invoked when @port is identified as a PCIe port device. To avoid conflicts + * with the BIOS PCIe port native services support requires the BIOS to yield + * control of these services to the kernel. The mask of services that the BIOS + * allows to be enabled for @port is written to @srv_mask. + * + * NOTE: It turns out that we cannot do that for individual port services + * separately, because that would make some systems work incorrectly. + */ +int pcie_port_acpi_setup(struct pci_dev *port, int *srv_mask) +{ + acpi_status status; + acpi_handle handle; + u32 flags; + + if (acpi_pci_disabled) + return 0; + + handle = acpi_find_root_bridge_handle(port); + if (!handle) + return -EINVAL; + + flags = OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL + | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL + | OSC_PCI_EXPRESS_PME_CONTROL; + + if (pci_aer_available()) { + if (pcie_aer_get_firmware_first(port)) + dev_dbg(&port->dev, "PCIe errors handled by BIOS.\n"); + else + flags |= OSC_PCI_EXPRESS_AER_CONTROL; + } + + status = acpi_pci_osc_control_set(handle, &flags, + OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); + if (ACPI_FAILURE(status)) { + dev_dbg(&port->dev, "ACPI _OSC request failed (code %d)\n", + status); + return -ENODEV; + } + + dev_info(&port->dev, "ACPI _OSC control granted for 0x%02x\n", flags); + + *srv_mask = PCIE_PORT_SERVICE_VC; + if (flags & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL) + *srv_mask |= PCIE_PORT_SERVICE_HP; + if (flags & OSC_PCI_EXPRESS_PME_CONTROL) + *srv_mask |= PCIE_PORT_SERVICE_PME; + if (flags & OSC_PCI_EXPRESS_AER_CONTROL) + *srv_mask |= PCIE_PORT_SERVICE_AER; + + return 0; +} diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index e73effbe402c..a9c222d79ebc 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -14,6 +14,8 @@ #include <linux/string.h> #include <linux/slab.h> #include <linux/pcieport_if.h> +#include <linux/aer.h> +#include <linux/pci-aspm.h> #include "../pci.h" #include "portdrv.h" @@ -236,24 +238,64 @@ static int get_port_device_capability(struct pci_dev *dev) int services = 0, pos; u16 reg16; u32 reg32; + int cap_mask; + int err; + + err = pcie_port_platform_notify(dev, &cap_mask); + if (pcie_ports_auto) { + if (err) { + pcie_no_aspm(); + return 0; + } + } else { + cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP + | PCIE_PORT_SERVICE_VC; + if (pci_aer_available()) + cap_mask |= PCIE_PORT_SERVICE_AER; + } pos = pci_pcie_cap(dev); pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); /* Hot-Plug Capable */ - if (reg16 & PCI_EXP_FLAGS_SLOT) { + if ((cap_mask & PCIE_PORT_SERVICE_HP) && (reg16 & PCI_EXP_FLAGS_SLOT)) { pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, ®32); - if (reg32 & PCI_EXP_SLTCAP_HPC) + if (reg32 & PCI_EXP_SLTCAP_HPC) { services |= PCIE_PORT_SERVICE_HP; + /* + * Disable hot-plug interrupts in case they have been + * enabled by the BIOS and the hot-plug service driver + * is not loaded. + */ + pos += PCI_EXP_SLTCTL; + pci_read_config_word(dev, pos, ®16); + reg16 &= ~(PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE); + pci_write_config_word(dev, pos, reg16); + } } /* AER capable */ - if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)) + if ((cap_mask & PCIE_PORT_SERVICE_AER) + && pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)) { services |= PCIE_PORT_SERVICE_AER; + /* + * Disable AER on this port in case it's been enabled by the + * BIOS (the AER service driver will enable it when necessary). + */ + pci_disable_pcie_error_reporting(dev); + } /* VC support */ if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VC)) services |= PCIE_PORT_SERVICE_VC; /* Root ports are capable of generating PME too */ - if (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) + if ((cap_mask & PCIE_PORT_SERVICE_PME) + && dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { services |= PCIE_PORT_SERVICE_PME; + /* + * Disable PME interrupt on this port in case it's been enabled + * by the BIOS (the PME service driver will enable it when + * necessary). + */ + pcie_pme_interrupt_enable(dev, false); + } return services; } @@ -494,6 +536,9 @@ static void pcie_port_shutdown_service(struct device *dev) {} */ int pcie_port_service_register(struct pcie_port_service_driver *new) { + if (pcie_ports_disabled) + return -ENODEV; + new->driver.name = (char *)new->name; new->driver.bus = &pcie_port_bus_type; new->driver.probe = pcie_port_probe_service; diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c index 3debed25e46b..f9033e190fb6 100644 --- a/drivers/pci/pcie/portdrv_pci.c +++ b/drivers/pci/pcie/portdrv_pci.c @@ -15,6 +15,7 @@ #include <linux/pcieport_if.h> #include <linux/aer.h> #include <linux/dmi.h> +#include <linux/pci-aspm.h> #include "portdrv.h" #include "aer/aerdrv.h" @@ -29,6 +30,31 @@ MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL"); +/* If this switch is set, PCIe port native services should not be enabled. */ +bool pcie_ports_disabled; + +/* + * If this switch is set, ACPI _OSC will be used to determine whether or not to + * enable PCIe port native services. + */ +bool pcie_ports_auto = true; + +static int __init pcie_port_setup(char *str) +{ + if (!strncmp(str, "compat", 6)) { + pcie_ports_disabled = true; + } else if (!strncmp(str, "native", 6)) { + pcie_ports_disabled = false; + pcie_ports_auto = false; + } else if (!strncmp(str, "auto", 4)) { + pcie_ports_disabled = false; + pcie_ports_auto = true; + } + + return 1; +} +__setup("pcie_ports=", pcie_port_setup); + /* global data */ static int pcie_portdrv_restore_config(struct pci_dev *dev) @@ -301,6 +327,11 @@ static int __init pcie_portdrv_init(void) { int retval; + if (pcie_ports_disabled) { + pcie_no_aspm(); + return -EACCES; + } + dmi_check_system(pcie_portdrv_dmi_table); retval = pcie_port_bus_register(); @@ -315,11 +346,4 @@ static int __init pcie_portdrv_init(void) return retval; } -static void __exit pcie_portdrv_exit(void) -{ - pci_unregister_driver(&pcie_portdriver); - pcie_port_bus_unregister(); -} - module_init(pcie_portdrv_init); -module_exit(pcie_portdrv_exit); diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index 659eaa0fc48f..968cfea04f74 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -49,7 +49,7 @@ static ssize_t address_read_file(struct pci_slot *slot, char *buf) } /* these strings match up with the values in pci_bus_speed */ -static char *pci_bus_speed_strings[] = { +static const char *pci_bus_speed_strings[] = { "33 MHz PCI", /* 0x00 */ "66 MHz PCI", /* 0x01 */ "66 MHz PCI-X", /* 0x02 */ diff --git a/drivers/s390/block/dasd_3990_erp.c b/drivers/s390/block/dasd_3990_erp.c index 85bfd8794856..bf7915dc64a6 100644 --- a/drivers/s390/block/dasd_3990_erp.c +++ b/drivers/s390/block/dasd_3990_erp.c @@ -221,6 +221,7 @@ dasd_3990_erp_DCTL(struct dasd_ccw_req * erp, char modifier) ccw->cmd_code = CCW_CMD_DCTL; ccw->count = 4; ccw->cda = (__u32)(addr_t) DCTL_data; + dctl_cqr->flags = erp->flags; dctl_cqr->function = dasd_3990_erp_DCTL; dctl_cqr->refers = erp; dctl_cqr->startdev = device; @@ -1710,6 +1711,7 @@ dasd_3990_erp_action_1B_32(struct dasd_ccw_req * default_erp, char *sense) ccw->cda = cpa; /* fill erp related fields */ + erp->flags = default_erp->flags; erp->function = dasd_3990_erp_action_1B_32; erp->refers = default_erp->refers; erp->startdev = device; @@ -2354,6 +2356,7 @@ static struct dasd_ccw_req *dasd_3990_erp_add_erp(struct dasd_ccw_req *cqr) ccw->cda = (long)(cqr->cpaddr); } + erp->flags = cqr->flags; erp->function = dasd_3990_erp_add_erp; erp->refers = cqr; erp->startdev = device; diff --git a/drivers/serial/68328serial.h b/drivers/serial/68328serial.h index 58aa2154655b..664ceb0a158c 100644 --- a/drivers/serial/68328serial.h +++ b/drivers/serial/68328serial.h @@ -181,13 +181,8 @@ struct m68k_serial { /* * Define the number of ports supported and their irqs. */ -#ifndef CONFIG_68328_SERIAL_UART2 #define NR_PORTS 1 #define UART_IRQ_DEFNS {UART_IRQ_NUM} -#else -#define NR_PORTS 2 -#define UART_IRQ_DEFNS {UART1_IRQ_NUM, UART2_IRQ_NUM} -#endif #endif /* __KERNEL__ */ #endif /* !(_MC683XX_SERIAL_H) */ diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 9b52f77a9305..d2352ac437c5 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -140,7 +140,15 @@ # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ -# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ + +#if defined(CONFIG_SH_SH2007) +/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ +# define SCSCR_INIT(port) 0x38 +#else +/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ +# define SCSCR_INIT(port) 0x3a +#endif + #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ defined(CONFIG_CPU_SUBTYPE_SH7786) # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ @@ -616,9 +624,10 @@ static inline int sci_rxd_in(struct uart_port *port) * -- Mitch Davis - 15 Jul 2000 */ -#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ - defined(CONFIG_CPU_SUBTYPE_SH7785) || \ - defined(CONFIG_CPU_SUBTYPE_SH7786) +#if (defined(CONFIG_CPU_SUBTYPE_SH7780) || \ + defined(CONFIG_CPU_SUBTYPE_SH7785) || \ + defined(CONFIG_CPU_SUBTYPE_SH7786)) && \ + !defined(CONFIG_SH_SH2007) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7720) || \ diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c index 9b03d7b3e456..c0fae0da6ec7 100644 --- a/drivers/serial/uartlite.c +++ b/drivers/serial/uartlite.c @@ -322,6 +322,26 @@ static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) return -EINVAL; } +#ifdef CONFIG_CONSOLE_POLL +static int ulite_get_poll_char(struct uart_port *port) +{ + while (!(ioread32be(port->membase + ULITE_STATUS) + & ULITE_STATUS_RXVALID)) + return NO_POLL_CHAR; + + return ioread32be(port->membase + ULITE_RX); +} + +static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) +{ + while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL) + cpu_relax(); + + /* write char to device */ + iowrite32be(ch, port->membase + ULITE_TX); +} +#endif + static struct uart_ops ulite_ops = { .tx_empty = ulite_tx_empty, .set_mctrl = ulite_set_mctrl, @@ -338,7 +358,11 @@ static struct uart_ops ulite_ops = { .release_port = ulite_release_port, .request_port = ulite_request_port, .config_port = ulite_config_port, - .verify_port = ulite_verify_port + .verify_port = ulite_verify_port, +#ifdef CONFIG_CONSOLE_POLL + .poll_get_char = ulite_get_poll_char, + .poll_put_char = ulite_put_poll_char, +#endif }; /* --------------------------------------------------------------------- diff --git a/drivers/sh/clk.c b/drivers/sh/clk.c index 5d84adac9ec4..b9c57a640c24 100644 --- a/drivers/sh/clk.c +++ b/drivers/sh/clk.c @@ -1,7 +1,7 @@ /* * drivers/sh/clk.c - SuperH clock framework * - * Copyright (C) 2005 - 2009 Paul Mundt + * Copyright (C) 2005 - 2010 Paul Mundt * * This clock framework is derived from the OMAP version by: * @@ -76,7 +76,8 @@ long clk_rate_table_round(struct clk *clk, unsigned long highest, lowest; int i; - highest = lowest = 0; + highest = 0; + lowest = ~0UL; for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { unsigned long freq = freq_table[i].frequency; @@ -354,10 +355,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent) ret = clk_reparent(clk, parent); if (ret == 0) { - pr_debug("clock: set parent of %s to %s (new rate %ld)\n", - clk->name, clk->parent->name, clk->rate); if (clk->ops->recalc) clk->rate = clk->ops->recalc(clk); + pr_debug("clock: set parent of %s to %s (new rate %ld)\n", + clk->name, clk->parent->name, clk->rate); propagate_rate(clk); } } else diff --git a/drivers/staging/comedi/drivers/das08_cs.c b/drivers/staging/comedi/drivers/das08_cs.c index c6aa52f8dcee..48d9fb1227df 100644 --- a/drivers/staging/comedi/drivers/das08_cs.c +++ b/drivers/staging/comedi/drivers/das08_cs.c @@ -222,7 +222,6 @@ static int das08_pcmcia_config_loop(struct pcmcia_device *p_dev, p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH; p_dev->resource[0]->flags |= pcmcia_io_cfg_data_width(io->flags); - p_dev->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK; p_dev->resource[0]->start = io->win[0].base; p_dev->resource[0]->end = io->win[0].len; if (io->nwin > 1) { diff --git a/drivers/staging/hv/netvsc_drv.c b/drivers/staging/hv/netvsc_drv.c index 56e11575c977..64a01147ecae 100644 --- a/drivers/staging/hv/netvsc_drv.c +++ b/drivers/staging/hv/netvsc_drv.c @@ -327,6 +327,9 @@ static const struct net_device_ops device_ops = { .ndo_stop = netvsc_close, .ndo_start_xmit = netvsc_start_xmit, .ndo_set_multicast_list = netvsc_set_multicast_list, + .ndo_change_mtu = eth_change_mtu, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_mac_address = eth_mac_addr, }; static int netvsc_probe(struct device *device) diff --git a/drivers/staging/hv/ring_buffer.c b/drivers/staging/hv/ring_buffer.c index 17bc7626f70a..d78c569ac94a 100644 --- a/drivers/staging/hv/ring_buffer.c +++ b/drivers/staging/hv/ring_buffer.c @@ -193,8 +193,7 @@ Description: static inline u64 GetRingBufferIndices(struct hv_ring_buffer_info *RingInfo) { - return ((u64)RingInfo->RingBuffer->WriteIndex << 32) - || RingInfo->RingBuffer->ReadIndex; + return (u64)RingInfo->RingBuffer->WriteIndex << 32; } diff --git a/drivers/staging/hv/storvsc_api.h b/drivers/staging/hv/storvsc_api.h index 0063bde9a4b2..8505a1c5f9ee 100644 --- a/drivers/staging/hv/storvsc_api.h +++ b/drivers/staging/hv/storvsc_api.h @@ -28,10 +28,10 @@ #include "vmbus_api.h" /* Defines */ -#define STORVSC_RING_BUFFER_SIZE (10*PAGE_SIZE) +#define STORVSC_RING_BUFFER_SIZE (20*PAGE_SIZE) #define BLKVSC_RING_BUFFER_SIZE (20*PAGE_SIZE) -#define STORVSC_MAX_IO_REQUESTS 64 +#define STORVSC_MAX_IO_REQUESTS 128 /* * In Hyper-V, each port/path/target maps to 1 scsi host adapter. In diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c index 075b61bd492f..3b9ccb062008 100644 --- a/drivers/staging/hv/storvsc_drv.c +++ b/drivers/staging/hv/storvsc_drv.c @@ -495,7 +495,7 @@ static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl, /* ASSERT(orig_sgl[i].offset + orig_sgl[i].length <= PAGE_SIZE); */ - if (j == 0) + if (bounce_addr == 0) bounce_addr = (unsigned long)kmap_atomic(sg_page((&bounce_sgl[j])), KM_IRQ0); while (srclen) { @@ -556,7 +556,7 @@ static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl, destlen = orig_sgl[i].length; /* ASSERT(orig_sgl[i].offset + orig_sgl[i].length <= PAGE_SIZE); */ - if (j == 0) + if (bounce_addr == 0) bounce_addr = (unsigned long)kmap_atomic(sg_page((&bounce_sgl[j])), KM_IRQ0); while (destlen) { diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig index 638ad6b35891..9493128e5fd2 100644 --- a/drivers/staging/octeon/Kconfig +++ b/drivers/staging/octeon/Kconfig @@ -1,6 +1,6 @@ config OCTEON_ETHERNET tristate "Cavium Networks Octeon Ethernet support" - depends on CPU_CAVIUM_OCTEON + depends on CPU_CAVIUM_OCTEON && NETDEVICES select PHYLIB select MDIO_OCTEON help diff --git a/drivers/staging/rt2860/usb_main_dev.c b/drivers/staging/rt2860/usb_main_dev.c index a0fe31de0a6d..ebf9074a9083 100644 --- a/drivers/staging/rt2860/usb_main_dev.c +++ b/drivers/staging/rt2860/usb_main_dev.c @@ -44,6 +44,7 @@ struct usb_device_id rtusb_usb_id[] = { {USB_DEVICE(0x07B8, 0x2870)}, /* AboCom */ {USB_DEVICE(0x07B8, 0x2770)}, /* AboCom */ {USB_DEVICE(0x0DF6, 0x0039)}, /* Sitecom 2770 */ + {USB_DEVICE(0x0DF6, 0x003F)}, /* Sitecom 2770 */ {USB_DEVICE(0x083A, 0x7512)}, /* Arcadyan 2770 */ {USB_DEVICE(0x0789, 0x0162)}, /* Logitec 2870 */ {USB_DEVICE(0x0789, 0x0163)}, /* Logitec 2870 */ @@ -95,7 +96,8 @@ struct usb_device_id rtusb_usb_id[] = { {USB_DEVICE(0x050d, 0x815c)}, {USB_DEVICE(0x1482, 0x3C09)}, /* Abocom */ {USB_DEVICE(0x14B2, 0x3C09)}, /* Alpha */ - {USB_DEVICE(0x04E8, 0x2018)}, /* samsung */ + {USB_DEVICE(0x04E8, 0x2018)}, /* samsung linkstick2 */ + {USB_DEVICE(0x1690, 0x0740)}, /* Askey */ {USB_DEVICE(0x5A57, 0x0280)}, /* Zinwell */ {USB_DEVICE(0x5A57, 0x0282)}, /* Zinwell */ {USB_DEVICE(0x7392, 0x7718)}, @@ -105,21 +107,34 @@ struct usb_device_id rtusb_usb_id[] = { {USB_DEVICE(0x1737, 0x0071)}, /* Linksys WUSB600N */ {USB_DEVICE(0x0411, 0x00e8)}, /* Buffalo WLI-UC-G300N */ {USB_DEVICE(0x050d, 0x815c)}, /* Belkin F5D8053 */ + {USB_DEVICE(0x100D, 0x9031)}, /* Motorola 2770 */ #endif /* RT2870 // */ #ifdef RT3070 {USB_DEVICE(0x148F, 0x3070)}, /* Ralink 3070 */ {USB_DEVICE(0x148F, 0x3071)}, /* Ralink 3071 */ {USB_DEVICE(0x148F, 0x3072)}, /* Ralink 3072 */ {USB_DEVICE(0x0DB0, 0x3820)}, /* Ralink 3070 */ + {USB_DEVICE(0x0DB0, 0x871C)}, /* Ralink 3070 */ + {USB_DEVICE(0x0DB0, 0x822C)}, /* Ralink 3070 */ + {USB_DEVICE(0x0DB0, 0x871B)}, /* Ralink 3070 */ + {USB_DEVICE(0x0DB0, 0x822B)}, /* Ralink 3070 */ {USB_DEVICE(0x0DF6, 0x003E)}, /* Sitecom 3070 */ {USB_DEVICE(0x0DF6, 0x0042)}, /* Sitecom 3072 */ + {USB_DEVICE(0x0DF6, 0x0048)}, /* Sitecom 3070 */ + {USB_DEVICE(0x0DF6, 0x0047)}, /* Sitecom 3071 */ {USB_DEVICE(0x14B2, 0x3C12)}, /* AL 3070 */ {USB_DEVICE(0x18C5, 0x0012)}, /* Corega 3070 */ {USB_DEVICE(0x083A, 0x7511)}, /* Arcadyan 3070 */ + {USB_DEVICE(0x083A, 0xA701)}, /* SMC 3070 */ + {USB_DEVICE(0x083A, 0xA702)}, /* SMC 3072 */ {USB_DEVICE(0x1740, 0x9703)}, /* EnGenius 3070 */ {USB_DEVICE(0x1740, 0x9705)}, /* EnGenius 3071 */ {USB_DEVICE(0x1740, 0x9706)}, /* EnGenius 3072 */ + {USB_DEVICE(0x1740, 0x9707)}, /* EnGenius 3070 */ + {USB_DEVICE(0x1740, 0x9708)}, /* EnGenius 3071 */ + {USB_DEVICE(0x1740, 0x9709)}, /* EnGenius 3072 */ {USB_DEVICE(0x13D3, 0x3273)}, /* AzureWave 3070 */ + {USB_DEVICE(0x13D3, 0x3305)}, /* AzureWave 3070*/ {USB_DEVICE(0x1044, 0x800D)}, /* Gigabyte GN-WB32L 3070 */ {USB_DEVICE(0x2019, 0xAB25)}, /* Planex Communications, Inc. RT3070 */ {USB_DEVICE(0x07B8, 0x3070)}, /* AboCom 3070 */ @@ -132,14 +147,36 @@ struct usb_device_id rtusb_usb_id[] = { {USB_DEVICE(0x07D1, 0x3C0D)}, /* D-Link 3070 */ {USB_DEVICE(0x07D1, 0x3C0E)}, /* D-Link 3070 */ {USB_DEVICE(0x07D1, 0x3C0F)}, /* D-Link 3070 */ + {USB_DEVICE(0x07D1, 0x3C16)}, /* D-Link 3070 */ + {USB_DEVICE(0x07D1, 0x3C17)}, /* D-Link 8070 */ {USB_DEVICE(0x1D4D, 0x000C)}, /* Pegatron Corporation 3070 */ {USB_DEVICE(0x1D4D, 0x000E)}, /* Pegatron Corporation 3070 */ {USB_DEVICE(0x5A57, 0x5257)}, /* Zinwell 3070 */ {USB_DEVICE(0x5A57, 0x0283)}, /* Zinwell 3072 */ {USB_DEVICE(0x04BB, 0x0945)}, /* I-O DATA 3072 */ + {USB_DEVICE(0x04BB, 0x0947)}, /* I-O DATA 3070 */ + {USB_DEVICE(0x04BB, 0x0948)}, /* I-O DATA 3072 */ {USB_DEVICE(0x203D, 0x1480)}, /* Encore 3070 */ + {USB_DEVICE(0x20B8, 0x8888)}, /* PARA INDUSTRIAL 3070 */ + {USB_DEVICE(0x0B05, 0x1784)}, /* Asus 3072 */ + {USB_DEVICE(0x203D, 0x14A9)}, /* Encore 3070*/ + {USB_DEVICE(0x0DB0, 0x899A)}, /* MSI 3070*/ + {USB_DEVICE(0x0DB0, 0x3870)}, /* MSI 3070*/ + {USB_DEVICE(0x0DB0, 0x870A)}, /* MSI 3070*/ + {USB_DEVICE(0x0DB0, 0x6899)}, /* MSI 3070 */ + {USB_DEVICE(0x0DB0, 0x3822)}, /* MSI 3070 */ + {USB_DEVICE(0x0DB0, 0x3871)}, /* MSI 3070 */ + {USB_DEVICE(0x0DB0, 0x871A)}, /* MSI 3070 */ + {USB_DEVICE(0x0DB0, 0x822A)}, /* MSI 3070 */ + {USB_DEVICE(0x0DB0, 0x3821)}, /* Ralink 3070 */ + {USB_DEVICE(0x0DB0, 0x821A)}, /* Ralink 3070 */ + {USB_DEVICE(0x083A, 0xA703)}, /* IO-MAGIC */ + {USB_DEVICE(0x13D3, 0x3307)}, /* Azurewave */ + {USB_DEVICE(0x13D3, 0x3321)}, /* Azurewave */ + {USB_DEVICE(0x07FA, 0x7712)}, /* Edimax */ + {USB_DEVICE(0x0789, 0x0166)}, /* Edimax */ + {USB_DEVICE(0x148F, 0x2070)}, /* Edimax */ #endif /* RT3070 // */ - {USB_DEVICE(0x0DF6, 0x003F)}, /* Sitecom WL-608 */ {USB_DEVICE(0x1737, 0x0077)}, /* Linksys WUSB54GC-EU v3 */ {USB_DEVICE(0x2001, 0x3C09)}, /* D-Link */ {USB_DEVICE(0x2001, 0x3C0A)}, /* D-Link 3072 */ diff --git a/drivers/staging/spectra/Kconfig b/drivers/staging/spectra/Kconfig index 5e2ffefb60af..d231ae27299d 100644 --- a/drivers/staging/spectra/Kconfig +++ b/drivers/staging/spectra/Kconfig @@ -2,6 +2,7 @@ menuconfig SPECTRA tristate "Denali Spectra Flash Translation Layer" depends on BLOCK + depends on X86_MRST default n ---help--- Enable the FTL pseudo-filesystem used with the NAND Flash diff --git a/drivers/staging/spectra/ffsport.c b/drivers/staging/spectra/ffsport.c index 44a7fbe7eccd..fa21a0fd8e84 100644 --- a/drivers/staging/spectra/ffsport.c +++ b/drivers/staging/spectra/ffsport.c @@ -28,6 +28,7 @@ #include <linux/log2.h> #include <linux/init.h> #include <linux/smp_lock.h> +#include <linux/slab.h> /**** Helper functions used for Div, Remainder operation on u64 ****/ diff --git a/drivers/staging/zram/zram_drv.c b/drivers/staging/zram/zram_drv.c index 77d4d715a789..722c840ac638 100644 --- a/drivers/staging/zram/zram_drv.c +++ b/drivers/staging/zram/zram_drv.c @@ -769,6 +769,7 @@ static int __init zram_init(void) free_devices: while (dev_id) destroy_device(&devices[--dev_id]); + kfree(devices); unregister: unregister_blkdev(zram_major, "zram"); out: diff --git a/fs/cifs/Kconfig b/fs/cifs/Kconfig index 0da1debd499d..0ed213970ced 100644 --- a/fs/cifs/Kconfig +++ b/fs/cifs/Kconfig @@ -2,6 +2,7 @@ config CIFS tristate "CIFS support (advanced network filesystem, SMBFS successor)" depends on INET select NLS + select CRYPTO select CRYPTO_MD5 select CRYPTO_ARC4 help diff --git a/fs/cifs/asn1.c b/fs/cifs/asn1.c index 21f0fbd86989..cfd1ce34e0bc 100644 --- a/fs/cifs/asn1.c +++ b/fs/cifs/asn1.c @@ -597,13 +597,13 @@ decode_negTokenInit(unsigned char *security_blob, int length, if (compare_oid(oid, oidlen, MSKRB5_OID, MSKRB5_OID_LEN)) server->sec_mskerberos = true; - if (compare_oid(oid, oidlen, KRB5U2U_OID, + else if (compare_oid(oid, oidlen, KRB5U2U_OID, KRB5U2U_OID_LEN)) server->sec_kerberosu2u = true; - if (compare_oid(oid, oidlen, KRB5_OID, + else if (compare_oid(oid, oidlen, KRB5_OID, KRB5_OID_LEN)) server->sec_kerberos = true; - if (compare_oid(oid, oidlen, NTLMSSP_OID, + else if (compare_oid(oid, oidlen, NTLMSSP_OID, NTLMSSP_OID_LEN)) server->sec_ntlmssp = true; diff --git a/fs/ext3/super.c b/fs/ext3/super.c index 5dbf4dba03c4..a367dd044280 100644 --- a/fs/ext3/super.c +++ b/fs/ext3/super.c @@ -1849,8 +1849,8 @@ static int ext3_fill_super (struct super_block *sb, void *data, int silent) goto failed_mount; } - if (le32_to_cpu(es->s_blocks_count) > - (sector_t)(~0ULL) >> (sb->s_blocksize_bits - 9)) { + if (generic_check_addressable(sb->s_blocksize_bits, + le32_to_cpu(es->s_blocks_count))) { ext3_msg(sb, KERN_ERR, "error: filesystem is too large to mount safely"); if (sizeof(sector_t) < 8) diff --git a/fs/ext4/super.c b/fs/ext4/super.c index 26147746c272..7f47c366bf15 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -2831,15 +2831,13 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent) * Test whether we have more sectors than will fit in sector_t, * and whether the max offset is addressable by the page cache. */ - if ((ext4_blocks_count(es) > - (sector_t)(~0ULL) >> (sb->s_blocksize_bits - 9)) || - (ext4_blocks_count(es) > - (pgoff_t)(~0ULL) >> (PAGE_CACHE_SHIFT - sb->s_blocksize_bits))) { + ret = generic_check_addressable(sb->s_blocksize_bits, + ext4_blocks_count(es)); + if (ret) { ext4_msg(sb, KERN_ERR, "filesystem" " too large to mount safely on this system"); if (sizeof(sector_t) < 8) ext4_msg(sb, KERN_WARNING, "CONFIG_LBDAF not enabled"); - ret = -EFBIG; goto failed_mount; } diff --git a/fs/gfs2/Kconfig b/fs/gfs2/Kconfig index cc9665522148..c465ae066c62 100644 --- a/fs/gfs2/Kconfig +++ b/fs/gfs2/Kconfig @@ -1,6 +1,6 @@ config GFS2_FS tristate "GFS2 file system support" - depends on EXPERIMENTAL && (64BIT || LBDAF) + depends on (64BIT || LBDAF) select DLM if GFS2_FS_LOCKING_DLM select CONFIGFS_FS if GFS2_FS_LOCKING_DLM select SYSFS if GFS2_FS_LOCKING_DLM diff --git a/fs/gfs2/aops.c b/fs/gfs2/aops.c index 194fe16d8418..180ef8a6de6b 100644 --- a/fs/gfs2/aops.c +++ b/fs/gfs2/aops.c @@ -36,8 +36,8 @@ #include "glops.h" -static void gfs2_page_add_databufs(struct gfs2_inode *ip, struct page *page, - unsigned int from, unsigned int to) +void gfs2_page_add_databufs(struct gfs2_inode *ip, struct page *page, + unsigned int from, unsigned int to) { struct buffer_head *head = page_buffers(page); unsigned int bsize = head->b_size; @@ -696,13 +696,11 @@ out: page_cache_release(page); - /* - * XXX(truncate): the call below should probably be replaced with - * a call to the gfs2-specific truncate blocks helper to actually - * release disk blocks.. - */ + gfs2_trans_end(sdp); if (pos + len > ip->i_inode.i_size) - truncate_setsize(&ip->i_inode, ip->i_inode.i_size); + gfs2_trim_blocks(&ip->i_inode); + goto out_trans_fail; + out_endtrans: gfs2_trans_end(sdp); out_trans_fail: @@ -802,10 +800,8 @@ static int gfs2_stuffed_write_end(struct inode *inode, struct buffer_head *dibh, page_cache_release(page); if (copied) { - if (inode->i_size < to) { + if (inode->i_size < to) i_size_write(inode, to); - ip->i_disksize = inode->i_size; - } gfs2_dinode_out(ip, di); mark_inode_dirty(inode); } @@ -876,8 +872,6 @@ static int gfs2_write_end(struct file *file, struct address_space *mapping, ret = generic_write_end(file, mapping, pos, len, copied, page, fsdata); if (ret > 0) { - if (inode->i_size > ip->i_disksize) - ip->i_disksize = inode->i_size; gfs2_dinode_out(ip, dibh->b_data); mark_inode_dirty(inode); } diff --git a/fs/gfs2/bmap.c b/fs/gfs2/bmap.c index 6f482809d1a3..04513e997df6 100644 --- a/fs/gfs2/bmap.c +++ b/fs/gfs2/bmap.c @@ -50,7 +50,7 @@ struct strip_mine { * @ip: the inode * @dibh: the dinode buffer * @block: the block number that was allocated - * @private: any locked page held by the caller process + * @page: The (optional) page. This is looked up if @page is NULL * * Returns: errno */ @@ -109,8 +109,7 @@ static int gfs2_unstuffer_page(struct gfs2_inode *ip, struct buffer_head *dibh, /** * gfs2_unstuff_dinode - Unstuff a dinode when the data has grown too big * @ip: The GFS2 inode to unstuff - * @unstuffer: the routine that handles unstuffing a non-zero length file - * @private: private data for the unstuffer + * @page: The (optional) page. This is looked up if the @page is NULL * * This routine unstuffs a dinode and returns it to a "normal" state such * that the height can be grown in the traditional way. @@ -132,7 +131,7 @@ int gfs2_unstuff_dinode(struct gfs2_inode *ip, struct page *page) if (error) goto out; - if (ip->i_disksize) { + if (i_size_read(&ip->i_inode)) { /* Get a free block, fill it with the stuffed data, and write it out to disk */ @@ -161,7 +160,7 @@ int gfs2_unstuff_dinode(struct gfs2_inode *ip, struct page *page) di = (struct gfs2_dinode *)dibh->b_data; gfs2_buffer_clear_tail(dibh, sizeof(struct gfs2_dinode)); - if (ip->i_disksize) { + if (i_size_read(&ip->i_inode)) { *(__be64 *)(di + 1) = cpu_to_be64(block); gfs2_add_inode_blocks(&ip->i_inode, 1); di->di_blocks = cpu_to_be64(gfs2_get_inode_blocks(&ip->i_inode)); @@ -885,83 +884,14 @@ out: } /** - * do_grow - Make a file look bigger than it is - * @ip: the inode - * @size: the size to set the file to - * - * Called with an exclusive lock on @ip. - * - * Returns: errno - */ - -static int do_grow(struct gfs2_inode *ip, u64 size) -{ - struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); - struct gfs2_alloc *al; - struct buffer_head *dibh; - int error; - - al = gfs2_alloc_get(ip); - if (!al) - return -ENOMEM; - - error = gfs2_quota_lock_check(ip); - if (error) - goto out; - - al->al_requested = sdp->sd_max_height + RES_DATA; - - error = gfs2_inplace_reserve(ip); - if (error) - goto out_gunlock_q; - - error = gfs2_trans_begin(sdp, - sdp->sd_max_height + al->al_rgd->rd_length + - RES_JDATA + RES_DINODE + RES_STATFS + RES_QUOTA, 0); - if (error) - goto out_ipres; - - error = gfs2_meta_inode_buffer(ip, &dibh); - if (error) - goto out_end_trans; - - if (size > sdp->sd_sb.sb_bsize - sizeof(struct gfs2_dinode)) { - if (gfs2_is_stuffed(ip)) { - error = gfs2_unstuff_dinode(ip, NULL); - if (error) - goto out_brelse; - } - } - - ip->i_disksize = size; - ip->i_inode.i_mtime = ip->i_inode.i_ctime = CURRENT_TIME; - gfs2_trans_add_bh(ip->i_gl, dibh, 1); - gfs2_dinode_out(ip, dibh->b_data); - -out_brelse: - brelse(dibh); -out_end_trans: - gfs2_trans_end(sdp); -out_ipres: - gfs2_inplace_release(ip); -out_gunlock_q: - gfs2_quota_unlock(ip); -out: - gfs2_alloc_put(ip); - return error; -} - - -/** * gfs2_block_truncate_page - Deal with zeroing out data for truncate * * This is partly borrowed from ext3. */ -static int gfs2_block_truncate_page(struct address_space *mapping) +static int gfs2_block_truncate_page(struct address_space *mapping, loff_t from) { struct inode *inode = mapping->host; struct gfs2_inode *ip = GFS2_I(inode); - loff_t from = inode->i_size; unsigned long index = from >> PAGE_CACHE_SHIFT; unsigned offset = from & (PAGE_CACHE_SIZE-1); unsigned blocksize, iblock, length, pos; @@ -1023,9 +953,11 @@ unlock: return err; } -static int trunc_start(struct gfs2_inode *ip, u64 size) +static int trunc_start(struct inode *inode, u64 oldsize, u64 newsize) { - struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); + struct gfs2_inode *ip = GFS2_I(inode); + struct gfs2_sbd *sdp = GFS2_SB(inode); + struct address_space *mapping = inode->i_mapping; struct buffer_head *dibh; int journaled = gfs2_is_jdata(ip); int error; @@ -1039,31 +971,26 @@ static int trunc_start(struct gfs2_inode *ip, u64 size) if (error) goto out; + gfs2_trans_add_bh(ip->i_gl, dibh, 1); + if (gfs2_is_stuffed(ip)) { - u64 dsize = size + sizeof(struct gfs2_dinode); - ip->i_disksize = size; - ip->i_inode.i_mtime = ip->i_inode.i_ctime = CURRENT_TIME; - gfs2_trans_add_bh(ip->i_gl, dibh, 1); - gfs2_dinode_out(ip, dibh->b_data); - if (dsize > dibh->b_size) - dsize = dibh->b_size; - gfs2_buffer_clear_tail(dibh, dsize); - error = 1; + gfs2_buffer_clear_tail(dibh, sizeof(struct gfs2_dinode) + newsize); } else { - if (size & (u64)(sdp->sd_sb.sb_bsize - 1)) - error = gfs2_block_truncate_page(ip->i_inode.i_mapping); - - if (!error) { - ip->i_disksize = size; - ip->i_inode.i_mtime = ip->i_inode.i_ctime = CURRENT_TIME; - ip->i_diskflags |= GFS2_DIF_TRUNC_IN_PROG; - gfs2_trans_add_bh(ip->i_gl, dibh, 1); - gfs2_dinode_out(ip, dibh->b_data); + if (newsize & (u64)(sdp->sd_sb.sb_bsize - 1)) { + error = gfs2_block_truncate_page(mapping, newsize); + if (error) + goto out_brelse; } + ip->i_diskflags |= GFS2_DIF_TRUNC_IN_PROG; } - brelse(dibh); + i_size_write(inode, newsize); + ip->i_inode.i_mtime = ip->i_inode.i_ctime = CURRENT_TIME; + gfs2_dinode_out(ip, dibh->b_data); + truncate_pagecache(inode, oldsize, newsize); +out_brelse: + brelse(dibh); out: gfs2_trans_end(sdp); return error; @@ -1123,7 +1050,7 @@ static int trunc_end(struct gfs2_inode *ip) if (error) goto out; - if (!ip->i_disksize) { + if (!i_size_read(&ip->i_inode)) { ip->i_height = 0; ip->i_goal = ip->i_no_addr; gfs2_buffer_clear_tail(dibh, sizeof(struct gfs2_dinode)); @@ -1143,92 +1070,154 @@ out: /** * do_shrink - make a file smaller - * @ip: the inode - * @size: the size to make the file - * @truncator: function to truncate the last partial block + * @inode: the inode + * @oldsize: the current inode size + * @newsize: the size to make the file * - * Called with an exclusive lock on @ip. + * Called with an exclusive lock on @inode. The @size must + * be equal to or smaller than the current inode size. * * Returns: errno */ -static int do_shrink(struct gfs2_inode *ip, u64 size) +static int do_shrink(struct inode *inode, u64 oldsize, u64 newsize) { + struct gfs2_inode *ip = GFS2_I(inode); int error; - error = trunc_start(ip, size); + error = trunc_start(inode, oldsize, newsize); if (error < 0) return error; - if (error > 0) + if (gfs2_is_stuffed(ip)) return 0; - error = trunc_dealloc(ip, size); - if (!error) + error = trunc_dealloc(ip, newsize); + if (error == 0) error = trunc_end(ip); return error; } -static int do_touch(struct gfs2_inode *ip, u64 size) +void gfs2_trim_blocks(struct inode *inode) { - struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); + u64 size = inode->i_size; + int ret; + + ret = do_shrink(inode, size, size); + WARN_ON(ret != 0); +} + +/** + * do_grow - Touch and update inode size + * @inode: The inode + * @size: The new size + * + * This function updates the timestamps on the inode and + * may also increase the size of the inode. This function + * must not be called with @size any smaller than the current + * inode size. + * + * Although it is not strictly required to unstuff files here, + * earlier versions of GFS2 have a bug in the stuffed file reading + * code which will result in a buffer overrun if the size is larger + * than the max stuffed file size. In order to prevent this from + * occuring, such files are unstuffed, but in other cases we can + * just update the inode size directly. + * + * Returns: 0 on success, or -ve on error + */ + +static int do_grow(struct inode *inode, u64 size) +{ + struct gfs2_inode *ip = GFS2_I(inode); + struct gfs2_sbd *sdp = GFS2_SB(inode); struct buffer_head *dibh; + struct gfs2_alloc *al = NULL; int error; - error = gfs2_trans_begin(sdp, RES_DINODE, 0); + if (gfs2_is_stuffed(ip) && + (size > (sdp->sd_sb.sb_bsize - sizeof(struct gfs2_dinode)))) { + al = gfs2_alloc_get(ip); + if (al == NULL) + return -ENOMEM; + + error = gfs2_quota_lock_check(ip); + if (error) + goto do_grow_alloc_put; + + al->al_requested = 1; + error = gfs2_inplace_reserve(ip); + if (error) + goto do_grow_qunlock; + } + + error = gfs2_trans_begin(sdp, RES_DINODE + 1, 0); if (error) - return error; + goto do_grow_release; - down_write(&ip->i_rw_mutex); + if (al) { + error = gfs2_unstuff_dinode(ip, NULL); + if (error) + goto do_end_trans; + } error = gfs2_meta_inode_buffer(ip, &dibh); if (error) - goto do_touch_out; + goto do_end_trans; + i_size_write(inode, size); ip->i_inode.i_mtime = ip->i_inode.i_ctime = CURRENT_TIME; gfs2_trans_add_bh(ip->i_gl, dibh, 1); gfs2_dinode_out(ip, dibh->b_data); brelse(dibh); -do_touch_out: - up_write(&ip->i_rw_mutex); +do_end_trans: gfs2_trans_end(sdp); +do_grow_release: + if (al) { + gfs2_inplace_release(ip); +do_grow_qunlock: + gfs2_quota_unlock(ip); +do_grow_alloc_put: + gfs2_alloc_put(ip); + } return error; } /** - * gfs2_truncatei - make a file a given size - * @ip: the inode - * @size: the size to make the file - * @truncator: function to truncate the last partial block + * gfs2_setattr_size - make a file a given size + * @inode: the inode + * @newsize: the size to make the file * - * The file size can grow, shrink, or stay the same size. + * The file size can grow, shrink, or stay the same size. This + * is called holding i_mutex and an exclusive glock on the inode + * in question. * * Returns: errno */ -int gfs2_truncatei(struct gfs2_inode *ip, u64 size) +int gfs2_setattr_size(struct inode *inode, u64 newsize) { - int error; + int ret; + u64 oldsize; - if (gfs2_assert_warn(GFS2_SB(&ip->i_inode), S_ISREG(ip->i_inode.i_mode))) - return -EINVAL; + BUG_ON(!S_ISREG(inode->i_mode)); - if (size > ip->i_disksize) - error = do_grow(ip, size); - else if (size < ip->i_disksize) - error = do_shrink(ip, size); - else - /* update time stamps */ - error = do_touch(ip, size); + ret = inode_newsize_ok(inode, newsize); + if (ret) + return ret; - return error; + oldsize = inode->i_size; + if (newsize >= oldsize) + return do_grow(inode, newsize); + + return do_shrink(inode, oldsize, newsize); } int gfs2_truncatei_resume(struct gfs2_inode *ip) { int error; - error = trunc_dealloc(ip, ip->i_disksize); + error = trunc_dealloc(ip, i_size_read(&ip->i_inode)); if (!error) error = trunc_end(ip); return error; @@ -1269,7 +1258,7 @@ int gfs2_write_alloc_required(struct gfs2_inode *ip, u64 offset, shift = sdp->sd_sb.sb_bsize_shift; BUG_ON(gfs2_is_dir(ip)); - end_of_file = (ip->i_disksize + sdp->sd_sb.sb_bsize - 1) >> shift; + end_of_file = (i_size_read(&ip->i_inode) + sdp->sd_sb.sb_bsize - 1) >> shift; lblock = offset >> shift; lblock_stop = (offset + len + sdp->sd_sb.sb_bsize - 1) >> shift; if (lblock_stop > end_of_file) diff --git a/fs/gfs2/bmap.h b/fs/gfs2/bmap.h index a20a5213135a..42fea03e2bd9 100644 --- a/fs/gfs2/bmap.h +++ b/fs/gfs2/bmap.h @@ -44,14 +44,16 @@ static inline void gfs2_write_calc_reserv(const struct gfs2_inode *ip, } } -int gfs2_unstuff_dinode(struct gfs2_inode *ip, struct page *page); -int gfs2_block_map(struct inode *inode, sector_t lblock, struct buffer_head *bh, int create); -int gfs2_extent_map(struct inode *inode, u64 lblock, int *new, u64 *dblock, unsigned *extlen); - -int gfs2_truncatei(struct gfs2_inode *ip, u64 size); -int gfs2_truncatei_resume(struct gfs2_inode *ip); -int gfs2_file_dealloc(struct gfs2_inode *ip); -int gfs2_write_alloc_required(struct gfs2_inode *ip, u64 offset, - unsigned int len); +extern int gfs2_unstuff_dinode(struct gfs2_inode *ip, struct page *page); +extern int gfs2_block_map(struct inode *inode, sector_t lblock, + struct buffer_head *bh, int create); +extern int gfs2_extent_map(struct inode *inode, u64 lblock, int *new, + u64 *dblock, unsigned *extlen); +extern int gfs2_setattr_size(struct inode *inode, u64 size); +extern void gfs2_trim_blocks(struct inode *inode); +extern int gfs2_truncatei_resume(struct gfs2_inode *ip); +extern int gfs2_file_dealloc(struct gfs2_inode *ip); +extern int gfs2_write_alloc_required(struct gfs2_inode *ip, u64 offset, + unsigned int len); #endif /* __BMAP_DOT_H__ */ diff --git a/fs/gfs2/dir.c b/fs/gfs2/dir.c index b9dd88a78dd4..c1042ae438cc 100644 --- a/fs/gfs2/dir.c +++ b/fs/gfs2/dir.c @@ -127,8 +127,8 @@ static int gfs2_dir_write_stuffed(struct gfs2_inode *ip, const char *buf, gfs2_trans_add_bh(ip->i_gl, dibh, 1); memcpy(dibh->b_data + offset + sizeof(struct gfs2_dinode), buf, size); - if (ip->i_disksize < offset + size) - ip->i_disksize = offset + size; + if (ip->i_inode.i_size < offset + size) + i_size_write(&ip->i_inode, offset + size); ip->i_inode.i_mtime = ip->i_inode.i_ctime = CURRENT_TIME; gfs2_dinode_out(ip, dibh->b_data); @@ -225,8 +225,8 @@ out: if (error) return error; - if (ip->i_disksize < offset + copied) - ip->i_disksize = offset + copied; + if (ip->i_inode.i_size < offset + copied) + i_size_write(&ip->i_inode, offset + copied); ip->i_inode.i_mtime = ip->i_inode.i_ctime = CURRENT_TIME; gfs2_trans_add_bh(ip->i_gl, dibh, 1); @@ -275,12 +275,13 @@ static int gfs2_dir_read_data(struct gfs2_inode *ip, char *buf, u64 offset, unsigned int o; int copied = 0; int error = 0; + u64 disksize = i_size_read(&ip->i_inode); - if (offset >= ip->i_disksize) + if (offset >= disksize) return 0; - if (offset + size > ip->i_disksize) - size = ip->i_disksize - offset; + if (offset + size > disksize) + size = disksize - offset; if (!size) return 0; @@ -727,7 +728,7 @@ static struct gfs2_dirent *gfs2_dirent_search(struct inode *inode, unsigned hsize = 1 << ip->i_depth; unsigned index; u64 ln; - if (hsize * sizeof(u64) != ip->i_disksize) { + if (hsize * sizeof(u64) != i_size_read(inode)) { gfs2_consist_inode(ip); return ERR_PTR(-EIO); } @@ -879,7 +880,7 @@ static int dir_make_exhash(struct inode *inode) for (x = sdp->sd_hash_ptrs; x--; lp++) *lp = cpu_to_be64(bn); - dip->i_disksize = sdp->sd_sb.sb_bsize / 2; + i_size_write(inode, sdp->sd_sb.sb_bsize / 2); gfs2_add_inode_blocks(&dip->i_inode, 1); dip->i_diskflags |= GFS2_DIF_EXHASH; @@ -1057,11 +1058,12 @@ static int dir_double_exhash(struct gfs2_inode *dip) u64 *buf; u64 *from, *to; u64 block; + u64 disksize = i_size_read(&dip->i_inode); int x; int error = 0; hsize = 1 << dip->i_depth; - if (hsize * sizeof(u64) != dip->i_disksize) { + if (hsize * sizeof(u64) != disksize) { gfs2_consist_inode(dip); return -EIO; } @@ -1072,7 +1074,7 @@ static int dir_double_exhash(struct gfs2_inode *dip) if (!buf) return -ENOMEM; - for (block = dip->i_disksize >> sdp->sd_hash_bsize_shift; block--;) { + for (block = disksize >> sdp->sd_hash_bsize_shift; block--;) { error = gfs2_dir_read_data(dip, (char *)buf, block * sdp->sd_hash_bsize, sdp->sd_hash_bsize, 1); @@ -1370,7 +1372,7 @@ static int dir_e_read(struct inode *inode, u64 *offset, void *opaque, unsigned depth = 0; hsize = 1 << dip->i_depth; - if (hsize * sizeof(u64) != dip->i_disksize) { + if (hsize * sizeof(u64) != i_size_read(inode)) { gfs2_consist_inode(dip); return -EIO; } @@ -1784,7 +1786,7 @@ static int foreach_leaf(struct gfs2_inode *dip, leaf_call_t lc, void *data) int error = 0; hsize = 1 << dip->i_depth; - if (hsize * sizeof(u64) != dip->i_disksize) { + if (hsize * sizeof(u64) != i_size_read(&dip->i_inode)) { gfs2_consist_inode(dip); return -EIO; } diff --git a/fs/gfs2/file.c b/fs/gfs2/file.c index 4edd662c8232..daadcd2e755f 100644 --- a/fs/gfs2/file.c +++ b/fs/gfs2/file.c @@ -491,7 +491,7 @@ static int gfs2_open(struct inode *inode, struct file *file) goto fail; if (!(file->f_flags & O_LARGEFILE) && - ip->i_disksize > MAX_NON_LFS) { + i_size_read(inode) > MAX_NON_LFS) { error = -EOVERFLOW; goto fail_gunlock; } diff --git a/fs/gfs2/glops.c b/fs/gfs2/glops.c index 49f97d3bb690..621d80e8fb2a 100644 --- a/fs/gfs2/glops.c +++ b/fs/gfs2/glops.c @@ -262,13 +262,12 @@ static int inode_go_dump(struct seq_file *seq, const struct gfs2_glock *gl) const struct gfs2_inode *ip = gl->gl_object; if (ip == NULL) return 0; - gfs2_print_dbg(seq, " I: n:%llu/%llu t:%u f:0x%02lx d:0x%08x s:%llu/%llu\n", + gfs2_print_dbg(seq, " I: n:%llu/%llu t:%u f:0x%02lx d:0x%08x s:%llu\n", (unsigned long long)ip->i_no_formal_ino, (unsigned long long)ip->i_no_addr, IF2DT(ip->i_inode.i_mode), ip->i_flags, (unsigned int)ip->i_diskflags, - (unsigned long long)ip->i_inode.i_size, - (unsigned long long)ip->i_disksize); + (unsigned long long)i_size_read(&ip->i_inode)); return 0; } diff --git a/fs/gfs2/incore.h b/fs/gfs2/incore.h index fdbf4b366fa5..578234bb03f8 100644 --- a/fs/gfs2/incore.h +++ b/fs/gfs2/incore.h @@ -267,7 +267,6 @@ struct gfs2_inode { u64 i_no_formal_ino; u64 i_generation; u64 i_eattr; - loff_t i_disksize; unsigned long i_flags; /* GIF_... */ struct gfs2_glock *i_gl; /* Move into i_gh? */ struct gfs2_holder i_iopen_gh; @@ -572,6 +571,7 @@ struct gfs2_sbd { struct list_head sd_rindex_mru_list; struct gfs2_rgrpd *sd_rindex_forward; unsigned int sd_rgrps; + unsigned int sd_max_rg_data; /* Journal index stuff */ diff --git a/fs/gfs2/inode.c b/fs/gfs2/inode.c index 08140f185a37..06370f8bd8cf 100644 --- a/fs/gfs2/inode.c +++ b/fs/gfs2/inode.c @@ -359,8 +359,7 @@ static int gfs2_dinode_in(struct gfs2_inode *ip, const void *buf) * to do that. */ ip->i_inode.i_nlink = be32_to_cpu(str->di_nlink); - ip->i_disksize = be64_to_cpu(str->di_size); - i_size_write(&ip->i_inode, ip->i_disksize); + i_size_write(&ip->i_inode, be64_to_cpu(str->di_size)); gfs2_set_inode_blocks(&ip->i_inode, be64_to_cpu(str->di_blocks)); atime.tv_sec = be64_to_cpu(str->di_atime); atime.tv_nsec = be32_to_cpu(str->di_atime_nsec); @@ -1055,7 +1054,7 @@ void gfs2_dinode_out(const struct gfs2_inode *ip, void *buf) str->di_uid = cpu_to_be32(ip->i_inode.i_uid); str->di_gid = cpu_to_be32(ip->i_inode.i_gid); str->di_nlink = cpu_to_be32(ip->i_inode.i_nlink); - str->di_size = cpu_to_be64(ip->i_disksize); + str->di_size = cpu_to_be64(i_size_read(&ip->i_inode)); str->di_blocks = cpu_to_be64(gfs2_get_inode_blocks(&ip->i_inode)); str->di_atime = cpu_to_be64(ip->i_inode.i_atime.tv_sec); str->di_mtime = cpu_to_be64(ip->i_inode.i_mtime.tv_sec); @@ -1085,8 +1084,8 @@ void gfs2_dinode_print(const struct gfs2_inode *ip) (unsigned long long)ip->i_no_formal_ino); printk(KERN_INFO " no_addr = %llu\n", (unsigned long long)ip->i_no_addr); - printk(KERN_INFO " i_disksize = %llu\n", - (unsigned long long)ip->i_disksize); + printk(KERN_INFO " i_size = %llu\n", + (unsigned long long)i_size_read(&ip->i_inode)); printk(KERN_INFO " blocks = %llu\n", (unsigned long long)gfs2_get_inode_blocks(&ip->i_inode)); printk(KERN_INFO " i_goal = %llu\n", diff --git a/fs/gfs2/inode.h b/fs/gfs2/inode.h index 300ada3f21de..6720d7d5fbc6 100644 --- a/fs/gfs2/inode.h +++ b/fs/gfs2/inode.h @@ -19,6 +19,8 @@ extern int gfs2_releasepage(struct page *page, gfp_t gfp_mask); extern int gfs2_internal_read(struct gfs2_inode *ip, struct file_ra_state *ra_state, char *buf, loff_t *pos, unsigned size); +extern void gfs2_page_add_databufs(struct gfs2_inode *ip, struct page *page, + unsigned int from, unsigned int to); extern void gfs2_set_aops(struct inode *inode); static inline int gfs2_is_stuffed(const struct gfs2_inode *ip) @@ -80,6 +82,19 @@ static inline void gfs2_inum_out(const struct gfs2_inode *ip, dent->de_inum.no_addr = cpu_to_be64(ip->i_no_addr); } +static inline int gfs2_check_internal_file_size(struct inode *inode, + u64 minsize, u64 maxsize) +{ + u64 size = i_size_read(inode); + if (size < minsize || size > maxsize) + goto err; + if (size & ((1 << inode->i_blkbits) - 1)) + goto err; + return 0; +err: + gfs2_consist_inode(GFS2_I(inode)); + return -EIO; +} extern void gfs2_set_iop(struct inode *inode); extern struct inode *gfs2_inode_lookup(struct super_block *sb, unsigned type, diff --git a/fs/gfs2/ops_fstype.c b/fs/gfs2/ops_fstype.c index 4d4b1e8ac64c..5b5c87dfbfee 100644 --- a/fs/gfs2/ops_fstype.c +++ b/fs/gfs2/ops_fstype.c @@ -586,7 +586,7 @@ static int map_journal_extents(struct gfs2_sbd *sdp) prev_db = 0; - for (lb = 0; lb < ip->i_disksize >> sdp->sd_sb.sb_bsize_shift; lb++) { + for (lb = 0; lb < i_size_read(jd->jd_inode) >> sdp->sd_sb.sb_bsize_shift; lb++) { bh.b_state = 0; bh.b_blocknr = 0; bh.b_size = 1 << ip->i_inode.i_blkbits; diff --git a/fs/gfs2/ops_inode.c b/fs/gfs2/ops_inode.c index 1009be2c9737..ce4f1dfb533f 100644 --- a/fs/gfs2/ops_inode.c +++ b/fs/gfs2/ops_inode.c @@ -18,6 +18,8 @@ #include <linux/gfs2_ondisk.h> #include <linux/crc32.h> #include <linux/fiemap.h> +#include <linux/swap.h> +#include <linux/falloc.h> #include <asm/uaccess.h> #include "gfs2.h" @@ -406,7 +408,6 @@ static int gfs2_symlink(struct inode *dir, struct dentry *dentry, ip = ghs[1].gh_gl->gl_object; - ip->i_disksize = size; i_size_write(inode, size); error = gfs2_meta_inode_buffer(ip, &dibh); @@ -461,7 +462,7 @@ static int gfs2_mkdir(struct inode *dir, struct dentry *dentry, int mode) ip = ghs[1].gh_gl->gl_object; ip->i_inode.i_nlink = 2; - ip->i_disksize = sdp->sd_sb.sb_bsize - sizeof(struct gfs2_dinode); + i_size_write(inode, sdp->sd_sb.sb_bsize - sizeof(struct gfs2_dinode)); ip->i_diskflags |= GFS2_DIF_JDATA; ip->i_entries = 2; @@ -990,7 +991,7 @@ static void *gfs2_follow_link(struct dentry *dentry, struct nameidata *nd) struct gfs2_inode *ip = GFS2_I(dentry->d_inode); struct gfs2_holder i_gh; struct buffer_head *dibh; - unsigned int x; + unsigned int x, size; char *buf; int error; @@ -1002,7 +1003,8 @@ static void *gfs2_follow_link(struct dentry *dentry, struct nameidata *nd) return NULL; } - if (!ip->i_disksize) { + size = (unsigned int)i_size_read(&ip->i_inode); + if (size == 0) { gfs2_consist_inode(ip); buf = ERR_PTR(-EIO); goto out; @@ -1014,7 +1016,7 @@ static void *gfs2_follow_link(struct dentry *dentry, struct nameidata *nd) goto out; } - x = ip->i_disksize + 1; + x = size + 1; buf = kmalloc(x, GFP_NOFS); if (!buf) buf = ERR_PTR(-ENOMEM); @@ -1071,30 +1073,6 @@ int gfs2_permission(struct inode *inode, int mask) return error; } -/* - * XXX(truncate): the truncate_setsize calls should be moved to the end. - */ -static int setattr_size(struct inode *inode, struct iattr *attr) -{ - struct gfs2_inode *ip = GFS2_I(inode); - struct gfs2_sbd *sdp = GFS2_SB(inode); - int error; - - if (attr->ia_size != ip->i_disksize) { - error = gfs2_trans_begin(sdp, 0, sdp->sd_jdesc->jd_blocks); - if (error) - return error; - truncate_setsize(inode, attr->ia_size); - gfs2_trans_end(sdp); - } - - error = gfs2_truncatei(ip, attr->ia_size); - if (error && (inode->i_size != ip->i_disksize)) - i_size_write(inode, ip->i_disksize); - - return error; -} - static int setattr_chown(struct inode *inode, struct iattr *attr) { struct gfs2_inode *ip = GFS2_I(inode); @@ -1195,7 +1173,7 @@ static int gfs2_setattr(struct dentry *dentry, struct iattr *attr) goto out; if (attr->ia_valid & ATTR_SIZE) - error = setattr_size(inode, attr); + error = gfs2_setattr_size(inode, attr->ia_size); else if (attr->ia_valid & (ATTR_UID | ATTR_GID)) error = setattr_chown(inode, attr); else if ((attr->ia_valid & ATTR_MODE) && IS_POSIXACL(inode)) @@ -1301,6 +1279,257 @@ static int gfs2_removexattr(struct dentry *dentry, const char *name) return ret; } +static void empty_write_end(struct page *page, unsigned from, + unsigned to) +{ + struct gfs2_inode *ip = GFS2_I(page->mapping->host); + + page_zero_new_buffers(page, from, to); + flush_dcache_page(page); + mark_page_accessed(page); + + if (!gfs2_is_writeback(ip)) + gfs2_page_add_databufs(ip, page, from, to); + + block_commit_write(page, from, to); +} + + +static int write_empty_blocks(struct page *page, unsigned from, unsigned to) +{ + unsigned start, end, next; + struct buffer_head *bh, *head; + int error; + + if (!page_has_buffers(page)) { + error = block_prepare_write(page, from, to, gfs2_block_map); + if (unlikely(error)) + return error; + + empty_write_end(page, from, to); + return 0; + } + + bh = head = page_buffers(page); + next = end = 0; + while (next < from) { + next += bh->b_size; + bh = bh->b_this_page; + } + start = next; + do { + next += bh->b_size; + if (buffer_mapped(bh)) { + if (end) { + error = block_prepare_write(page, start, end, + gfs2_block_map); + if (unlikely(error)) + return error; + empty_write_end(page, start, end); + end = 0; + } + start = next; + } + else + end = next; + bh = bh->b_this_page; + } while (next < to); + + if (end) { + error = block_prepare_write(page, start, end, gfs2_block_map); + if (unlikely(error)) + return error; + empty_write_end(page, start, end); + } + + return 0; +} + +static int fallocate_chunk(struct inode *inode, loff_t offset, loff_t len, + int mode) +{ + struct gfs2_inode *ip = GFS2_I(inode); + struct buffer_head *dibh; + int error; + u64 start = offset >> PAGE_CACHE_SHIFT; + unsigned int start_offset = offset & ~PAGE_CACHE_MASK; + u64 end = (offset + len - 1) >> PAGE_CACHE_SHIFT; + pgoff_t curr; + struct page *page; + unsigned int end_offset = (offset + len) & ~PAGE_CACHE_MASK; + unsigned int from, to; + + if (!end_offset) + end_offset = PAGE_CACHE_SIZE; + + error = gfs2_meta_inode_buffer(ip, &dibh); + if (unlikely(error)) + goto out; + + gfs2_trans_add_bh(ip->i_gl, dibh, 1); + + if (gfs2_is_stuffed(ip)) { + error = gfs2_unstuff_dinode(ip, NULL); + if (unlikely(error)) + goto out; + } + + curr = start; + offset = start << PAGE_CACHE_SHIFT; + from = start_offset; + to = PAGE_CACHE_SIZE; + while (curr <= end) { + page = grab_cache_page_write_begin(inode->i_mapping, curr, + AOP_FLAG_NOFS); + if (unlikely(!page)) { + error = -ENOMEM; + goto out; + } + + if (curr == end) + to = end_offset; + error = write_empty_blocks(page, from, to); + if (!error && offset + to > inode->i_size && + !(mode & FALLOC_FL_KEEP_SIZE)) { + i_size_write(inode, offset + to); + } + unlock_page(page); + page_cache_release(page); + if (error) + goto out; + curr++; + offset += PAGE_CACHE_SIZE; + from = 0; + } + + gfs2_dinode_out(ip, dibh->b_data); + mark_inode_dirty(inode); + + brelse(dibh); + +out: + return error; +} + +static void calc_max_reserv(struct gfs2_inode *ip, loff_t max, loff_t *len, + unsigned int *data_blocks, unsigned int *ind_blocks) +{ + const struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); + unsigned int max_blocks = ip->i_alloc->al_rgd->rd_free_clone; + unsigned int tmp, max_data = max_blocks - 3 * (sdp->sd_max_height - 1); + + for (tmp = max_data; tmp > sdp->sd_diptrs;) { + tmp = DIV_ROUND_UP(tmp, sdp->sd_inptrs); + max_data -= tmp; + } + /* This calculation isn't the exact reverse of gfs2_write_calc_reserve, + so it might end up with fewer data blocks */ + if (max_data <= *data_blocks) + return; + *data_blocks = max_data; + *ind_blocks = max_blocks - max_data; + *len = ((loff_t)max_data - 3) << sdp->sd_sb.sb_bsize_shift; + if (*len > max) { + *len = max; + gfs2_write_calc_reserv(ip, max, data_blocks, ind_blocks); + } +} + +static long gfs2_fallocate(struct inode *inode, int mode, loff_t offset, + loff_t len) +{ + struct gfs2_sbd *sdp = GFS2_SB(inode); + struct gfs2_inode *ip = GFS2_I(inode); + unsigned int data_blocks = 0, ind_blocks = 0, rblocks; + loff_t bytes, max_bytes; + struct gfs2_alloc *al; + int error; + loff_t next = (offset + len - 1) >> sdp->sd_sb.sb_bsize_shift; + next = (next + 1) << sdp->sd_sb.sb_bsize_shift; + + offset = (offset >> sdp->sd_sb.sb_bsize_shift) << + sdp->sd_sb.sb_bsize_shift; + + len = next - offset; + bytes = sdp->sd_max_rg_data * sdp->sd_sb.sb_bsize / 2; + if (!bytes) + bytes = UINT_MAX; + + gfs2_holder_init(ip->i_gl, LM_ST_EXCLUSIVE, 0, &ip->i_gh); + error = gfs2_glock_nq(&ip->i_gh); + if (unlikely(error)) + goto out_uninit; + + if (!gfs2_write_alloc_required(ip, offset, len)) + goto out_unlock; + + while (len > 0) { + if (len < bytes) + bytes = len; + al = gfs2_alloc_get(ip); + if (!al) { + error = -ENOMEM; + goto out_unlock; + } + + error = gfs2_quota_lock_check(ip); + if (error) + goto out_alloc_put; + +retry: + gfs2_write_calc_reserv(ip, bytes, &data_blocks, &ind_blocks); + + al->al_requested = data_blocks + ind_blocks; + error = gfs2_inplace_reserve(ip); + if (error) { + if (error == -ENOSPC && bytes > sdp->sd_sb.sb_bsize) { + bytes >>= 1; + goto retry; + } + goto out_qunlock; + } + max_bytes = bytes; + calc_max_reserv(ip, len, &max_bytes, &data_blocks, &ind_blocks); + al->al_requested = data_blocks + ind_blocks; + + rblocks = RES_DINODE + ind_blocks + RES_STATFS + RES_QUOTA + + RES_RG_HDR + ip->i_alloc->al_rgd->rd_length; + if (gfs2_is_jdata(ip)) + rblocks += data_blocks ? data_blocks : 1; + + error = gfs2_trans_begin(sdp, rblocks, + PAGE_CACHE_SIZE/sdp->sd_sb.sb_bsize); + if (error) + goto out_trans_fail; + + error = fallocate_chunk(inode, offset, max_bytes, mode); + gfs2_trans_end(sdp); + + if (error) + goto out_trans_fail; + + len -= max_bytes; + offset += max_bytes; + gfs2_inplace_release(ip); + gfs2_quota_unlock(ip); + gfs2_alloc_put(ip); + } + goto out_unlock; + +out_trans_fail: + gfs2_inplace_release(ip); +out_qunlock: + gfs2_quota_unlock(ip); +out_alloc_put: + gfs2_alloc_put(ip); +out_unlock: + gfs2_glock_dq(&ip->i_gh); +out_uninit: + gfs2_holder_uninit(&ip->i_gh); + return error; +} + + static int gfs2_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo, u64 start, u64 len) { @@ -1351,6 +1580,7 @@ const struct inode_operations gfs2_file_iops = { .getxattr = gfs2_getxattr, .listxattr = gfs2_listxattr, .removexattr = gfs2_removexattr, + .fallocate = gfs2_fallocate, .fiemap = gfs2_fiemap, }; diff --git a/fs/gfs2/quota.c b/fs/gfs2/quota.c index 1bc6b5695e6d..9bc6dd9a5443 100644 --- a/fs/gfs2/quota.c +++ b/fs/gfs2/quota.c @@ -735,10 +735,8 @@ get_a_page: goto out; size = loc + sizeof(struct gfs2_quota); - if (size > inode->i_size) { - ip->i_disksize = size; + if (size > inode->i_size) i_size_write(inode, size); - } inode->i_mtime = inode->i_atime = CURRENT_TIME; gfs2_trans_add_bh(ip->i_gl, dibh, 1); gfs2_dinode_out(ip, dibh->b_data); @@ -1190,18 +1188,17 @@ static void gfs2_quota_change_in(struct gfs2_quota_change_host *qc, const void * int gfs2_quota_init(struct gfs2_sbd *sdp) { struct gfs2_inode *ip = GFS2_I(sdp->sd_qc_inode); - unsigned int blocks = ip->i_disksize >> sdp->sd_sb.sb_bsize_shift; + u64 size = i_size_read(sdp->sd_qc_inode); + unsigned int blocks = size >> sdp->sd_sb.sb_bsize_shift; unsigned int x, slot = 0; unsigned int found = 0; u64 dblock; u32 extlen = 0; int error; - if (!ip->i_disksize || ip->i_disksize > (64 << 20) || - ip->i_disksize & (sdp->sd_sb.sb_bsize - 1)) { - gfs2_consist_inode(ip); + if (gfs2_check_internal_file_size(sdp->sd_qc_inode, 1, 64 << 20)) return -EIO; - } + sdp->sd_quota_slots = blocks * sdp->sd_qc_per_block; sdp->sd_quota_chunks = DIV_ROUND_UP(sdp->sd_quota_slots, 8 * PAGE_SIZE); diff --git a/fs/gfs2/rgrp.c b/fs/gfs2/rgrp.c index 171a744f8e45..f9ddcf401753 100644 --- a/fs/gfs2/rgrp.c +++ b/fs/gfs2/rgrp.c @@ -500,7 +500,7 @@ u64 gfs2_ri_total(struct gfs2_sbd *sdp) for (rgrps = 0;; rgrps++) { loff_t pos = rgrps * sizeof(struct gfs2_rindex); - if (pos + sizeof(struct gfs2_rindex) >= ip->i_disksize) + if (pos + sizeof(struct gfs2_rindex) >= i_size_read(inode)) break; error = gfs2_internal_read(ip, &ra_state, buf, &pos, sizeof(struct gfs2_rindex)); @@ -588,7 +588,9 @@ static int gfs2_ri_update(struct gfs2_inode *ip) struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); struct inode *inode = &ip->i_inode; struct file_ra_state ra_state; - u64 rgrp_count = ip->i_disksize; + u64 rgrp_count = i_size_read(inode); + struct gfs2_rgrpd *rgd; + unsigned int max_data = 0; int error; do_div(rgrp_count, sizeof(struct gfs2_rindex)); @@ -603,6 +605,10 @@ static int gfs2_ri_update(struct gfs2_inode *ip) } } + list_for_each_entry(rgd, &sdp->sd_rindex_list, rd_list) + if (rgd->rd_data > max_data) + max_data = rgd->rd_data; + sdp->sd_max_rg_data = max_data; sdp->sd_rindex_uptodate = 1; return 0; } @@ -622,13 +628,15 @@ static int gfs2_ri_update_special(struct gfs2_inode *ip) struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); struct inode *inode = &ip->i_inode; struct file_ra_state ra_state; + struct gfs2_rgrpd *rgd; + unsigned int max_data = 0; int error; file_ra_state_init(&ra_state, inode->i_mapping); for (sdp->sd_rgrps = 0;; sdp->sd_rgrps++) { /* Ignore partials */ if ((sdp->sd_rgrps + 1) * sizeof(struct gfs2_rindex) > - ip->i_disksize) + i_size_read(inode)) break; error = read_rindex_entry(ip, &ra_state); if (error) { @@ -636,6 +644,10 @@ static int gfs2_ri_update_special(struct gfs2_inode *ip) return error; } } + list_for_each_entry(rgd, &sdp->sd_rindex_list, rd_list) + if (rgd->rd_data > max_data) + max_data = rgd->rd_data; + sdp->sd_max_rg_data = max_data; sdp->sd_rindex_uptodate = 1; return 0; @@ -1496,11 +1508,19 @@ int gfs2_alloc_block(struct gfs2_inode *ip, u64 *bn, unsigned int *n) struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); struct buffer_head *dibh; struct gfs2_alloc *al = ip->i_alloc; - struct gfs2_rgrpd *rgd = al->al_rgd; + struct gfs2_rgrpd *rgd; u32 goal, blk; u64 block; int error; + /* Only happens if there is a bug in gfs2, return something distinctive + * to ensure that it is noticed. + */ + if (al == NULL) + return -ECANCELED; + + rgd = al->al_rgd; + if (rgrp_contains_block(rgd, ip->i_goal)) goal = ip->i_goal - rgd->rd_data0; else diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c index 77cb9f830ee4..e031fa4965a3 100644 --- a/fs/gfs2/super.c +++ b/fs/gfs2/super.c @@ -342,15 +342,14 @@ int gfs2_jdesc_check(struct gfs2_jdesc *jd) { struct gfs2_inode *ip = GFS2_I(jd->jd_inode); struct gfs2_sbd *sdp = GFS2_SB(jd->jd_inode); + u64 size = i_size_read(jd->jd_inode); - if (ip->i_disksize < (8 << 20) || ip->i_disksize > (1 << 30) || - (ip->i_disksize & (sdp->sd_sb.sb_bsize - 1))) { - gfs2_consist_inode(ip); + if (gfs2_check_internal_file_size(jd->jd_inode, 8 << 20, 1 << 30)) return -EIO; - } - jd->jd_blocks = ip->i_disksize >> sdp->sd_sb.sb_bsize_shift; - if (gfs2_write_alloc_required(ip, 0, ip->i_disksize)) { + jd->jd_blocks = size >> sdp->sd_sb.sb_bsize_shift; + + if (gfs2_write_alloc_required(ip, 0, size)) { gfs2_consist_inode(ip); return -EIO; } diff --git a/fs/gfs2/trans.h b/fs/gfs2/trans.h index edf9d4bd908e..b849eb7ad37d 100644 --- a/fs/gfs2/trans.h +++ b/fs/gfs2/trans.h @@ -20,6 +20,7 @@ struct gfs2_glock; #define RES_JDATA 1 #define RES_DATA 1 #define RES_LEAF 1 +#define RES_RG_HDR 1 #define RES_RG_BIT 2 #define RES_EATTR 1 #define RES_STATFS 1 diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c index 0e8014ea6b94..262419f83d80 100644 --- a/fs/jbd2/journal.c +++ b/fs/jbd2/journal.c @@ -1371,6 +1371,10 @@ int jbd2_journal_check_used_features (journal_t *journal, unsigned long compat, if (!compat && !ro && !incompat) return 1; + /* Load journal superblock if it is not loaded yet. */ + if (journal->j_format_version == 0 && + journal_get_superblock(journal) != 0) + return 0; if (journal->j_format_version == 1) return 0; diff --git a/fs/libfs.c b/fs/libfs.c index 0a9da95317f7..62baa0387d6e 100644 --- a/fs/libfs.c +++ b/fs/libfs.c @@ -913,6 +913,35 @@ int generic_file_fsync(struct file *file, int datasync) } EXPORT_SYMBOL(generic_file_fsync); +/** + * generic_check_addressable - Check addressability of file system + * @blocksize_bits: log of file system block size + * @num_blocks: number of blocks in file system + * + * Determine whether a file system with @num_blocks blocks (and a + * block size of 2**@blocksize_bits) is addressable by the sector_t + * and page cache of the system. Return 0 if so and -EFBIG otherwise. + */ +int generic_check_addressable(unsigned blocksize_bits, u64 num_blocks) +{ + u64 last_fs_block = num_blocks - 1; + u64 last_fs_page = + last_fs_block >> (PAGE_CACHE_SHIFT - blocksize_bits); + + if (unlikely(num_blocks == 0)) + return 0; + + if ((blocksize_bits < 9) || (blocksize_bits > PAGE_CACHE_SHIFT)) + return -EINVAL; + + if ((last_fs_block > (sector_t)(~0ULL) >> (blocksize_bits - 9)) || + (last_fs_page > (pgoff_t)(~0ULL))) { + return -EFBIG; + } + return 0; +} +EXPORT_SYMBOL(generic_check_addressable); + /* * No-op implementation of ->fsync for in-memory filesystems. */ diff --git a/fs/nilfs2/gcinode.c b/fs/nilfs2/gcinode.c index bed3a783129b..34f8f84a22e3 100644 --- a/fs/nilfs2/gcinode.c +++ b/fs/nilfs2/gcinode.c @@ -28,13 +28,6 @@ * gcinodes), and this file provides lookup function of the dummy * inodes and their buffer read function. * - * Since NILFS2 keeps up multiple checkpoints/snapshots across GC, it - * has to treat blocks that belong to a same file but have different - * checkpoint numbers. To avoid interference among generations, dummy - * inodes are managed separately from actual inodes, and their lookup - * function (nilfs_gc_iget) is designed to be specified with a - * checkpoint number argument as well as an inode number. - * * Buffers and pages held by the dummy inodes will be released each * time after they are copied to a new log. Dirty blocks made on the * current generation and the blocks to be moved by GC never overlap @@ -180,120 +173,41 @@ int nilfs_gccache_wait_and_mark_dirty(struct buffer_head *bh) return 0; } -/* - * nilfs_init_gccache() - allocate and initialize gc_inode hash table - * @nilfs - the_nilfs - * - * Return Value: On success, 0. - * On error, a negative error code is returned. - */ -int nilfs_init_gccache(struct the_nilfs *nilfs) -{ - int loop; - - BUG_ON(nilfs->ns_gc_inodes_h); - - INIT_LIST_HEAD(&nilfs->ns_gc_inodes); - - nilfs->ns_gc_inodes_h = - kmalloc(sizeof(struct hlist_head) * NILFS_GCINODE_HASH_SIZE, - GFP_NOFS); - if (nilfs->ns_gc_inodes_h == NULL) - return -ENOMEM; - - for (loop = 0; loop < NILFS_GCINODE_HASH_SIZE; loop++) - INIT_HLIST_HEAD(&nilfs->ns_gc_inodes_h[loop]); - return 0; -} - -/* - * nilfs_destroy_gccache() - free gc_inode hash table - * @nilfs - the nilfs - */ -void nilfs_destroy_gccache(struct the_nilfs *nilfs) -{ - if (nilfs->ns_gc_inodes_h) { - nilfs_remove_all_gcinode(nilfs); - kfree(nilfs->ns_gc_inodes_h); - nilfs->ns_gc_inodes_h = NULL; - } -} - -static struct inode *alloc_gcinode(struct the_nilfs *nilfs, ino_t ino, - __u64 cno) -{ - struct inode *inode; - struct nilfs_inode_info *ii; - - inode = nilfs_mdt_new_common(nilfs, NULL, ino, GFP_NOFS, 0); - if (!inode) - return NULL; - - inode->i_op = NULL; - inode->i_fop = NULL; - inode->i_mapping->a_ops = &def_gcinode_aops; - - ii = NILFS_I(inode); - ii->i_cno = cno; - ii->i_flags = 0; - ii->i_state = 1 << NILFS_I_GCINODE; - ii->i_bh = NULL; - nilfs_bmap_init_gc(ii->i_bmap); - - return inode; -} - -static unsigned long ihash(ino_t ino, __u64 cno) +int nilfs_init_gcinode(struct inode *inode) { - return hash_long((unsigned long)((ino << 2) + cno), - NILFS_GCINODE_HASH_BITS); -} + struct nilfs_inode_info *ii = NILFS_I(inode); + struct the_nilfs *nilfs = NILFS_SB(inode->i_sb)->s_nilfs; + int ret; -/* - * nilfs_gc_iget() - find or create gc inode with specified (ino,cno) - */ -struct inode *nilfs_gc_iget(struct the_nilfs *nilfs, ino_t ino, __u64 cno) -{ - struct hlist_head *head = nilfs->ns_gc_inodes_h + ihash(ino, cno); - struct hlist_node *node; - struct inode *inode; + ret = nilfs_mdt_init(inode, nilfs, GFP_NOFS, 0); + if (!ret) { + inode->i_mapping->a_ops = &def_gcinode_aops; - hlist_for_each_entry(inode, node, head, i_hash) { - if (inode->i_ino == ino && NILFS_I(inode)->i_cno == cno) - return inode; - } + ii->i_flags = 0; + nilfs_bmap_init_gc(ii->i_bmap); - inode = alloc_gcinode(nilfs, ino, cno); - if (likely(inode)) { - hlist_add_head(&inode->i_hash, head); + /* + * Add the inode to GC inode list. Garbage Collection + * is serialized and no two processes manipulate the + * list simultaneously. + */ + igrab(inode); list_add(&NILFS_I(inode)->i_dirty, &nilfs->ns_gc_inodes); } - return inode; -} - -/* - * nilfs_clear_gcinode() - clear and free a gc inode - */ -void nilfs_clear_gcinode(struct inode *inode) -{ - nilfs_mdt_destroy(inode); + return ret; } -/* - * nilfs_remove_all_gcinode() - remove all inodes from the_nilfs +/** + * nilfs_remove_all_gcinodes() - remove all unprocessed gc inodes */ -void nilfs_remove_all_gcinode(struct the_nilfs *nilfs) +void nilfs_remove_all_gcinodes(struct the_nilfs *nilfs) { - struct hlist_head *head = nilfs->ns_gc_inodes_h; - struct hlist_node *node, *n; - struct inode *inode; - int loop; + struct list_head *head = &nilfs->ns_gc_inodes; + struct nilfs_inode_info *ii; - for (loop = 0; loop < NILFS_GCINODE_HASH_SIZE; loop++, head++) { - hlist_for_each_entry_safe(inode, node, n, head, i_hash) { - hlist_del_init(&inode->i_hash); - list_del_init(&NILFS_I(inode)->i_dirty); - nilfs_clear_gcinode(inode); /* might sleep */ - } + while (!list_empty(head)) { + ii = list_first_entry(head, struct nilfs_inode_info, i_dirty); + list_del_init(&ii->i_dirty); + iput(&ii->vfs_inode); } } diff --git a/fs/nilfs2/inode.c b/fs/nilfs2/inode.c index eccb2f2e2315..82cfdbc43e1c 100644 --- a/fs/nilfs2/inode.c +++ b/fs/nilfs2/inode.c @@ -34,6 +34,11 @@ #include "cpfile.h" #include "ifile.h" +struct nilfs_iget_args { + u64 ino; + __u64 cno; + int for_gc; +}; /** * nilfs_get_block() - get a file block on the filesystem (callback function) @@ -320,7 +325,6 @@ struct inode *nilfs_new_inode(struct inode *dir, int mode) /* ii->i_file_acl = 0; */ /* ii->i_dir_acl = 0; */ ii->i_dir_start_lookup = 0; - ii->i_cno = 0; nilfs_set_inode_flags(inode); spin_lock(&sbi->s_next_gen_lock); inode->i_generation = sbi->s_next_generation++; @@ -410,7 +414,6 @@ int nilfs_read_inode_common(struct inode *inode, 0 : le32_to_cpu(raw_inode->i_dir_acl); #endif ii->i_dir_start_lookup = 0; - ii->i_cno = 0; inode->i_generation = le32_to_cpu(raw_inode->i_generation); if (S_ISREG(inode->i_mode) || S_ISDIR(inode->i_mode) || @@ -476,12 +479,40 @@ static int __nilfs_read_inode(struct super_block *sb, unsigned long ino, return err; } +static int nilfs_iget_test(struct inode *inode, void *opaque) +{ + struct nilfs_iget_args *args = opaque; + struct nilfs_inode_info *ii; + + if (args->ino != inode->i_ino) + return 0; + + ii = NILFS_I(inode); + if (!test_bit(NILFS_I_GCINODE, &ii->i_state)) + return !args->for_gc; + + return args->for_gc && args->cno == ii->i_cno; +} + +static int nilfs_iget_set(struct inode *inode, void *opaque) +{ + struct nilfs_iget_args *args = opaque; + + inode->i_ino = args->ino; + if (args->for_gc) { + NILFS_I(inode)->i_state = 1 << NILFS_I_GCINODE; + NILFS_I(inode)->i_cno = args->cno; + } + return 0; +} + struct inode *nilfs_iget(struct super_block *sb, unsigned long ino) { + struct nilfs_iget_args args = { .ino = ino, .cno = 0, .for_gc = 0 }; struct inode *inode; int err; - inode = iget_locked(sb, ino); + inode = iget5_locked(sb, ino, nilfs_iget_test, nilfs_iget_set, &args); if (unlikely(!inode)) return ERR_PTR(-ENOMEM); if (!(inode->i_state & I_NEW)) @@ -496,6 +527,28 @@ struct inode *nilfs_iget(struct super_block *sb, unsigned long ino) return inode; } +struct inode *nilfs_iget_for_gc(struct super_block *sb, unsigned long ino, + __u64 cno) +{ + struct nilfs_iget_args args = { .ino = ino, .cno = cno, .for_gc = 1 }; + struct inode *inode; + int err; + + inode = iget5_locked(sb, ino, nilfs_iget_test, nilfs_iget_set, &args); + if (unlikely(!inode)) + return ERR_PTR(-ENOMEM); + if (!(inode->i_state & I_NEW)) + return inode; + + err = nilfs_init_gcinode(inode); + if (unlikely(err)) { + iget_failed(inode); + return ERR_PTR(err); + } + unlock_new_inode(inode); + return inode; +} + void nilfs_write_inode_common(struct inode *inode, struct nilfs_inode *raw_inode, int has_bmap) { @@ -808,6 +861,7 @@ int nilfs_mark_inode_dirty(struct inode *inode) void nilfs_dirty_inode(struct inode *inode) { struct nilfs_transaction_info ti; + struct nilfs_mdt_info *mdi = NILFS_MDT(inode); if (is_bad_inode(inode)) { nilfs_warning(inode->i_sb, __func__, @@ -815,6 +869,10 @@ void nilfs_dirty_inode(struct inode *inode) dump_stack(); return; } + if (mdi) { + nilfs_mdt_mark_dirty(inode); + return; + } nilfs_transaction_begin(inode->i_sb, &ti, 0); nilfs_mark_inode_dirty(inode); nilfs_transaction_commit(inode->i_sb); /* never fails */ diff --git a/fs/nilfs2/ioctl.c b/fs/nilfs2/ioctl.c index f90a33d9a5b0..f0a99bdb10f5 100644 --- a/fs/nilfs2/ioctl.c +++ b/fs/nilfs2/ioctl.c @@ -334,7 +334,7 @@ static int nilfs_ioctl_move_inode_block(struct inode *inode, return 0; } -static int nilfs_ioctl_move_blocks(struct the_nilfs *nilfs, +static int nilfs_ioctl_move_blocks(struct super_block *sb, struct nilfs_argv *argv, void *buf) { size_t nmembs = argv->v_nmembs; @@ -349,7 +349,7 @@ static int nilfs_ioctl_move_blocks(struct the_nilfs *nilfs, for (i = 0, vdesc = buf; i < nmembs; ) { ino = vdesc->vd_ino; cno = vdesc->vd_cno; - inode = nilfs_gc_iget(nilfs, ino, cno); + inode = nilfs_iget_for_gc(sb, ino, cno); if (unlikely(inode == NULL)) { ret = -ENOMEM; goto failed; @@ -357,11 +357,15 @@ static int nilfs_ioctl_move_blocks(struct the_nilfs *nilfs, do { ret = nilfs_ioctl_move_inode_block(inode, vdesc, &buffers); - if (unlikely(ret < 0)) + if (unlikely(ret < 0)) { + iput(inode); goto failed; + } vdesc++; } while (++i < nmembs && vdesc->vd_ino == ino && vdesc->vd_cno == cno); + + iput(inode); /* The inode still remains in GC inode list */ } list_for_each_entry_safe(bh, n, &buffers, b_assoc_buffers) { @@ -567,7 +571,7 @@ static int nilfs_ioctl_clean_segments(struct inode *inode, struct file *filp, } /* - * nilfs_ioctl_move_blocks() will call nilfs_gc_iget(), + * nilfs_ioctl_move_blocks() will call nilfs_iget_for_gc(), * which will operates an inode list without blocking. * To protect the list from concurrent operations, * nilfs_ioctl_move_blocks should be atomic operation. @@ -577,15 +581,14 @@ static int nilfs_ioctl_clean_segments(struct inode *inode, struct file *filp, goto out_free; } - ret = nilfs_ioctl_move_blocks(nilfs, &argv[0], kbufs[0]); + ret = nilfs_ioctl_move_blocks(inode->i_sb, &argv[0], kbufs[0]); if (ret < 0) printk(KERN_ERR "NILFS: GC failed during preparation: " "cannot read source blocks: err=%d\n", ret); else ret = nilfs_clean_segments(inode->i_sb, argv, kbufs); - if (ret < 0) - nilfs_remove_all_gcinode(nilfs); + nilfs_remove_all_gcinodes(nilfs); clear_nilfs_gc_running(nilfs); out_free: diff --git a/fs/nilfs2/mdt.c b/fs/nilfs2/mdt.c index d01aff4957d9..73e5da3b097e 100644 --- a/fs/nilfs2/mdt.c +++ b/fs/nilfs2/mdt.c @@ -439,6 +439,27 @@ static const struct address_space_operations def_mdt_aops = { static const struct inode_operations def_mdt_iops; static const struct file_operations def_mdt_fops; + +int nilfs_mdt_init(struct inode *inode, struct the_nilfs *nilfs, + gfp_t gfp_mask, size_t objsz) +{ + struct nilfs_mdt_info *mi; + + mi = kzalloc(max(sizeof(*mi), objsz), GFP_NOFS); + if (!mi) + return -ENOMEM; + + mi->mi_nilfs = nilfs; + init_rwsem(&mi->mi_sem); + inode->i_private = mi; + + inode->i_mode = S_IFREG; + mapping_set_gfp_mask(inode->i_mapping, gfp_mask); + inode->i_mapping->backing_dev_info = nilfs->ns_bdi; + + return 0; +} + /* * NILFS2 uses pseudo inodes for meta data files such as DAT, cpfile, sufile, * ifile, or gcinodes. This allows the B-tree code and segment constructor @@ -454,12 +475,10 @@ static const struct file_operations def_mdt_fops; * @nilfs: nilfs object * @sb: super block instance the metadata file belongs to * @ino: inode number - * @gfp_mask: gfp mask for data pages - * @objsz: size of the private object attached to inode->i_private */ struct inode * nilfs_mdt_new_common(struct the_nilfs *nilfs, struct super_block *sb, - ino_t ino, gfp_t gfp_mask, size_t objsz) + ino_t ino) { struct inode *inode = nilfs_alloc_inode_common(nilfs); @@ -467,15 +486,6 @@ nilfs_mdt_new_common(struct the_nilfs *nilfs, struct super_block *sb, return NULL; else { struct address_space * const mapping = &inode->i_data; - struct nilfs_mdt_info *mi; - - mi = kzalloc(max(sizeof(*mi), objsz), GFP_NOFS); - if (!mi) { - nilfs_destroy_inode(inode); - return NULL; - } - mi->mi_nilfs = nilfs; - init_rwsem(&mi->mi_sem); inode->i_sb = sb; /* sb may be NULL for some meta data files */ inode->i_blkbits = nilfs->ns_blocksize_bits; @@ -483,8 +493,6 @@ nilfs_mdt_new_common(struct the_nilfs *nilfs, struct super_block *sb, atomic_set(&inode->i_count, 1); inode->i_nlink = 1; inode->i_ino = ino; - inode->i_mode = S_IFREG; - inode->i_private = mi; #ifdef INIT_UNUSED_INODE_FIELDS atomic_set(&inode->i_writecount, 0); @@ -515,9 +523,7 @@ nilfs_mdt_new_common(struct the_nilfs *nilfs, struct super_block *sb, mapping->host = NULL; /* instead of inode */ mapping->flags = 0; - mapping_set_gfp_mask(mapping, gfp_mask); mapping->assoc_mapping = NULL; - mapping->backing_dev_info = nilfs->ns_bdi; inode->i_mapping = mapping; } @@ -530,10 +536,14 @@ struct inode *nilfs_mdt_new(struct the_nilfs *nilfs, struct super_block *sb, { struct inode *inode; - inode = nilfs_mdt_new_common(nilfs, sb, ino, NILFS_MDT_GFP, objsz); + inode = nilfs_mdt_new_common(nilfs, sb, ino); if (!inode) return NULL; + if (nilfs_mdt_init(inode, nilfs, NILFS_MDT_GFP, objsz) < 0) { + nilfs_destroy_inode(inode); + return NULL; + } inode->i_op = &def_mdt_iops; inode->i_fop = &def_mdt_fops; inode->i_mapping->a_ops = &def_mdt_aops; @@ -577,7 +587,5 @@ void nilfs_mdt_destroy(struct inode *inode) nilfs_palloc_destroy_cache(inode); nilfs_mdt_clear(inode); - kfree(mdi->mi_bgl); /* kfree(NULL) is safe */ - kfree(mdi); nilfs_destroy_inode(inode); } diff --git a/fs/nilfs2/mdt.h b/fs/nilfs2/mdt.h index 6c4bbb0470fc..f44560224bd1 100644 --- a/fs/nilfs2/mdt.h +++ b/fs/nilfs2/mdt.h @@ -76,10 +76,12 @@ int nilfs_mdt_forget_block(struct inode *, unsigned long); int nilfs_mdt_mark_block_dirty(struct inode *, unsigned long); int nilfs_mdt_fetch_dirty(struct inode *); +int nilfs_mdt_init(struct inode *inode, struct the_nilfs *nilfs, + gfp_t gfp_mask, size_t objsz); struct inode *nilfs_mdt_new(struct the_nilfs *, struct super_block *, ino_t, size_t); struct inode *nilfs_mdt_new_common(struct the_nilfs *, struct super_block *, - ino_t, gfp_t, size_t); + ino_t); void nilfs_mdt_destroy(struct inode *); void nilfs_mdt_set_entry_size(struct inode *, unsigned, unsigned); void nilfs_mdt_set_shadow(struct inode *, struct inode *); diff --git a/fs/nilfs2/nilfs.h b/fs/nilfs2/nilfs.h index d3d54046e5f8..797cd437970e 100644 --- a/fs/nilfs2/nilfs.h +++ b/fs/nilfs2/nilfs.h @@ -248,6 +248,8 @@ extern void nilfs_set_inode_flags(struct inode *); extern int nilfs_read_inode_common(struct inode *, struct nilfs_inode *); extern void nilfs_write_inode_common(struct inode *, struct nilfs_inode *, int); extern struct inode *nilfs_iget(struct super_block *, unsigned long); +extern struct inode *nilfs_iget_for_gc(struct super_block *sb, + unsigned long ino, __u64 cno); extern void nilfs_update_inode(struct inode *, struct buffer_head *); extern void nilfs_truncate(struct inode *); extern void nilfs_evict_inode(struct inode *); @@ -292,11 +294,8 @@ int nilfs_gccache_submit_read_data(struct inode *, sector_t, sector_t, __u64, int nilfs_gccache_submit_read_node(struct inode *, sector_t, __u64, struct buffer_head **); int nilfs_gccache_wait_and_mark_dirty(struct buffer_head *); -int nilfs_init_gccache(struct the_nilfs *); -void nilfs_destroy_gccache(struct the_nilfs *); -void nilfs_clear_gcinode(struct inode *); -struct inode *nilfs_gc_iget(struct the_nilfs *, ino_t, __u64); -void nilfs_remove_all_gcinode(struct the_nilfs *); +int nilfs_init_gcinode(struct inode *inode); +void nilfs_remove_all_gcinodes(struct the_nilfs *nilfs); /* gcdat.c */ int nilfs_init_gcdat_inode(struct the_nilfs *); diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c index 9fd051a33c4f..9cf71389f369 100644 --- a/fs/nilfs2/segment.c +++ b/fs/nilfs2/segment.c @@ -366,8 +366,7 @@ static int nilfs_segctor_reset_segment_buffer(struct nilfs_sc_info *sci) if (nilfs_doing_gc()) flags = NILFS_SS_GC; - err = nilfs_segbuf_reset(segbuf, flags, sci->sc_seg_ctime, - sci->sc_sbi->s_nilfs->ns_cno); + err = nilfs_segbuf_reset(segbuf, flags, sci->sc_seg_ctime, sci->sc_cno); if (unlikely(err)) return err; @@ -440,17 +439,26 @@ static void nilfs_segctor_end_finfo(struct nilfs_sc_info *sci, struct nilfs_finfo *finfo; struct nilfs_inode_info *ii; struct nilfs_segment_buffer *segbuf; + __u64 cno; if (sci->sc_blk_cnt == 0) return; ii = NILFS_I(inode); + + if (test_bit(NILFS_I_GCINODE, &ii->i_state)) + cno = ii->i_cno; + else if (NILFS_ROOT_METADATA_FILE(inode->i_ino)) + cno = 0; + else + cno = sci->sc_cno; + finfo = nilfs_segctor_map_segsum_entry(sci, &sci->sc_finfo_ptr, sizeof(*finfo)); finfo->fi_ino = cpu_to_le64(inode->i_ino); finfo->fi_nblocks = cpu_to_le32(sci->sc_blk_cnt); finfo->fi_ndatablk = cpu_to_le32(sci->sc_datablk_cnt); - finfo->fi_cno = cpu_to_le64(ii->i_cno); + finfo->fi_cno = cpu_to_le64(cno); segbuf = sci->sc_curseg; segbuf->sb_sum.sumbytes = sci->sc_binfo_ptr.offset + @@ -1976,7 +1984,6 @@ static int nilfs_segctor_check_in_files(struct nilfs_sc_info *sci, struct nilfs_sb_info *sbi) { struct nilfs_inode_info *ii, *n; - __u64 cno = sbi->s_nilfs->ns_cno; spin_lock(&sbi->s_inode_lock); retry: @@ -2002,7 +2009,6 @@ static int nilfs_segctor_check_in_files(struct nilfs_sc_info *sci, brelse(ibh); goto retry; } - ii->i_cno = cno; clear_bit(NILFS_I_QUEUED, &ii->i_state); set_bit(NILFS_I_BUSY, &ii->i_state); @@ -2011,8 +2017,6 @@ static int nilfs_segctor_check_in_files(struct nilfs_sc_info *sci, } spin_unlock(&sbi->s_inode_lock); - NILFS_I(sbi->s_ifile)->i_cno = cno; - return 0; } @@ -2021,19 +2025,13 @@ static void nilfs_segctor_check_out_files(struct nilfs_sc_info *sci, { struct nilfs_transaction_info *ti = current->journal_info; struct nilfs_inode_info *ii, *n; - __u64 cno = sbi->s_nilfs->ns_cno; spin_lock(&sbi->s_inode_lock); list_for_each_entry_safe(ii, n, &sci->sc_dirty_files, i_dirty) { if (!test_and_clear_bit(NILFS_I_UPDATED, &ii->i_state) || - test_bit(NILFS_I_DIRTY, &ii->i_state)) { - /* The current checkpoint number (=nilfs->ns_cno) is - changed between check-in and check-out only if the - super root is written out. So, we can update i_cno - for the inodes that remain in the dirty list. */ - ii->i_cno = cno; + test_bit(NILFS_I_DIRTY, &ii->i_state)) continue; - } + clear_bit(NILFS_I_BUSY, &ii->i_state); brelse(ii->i_bh); ii->i_bh = NULL; @@ -2054,6 +2052,7 @@ static int nilfs_segctor_do_construct(struct nilfs_sc_info *sci, int mode) int err; sci->sc_stage.scnt = NILFS_ST_INIT; + sci->sc_cno = nilfs->ns_cno; err = nilfs_segctor_check_in_files(sci, sbi); if (unlikely(err)) @@ -2452,9 +2451,8 @@ nilfs_remove_written_gcinodes(struct the_nilfs *nilfs, struct list_head *head) list_for_each_entry_safe(ii, n, head, i_dirty) { if (!test_bit(NILFS_I_UPDATED, &ii->i_state)) continue; - hlist_del_init(&ii->vfs_inode.i_hash); list_del_init(&ii->i_dirty); - nilfs_clear_gcinode(&ii->vfs_inode); + iput(&ii->vfs_inode); } } diff --git a/fs/nilfs2/segment.h b/fs/nilfs2/segment.h index 17c487bd8152..675d932148a4 100644 --- a/fs/nilfs2/segment.h +++ b/fs/nilfs2/segment.h @@ -107,6 +107,7 @@ struct nilfs_segsum_pointer { * @sc_datablk_cnt: Data block count of a file * @sc_nblk_this_inc: Number of blocks included in the current logical segment * @sc_seg_ctime: Creation time + * @sc_cno: checkpoint number of current log * @sc_flags: Internal flags * @sc_state_lock: spinlock for sc_state and so on * @sc_state: Segctord state flags @@ -156,7 +157,7 @@ struct nilfs_sc_info { unsigned long sc_datablk_cnt; unsigned long sc_nblk_this_inc; time_t sc_seg_ctime; - + __u64 sc_cno; unsigned long sc_flags; spinlock_t sc_state_lock; diff --git a/fs/nilfs2/super.c b/fs/nilfs2/super.c index 922263393c76..452004b4050d 100644 --- a/fs/nilfs2/super.c +++ b/fs/nilfs2/super.c @@ -156,6 +156,7 @@ struct inode *nilfs_alloc_inode_common(struct the_nilfs *nilfs) return NULL; ii->i_bh = NULL; ii->i_state = 0; + ii->i_cno = 0; ii->vfs_inode.i_version = 1; nilfs_btnode_cache_init(&ii->i_btnode_cache, nilfs->ns_bdi); return &ii->vfs_inode; @@ -168,6 +169,12 @@ struct inode *nilfs_alloc_inode(struct super_block *sb) void nilfs_destroy_inode(struct inode *inode) { + struct nilfs_mdt_info *mdi = NILFS_MDT(inode); + + if (mdi) { + kfree(mdi->mi_bgl); /* kfree(NULL) is safe */ + kfree(mdi); + } kmem_cache_free(nilfs_inode_cachep, NILFS_I(inode)); } diff --git a/fs/nilfs2/the_nilfs.c b/fs/nilfs2/the_nilfs.c index 4317f177ea7c..6a012b9e1b31 100644 --- a/fs/nilfs2/the_nilfs.c +++ b/fs/nilfs2/the_nilfs.c @@ -87,8 +87,8 @@ static struct the_nilfs *alloc_nilfs(struct block_device *bdev) init_rwsem(&nilfs->ns_writer_sem); INIT_LIST_HEAD(&nilfs->ns_list); INIT_LIST_HEAD(&nilfs->ns_supers); + INIT_LIST_HEAD(&nilfs->ns_gc_inodes); spin_lock_init(&nilfs->ns_last_segment_lock); - nilfs->ns_gc_inodes_h = NULL; init_rwsem(&nilfs->ns_segctor_sem); return nilfs; @@ -164,7 +164,6 @@ void put_nilfs(struct the_nilfs *nilfs) nilfs_mdt_destroy(nilfs->ns_gc_dat); } if (nilfs_init(nilfs)) { - nilfs_destroy_gccache(nilfs); brelse(nilfs->ns_sbh[0]); brelse(nilfs->ns_sbh[1]); } @@ -446,6 +445,7 @@ int load_nilfs(struct the_nilfs *nilfs, struct nilfs_sb_info *sbi) nilfs_mdt_destroy(nilfs->ns_cpfile); nilfs_mdt_destroy(nilfs->ns_sufile); nilfs_mdt_destroy(nilfs->ns_dat); + nilfs_mdt_destroy(nilfs->ns_gc_dat); failed: nilfs_clear_recovery_info(&ri); @@ -467,8 +467,8 @@ static unsigned long long nilfs_max_size(unsigned int blkbits) static int nilfs_store_disk_layout(struct the_nilfs *nilfs, struct nilfs_super_block *sbp) { - if (le32_to_cpu(sbp->s_rev_level) != NILFS_CURRENT_REV) { - printk(KERN_ERR "NILFS: revision mismatch " + if (le32_to_cpu(sbp->s_rev_level) < NILFS_MIN_SUPP_REV) { + printk(KERN_ERR "NILFS: unsupported revision " "(superblock rev.=%d.%d, current rev.=%d.%d). " "Please check the version of mkfs.nilfs.\n", le32_to_cpu(sbp->s_rev_level), @@ -735,11 +735,6 @@ int init_nilfs(struct the_nilfs *nilfs, struct nilfs_sb_info *sbi, char *data) if (err) goto failed_sbh; - /* Initialize gcinode cache */ - err = nilfs_init_gccache(nilfs); - if (err) - goto failed_sbh; - set_nilfs_init(nilfs); err = 0; out: diff --git a/fs/nilfs2/the_nilfs.h b/fs/nilfs2/the_nilfs.h index f785a7b0ab99..c7ecd0c623a3 100644 --- a/fs/nilfs2/the_nilfs.h +++ b/fs/nilfs2/the_nilfs.h @@ -81,7 +81,6 @@ enum { * @ns_sufile: segusage file inode * @ns_gc_dat: shadow inode of the DAT file inode for GC * @ns_gc_inodes: dummy inodes to keep live blocks - * @ns_gc_inodes_h: hash list to keep dummy inode holding live blocks * @ns_blocksize_bits: bit length of block size * @ns_blocksize: block size * @ns_nsegments: number of segments in filesystem @@ -165,9 +164,8 @@ struct the_nilfs { struct inode *ns_sufile; struct inode *ns_gc_dat; - /* GC inode list and hash table head */ + /* GC inode list */ struct list_head ns_gc_inodes; - struct hlist_head *ns_gc_inodes_h; /* Disk layout information (static) */ unsigned int ns_blocksize_bits; @@ -182,9 +180,6 @@ struct the_nilfs { u32 ns_crc_seed; }; -#define NILFS_GCINODE_HASH_BITS 8 -#define NILFS_GCINODE_HASH_SIZE (1<<NILFS_GCINODE_HASH_BITS) - #define THE_NILFS_FNS(bit, name) \ static inline void set_nilfs_##name(struct the_nilfs *nilfs) \ { \ diff --git a/fs/ocfs2/aops.c b/fs/ocfs2/aops.c index 0de69c9a08be..5cfeee118158 100644 --- a/fs/ocfs2/aops.c +++ b/fs/ocfs2/aops.c @@ -883,8 +883,8 @@ struct ocfs2_write_ctxt { * out in so that future reads from that region will get * zero's. */ - struct page *w_pages[OCFS2_MAX_CTXT_PAGES]; unsigned int w_num_pages; + struct page *w_pages[OCFS2_MAX_CTXT_PAGES]; struct page *w_target_page; /* @@ -1642,7 +1642,8 @@ static int ocfs2_zero_tail(struct inode *inode, struct buffer_head *di_bh, return ret; } -int ocfs2_write_begin_nolock(struct address_space *mapping, +int ocfs2_write_begin_nolock(struct file *filp, + struct address_space *mapping, loff_t pos, unsigned len, unsigned flags, struct page **pagep, void **fsdata, struct buffer_head *di_bh, struct page *mmap_page) @@ -1692,7 +1693,7 @@ int ocfs2_write_begin_nolock(struct address_space *mapping, mlog_errno(ret); goto out; } else if (ret == 1) { - ret = ocfs2_refcount_cow(inode, di_bh, + ret = ocfs2_refcount_cow(inode, filp, di_bh, wc->w_cpos, wc->w_clen, UINT_MAX); if (ret) { mlog_errno(ret); @@ -1854,7 +1855,7 @@ static int ocfs2_write_begin(struct file *file, struct address_space *mapping, */ down_write(&OCFS2_I(inode)->ip_alloc_sem); - ret = ocfs2_write_begin_nolock(mapping, pos, len, flags, pagep, + ret = ocfs2_write_begin_nolock(file, mapping, pos, len, flags, pagep, fsdata, di_bh, NULL); if (ret) { mlog_errno(ret); diff --git a/fs/ocfs2/aops.h b/fs/ocfs2/aops.h index c48e93ffc513..7606f663da6d 100644 --- a/fs/ocfs2/aops.h +++ b/fs/ocfs2/aops.h @@ -48,7 +48,8 @@ int ocfs2_write_end_nolock(struct address_space *mapping, loff_t pos, unsigned len, unsigned copied, struct page *page, void *fsdata); -int ocfs2_write_begin_nolock(struct address_space *mapping, +int ocfs2_write_begin_nolock(struct file *filp, + struct address_space *mapping, loff_t pos, unsigned len, unsigned flags, struct page **pagep, void **fsdata, struct buffer_head *di_bh, struct page *mmap_page); diff --git a/fs/ocfs2/blockcheck.c b/fs/ocfs2/blockcheck.c index ec6d12339593..c7ee03c22226 100644 --- a/fs/ocfs2/blockcheck.c +++ b/fs/ocfs2/blockcheck.c @@ -439,7 +439,7 @@ int ocfs2_block_check_validate(void *data, size_t blocksize, ocfs2_blockcheck_inc_failure(stats); mlog(ML_ERROR, - "CRC32 failed: stored: %u, computed %u. Applying ECC.\n", + "CRC32 failed: stored: 0x%x, computed 0x%x. Applying ECC.\n", (unsigned int)check.bc_crc32e, (unsigned int)crc); /* Ok, try ECC fixups */ @@ -453,7 +453,7 @@ int ocfs2_block_check_validate(void *data, size_t blocksize, goto out; } - mlog(ML_ERROR, "Fixed CRC32 failed: stored: %u, computed %u\n", + mlog(ML_ERROR, "Fixed CRC32 failed: stored: 0x%x, computed 0x%x\n", (unsigned int)check.bc_crc32e, (unsigned int)crc); rc = -EIO; diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index 81296b4e3646..b714f76b82db 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -36,6 +36,7 @@ #include <linux/writeback.h> #include <linux/falloc.h> #include <linux/quotaops.h> +#include <linux/blkdev.h> #define MLOG_MASK_PREFIX ML_INODE #include <cluster/masklog.h> @@ -63,12 +64,6 @@ #include "buffer_head_io.h" -static int ocfs2_sync_inode(struct inode *inode) -{ - filemap_fdatawrite(inode->i_mapping); - return sync_mapping_buffers(inode->i_mapping); -} - static int ocfs2_init_file_private(struct inode *inode, struct file *file) { struct ocfs2_file_private *fp; @@ -186,12 +181,16 @@ static int ocfs2_sync_file(struct file *file, int datasync) mlog_entry("(0x%p, 0x%p, %d, '%.*s')\n", file, dentry, datasync, dentry->d_name.len, dentry->d_name.name); - err = ocfs2_sync_inode(dentry->d_inode); - if (err) - goto bail; - - if (datasync && !(inode->i_state & I_DIRTY_DATASYNC)) + if (datasync && !(inode->i_state & I_DIRTY_DATASYNC)) { + /* + * We still have to flush drive's caches to get data to the + * platter + */ + if (osb->s_mount_opt & OCFS2_MOUNT_BARRIER) + blkdev_issue_flush(inode->i_sb->s_bdev, GFP_KERNEL, + NULL, BLKDEV_IFL_WAIT); goto bail; + } journal = osb->journal->j_journal; err = jbd2_journal_force_commit(journal); @@ -361,7 +360,7 @@ static int ocfs2_cow_file_pos(struct inode *inode, if (!(ext_flags & OCFS2_EXT_REFCOUNTED)) goto out; - return ocfs2_refcount_cow(inode, fe_bh, cpos, 1, cpos+1); + return ocfs2_refcount_cow(inode, NULL, fe_bh, cpos, 1, cpos+1); out: return status; @@ -904,8 +903,8 @@ static int ocfs2_zero_extend_get_range(struct inode *inode, zero_clusters = last_cpos - zero_cpos; if (needs_cow) { - rc = ocfs2_refcount_cow(inode, di_bh, zero_cpos, zero_clusters, - UINT_MAX); + rc = ocfs2_refcount_cow(inode, NULL, di_bh, zero_cpos, + zero_clusters, UINT_MAX); if (rc) { mlog_errno(rc); goto out; @@ -2053,6 +2052,7 @@ out: } static int ocfs2_prepare_inode_for_refcount(struct inode *inode, + struct file *file, loff_t pos, size_t count, int *meta_level) { @@ -2070,7 +2070,7 @@ static int ocfs2_prepare_inode_for_refcount(struct inode *inode, *meta_level = 1; - ret = ocfs2_refcount_cow(inode, di_bh, cpos, clusters, UINT_MAX); + ret = ocfs2_refcount_cow(inode, file, di_bh, cpos, clusters, UINT_MAX); if (ret) mlog_errno(ret); out: @@ -2078,7 +2078,7 @@ out: return ret; } -static int ocfs2_prepare_inode_for_write(struct dentry *dentry, +static int ocfs2_prepare_inode_for_write(struct file *file, loff_t *ppos, size_t count, int appending, @@ -2086,6 +2086,7 @@ static int ocfs2_prepare_inode_for_write(struct dentry *dentry, int *has_refcount) { int ret = 0, meta_level = 0; + struct dentry *dentry = file->f_path.dentry; struct inode *inode = dentry->d_inode; loff_t saved_pos, end; @@ -2141,6 +2142,7 @@ static int ocfs2_prepare_inode_for_write(struct dentry *dentry, meta_level = -1; ret = ocfs2_prepare_inode_for_refcount(inode, + file, saved_pos, count, &meta_level); @@ -2255,7 +2257,7 @@ relock: } can_do_direct = direct_io; - ret = ocfs2_prepare_inode_for_write(file->f_path.dentry, ppos, + ret = ocfs2_prepare_inode_for_write(file, ppos, iocb->ki_left, appending, &can_do_direct, &has_refcount); if (ret < 0) { @@ -2303,17 +2305,6 @@ relock: written = generic_file_direct_write(iocb, iov, &nr_segs, *ppos, ppos, count, ocount); if (written < 0) { - /* - * direct write may have instantiated a few - * blocks outside i_size. Trim these off again. - * Don't need i_size_read because we hold i_mutex. - * - * XXX(truncate): this looks buggy because ocfs2 did not - * actually implement ->truncate. Take a look at - * the new truncate sequence and update this accordingly - */ - if (*ppos + count > inode->i_size) - truncate_setsize(inode, inode->i_size); ret = written; goto out_dio; } @@ -2385,7 +2376,7 @@ static int ocfs2_splice_to_file(struct pipe_inode_info *pipe, { int ret; - ret = ocfs2_prepare_inode_for_write(out->f_path.dentry, &sd->pos, + ret = ocfs2_prepare_inode_for_write(out, &sd->pos, sd->total_len, 0, NULL, NULL); if (ret < 0) { mlog_errno(ret); diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 0492464916b1..eece3e05d9d0 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -488,7 +488,11 @@ static int ocfs2_read_locked_inode(struct inode *inode, OCFS2_BH_IGNORE_CACHE); } else { status = ocfs2_read_blocks_sync(osb, args->fi_blkno, 1, &bh); - if (!status) + /* + * If buffer is in jbd, then its checksum may not have been + * computed as yet. + */ + if (!status && !buffer_jbd(bh)) status = ocfs2_validate_inode_block(osb->sb, bh); } if (status < 0) { diff --git a/fs/ocfs2/inode.h b/fs/ocfs2/inode.h index 6de5a869db30..0bc477a3aeb8 100644 --- a/fs/ocfs2/inode.h +++ b/fs/ocfs2/inode.h @@ -46,27 +46,24 @@ struct ocfs2_inode_info /* These fields are protected by ip_lock */ spinlock_t ip_lock; u32 ip_open_count; - u32 ip_clusters; struct list_head ip_io_markers; + u32 ip_clusters; + u16 ip_dyn_features; struct mutex ip_io_mutex; - u32 ip_flags; /* see below */ u32 ip_attr; /* inode attributes */ - u16 ip_dyn_features; /* protected by recovery_lock. */ struct inode *ip_next_orphan; - u32 ip_dir_start_lookup; - struct ocfs2_caching_info ip_metadata_cache; - struct ocfs2_extent_map ip_extent_map; - struct inode vfs_inode; struct jbd2_inode ip_jinode; + u32 ip_dir_start_lookup; + /* Only valid if the inode is the dir. */ u32 ip_last_used_slot; u64 ip_last_used_group; diff --git a/fs/ocfs2/ioctl.c b/fs/ocfs2/ioctl.c index 7d9d9c132cef..7a4868196152 100644 --- a/fs/ocfs2/ioctl.c +++ b/fs/ocfs2/ioctl.c @@ -26,6 +26,26 @@ #include <linux/ext2_fs.h> +#define o2info_from_user(a, b) \ + copy_from_user(&(a), (b), sizeof(a)) +#define o2info_to_user(a, b) \ + copy_to_user((typeof(a) __user *)b, &(a), sizeof(a)) + +/* + * This call is void because we are already reporting an error that may + * be -EFAULT. The error will be returned from the ioctl(2) call. It's + * just a best-effort to tell userspace that this request caused the error. + */ +static inline void __o2info_set_request_error(struct ocfs2_info_request *kreq, + struct ocfs2_info_request __user *req) +{ + kreq->ir_flags |= OCFS2_INFO_FL_ERROR; + (void)put_user(kreq->ir_flags, (__u32 __user *)&(req->ir_flags)); +} + +#define o2info_set_request_error(a, b) \ + __o2info_set_request_error((struct ocfs2_info_request *)&(a), b) + static int ocfs2_get_inode_attr(struct inode *inode, unsigned *flags) { int status; @@ -109,6 +129,328 @@ bail: return status; } +int ocfs2_info_handle_blocksize(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_blocksize oib; + + if (o2info_from_user(oib, req)) + goto bail; + + oib.ib_blocksize = inode->i_sb->s_blocksize; + oib.ib_req.ir_flags |= OCFS2_INFO_FL_FILLED; + + if (o2info_to_user(oib, req)) + goto bail; + + status = 0; +bail: + if (status) + o2info_set_request_error(oib, req); + + return status; +} + +int ocfs2_info_handle_clustersize(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_clustersize oic; + struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); + + if (o2info_from_user(oic, req)) + goto bail; + + oic.ic_clustersize = osb->s_clustersize; + oic.ic_req.ir_flags |= OCFS2_INFO_FL_FILLED; + + if (o2info_to_user(oic, req)) + goto bail; + + status = 0; +bail: + if (status) + o2info_set_request_error(oic, req); + + return status; +} + +int ocfs2_info_handle_maxslots(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_maxslots oim; + struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); + + if (o2info_from_user(oim, req)) + goto bail; + + oim.im_max_slots = osb->max_slots; + oim.im_req.ir_flags |= OCFS2_INFO_FL_FILLED; + + if (o2info_to_user(oim, req)) + goto bail; + + status = 0; +bail: + if (status) + o2info_set_request_error(oim, req); + + return status; +} + +int ocfs2_info_handle_label(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_label oil; + struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); + + if (o2info_from_user(oil, req)) + goto bail; + + memcpy(oil.il_label, osb->vol_label, OCFS2_MAX_VOL_LABEL_LEN); + oil.il_req.ir_flags |= OCFS2_INFO_FL_FILLED; + + if (o2info_to_user(oil, req)) + goto bail; + + status = 0; +bail: + if (status) + o2info_set_request_error(oil, req); + + return status; +} + +int ocfs2_info_handle_uuid(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_uuid oiu; + struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); + + if (o2info_from_user(oiu, req)) + goto bail; + + memcpy(oiu.iu_uuid_str, osb->uuid_str, OCFS2_TEXT_UUID_LEN + 1); + oiu.iu_req.ir_flags |= OCFS2_INFO_FL_FILLED; + + if (o2info_to_user(oiu, req)) + goto bail; + + status = 0; +bail: + if (status) + o2info_set_request_error(oiu, req); + + return status; +} + +int ocfs2_info_handle_fs_features(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_fs_features oif; + struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); + + if (o2info_from_user(oif, req)) + goto bail; + + oif.if_compat_features = osb->s_feature_compat; + oif.if_incompat_features = osb->s_feature_incompat; + oif.if_ro_compat_features = osb->s_feature_ro_compat; + oif.if_req.ir_flags |= OCFS2_INFO_FL_FILLED; + + if (o2info_to_user(oif, req)) + goto bail; + + status = 0; +bail: + if (status) + o2info_set_request_error(oif, req); + + return status; +} + +int ocfs2_info_handle_journal_size(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_journal_size oij; + struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); + + if (o2info_from_user(oij, req)) + goto bail; + + oij.ij_journal_size = osb->journal->j_inode->i_size; + + oij.ij_req.ir_flags |= OCFS2_INFO_FL_FILLED; + + if (o2info_to_user(oij, req)) + goto bail; + + status = 0; +bail: + if (status) + o2info_set_request_error(oij, req); + + return status; +} + +int ocfs2_info_handle_unknown(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_request oir; + + if (o2info_from_user(oir, req)) + goto bail; + + oir.ir_flags &= ~OCFS2_INFO_FL_FILLED; + + if (o2info_to_user(oir, req)) + goto bail; + + status = 0; +bail: + if (status) + o2info_set_request_error(oir, req); + + return status; +} + +/* + * Validate and distinguish OCFS2_IOC_INFO requests. + * + * - validate the magic number. + * - distinguish different requests. + * - validate size of different requests. + */ +int ocfs2_info_handle_request(struct inode *inode, + struct ocfs2_info_request __user *req) +{ + int status = -EFAULT; + struct ocfs2_info_request oir; + + if (o2info_from_user(oir, req)) + goto bail; + + status = -EINVAL; + if (oir.ir_magic != OCFS2_INFO_MAGIC) + goto bail; + + switch (oir.ir_code) { + case OCFS2_INFO_BLOCKSIZE: + if (oir.ir_size == sizeof(struct ocfs2_info_blocksize)) + status = ocfs2_info_handle_blocksize(inode, req); + break; + case OCFS2_INFO_CLUSTERSIZE: + if (oir.ir_size == sizeof(struct ocfs2_info_clustersize)) + status = ocfs2_info_handle_clustersize(inode, req); + break; + case OCFS2_INFO_MAXSLOTS: + if (oir.ir_size == sizeof(struct ocfs2_info_maxslots)) + status = ocfs2_info_handle_maxslots(inode, req); + break; + case OCFS2_INFO_LABEL: + if (oir.ir_size == sizeof(struct ocfs2_info_label)) + status = ocfs2_info_handle_label(inode, req); + break; + case OCFS2_INFO_UUID: + if (oir.ir_size == sizeof(struct ocfs2_info_uuid)) + status = ocfs2_info_handle_uuid(inode, req); + break; + case OCFS2_INFO_FS_FEATURES: + if (oir.ir_size == sizeof(struct ocfs2_info_fs_features)) + status = ocfs2_info_handle_fs_features(inode, req); + break; + case OCFS2_INFO_JOURNAL_SIZE: + if (oir.ir_size == sizeof(struct ocfs2_info_journal_size)) + status = ocfs2_info_handle_journal_size(inode, req); + break; + default: + status = ocfs2_info_handle_unknown(inode, req); + break; + } + +bail: + return status; +} + +int ocfs2_get_request_ptr(struct ocfs2_info *info, int idx, + u64 *req_addr, int compat_flag) +{ + int status = -EFAULT; + u64 __user *bp = NULL; + + if (compat_flag) { +#ifdef CONFIG_COMPAT + /* + * pointer bp stores the base address of a pointers array, + * which collects all addresses of separate request. + */ + bp = (u64 __user *)(unsigned long)compat_ptr(info->oi_requests); +#else + BUG(); +#endif + } else + bp = (u64 __user *)(unsigned long)(info->oi_requests); + + if (o2info_from_user(*req_addr, bp + idx)) + goto bail; + + status = 0; +bail: + return status; +} + +/* + * OCFS2_IOC_INFO handles an array of requests passed from userspace. + * + * ocfs2_info_handle() recevies a large info aggregation, grab and + * validate the request count from header, then break it into small + * pieces, later specific handlers can handle them one by one. + * + * Idea here is to make each separate request small enough to ensure + * a better backward&forward compatibility, since a small piece of + * request will be less likely to be broken if disk layout get changed. + */ +int ocfs2_info_handle(struct inode *inode, struct ocfs2_info *info, + int compat_flag) +{ + int i, status = 0; + u64 req_addr; + struct ocfs2_info_request __user *reqp; + + if ((info->oi_count > OCFS2_INFO_MAX_REQUEST) || + (!info->oi_requests)) { + status = -EINVAL; + goto bail; + } + + for (i = 0; i < info->oi_count; i++) { + + status = ocfs2_get_request_ptr(info, i, &req_addr, compat_flag); + if (status) + break; + + reqp = (struct ocfs2_info_request *)(unsigned long)req_addr; + if (!reqp) { + status = -EINVAL; + goto bail; + } + + status = ocfs2_info_handle_request(inode, reqp); + if (status) + break; + } + +bail: + return status; +} + long ocfs2_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { struct inode *inode = filp->f_path.dentry->d_inode; @@ -120,6 +462,7 @@ long ocfs2_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) struct reflink_arguments args; const char *old_path, *new_path; bool preserve; + struct ocfs2_info info; switch (cmd) { case OCFS2_IOC_GETFLAGS: @@ -174,6 +517,12 @@ long ocfs2_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) preserve = (args.preserve != 0); return ocfs2_reflink_ioctl(inode, old_path, new_path, preserve); + case OCFS2_IOC_INFO: + if (copy_from_user(&info, (struct ocfs2_info __user *)arg, + sizeof(struct ocfs2_info))) + return -EFAULT; + + return ocfs2_info_handle(inode, &info, 0); default: return -ENOTTY; } @@ -185,6 +534,7 @@ long ocfs2_compat_ioctl(struct file *file, unsigned cmd, unsigned long arg) bool preserve; struct reflink_arguments args; struct inode *inode = file->f_path.dentry->d_inode; + struct ocfs2_info info; switch (cmd) { case OCFS2_IOC32_GETFLAGS: @@ -209,6 +559,12 @@ long ocfs2_compat_ioctl(struct file *file, unsigned cmd, unsigned long arg) return ocfs2_reflink_ioctl(inode, compat_ptr(args.old_path), compat_ptr(args.new_path), preserve); + case OCFS2_IOC_INFO: + if (copy_from_user(&info, (struct ocfs2_info __user *)arg, + sizeof(struct ocfs2_info))) + return -EFAULT; + + return ocfs2_info_handle(inode, &info, 1); default: return -ENOIOCTLCMD; } diff --git a/fs/ocfs2/journal.c b/fs/ocfs2/journal.c index 9b57c0350ff9..faa2303dbf0a 100644 --- a/fs/ocfs2/journal.c +++ b/fs/ocfs2/journal.c @@ -301,7 +301,6 @@ static int ocfs2_commit_cache(struct ocfs2_super *osb) { int status = 0; unsigned int flushed; - unsigned long old_id; struct ocfs2_journal *journal = NULL; mlog_entry_void(); @@ -326,7 +325,7 @@ static int ocfs2_commit_cache(struct ocfs2_super *osb) goto finally; } - old_id = ocfs2_inc_trans_id(journal); + ocfs2_inc_trans_id(journal); flushed = atomic_read(&journal->j_num_trans); atomic_set(&journal->j_num_trans, 0); @@ -342,9 +341,6 @@ finally: return status; } -/* pass it NULL and it will allocate a new handle object for you. If - * you pass it a handle however, it may still return error, in which - * case it has free'd the passed handle for you. */ handle_t *ocfs2_start_trans(struct ocfs2_super *osb, int max_buffs) { journal_t *journal = osb->journal->j_journal; @@ -1888,6 +1884,8 @@ void ocfs2_queue_orphan_scan(struct ocfs2_super *osb) os = &osb->osb_orphan_scan; + mlog(0, "Begin orphan scan\n"); + if (atomic_read(&os->os_state) == ORPHAN_SCAN_INACTIVE) goto out; @@ -1920,6 +1918,7 @@ void ocfs2_queue_orphan_scan(struct ocfs2_super *osb) unlock: ocfs2_orphan_scan_unlock(osb, seqno); out: + mlog(0, "Orphan scan completed\n"); return; } diff --git a/fs/ocfs2/journal.h b/fs/ocfs2/journal.h index b5baaa8e710f..43e56b97f9c0 100644 --- a/fs/ocfs2/journal.h +++ b/fs/ocfs2/journal.h @@ -67,11 +67,12 @@ struct ocfs2_journal { struct buffer_head *j_bh; /* Journal disk inode block */ atomic_t j_num_trans; /* Number of transactions * currently in the system. */ + spinlock_t j_lock; unsigned long j_trans_id; struct rw_semaphore j_trans_barrier; wait_queue_head_t j_checkpointed; - spinlock_t j_lock; + /* both fields protected by j_lock*/ struct list_head j_la_cleanups; struct work_struct j_recovery_work; }; diff --git a/fs/ocfs2/mmap.c b/fs/ocfs2/mmap.c index af2b8fe1f139..b04d6961c0d4 100644 --- a/fs/ocfs2/mmap.c +++ b/fs/ocfs2/mmap.c @@ -59,10 +59,11 @@ static int ocfs2_fault(struct vm_area_struct *area, struct vm_fault *vmf) return ret; } -static int __ocfs2_page_mkwrite(struct inode *inode, struct buffer_head *di_bh, +static int __ocfs2_page_mkwrite(struct file *file, struct buffer_head *di_bh, struct page *page) { int ret; + struct inode *inode = file->f_path.dentry->d_inode; struct address_space *mapping = inode->i_mapping; loff_t pos = page_offset(page); unsigned int len = PAGE_CACHE_SIZE; @@ -109,7 +110,7 @@ static int __ocfs2_page_mkwrite(struct inode *inode, struct buffer_head *di_bh, if (page->index == last_index) len = size & ~PAGE_CACHE_MASK; - ret = ocfs2_write_begin_nolock(mapping, pos, len, 0, &locked_page, + ret = ocfs2_write_begin_nolock(file, mapping, pos, len, 0, &locked_page, &fsdata, di_bh, page); if (ret) { if (ret != -ENOSPC) @@ -157,7 +158,7 @@ static int ocfs2_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) */ down_write(&OCFS2_I(inode)->ip_alloc_sem); - ret = __ocfs2_page_mkwrite(inode, di_bh, page); + ret = __ocfs2_page_mkwrite(vma->vm_file, di_bh, page); up_write(&OCFS2_I(inode)->ip_alloc_sem); diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h index c67003b6b5a2..65739b3b3276 100644 --- a/fs/ocfs2/ocfs2.h +++ b/fs/ocfs2/ocfs2.h @@ -150,26 +150,33 @@ typedef void (*ocfs2_lock_callback)(int status, unsigned long data); struct ocfs2_lock_res { void *l_priv; struct ocfs2_lock_res_ops *l_ops; - spinlock_t l_lock; + struct list_head l_blocked_list; struct list_head l_mask_waiters; - enum ocfs2_lock_type l_type; unsigned long l_flags; char l_name[OCFS2_LOCK_ID_MAX_LEN]; - int l_level; unsigned int l_ro_holders; unsigned int l_ex_holders; - struct ocfs2_dlm_lksb l_lksb; + unsigned char l_level; + + /* Data packed - type enum ocfs2_lock_type */ + unsigned char l_type; /* used from AST/BAST funcs. */ - enum ocfs2_ast_action l_action; - enum ocfs2_unlock_action l_unlock_action; - int l_requested; - int l_blocking; + /* Data packed - enum type ocfs2_ast_action */ + unsigned char l_action; + /* Data packed - enum type ocfs2_unlock_action */ + unsigned char l_unlock_action; + unsigned char l_requested; + unsigned char l_blocking; unsigned int l_pending_gen; + spinlock_t l_lock; + + struct ocfs2_dlm_lksb l_lksb; + wait_queue_head_t l_event; struct list_head l_debug_list; diff --git a/fs/ocfs2/ocfs2_ioctl.h b/fs/ocfs2/ocfs2_ioctl.h index 2d3420af1a83..9bc535499868 100644 --- a/fs/ocfs2/ocfs2_ioctl.h +++ b/fs/ocfs2/ocfs2_ioctl.h @@ -76,4 +76,99 @@ struct reflink_arguments { }; #define OCFS2_IOC_REFLINK _IOW('o', 4, struct reflink_arguments) +/* Following definitions dedicated for ocfs2_info_request ioctls. */ +#define OCFS2_INFO_MAX_REQUEST (50) +#define OCFS2_TEXT_UUID_LEN (OCFS2_VOL_UUID_LEN * 2) + +/* Magic number of all requests */ +#define OCFS2_INFO_MAGIC (0x4F32494E) + +/* + * Always try to separate info request into small pieces to + * guarantee the backward&forward compatibility. + */ +struct ocfs2_info { + __u64 oi_requests; /* Array of __u64 pointers to requests */ + __u32 oi_count; /* Number of requests in info_requests */ + __u32 oi_pad; +}; + +struct ocfs2_info_request { +/*00*/ __u32 ir_magic; /* Magic number */ + __u32 ir_code; /* Info request code */ + __u32 ir_size; /* Size of request */ + __u32 ir_flags; /* Request flags */ +/*10*/ /* Request specific fields */ +}; + +struct ocfs2_info_clustersize { + struct ocfs2_info_request ic_req; + __u32 ic_clustersize; + __u32 ic_pad; +}; + +struct ocfs2_info_blocksize { + struct ocfs2_info_request ib_req; + __u32 ib_blocksize; + __u32 ib_pad; +}; + +struct ocfs2_info_maxslots { + struct ocfs2_info_request im_req; + __u32 im_max_slots; + __u32 im_pad; +}; + +struct ocfs2_info_label { + struct ocfs2_info_request il_req; + __u8 il_label[OCFS2_MAX_VOL_LABEL_LEN]; +} __attribute__ ((packed)); + +struct ocfs2_info_uuid { + struct ocfs2_info_request iu_req; + __u8 iu_uuid_str[OCFS2_TEXT_UUID_LEN + 1]; +} __attribute__ ((packed)); + +struct ocfs2_info_fs_features { + struct ocfs2_info_request if_req; + __u32 if_compat_features; + __u32 if_incompat_features; + __u32 if_ro_compat_features; + __u32 if_pad; +}; + +struct ocfs2_info_journal_size { + struct ocfs2_info_request ij_req; + __u64 ij_journal_size; +}; + +/* Codes for ocfs2_info_request */ +enum ocfs2_info_type { + OCFS2_INFO_CLUSTERSIZE = 1, + OCFS2_INFO_BLOCKSIZE, + OCFS2_INFO_MAXSLOTS, + OCFS2_INFO_LABEL, + OCFS2_INFO_UUID, + OCFS2_INFO_FS_FEATURES, + OCFS2_INFO_JOURNAL_SIZE, + OCFS2_INFO_NUM_TYPES +}; + +/* Flags for struct ocfs2_info_request */ +/* Filled by the caller */ +#define OCFS2_INFO_FL_NON_COHERENT (0x00000001) /* Cluster coherency not + required. This is a hint. + It is up to ocfs2 whether + the request can be fulfilled + without locking. */ +/* Filled by ocfs2 */ +#define OCFS2_INFO_FL_FILLED (0x40000000) /* Filesystem understood + this request and + filled in the answer */ + +#define OCFS2_INFO_FL_ERROR (0x80000000) /* Error happened during + request handling. */ + +#define OCFS2_IOC_INFO _IOR('o', 5, struct ocfs2_info) + #endif /* OCFS2_IOCTL_H */ diff --git a/fs/ocfs2/refcounttree.c b/fs/ocfs2/refcounttree.c index 73a11ccfd4c2..7f13d2059b44 100644 --- a/fs/ocfs2/refcounttree.c +++ b/fs/ocfs2/refcounttree.c @@ -49,6 +49,7 @@ struct ocfs2_cow_context { struct inode *inode; + struct file *file; u32 cow_start; u32 cow_len; struct ocfs2_extent_tree data_et; @@ -2932,13 +2933,16 @@ static int ocfs2_duplicate_clusters_by_page(handle_t *handle, u64 new_block = ocfs2_clusters_to_blocks(sb, new_cluster); struct page *page; pgoff_t page_index; - unsigned int from, to; + unsigned int from, to, readahead_pages; loff_t offset, end, map_end; struct address_space *mapping = context->inode->i_mapping; mlog(0, "old_cluster %u, new %u, len %u at offset %u\n", old_cluster, new_cluster, new_len, cpos); + readahead_pages = + (ocfs2_cow_contig_clusters(sb) << + OCFS2_SB(sb)->s_clustersize_bits) >> PAGE_CACHE_SHIFT; offset = ((loff_t)cpos) << OCFS2_SB(sb)->s_clustersize_bits; end = offset + (new_len << OCFS2_SB(sb)->s_clustersize_bits); /* @@ -2969,6 +2973,14 @@ static int ocfs2_duplicate_clusters_by_page(handle_t *handle, if (PAGE_CACHE_SIZE <= OCFS2_SB(sb)->s_clustersize) BUG_ON(PageDirty(page)); + if (PageReadahead(page) && context->file) { + page_cache_async_readahead(mapping, + &context->file->f_ra, + context->file, + page, page_index, + readahead_pages); + } + if (!PageUptodate(page)) { ret = block_read_full_page(page, ocfs2_get_block); if (ret) { @@ -3408,12 +3420,35 @@ static int ocfs2_replace_cow(struct ocfs2_cow_context *context) return ret; } +static void ocfs2_readahead_for_cow(struct inode *inode, + struct file *file, + u32 start, u32 len) +{ + struct address_space *mapping; + pgoff_t index; + unsigned long num_pages; + int cs_bits = OCFS2_SB(inode->i_sb)->s_clustersize_bits; + + if (!file) + return; + + mapping = file->f_mapping; + num_pages = (len << cs_bits) >> PAGE_CACHE_SHIFT; + if (!num_pages) + num_pages = 1; + + index = ((loff_t)start << cs_bits) >> PAGE_CACHE_SHIFT; + page_cache_sync_readahead(mapping, &file->f_ra, file, + index, num_pages); +} + /* * Starting at cpos, try to CoW write_len clusters. Don't CoW * past max_cpos. This will stop when it runs into a hole or an * unrefcounted extent. */ static int ocfs2_refcount_cow_hunk(struct inode *inode, + struct file *file, struct buffer_head *di_bh, u32 cpos, u32 write_len, u32 max_cpos) { @@ -3442,6 +3477,8 @@ static int ocfs2_refcount_cow_hunk(struct inode *inode, BUG_ON(cow_len == 0); + ocfs2_readahead_for_cow(inode, file, cow_start, cow_len); + context = kzalloc(sizeof(struct ocfs2_cow_context), GFP_NOFS); if (!context) { ret = -ENOMEM; @@ -3463,6 +3500,7 @@ static int ocfs2_refcount_cow_hunk(struct inode *inode, context->ref_root_bh = ref_root_bh; context->cow_duplicate_clusters = ocfs2_duplicate_clusters_by_page; context->get_clusters = ocfs2_di_get_clusters; + context->file = file; ocfs2_init_dinode_extent_tree(&context->data_et, INODE_CACHE(inode), di_bh); @@ -3491,6 +3529,7 @@ out: * clusters between cpos and cpos+write_len are safe to modify. */ int ocfs2_refcount_cow(struct inode *inode, + struct file *file, struct buffer_head *di_bh, u32 cpos, u32 write_len, u32 max_cpos) { @@ -3510,7 +3549,7 @@ int ocfs2_refcount_cow(struct inode *inode, num_clusters = write_len; if (ext_flags & OCFS2_EXT_REFCOUNTED) { - ret = ocfs2_refcount_cow_hunk(inode, di_bh, cpos, + ret = ocfs2_refcount_cow_hunk(inode, file, di_bh, cpos, num_clusters, max_cpos); if (ret) { mlog_errno(ret); diff --git a/fs/ocfs2/refcounttree.h b/fs/ocfs2/refcounttree.h index 9983ba1570e2..c8ce46f7d8e3 100644 --- a/fs/ocfs2/refcounttree.h +++ b/fs/ocfs2/refcounttree.h @@ -21,14 +21,14 @@ struct ocfs2_refcount_tree { struct rb_node rf_node; u64 rf_blkno; u32 rf_generation; + struct kref rf_getcnt; struct rw_semaphore rf_sem; struct ocfs2_lock_res rf_lockres; - struct kref rf_getcnt; int rf_removed; /* the following 4 fields are used by caching_info. */ - struct ocfs2_caching_info rf_ci; spinlock_t rf_lock; + struct ocfs2_caching_info rf_ci; struct mutex rf_io_mutex; struct super_block *rf_sb; }; @@ -52,7 +52,8 @@ int ocfs2_prepare_refcount_change_for_del(struct inode *inode, u32 clusters, int *credits, int *ref_blocks); -int ocfs2_refcount_cow(struct inode *inode, struct buffer_head *di_bh, +int ocfs2_refcount_cow(struct inode *inode, + struct file *filep, struct buffer_head *di_bh, u32 cpos, u32 write_len, u32 max_cpos); typedef int (ocfs2_post_refcount_func)(struct inode *inode, diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index fa1be1b304d1..47415398d56a 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -1990,6 +1990,36 @@ static int ocfs2_setup_osb_uuid(struct ocfs2_super *osb, const unsigned char *uu return 0; } +/* Make sure entire volume is addressable by our journal. Requires + osb_clusters_at_boot to be valid and for the journal to have been + initialized by ocfs2_journal_init(). */ +static int ocfs2_journal_addressable(struct ocfs2_super *osb) +{ + int status = 0; + u64 max_block = + ocfs2_clusters_to_blocks(osb->sb, + osb->osb_clusters_at_boot) - 1; + + /* 32-bit block number is always OK. */ + if (max_block <= (u32)~0ULL) + goto out; + + /* Volume is "huge", so see if our journal is new enough to + support it. */ + if (!(OCFS2_HAS_COMPAT_FEATURE(osb->sb, + OCFS2_FEATURE_COMPAT_JBD2_SB) && + jbd2_journal_check_used_features(osb->journal->j_journal, 0, 0, + JBD2_FEATURE_INCOMPAT_64BIT))) { + mlog(ML_ERROR, "The journal cannot address the entire volume. " + "Enable the 'block64' journal option with tunefs.ocfs2"); + status = -EFBIG; + goto out; + } + + out: + return status; +} + static int ocfs2_initialize_super(struct super_block *sb, struct buffer_head *bh, int sector_size, @@ -2002,6 +2032,7 @@ static int ocfs2_initialize_super(struct super_block *sb, struct ocfs2_journal *journal; __le32 uuid_net_key; struct ocfs2_super *osb; + u64 total_blocks; mlog_entry_void(); @@ -2214,11 +2245,15 @@ static int ocfs2_initialize_super(struct super_block *sb, goto bail; } - if (ocfs2_clusters_to_blocks(osb->sb, le32_to_cpu(di->i_clusters) - 1) - > (u32)~0UL) { - mlog(ML_ERROR, "Volume might try to write to blocks beyond " - "what jbd can address in 32 bits.\n"); - status = -EINVAL; + total_blocks = ocfs2_clusters_to_blocks(osb->sb, + le32_to_cpu(di->i_clusters)); + + status = generic_check_addressable(osb->sb->s_blocksize_bits, + total_blocks); + if (status) { + mlog(ML_ERROR, "Volume too large " + "to mount safely on this system"); + status = -EFBIG; goto bail; } @@ -2380,6 +2415,12 @@ static int ocfs2_check_volume(struct ocfs2_super *osb) goto finally; } + /* Now that journal has been initialized, check to make sure + entire volume is addressable. */ + status = ocfs2_journal_addressable(osb); + if (status) + goto finally; + /* If the journal was unmounted cleanly then we don't want to * recover anything. Otherwise, journal_load will do that * dirty work for us :) */ diff --git a/fs/quota/Kconfig b/fs/quota/Kconfig index 3e21b1e2ad3a..880fd9884366 100644 --- a/fs/quota/Kconfig +++ b/fs/quota/Kconfig @@ -4,6 +4,7 @@ config QUOTA bool "Quota support" + select QUOTACTL help If you say Y here, you will be able to set per user limits for disk usage (also called disk quotas). Currently, it works for the @@ -65,8 +66,7 @@ config QFMT_V2 config QUOTACTL bool - depends on XFS_QUOTA || QUOTA - default y + default n config QUOTACTL_COMPAT bool diff --git a/fs/xfs/Kconfig b/fs/xfs/Kconfig index 480f28127f09..6100ec0fa1d4 100644 --- a/fs/xfs/Kconfig +++ b/fs/xfs/Kconfig @@ -22,6 +22,7 @@ config XFS_FS config XFS_QUOTA bool "XFS Quota support" depends on XFS_FS + select QUOTACTL help If you say Y here, you will be able to set limits for disk usage on a per user and/or a per group basis under XFS. XFS considers quota diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index baacd98e7cc6..4de84ce3a927 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -377,9 +377,6 @@ struct acpi_pci_root { u32 osc_support_set; /* _OSC state of support bits */ u32 osc_control_set; /* _OSC state of control bits */ - u32 osc_control_qry; /* the latest _OSC query result */ - - u32 osc_queried:1; /* has _OSC control been queried? */ }; /* helper */ diff --git a/include/linux/acpi.h b/include/linux/acpi.h index ccf94dc5acdf..c227757feb06 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -304,8 +304,8 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context); OSC_PCI_EXPRESS_PME_CONTROL | \ OSC_PCI_EXPRESS_AER_CONTROL | \ OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL) - -extern acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 flags); +extern acpi_status acpi_pci_osc_control_set(acpi_handle handle, + u32 *mask, u32 req); extern void acpi_early_init(void); #else /* !CONFIG_ACPI */ diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h index ca84ce70d5d5..f4ee9acc9721 100644 --- a/include/linux/amba/mmci.h +++ b/include/linux/amba/mmci.h @@ -24,6 +24,7 @@ * whether a card is present in the MMC slot or not * @gpio_wp: read this GPIO pin to see if the card is write protected * @gpio_cd: read this GPIO pin to detect card insertion + * @cd_invert: true if the gpio_cd pin value is active low * @capabilities: the capabilities of the block as implemented in * this platform, signify anything MMC_CAP_* from mmc/host.h */ @@ -35,6 +36,7 @@ struct mmci_platform_data { unsigned int (*status)(struct device *); int gpio_wp; int gpio_cd; + bool cd_invert; unsigned long capabilities; }; diff --git a/include/linux/fs.h b/include/linux/fs.h index 76041b614758..1a759f40ab9e 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2374,6 +2374,8 @@ extern ssize_t simple_write_to_buffer(void *to, size_t available, loff_t *ppos, extern int generic_file_fsync(struct file *, int); +extern int generic_check_addressable(unsigned, u64); + #ifdef CONFIG_MIGRATION extern int buffer_migrate_page(struct address_space *, struct page *, struct page *); diff --git a/include/linux/nilfs2_fs.h b/include/linux/nilfs2_fs.h index f5487b6f91ed..bcdb34c68d08 100644 --- a/include/linux/nilfs2_fs.h +++ b/include/linux/nilfs2_fs.h @@ -229,6 +229,7 @@ struct nilfs_super_block { */ #define NILFS_CURRENT_REV 2 /* current major revision */ #define NILFS_MINOR_REV 0 /* minor revision */ +#define NILFS_MIN_SUPP_REV 2 /* minimum supported revision */ /* * Feature set definitions @@ -270,6 +271,14 @@ struct nilfs_super_block { segments */ /* + * We call DAT, cpfile, and sufile root metadata files. Inodes of + * these files are written in super root block instead of ifile, and + * garbage collector doesn't keep any past versions of these files. + */ +#define NILFS_ROOT_METADATA_FILE(ino) \ + ((ino) >= NILFS_DAT_INO && (ino) <= NILFS_SUFILE_INO) + +/* * bytes offset of secondary super block */ #define NILFS_SB2_OFFSET_BYTES(devsize) ((((devsize) >> 12) - 1) << 12) diff --git a/include/linux/pci.h b/include/linux/pci.h index b1d17956a153..c8d95e369ff4 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1214,6 +1214,9 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn) { return NULL; } +static inline int pci_domain_nr(struct pci_bus *bus) +{ return 0; } + #define dev_is_pci(d) (false) #define dev_is_pf(d) (false) #define dev_num_vf(d) (0) diff --git a/lib/raid6/.gitignore b/lib/raid6/.gitignore new file mode 100644 index 000000000000..162becacf97c --- /dev/null +++ b/lib/raid6/.gitignore @@ -0,0 +1,4 @@ +mktables +altivec*.c +int*.c +tables.c diff --git a/net/irda/af_irda.c b/net/irda/af_irda.c index 79986a674f6e..fd55b5135de5 100644 --- a/net/irda/af_irda.c +++ b/net/irda/af_irda.c @@ -824,8 +824,8 @@ static int irda_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) err = irda_open_tsap(self, addr->sir_lsap_sel, addr->sir_name); if (err < 0) { - kfree(self->ias_obj->name); - kfree(self->ias_obj); + irias_delete_object(self->ias_obj); + self->ias_obj = NULL; goto out; } diff --git a/net/mac80211/main.c b/net/mac80211/main.c index 798a91b100cc..ded5c3843e06 100644 --- a/net/mac80211/main.c +++ b/net/mac80211/main.c @@ -732,6 +732,12 @@ void ieee80211_unregister_hw(struct ieee80211_hw *hw) rtnl_unlock(); + /* + * Now all work items will be gone, but the + * timer might still be armed, so delete it + */ + del_timer_sync(&local->work_timer); + cancel_work_sync(&local->reconfig_filter); ieee80211_clear_tx_pending(local); diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index 980fe4ad0016..cd96ed3ccee4 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -2102,6 +2102,26 @@ static void __net_exit netlink_net_exit(struct net *net) #endif } +static void __init netlink_add_usersock_entry(void) +{ + unsigned long *listeners; + int groups = 32; + + listeners = kzalloc(NLGRPSZ(groups) + sizeof(struct listeners_rcu_head), + GFP_KERNEL); + if (!listeners) + panic("netlink_add_usersock_entry: Cannot allocate listneres\n"); + + netlink_table_grab(); + + nl_table[NETLINK_USERSOCK].groups = groups; + nl_table[NETLINK_USERSOCK].listeners = listeners; + nl_table[NETLINK_USERSOCK].module = THIS_MODULE; + nl_table[NETLINK_USERSOCK].registered = 1; + + netlink_table_ungrab(); +} + static struct pernet_operations __net_initdata netlink_net_ops = { .init = netlink_net_init, .exit = netlink_net_exit, @@ -2150,6 +2170,8 @@ static int __init netlink_proto_init(void) hash->rehash_time = jiffies; } + netlink_add_usersock_entry(); + sock_register(&netlink_family_ops); register_pernet_subsys(&netlink_net_ops); /* The netlink device handler may be needed early. */ diff --git a/net/wireless/core.c b/net/wireless/core.c index 541e2fff5e9c..d6d046b9f6f2 100644 --- a/net/wireless/core.c +++ b/net/wireless/core.c @@ -475,12 +475,10 @@ int wiphy_register(struct wiphy *wiphy) mutex_lock(&cfg80211_mutex); res = device_add(&rdev->wiphy.dev); - if (res) - goto out_unlock; - - res = rfkill_register(rdev->rfkill); - if (res) - goto out_rm_dev; + if (res) { + mutex_unlock(&cfg80211_mutex); + return res; + } /* set up regulatory info */ wiphy_update_regulatory(wiphy, NL80211_REGDOM_SET_BY_CORE); @@ -509,13 +507,18 @@ int wiphy_register(struct wiphy *wiphy) cfg80211_debugfs_rdev_add(rdev); mutex_unlock(&cfg80211_mutex); + /* + * due to a locking dependency this has to be outside of the + * cfg80211_mutex lock + */ + res = rfkill_register(rdev->rfkill); + if (res) + goto out_rm_dev; + return 0; out_rm_dev: device_del(&rdev->wiphy.dev); - -out_unlock: - mutex_unlock(&cfg80211_mutex); return res; } EXPORT_SYMBOL(wiphy_register); diff --git a/net/wireless/wext-compat.c b/net/wireless/wext-compat.c index bb5e0a5ecfa1..7e5c3a45f811 100644 --- a/net/wireless/wext-compat.c +++ b/net/wireless/wext-compat.c @@ -1420,6 +1420,9 @@ int cfg80211_wext_giwessid(struct net_device *dev, { struct wireless_dev *wdev = dev->ieee80211_ptr; + data->flags = 0; + data->length = 0; + switch (wdev->iftype) { case NL80211_IFTYPE_ADHOC: return cfg80211_ibss_wext_giwessid(dev, info, data, ssid); diff --git a/net/wireless/wext-core.c b/net/wireless/wext-core.c index 0ef17bc42bac..8f5116f5af19 100644 --- a/net/wireless/wext-core.c +++ b/net/wireless/wext-core.c @@ -782,6 +782,22 @@ static int ioctl_standard_iw_point(struct iw_point *iwp, unsigned int cmd, } } + if (IW_IS_GET(cmd) && !(descr->flags & IW_DESCR_FLAG_NOMAX)) { + /* + * If this is a GET, but not NOMAX, it means that the extra + * data is not bounded by userspace, but by max_tokens. Thus + * set the length to max_tokens. This matches the extra data + * allocation. + * The driver should fill it with the number of tokens it + * provided, and it may check iwp->length rather than having + * knowledge of max_tokens. If the driver doesn't change the + * iwp->length, this ioctl just copies back max_token tokens + * filled with zeroes. Hopefully the driver isn't claiming + * them to be valid data. + */ + iwp->length = descr->max_tokens; + } + err = handler(dev, info, (union iwreq_data *) iwp, extra); iwp->length += essid_compat; diff --git a/sound/soc/sh/siu_pcm.c b/sound/soc/sh/siu_pcm.c index 36170be15aa7..b0ccd0b862fc 100644 --- a/sound/soc/sh/siu_pcm.c +++ b/sound/soc/sh/siu_pcm.c @@ -127,6 +127,7 @@ static int siu_pcm_wr_set(struct siu_port *port_info, sg_init_table(&sg, 1); sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)), size, offset_in_page(buff)); + sg_dma_len(&sg) = size; sg_dma_address(&sg) = buff; desc = siu_stream->chan->device->device_prep_slave_sg(siu_stream->chan, @@ -176,6 +177,7 @@ static int siu_pcm_rd_set(struct siu_port *port_info, sg_init_table(&sg, 1); sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)), size, offset_in_page(buff)); + sg_dma_len(&sg) = size; sg_dma_address(&sg) = buff; desc = siu_stream->chan->device->device_prep_slave_sg(siu_stream->chan, |