diff options
| -rw-r--r-- | drivers/clk/spacemit/ccu-k1.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 8a0dd8146dbd..cdde37a05235 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -328,6 +328,12 @@ CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0 CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0); +/* + * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero. + * Combine functional and bus bits together as a gate to avoid sharing the + * write-only register between different clock hardwares. + */ +CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0); static const struct clk_parent_data timer_parents[] = { CCU_PARENT_HW(pll1_d192_12p8), @@ -412,6 +418,8 @@ CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0 CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0); +/* Placeholder to workaround quirk of the register */ +CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1); CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); @@ -896,6 +904,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { [CLK_TWSI5] = &twsi5_clk.common.hw, [CLK_TWSI6] = &twsi6_clk.common.hw, [CLK_TWSI7] = &twsi7_clk.common.hw, + [CLK_TWSI8] = &twsi8_clk.common.hw, [CLK_TIMERS1] = &timers1_clk.common.hw, [CLK_TIMERS2] = &timers2_clk.common.hw, [CLK_AIB] = &aib_clk.common.hw, @@ -947,6 +956,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { [CLK_TWSI5_BUS] = &twsi5_bus_clk.common.hw, [CLK_TWSI6_BUS] = &twsi6_bus_clk.common.hw, [CLK_TWSI7_BUS] = &twsi7_bus_clk.common.hw, + [CLK_TWSI8_BUS] = &twsi8_bus_clk.common.hw, [CLK_TIMERS1_BUS] = &timers1_bus_clk.common.hw, [CLK_TIMERS2_BUS] = &timers2_bus_clk.common.hw, [CLK_AIB_BUS] = &aib_bus_clk.common.hw, |