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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car PCIe Host
+
+maintainers:
+ - Marek Vasut <marek.vasut+renesas@gmail.com>
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: pci-bus.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,pcie-r8a7742 # RZ/G1H
+ - renesas,pcie-r8a7743 # RZ/G1M
+ - renesas,pcie-r8a7744 # RZ/G1N
+ - renesas,pcie-r8a7790 # R-Car H2
+ - renesas,pcie-r8a7791 # R-Car M2-W
+ - renesas,pcie-r8a7793 # R-Car M2-N
+ - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
+ - items:
+ - enum:
+ - renesas,pcie-r8a774a1 # RZ/G2M
+ - renesas,pcie-r8a774b1 # RZ/G2N
+ - renesas,pcie-r8a774c0 # RZ/G2E
+ - renesas,pcie-r8a774e1 # RZ/G2H
+ - renesas,pcie-r8a7795 # R-Car H3
+ - renesas,pcie-r8a7796 # R-Car M3-W
+ - renesas,pcie-r8a77961 # R-Car M3-W+
+ - renesas,pcie-r8a77965 # R-Car M3-N
+ - renesas,pcie-r8a77980 # R-Car V3H
+ - renesas,pcie-r8a77990 # R-Car E3
+ - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: pcie
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
+ <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ };
+ };