diff options
Diffstat (limited to 'Documentation/devicetree')
10 files changed, 259 insertions, 59 deletions
diff --git a/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml b/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml new file mode 100644 index 000000000000..6604dcd47251 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/hpe,gxp-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE GXP SoC I2C Controller + +maintainers: + - Nick Hawkins <nick.hawkins@hpe.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: hpe,gxp-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + default: 100000 + + hpe,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the global status and enable interrupt registers shared + between each I2C engine controller instance. It enables the I2C + engine controller to act as both a master or slave by being able to + arm and respond to interrupts from its engine. Each bit in the + registers represent the respective bit position. + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + i2c@2600 { + compatible = "hpe,gxp-i2c"; + reg = <0x2500 0x70>; + interrupts = <9>; + #address-cells = <1>; + #size-cells = <0>; + hpe,sysreg = <&sysreg_system_controller>; + clock-frequency = <10000>; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml b/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml index e0d76d5eb103..afd4925c2a7d 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml @@ -33,6 +33,10 @@ properties: open drain. maxItems: 1 + i2c-gpio,sda-output-only: + description: sda as output only + type: boolean + i2c-gpio,scl-output-only: description: scl as output only type: boolean @@ -63,6 +67,28 @@ properties: GPIO line used for SCL into open drain mode, and that something is not the GPIO chip. It is essentially an inconsistency flag. + i2c-gpio,sda-has-no-pullup: + type: boolean + description: sda is used in a non-compliant way and has no pull-up. + Therefore disable open-drain. This property is mutually-exclusive + with i2c-gpio,sda-open-drain. + + i2c-gpio,scl-has-no-pullup: + type: boolean + description: scl is used in a non-compliant way and has no pull-up. + Therefore disable open-drain. This property is mutually-exclusive + with i2c-gpio,scl-open-drain. + +dependencies: + i2c-gpio,sda-has-no-pullup: + not: + required: + - i2c-gpio,sda-open-drain + i2c-gpio,scl-has-no-pullup: + not: + required: + - i2c-gpio,scl-open-drain + required: - compatible - sda-gpios diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index 421563bf576c..72ae2e01cf22 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -43,6 +43,10 @@ properties: - const: mediatek,mt6577-i2c - items: - enum: + - mediatek,mt8365-i2c + - const: mediatek,mt8168-i2c + - items: + - enum: - mediatek,mt8195-i2c - const: mediatek,mt8192-i2c diff --git a/Documentation/devicetree/bindings/i2c/i2c-st.txt b/Documentation/devicetree/bindings/i2c/i2c-st.txt deleted file mode 100644 index 4c26fda3844a..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-st.txt +++ /dev/null @@ -1,41 +0,0 @@ -ST SSC binding, for I2C mode operation - -Required properties : -- compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c" -- reg : Offset and length of the register set for the device -- interrupts : the interrupt specifier -- clock-names: Must contain "ssc". -- clocks: Must contain an entry for each name in clock-names. See the common - clock bindings. -- A pinctrl state named "default" must be defined to set pins in mode of - operation for I2C transfer. - -Optional properties : -- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, - the default 100 kHz frequency will be used. As only Normal and Fast modes - are supported, possible values are 100000 and 400000. -- st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is - allowed through the deglitch circuit. In units of us. -- st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is - allowed through the deglitch circuit. In units of us. -- A pinctrl state named "idle" could be defined to set pins in idle state - when I2C instance is not performing a transfer. -- A pinctrl state named "sleep" could be defined to set pins in sleep state - when driver enters in suspend. - - - -Example : - -i2c0: i2c@fed40000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0xfed40000 0x110>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_a0_ls CLK_ICN_REG>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; -}; diff --git a/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml b/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml new file mode 100644 index 000000000000..67882ec6e06a --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/loongson,ls2x-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS2X I2C Controller + +maintainers: + - Binbin Zhou <zhoubinbin@loongson.cn> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - loongson,ls2k-i2c + - loongson,ls7a-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c0: i2c@1fe21000 { + compatible = "loongson,ls2k-i2c"; + reg = <0x1fe21000 0x8>; + interrupt-parent = <&extioiic>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c16"; + reg = <0x57>; + pagesize = <16>; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index cf9f8fda595f..ec79b7270437 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -12,14 +12,24 @@ maintainers: properties: compatible: - enum: - - qcom,msm8226-cci - - qcom,msm8916-cci - - qcom,msm8974-cci - - qcom,msm8996-cci - - qcom,sdm845-cci - - qcom,sm8250-cci - - qcom,sm8450-cci + oneOf: + - enum: + - qcom,msm8226-cci + - qcom,msm8974-cci + - qcom,msm8996-cci + + - items: + - enum: + - qcom,msm8916-cci + - const: qcom,msm8226-cci # CCI v1 + + - items: + - enum: + - qcom,sdm845-cci + - qcom,sm6350-cci + - qcom,sm8250-cci + - qcom,sm8450-cci + - const: qcom,msm8996-cci # CCI v2 "#address-cells": const: 1 @@ -88,10 +98,12 @@ allOf: - if: properties: compatible: - contains: - enum: - - qcom,msm8226-cci - - qcom,msm8974-cci + oneOf: + - contains: + enum: + - qcom,msm8974-cci + + - const: qcom,msm8226-cci then: properties: clocks: @@ -105,10 +117,12 @@ allOf: - if: properties: compatible: - contains: - enum: - - qcom,msm8916-cci - - qcom,msm8996-cci + oneOf: + - contains: + enum: + - qcom,msm8916-cci + + - const: qcom,msm8996-cci then: properties: clocks: @@ -126,6 +140,7 @@ allOf: contains: enum: - qcom,sdm845-cci + - qcom,sm6350-cci then: properties: clocks: @@ -169,7 +184,7 @@ examples: cci@ac4a000 { reg = <0x0ac4a000 0x4000>; - compatible = "qcom,sdm845-cci"; + compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml index c76131902b77..4bbe9e775da1 100644 --- a/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml +++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml @@ -29,6 +29,9 @@ properties: minimum: 100000 maximum: 400000 + resets: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml index ddde08636ab0..5abf496edb59 100644 --- a/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml @@ -29,6 +29,9 @@ properties: minimum: 100000 maximum: 400000 + resets: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml new file mode 100644 index 000000000000..08f9c1e446fd --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/st,sti-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C controller embedded in STMicroelectronics STi platform + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - st,comms-ssc-i2c + - st,comms-ssc4-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + clock-frequency: + enum: [ 100000, 400000 ] + default: 100000 + + st,i2c-min-scl-pulse-width-us: + description: + The minimum valid SCL pulse width that is allowed through the + deglitch circuit. In units of us. + + st,i2c-min-sda-pulse-width-us: + description: + The minimum valid SDA pulse width that is allowed through the + deglitch circuit. In units of us. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stih407-clks.h> + i2c@fed40000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed40000 0x110>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; diff --git a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml index 8d241a703d85..1b598638d457 100644 --- a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml +++ b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: xlnx,xps-iic-2.00.a + enum: + - xlnx,axi-iic-2.1 + - xlnx,xps-iic-2.00.a reg: maxItems: 1 @@ -30,6 +32,13 @@ properties: description: | Input clock name. + clock-frequency: + description: + Optional I2C SCL clock frequency. If not specified, do not configure + in software, rely only on hardware design value. + default: 100000 + enum: [ 100000, 400000, 1000000 ] + required: - compatible - reg |