1 files changed, 2 insertions, 54 deletions

diff --git a/arch/arm/mach-omap2/dpll44xx_54xx.c b/arch/arm/mach-omap2/dpll44xx_54xx.c
index 89bcd2da26bc..3cbd949f9775 100644
--- a/arch/arm/mach-omap2/dpll44xx_54xx.c
+++ b/arch/arm/mach-omap2/dpll44xx_54xx.c
@@ -14,6 +14,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <linux/emif.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
@@ -22,7 +23,7 @@
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm-regbits-44xx.h"
-#include <mach/omap4-common.h>
+#include "common.h"
 #include "cm.h"
 #include "clock44xx.h"
 #include "clock54xx.h"
@@ -285,30 +286,6 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
 	return rate;
 }
 
-long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
-{
-	u32 v;
-	struct dpll_data *dd;
-
-	if (!clk || !clk->dpll_data)
-		return -EINVAL;
-
-	dd = clk->dpll_data;
-
-	/* regm4xen adds a multiplier of 4 to DPLL calculations */
-	v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
-
-	if (v)
-		target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
-
-	omap2_dpll_round_rate(clk, target_rate);
-
-	if (v)
-		clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
-
-	return clk->dpll_data->last_rounded_rate;
-}
-
 /* Supported only on OMAP4 */
 int omap4_dpllmx_gatectrl_read(struct clk *clk)
 {
@@ -370,35 +347,6 @@ const struct clkops clkops_omap4_dpllmx_ops = {
 	.deny_idle	= omap4_dpllmx_deny_gatectrl,
 };
 
-/**
- * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
- * @clk: struct clk * of the DPLL to compute the rate for
- *
- * Compute the output rate for the OMAP4 DPLL represented by @clk.
- * Takes the REGM4XEN bit into consideration, which is needed for the
- * OMAP4 ABE DPLL.  Returns the DPLL's output rate (before M-dividers)
- * upon success, or 0 upon error.
- */
-unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
-{
-	u32 v;
-	unsigned long rate;
-	struct dpll_data *dd;
-
-	if (!clk || !clk->dpll_data)
-		return 0;
-
-	dd = clk->dpll_data;
-
-	rate = omap2_get_dpll_rate(clk);
-
-	/* regm4xen adds a multiplier of 4 to DPLL calculations */
-	v = __raw_readl(dd->control_reg);
-	if (v & OMAP4430_DPLL_REGM4XEN_MASK)
-		rate *= OMAP4430_REGM4XEN_MULT;
-
-	return rate;
-}
 
 /**
  * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit