diff options
Diffstat (limited to 'arch')
132 files changed, 20016 insertions, 404 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f6179f41566d..5dec03f1e5ae 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1371,6 +1371,25 @@ config UACCESS_WITH_MEMCPY However, if the CPU data cache is using a write-allocate mode, this option is unlikely to provide any performance gain. +config UNOFFICIAL_USER_DMA_API + bool "Enable unofficial user DMA API (READ HELP TEXT)" + depends on EXPERIMENTAL + help + This option enables the exposure of the kernel's three DMA cache + coherence functions to userspace via three ARM private syscalls. + + This API is not officially supported; it is a stop gap measure + to allow developers to achieve their goals. It doesn't take + account of any DMA restrictions which may be in the system, and + makes no attempt to work around those. + + The user is entirely responsible for coordinating the use of this + API with DMA activity and CPU snooping activity. Improper use + of this API can result in random data corruption, especially if + the memory contains DMA scatterlists. + + Use of this API will taint the kernel. + endmenu menu "Boot options" diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index 1b6cd52f5451..c0c76eaf3ed3 100644..100755 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.34 -# Wed Jul 7 13:16:21 2010 +# Sat Jul 10 05:15:05 2010 # CONFIG_ARM=y CONFIG_HAVE_PWM=y @@ -249,7 +249,10 @@ CONFIG_ARCH_OMAP4=y # CONFIG_OMAP_RESET_CLOCKS is not set # CONFIG_OMAP_MUX is not set CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MBOX_FWK is not set +CONFIG_OMAP_MBOX_FWK=y +CONFIG_OMAP_REMOTE_PROC=y +CONFIG_OMAP_RPROC_MEMPOOL_SIZE=0x600000 +CONFIG_OMAP_IOMMU=y # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 @@ -260,6 +263,8 @@ CONFIG_OMAP_PM_NOOP=y # # OMAP Board Type # +# CONFIG_WIFI_CONTROL_FUNC is not set +# CONFIG_TIWLAN_SDIO is not set # CONFIG_OMAP4_ES1 is not set CONFIG_MACH_OMAP_4430SDP=y # CONFIG_ERRATA_OMAP4_AXI2OCP is not set @@ -352,6 +357,7 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_LEDS is not set CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_UNOFFICIAL_USER_DMA_API=y # # Boot options @@ -465,7 +471,24 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set -# CONFIG_BT is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +# CONFIG_BT_BNEP is not set +# CONFIG_BT_HIDP is not set + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +# CONFIG_BT_HCIUART_H4 is not set +# CONFIG_BT_HCIUART_BCSP is not set +CONFIG_BT_HCIUART_LL=y +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set # CONFIG_AF_RXRPC is not set # CONFIG_WIRELESS is not set # CONFIG_WIMAX is not set @@ -484,7 +507,9 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -528,6 +553,13 @@ CONFIG_BMP085=y # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +CONFIG_TI_ST=m +CONFIG_TI_ST_BT=m +CONFIG_TI_ST_FM=m CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -657,7 +689,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_TWL4030_PWRBUTTON is not set # CONFIG_INPUT_TWL4030_VIBRA is not set -# CONFIG_INPUT_UINPUT is not set +CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set CONFIG_INPUT_SFH7741=y CONFIG_INPUT_CMA3000_I2C=y @@ -943,27 +975,204 @@ CONFIG_REGULATOR_TWL4030=y # CONFIG_REGULATOR_LP3971 is not set # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_MEDIA_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_IR_CORE=y +CONFIG_VIDEO_IR=y +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_SG=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_IR_I2C=y +# CONFIG_VIDEO_VIVI is not set +CONFIG_VIDEO_OMAP2_VOUT=y +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_DAB is not set +CONFIG_DMM_OMAP=y +CONFIG_TILER_OMAP=y # # Graphics support # # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_OMAP2_VRAM=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_VRAM_SIZE=4 +CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y +# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set +CONFIG_OMAP2_DSS_DPI=y +# CONFIG_OMAP2_DSS_RFBI is not set +# CONFIG_OMAP2_DSS_VENC is not set +CONFIG_OMAP2_DSS_HDMI=y +CONFIG_OMAP2_DSS_DSI=y +# CONFIG_OMAP2_DSS_USE_DSI_PLL is not set +CONFIG_OMAP2_DSS_FAKE_VSYNC=y +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 +CONFIG_FB_OMAP2=y +CONFIG_FB_OMAP2_DEBUG_SUPPORT=y +CONFIG_FB_OMAP2_NUM_FBS=2 + +# +# OMAP2/3 Display Device Drivers +# +# CONFIG_PANEL_GENERIC is not set +# CONFIG_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set +CONFIG_PANEL_PICO_DLP=y +CONFIG_PANEL_TAAL=y +# CONFIG_PANEL_TOPPOLY_TDO35S is not set +# CONFIG_PANEL_TPO_TD043MTEA1 is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_PWM is not set # # Display device support # -# CONFIG_DISPLAY_SUPPORT is not set +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# # # Console display driver support # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_SOUND is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_SPI=y +CONFIG_SND_SOC=y +CONFIG_SND_OMAP_SOC=y +CONFIG_SND_OMAP_SOC_MCBSP=y +CONFIG_OMAP_MCPDM=y +CONFIG_SND_OMAP_SOC_ABE=y +CONFIG_SND_OMAP_SOC_SDP4430=y +CONFIG_SND_OMAP_SOC_HDMI=y +# CONFIG_SND_OMAP_VOICE_TEST is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_ABE_TWL6040=y +# CONFIG_SOUND_PRIME is not set # CONFIG_HID_SUPPORT is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -1198,6 +1407,16 @@ CONFIG_SENSORS_HMC5843=y # CONFIG_RAMZSWAP is not set # CONFIG_BATMAN_ADV is not set # CONFIG_STRIP is not set +# CONFIG_FB_SM7XX is not set +CONFIG_Sys_Link=y +CONFIG_SYSLINK_PROC=y +CONFIG_SYSLINK_PROC4430=y +CONFIG_DUCATI_BASEIMAGE_PHYS_ADDR=0x9CF00000 +CONFIG_SYSLINK_DUCATI_PM=y +CONFIG_MPU_SYSLINK_PLATFORM=y +CONFIG_MPU_SYSLINK_IPC=y +CONFIG_SYSLINK_USE_SYSMGR=y +CONFIG_OMAP_IOMMU_DEBUG_MODULE=y # # File systems @@ -1557,7 +1776,7 @@ CONFIG_CRYPTO_HW=y CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y diff --git a/arch/arm/configs/omap_4430simulator_defconfig b/arch/arm/configs/omap_4430simulator_defconfig new file mode 100644 index 000000000000..6274bb1c53e0 --- /dev/null +++ b/arch/arm/configs/omap_4430simulator_defconfig @@ -0,0 +1,1017 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc9 +# Thu Oct 1 15:58:54 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y + +# +# TI OMAP Implementations +# +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2 is not set +# CONFIG_ARCH_OMAP3 is not set +CONFIG_ARCH_OMAP4=y + +# +# OMAP Feature Selections +# +# CONFIG_OMAP_RESET_CLOCKS is not set +CONFIG_OMAP_MUX=y +CONFIG_OMAP_MCBSP=y +CONFIG_OMAP_MBOX_FWK=y +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +CONFIG_OMAP_DM_TIMER=y +CONFIG_OMAP_LL_DEBUG_UART1=y +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +# CONFIG_OMAP_LL_DEBUG_UART3 is not set + +# +# OMAP Board Type +# +CONFIG_MACH_OMAP_4430SDP=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_ARM_ERRATA_484863=y + +CONFIG_ARM_GIC=y +# CONFIG_OMAP_L2_EVENT_DEBUG is not set +CONFIG_OMAP4_SUDO_ROMCODE=y +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_SMP=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +# CONFIG_LOCAL_TIMERS is not set +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480 loglevel=1" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=y +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_OMAP=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_SPI=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +CONFIG_I2C_OMAP=y +CONFIG_SPI_OMAP24XX=y +CONFIG_SPI_MASTER=y +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_OMAP_WATCHDOG=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_SSB_POSSIBLE=y + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MEDIA_SUPPORT is not set +CONFIG_TWL6030_CORE=y + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=m +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_OMAP=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SOC=y + +# +# OMAP 44xx high speed USB support +# +# CONFIG_USB_MUSB_HOST is not set +CONFIG_USB_MUSB_PERIPHERAL=y +# CONFIG_USB_MUSB_OTG is not set +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_MUSB_DEBUG=y + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP_HS=y +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_TWL=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_TWL=y +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index d3730f0f4b50..9792a717174a 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -198,6 +198,21 @@ * DMA Cache Coherency * =================== * + * dma_inv_range(start, end) + * + * Invalidate (discard) the specified virtual address range. + * May not write back any entries. If 'start' or 'end' + * are not cache line aligned, those lines must be written + * back. + * - start - virtual start address + * - end - virtual end address + * + * dma_clean_range(start, end) + * + * Clean (write back) the specified virtual address range. + * - start - virtual start address + * - end - virtual end address + * * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. @@ -217,6 +232,8 @@ struct cpu_cache_fns { void (*dma_map_area)(const void *, size_t, int); void (*dma_unmap_area)(const void *, size_t, int); + void (*dma_inv_range)(const void *, const void *); + void (*dma_clean_range)(const void *, const void *); void (*dma_flush_range)(const void *, const void *); }; @@ -242,6 +259,8 @@ extern struct cpu_cache_fns cpu_cache; */ #define dmac_map_area cpu_cache.dma_map_area #define dmac_unmap_area cpu_cache.dma_unmap_area +#define dmac_inv_range cpu_cache.dma_inv_range +#define dmac_clean_range cpu_cache.dma_clean_range #define dmac_flush_range cpu_cache.dma_flush_range #else @@ -268,10 +287,14 @@ extern void __cpuc_flush_dcache_area(void *, size_t); */ #define dmac_map_area __glue(_CACHE,_dma_map_area) #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) +#define dmac_inv_range __glue(_CACHE,_dma_inv_range) +#define dmac_clean_range __glue(_CACHE,_dma_clean_range) #define dmac_flush_range __glue(_CACHE,_dma_flush_range) extern void dmac_map_area(const void *, size_t, int); extern void dmac_unmap_area(const void *, size_t, int); +extern void dmac_inv_range(const void *, const void *); +extern void dmac_clean_range(const void *, const void *); extern void dmac_flush_range(const void *, const void *); #endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index c980156f3263..ea6123b8fcc3 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -79,6 +79,9 @@ extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int, extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int); +extern void __iomem * __arm_multi_strided_ioremap(int, unsigned long *, + size_t *,unsigned long *, unsigned long *, unsigned int); + extern void __iounmap(volatile void __iomem *addr); /* diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index dd2bf53000fe..f4e4726985fc 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -407,7 +407,17 @@ * *NOTE*: This is a ghost syscall private to the kernel. Only the * __kuser_cmpxchg code in entry-armv.S should be aware of its * existence. Don't ever use this from user code. +======= + * These are temporary interfaces; they are a stop gap until we get + * a proper solution to DMA. These won't always work for every + * device. Only use these IF you *really* know what you're doing. + * Don't be surprised if they go away in later kernels. +>>>>>>> ARM: UNOFFICIAL_USER_DMA_API:arch/arm/include/asm/unistd.h */ +#define __ARM_NR_temp_dma_inv_range (__ARM_NR_BASE+0x0007fd) +#define __ARM_NR_temp_dma_clean_range (__ARM_NR_BASE+0x0007fe) +#define __ARM_NR_temp_dma_flush_range (__ARM_NR_BASE+0x0007ff) + #ifdef __KERNEL__ #define __ARM_NR_cmpxchg (__ARM_NR_BASE+0x00fff0) #endif diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 056b2a9f1be8..0330a4058e1d 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -437,7 +437,7 @@ static int bad_syscall(int n, struct pt_regs *regs) return regs->ARM_r0; } -static inline void +static void do_cache_op(unsigned long start, unsigned long end, int flags) { struct mm_struct *mm = current->active_mm; @@ -532,6 +532,22 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) #endif return 0; +#ifdef CONFIG_UNOFFICIAL_USER_DMA_API + /* + * These are temporary interfaces; they are a stop gap until we get + * a proper solution to DMA. These won't always work for every + * device. Only use these IF you *really* know what you're doing. + * Don't be surprised if they go away in later kernels. + */ + case NR(temp_dma_inv_range): + case NR(temp_dma_clean_range): + case NR(temp_dma_flush_range): + { + extern int temp_user_dma_op(unsigned long, unsigned long, int); + return temp_user_dma_op(regs->ARM_r0, regs->ARM_r1, no & 3); + } +#endif + #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG /* * Atomically store r1 in *r2 if *r2 is equal to r0 for user space. diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 2ae09b48df84..c54cae27444b 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -79,6 +79,32 @@ config MACH_OMAP3EVM depends on ARCH_OMAP3 select OMAP_PACKAGE_CBB +config WIFI_CONTROL_FUNC + bool "Enable WiFi control function abstraction" + depends on MACH_OMAP_4430SDP + select WIRELESS_EXT + select WEXT_CORE + select WEXT_PROC + select WEXT_PRIV + default Y + help + Enables Power/Reset/Carddetect function abstraction +config TIWLAN_SDIO + bool "TI WLAN Enhanced SDIO Contoller support" + depends on MMC_OMAP || MMC_OMAP_MODULE || MMC_OMAP_HS || MMC_OMAP_HS_MODULE + help + Say Y here if you want to be able to use TI's WLAN device using the + SDIO interface. If unsure, say N. +config TIWLAN_MMC_CONTROLLER + int "MMC Controller number that TI WLAN chip is connected to" + range 1 5 + depends on TIWLAN_SDIO + default "5" + help + Choose the number of the MMC controller that TI WLAN chip is + connected to. TI WLAN has SDIO host controller that will control + this MMC port. + config MACH_OMAP3517EVM bool "OMAP3517/ AM3517 EVM board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 13825a2ff2e9..0ab62c2082a2 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -106,11 +106,20 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o -iommu-y += iommu2.o -iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o - +ifeq ($(CONFIG_OMAP_REMOTE_PROC),y) +obj-$(CONFIG_ARCH_OMAP2) += remoteproc24xx.o +obj-$(CONFIG_ARCH_OMAP3) += remoteproc3xxx.o +obj-$(CONFIG_ARCH_OMAP4) += remoteproc44xx.o +endif +iommu-y += iommu2.o omap-iommu.o obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) +ifeq ($(CONFIG_OMAP_REMOTE_PROC),y) +obj-$(CONFIG_ARCH_OMAP2) += remoteproc24xx.o +obj-$(CONFIG_ARCH_OMAP3) += remoteproc3xxx.o +obj-$(CONFIG_ARCH_OMAP4) += remoteproc44xx.o +endif + i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) @@ -159,6 +168,7 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ hsmmc.o +obj-$(CONFIG_TIWLAN_SDIO) += board-4430sdp-wifi.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o diff --git a/arch/arm/mach-omap2/board-4430sdp-wifi.c b/arch/arm/mach-omap2/board-4430sdp-wifi.c new file mode 100644 index 000000000000..b13e9fc3767a --- /dev/null +++ b/arch/arm/mach-omap2/board-4430sdp-wifi.c @@ -0,0 +1,138 @@ +/* + * Board support file for containing WiFi specific details for OMAP4430 SDP. + * + * Copyright (C) 2009 Texas Instruments + * + * Author: Pradeep Gurumath <pradeepgurumath@ti.com> + * + * Based on mach-omap2/board-3430sdp.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* linux/arch/arm/mach-omap2/board-4430sdp-wifi.c +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sdio_ids.h> +#include <linux/err.h> + +#include <asm/gpio.h> +#include <asm/io.h> +#include <plat/wifi_tiwlan.h> + +#define SDP4430_WIFI_PMENA_GPIO 54 +#define SDP4430_WIFI_IRQ_GPIO 53 + +static int sdp4430_wifi_cd; /* WIFI virtual 'card detect' status */ +static void (*wifi_status_cb)(int card_present, void *dev_id); +static void *wifi_status_cb_devid; + +int omap_wifi_status_register(void (*callback)(int card_present, + void *dev_id), void *dev_id) +{ + if (wifi_status_cb) + return -EAGAIN; + wifi_status_cb = callback; + + wifi_status_cb_devid = dev_id; + + return 0; +} + +int omap_wifi_status(int irq) +{ + return sdp4430_wifi_cd; +} + +int sdp4430_wifi_set_carddetect(int val) +{ + printk(KERN_WARNING"%s: %d\n", __func__, val); + sdp4430_wifi_cd = val; + if (wifi_status_cb) + wifi_status_cb(val, wifi_status_cb_devid); + else + printk(KERN_WARNING "%s: Nobody to notify\n", __func__); + return 0; +} +#ifndef CONFIG_WIFI_CONTROL_FUNC +EXPORT_SYMBOL(sdp4430_wifi_set_carddetect); +#endif + +static int sdp4430_wifi_power_state; + +int sdp4430_wifi_power(int on) +{ + printk(KERN_WARNING"%s: %d\n", __func__, on); + gpio_set_value(SDP4430_WIFI_PMENA_GPIO, on); + sdp4430_wifi_power_state = on; + return 0; +} +#ifndef CONFIG_WIFI_CONTROL_FUNC +EXPORT_SYMBOL(sdp4430_wifi_power); +#endif + +static int sdp4430_wifi_reset_state; +int sdp4430_wifi_reset(int on) +{ + printk(KERN_WARNING"%s: %d\n", __func__, on); + sdp4430_wifi_reset_state = on; + return 0; +} +#ifndef CONFIG_WIFI_CONTROL_FUNC +EXPORT_SYMBOL(sdp4430_wifi_reset); +#endif + +struct wifi_platform_data sdp4430_wifi_control = { + .set_power = sdp4430_wifi_power, + .set_reset = sdp4430_wifi_reset, + .set_carddetect = sdp4430_wifi_set_carddetect, +}; + +#ifdef CONFIG_WIFI_CONTROL_FUNC +static struct resource sdp4430_wifi_resources[] = { + [0] = { + .name = "device_wifi_irq", + .start = OMAP_GPIO_IRQ(SDP4430_WIFI_IRQ_GPIO), + .end = OMAP_GPIO_IRQ(SDP4430_WIFI_IRQ_GPIO), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, + }, +}; + +static struct platform_device sdp4430_wifi_device = { + .name = "device_wifi", + .id = 1, + .num_resources = ARRAY_SIZE(sdp4430_wifi_resources), + .resource = sdp4430_wifi_resources, + .dev = { + .platform_data = &sdp4430_wifi_control, + }, +}; +#endif + +static int __init sdp4430_wifi_init(void) +{ + int ret; + + printk(KERN_WARNING"%s: start\n", __func__); + ret = gpio_request(SDP4430_WIFI_IRQ_GPIO, "wifi_irq"); + if (ret < 0) { + printk(KERN_ERR "%s: can't reserve GPIO: %d\n", __func__, + SDP4430_WIFI_IRQ_GPIO); + goto out; + } + gpio_direction_input(SDP4430_WIFI_IRQ_GPIO); +#ifdef CONFIG_WIFI_CONTROL_FUNC + ret = platform_device_register(&sdp4430_wifi_device); +#endif +out: + return ret; +} + +device_initcall(sdp4430_wifi_init); diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 0439e17db27b..6ef0095f6ce1 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -38,6 +38,8 @@ #include <plat/common.h> #include <plat/control.h> #include <plat/timer-gp.h> +#include <plat/display.h> +#include <linux/delay.h> #include <plat/usb.h> #include <plat/omap_device.h> #include <plat/omap_hwmod.h> @@ -361,8 +363,6 @@ error1: return status; } -/* Begin Synaptic Touchscreen TM-01217 */ - static char *tm12xx_idev_names[] = { "Synaptic TM12XX TouchPoint 1", "Synaptic TM12XX TouchPoint 2", @@ -396,20 +396,245 @@ static struct tm12xx_ts_platform_data tm12xx_platform_data[] = { .swap_xy = 1, }, }; +/* Begin Synaptic Touchscreen TM-01217 */ +static int sdp4430_taal_enable(struct omap_dss_device *dssdev) +{ + if (dssdev->channel == OMAP_DSS_CHANNEL_LCD) { + gpio_request(102, "dsi1_en_gpio"); /* DSI1_GPIO_102*/ + gpio_direction_output(102, 0); + mdelay(500); + gpio_set_value(102, 1); + mdelay(500); + gpio_set_value(102, 0); + mdelay(500); + gpio_set_value(102, 1); + + twl_i2c_write_u8(TWL_MODULE_PWM, 0xFF, 0x03); + twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, 0x04); + twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x30, 0x92); + + gpio_request(27, "dsi1_bl_gpio"); /*DSI1_GPIO_27*/ + gpio_direction_output(27, 1); + mdelay(120); + gpio_set_value(27, 0); + mdelay(120); + gpio_set_value(27, 1); + } else { + gpio_request(104, "dsi2_en_gpio"); /* DSI2_GPIO_104 */ + gpio_direction_output(104, 0); + mdelay(500); + gpio_set_value(104, 1); + mdelay(500); + gpio_set_value(104, 0); + mdelay(500); + gpio_set_value(104, 1); + + twl_i2c_write_u8(TWL_MODULE_PWM, 0xFF, 0x03); + twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, 0x04); + twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x30, 0x92); + + gpio_request(59, "dsi2_bl_gpio"); /* DSI2_GPIO_59 */ + gpio_direction_output(59, 1); + mdelay(120); + gpio_set_value(59, 0); + mdelay(120); + gpio_set_value(59, 1); + } + return 0; +} -/* End Synaptic Touchscreen TM-01217 */ +static void sdp4430_taal_disable(struct omap_dss_device *dssdev) +{ + if (dssdev->channel == OMAP_DSS_CHANNEL_LCD) { + gpio_set_value(102, 1); /*DSI1_GPIO_102*/ + gpio_set_value(27, 0); /*DSI1_GPIO_27*/ + } else { + gpio_set_value(104, 1); /* DSI2_GPIO_104 */ + gpio_set_value(59, 0); /* DSI2_GPIO_59 */ + } +} -static struct platform_device sdp4430_lcd_device = { - .name = "sdp4430_lcd", - .id = -1, +static struct omap_dss_device sdp4430_lcd_device = { + .name = "lcd", + .driver_name = "taal", + .type = OMAP_DISPLAY_TYPE_DSI, + .reset_gpio = 102, + .phy.dsi = { + .clk_lane = 1, + .clk_pol = 0, + .data1_lane = 2, + .data1_pol = 0, + .data2_lane = 3, + .data2_pol = 0, + .ext_te = true, + .ext_te_gpio = 101, + .div = { + .lck_div = 1, + .pck_div = 6, + .regm = 200, + .regn = 19, + .regm3 = 4, + .regm4 = 5, + .lp_clk_div = 6, + }, + }, + .platform_enable = sdp4430_taal_enable, + .platform_disable = sdp4430_taal_disable, + .channel = OMAP_DSS_CHANNEL_LCD, }; -static struct platform_device *sdp4430_devices[] __initdata = { +static struct omap_dss_device sdp4430_lcd2_device = { + .name = "2lcd", + .driver_name = "taal2", + .type = OMAP_DISPLAY_TYPE_DSI, + .reset_gpio = 102, + .phy.dsi = { + .clk_lane = 1, + .clk_pol = 0, + .data1_lane = 2, + .data1_pol = 0, + .data2_lane = 3, + .data2_pol = 0, + .ext_te = true, + .ext_te_gpio = 103, + .div = { + .lck_div = 1, + .pck_div = 6, + .regm = 200, + .regn = 19, + .regm3 = 4, + .regm4 = 5, + .lp_clk_div = 6, + }, + }, + .platform_enable = sdp4430_taal_enable, + .platform_disable = sdp4430_taal_disable, + .channel = OMAP_DSS_CHANNEL_LCD2, + }; + +static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) +{ + gpio_request(HDMI_GPIO_60 , "hdmi_gpio_60"); + gpio_request(HDMI_GPIO_41 , "hdmi_gpio_41"); + gpio_direction_output(HDMI_GPIO_60, 0); + gpio_direction_output(HDMI_GPIO_41, 0); + gpio_set_value(HDMI_GPIO_60, 1); + gpio_set_value(HDMI_GPIO_41, 1); + gpio_set_value(HDMI_GPIO_60, 0); + gpio_set_value(HDMI_GPIO_41, 0); + gpio_set_value(HDMI_GPIO_60, 1); + gpio_set_value(HDMI_GPIO_41, 1); + return 0; +} + +static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) +{ + gpio_set_value(HDMI_GPIO_60, 1); + gpio_set_value(HDMI_GPIO_41, 1); + +} + +static __attribute__ ((unused)) void __init sdp4430_hdmi_init(void) +{ + return; +} + +static struct omap_dss_device sdp4430_hdmi_device = { + .name = "hdmi", + .driver_name = "hdmi_panel", + .type = OMAP_DISPLAY_TYPE_HDMI, + .phy.dpi.data_lines = 24, + .platform_enable = sdp4430_panel_enable_hdmi, + .platform_disable = sdp4430_panel_disable_hdmi, +}; + +static int sdp4430_panel_enable_pico_DLP(struct omap_dss_device *dssdev) +{ + int i = 0; + gpio_request(DLP_4430_GPIO_59, "DLP DISPLAY SEL"); + gpio_direction_output(DLP_4430_GPIO_59, 0); + gpio_request(DLP_4430_GPIO_45, "DLP PARK"); + gpio_direction_output(DLP_4430_GPIO_45, 0); + gpio_request(DLP_4430_GPIO_40, "DLP PHY RESET"); + gpio_direction_output(DLP_4430_GPIO_40, 0); + gpio_request(DLP_4430_GPIO_44, "DLP READY RESET"); + gpio_direction_input(DLP_4430_GPIO_44); + mdelay(500); + + gpio_set_value(DLP_4430_GPIO_59, 1); + gpio_set_value(DLP_4430_GPIO_45, 1); + mdelay(1000); + + gpio_set_value(DLP_4430_GPIO_40, 1); + mdelay(1000); + + /*FIXME with the MLO gpio changes , gpio read is not retuning correct value even though it is set in hardware so the check is comment till the problem is fixed */ + /*while(i == 0){ + i=gpio_get_value(DLP_4430_GPIO_44); + printk("wait for ready bit %d\n",i); + }*/ + printk("%d ready bit ", i); + mdelay(2000); + return 0; +} + +static void sdp4430_panel_disable_pico_DLP(struct omap_dss_device *dssdev) +{ + gpio_set_value(DLP_4430_GPIO_40, 0); + gpio_set_value(DLP_4430_GPIO_45, 0); + +} + +static struct omap_dss_device sdp4430_picoDLP_device = { + .name = "pico_DLP", + .driver_name = "picoDLP_panel", + .type = OMAP_DISPLAY_TYPE_DPI, + .phy.dpi.data_lines = 24, + .platform_enable = sdp4430_panel_enable_pico_DLP, + .platform_disable = sdp4430_panel_disable_pico_DLP, + .channel = OMAP_DSS_CHANNEL_LCD2, +}; + +/* wl128x BT, FM, GPS connectivity chip */ +static int gpios[] = {55, -1, -1}; +static struct platform_device wl128x_device = { + .name = "kim", + .id = -1, + .dev.platform_data = &gpios, +}; + +static struct omap_dss_device *sdp4430_dss_devices[] = { &sdp4430_lcd_device, + &sdp4430_lcd2_device, +#ifdef CONFIG_OMAP2_DSS_HDMI + &sdp4430_hdmi_device, +#endif +#ifdef CONFIG_PANEL_PICO_DLP + &sdp4430_picoDLP_device, +#endif +}; + +static struct omap_dss_board_info sdp4430_dss_data = { + .num_devices = ARRAY_SIZE(sdp4430_dss_devices), + .devices = sdp4430_dss_devices, + .default_device = &sdp4430_lcd_device, +}; + +static struct platform_device sdp4430_dss_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = &sdp4430_dss_data, + }, +}; + +static struct platform_device *sdp4430_devices[] __initdata = { + &sdp4430_dss_device, &sdp4430_keypad_device, &sdp4430_proximity_device, &sdp4430_leds_gpio, &sdp4430_leds_pwm, + &wl128x_device, }; static struct omap_lcd_config sdp4430_lcd_config __initdata = { @@ -534,6 +759,13 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) for (c = controllers; c->mmc; c++) omap4_twl6030_hsmmc_set_late_init(c->dev); +#ifdef CONFIG_TIWLAN_SDIO + /* The controller that is connected to the 128x device + should hould have the card detect gpio disabled. This is + achieved by initializing it with a negative value */ + c[CONFIG_TIWLAN_MMC_CONTROLLER - 1].gpio_cd = -EINVAL; +#endif + return 0; } @@ -680,6 +912,17 @@ static struct twl4030_bci_platform_data sdp4430_bci_data = { .low_bat_voltagemV = 3300, }; +static struct twl4030_codec_data twl6040_codec = { +#ifdef CONFIG_OMAP4_AUDIO_PWRON + .audpwron_gpio = 127, +#else + /* provide GPIO number above the valid value + * to mean there is no GPIO connected. */ + .audpwron_gpio = 1024, + .naudint_irq = OMAP44XX_IRQ_SYS_2N, +#endif +}; + static struct twl4030_platform_data sdp4430_twldata = { .irq_base = TWL6030_IRQ_BASE, .irq_end = TWL6030_IRQ_END, @@ -697,6 +940,9 @@ static struct twl4030_platform_data sdp4430_twldata = { .vaux3 = &sdp4430_vaux3, .madc = &sdp4430_gpadc_data, .bci = &sdp4430_bci_data, + + /* children */ + .codec = &twl6040_codec, }; static struct bq2415x_platform_data sdp4430_bqdata = { @@ -716,6 +962,12 @@ static struct cma3000_platform_data cma3000_platform_data = { .irqflags = IRQF_TRIGGER_HIGH, }; +static struct pico_platform_data picodlp_platform_data[] = { + [0] = { /* DLP Controller */ + .gpio_intr = 40, + }, +}; + static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { { I2C_BOARD_INFO("twl6030", 0x48), @@ -734,6 +986,10 @@ static struct i2c_board_info __initdata sdp4430_i2c_2_boardinfo[] = { I2C_BOARD_INFO("tm12xx_ts_primary", 0x4b), .platform_data = &tm12xx_platform_data[0], }, + { + I2C_BOARD_INFO("picoDLP_i2c_driver", 0x1b), + .platform_data = &picodlp_platform_data[0], + }, }; static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { @@ -827,6 +1083,38 @@ fail1: gpio_free(OMAP4_SFH7741_SENSOR_OUTPUT_GPIO); } +#ifdef CONFIG_TIWLAN_SDIO +static void pad_config(unsigned long pad_addr, u32 andmask, u32 ormask) +{ + int val; + u32 *addr; + + addr = (u32 *) ioremap(pad_addr, 4); + if (!addr) { + printk(KERN_ERR"OMAP_pad_config: ioremap failed with addr %lx\n", + pad_addr); + return; + } + + val = __raw_readl(addr); + val &= andmask; + val |= ormask; + __raw_writel(val, addr); + + iounmap(addr); +} + +void wlan_1283_config() +{ + pad_config(0x4A100078, 0xFFECFFFF, 0x00030000); + pad_config(0x4A10007C, 0xFFFFFFEF, 0x0000000B); + if (gpio_request(54, NULL) != 0) + printk(KERN_ERR "GPIO 54 request failed\n"); + gpio_direction_output(54, 0); + return ; +} +#endif + static void omap_cma3000accl_init(void) { if (gpio_request(OMAP4_CMA3000ACCL_GPIO, "Accelerometer") < 0) { @@ -836,14 +1124,28 @@ static void omap_cma3000accl_init(void) gpio_direction_input(OMAP4_CMA3000ACCL_GPIO); } +static void __init omap4_display_init(void) +{ + void __iomem *phymux_base = NULL; + unsigned int dsimux = 0xFFFFFFFF; + phymux_base = ioremap(0x4A100000, 0x1000); + /* Turning on DSI PHY Mux*/ + __raw_writel(dsimux, phymux_base+0x618); + dsimux = __raw_readl(phymux_base+0x618); +} + static void __init omap_4430sdp_init(void) { int status; omap4_i2c_init(); + omap4_display_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); +#ifdef CONFIG_TIWLAN_SDIO + wlan_1283_config(); +#endif /* OMAP4 SDP uses internal transceiver so register nop transceiver */ usb_nop_xceiv_register(); usb_musb_init(&musb_board_data); diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 7f862ac1b8de..40440913e7c0 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -733,6 +733,58 @@ static inline void omap_hdq_init(void) static inline void omap_hdq_init(void) {} #endif +/*---------------------------------------------------------------------------*/ + +#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ + defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) +#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) +#ifdef CONFIG_ARCH_OMAP4 +static struct resource omap_vout_resource[4 - CONFIG_FB_OMAP2_NUM_FBS] = { +#else +static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { +#endif +}; +#else +#ifdef CONFIG_ARCH_OMAP4 +static struct resource omap_vout_resource[3] = { +#else +static struct resource omap_vout_resource[2] = { +#endif +}; +#endif + +static struct platform_device omap_vout_device = { + .name = "omap_vout", + .num_resources = ARRAY_SIZE(omap_vout_resource), + .resource = &omap_vout_resource[0], + .id = -1, +}; +static void omap_init_vout(void) +{ + if (platform_device_register(&omap_vout_device) < 0) + printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); +} + +static struct resource sdp4430_wb_resource[1] = { +}; + +static struct platform_device sdp4430_wb_device = { + .name = "omap_wb", + .num_resources = ARRAY_SIZE(sdp4430_wb_resource), + .resource = &sdp4430_wb_resource[0], + .id = -1, +}; + +static void omap_init_wb(void) +{ + (void) platform_device_register(&sdp4430_wb_device); +} + +#else +static inline void omap_init_vout(void) {} +static void omap_init_wb(void) {} +#endif + /*-------------------------------------------------------------------------*/ static int __init omap2_init_devices(void) @@ -747,6 +799,9 @@ static int __init omap2_init_devices(void) omap_hdq_init(); omap_init_sti(); omap_init_sha1_md5(); + omap_init_vout(); + if (cpu_is_omap44xx()) + omap_init_wb(); return 0; } diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 6a6dd3e7a772..215bb3fadabb 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -19,6 +19,11 @@ #include <plat/omap-pm.h> #include <plat/omap_device.h> +#ifdef CONFIG_TIWLAN_SDIO +#include <linux/mmc/sdio_ids.h> +#include <linux/mmc/sdio_func.h> +#endif + #include "hsmmc.h" #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) @@ -197,6 +202,30 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot, static struct omap_mmc_platform_data *hsmmc_data[OMAP44XX_NR_MMC] __initdata; +#ifdef CONFIG_TIWLAN_SDIO +static struct sdio_embedded_func wifi_func_array[] = { + { + .f_class = SDIO_CLASS_BT_A, + .f_maxblksize = 512, + }, + { + .f_class = SDIO_CLASS_WLAN, + .f_maxblksize = 512, + }, +}; + +static struct embedded_sdio_data omap_wifi_emb_data = { + .cis = { + .vendor = SDIO_VENDOR_ID_TI, + .device = SDIO_DEVICE_ID_TI_WL12xx, + .blksize = 512, + .max_dtr = 24000000, + }, + .funcs = wifi_func_array, + .quirks = MMC_QUIRK_VDD_165_195 | MMC_QUIRK_LENIENT_FUNC0, +}; +#endif + void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { struct omap2_hsmmc_info *c; @@ -254,6 +283,16 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) else snprintf(hc->name, ARRAY_SIZE(hc->name), "mmc%islot%i", c->mmc, 1); + +#ifdef CONFIG_TIWLAN_SDIO + if (c->mmc == CONFIG_TIWLAN_MMC_CONTROLLER) { + mmc->slots[0].embedded_sdio = &omap_wifi_emb_data; + mmc->slots[0].register_status_notify = + &omap_wifi_status_register; + mmc->slots[0].card_detect = &omap_wifi_status; + } +#endif + mmc->slots[0].name = hc->name; mmc->nr_slots = 1; mmc->slots[0].wires = c->wires; @@ -327,6 +366,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) /* TODO Update required */ mmc->slots[0].before_set_reg = NULL; mmc->slots[0].after_set_reg = NULL; +#ifdef CONFIG_TIWLAN_SDIO + mmc->slots[0].ocr_mask = MMC_VDD_165_195; +#endif break; default: pr_err("MMC%d configuration not supported!\n", c->mmc); diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8d89e2..abaaa753dc53 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -25,6 +25,12 @@ struct omap2_hsmmc_info { void (*remux)(struct device *dev, int slot, int power_on); }; +#ifdef CONFIG_TIWLAN_SDIO +int omap_wifi_status_register(void (*callback)(int card_present, + void *dev_id), void *dev_id); +int omap_wifi_status(int irq); +#endif + #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) void omap2_hsmmc_init(struct omap2_hsmmc_info *); diff --git a/arch/arm/mach-omap2/include/mach/dmm.h b/arch/arm/mach-omap2/include/mach/dmm.h new file mode 100644 index 000000000000..700f08aefbc4 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/dmm.h @@ -0,0 +1,126 @@ +/* + * dmm.h + * + * DMM driver support functions for TI OMAP processors. + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef DMM_H +#define DMM_H + +#define DMM_BASE 0x4E000000 +#define DMM_SIZE 0x800 + +#define DMM_REVISION 0x000 +#define DMM_HWINFO 0x004 +#define DMM_LISA_HWINFO 0x008 +#define DMM_DMM_SYSCONFIG 0x010 +#define DMM_LISA_LOCK 0x01C +#define DMM_LISA_MAP__0 0x040 +#define DMM_LISA_MAP__1 0x044 +#define DMM_TILER_HWINFO 0x208 +#define DMM_TILER_OR__0 0x220 +#define DMM_TILER_OR__1 0x224 +#define DMM_PAT_HWINFO 0x408 +#define DMM_PAT_GEOMETRY 0x40C +#define DMM_PAT_CONFIG 0x410 +#define DMM_PAT_VIEW__0 0x420 +#define DMM_PAT_VIEW__1 0x424 +#define DMM_PAT_VIEW_MAP__0 0x440 +#define DMM_PAT_VIEW_MAP_BASE 0x460 +#define DMM_PAT_IRQ_EOI 0x478 +#define DMM_PAT_IRQSTATUS_RAW 0x480 +#define DMM_PAT_IRQSTATUS 0x490 +#define DMM_PAT_IRQENABLE_SET 0x4A0 +#define DMM_PAT_IRQENABLE_CLR 0x4B0 +#define DMM_PAT_STATUS__0 0x4C0 +#define DMM_PAT_STATUS__1 0x4C4 +#define DMM_PAT_STATUS__2 0x4C8 +#define DMM_PAT_STATUS__3 0x4CC +#define DMM_PAT_DESCR__0 0x500 +#define DMM_PAT_AREA__0 0x504 +#define DMM_PAT_CTRL__0 0x508 +#define DMM_PAT_DATA__0 0x50C +#define DMM_PEG_HWINFO 0x608 +#define DMM_PEG_PRIO 0x620 +#define DMM_PEG_PRIO_PAT 0x640 + +/** + * PAT refill programming mode. + */ +enum pat_mode { + MANUAL, + AUTO +}; + +/** + * Area definition for DMM physical address translator. + */ +struct pat_area { + s32 x0:8; + s32 y0:8; + s32 x1:8; + s32 y1:8; +}; + +/** + * DMM physical address translator control. + */ +struct pat_ctrl { + s32 start:4; + s32 dir:4; + s32 lut_id:8; + s32 sync:12; + s32 ini:4; +}; + +/** + * PAT descriptor. + */ +struct pat { + struct pat *next; + struct pat_area area; + struct pat_ctrl ctrl; + u32 data; +}; + +/** + * DMM device data + */ +struct dmm { + void __iomem *base; +}; + +/** + * Create and initialize the physical address translator. + * @param id PAT id + * @return pointer to device data + */ +struct dmm *dmm_pat_init(u32 id); + +/** + * Program the physical address translator. + * @param dmm Device data + * @param desc PAT descriptor + * @param mode programming mode + * @return an error status. + */ +s32 dmm_pat_refill(struct dmm *dmm, struct pat *desc, enum pat_mode mode); + +/** + * Clean up the physical address translator. + * @param dmm Device data + * @return an error status. + */ +void dmm_pat_release(struct dmm *dmm); + +#endif diff --git a/arch/arm/mach-omap2/include/mach/tiler.h b/arch/arm/mach-omap2/include/mach/tiler.h new file mode 100644 index 000000000000..ba3b779d6223 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/tiler.h @@ -0,0 +1,216 @@ +/* + * tiler.h + * + * TILER driver support functions for TI OMAP processors. + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef TILER_H +#define TILER_H + +#define TILER_PAGE 0x1000 +#define TILER_WIDTH 256 +#define TILER_HEIGHT 128 +#define TILER_BLOCK_WIDTH 64 +#define TILER_BLOCK_HEIGHT 64 +#define TILER_LENGTH (TILER_WIDTH * TILER_HEIGHT * TILER_PAGE) + +#define TILER_MAX_NUM_BLOCKS 16 + +#define TILIOC_GBUF _IOWR('z', 100, u32) +#define TILIOC_FBUF _IOWR('z', 101, u32) +#define TILIOC_GSSP _IOWR('z', 102, u32) +#define TILIOC_MBUF _IOWR('z', 103, u32) +#define TILIOC_UMBUF _IOWR('z', 104, u32) +#define TILIOC_QBUF _IOWR('z', 105, u32) +#define TILIOC_RBUF _IOWR('z', 106, u32) +#define TILIOC_URBUF _IOWR('z', 107, u32) +#define TILIOC_QUERY_BLK _IOWR('z', 108, u32) + +enum tiler_fmt { + TILFMT_MIN = -1, + TILFMT_INVALID = -1, + TILFMT_NONE = 0, + TILFMT_8BIT = 1, + TILFMT_16BIT = 2, + TILFMT_32BIT = 3, + TILFMT_PAGE = 4, + TILFMT_MAX = 4 +}; + +struct area { + u16 width; + u16 height; +}; + +struct tiler_block_info { + enum tiler_fmt fmt; + union { + struct area area; + u32 len; + } dim; + u32 stride; + void *ptr; + u32 ssptr; +}; + +struct tiler_buf_info { + s32 num_blocks; + struct tiler_block_info blocks[TILER_MAX_NUM_BLOCKS]; + s32 offset; +}; + +struct tiler_view_orient { + u8 rotate_90; + u8 x_invert; + u8 y_invert; +}; + +/* utility functions */ +static inline u32 tilfmt_bpp(enum tiler_fmt fmt) +{ + return fmt == TILFMT_8BIT ? 1 : + fmt == TILFMT_16BIT ? 2 : + fmt == TILFMT_32BIT ? 4 : 0; +} + +/** + * Reserves a 1D or 2D TILER block area and memory for the + * current process with group ID 0. + * + * @param fmt TILER bit mode + * @param width block width + * @param height block height (must be 1 for 1D) + * @param sys_addr pointer where system space (L3) address + * will be stored. + * + * @return error status + */ +s32 tiler_alloc(enum tiler_fmt fmt, u32 width, u32 height, u32 *sys_addr); + +/** + * Reserves a 1D or 2D TILER block area and memory with extended + * arguments. + * + * @param fmt TILER bit mode + * @param width block width + * @param height block height (must be 1 for 1D) + * @param align block alignment (default: PAGE_SIZE) + * @param offs block offset + * @param gid group ID + * @param pid process ID + * @param sys_addr pointer where system space (L3) address + * will be stored. + * + * @return error status + */ +s32 tiler_allocx(enum tiler_fmt fmt, u32 width, u32 height, + u32 align, u32 offs, u32 gid, pid_t pid, u32 *sys_addr); + +/** + * Maps an existing buffer to a 1D or 2D TILER area for the + * current process with group ID 0. + * + * Currently, only 1D area mapping is supported. + * + * @param fmt TILER bit mode + * @param width block width + * @param height block height (must be 1 for 1D) + * @param sys_addr pointer where system space (L3) address + * will be stored. + * @param usr_addr user space address of existing buffer. + * + * @return error status + */ +s32 tiler_map(enum tiler_fmt fmt, u32 width, u32 height, u32 *sys_addr, + u32 usr_addr); + +/** + * Maps an existing buffer to a 1D or 2D TILER area with + * extended arguments. + * + * Currently, only 1D area mapping is supported. + * + * NOTE: alignment is always PAGE_SIZE and offset is 0 + * + * @param fmt TILER bit mode + * @param width block width + * @param height block height (must be 1 for 1D) + * @param gid group ID + * @param pid process ID + * @param sys_addr pointer where system space (L3) address + * will be stored. + * @param usr_addr user space address of existing buffer. + * + * @return error status + */ +s32 tiler_mapx(enum tiler_fmt fmt, u32 width, u32 height, + u32 gid, pid_t pid, u32 *sys_addr, u32 usr_addr); + +/** + * Free TILER memory. + * + * @param sys_addr system space (L3) address. + * + * @return an error status. + */ +s32 tiler_free(u32 sys_addr); + +/** + * Reserves tiler area for n identical set of blocks (buffer) + * for the current process. Use this method to get optimal + * placement of multiple related tiler blocks; however, it may + * not reserve area if tiler_alloc is equally efficient. + * + * @param n number of identical set of blocks + * @param b information on the set of blocks (ptr, ssptr and + * stride fields are ignored) + * + * @return error status + */ +s32 tiler_reserve(u32 n, struct tiler_buf_info *b); + +/** + * Reserves tiler area for n identical set of blocks (buffer) fo + * a given process. Use this method to get optimal placement of + * multiple related tiler blocks; however, it may not reserve + * area if tiler_alloc is equally efficient. + * + * @param n number of identical set of blocks + * @param b information on the set of blocks (ptr, ssptr and + * stride fields are ignored) + * @param pid process ID + * + * @return error status + */ +s32 tiler_reservex(u32 n, struct tiler_buf_info *b, pid_t pid); + +u32 tiler_reorient_addr(u32 tsptr, struct tiler_view_orient orient); + +u32 tiler_get_natural_addr(void *sys_ptr); + +u32 tiler_reorient_topleft(u32 tsptr, struct tiler_view_orient orient, + u32 width, u32 height); + +u32 tiler_stride(u32 tsptr); + +void tiler_rotate_view(struct tiler_view_orient *orient, u32 rotation); + +void tiler_alloc_packed(s32 *count, enum tiler_fmt fmt, u32 width, u32 height, + void **sysptr, void **allocptr, s32 aligned); + +void tiler_alloc_packed_nv12(s32 *count, u32 width, u32 height, void **y_sysptr, + void **uv_sysptr, void **y_allocptr, + void **uv_allocptr, s32 aligned); + +#endif + diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index 4f63dc6859a4..3cfe1c4b5f11 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -44,9 +44,13 @@ #define MMU_IRQ_EMUMISS (1 << 2) #define MMU_IRQ_TRANSLATIONFAULT (1 << 1) #define MMU_IRQ_TLBMISS (1 << 0) -#define MMU_IRQ_MASK \ - (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ - MMU_IRQ_TRANSLATIONFAULT) + +#define __MMU_IRQ_FAULT \ + (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) +#define MMU_IRQ_MASK \ + (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) +#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) +#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) /* MMU_CNTL */ #define MMU_CNTL_SHIFT 1 @@ -61,6 +65,25 @@ ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) + +static void omap2_iommu_set_twl(struct iommu *obj, bool on) +{ + u32 l = iommu_read_reg(obj, MMU_CNTL); + + if (on) + iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); + else + iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); + + l &= ~MMU_CNTL_MASK; + if (on) + l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); + else + l |= (MMU_CNTL_MMU_EN); + + iommu_write_reg(obj, l, MMU_CNTL); +} + static int omap2_iommu_enable(struct iommu *obj) { u32 l, pa; @@ -96,13 +119,9 @@ static int omap2_iommu_enable(struct iommu *obj) l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); iommu_write_reg(obj, l, MMU_SYSCONFIG); - iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); iommu_write_reg(obj, pa, MMU_TTB); - l = iommu_read_reg(obj, MMU_CNTL); - l &= ~MMU_CNTL_MASK; - l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); - iommu_write_reg(obj, l, MMU_CNTL); + omap2_iommu_set_twl(obj, true); return 0; } @@ -147,6 +166,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) printk("\n"); iommu_write_reg(obj, stat, MMU_IRQSTATUS); + omap2_iommu_disable(obj); return stat; } @@ -184,7 +204,7 @@ static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e) if (!cr) return ERR_PTR(-ENOMEM); - cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz; + cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; cr->ram = e->pa | e->endian | e->elsz | e->mixed; return cr; @@ -212,7 +232,8 @@ static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) char *p = buf; /* FIXME: Need more detail analysis of cam/ram */ - p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram); + p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram, + (cr->cam & MMU_CAM_P) ? 1 : 0); return p - buf; } @@ -298,6 +319,7 @@ static const struct iommu_functions omap2_iommu_ops = { .enable = omap2_iommu_enable, .disable = omap2_iommu_disable, + .set_twl = omap2_iommu_set_twl, .fault_isr = omap2_iommu_fault_isr, .tlb_read_cr = omap2_tlb_read_cr, diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 318f3638653c..afc95aa5b519 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -94,13 +94,15 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) u32 l; unsigned long timeout; - mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); - if (IS_ERR(mbox_ick_handle)) { - printk(KERN_ERR "Could not get mailboxes_ick: %ld\n", - PTR_ERR(mbox_ick_handle)); - return PTR_ERR(mbox_ick_handle); + if (!cpu_is_omap44xx()) { + mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); + if (IS_ERR(mbox_ick_handle)) { + printk(KERN_ERR "Could not get mailboxes_ick: %ld\n", + PTR_ERR(mbox_ick_handle)); + return PTR_ERR(mbox_ick_handle); + } + clk_enable(mbox_ick_handle); } - clk_enable(mbox_ick_handle); if (cpu_is_omap44xx()) { mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG); @@ -146,9 +148,11 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) static void omap2_mbox_shutdown(struct omap_mbox *mbox) { - clk_disable(mbox_ick_handle); - clk_put(mbox_ick_handle); - mbox_ick_handle = NULL; + if (!cpu_is_omap44xx()) { + clk_disable(mbox_ick_handle); + clk_put(mbox_ick_handle); + mbox_ick_handle = NULL; + } } /* Mailbox FIFO handle functions */ @@ -486,5 +490,6 @@ module_exit(omap2_mbox_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions"); -MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt"); +MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); +MODULE_AUTHOR("Paul Mundt"); MODULE_ALIAS("platform:"DRV_NAME); diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 1fbbdda76717..9cf02a71653a 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -195,7 +195,6 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .phys_base = OMAP44XX_MCBSP1_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, - .rx_irq = OMAP44XX_IRQ_MCBSP1, .tx_irq = OMAP44XX_IRQ_MCBSP1, .ops = &omap2_mcbsp_ops, }, @@ -203,7 +202,6 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .phys_base = OMAP44XX_MCBSP2_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, - .rx_irq = OMAP44XX_IRQ_MCBSP2, .tx_irq = OMAP44XX_IRQ_MCBSP2, .ops = &omap2_mcbsp_ops, }, @@ -211,7 +209,6 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, - .rx_irq = OMAP44XX_IRQ_MCBSP3, .tx_irq = OMAP44XX_IRQ_MCBSP3, .ops = &omap2_mcbsp_ops, }, @@ -219,7 +216,6 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, - .rx_irq = OMAP44XX_IRQ_MCBSP4, .tx_irq = OMAP44XX_IRQ_MCBSP4, .ops = &omap2_mcbsp_ops, }, diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c new file mode 100644 index 000000000000..f6015702f8ee --- /dev/null +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -0,0 +1,168 @@ +/* + * omap iommu: omap device registration + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> + +#include <plat/iommu.h> +#include <plat/irqs.h> + +struct iommu_device { + resource_size_t base; + int irq; + struct iommu_platform_data pdata; + struct resource res[2]; +}; +static struct iommu_device *devices; +static int num_iommu_devices; + +#ifdef CONFIG_ARCH_OMAP3 +static struct iommu_device omap3_devices[] = { + { + .base = 0x480bd400, + .irq = 24, + .pdata = { + .name = "isp", + .nr_tlb_entries = 8, + .clk_name = "cam_ick", + }, + }, +#if defined(CONFIG_MPU_BRIDGE_IOMMU) + { + .base = 0x5d000000, + .irq = 28, + .pdata = { + .name = "iva2", + .nr_tlb_entries = 32, + .clk_name = "iva2_ck", + }, + }, +#endif +}; +#define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices) +static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; +#else +#define omap3_devices NULL +#define NR_OMAP3_IOMMU_DEVICES 0 +#define omap3_iommu_pdev NULL +#endif + +#ifdef CONFIG_ARCH_OMAP4 +static struct iommu_device omap4_devices[] = { + { + .base = OMAP4_MMU1_BASE, + .irq = OMAP44XX_IRQ_DUCATI_MMU, + .pdata = { + .name = "ducati", + .nr_tlb_entries = 32, + .clk_name = "ipu_ick", + }, + }, +#if defined(CONFIG_MPU_TESLA_IOMMU) + { + .base = OMAP4_MMU2_BASE, + .irq = INT_44XX_DSP_MMU, + .pdata = { + .name = "tesla", + .nr_tlb_entries = 32, + .clk_name = "iva_ick", + }, + }, +#endif +}; +#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices) +static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES]; +#else +#define omap4_devices NULL +#define NR_OMAP4_IOMMU_DEVICES 0 +#define omap4_iommu_pdev NULL +#endif + +static struct platform_device **omap_iommu_pdev; + +int iommu_get_plat_data_size() +{ + return num_iommu_devices; +} +EXPORT_SYMBOL(iommu_get_plat_data_size); + +struct iommu_device *iommu_get_device_data(void) +{ + return devices; +} + +static int __init omap_iommu_init(void) +{ + int i, err; + struct resource res[] = { + { .flags = IORESOURCE_MEM }, + { .flags = IORESOURCE_IRQ }, + }; + + if (cpu_is_omap34xx()) { + devices = omap3_devices; + omap_iommu_pdev = omap3_iommu_pdev; + num_iommu_devices = NR_OMAP3_IOMMU_DEVICES; + } else if (cpu_is_omap44xx()) { + devices = omap4_devices; + omap_iommu_pdev = omap4_iommu_pdev; + num_iommu_devices = NR_OMAP4_IOMMU_DEVICES; + } else + return -ENODEV; + + for (i = 0; i < num_iommu_devices; i++) { + struct platform_device *pdev; + const struct iommu_device *d = &devices[i]; + + pdev = platform_device_alloc("omap-iommu", i); + if (!pdev) { + err = -ENOMEM; + goto err_out; + } + + res[0].start = d->base; + res[0].end = d->base + MMU_REG_SIZE - 1; + res[1].start = res[1].end = d->irq; + + err = platform_device_add_resources(pdev, res, + ARRAY_SIZE(res)); + if (err) + goto err_out; + err = platform_device_add_data(pdev, &d->pdata, + sizeof(d->pdata)); + if (err) + goto err_out; + err = platform_device_add(pdev); + if (err) + goto err_out; + omap_iommu_pdev[i] = pdev; + } + return 0; + +err_out: + while (i--) + platform_device_put(omap_iommu_pdev[i]); + return err; +} +module_init(omap_iommu_init); + +static void __exit omap_iommu_exit(void) +{ + int i; + + for (i = 0; i < num_iommu_devices; i++) + platform_device_unregister(omap_iommu_pdev[i]); +} +module_exit(omap_iommu_exit); + +MODULE_AUTHOR("Hiroshi DOYU"); +MODULE_DESCRIPTION("omap iommu: omap device registration"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c deleted file mode 100644 index fbbcb5c83367..000000000000 --- a/arch/arm/mach-omap2/omap3-iommu.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * omap iommu: omap3 device registration - * - * Copyright (C) 2008-2009 Nokia Corporation - * - * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> - -#include <plat/iommu.h> - -struct iommu_device { - resource_size_t base; - int irq; - struct iommu_platform_data pdata; - struct resource res[2]; -}; - -static struct iommu_device devices[] = { - { - .base = 0x480bd400, - .irq = 24, - .pdata = { - .name = "isp", - .nr_tlb_entries = 8, - .clk_name = "cam_ick", - }, - }, -#if defined(CONFIG_MPU_BRIDGE_IOMMU) - { - .base = 0x5d000000, - .irq = 28, - .pdata = { - .name = "iva2", - .nr_tlb_entries = 32, - .clk_name = "iva2_ck", - }, - }, -#endif -}; -#define NR_IOMMU_DEVICES ARRAY_SIZE(devices) - -static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES]; - -static int __init omap3_iommu_init(void) -{ - int i, err; - struct resource res[] = { - { .flags = IORESOURCE_MEM }, - { .flags = IORESOURCE_IRQ }, - }; - - for (i = 0; i < NR_IOMMU_DEVICES; i++) { - struct platform_device *pdev; - const struct iommu_device *d = &devices[i]; - - pdev = platform_device_alloc("omap-iommu", i); - if (!pdev) { - err = -ENOMEM; - goto err_out; - } - - res[0].start = d->base; - res[0].end = d->base + MMU_REG_SIZE - 1; - res[1].start = res[1].end = d->irq; - - err = platform_device_add_resources(pdev, res, - ARRAY_SIZE(res)); - if (err) - goto err_out; - err = platform_device_add_data(pdev, &d->pdata, - sizeof(d->pdata)); - if (err) - goto err_out; - err = platform_device_add(pdev); - if (err) - goto err_out; - omap3_iommu_pdev[i] = pdev; - } - return 0; - -err_out: - while (i--) - platform_device_put(omap3_iommu_pdev[i]); - return err; -} -module_init(omap3_iommu_init); - -static void __exit omap3_iommu_exit(void) -{ - int i; - - for (i = 0; i < NR_IOMMU_DEVICES; i++) - platform_device_unregister(omap3_iommu_pdev[i]); -} -module_exit(omap3_iommu_exit); - -MODULE_AUTHOR("Hiroshi DOYU"); -MODULE_DESCRIPTION("omap iommu: omap3 device registration"); -MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-omap2/remoteproc44xx.c b/arch/arm/mach-omap2/remoteproc44xx.c new file mode 100644 index 000000000000..5972e2c02c37 --- /dev/null +++ b/arch/arm/mach-omap2/remoteproc44xx.c @@ -0,0 +1,236 @@ +/* + * Remote Processor machine-specific module for OMAP3 + * + * Copyright (C) 2010 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/pm_runtime.h> +#include <plat/remoteproc.h> +#include <mach/irqs.h> +#include <plat/omap_device.h> + +#include "cm.h" +#include "prm.h" + +#define RM_M3_RST1ST 0x1 +#define RM_M3_RST2ST 0x2 +#define RM_M3_RST3ST 0x4 +#define RM_M3_REL_RST1_MASK 0x2 +#define RM_M3_REL_RST2_MASK 0x0 +#define RM_M3_AST_RST1_MASK 0x3 +#define RM_M3_AST_RST2_MASK 0x2 + +#define M3_CLK_MOD_MODE_HW_AUTO 0x1 +#define M3_CLKTRCTRL_SW_WKUP 0x2 +#define M3_CLKTRCTRL_SW_SLEEP 0x1 +#define M3_CLKACTIVITY_MPU_M3_CLK 0x100 + +static inline int proc44x_sysm3_start(struct omap_rproc *rproc) +{ + u32 reg; + int counter = 10; + struct device *dev = rproc->dev; + + /* Module is managed automatically by HW */ + cm_write_mod_reg(M3_CLK_MOD_MODE_HW_AUTO, OMAP4430_CM2_CORE_MOD, + OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET); + + /* Enable the M3 clock */ + cm_write_mod_reg(M3_CLKTRCTRL_SW_WKUP, OMAP4430_CM2_CORE_MOD, + OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET); + do { + reg = cm_read_mod_reg(OMAP4430_CM2_CORE_MOD, + OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET); + if (reg & M3_CLKACTIVITY_MPU_M3_CLK) { + dev_info(dev, "M3 clock enabled:" + "OMAP4430_CM_DUCATI_CLKSTCTRL = 0x%x\n", reg); + break; + } + msleep(1); + } while (--counter); + if (counter == 0) { + dev_info(dev, "FAILED TO ENABLE DUCATI M3 CLOCK !%x\n", reg); + return -EFAULT; + } + + /* De-assert RST1, and clear the Reset status */ + dev_info(dev, "De-assert RST1\n"); + prm_write_mod_reg(RM_M3_REL_RST1_MASK, OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTCTRL_OFFSET); + while (!(prm_read_mod_reg(OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTST_OFFSET) & RM_M3_RST1ST)) + ; + dev_info(dev, "RST1 released!"); + + prm_write_mod_reg(RM_M3_RST1ST, OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTST_OFFSET); + + return 0; +} + +static inline int proc44x_appm3_start(struct omap_rproc *rproc) +{ + struct device *dev = rproc->dev; + + /* De-assert RST2, and clear the Reset status */ + dev_info(dev, "De-assert RST2\n"); + prm_write_mod_reg(RM_M3_REL_RST2_MASK, OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTCTRL_OFFSET); + + while (!(prm_read_mod_reg(OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTST_OFFSET) & RM_M3_RST2ST)) + ; + dev_info(dev, "RST2 released!"); + + prm_write_mod_reg(RM_M3_RST2ST, OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTST_OFFSET); + + return 0; +} + +static inline int proc44x_sysm3_stop(struct omap_rproc *rproc) +{ + struct device *dev = rproc->dev; + u32 reg; + + reg = prm_read_mod_reg(OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTCTRL_OFFSET); + + dev_info(dev, "assert RST1 reg = 0x%x\n", reg); + prm_write_mod_reg((reg | RM_M3_AST_RST1_MASK), OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTCTRL_OFFSET); + return 0; +} + +static inline int proc44x_appm3_stop(struct omap_rproc *rproc) +{ + struct device *dev = rproc->dev; + u32 reg; + + reg = prm_read_mod_reg(OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTCTRL_OFFSET); + + dev_info(dev, "assert RST2 reg = 0x%x\n", reg); + prm_write_mod_reg((reg | RM_M3_AST_RST2_MASK), OMAP4430_PRM_CORE_MOD, + OMAP4_RM_DUCATI_RSTCTRL_OFFSET); + return 0; +} + +static inline int omap4_rproc_get_state(struct omap_rproc *rproc) +{ + return rproc->state; +} + +static struct omap_rproc_ops omap4_ducati0_ops = { + .start = proc44x_sysm3_start, + .stop = proc44x_sysm3_stop, + .get_state = omap4_rproc_get_state, +}; + +static struct omap_rproc_ops omap4_ducati1_ops = { + .start = proc44x_appm3_start, + .stop = proc44x_appm3_stop, + .get_state = omap4_rproc_get_state, +}; + +static struct omap_rproc_ops omap4_tesla_ops = { + .start = NULL, + .stop = NULL, +}; + +static struct omap_rproc_platform_data omap4_rproc_data[] = { + { + .name = "tesla", + .ops = &omap4_tesla_ops, + .oh_name = "tesla_hwmod", + }, + { + .name = "ducati-proc0", + .ops = &omap4_ducati0_ops, + .oh_name = "ducati_hwmod0", + }, + { + .name = "ducati-proc1", + .ops = &omap4_ducati1_ops, + .oh_name = "ducati_hwmod1", + }, +}; + +struct omap_rproc_platform_data *remoteproc_get_plat_data(void) +{ + return omap4_rproc_data; +} + +int remoteproc_get_plat_data_size(void) +{ + return ARRAY_SIZE(omap4_rproc_data); +} +EXPORT_SYMBOL(remoteproc_get_plat_data_size); + + +#define NR_RPROC_DEVICES ARRAY_SIZE(omap4_rproc_data) + +static struct platform_device *omap4_rproc_pdev[NR_RPROC_DEVICES]; + +static int __init omap4_rproc_init(void) +{ + int i, err; + + for (i = 0; i < NR_RPROC_DEVICES; i++) { + struct platform_device *pdev; + + pdev = platform_device_alloc("omap-remoteproc", i); + if (!pdev) { + err = -ENOMEM; + goto err_out; + } + + err = platform_device_add_data(pdev, &omap4_rproc_data[i], + sizeof(omap4_rproc_data[0])); + err = platform_device_add(pdev); + if (err) + goto err_out; + omap4_rproc_pdev[i] = pdev; + } + return 0; + +err_out: + while (i--) + platform_device_put(omap4_rproc_pdev[i]); + return err; +} +module_init(omap4_rproc_init); + +static void __exit omap4_rproc_exit(void) +{ + int i; + + for (i = 0; i < NR_RPROC_DEVICES; i++) + platform_device_unregister(omap4_rproc_pdev[i]); +} +module_exit(omap4_rproc_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("OMAP4 Remote Processor module"); +MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>"); +MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>"); diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S index 7148e53e6078..8ebffdd6fcff 100644 --- a/arch/arm/mm/cache-fa.S +++ b/arch/arm/mm/cache-fa.S @@ -157,7 +157,7 @@ ENTRY(fa_flush_kern_dcache_area) * - start - virtual start address * - end - virtual end address */ -fa_dma_inv_range: +ENTRY(fa_dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry @@ -180,7 +180,7 @@ fa_dma_inv_range: * - start - virtual start address * - end - virtual end address */ -fa_dma_clean_range: +ENTRY(fa_dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE @@ -241,5 +241,7 @@ ENTRY(fa_cache_fns) .long fa_flush_kern_dcache_area .long fa_dma_map_area .long fa_dma_unmap_area + .long fa_dma_inv_range + .long fa_dma_clean_range .long fa_dma_flush_range .size fa_cache_fns, . - fa_cache_fns diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S index c2ff3c599fee..6df52dc014be 100644 --- a/arch/arm/mm/cache-v3.S +++ b/arch/arm/mm/cache-v3.S @@ -84,6 +84,20 @@ ENTRY(v3_flush_kern_dcache_area) /* FALLTHROUGH */ /* + * dma_inv_range(start, end) + * + * Invalidate (discard) the specified virtual address range. + * May not write back any entries. If 'start' or 'end' + * are not cache line aligned, those lines must be written + * back. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(v3_dma_inv_range) + /* FALLTHROUGH */ + +/* * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. @@ -94,6 +108,17 @@ ENTRY(v3_flush_kern_dcache_area) ENTRY(v3_dma_flush_range) mov r0, #0 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache + /* FALLTHROUGH */ + +/* + * dma_clean_range(start, end) + * + * Clean (write back) the specified virtual address range. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(v3_dma_clean_range) mov pc, lr /* @@ -104,7 +129,7 @@ ENTRY(v3_dma_flush_range) */ ENTRY(v3_dma_unmap_area) teq r2, #DMA_TO_DEVICE - bne v3_dma_flush_range + bne v3_dma_inv_range /* FALLTHROUGH */ /* @@ -130,5 +155,7 @@ ENTRY(v3_cache_fns) .long v3_flush_kern_dcache_area .long v3_dma_map_area .long v3_dma_unmap_area + .long v3_dma_inv_range + .long v3_dma_clean_range .long v3_dma_flush_range .size v3_cache_fns, . - v3_cache_fns diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index 4810f7e3e813..df3b423713b9 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -94,6 +94,20 @@ ENTRY(v4_flush_kern_dcache_area) /* FALLTHROUGH */ /* + * dma_inv_range(start, end) + * + * Invalidate (discard) the specified virtual address range. + * May not write back any entries. If 'start' or 'end' + * are not cache line aligned, those lines must be written + * back. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(v4_dma_inv_range) + /* FALLTHROUGH */ + +/* * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. @@ -106,6 +120,17 @@ ENTRY(v4_dma_flush_range) mov r0, #0 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache #endif + /* FALLTHROUGH */ + +/* + * dma_clean_range(start, end) + * + * Clean (write back) the specified virtual address range. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(v4_dma_clean_range) mov pc, lr /* @@ -116,7 +141,7 @@ ENTRY(v4_dma_flush_range) */ ENTRY(v4_dma_unmap_area) teq r2, #DMA_TO_DEVICE - bne v4_dma_flush_range + bne v4_dma_inv_range /* FALLTHROUGH */ /* @@ -142,5 +167,7 @@ ENTRY(v4_cache_fns) .long v4_flush_kern_dcache_area .long v4_dma_map_area .long v4_dma_unmap_area + .long v4_dma_inv_range + .long v4_dma_clean_range .long v4_dma_flush_range .size v4_cache_fns, . - v4_cache_fns diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index df8368afa102..32e7a7448496 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -173,7 +173,7 @@ ENTRY(v4wb_coherent_user_range) * - start - virtual start address * - end - virtual end address */ -v4wb_dma_inv_range: +ENTRY(v4wb_dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -194,7 +194,7 @@ v4wb_dma_inv_range: * - start - virtual start address * - end - virtual end address */ -v4wb_dma_clean_range: +ENTRY(v4wb_dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE @@ -252,5 +252,7 @@ ENTRY(v4wb_cache_fns) .long v4wb_flush_kern_dcache_area .long v4wb_dma_map_area .long v4wb_dma_unmap_area + .long v4wb_dma_inv_range + .long v4wb_dma_clean_range .long v4wb_dma_flush_range .size v4wb_cache_fns, . - v4wb_cache_fns diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index 45c70312f43b..3d8dad5b2650 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -142,12 +142,23 @@ ENTRY(v4wt_flush_kern_dcache_area) * - start - virtual start address * - end - virtual end address */ -v4wt_dma_inv_range: +ENTRY(v4wt_dma_inv_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b + /* FALLTHROUGH */ + +/* + * dma_clean_range(start, end) + * + * Clean the specified virtual address range. + * + * - start - virtual start address + * - end - virtual end address + */ +ENTRY(v4wt_dma_clean_range) mov pc, lr /* @@ -196,5 +207,7 @@ ENTRY(v4wt_cache_fns) .long v4wt_flush_kern_dcache_area .long v4wt_dma_map_area .long v4wt_dma_unmap_area + .long v4wt_dma_inv_range + .long v4wt_dma_clean_range .long v4wt_dma_flush_range .size v4wt_cache_fns, . - v4wt_cache_fns diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index e46ecd847138..c58392d4ff5a 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -195,7 +195,7 @@ ENTRY(v6_flush_kern_dcache_area) * - start - virtual start address of region * - end - virtual end address of region */ -v6_dma_inv_range: +ENTRY(v6_dma_inv_range) tst r0, #D_CACHE_LINE_SIZE - 1 bic r0, r0, #D_CACHE_LINE_SIZE - 1 #ifdef HARVARD_CACHE @@ -231,7 +231,7 @@ v6_dma_inv_range: * - start - virtual start address of region * - end - virtual end address of region */ -v6_dma_clean_range: +ENTRY(v6_dma_clean_range) bic r0, r0, #D_CACHE_LINE_SIZE - 1 1: #ifdef CONFIG_SMP @@ -310,5 +310,7 @@ ENTRY(v6_cache_fns) .long v6_flush_kern_dcache_area .long v6_dma_map_area .long v6_dma_unmap_area + .long v6_dma_inv_range + .long v6_dma_clean_range .long v6_dma_flush_range .size v6_cache_fns, . - v6_cache_fns diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 37c8157e116e..884ac48a2010 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -224,7 +224,7 @@ ENDPROC(v7_flush_kern_dcache_area) * - start - virtual start address of region * - end - virtual end address of region */ -v7_dma_inv_range: +ENTRY(v7_dma_inv_range) dcache_line_size r2, r3 sub r3, r2, #1 tst r0, r3 @@ -248,7 +248,7 @@ ENDPROC(v7_dma_inv_range) * - start - virtual start address of region * - end - virtual end address of region */ -v7_dma_clean_range: +ENTRY(v7_dma_clean_range) dcache_line_size r2, r3 sub r3, r2, #1 bic r0, r0, r3 @@ -317,5 +317,7 @@ ENTRY(v7_cache_fns) .long v7_flush_kern_dcache_area .long v7_dma_map_area .long v7_dma_unmap_area + .long v7_dma_inv_range + .long v7_dma_clean_range .long v7_dma_flush_range .size v7_cache_fns, . - v7_cache_fns diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index bb9b6124a0d5..20a3e7fea2c4 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -622,3 +622,86 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, } } EXPORT_SYMBOL(dma_sync_sg_for_device); + +#ifdef CONFIG_UNOFFICIAL_USER_DMA_API +int temp_user_dma_op(unsigned long start, unsigned long end, int op) +{ + struct mm_struct *mm = current->active_mm; + void (*inner_op)(const void *, const void *); + void (*outer_op)(unsigned long, unsigned long); + + if (!test_taint(TAINT_USER)) { + printk(KERN_WARNING "%s: using unofficial user DMA API, kernel tainted.\n", + current->comm); + add_taint(TAINT_USER); + } + + switch (op) { + case 1: + inner_op = dmac_inv_range; + outer_op = outer_inv_range; + break; + case 2: + inner_op = dmac_clean_range; + outer_op = outer_clean_range; + break; + case 3: + inner_op = dmac_flush_range; + outer_op = outer_flush_range; + break; + default: + return -EINVAL; + } + + if (end < start) + return -EINVAL; + + down_read(&mm->mmap_sem); + do { + struct vm_area_struct *vma = find_vma(mm, start); + + if (!vma || start < vma->vm_start || + vma->vm_flags & (VM_IO | VM_PFNMAP)) { + up_read(&mm->mmap_sem); + return -EFAULT; + } + + do { + unsigned long e = (start | ~PAGE_MASK) + 1; + struct page *page; + + if (e > end) + e = end; + + page = follow_page(vma, start, FOLL_GET); + if (IS_ERR(page)) { + up_read(&mm->mmap_sem); + return PTR_ERR(page); + } + + if (page) { + unsigned long phys; + + /* + * This flushes the userspace address - which + * is not what this API was intended to do. + * Things may go astray as a result. + */ + inner_op((void *)start, (void *)e); + + /* + * Now handle the L2 cache. + */ + phys = page_to_phys(page) + (start & ~PAGE_MASK); + outer_op(phys, phys + e - start); + + put_page(page); + } + start = e; + } while (start < end && start < vma->vm_end); + } while (start < end); + up_read(&mm->mmap_sem); + + return 0; +} +#endif diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 28c8b950ef04..d5a38801cc08 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -349,6 +349,109 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) } EXPORT_SYMBOL(__arm_ioremap); +#define MAX_SECTIONS 4 +void __iomem * +__arm_multi_strided_ioremap(int sections, + unsigned long *phys_addr, size_t *phys_size, + unsigned long *phys_stride, + unsigned long *virt_stride, + unsigned int mtype) +{ + unsigned long pfns[MAX_SECTIONS]; + const struct mem_type *type; + unsigned long total_size = 0, j; + int err = 0, i; + unsigned long addr, addr_i, pstride, vstride; + struct vm_struct * area; + + if (sections > MAX_SECTIONS) + return NULL; + + for (i = 0; i < sections; i++) { + /* both physical and virtual strides must be both specified + or neither specified */ + pstride = ((phys_stride && phys_stride[i]) ? + phys_stride[i] : phys_size[i]); + vstride = ((virt_stride && virt_stride[i]) ? + virt_stride[i] : phys_size[i]); + + if (!pstride ^ !vstride) + return NULL; + + /* + * Don't allow wraparound or zero size. Also, sections + * must end/begin on page boundary, and strides be page + * aligned + * + * For now, size must be multiple of physical stride. This + * may be relaxed to contain only full virtual strides. (E.g. + * not have to contain the waste after the last virtual block.) + * + */ + if (((phys_addr[i] | phys_size[i] | + vstride | pstride) & ~PAGE_MASK) || + !phys_size[i] || + vstride > pstride || + (pstride && (phys_size[i] % pstride)) || + (phys_addr[i] + phys_size[i] - 1 < phys_addr[i])) + return NULL; + + pfns[i] = __phys_to_pfn(phys_addr[i]); + + /* + * High mappings must be supersection aligned + */ + if (pfns[i] >= 0x100000 && + (__pfn_to_phys(pfns[i]) & ~SUPERSECTION_MASK)) + return NULL; + + total_size += phys_size[i] / pstride * vstride; + } + + type = get_mem_type(mtype); + if (!type) + return NULL; + + area = get_vm_area(total_size, VM_IOREMAP); + if (!area) + return NULL; + addr = addr_i = (unsigned long)area->addr; + + for (i = 0; i < sections && !err; i++) { + printk(KERN_ERR "mapping %lx to %lx (%x)\n", __pfn_to_phys(pfns[i]), addr_i, phys_size[i]); + pstride = ((phys_stride && phys_stride[i]) ? + phys_stride[i] : phys_size[i]); + vstride = ((virt_stride && virt_stride[i]) ? + virt_stride[i] : phys_size[i]); + for (j = 0; j < phys_size[i]; j += pstride) { + #ifndef CONFIG_SMP + if (DOMAIN_IO == 0 && + (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) || + cpu_is_xsc3()) && pfns[i] >= 0x100000 && + !((__pfn_to_phys(pfns[i]) | vstride | addr_i) & ~SUPERSECTION_MASK)) { + area->flags |= VM_ARM_SECTION_MAPPING; + err = remap_area_supersections(addr_i, pfns[i], size[i], type); + } else if (!((__pfn_to_phys(pfns[i]) | vstride | addr_i) & ~PMD_MASK)) { + area->flags |= VM_ARM_SECTION_MAPPING; + err = remap_area_sections(addr_i, pfns[i], vstride, type); + } else + #endif + err = remap_area_pages(addr_i, pfns[i], vstride, type); + pfns[i] += __phys_to_pfn(pstride); + addr_i += vstride; + } + } + + if (err) { + vunmap((void *)addr); + return NULL; + } + + flush_cache_vmap(addr, addr + total_size); + return (void __iomem *) addr; +} +EXPORT_SYMBOL(__arm_multi_strided_ioremap); + void __iounmap(volatile void __iomem *io_addr) { void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr); diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 72507c630ceb..c85f5eb42634 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -265,7 +265,7 @@ ENTRY(arm1020_flush_kern_dcache_area) * * (same as v4wb) */ -arm1020_dma_inv_range: +ENTRY(arm1020_dma_inv_range) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE tst r0, #CACHE_DLINESIZE - 1 @@ -295,7 +295,7 @@ arm1020_dma_inv_range: * * (same as v4wb) */ -arm1020_dma_clean_range: +ENTRY(arm1020_dma_clean_range) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE bic r0, r0, #CACHE_DLINESIZE - 1 @@ -363,6 +363,8 @@ ENTRY(arm1020_cache_fns) .long arm1020_flush_kern_dcache_area .long arm1020_dma_map_area .long arm1020_dma_unmap_area + .long arm1020_dma_inv_range + .long arm1020_dma_clean_range .long arm1020_dma_flush_range .align 5 diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index d27829805609..5a3cf7620a2c 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -258,7 +258,7 @@ ENTRY(arm1020e_flush_kern_dcache_area) * * (same as v4wb) */ -arm1020e_dma_inv_range: +ENTRY(arm1020e_dma_inv_range) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE tst r0, #CACHE_DLINESIZE - 1 @@ -284,7 +284,7 @@ arm1020e_dma_inv_range: * * (same as v4wb) */ -arm1020e_dma_clean_range: +ENTRY(arm1020e_dma_clean_range) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE bic r0, r0, #CACHE_DLINESIZE - 1 @@ -349,6 +349,8 @@ ENTRY(arm1020e_cache_fns) .long arm1020e_flush_kern_dcache_area .long arm1020e_dma_map_area .long arm1020e_dma_unmap_area + .long arm1020e_dma_inv_range + .long arm1020e_dma_clean_range .long arm1020e_dma_flush_range .align 5 diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index ce13e4a827de..fec8f5878438 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -247,7 +247,7 @@ ENTRY(arm1022_flush_kern_dcache_area) * * (same as v4wb) */ -arm1022_dma_inv_range: +ENTRY(arm1022_dma_inv_range) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE tst r0, #CACHE_DLINESIZE - 1 @@ -273,7 +273,7 @@ arm1022_dma_inv_range: * * (same as v4wb) */ -arm1022_dma_clean_range: +ENTRY(arm1022_dma_clean_range) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE bic r0, r0, #CACHE_DLINESIZE - 1 @@ -338,6 +338,8 @@ ENTRY(arm1022_cache_fns) .long arm1022_flush_kern_dcache_area .long arm1022_dma_map_area .long arm1022_dma_unmap_area + .long arm1022_dma_inv_range + .long arm1022_dma_clean_range .long arm1022_dma_flush_range .align 5 diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 636672a29c6d..9ece6f666497 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -241,7 +241,7 @@ ENTRY(arm1026_flush_kern_dcache_area) * * (same as v4wb) */ -arm1026_dma_inv_range: +ENTRY(arm1026_dma_inv_range) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE tst r0, #CACHE_DLINESIZE - 1 @@ -267,7 +267,7 @@ arm1026_dma_inv_range: * * (same as v4wb) */ -arm1026_dma_clean_range: +ENTRY(arm1026_dma_clean_range) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE bic r0, r0, #CACHE_DLINESIZE - 1 @@ -332,6 +332,8 @@ ENTRY(arm1026_cache_fns) .long arm1026_flush_kern_dcache_area .long arm1026_dma_map_area .long arm1026_dma_unmap_area + .long arm1026_dma_inv_range + .long arm1026_dma_clean_range .long arm1026_dma_flush_range .align 5 diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 8be81992645d..6f6ab2747da6 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -239,7 +239,7 @@ ENTRY(arm920_flush_kern_dcache_area) * * (same as v4wb) */ -arm920_dma_inv_range: +ENTRY(arm920_dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -262,7 +262,7 @@ arm920_dma_inv_range: * * (same as v4wb) */ -arm920_dma_clean_range: +ENTRY(arm920_dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE @@ -321,6 +321,8 @@ ENTRY(arm920_cache_fns) .long arm920_flush_kern_dcache_area .long arm920_dma_map_area .long arm920_dma_unmap_area + .long arm920_dma_inv_range + .long arm920_dma_clean_range .long arm920_dma_flush_range #endif diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index c0ff8e4b1074..4e4396b121ca 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -241,7 +241,7 @@ ENTRY(arm922_flush_kern_dcache_area) * * (same as v4wb) */ -arm922_dma_inv_range: +ENTRY(arm922_dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -264,7 +264,7 @@ arm922_dma_inv_range: * * (same as v4wb) */ -arm922_dma_clean_range: +ENTRY(arm922_dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE @@ -323,6 +323,8 @@ ENTRY(arm922_cache_fns) .long arm922_flush_kern_dcache_area .long arm922_dma_map_area .long arm922_dma_unmap_area + .long arm922_dma_inv_range + .long arm922_dma_clean_range .long arm922_dma_flush_range #endif diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 3c6cffe400f6..7c01c5d1108c 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -283,7 +283,7 @@ ENTRY(arm925_flush_kern_dcache_area) * * (same as v4wb) */ -arm925_dma_inv_range: +ENTRY(arm925_dma_inv_range) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH tst r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -308,7 +308,7 @@ arm925_dma_inv_range: * * (same as v4wb) */ -arm925_dma_clean_range: +ENTRY(arm925_dma_clean_range) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry @@ -374,6 +374,8 @@ ENTRY(arm925_cache_fns) .long arm925_flush_kern_dcache_area .long arm925_dma_map_area .long arm925_dma_unmap_area + .long arm925_dma_inv_range + .long arm925_dma_clean_range .long arm925_dma_flush_range ENTRY(cpu_arm925_dcache_clean_area) diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 75b707c9cce1..72a01a4b80ab 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -246,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_area) * * (same as v4wb) */ -arm926_dma_inv_range: +ENTRY(arm926_dma_inv_range) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH tst r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -271,7 +271,7 @@ arm926_dma_inv_range: * * (same as v4wb) */ -arm926_dma_clean_range: +ENTRY(arm926_dma_clean_range) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry @@ -337,6 +337,8 @@ ENTRY(arm926_cache_fns) .long arm926_flush_kern_dcache_area .long arm926_dma_map_area .long arm926_dma_unmap_area + .long arm926_dma_inv_range + .long arm926_dma_clean_range .long arm926_dma_flush_range ENTRY(cpu_arm926_dcache_clean_area) diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 1af1657819eb..6bb58fca7270 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -171,7 +171,7 @@ ENTRY(arm940_flush_kern_dcache_area) * - start - virtual start address * - end - virtual end address */ -arm940_dma_inv_range: +ENTRY(arm940_dma_inv_range) mov ip, #0 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries @@ -192,7 +192,7 @@ arm940_dma_inv_range: * - start - virtual start address * - end - virtual end address */ -arm940_dma_clean_range: +ENTRY(arm940_dma_clean_range) ENTRY(cpu_arm940_dcache_clean_area) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH @@ -266,6 +266,8 @@ ENTRY(arm940_cache_fns) .long arm940_flush_kern_dcache_area .long arm940_dma_map_area .long arm940_dma_unmap_area + .long arm940_dma_inv_range + .long arm940_dma_clean_range .long arm940_dma_flush_range __INIT diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 1664b6aaff79..ac0f9ba719d7 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -215,7 +215,7 @@ ENTRY(arm946_flush_kern_dcache_area) * - end - virtual end address * (same as arm926) */ -arm946_dma_inv_range: +ENTRY(arm946_dma_inv_range) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH tst r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -240,7 +240,7 @@ arm946_dma_inv_range: * * (same as arm926) */ -arm946_dma_clean_range: +ENTRY(arm946_dma_clean_range) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry @@ -308,6 +308,8 @@ ENTRY(arm946_cache_fns) .long arm946_flush_kern_dcache_area .long arm946_dma_map_area .long arm946_dma_unmap_area + .long arm946_dma_inv_range + .long arm946_dma_clean_range .long arm946_dma_flush_range diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 53e632343849..97e1d784f152 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -274,7 +274,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area) * (same as v4wb) */ .align 5 -feroceon_dma_inv_range: +ENTRY(feroceon_dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -288,7 +288,7 @@ feroceon_dma_inv_range: mov pc, lr .align 5 -feroceon_range_dma_inv_range: +ENTRY(feroceon_range_dma_inv_range) mrs r2, cpsr tst r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -314,7 +314,7 @@ feroceon_range_dma_inv_range: * (same as v4wb) */ .align 5 -feroceon_dma_clean_range: +ENTRY(feroceon_dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE @@ -324,7 +324,7 @@ feroceon_dma_clean_range: mov pc, lr .align 5 -feroceon_range_dma_clean_range: +ENTRY(feroceon_range_dma_clean_range) mrs r2, cpsr cmp r1, r0 subne r1, r1, #1 @ top address is inclusive @@ -414,6 +414,8 @@ ENTRY(feroceon_cache_fns) .long feroceon_flush_kern_dcache_area .long feroceon_dma_map_area .long feroceon_dma_unmap_area + .long feroceon_dma_inv_range + .long feroceon_dma_clean_range .long feroceon_dma_flush_range ENTRY(feroceon_range_cache_fns) @@ -425,6 +427,8 @@ ENTRY(feroceon_range_cache_fns) .long feroceon_range_flush_kern_dcache_area .long feroceon_range_dma_map_area .long feroceon_dma_unmap_area + .long feroceon_range_dma_inv_range + .long feroceon_range_dma_clean_range .long feroceon_range_dma_flush_range .align 5 diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index caa31154e7db..55b7fbec6548 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -218,7 +218,7 @@ ENTRY(mohawk_flush_kern_dcache_area) * * (same as v4wb) */ -mohawk_dma_inv_range: +ENTRY(mohawk_dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry tst r1, #CACHE_DLINESIZE - 1 @@ -241,7 +241,7 @@ mohawk_dma_inv_range: * * (same as v4wb) */ -mohawk_dma_clean_range: +ENTRY(mohawk_dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE @@ -301,6 +301,8 @@ ENTRY(mohawk_cache_fns) .long mohawk_flush_kern_dcache_area .long mohawk_dma_map_area .long mohawk_dma_unmap_area + .long mohawk_dma_inv_range + .long mohawk_dma_clean_range .long mohawk_dma_flush_range ENTRY(cpu_mohawk_dcache_clean_area) diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index e5797f1c1db7..32231a0e917e 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -257,7 +257,7 @@ ENTRY(xsc3_flush_kern_dcache_area) * - start - virtual start address * - end - virtual end address */ -xsc3_dma_inv_range: +ENTRY(xsc3_dma_inv_range) tst r0, #CACHELINESIZE - 1 bic r0, r0, #CACHELINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line @@ -278,7 +278,7 @@ xsc3_dma_inv_range: * - start - virtual start address * - end - virtual end address */ -xsc3_dma_clean_range: +ENTRY(xsc3_dma_clean_range) bic r0, r0, #CACHELINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line add r0, r0, #CACHELINESIZE @@ -337,6 +337,8 @@ ENTRY(xsc3_cache_fns) .long xsc3_flush_kern_dcache_area .long xsc3_dma_map_area .long xsc3_dma_unmap_area + .long xsc3_dma_inv_range + .long xsc3_dma_clean_range .long xsc3_dma_flush_range ENTRY(cpu_xsc3_dcache_clean_area) diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 63037e2162f2..a7999f94bf27 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -315,7 +315,7 @@ ENTRY(xscale_flush_kern_dcache_area) * - start - virtual start address * - end - virtual end address */ -xscale_dma_inv_range: +ENTRY(xscale_dma_inv_range) tst r0, #CACHELINESIZE - 1 bic r0, r0, #CACHELINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -336,7 +336,7 @@ xscale_dma_inv_range: * - start - virtual start address * - end - virtual end address */ -xscale_dma_clean_range: +ENTRY(xscale_dma_clean_range) bic r0, r0, #CACHELINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHELINESIZE @@ -409,6 +409,8 @@ ENTRY(xscale_cache_fns) .long xscale_flush_kern_dcache_area .long xscale_dma_map_area .long xscale_dma_unmap_area + .long xscale_dma_inv_range + .long xscale_dma_clean_range .long xscale_dma_flush_range /* @@ -434,6 +436,8 @@ ENTRY(xscale_80200_A0_A1_cache_fns) .long xscale_dma_a0_map_area .long xscale_dma_unmap_area .long xscale_dma_flush_range + .long xscale_dma_clean_range + .long xscale_dma_flush_range ENTRY(cpu_xscale_dcache_clean_area) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 33256d8a9003..a5a473a88050 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -147,6 +147,21 @@ config OMAP_MBOX_FWK Say Y here if you want to use OMAP Mailbox framework support for DSP, IVA1.0 and IVA2 in OMAP1/2/3. +config OMAP_REMOTE_PROC + bool "Remote Processor framework support" + depends on ARCH_OMAP + help + Say Y here if you want to use OMAP Remote Processor framework + support for DSP, IVA, Tesla and Ducati (OMAP2/3/4). + +config OMAP_RPROC_MEMPOOL_SIZE + hex "Physical memory pool size for remote processor (in bytes)" + depends on OMAP_REMOTE_PROC + default 0x600000 + help + Allocate specified size of memory at booting time to avoid allocation + failure under heavy memory fragmentation after some use time. + config OMAP_IOMMU tristate diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 87e5124fe556..34c6b46f5fb4 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ - usb.o fb.o io.o timer-32k-sync.o + usb.o fb.o io.o hdmi_lib.o timer-32k-sync.o obj-m := obj-n := obj- := @@ -36,5 +36,6 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) # OMAP mailbox framework obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o +obj-$(CONFIG_OMAP_REMOTE_PROC) += remoteproc.o obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 701e4ea4d0e9..104eaecc2278 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -336,6 +336,7 @@ struct clk *omap_clk_get_by_name(const char *name) return ret; } +EXPORT_SYMBOL(omap_clk_get_by_name); /* * Low level helpers diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 1dc7a3986e5b..a8446b4ae152 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -15,6 +15,8 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/slab.h> +#include <linux/delay.h> +#include <linux/i2c/twl.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -28,8 +30,11 @@ #include <mach/gpio.h> #include <plat/menelaus.h> #include <plat/mcbsp.h> +#include <plat/mcpdm.h> #include <plat/dsp_common.h> #include <plat/omap44xx.h> +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) @@ -194,34 +199,41 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, /*-------------------------------------------------------------------------*/ -#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ - defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) +#if defined(CONFIG_OMAP_MCPDM) || defined(CONFIG_OMAP_MCPDM_MODULE) -static struct resource mcpdm_resources[] = { +static struct omap_device_pm_latency omap_mcpdm_latency[] = { { - .name = "mcpdm_mem", - .start = OMAP44XX_MCPDM_BASE, - .end = OMAP44XX_MCPDM_BASE + SZ_4K, - .flags = IORESOURCE_MEM, - }, - { - .name = "mcpdm_irq", - .start = OMAP44XX_IRQ_MCPDM, - .end = OMAP44XX_IRQ_MCPDM, - .flags = IORESOURCE_IRQ, + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, }; -static struct platform_device omap_mcpdm_device = { - .name = "omap-mcpdm", - .id = -1, - .num_resources = ARRAY_SIZE(mcpdm_resources), - .resource = mcpdm_resources, -}; - static void omap_init_mcpdm(void) { - (void) platform_device_register(&omap_mcpdm_device); + struct omap_hwmod *oh; + struct omap_device *od; + struct omap_mcpdm_platform_data *pdata; + + oh = omap_hwmod_lookup("mcpdm"); + if (!oh) + printk(KERN_ERR "Could not look up mcpdm hw_mod\n"); + + pdata = kzalloc(sizeof(struct omap_mcpdm_platform_data), GFP_KERNEL); + if (!pdata) + printk(KERN_ERR "Could not allocate platform data\n"); + + pdata->device_enable = omap_device_enable; + pdata->device_idle = omap_device_idle; + pdata->device_shutdown = omap_device_shutdown; + + od = omap_device_build("omap-mcpdm", -1, oh, pdata, + sizeof(struct omap_mcpdm_platform_data), + omap_mcpdm_latency, + ARRAY_SIZE(omap_mcpdm_latency), 0); + + if (od <= 0) + printk(KERN_ERR "Could not build omap_device for omap-mcpdm\n"); } #else static inline void omap_init_mcpdm(void) {} @@ -229,6 +241,45 @@ static inline void omap_init_mcpdm(void) {} /*-------------------------------------------------------------------------*/ +#if defined(SND_SOC_ABE_TWL6040) + +static struct omap_device_pm_latency omap_aess_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +static void omap_init_aess(void) +{ + struct omap_hwmod *oh; + struct omap_device *od; + struct twl6040_code_data *pdata; + + oh = omap_hwmod_lookup("aess"); + if (!oh) + printk (KERN_ERR "Could not look up aess hw_mod\n"); + + + pdata->device_enable = omap_device_enable; + pdata->device_idle = omap_device_idle; + pdata->device_shutdown = omap_device_shutdown; + + od = omap_device_build("omap-aess", -1, oh, pdata, + sizeof(struct omap_aess_platform_data), + omap_aess_latency, + ARRAY_SIZE(omap_aess_latency), 0); + + if (od <= 0) + printk(KERN_ERR "Could not build omap_device for omap-aess\n"); +} +#else +static inline void omap_init_aess(void) {} +#endif + +/*-------------------------------------------------------------------------*/ + #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) #ifdef CONFIG_ARCH_OMAP2 diff --git a/arch/arm/plat-omap/hdmi_lib.c b/arch/arm/plat-omap/hdmi_lib.c new file mode 100644 index 000000000000..efc409a35534 --- /dev/null +++ b/arch/arm/plat-omap/hdmi_lib.c @@ -0,0 +1,1482 @@ +/* + * hdmi_lib.c + * + * HDMI library support functions for TI OMAP processors. + * + * Copyright (C) 2010 Texas Instruments + * Author: Yong Zhi <y-zhi@ti.com> + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* Rev history: + * Yong Zhi <y-zhi@ti.com> changed SiVal macros + * added PLL/PHY code + * added EDID code + * moved PLL/PHY code to hdmi panel driver + * cleanup 2/08/10 + * MythriPk <mythripk@ti.com> Apr 2010 Modified to read extended EDID partition + * and handle checksum with and without extension + * May 2010 Added support for Hot Plug Detect. + * + */ + +#define DSS_SUBSYS_NAME "HDMI" + +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/mutex.h> +#include <linux/string.h> +#include <plat/hdmi_lib.h> +#include <linux/delay.h> +#include <linux/module.h> + +/* HDMI PHY */ +#define HDMI_TXPHY_TX_CTRL 0x0ul +#define HDMI_TXPHY_DIGITAL_CTRL 0x4ul +#define HDMI_TXPHY_POWER_CTRL 0x8ul + +/* HDMI Wrapper */ +#define HDMI_WP_REVISION 0x0ul +#define HDMI_WP_SYSCONFIG 0x10ul +#define HDMI_WP_IRQSTATUS_RAW 0x24ul +#define HDMI_WP_IRQSTATUS 0x28ul +#define HDMI_WP_PWR_CTRL 0x40ul +#define HDMI_WP_IRQENABLE_SET 0x2Cul +#define HDMI_WP_VIDEO_CFG 0x50ul +#define HDMI_WP_VIDEO_SIZE 0x60ul +#define HDMI_WP_VIDEO_TIMING_H 0x68ul +#define HDMI_WP_VIDEO_TIMING_V 0x6Cul +#define HDMI_WP_WP_CLK 0x70ul + +/* HDMI IP Core System */ +#define HDMI_CORE_SYS__VND_IDL 0x0ul +#define HDMI_CORE_SYS__DEV_IDL 0x8ul +#define HDMI_CORE_SYS__DEV_IDH 0xCul +#define HDMI_CORE_SYS__DEV_REV 0x10ul +#define HDMI_CORE_SYS__SRST 0x14ul +#define HDMI_CORE_CTRL1 0x20ul +#define HDMI_CORE_SYS__SYS_STAT 0x24ul +#define HDMI_CORE_SYS__VID_ACEN 0x124ul +#define HDMI_CORE_SYS__VID_MODE 0x128ul +#define HDMI_CORE_SYS__INTR_STATE 0x1C0ul +#define HDMI_CORE_SYS__INTR1 0x1C4ul +#define HDMI_CORE_SYS__INTR2 0x1C8ul +#define HDMI_CORE_SYS__INTR3 0x1CCul +#define HDMI_CORE_SYS__INTR4 0x1D0ul +#define HDMI_CORE_SYS__UMASK1 0x1D4ul +#define HDMI_CORE_SYS__TMDS_CTRL 0x208ul +#define HDMI_CORE_CTRL1_VEN__FOLLOWVSYNC 0x1ul +#define HDMI_CORE_CTRL1_HEN__FOLLOWHSYNC 0x1ul +#define HDMI_CORE_CTRL1_BSEL__24BITBUS 0x1ul +#define HDMI_CORE_CTRL1_EDGE__RISINGEDGE 0x1ul + +#define HDMI_CORE_SYS__DE_DLY 0xC8ul +#define HDMI_CORE_SYS__DE_CTRL 0xCCul +#define HDMI_CORE_SYS__DE_TOP 0xD0ul +#define HDMI_CORE_SYS__DE_CNTL 0xD8ul +#define HDMI_CORE_SYS__DE_CNTH 0xDCul +#define HDMI_CORE_SYS__DE_LINL 0xE0ul +#define HDMI_CORE_SYS__DE_LINH__1 0xE4ul + +/* HDMI IP Core Audio Video */ +#define HDMI_CORE_AV_HDMI_CTRL 0xBCul +#define HDMI_CORE_AV_DPD 0xF4ul +#define HDMI_CORE_AV_PB_CTRL1 0xF8ul +#define HDMI_CORE_AV_PB_CTRL2 0xFCul +#define HDMI_CORE_AV_AVI_TYPE 0x100ul +#define HDMI_CORE_AV_AVI_VERS 0x104ul +#define HDMI_CORE_AV_AVI_LEN 0x108ul +#define HDMI_CORE_AV_AVI_CHSUM 0x10Cul +#define HDMI_CORE_AV_AVI_DBYTE 0x110ul +#define HDMI_CORE_AV_AVI_DBYTE__ELSIZE 0x4ul + +/* HDMI DDC E-DID */ +#define HDMI_CORE_DDC_CMD 0x3CCul +#define HDMI_CORE_DDC_STATUS 0x3C8ul +#define HDMI_CORE_DDC_ADDR 0x3B4ul +#define HDMI_CORE_DDC_OFFSET 0x3BCul +#define HDMI_CORE_DDC_COUNT1 0x3C0ul +#define HDMI_CORE_DDC_COUNT2 0x3C4ul +#define HDMI_CORE_DDC_DATA 0x3D0ul +#define HDMI_CORE_DDC_SEGM 0x3B8ul + +#define HDMI_WP_AUDIO_CFG 0x80ul +#define HDMI_WP_AUDIO_CFG2 0x84ul +#define HDMI_WP_AUDIO_CTRL 0x88ul +#define HDMI_WP_AUDIO_DATA 0x8Cul + +#define HDMI_CORE_AV__AVI_DBYTE 0x110ul +#define HDMI_CORE_AV__AVI_DBYTE__ELSIZE 0x4ul +#define HDMI_IP_CORE_AV__AVI_DBYTE__NELEMS 15 +#define HDMI_CORE_AV__SPD_DBYTE 0x190ul +#define HDMI_CORE_AV__SPD_DBYTE__ELSIZE 0x4ul +#define HDMI_CORE_AV__SPD_DBYTE__NELEMS 27 +#define HDMI_CORE_AV__AUDIO_DBYTE 0x210ul +#define HDMI_CORE_AV__AUDIO_DBYTE__ELSIZE 0x4ul +#define HDMI_CORE_AV__AUDIO_DBYTE__NELEMS 10 +#define HDMI_CORE_AV__MPEG_DBYTE 0x290ul +#define HDMI_CORE_AV__MPEG_DBYTE__ELSIZE 0x4ul +#define HDMI_CORE_AV__MPEG_DBYTE__NELEMS 27 +#define HDMI_CORE_AV__GEN_DBYTE 0x300ul +#define HDMI_CORE_AV__GEN_DBYTE__ELSIZE 0x4ul +#define HDMI_CORE_AV__GEN_DBYTE__NELEMS 31 +#define HDMI_CORE_AV__GEN2_DBYTE 0x380ul +#define HDMI_CORE_AV__GEN2_DBYTE__ELSIZE 0x4ul +#define HDMI_CORE_AV__GEN2_DBYTE__NELEMS 31 +#define HDMI_CORE_AV__ACR_CTRL 0x4ul +#define HDMI_CORE_AV__FREQ_SVAL 0x8ul +#define HDMI_CORE_AV__N_SVAL1 0xCul +#define HDMI_CORE_AV__N_SVAL2 0x10ul +#define HDMI_CORE_AV__N_SVAL3 0x14ul +#define HDMI_CORE_AV__CTS_SVAL1 0x18ul +#define HDMI_CORE_AV__CTS_SVAL2 0x1Cul +#define HDMI_CORE_AV__CTS_SVAL3 0x20ul +#define HDMI_CORE_AV__CTS_HVAL1 0x24ul +#define HDMI_CORE_AV__CTS_HVAL2 0x28ul +#define HDMI_CORE_AV__CTS_HVAL3 0x2Cul +#define HDMI_CORE_AV__AUD_MODE 0x50ul +#define HDMI_CORE_AV__SPDIF_CTRL 0x54ul +#define HDMI_CORE_AV__HW_SPDIF_FS 0x60ul +#define HDMI_CORE_AV__SWAP_I2S 0x64ul +#define HDMI_CORE_AV__SPDIF_ERTH 0x6Cul +#define HDMI_CORE_AV__I2S_IN_MAP 0x70ul +#define HDMI_CORE_AV__I2S_IN_CTRL 0x74ul +#define HDMI_CORE_AV__I2S_CHST0 0x78ul +#define HDMI_CORE_AV__I2S_CHST1 0x7Cul +#define HDMI_CORE_AV__I2S_CHST2 0x80ul +#define HDMI_CORE_AV__I2S_CHST4 0x84ul +#define HDMI_CORE_AV__I2S_CHST5 0x88ul +#define HDMI_CORE_AV__ASRC 0x8Cul +#define HDMI_CORE_AV__I2S_IN_LEN 0x90ul +#define HDMI_CORE_AV__HDMI_CTRL 0xBCul +#define HDMI_CORE_AV__AUDO_TXSTAT 0xC0ul +#define HDMI_CORE_AV__AUD_PAR_BUSCLK_1 0xCCul +#define HDMI_CORE_AV__AUD_PAR_BUSCLK_2 0xD0ul +#define HDMI_CORE_AV__AUD_PAR_BUSCLK_3 0xD4ul +#define HDMI_CORE_AV__TEST_TXCTRL 0xF0ul +#define HDMI_CORE_AV__DPD 0xF4ul +#define HDMI_CORE_AV__PB_CTRL1 0xF8ul +#define HDMI_CORE_AV__PB_CTRL2 0xFCul +#define HDMI_CORE_AV__AVI_TYPE 0x100ul +#define HDMI_CORE_AV__AVI_VERS 0x104ul +#define HDMI_CORE_AV__AVI_LEN 0x108ul +#define HDMI_CORE_AV__AVI_CHSUM 0x10Cul +#define HDMI_CORE_AV__SPD_TYPE 0x180ul +#define HDMI_CORE_AV__SPD_VERS 0x184ul +#define HDMI_CORE_AV__SPD_LEN 0x188ul +#define HDMI_CORE_AV__SPD_CHSUM 0x18Cul +#define HDMI_CORE_AV__AUDIO_TYPE 0x200ul +#define HDMI_CORE_AV__AUDIO_VERS 0x204ul +#define HDMI_CORE_AV__AUDIO_LEN 0x208ul +#define HDMI_CORE_AV__AUDIO_CHSUM 0x20Cul +#define HDMI_CORE_AV__MPEG_TYPE 0x280ul +#define HDMI_CORE_AV__MPEG_VERS 0x284ul +#define HDMI_CORE_AV__MPEG_LEN 0x288ul +#define HDMI_CORE_AV__MPEG_CHSUM 0x28Cul +#define HDMI_CORE_AV__CP_BYTE1 0x37Cul +#define HDMI_CORE_AV__CEC_ADDR_ID 0x3FCul + + +static struct { + void __iomem *base_core; /*0*/ + void __iomem *base_core_av; /*1*/ + void __iomem *base_wp; /*2*/ + struct mutex hdmi_lock; +} hdmi; + +int count = 0, count_hpd = 0; + +static inline void hdmi_write_reg(u32 base, u16 idx, u32 val) +{ + void __iomem *b; + + switch (base) { + case HDMI_CORE_SYS: + b = hdmi.base_core; + break; + case HDMI_CORE_AV: + b = hdmi.base_core_av; + break; + case HDMI_WP: + b = hdmi.base_wp; + break; + default: + BUG(); + } + __raw_writel(val, b + idx); + /* DBG("write = 0x%x idx =0x%x\r\n", val, idx); */ +} + +static inline u32 hdmi_read_reg(u32 base, u16 idx) +{ + void __iomem *b; + u32 l; + + switch (base) { + case HDMI_CORE_SYS: + b = hdmi.base_core; + break; + case HDMI_CORE_AV: + b = hdmi.base_core_av; + break; + case HDMI_WP: + b = hdmi.base_wp; + break; + default: + BUG(); + } + l = __raw_readl(b + idx); + + /* DBG("addr = 0x%p rd = 0x%x idx = 0x%x\r\n", (b+idx), l, idx); */ + return l; +} + +#define FLD_MASK(start, end) (((1 << (start - end + 1)) - 1) << (end)) +#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end)) +#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) +#define FLD_MOD(orig, val, start, end) \ + (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) + +#define REG_FLD_MOD(base, idx, val, start, end) \ + hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx), val, start, end)) + +#define RD_REG_32(COMP, REG) hdmi_read_reg(COMP, REG) +#define WR_REG_32(COMP, REG, VAL) hdmi_write_reg(COMP, REG, (u32)(VAL)) + +u8 edid_backup[256]; + + +int hdmi_get_image_format(void) +{ + int offset = 0x4, i, current_byte, length, flag = 0, j = 0; + if (edid_backup[0x7e] != 0x00) { + printk(KERN_INFO"Extension block present"); + offset = edid_backup[(0x80) + 2]; + if (offset != 0x4) { + i = 0x80 + 4; + while (i < (0x80 + offset)) { + current_byte = edid_backup[i]; + if ((current_byte >> 5) == 0x2) { + length = current_byte & 0x1F; + for (j = 1 ; j < length ; j++) { + current_byte = edid_backup[i+j]; + printk(KERN_INFO"Image format supported is %d", current_byte & 0x7F); + + } + flag = 1; + break; + + } else { + length = (current_byte & 0x1F) + 1; + i += length; + } + } + } + + } else if (edid_backup[0x7e] != 0x00 && flag == 0) { + printk(KERN_INFO "Video Information Data Not found"); + } else { + printk(KERN_INFO "TV does not have Extension Block"); + } + return 0 ; +} +EXPORT_SYMBOL(hdmi_get_image_format); + +int hdmi_get_audio_format(void) +{ + int offset = 0x4, i, current_byte, length, flag = 0, j = 0; + if (edid_backup[0x7e] != 0x00) { + printk(KERN_INFO"Extension block present"); + offset = edid_backup[(0x80) + 2]; + if (offset != 0x4) { + i = 0x80 + 4; + while (i < (0x80 + offset)) { + current_byte = edid_backup[i]; + if ((current_byte >> 5) == 1) { + current_byte = edid_backup[i]; + length = current_byte & 0x1F; + for (j = 1 ; j < length ; j++) { + if (j%3 == 1) { + current_byte = edid_backup[i+j]; + printk(KERN_INFO"Audio format supported is %d", current_byte & 0x78); +printk(KERN_INFO"Number of channels supported %d", (current_byte & 0x07) + 1); + } + + } + flag = 1; + break; + } else { + length = (current_byte & 0x1F) + 1; + i += length; + } + } + } + + } else if (edid_backup[0x7e] != 0x00 && flag == 0) { + printk(KERN_INFO "Audio Information Data Not found"); + } else { + printk(KERN_INFO "TV does not have Extension Block"); + } + return 0; +} +EXPORT_SYMBOL(hdmi_get_audio_format); + +int hdmi_get_audio_video_latency(void) +{ + printk("This is yet to be implemented"); + return 0; +} +EXPORT_SYMBOL(hdmi_get_audio_video_latency); + +int hdmi_get_pixel_append_position(void) +{ + printk("This is yet to be implemented"); + return 0; +} +EXPORT_SYMBOL(hdmi_get_pixel_append_position); + +int hdmi_core_ddc_edid(u8 *pEDID) +{ + u32 i, j, l; + char checksum = 0; + u32 sts = HDMI_CORE_DDC_STATUS; + u32 ins = HDMI_CORE_SYS; + + /* Turn on CLK for DDC */ + REG_FLD_MOD(HDMI_CORE_AV, HDMI_CORE_AV_DPD, 0x7, 2, 0); + + /* Wait */ + mdelay(10); + + /* Clk SCL Devices */ + REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0xA, 3, 0); + + /* HDMI_CORE_DDC_STATUS__IN_PROG */ + while (FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1) + + /* Clear FIFO */ + REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x9, 3, 0); + + /* HDMI_CORE_DDC_STATUS__IN_PROG */ + while (FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1) + + /* Load Slave Address Register */ + REG_FLD_MOD(ins, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); + + /* Load Offset Address Register */ + REG_FLD_MOD(ins, HDMI_CORE_DDC_OFFSET, 0x0, 7, 0); + /* Load Byte Count */ + REG_FLD_MOD(ins, HDMI_CORE_DDC_COUNT1, 0x100, 7, 0); + REG_FLD_MOD(ins, HDMI_CORE_DDC_COUNT2, 0x100>>8, 1, 0); + /* Set DDC_CMD */ + REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x2, 3, 0); + + /* Yong: do not optimize this part of the code, seems + DDC bus needs some time to get stabilized + */ + l = hdmi_read_reg(ins, sts); + + /* HDMI_CORE_DDC_STATUS__BUS_LOW */ + if (FLD_GET(l, 6, 6) == 1) { + printk("I2C Bus Low?\n\r"); + return -1; + } + /* HDMI_CORE_DDC_STATUS__NO_ACK */ + if (FLD_GET(l, 5, 5) == 1) { + printk("I2C No Ack\n\r"); + return -1; + } + + j = 100; + while (j--) { + l = hdmi_read_reg(ins, sts); + /* progress */ + if (FLD_GET(l, 4, 4) == 1) { + /* HACK: Load Slave Address Register again */ + REG_FLD_MOD(ins, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); + REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x2, 3, 0); + break; + } + mdelay(20); + } + + i = 0; + while (((FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1) + | (FLD_GET(hdmi_read_reg(ins, sts), 2, 2) == 0)) && i < 256) { + if (FLD_GET(hdmi_read_reg(ins, + sts), 2, 2) == 0) { + /* FIFO not empty */ + pEDID[i++] = FLD_GET(hdmi_read_reg(ins, HDMI_CORE_DDC_DATA), 7, 0); + } + } + + if (pEDID[0x14] == 0x80) {/* Digital Display */ + if (pEDID[0x7e] == 0x00) {/* No Extention Block */ + for (j = 0; j < 128; j++) + checksum += pEDID[j]; + DBG("No extension 128 bit checksum\n"); + } else { + for (j = 0; j < 256; j++) + checksum += pEDID[j]; + DBG("Extension present 256 bit checksum\n"); + /* HDMI_CORE_DDC_READ_EXTBLOCK(); */ + } + } else { + DBG("Analog Display\n"); + } + + DBG("EDID Content %d\n", i); + for (i = 0 ; i < 256 ; i++) + edid_backup[i] = pEDID[i]; + +#ifdef DEBUG_EDID + DBG("Header:\n"); + for (i = 0x00; i < 0x08; i++) + DBG("%02x\n", pEDID[i]); + DBG("Vendor & Product:\n"); + for (i = 0x08; i < 0x12; i++) + DBG("%02x\n", pEDID[i]); + DBG("EDID Structure:\n"); + for (i = 0x12; i < 0x14; i++) + DBG("%02x\n", pEDID[i]); + DBG("Basic Display Parameter:\n"); + for (i = 0x14; i < 0x19; i++) + DBG("%02x\n", pEDID[i]); + DBG("Color Characteristics:\n"); + for (i = 0x19; i < 0x23; i++) + DBG("%02x\n", pEDID[i]); + DBG("Established timings:\n"); + for (i = 0x23; i < 0x26; i++) + DBG("%02x\n", pEDID[i]); + DBG("Standart timings:\n"); + for (i = 0x26; i < 0x36; i++) + DBG("%02x\n", pEDID[i]); + DBG("Detailed timing1:\n"); + for (i = 0x36; i < 0x48; i++) + DBG("%02x\n", pEDID[i]); + DBG("Detailed timing2:\n"); + for (i = 0x48; i < 0x5a; i++) + DBG("%02x\n", pEDID[i]); + DBG("Detailed timing3:\n"); + for (i = 0x5a; i < 0x6c; i++) + DBG("%02x\n", pEDID[i]); + DBG("Detailed timing4:\n"); + for (i = 0x6c; i < 0x7e; i++) + DBG("%02x\n", pEDID[i]); +#endif + if (checksum != 0) { + printk("E-EDID checksum failed!!"); + return -1; + } + return 0; +} + +static void hdmi_core_init(struct hdmi_core_video_config_t *v_cfg, + struct hdmi_core_audio_config *audio_cfg, + struct hdmi_core_infoframe_avi *avi, + struct hdmi_core_packet_enable_repeat *r_p) +{ + DBG("Enter HDMI_Core_GlobalInitVars()\n"); + + /*video core*/ + v_cfg->CoreInputBusWide = HDMI_INPUT_8BIT; + v_cfg->CoreOutputDitherTruncation = HDMI_OUTPUTTRUNCATION_8BIT; + v_cfg->CoreDeepColorPacketED = HDMI_DEEPCOLORPACKECTDISABLE; + v_cfg->CorePacketMode = HDMI_PACKETMODERESERVEDVALUE; + v_cfg->CoreHdmiDvi = HDMI_DVI; + v_cfg->CoreTclkSelClkMult = FPLL10IDCK; + + /*audio core*/ + audio_cfg->fs = FS_44100; + audio_cfg->n = 0; + audio_cfg->cts = 0; + audio_cfg->layout = LAYOUT_2CH; /*2channel audio*/ + audio_cfg->aud_par_busclk = 0; + audio_cfg->cts_mode = CTS_MODE_HW; + + /*info frame*/ + avi->db1y_rgb_yuv422_yuv444 = 0; + avi->db1a_active_format_off_on = 0; + avi->db1b_no_vert_hori_verthori = 0; + avi->db1s_0_1_2 = 0; + avi->db2c_no_itu601_itu709_extented = 0; + avi->db2m_no_43_169 = 0; + avi->db2r_same_43_169_149 = 0; + avi->db3itc_no_yes = 0; + avi->db3ec_xvyuv601_xvyuv709 = 0; + avi->db3q_default_lr_fr = 0; + avi->db3sc_no_hori_vert_horivert = 0; + avi->db4vic_videocode = 0; + avi->db5pr_no_2_3_4_5_6_7_8_9_10 = 0; + avi->db6_7_lineendoftop = 0 ; + avi->db8_9_linestartofbottom = 0; + avi->db10_11_pixelendofleft = 0; + avi->db12_13_pixelstartofright = 0; + + /*packet enable and repeat*/ + r_p->AudioPacketED = 0; + r_p->AudioPacketRepeat = 0; + r_p->AVIInfoFrameED = 0; + r_p->AVIInfoFrameRepeat = 0; + r_p->GeneralcontrolPacketED = 0; + r_p->GeneralcontrolPacketRepeat = 0; + r_p->GenericPacketED = 0; + r_p->GenericPacketRepeat = 0; +} + +static void hdmi_core_powerdown_disable(void) +{ + DBG("Enter DSS_HDMI_CORE_POWER_DOWN_DISABLE()\n"); + REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_CTRL1, 0x0, 0, 0); +} + +/* todo: power off the core */ +static __attribute__ ((unused)) void hdmi_core_powerdown_enable(void) +{ + REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_CTRL1, 0x1, 0, 0); +} + +static void hdmi_core_swreset_release(void) +{ + DBG("Enter DSS_HDMI_CORE_SW_RESET_RELEASE()\n"); + REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_SYS__SRST, 0x0, 0, 0); +} + +static void hdmi_core_swreset_assert(void) +{ + DBG("Enter DSS_HDMI_CORE_SW_RESET_ASSERT ()\n"); + REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_SYS__SRST, 0x1, 0, 0); +} + +/* DSS_HDMI_CORE_VIDEO_CONFIG */ +static int hdmi_core_video_config( + struct hdmi_core_video_config_t *cfg) +{ + u32 name = HDMI_CORE_SYS; + u32 av_name = HDMI_CORE_AV; + u32 r = 0; + + /*sys_ctrl1 default configuration not tunable*/ + u32 ven; + u32 hen; + u32 bsel; + u32 edge; + + /*sys_ctrl1 default configuration not tunable*/ + ven = HDMI_CORE_CTRL1_VEN__FOLLOWVSYNC; + hen = HDMI_CORE_CTRL1_HEN__FOLLOWHSYNC; + bsel = HDMI_CORE_CTRL1_BSEL__24BITBUS; + edge = HDMI_CORE_CTRL1_EDGE__RISINGEDGE; + + /*sys_ctrl1 default configuration not tunable*/ + r = hdmi_read_reg(name, HDMI_CORE_CTRL1); + r = FLD_MOD(r, ven, 5, 5); + r = FLD_MOD(r, hen, 4, 4); + r = FLD_MOD(r, bsel, 2, 2); + r = FLD_MOD(r, edge, 1, 1); + hdmi_write_reg(name, HDMI_CORE_CTRL1, r); + + REG_FLD_MOD(name, HDMI_CORE_SYS__VID_ACEN, cfg->CoreInputBusWide, 7, 6); + + /*Vid_Mode */ + r = hdmi_read_reg(name, HDMI_CORE_SYS__VID_MODE); + /*dither truncation configuration*/ + if (cfg->CoreOutputDitherTruncation > + HDMI_OUTPUTTRUNCATION_12BIT) { + r = FLD_MOD(r, cfg->CoreOutputDitherTruncation - 3, 7, 6); + r = FLD_MOD(r, 1, 5, 5); + } else { + r = FLD_MOD(r, cfg->CoreOutputDitherTruncation, 7, 6); + r = FLD_MOD(r, 0, 5, 5); + } + hdmi_write_reg(name, HDMI_CORE_SYS__VID_MODE, r); + + /*HDMI_Ctrl*/ + r = hdmi_read_reg(av_name, HDMI_CORE_AV_HDMI_CTRL); + r = FLD_MOD(r, cfg->CoreDeepColorPacketED, 6, 6); + r = FLD_MOD(r, cfg->CorePacketMode, 5, 3); + r = FLD_MOD(r, cfg->CoreHdmiDvi, 0, 0); + hdmi_write_reg(av_name, HDMI_CORE_AV_HDMI_CTRL, r); + + /*TMDS_CTRL*/ + REG_FLD_MOD(name, HDMI_CORE_SYS__TMDS_CTRL, + cfg->CoreTclkSelClkMult, 6, 5); + + return 0; +} + +static int hdmi_core_audio_mode_enable(u32 instanceName) +{ + REG_FLD_MOD(instanceName, HDMI_CORE_AV__AUD_MODE, 1, 0, 0); + return 0; +} + +static int hdmi_core_audio_config(u32 name, + struct hdmi_core_audio_config *audio_cfg) +{ + int ret = 0; + u32 SD3_EN, SD2_EN, SD1_EN, SD0_EN; + u8 DBYTE1, DBYTE2, DBYTE4, CHSUM; + u8 size1; + u16 size0; + + /*CTS_MODE*/ + WR_REG_32(name, HDMI_CORE_AV__ACR_CTRL, + ((0x0 << 2) | /* MCLK_EN (0: Mclk is not used)*/ + (0x1 << 1) | /* CTS Request Enable (1:Packet Enable, 0:Disable) */ + (audio_cfg->cts_mode << 0))); /* CTS Source Select (1:SW, 0:HW)*/ + + REG_FLD_MOD(name, HDMI_CORE_AV__FREQ_SVAL, 0, 2, 0); + REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL1, audio_cfg->n, 7, 0); + REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL2, (audio_cfg->n >> 8), 7, 0); + REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL3, (audio_cfg->n >> 16), 7, 0); + REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL1, (audio_cfg->cts), 7, 0); + REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL2, (audio_cfg->cts >> 8), 7, 0); + REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL3, (audio_cfg->cts >> 16), 7, 0); + + /*number of channel*/ + REG_FLD_MOD(name, HDMI_CORE_AV__HDMI_CTRL, audio_cfg->layout, 2, 1); + REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_1, + audio_cfg->aud_par_busclk, 7, 0); + REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_2, + (audio_cfg->aud_par_busclk >> 8), 7, 0); + REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_3, + (audio_cfg->aud_par_busclk >> 16), 7, 0); + /* FS_OVERRIDE = 1 because // input is used*/ + WR_REG_32(name, HDMI_CORE_AV__SPDIF_CTRL, 0x1); + /* refer to table209 p192 in func core spec*/ + WR_REG_32(name, HDMI_CORE_AV__I2S_CHST4, audio_cfg->fs); + + /* audio config is mainly due to wrapper hardware connection + and so are fixe (hardware) I2S deserializer is by-pass + so I2S configuration is not needed (I2S don't care). + Wrapper are directly connected at the I2S deserialiser + output level so some register call I2S... need to be + programm to configure this parallel bus, there configuration + is also fixe and due to the hardware connection (I2S hardware) + */ + WR_REG_32(name, HDMI_CORE_AV__I2S_IN_CTRL, + (0 << 7) | /* HBRA_ON */ + (1 << 6) | /* SCK_EDGE Sample clock is rising */ + (0 << 5) | /* CBIT_ORDER */ + (0 << 4) | /* VBit, 0x0=PCM, 0x1=compressed */ + (0 << 3) | /* I2S_WS, 0xdon't care */ + (0 << 2) | /* I2S_JUST, 0=left-justified 1=right-justified */ + (0 << 1) | /* I2S_DIR, 0xdon't care */ + (0)); /* I2S_SHIFT, 0x0 don't care*/ + + WR_REG_32(name, HDMI_CORE_AV__I2S_CHST5, /* mode only */ + (0 << 4) | /* FS_ORIG */ + (1 << 1) | /* I2S lenght 16bits (refer doc) */ + (0));/* Audio sample lenght */ + + WR_REG_32(name, HDMI_CORE_AV__I2S_IN_LEN, /* mode only */ + (0xb)); /* In lenght b=>24bits i2s hardware */ + + /*channel enable depend of the layout*/ + if (audio_cfg->layout == LAYOUT_2CH) { + SD3_EN = 0x0; + SD2_EN = 0x0; + SD1_EN = 0x0; + SD0_EN = 0x1; + } + if (audio_cfg->layout == LAYOUT_8CH) { + SD3_EN = 0x1; + SD2_EN = 0x1; + SD1_EN = 0x1; + SD0_EN = 0x1; + } + + WR_REG_32(name, HDMI_CORE_AV__AUD_MODE, + (SD3_EN << 7) | /* SD3_EN */ + (SD2_EN << 6) | /* SD2_EN */ + (SD1_EN << 5) | /* SD1_EN */ + (SD0_EN << 4) | /* SD0_EN */ + (0 << 3) | /* DSD_EN */ + (1 << 2) | /* AUD_PAR_EN*/ + (0 << 1) | /* SPDIF_EN*/ + (0)); /* AUD_EN*/ + + /* Audio info frame setting refer to CEA-861-d spec p75 */ + /*0x10 because only PCM is supported / -1 because 1 is for 2 channel*/ + DBYTE1 = 0x10 + (audio_cfg->if_channel_number - 1); + DBYTE2 = (audio_cfg->if_fs << 2) + audio_cfg->if_sample_size; + /*channel location according to CEA spec*/ + DBYTE4 = audio_cfg->if_audio_channel_location; + + CHSUM = 0x100-0x84-0x01-0x0A-DBYTE1-DBYTE2-DBYTE4; + + WR_REG_32(name, HDMI_CORE_AV__AUDIO_TYPE, 0x084); + WR_REG_32(name, HDMI_CORE_AV__AUDIO_VERS, 0x001); + WR_REG_32(name, HDMI_CORE_AV__AUDIO_LEN, 0x00A); + WR_REG_32(name, HDMI_CORE_AV__AUDIO_CHSUM, CHSUM); /*don't care on VMP*/ + + size0 = HDMI_CORE_AV__AUDIO_DBYTE; + size1 = HDMI_CORE_AV__AUDIO_DBYTE__ELSIZE; + hdmi_write_reg(name, (size0 + 0 * size1), DBYTE1); + hdmi_write_reg(name, (size0 + 1 * size1), DBYTE2); + hdmi_write_reg(name, (size0 + 2 * size1), 0x000); + hdmi_write_reg(name, (size0 + 3 * size1), DBYTE4); + hdmi_write_reg(name, (size0 + 4 * size1), 0x000); + hdmi_write_reg(name, (size0 + 5 * size1), 0x000); + hdmi_write_reg(name, (size0 + 6 * size1), 0x000); + hdmi_write_reg(name, (size0 + 7 * size1), 0x000); + hdmi_write_reg(name, (size0 + 8 * size1), 0x000); + hdmi_write_reg(name, (size0 + 9 * size1), 0x000); + + return ret; +} + +static int hdmi_core_audio_infoframe_avi(u32 name, + struct hdmi_core_infoframe_avi info_avi) +{ + u16 offset; + int dbyte, dbyte_size; + u32 val; + + dbyte = HDMI_CORE_AV_AVI_DBYTE; + dbyte_size = HDMI_CORE_AV_AVI_DBYTE__ELSIZE; + /*info frame video*/ + hdmi_write_reg(name, HDMI_CORE_AV_AVI_TYPE, 0x082); + hdmi_write_reg(name, HDMI_CORE_AV_AVI_VERS, 0x002); + hdmi_write_reg(name, HDMI_CORE_AV_AVI_LEN, 0x00D); + + offset = dbyte + (0 * dbyte_size); + val = (info_avi.db1y_rgb_yuv422_yuv444 << 5) | + (info_avi.db1a_active_format_off_on << 4) | + (info_avi.db1b_no_vert_hori_verthori << 2) | + (info_avi.db1s_0_1_2); + hdmi_write_reg(name, offset, val); + + offset = dbyte + (1 * dbyte_size); + val = (info_avi.db2c_no_itu601_itu709_extented << 6) | + (info_avi.db2m_no_43_169 << 4) | + (info_avi.db2r_same_43_169_149); + hdmi_write_reg(name, offset, val); + + offset = dbyte + (2 * dbyte_size); + val = (info_avi.db3itc_no_yes << 7) | + (info_avi.db3ec_xvyuv601_xvyuv709 << 4) | + (info_avi.db3q_default_lr_fr << 2) | + (info_avi.db3sc_no_hori_vert_horivert); + hdmi_write_reg(name, offset, val); + + offset = dbyte + (3 * dbyte_size); + hdmi_write_reg(name, offset, info_avi.db4vic_videocode); + + offset = dbyte + (4 * dbyte_size); + val = info_avi.db5pr_no_2_3_4_5_6_7_8_9_10; + hdmi_write_reg(name, offset, val); + + offset = dbyte + (5 * dbyte_size); + val = info_avi.db6_7_lineendoftop & 0x00FF; + hdmi_write_reg(name, offset, val); + + offset = dbyte + (6 * dbyte_size); + val = ((info_avi.db6_7_lineendoftop >> 8) & 0x00FF); + hdmi_write_reg(name, offset, val); + + offset = dbyte + (7 * dbyte_size); + val = info_avi.db8_9_linestartofbottom & 0x00FF; + hdmi_write_reg(name, offset, val); + + offset = dbyte + (8 * dbyte_size); + val = ((info_avi.db8_9_linestartofbottom >> 8) & 0x00FF); + hdmi_write_reg(name, offset, val); + + offset = dbyte + (9 * dbyte_size); + val = info_avi.db10_11_pixelendofleft & 0x00FF; + hdmi_write_reg(name, offset, val); + + offset = dbyte + (10 * dbyte_size); + val = ((info_avi.db10_11_pixelendofleft >> 8) & 0x00FF); + hdmi_write_reg(name, offset, val); + + offset = dbyte + (11 * dbyte_size); + val = info_avi.db12_13_pixelstartofright & 0x00FF; + hdmi_write_reg(name, offset , val); + + offset = dbyte + (12 * dbyte_size); + val = ((info_avi.db12_13_pixelstartofright >> 8) & 0x00FF); + hdmi_write_reg(name, offset, val); + + return 0; +} + +static int hdmi_core_av_packet_config(u32 name, + struct hdmi_core_packet_enable_repeat r_p) +{ + /*enable/repeat the infoframe*/ + hdmi_write_reg(name, HDMI_CORE_AV_PB_CTRL1, + (r_p.AudioPacketED << 5)| + (r_p.AudioPacketRepeat << 4)| + (r_p.AVIInfoFrameED << 1)| + (r_p.AVIInfoFrameRepeat)); + + /*enable/repeat the packet*/ + hdmi_write_reg(name, HDMI_CORE_AV_PB_CTRL2, + (r_p.GeneralcontrolPacketED << 3)| + (r_p.GeneralcontrolPacketRepeat << 2)| + (r_p.GenericPacketED << 1)| + (r_p.GenericPacketRepeat)); + return 0; +} + +static void hdmi_w1_init(struct hdmi_video_timing *t_p, + struct hdmi_video_format *f_p, + struct hdmi_video_interface *i_p, + struct hdmi_irq_vector *pIrqVectorEnable, + struct hdmi_audio_format *audio_fmt, + struct hdmi_audio_dma *audio_dma) +{ + DBG("Enter HDMI_W1_GlobalInitVars()\n"); + + t_p->horizontalBackPorch = 0; + t_p->horizontalFrontPorch = 0; + t_p->horizontalSyncPulse = 0; + t_p->verticalBackPorch = 0; + t_p->verticalFrontPorch = 0; + t_p->verticalSyncPulse = 0; + + f_p->packingMode = HDMI_PACK_10b_RGB_YUV444; + f_p->linePerPanel = 0; + f_p->pixelPerLine = 0; + + i_p->vSyncPolarity = 0; + i_p->hSyncPolarity = 0; + + i_p->interlacing = 0; + i_p->timingMode = 0; /* HDMI_TIMING_SLAVE */ + + pIrqVectorEnable->pllRecal = 0; + pIrqVectorEnable->pllUnlock = 0; + pIrqVectorEnable->pllLock = 0; + pIrqVectorEnable->phyDisconnect = 1; + pIrqVectorEnable->phyConnect = 1; + pIrqVectorEnable->phyShort5v = 0; + pIrqVectorEnable->videoEndFrame = 0; + pIrqVectorEnable->videoVsync = 0; + pIrqVectorEnable->fifoSampleRequest = 0; + pIrqVectorEnable->fifoOverflow = 0; + pIrqVectorEnable->fifoUnderflow = 0; + pIrqVectorEnable->ocpTimeOut = 0; + pIrqVectorEnable->core = 1; + + audio_fmt->stereo_channel_enable = HDMI_STEREO_ONECHANNELS; + audio_fmt->audio_channel_location = HDMI_CEA_CODE_03; + audio_fmt->iec = HDMI_AUDIO_FORMAT_LPCM; + audio_fmt->justify = HDMI_AUDIO_JUSTIFY_LEFT; + audio_fmt->left_before = HDMI_SAMPLE_LEFT_FIRST; + audio_fmt->sample_number = HDMI_ONEWORD_ONE_SAMPLE; + audio_fmt->sample_size = HDMI_SAMPLE_24BITS; + + audio_dma->dma_transfer = 0x10; + audio_dma->block_size = 0xC0; + audio_dma->dma_or_irq = HDMI_THRESHOLD_DMA; + audio_dma->threshold_value = 0x10; + audio_dma->block_start_end = HDMI_BLOCK_STARTEND_ON; + +} + + +static void hdmi_w1_irq_enable(struct hdmi_irq_vector *pIrqVectorEnable) +{ + u32 r = 0; + + r = ((pIrqVectorEnable->pllRecal << 31) | + (pIrqVectorEnable->pllUnlock << 30) | + (pIrqVectorEnable->pllLock << 29) | + (pIrqVectorEnable->phyDisconnect << 26) | + (pIrqVectorEnable->phyConnect << 25) | + (pIrqVectorEnable->phyShort5v << 24) | + (pIrqVectorEnable->videoEndFrame << 17) | + (pIrqVectorEnable->videoVsync << 16) | + (pIrqVectorEnable->fifoSampleRequest << 10) | + (pIrqVectorEnable->fifoOverflow << 9) | + (pIrqVectorEnable->fifoUnderflow << 8) | + (pIrqVectorEnable->ocpTimeOut << 4) | + (pIrqVectorEnable->core << 0)); + + hdmi_write_reg(HDMI_WP, HDMI_WP_IRQENABLE_SET, r); +} + +static inline int hdmi_w1_wait_for_bit_change(const u32 ins, + u32 idx, int b2, int b1, int val) +{ + int t = 0; + while (val != FLD_GET(hdmi_read_reg(ins, idx), b2, b1)) { + udelay(1); + if (t++ > 1000) + return !val; + } + return val; +} + +/* todo: add timeout value */ +int hdmi_w1_set_wait_srest(void) +{ + /* reset W1 */ + REG_FLD_MOD(HDMI_WP, HDMI_WP_SYSCONFIG, 0x1, 0, 0); + + /* wait till SOFTRESET == 0 */ + while (FLD_GET(hdmi_read_reg(HDMI_WP, HDMI_WP_SYSCONFIG), 0, 0)) + ; + + return 0; +} + +/* PHY_PWR_CMD */ +int hdmi_w1_set_wait_phy_pwr(HDMI_PhyPwr_t val) +{ + REG_FLD_MOD(HDMI_WP, HDMI_WP_PWR_CTRL, val, 7, 6); + + if (hdmi_w1_wait_for_bit_change(HDMI_WP, + HDMI_WP_PWR_CTRL, 5, 4, val) != val) { + ERR("Failed to set PHY power mode to %d\n", val); + return -ENODEV; + } + return 0; +} + +/* PLL_PWR_CMD */ +int hdmi_w1_set_wait_pll_pwr(HDMI_PllPwr_t val) +{ + REG_FLD_MOD(HDMI_WP, HDMI_WP_PWR_CTRL, val, 3, 2); + + /* wait till PHY_PWR_STATUS=ON */ + if (hdmi_w1_wait_for_bit_change(HDMI_WP, + HDMI_WP_PWR_CTRL, 1, 0, val) != val) { + ERR("Failed to set PHY_PWR_STATUS to ON\n"); + return -ENODEV; + } + + return 0; +} + +void hdmi_w1_video_stop(void) +{ + REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, 0, 31, 31); +} + +void hdmi_w1_video_start(void) +{ + REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, (u32)0x1, 31, 31); +} + +static void hdmi_w1_video_init_format(struct hdmi_video_format *f_p, + struct hdmi_video_timing *t_p, struct hdmi_config *param) +{ + DBG("Enter HDMI_W1_ConfigVideoResolutionTiming()\n"); + + f_p->linePerPanel = param->lpp; + f_p->pixelPerLine = param->ppl; + + t_p->horizontalBackPorch = param->hbp; + t_p->horizontalFrontPorch = param->hfp; + t_p->horizontalSyncPulse = param->hsw; + t_p->verticalBackPorch = param->vbp; + t_p->verticalFrontPorch = param->vfp; + t_p->verticalSyncPulse = param->vsw; +} + +static void hdmi_w1_video_config_format( + struct hdmi_video_format *f_p) +{ + u32 l = 0; + + REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, f_p->packingMode, 10, 8); + + l |= FLD_VAL(f_p->linePerPanel, 31, 16); + l |= FLD_VAL(f_p->pixelPerLine, 15, 0); + hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE, l); +} + +static void hdmi_w1_video_config_interface( + struct hdmi_video_interface *i_p) +{ + u32 r; + DBG("Enter HDMI_W1_ConfigVideoInterface()\n"); + + r = hdmi_read_reg(HDMI_WP, HDMI_WP_VIDEO_CFG); + r = FLD_MOD(r, i_p->vSyncPolarity, 7, 7); + r = FLD_MOD(r, i_p->hSyncPolarity, 6, 6); + r = FLD_MOD(r, i_p->interlacing, 3, 3); + r = FLD_MOD(r, i_p->timingMode, 1, 0); + hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_CFG, r); +} + +static void hdmi_w1_video_config_timing( + struct hdmi_video_timing *t_p) +{ + u32 timing_h = 0; + u32 timing_v = 0; + + DBG("Enter HDMI_W1_ConfigVideoTiming ()\n"); + + timing_h |= FLD_VAL(t_p->horizontalBackPorch, 31, 20); + timing_h |= FLD_VAL(t_p->horizontalFrontPorch, 19, 8); + timing_h |= FLD_VAL(t_p->horizontalSyncPulse, 7, 0); + hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_TIMING_H, timing_h); + + timing_v |= FLD_VAL(t_p->verticalBackPorch, 31, 20); + timing_v |= FLD_VAL(t_p->verticalFrontPorch, 19, 8); + timing_v |= FLD_VAL(t_p->verticalSyncPulse, 7, 0); + hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_TIMING_V, timing_v); +} + +static int hdmi_w1_audio_config_format(u32 name, + struct hdmi_audio_format *audio_fmt) +{ + int ret = 0; + u32 value = 0; + + value = hdmi_read_reg(name, HDMI_WP_AUDIO_CFG); + value &= 0xfffffff7; + value |= ((audio_fmt->justify) << 3);; + value &= 0xfffffffb; + value |= ((audio_fmt->left_before) << 2); + value &= 0xfffffffd; + value |= ((audio_fmt->sample_number) << 1); + value &= 0xfffffffe; + value |= ((audio_fmt->sample_size)); + value &= 0xf8ffffff; + value |= ((audio_fmt->stereo_channel_enable) << 24); + value &= 0xff00ffff; + value |= ((audio_fmt->audio_channel_location) << 16); + value &= 0xffffffef; + value |= ((audio_fmt->iec) << 4); + /* Wakeup */ + value = 0x1030022; + hdmi_write_reg(name, HDMI_WP_AUDIO_CFG, value); + DBG("HDMI_WP_AUDIO_CFG = 0x%x \n", value); + + return ret; +} + +static int hdmi_w1_audio_config_dma(u32 name, struct hdmi_audio_dma *audio_dma) + +{ + int ret = 0; + u32 value = 0; + + value = hdmi_read_reg(name, HDMI_WP_AUDIO_CFG2); + value &= 0xffffff00; + value |= (audio_dma->block_size); + value &= 0xffff00ff; + value |= ((audio_dma->dma_transfer) << 8); + /* Wakeup */ + value = 0x20C0; + hdmi_write_reg(name, HDMI_WP_AUDIO_CFG2, value); + DBG("HDMI_WP_AUDIO_CFG2 = 0x%x \n", value); + + value = hdmi_read_reg(name, HDMI_WP_AUDIO_CTRL); + value &= 0xfffffdff; + value |= ((audio_dma->dma_or_irq)<<9); + value &= 0xfffffe00; + value |= (audio_dma->threshold_value); + /* Wakeup */ + value = 0x020; + hdmi_write_reg(name, HDMI_WP_AUDIO_CTRL, value); + DBG("HDMI_WP_AUDIO_CTRL = 0x%x \n", value); + + return ret; +} + +static void hdmi_w1_audio_enable(void) +{ + REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 1, 31, 31); +} + +static __attribute__ ((unused))__attribute__ ((unused)) void hdmi_w1_audio_disable(void) +{ + REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 0, 31, 31); +} + +static void hdmi_w1_audio_start(void) +{ + REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 1, 30, 30); +} + +static void hdmi_w1_audio_stop(void) +{ + REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 0, 30, 30); +} + +static int hdmi_w1_audio_config(void) +{ + int ret; + + struct hdmi_audio_format audio_fmt; + struct hdmi_audio_dma audio_dma; + + audio_fmt.justify = HDMI_AUDIO_JUSTIFY_LEFT; + audio_fmt.sample_number = HDMI_ONEWORD_ONE_SAMPLE; + audio_fmt.sample_size = HDMI_SAMPLE_24BITS; + audio_fmt.stereo_channel_enable = HDMI_STEREO_ONECHANNELS; + audio_fmt.audio_channel_location = 0x03; + + ret = hdmi_w1_audio_config_format(HDMI_WP, &audio_fmt); + + audio_dma.dma_transfer = 0x20; + audio_dma.threshold_value = 0x60; + audio_dma.dma_or_irq = HDMI_THRESHOLD_DMA; + + ret = hdmi_w1_audio_config_dma(HDMI_WP, &audio_dma); + + return ret; +} + +int hdmi_lib_enable(struct hdmi_config *cfg) +{ + u32 r, val; + + u32 av_name = HDMI_CORE_AV; + + /*HDMI*/ + struct hdmi_video_timing VideoTimingParam; + struct hdmi_video_format VideoFormatParam; + struct hdmi_video_interface VideoInterfaceParam; + struct hdmi_irq_vector IrqHdmiVectorEnable; + struct hdmi_audio_format audio_fmt; + struct hdmi_audio_dma audio_dma; + + /*HDMI core*/ + struct hdmi_core_infoframe_avi avi_param; + struct hdmi_core_video_config_t v_core_cfg; + struct hdmi_core_audio_config audio_cfg; + struct hdmi_core_packet_enable_repeat repeat_param; + + hdmi_w1_init(&VideoTimingParam, &VideoFormatParam, + &VideoInterfaceParam, &IrqHdmiVectorEnable, + &audio_fmt, &audio_dma); + + hdmi_core_init(&v_core_cfg, + &audio_cfg, + &avi_param, + &repeat_param); + + /* Enable PLL Lock and UnLock intrerrupts */ + IrqHdmiVectorEnable.pllUnlock = 1; + IrqHdmiVectorEnable.pllLock = 1; + + /***************** init DSS register **********************/ + hdmi_w1_irq_enable(&IrqHdmiVectorEnable); + + hdmi_w1_video_init_format(&VideoFormatParam, + &VideoTimingParam, cfg); + + hdmi_w1_video_config_timing(&VideoTimingParam); + + /*video config*/ + VideoFormatParam.packingMode = HDMI_PACK_24b_RGB_YUV444_YUV422; + + hdmi_w1_video_config_format(&VideoFormatParam); + + /* FIXME */ + VideoInterfaceParam.vSyncPolarity = cfg->v_pol; + VideoInterfaceParam.hSyncPolarity = cfg->h_pol; + VideoInterfaceParam.interlacing = cfg->interlace; + VideoInterfaceParam.timingMode = 1 ; /* HDMI_TIMING_MASTER_24BIT */ + + hdmi_w1_video_config_interface(&VideoInterfaceParam); + +#if 0 + /* hnagalla */ + val = hdmi_read_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE); + + val &= 0x0FFFFFFF; + val |= ((0x1f) << 27); /* wakeup */ + hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE, val); + + hdmi_w1_audio_config(); +#endif + + /****************************** CORE *******************************/ + /************* configure core video part ********************************/ + /*set software reset in the core*/ + hdmi_core_swreset_assert(); + + /*power down off*/ + hdmi_core_powerdown_disable(); + + v_core_cfg.CorePacketMode = HDMI_PACKETMODE24BITPERPIXEL; + v_core_cfg.CoreHdmiDvi = HDMI_HDMI; + + /* hnagalla */ + audio_cfg.fs = 0x02; + audio_cfg.if_fs = 0x00; + audio_cfg.n = 6144; + audio_cfg.cts = 74250; + + /* audio channel */ + audio_cfg.if_sample_size = 0x0; + audio_cfg.layout = 0; + audio_cfg.if_channel_number = 2; + audio_cfg.if_audio_channel_location = 0x00; + + /* TODO: Is this configuration correct? */ + audio_cfg.aud_par_busclk = (((128 * 31) - 1) << 8); + audio_cfg.cts_mode = 0; + + r = hdmi_core_video_config(&v_core_cfg); + + /* hnagalla */ + hdmi_core_audio_config(av_name, &audio_cfg); + hdmi_core_audio_mode_enable(av_name); + + /*release software reset in the core*/ + hdmi_core_swreset_release(); + + /*configure packet*/ + /*info frame video see doc CEA861-D page 65*/ + avi_param.db1y_rgb_yuv422_yuv444 = INFOFRAME_AVI_DB1Y_RGB; + avi_param.db1a_active_format_off_on = + INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; + avi_param.db1b_no_vert_hori_verthori = INFOFRAME_AVI_DB1B_NO; + avi_param.db1s_0_1_2 = INFOFRAME_AVI_DB1S_0; + avi_param.db2c_no_itu601_itu709_extented = INFOFRAME_AVI_DB2C_NO; + avi_param.db2m_no_43_169 = INFOFRAME_AVI_DB2M_NO; + avi_param.db2r_same_43_169_149 = INFOFRAME_AVI_DB2R_SAME; + avi_param.db3itc_no_yes = INFOFRAME_AVI_DB3ITC_NO; + avi_param.db3ec_xvyuv601_xvyuv709 = INFOFRAME_AVI_DB3EC_XVYUV601; + avi_param.db3q_default_lr_fr = INFOFRAME_AVI_DB3Q_DEFAULT; + avi_param.db3sc_no_hori_vert_horivert = INFOFRAME_AVI_DB3SC_NO; + avi_param.db4vic_videocode = cfg->video_format; + avi_param.db5pr_no_2_3_4_5_6_7_8_9_10 = INFOFRAME_AVI_DB5PR_NO; + avi_param.db6_7_lineendoftop = 0; + avi_param.db8_9_linestartofbottom = 0; + avi_param.db10_11_pixelendofleft = 0; + avi_param.db12_13_pixelstartofright = 0; + + r = hdmi_core_audio_infoframe_avi(av_name, avi_param); + + /*enable/repeat the infoframe*/ + repeat_param.AVIInfoFrameED = PACKETENABLE; + repeat_param.AVIInfoFrameRepeat = PACKETREPEATON; + /* wakeup */ + repeat_param.AudioPacketED = PACKETENABLE; + repeat_param.AudioPacketRepeat = PACKETREPEATON; + r = hdmi_core_av_packet_config(av_name, repeat_param); + + REG_FLD_MOD(av_name, HDMI_CORE_AV__HDMI_CTRL, cfg->hdmi_dvi, 0, 0); + return r; +} + +int hdmi_lib_init(void){ + u32 rev; + + hdmi.base_wp = ioremap(HDMI_WP, (HDMI_HDCP - HDMI_WP)); + + if (!hdmi.base_wp) { + ERR("can't ioremap WP\n"); + return -ENOMEM; + } + + hdmi.base_core = hdmi.base_wp + 0x400; + hdmi.base_core_av = hdmi.base_wp + 0x900; + + rev = hdmi_read_reg(HDMI_WP, HDMI_WP_REVISION); + + printk(KERN_INFO "OMAP HDMI W1 rev %d.%d\n", + FLD_GET(rev, 10, 8), FLD_GET(rev, 5, 0)); + + return 0; +} + +void hdmi_lib_exit(void){ + iounmap(hdmi.base_wp); +} + +void dump_regs(void){ + DBG("W1 VIDEO_CFG = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x50ul)); + DBG("Core CTRL1 = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x420ul)); + DBG("Core VID_MODE = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x528ul)); + DBG("Core AV_CTRL = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x9bcul)); + DBG("Core VID_ACEN = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x524ul)); + DBG("Core PB_CTR2 packet buf = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x9fcul)); +} + +int hdmi_set_irqs(void) +{ + u32 r = 0 , hpd = 0; + struct hdmi_irq_vector pIrqVectorEnable; + + pIrqVectorEnable.pllRecal = 0; + pIrqVectorEnable.phyShort5v = 0; + pIrqVectorEnable.videoEndFrame = 0; + pIrqVectorEnable.videoVsync = 0; + pIrqVectorEnable.fifoSampleRequest = 0; + pIrqVectorEnable.fifoOverflow = 0; + pIrqVectorEnable.fifoUnderflow = 0; + pIrqVectorEnable.ocpTimeOut = 0; + pIrqVectorEnable.pllUnlock = 1; + pIrqVectorEnable.pllLock = 1; + pIrqVectorEnable.phyDisconnect = 1; + pIrqVectorEnable.phyConnect = 1; + pIrqVectorEnable.core = 1; + + hdmi_w1_irq_enable(&pIrqVectorEnable); + + r = hdmi_read_reg(HDMI_WP, HDMI_WP_IRQENABLE_SET); + DBG("Irqenable %x \n", r); + hpd = hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__UMASK1); + DBG("%x hpd\n", hpd); + return 0; +} + +/* Interrupt handler*/ +void HDMI_W1_HPD_handler(int *r) +{ + u32 val, intr, set; + mdelay(30); + val = hdmi_read_reg(HDMI_WP, HDMI_WP_IRQSTATUS); + DBG("%x hdmi_wp_irqstatus\n", val); + mdelay(30); + set = 0; + set = hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__SYS_STAT); + DBG("%x hdmi_core_sys_sys_stat\n", set); + mdelay(30); + hdmi_write_reg(HDMI_WP, HDMI_WP_IRQSTATUS, val); + /* flush posted write */ + hdmi_read_reg(HDMI_WP, HDMI_WP_IRQSTATUS); + mdelay(30); + *r = 0; + if ((count == 0) && ((val & 0x02000000) == 0x02000000) && + ((set & 0x00000002) != 0x00000002)) { + *r = 2; + DBG("First interrupt physical attach but not HPD"); + count_hpd = 0; + } + count++; + hdmi_set_irqs(); + DBG("%d count and count_hpd %d", count, count_hpd); + if ((set & 0x00000002) == 0x00000002) { + if (count_hpd == 0) { + *r = 4; + count_hpd++; + goto end; + } else + *r = 1; + DBG("HPD is set you can read edid"); + } + if (((val & 0x04000000) == 0x04000000) && ((set & 0x00000002) != 0x00000002)) { + *r = 3; + count = 0; + count_hpd = 0; + } + intr = hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__INTR1); + DBG("%x hdmi_core_sys_sys_intr\n", intr); + end: /*Do nothing*/; +} + + +/* wrapper functions to be used until L24.5 release*/ +int HDMI_CORE_DDC_READEDID(u32 name, u8 *p) +{ + int r = hdmi_core_ddc_edid(p); + return r; +} + +int HDMI_W1_StopVideoFrame(u32 name) +{ + DBG("Enter HDMI_W1_StopVideoFrame()\n"); + hdmi_w1_video_stop(); + return 0; +} + +int HDMI_W1_StartVideoFrame(u32 name) +{ + DBG("Enter HDMI_W1_StartVideoFrame ()\n"); + hdmi_w1_video_start(); + return 0; +} + +/* PHY_PWR_CMD */ +int HDMI_W1_SetWaitPhyPwrState(u32 name, + HDMI_PhyPwr_t param) +{ + int r = hdmi_w1_set_wait_phy_pwr(param); + return r; +} + +/* PLL_PWR_CMD */ +int HDMI_W1_SetWaitPllPwrState(u32 name, + HDMI_PllPwr_t param) +{ + int r = hdmi_w1_set_wait_pll_pwr(param); + return r; +} + +int HDMI_W1_SetWaitSoftReset(void) +{ + /* reset W1 */ + REG_FLD_MOD(HDMI_WP, HDMI_WP_SYSCONFIG, 0x1, 0, 0); + + /* wait till SOFTRESET == 0 */ + while (FLD_GET(hdmi_read_reg(HDMI_WP, HDMI_WP_SYSCONFIG), 0, 0)) + ; + + return 0; +} + +int hdmi_w1_wrapper_enable(u32 instanceName) +{ + printk(KERN_INFO "Wrapper Enabled...\n"); + hdmi_w1_audio_enable(); + return 0; +} + +int hdmi_w1_wrapper_disable(u32 instanceName) +{ + hdmi_w1_audio_enable(); + printk(KERN_INFO "Wrapper disabled...\n"); + return 0; +} + +int hdmi_w1_stop_audio_transfer(u32 instanceName) +{ + hdmi_w1_audio_stop(); + return 0; +} + +int hdmi_w1_start_audio_transfer(u32 instanceName) +{ + hdmi_w1_audio_start(); + printk(KERN_INFO "Start audio transfer...\n"); + return 0; +} + +int DSS_HDMI_CONFIG(HDMI_Timing_t timings, u32 video_format, + u32 mode) +{ + int err; + struct hdmi_config data; + + data.ppl = timings.pixelPerLine; + data.lpp = timings.linePerPanel; + data.pixel_clock = timings.pplclk; + + data.hsw = timings.horizontalSyncPulse; + data.hfp = timings.horizontalFrontPorch; + data.hbp = timings.horizontalBackPorch; + data.vsw = timings.verticalSyncPulse; + data.vfp = timings.verticalFrontPorch; + data.vbp = timings.verticalBackPorch; + + data.h_pol = 1; + data.v_pol = 1; + data.hdmi_dvi = mode; + data.video_format = video_format; + + err = hdmi_lib_enable(&data); + return err; +} + diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 1c529ce9dc11..c5a54458d72a 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -42,6 +42,17 @@ #define DISPC_IRQ_SYNC_LOST (1 << 14) #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) #define DISPC_IRQ_WAKEUP (1 << 16) +#define DISPC_IRQ_SYNC_LOST_2 (1 << 17) +#define DISPC_IRQ_VSYNC2 (1 << 18) +#define DISPC_IRQ_VID3_END_WIN (1 << 19) +#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) + /* VID3_BUF_UNDERFLOW*/ +#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) +#define DISPC_IRQ_FRAMEDONE2 (1 << 22) +#define DISPC_IRQ_FRAMEDONE_WB (1 << 23) +#define DISPC_IRQ_FRAMEDONE_DIG (1 << 24) /* FRAMEDONE_TV*/ +#define DISPC_IRQ_WB_BUF_OVERFLOW (1 << 25) + struct omap_dss_device; struct omap_overlay_manager; @@ -53,17 +64,21 @@ enum omap_display_type { OMAP_DISPLAY_TYPE_SDI = 1 << 2, OMAP_DISPLAY_TYPE_DSI = 1 << 3, OMAP_DISPLAY_TYPE_VENC = 1 << 4, + OMAP_DISPLAY_TYPE_HDMI = 1 << 5, }; enum omap_plane { OMAP_DSS_GFX = 0, OMAP_DSS_VIDEO1 = 1, - OMAP_DSS_VIDEO2 = 2 + OMAP_DSS_VIDEO2 = 2, + OMAP_DSS_VIDEO3 = 3, + OMAP_DSS_WB = 4 }; enum omap_channel { OMAP_DSS_CHANNEL_LCD = 0, OMAP_DSS_CHANNEL_DIGIT = 1, + OMAP_DSS_CHANNEL_LCD2 = 2, }; enum omap_color_mode { @@ -81,6 +96,13 @@ enum omap_color_mode { OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ + OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ + OMAP_DSS_COLOR_RGBA12 = 1 << 15, /* RGBA12 - 4444 */ + OMAP_DSS_COLOR_XRGB12 = 1 << 16, /* xRGB12, 16-bit container */ + OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16-1555 */ + OMAP_DSS_COLOR_RGBX24_32_ALGN = 1 << 18, /* 32-msb aligned 24bit */ + OMAP_DSS_COLOR_XRGB15 = 1 << 19, /* xRGB15: 1555*/ + OMAP_DSS_COLOR_GFX_OMAP2 = OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | @@ -102,16 +124,26 @@ enum omap_color_mode { OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, OMAP_DSS_COLOR_VID1_OMAP3 = + OMAP_DSS_COLOR_NV12 | OMAP_DSS_COLOR_RGBA12 | + OMAP_DSS_COLOR_XRGB12 | OMAP_DSS_COLOR_ARGB16_1555 | + OMAP_DSS_COLOR_RGBX24_32_ALGN | OMAP_DSS_COLOR_XRGB15 | OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P | - OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY, + OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY | + OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBA32 | + OMAP_DSS_COLOR_RGBX32, OMAP_DSS_COLOR_VID2_OMAP3 = + OMAP_DSS_COLOR_NV12 | OMAP_DSS_COLOR_RGBA12 | + OMAP_DSS_COLOR_XRGB12 | OMAP_DSS_COLOR_ARGB16_1555 | + OMAP_DSS_COLOR_RGBX24_32_ALGN | OMAP_DSS_COLOR_XRGB15 | OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, + + OMAP_DSS_COLOR_VID3_OMAP3 = OMAP_DSS_COLOR_VID2_OMAP3, }; enum omap_lcd_display_type { @@ -173,11 +205,13 @@ enum omap_dss_display_state { enum omap_dss_overlay_managers { OMAP_DSS_OVL_MGR_LCD, OMAP_DSS_OVL_MGR_TV, + OMAP_DSS_OVL_MGR_LCD2, }; enum omap_dss_rotation_type { OMAP_DSS_ROT_DMA = 0, OMAP_DSS_ROT_VRFB = 1, + OMAP_DSS_ROT_TILER = 2, }; /* clockwise rotation angle */ @@ -197,6 +231,34 @@ enum omap_overlay_manager_caps { OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0, }; +enum omap_overlay_zorder { + OMAP_DSS_OVL_ZORDER_0 = 0x0, + OMAP_DSS_OVL_ZORDER_1 = 0x1, + OMAP_DSS_OVL_ZORDER_2 = 0x2, + OMAP_DSS_OVL_ZORDER_3 = 0x3, +}; + +/* write back*/ +enum omap_writeback_source { + OMAP_WB_LCD_1_MANAGER = 0, + OMAP_WB_LCD_2_MANAGER = 1, + OMAP_WB_TV_MANAGER = 2, + OMAP_WB_OVERLAY0 = 3, + OMAP_WB_OVERLAY1 = 4, + OMAP_WB_OVERLAY2 = 5, + OMAP_WB_OVERLAY3 = 6 +}; + +enum omap_writeback_capturemode { + OMAP_WB_CAPTURE_ALL = 0x0, + OMAP_WB_CAPTURE_1 = 0x1, + OMAP_WB_CAPTURE_1_OF_2 = 0x2, + OMAP_WB_CAPTURE_1_OF_3 = 0x3, + OMAP_WB_CAPTURE_1_OF_4 = 0x4, + OMAP_WB_CAPTURE_1_OF_5 = 0x5, + OMAP_WB_CAPTURE_1_OF_6 = 0x6, + OMAP_WB_CAPTURE_1_OF_7 = 0x7 +}; /* RFBI */ struct rfbi_timings { @@ -230,20 +292,42 @@ int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, int hs_pol_inv, int vs_pol_inv, int extif_div); /* DSI */ -void dsi_bus_lock(void); -void dsi_bus_unlock(void); -int dsi_vc_dcs_write(int channel, u8 *data, int len); -int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd); -int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param); -int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len); -int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen); -int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data); -int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data); -int dsi_vc_set_max_rx_packet_size(int channel, u16 len); -int dsi_vc_send_null(int channel); -int dsi_vc_send_bta_sync(int channel); +enum omap_dsi_index { + DSI1 = 0, + DSI2 = 1, +}; +void dsi_bus_lock(enum omap_dsi_index ix); +void dsi_bus_unlock(enum omap_dsi_index ix); +int dsi_vc_dcs_write(enum omap_dsi_index ix, int channel, + u8 *data, int len); +int dsi_vc_dcs_write_0(enum omap_dsi_index ix, int channel, + u8 dcs_cmd); +int dsi_vc_dcs_write_1(enum omap_dsi_index ix, int channel, + u8 dcs_cmd, u8 param); +int dsi_vc_dcs_write_nosync(enum omap_dsi_index ix, int channel, + u8 *data, int len); +int dsi_vc_dcs_read(enum omap_dsi_index ix, int channel, + u8 dcs_cmd, u8 *buf, int buflen); +int dsi_vc_dcs_read_1(enum omap_dsi_index ix, int channel, + u8 dcs_cmd, u8 *data); +int dsi_vc_dcs_read_2(enum omap_dsi_index ix, int channel, + u8 dcs_cmd, u16 *data); +int dsi_vc_set_max_rx_packet_size(enum omap_dsi_index ix, + int channel, u16 len); +int dsi_vc_send_null(enum omap_dsi_index ix, int channel); +int dsi_vc_send_bta_sync(enum omap_dsi_index ix, int channel); /* Board specific data */ +#define PWM2ON 0x03 +#define PWM2OFF 0x04 +#define TOGGLE3 0x92 +#define HDMI_GPIO_60 60 +#define HDMI_GPIO_41 41 +#define DLP_4430_GPIO_40 40 +#define DLP_4430_GPIO_44 44 +#define DLP_4430_GPIO_45 45 +#define DLP_4430_GPIO_59 59 + struct omap_dss_board_info { int (*get_last_off_on_transaction_id)(struct device *dev); int num_devices; @@ -299,6 +383,8 @@ struct omap_overlay_info { u16 out_width; /* if 0, out_width == width */ u16 out_height; /* if 0, out_height == height */ u8 global_alpha; + enum omap_overlay_zorder zorder; + u32 p_uv_addr; /* relevant for NV12 format only */ }; struct omap_overlay { @@ -377,6 +463,43 @@ struct omap_overlay_manager { int (*disable)(struct omap_overlay_manager *mgr); }; +enum omap_writeback_source_type { + OMAP_WB_SOURCE_OVERLAY = 0, + OMAP_WB_SOURCE_MANAGER = 1 +}; + + +struct omap_writeback_info { + bool enabled; + bool info_dirty; + enum omap_writeback_source source; + enum omap_writeback_source_type source_type; + unsigned long width; + unsigned long height; + enum omap_color_mode dss_mode; + enum omap_writeback_capturemode capturemode; + unsigned long paddr; + /* NV12 support*/ + unsigned long puv_addr; + +}; + +struct omap_writeback { + struct kobject kobj; + struct list_head list; + bool enabled; + bool info_dirty; + bool first_time; + /* mutex to control access to wb data */ + struct mutex lock; + struct omap_writeback_info info; + bool (*check_wb)(struct omap_writeback *wb); + + int (*set_wb_info)(struct omap_writeback *wb, struct omap_writeback_info *info); + void (*get_wb_info)(struct omap_writeback *wb, struct omap_writeback_info *info); + +}; + struct omap_dss_device { struct device dev; @@ -460,8 +583,10 @@ struct omap_dss_device { enum omap_display_caps caps; struct omap_overlay_manager *manager; + struct omap_writeback *wb_manager; enum omap_dss_display_state state; + enum omap_channel channel; /* platform specific */ int (*platform_enable)(struct omap_dss_device *dssdev); @@ -494,6 +619,7 @@ struct omap_dss_driver { int (*enable_te)(struct omap_dss_device *dssdev, bool enable); int (*get_te)(struct omap_dss_device *dssdev); + int (*wait_for_te)(struct omap_dss_device *dssdev); u8 (*get_rotate)(struct omap_dss_device *dssdev); int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); @@ -517,6 +643,15 @@ struct omap_dss_driver { int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); u32 (*get_wss)(struct omap_dss_device *dssdev); + +/*HDMI specific */ + void (*get_edid)(struct omap_dss_device *dssdev); + void (*set_custom_edid_timing_code)(struct omap_dss_device *dssdev, int mode, int code); + int (*hpd_enable)(struct omap_dss_device *dssdev); +}; + +struct pico_platform_data { + u8 gpio_intr; }; int omap_dss_register_driver(struct omap_dss_driver *); @@ -540,11 +675,13 @@ struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); int omap_dss_get_num_overlays(void); struct omap_overlay *omap_dss_get_overlay(int num); +struct omap_writeback *omap_dss_get_wb(int num); void omapdss_default_get_resolution(struct omap_dss_device *dssdev, u16 *xres, u16 *yres); int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); - +bool dispc_go_busy(enum omap_channel channel); +void dispc_go(enum omap_channel channel); typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); @@ -556,7 +693,8 @@ int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) #define to_dss_device(x) container_of((x), struct omap_dss_device, dev) -void omapdss_dsi_vc_enable_hs(int channel, bool enable); +void omapdss_dsi_vc_enable_hs(enum omap_dsi_index ix, int channel, + bool enable); int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); int omap_dsi_prepare_update(struct omap_dss_device *dssdev, diff --git a/arch/arm/plat-omap/include/plat/hdmi_lib.h b/arch/arm/plat-omap/include/plat/hdmi_lib.h new file mode 100644 index 000000000000..bf45e025dc98 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/hdmi_lib.h @@ -0,0 +1,428 @@ + /* + * hdmi_lib.h + * + * HDMI driver definition for TI OMAP processors. + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _HDMI_H_ +#define _HDMI_H_ + +#include <linux/string.h> + +#define HDMI_WP 0x58006000 +#define HDMI_CORE_SYS 0x58006400 +#define HDMI_CORE_AV 0x58006900 +#define HDMI_HDCP 0x58007000 + +#define HDMI_WP_AUDIO_DATA 0x8Cul + +#define DBG(format, ...) \ + printk(KERN_DEBUG "hdmi: " format, ## __VA_ARGS__) +#define ERR(format, ...) \ + printk(KERN_ERR "hdmi error: " format, ## __VA_ARGS__) + +#define BITS_32(in_NbBits) \ + ((((u32)1 << in_NbBits) - 1) | ((u32)1 << in_NbBits)) + +#define BITFIELD(in_UpBit, in_LowBit) \ + (BITS_32(in_UpBit) & ~((BITS_32(in_LowBit)) >> 1)) + +struct hdmi_irq_vector { + u8 pllRecal; + u8 pllUnlock; + u8 pllLock; + u8 phyDisconnect; + u8 phyConnect; + u8 phyShort5v; + u8 videoEndFrame; + u8 videoVsync; + u8 fifoSampleRequest; + u8 fifoOverflow; + u8 fifoUnderflow; + u8 ocpTimeOut; + u8 core; +}; + +typedef enum HDMI_PhyPwr_label { + HDMI_PHYPWRCMD_OFF = 0, + HDMI_PHYPWRCMD_LDOON = 1, + HDMI_PHYPWRCMD_TXON = 2 +} HDMI_PhyPwr_t, *pHDMI_PhyPwr_t; + +typedef enum HDMI_PllPwr_label { + HDMI_PLLPWRCMD_ALLOFF = 0, + HDMI_PLLPWRCMD_PLLONLY = 1, + HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, + HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 +} HDMI_PllPwr_t, *pHDMI_PllPwr_t; + +enum hdmi_core_inputbus_width { + HDMI_INPUT_8BIT = 0, + HDMI_INPUT_10BIT = 1, + HDMI_INPUT_12BIT = 2 +}; + +enum hdmi_core_dither_trunc { + HDMI_OUTPUTTRUNCATION_8BIT = 0, + HDMI_OUTPUTTRUNCATION_10BIT = 1, + HDMI_OUTPUTTRUNCATION_12BIT = 2, + HDMI_OUTPUTDITHER_8BIT = 3, + HDMI_OUTPUTDITHER_10BIT = 4, + HDMI_OUTPUTDITHER_12BIT = 5 +}; + +enum hdmi_core_deepcolor_ed { + HDMI_DEEPCOLORPACKECTDISABLE = 0, + HDMI_DEEPCOLORPACKECTENABLE = 1 +}; + +enum hdmi_core_packet_mode { + HDMI_PACKETMODERESERVEDVALUE = 0, + HDMI_PACKETMODE24BITPERPIXEL = 4, + HDMI_PACKETMODE30BITPERPIXEL = 5, + HDMI_PACKETMODE36BITPERPIXEL = 6, + HDMI_PACKETMODE48BITPERPIXEL = 7 +}; + +enum hdmi_core_hdmi_dvi { + HDMI_DVI = 0, + HDMI_HDMI = 1 +}; + +enum hdmi_core_tclkselclkmult { + FPLL05IDCK = 0, + FPLL10IDCK = 1, + FPLL20IDCK = 2, + FPLL40IDCK = 3 +}; + +struct hdmi_core_video_config_t { + enum hdmi_core_inputbus_width CoreInputBusWide; + enum hdmi_core_dither_trunc CoreOutputDitherTruncation; + enum hdmi_core_deepcolor_ed CoreDeepColorPacketED; + enum hdmi_core_packet_mode CorePacketMode; + enum hdmi_core_hdmi_dvi CoreHdmiDvi; + enum hdmi_core_tclkselclkmult CoreTclkSelClkMult; +}; + +enum hdmi_core_fs { + FS_32000 = 0, + FS_44100 = 1 +}; + +enum hdmi_core_layout { + LAYOUT_2CH = 0, + LAYOUT_8CH = 1 +}; + +enum hdmi_core_cts_mode { + CTS_MODE_HW = 0, + CTS_MODE_SW = 1 +}; + +enum hdmi_core_packet_ctrl { + PACKETENABLE = 1, + PACKETDISABLE = 0, + PACKETREPEATON = 1, + PACKETREPEATOFF = 0 +}; + +/* INFOFRAME_AVI_ definations */ +enum hdmi_core_infoframe { + INFOFRAME_AVI_DB1Y_RGB = 0, + INFOFRAME_AVI_DB1Y_YUV422 = 1, + INFOFRAME_AVI_DB1Y_YUV444 = 2, + INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0, + INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, + INFOFRAME_AVI_DB1B_NO = 0, + INFOFRAME_AVI_DB1B_VERT = 1, + INFOFRAME_AVI_DB1B_HORI = 2, + INFOFRAME_AVI_DB1B_VERTHORI = 3, + INFOFRAME_AVI_DB1S_0 = 0, + INFOFRAME_AVI_DB1S_1 = 1, + INFOFRAME_AVI_DB1S_2 = 2, + INFOFRAME_AVI_DB2C_NO = 0, + INFOFRAME_AVI_DB2C_ITU601 = 1, + INFOFRAME_AVI_DB2C_ITU709 = 2, + INFOFRAME_AVI_DB2C_EC_EXTENDED = 3, + INFOFRAME_AVI_DB2M_NO = 0, + INFOFRAME_AVI_DB2M_43 = 1, + INFOFRAME_AVI_DB2M_169 = 2, + INFOFRAME_AVI_DB2R_SAME = 8, + INFOFRAME_AVI_DB2R_43 = 9, + INFOFRAME_AVI_DB2R_169 = 10, + INFOFRAME_AVI_DB2R_149 = 11, + INFOFRAME_AVI_DB3ITC_NO = 0, + INFOFRAME_AVI_DB3ITC_YES = 1, + INFOFRAME_AVI_DB3EC_XVYUV601 = 0, + INFOFRAME_AVI_DB3EC_XVYUV709 = 1, + INFOFRAME_AVI_DB3Q_DEFAULT = 0, + INFOFRAME_AVI_DB3Q_LR = 1, + INFOFRAME_AVI_DB3Q_FR = 2, + INFOFRAME_AVI_DB3SC_NO = 0, + INFOFRAME_AVI_DB3SC_HORI = 1, + INFOFRAME_AVI_DB3SC_VERT = 2, + INFOFRAME_AVI_DB3SC_HORIVERT = 3, + INFOFRAME_AVI_DB5PR_NO = 0, + INFOFRAME_AVI_DB5PR_2 = 1, + INFOFRAME_AVI_DB5PR_3 = 2, + INFOFRAME_AVI_DB5PR_4 = 3, + INFOFRAME_AVI_DB5PR_5 = 4, + INFOFRAME_AVI_DB5PR_6 = 5, + INFOFRAME_AVI_DB5PR_7 = 6, + INFOFRAME_AVI_DB5PR_8 = 7, + INFOFRAME_AVI_DB5PR_9 = 8, + INFOFRAME_AVI_DB5PR_10 = 9 +}; + +struct hdmi_core_infoframe_avi { + u8 db1y_rgb_yuv422_yuv444; + u8 db1a_active_format_off_on; + u8 db1b_no_vert_hori_verthori; + u8 db1s_0_1_2; + u8 db2c_no_itu601_itu709_extented; + u8 db2m_no_43_169; + u8 db2r_same_43_169_149; + u8 db3itc_no_yes; + u8 db3ec_xvyuv601_xvyuv709; + u8 db3q_default_lr_fr; + u8 db3sc_no_hori_vert_horivert; + u8 db4vic_videocode; + u8 db5pr_no_2_3_4_5_6_7_8_9_10; + u16 db6_7_lineendoftop; + u16 db8_9_linestartofbottom; + u16 db10_11_pixelendofleft; + u16 db12_13_pixelstartofright; +}; + +struct hdmi_core_packet_enable_repeat { + u32 AudioPacketED; + u32 AudioPacketRepeat; + u32 AVIInfoFrameED; + u32 AVIInfoFrameRepeat; + u32 GeneralcontrolPacketED; + u32 GeneralcontrolPacketRepeat; + u32 GenericPacketED; + u32 GenericPacketRepeat; +}; + +enum hdmi_stereo_channel { + HDMI_STEREO_NOCHANNEL = 0, + HDMI_STEREO_ONECHANNELS = 1, + HDMI_STEREO_TWOCHANNELS = 2, + HDMI_STEREO_THREECHANNELS = 3, + HDMI_STEREO_FOURCHANNELS = 4 +}; + +enum hdmi_cea_code { + HDMI_CEA_CODE_00 = 0x0, + HDMI_CEA_CODE_01 = 0x1, + HDMI_CEA_CODE_02 = 0x2, + HDMI_CEA_CODE_03 = 0x3, + HDMI_CEA_CODE_04 = 0x4, + HDMI_CEA_CODE_05 = 0x5, + HDMI_CEA_CODE_06 = 0x6, + HDMI_CEA_CODE_07 = 0x7, + HDMI_CEA_CODE_08 = 0x8, + HDMI_CEA_CODE_09 = 0x9, + HDMI_CEA_CODE_0A = 0xA, + HDMI_CEA_CODE_0B = 0xB, + HDMI_CEA_CODE_0C = 0xC, + HDMI_CEA_CODE_0D = 0xD, + HDMI_CEA_CODE_0E = 0xE, + HDMI_CEA_CODE_0F = 0xF, + HDMI_CEA_CODE_10 = 0x10, + HDMI_CEA_CODE_11 = 0x11, + HDMI_CEA_CODE_12 = 0x12, + HDMI_CEA_CODE_13 = 0x13, + HDMI_CEA_CODE_14 = 0x14, + HDMI_CEA_CODE_15 = 0x15, + HDMI_CEA_CODE_16 = 0x16, + HDMI_CEA_CODE_17 = 0x17, + HDMI_CEA_CODE_18 = 0x18, + HDMI_CEA_CODE_19 = 0x19, + HDMI_CEA_CODE_1A = 0x1A, + HDMI_CEA_CODE_1B = 0x1B, + HDMI_CEA_CODE_1C = 0x1C, + HDMI_CEA_CODE_1D = 0x1D, + HDMI_CEA_CODE_1E = 0x1E, + HDMI_CEA_CODE_1F = 0x1F, + HDMI_CEA_CODE_20 = 0x20, + HDMI_CEA_CODE_21 = 0x21, + HDMI_CEA_CODE_22 = 0x22, + HDMI_CEA_CODE_23 = 0x23, + HDMI_CEA_CODE_24 = 0x24, + HDMI_CEA_CODE_25 = 0x25, + HDMI_CEA_CODE_26 = 0x26 +}; + +enum hdmi_iec_format { + HDMI_AUDIO_FORMAT_LPCM = 0, + HDMI_AUDIO_FORMAT_IEC = 1 +}; + +enum hdmi_audio_justify { + HDMI_AUDIO_JUSTIFY_LEFT = 0, + HDMI_AUDIO_JUSTIFY_RIGHT = 1 +}; + +enum hdmi_sample_order { + HDMI_SAMPLE_RIGHT_FIRST = 0, + HDMI_SAMPLE_LEFT_FIRST = 1 +}; + +enum hdmi_sample_perword { + HDMI_ONEWORD_ONE_SAMPLE = 0, + HDMI_ONEWORD_TWO_SAMPLES = 1 +}; + +enum hdmi_sample_size { + HDMI_SAMPLE_16BITS = 0, + HDMI_SAMPLE_24BITS = 1 +}; + +struct hdmi_audio_format { + enum hdmi_stereo_channel stereo_channel_enable; + enum hdmi_cea_code audio_channel_location; + enum hdmi_iec_format iec; + enum hdmi_audio_justify justify; + enum hdmi_sample_order left_before; + enum hdmi_sample_perword sample_number; + enum hdmi_sample_size sample_size; +}; + +enum hdmi_dma_irq { + HDMI_THRESHOLD_DMA = 0, + HDMI_THRESHOLD_IRQ = 1 +}; + +enum hdmi_block_start_end { + HDMI_BLOCK_STARTEND_ON = 0, + HDMI_BLOCK_STARTEND_OFF = 1 +}; + +struct hdmi_audio_dma { + u8 dma_transfer; + u8 block_size; + enum hdmi_dma_irq dma_or_irq; + u16 threshold_value; + enum hdmi_block_start_end block_start_end; +}; + +enum hdmi_packing_mode { + HDMI_PACK_10b_RGB_YUV444 = 0, + HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, + HDMI_PACK_20b_YUV422 = 2, + HDMI_PACK_ALREADYPACKED = 7 +}; + +struct hdmi_video_format { + enum hdmi_packing_mode packingMode; + u32 linePerPanel; + u32 pixelPerLine; +}; + +struct hdmi_video_interface { + int vSyncPolarity; + int hSyncPolarity; + int interlacing; + int timingMode; +}; + +struct hdmi_video_timing { + u32 horizontalBackPorch; + u32 horizontalFrontPorch; + u32 horizontalSyncPulse; + u32 verticalBackPorch; + u32 verticalFrontPorch; + u32 verticalSyncPulse; +}; + +typedef struct HDMI_Timing_label { + u32 pixelPerLine; + u32 linePerPanel; + u32 horizontalBackPorch; + u32 horizontalFrontPorch; + u32 horizontalSyncPulse; + u32 verticalBackPorch; + u32 verticalFrontPorch; + u32 verticalSyncPulse; + u32 pplclk; +} HDMI_Timing_t, *pHDMI_Timing_t; + +struct hdmi_config { + u16 ppl; /* pixel per line */ + u16 lpp; /* line per panel */ + u32 pixel_clock; + u16 hsw; /* Horizontal synchronization pulse width */ + u16 hfp; /* Horizontal front porch */ + u16 hbp; /* Horizontal back porch */ + u16 vsw; /* Vertical synchronization pulse width */ + u16 vfp; /* Vertical front porch */ + u16 vbp; /* Vertical back porch */ + u16 interlace; + u16 h_pol; + u16 v_pol; + u16 hdmi_dvi; + u16 video_format; +}; + +enum hdmi_core_if_fs { + IF_FS_NO = 0x0, + IF_FS_32000 = 0x1, + IF_FS_44100 = 0x2, + IF_FS_48000 = 0x3, + IF_FS_88200 = 0x4, + IF_FS_96000 = 0x5, + IF_FS_176400 = 0x6, + IF_FS_192000 = 0x7 +}; + +enum hdmi_core_if_sample_size{ + IF_NO_PER_SAMPLE = 0x0, + IF_16BIT_PER_SAMPLE = 0x1, + IF_20BIT_PER_SAMPLE = 0x2, + IF_24BIT_PER_SAMPLE = 0x3 +}; + +struct hdmi_core_audio_config { + enum hdmi_core_fs fs; /* 0=32KHz - 1=44.1KHz */ + u32 n; + u32 cts; + u32 aud_par_busclk; + enum hdmi_core_layout layout; /* 0: 2Ch - 1: 8Ch */ + enum hdmi_core_cts_mode cts_mode; /* 0: HW - 1: SW*/ + enum hdmi_core_if_fs if_fs; + u32 if_channel_number; + enum hdmi_core_if_sample_size if_sample_size; + enum hdmi_cea_code if_audio_channel_location; + }; + +/* Function prototype */ +int HDMI_W1_StopVideoFrame(u32); +int HDMI_W1_StartVideoFrame(u32); +int HDMI_W1_SetWaitPhyPwrState(u32 name, HDMI_PhyPwr_t param); +int HDMI_W1_SetWaitPllPwrState(u32 name, HDMI_PllPwr_t param); +int HDMI_W1_SetWaitSoftReset(void); +int hdmi_w1_wrapper_disable(u32); +int hdmi_w1_wrapper_enable(u32); +int hdmi_w1_stop_audio_transfer(u32); +int hdmi_w1_start_audio_transfer(u32); +int HDMI_CORE_DDC_READEDID(u32 Core, u8 *data); +int DSS_HDMI_CONFIG(HDMI_Timing_t timings, u32 video_format, u32 mode); +void HDMI_W1_HPD_handler(int *r); +int hdmi_lib_init(void); +void hdmi_lib_exit(void); + +#endif + diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index 128b549c2796..55e24a4127cf 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -205,6 +205,7 @@ #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) #define L4_PER_44XX_SIZE SZ_4M +#define L4_ABE_44XX_BASE 0x49000000 #define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE /* 0x49000000 --> 0xfb000000 */ #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 0752af9d099e..a45a0b1c348f 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -13,6 +13,9 @@ #ifndef __MACH_IOMMU_H #define __MACH_IOMMU_H +#include <linux/device.h> +#include <linux/cdev.h> + struct iotlb_entry { u32 da; u32 pa; @@ -50,6 +53,8 @@ struct iommu { int (*isr)(struct iommu *obj); void *ctx; /* iommu context: registres saved area */ + struct cdev cdev; + int minor; }; struct cr_regs { @@ -80,6 +85,7 @@ struct iommu_functions { int (*enable)(struct iommu *obj); void (*disable)(struct iommu *obj); + void (*set_twl)(struct iommu *obj, bool on); u32 (*fault_isr)(struct iommu *obj, u32 *ra); void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); @@ -104,6 +110,11 @@ struct iommu_platform_data { const int nr_tlb_entries; }; +#define IOMMU_IOC_MAGIC 'I' + +#define IOMMU_IOCSETTLBENT _IO(IOMMU_IOC_MAGIC, 0) + + #if defined(CONFIG_ARCH_OMAP1) #error "iommu for this processor not implemented yet" #else @@ -143,6 +154,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); extern u32 iotlb_cr_to_virt(struct cr_regs *cr); extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); +extern void iommu_set_twl(struct iommu *obj, bool on); extern void flush_iotlb_page(struct iommu *obj, u32 da); extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); extern void flush_iotlb_all(struct iommu *obj); @@ -165,4 +177,5 @@ extern int foreach_iommu_device(void *data, extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len); extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len); +extern int iommu_get_plat_data_size(void); #endif /* __MACH_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h index 729166b76a7c..0486d64c24f7 100644 --- a/arch/arm/plat-omap/include/plat/mailbox.h +++ b/arch/arm/plat-omap/include/plat/mailbox.h @@ -7,6 +7,7 @@ #include <linux/workqueue.h> #include <linux/blkdev.h> #include <linux/interrupt.h> +#include <linux/kfifo.h> typedef u32 mbox_msg_t; struct omap_mbox; @@ -19,6 +20,8 @@ typedef int __bitwise omap_mbox_type_t; #define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1) #define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2) +#define MBOX_KFIFO_SIZE (256) + struct omap_mbox_ops { omap_mbox_type_t type; int (*startup)(struct omap_mbox *mbox); @@ -42,7 +45,7 @@ struct omap_mbox_ops { struct omap_mbox_queue { spinlock_t lock; - struct request_queue *queue; + struct kfifo fifo; struct work_struct work; struct tasklet_struct tasklet; int (*callback)(void *); diff --git a/arch/arm/plat-omap/include/plat/mcpdm.h b/arch/arm/plat-omap/include/plat/mcpdm.h new file mode 100644 index 000000000000..3c7c783c36e1 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/mcpdm.h @@ -0,0 +1 @@ +#include "../../../../../sound/soc/omap/mcpdm.h" diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index f5a08367cd0c..ac33cc848097 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -20,6 +20,10 @@ #include <plat/board.h> #include <plat/omap_hwmod.h> +#ifdef CONFIG_TIWLAN_SDIO +#include <linux/mmc/card.h> +#endif + #define OMAP15XX_NR_MMC 1 #define OMAP16XX_NR_MMC 2 #define OMAP1_MMC_SIZE 0x080 @@ -50,6 +54,13 @@ #define MMC_SUPPORT_18V_3V (1 << 0) #define MMC_SUPPORT_3V (1 << 1) +#ifdef CONFIG_TIWLAN_SDIO +struct embedded_sdio_data { +struct sdio_cis cis; +struct sdio_embedded_func *funcs; +unsigned int quirks; +}; +#endif struct mmc_dev_attr { u8 flags; @@ -151,6 +162,13 @@ struct omap_mmc_platform_data { unsigned int ban_openended:1; +#ifdef CONFIG_TIWLAN_SDIO + struct embedded_sdio_data *embedded_sdio; + int (*register_status_notify) + (void (*callback)(int card_present, void *dev_id), + void *dev_id); +#endif + } slots[OMAP_MMC_MAX_SLOTS]; }; diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index 76832d387ea6..8b3f12ff5cbc 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h @@ -49,5 +49,8 @@ #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) #define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) +#define OMAP4_MMU1_BASE 0x55082000 +#define OMAP4_MMU2_BASE 0x4A066000 + #endif /* __ASM_ARCH_OMAP44XX_H */ diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h new file mode 100644 index 000000000000..351553d18fc4 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/remoteproc.h @@ -0,0 +1,75 @@ +/* + * OMAP Remote Processor driver + * + * Copyright (C) 2010 Texas Instruments Inc. + * + * Written by Ohad Ben-Cohen <ohad@wizery.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef REMOTEPROC_H +#define REMOTEPROC_H + +#include <linux/ioctl.h> +#include <linux/cdev.h> + +#define RPROC_IOC_MAGIC 'P' + +#define RPROC_IOCMONITOR _IO(RPROC_IOC_MAGIC, 0) +#define RPROC_IOCSTART _IO(RPROC_IOC_MAGIC, 1) +#define RPROC_IOCSTOP _IO(RPROC_IOC_MAGIC, 2) +#define RPROC_IOCGETSTATE _IOR(RPROC_IOC_MAGIC, 3, int) + +#define RPROC_IOC_MAXNR (3) + +struct omap_rproc; + +struct omap_rproc_ops { + int (*startup)(struct omap_rproc *rproc); + int (*shutdown)(struct omap_rproc *rproc); + int (*start)(struct omap_rproc *rproc); + int (*stop)(struct omap_rproc *rproc); + int (*get_state)(struct omap_rproc *rproc); +}; + +struct omap_rproc_clk_t { + void *clk_handle; + const char *dev_id; + const char *con_id; +}; + +struct omap_rproc_platform_data { + struct omap_rproc_ops *ops; + char *name; + char *oh_name; +}; + +struct omap_rproc { + struct device *dev; + struct cdev cdev; + atomic_t count; + int state; + int minor; +}; + +extern struct omap_rproc_platform_data *remoteproc_get_plat_data(void); +extern int remoteproc_get_plat_data_size(void); + +struct omap_rproc *rproc_get(const char *name); +void rproc_put(struct omap_rproc *obj); + +#endif /* REMOTEPROC_H */ diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h index d8a03ced3b10..3792bdea2f6d 100644 --- a/arch/arm/plat-omap/include/plat/vrfb.h +++ b/arch/arm/plat-omap/include/plat/vrfb.h @@ -35,6 +35,7 @@ struct vrfb { bool yuv_mode; }; +#ifdef CONFIG_OMAP2_VRFB extern int omap_vrfb_request_ctx(struct vrfb *vrfb); extern void omap_vrfb_release_ctx(struct vrfb *vrfb); extern void omap_vrfb_adjust_size(u16 *width, u16 *height, @@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot); extern void omap_vrfb_restore_context(void); +#else +static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; } +static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {} +static inline void omap_vrfb_adjust_size(u16 *width, u16 *height, + u8 bytespp) {} +static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp) + { return 0; } +static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp) + { return 0; } +static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, + u16 width, u16 height, unsigned bytespp, bool yuv_mode) {} +static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot) + { return 0; } +static inline void omap_vrfb_restore_context(void) {} +#endif #endif /* __VRFB_H */ diff --git a/arch/arm/plat-omap/include/plat/wifi_tiwlan.h b/arch/arm/plat-omap/include/plat/wifi_tiwlan.h new file mode 100644 index 000000000000..b0332b04ddc9 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/wifi_tiwlan.h @@ -0,0 +1,23 @@ +/* mach/wifi_tiwlan.h + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef _LINUX_WIFI_TIWLAN_H_ +#define _LINUX_WIFI_TIWLAN_H_ + +struct wifi_platform_data { + int (*set_power)(int val); + int (*set_reset)(int val); + int (*set_carddetect)(int val); + void *(*mem_prealloc)(int section, unsigned long size); +}; + +#endif diff --git a/arch/arm/plat-omap/include/syslink/GlobalTypes.h b/arch/arm/plat-omap/include/syslink/GlobalTypes.h new file mode 100644 index 000000000000..6cd959cde952 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/GlobalTypes.h @@ -0,0 +1,154 @@ +/* + * GlobalTypes.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef __GLOBALTYPES_H +#define __GLOBALTYPES_H + +#define REG volatile + +/* + * Definition: RET_CODE_BASE + * + * DESCRIPTION: Base value for return code offsets + * + * + */ +#define RET_CODE_BASE 0 + +/* + * TYPE: ReturnCode_t + * + * DESCRIPTION: Return codes to be returned by all library functions + * + * + */ +enum ReturnCode_label { +RET_OK = 0, +RET_FAIL = -1, +RET_BAD_NULL_PARAM = -2, +RET_PARAM_OUT_OF_RANGE = -3, +RET_INVALID_ID = -4, +RET_EMPTY = -5, +RET_FULL = -6, +RET_TIMEOUT = -7, +RET_INVALID_OPERATION = -8, +/* Add new error codes at end of above list */ +RET_NUM_RET_CODES /* this should ALWAYS be LAST entry */ +}; + + + +/* + * MACRO: RD_MEM_32_VOLATILE, WR_MEM_32_VOLATILE + * + * DESCRIPTION: 32 bit register access macros + * + * + */ +#define RD_MEM_32_VOLATILE(addr) \ +((unsigned long)(*((REG unsigned long *)(addr)))) + +#define WR_MEM_32_VOLATILE(addr, data) \ +(*((REG unsigned long *)(addr)) = (unsigned long)(data)) + + + + +#ifdef CHECK_INPUT_PARAMS +/* + * MACRO: CHECK_INPUT_PARAMS + * + * DESCRIPTION: Checks an input code and returns a specified value if code is + * invalid value, also writes spy value if error found. + * + * NOTE: Can be disabled to save HW cycles. + * + * + */ +#define CHECK_INPUT_PARAM(actualValue, invalidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) do {\ + if ((invalidValue) == (actualValue)) {\ + RES_Set((spyCodeIfMisMatch));\ + return returnCodeIfMismatch; \ + } \ +} while (0) + +/* + * MACRO: CHECK_INPUT_RANGE + * + * DESCRIPTION: Checks an input value and returns a specified value if not in + * specified range, also writes spy value if error found. + * +* NOTE: Can be disabled to save HW cycles. + * + * + */ +#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) do {\ + if (((actualValue) < (minValidValue)) || \ + ((actualValue) > (maxValidValue))) {\ + RES_Set((spyCodeIfMisMatch));\ + return returnCodeIfMismatch; \ + } \ +} while (0) + +/* + * MACRO: CHECK_INPUT_RANGE_MIN0 + * + * DESCRIPTION: Checks an input value and returns a + * specified value if not in + * specified range, also writes spy value if error found. + * The minimum + * value is 0. + * + * NOTE: Can be disabled to save HW cycles. + * + * + */ +#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) do {\ + if ((actualValue) > (maxValidValue)) {\ + RES_Set((spyCodeIfMisMatch));\ + return returnCodeIfMismatch; \ + } \ +} while (0) + +#else + +#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\ +spyCodeIfMisMatch) + +#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue, \ +returnCodeIfMismatch) + +#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) + +#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue , \ +maxValidValue, returnCodeIfMismatch) + +#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) + +#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, \ +maxValidValue, returnCodeIfMismatch) + +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __GLOBALTYPES_H */ diff --git a/arch/arm/plat-omap/include/syslink/MBXAccInt.h b/arch/arm/plat-omap/include/syslink/MBXAccInt.h new file mode 100644 index 000000000000..84e333d0d5da --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MBXAccInt.h @@ -0,0 +1,550 @@ +/* + * MBXAccInt.h + * + * Notify mailbox driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef _MLB_ACC_INT_H +#define _MLB_ACC_INT_H + + +/* + * EXPORTED DEFINITIONS + * + */ + + +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET (unsigned long)(0x0040) +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP (unsigned long)(0x0004) +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_BANKS (unsigned long)(16) + +/* Register offset address definitions relative +to register set MAILBOX_MESSAGE___REGSET_0_15 */ + +#define MLB_MAILBOX_MESSAGE___0_15_OFFSET (unsigned long)(0x0) + + +/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 +address offset, bank address increment and number of banks */ + +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET (unsigned long)(0x0080) +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP (unsigned long)(0x0004) +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_BANKS (unsigned long)(16) + +/* Register offset address definitions relative to +register set MAILBOX_FIFOSTATUS___REGSET_0_15 */ + +#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET (unsigned long)(0x0) + + +/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 +address offset, bank address increment and number of banks */ + +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET (unsigned long)(0x00c0) +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP (unsigned long)(0x0004) +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_BANKS (unsigned long)(16) + +/* Register offset address definitions relative to +register set MAILBOX_MSGSTATUS___REGSET_0_15 */ + +#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET (unsigned long)(0x0) + + +/*Register set MAILBOX_IRQSTATUS___REGSET_0_3 address +offset, bank address increment and number of banks */ + +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET (unsigned long)(0x0100) +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP (unsigned long)(0x0008) +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_BANKS (unsigned long)(4) + +#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET (unsigned long)(0x0104) +#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP (unsigned long)(0x0010) +#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_BANKS (unsigned long)(4) + +/* Register offset address definitions relative to +register set MAILBOX_IRQSTATUS___REGSET_0_3 */ + +#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET (unsigned long)(0x0) + + +/* Register set MAILBOX_IRQENABLE___REGSET_0_3 +address offset, bank address increment and number of banks */ + +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET (unsigned long)(0x0104) +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP (unsigned long)(0x0008) +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_BANKS (unsigned long)(4) + +#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET (unsigned long)(0x0108) +#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP (unsigned long)(0x0010) +#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_BANKS (unsigned long)(4) + +#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_OFFSET (unsigned long)(0x010C) +#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_STEP (unsigned long)(0x0010) +#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_BANKS (unsigned long)(4) + +/* Register offset address definitions relative to register +set MAILBOX_IRQENABLE___REGSET_0_3 */ + +#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET (unsigned long)(0x0) + + +/* Register offset address definitions */ + +#define MLB_MAILBOX_REVISION_OFFSET (unsigned long)(0x0) +#define MLB_MAILBOX_SYSCONFIG_OFFSET (unsigned long)(0x10) +#define MLB_MAILBOX_SYSSTATUS_OFFSET (unsigned long)(0x14) + + +/* Bitfield mask and offset declarations */ + +#define MLB_MAILBOX_REVISION_Rev_MASK (unsigned long)(0xff) +#define MLB_MAILBOX_REVISION_Rev_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK (unsigned long)(0x100) +#define MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET (unsigned long)(8) + +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK (unsigned long)(0x18) +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET (unsigned long)(3) + +#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK (unsigned long)(0x2) +#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET (unsigned long)(1) + +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK (unsigned long)(0x1) +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK (unsigned long)(0x1) +#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK \ +(unsigned long)(0xffffffff) + +#define MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK (unsigned long)(0x1) +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK (unsigned long)(0x7f) +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK \ +(unsigned long)(0x80000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET \ +(unsigned long)(31) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK \ +(unsigned long)(0x40000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET \ +(unsigned long)(30) + + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK \ +(unsigned long)(0x20000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET \ +(unsigned long)(29) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK \ +(unsigned long)(0x10000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET \ +(unsigned long)(28) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK \ +(unsigned long)(0x8000000) +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET \ +(unsigned long)(27) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK \ +(unsigned long)(0x4000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET \ +(unsigned long)(26) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK \ +(unsigned long)(0x2000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET \ +(unsigned long)(25) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK \ +(unsigned long)(0x1000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET \ +(unsigned long)(24) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK \ +(unsigned long)(0x800000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET \ +(unsigned long)(23) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK \ +(unsigned long)(0x400000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET \ +(unsigned long)(22) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK \ +(unsigned long)(0x200000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET \ +(unsigned long)(21) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK \ +(unsigned long)(0x100000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET \ +(unsigned long)(20) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK \ +(unsigned long)(0x80000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET \ +(unsigned long)(19) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK \ +(unsigned long)(0x40000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET \ +(unsigned long)(18) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK \ +(unsigned long)(0x20000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET \ +(unsigned long)(17) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK \ +(unsigned long)(0x10000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET \ +(unsigned long)(16) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK \ +(unsigned long)(0x8000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET \ +(unsigned long)(15) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK \ +(unsigned long)(0x4000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET \ +(unsigned long)(14) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK \ +(unsigned long)(0x2000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET \ +(unsigned long)(13) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK \ +(unsigned long)(0x1000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET \ +(unsigned long)(12) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK \ +(unsigned long)(0x800) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET \ +(unsigned long)(11) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK \ +(unsigned long)(0x400) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET \ +(unsigned long)(10) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK \ +(unsigned long)(0x200) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET \ +(unsigned long)(9) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK \ +(unsigned long)(0x100) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET \ +(unsigned long)(8) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK \ +(unsigned long)(0x80) +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET \ +(unsigned long)(7) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK \ +(unsigned long)(0x40) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET \ +(unsigned long)(6) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK \ +(unsigned long)(0x20) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET \ +(unsigned long)(5) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK \ +(unsigned long)(0x10) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET \ +(unsigned long)(4) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK \ +(unsigned long)(0x8) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET \ +(unsigned long)(3) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK \ +(unsigned long)(0x4) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET \ +(unsigned long)(2) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK \ +(unsigned long)(0x2) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET \ +(unsigned long)(1) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK \ +(unsigned long)(0x1) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET \ +(unsigned long)(0) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK \ +(unsigned long)(0x80000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET \ +(unsigned long)(31) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK \ +(unsigned long)(0x40000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET \ +(unsigned long)(30) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK \ +(unsigned long)(0x20000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET \ +(unsigned long)(29) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK \ +(unsigned long)(0x10000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET \ +(unsigned long)(28) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK \ +(unsigned long)(0x8000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET \ +(unsigned long)(27) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK \ +(unsigned long)(0x4000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET \ +(unsigned long)(26) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK \ +(unsigned long)(0x2000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET \ +(unsigned long)(25) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK \ +(unsigned long)(0x1000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET \ +(unsigned long)(24) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK \ +(unsigned long)(0x800000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET \ +(unsigned long)(23) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK \ +(unsigned long)(0x400000) +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET \ +(unsigned long)(22) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK \ +(unsigned long)(0x200000) +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET \ +(unsigned long)(21) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK \ +(unsigned long)(0x100000) +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET \ +(unsigned long)(20) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK \ +(unsigned long)(0x80000) +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET \ +(unsigned long)(19) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK \ +(unsigned long)(0x40000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET \ +(unsigned long)(18) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK \ +(unsigned long)(0x20000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET \ +(unsigned long)(17) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK \ +(unsigned long)(0x10000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET \ +(unsigned long)(16) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK \ +(unsigned long)(0x8000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET \ +(unsigned long)(15) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK \ +(unsigned long)(0x4000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET \ +(unsigned long)(14) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK \ +(unsigned long)(0x2000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET \ +(unsigned long)(13) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK \ +(unsigned long)(0x1000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET \ +(unsigned long)(12) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK \ +(unsigned long)(0x800) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET \ +(unsigned long)(11) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK \ +(unsigned long)(0x400) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET \ +(unsigned long)(10) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK \ +(unsigned long)(0x200) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET \ +(unsigned long)(9) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK \ +(unsigned long)(0x100) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET \ +(unsigned long)(8) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK \ +(unsigned long)(0x80) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET \ +(unsigned long)(7) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK \ +(unsigned long)(0x40) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET \ +(unsigned long)(6) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK \ +(unsigned long)(0x20) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET \ +(unsigned long)(5) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK \ +(unsigned long)(0x10) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET \ +(unsigned long)(4) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK \ +(unsigned long)(0x8) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET \ +(unsigned long)(3) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK \ +(unsigned long)(0x4) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET \ +(unsigned long)(2) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK \ +(unsigned long)(0x2) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET \ +(unsigned long)(1) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK \ +(unsigned long)(0x1) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET \ +(unsigned long)(0) + + +/* + * EXPORTED TYPES + * + */ + +/* The following type definitions +represent the enumerated values for each bitfield */ + +enum MLBMAILBOX_SYSCONFIGSIdleModeE { + MLBMAILBOX_SYSCONFIGSIdleModeb00 = 0x0000, + MLBMAILBOX_SYSCONFIGSIdleModeb01 = 0x0001, + MLBMAILBOX_SYSCONFIGSIdleModeb10 = 0x0002, + MLBMAILBOX_SYSCONFIGSIdleModeb11 = 0x0003 +}; + +enum MLBMAILBOX_SYSCONFIGSoftResetE { + MLBMAILBOX_SYSCONFIGSoftResetb0 = 0x0000, + MLBMAILBOX_SYSCONFIGSoftResetb1 = 0x0001 +}; + +enum MLBMAILBOX_SYSCONFIGAutoIdleE { + MLBMAILBOX_SYSCONFIGAutoIdleb0 = 0x0000, + MLBMAILBOX_SYSCONFIGAutoIdleb1 = 0x0001 +}; + +enum MLBMAILBOX_SYSSTATUSResetDoneE { + MLBMAILBOX_SYSSTATUSResetDonerstongoing = 0x0000, + MLBMAILBOX_SYSSTATUSResetDonerstcomp = 0x0001 +}; + +#endif /* _MLB_ACC_INT_H */ diff --git a/arch/arm/plat-omap/include/syslink/MBXRegAcM.h b/arch/arm/plat-omap/include/syslink/MBXRegAcM.h new file mode 100644 index 000000000000..1c6732ecc9a2 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MBXRegAcM.h @@ -0,0 +1,3027 @@ +/* + * MBXRegAcM.h + * + * Notify mailbox driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _MBX_REG_ACM_H +#define _MBX_REG_ACM_H + + +#include <syslink/GlobalTypes.h> +#include <syslink/MBXAccInt.h> + + +/* + * EXPORTED DEFINITIONS + * + */ + +#if defined(USE_LEVEL_1_MACROS) + +#define MLBMAILBOX_REVISIONReadRegister32(base_address)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +MLB_MAILBOX_REVISION_OFFSET)) + + + +#define MLBMAILBOX_REVISIONRevRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+ \ +(MLB_MAILBOX_REVISION_OFFSET)))) &\ +MLB_MAILBOX_REVISION_Rev_MASK) >>\ +MLB_MAILBOX_REVISION_Rev_OFFSET)) + + + +#define MLBMAILBOX_REVISIONRevGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_REVISION_Rev_MASK) \ +>> MLB_MAILBOX_REVISION_Rev_OFFSET)) + + + +#define MLBMAILBOX_SYSCONFIGReadRegister32(base_address)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +MLB_MAILBOX_SYSCONFIG_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGWriteRegister32(base_address, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+ \ + offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_SYSCONFIGClockActivityRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGClockActivityGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK) \ +>> MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb0032(base_address)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb00 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb0132(base_address)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb01 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb1032(base_address)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb10 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb1132(base_address)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb11 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >> \ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGSIdleModeIsb0032(var)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb00 == \ +(MLBMAILBOX_SYSCONFIGSIdleModeE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeIsb0132(var)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb01 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeIsb1032(var)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb10 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeIsb1132(var)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb11 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(base_address, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+ \ + offset, newValue);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb0032(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb00 <<\ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb0132(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb01 <<\ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb1032(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb10 <<\ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb1132(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb11 <<\ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeSet32(var, value)\ +(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK)) |\ +((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK))) + +#define MLBMAILBOX_SYSCONFIGSoftResetRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGSoftResetReadIsb032(base_address)\ +((MLBMAILBOX_SYSCONFIGSoftResetb0 == (MLBMAILBOX_SYSCONFIGSoftResetE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSoftResetReadIsb132(base_address)\ +((MLBMAILBOX_SYSCONFIGSoftResetb1 == (MLBMAILBOX_SYSCONFIGSoftResetE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSoftResetGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >> \ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGSoftResetIsb032(var)\ +((MLBMAILBOX_SYSCONFIGSoftResetb0 == (MLBMAILBOX_SYSCONFIGSoftResetE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSoftResetIsb132(var)\ +((MLBMAILBOX_SYSCONFIGSoftResetb1 == (MLBMAILBOX_SYSCONFIGSoftResetE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(base_address, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSoftResetWriteb032(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSoftResetb0 <<\ + MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSoftResetWriteb132(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSoftResetb1 <<\ + MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSoftResetSet32(var, value)\ +(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK)) |\ +((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET) &\ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGAutoIdleReadIsb032(base_address)\ +((MLBMAILBOX_SYSCONFIGAutoIdleb0 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleReadIsb132(base_address)\ +((MLBMAILBOX_SYSCONFIGAutoIdleb1 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >> MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGAutoIdleIsb032(var)\ +((MLBMAILBOX_SYSCONFIGAutoIdleb0 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleIsb132(var)\ +((MLBMAILBOX_SYSCONFIGAutoIdleb1 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(base_address, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGAutoIdleWriteb032(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGAutoIdleb0 <<\ + MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGAutoIdleWriteb132(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGAutoIdleb1 <<\ + MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGAutoIdleSet32(var, value)\ +(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK)) |\ +((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK))) + +#define MLBMAILBOX_SYSSTATUSReadRegister32(base_address)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +MLB_MAILBOX_SYSSTATUS_OFFSET)) + +#define MLBMAILBOX_SYSSTATUSResetDoneRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)) + +#define MLBMAILBOX_SYSSTATUSResetDoneReadisrstongoing32(base_address)\ +((MLBMAILBOX_SYSSTATUSResetDonerstongoing == (MLBMAILBOX_SYSSTATUSResetDoneE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))) + +#define MLBMAILBOX_SYSSTATUSResetDoneReadisrstcomp32(base_address)\ +((MLBMAILBOX_SYSSTATUSResetDonerstcomp == (MLBMAILBOX_SYSSTATUSResetDoneE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))) + +#define MLBMAILBOX_SYSSTATUSResetDoneGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >> \ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)) + +#define MLBMAILBOX_SYSSTATUSResetDoneisrstongoing32(var)\ +((MLBMAILBOX_SYSSTATUSResetDonerstongoing == (MLBMAILBOX_SYSSTATUSResetDoneE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))) + +#define MLBMAILBOX_SYSSTATUSResetDoneisrstcomp32(var)\ +((MLBMAILBOX_SYSSTATUSResetDonerstcomp == (MLBMAILBOX_SYSSTATUSResetDoneE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))) + +#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MESSAGE___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) + +#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(base_address, bank, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ + MLB_MAILBOX_MESSAGE___0_15_OFFSET +\ + ((bank) * MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmRead32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MESSAGE___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK) >>\ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET)) + +#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK) >> \ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET)) + +#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmWrite32\ +(base_address, bank, value) do {\ + const unsigned long offset = \ + MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ + MLB_MAILBOX_MESSAGE___0_15_OFFSET +\ + ((bank) * MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK);\ + newValue <<= MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET;\ + newValue &= MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmSet32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET) &\ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK))) + +#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) + +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET)) + +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >> \ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET)) + +#define MLBMAILBOX_MSGSTATUS___0_15ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) + +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET)) + +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) \ +>> MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET)) + +#if defined(OMAP44XX) || defined(VPOM4430_1_06) + +#define MLBMAILBOX_IRQSTATUS_CLR___0_3ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP)))) + +#else + +#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) + +#endif + +#if defined(OMAP44XX) || defined(VPOM4430_1_06) + +#define MLBMAILBOX_IRQSTATUS_CLR___0_3WriteRegister32\ +(base_address, bank, value) do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * \ + MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+ \ + offset, newValue);\ +} while (0) + +#else + +#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#endif + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Write32\ +(base_address, bank, value)\ +do {\ + onst unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)\ +*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = RD_\ + MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK))) + +#if defined(OMAP44XX) || defined(VPOM4430_1_06) + +#define MLBMAILBOX_IRQENABLE_SET___0_3ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP)))) + +#else + +#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) + +#endif + +#if defined(OMAP44XX) || defined(VPOM4430_1_06) + +#define MLBMAILBOX_IRQENABLE_SET___0_3WriteRegister32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * \ + MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE_CLR___0_3WriteRegister32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * \ + MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#else + +#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#endif + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = \ + ((unsigned long)(value));\ + data &= \ + ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK);\ + newValue <<= \ + MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET;\ + newValue \ + &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = \ + ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Set32\ +(var, value)\ +(((((unsigned long)(var)) &\ +~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Get32(var)\ +((unsigned long)((((unsigned long)(var)) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Get32\ +(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)\ +*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Get32\ +(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)\ +*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Read32\ +(base_address, bank) do {\ + ((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ + (MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ + MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK) >>\ + MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET))\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Set32(var, value)\ +(((((unsigned long)(var)) &\ +~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK))) + +#endif /* USE_LEVEL_1_MACROS */ + + +#endif /* _MBX_REG_ACM_H */ diff --git a/arch/arm/plat-omap/include/syslink/MLBAccInt.h b/arch/arm/plat-omap/include/syslink/MLBAccInt.h new file mode 100644 index 000000000000..6cd469709005 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MLBAccInt.h @@ -0,0 +1,132 @@ +/* + * MLBAccInt.h + * + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef _MLB_ACC_INT_H +#define _MLB_ACC_INT_H + +/* Mappings of level 1 EASI function numbers to function names */ + +#define EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32 (MLB_BASE_EASIL1 + 3) +#define EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32 (MLB_BASE_EASIL1 + 4) +#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32 (MLB_BASE_EASIL1 + 7) +#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32 (MLB_BASE_EASIL1 + 17) +#define EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32 (MLB_BASE_EASIL1 + 29) +#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32 \ + (MLB_BASE_EASIL1 + 33) +#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32 (MLB_BASE_EASIL1 + 39) +#define EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32 (MLB_BASE_EASIL1 + 44) +#define EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32 \ + (MLB_BASE_EASIL1 + 50) +#define EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32 \ + (MLB_BASE_EASIL1 + 51) +#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32 \ + (MLB_BASE_EASIL1 + 56) +#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32 \ + (MLB_BASE_EASIL1 + 57) +#define EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32 \ + (MLB_BASE_EASIL1 + 60) +#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32 \ + (MLB_BASE_EASIL1 + 62) +#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32 \ + (MLB_BASE_EASIL1 + 63) +#define EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32 \ + (MLB_BASE_EASIL1 + 192) +#define EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32 \ + (MLB_BASE_EASIL1 + 193) + +/* Register set MAILBOX_MESSAGE___REGSET_0_15 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET (u32)(0x0040) +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP (u32)(0x0004) + +/* Register offset address definitions relative to register set + * MAILBOX_MESSAGE___REGSET_0_15 */ + +#define MLB_MAILBOX_MESSAGE___0_15_OFFSET (u32)(0x0) + + +/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET (u32)(0x0080) +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP (u32)(0x0004) + +/* Register offset address definitions relative to register set + * MAILBOX_FIFOSTATUS___REGSET_0_15 */ + +#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET (u32)(0x0) + + +/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET (u32)(0x00c0) +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP (u32)(0x0004) + +/* Register offset address definitions relative to register set + * MAILBOX_MSGSTATUS___REGSET_0_15 */ + +#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET (u32)(0x0) + + +/* Register set MAILBOX_IRQSTATUS___REGSET_0_3 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET (u32)(0x0100) +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP (u32)(0x0008) + +/* Register offset address definitions relative to register set + * MAILBOX_IRQSTATUS___REGSET_0_3 */ + +#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET (u32)(0x0) + + +/* Register set MAILBOX_IRQENABLE___REGSET_0_3 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET (u32)(0x0104) +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP (u32)(0x0008) + +/* Register offset address definitions relative to register set + * MAILBOX_IRQENABLE___REGSET_0_3 */ + +#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET (u32)(0x0) + + +/* Register offset address definitions */ + +#define MLB_MAILBOX_SYSCONFIG_OFFSET (u32)(0x10) +#define MLB_MAILBOX_SYSSTATUS_OFFSET (u32)(0x14) + + +/* Bitfield mask and offset declarations */ + +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK (u32)(0x18) +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET (u32)(3) +#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK (u32)(0x2) +#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET (u32)(1) +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK (u32)(0x1) +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET (u32)(0) +#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK (u32)(0x1) +#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET (u32)(0) +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK (u32)(0x1) +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET (u32)(0) +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK (u32)(0x7f) +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET (u32)(0) + +#endif /* _MLB_ACC_INT_H */ diff --git a/arch/arm/plat-omap/include/syslink/MLBRegAcM.h b/arch/arm/plat-omap/include/syslink/MLBRegAcM.h new file mode 100644 index 000000000000..5ef9cf32aef2 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MLBRegAcM.h @@ -0,0 +1,206 @@ +/* + * MLBRegAcM.h + * + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2007 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _MLB_REG_ACM_H +#define _MLB_REG_ACM_H + +#include <syslink/GlobalTypes.h> +#include <syslink/EasiGlobal.h> +#include <syslink/MLBAccInt.h> + +#if defined(USE_LEVEL_1_MACROS) + +#define MLBMAILBOX_SYSCONFIGReadRegister32(base_address)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+ \ +MLB_MAILBOX_SYSCONFIG_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGWriteRegister32(base_address, value)\ +do {\ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\ + WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(base_address)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32),\ +(((RD_MEM_32_VOLATILE((((u32)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(base_address, value)\ +do {\ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(((u32)(base_address)) +\ + offset);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(base_address, value)\ +do {\ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register u32 data =\ + RD_MEM_32_VOLATILE(((u32)(base_address))+offset);\ + register u32 newValue = ((u32)(value));\ + printk(KERN_ALERT "In SYSCONFIG MACOR line %i file %s", \ + __LINE__, __FILE__);\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32);\ + printk(KERN_ALERT "******************BEFORE DATA WRITE");\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ + printk(KERN_ALERT "line %i file %s", __LINE__, __FILE__);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\ + newValue |= data;\ + printk(KERN_ALERT "line %i file %s", __LINE__, __FILE__);\ + WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\ + printk(KERN_ALERT "line %i file %s", __LINE__, __FILE__);\ +} while (0) + + +#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(base_address)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32),\ +(((RD_MEM_32_VOLATILE((((u32)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(base_address, value)\ +{\ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register u32 data =\ + RD_MEM_32_VOLATILE(((u32)(base_address))+offset);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\ +} + + +#define MLBMAILBOX_SYSSTATUSResetDoneRead32(base_address)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32),\ +(((RD_MEM_32_VOLATILE((((u32)(base_address))+\ +(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)) + + +#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MESSAGE___0_15_OFFSET+(\ +(bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) + + +#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(base_address, bank, value)\ +do {\ + const u32 offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ + MLB_MAILBOX_MESSAGE___0_15_OFFSET +\ + ((bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32);\ + WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(\ +EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\ +((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) + + +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(\ +EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32),\ +(((RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\ +((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET)) + + +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(\ +EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32),\ +(((RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+\ +((bank)*MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET)) + + +#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) + + +#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(base_address, bank, value)\ +do {\ + const u32 offset = MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32);\ + WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) + + +#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(base_address, bank, value)\ +do {\ + const u32 offset = MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32);\ + WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\ +} while (0) + + +#endif /* USE_LEVEL_1_MACROS */ + +#endif /* _MLB_REG_ACM_H */ diff --git a/arch/arm/plat-omap/include/syslink/MMUAccInt.h b/arch/arm/plat-omap/include/syslink/MMUAccInt.h new file mode 100644 index 000000000000..2aa0fa2436ae --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MMUAccInt.h @@ -0,0 +1,180 @@ +/* + * MMUAccInt.h + * + * Syslink ducati driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _MMU_ACC_INT_H +#define _MMU_ACC_INT_H + + +/* Register offset address definitions */ + +#define MMU_MMU_REVISION_OFFSET 0x0 +#define MMU_MMU_SYSCONFIG_OFFSET 0x10 +#define MMU_MMU_SYSSTATUS_OFFSET 014 +#define MMU_MMU_IRQSTATUS_OFFSET 0x18 +#define MMU_MMU_IRQENABLE_OFFSET 0x1c +#define MMU_MMU_WALKING_ST_OFFSET 0x40 +#define MMU_MMU_CNTL_OFFSET 0x44 +#define MMU_MMU_FAULT_AD_OFFSET 0x48 +#define MMU_MMU_TTB_OFFSET 0x4c +#define MMU_MMU_LOCK_OFFSET 0x50 +#define MMU_MMU_LD_TLB_OFFSET 0x54 +#define MMU_MMU_CAM_OFFSET 0x58 +#define MMU_MMU_RAM_OFFSET 0x5c +#define MMU_MMU_GFLUSH_OFFSET 0x60 +#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64 +#define MMU_MMU_READ_CAM_OFFSET 0x68 +#define MMU_MMU_READ_RAM_OFFSET 0x6c +#define MMU_MMU_EMU_FAULT_AD_OFFSET 0x70 +#define MMU_MMU_FAULT_PC_OFFSET 0x80 +#define MMU_MMU_FAULT_STATUS_OFFSET 0x84 + +/* Bitfield mask and offset declarations */ + +#define MMU_MMU_REVISION_Rev_MASK 0xff +#define MMU_MMU_REVISION_Rev_OFFSET 0 + +#define MMU_MMU_SYSCONFIG_ClockActivity_MASK 0x300 +#define MMU_MMU_SYSCONFIG_ClockActivity_OFFSET 8 + +#define MMU_MMU_SYSCONFIG_IdleMode_MASK 0x18 +#define MMU_MMU_SYSCONFIG_IdleMode_OFFSET 3 + +#define MMU_MMU_SYSCONFIG_SoftReset_MASK 0x2 +#define MMU_MMU_SYSCONFIG_SoftReset_OFFSET 1 + +#define MMU_MMU_SYSCONFIG_AutoIdle_MASK 0x1 +#define MMU_MMU_SYSCONFIG_AutoIdle_OFFSET 0 + +#define MMU_MMU_SYSSTATUS_ResetDone_MASK 0x1 +#define MMU_MMU_SYSSTATUS_ResetDone_OFFSET 0 + +#define MMU_MMU_IRQSTATUS_MultiHitFault_MASK 0x10 +#define MMU_MMU_IRQSTATUS_MultiHitFault_OFFSET 4 + +#define MMU_MMU_IRQSTATUS_TableWalkFault_MASK 0x8 +#define MMU_MMU_IRQSTATUS_TableWalkFault_OFFSET 3 + +#define MMU_MMU_IRQSTATUS_EMUMiss_MASK 0x4 +#define MMU_MMU_IRQSTATUS_EMUMiss_OFFSET 2 + +#define MMU_MMU_IRQSTATUS_TranslationFault_MASK 0x2 +#define MMU_MMU_IRQSTATUS_TranslationFault_OFFSET 1 + +#define MMU_MMU_IRQSTATUS_TLBMiss_MASK 0x1 +#define MMU_MMU_IRQSTATUS_TLBMiss_OFFSET 0 + +#define MMU_MMU_IRQENABLE_MultiHitFault_MASK 0x10 +#define MMU_MMU_IRQENABLE_MultiHitFault_OFFSET 4 + +#define MMU_MMU_IRQENABLE_TableWalkFault_MASK 0x8 +#define MMU_MMU_IRQENABLE_TableWalkFault_OFFSET 3 + +#define MMU_MMU_IRQENABLE_EMUMiss_MASK 0x4 +#define MMU_MMU_IRQENABLE_EMUMiss_OFFSET 2 + +#define MMU_MMU_IRQENABLE_TranslationFault_MASK 0x2 +#define MMU_MMU_IRQENABLE_TranslationFault_OFFSET 1 + +#define MMU_MMU_IRQENABLE_TLBMiss_MASK 0x1 +#define MMU_MMU_IRQENABLE_TLBMiss_OFFSET 0 + +#define MMU_MMU_WALKING_ST_TWLRunning_MASK 0x1 +#define MMU_MMU_WALKING_ST_TWLRunning_OFFSET 0 + +#define MMU_MMU_CNTL_EmuTLBUpdate_MASK 0x8 +#define MMU_MMU_CNTL_EmuTLBUpdate_OFFSET 3 + +#define MMU_MMU_CNTL_TWLEnable_MASK 0x4 +#define MMU_MMU_CNTL_TWLEnable_OFFSET 2 + +#define MMU_MMU_CNTL_MMUEnable_MASK 0x2 +#define MMU_MMU_CNTL_MMUEnable_OFFSET 1 + +#define MMU_MMU_FAULT_AD_FaultAddress_MASK 0xffffffff +#define MMU_MMU_FAULT_AD_FaultAddress_OFFSET 0 + +#define MMU_MMU_TTB_TTBAddress_MASK 0xffffff00 +#define MMU_MMU_TTB_TTBAddress_OFFSET 8 + +#define MMU_MMU_LOCK_BaseValue_MASK 0xfc00 +#define MMU_MMU_LOCK_BaseValue_OFFSET 10 + +#define MMU_MMU_LOCK_CurrentVictim_MASK 0x3f0 +#define MMU_MMU_LOCK_CurrentVictim_OFFSET 4 + +#define MMU_MMU_LD_TLB_LdTLBItem_MASK 0x1 +#define MMU_MMU_LD_TLB_LdTLBItem_OFFSET 0 + +#define MMU_MMU_CAM_VATag_MASK 0xfffff000 +#define MMU_MMU_CAM_VATag_OFFSET 12 + +#define MMU_MMU_CAM_P_MASK 0x8 +#define MMU_MMU_CAM_P_OFFSET 3 + +#define MMU_MMU_CAM_V_MASK 0x4 +#define MMU_MMU_CAM_V_OFFSET 2 + +#define MMU_MMU_CAM_PageSize_MASK 0x3 +#define MMU_MMU_CAM_PageSize_OFFSET 0 + +#define MMU_MMU_RAM_PhysicalAddress_MASK 0xfffff000 +#define MMU_MMU_RAM_PhysicalAddress_OFFSET 12 + +#define MMU_MMU_RAM_Endianness_MASK 0x200 +#define MMU_MMU_RAM_Endianness_OFFSET 9 + +#define MMU_MMU_RAM_ElementSize_MASK 0x180 +#define MMU_MMU_RAM_ElementSize_OFFSET 7 + +#define MMU_MMU_RAM_Mixed_MASK 0x40 +#define MMU_MMU_RAM_Mixed_OFFSET 6 + +#define MMU_MMU_GFLUSH_GlobalFlush_MASK 0x1 +#define MMU_MMU_GFLUSH_GlobalFlush_OFFSET 0 + +#define MMU_MMU_FLUSH_ENTRY_FlushEntry_MASK 0x1 +#define MMU_MMU_FLUSH_ENTRY_FlushEntry_OFFSET 0 + +#define MMU_MMU_READ_CAM_VATag_MASK 0xfffff000 +#define MMU_MMU_READ_CAM_VATag_OFFSET 12 + +#define MMU_MMU_READ_CAM_P_MASK 0x8 +#define MMU_MMU_READ_CAM_P_OFFSET 3 + +#define MMU_MMU_READ_CAM_V_MASK 0x4 +#define MMU_MMU_READ_CAM_V_OFFSET 2 + +#define MMU_MMU_READ_CAM_PageSize_MASK 0x3 +#define MMU_MMU_READ_CAM_PageSize_OFFSET 0 + +#define MMU_MMU_READ_RAM_PhysicalAddress_MASK 0xfffff000 +#define MMU_MMU_READ_RAM_PhysicalAddress_OFFSET 12 + +#define MMU_MMU_READ_RAM_Endianness_MASK 0x200 +#define MMU_MMU_READ_RAM_Endianness_OFFSET 9 + +#define MMU_MMU_READ_RAM_ElementSize_MASK 0x180 +#define MMU_MMU_READ_RAM_ElementSize_OFFSET 7 + +#define MMU_MMU_READ_RAM_Mixed_MASK 0x40 +#define MMU_MMU_READ_RAM_Mixed_OFFSET 6 + +#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_MASK 0xffffffff +#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_OFFSET 0 + +#endif /* _MMU_ACC_INT_H */ +/* EOF */ + diff --git a/arch/arm/plat-omap/include/syslink/MMURegAcM.h b/arch/arm/plat-omap/include/syslink/MMURegAcM.h new file mode 100644 index 000000000000..c4944110789e --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MMURegAcM.h @@ -0,0 +1,434 @@ +/* + * MMURegAcM.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _MMU_REG_ACM_H +#define _MMU_REG_ACM_H + + + +#include "GlobalTypes.h" +#include "MMUAccInt.h" + + +/* +* EXPORTED DEFINITIONS +* +*/ + +#if defined(USE_LEVEL_1_MACROS) + + +#define MMUMMU_SYSCONFIGReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_SYSCONFIG_OFFSET)) + + +#define MMUMMU_SYSCONFIGWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_SYSCONFIGClockActivityGet32(var)\ + ((u32)(((var) & MMU_MMU_SYSCONFIG_ClockActivity_MASK)\ + >> MMU_MMU_SYSCONFIG_ClockActivity_OFFSET)) + +#define mmu_sisconf_auto_idle_set32(var, value)\ + ((((var) & ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK)) |\ + (((value) << MMU_MMU_SYSCONFIG_AutoIdle_OFFSET) &\ + MMU_MMU_SYSCONFIG_AutoIdle_MASK))) + +#define MMUMMU_IRQSTATUSReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_IRQSTATUS_OFFSET)) + + +#define MMUMMU_IRQSTATUSWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + + +#define MMUMMU_IRQENABLEReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_IRQENABLE_OFFSET)) + + +#define MMUMMU_IRQENABLEWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_IRQENABLETableWalkFaultSet32(var, value)\ + ((((var) & ~(MMU_MMU_IRQENABLE_TableWalkFault_MASK)) |\ + (((value) << MMU_MMU_IRQENABLE_TableWalkFault_OFFSET) &\ + MMU_MMU_IRQENABLE_TableWalkFault_MASK))) + +#define MMUMMU_IRQENABLETranslationFaultRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\ + MMU_MMU_IRQENABLE_TranslationFault_MASK) >>\ + MMU_MMU_IRQENABLE_TranslationFault_OFFSET)) + + + +#define MMUMMU_IRQENABLETranslationFaultSet32(var, value)\ + ((((var) & ~(MMU_MMU_IRQENABLE_TranslationFault_MASK)) |\ + (((value) << MMU_MMU_IRQENABLE_TranslationFault_OFFSET) &\ + MMU_MMU_IRQENABLE_TranslationFault_MASK))) + + +#define MMUMMU_IRQENABLETLBMissRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\ + MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET)) + + +#define MMUMMU_IRQENABLETLBMissReadIsTrMissIntM32(base_address)\ + ((MMUMMU_IRQENABLETLBMissTrMissIntM == (MMUMMU_IRQENABLETLBMissE)\ + (((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\ + MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET))) + + +#define MMUMMU_IRQENABLETLBMissReadIsTrMissGInt32(base_address)\ + ((MMUMMU_IRQENABLETLBMissTrMissGInt == (MMUMMU_IRQENABLETLBMissE)\ + (((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\ + MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET))) + + +#define MMUMMU_IRQENABLETLBMissGet32(var)\ + ((u32)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK)\ + >> MMU_MMU_IRQENABLE_TLBMiss_OFFSET)) + + +#define MMUMMU_IRQENABLETLBMissIsTrMissIntM32(var)\ + ((MMUMMU_IRQENABLETLBMissTrMissIntM == \ + (MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET))) + +#define MMUMMU_IRQENABLETLBMissIsTrMissGInt32(var)\ + ((MMUMMU_IRQENABLETLBMissTrMissGInt ==\ + (MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET))) + +#define MMUMMU_IRQENABLETLBMissWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\ + newValue <<= MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\ + newValue &= MMU_MMU_IRQENABLE_TLBMiss_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_IRQENABLETLBMissWriteTrMissIntM32(base_address)\ +{\ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ + const u32 newValue = (u32)MMUMMU_IRQENABLETLBMissTrMissIntM <<\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\ + data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE(base_address+offset, data);\ +} + + +#define MMUMMU_IRQENABLETLBMissWriteTrMissGInt32(base_address)\ +{\ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ + const u32 newValue = (u32)MMUMMU_IRQENABLETLBMissTrMissGInt <<\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\ + data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE(base_address+offset, data);\ +} + + +#define MMUMMU_IRQENABLETLBMissSet32(var, value)\ + ((((var) & ~(MMU_MMU_IRQENABLE_TLBMiss_MASK)) |\ + (((value) << MMU_MMU_IRQENABLE_TLBMiss_OFFSET) &\ + MMU_MMU_IRQENABLE_TLBMiss_MASK))) + + +#define MMUMMU_WALKING_STTWLRunningRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_WALKING_ST_OFFSET)))) &\ + MMU_MMU_WALKING_ST_TWLRunning_MASK) >>\ + MMU_MMU_WALKING_ST_TWLRunning_OFFSET)) + + + +#define MMUMMU_CNTLTWLEnableRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_CNTL_OFFSET)))) &\ + MMU_MMU_CNTL_TWLEnable_MASK) >>\ + MMU_MMU_CNTL_TWLEnable_OFFSET)) + + +#define MMUMMU_CNTLTWLEnableWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_CNTL_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_CNTL_TWLEnable_MASK);\ + newValue <<= MMU_MMU_CNTL_TWLEnable_OFFSET;\ + newValue &= MMU_MMU_CNTL_TWLEnable_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_CNTLMMUEnableWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_CNTL_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_CNTL_MMUEnable_MASK);\ + newValue <<= MMU_MMU_CNTL_MMUEnable_OFFSET;\ + newValue &= MMU_MMU_CNTL_MMUEnable_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_FAULT_ADReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FAULT_AD_OFFSET)) + + +#define MMUMMU_FAULT_ADFaultAddressRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_FAULT_AD_OFFSET)))) &\ + MMU_MMU_FAULT_AD_FaultAddress_MASK) >>\ + MMU_MMU_FAULT_AD_FaultAddress_OFFSET)) + +#define MMUMMU_FAULT_ADFaultAddressGet32(var)\ + ((u32)(((var) & MMU_MMU_FAULT_AD_FaultAddress_MASK)\ + >> MMU_MMU_FAULT_AD_FaultAddress_OFFSET)) + + +#define MMUMMU_TTBReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_TTB_OFFSET)) + +#define MMUMMU_TTBWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_TTB_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_TTBTTBAddressRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_TTB_OFFSET)))) &\ + MMU_MMU_TTB_TTBAddress_MASK) >>\ + MMU_MMU_TTB_TTBAddress_OFFSET)) + +#define MMUMMU_TTBTTBAddressGet32(var)\ + ((u32)(((var) & MMU_MMU_TTB_TTBAddress_MASK)\ + >> MMU_MMU_TTB_TTBAddress_OFFSET)) + + +#define MMUMMU_TTBTTBAddressWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_TTB_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_TTB_TTBAddress_MASK);\ + newValue <<= MMU_MMU_TTB_TTBAddress_OFFSET;\ + newValue &= MMU_MMU_TTB_TTBAddress_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + +#define MMUMMU_TTBTTBAddressSet32(var, value)\ + ((((var) & ~(MMU_MMU_TTB_TTBAddress_MASK)) |\ + (((value) << MMU_MMU_TTB_TTBAddress_OFFSET) &\ + MMU_MMU_TTB_TTBAddress_MASK))) + + +#define mmu_lckread_reg_32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_LOCK_OFFSET)) + +#define mmu_lck_write_reg32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_LOCK_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + + +#define MMUMMU_LOCKBaseValueRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\ + MMU_MMU_LOCK_BaseValue_MASK) >>\ + MMU_MMU_LOCK_BaseValue_OFFSET)) +#define MMUMMU_LOCKBaseValueGet32(var)\ + ((u32)(((var) & MMU_MMU_LOCK_BaseValue_MASK)\ + >> MMU_MMU_LOCK_BaseValue_OFFSET)) + + +#define MMUMMU_LOCKBaseValueWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_LOCK_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_LOCK_BaseValue_MASK);\ + newValue <<= MMU_MMU_LOCK_BaseValue_OFFSET;\ + newValue &= MMU_MMU_LOCK_BaseValue_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_LOCKBaseValueSet32(var, value)\ + ((((var) & ~(MMU_MMU_LOCK_BaseValue_MASK)) |\ + (((value) << MMU_MMU_LOCK_BaseValue_OFFSET) &\ + MMU_MMU_LOCK_BaseValue_MASK))) + +#define MMUMMU_LOCKCurrentVictimRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\ + MMU_MMU_LOCK_CurrentVictim_MASK) >>\ + MMU_MMU_LOCK_CurrentVictim_OFFSET)) + + +#define MMUMMU_LOCKCurrentVictimGet32(var)\ + ((u32)(((var) & MMU_MMU_LOCK_CurrentVictim_MASK)\ + >> MMU_MMU_LOCK_CurrentVictim_OFFSET)) + + +#define mmu_lck_crnt_vctmwite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_LOCK_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_LOCK_CurrentVictim_MASK);\ + newValue <<= MMU_MMU_LOCK_CurrentVictim_OFFSET;\ + newValue &= MMU_MMU_LOCK_CurrentVictim_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_LOCKCurrentVictimSet32(var, value)\ + ((((var) & ~(MMU_MMU_LOCK_CurrentVictim_MASK)) |\ + (((value) << MMU_MMU_LOCK_CurrentVictim_OFFSET) &\ + MMU_MMU_LOCK_CurrentVictim_MASK))) + + +#define MMUMMU_LD_TLBReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_LD_TLB_OFFSET)) + +#define mmu_ld_tlbwrt_reg32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_LD_TLB_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_LD_TLBLdTLBItemRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LD_TLB_OFFSET)))) &\ + MMU_MMU_LD_TLB_LdTLBItem_MASK) >>\ + MMU_MMU_LD_TLB_LdTLBItem_OFFSET)) + + +#define MMUMMU_CAMReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_READ_CAM_OFFSET)) + + +#define MMUMMU_CAMWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_CAM_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_RAMReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_READ_RAM_OFFSET)) + + +#define MMUMMU_RAMWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_RAM_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_GFLUSHGlobalFlushWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_GFLUSH_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\ + newValue <<= MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\ + newValue &= MMU_MMU_GFLUSH_GlobalFlush_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + +#define MMUMMU_GFLUSHGlobalFlushWritenft_w32(base_address)\ +{\ + const u32 offset = MMU_MMU_GFLUSH_OFFSET;\ + const u32 newValue = (u32)MMUMMU_GFLUSHGlobalFlushnft_w <<\ + MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\ + data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE(base_address+offset, data);\ +} + +#define MMUMMU_GFLUSHGlobalFlushWriteflush_w32(base_address)\ +{\ + const u32 offset = MMU_MMU_GFLUSH_OFFSET;\ + const u32 newValue = (u32)MMUMMU_GFLUSHGlobalFlushflush_w <<\ + MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\ + data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE(base_address+offset, data);\ +} + + +#define MMUMMU_GFLUSHGlobalFlushSet32(var, value)\ + ((((var) & ~(MMU_MMU_GFLUSH_GlobalFlush_MASK)) |\ + (((value) << MMU_MMU_GFLUSH_GlobalFlush_OFFSET) &\ + MMU_MMU_GFLUSH_GlobalFlush_MASK))) + +#define MMUMMU_FLUSH_ENTRYReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FLUSH_ENTRY_OFFSET)) + + +#define MMUMMU_FLUSH_ENTRYWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_FAULT_PCReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FAULT_PC_OFFSET)) + +#define MMUMMU_FAULT_STATUSReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FAULT_STATUS_OFFSET)) + +#define MMUMMU_FAULT_EMUAddressReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_EMU_FAULT_AD_OFFSET)) + +#endif /* USE_LEVEL_1_MACROS */ + +#endif /* _MMU_REG_ACM_H */ +/* EOF */ + diff --git a/arch/arm/plat-omap/include/syslink/_listmp.h b/arch/arm/plat-omap/include/syslink/_listmp.h new file mode 100644 index 000000000000..282d2c8c10e9 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/_listmp.h @@ -0,0 +1,68 @@ +/* + * _listmp.h + * + * Internal definitions for shared memory doubly linked list. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __LISTMP_H_ +#define __LISTMP_H_ + +/* Standard headers */ +#include <linux/types.h> +#include <linux/list.h> + +#include <listmp.h> +#include <sharedregion.h> + +/* Unique module ID. */ +#define LISTMP_MODULEID (0xa413) + +/* Created tag */ +#define LISTMP_CREATED 0x12181964 + + +/* Structure defining shared memory attributes for the ListMP module. */ +struct listmp_attrs { + u32 status; + u32 *gatemp_addr; + struct listmp_elem head; +}; + +/* Structure defining config parameters for the ListMP module. */ +struct listmp_config { + uint max_runtime_entries; + /* Maximum number of ListMP's that can be dynamically created and + added to the NameServer. */ + uint max_name_len; /* Maximum length of name */ +}; + + +/* Structure defining processor related information for the ListMP module. */ +struct listmp_proc_attrs { + bool creator; /* Creator or opener */ + u16 proc_id; /* Processor Identifier */ + u32 open_count; /* How many times it is opened on a processor */ +}; + + +/* Function to get the configuration */ +void listmp_get_config(struct listmp_config *cfg_params); + +/* Function to setup the listmp module */ +int listmp_setup(const struct listmp_config *config); + +/* Function to destroy the listmp module */ +int listmp_destroy(void); + +#endif /* __LISTMP_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/_notify.h b/arch/arm/plat-omap/include/syslink/_notify.h new file mode 100644 index 000000000000..9f9d88914160 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/_notify.h @@ -0,0 +1,83 @@ +/* + * _notify.h + * + * The MessageQ module supports the structured sending and receiving of + * variable length messages. This module can be used for homogeneous or + * heterogeneous multi-processor messaging. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#if !defined(__NOTIFY_H_) +#define __NOTIFY_H_ + + +/* Module headers */ +#include <syslink/notify.h> + + +/* Module ID for notify. */ +#define NOTIFY_MODULEID ((u16) 0x5F84) + +/* Mask to check for event ID. */ +#define NOTIFY_EVENT_MASK ((u16) 0xFFFF) + +#define ISRESERVED(event_id, reserved_event) \ + (((event_id & NOTIFY_EVENT_MASK) >= reserved_event) || \ + ((event_id >> 16) == NOTIFY_SYSTEMKEY)) + +/* This structure defines attributes for initialization of the notify module. */ +struct notify_config { + u32 num_events; + /* Number of events to be supported */ + u32 send_event_poll_count; + /* Poll for specified amount before send_event times out */ + u32 num_lines; + /* Max. number of interrupt lines between a single pair of processors */ + u32 reserved_events; + /* Number of reserved events to be supported */ +}; + +/* This structure defines the configuration structure for initialization + * of the notify object. */ +struct notify_params { + u32 reserved; /* Reserved field */ +}; + + +/* Function to get the default configuration for the notify module. */ +void notify_get_config(struct notify_config *cfg); + +/* Function to setup the notify module */ +int notify_setup(struct notify_config *cfg); + +/* Function to destroy the notify module */ +int notify_destroy(void); + +/* Function to create an instance of notify driver */ +struct notify_object *notify_create(void *driver_handle, u16 remote_proc_id, + u16 line_id, const struct notify_params *params); + +/* Function to delete an instance of notify driver */ +int notify_delete(struct notify_object **handle_ptr); + +/* Function to call device specific the notify module setup */ +int notify_attach(u16 proc_id, void *shared_addr); + +/* Function to destroy the device specific notify module */ +int notify_detach(u16 proc_id); + +/* Function registered as callback with the notify driver */ +void notify_exec(struct notify_object *obj, u32 event_id, u32 payload); + + +#endif /* !defined(__NOTIFY_H_) */ diff --git a/arch/arm/plat-omap/include/syslink/_sysmgr.h b/arch/arm/plat-omap/include/syslink/_sysmgr.h new file mode 100644 index 000000000000..58fbdd378155 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/_sysmgr.h @@ -0,0 +1,50 @@ +/* + * _sysmgr.h + * + * Defines for system manager functions + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __SYSMGR_H_ +#define __SYSMGR_H_ + +/* Structure to retrieve the scalability proc info from the slave */ +struct sysmgr_proc_config { + u32 proc_id; + u32 use_notify; + u32 use_messageq; + u32 use_heapbuf; + u32 use_frameq; + u32 use_ringio; + u32 use_listmp; + u32 use_nameserver; + u32 boot_mode; +}; + +/* Function to set the boot load page address for a slave */ +void sysmgr_set_boot_load_page(u16 proc_id, u32 boot_load_page); + +/* Function to get configuration values for a host object(component/instance) */ +u32 sysmgr_get_object_config(u16 proc_id, void *config, u32 cmd_id, u32 size); + +/* Function to put configuration values for a slave object(component/instance)*/ +u32 sysmgr_put_object_config(u16 proc_id, void *config, u32 cmd_id, u32 size); + +/* Function to wait for scalability handshake value. */ +void sysmgr_wait_for_scalability_info(u16 proc_id); + +/* Function to wait for slave to complete setup */ +void sysmgr_wait_for_slave_setup(u16 proc_id); + + +#endif /* ifndef __SYSMGR_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/atomic_linux.h b/arch/arm/plat-omap/include/syslink/atomic_linux.h new file mode 100644 index 000000000000..76fd8a1b9dc5 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/atomic_linux.h @@ -0,0 +1,105 @@ +/* +* atomic_linux.h +* +* Atomic operations functions +* +* Copyright (C) 2008-2009 Texas Instruments, Inc. +* +* This package is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +*/ + +#ifndef _ATOMIC_LINUX_H +#define _ATOMIC_LINUX_H + +#include <linux/types.h> +#include <generated/autoconf.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <asm/atomic.h> + +/* + * ======== atomic_cmpmask_and_set ======== + * Purpose: + * This will compare a mask and set if not equal + */ +static inline void atomic_cmpmask_and_set(atomic_t *v, u32 mask, u32 val) +{ + s32 ret; + unsigned long flags; + atomic_t *atm = v; + + raw_local_irq_save(flags); + ret = atm->counter; + if (likely(((ret & mask) != mask))) + atm->counter = val; + raw_local_irq_restore(flags); +} + +/* + * ======== atomic_cmpmask_and_set ======== + * Purpose: + * This will compare a mask and then check current value less than + * provided value. + */ +static inline bool atomic_cmpmask_and_lt(atomic_t *v, u32 mask, u32 val) +{ + bool ret = true; + atomic_t *atm = v; + s32 cur; + unsigned long flags; + + raw_local_irq_save(flags); + cur = atm->counter; + /* Compare mask, if matches then compare val */ + if (likely(((cur & mask) == mask))) { + if (likely(cur >= val)) + ret = false; + } + raw_local_irq_restore(flags); + + /* retval = true if mask matches and current value is less than given + * value */ + /* retval = false either mask doesnot matches or current value is not + * less than given value */ + return ret; +} + + +/* + * ======== atomic_cmpmask_and_set ======== + * Purpose: + * This will compare a mask and then check current value greater than + * provided value. + */ +static inline bool atomic_cmpmask_and_gt(atomic_t *v, u32 mask, u32 val) +{ + bool ret = false; + atomic_t *atm = v; + s32 cur; + unsigned long flags; + + raw_local_irq_save(flags); + cur = atm->counter; + /* Compare mask, if matches then compare val */ + if (likely(((cur & mask) == mask))) { + if (likely(cur > val)) + ret = true; + } + + raw_local_irq_restore(flags); + /* retval = true if mask matches and current value is less than given + * value */ + /* etval =false either mask doesnot matches or current value is not + * greater than given value */ + return ret; +} + +#endif /* if !defined(_ATOMIC_LINUX_H) */ + diff --git a/arch/arm/plat-omap/include/syslink/drv_notify.h b/arch/arm/plat-omap/include/syslink/drv_notify.h new file mode 100644 index 000000000000..2f386170e311 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/drv_notify.h @@ -0,0 +1,43 @@ +/* + * drv_notify.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined _DRV_NOTIFY_H_ +#define _DRV_NOTIFY_H_ + + +/* Module includes */ +#include <syslink/notify_driverdefs.h> +#include <syslink/_notify.h> + + +/* read function for of Notify driver.*/ +int notify_drv_read(struct file *filp, char *dst, size_t size, + loff_t *offset); + +/* Linux driver function to map memory regions to user space. */ +int notify_drv_mmap(struct file *filp, struct vm_area_struct *vma); + +/* ioctl function for of Linux Notify driver.*/ +int notify_drv_ioctl(struct inode *inode, struct file *filp, u32 cmd, + unsigned long args); + +void _notify_drv_setup(void); + +void _notify_drv_destroy(void); + + +#endif /* !defined (_DRV_NOTIFY_H_) */ diff --git a/arch/arm/plat-omap/include/syslink/ducatienabler.h b/arch/arm/plat-omap/include/syslink/ducatienabler.h new file mode 100644 index 000000000000..f2f8023ce8b4 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/ducatienabler.h @@ -0,0 +1,291 @@ +/* + * ducatienabler.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef _DDUCATIMMU_ENABLER_H_ +#define _DDUCATIMMU_ENABLER_H_ + +#include <linux/types.h> +#include <linux/mm.h> + +#include <syslink/hw_defs.h> +#include <syslink/hw_mmu.h> + + +#define PAGE_SIZE_4KB 0x1000 +#define PAGE_SIZE_64KB 0x10000 +#define PAGE_SIZE_1MB 0x100000 +#define PAGE_SIZE_16MB 0x1000000 + +/* Define the Peripheral PAs and their Ducati VAs. */ +#define L4_PERIPHERAL_MBOX 0x4A0F4000 +#define DUCATI_PERIPHERAL_MBOX 0xAA0F4000 + +#define L4_PERIPHERAL_I2C1 0x48070000 +#define DUCATI_PERIPHERAL_I2C1 0xA8070000 +#define L4_PERIPHERAL_I2C2 0x48072000 +#define DUCATI_PERIPHERAL_I2C2 0xA8072000 +#define L4_PERIPHERAL_I2C3 0x48060000 +#define DUCATI_PERIPHERAL_I2C3 0xA8060000 + +#define L4_PERIPHERAL_DMA 0x4A056000 +#define DUCATI_PERIPHERAL_DMA 0xAA056000 + +#define L4_PERIPHERAL_GPIO1 0x4A310000 +#define DUCATI_PERIPHERAL_GPIO1 0xAA310000 +#define L4_PERIPHERAL_GPIO2 0x48055000 +#define DUCATI_PERIPHERAL_GPIO2 0xA8055000 +#define L4_PERIPHERAL_GPIO3 0x48057000 +#define DUCATI_PERIPHERAL_GPIO3 0xA8057000 + +#define L4_PERIPHERAL_GPTIMER3 0x48034000 +#define DUCATI_PERIPHERAL_GPTIMER3 0xA8034000 +#define L4_PERIPHERAL_GPTIMER4 0x48036000 +#define DUCATI_PERIPHERAL_GPTIMER4 0xA8036000 +#define L4_PERIPHERAL_GPTIMER9 0x48040000 +#define DUCATI_PERIPHERAL_GPTIMER9 0xA8040000 +#define L4_PERIPHERAL_GPTIMER11 0x48088000 +#define DUCATI_PERIPHERAL_GPTIMER11 0xA8088000 + +#define L4_PERIPHERAL_UART1 0x4806A000 +#define DUCATI_PERIPHERAL_UART1 0xA806A000 +#define L4_PERIPHERAL_UART2 0x4806C000 +#define DUCATI_PERIPHERAL_UART2 0xA806C000 +#define L4_PERIPHERAL_UART3 0x48020000 +#define DUCATI_PERIPHERAL_UART3 0xA8020000 +#define L4_PERIPHERAL_UART4 0x4806E000 +#define DUCATI_PERIPHERAL_UART4 0xA806E000 + + +#define L3_TILER_VIEW0_ADDR 0x60000000 +#define DUCATIVA_TILER_VIEW0_ADDR 0x60000000 +#define DUCATIVA_TILER_VIEW0_LEN 0x20000000 + + + +#if 0 /* Original definitions for OMAP4430. */ +/* Define the various Ducati Memory Regions. */ +/* The first 4K page of BOOTVECS is programmed as a TLB entry. The remaining */ +/* three pages are not used and are mapped to minimize number of PTEs */ +#define DUCATI_BOOTVECS_ADDR 0x1000 +#define DUCATI_BOOTVECS_LEN 0x3000 + +#define DUCATI_EXTMEM_SYSM3_ADDR 0x4000 +#define DUCATI_EXTMEM_SYSM3_LEN 0x1FC000 + +#define DUCATI_EXTMEM_APPM3_ADDR 0x10000000 +#define DUCATI_EXTMEM_APPM3_LEN 0x200000 + +#define DUCATI_PRIVATE_SYSM3_DATA_ADDR 0x84000000 +#define DUCATI_PRIVATE_SYSM3_DATA_LEN 0x200000 + +#define DUCATI_PRIVATE_APPM3_DATA_ADDR 0x8A000000 +#define DUCATI_PRIVATE_APPM3_DATA_LEN 0x200000 + +#define DUCATI_SHARED_M3_DATA_ADDR 0x90000000 +#define DUCATI_SHARED_M3_DATA_LEN 0x100000 + +#define DUCATI_SHARED_IPC_ADDR 0x98000000 +#define DUCATI_SHARED_IPC_LEN 0x100000 + +#define DUCATI_SW_DMM_ADDR 0x80000000 +#define DUCATI_SW_DMM_LEN 0x400000 +#endif + +/* OMAP4430 SDC definitions */ +#define L4_PERIPHERAL_L4CFG 0x4A000000 +#define DUCATI_PERIPHERAL_L4CFG 0xAA000000 + +#define L4_PERIPHERAL_L4PER 0x48000000 +#define DUCATI_PERIPHERAL_L4PER 0xA8000000 + +#define L3_IVAHD_CONFIG 0x5A000000 +#define DUCATI_IVAHD_CONFIG 0xBA000000 + +#define L3_IVAHD_SL2 0x5B000000 +#define DUCATI_IVAHD_SL2 0xBB000000 + +#define L3_TILER_MODE0_1_ADDR 0x60000000 +#define DUCATI_TILER_MODE0_1_ADDR 0x60000000 +#define DUCATI_TILER_MODE0_1_LEN 0x10000000 + +#define L3_TILER_MODE3_ADDR 0x78000000 +#define DUCATI_TILER_MODE3_ADDR 0x78000000 +#define DUCATI_TILER_MODE3_LEN 0x8000000 + +#define DUCATI_BOOTVECS_UNUSED_ADDR 0x1000 +#define DUCATI_BOOTVECS_UNUSED_LEN 0x3000 + +#define DUCATI_MEM_CODE_SYSM3_ADDR 0x4000 +#define DUCATI_MEM_CODE_SYSM3_LEN 0x1FC000 + +#define DUCATI_MEM_CODE_APPM3_ADDR 0x800000 +#define DUCATI_MEM_CODE_APPM3_LEN 0x200000 + +#define DUCATI_MEM_CONST_SYSM3_ADDR 0x80000000 +#define DUCATI_MEM_CONST_SYSM3_LEN 0x100000 + +#define DUCATI_MEM_CONST_APPM3_ADDR 0x80100000 +#define DUCATI_MEM_CONST_APPM3_LEN 0x100000 + +#define DUCATI_MEM_HEAP_SYSM3_ADDR 0x80200000 +#define DUCATI_MEM_HEAP_SYSM3_LEN 0x100000 + +#define DUCATI_MEM_HEAP_APPM3_ADDR 0x80300000 +#define DUCATI_MEM_HEAP_APPM3_LEN 0x1000000 + +#define DUCATI_MEM_MPU_DUCATI_SHMEM_ADDR 0x81300000 +#define DUCATI_MEM_MPU_DUCATI_SHMEM_LEN 0xC00000 + +#define DUCATI_MEM_IPC_SHMEM_ADDR 0x81F00000 +#define DUCATI_MEM_IPC_SHMEM_LEN 0x100000 + +#define DUCATI_MEM_IPC_HEAP0_ADDR 0xA0000000 +#define DUCATI_MEM_IPC_HEAP0_LEN 0x55000 + +#define DUCATI_MEM_IPC_HEAP1_ADDR 0xA0055000 +#define DUCATI_MEM_IPC_HEAP1_LEN 0x55000 + +#define DUCATI_MEM_IPC_HEAP2_ADDR 0xA00AA000 +#define DUCATI_MEM_IPC_HEAP2_LEN 0x56000 + + +/* Types of mapping attributes */ + +/* MPU address is virtual and needs to be translated to physical addr */ +#define DSP_MAPVIRTUALADDR 0x00000000 +#define DSP_MAPPHYSICALADDR 0x00000001 + +/* Mapped data is big endian */ +#define DSP_MAPBIGENDIAN 0x00000002 +#define DSP_MAPLITTLEENDIAN 0x00000000 + +/* Element size is based on DSP r/w access size */ +#define DSP_MAPMIXEDELEMSIZE 0x00000004 + +/* + * Element size for MMU mapping (8, 16, 32, or 64 bit) + * Ignored if DSP_MAPMIXEDELEMSIZE enabled + */ +#define DSP_MAPELEMSIZE8 0x00000008 +#define DSP_MAPELEMSIZE16 0x00000010 +#define DSP_MAPELEMSIZE32 0x00000020 +#define DSP_MAPELEMSIZE64 0x00000040 + +#define DSP_MAPVMALLOCADDR 0x00000080 +#define DSP_MAPTILERADDR 0x00000100 + + +#define PG_MASK(pg_size) (~((pg_size)-1)) +#define PG_ALIGN_LOW(addr, pg_size) ((addr) & PG_MASK(pg_size)) +#define PG_ALIGN_HIGH(addr, pg_size) (((addr)+(pg_size)-1) & PG_MASK(pg_size)) + + +struct mmu_entry { + u32 ul_phy_addr ; + u32 ul_virt_addr ; + u32 ul_size ; +}; + +struct memory_entry { + u32 ul_virt_addr; + u32 ul_size; +}; + +#if 0 /* Original definitions for OMAP4430. */ +static const struct mmu_entry l4_map[] = { + /* Mailbox 4KB*/ + {L4_PERIPHERAL_MBOX, DUCATI_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB}, + /* I2C 4KB each */ + {L4_PERIPHERAL_I2C1, DUCATI_PERIPHERAL_I2C1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_I2C2, DUCATI_PERIPHERAL_I2C2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_I2C3, DUCATI_PERIPHERAL_I2C3, HW_PAGE_SIZE_4KB}, + /* DMA 4KB */ + {L4_PERIPHERAL_DMA, DUCATI_PERIPHERAL_DMA, HW_PAGE_SIZE_4KB}, + /* GPIO Banks 4KB each */ + {L4_PERIPHERAL_GPIO1, DUCATI_PERIPHERAL_GPIO1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPIO2, DUCATI_PERIPHERAL_GPIO2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPIO3, DUCATI_PERIPHERAL_GPIO3, HW_PAGE_SIZE_4KB}, + /* GPTimers 4KB each */ + {L4_PERIPHERAL_GPTIMER3, DUCATI_PERIPHERAL_GPTIMER3, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER4, DUCATI_PERIPHERAL_GPTIMER4, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER9, DUCATI_PERIPHERAL_GPTIMER9, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER11, DUCATI_PERIPHERAL_GPTIMER11, + HW_PAGE_SIZE_4KB}, + /* UARTs 4KB each */ + {L4_PERIPHERAL_UART1, DUCATI_PERIPHERAL_UART1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART2, DUCATI_PERIPHERAL_UART2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART3, DUCATI_PERIPHERAL_UART3, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART4, DUCATI_PERIPHERAL_UART4, + HW_PAGE_SIZE_4KB}, +}; + +static const struct memory_entry l3_memory_regions[] = { + /* BootVecs regions */ + {0, (PAGE_SIZE_1MB * 2)}, + /* EXTMEM_CORE1: 0x10000000 to 0x100FFFFF */ + {DUCATI_EXTMEM_APPM3_ADDR, DUCATI_EXTMEM_APPM3_LEN}, + /* PRIVATE_SYSM3_DATA*/ + {DUCATI_PRIVATE_SYSM3_DATA_ADDR, DUCATI_PRIVATE_SYSM3_DATA_LEN}, + /* PRIVATE_APPM3_DATA*/ + {DUCATI_PRIVATE_APPM3_DATA_ADDR, DUCATI_PRIVATE_APPM3_DATA_LEN}, + /* SHARED_M3_DATA*/ + {DUCATI_SHARED_M3_DATA_ADDR, DUCATI_SHARED_M3_DATA_LEN}, + /* IPC*/ + {DUCATI_SHARED_IPC_ADDR, DUCATI_SHARED_IPC_LEN}, + /* DMM*/ + {DUCATI_SW_DMM_ADDR, DUCATI_SW_DMM_LEN}, +}; +#endif + +/* OMAP4430 SDC definitions */ +static const struct mmu_entry l4_map[] = { + /* TILER 8-bit and 16-bit modes */ + {L3_TILER_MODE0_1_ADDR, DUCATI_TILER_MODE0_1_ADDR, + (HW_PAGE_SIZE_16MB * 16)}, + /* TILER: Pages-mode */ + {L3_TILER_MODE3_ADDR, DUCATI_TILER_MODE3_ADDR, + (HW_PAGE_SIZE_16MB * 8)}, + /* L4_CFG: Covers all modules in L4_CFG 16MB*/ + {L4_PERIPHERAL_L4CFG, DUCATI_PERIPHERAL_L4CFG, HW_PAGE_SIZE_16MB}, + /* L4_PER: Covers all modules in L4_PER 16MB*/ + {L4_PERIPHERAL_L4PER, DUCATI_PERIPHERAL_L4PER, HW_PAGE_SIZE_16MB}, + /* IVA_HD Config: Covers all modules in IVA_HD Config space 16MB */ + {L3_IVAHD_CONFIG, DUCATI_IVAHD_CONFIG, HW_PAGE_SIZE_16MB}, + /* IVA_HD SL2: Covers all memory in IVA_HD SL2 space 16MB */ + {L3_IVAHD_SL2, DUCATI_IVAHD_SL2, HW_PAGE_SIZE_16MB}, +}; + +static const struct memory_entry l3_memory_regions[] = { + /* MEM_IPC_HEAP0, MEM_IPC_HEAP1, MEM_IPC_HEAP2 */ + {DUCATI_MEM_IPC_HEAP0_ADDR, PAGE_SIZE_1MB}, + /* MEM_INTVECS_SYSM3, MEM_INTVECS_APPM3, MEM_CODE_SYSM3, + MEM_CODE_APPM3 */ + {0, PAGE_SIZE_16MB}, + /* MEM_CONST_SYSM3, MEM_CONST_APPM3, MEM_HEAP_SYSM3, MEM_HEAP_APPM3, + MEM_MPU_DUCATI_SHMEM, MEM_IPC_SHMEM */ + {DUCATI_MEM_CONST_SYSM3_ADDR, (PAGE_SIZE_16MB * 2)}, +}; + + +void dbg_print_ptes(bool ashow_inv_entries, bool ashow_repeat_entries); +int ducati_setup(void); +void ducati_destroy(void); +u32 get_ducati_virt_mem(void); +void unmap_ducati_virt_mem(u32 shm_virt_addr); +int ducati_mem_map(u32 va, u32 da, u32 num_bytes, u32 map_attr); +int ducati_mem_unmap(u32 da, u32 num_bytes); +u32 user_va2pa(struct mm_struct *mm, u32 address); +inline u32 ducati_mem_virtToPhys(u32 da); +#endif /* _DDUCATIMMU_ENABLER_H_*/ diff --git a/arch/arm/plat-omap/include/syslink/gate.h b/arch/arm/plat-omap/include/syslink/gate.h new file mode 100644 index 000000000000..1041f752f46c --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gate.h @@ -0,0 +1,76 @@ +/* + * gate.h + * + * Critical section support. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ +/** ============================================================================ + * Gates are used by clients to protect concurrent access to critical + * data structures. Critical data structures are those that must be + * updated by at most one thread at a time. All code that needs access + * to a critical data structure "enters" a gate (that's associated with the + * data structure) prior to accessing the data, modifies the data structure, + * then "leaves" the gate. + * + * A gate is responsible for ensuring that at most one thread at a time + * can enter and execute "inside" the gate. There are several + * implementations of gates, with different system executation times and + * latency tradoffs. In addition, some gates must not be entered by certain + * thread types; e.g., a gate that is implemented via a "blocking" semaphore + * must not be called by an interrupt service routine (ISR). + * + * A module can be declared "gated" by adding the `@Gated` attribute to the + * module's XDC spec file. A "gated" module is assigned a module-level gate + * at the configuration time, and that gate is then used to protect critical + * sections in the module's target code. A module-level gate is an instance of + * a module implementing `{@link IGateProvider}` interface. However, gated + * modules do not access their module-level gates directly. They use this + * module to access transparently their module-level gate. + * + * Application code that is not a part of any module also has a + * module-level gate, configured through the module `{@link Main}`. + * + * Each gated module can optionally create gates on an adhoc basis at + * runtime using the same gate module that was used to create the module + * level gate. + * + * Gates that work by disabling all preemption while inside a gate can be + * used to protect data structures accessed by ISRs and other + * threads. But, if the time required to update the data structure is not + * a small constant, this type of gate may violate a system's real-time + * requirements. + * + * Gates have two orthogonal attributes: "blocking" and "preemptible". + * In general, gates that are "blocking" can not be use by code that is + * called by ISRs and gates that are not "preemptible" should only be used to + * to protect data manipulated by code that has small constant execution + * time. + * ============================================================================ + */ + + +#ifndef GATE_H_0xAF6F +#define GATE_H_0xAF6F + +#include <igateprovider.h> + +extern struct igateprovider_object *gate_system_handle; + +/* Function to enter a Gate */ +int *gate_enter_system(void); + +/* Function to leave a Gate */ +void gate_leave_system(int *key); + + +#endif /* GATE_H_0xAF6F */ diff --git a/arch/arm/plat-omap/include/syslink/gate_remote.h b/arch/arm/plat-omap/include/syslink/gate_remote.h new file mode 100644 index 000000000000..e8115d59535a --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gate_remote.h @@ -0,0 +1,34 @@ +/* + * gate_remote.h + * + * This includes the functions to handle remote gates + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVER_REMOTE_H_ +#define _GATE_REMOTE_H_ + +#include <linux/types.h> + +/* + * This function is used to enter in to a remote gate + */ +int gate_remote_enter(void *ghandle, u32 key); + +/* + * This function is used to leave from a remote gate + */ +int gate_remote_leave(void *ghandle, u32 key); + +#endif /* _GATE_REMOTE_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/gatehwspinlock.h b/arch/arm/plat-omap/include/syslink/gatehwspinlock.h new file mode 100644 index 000000000000..afcfcbde7d45 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gatehwspinlock.h @@ -0,0 +1,158 @@ +/* + * gatehwspinlock.h + * + * Defines for gatehwspinlock. + * + * Copyright(C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + + +#ifndef GATEHWSPINLOCK_H_ +#define GATEHWSPINLOCK_H_ + +/* Module headers */ +#include <multiproc.h> +#include <gatemp.h> +#include <igatempsupport.h> +#include <sharedregion.h> + +/* Unique module ID. */ +#define GATEHWSPINLOCK_MODULEID (0xF416) + +/* ============================================================================= + * Module Success and Failure codes + * ============================================================================= + */ +/* Argument passed to a function is invalid. */ +#define GATEHWSPINLOCK_E_INVALIDARG -1 + +/* Memory allocation failed. */ +#define GATEHWSPINLOCK_E_MEMORY -2 + +/* the name is already registered or not. */ +#define GATEHWSPINLOCK_E_BUSY -3 + +/* Generic failure. */ +#define GATEHWSPINLOCK_E_FAIL -4 + +/* name not found in the nameserver. */ +#define GATEHWSPINLOCK_E_NOTFOUND -5 + +/* Module is not initialized. */ +#define GATEHWSPINLOCK_E_INVALIDSTATE -6 + +/* Instance is not created on this processor. */ +#define GATEHWSPINLOCK_E_NOTONWER -7 + +/* Remote opener of the instance has not closed the instance. */ +#define GATEHWSPINLOCK_E_REMOTEACTIVE -8 + +/* Indicates that the instance is in use. */ +#define GATEHWSPINLOCK_E_INUSE -9 + +/* Failure in OS call. */ +#define GATEHWSPINLOCK_E_OSFAILURE -10 + +/* Version mismatch error. */ +#define GATEHWSPINLOCK_E_VERSION -11 + +/* Operation successful. */ +#define GATEHWSPINLOCK_S_SUCCESS 0 + +/* The GATEHWSPINLOCK module has already been setup in this process. */ +#define GATEHWSPINLOCK_S_ALREADYSETUP 1 + + +/* ============================================================================= + * Macros + * ============================================================================= + */ + +/* Q_BLOCKING */ +#define GATEHWSEM_Q_BLOCKING (1) + +/* Q_PREEMPTING */ +#define GATEHWSEM_Q_PREEMPTING (2) + + +/* ============================================================================= + * Enums & Structures + * ============================================================================= + */ + +/* Structure defining config parameters for the gatehwspinlock module. */ +struct gatehwspinlock_config { + enum gatemp_local_protect default_protection; + /* Default module-wide local context protection level. The level of + * protection specified here determines which local gate is created + * per gatehwspinlock instance for local protection during create. + * The instance configuration parameter may be used to override this + * module setting per instance. The configuration used here should + * reflect both the context in which enter and leave are to be called, + * as well as the maximum level protection needed locally. + */ + u32 base_addr; + /* Device-specific base address for HW Semaphore subsystem in HOST OS + * address space, this is updated in Ipc module */ + u32 num_locks; + /* Device-specific number of semphores in the HW Semaphore subsystem */ +}; + +/* Structure defining config parameters for the gatehwspinlock instances. */ +struct gatehwspinlock_params { + IGATEMPSUPPORT_SUPERPARAMS; +}; + + +/* Inherit everything from IGateMPSupport */ +IGATEMPSUPPORT_INHERIT(gatehwspinlock); + + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Function to get the default configuration for the gatehwspinlock module. */ +void gatehwspinlock_get_config(struct gatehwspinlock_config *config); + +/* Function to setup the gatehwspinlock module. */ +int gatehwspinlock_setup(const struct gatehwspinlock_config *config); + +/* Function to destroy the gatehwspinlock module */ +int gatehwspinlock_destroy(void); + +/* Get the default parameters for the gatehwspinlock instance. */ +void gatehwspinlock_params_init(struct gatehwspinlock_params *params); + +/* Function to create an instance of gatehwspinlock */ +void *gatehwspinlock_create(enum igatempsupport_local_protect local_protect, + const struct gatehwspinlock_params *params); + +/* Function to delete an instance of gatehwspinlock */ +int gatehwspinlock_delete(void **handle_ptr); + +/* Function to enter the gatehwspinlock instance */ +int *gatehwspinlock_enter(void *handle); + +/* Function to leave the gatehwspinlock instance */ +void gatehwspinlock_leave(void *handle, int *key); + +/* Function to return the shared memory requirement for a single instance */ +u32 gatehwspinlock_shared_mem_req(const struct gatehwspinlock_params *params); + +/* Function to return the number of instances configured in the module. */ +u32 gatehwspinlock_get_num_instances(void); + +/* Function to initialize the locks module. */ +void gatehwspinlock_locks_init(void); + +#endif /* ifndef GATEHWSPINLOCK_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/gatemp.h b/arch/arm/plat-omap/include/syslink/gatemp.h new file mode 100644 index 000000000000..ea0af5b692fa --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gatemp.h @@ -0,0 +1,237 @@ +/* + * gatemp.h + * + * gatemp wrapper defines + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _GATEMP_H_ +#define _GATEMP_H_ + +#include <sharedregion.h> + +/* Unique module ID. */ +#define GATEMP_MODULEID (0xAF70) + +/* The resource is still in use */ +#define GateMP_S_BUSY 2 + +/* The module has been already setup */ +#define GateMP_S_ALREADYSETUP 1 + +/* Operation is successful. */ +#define GateMP_S_SUCCESS 0 + +/* Generic failure. */ +#define GateMP_E_FAIL -1 + +/* The specified entity already exists. */ +#define GateMP_E_ALREADYEXISTS -4 + +/* Unable to find the specified entity. */ +#define GateMP_E_NOTFOUND -5 + +/* Operation timed out. */ +#define GateMP_E_TIMEOUT -6 + +/* Module is not initialized. */ +#define GateMP_E_INVALIDSTATE -7 + +/* A failure occurred in an OS-specific call */ +#define GateMP_E_OSFAILURE -8 + +/* Specified resource is not available */ +#define GateMP_E_RESOURCE -9 + +/* Operation was interrupted. Please restart the operation */ +#define GateMP_E_RESTART -10 + +/* Gate is local gate not remote */ +#define GateMP_E_LOCALGATE -11 + + +/* + * A set of local context protection levels + * + * Each member corresponds to a specific local processor gates used for + * local protection. + * + * In linux user mode, the following are the mapping for the constants + * - INTERRUPT -> [N/A] + * - TASKLET -> [N/A] + * - THREAD -> GateMutex + * - PROCESS -> GateMutex + * + * In linux kernel mode, the following are the mapping for the constants + * - INTERRUPT -> [Interrupts disabled] + * - TASKLET -> GateMutex + * - THREAD -> GateMutex + * - PROCESS -> GateMutex + * + * For SYS/BIOS users, the following are the mappings for the constants + * - INTERRUPT -> GateHwi: disables interrupts + * - TASKLET -> GateSwi: disables Swi's (software interrupts) + * - THREAD -> GateMutexPri: based on Semaphores + * - PROCESS -> GateMutexPri: based on Semaphores + */ +enum gatemp_local_protect { + GATEMP_LOCALPROTECT_NONE = 0, + /* Use no local protection */ + + GATEMP_LOCALPROTECT_INTERRUPT = 1, + /* Use the INTERRUPT local protection level */ + + GATEMP_LOCALPROTECT_TASKLET = 2, + /* Use the TASKLET local protection level */ + + GATEMP_LOCALPROTECT_THREAD = 3, + /* Use the THREAD local protection level */ + + GATEMP_LOCALPROTECT_PROCESS = 4 + /* Use the PROCESS local protection level */ +}; + +/* + * Type of remote Gate + * + * Each member corresponds to a specific type of remote gate. + * Each enum value corresponds to the following remote protection levels: + * - NONE -> No remote protection (the gatemp instance will + * exclusively offer local protection configured in + * #GateMP_Params::local_protect + * - SYSTEM -> Use the SYSTEM remote protection level (default for + * remote protection + * - CUSTOM1 -> Use the CUSTOM1 remote protection level + * - CUSTOM2 -> Use the CUSTOM2 remote protection level + */ +enum gatemp_remote_protect { + GATEMP_REMOTEPROTECT_NONE = 0, + /* No remote protection (the gatemp instance will exclusively + * offer local protection configured in #GateMP_Params::local_protect) + */ + + GATEMP_REMOTEPROTECT_SYSTEM = 1, + /* Use the SYSTEM remote protection level (default remote protection) */ + + GATEMP_REMOTEPROTECT_CUSTOM1 = 2, + /* Use the CUSTOM1 remote protection level */ + + GATEMP_REMOTEPROTECT_CUSTOM2 = 3 + /* Use the CUSTOM2 remote protection level */ +}; + +/* Structure defining parameters for the gatemp module. */ +struct gatemp_params { + char *name; + /* Name of this instance. + * The name (if not NULL) must be unique among all GateMP + * instances in the entire system. When creating a new + * heap, it is necessary to supply an instance name. + */ + + u32 region_id; + /* Shared region ID + * The index corresponding to the shared region from which shared memory + * will be allocated. + * If not specified, the default of '0' will be used. + */ + + void *shared_addr; + /* Physical address of the shared memory + * This value can be left as 'null' unless it is required to place the + * heap at a specific location in shared memory. If sharedAddr is null, + * then shared memory for a new instance will be allocated from the + * heap belonging to the region identified by #GateMP_Params::region_id. + */ + + enum gatemp_local_protect local_protect; + /* Local protection level. + * The default value is #GATEMP_LOCALPROTECT_THREAD */ + + enum gatemp_remote_protect remote_protect; + /* Remote protection level + * The default value is #GATEMP_REMOTEPROTECT_SYSTEM */ +}; + +/* Structure defining config parameters for the gatemp module. */ +struct gatemp_config { + u32 num_resources; + /* Maximum number of resources */ + enum gatemp_local_protect default_protection; + u32 max_name_len; + u32 max_runtime_entries; +}; + + +/* Close an opened gate */ +int gatemp_close(void **handle_ptr); + +/* Create a gatemp instance */ +void *gatemp_create(const struct gatemp_params *params); + +/* Delete a created gatemp instance */ +int gatemp_delete(void **handle_ptr); + +/* Get the default remote gate */ +void *gatemp_get_default_remote(void); + +/* Open a created gatemp by name */ +int gatemp_open(char *name, void **handle_ptr); + +/* Open a created gatemp by address */ +int gatemp_open_by_addr(void *shared_addr, void **handle_ptr); + +/* Initialize a gatemp parameters struct */ +void gatemp_params_init(struct gatemp_params *params); + +/* Amount of shared memory required for creation of each instance */ +uint gatemp_shared_mem_req(const struct gatemp_params *params); + +/* Enter the gatemp */ +int *gatemp_enter(void *handle); + +/* Leave the gatemp */ +void gatemp_leave(void *handle, int *key); + +/* Get the default configuration for the gatemp module. */ +void gatemp_get_config(struct gatemp_config *cfg_params); + +/* Setup the gatemp module. */ +s32 gatemp_setup(const struct gatemp_config *cfg); + +/* Function to destroy the gatemp module. */ +s32 gatemp_destroy(void); + +/* Function to attach gatemp to a remote processor */ +int gatemp_attach(u16 remote_proc_id, void *shared_addr); + +/* Function to detach gatemp from a remote processor */ +int gatemp_detach(u16 remote_proc_id, void *shared_addr); + +/* Function to start gatemp */ +int gatemp_start(void *shared_addr); + +/* Function to start gatemp */ +int gatemp_stop(void); + +/* Function to create local gatemp */ +void *gatemp_create_local(enum gatemp_local_protect local_protect); + +/* Function to return size required in shared region 0 */ +uint gatemp_get_region0_reserved_size(void); + +/* Function to get the shared address of a gatemp object */ +u32 *gatemp_get_shared_addr(void *obj); + + +#endif /* _GATEMP_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/gatemp_ioctl.h b/arch/arm/plat-omap/include/syslink/gatemp_ioctl.h new file mode 100644 index 000000000000..203f6b1a4961 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gatemp_ioctl.h @@ -0,0 +1,177 @@ +/* + * gatemp_ioctl.h + * + * Definitions of gatemp ioctl types and structures. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _GATEMP_IOCTL_H_ +#define _GATEMP_IOCTL_H_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <gatemp.h> + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +#define GATEMP_IOC_MAGIC IPC_IOC_MAGIC +/* IOCTL command ID definitions for GateMP */ +enum CMD_GATEMP { + GATEMP_GETCONFIG = GATEMP_BASE_CMD, + GATEMP_SETUP, + GATEMP_DESTROY, + GATEMP_PARAMS_INIT, + GATEMP_CREATE, + GATEMP_DELETE, + GATEMP_OPEN, + GATEMP_CLOSE, + GATEMP_ENTER, + GATEMP_LEAVE, + GATEMP_SHAREDMEMREQ, + GATEMP_OPENBYADDR, + GATEMP_GETDEFAULTREMOTE +}; + +/* + * IOCTL command IDs for GateMP + */ +/* Command for gatemp_get_config */ +#define CMD_GATEMP_GETCONFIG _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_GETCONFIG, \ + struct gatemp_cmd_args) +/* Command for gatemp_setup */ +#define CMD_GATEMP_SETUP _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_SETUP, \ + struct gatemp_cmd_args) +/* Command for gatemp_destroy */ +#define CMD_GATEMP_DESTROY _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_DESTROY, \ + struct gatemp_cmd_args) +/* Command for gatemp_params_init */ +#define CMD_GATEMP_PARAMS_INIT _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_PARAMS_INIT, \ + struct gatemp_cmd_args) +/* Command for gatemp_create */ +#define CMD_GATEMP_CREATE _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_CREATE, \ + struct gatemp_cmd_args) +/* Command for gatemp_delete */ +#define CMD_GATEMP_DELETE _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_DELETE, \ + struct gatemp_cmd_args) +/* Command for gatemp_open */ +#define CMD_GATEMP_OPEN _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_OPEN, \ + struct gatemp_cmd_args) +/* Command for gatemp_close */ +#define CMD_GATEMP_CLOSE _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_CLOSE, \ + struct gatemp_cmd_args) +/* Command for gatemp_enter */ +#define CMD_GATEMP_ENTER _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_ENTER, \ + struct gatemp_cmd_args) +/* Command for gatemp_leave */ +#define CMD_GATEMP_LEAVE _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_LEAVE, \ + struct gatemp_cmd_args) +/* Command for gatemp_shared_mem_req */ +#define CMD_GATEMP_SHAREDMEMREQ _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_SHAREDMEMREQ, \ + struct gatemp_cmd_args) +/* Command for gatemp_open_by_addr */ +#define CMD_GATEMP_OPENBYADDR _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_OPENBYADDR, \ + struct gatemp_cmd_args) +/* Command for gatemp_get_default_remote */ +#define CMD_GATEMP_GETDEFAULTREMOTE _IOWR(GATEMP_IOC_MAGIC, \ + GATEMP_GETDEFAULTREMOTE, \ + struct gatemp_cmd_args) + +/* Command arguments for GateMP */ +struct gatemp_cmd_args { + union { + struct { + struct gatemp_params *params; + } params_init; + + struct { + struct gatemp_config *config; + } get_config; + + struct { + struct gatemp_config *config; + } setup; + + struct { + void *handle; + struct gatemp_params *params; + u32 name_len; + u32 *shared_addr_srptr; + } create; + + struct { + void *handle; + } delete_instance; + + struct { + void *handle; + char *name; + u32 name_len; + u32 *shared_addr_srptr; + } open; + + struct { + void *handle; + u32 *shared_addr_srptr; + } open_by_addr; + + struct { + void *handle; + } close; + + struct { + void *handle; + int *flags; + } enter; + + struct { + void *handle; + int *flags; + } leave; + + struct { + struct gatemp_params *params; + u32 ret_val; + } shared_mem_req; + + struct { + void *handle; + } get_default_remote; + } args; + + s32 api_status; +}; + + +/* + * ioctl interface function for gatemp + */ +int gatemp_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _GATEMP_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/gatempdefs.h b/arch/arm/plat-omap/include/syslink/gatempdefs.h new file mode 100644 index 000000000000..d12d8f84414c --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gatempdefs.h @@ -0,0 +1,116 @@ +/* + * gatemp.h + * + * Definitions of gatemp support proxies + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _GATEMPDEFS_H_ +#define _GATEMPDEFS_H_ + + +/* Utilities headers */ +#include <gatepeterson.h> +#include <gatehwspinlock.h> +/* Enable once ported - GateMPSupportNull may not be needed +#include <_GateMPSupportNull.h> +#include <GateMPSupportNull.h> +*/ + +#if 1 /* Enable when SpinLock is available */ +#define gatemp_remote_system_proxy_params_init gatehwspinlock_params_init +#define gatemp_remote_custom1_proxy_params_init gatepeterson_params_init +#define gatemp_remote_custom2_proxy_params_init gatepeterson_params_init +#define gatemp_remote_system_proxy_create gatehwspinlock_create +#define gatemp_remote_custom1_proxy_create gatepeterson_create +#define gatemp_remote_custom2_proxy_create gatepeterson_create +#define gatemp_remote_system_proxy_delete gatehwspinlock_delete +#define gatemp_remote_custom1_proxy_delete gatepeterson_delete +#define gatemp_remote_custom2_proxy_delete gatepeterson_delete +#define gatemp_remote_system_proxy_params struct gatehwspinlock_params +#define gatemp_remote_custom1_proxy_params struct gatepeterson_params +#define gatemp_remote_custom2_proxy_params struct gatepeterson_params +#define gatemp_remote_system_proxy_shared_mem_req \ + gatehwspinlock_shared_mem_req +#define gatemp_remote_custom1_proxy_shared_mem_req \ + gatepeterson_shared_mem_req +#define gatemp_remote_custom2_proxy_shared_mem_req \ + gatepeterson_shared_mem_req +#define gatemp_remote_system_proxy_get_num_instances \ + gatehwspinlock_get_num_instances +#define gatemp_remote_custom1_proxy_get_num_instances \ + gatepeterson_get_num_instances +#define gatemp_remote_custom2_proxy_get_num_instances \ + gatepeterson_get_num_instances +#define gatemp_remote_system_proxy_locks_init gatehwspinlock_locks_init +#define gatemp_remote_custom1_proxy_locks_init gatepeterson_locks_init +#define gatemp_remote_custom2_proxy_locks_init gatepeterson_locks_init +#define gatemp_remote_system_proxy_handle void * +#define gatemp_remote_custom1_proxy_handle void * +#define gatemp_remote_custom2_proxy_handle void * +#define gatemp_remote_system_proxy_open_by_addr gatehwspinlock_open_by_addr +#define gatemp_remote_custom1_proxy_open_by_addr \ + gatepeterson_open_by_addr +#define gatemp_remote_custom2_proxy_open_by_addr \ + gatepeterson_open_by_addr +#define gatemp_remote_system_proxy_enter gatehwspinlock_enter +#define gatemp_remote_system_proxy_leave gatehwspinlock_leave +#define gatemp_remote_custom1_proxy_enter gatepeterson_enter +#define gatemp_remote_custom1_proxy_leave gatepeterson_leave +#define gatemp_remote_custom2_proxy_enter gatepeterson_enter +#define gatemp_remote_custom2_proxy_leave gatepeterson_leave +#else +#define gatemp_remote_system_proxy_params_init gatepeterson_params_init +#define gatemp_remote_custom1_proxy_params_init gatepeterson_params_init +#define gatemp_remote_custom2_proxy_params_init gatepeterson_params_init +#define gatemp_remote_system_proxy_create gatepeterson_create +#define gatemp_remote_custom1_proxy_create gatepeterson_create +#define gatemp_remote_custom2_proxy_create gatepeterson_create +#define gatemp_remote_system_proxy_delete gatepeterson_delete +#define gatemp_remote_custom1_proxy_delete gatepeterson_delete +#define gatemp_remote_custom2_proxy_delete gatepeterson_delete +#define gatemp_remote_system_proxy_params struct gatepeterson_params +#define gatemp_remote_custom1_proxy_params struct gatepeterson_params +#define gatemp_remote_custom2_proxy_params struct gatepeterson_params +#define gatemp_remote_system_proxy_shared_mem_req \ + gatepeterson_shared_mem_req +#define gatemp_remote_custom1_proxy_shared_mem_req \ + gatepeterson_shared_mem_req +#define gatemp_remote_custom2_proxy_shared_mem_req \ + gatepeterson_shared_mem_req +#define gatemp_remote_system_proxy_get_num_instances \ + gatepeterson_get_num_instances +#define gatemp_remote_custom1_proxy_get_num_instances \ + gatepeterson_get_num_instances +#define gatemp_remote_custom2_proxy_get_num_instances \ + gatepeterson_get_num_instances +#define gatemp_remote_system_proxy_locks_init gatepeterson_locks_init +#define gatemp_remote_custom1_proxy_locks_init gatepeterson_locks_init +#define gatemp_remote_custom2_proxy_locks_init gatepeterson_locks_init +#define gatemp_remote_system_proxy_handle void * +#define gatemp_remote_custom1_proxy_handle void * +#define gatemp_remote_custom2_proxy_handle void * +#define gatemp_remote_system_proxy_open_by_addr gatepeterson_open_by_addr +#define gatemp_remote_custom1_proxy_open_by_addr \ + gatepeterson_open_by_addr +#define gatemp_remote_custom2_proxy_open_by_addr \ + gatepeterson_open_by_addr +#define gatemp_remote_system_proxy_enter gatepeterson_enter +#define gatemp_remote_system_proxy_leave gatepeterson_leave +#define gatemp_remote_custom1_proxy_enter gatepeterson_enter +#define gatemp_remote_custom1_proxy_leave gatepeterson_leave +#define gatemp_remote_custom2_proxy_enter gatepeterson_enter +#define gatemp_remote_custom2_proxy_leave gatepeterson_leave +#endif + +#endif /* _GATEMPDEFS_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/gatepeterson.h b/arch/arm/plat-omap/include/syslink/gatepeterson.h new file mode 100644 index 000000000000..461ebe06f193 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gatepeterson.h @@ -0,0 +1,140 @@ +/* + * gatepeterson.h + * + * The Gate Peterson Algorithm for mutual exclusion of shared memory. + * Current implementation works for 2 processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _GATEPETERSON_H_ +#define _GATEPETERSON_H_ + +#include <linux/types.h> + +#include <igatempsupport.h> + +/* + * GATEPETERSON_MODULEID + * Unique module ID + */ +#define GATEPETERSON_MODULEID (0xF415) + +/* + * A set of context protection levels that each correspond to + * single processor gates used for local protection + */ +enum gatepeterson_protect { + GATEPETERSON_PROTECT_DEFAULT = 0, + GATEPETERSON_PROTECT_NONE = 1, + GATEPETERSON_PROTECT_INTERRUPT = 2, + GATEPETERSON_PROTECT_TASKLET = 3, + GATEPETERSON_PROTECT_THREAD = 4, + GATEPETERSON_PROTECT_PROCESS = 5, + GATEPETERSON_PROTECT_END_VALUE = 6 +}; + +/* + * Structure defining config parameters for the Gate Peterson + * module + */ +struct gatepeterson_config { + enum gatepeterson_protect default_protection; + /*!< Default module-wide local context protection level. The level of + * protection specified here determines which local gate is created per + * GatePeterson instance for local protection during create. The instance + * configuration parameter may be usedto override this module setting per + * instance. The configuration used here should reflect both the context + * in which enter and leave are to be called,as well as the maximum level + * of protection needed locally. + */ + u32 num_instances; + /*!< Maximum number of instances supported by the GatePeterson module */ + +}; + +/* + * Structure defining config parameters for the Gate Peterson + * instances + */ +struct gatepeterson_params { + IGATEMPSUPPORT_SUPERPARAMS; +}; + +/* + * Function to initialize the parameter structure + */ +void gatepeterson_get_config(struct gatepeterson_config *config); + +/* + * Function to initialize GP module + */ +int gatepeterson_setup(const struct gatepeterson_config *config); + +/* + * Function to destroy the GP module + */ +int gatepeterson_destroy(void); + +/* + * Function to initialize the parameter structure + */ +void gatepeterson_params_init(struct gatepeterson_params *params); + +/* + * Function to create an instance of GatePeterson + */ +void *gatepeterson_create(enum igatempsupport_local_protect local_protect, + const struct gatepeterson_params *params); + +/* + * Function to delete an instance of GatePeterson + */ +int gatepeterson_delete(void **gphandle); + +/* + * Function to open a previously created instance by address + */ +int gatepeterson_open_by_addr(enum igatempsupport_local_protect local_protect, + void *shared_addr, void **gphandle); + +/* + * Function to close a previously opened instance + */ +int gatepeterson_close(void **gphandle); + +/* + * Function to enter the gate peterson + */ +int *gatepeterson_enter(void *gphandle); + +/* + *Function to leave the gate peterson + */ +void gatepeterson_leave(void *gphandle, int *key); + +/* + * Function to return the shared memory requirement + */ +u32 gatepeterson_shared_mem_req(const struct gatepeterson_params *params); + +/* + * Function to return the number of instances configured in the module. + */ +u32 gatepeterson_get_num_instances(void); + +/* + * Function to initialize the locks module. + */ +void gatepeterson_locks_init(void); + +#endif /* _GATEPETERSON_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/gt.h b/arch/arm/plat-omap/include/syslink/gt.h new file mode 100644 index 000000000000..95e3feb18e7b --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gt.h @@ -0,0 +1,320 @@ + +/* + * gt.h + * + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2008 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +/* + * ======== gt.h ======== + * Purpose: + * There are two definitions that affect which portions of trace + * are acutally compiled into the client: GT_TRACE and GT_ASSERT. If + * GT_TRACE is set to 0 then all trace statements (except for assertions) + * will be compiled out of the client. If GT_ASSERT is set to 0 then + * assertions will be compiled out of the client. GT_ASSERT can not be + * set to 0 unless GT_TRACE is also set to 0 (i.e. GT_TRACE == 1 implies + * GT_ASSERT == 1). + * + *! Revision History + *! ================ + *! 02-Feb-2000 rr: Renamed this file to gtce.h. GT CLASS and trace + *! definitions are WinCE Specific. + *! 03-Jan-1997 ge Replaced "GT_" prefix to GT_Config structure members + *! to eliminate preprocessor confusion with other macros. + */ +#include <linux/types.h> +#ifndef GT_ +#define GT_ + +#ifndef GT_TRACE +#define GT_TRACE 0 /* 0 = "trace compiled out"; 1 = "trace active" */ +#endif + +/* #include <syslink/host_os.h> */ + +typedef s32(*Fxn)(); /* generic function type */ + + +#if !defined(GT_ASSERT) || GT_TRACE +#define GT_ASSERT 1 +#endif + +struct GT_Config { + Fxn PRINTFXN; + Fxn PIDFXN; + Fxn TIDFXN; + Fxn ERRORFXN; +}; + +extern struct GT_Config *GT; + +struct gt_mask { + char *modName; + u8 *flags; +} ; + +/* + * New GT Class defenitions. + * + * The following are the explanations and how it could be used in the code + * + * - GT_ENTER On Entry to Functions + * + * - GT_1CLASS Display level of debugging status- Object/Automatic + * variables + * - GT_2CLASS ---- do ---- + * + * - GT_3CLASS ---- do ---- + It can be used(recommended) for debug + * status in the ISR, IST + * - GT_4CLASS ---- do ---- + * + * - GT_5CLASS Display entry for module init/exit functions + * + * - GT_6CLASS Warn whenever SERVICES function fails + * + * - GT_7CLASS Warn failure of Critical failures + * + */ + +#define GT_ENTER ((u8)0x01) +#define GT_1CLASS ((u8)0x02) +#define GT_2CLASS ((u8)0x04) +#define GT_3CLASS ((u8)0x08) +#define GT_4CLASS ((u8)0x10) +#define GT_5CLASS ((u8)0x20) +#define GT_6CLASS ((u8)0x40) +#define GT_7CLASS ((u8)0x80) +#define GT_LEAVE ((u8)0x02) + +#ifdef _LINT_ + +/* LINTLIBRARY */ + +/* + * ======== GT_assert ======== + */ +/* ARGSUSED */ +void GT_assert(struct gt_mask mask, s32 expr) +{ +} + +/* + * ======== GT_config ======== + */ +/* ARGSUSED */ +void GT_config(struct GT_Config config) +{ +} + +/* + * ======== GT_create ======== + */ +/* ARGSUSED */ +void GT_create(struct gt_mask *mask, char *modName) +{ +} + +/* + * ======== GT_curline ======== + * Purpose: + * Returns the current source code line number. Is useful for performing + * branch testing using trace. For example, + * + * gt_1trace(curTrace, GT_1CLASS, + * "in module XX_mod, executing line %u\n", GT_curline()); + */ +/* ARGSUSED */ +u16 GT_curline(void) +{ + return (u16)NULL; +} + +/* + * ======== GT_exit ======== + */ +/* ARGSUSED */ +void GT_exit(void) +{ +} + +/* + * ======== GT_init ======== + */ +/* ARGSUSED */ +void GT_init(void) +{ +} + +/* + * ======== GT_query ======== + */ +/* ARGSUSED */ +bool GT_query(struct gt_mask mask, u8 class) +{ + return false; +} + +/* + * ======== GT_set ======== + * sets trace mask according to settings + */ + +/* ARGSUSED */ +void GT_set(char *settings) +{ +} + +/* + * ======== GT_setprintf ======== + * sets printf function + */ + +/* ARGSUSED */ +void GT_setprintf(Fxn fxn) +{ +} + +/* ARGSUSED */ +void gt_0trace(struct gt_mask mask, u8 class, char *format) +{ +} + +/* ARGSUSED */ +void gt_1trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void gt_2trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void gt_3trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void gt_4trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void gt_5trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void GT_6trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +#else + +#define GT_BOUND 26 /* 26 letters in alphabet */ + +extern void _GT_create(struct gt_mask *mask, char *modName); + +#define GT_exit() + +extern void GT_init(void); +extern void _GT_set(char *str); +extern s32 _GT_trace(struct gt_mask *mask, char *format, ...); + +#if GT_ASSERT == 0 + +#define GT_assert(mask, expr) +#define GT_config(config) +#define GT_configInit(config) +#define GT_seterror(fxn) + +#else + +extern struct GT_Config _GT_params; + +#define GT_assert(mask, expr) \ + (!(expr) ? \ + printk(KERN_ALERT "assertion violation: %s, line %d\n", \ + __FILE__, __LINE__), NULL : NULL) + +#define GT_config(config) (_GT_params = *(config)) +#define GT_configInit(config) (*(config) = _GT_params) +#define GT_seterror(fxn) (_GT_params.ERRORFXN = (Fxn)(fxn)) + +#endif + +#if GT_TRACE == 0 + +#define GT_curline() ((u16)__LINE__) +#define GT_create(mask, modName) +#define GT_exit() +#define GT_init() +#define GT_set(settings) +#define GT_setprintf(fxn) + +#define GT_query(mask, class) false + +#define gt_0trace(mask, class, format) +#define gt_1trace(mask, class, format, arg1) +#define gt_2trace(mask, class, format, arg1, arg2) +#define gt_3trace(mask, class, format, arg1, arg2, arg3) +#define gt_4trace(mask, class, format, arg1, arg2, arg3, arg4) +#define gt_5trace(mask, class, format, arg1, arg2, arg3, arg4, arg5) +#define GT_6trace(mask, class, format, arg1, arg2, arg3, arg4, arg5, arg6) + +#else /* GT_TRACE == 1 */ + +#define GT_create(mask, modName) _GT_create((mask), (modName)) +#define GT_curline() ((u16)__LINE__) +#define GT_set(settings) _GT_set(settings) +#define GT_setprintf(fxn) (_GT_params.PRINTFXN = (Fxn)(fxn)) + +#define GT_query(mask, class) ((*(mask).flags & (class))) + +#define gt_0trace(mask, class, format) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format)) : 0) + +#define gt_1trace(mask, class, format, arg1) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1)) : 0) + +#define gt_2trace(mask, class, format, arg1, arg2) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2)) : 0) + +#define gt_3trace(mask, class, format, arg1, arg2, arg3) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2), (arg3)) : 0) + +#define gt_4trace(mask, class, format, arg1, arg2, arg3, arg4) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4)) : 0) + +#define gt_5trace(mask, class, format, arg1, arg2, arg3, arg4, arg5) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4), (arg5)) \ + : 0) + +#define GT_6trace(mask, class, format, arg1, arg2, arg3, arg4, arg5, arg6) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4), (arg5), \ + (arg6)) : 0) + +#endif /* GT_TRACE */ + +#endif /* _LINT_ */ + +#endif /* GTCE_ */ diff --git a/arch/arm/plat-omap/include/syslink/heap.h b/arch/arm/plat-omap/include/syslink/heap.h new file mode 100644 index 000000000000..1d3e9fb237de --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/heap.h @@ -0,0 +1,97 @@ +/* + * heap.h + * + * Heap module manages fixed size buffers that can be used + * in a multiprocessor system with shared memory. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _HEAP_H_ +#define _HEAP_H_ + +#include <linux/types.h> + +/* + * Structure defining memory related statistics + */ +struct memory_stats{ + u32 total_size; /* Total memory size */ + u32 total_free_size; /* Total free memory size */ + u32 largest_free_size; /* Largest free memory size */ +}; + +/*! + * ======== extendedstats ======== + * Stats structure for the get_extended_stats API. + * + * max_allocated_blocks: The maximum number of blocks allocated + * from this heap at any single point in time during the lifetime of this + * heap instance. + * + * num_allocated_blocks: The total number of blocks currently + * allocated in this Heap instance. + */ +struct heap_extended_stats { + u32 max_allocated_blocks; + u32 num_allocated_blocks; +}; + +/* + * Structure defining config parameters for the heapbuf module + */ +struct heap_config { + u32 max_name_len; /* Maximum length of name */ + bool track_max_allocs; /* Track the max number of allocated blocks */ +}; + +/* + * Structure for the handle for the heap + */ +struct heap_object { + void* (*alloc) (void *handle, u32 size, u32 align); + int (*free) (void *handle, void *block, u32 size); + void (*get_stats) (void *handle, struct memory_stats *stats); + void (*get_extended_stats) (void *handle, + struct heap_extended_stats *stats); + bool (*is_blocking) (void *handle); + void *obj; +}; + +/* + * Allocate a block + */ +void *sl_heap_alloc(void *handle, u32 size, u32 align); + +/* + * Frees the block to this Heap + */ +int sl_heap_free(void *handle, void *block, u32 size); + +/* + * Get heap statistics + */ +void sl_heap_get_stats(void *handle, struct memory_stats *stats); + +/* + * Get heap extended statistics + */ +void sl_heap_get_extended_stats(void *hphandle, + struct heap_extended_stats *stats); + +/* + * Indicates whether a heap will block on free or alloc + */ +bool sl_heap_is_blocking(void *hphandle); + +#endif /* _HEAP_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/heapbufmp.h b/arch/arm/plat-omap/include/syslink/heapbufmp.h new file mode 100644 index 000000000000..56699f3bc968 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/heapbufmp.h @@ -0,0 +1,253 @@ +/* + * heapbufmp.h + * + * Heap module manages fixed size buffers that can be used + * in a multiprocessor system with shared memory. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _HEAPBUFMP_H_ +#define _HEAPBUFMP_H_ + +#include <linux/types.h> +#include <heap.h> +#include <listmp.h> + +/*! + * @def LISTMP_MODULEID + * @brief Unique module ID. + */ +#define HEAPBUFMP_MODULEID (0x4cd5) + +/* + * Creation of Heap Buf succesful. +*/ +#define HEAPBUFMP_CREATED (0x05251995) + +/* + * Version. + */ +#define HEAPBUFMP_VERSION (1) + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ + +/*! + * @def HEAPBUFMP_S_BUSY + * @brief The resource is still in use + */ +#define HEAPBUFMP_S_BUSY 2 + +/*! + * @def HEAPBUFMP_S_ALREADYSETUP + * @brief The module has been already setup + */ +#define HEAPBUFMP_S_ALREADYSETUP 1 + +/*! + * @def HEAPBUFMP_S_SUCCESS + * @brief Operation is successful. + */ +#define HEAPBUFMP_S_SUCCESS 0 + +/*! + * @def HEAPBUFMP_E_FAIL + * @brief Generic failure. + */ +#define HEAPBUFMP_E_FAIL -1 + +/*! + * @def HEAPBUFMP_E_INVALIDARG + * @brief Argument passed to function is invalid. + */ +#define HEAPBUFMP_E_INVALIDARG -2 + +/*! + * @def HEAPBUFMP_E_MEMORY + * @brief Operation resulted in memory failure. + */ +#define HEAPBUFMP_E_MEMORY -3 + +/*! + * @def HEAPBUFMP_E_ALREADYEXISTS + * @brief The specified entity already exists. + */ +#define HEAPBUFMP_E_ALREADYEXISTS -4 + +/*! + * @def HEAPBUFMP_E_NOTFOUND + * @brief Unable to find the specified entity. + */ +#define HEAPBUFMP_E_NOTFOUND -5 + +/*! + * @def HEAPBUFMP_E_TIMEOUT + * @brief Operation timed out. + */ +#define HEAPBUFMP_E_TIMEOUT -6 + +/*! + * @def HEAPBUFMP_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define HEAPBUFMP_E_INVALIDSTATE -7 + +/*! + * @def HEAPBUFMP_E_OSFAILURE + * @brief A failure occurred in an OS-specific call */ +#define HEAPBUFMP_E_OSFAILURE -8 + +/*! + * @def HEAPBUFMP_E_RESOURCE + * @brief Specified resource is not available */ +#define HEAPBUFMP_E_RESOURCE -9 + +/*! + * @def HEAPBUFMP_E_RESTART + * @brief Operation was interrupted. Please restart the operation */ +#define HEAPBUFMP_E_RESTART -10 + + +/* ============================================================================= + * Macros + * ============================================================================= + */ + + +/* ============================================================================= + * Structures & Enums + * ============================================================================= + */ + +/* + * Structure defining config parameters for the HeapBuf module. + */ +struct heapbufmp_config { + u32 max_name_len; /* Maximum length of name */ + u32 max_runtime_entries; /* Maximum number of heapbufmp instances */ + /* that can be created */ + bool track_allocs; /* Track the maximum number of allocated */ + /* blocks */ +}; + +/* + * Structure defining parameters for the HeapBuf module + */ +struct heapbufmp_params { + char *name; /* Name of this instance */ + u16 region_id; /* Shared region ID */ + void *shared_addr; /* Physical address of the shared memory */ + u32 block_size; /* Size (in MAUs) of each block */ + u32 num_blocks; /* Number of fixed-size blocks */ + u32 align; /* Alignment (in MAUs, power of 2) of each block */ + bool exact; /* Only allocate on exact match of rquested size */ + void *gate; /* GateMP used for critical region management of */ + /* the shared memory */ +}; + +/* + * Stats structure for the getExtendedStats API. + */ +struct heapbufmp_extended_stats { + u32 max_allocated_blocks; + /* maximum number of blocks allocated from this heap instance */ + u32 num_allocated_blocks; + /* total number of blocks currently allocated from this heap instance*/ +}; + +/* ============================================================================= + * APIs + * ============================================================================= + */ + +/* + * Function to get default configuration for the heapbufmp module + */ +int heapbufmp_get_config(struct heapbufmp_config *cfgparams); + +/* + * Function to setup the heapbufmp module + */ +int heapbufmp_setup(const struct heapbufmp_config *cfg); + +/* + * Function to destroy the heapbufmp module + */ +int heapbufmp_destroy(void); + +/* Initialize this config-params structure with supplier-specified + * defaults before instance creation + */ +void heapbufmp_params_init(struct heapbufmp_params *params); + +/* + * Creates a new instance of heapbufmp module + */ +void *heapbufmp_create(const struct heapbufmp_params *params); + +/* + * Deletes a instance of heapbufmp module + */ +int heapbufmp_delete(void **handle_ptr); + +/* + * Opens a created instance of heapbufmp module by name + */ +int heapbufmp_open(char *name, void **handle_ptr); + +/* + * Opens a created instance of heapbufmp module by address + */ +int heapbufmp_open_by_addr(void *shared_addr, void **handle_ptr); + +/* + * Closes previously opened/created instance of heapbufmp module + */ +int heapbufmp_close(void **handle_ptr); + +/* + * Returns the amount of shared memory required for creation + * of each instance + */ +int heapbufmp_shared_mem_req(const struct heapbufmp_params *params); + +/* + * Allocate a block + */ +void *heapbufmp_alloc(void *hphandle, u32 size, u32 align); + +/* + * Frees the block to this heapbufmp + */ +int heapbufmp_free(void *hphandle, void *block, u32 size); + +/* + * Get memory statistics + */ +void heapbufmp_get_stats(void *hphandle, struct memory_stats *stats); + +/* + * Indicate whether the heap may block during an alloc or free call + */ +bool heapbufmp_isblocking(void *handle); + +/* + * Get extended statistics + */ +void heapbufmp_get_extended_stats(void *hphandle, + struct heapbufmp_extended_stats *stats); + + +#endif /* _HEAPBUFMP_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/heapbufmp_ioctl.h b/arch/arm/plat-omap/include/syslink/heapbufmp_ioctl.h new file mode 100644 index 000000000000..5c801487fc11 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/heapbufmp_ioctl.h @@ -0,0 +1,232 @@ +/* + * heapbufmp_ioctl.h + * + * Heap module manages fixed size buffers that can be used + * in a multiprocessor system with shared memory. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _HEAPBUFMP_IOCTL_ +#define _HEAPBUFMP_IOCTL_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <heapbufmp.h> + + +enum CMD_HEAPBUF { + HEAPBUFMP_GETCONFIG = HEAPBUFMP_BASE_CMD, + HEAPBUFMP_SETUP, + HEAPBUFMP_DESTROY, + HEAPBUFMP_PARAMS_INIT, + HEAPBUFMP_CREATE, + HEAPBUFMP_DELETE, + HEAPBUFMP_OPEN, + HEAPBUFMP_OPENBYADDR, + HEAPBUFMP_CLOSE, + HEAPBUFMP_ALLOC, + HEAPBUFMP_FREE, + HEAPBUFMP_SHAREDMEMREQ, + HEAPBUFMP_GETSTATS, + HEAPBUFMP_GETEXTENDEDSTATS +}; + +/* + * Command for heapbufmp_get_config + */ +#define CMD_HEAPBUFMP_GETCONFIG _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_GETCONFIG, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_setup + */ +#define CMD_HEAPBUFMP_SETUP _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_SETUP, \ + struct heapbufmp_cmd_args) +/* + * Command for heapbufmp_destroy + */ +#define CMD_HEAPBUFMP_DESTROY _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_DESTROY, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_prams_init + */ +#define CMD_HEAPBUFMP_PARAMS_INIT _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_PARAMS_INIT, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_create + */ +#define CMD_HEAPBUFMP_CREATE _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_CREATE, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_delete + */ +#define CMD_HEAPBUFMP_DELETE _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_DELETE, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_open + */ +#define CMD_HEAPBUFMP_OPEN _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_OPEN, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_open_by_addr + */ +#define CMD_HEAPBUFMP_OPENBYADDR _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_OPENBYADDR, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_close + */ +#define CMD_HEAPBUFMP_CLOSE _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_CLOSE, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_alloc + */ +#define CMD_HEAPBUFMP_ALLOC _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_ALLOC, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_free + */ +#define CMD_HEAPBUFMP_FREE _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_FREE, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_shared_mem_req + */ +#define CMD_HEAPBUFMP_SHAREDMEMREQ _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_SHAREDMEMREQ, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_get_stats + */ +#define CMD_HEAPBUFMP_GETSTATS _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_GETSTATS, \ + struct heapbufmp_cmd_args) + +/* + * Command for heapbufmp_get_extended_stats + */ +#define CMD_HEAPBUFMP_GETEXTENDEDSTATS _IOWR(IPC_IOC_MAGIC, \ + HEAPBUFMP_GETEXTENDEDSTATS, \ + struct heapbufmp_cmd_args) + + +/* + * Command arguments for heapbuf + */ +union heapbufmp_arg { + struct { + struct heapbufmp_params *params; + } params_init; + + struct { + struct heapbufmp_config *config; + } get_config; + + struct { + struct heapbufmp_config *config; + } setup; + + struct { + void *handle; + struct heapbufmp_params *params; + u32 name_len; + u32 *shared_addr_srptr; + void *knl_gate; + } create; + + struct { + void *handle; + } delete; + + struct { + void *handle; + char *name; + u32 name_len; + } open; + + struct { + void *handle; + u32 *shared_addr_srptr; + } open_by_addr; + + struct { + void *handle; + } close; + + struct { + void *handle; + u32 size; + u32 align; + u32 *block_srptr; + } alloc; + + struct { + void *handle; + u32 *block_srptr; + u32 size; + } free; + + struct { + void *handle; + struct memory_stats *stats; + } get_stats; + + struct { + void *handle; + struct heapbufmp_extended_stats *stats; + } get_extended_stats; + + struct { + void *handle; + struct heapbufmp_params *params; + u32 *shared_addr_srptr; + u32 bytes; + } shared_mem_req; +}; + +/* + * Command arguments for heapbuf + */ +struct heapbufmp_cmd_args{ + union heapbufmp_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for heapbuf module + */ +int heapbufmp_ioctl(struct inode *pinode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _HEAPBUFMP_IOCTL_ */ diff --git a/arch/arm/plat-omap/include/syslink/heapmemmp.h b/arch/arm/plat-omap/include/syslink/heapmemmp.h new file mode 100644 index 000000000000..bfce85be4b5b --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/heapmemmp.h @@ -0,0 +1,252 @@ +/* + * heapmemmp.h + * + * Heap module manages fixed size buffers that can be used + * in a multiprocessor system with shared memory. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _HEAPMEMMP_H_ +#define _HEAPMEMMP_H_ + +#include <linux/types.h> +#include <heap.h> +#include <listmp.h> + +/*! + * @def LISTMP_MODULEID + * @brief Unique module ID. + */ +#define HEAPMEMMP_MODULEID (0x4cd7) + +/* + * Creation of Heap Buf succesful. +*/ +#define HEAPMEMMP_CREATED (0x07041776) + +/* + * Version. + */ +#define HEAPMEMMP_VERSION (1) + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ + +/*! + * @def HEAPMEMMP_S_BUSY + * @brief The resource is still in use + */ +#define HEAPMEMMP_S_BUSY 2 + +/*! + * @def HEAPMEMMP_S_ALREADYSETUP + * @brief The module has been already setup + */ +#define HEAPMEMMP_S_ALREADYSETUP 1 + +/*! + * @def HEAPMEMMP_S_SUCCESS + * @brief Operation is successful. + */ +#define HEAPMEMMP_S_SUCCESS 0 + +/*! + * @def HEAPMEMMP_E_FAIL + * @brief Generic failure. + */ +#define HEAPMEMMP_E_FAIL -1 + +/*! + * @def HEAPMEMMP_E_INVALIDARG + * @brief Argument passed to function is invalid. + */ +#define HEAPMEMMP_E_INVALIDARG -2 + +/*! + * @def HEAPMEMMP_E_MEMORY + * @brief Operation resulted in memory failure. + */ +#define HEAPMEMMP_E_MEMORY -3 + +/*! + * @def HEAPMEMMP_E_ALREADYEXISTS + * @brief The specified entity already exists. + */ +#define HEAPMEMMP_E_ALREADYEXISTS -4 + +/*! + * @def HEAPMEMMP_E_NOTFOUND + * @brief Unable to find the specified entity. + */ +#define HEAPMEMMP_E_NOTFOUND -5 + +/*! + * @def HEAPMEMMP_E_TIMEOUT + * @brief Operation timed out. + */ +#define HEAPMEMMP_E_TIMEOUT -6 + +/*! + * @def HEAPMEMMP_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define HEAPMEMMP_E_INVALIDSTATE -7 + +/*! + * @def HEAPMEMMP_E_OSFAILURE + * @brief A failure occurred in an OS-specific call */ +#define HEAPMEMMP_E_OSFAILURE -8 + +/*! + * @def HEAPMEMMP_E_RESOURCE + * @brief Specified resource is not available */ +#define HEAPMEMMP_E_RESOURCE -9 + +/*! + * @def HEAPMEMMP_E_RESTART + * @brief Operation was interrupted. Please restart the operation */ +#define HEAPMEMMP_E_RESTART -10 + + +/* ============================================================================= + * Macros + * ============================================================================= + */ + + +/* ============================================================================= + * Structures & Enums + * ============================================================================= + */ + +/* + * Structure defining config parameters for the HeapBuf module. + */ +struct heapmemmp_config { + u32 max_name_len; /* Maximum length of name */ + u32 max_runtime_entries; /* Maximum number of heapmemmp instances */ + /* that can be created */ +}; + +/* + * Structure defining parameters for the HeapBuf module + */ +struct heapmemmp_params { + char *name; /* Name of this instance */ + u16 region_id; /* Shared region ID */ + void *shared_addr; /* Physical address of the shared memory */ + u32 shared_buf_size; /* Size of shared buffer */ + void *gate; /* GateMP used for critical region management of the */ + /* shared memory */ +}; + +/* + * Stats structure for the getExtendedStats API. + */ +struct heapmemmp_extended_stats { + void *buf; + /* Local address of the shared buffer */ + + u32 size; + /* Size of the shared buffer */ +}; + +/* ============================================================================= + * APIs + * ============================================================================= + */ + +/* + * Function to get default configuration for the heapmemmp module + */ +int heapmemmp_get_config(struct heapmemmp_config *cfgparams); + +/* + * Function to setup the heapmemmp module + */ +int heapmemmp_setup(const struct heapmemmp_config *cfg); + +/* + * Function to destroy the heapmemmp module + */ +int heapmemmp_destroy(void); + +/* Initialize this config-params structure with supplier-specified + * defaults before instance creation + */ +void heapmemmp_params_init(struct heapmemmp_params *params); + +/* + * Creates a new instance of heapmemmp module + */ +void *heapmemmp_create(const struct heapmemmp_params *params); + +/* + * Deletes a instance of heapmemmp module + */ +int heapmemmp_delete(void **handle_ptr); + +/* + * Opens a created instance of heapmemmp module by name + */ +int heapmemmp_open(char *name, void **handle_ptr); + +/* + * Opens a created instance of heapmemmp module by address + */ +int heapmemmp_open_by_addr(void *shared_addr, void **handle_ptr); + +/* + * Closes previously opened/created instance of heapmemmp module + */ +int heapmemmp_close(void **handle_ptr); + +/* + * Returns the amount of shared memory required for creation + * of each instance + */ +int heapmemmp_shared_mem_req(const struct heapmemmp_params *params); + +/* + * Allocate a block + */ +void *heapmemmp_alloc(void *hphandle, u32 size, u32 align); + +/* + * Frees the block to this heapmemmp + */ +int heapmemmp_free(void *hphandle, void *block, u32 size); + +/* + * Get memory statistics + */ +void heapmemmp_get_stats(void *hphandle, struct memory_stats *stats); + +/* + * Indicate whether the heap may block during an alloc or free call + */ +bool heapmemmp_isblocking(void *handle); + +/* + * Get extended statistics + */ +void heapmemmp_get_extended_stats(void *hphandle, + struct heapmemmp_extended_stats *stats); +/* + * Restore an instance to it's original created state. + */ +void heapmemmp_restore(void *handle); + +#endif /* _HEAPMEMMP_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/heapmemmp_ioctl.h b/arch/arm/plat-omap/include/syslink/heapmemmp_ioctl.h new file mode 100644 index 000000000000..f95dad36c45b --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/heapmemmp_ioctl.h @@ -0,0 +1,243 @@ +/* + * heapmemmp_ioctl.h + * + * Heap module manages fixed size buffers that can be used + * in a multiprocessor system with shared memory. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _HEAPMEMMP_IOCTL_ +#define _HEAPMEMMP_IOCTL_ + +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <heapmemmp.h> + + +enum CMD_HEAPMEM { + HEAPMEMMP_GETCONFIG = HEAPMEMMP_BASE_CMD, + HEAPMEMMP_SETUP, + HEAPMEMMP_DESTROY, + HEAPMEMMP_PARAMS_INIT, + HEAPMEMMP_CREATE, + HEAPMEMMP_DELETE, + HEAPMEMMP_OPEN, + HEAPMEMMP_OPENBYADDR, + HEAPMEMMP_CLOSE, + HEAPMEMMP_ALLOC, + HEAPMEMMP_FREE, + HEAPMEMMP_SHAREDMEMREQ, + HEAPMEMMP_GETSTATS, + HEAPMEMMP_GETEXTENDEDSTATS, + HEAPMEMMP_RESTORE +}; + +/* + * Command for heapmemmp_get_config + */ +#define CMD_HEAPMEMMP_GETCONFIG _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_GETCONFIG,\ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_setup + */ +#define CMD_HEAPMEMMP_SETUP _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_SETUP, \ + struct heapmemmp_cmd_args) +/* + * Command for heapmemmp_destroy + */ +#define CMD_HEAPMEMMP_DESTROY _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_DESTROY, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_prams_init + */ +#define CMD_HEAPMEMMP_PARAMS_INIT _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_PARAMS_INIT, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_create + */ +#define CMD_HEAPMEMMP_CREATE _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_CREATE, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_delete + */ +#define CMD_HEAPMEMMP_DELETE _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_DELETE, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_open + */ +#define CMD_HEAPMEMMP_OPEN _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_OPEN, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_open_by_addr + */ +#define CMD_HEAPMEMMP_OPENBYADDR _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_OPENBYADDR, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_close + */ +#define CMD_HEAPMEMMP_CLOSE _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_CLOSE, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_alloc + */ +#define CMD_HEAPMEMMP_ALLOC _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_ALLOC, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_free + */ +#define CMD_HEAPMEMMP_FREE _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_FREE, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_shared_mem_req + */ +#define CMD_HEAPMEMMP_SHAREDMEMREQ _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_SHAREDMEMREQ, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_get_stats + */ +#define CMD_HEAPMEMMP_GETSTATS _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_GETSTATS, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_get_extended_stats + */ +#define CMD_HEAPMEMMP_GETEXTENDEDSTATS _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_GETEXTENDEDSTATS, \ + struct heapmemmp_cmd_args) + +/* + * Command for heapmemmp_restore + */ +#define CMD_HEAPMEMMP_RESTORE _IOWR(IPC_IOC_MAGIC, \ + HEAPMEMMP_RESTORE, \ + struct heapmemmp_cmd_args) + + +/* + * Command arguments for heapmem + */ +union heapmemmp_arg { + struct { + struct heapmemmp_params *params; + } params_init; + + struct { + struct heapmemmp_config *config; + } get_config; + + struct { + struct heapmemmp_config *config; + } setup; + + struct { + void *handle; + struct heapmemmp_params *params; + u32 name_len; + u32 *shared_addr_srptr; + u32 *shared_buf_srptr; + void *knl_gate; + } create; + + struct { + void *handle; + } delete; + + struct { + void *handle; + char *name; + u32 name_len; + } open; + + struct { + void *handle; + u32 *shared_addr_srptr; + } open_by_addr; + + struct { + void *handle; + } close; + + struct { + void *handle; + u32 size; + u32 align; + u32 *block_srptr; + } alloc; + + struct { + void *handle; + u32 *block_srptr; + u32 size; + } free; + + struct { + void *handle; + struct memory_stats *stats; + } get_stats; + + struct { + void *handle; + } restore; + + struct { + void *handle; + struct heapmemmp_extended_stats *stats; + } get_extended_stats; + + struct { + struct heapmemmp_params *params; + u32 *shared_addr_srptr; + u32 bytes; + } shared_mem_req; +}; + +/* + * Command arguments for heapmem + */ +struct heapmemmp_cmd_args{ + union heapmemmp_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for heapmem module + */ +int heapmemmp_ioctl(struct inode *pinode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _HEAPMEMMP_IOCTL_ */ diff --git a/arch/arm/plat-omap/include/syslink/host_os.h b/arch/arm/plat-omap/include/syslink/host_os.h new file mode 100644 index 000000000000..2e2164f314fa --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/host_os.h @@ -0,0 +1,72 @@ + +/* + * host_os.h + * + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2008 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +/* + * ======== windows.h ======== + * + *! Revision History + *! ================ + *! 08-Mar-2004 sb Added cacheflush.h to support Dynamic Memory Mapping feature + *! 16-Feb-2004 sb Added headers required for consistent_alloc + */ + +#ifndef _HOST_OS_H_ +#define _HOST_OS_H_ + +#include <generated/autoconf.h> +#include <asm/system.h> +#include <asm/atomic.h> +#include <linux/semaphore.h> +#include <linux/uaccess.h> +#include <asm/irq.h> +#include <linux/io.h> +#include <linux/syscalls.h> +#include <linux/version.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/stddef.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/sched.h> +#include <linux/fs.h> +#include <linux/file.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/ctype.h> +#include <linux/mm.h> +#include <linux/device.h> +#include <linux/vmalloc.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/pagemap.h> +#include <asm/cacheflush.h> +#include <linux/dma-mapping.h> + +/* ----------------------------------- Macros */ + +#define SEEK_SET 0 /* Seek from beginning of file. */ +#define SEEK_CUR 1 /* Seek from current position. */ +#define SEEK_END 2 /* Seek from end of file. */ + +/* TODO -- Remove, once BP defines them */ +#define INT_MAIL_MPU_IRQ 26 +#define INT_DSP_MMU_IRQ 28 + +#endif diff --git a/arch/arm/plat-omap/include/syslink/hw_defs.h b/arch/arm/plat-omap/include/syslink/hw_defs.h new file mode 100644 index 000000000000..440dbb14445e --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/hw_defs.h @@ -0,0 +1,63 @@ +/* + * hw_defs.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __HW_DEFS_H +#define __HW_DEFS_H + +#include <syslink/GlobalTypes.h> + +/* Page size */ +#define HW_PAGE_SIZE_4KB 0x1000 +#define HW_PAGE_SIZE_64KB 0x10000 +#define HW_PAGE_SIZE_1MB 0x100000 +#define HW_PAGE_SIZE_16MB 0x1000000 + +/* hw_status: return type for HW API */ +typedef long hw_status; + +/* hw_set_clear_t: Enumerated Type used to set and clear any bit */ +enum hw_set_clear_t { + HW_CLEAR, + HW_SET +} ; + +/* hw_endianism_t: Enumerated Type used to specify the endianism + * Do NOT change these values. They are used as bit fields. */ +enum hw_endianism_t { + HW_LITTLE_ENDIAN, + HW_BIG_ENDIAN + +} ; + +/* hw_elemnt_siz_t: Enumerated Type used to specify the element size + * Do NOT change these values. They are used as bit fields. */ +enum hw_elemnt_siz_t { + HW_ELEM_SIZE_8BIT, + HW_ELEM_SIZE_16BIT, + HW_ELEM_SIZE_32BIT, + HW_ELEM_SIZE_64BIT + +} ; + +/* HW_IdleMode_t: Enumerated Type used to specify Idle modes */ +enum HW_IdleMode_t { + HW_FORCE_IDLE, + HW_NO_IDLE, + HW_SMART_IDLE +} ; + +#endif /* __HW_DEFS_H */ diff --git a/arch/arm/plat-omap/include/syslink/hw_mbox.h b/arch/arm/plat-omap/include/syslink/hw_mbox.h new file mode 100644 index 000000000000..f50ef782e66f --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/hw_mbox.h @@ -0,0 +1,447 @@ +/* + * hw_mbox.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __MBOX_H +#define __MBOX_H + +#include <syslink/hw_defs.h> + + +#define HW_MBOX_INT_NEW_MSG 0x1 +#define HW_MBOX_INT_NOT_FULL 0x2 +#define HW_MBOX_INT_ALL 0x3 + +/* + * DEFINITION: HW_MBOX_MAX_NUM_MESSAGES + * + * DESCRIPTION: Maximum number of messages that mailbox can hald at a time. + * + * + */ + +#define HW_MBOX_MAX_NUM_MESSAGES 4 + + + /* width in bits of MBOX Id */ +#define HW_MBOX_ID_WIDTH 2 + + +/* + * TYPE: enum hw_mbox_id_t + * + * DESCRIPTION: Enumerated Type used to specify Mail Box Sub Module Id Number + * + * + */ + enum hw_mbox_id_t { + HW_MBOX_ID_0, + HW_MBOX_ID_1, + HW_MBOX_ID_2, + HW_MBOX_ID_3, + HW_MBOX_ID_4, + HW_MBOX_ID_5 + }; + +/* + * TYPE: enum hw_mbox_userid_t + * + * DESCRIPTION: Enumerated Type used to specify Mail box User Id + * + * + */ + enum hw_mbox_userid_t { + HW_MBOX_U0_ARM11, + HW_MBOX_U1_UMA, + HW_MBOX_U2_IVA, + HW_MBOX_U3_ARM11 + }; + +#if defined(OMAP3430) +/* +* TYPE: mailbox_context +* +* DESCRIPTION: Mailbox context settings +* +* +*/ +struct mailbox_context { + unsigned long sysconfig; + unsigned long irqEnable0; + unsigned long irqEnable1; +}; +#endif/* defined(OMAP3430)*/ + +/* +* FUNCTION : hw_mbox_msg_read +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to read +* +* OUTPUTS: +* +* Identifier : p_read_value +* Type : unsigned long *const +* Description : Value read from MailBox +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* RET_EMPTY Mailbox empty +* +* PURPOSE: +* : this function reads a unsigned long from the sub module message +* box Specified. if there are no messages in the mailbox +* then and error is returned. +* +*/ +extern long hw_mbox_msg_read( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + unsigned long *const p_read_value + ); + +/* +* FUNCTION : hw_mbox_msg_write +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to write +* +* Identifier : write_value +* Type : const unsigned long +* Description : Value to write to MailBox +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE:: this function writes a unsigned long from the sub module message +* box Specified. +* +* +*/ +extern long hw_mbox_msg_write( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const unsigned long write_value + ); + +/* +* FUNCTION : hw_mbox_is_full +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to check +* +* OUTPUTS: +* +* Identifier : p_is_full +* Type : unsigned long *const +* Description : false means mail box not Full +* true means mailbox full. +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function reads the full status register for mailbox. +* +* +*/ +extern long hw_mbox_is_full( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + unsigned long *const p_is_full + ); + +/* ----------------------------------------------------------------- +* FUNCTION : hw_mbox_nomsg_get +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to get num messages +* +* OUTPUTS: +* +* Identifier : p_num_msg +* Type : unsigned long *const +* Description : Number of messages in mailbox +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Inavlid ID input at parameter +* +* PURPOSE: +* : this function gets number of messages in a specified mailbox. +* +* +*/ +extern long hw_mbox_nomsg_get( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + unsigned long *const p_num_msg + ); + +/* +* FUNCTION : hw_mbox_event_enable +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to enable +* +* Identifier : user_id +* Type : const enum hw_mbox_userid_t +* Description : Mail box User Id to enable +* +* Identifier : enableIrq +* Type : const unsigned long +* Description : Irq value to enable +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM A Pointer Paramater was set to NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function enables the specified IRQ. +* +* +*/ +extern long hw_mbox_event_enable( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const enum hw_mbox_userid_t user_id, + const unsigned long events + ); + +/* +* FUNCTION : hw_mbox_event_disable +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to disable +* +* Identifier : user_id +* Type : const enum hw_mbox_userid_t +* Description : Mail box User Id to disable +* +* Identifier : enableIrq +* Type : const unsigned long +* Description : Irq value to disable +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM A Pointer Paramater was set to NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function disables the specified IRQ. +* +* +*/ +extern long hw_mbox_event_disable( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const enum hw_mbox_userid_t user_id, + const unsigned long events + ); + +/* +* FUNCTION : hw_mbox_event_status +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to clear +* +* Identifier : user_id +* Type : const enum hw_mbox_userid_t +* Description : Mail box User Id to clear +* +* OUTPUTS: +* +* Identifier : pIrqStatus +* Type : pMBOX_Int_t *const +* Description : The value in IRQ status register +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function gets the status of the specified IRQ. +* +* +*/ +extern long hw_mbox_event_status( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const enum hw_mbox_userid_t user_id, + unsigned long *const p_eventStatus + ); + +/* +* FUNCTION : hw_mbox_event_ack +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to set +* +* Identifier : user_id +* Type : const enum hw_mbox_userid_t +* Description : Mail box User Id to set +* +* Identifier : irqStatus +* Type : const unsigned long +* Description : The value to write IRQ status +* +* OUTPUTS: +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address Paramater was set to 0 +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function sets the status of the specified IRQ. +* +* +*/ +extern long hw_mbox_event_ack( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const enum hw_mbox_userid_t user_id, + const unsigned long event + ); + +#if defined(OMAP3430) +/* --------------------------------------------------------------- +* FUNCTION : hw_mbox_save_settings +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* RET_EMPTY Mailbox empty +* +* PURPOSE: : this function saves the context of mailbox +* +* ---------------------------------------------------------------- +*/ +extern long hw_mbox_save_settings(unsigned long baseAddres); + +/* +* FUNCTION : hw_mbox_restore_settings +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* RET_EMPTY Mailbox empty +* +* PURPOSE: : this function restores the context of mailbox +* +* +*/ +extern long hw_mbox_restore_settings(unsigned long baseAddres); +#endif/* defined(OMAP3430)*/ + +#endif /* __MBOX_H */ + diff --git a/arch/arm/plat-omap/include/syslink/hw_mmu.h b/arch/arm/plat-omap/include/syslink/hw_mmu.h new file mode 100644 index 000000000000..3463fe1e4086 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/hw_mmu.h @@ -0,0 +1,171 @@ +/* + * hw_mbox.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __HW_MMU_H +#define __HW_MMU_H + +#include <linux/types.h> + +/* Bitmasks for interrupt sources */ +#define HW_MMU_TRANSLATION_FAULT 0x2 +#define HW_MMU_ALL_INTERRUPTS 0x1F + +#define HW_MMU_COARSE_PAGE_SIZE 0x400 + +/* hw_mmu_mixed_size_t: Enumerated Type used to specify whether to follow + CPU/TLB Element size */ +enum hw_mmu_mixed_size_t { + HW_MMU_TLBES, + HW_MMU_CPUES + +} ; + +/* hw_mmu_map_attrs_t: Struct containing MMU mapping attributes */ +struct hw_mmu_map_attrs_t { + enum hw_endianism_t endianism; + enum hw_elemnt_siz_t element_size; + enum hw_mmu_mixed_size_t mixedSize; +} ; + +extern hw_status hw_mmu_enable(const u32 base_address); + +extern hw_status hw_mmu_disable(const u32 base_address); + +extern hw_status hw_mmu_numlocked_set(const u32 base_address, + u32 num_lcked_entries); + +extern hw_status hw_mmu_victim_numset(const u32 base_address, + u32 vctm_entry_num); + +/* For MMU faults */ +extern hw_status hw_mmu_eventack(const u32 base_address, + u32 irq_mask); + +extern hw_status hw_mmu_event_disable(const u32 base_address, + u32 irq_mask); + +extern hw_status hw_mmu_event_enable(const u32 base_address, + u32 irq_mask); + +extern hw_status hw_mmu_event_status(const u32 base_address, + u32 *irq_mask); + +extern hw_status hw_mmu_flt_adr_rd(const u32 base_address, + u32 *addr); + +/* Set the TT base address */ +extern hw_status hw_mmu_ttbset(const u32 base_address, + u32 ttb_phys_addr); + +extern hw_status hw_mmu_twl_enable(const u32 base_address); + +extern hw_status hw_mmu_twl_disable(const u32 base_address); + +extern hw_status hw_mmu_tlb_flush(const u32 base_address, + u32 virtual_addr, + u32 page_size); + +extern hw_status hw_mmu_tlb_flushAll(const u32 base_address); + +extern hw_status hw_mmu_tlb_add(const u32 base_address, + u32 physical_addr, + u32 virtual_addr, + u32 page_size, + u32 entryNum, + struct hw_mmu_map_attrs_t *map_attrs, + enum hw_set_clear_t preserve_bit, + enum hw_set_clear_t valid_bit); + + +/* For PTEs */ +extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, + u32 physical_addr, + u32 virtual_addr, + u32 page_size, + struct hw_mmu_map_attrs_t *map_attrs); + +extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, + u32 pg_size, + u32 virtual_addr); + +static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va) +{ + u32 pte_addr; + u32 VA_31_to_20; + + VA_31_to_20 = va >> (20 - 2); /* Left-shift by 2 here itself */ + VA_31_to_20 &= 0xFFFFFFFCUL; + pte_addr = l1_base + VA_31_to_20; + + return pte_addr; +} + +static inline u32 hw_mmu_pte_addr_l2(u32 l2_base, u32 va) +{ + u32 pte_addr; + + pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC); + + return pte_addr; +} + +static inline u32 hw_mmu_pte_coarsel1(u32 pte_val) +{ + u32 pteCoarse; + + pteCoarse = pte_val & 0xFFFFFC00; + + return pteCoarse; +} + +static inline u32 hw_mmu_pte_sizel1(u32 pte_val) +{ + u32 pte_size = 0; + + if ((pte_val & 0x3) == 0x1) { + /* Points to L2 PT */ + pte_size = HW_MMU_COARSE_PAGE_SIZE; + } + + if ((pte_val & 0x3) == 0x2) { + if (pte_val & (1 << 18)) + pte_size = HW_PAGE_SIZE_16MB; + else + pte_size = HW_PAGE_SIZE_1MB; + } + + return pte_size; +} + +static inline u32 hw_mmu_pte_sizel2(u32 pte_val) +{ + u32 pte_size = 0; + + if (pte_val & 0x2) + pte_size = HW_PAGE_SIZE_4KB; + else if (pte_val & 0x1) + pte_size = HW_PAGE_SIZE_64KB; + + return pte_size; +} +extern hw_status hw_mmu_tlb_dump(u32 base_address, bool shw_inv_entries); + +extern u32 hw_mmu_pte_phyaddr(u32 pte_val, u32 pte_size); + +extern u32 hw_mmu_fault_dump(const u32 base_address); + +#endif /* __HW_MMU_H */ diff --git a/arch/arm/plat-omap/include/syslink/hw_ocp.h b/arch/arm/plat-omap/include/syslink/hw_ocp.h new file mode 100644 index 000000000000..7277bbfcde33 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/hw_ocp.h @@ -0,0 +1,60 @@ +/* + * hw_ocp.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + + +#ifndef __HW_OCP_H +#define __HW_OCP_H + +#include <syslink/GlobalTypes.h> +#include <syslink/hw_ocp.h> +#include <syslink/hw_defs.h> +#include <syslink/MBXRegAcM.h> +#include <syslink/MBXAccInt.h> + + +/* +* TYPE: HW_IdleMode_t +* +* DESCRIPTION: Enumerated Type for idle modes in OCP SYSCONFIG register +* +* +*/ +enum hal_ocp_idlemode_t { + HW_OCP_FORCE_IDLE, + HW_OCP_NO_IDLE, + HW_OCP_SMART_IDLE +}; + +extern long hw_ocp_soft_reset(const unsigned long base_address); + +extern long hw_ocp_soft_reset_isdone(const unsigned long base_address, + unsigned long *reset_is_done); + +extern long hw_ocp_idle_modeset(const unsigned long base_address, + enum hal_ocp_idlemode_t idle_mode); + +extern long hw_ocp_idlemode_get(const unsigned long base_address, + enum hal_ocp_idlemode_t *idle_mode); + +extern long hw_ocp_autoidle_set(const unsigned long base_address, + enum hw_set_clear_t auto_idle); + +extern long hw_ocp_autoidle_get(const unsigned long base_address, + enum hw_set_clear_t *auto_idle); + +#endif /* __HW_OCP_H */ + diff --git a/arch/arm/plat-omap/include/syslink/igatempsupport.h b/arch/arm/plat-omap/include/syslink/igatempsupport.h new file mode 100644 index 000000000000..0f350d123ad1 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/igatempsupport.h @@ -0,0 +1,74 @@ +/* + * igatempsupport.h + * + * Interface implemented by all multiprocessor gates. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + * + */ + +#ifndef _IGATEMPSUPPORT_H_ +#define _IGATEMPSUPPORT_H_ + + +/* Invalid Igate */ +#define IGATEMPSUPPORT_NULL (void *)0xFFFFFFFF + +/* Gates with this "quality" may cause the calling thread to block; + * i.e., suspend execution until another thread leaves the gate. */ +#define IGATEMPSUPPORT_Q_BLOCKING 1 + +/* Gates with this "quality" allow other threads to preempt the thread + * that has already entered the gate. */ +#define IGATEMPSUPPORT_Q_PREEMPTING 2 + +/* Object embedded in other Gate modules. (Inheritance) */ +#define IGATEMPSUPPORT_SUPERPARAMS \ + u32 resource_id; \ + bool open_flag; \ + u16 region_id; \ + void *shared_addr \ + +/* All other GateMP modules inherit this. */ +#define IGATEMPSUPPORT_INHERIT(X) \ +enum X##_local_protect { \ + X##_LOCALPROTECT_NONE = 0, \ + X##_LOCALPROTECT_INTERRUPT = 1, \ + X##_LOCALPROTECT_TASKLET = 2, \ + X##_LOCALPROTECT_THREAD = 3, \ + X##_LOCALPROTECT_PROCESS = 4 \ +}; + +/* Paramter initializer. */ +#define IGATEMPSUPPORT_PARAMSINTIALIZER(x) \ + (x)->resource_id = 0; \ + (x)->open_flag = true; \ + (x)->region_id = 0; \ + (x)->shared_addr = NULL + +enum igatempsupport_local_protect { + IGATEMPSUPPORT_LOCALPROTECT_NONE = 0, + IGATEMPSUPPORT_LOCALPROTECT_INTERRUPT = 1, + IGATEMPSUPPORT_LOCALPROTECT_TASKLET = 2, + IGATEMPSUPPORT_LOCALPROTECT_THREAD = 3, + IGATEMPSUPPORT_LOCALPROTECT_PROCESS = 4 +}; + +struct igatempsupport_params { + u32 resource_id; + bool open_flag; + u16 region_id; + void *shared_addr; +}; + + +#endif /* ifndef __IGATEMPSUPPORT_H__ */ diff --git a/arch/arm/plat-omap/include/syslink/igateprovider.h b/arch/arm/plat-omap/include/syslink/igateprovider.h new file mode 100644 index 000000000000..6c10591cca97 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/igateprovider.h @@ -0,0 +1,121 @@ +/* + * igateprovider.h + * + * Interface implemented by all gate providers. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + * + */ +/** ============================================================================ + * Gates are used serialize access to data structures that are used by more + * than one thread. + * + * Gates are responsible for ensuring that only one out of multiple threads + * can access a data structure at a time. There + * are important scheduling latency and performance considerations that + * affect the "type" of gate used to protect each data structure. For + * example, the best way to protect a shared counter is to simply disable + * all interrupts before the update and restore the interrupt state after + * the update; disabling all interrupts prevents all thread switching, so + * the update is guaranteed to be "atomic". Although highly efficient, this + * method of creating atomic sections causes serious system latencies when + * the time required to update the data structure can't be bounded. + * + * For example, a memory manager's list of free blocks can grow indefinitely + * long during periods of high fragmentation. Searching such a list with + * interrupts disabled would cause system latencies to also become unbounded. + * In this case, the best solution is to provide a gate that suspends the + * execution of threads that try to enter a gate that has already been + * entered; i.e., the gate "blocks" the thread until the thread + * already in the gate leaves. The time required to enter and leave the + * gate is greater than simply enabling and restoring interrupts, but since + * the time spent within the gate is relatively large, the overhead caused by + * entering and leaving gates will not become a significant percentage of + * overall system time. More importantly, threads that do not need to + * access the shared data structure are completely unaffected by threads + * that do access it. + * ============================================================================ + */ + + +#ifndef _IGATEPROVIDER_H_ +#define _IGATEPROVIDER_H_ + + +/* Invalid Igate */ +#define IGATEPROVIDER_NULL (struct igateprovider_object *)0xFFFFFFFF + +/* Gates with this "quality" may cause the calling thread to block; + * i.e., suspend execution until another thread leaves the gate. */ +#define IGateProvider_Q_BLOCKING 1 + +/* Gates with this "quality" allow other threads to preempt the thread + * that has already entered the gate. */ +#define IGateProvider_Q_PREEMPTING 2 + +/* Object embedded in other Gate modules. (Inheritance) */ +#define IGATEPROVIDER_SUPEROBJECT \ + int *(*enter)(void *); \ + void (*leave)(void *, int *) + +#define IGATEPROVIDER_OBJECTINITIALIZER(x, y) \ + ((struct igateprovider_object *)(x))->enter = y##_enter; \ + ((struct igateprovider_object *)(x))->leave = y##_leave; + + +/* Structure for generic gate instance */ +struct igateprovider_object { + IGATEPROVIDER_SUPEROBJECT; +}; + + +/* + * Enter this gate + * + * Each gate provider can implement mutual exclusion using different + * algorithms; e.g., disabling all scheduling, disabling the scheduling + * of all threads below a specified "priority level", suspending the + * caller when the gate has been entered by another thread and + * re-enabling it when the the other thread leaves the gate. However, + * in all cases, after this method returns that caller has exclusive + * access to the data protected by this gate. + * + * A thread may reenter a gate without blocking or failing. + */ +static inline int *igateprovider_enter(struct igateprovider_object *handle) +{ + int *key = 0; + + if (handle != IGATEPROVIDER_NULL) + key = (handle->enter)((void *)handle); + return key; +} + + +/* + * Leave this gate + * + * This method is only called by threads that have previously entered + * this gate via `{@link #enter}`. After this method returns, the + * caller must not access the data structure protected by this gate + * (unless the caller has entered the gate more than once and other + * calls to `leave` remain to balance the number of previous + * calls to `enter`). + */ +static inline void igateprovider_leave(struct igateprovider_object *handle, + int *key) +{ + if (handle != IGATEPROVIDER_NULL) + (handle->leave)((void *)handle, key); +} + +#endif /* ifndef _IGATEPROVIDER_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/iobject.h b/arch/arm/plat-omap/include/syslink/iobject.h new file mode 100644 index 000000000000..4d0c1e6c7e03 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/iobject.h @@ -0,0 +1,176 @@ +/* + * iobject.h + * + * Interface to provide object creation facilities. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + + +#ifndef _IOBJECT_H_ +#define _IOBJECT_H_ + +/* ObjType */ +enum ipc_obj_type { + IPC_OBJTYPE_CREATESTATIC = 0x1, + IPC_OBJTYPE_CREATESTATIC_REGION = 0x2, + IPC_OBJTYPE_CREATEDYNAMIC = 0x4, + IPC_OBJTYPE_CREATEDYNAMIC_REGION = 0x8, + IPC_OBJTYPE_OPENDYNAMIC = 0x10, + IPC_OBJTYPE_LOCAL = 0x20 +}; + + +/* Object embedded in other module's object */ +#define IOBJECT_SUPEROBJECT \ + void *next; \ + int status; + +/* Generic macro to define a create/delete function for a module */ +#define IOBJECT_CREATE0(MNAME) \ +static struct MNAME##_object *MNAME##_first_object;\ +\ +\ +void *MNAME##_create(const struct MNAME##_params *params)\ +{ \ + int *key;\ + struct MNAME##_object *obj = (struct MNAME##_object *)\ + kmalloc(sizeof(struct MNAME##_object),\ + GFP_KERNEL);\ + if (!obj)\ + return NULL;\ + memset(obj, 0, sizeof(struct MNAME##_object));\ + obj->status = MNAME##_instance_init(obj, params);\ + if (obj->status == 0) { \ + key = gate_enter_system();\ + if (MNAME##_first_object == NULL) { \ + MNAME##_first_object = obj;\ + obj->next = NULL;\ + } else { \ + obj->next = MNAME##_first_object;\ + MNAME##_first_object = obj;\ + } \ + gate_leave_system(key);\ + } else { \ + kfree(obj);\ + obj = NULL;\ + } \ + return obj;\ +} \ +\ +\ +int MNAME##_delete(void **handle)\ +{ \ + int *key;\ + struct MNAME##_object *temp;\ + struct MNAME##_object *obj;\ + \ + if (handle == NULL) \ + return -EINVAL;\ + if (*handle == NULL) \ + return -EINVAL;\ + obj = (struct MNAME##_object *)(*handle);\ + key = gate_enter_system();\ + if (obj == MNAME##_first_object) \ + MNAME##_first_object = obj->next;\ + else { \ + temp = MNAME##_first_object;\ + while (temp) { \ + if (temp->next == obj) { \ + temp->next = obj->next;\ + break;\ + } else { \ + temp = temp->next;\ + } \ + } \ + if (temp == NULL) { \ + gate_leave_system(key);\ + return -EINVAL;\ + } \ + } \ + gate_leave_system(key);\ + MNAME##_instance_finalize(obj, obj->status);\ + kfree(obj);\ + *handle = NULL;\ + return 0;\ +} + +#define IOBJECT_CREATE1(MNAME, ARG) \ +static struct MNAME##_object *MNAME##_first_object;\ +\ +\ +void *MNAME##_create(ARG arg, const struct MNAME##_params *params)\ +{ \ + int *key;\ + struct MNAME##_object *obj = (struct MNAME##_object *) \ + kmalloc(sizeof(struct MNAME##_object),\ + GFP_KERNEL);\ + if (!obj) \ + return NULL;\ + memset(obj, 0, sizeof(struct MNAME##_object));\ + obj->status = MNAME##_instance_init(obj, arg, params);\ + if (obj->status == 0) { \ + key = gate_enter_system();\ + if (MNAME##_first_object == NULL) { \ + MNAME##_first_object = obj;\ + obj->next = NULL;\ + } else { \ + obj->next = MNAME##_first_object;\ + MNAME##_first_object = obj;\ + } \ + gate_leave_system(key);\ + } else { \ + kfree(obj);\ + obj = NULL;\ + } \ + return obj;\ +} \ +\ +\ +int MNAME##_delete(void **handle)\ +{ \ + int *key;\ + struct MNAME##_object *temp;\ + struct MNAME##_object *obj;\ + \ + if (handle == NULL) \ + return -EINVAL;\ + if (*handle == NULL) \ + return -EINVAL;\ + obj = (struct MNAME##_object *)(*handle);\ + key = gate_enter_system();\ + if (obj == MNAME##_first_object) \ + MNAME##_first_object = obj->next;\ + else { \ + temp = MNAME##_first_object;\ + while (temp) { \ + if (temp->next == obj) { \ + temp->next = obj->next;\ + break;\ + } else { \ + temp = temp->next;\ + } \ + } \ + if (temp == NULL) { \ + gate_leave_system(key);\ + return -EINVAL;\ + } \ + } \ + gate_leave_system(key);\ + MNAME##_instance_finalize(obj, obj->status);\ + kfree(obj);\ + *handle = NULL;\ + return 0;\ +} + + +#endif /* ifndef _IOBJECT_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/ipc.h b/arch/arm/plat-omap/include/syslink/ipc.h new file mode 100644 index 000000000000..ddd3faeeee11 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/ipc.h @@ -0,0 +1,167 @@ +/* + * sysmgr.h + * + * Defines for System manager. + * + * Copyright(C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _IPC_H_ +#define _IPC_H_ + + +/* Module headers */ +#include <multiproc.h> +#include <gatepeterson.h> +#include <sharedregion.h> +#include <notify.h> +#include <notify_ducatidriver.h> +#include <heap.h> +#include <heapbufmp.h> +#include <heapmemmp.h> + + + +/* Unique module ID. */ +#define IPC_MODULEID (0xF086) + + +/* ============================================================================= + * Module Success and Failure codes + * ============================================================================= + */ +/* The resource is still in use */ +#define IPC_S_BUSY 2 + +/* The module has been already setup */ +#define IPC_S_ALREADYSETUP 1 + +/* Operation is successful. */ +#define IPC_S_SUCCESS 0 + +/* Generic failure. */ +#define IPC_E_FAIL -1 + +/* Argument passed to function is invalid. */ +#define IPC_E_INVALIDARG -2 + +/* Operation resulted in memory failure. */ +#define IPC_E_MEMORY -3 + +/* The specified entity already exists. */ +#define IPC_E_ALREADYEXISTS -4 + +/* Unable to find the specified entity. */ +#define IPC_E_NOTFOUND -5 + +/* Operation timed out. */ +#define IPC_E_TIMEOUT -6 + +/* Module is not initialized. */ +#define IPC_E_INVALIDSTATE -7 + +/* A failure occurred in an OS-specific call */ +#define IPC_E_OSFAILURE -8 + +/* Specified resource is not available */ +#define IPC_E_RESOURCE -9 + +/* Operation was interrupted. Please restart the operation */ +#define IPC_E_RESTART -10 + + +/* ============================================================================= + * Macros + * ============================================================================= + */ +/* IPC_CONTROLCMD_LOADCALLBACK */ +#define IPC_CONTROLCMD_LOADCALLBACK (0xBABE0000) + +/* IPC_CONTROLCMD_STARTCALLBACK */ +#define IPC_CONTROLCMD_STARTCALLBACK (0xBABE0001) + +/* IPC_CONTROLCMD_STOPCALLBACK */ +#define IPC_CONTROLCMD_STOPCALLBACK (0xBABE0002) + + +/* ============================================================================= + * Enums & Structures + * ============================================================================= + */ +/* the different options for processor synchronization */ +enum ipc_proc_sync { + IPC_PROCSYNC_NONE, /* don't do any processor sync */ + IPC_PROCSYNC_PAIR, /* sync pair of processors in ipc_attach */ + IPC_PROCSYNC_ALL /* sync all processors, done in ipc_start */ +}; + +/* ipc configuration structure. */ +struct ipc_config { + enum ipc_proc_sync proc_sync; + /* the different options for processor synchronization */ +}; + +/* ipc configuration structure. */ +struct ipc_params { + bool setup_messageq; + bool setup_notify; + bool setup_ipu_pm; + bool slave; + enum ipc_proc_sync proc_sync; +}; + + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Attach to remote processor */ +int ipc_attach(u16 remote_proc_id); + +/* Detach from the remote processor */ +int ipc_detach(u16 remote_proc_id); + +/* Reads the config entry from the config area. */ +int ipc_read_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size); + +/* Reserves memory, creates default gatemp and heapmemmp */ +int ipc_start(void); + +/* Writes the config entry to the config area. */ +int ipc_write_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size); + +/* Returns default configuration values for ipc. */ +void ipc_get_config(struct ipc_config *cfg_params); + +/* Sets up ipc for this processor. */ +int ipc_setup(const struct ipc_config *cfg_params); + +/* Destroys ipc for this processor. */ +int ipc_destroy(void); + +/* Creates a ipc. */ +int ipc_create(u16 proc_id, struct ipc_params *params); + +/* Function to control a Ipc instance for a slave */ +int ipc_control(u16 proc_id, u32 cmd_id, void *arg); + +/* Function to read configuration information from ipc module */ +int ipc_read_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size); + +/* Function to write configuration information to ipc module */ +int ipc_write_config(u16 remote_proc_id, u32 tag, void *cfg, u32 size); + +/* Clears memory, deletes default gatemp and heapmemmp */ +int ipc_stop(void); + + +#endif /* ifndef _IPC_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/ipc_ioctl.h b/arch/arm/plat-omap/include/syslink/ipc_ioctl.h new file mode 100644 index 000000000000..6c16a3d22e12 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/ipc_ioctl.h @@ -0,0 +1,92 @@ +/* + * ipc_ioctl.h + * + * Base file for all TI OMAP IPC ioctl's. + * Linux-OMAP IPC has allocated base 0xEE with a range of 0x00-0xFF. + * (need to get the real one from open source maintainers) + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _IPC_IOCTL_H +#define _IPC_IOCTL_H + +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/fs.h> + +#define IPC_IOC_MAGIC 0xE0 +#define IPC_IOC_BASE 2 + +enum ipc_command_count { + MULTIPROC_CMD_NOS = 4, + NAMESERVER_CMD_NOS = 15, + HEAPBUFMP_CMD_NOS = 14, + SHAREDREGION_CMD_NOS = 13, + GATEMP_CMD_NOS = 13, + LISTMP_CMD_NOS = 19, + MESSAGEQ_CMD_NOS = 18, + IPC_CMD_NOS = 5, + SYSMEMMGR_CMD_NOS = 6, + HEAPMEMMP_CMD_NOS = 15, + NOTIFY_CMD_NOS = 18 +}; + +enum ipc_command_ranges { + MULTIPROC_BASE_CMD = IPC_IOC_BASE, + MULTIPROC_END_CMD = (MULTIPROC_BASE_CMD + \ + MULTIPROC_CMD_NOS - 1), + + NAMESERVER_BASE_CMD = 10, + NAMESERVER_END_CMD = (NAMESERVER_BASE_CMD + \ + NAMESERVER_CMD_NOS - 1), + + HEAPBUFMP_BASE_CMD = 30, + HEAPBUFMP_END_CMD = (HEAPBUFMP_BASE_CMD + \ + HEAPBUFMP_CMD_NOS - 1), + + SHAREDREGION_BASE_CMD = 50, + SHAREDREGION_END_CMD = (SHAREDREGION_BASE_CMD + \ + SHAREDREGION_CMD_NOS - 1), + + GATEMP_BASE_CMD = 70, + GATEMP_END_CMD = (GATEMP_BASE_CMD + \ + GATEMP_CMD_NOS - 1), + + LISTMP_BASE_CMD = 90, + LISTMP_END_CMD = (LISTMP_BASE_CMD + \ + LISTMP_CMD_NOS - 1), + + MESSAGEQ_BASE_CMD = 110, + MESSAGEQ_END_CMD = (MESSAGEQ_BASE_CMD + \ + MESSAGEQ_CMD_NOS - 1), + + IPC_BASE_CMD = 130, + IPC_END_CMD = (IPC_BASE_CMD + \ + IPC_CMD_NOS - 1), + + SYSMEMMGR_BASE_CMD = 140, + SYSMEMMGR_END_CMD = (SYSMEMMGR_BASE_CMD + \ + SYSMEMMGR_CMD_NOS - 1), + + HEAPMEMMP_BASE_CMD = 150, + HEAPMEMMP_END_CMD = (HEAPMEMMP_BASE_CMD + \ + HEAPMEMMP_CMD_NOS - 1), + + NOTIFY_BASE_CMD = 170, + NOTIFY_END_CMD = (NOTIFY_BASE_CMD + \ + NOTIFY_CMD_NOS - 1) +}; + +int ipc_ioc_router(u32 cmd, ulong arg); + +#endif /* _IPC_IOCTL_H */ diff --git a/arch/arm/plat-omap/include/syslink/listmp.h b/arch/arm/plat-omap/include/syslink/listmp.h new file mode 100644 index 000000000000..31d2429e851f --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/listmp.h @@ -0,0 +1,146 @@ +/* + * listmp.h + * + * The listmp module defines the shared memory doubly linked list. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _LISTMP_H_ +#define _LISTMP_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Utilities headers */ +#include <linux/list.h> +/*#include <heap.h>*/ + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ +/* The resource is still in use */ +#define LISTMP_S_BUSY 2 + +/* The module has already been setup */ +#define LISTMP_S_ALREADYSETUP 1 + +/* Operation is successful. */ +#define LISTMP_SUCCESS 0 + +/* Generic failure. */ +#define LISTMP_E_FAIL -1 + +/* Argument passed to a function is invalid. */ +#define LISTMP_E_INVALIDARG -2 + +/* Memory allocation failed. */ +#define LISTMP_E_MEMORY -3 + +/* The specified entity already exists. */ +#define LISTMP_E_ALREADYEXISTS -4 + +/* Unable to find the specified entity. */ +#define LISTMP_E_NOTFOUND -5 + +/* Operation timed out. */ +#define LISTMP_E_TIMEOUT -6 + +/* Module is not initialized. */ +#define LISTMP_E_INVALIDSTATE -7 + +/* A failure occurred in an OS-specific call */ +#define LISTMP_E_OSFAILURE -8 + +/* Specified resource is not available */ +#define LISTMP_E_RESOURCE -9 + +/* Operation was interrupted. Please restart the operation */ +#define LISTMP_E_RESTART -10 + + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +#define VOLATILE volatile + +/* Structure defining list element for the ListMP. */ +struct listmp_elem { + VOLATILE struct listmp_elem *next; + VOLATILE struct listmp_elem *prev; +}; + +/* Structure defining config parameters for the ListMP instances. */ +struct listmp_params { + /* gatemp instance for critical management of shared memory */ + void *gatemp_handle; + void *shared_addr; /* physical address of the shared memory */ + char *name; /* name of the instance */ + u16 region_id; /* sharedregion id */ +}; + + +/* Function initializes listmp parameters */ +void listmp_params_init(struct listmp_params *params); + +/* Function to create an instance of ListMP */ +void *listmp_create(const struct listmp_params *params); + +/* Function to delete an instance of ListMP */ +int listmp_delete(void **listmp_handle_ptr); + +/* Function to open a previously created instance */ +int listmp_open(char *name, void **listmp_handle_ptr); + +/* Function to open a previously created instance */ +int listmp_open_by_addr(void *shared_addr, void **listmp_handle_ptr); + +/* Function to close a previously opened instance */ +int listmp_close(void **listmp_handle); + +/* Function to check if list is empty */ +bool listmp_empty(void *listmp_handle); + +/* Retrieves the GateMP handle associated with the ListMP instance. */ +void *listmp_get_gate(void *listmp_handle); + +/* Function to get head element from list */ +void *listmp_get_head(void *listmp_handle); + +/* Function to get tail element from list */ +void *listmp_get_tail(void *listmp_handle); + +/* Function to insert element into list */ +int listmp_insert(void *listmp_handle, struct listmp_elem *new_elem, + struct listmp_elem *cur_elem); + +/* Function to traverse to next element in list */ +void *listmp_next(void *listmp_handle, struct listmp_elem *elem); + +/* Function to traverse to prev element in list */ +void *listmp_prev(void *listmp_handle, struct listmp_elem *elem); + +/* Function to put head element into list */ +int listmp_put_head(void *listmp_handle, struct listmp_elem *elem); + +/* Function to put tail element into list */ +int listmp_put_tail(void *listmp_handle, struct listmp_elem *elem); + +/* Function to traverse to remove element from list */ +int listmp_remove(void *listmp_handle, struct listmp_elem *elem); + +/* Function to get shared memory requirement for the module */ +uint listmp_shared_mem_req(const struct listmp_params *params); + +#endif /* _LISTMP_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/listmp_ioctl.h b/arch/arm/plat-omap/include/syslink/listmp_ioctl.h new file mode 100644 index 000000000000..bb0825efcef3 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/listmp_ioctl.h @@ -0,0 +1,268 @@ +/* + * listmp_ioctl.h + * + * Definitions of listmp driver types and structures. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _LISTMP_IOCTL_H_ +#define _LISTMP_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <listmp.h> +#include <sharedregion.h> + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/* Base command ID for listmp */ +#define LISTMP_IOC_MAGIC IPC_IOC_MAGIC +enum listmp_drv_cmd { + LISTMP_GETCONFIG = LISTMP_BASE_CMD, + LISTMP_SETUP, + LISTMP_DESTROY, + LISTMP_PARAMS_INIT, + LISTMP_CREATE, + LISTMP_DELETE, + LISTMP_OPEN, + LISTMP_CLOSE, + LISTMP_ISEMPTY, + LISTMP_GETHEAD, + LISTMP_GETTAIL, + LISTMP_PUTHEAD, + LISTMP_PUTTAIL, + LISTMP_INSERT, + LISTMP_REMOVE, + LISTMP_NEXT, + LISTMP_PREV, + LISTMP_SHAREDMEMREQ, + LISTMP_OPENBYADDR +}; + +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for listmp + * ---------------------------------------------------------------------------- + */ +/* Command for listmp_get_config */ +#define CMD_LISTMP_GETCONFIG _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_GETCONFIG, \ + struct listmp_cmd_args) + +/* Command for listmp_setup */ +#define CMD_LISTMP_SETUP _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_SETUP, \ + struct listmp_cmd_args) + +/* Command for listmp_destroy */ +#define CMD_LISTMP_DESTROY _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_DESTROY, \ + struct listmp_cmd_args) + +/* Command for listmp_params_init */ +#define CMD_LISTMP_PARAMS_INIT _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_PARAMS_INIT, \ + struct listmp_cmd_args) + +/* Command for listmp_create */ +#define CMD_LISTMP_CREATE _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_CREATE, \ + struct listmp_cmd_args) + +/* Command for listmp_delete */ +#define CMD_LISTMP_DELETE _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_DELETE, \ + struct listmp_cmd_args) + +/* Command for listmp_open */ +#define CMD_LISTMP_OPEN _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_OPEN, \ + struct listmp_cmd_args) + +/* Command for listmp_close */ +#define CMD_LISTMP_CLOSE _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_CLOSE, \ + struct listmp_cmd_args) + +/* Command for listmp_is_empty */ +#define CMD_LISTMP_ISEMPTY _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_ISEMPTY, \ + struct listmp_cmd_args) + +/* Command for listmp_get_head */ +#define CMD_LISTMP_GETHEAD _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_GETHEAD, \ + struct listmp_cmd_args) + +/* Command for listmp_get_tail */ +#define CMD_LISTMP_GETTAIL _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_GETTAIL, \ + struct listmp_cmd_args) + +/* Command for listmp_put_head */ +#define CMD_LISTMP_PUTHEAD _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_PUTHEAD, \ + struct listmp_cmd_args) + +/* Command for listmp_put_tail */ +#define CMD_LISTMP_PUTTAIL _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_PUTTAIL, \ + struct listmp_cmd_args) + +/* Command for listmp_insert */ +#define CMD_LISTMP_INSERT _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_INSERT, \ + struct listmp_cmd_args) + +/* Command for listmp_remove */ +#define CMD_LISTMP_REMOVE _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_REMOVE, \ + struct listmp_cmd_args) + +/* Command for listmp_next */ +#define CMD_LISTMP_NEXT _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_NEXT, \ + struct listmp_cmd_args) + +/* Command for listmp_prev */ +#define CMD_LISTMP_PREV _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_PREV, \ + struct listmp_cmd_args) + +/* Command for listmp_shared_mem_req */ +#define CMD_LISTMP_SHAREDMEMREQ _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_SHAREDMEMREQ, \ + struct listmp_cmd_args) + +/* Command for listmp_open_by_addr */ +#define CMD_LISTMP_OPENBYADDR _IOWR(LISTMP_IOC_MAGIC, \ + LISTMP_OPENBYADDR, \ + struct listmp_cmd_args) + +/* Command arguments for listmp */ +struct listmp_cmd_args { + union { + struct { + struct listmp_params *params; + } params_init; + + struct { + struct listmp_config *config; + } get_config; + + struct { + struct listmp_config *config; + } setup; + + struct { + void *listmp_handle; + struct listmp_params *params; + u32 name_len; + u32 shared_addr_srptr; + void *knl_gate; + } create; + + struct { + void *listmp_handle; + } delete_instance; + + struct { + void *listmp_handle; + u32 name_len; + char *name; + } open; + + struct { + void *listmp_handle; + u32 shared_addr_srptr; + } open_by_addr; + + + struct { + void *listmp_handle; + } close; + + struct { + void *listmp_handle; + bool is_empty; + } is_empty; + + struct { + void *listmp_handle; + u32 *elem_srptr; + } get_head; + + struct { + void *listmp_handle; + u32 *elem_srptr; + } get_tail; + + struct { + void *listmp_handle; + u32 *elem_srptr; + } put_head; + + struct { + void *listmp_handle; + u32 *elem_srptr; + } put_tail; + + struct { + void *listmp_handle; + u32 *new_elem_srptr; + u32 *cur_elem_srptr; + } insert; + + struct { + void *listmp_handle; + u32 *elem_srptr; + } remove; + + struct { + void *listmp_handle; + u32 *elem_srptr; + u32 *next_elem_srptr; + } next; + + struct { + void *listmp_handle; + u32 *elem_srptr; + u32 *prev_elem_srptr; + } prev; + + struct { + struct listmp_params *params; + u32 bytes; + void *knl_gate; + u32 *shared_addr_srptr; + u32 name_len; + void *listmp_handle; + } shared_mem_req; + } args; + + int api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for listmp module + * ---------------------------------------------------------------------------- + */ +/* ioctl interface function for listmp */ +int listmp_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _LISTMP_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/messageq.h b/arch/arm/plat-omap/include/syslink/messageq.h new file mode 100644 index 000000000000..d0d59970a49b --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/messageq.h @@ -0,0 +1,440 @@ +/* + * messageq.h + * + * The MessageQ module supports the structured sending and receiving of + * variable length messages. This module can be used for homogeneous or + * heterogeneous multi-processor messaging. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _MESSAGEQ_H_ +#define _MESSAGEQ_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Utilities headers */ +#include <linux/list.h> + +/* Syslink headers */ +#include <listmp.h> + +/*! + * @def MESSAGEQ_MODULEID + * @brief Unique module ID. + */ +#define MESSAGEQ_MODULEID (0xded2) + + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ + +/*! + * @def MESSAGEQ_S_BUSY + * @brief The resource is still in use + */ +#define MESSAGEQ_S_BUSY 2 + +/*! + * @def MESSAGEQ_S_ALREADYSETUP + * @brief The module has been already setup + */ +#define MESSAGEQ_S_ALREADYSETUP 1 + +/*! + * @def MESSAGEQ_S_SUCCESS + * @brief Operation is successful. + */ +#define MESSAGEQ_S_SUCCESS 0 + +/*! + * @def MESSAGEQ_E_FAIL + * @brief Operation is not successful. + */ +#define MESSAGEQ_E_FAIL -1 + +/*! + * @def MESSAGEQ_E_INVALIDARG + * @brief There is an invalid argument. + */ +#define MESSAGEQ_E_INVALIDARG -2 + +/*! + * @def MESSAGEQ_E_MEMORY + * @brief Operation resulted in memory failure. + */ +#define MESSAGEQ_E_MEMORY -3 + +/*! + * @def MESSAGEQ_E_ALREADYEXISTS + * @brief The specified entity already exists. + */ +#define MESSAGEQ_E_ALREADYEXISTS -4 + +/*! + * @def MESSAGEQ_E_NOTFOUND + * @brief Unable to find the specified entity. + */ +#define MESSAGEQ_E_NOTFOUND -5 + +/*! + * @def MESSAGEQ_E_TIMEOUT + * @brief Operation timed out. + */ +#define MESSAGEQ_E_TIMEOUT -6 + +/*! + * @def MESSAGEQ_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define MESSAGEQ_E_INVALIDSTATE -7 + +/*! + * @def MESSAGEQ_E_OSFAILURE + * @brief A failure occurred in an OS-specific call + */ +#define MESSAGEQ_E_OSFAILURE -8 + +/*! + * @def MESSAGEQ_E_RESOURCE + * @brief Specified resource is not available + */ +#define MESSAGEQ_E_RESOURCE -9 + +/*! + * @def MESSAGEQ_E_RESTART + * @brief Operation was interrupted. Please restart the operation + */ +#define MESSAGEQ_E_RESTART -10 + +/*! + * @def MESSAGEQ_E_INVALIDMSG + * @brief Operation is successful. + */ +#define MESSAGEQ_E_INVALIDMSG -11 + +/*! + * @def MESSAGEQ_E_NOTOWNER + * @brief Not the owner + */ +#define MESSAGEQ_E_NOTOWNER -12 + +/*! + * @def MESSAGEQ_E_REMOTEACTIVE + * @brief Operation is successful. + */ +#define MESSAGEQ_E_REMOTEACTIVE -13 + +/*! + * @def MESSAGEQ_E_INVALIDHEAPID + * @brief Operation is successful. + */ +#define MESSAGEQ_E_INVALIDHEAPID -14 + +/*! + * @def MESSAGEQ_E_INVALIDPROCID + * @brief Operation is successful. + */ +#define MESSAGEQ_E_INVALIDPROCID -15 + +/*! + * @def MESSAGEQ_E_MAXREACHED + * @brief Operation is successful. + */ +#define MESSAGEQ_E_MAXREACHED -16 + +/*! + * @def MESSAGEQ_E_UNREGISTEREDHEAPID + * @brief Operation is successful. + */ +#define MESSAGEQ_E_UNREGISTEREDHEAPID -17 + +/*! + * @def MESSAGEQ_E_CANNOTFREESTATICMSG + * @brief Operation is successful. + */ +#define MESSAGEQ_E_CANNOTFREESTATICMSG -18 + + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/*! + * @brief Mask to extract version setting + */ +#define MESSAGEQ_HEADERVERSION 0x2000u + +/*! Mask to extract Trace setting */ +#define MESSAGEQ_TRACEMASK (uint) 0x1000 + +/*! Shift for Trace setting */ +#define MESSAGEQ_TRACESHIFT (uint) 12 + +/*! + * @brief Mask to extract priority setting + */ +#define MESSAGEQ_PRIORITYMASK 0x3u + +/*! + * Used as the timeout value to specify wait forever + */ +#define MESSAGEQ_FOREVER (~((u32) 0)) + +/*! + * Invalid message id + */ +#define MESSAGEQ_INVALIDMSGID 0xFFFF + +/*! + * Invalid message queue + */ +#define MESSAGEQ_INVALIDMESSAGEQ 0xFFFF + +/*! + * Indicates that if maximum number of message queues are already created, + * should allow growth to create additional Message Queue. + */ +#define MESSAGEQ_ALLOWGROWTH (~((u32) 0)) + +/*! + * Number of types of priority queues for each transport + */ +#define MESSAGEQ_NUM_PRIORITY_QUEUES 2 + + +/* ============================================================================= + * Structures & Enums + * ============================================================================= + */ +/*! + * Message priority + */ +enum messageq_priority { + MESSAGEQ_NORMALPRI = 0, + /*!< Normal priority message */ + MESSAGEQ_HIGHPRI = 1, + /*!< High priority message */ + MESSAGEQ_RESERVEDPRI = 2, + /*!< Reserved value for message priority */ + MESSAGEQ_URGENTPRI = 3 + /*!< Urgent priority message */ +}; + +/*! Structure which defines the first field in every message */ +struct msgheader { + u32 reserved0; + /*!< Reserved field */ + u32 reserved1; + /*!< Reserved field */ + u32 msg_size; + /*!< Size of the message (including header) */ + u16 flags; + /*!< Flags */ + u16 msg_id; + /*!< Maximum length for Message queue names */ + u16 dst_id; + /*!< Maximum length for Message queue names */ + u16 dst_proc; + /*!< Maximum length for Message queue names */ + u16 reply_id; + /*!< Maximum length for Message queue names */ + u16 reply_proc; + /*!< Maximum length for Message queue names */ + u16 src_proc; + /*!< Maximum length for Message queue names */ + u16 heap_id; + /*!< Maximum length for Message queue names */ + u16 seq_num; + /*!< sequence number */ + u32 reserved; + /*!< Reserved field */ +}; + +/*! Structure which defines the first field in every message */ +#define messageq_msg struct msgheader * +/*typedef struct msgheader *messageq_msg;*/ + + +/*! + * @brief Structure defining config parameters for the MessageQ Buf module. + */ +struct messageq_config { + bool trace_flag; + /*!< Trace Flag + * This flag allows the configuration of the default module trace + * settings. + */ + + u16 num_heaps; + /*!< Number of heapIds in the system + * This allows MessageQ to pre-allocate the heaps table. + * The heaps table is used when registering heaps. + * The default is 1 since generally all systems need at least one heap. + * There is no default heap, so unless the system is only using + * staticMsgInit, the application must register a heap. + */ + + u32 max_runtime_entries; + /*! + * Maximum number of MessageQs that can be dynamically created + */ + + u32 max_name_len; + /*!< Maximum length for Message queue names */ +}; + +struct messageq_params { + void *synchronizer; + /*!< Synchronizer instance used to signal IO completion + * + * The synchronizer is used in the #MessageQ_put and #MessageQ_get calls. + * The synchronizer signal is called as part of the #MessageQ_put call. + * The synchronizer waits in the #MessageQ_get if there are no messages + * present. + */ +}; + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Functions to get the configuration for messageq setup */ +void messageq_get_config(struct messageq_config *cfg); + +/* Function to setup the MessageQ module. */ +int messageq_setup(const struct messageq_config *cfg); + +/* Function to destroy the MessageQ module. */ +int messageq_destroy(void); + +/* Returns the amount of shared memory used by one transport instance. + * + * The MessageQ module itself does not use any shared memory but the + * underlying transport may use some shared memory. + */ +uint messageq_shared_mem_req(void *shared_addr); + +/* Calls the SetupProxy function to setup the MessageQ transports. */ +int messageq_attach(u16 remote_proc_id, void *shared_addr); + +/* Calls the SetupProxy function to detach the MessageQ transports. */ +int messageq_detach(u16 remote_proc_id); + +/* Initialize this config-params structure with supplier-specified + * defaults before instance creation. + */ +void messageq_params_init(struct messageq_params *params); + +/* Create a message queue */ +void *messageq_create(char *name, const struct messageq_params *params); + +/* Deletes a instance of MessageQ module. */ +int messageq_delete(void **messageq_handleptr); + +/* Open a message queue */ +int messageq_open(char *name, u32 *queue_id); + +/* Close an opened message queue handle */ +int messageq_close(u32 *queue_id); + +/* Allocates a message from the heap */ +messageq_msg messageq_alloc(u16 heapId, u32 size); + +/* Frees a message back to the heap */ +int messageq_free(messageq_msg msg); + +/* Initializes a message not obtained from MessageQ_alloc */ +void messageq_static_msg_init(messageq_msg msg, u32 size); + +/* Place a message onto a message queue */ +int messageq_put(u32 queueId, messageq_msg msg); + +/* Gets a message for a message queue and blocks if the queue is empty */ +int messageq_get(void *messageq_handle, messageq_msg *msg, u32 timeout); + +/* Register a heap with MessageQ */ +int messageq_register_heap(void *heap_handle, u16 heap_id); + +/* Unregister a heap with MessageQ */ +int messageq_unregister_heap(u16 heapId); + +/* Returns the number of messages in a message queue */ +int messageq_count(void *messageq_handle); + +/* Get the proc Id of the message. */ +u16 messageq_get_proc_id(void *messageq_handle); + +/* Get the queue Id of the message. */ +u32 messageq_get_queue_id(void *messageq_handle); + +/* Set the destination queue of the message. */ +void messageq_set_reply_queue(void *messageq_handle, messageq_msg msg); + +/* Set the tracing of a message */ +void messageq_set_msg_trace(messageq_msg msg, bool trace_flag); + +/* + * Functions to set Message properties + */ +/*! + * @brief Returns the MessageQ_Queue handle of the destination + * message queue for the specified message. + */ +u32 messageq_get_dst_queue(messageq_msg msg); + +/*! + * @brief Returns the message ID of the specified message. + */ +u16 messageq_get_msg_id(messageq_msg msg); + +/*! + * @brief Returns the size of the specified message. + */ +u32 messageq_get_msg_size(messageq_msg msg); + +/*! + * @brief Gets the message priority of a message + */ +u32 messageq_get_msg_pri(messageq_msg msg); + +/*! + * @brief Returns the MessageQ_Queue handle of the destination + * message queue for the specified message. + */ +u32 messageq_get_reply_queue(messageq_msg msg); + +/*! + * @brief Sets the message ID in the specified message. + */ +void messageq_set_msg_id(messageq_msg msg, u16 msg_id); +/*! + * @brief Sets the message priority in the specified message. + */ +void messageq_set_msg_pri(messageq_msg msg, u32 priority); + +/* ============================================================================= + * APIs called internally by MessageQ transports + * ============================================================================= + */ +/* Register a transport with MessageQ */ +int messageq_register_transport(void *imessageq_transport_handle, + u16 proc_id, u32 priority); + +/* Unregister a transport with MessageQ */ +void messageq_unregister_transport(u16 proc_id, u32 priority); + + +#endif /* _MESSAGEQ_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/messageq_ioctl.h b/arch/arm/plat-omap/include/syslink/messageq_ioctl.h new file mode 100644 index 000000000000..34da7e1f3a5b --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/messageq_ioctl.h @@ -0,0 +1,255 @@ +/* + * messageq_ioctl.h + * + * Definitions of messageq driver types and structures. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _MESSAGEQ_IOCTL_H_ +#define _MESSAGEQ_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <messageq.h> +#include <heap.h> +#include <sharedregion.h> + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +#define MESSAGEQ_IOC_MAGIC IPC_IOC_MAGIC +enum messageq_drv_cmd { + MESSAGEQ_GETCONFIG = MESSAGEQ_BASE_CMD, + MESSAGEQ_SETUP, + MESSAGEQ_DESTROY, + MESSAGEQ_PARAMS_INIT, + MESSAGEQ_CREATE, + MESSAGEQ_DELETE, + MESSAGEQ_OPEN, + MESSAGEQ_CLOSE, + MESSAGEQ_COUNT, + MESSAGEQ_ALLOC, + MESSAGEQ_FREE, + MESSAGEQ_PUT, + MESSAGEQ_REGISTERHEAP, + MESSAGEQ_UNREGISTERHEAP, + MESSAGEQ_ATTACH, + MESSAGEQ_DETACH, + MESSAGEQ_GET, + MESSAGEQ_SHAREDMEMREQ +}; + +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for messageq + * ---------------------------------------------------------------------------- + */ +/* Base command ID for messageq */ +#define MESSAGEQ_BASE_CMD 0x0 + +/* Command for messageq_get_config */ +#define CMD_MESSAGEQ_GETCONFIG \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_GETCONFIG, \ + struct messageq_cmd_args) + +/* Command for messageq_setup */ +#define CMD_MESSAGEQ_SETUP \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_SETUP, \ + struct messageq_cmd_args) + +/* Command for messageq_destroy */ +#define CMD_MESSAGEQ_DESTROY \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_DESTROY, \ + struct messageq_cmd_args) + +/* Command for messageq_params_init */ +#define CMD_MESSAGEQ_PARAMS_INIT \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_PARAMS_INIT, \ + struct messageq_cmd_args) + +/* Command for messageq_create */ +#define CMD_MESSAGEQ_CREATE \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_CREATE, \ + struct messageq_cmd_args) + +/* Command for messageq_delete */ +#define CMD_MESSAGEQ_DELETE \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_DELETE, \ + struct messageq_cmd_args) + +/* Command for messageq_open */ +#define CMD_MESSAGEQ_OPEN \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_OPEN, \ + struct messageq_cmd_args) + +/* Command for messageq_close */ +#define CMD_MESSAGEQ_CLOSE \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_CLOSE, \ + struct messageq_cmd_args) + +/* Command for messageq_count */ +#define CMD_MESSAGEQ_COUNT \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_COUNT, \ + struct messageq_cmd_args) + +/* Command for messageq_alloc */ +#define CMD_MESSAGEQ_ALLOC \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_ALLOC, \ + struct messageq_cmd_args) + +/* Command for messageq_free */ +#define CMD_MESSAGEQ_FREE \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_FREE, \ + struct messageq_cmd_args) + +/* Command for messageq_put */ +#define CMD_MESSAGEQ_PUT \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_PUT, \ + struct messageq_cmd_args) + +/* Command for messageq_register_heap */ +#define CMD_MESSAGEQ_REGISTERHEAP \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_REGISTERHEAP, \ + struct messageq_cmd_args) + +/* Command for messageq_unregister_heap */ +#define CMD_MESSAGEQ_UNREGISTERHEAP \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_UNREGISTERHEAP, \ + struct messageq_cmd_args) + + +/* Command for messageq_attach */ +#define CMD_MESSAGEQ_ATTACH \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_ATTACH, \ + struct messageq_cmd_args) + +/* Command for messageq_detach */ +#define CMD_MESSAGEQ_DETACH \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_DETACH, \ + struct messageq_cmd_args) + +/* Command for messageq_get */ +#define CMD_MESSAGEQ_GET \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_GET, \ + struct messageq_cmd_args) + +/* Command for messageq_sharedmem_req */ +#define CMD_MESSAGEQ_SHAREDMEMREQ \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_SHAREDMEMREQ, \ + struct messageq_cmd_args) + +/* Command arguments for messageq */ +struct messageq_cmd_args { + union { + struct { + void *messageq_handle; + struct messageq_params *params; + } params_init; + + struct { + struct messageq_config *config; + } get_config; + + struct { + struct messageq_config *config; + } setup; + + struct { + void *messageq_handle; + char *name; + struct messageq_params *params; + u32 name_len; + u32 queue_id; + } create; + + struct { + void *messageq_handle; + } delete_messageq; + + struct { + char *name; + u32 queue_id; + u32 name_len; + } open; + + struct { + u32 queue_id; + } close; + + struct { + void *messageq_handle; + u32 timeout; + u32 *msg_srptr; + } get; + + struct { + void *messageq_handle; + int count; + } count; + + struct { + u16 heap_id; + u32 size; + u32 *msg_srptr; + } alloc; + + struct { + u32 *msg_srptr; + } free; + + struct { + u32 queue_id; + u32 *msg_srptr; + } put; + + struct { + void *heap_handle; + u16 heap_id; + } register_heap; + + struct { + u16 heap_id; + } unregister_heap; + + struct { + u32 *shared_addr_srptr; + uint mem_req; + } shared_mem_req; + + struct { + u16 remote_proc_id; + u32 *shared_addr_srptr; + } attach; + + struct { + u16 remote_proc_id; + } detach; + } args; + + int api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for messageq module + * ---------------------------------------------------------------------------- + */ +/* + * ioctl interface function for messageq + */ +int messageq_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _MESSAGEQ_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/multiproc.h b/arch/arm/plat-omap/include/syslink/multiproc.h new file mode 100644 index 000000000000..4d14e8c193c6 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/multiproc.h @@ -0,0 +1,89 @@ +/* +* multiproc.h +* +* Many multi-processor modules have the concept of processor id. multiproc +* centeralizes the processor id management. +* +* Copyright (C) 2008-2009 Texas Instruments, Inc. +* +* This package is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +*/ + +#ifndef _MULTIPROC_H_ +#define _MULTIPROC_H_ + +#include <linux/types.h> + + +#define VOLATILE volatile + +/* + * Unique module ID + */ +#define MULTIPROC_MODULEID (u16)0xB522 + +/* Macro to define invalid processor id */ +#define MULTIPROC_INVALIDID ((u16)0xFFFF) + +/* + * Maximum number of processors in the system + * OMAP4 has 4 processors in single core. + */ +#define MULTIPROC_MAXPROCESSORS 4 + +/* + * Max name length for a processor name + */ +#define MULTIPROC_MAXNAMELENGTH 32 + +/* + * Configuration structure for multiproc module + */ +struct multiproc_config { + s32 num_processors; /* Number of procs for particular system */ + char name_list[MULTIPROC_MAXPROCESSORS][MULTIPROC_MAXNAMELENGTH]; + /* Name List for processors in the system */ + u16 id; /* Local Proc ID. This needs to be set before calling any + other APIs */ +}; + +/* ============================================================================= + * APIs + * ============================================================================= + */ + +/* Function to get the default configuration for the multiproc module. */ +void multiproc_get_config(struct multiproc_config *cfg); + +/* Function to setup the multiproc Module */ +s32 multiproc_setup(struct multiproc_config *cfg); + +/* Function to destroy the multiproc module */ +s32 multiproc_destroy(void); + +/* Function to set local processor Id */ +int multiproc_set_local_id(u16 proc_id); + +/* Function to get processor id from processor name. */ +u16 multiproc_get_id(const char *proc_name); + +/* Function to get name from processor id. */ +char *multiproc_get_name(u16 proc_id); + +/* Function to get number of processors in the system. */ +u16 multiproc_get_num_processors(void); + +/* Return Id of current processor */ +u16 multiproc_self(void); + +/* Determines the offset for any two processors. */ +u32 multiproc_get_slot(u16 remote_proc_id); + +#endif /* _MULTIPROC_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h b/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h new file mode 100644 index 000000000000..0c9780136b02 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h @@ -0,0 +1,94 @@ +/* +* multiproc_ioctl.h +* +* This provides the ioctl interface for multiproc module +* +* Copyright (C) 2008-2009 Texas Instruments, Inc. +* +* This package is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +*/ + +#ifndef _MULTIPROC_IOCTL_H_ +#define _MULTIPROC_IOCTL_H_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <multiproc.h> + +enum CMD_MULTIPROC { + MULTIPROC_SETUP = MULTIPROC_BASE_CMD, + MULTIPROC_DESTROY, + MULTIPROC_GETCONFIG, + MULTIPROC_SETLOCALID +}; + +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for MultiProc + * ---------------------------------------------------------------------------- + */ + +/* + * Command for multiproc_setup + */ +#define CMD_MULTIPROC_SETUP _IOWR(IPC_IOC_MAGIC, MULTIPROC_SETUP, \ + struct multiproc_cmd_args) + +/* + * Command for multiproc_destroy + */ +#define CMD_MULTIPROC_DESTROY _IOWR(IPC_IOC_MAGIC, MULTIPROC_DESTROY, \ + struct multiproc_cmd_args) + +/* + * Command for multiproc_get_config + */ +#define CMD_MULTIPROC_GETCONFIG _IOWR(IPC_IOC_MAGIC, MULTIPROC_GETCONFIG, \ + struct multiproc_cmd_args) + +/* + * Command for multiproc_set_local_id + */ +#define CMD_MULTIPROC_SETLOCALID _IOWR(IPC_IOC_MAGIC, MULTIPROC_SETLOCALID, \ + struct multiproc_cmd_args) + +/* + * Command arguments for multiproc + */ +union multiproc_arg { + struct { + struct multiproc_config *config; + } get_config; + + struct { + struct multiproc_config *config; + } setup; + + struct { + u16 id; + } set_local_id; +}; + +/* + * Command arguments for multiproc + */ +struct multiproc_cmd_args { + union multiproc_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for multiproc module + */ +int multiproc_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _MULTIPROC_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/nameserver.h b/arch/arm/plat-omap/include/syslink/nameserver.h new file mode 100644 index 000000000000..3aeee242bc39 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver.h @@ -0,0 +1,157 @@ +/* + * nameserver.h + * + * The nameserver module manages local name/value pairs that + * enables an application and other modules to store and retrieve + * values based on a name. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVER_H_ +#define _NAMESERVER_H_ + +#include <linux/types.h> +#include <linux/list.h> + +/* + * NAMESERVER_MODULEID + * Unique module ID + */ +#define NAMESERVER_MODULEID (0xF414) + +struct nameserver_config { + u32 reserved; +}; + +/* + * Instance config-params object. + */ +struct nameserver_params { + u32 max_runtime_entries; + void *table_heap; /* Table is placed into a section on dyn creates */ + bool check_existing; /* Prevents duplicate entry add in to the table */ + u32 max_value_len; /* Length, in MAUs, of the value field */ + u16 max_name_len; /* Length, in MAUs, of name field */ +}; + + +/* + * Function to get the default configuration for the nameserver module + */ +void nameserver_get_config(struct nameserver_config *cfg); + +/* + * Function to setup the nameserver module + */ +int nameserver_setup(void); + +/* + * Function to destroy the nameserver module + */ +int nameserver_destroy(void); + +/* + * Function to construct a name server. + */ +void nameserver_construct(void *object, const char *name, + const struct nameserver_params *params); + +/* + * Function to destruct a name server + */ +void nameserver_destruct(void *object); + +/* + * Function to register a remote driver + */ +int nameserver_register_remote_driver(void *handle, u16 proc_id); + +/* + * Function to unregister a remote driver + */ +int nameserver_unregister_remote_driver(u16 proc_id); + +/* + * Determines if a remote driver is registered for the specified id. + */ +bool nameserver_is_registered(u16 proc_id); + +/* + * Function to initialize the parameter structure + */ +void nameserver_params_init(struct nameserver_params *params); + +/* + * Function to create a name server + */ +void *nameserver_create(const char *name, + const struct nameserver_params *params); + +/* + * Function to delete a name server + */ +int nameserver_delete(void **handle); + +/* + * Function to handle for a name + */ +void *nameserver_get_handle(const char *name); + +/* + * Function to add a variable length value into the local table + */ +void *nameserver_add(void *handle, const char *name, void *buf, u32 len); + +/* + * Function to add a 32 bit value into the local table + */ +void *nameserver_add_uint32(void *handle, const char *name, u32 value); + +/* + * Function to retrieve the value portion of a name/value pair + */ +int nameserver_get(void *handle, const char *name, void *buf, u32 *len, + u16 procId[]); + +/* + * Function to retrieve a 32-bit value of a name/value pair + */ +int nameserver_get_uint32(void *handle, const char *name, void *buf, + u16 procId[]); + +/* + * Function to get the value portion of a name/value pair from local table + */ +int nameserver_get_local(void *handle, const char *name, void *buf, u32 *len); + +/* + * Function to retrieve a 32-bit value from the local name/value table + */ +int nameserver_get_local_uint32(void *handle, const char *name, void *buf); + +/* + * Function to match the name + */ +int nameserver_match(void *handle, const char *name, u32 *value); + +/* + * Function to removes a value/pair + */ +int nameserver_remove(void *handle, const char *name); + +/* + * Function to remove an entry from the table + */ +int nameserver_remove_entry(void *handle, void *entry); + +#endif /* _NAMESERVER_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h b/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h new file mode 100644 index 000000000000..4909aa3fa3cb --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h @@ -0,0 +1,261 @@ +/* +* nameserver_ioctl.h +* +* This provides the ioctl interface for nameserver module +* +* Copyright (C) 2008-2009 Texas Instruments, Inc. +* +* This package is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +*/ + +#ifndef _NAMESERVER_IOCTL_H_ +#define _NAMESERVER_IOCTL_H_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <nameserver.h> + +enum CMD_NAMESERVER { + NAMESERVER_SETUP = NAMESERVER_BASE_CMD, + NAMESERVER_DESTROY, + NAMESERVER_PARAMS_INIT, + NAMESERVER_CREATE, + NAMESERVER_DELETE, + NAMESERVER_ADD, + NAMESERVER_ADDUINT32, + NAMESERVER_GET, + NAMESERVER_GETLOCAL, + NAMESERVER_MATCH, + NAMESERVER_REMOVE, + NAMESERVER_REMOVEENTRY, + NAMESERVER_GETHANDLE, + NAMESERVER_ISREGISTERED, + NAMESERVER_GETCONFIG +}; + +/* + * IOCTL command IDs for nameserver + * + */ +/* + * Command for nameserver_setup + */ +#define CMD_NAMESERVER_SETUP _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_SETUP, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_destroy + */ +#define CMD_NAMESERVER_DESTROY _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_DESTROY, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_params_init + */ +#define CMD_NAMESERVER_PARAMS_INIT _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_PARAMS_INIT, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_create + */ +#define CMD_NAMESERVER_CREATE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_CREATE, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_delete + */ +#define CMD_NAMESERVER_DELETE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_DELETE, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_add + */ +#define CMD_NAMESERVER_ADD _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_ADD, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_addu32 + */ +#define CMD_NAMESERVER_ADDUINT32 _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_ADDUINT32, \ + struct nameserver_cmd_args) +/* + * Command for nameserver_get + */ +#define CMD_NAMESERVER_GET _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_GET, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_get_local + */ +#define CMD_NAMESERVER_GETLOCAL _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_GETLOCAL, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_match + */ +#define CMD_NAMESERVER_MATCH _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_MATCH, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_remove + */ +#define CMD_NAMESERVER_REMOVE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_REMOVE, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_remove_entry + */ +#define CMD_NAMESERVER_REMOVEENTRY _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_REMOVEENTRY, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_get_handle + */ +#define CMD_NAMESERVER_GETHANDLE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_GETHANDLE, \ + struct nameserver_cmd_args) + +/* + * Command for NameServer_isRegistered + */ +#define CMD_NAMESERVER_ISREGISTERED _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_ISREGISTERED, \ + struct nameserver_cmd_args) + +/* + * Command for NameServer_getConfig + */ +#define CMD_NAMESERVER_GETCONFIG _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_GETCONFIG, \ + struct nameserver_cmd_args) + +/* + * Command arguments for nameserver + */ +union nameserver_arg { + struct { + struct nameserver_config *config; + } get_config; + + struct { + struct nameserver_config *config; + } setup; + + struct { + struct nameserver_params *params; + } params_init; + + struct { + void *handle; + char *name; + u32 name_len; + struct nameserver_params *params; + } create; + + struct { + void *handle; + } delete_instance; + + struct { + void *handle; + char *name; + u32 name_len; + void *buf; + s32 len; + void *entry; + void *node; + } add; + + struct { + void *handle; + char *name; + u32 name_len; + u32 value; + void *entry; + } addu32; + + struct { + void *handle; + char *name; + u32 name_len; + void *value; + u32 len; + u16 *proc_id; + u32 proc_len; + } get; + + struct { + void *handle; + char *name; + u32 name_len; + void *value; + u32 len; + } get_local; + + struct { + void *handle; + char *name; + u32 name_len; + u32 value; + u32 count; + } match; + + struct { + void *handle; + char *name; + u32 name_len; + } remove; + + struct { + void *handle; + void *entry; + } remove_entry; + + struct { + void *handle; + char *name; + u32 name_len; + } get_handle; + + struct { + u16 proc_id; + bool check; + } is_registered; +}; + +/* + * Command arguments for nameserver + */ +struct nameserver_cmd_args { + union nameserver_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for nameserver module + */ +int nameserver_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _NAMESERVER_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/nameserver_remote.h b/arch/arm/plat-omap/include/syslink/nameserver_remote.h new file mode 100644 index 000000000000..bc0921b08e06 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver_remote.h @@ -0,0 +1,39 @@ +/* + * nameserver_remote.h + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVER_REMOTE_H_ +#define _NAMESERVER_REMOTE_H_ + +#include <linux/types.h> + +/* + * Structure defining object for the nameserver remote driver + */ +struct nameserver_remote_object { + int (*get)(const struct nameserver_remote_object *obj, + const char *instance_name, const char *name, + void *value, u32 *value_len, void *reserved); + /* Function to get data from remote nameserver */ + void *obj; /* Implementation specific object */ +}; + +/* + * Function get data from remote name server + */ +int nameserver_remote_get(const struct nameserver_remote_object *handle, + const char *instance_name, const char *name, + void *value, u32 *value_len, void *reserved); + +#endif /* _NAMESERVER_REMOTE_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h b/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h new file mode 100644 index 000000000000..cb9b6218930d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h @@ -0,0 +1,90 @@ +/* + * nameserver_remotenotify.h + * + * The nameserver_remotenotify module provides functionality to get name + * value pair from a remote nameserver. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVER_REMOTENOTIFY_H_ +#define _NAMESERVER_REMOTENOTIFY_H_ + +#include <linux/types.h> + +/* + * NAMESERVERREMOTENOTIFY_MODULEID + * Unique module ID + */ +#define NAMESERVERREMOTENOTIFY_MODULEID (0x08FD) + +/* + * Module configuration structure + */ +struct nameserver_remotenotify_config { + u32 notify_event_id; + /* Notify event number */ +}; + +/* + * Module configuration structure + */ +struct nameserver_remotenotify_params { + void *shared_addr; /* Address of the shared memory */ + void *gatemp; /* Handle to the gatemp used for protecting the + nameserver_remotenotify instance. Using the default + value of NULL will result in the default gatemp being + used for context protection */ +}; + +/* Function to get the default configuration for the nameserver_remotenotify + * module */ +void nameserver_remotenotify_get_config( + struct nameserver_remotenotify_config *cfg); + +/* Function to setup the nameserver_remotenotify module */ +int nameserver_remotenotify_setup(struct nameserver_remotenotify_config *cfg); + +/* Function to destroy the nameserver_remotenotify module */ +int nameserver_remotenotify_destroy(void); + +/* Function to get the current configuration values */ +void nameserver_remotenotify_params_init( + struct nameserver_remotenotify_params *params); + +/* Function to create the nameserver_remotenotify object */ +void *nameserver_remotenotify_create(u16 remote_proc_id, + const struct nameserver_remotenotify_params *params); + +/* Function to delete the nameserver_remotenotify object */ +int nameserver_remotenotify_delete(void **handle); + +/* Function to get a name/value from remote nameserver */ +int nameserver_remotenotify_get(void *handle, + const char *instance_name, const char *name, + void *value, u32 *value_len, void *reserved); + +/* Get the shared memory requirements for the nameserver_remotenotify */ +uint nameserver_remotenotify_shared_mem_req( + const struct nameserver_remotenotify_params *params); + +/* Create all the NameServerRemoteNotify drivers. */ +int nameserver_remotenotify_start(void *shared_addr); + +/* Attaches to remote processor */ +int nameserver_remotenotify_attach(u16 remote_proc_id, void *shared_addr); + +/* Detaches from remote processor */ +int nameserver_remotenotify_detach(u16 remote_proc_id); + + +#endif /* _NAMESERVER_REMOTENOTIFY_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/notify.h b/arch/arm/plat-omap/include/syslink/notify.h new file mode 100644 index 000000000000..0f9a399e5ceb --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify.h @@ -0,0 +1,146 @@ +/* + * notify.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined(_NOTIFY_H_) +#define _NOTIFY_H_ + +/* The resource is still in use */ +#define NOTIFY_S_BUSY 2 + +/* Module already set up */ +#define NOTIFY_S_ALREADYSETUP 1 + +/* Operation is successful. */ +#define NOTIFY_S_SUCCESS 0 + +/* Generic failure */ +#define NOTIFY_E_FAIL -1 + +/* Argument passed to function is invalid.. */ +#define NOTIFY_E_INVALIDARG -2 + +/* Operation resulted in memory failure. */ +#define NOTIFY_E_MEMORY -3 + +/* The specified entity already exists. */ +#define NOTIFY_E_ALREADYEXISTS -4 + +/* Unable to find the specified entity. */ +#define NOTIFY_E_NOTFOUND -5 + +/* Operation timed out. */ +#define NOTIFY_E_TIMEOUT -6 + +/* Module is not initialized. */ +#define NOTIFY_E_INVALIDSTATE -7 + +/* A failure occurred in an OS-specific call */ +#define NOTIFY_E_OSFAILURE -8 + +/* The module has been already setup */ +#define NOTIFY_E_ALREADYSETUP -9 + +/* Specified resource is not available */ +#define NOTIFY_E_RESOURCE -10 + +/* Operation was interrupted. Please restart the operation */ +#define NOTIFY_E_RESTART -11 + +/* The resource is still in use */ +#define NOTIFY_E_BUSY -12 + +/* Driver corresponding to the specified eventId is not registered */ +#define NOTIFY_E_DRIVERNOTREGISTERED -13 + +/* Event not registered */ +#define NOTIFY_E_EVTNOTREGISTERED -14 + +/* Event is disabled */ +#define NOTIFY_E_EVTDISABLED -15 + +/* Remote notification is not initialized */ +#define NOTIFY_E_NOTINITIALIZED -16 + +/* Trying to illegally use a reserved event */ +#define NOTIFY_E_EVTRESERVED -17 + +/* Macro to make a correct module magic number with refCount */ +#define NOTIFY_MAKE_MAGICSTAMP(x) ((NOTIFY_MODULEID << 12u) | (x)) + +#define REG volatile + +/* Maximum number of events supported by the Notify module */ +#define NOTIFY_MAXEVENTS (u16)32 + +/* Maximum number of IPC interrupt lines per processor. */ +#define NOTIFY_MAX_INTLINES 4u + +/* This key must be provided as the upper 16 bits of the eventNo when + * registering for an event, if any reserved event numbers are to be + * used. */ +#define NOTIFY_SYSTEMKEY 0xC1D2 + + +typedef void (*notify_fn_notify_cbck)(u16 proc_id, u16 line_id, u32 event_id, + uint *arg, u32 payload); + +extern struct notify_module_object notify_state; + + +/* Function to disable Notify module */ +u32 notify_disable(u16 procId, u16 line_id); + +/* Function to disable particular event */ +void notify_disable_event(u16 proc_id, u16 line_id, u32 event_id); + +/* Function to enable particular event */ +void notify_enable_event(u16 proc_id, u16 line_id, u32 event_id); + +/* Function to find out whether notification via interrupt line has been + * registered. */ +bool notify_is_registered(u16 proc_id, u16 line_id); + +/* Returns the amount of shared memory used by one Notify instance. */ +uint notify_shared_mem_req(u16 proc_id, void *shared_addr); + +/* Function to register an event */ +int notify_register_event(u16 proc_id, u16 line_id, u32 event_id, + notify_fn_notify_cbck notify_callback_fxn, + void *cbck_arg); + +/* Function to register an event */ +int notify_register_event_single(u16 proc_id, u16 line_id, u32 event_id, + notify_fn_notify_cbck notify_callback_fxn, + void *cbck_arg); + +/* Function to restore Notify module state */ +void notify_restore(u16 proc_id, u16 line_id, u32 key); + +/* Function to send an event to other processor */ +int notify_send_event(u16 proc_id, u16 line_id, u32 event_id, u32 payload, + bool wait_clear); + +/* Function to unregister an event */ +int notify_unregister_event(u16 proc_id, u16 line_id, u32 event_id, + notify_fn_notify_cbck notify_callback_fxn, + void *cbck_arg); + +/* Function to unregister an event */ +int notify_unregister_event_single(u16 proc_id, u16 line_id, u32 event_id); + + +#endif /* !defined(_NOTIFY_H_) */ diff --git a/arch/arm/plat-omap/include/syslink/notify_dispatcher.h b/arch/arm/plat-omap/include/syslink/notify_dispatcher.h new file mode 100644 index 000000000000..efd87315815e --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_dispatcher.h @@ -0,0 +1,158 @@ +/* + * notify_dispatcher.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef __TMBX_H__ +#define __TMBX_H__ + + +#include <syslink/notifydefs.h> +#include <linux/interrupt.h> + +#include <syslink/notifyerr.h> + +#define MAX_MBOX_MODULES 2 +#define MAX_MBOX_ISRS 32 +#define KErrNone 0 +#define KErrNotSupported 1 +#define KErrNotReady 2 +#define KErrArgument 2 + +typedef void (*isr_call_back)(void *); + +struct mbox_config { + unsigned long int mbox_linear_addr; + unsigned long int mbox_modules; + signed long int interrupt_lines[MAX_MBOX_MODULES]; + signed long int mailboxes[MAX_MBOX_MODULES]; +}; + +struct mbox_isrs { + signed long int isrNo[MAX_MBOX_MODULES]; + /* TODO: Remove this - seems to be unused.*/ + isr_call_back isrs[MAX_MBOX_MODULES][MAX_MBOX_ISRS]; + void *isr_params[MAX_MBOX_MODULES][MAX_MBOX_ISRS]; +}; + +extern const unsigned long *linear_address; + +irqreturn_t notify_mailbx0_user0_isr(int temp, void *anArg, struct pt_regs *p); + +/* + *func ntfy_disp_bind_interrupt + * + * desc Bind an ISR to the HW interrupt line coming into the processor + */ +int ntfy_disp_bind_interrupt(int interrupt_no, + isr_call_back hw_isr, + void *isr_arg); + + +/* + * desc Print the mailbox registers and other useful debug information + * + */ +void ntfy_disp_debug(void); + + +/* + * func ntfy_disp_deinit + * desc Uninitialize the Mailbox Manager module + */ +int ntfy_disp_deinit(void); + + +/* + * desc Return the pointer to the Mailbox Manager's configuration object + */ +struct mbox_config *ntfy_disp_get_config(void); + + +/* + * desc Initialize the Mailbox Manager module + */ +int ntfy_disp_init(void); + + +/* + * desc Disable a particular IRQ bit on a Mailbox IRQ Enable Register + */ +int ntfy_disp_interrupt_disable(unsigned long int mbox_module_no, + int a_irq_bit); + + +/* + * desc Enable a particular IRQ bit on a Mailbox IRQ Enable Register + */ +int ntfy_disp_interrupt_enable(unsigned long int mbox_module_no, + int a_irq_bit); + + +/* + * desc Read a message on a Mailbox FIFO queue + */ +int ntfy_disp_read(unsigned long int mbox_module_no, + int a_mbox_no, + int *messages, + int *num_messages, + short int read_all); + + +/* + * func ntfy_disp_register + * desc Register a ISR callback associated with a particular IRQ bit on a + * Mailbox IRQ Enable Register + */ +int ntfy_disp_register(unsigned long int mbox_module_no, + int a_irq_bit, + isr_call_back isr_cbck_fn, + void *isrCallbackArgs); + + +/* + * func ntfy_disp_send + * desc Send a message on a Mailbox FIFO queue + */ +int ntfy_disp_send(unsigned long int mbox_module_no, + int a_mbox_no, + int message); + + +/* + * func ntfy_disp_unbind_interrupt + * desc Remove the ISR to the HW interrupt line coming into the processor + */ +int ntfy_disp_unbind_interrupt(int interrupt_no); + + +/* + * func ntfy_disp_unregister + * desc Unregister a ISR callback associated with a particular IRQ bit on a + * Mailbox IRQ Enable Register + */ +int ntfy_disp_unregister(unsigned long int mbox_module_no, + int a_irq_bit); + +/* + * func notify_mailbx0_user0_isr + * desc mail ISR + * + */ + +irqreturn_t notify_mailbx0_user0_isr(int temp, void *anArg, struct pt_regs *p); + + +#endif diff --git a/arch/arm/plat-omap/include/syslink/notify_driver.h b/arch/arm/plat-omap/include/syslink/notify_driver.h new file mode 100644 index 000000000000..95c586b77626 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_driver.h @@ -0,0 +1,45 @@ +/* + * notify_driver.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined _NOTIFY_DRIVER_H_ +#define _NOTIFY_DRIVER_H_ + + +/* Module includes */ +#include <syslink/notify_driverdefs.h> +#include <syslink/_notify.h> + + +/* Function to register notify driver */ +int notify_register_driver(u16 remote_proc_id, + u16 line_id, + struct notify_driver_fxn_table *fxn_table, + struct notify_driver_object **driver_handle); + +/* Function to unregister notify driver */ +int notify_unregister_driver(struct notify_driver_object *drv_handle); + +/* Function to set the driver handle */ +int notify_set_driver_handle(u16 remote_proc_id, u16 line_id, + struct notify_object *handle); + +/* Function to find the driver in the list of drivers */ +struct notify_driver_object *notify_get_driver_handle(u16 remote_proc_id, + u16 line_id); + + +#endif /* !defined (_NOTIFY_DRIVER_H_) */ diff --git a/arch/arm/plat-omap/include/syslink/notify_driverdefs.h b/arch/arm/plat-omap/include/syslink/notify_driverdefs.h new file mode 100644 index 000000000000..56f6b282caf7 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_driverdefs.h @@ -0,0 +1,137 @@ +/* + * notify_driverdefs.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined(_NOTIFY_DRIVERDEFS_H_) +#define _NOTIFY_DRIVERDEFS_H_ + + +/* Module headers */ +#include <syslink/multiproc.h> +#include <syslink/notify.h> +#include <syslink/_notify.h> + + +/* Enumerations to indicate types of Driver initialization status */ +enum notify_driver_init_status { + NOTIFY_DRIVERINITSTATUS_NOTDONE = 0, + /* Driver initialization is not done. */ + NOTIFY_DRIVERINITSTATUS_DONE = 1, + /* Driver initialization is complete. */ + NOTIFY_DRIVERINITSTATUS_INPROGRESS = 2, + /* Driver initialization is in progress. */ + NOTIFY_DRIVERINITSTATUS_ENDVALUE = 3 + /* End delimiter indicating start of invalid values for this enum */ +}; + +struct notify_driver_object; + +/* This structure defines the function table interface for the Notify + * driver. + * This function table interface must be implemented by each Notify + * driver and registered with the Notify module. */ +struct notify_driver_fxn_table { + int (*register_event)(struct notify_driver_object *handle, + u32 event_id); + /* interface function register_event */ + int (*unregister_event)(struct notify_driver_object *handle, + u32 event_id); + /* interface function unregister_event */ + int (*send_event)(struct notify_driver_object *handle, u32 event_id, + u32 payload, bool wait_clear); + /* interface function send_event */ + u32 (*disable)(struct notify_driver_object *handle); + /* interface function disable */ + void (*enable)(struct notify_driver_object *handle); + /* interface function enable */ + void (*disable_event)(struct notify_driver_object *handle, + u32 event_id); + /* interface function disable_event */ + void (*enable_event)(struct notify_driver_object *handle, u32 event_id); + /* interface function enable_event */ +}; + +/* This structure defines the Notify driver object and handle used + * internally to contain all information required for the Notify driver + * This object contains all information for the Notify module to be + * able to identify and interact with the Notify driver. */ +struct notify_driver_object { + enum notify_driver_init_status is_init; + struct notify_driver_fxn_table fxn_table; + struct notify_object *notify_handle; +}; + +#if 0 +/* + *This structure defines information for all processors supported by + *the Notify driver. + *An instance of this object is provided for each processor handled by + *the Notify driver, when registering itself with the Notify module. + * + */ +struct notify_driver_proc_info { + u32 max_events; + u32 reserved_events; + bool event_priority; + u32 payload_size; + u16 proc_id; +}; + +/* + * This structure defines the structure for specifying Notify driver + * attributes to the Notify module. + * This structure provides information about the Notify driver to the + * Notify module. The information is used by the Notify module mainly + * for parameter validation. It may also be used by the Notify module + * to take appropriate action if required, based on the characteristics + * of the Notify driver. + */ +struct notify_driver_attrs { + u32 numProc; + struct notify_driver_proc_info + proc_info[MULTIPROC_MAXPROCESSORS]; +}; + +union notify_drv_procevents{ + struct { + struct notify_shmdrv_attrs attrs; + struct notify_shmdrv_ctrl *ctrl_ptr; + } shm_events; + + struct { + /*Attributes */ + unsigned long int num_events; + unsigned long int send_event_pollcount; + /*Control Paramters */ + unsigned long int send_init_status ; + struct notify_shmdrv_eventreg_mask reg_mask ; + } non_shm_events; +}; + +struct notify_drv_eventlist { + unsigned long int event_handler_count; + struct list_head listeners; +}; + +struct notify_drv_proc_module { + unsigned long int proc_id; + struct notify_drv_eventlist *event_list; + struct notify_shmdrv_eventreg *reg_chart; + union notify_drv_procevents events_obj; +}; +#endif + +#endif /* !defined(_NOTIFY_DRIVERDEFS_H_) */ diff --git a/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h b/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h new file mode 100644 index 000000000000..aa805ffbb3cb --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h @@ -0,0 +1,141 @@ +/* + * notify_ducatidriver.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef NOTIFY_DUCATIDRIVER_H_ +#define NOTIFY_DUCATIDRIVER_H_ + + + +/* Notify*/ +#include <syslink/notify.h> +#include <syslink/notify_driverdefs.h> + +/* Module ID for NotifyDriverShm. */ +#define NOTIFY_DUCATIDRIVER_MODULEID ((u16) 0xb9d4) + +#define VOLATILE volatile + +extern u32 get_ducati_virt_mem(); +extern void unmap_ducati_virt_mem(u32 shm_virt_addr); + + +/* module configuration structure */ +struct notify_ducatidrv_config { + u32 reserved; +}; + +/* This structure defines the configuration structure for + * initialization of the Notify driver. */ +struct notify_ducatidrv_params { + void *shared_addr; + /* Address in shared memory where this instance will be placed */ + bool cache_enabled; + /* Whether cache operations will be performed */ + u32 cache_line_size; + /* The cache line size of the shared memory */ + u32 remote_proc_id; + /* Processor Id of remote processor required for communication */ + u32 line_id; + /* Line ID for the interrupt */ + u32 local_int_id; + /* Local interrupt ID for interrupt line for incoming interrupts */ + u32 remote_int_id; + /* Remote interrupt ID for interrupt line for outgoing interrupts */ +}; + +/* Defines the structure of event entry within the event chart. + * Each entry contains occured event-specific information. + * Used to flag a remote event and determine if a local event has been + * flagged. This struct is placed in shared memory. */ +struct notify_ducatidrv_event_entry { + VOLATILE u32 flag; + /* Flag indicating whether event is set */ + VOLATILE u32 payload; + /* Payload associated with event */ + VOLATILE u32 reserved; + /* Reserved field */ + /* Padding for cache line alignment */ +}; + +/* Defines the NotifyDriverShm control structure, which contains all + * information for one processor. This structure is shared between the + * two processors. */ +struct notify_ducatidrv_proc_ctrl { + VOLATILE u32 recv_init_status; + /* Initialization status for receiving events */ + VOLATILE u32 send_init_status; + /* Initialization status for sending events */ + VOLATILE u32 event_reg_mask; + /* Event Registered mask */ + VOLATILE u32 event_enable_mask; + /* Event Enabled mask */ +}; + + +/* Function to get the default configuration for the notify_ducati driver + * module. */ +void notify_ducatidrv_get_config(struct notify_ducatidrv_config *cfg); + +/* Function to setup the notify ducati driver with the given configuration*/ +int notify_ducatidrv_setup(struct notify_ducatidrv_config *cfg); + +/* Function to destroy the notify ducati driver */ +int notify_ducatidrv_destroy(void); + +/*Function to initialize the given parameters */ +void notify_ducatidrv_params_init(struct notify_ducatidrv_params *params); + +/* Function to create the ducati driver handle and performs initialization. */ +struct notify_ducatidrv_object *notify_ducatidrv_create( + const struct notify_ducatidrv_params *params); + +/* Function to delete the ducati driver handle and performs de initialization.*/ +int notify_ducatidrv_delete(struct notify_ducatidrv_object **handle); + +/* Get the shared memory requirements for the notify ducati driver. */ +uint notify_ducatidrv_shared_mem_req( + const struct notify_ducatidrv_params *params); + + +/* Register a callback for an event with the Notify driver. */ +int notify_ducatidrv_register_event(struct notify_driver_object *handle, + u32 event_id); + +/* Unregister a callback for an event with the Notify driver. */ +int notify_ducatidrv_unregister_event(struct notify_driver_object *handle, + u32 event_id); + +/* Send a notification event to the registered users for this + notification on the specified processor. */ +int notify_ducatidrv_send_event(struct notify_driver_object *handle, + u32 event_id, u32 payload, bool wait_clear); + +/* Disable all events for this Notify driver. */ +int notify_ducatidrv_disable(struct notify_driver_object *handle); + +/* Restore the Notify driver to the state before the last disable was called. */ +void notify_ducatidrv_enable(struct notify_driver_object *handle); + +/* Disable a specific event for this Notify driver. */ +void notify_ducatidrv_disable_event(struct notify_driver_object *handle, + u32 event_id); + +/* Enable a specific event for this Notify driver. */ +void notify_ducatidrv_enable_event(struct notify_driver_object *handle, + u32 event_id); + + +#endif /* !defined NOTIFY_SHMDRIVER_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/notify_ioctl.h b/arch/arm/plat-omap/include/syslink/notify_ioctl.h new file mode 100644 index 000000000000..9d1dcadd4ba3 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_ioctl.h @@ -0,0 +1,278 @@ +/* + * notify_driverdefs.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined(_NOTIFY_IOCTL_H_) +#define _NOTIFY_IOCTL_H_ + +/* Linux headers */ +#include <linux/ioctl.h> + +/* Utilities headers */ +#include <syslink/host_os.h> + +/* Module headers */ +#include <ipc_ioctl.h> +#include <syslink/notify.h> +#include <syslink/notify_ducatidriver.h> +#include <syslink/notifydefs.h> + + +enum CMD_NOTIFY { + NOTIFY_GETCONFIG = NOTIFY_BASE_CMD, + NOTIFY_SETUP, + NOTIFY_DESTROY, + NOTIFY_REGISTEREVENT, + NOTIFY_UNREGISTEREVENT, + NOTIFY_SENDEVENT, + NOTIFY_DISABLE, + NOTIFY_RESTORE, + NOTIFY_DISABLEEVENT, + NOTIFY_ENABLEEVENT, + NOTIFY_ATTACH, + NOTIFY_DETACH, + NOTIFY_THREADATTACH, + NOTIFY_THREADDETACH, + NOTIFY_ISREGISTERED, + NOTIFY_SHAREDMEMREQ, + NOTIFY_REGISTEREVENTSINGLE, + NOTIFY_UNREGISTEREVENTSINGLE +}; + +/* Command for notify_get_config */ +#define CMD_NOTIFY_GETCONFIG _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_GETCONFIG, \ + struct notify_cmd_args_get_config) + +/* Command for notify_setup */ +#define CMD_NOTIFY_SETUP _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_SETUP, \ + struct notify_cmd_args_setup) + +/* Command for notify_destroy */ +#define CMD_NOTIFY_DESTROY _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_DESTROY, \ + struct notify_cmd_args_destroy) + +/* Command for notify_register_event */ +#define CMD_NOTIFY_REGISTEREVENT _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_REGISTEREVENT, \ + struct notify_cmd_args_register_event) + +/* Command for notify_unregister_event */ +#define CMD_NOTIFY_UNREGISTEREVENT _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_UNREGISTEREVENT, \ + struct notify_cmd_args_unregister_event) + +/* Command for notify_send_event */ +#define CMD_NOTIFY_SENDEVENT _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_SENDEVENT, \ + struct notify_cmd_args_send_event) +/* Command for notify_disable */ +#define CMD_NOTIFY_DISABLE _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_DISABLE, \ + struct notify_cmd_args_disable) + +/* Command for notify_restore */ +#define CMD_NOTIFY_RESTORE _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_RESTORE, \ + struct notify_cmd_args_restore) + +/* Command for notify_disable_event */ +#define CMD_NOTIFY_DISABLEEVENT _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_DISABLEEVENT, \ + struct notify_cmd_args_disable_event) + +/* Command for notify_enable_event */ +#define CMD_NOTIFY_ENABLEEVENT _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_ENABLEEVENT, \ + struct notify_cmd_args_enable_event) + +/* Command for notify_attach */ +#define CMD_NOTIFY_ATTACH _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_ATTACH, \ + struct notify_cmd_args_attach) + +/* Command for notify_detach */ +#define CMD_NOTIFY_DETACH _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_DETACH, \ + struct notify_cmd_args_detach) + +/* Command for notify_thread_attach */ +#define CMD_NOTIFY_THREADATTACH _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_THREADATTACH, \ + struct notify_cmd_args) + +/* Command for notify_thread_detach */ +#define CMD_NOTIFY_THREADDETACH _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_THREADDETACH, \ + struct notify_cmd_args) + +/* Command for notify_is_registered */ +#define CMD_NOTIFY_ISREGISTERED _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_ISREGISTERED, \ + struct notify_cmd_args_is_registered) + +/* Command for notify_shared_mem_req */ +#define CMD_NOTIFY_SHAREDMEMREQ _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_SHAREDMEMREQ, \ + struct notify_cmd_args_shared_mem_req) +/* Command for notify_register_event_single */ +#define CMD_NOTIFY_REGISTEREVENTSINGLE _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_REGISTEREVENTSINGLE, \ + struct notify_cmd_args_register_event) + +/* Command for notify_unregister_event_single */ +#define CMD_NOTIFY_UNREGISTEREVENTSINGLE _IOWR(IPC_IOC_MAGIC, \ + NOTIFY_UNREGISTEREVENTSINGLE, \ + struct notify_cmd_args_unregister_event) + + +/*Structure of Event Packet read from notify kernel-side..*/ +struct notify_drv_event_packet { + struct list_head element; + u32 pid; + u32 proc_id; + u32 event_id; + u16 line_id; + u32 data; + notify_fn_notify_cbck func; + void *param; + bool is_exit; +}; + +/* Common arguments for all ioctl commands */ +struct notify_cmd_args { + int api_status; +}; + +/* Command arguments for notify_get_config */ +struct notify_cmd_args_get_config { + struct notify_cmd_args common_args; + struct notify_config *cfg; +}; + +/* Command arguments for notify_setup */ +struct notify_cmd_args_setup { + struct notify_cmd_args common_args; + struct notify_config *cfg; +}; + +/* Command arguments for notify_destroy */ +struct notify_cmd_args_destroy { + struct notify_cmd_args common_args; +}; + +/* Command arguments for notify_attach */ +struct notify_cmd_args_attach { + struct notify_cmd_args common_args; + u16 proc_id; + void *shared_addr; +}; + +/* Command arguments for notify_detach */ +struct notify_cmd_args_detach { + struct notify_cmd_args common_args; + u16 proc_id; +}; + +/* Command arguments for notify_cmd_args_shared_mem_req */ +struct notify_cmd_args_shared_mem_req { + struct notify_cmd_args common_args; + u16 proc_id; + void *shared_addr; + uint shared_mem_size; +}; + +/* Command arguments for notify_cmd_args_is_registered */ +struct notify_cmd_args_is_registered { + struct notify_cmd_args common_args; + u16 proc_id; + u16 line_id; + bool is_registered; +}; + +/* Command arguments for notify_register_event */ +struct notify_cmd_args_register_event { + struct notify_cmd_args common_args; + u16 proc_id; + u16 line_id; + u32 event_id; + notify_fn_notify_cbck fn_notify_cbck; + uint *cbck_arg; + u32 pid; +}; + +/* Command arguments for notify_unregister_event */ +struct notify_cmd_args_unregister_event { + struct notify_cmd_args common_args; + u16 proc_id; + u16 line_id; + u32 event_id; + notify_fn_notify_cbck fn_notify_cbck; + uint *cbck_arg; + u32 pid; +}; + +/* Command arguments for notify_send_event */ +struct notify_cmd_args_send_event { + struct notify_cmd_args common_args; + u16 proc_id; + u16 line_id; + u32 event_id; + u32 payload; + bool wait_clear; +}; + +/* Command arguments for notify_disable */ +struct notify_cmd_args_disable { + struct notify_cmd_args common_args; + u16 proc_id; + u16 line_id; + u32 flags; +}; + +/* Command arguments for notify_restore */ +struct notify_cmd_args_restore { + struct notify_cmd_args common_args; + u32 key; + u16 proc_id; + u16 line_id; +}; + +/* Command arguments for notify_disable_event */ +struct notify_cmd_args_disable_event { + struct notify_cmd_args common_args; + u16 proc_id; + u16 line_id; + u32 event_id; +}; + +/* Command arguments for notify_enable_event */ +struct notify_cmd_args_enable_event { + struct notify_cmd_args common_args; + u16 proc_id; + u16 line_id; + u32 event_id; +}; + +/* Command arguments for notify_exit */ +struct notify_cmd_args_exit { + struct notify_cmd_args common_args; +}; + + +#endif /* !defined(_NOTIFY_IOCTL_H_) */ diff --git a/arch/arm/plat-omap/include/syslink/notify_setup_proxy.h b/arch/arm/plat-omap/include/syslink/notify_setup_proxy.h new file mode 100644 index 000000000000..383b3150a7d7 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_setup_proxy.h @@ -0,0 +1,53 @@ +/* + * notify_setup_proxy.h + * + * Proxy to connect notify setup to device specific implementation + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#if !defined(_NOTIFYSETUPPROXY_H_0x5f84) +#define _NOTIFYSETUPPROXY_H_0x5f84 + +#if defined(CONFIG_ARCH_OMAP4) +/* Function that will be called in Notify_attach */ +extern int notify_setup_omap4_attach(u16 proc_id, void *shared_addr); +#define notify_setup_proxy_attach(proc_id, shared_addr) \ + notify_setup_omap4_attach(proc_id, shared_addr) + +/* Function that will be called in notify_stop */ +extern int notify_setup_omap4_detach(u16 proc_id); +#define notify_setup_proxy_detach notify_setup_omap4_detach + +/* Shared Memory Required for notify setup */ +extern uint notify_setup_omap4_shared_mem_req(u16 proc_id, void *shared_addr); +#define notify_setup_proxy_shared_mem_req(proc_id, shared_addr) \ + notify_setup_omap4_shared_mem_req(proc_id, shared_addr) + +/* Is interrupt line available? */ +extern bool notify_setup_omap4_int_line_available(u16 remote_proc_id); +#define notify_setup_proxy_int_line_available(remote_proc_id) \ + notify_setup_omap4_int_line_available(remote_proc_id) +#else +/* Function that will be called in Notify_attach */ +#define notify_setup_proxy_attach(proc_id, shared_addr) + +/* Function that will be called in notify_stop */ +#define notify_setup_proxy_detach + +/* Shared Memory Required for notify setup */ +#define notify_setup_proxy_shared_mem_req(proc_id, shared_addr) + +/* Is interrupt line available? */ +#define notify_setup_proxy_int_line_available(remote_proc_id) +#endif /* if defined (SYSLINK_PLATFORM_OMAPL1XX) */ + +#endif /* !defined(_NOTIFYSETUPPROXY_H_0x5f84) */ diff --git a/arch/arm/plat-omap/include/syslink/notifydefs.h b/arch/arm/plat-omap/include/syslink/notifydefs.h new file mode 100644 index 000000000000..b0df5d536168 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notifydefs.h @@ -0,0 +1,92 @@ +/* + * notifydefs.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined(_NOTIFYDEFS_H_) +#define _NOTIFYDEFS_H_ + +/* Linux headers */ +#include <linux/list.h> + +/* Osal And Utils headers */ +#include <syslink/atomic_linux.h> + +/* Module headers */ +#include <syslink/notify.h> +#include <syslink/_notify.h> +#include <syslink/notify_driverdefs.h> + + +/*Macro to make a correct module magic number with ref Count */ +#define NOTIFY_MAKE_MAGICSTAMP(x) ((NOTIFY_MODULEID << 12u) | (x)) + +/* Maximum number of Notify drivers supported. */ +#define NOTIFY_MAX_DRIVERS 4u + +/* Mask to check for system key. */ +#define NOTIFY_SYSTEMKEY_MASK ((u16)0xFFFF0000) + + +/* Defines the Event callback information instance */ +struct notify_event_callback { + notify_fn_notify_cbck fn_notify_cbck; + /* Callback function pointer */ + uint *cbck_arg; + /* Argument associated with callback function */ +}; + +/* Defines the Notify state object, which contains all the module + * specific information. */ +struct notify_module_object { + atomic_t ref_count; + /* Reference count */ + struct notify_config cfg; + /* Notify configuration structure */ + struct notify_config def_cfg; + /* Default module configuration */ + struct mutex *gate_handle; + /* Handle of gate to be used for local thread safety */ + struct notify_driver_object + drivers[NOTIFY_MAX_DRIVERS][NOTIFY_MAX_INTLINES]; + /* Array of configured drivers. */ + u32 local_enable_mask; + /* This is used for local/loopback events. Default to enabled (-1) */ + bool start_complete; + /* TRUE if start() was called */ + bool is_setup; + /* Indicates whether the Notify module is setup. */ + struct notify_object *local_notify_handle; + /* Handle to Notify object for local notifications. */ +}; + +/* Defines the Notify instance object. */ +struct notify_object { + uint nesting; + /* Disable/restore nesting */ + void *driver_handle; + /* Handle to device specific driver */ + u16 remote_proc_id; + /* Remote MultiProc id */ + u16 line_id; + /* Interrupt line id */ + struct notify_event_callback callbacks[NOTIFY_MAXEVENTS]; + /* List of event callbacks registered */ + struct list_head event_list[NOTIFY_MAXEVENTS]; + /* List of event listeners registered */ +}; + + +#endif /* !defined (_NOTIFYDEFS_H_) */ diff --git a/arch/arm/plat-omap/include/syslink/notifyerr.h b/arch/arm/plat-omap/include/syslink/notifyerr.h new file mode 100644 index 000000000000..9bbaa238fa3a --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notifyerr.h @@ -0,0 +1,198 @@ +/* + * notifyerr.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined NOTIFYERR_H +#define NOTIFYERR_H + + +/* + * name NOTIFY_SUCCEEDED + * + * desc Check if the provided status code indicates a success code. + * + * arg status + * Status code to be checked + * + * ret TRUE + * If status code indicates success + * FALSE + * If status code indicates failure + * + * enter None. + * + * leave None. + * + * see NOTIFY_FAILED + * + */ +#define NOTIFY_SUCCEEDED(status)\ +(((signed long int) (status) >= (NOTIFY_SBASE)) \ +&& ((signed long int) (status) <= (NOTIFY_SLAST))) + + +/* + * @name NOTIFY_FAILED + * + * @desc Check if the provided status code indicates a failure code. + * + * @arg status + * Status code to be checked + * + * @ret TRUE + * If status code indicates failure + * FALSE + * If status code indicates success + * + * @enter None. + * + * @leave None. + * + * @see NOTIFY_FAILED + * + */ +#define NOTIFY_FAILED(status) (!NOTIFY_SUCCEEDED(status)) + + + +/* + * name NOTIFY_SBASE, NOTIFY_SLAST + * + * desc Defines the base and range for the success codes used by the + * Notify module + * + */ +#define NOTIFY_SBASE (signed long int)0x00002000l +#define NOTIFY_SLAST (signed long int)0x000020FFl + +/* + * name NOTIFY_EBASE, NOTIFY_ELAST + * + * desc Defines the base and range for the failure codes used by the + * Notify module + * + */ +#define NOTIFY_EBASE (signed long int)0x80002000l +#define NOTIFY_ELAST (signed long int)0x800020FFl + + +/* + * SUCCESS Codes + * + */ + +/* Generic success code for Notify module */ +#define NOTIFY_SOK (NOTIFY_SBASE + 0x01l) + +/* Indicates that the Notify module (or driver) has already been initialized + * by another client, and this process has now successfully acquired the right + * to use the Notify module. + */ +#define NOTIFY_SALREADYINIT (NOTIFY_SBASE + 0x02l) + +/* Indicates that the Notify module (or driver) is now being finalized, since + * the calling client is the last one finalizing the module, and all open + * handles to it have been closed. + */ +#define NOTIFY_SEXIT (NOTIFY_SBASE + 0x03l) + + +/* + * FAILURE Codes + * + */ + +/* Generic failure code for Notify module */ +#define NOTIFY_EFAIL (NOTIFY_EBASE + 0x01l) + +/* This failure code indicates that an operation has timed out. */ +#define NOTIFY_ETIMEOUT (NOTIFY_EBASE + 0x02l) + +/* This failure code indicates a configuration error */ +#define NOTIFY_ECONFIG (NOTIFY_EBASE + 0x03l) + +/* This failure code indicates that the Notify module has already been + * initialized from the calling client (process). + */ +#define NOTIFY_EALREADYINIT (NOTIFY_EBASE + 0x04l) + +/* This failure code indicates that the specified entity was not found + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_ENOTFOUND (NOTIFY_EBASE + 0x05l) + +/* This failure code indicates that the specified feature is not supported + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_ENOTSUPPORTED (NOTIFY_EBASE + 0x06l) + +/* This failure code indicates that the specified event number is + * not supported + */ +#define NOTIFY_EINVALIDEVENT (NOTIFY_EBASE + 0x07l) + +/* This failure code indicates that the specified pointer is invalid */ +#define NOTIFY_EPOINTER (NOTIFY_EBASE + 0x08l) + +/* This failure code indicates that a provided parameter was outside its valid + * range. + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_ERANGE (NOTIFY_EBASE + 0x09l) + +/* This failure code indicates that the specified handle is invalid */ +#define NOTIFY_EHANDLE (NOTIFY_EBASE + 0x0Al) + +/* This failure code indicates that an invalid argument was specified */ +#define NOTIFY_EINVALIDARG (NOTIFY_EBASE + 0x0Bl) + +/* This failure code indicates a memory related failure */ +#define NOTIFY_EMEMORY (NOTIFY_EBASE + 0x0Cl) + +/* This failure code indicates that the Notify module has not been initialized*/ +#define NOTIFY_EINIT (NOTIFY_EBASE + 0x0Dl) + +/* This failure code indicates that a resource was not available. + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_ERESOURCE (NOTIFY_EBASE + 0x0El) + +/* This failure code indicates that there was an attempt to register for a + * reserved event. + */ +#define NOTIFY_ERESERVEDEVENT (NOTIFY_EBASE + 0x0Fl) + +/* This failure code indicates that the specified entity already exists. + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_EALREADYEXISTS (NOTIFY_EBASE + 0x10l) + +/* This failure code indicates that the Notify driver has not been fully + * initialized + */ +#define NOTIFY_EDRIVERINIT (NOTIFY_EBASE + 0x11l) + +/* This failure code indicates that the other side is not ready to receive + * notifications. + */ +#define NOTIFY_ENOTREADY (NOTIFY_EBASE + 0x12l) + +#endif /* !defined (NOTIFYERR_H) */ diff --git a/arch/arm/plat-omap/include/syslink/platform.h b/arch/arm/plat-omap/include/syslink/platform.h new file mode 100644 index 000000000000..9dbae5cf1521 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/platform.h @@ -0,0 +1,44 @@ +/* + * platform.h + * + * Defines the platform functions to be used by SysMgr module. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ + +#define PLATFORM_S_SUCCESS 0 +#define PLATFORM_E_FAIL -1 +#define PLATFORM_E_INVALIDARG -2 + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Function to setup the platform */ +s32 platform_setup(void); + +/* Function to destroy the platform */ +s32 platform_destroy(void); + +/* Function called when slave is loaded with executable */ +int platform_load_callback(u16 proc_id, void *arg); + +/* Function called when slave is in started state*/ +int platform_start_callback(u16 proc_id, void *arg); + +/* Function called when slave is stopped state */ +int platform_stop_callback(u16 proc_id, void *arg); + +#endif /* ifndef _PLATFORM_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/platform_mem.h b/arch/arm/plat-omap/include/syslink/platform_mem.h new file mode 100644 index 000000000000..874a1153fc21 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/platform_mem.h @@ -0,0 +1,137 @@ +/* + * platform_mem.c + * + * Target memory management interface implementation. + * + * This abstracts the Memory management interface in the kernel + * code. Allocation, Freeing-up, copy and address translate are + * supported for the kernel memory management. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _PLATFORM_MEM_H_ +#define _PLATFORM_MEM_H_ + +#include <linux/types.h> + +/* + * MEMORYOS_MODULEID + * Module ID for platform mem module + */ +#define PLATFORM_MEM_MODULEID (u16) 0x97D2 + +/* + * Enumerates the types of caching for memory regions + */ +enum platform_mem_cache_flags { + PLATFORM_MEM_CACHE_FLAGS_DEFAULT = 0x00000000, + /* Default flags - Cached */ + PLATFORM_MEM_CACHE_FLAGS_CACHED = 0x00010000, + /* Cached memory */ + PLATFORM_MEM_CACHE_FLAGS_UNCACHED = 0x00020000, + /* Uncached memory */ + PLATFORM_MEM_CACHE_FLAGS_END_VALUE = 0x00030000 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Enumerates the types of memory allocation + */ +enum platform_mem_mtype_flags{ + PLATFORM_MEM_MTYPE_FLAGS_DEFAULT = 0x00000000, + /* Default flags - virtually contiguous */ + PLATFORM_MEM_MTYPE_FLAGS_PHYSICAL = 0x00000001, + /* Physically contiguous */ + PLATFORM_MEM_MTYPE_FLAGS_DMA = 0x00000002, + /* Physically contiguous */ + PLATFORM_MEM_MTYPE_FLAGS_END_VALUE = 0x00000003 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Enumerates the types of translation + */ +enum memory_xlt_flags{ + PLATFORM_MEM_XLT_FLAGS_VIRT2PHYS = 0x00000000, + /* Virtual to physical */ + PLATFORM_MEM_XLT_FLAGS_PHYS2VIRT = 0x00000001, + /* Virtual to physical */ + PLATFORM_MEM_XLT_FLAGS_END_VALUE = 0x00000002 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Structure containing information required for mapping a + * memory region. + */ +struct platform_mem_map_info { + u32 src; + /* Address to be mapped. */ + u32 size; + /* Size of memory region to be mapped. */ + u32 dst; + /* Mapped address. */ + bool is_cached; + /* Whether the mapping is to a cached area or uncached area. */ + void *drv_handle; + /* Handle to the driver that is implementing the mmap call. Ignored for + Kernel-side version. */ +}; + +/* + * Structure containing information required for unmapping a + * memory region. + */ +struct platform_mem_unmap_info { + u32 addr; + /* Address to be unmapped.*/ + u32 size; + /* Size of memory region to be unmapped.*/ + bool is_cached; + /* Whether the mapping is to a cached area or uncached area. */ +}; + +/* + * Structure containing information required for mapping a + * memory region. + */ +#define memory_map_info struct platform_mem_map_info + +/* + * Structure containing information required for unmapping a + * memory region. + */ +#define memory_unmap_info struct platform_mem_unmap_info + + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Initialize the platform mem module. */ +int platform_mem_setup(void); + +/* Finalize the platform mem module. */ +int platform_mem_destroy(void); + +/* Maps a memory area into virtual space. */ +int platform_mem_map(memory_map_info *map_info); + +/* Unmaps a memory area into virtual space. */ +int platform_mem_unmap(memory_unmap_info *unmap_info); + +/* Translate API */ +void *platform_mem_translate(void *srcAddr, enum memory_xlt_flags flags); + +#endif /* ifndef _PLATFORM_MEM_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/procmgr.h b/arch/arm/plat-omap/include/syslink/procmgr.h new file mode 100644 index 000000000000..4d113c9fa90d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/procmgr.h @@ -0,0 +1,280 @@ +/* + * procmgr.h + * + * Syslink driver support functions for TI OMAP processors. + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef SYSLINK_PROC_MGR_H +#define SYSLINK_PROC_MGR_H + +#include <linux/types.h> +#include <syslink/multiproc.h> + + + +#define PROCMGR_MODULEID 0xf2ba + +/* + * Maximum name length for ProcMgr module strings. + */ +#define PROCMGR_MAX_STRLEN 32 + +/* + * Maximum number of memory regions supported by ProcMgr module. + */ +#define PROCMGR_MAX_MEMORY_REGIONS 32 + +/* + * IS_VALID_PROCID + * Checks if the Processor ID is valid + */ +#define IS_VALID_PROCID(id) (id < MULTIPROC_MAXPROCESSORS) + + +/* + * Enumerations to indicate Processor states. + */ +enum proc_mgr_state { + PROC_MGR_STATE_UNKNOWN = 0, + /* Unknown Processor state (e.g. at startup or error). */ + PROC_MGR_STATE_POWERED = 1, + /* Indicates the Processor is powered up. */ + PROC_MGR_STATE_RESET = 2, + /* Indicates the Processor is reset. */ + PROC_MGR_STATE_LOADED = 3, + /* Indicates the Processor is loaded. */ + PROC_MGR_STATE_RUNNNING = 4, + /* Indicates the Processor is running. */ + PROC_MGR_STATE_UNAVAILABLE = 5, + /* Indicates the Processor is unavailable to the physical transport. */ + PROC_MGR_STATE_ENDVALUE = 6 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Enumerations to indicate different types of slave boot modes. + */ +enum proc_mgr_boot_mode { + PROC_MGR_BOOTMODE_BOOT = 0, + /* ProcMgr is responsible for loading the slave and its reset control */ + PROC_MGR_BOOTMODE_NOLOAD = 1, + /* ProcMgr is not responsible for loading the slave. It is responsible + for reset control of the slave. */ + PROC_MGR_BOOTMODE_NOBOOT = 2, + /* ProcMgr is not responsible for loading or reset control of the slave. + The slave either self-boots, or this is done by some entity outside of + the ProcMgr module. */ + PROC_MGR_BOOTMODE_ENDVALUE = 3 + /* End delimiter indicating start of invalid values for this enum */ +} ; + +/* + * Enumerations to indicate address types used for translation + */ +enum proc_mgr_addr_type{ + PROC_MGR_ADDRTYPE_MASTERKNLVIRT = 0, + /* Kernel Virtual address on master processor */ + PROC_MGR_ADDRTYPE_MASTERUSRVIRT = 1, + /* User Virtual address on master processor */ + PROC_MGR_ADDRTYPE_SLAVEVIRT = 2, + /* Virtual address on slave processor */ + PROC_MGR_ADDRTYPE_ENDVALUE = 3 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Enumerations to indicate types of address mapping + */ +enum proc_mgr_map_type { + PROC_MGR_MAPTYPE_VIRT = 0, + /* Map/unmap to virtual address space (kernel/user) */ + PROC_MGR_MAPTYPE_SLAVE = 1, + /* Map/unmap to slave address space */ + PROC_MGR_MAPTYPE_ENDVALUE = 2 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Module configuration structure. + */ +struct proc_mgr_config { + void *gate_handle; +} ; + +/* + * Configuration parameters specific to the slave ProcMgr instance. + */ +struct proc_mgr_params { + void *proc_handle; + /* void * to the Processor object associated with this ProcMgr. */ + void *loader_handle; + /*!< Handle to the Loader object associated with this ProcMgr. */ + void *pwr_handle; + /*!< Handle to the PwrMgr object associated with this ProcMgr. */ +}; + +/* + * Configuration parameters specific to the slave ProcMgr instance. + */ +struct proc_mgr_attach_params { + enum proc_mgr_boot_mode boot_mode; + /* Boot mode for the slave processor. */ +} ; + +/* + * Configuration parameters to be provided while starting the slave + * processor. + */ +struct proc_mgr_start_params { + u32 proc_id; +}; + +/* + * Configuration parameters to be provided while stopping the slave + * processor. + */ +struct proc_mgr_stop_params { + u32 proc_id; +}; + +/* + * This structure defines information about memory regions mapped by + * the ProcMgr module. + */ +struct proc_mgr_addr_info { +/* bool is_init; */ + unsigned short is_init; + /* Is this memory region initialized? */ + u32 addr[PROC_MGR_ADDRTYPE_ENDVALUE]; + /* Addresses for each type of address space */ + u32 size; + /* Size of the memory region in bytes */ +}; + +/* + * Characteristics of the slave processor + */ +struct proc_mgr_proc_info { + enum proc_mgr_boot_mode boot_mode; + /* Boot mode of the processor. */ + u16 num_mem_entries; + /* Number of valid memory entries */ + struct proc_mgr_addr_info mem_entries[PROCMGR_MAX_MEMORY_REGIONS]; + /* Configuration of memory regions */ +}; + + +/* + * Function pointer type that is passed to the proc_mgr_registerNotify function +*/ +typedef int (*proc_mgr_callback_fxn)(u16 proc_id, void *handle, + enum proc_mgr_state from_state, enum proc_mgr_state to_state); + +/* Function to get the default configuration for the ProcMgr module. */ +void proc_mgr_get_config(struct proc_mgr_config *cfg); + +/* Function to setup the ProcMgr module. */ +int proc_mgr_setup(struct proc_mgr_config *cfg); + +/* Function to destroy the ProcMgr module. */ +int proc_mgr_destroy(void); + +/* Function to initialize the parameters for the ProcMgr instance. */ +void proc_mgr_params_init(void *handle, struct proc_mgr_params *params); + +/* Function to create a ProcMgr object for a specific slave processor. */ +void *proc_mgr_create(u16 proc_id, const struct proc_mgr_params *params); + +/* Function to delete a ProcMgr object for a specific slave processor. */ +int proc_mgr_delete(void **handle_ptr); + +/* Function to open a handle to an existing ProcMgr object handling the + * proc_id. + */ +int proc_mgr_open(void **handle, u16 proc_id); + +/* Function to close this handle to the ProcMgr instance. */ +int proc_mgr_close(void *handle); + +/* Function to initialize the parameters for the ProcMgr attach function. */ +void proc_mgr_get_attach_params(void *handle, + struct proc_mgr_attach_params *params); + +/* Function to attach the client to the specified slave and also initialize the + * slave(if required). + */ +int proc_mgr_attach(void *handle, struct proc_mgr_attach_params *params); + +/* Function to detach the client from the specified slave and also finalze the + * slave(if required). + */ +int proc_mgr_detach(void *handle); + +/* Function to initialize the parameters for the ProcMgr start function. */ +void proc_mgr_get_start_params(void *handle, + struct proc_mgr_start_params *params); + +/* Function to starts execution of the loaded code on the slave from the + * starting point specified in the slave executable loaded earlier by call to + * proc_mgr_load(). + */ +int proc_mgr_start(void *handle, u32 entry_point, + struct proc_mgr_start_params *params); + +/* Function to stop execution of the slave Processor. */ +int proc_mgr_stop(void *handle, struct proc_mgr_stop_params *params); + +/* Function to get the current state of the slave Processor as maintained on + * the master Processor state machine. + */ +enum proc_mgr_state proc_mgr_get_state(void *handle); + +/* Function to read from the slave Processor's memory space. */ +int proc_mgr_read(void *handle, u32 proc_addr, u32 *num_bytes, + void *buffer); + +/* Function to read from the slave Processor's memory space. */ +int proc_mgr_write(void *handle, u32 proc_addr, u32 *num_bytes, void *buffer); + +/* Function that provides a hook for performing device dependent operations on + * the slave Processor. + */ +int proc_mgr_control(void *handle, int cmd, void *arg); + +int proc_mgr_translate_addr(void *handle, void **dst_addr, + enum proc_mgr_addr_type dst_addr_type, void *src_addr, + enum proc_mgr_addr_type src_addr_type); + +/* Function that maps the specified slave address to master address space. */ +int proc_mgr_map(void *handle, u32 proc_addr, u32 size, + u32 *mappedAddr, u32 *mapped_size, u32 map_attribs); + +/* Function that unmaps the specified slave address to master address space. */ +int proc_mgr_unmap(void *handle, u32 mapped_addr); + +/* Function that registers for notification when the slave processor + * transitions to any of the states specified. + */ +int proc_mgr_register_notify(void *handle, proc_mgr_callback_fxn fxn, + void *args, enum proc_mgr_state state[]); + +/* Function that returns information about the characteristics of the slave + * processor. + */ +int proc_mgr_get_proc_info(void *handle, struct proc_mgr_proc_info *proc_info); + +/* Function that returns virtual to physical translations + */ +int proc_mgr_virt_to_phys(void *handle, u32 da, u32 *mapped_entries, + u32 num_of_entries); + +#endif diff --git a/arch/arm/plat-omap/include/syslink/sharedregion.h b/arch/arm/plat-omap/include/syslink/sharedregion.h new file mode 100644 index 000000000000..ca644e7ebcdc --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sharedregion.h @@ -0,0 +1,244 @@ +/* + * sharedregion.h + * + * The SharedRegion module is designed to be used in a + * multi-processor environment where there are memory regions + * that are shared and accessed across different processors + * + * Copyright (C) 2008-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SHAREDREGION_H_ +#define _SHAREDREGION_H_ + +#include <linux/types.h> +#include <heapmemmp.h> + +/* + * SHAREDREGION_MODULEID + * Module ID for Shared region manager + */ +#define SHAREDREGION_MODULEID (0x5D8A) + +/* + * Name of the reserved nameserver used for application + */ +#define SHAREDREGION_NAMESERVER "SHAREDREGION" + +/* + * Name of the reserved nameserver used for application + */ +#define SHAREDREGION_INVALIDREGIONID ((u16)(~0)) + +/*! + * @def SharedRegion_DEFAULTOWNERID + * @brief Default owner processor id + */ +#define SHAREDREGION_DEFAULTOWNERID ((u16)(~0)) + +/* + * Name of the reserved nameserver used for application + */ +#define SHAREDREGION_INVALIDSRPTR ((u32 *)(~0)) + + +struct sharedregion_entry { + /* The base address of the region */ + void *base; + /* The length of the region */ + uint len; + /* The MultiProc id of the owner of the region */ + u16 owner_proc_id; + /* Whether the region is valid */ + bool is_valid; + /* Whether to perform cache operations for the region */ + bool cache_enable; + /* The cache line size of the region */ + uint cache_line_size; + /* Whether a heap is created for the region */ + bool create_heap; + /* The name of the region */ + char *name; +}; + +/* + * Module configuration structure + */ +struct sharedregion_config { + uint cache_line_size; + /* + * Worst-case cache line size + * + * This is the default system cache line size for all modules. + * When a module puts structures in shared memory, this value is + * used to make sure items are aligned on a cache line boundary. + * If no cacheLineSize is specified for a region, it will use this + * value. + */ + + u16 num_entries; + /* + * The number of shared region table entries. + * + * This value is used for calculating the number of bits for the offset. + * Note: This value must be the same across all processors in the + * system. Increasing this parameter will increase the footprint + * and the time for translating a pointer to a SRPtr. + */ + + bool translate; + /* + * This configuration parameter should be set to 'true' + * if and only if all shared memory regions are the same + * for all processors. If 'true', it results in a fast + * getPtr and getSRPtr. + */ +}; + +/* + * Information stored on a per region basis + */ +struct sharedregion_region { + struct sharedregion_entry entry; + uint reserved_size; + struct heapmemmp_object *heap; +}; + + +/* + * Function to get the configuration + */ +int sharedregion_get_config(struct sharedregion_config *config); + +/* + * Function to setup the SharedRegion module + */ +int sharedregion_setup(const struct sharedregion_config *config); + +/* + * Function to destroy the SharedRegion module + */ +int sharedregion_destroy(void); + +/* + * Creates a heap by owner of region for each SharedRegion. + * Function is called by ipc_start(). Requires that SharedRegion 0 + * be valid before calling start(). + */ +int sharedregion_start(void); + +/* + * Function to stop Shared Region 0 + */ +int sharedregion_stop(void); + +/* + * Opens a heap, for non-owner processors, for each SharedRegion. + */ +int sharedregion_attach(u16 remote_proc_id); + +/* + * Closes a heap, for non-owner processors, for each SharedRegion. + */ +int sharedregion_detach(u16 remote_proc_id); + +/* + * Reserve shared region memory + */ +void *sharedregion_reserve_memory(u16 id, u32 size); + +/* + * Reserve shared region memory + */ +void sharedregion_unreserve_memory(u16 id, u32 size); + +/* + * Sets the entry at the specified region id(doesn't create heap) + */ +int _sharedregion_set_entry(u16 region_id, struct sharedregion_entry *entry); + +/* + * Function to clear the reserved memory + */ +void sharedregion_clear_reserved_memory(void); + +/* + * Return the region info + */ +void sharedregion_get_region_info(u16 i, struct sharedregion_region *region); + +/* + * Clears the entry at the specified region id + */ +int sharedregion_clear_entry(u16 region_id); + +/* + * Initializes the entry fields + */ +void sharedregion_entry_init(struct sharedregion_entry *entry); + +/* + * Gets the cache line size for the specified region id + */ +uint sharedregion_get_cache_line_size(u16 region_id); + +/* + * Gets the entry information for the specified region id + */ +int sharedregion_get_entry(u16 region_id, struct sharedregion_entry *entry); + +/* + * Gets the heap associated with the specified region id + */ +void *sharedregion_get_heap(u16 region_id); + +/* + * Gets the region id for the specified address + */ +u16 sharedregion_get_id(void *addr); + +/* + * Gets the id of a region, given the name + */ +u16 sharedregion_get_id_by_name(char *name); + +/* + * Gets the number of regions + */ +u16 sharedregion_get_num_regions(void); + +/* + * Returns the address pointer associated with the shared region pointer + */ +void *sharedregion_get_ptr(u32 *srptr); + +/* + * Returns the shared region pointer + */ +u32 *sharedregion_get_srptr(void *addr, u16 index); + +/* + * whether cache enable was specified + */ +bool sharedregion_is_cache_enabled(u16 region_id); + +/* + * Sets the entry at the specified region id + */ +int sharedregion_set_entry(u16 region_id, struct sharedregion_entry *entry); + +/* + * Whether address translation is enabled + */ +bool sharedregion_translate_enabled(void); + +#endif /* _SHAREDREGION_H */ diff --git a/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h b/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h new file mode 100644 index 000000000000..4d45df002046 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h @@ -0,0 +1,189 @@ +/* + * sharedregion_ioctl.h + * + * The sharedregion module is designed to be used in a + * multi-processor environment where there are memory regions + * that are shared and accessed across different processors + * + * Copyright (C) 2008-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SHAREDREGION_IOCTL_H +#define _SHAREDREGION_IOCTL_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <sharedregion.h> + +enum CMD_SHAREDREGION { + SHAREDREGION_GETCONFIG = SHAREDREGION_BASE_CMD, + SHAREDREGION_SETUP, + SHAREDREGION_DESTROY, + SHAREDREGION_START, + SHAREDREGION_STOP, + SHAREDREGION_ATTACH, + SHAREDREGION_DETACH, + SHAREDREGION_GETHEAP, + SHAREDREGION_CLEARENTRY, + SHAREDREGION_SETENTRY, + SHAREDREGION_RESERVEMEMORY, + SHAREDREGION_CLEARRESERVEDMEMORY, + SHAREDREGION_GETREGIONINFO +}; + +/* + * IOCTL command IDs for sharedregion + * + */ + +/* + * Command for sharedregion_get_config + */ +#define CMD_SHAREDREGION_GETCONFIG _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_GETCONFIG, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_setup + */ +#define CMD_SHAREDREGION_SETUP _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_SETUP, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_setup + */ +#define CMD_SHAREDREGION_DESTROY _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_DESTROY, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_start + */ +#define CMD_SHAREDREGION_START _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_START, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_stop + */ +#define CMD_SHAREDREGION_STOP _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_STOP, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_attach + */ +#define CMD_SHAREDREGION_ATTACH _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_ATTACH, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_detach + */ +#define CMD_SHAREDREGION_DETACH _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_DETACH, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_get_heap + */ +#define CMD_SHAREDREGION_GETHEAP _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_GETHEAP, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_clear_entry + */ +#define CMD_SHAREDREGION_CLEARENTRY _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_CLEARENTRY, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_set_entry + */ +#define CMD_SHAREDREGION_SETENTRY _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_SETENTRY, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_reserve_memory + */ +#define CMD_SHAREDREGION_RESERVEMEMORY _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_RESERVEMEMORY, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_clear_reserved_memory + */ +#define CMD_SHAREDREGION_CLEARRESERVEDMEMORY \ + _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_CLEARRESERVEDMEMORY, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_get_region_info + */ +#define CMD_SHAREDREGION_GETREGIONINFO _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_GETREGIONINFO, \ + struct sharedregion_cmd_args) + +/* + * Command arguments for sharedregion + */ +union sharedregion_arg { + struct { + struct sharedregion_config *config; + } get_config; + + struct { + struct sharedregion_region *regions; + struct sharedregion_config *config; + } setup; + + struct { + struct sharedregion_region *regions; + } get_region_info; + + struct { + u16 remote_proc_id; + } attach; + + struct { + u16 remote_proc_id; + } detach; + + struct { + u16 id; + void *heap_handle; + } get_heap; + + struct { + u16 id; + struct sharedregion_entry entry; + } set_entry; + + struct { + u16 id; + } clear_entry; + + struct { + u16 id; + u32 size; + } reserve_memory; +}; + +/* + * Command arguments for sharedregion + */ +struct sharedregion_cmd_args { + union sharedregion_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for sharedregion module + */ +int sharedregion_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _SHAREDREGION_IOCTL_H */ diff --git a/arch/arm/plat-omap/include/syslink/sysipc_ioctl.h b/arch/arm/plat-omap/include/syslink/sysipc_ioctl.h new file mode 100644 index 000000000000..d5896c21c96d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sysipc_ioctl.h @@ -0,0 +1,118 @@ +/* + * sysipc_ioctl.h + * + * Definitions of sysmgr driver types and structures.. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SYSIPC_IOCTL_H_ +#define _SYSIPC_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <ipc.h> + + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for sysmgr + * ---------------------------------------------------------------------------- + */ +/* IOC Magic Number for sysmgr */ +#define SYSIPC_IOC_MAGIC IPC_IOC_MAGIC + +/* IOCTL command numbers for ipc/sysipc */ +enum sysipc_drv_cmd { + IPC_SETUP = IPC_BASE_CMD, + IPC_DESTROY, + IPC_CONTROL, + IPC_READCONFIG, + IPC_WRITECONFIG + }; + +/* Command for ipc_setup */ +#define CMD_IPC_SETUP \ + _IOWR(SYSIPC_IOC_MAGIC, IPC_SETUP, \ + struct sysipc_cmd_args) + +/* Command for ipc_destroy */ +#define CMD_IPC_DESTROY \ + _IOWR(SYSIPC_IOC_MAGIC, IPC_DESTROY, \ + struct sysipc_cmd_args) + +/* Command for load callback */ +#define CMD_IPC_CONTROL \ + _IOWR(SYSIPC_IOC_MAGIC, IPC_CONTROL, \ + struct sysipc_cmd_args) + +/* Command for ipc_read_config */ +#define CMD_IPC_READCONFIG \ + _IOWR(SYSIPC_IOC_MAGIC, IPC_READCONFIG, \ + struct sysipc_cmd_args) + +/* Command for ipc_write_config */ +#define CMD_IPC_WRITECONFIG \ + _IOWR(SYSIPC_IOC_MAGIC, IPC_WRITECONFIG, \ + struct sysipc_cmd_args) + + +/* ---------------------------------------------------------------------------- + * Command arguments for sysmgr + * ---------------------------------------------------------------------------- + */ +/* Command arguments for sysmgr */ +struct sysipc_cmd_args { + union { + struct { + u16 proc_id; + s32 cmd_id; + void *arg; + } control; + + struct { + u16 remote_proc_id; + u32 tag; + void *cfg; + u32 size; + } read_config; + + struct { + u16 remote_proc_id; + u32 tag; + void *cfg; + u32 size; + } write_config; + + struct { + struct ipc_config *config; + } setup; + } args; + + s32 api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for sysmgr module + * ---------------------------------------------------------------------------- + */ +/* ioctl interface function for sysmgr */ +int sysipc_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _SYSIPC_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/sysmemmgr.h b/arch/arm/plat-omap/include/syslink/sysmemmgr.h new file mode 100644 index 000000000000..34c3b4182288 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sysmemmgr.h @@ -0,0 +1,179 @@ +/* + * sysmemmgr.h + * + * Manager for the Slave system memory. Slave system level memory is allocated + * through this module. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + + +#ifndef _SYSTEMMEMORYMANAGER_H_ +#define _SYSTEMMEMORYMANAGER_H_ + + +/*! + * @def SYSMEMMGR_MODULEID + * @brief Module identifier for System memory manager. + */ +#define SYSMEMMGR_MODULEID (0xb53d) + +/*! + * @def SYSMEMMGR_STATUSCODEBASE + * @brief Error code base for system memory manager module. + */ +#define SYSMEMMGR_STATUSCODEBASE (SYSMEMMGR_MODULEID << 12u) + +/*! + * @def SYSMEMMGR_MAKE_ERROR + * @brief Macro to make error code. + */ +#define SYSMEMMGR_MAKE_ERROR(x) ((int)(0x80000000 + \ + (SYSMEMMGR_STATUSCODEBASE + \ + (x)))) + +/*! + * @def SYSMEMMGR_MAKE_SUCCESS + * @brief Macro to make success code. + */ +#define SYSMEMMGR_MAKE_SUCCESS(x) (SYSMEMMGR_STATUSCODEBASE + (x)) + +/*! + * @def SYSMEMMGR_E_CREATEALLOCATOR + * @brief Static allocator creation failed. + */ +#define SYSMEMMGR_E_CREATEALLOCATOR SYSMEMMGR_MAKE_ERROR(1) + +/*! + * @def SYSMEMMGR_E_CREATELOCK + * @brief Mutex lock creation failed. + */ +#define SYSMEMMGR_E_CREATELOCK SYSMEMMGR_MAKE_ERROR(2) + +/*! + * @def SYSMEMMGR_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define SYSMEMMGR_E_INVALIDSTATE SYSMEMMGR_MAKE_ERROR(3) + +/*! + * @def SYSMEMMGR_E_INVALIDARG + * @brief Argument passed to a function is invalid. + */ +#define SYSMEMMGR_E_INVALIDARG SYSMEMMGR_MAKE_ERROR(4) + +/*! + * @def SYSMEMMGR_E_BPAFREE + * @brief Freeing to buddy allocator failed. + */ +#define SYSMEMMGR_E_BPAFREE SYSMEMMGR_MAKE_ERROR(5) + +/*! + * @def SYSMEMMGR_E_MEMORY + * @brief Memory allocation failed. + */ +#define SYSMEMMGR_E_MEMORY SYSMEMMGR_MAKE_ERROR(6) + +/*! + * @def SYSMEMMGR_SUCCESS + * @brief Operation successful. + */ +#define SYSMEMMGR_SUCCESS SYSMEMMGR_MAKE_SUCCESS(0) + +/*! + * @def SYSMEMMGR_S_ALREADYSETUP + * @brief Module already initialized. + */ +#define SYSMEMMGR_S_ALREADYSETUP SYSMEMMGR_MAKE_SUCCESS(1) + +/*! + * @def SYSMEMMGR_S_DRVALREADYOPENED + * @brief Internal OS Driver is already opened. + */ +#define SYSMEMMGR_S_DRVALREADYOPENED SYSMEMMGR_MAKE_SUCCESS(2) + +/*! + * @brief Configuration data structure of system memory manager. + */ +struct sysmemmgr_config { + u32 sizeof_valloc; + /* Total size for virtual memory allocation */ + u32 sizeof_palloc; + /* Total size for physical memory allocation */ + u32 static_phys_base_addr; + /* Physical address of static memory region */ + u32 static_virt_base_addr; + /* Virtual address of static memory region */ + u32 static_mem_size; + /* size of static memory region */ + u32 page_size; + /* Page size */ + u32 event_no; + /* Event number to be used */ +}; + +/*! + * @brief Flag used for allocating memory blocks. + */ +enum sysmemmgr_allocflag { + sysmemmgr_allocflag_uncached = 0u, + /* Flag used for allocating uncacheable block */ + sysmemmgr_allocflag_cached = 1u, + /* Flag used for allocating cacheable block */ + sysmemmgr_allocflag_physical = 2u, + /* Flag used for allocating physically contiguous block */ + sysmemmgr_allocflag_virtual = 3u, + /* Flag used for allocating virtually contiguous block */ + sysmemmgr_allocflag_dma = 4u + /* Flag used for allocating DMAable (physically contiguous) block */ +}; + +/*! + * @brief Flag used for translating address. + */ +enum sysmemmgr_xltflag { + sysmemmgr_xltflag_kvirt2phys = 0x0001u, + /* Flag used for converting Kernel virtual address to physical + * address */ + sysmemmgr_xltflag_kvirt2uvirt = 0x0002u, + /* Flag used for converting Kernel virtual address to user virtual + * address */ + sysmemmgr_xltflag_uvirt2phys = 0x0003u, + /* Flag used for converting user virtual address to physical address */ + sysmemmgr_xltflag_uvirt2kvirt = 0x0004u, + /* Flag used for converting user virtual address to Kernel virtual + * address */ + sysmemmgr_xltflag_phys2kvirt = 0x0005u, + /* Flag used for converting physical address to user virtual address */ + sysmemmgr_xltflag_phys2uvirt = 0x0006u + /* Flag used for converting physical address to Kernel virtual + * address */ +}; + + +/* Function prototypes */ +void sysmemmgr_get_config(struct sysmemmgr_config *config); + +int sysmemmgr_setup(struct sysmemmgr_config *params); + +int sysmemmgr_destroy(void); + +int sysmemmgr_attach(u16 slave_id); + +void *sysmemmgr_alloc(u32 size, enum sysmemmgr_allocflag flag); + +int sysmemmgr_free(void *blk, u32 size, enum sysmemmgr_allocflag flag); + +void *sysmemmgr_translate(void *srcAddr, enum sysmemmgr_xltflag flag); + + +#endif /* _SYSTEMMEMORYMANAGER_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h b/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h new file mode 100644 index 000000000000..4b0d99615560 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h @@ -0,0 +1,130 @@ +/* + * sysmemmgr_ioctl.h + * + * Definitions of sysmemmgr driver types and structures.. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SYSMEMMGR_IOCTL_H_ +#define _SYSMEMMGR_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <sysmgr.h> + + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for sysmemmgr + * ---------------------------------------------------------------------------- + */ +/* IOC Magic Number for sysmemmgr */ +#define SYSMEMMGR_IOC_MAGIC IPC_IOC_MAGIC + +/* IOCTL command numbers for sysmemmgr */ +enum sysmemmgr_drv_cmd { + SYSMEMMGR_GETCONFIG = SYSMEMMGR_BASE_CMD, + SYSMEMMGR_SETUP, + SYSMEMMGR_DESTROY, + SYSMEMMGR_ALLOC, + SYSMEMMGR_FREE, + SYSMEMMGR_TRANSLATE +}; + +/* Command for sysmemmgr_getConfig */ +#define CMD_SYSMEMMGR_GETCONFIG \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_GETCONFIG, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_setup */ +#define CMD_SYSMEMMGR_SETUP \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_SETUP, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_destroy */ +#define CMD_SYSMEMMGR_DESTROY \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_DESTROY, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_alloc */ +#define CMD_SYSMEMMGR_ALLOC \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_ALLOC, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_free */ +#define CMD_SYSMEMMGR_FREE \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_FREE, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_translate */ +#define CMD_SYSMEMMGR_TRANSLATE \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_TRANSLATE, \ + struct sysmemmgr_cmd_args) + + +/* ---------------------------------------------------------------------------- + * Command arguments for sysmemmgr + * ---------------------------------------------------------------------------- + */ +/* Command arguments for sysmemmgr */ +struct sysmemmgr_cmd_args { + union { + struct { + struct sysmemmgr_config *config; + } get_config; + + struct { + struct sysmemmgr_config *config; + } setup; + + struct { + u32 size; + void *buf; + void *phys; + void *kbuf; + enum sysmemmgr_allocflag flags; + } alloc; + + struct { + u32 size; + void *buf; + void *phys; + void *kbuf; + enum sysmemmgr_allocflag flags; + } free; + + struct { + void *buf; + void *ret_ptr; + enum sysmemmgr_xltflag flags; + } translate; + } args; + + s32 api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for sysmemmgr module + * ---------------------------------------------------------------------------- + */ +/* ioctl interface function for sysmemmgr */ +int sysmemmgr_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* SYSMEMMGR_DRVDEFS_H_0xF414 */ diff --git a/arch/arm/plat-omap/include/syslink/sysmgr.h b/arch/arm/plat-omap/include/syslink/sysmgr.h new file mode 100644 index 000000000000..19fab220b2c4 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sysmgr.h @@ -0,0 +1,182 @@ +/* + * sysmgr.h + * + * Defines for System manager. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SYSMGR_H_ +#define _SYSMGR_H_ + + +/* Module headers */ +#include <multiproc.h> +#include <gatepeterson.h> +#include <sharedregion.h> +#include <listmp.h> +#include <listmp_sharedmemory.h> +#include <messageq.h> +#include <messageq_transportshm.h> +#include <notify.h> +#include <notify_ducatidriver.h> +#include <nameserver.h> +#include <nameserver_remote.h> +#include <nameserver_remotenotify.h> +#include <procmgr.h> +#include <heap.h> +#include <heapbuf.h> +#include <sysmemmgr.h> + + +/*! + * @def SYSMGR_MODULEID + * @brief Unique module ID. + */ +#define SYSMGR_MODULEID (0xF086) + + +/* ============================================================================= + * Module Success and Failure codes + * ============================================================================= + */ +/*! + * @def SYSMGR_STATUSCODEBASE + * @brief Error code base for System manager. + */ +#define SYSMGR_STATUSCODEBASE (SYSMGR_MODULEID << 12u) + +/*! + * @def SYSMGR_MAKE_FAILURE + * @brief Macro to make error code. + */ +#define SYSMGR_MAKE_FAILURE(x) ((s32)(0x80000000 + \ + (SYSMGR_STATUSCODEBASE + \ + (x)))) + +/*! + * @def SYSMGR_MAKE_SUCCESS + * @brief Macro to make success code. + */ +#define SYSMGR_MAKE_SUCCESS(x) (SYSMGR_STATUSCODEBASE + (x)) + +/*! + * @def SYSMGR_E_INVALIDARG + * @brief Argument passed to a function is invalid. + */ +#define SYSMGR_E_INVALIDARG SYSMGR_MAKE_FAILURE(1) + +/*! + * @def SYSMGR_E_MEMORY + * @brief Memory allocation failed. + */ +#define SYSMGR_E_MEMORY SYSMGR_MAKE_FAILURE(2) + +/*! + * @def SYSMGR_E_FAIL + * @brief General failure. + */ +#define SYSMGR_E_FAIL SYSMGR_MAKE_FAILURE(3) + +/*! + * @def SYSMGR_E_INVALIDSTATE + * @brief Module is in invalid state. + */ +#define SYSMGR_E_INVALIDSTATE SYSMGR_MAKE_FAILURE(4) + +/*! + * @def SYSMGR_E_OSFAILURE + * @brief Failure in OS call. + */ +#define SYSMGR_E_OSFAILURE SYSMGR_MAKE_FAILURE(5) + +/*! + * @def SYSMGR_S_ALREADYSETUP + * @brief Module is already initialized. + */ +#define SYSMGR_S_ALREADYSETUP SYSMGR_MAKE_SUCCESS(1) + +/*! + * @def SYSMGR_CMD_SCALABILITY + * @brief Command ID for scalability info. + */ +#define SYSMGR_CMD_SCALABILITY (0x00000000) + +/*! + * @def SYSMGR_CMD_SHAREDREGION_ENTRY_BASE + * @brief Base of command IDs for entries used by Shared region. + */ +#define SYSMGR_CMD_SHAREDREGION_ENTRY_START (0x00000001) +#define SYSMGR_CMD_SHAREDREGION_ENTRY_END (0x00001000) + + +/* ============================================================================= + * Structures & Enums + * ============================================================================= + */ +/*! + * @brief Structure defining config parameters for overall System. + */ +struct sysmgr_config { + struct sysmemmgr_config sysmemmgr_cfg; + /*!< System memory manager config parameter */ + + struct multiproc_config multiproc_cfg; + /*!< Multiproc config parameter */ + + struct gatepeterson_config gatepeterson_cfg; + /*!< Gatepeterson config parameter */ + + struct sharedregion_config sharedregion_cfg; + /*!< SharedRegion config parameter */ + + struct messageq_config messageq_cfg; + /*!< MessageQ config parameter */ + + struct notify_config notify_cfg; + /*!< Notify config parameter */ + + struct proc_mgr_config proc_mgr_cfg; + /*!< Processor manager config parameter */ + + struct heapbuf_config heapbuf_cfg; + /*!< Heap Buf config parameter */ + + struct listmp_config listmp_sharedmemory_cfg; + /*!< ListMPSharedMemory config parameter */ + + struct messageq_transportshm_config messageq_transportshm_cfg; + /*!< MessageQTransportShm config parameter */ + + struct notify_ducatidrv_config notify_ducatidrv_cfg; + /*!< NotifyDriverShm config parameter */ + + struct nameserver_remotenotify_config nameserver_remotenotify_cfg; + /*!< NameServerRemoteNotify config parameter */ +}; + + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Function to initialize the parameter structure */ +void sysmgr_get_config(struct sysmgr_config *config); + +/* Function to initialize sysmgr module */ +s32 sysmgr_setup(const struct sysmgr_config *config); + +/* Function to Finalize sysmgr module */ +s32 sysmgr_destroy(void); + + +#endif /* ifndef SYSMGR_H_0xF086 */ diff --git a/arch/arm/plat-omap/include/syslink/transportshm.h b/arch/arm/plat-omap/include/syslink/transportshm.h new file mode 100644 index 000000000000..02a2b6a80c90 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/transportshm.h @@ -0,0 +1,220 @@ +/* + * transportshm.h + * + * Shared memory based physical transport for + * communication with the remote processor. + * + * This file contains the declarations of types and APIs as part + * of interface of the shared memory transport. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _TRANSPORTSHM_H_ +#define _TRANSPORTSHM_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Utilities headers */ +#include <linux/list.h> + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ +/* Unique module ID. */ +#define TRANSPORTSHM_MODULEID (0x0a7a) + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ +/* Error code base for TransportShm. */ +#define TRANSPORTSHM_STATUSCODEBASE (TRANSPORTSHM_MODULEID << 12) + +/* Macro to make error code. */ +#define TRANSPORTSHM_MAKE_FAILURE(x) ((int) (0x80000000 \ + + (TRANSPORTSHM_STATUSCODEBASE \ + + (x)))) + +/* Macro to make success code. */ +#define TRANSPORTSHM_MAKE_SUCCESS(x) (TRANSPORTSHM_STATUSCODEBASE + (x)) + +/* Argument passed to a function is invalid. */ +#define TRANSPORTSHM_E_INVALIDARG TRANSPORTSHM_MAKE_FAILURE(1) + +/* Invalid shared address size */ +#define TRANSPORTSHM_E_INVALIDSIZE TRANSPORTSHM_MAKE_FAILURE(2) + +/* Module is not initialized. */ +#define TRANSPORTSHM_E_INVALIDSTATE TRANSPORTSHM_MAKE_FAILURE(3) + +/* Versions don't match */ +#define TRANSPORTSHM_E_BADVERSION TRANSPORTSHM_MAKE_FAILURE(4) + +/* General Failure */ +#define TRANSPORTSHM_E_FAIL TRANSPORTSHM_MAKE_FAILURE(5) + +/* Memory allocation failed */ +#define TRANSPORTSHM_E_MEMORY TRANSPORTSHM_MAKE_FAILURE(6) + +/* Failure in OS call. */ +#define TRANSPORTSHM_E_OSFAILURE TRANSPORTSHM_MAKE_FAILURE(7) + +/* Invalid handle specified. */ +#define TRANSPORTSHM_E_HANDLE TRANSPORTSHM_MAKE_FAILURE(8) + +/* The specified operation is not supported. */ +#define TRANSPORTSHM_E_NOTSUPPORTED TRANSPORTSHM_MAKE_FAILURE(9) + +/* Operation successful. */ +#define TRANSPORTSHM_SUCCESS TRANSPORTSHM_MAKE_SUCCESS(0) + +/* The MESSAGETRANSPORTSHM module has already been setup in this process. */ +#define TRANSPORTSHM_S_ALREADYSETUP TRANSPORTSHM_MAKE_SUCCESS(1) + + +/* ============================================================================= + * Structures & Enums + * ============================================================================= + */ + +/* + * Structure defining the reason for error function being called + */ +enum transportshm_reason { + TRANSPORTSHM_REASON_FAILEDPUT, + /* Failed to send the message. */ + TRANSPORTSHM_REASON_INTERNALERR, + /* An internal error occurred in the transport */ + TRANSPORTSHM_REASON_PHYSICALERR, + /* An error occurred in the physical link in the transport */ + TRANSPORTSHM_REASON_FAILEDALLOC + /* Failed to allocate a message. */ +}; + +/* + * transport error callback function. + * + * First parameter: Why the error function is being called. + * + * Second parameter: Handle of transport that had the error. NULL denotes + * that it is a system error, not a specific transport. + * + * Third parameter: Pointer to the message. This is only valid for + * #TRANSPORTSHM_REASON_FAILEDPUT. + * + * Fourth parameter: Transport specific information. Refer to individual + * transports for more details. + */ + +/* + * Module configuration structure. + */ +struct transportshm_config { + void (*err_fxn)(enum transportshm_reason reason, + void *handle, + void *msg, + u32 info); + /* Asynchronous error function for the transport module */ +}; + +/* + * Structure defining config parameters for the transport + * instances. + */ +struct transportshm_params { + u32 priority; + /*< Priority of messages supported by this transport */ + void *gate; + /*< Gate used for critical region management of the shared memory */ + void *shared_addr; + /*< Address of the shared memory. The creator must supply the shared + * memory that this will use for maintain shared state information. + */ + u32 notify_event_id; + /*< Notify event number to be used by the transport */ +}; + +/* + * Structure defining Transport status values + */ +enum transportshm_status { + transportshm_status_INIT, + /*< Transport Shm instance has not not completed + * initialization. */ + transportshm_status_UP, + /*< Transport Shm instance is up and functional. */ + transportshm_status_DOWN, + /*< Transport Shm instance is down and not functional. */ + transportshm_status_RESETTING + /*< Transport Shm instance was up at one point and is in + * process of resetting. + */ +}; + + +/* ============================================================================= + * APIs called by applications + * ============================================================================= + */ +/* Function to get the default configuration for the TransportShm + * module. */ +void transportshm_get_config(struct transportshm_config *cfg); + +/* Function to setup the TransportShm module. */ +int transportshm_setup(const struct transportshm_config *cfg); + +/* Function to destroy the TransportShm module. */ +int transportshm_destroy(void); + +/* Get the default parameters for the NotifyShmDriver. */ +void transportshm_params_init(struct transportshm_params *params); + +/* Create an instance of the TransportShm. */ +void *transportshm_create(u16 proc_id, + const struct transportshm_params *params); + +/* Delete an instance of the TransportShm. */ +int transportshm_delete(void **handle_ptr); + +/* Open a created TransportShm instance by address */ +int transportshm_open_by_addr(void *shared_addr, void **handle_ptr); + +/* Close an opened instance */ +int transportshm_close(void **handle_ptr); + +/* Get the shared memory requirements for the TransportShm. */ +u32 transportshm_shared_mem_req(const struct transportshm_params *params); + +/* Set the asynchronous error function for the transport module */ +void transportshm_set_err_fxn(void (*err_fxn)(enum transportshm_reason reason, + void *handle, + void *msg, + u32 info)); + + +/* ============================================================================= + * APIs called internally by TransportShm module. + * ============================================================================= + */ +/* Put msg to remote list */ +int transportshm_put(void *handle, void *msg); + +/* Control Function */ +int transportshm_control(void *handle, u32 cmd, u32 *cmd_arg); + +/* Get current status of the TransportShm */ +enum transportshm_status transportshm_get_status(void *handle); + +#endif /* _TRANSPORTSHM_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/transportshm_setup.h b/arch/arm/plat-omap/include/syslink/transportshm_setup.h new file mode 100644 index 000000000000..99345773dd8f --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/transportshm_setup.h @@ -0,0 +1,47 @@ +/* + * transportshm_setup.h + * + * Shared Memory Transport setup layer + * + * This file contains the declarations of types and APIs as part + * of interface of the shared memory transport. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _TRANSPORTSHM_SETUP_H_ +#define _TRANSPORTSHM_SETUP_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Utilities headers */ +#include <linux/list.h> + +/* ============================================================================= + * APIs called by applications + * ============================================================================= + */ + +/* Function that will be called in messageq_attach */ +int transportshm_setup_attach(u16 remote_proc_id, u32 *shared_addr); + +/* Function that will be called in messageq_detach */ +int transportshm_setup_detach(u16 remote_proc_id); + +/* Function that returns the amount of shared memory required */ +u32 transportshm_setup_shared_mem_req(u32 *shared_addr); + +/* Determines if a transport has been registered to a remote processor */ +bool transportshm_setup_is_registered(u16 remote_proc_id); + +#endif /* _TRANSPORTSHM_SETUP_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/transportshm_setup_proxy.h b/arch/arm/plat-omap/include/syslink/transportshm_setup_proxy.h new file mode 100644 index 000000000000..72eaf400a195 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/transportshm_setup_proxy.h @@ -0,0 +1,48 @@ +/* + * transportshm_setup_proxy.h + * + * Shared Memory Transport setup layer + * + * This file contains the declarations of types and APIs as part + * of interface of the shared memory transport. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _TRANSPORTSHM_SETUP_PROXY_H_ +#define _TRANSPORTSHM_SETUP_PROXY_H_ + +/* Module headers */ +#include <transportshm_setup.h> + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* function that will be called in messageq_attach */ +#define messageq_setup_transport_proxy_attach(remote_proc_id, shared_addr) \ + transportshm_setup_attach(remote_proc_id, \ + shared_addr) + +/* function that will be called in messageq_detach */ +#define messageq_setup_transport_proxy_detach(remote_proc_id) \ + transportshm_setup_detach(remote_proc_id) + +/* Shared memory req function */ +#define messageq_setup_transport_proxy_shared_mem_req(shared_addr) \ + transportshm_setup_shared_mem_req(shared_addr) + +/* is_registered function */ +#define messageq_setup_transport_proxy_is_registered(remote_proc_id) \ + transportshm_setup_is_registered(remote_proc_id) + +#endif /* _TRANSPORTSHM_SETUP_PROXY_H_ */ diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 0e137663349c..bd196a383332 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -25,6 +25,24 @@ #include "iopgtable.h" +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/file.h> +#include <linux/poll.h> + + +#define for_each_iotlb_cr(obj, n, __i, cr) \ + for (__i = 0; \ + (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ + __i++) +#define OMAP_IOMMU_NAME "omap-iommu" + +static atomic_t num_of_iommus; +static struct class *omap_iommu_class; +static dev_t omap_iommu_dev; + + /* accommodate the difference between omap1 and omap2/3 */ static const struct iommu_functions *arch_iommu; @@ -98,12 +116,7 @@ static int iommu_enable(struct iommu *obj) if (!obj) return -EINVAL; - - clk_enable(obj->clk); - err = arch_iommu->enable(obj); - - clk_disable(obj->clk); return err; } @@ -111,12 +124,7 @@ static void iommu_disable(struct iommu *obj) { if (!obj) return; - - clk_enable(obj->clk); - arch_iommu->disable(obj); - - clk_disable(obj->clk); } /* @@ -171,16 +179,12 @@ static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l) l->base = MMU_LOCK_BASE(val); l->vict = MMU_LOCK_VICT(val); - - BUG_ON(l->base != 0); /* Currently no preservation is used */ } static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) { u32 val; - BUG_ON(l->base != 0); /* Currently no preservation is used */ - val = (l->base << MMU_LOCK_BASE_SHIFT); val |= (l->vict << MMU_LOCK_VICT_SHIFT); @@ -214,6 +218,20 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, return arch_iommu->dump_cr(obj, cr, buf); } +/* only used for iotlb iteration in for-loop */ +static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n) +{ + struct cr_regs cr; + struct iotlb_lock l; + + iotlb_lock_get(obj, &l); + l.vict = n; + iotlb_lock_set(obj, &l); + iotlb_read_cr(obj, &cr); + + return cr; +} + /** * load_iotlb_entry - Set an iommu tlb entry * @obj: target iommu @@ -221,7 +239,6 @@ static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, **/ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) { - int i; int err = 0; struct iotlb_lock l; struct cr_regs *cr; @@ -229,40 +246,46 @@ int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) if (!obj || !obj->nr_tlb_entries || !e) return -EINVAL; - clk_enable(obj->clk); - - for (i = 0; i < obj->nr_tlb_entries; i++) { + iotlb_lock_get(obj, &l); + if (l.base == obj->nr_tlb_entries) { + dev_warn(obj->dev, "%s: preserve entries full\n", __func__); + err = -EBUSY; + goto out; + } + if (!e->prsvd) { + int i; struct cr_regs tmp; + for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) + if (!iotlb_cr_valid(&tmp)) + break; + + if (i == obj->nr_tlb_entries) { + dev_dbg(obj->dev, "%s: full: no entry\n", __func__); + err = -EBUSY; + goto out; + } + iotlb_lock_get(obj, &l); - l.vict = i; + } else { + l.vict = l.base; iotlb_lock_set(obj, &l); - iotlb_read_cr(obj, &tmp); - if (!iotlb_cr_valid(&tmp)) - break; - } - - if (i == obj->nr_tlb_entries) { - dev_dbg(obj->dev, "%s: full: no entry\n", __func__); - err = -EBUSY; - goto out; } cr = iotlb_alloc_cr(obj, e); - if (IS_ERR(cr)) { - clk_disable(obj->clk); + if (IS_ERR(cr)) return PTR_ERR(cr); - } iotlb_load_cr(obj, cr); kfree(cr); + if (e->prsvd) + l.base++; /* increment victim for next tlb load */ if (++l.vict == obj->nr_tlb_entries) - l.vict = 0; + l.vict = l.base; iotlb_lock_set(obj, &l); out: - clk_disable(obj->clk); return err; } EXPORT_SYMBOL_GPL(load_iotlb_entry); @@ -276,20 +299,13 @@ EXPORT_SYMBOL_GPL(load_iotlb_entry); **/ void flush_iotlb_page(struct iommu *obj, u32 da) { - struct iotlb_lock l; int i; + struct cr_regs cr; - clk_enable(obj->clk); - - for (i = 0; i < obj->nr_tlb_entries; i++) { - struct cr_regs cr; + for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { u32 start; size_t bytes; - iotlb_lock_get(obj, &l); - l.vict = i; - iotlb_lock_set(obj, &l); - iotlb_read_cr(obj, &cr); if (!iotlb_cr_valid(&cr)) continue; @@ -299,12 +315,9 @@ void flush_iotlb_page(struct iommu *obj, u32 da) if ((start <= da) && (da < start + bytes)) { dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", __func__, start, da, bytes); - iotlb_load_cr(obj, &cr); iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); } } - clk_disable(obj->clk); - if (i == obj->nr_tlb_entries) dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); } @@ -338,18 +351,28 @@ void flush_iotlb_all(struct iommu *obj) { struct iotlb_lock l; - clk_enable(obj->clk); - l.base = 0; l.vict = 0; iotlb_lock_set(obj, &l); - iommu_write_reg(obj, 1, MMU_GFLUSH); - - clk_disable(obj->clk); } EXPORT_SYMBOL_GPL(flush_iotlb_all); +/** + * iommu_set_twl - enable/disable table walking logic + * @obj: target iommu + * @on: enable/disable + * + * Function used to enable/disable TWL. If one wants to work + * exclusively with locked TLB entries and receive notifications + * for TLB miss then call this function to disable TWL. + */ +void iommu_set_twl(struct iommu *obj, bool on) +{ + arch_iommu->set_twl(obj, on); +} +EXPORT_SYMBOL_GPL(iommu_set_twl); + #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) @@ -357,12 +380,7 @@ ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) if (!obj || !buf) return -EINVAL; - clk_enable(obj->clk); - bytes = arch_iommu->dump_ctx(obj, buf, bytes); - - clk_disable(obj->clk); - return bytes; } EXPORT_SYMBOL_GPL(iommu_dump_ctx); @@ -370,29 +388,18 @@ EXPORT_SYMBOL_GPL(iommu_dump_ctx); static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num) { int i; - struct iotlb_lock saved, l; + struct iotlb_lock saved; + struct cr_regs tmp; struct cr_regs *p = crs; - clk_enable(obj->clk); - iotlb_lock_get(obj, &saved); - memcpy(&l, &saved, sizeof(saved)); - - for (i = 0; i < num; i++) { - struct cr_regs tmp; - - iotlb_lock_get(obj, &l); - l.vict = i; - iotlb_lock_set(obj, &l); - iotlb_read_cr(obj, &tmp); + for_each_iotlb_cr(obj, num, i, tmp) { if (!iotlb_cr_valid(&tmp)) continue; - *p++ = tmp; } - iotlb_lock_set(obj, &saved); - clk_disable(obj->clk); + iotlb_lock_set(obj, &saved); return p - crs; } @@ -745,10 +752,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) if (!err) return IRQ_HANDLED; - - clk_enable(obj->clk); stat = iommu_report_fault(obj, &da); - clk_disable(obj->clk); if (!stat) return IRQ_HANDLED; @@ -787,28 +791,23 @@ struct iommu *iommu_get(const char *name) int err = -ENOMEM; struct device *dev; struct iommu *obj; - dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, device_match_by_alias); if (!dev) return ERR_PTR(-ENODEV); - obj = to_iommu(dev); mutex_lock(&obj->iommu_lock); - if (obj->refcount++ == 0) { err = iommu_enable(obj); if (err) goto err_enable; flush_iotlb_all(obj); } - if (!try_module_get(obj->owner)) goto err_module; mutex_unlock(&obj->iommu_lock); - dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); return obj; @@ -844,6 +843,86 @@ void iommu_put(struct iommu *obj) } EXPORT_SYMBOL_GPL(iommu_put); +struct omap_iommu_dev { + struct device *dev; + struct cdev cdev; + atomic_t count; + int state; + int minor; +}; + +static int omap_iommu_open(struct inode *inode, struct file *filp) +{ + int ret = 0; + struct iommu *obj; + + obj = container_of(inode->i_cdev, struct iommu, cdev); + if (!obj->dev) + return -EINVAL; + + filp->private_data = obj; + iommu_get(obj->name); + + return ret; +} + +static int omap_iommu_release(struct inode *inode, struct file *filp) +{ + struct iommu *obj; + obj = container_of(inode->i_cdev, struct iommu, cdev); + if (!obj->dev) + return -EINVAL; + iommu_put(obj); + return 0; +} + +static int omap_iommu_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args) + +{ + struct iommu *obj; + int ret = 0; + + obj = filp->private_data; + if (!obj) + return -EINVAL; + + if (_IOC_TYPE(cmd) != IOMMU_IOC_MAGIC) + return -ENOTTY; + + switch (cmd) { + case IOMMU_IOCSETTLBENT: + { + struct iotlb_entry e; + int size; + /* FIXME: Re-visit the following check */ + /*if (!capable(CAP_SYS_ADMIN)) + return -EPERM;*/ + size = copy_from_user(&e, (void __user *)args, + sizeof(struct iotlb_entry)); + if (size) { + ret = -EINVAL; + goto err_user_buf; + } + load_iotlb_entry(obj, &e); + break; + } + default: + return -ENOTTY; + } +err_user_buf: + return ret; +} + + +static const struct file_operations omap_iommu_fops = { + .owner = THIS_MODULE, + .open = omap_iommu_open, + .release = omap_iommu_release, + .ioctl = omap_iommu_ioctl, +}; + + /* * OMAP Device MMU(IOMMU) detection */ @@ -855,6 +934,9 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev) struct iommu *obj; struct resource *res; struct iommu_platform_data *pdata = pdev->dev.platform_data; + int major, minor; + struct device *tmpdev; + int ret = 0; if (pdev->num_resources != 2) return -EINVAL; @@ -918,8 +1000,42 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev) BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE)); dev_info(&pdev->dev, "%s registered\n", obj->name); + + major = MAJOR(omap_iommu_dev); + minor = atomic_read(&num_of_iommus); + atomic_inc(&num_of_iommus); + + obj->minor = minor; + + cdev_init(&obj->cdev, &omap_iommu_fops); + obj->cdev.owner = THIS_MODULE; + ret = cdev_add(&obj->cdev, MKDEV(major, minor), 1); + if (ret) { + dev_err(&pdev->dev, "%s: cdev_add failed: %d\n", __func__, ret); + goto err_cdev; + } + + tmpdev = device_create(omap_iommu_class, NULL, + MKDEV(major, minor), + NULL, + OMAP_IOMMU_NAME "%d", minor); + if (IS_ERR(tmpdev)) { + ret = PTR_ERR(tmpdev); + pr_err("%s: device_create failed: %d\n", __func__, ret); + goto clean_cdev; + } + + pr_info("%s initialized %s, major: %d, base-minor: %d\n", + OMAP_IOMMU_NAME, + pdata->name, + MAJOR(omap_iommu_dev), + minor); + return 0; +clean_cdev: + cdev_del(&obj->cdev); +err_cdev: err_pgd: free_irq(irq, obj); err_irq: @@ -937,6 +1053,10 @@ static int __devexit omap_iommu_remove(struct platform_device *pdev) int irq; struct resource *res; struct iommu *obj = platform_get_drvdata(pdev); + int major = MAJOR(omap_iommu_dev); + + device_destroy(omap_iommu_class, MKDEV(major, obj->minor)); + cdev_del(&obj->cdev); platform_set_drvdata(pdev, NULL); @@ -968,11 +1088,13 @@ static void iopte_cachep_ctor(void *iopte) clean_dcache_area(iopte, IOPTE_TABLE_SIZE); } + static int __init omap_iommu_init(void) { struct kmem_cache *p; const unsigned long flags = SLAB_HWCACHE_ALIGN; size_t align = 1 << 10; /* L2 pagetable alignement */ + int ret, num; p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, iopte_cachep_ctor); @@ -980,7 +1102,28 @@ static int __init omap_iommu_init(void) return -ENOMEM; iopte_cachep = p; + num = iommu_get_plat_data_size(); + ret = alloc_chrdev_region(&omap_iommu_dev, 0, num, OMAP_IOMMU_NAME); + + if (ret) { + pr_err("%s: alloc_chrdev_region failed: %d\n", __func__, ret); + goto out; + } + + omap_iommu_class = class_create(THIS_MODULE, OMAP_IOMMU_NAME); + if (IS_ERR(omap_iommu_class)) { + ret = PTR_ERR(omap_iommu_class); + pr_err("%s: class_create failed: %d\n", __func__, ret); + goto unreg_region; + } + atomic_set(&num_of_iommus, 0); + return platform_driver_register(&omap_iommu_driver); + +unreg_region: + unregister_chrdev_region(omap_iommu_dev, num); +out: + return ret; } module_init(omap_iommu_init); @@ -989,6 +1132,9 @@ static void __exit omap_iommu_exit(void) kmem_cache_destroy(iopte_cachep); platform_driver_unregister(&omap_iommu_driver); + + if (omap_iommu_class) + class_destroy(omap_iommu_class); } module_exit(omap_iommu_exit); diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index 08a2df766289..b06d3de49a80 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c @@ -26,12 +26,14 @@ #include <linux/device.h> #include <linux/delay.h> #include <linux/slab.h> +#include <linux/kfifo.h> #include <plat/mailbox.h> static struct workqueue_struct *mboxd; static struct omap_mbox *mboxes; -static DEFINE_RWLOCK(mboxes_lock); +static DEFINE_SPINLOCK(mboxes_lock); +static bool rq_full; static int mbox_configured; @@ -67,61 +69,69 @@ static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) /* * message sender */ -static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) +static int __mbox_poll_for_space(struct omap_mbox *mbox) { int ret = 0, i = 1000; while (mbox_fifo_full(mbox)) { - if (mbox->ops->type == OMAP_MBOX_TYPE2) - return -1; if (--i == 0) return -1; udelay(1); + printk(KERN_ERR "Mailbox FIFO full %d\n", i); } - mbox_fifo_write(mbox, msg); return ret; } int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) { + struct omap_mbox_queue *mq = mbox->txq; + int ret = 0, len; - struct request *rq; - struct request_queue *q = mbox->txq->queue; + spin_lock_bh(&mq->lock); + if (kfifo_avail(&mq->fifo) < sizeof(msg)) { + ret = -ENOMEM; + goto out; + } - rq = blk_get_request(q, WRITE, GFP_ATOMIC); - if (unlikely(!rq)) - return -ENOMEM; + len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); + if (unlikely(len != sizeof(msg))) { + pr_err("%s: kfifo_in anomaly\n", __func__); + ret = -ENOMEM; + } - blk_insert_request(q, rq, 0, (void *) msg); tasklet_schedule(&mbox->txq->tasklet); - return 0; +out: + spin_unlock_bh(&mq->lock); + return ret; } EXPORT_SYMBOL(omap_mbox_msg_send); static void mbox_tx_tasklet(unsigned long tx_data) { - int ret; - struct request *rq; struct omap_mbox *mbox = (struct omap_mbox *)tx_data; - struct request_queue *q = mbox->txq->queue; + struct omap_mbox_queue *mq = mbox->txq; + mbox_msg_t msg; + int ret; - while (1) { + spin_lock(&mq->lock); + while (kfifo_len(&mq->fifo)) { + if (__mbox_poll_for_space(mbox)) { + omap_mbox_enable_irq(mbox, IRQ_TX); + break; + } - rq = blk_fetch_request(q); + ret = kfifo_out(&mq->fifo, (unsigned char *)&msg, + sizeof(msg)); + if (unlikely(ret != sizeof(msg))) + pr_err("%s: kfifo_out anomaly\n", __func__); + + mbox_fifo_write(mbox, msg); - if (!rq) - break; - ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special); - if (ret) { - omap_mbox_enable_irq(mbox, IRQ_TX); - blk_requeue_request(q, rq); - return; - } - blk_end_request_all(rq, 0); } + spin_unlock(&mq->lock); } /* @@ -131,36 +141,22 @@ static void mbox_rx_work(struct work_struct *work) { struct omap_mbox_queue *mq = container_of(work, struct omap_mbox_queue, work); - struct omap_mbox *mbox = mq->queue->queuedata; - struct request_queue *q = mbox->rxq->queue; - struct request *rq; mbox_msg_t msg; - unsigned long flags; + int len; - while (1) { - spin_lock_irqsave(q->queue_lock, flags); - rq = blk_fetch_request(q); - spin_unlock_irqrestore(q->queue_lock, flags); - if (!rq) - break; + while (kfifo_len(&mq->fifo) >= sizeof(msg)) { + len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); + if (unlikely(len != sizeof(msg))) + pr_err("%s: kfifo_out anomaly detected\n", __func__); - msg = (mbox_msg_t)rq->special; - blk_end_request_all(rq, 0); - mbox->rxq->callback((void *)msg); + if (mq->callback) + mq->callback((void *)msg); } } /* * Mailbox interrupt handler */ -static void mbox_txq_fn(struct request_queue *q) -{ -} - -static void mbox_rxq_fn(struct request_queue *q) -{ -} - static void __mbox_tx_interrupt(struct omap_mbox *mbox) { omap_mbox_disable_irq(mbox, IRQ_TX); @@ -170,19 +166,22 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox) static void __mbox_rx_interrupt(struct omap_mbox *mbox) { - struct request *rq; + struct omap_mbox_queue *mq = mbox->rxq; mbox_msg_t msg; - struct request_queue *q = mbox->rxq->queue; + int len; while (!mbox_fifo_empty(mbox)) { - rq = blk_get_request(q, WRITE, GFP_ATOMIC); - if (unlikely(!rq)) + if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { + omap_mbox_disable_irq(mbox, IRQ_RX); + rq_full = true; goto nomem; + } msg = mbox_fifo_read(mbox); - - blk_insert_request(q, rq, 0, (void *)msg); + len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); + if (unlikely(len != sizeof(msg))) + pr_err("%s: kfifo_in anomaly detected\n", __func__); if (mbox->ops->type == OMAP_MBOX_TYPE1) break; } @@ -207,11 +206,9 @@ static irqreturn_t mbox_interrupt(int irq, void *p) } static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, - request_fn_proc *proc, void (*work) (struct work_struct *), void (*tasklet)(unsigned long)) { - struct request_queue *q; struct omap_mbox_queue *mq; mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL); @@ -220,11 +217,8 @@ static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, spin_lock_init(&mq->lock); - q = blk_init_queue(proc, &mq->lock); - if (!q) + if (kfifo_alloc(&mq->fifo, MBOX_KFIFO_SIZE, GFP_KERNEL)) goto error; - q->queuedata = mbox; - mq->queue = q; if (work) INIT_WORK(&mq->work, work); @@ -239,7 +233,7 @@ error: static void mbox_queue_free(struct omap_mbox_queue *q) { - blk_cleanup_queue(q->queue); + kfifo_free(&q->fifo); kfree(q); } @@ -249,16 +243,16 @@ static int omap_mbox_startup(struct omap_mbox *mbox) struct omap_mbox_queue *mq; if (likely(mbox->ops->startup)) { - write_lock(&mboxes_lock); + spin_lock(&mboxes_lock); if (!mbox_configured) ret = mbox->ops->startup(mbox); if (unlikely(ret)) { - write_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); return ret; } mbox_configured++; - write_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); } ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, @@ -269,14 +263,14 @@ static int omap_mbox_startup(struct omap_mbox *mbox) goto fail_request_irq; } - mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet); + mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); if (!mq) { ret = -ENOMEM; goto fail_alloc_txq; } mbox->txq = mq; - mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL); + mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); if (!mq) { ret = -ENOMEM; goto fail_alloc_rxq; @@ -290,7 +284,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox) fail_alloc_txq: free_irq(mbox->irq, mbox); fail_request_irq: - if (unlikely(mbox->ops->shutdown)) + if (likely(mbox->ops->shutdown)) mbox->ops->shutdown(mbox); return ret; @@ -303,13 +297,13 @@ static void omap_mbox_fini(struct omap_mbox *mbox) free_irq(mbox->irq, mbox); - if (unlikely(mbox->ops->shutdown)) { - write_lock(&mboxes_lock); + if (likely(mbox->ops->shutdown)) { + spin_lock(&mboxes_lock); if (mbox_configured > 0) mbox_configured--; if (!mbox_configured) mbox->ops->shutdown(mbox); - write_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); } } @@ -330,14 +324,14 @@ struct omap_mbox *omap_mbox_get(const char *name) struct omap_mbox *mbox; int ret; - read_lock(&mboxes_lock); + spin_lock(&mboxes_lock); mbox = *(find_mboxes(name)); if (mbox == NULL) { - read_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); return ERR_PTR(-ENOENT); } - read_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); ret = omap_mbox_startup(mbox); if (ret) @@ -363,15 +357,15 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox) if (mbox->next) return -EBUSY; - write_lock(&mboxes_lock); + spin_lock(&mboxes_lock); tmp = find_mboxes(mbox->name); if (*tmp) { ret = -EBUSY; - write_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); goto err_find; } *tmp = mbox; - write_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); return 0; @@ -384,18 +378,18 @@ int omap_mbox_unregister(struct omap_mbox *mbox) { struct omap_mbox **tmp; - write_lock(&mboxes_lock); + spin_lock(&mboxes_lock); tmp = &mboxes; while (*tmp) { if (mbox == *tmp) { *tmp = mbox->next; mbox->next = NULL; - write_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); return 0; } tmp = &(*tmp)->next; } - write_unlock(&mboxes_lock); + spin_unlock(&mboxes_lock); return -EINVAL; } @@ -403,7 +397,7 @@ EXPORT_SYMBOL(omap_mbox_unregister); static int __init omap_mbox_init(void) { - mboxd = create_workqueue("mboxd"); + mboxd = create_singlethread_workqueue("mboxd"); if (!mboxd) return -ENOMEM; @@ -419,4 +413,5 @@ module_exit(omap_mbox_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); -MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU"); +MODULE_AUTHOR("Toshihiro Kobayashi"); +MODULE_AUTHOR("Hiroshi DOYU"); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 2aa5337855ed..6c77d6f12188 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -491,7 +491,7 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) return; if (!omap_mcbsp_check_valid_id(id)) { @@ -513,7 +513,7 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { struct omap_mcbsp *mcbsp; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) return; if (!omap_mcbsp_check_valid_id(id)) { @@ -589,7 +589,7 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) * Enable wakup behavior, smart idle and all wakeups * REVISIT: some wakeups may be unnecessary */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { u16 syscon; syscon = MCBSP_READ(mcbsp, SYSCON); @@ -612,7 +612,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) /* * Disable wakup behavior, smart idle and all wakeups */ - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { u16 syscon; syscon = MCBSP_READ(mcbsp, SYSCON); @@ -726,14 +726,17 @@ int omap_mcbsp_request(unsigned int id) goto err_clk_disable; } - init_completion(&mcbsp->rx_irq_completion); - err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, + if (mcbsp->rx_irq) { + init_completion(&mcbsp->rx_irq_completion); + err = request_irq(mcbsp->rx_irq, + omap_mcbsp_rx_irq_handler, 0, "McBSP", (void *)mcbsp); - if (err != 0) { - dev_err(mcbsp->dev, "Unable to request RX IRQ %d " - "for McBSP%d\n", mcbsp->rx_irq, - mcbsp->id); - goto err_free_irq; + if (err != 0) { + dev_err(mcbsp->dev, "Unable to request RX IRQ %d " + "for McBSP%d\n", mcbsp->rx_irq, + mcbsp->id); + goto err_free_irq; + } } } @@ -783,7 +786,8 @@ void omap_mcbsp_free(unsigned int id) if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { /* Free IRQs */ - free_irq(mcbsp->rx_irq, (void *)mcbsp); + if (mcbsp->rx_irq) + free_irq(mcbsp->rx_irq, (void *)mcbsp); free_irq(mcbsp->tx_irq, (void *)mcbsp); } @@ -857,7 +861,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); } - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { /* Release the transmitter and receiver */ w = MCBSP_READ_CACHE(mcbsp, XCCR); w &= ~(tx ? XDISABLE : 0); @@ -887,7 +891,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset transmitter */ tx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { w = MCBSP_READ_CACHE(mcbsp, XCCR); w |= (tx ? XDISABLE : 0); MCBSP_WRITE(mcbsp, XCCR, w); @@ -897,7 +901,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) /* Reset receiver */ rx &= 1; - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { w = MCBSP_READ_CACHE(mcbsp, RCCR); w |= (rx ? RDISABLE : 0); MCBSP_WRITE(mcbsp, RCCR, w); diff --git a/arch/arm/plat-omap/remoteproc.c b/arch/arm/plat-omap/remoteproc.c new file mode 100644 index 000000000000..9056be5a8c6b --- /dev/null +++ b/arch/arm/plat-omap/remoteproc.c @@ -0,0 +1,349 @@ +/* + * OMAP Remote Processor driver + * + * Copyright (C) 2010 Texas Instruments Inc. + * + * Written by Ohad Ben-Cohen <ohad@wizery.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/file.h> +#include <linux/poll.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/platform_device.h> + +#include <plat/remoteproc.h> + +#define OMAP_RPROC_NAME "omap-rproc" +#define DRV_NAME "omap-remoteproc" + +static struct class *omap_rproc_class; +static dev_t omap_rproc_dev; +static atomic_t num_of_rprocs; +static struct platform_driver omap_rproc_driver; + +static inline int rproc_start(struct omap_rproc *rproc) +{ + struct omap_rproc_platform_data *pdata; + if (!rproc->dev) + return -EINVAL; + + pdata = rproc->dev->platform_data; + if (!pdata->ops) + return -EINVAL; + + return pdata->ops->start(rproc); +} + +static inline int rproc_stop(struct omap_rproc *rproc) +{ + struct omap_rproc_platform_data *pdata; + if (!rproc->dev) + return -EINVAL; + + pdata = rproc->dev->platform_data; + if (!pdata->ops) + return -EINVAL; + + return pdata->ops->stop(rproc); +} + +static inline int rproc_get_state(struct omap_rproc *rproc) +{ + struct omap_rproc_platform_data *pdata; + if (!rproc->dev) + return -EINVAL; + + pdata = rproc->dev->platform_data; + if (!pdata->ops) + return -EINVAL; + + return pdata->ops->get_state(rproc); +} +static int omap_rproc_open(struct inode *inode, struct file *filp) +{ + int ret = 0; + struct omap_rproc *rproc; + struct omap_rproc_platform_data *pdata; + + rproc = container_of(inode->i_cdev, struct omap_rproc, cdev); + if (!rproc->dev) + return -EINVAL; + + pdata = rproc->dev->platform_data; + + if (pdata->ops->startup) { + ret = pdata->ops->startup(rproc); + if (ret) + goto out; + } + filp->private_data = rproc; + +out: + return ret; +} + +static int omap_rproc_release(struct inode *inode, struct file *filp) +{ + struct omap_rproc_platform_data *pdata; + struct omap_rproc *rproc = filp->private_data; + if (!rproc || !rproc->dev) + return -EINVAL; + + pdata = rproc->dev->platform_data; + + if (pdata->ops->shutdown) + pdata->ops->shutdown(rproc); + + return 0; +} + +static int omap_rproc_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int rc = 0; + struct omap_rproc *rproc = filp->private_data; + + if (!rproc) + return -EINVAL; + + if (_IOC_TYPE(cmd) != RPROC_IOC_MAGIC) + return -ENOTTY; + if (_IOC_NR(cmd) > RPROC_IOC_MAXNR) + return -ENOTTY; + if (_IOC_DIR(cmd) & _IOC_READ) { + if (!access_ok(VERIFY_WRITE, (void __user *)arg, + _IOC_SIZE(cmd))) + return -EFAULT; + } else if (_IOC_DIR(cmd) & _IOC_WRITE) { + if (!access_ok(VERIFY_READ, (void __user *)arg, + _IOC_SIZE(cmd))) + return -EFAULT; + } + + switch (cmd) { + case RPROC_IOCSTART: + /*FIXME: re-visit this check to perform + proper permission checks */ + /*if (!capable(CAP_SYS_ADMIN)) + return -EPERM;*/ + rc = rproc_start(rproc); + break; + case RPROC_IOCSTOP: + /*FIXME: re-visit this check to perform + proper permission checks */ + /*if (!capable(CAP_SYS_ADMIN)) + return -EPERM;*/ + rc = rproc_stop(rproc); + break; + case RPROC_IOCGETSTATE: + rc = rproc_get_state(rproc); + break; + + default: + return -ENOTTY; + } + + return rc; +} + +static int omap_rproc_mmap(struct file *filp, struct vm_area_struct *vma) +{ + + vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot); + vma->vm_flags |= VM_RESERVED; + + if (remap_pfn_range(vma, + vma->vm_start, + vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) { + return -EAGAIN; + } + return 0; +} + +static const struct file_operations omap_rproc_fops = { + .open = omap_rproc_open, + .release = omap_rproc_release, + .ioctl = omap_rproc_ioctl, + .mmap = omap_rproc_mmap, + .owner = THIS_MODULE, +}; + +static int omap_rproc_probe(struct platform_device *pdev) +{ + int ret = 0, major, minor; + struct device *tmpdev; + struct device *dev = &pdev->dev; + struct omap_rproc_platform_data *pdata = dev->platform_data; + struct omap_rproc *rproc; + + if (!pdata || !pdata->name || !pdata->oh_name || !pdata->ops) + return -EINVAL; + + dev_info(dev, "%s: adding rproc %s\n", __func__, pdata->name); + + rproc = kzalloc(sizeof(struct omap_rproc), GFP_KERNEL); + if (!rproc) { + dev_err(dev, "%s: kzalloc failed\n", __func__); + ret = -ENOMEM; + goto out; + } + + platform_set_drvdata(pdev, rproc); + major = MAJOR(omap_rproc_dev); + minor = atomic_read(&num_of_rprocs); + atomic_inc(&num_of_rprocs); + + rproc->dev = dev; + rproc->minor = minor; + + cdev_init(&rproc->cdev, &omap_rproc_fops); + rproc->cdev.owner = THIS_MODULE; + ret = cdev_add(&rproc->cdev, MKDEV(major, minor), 1); + if (ret) { + dev_err(dev, "%s: cdev_add failed: %d\n", __func__, ret); + goto free_rproc; + } + + tmpdev = device_create(omap_rproc_class, NULL, + MKDEV(major, minor), + NULL, + OMAP_RPROC_NAME "%d", minor); + if (IS_ERR(tmpdev)) { + ret = PTR_ERR(tmpdev); + pr_err("%s: device_create failed: %d\n", __func__, ret); + goto clean_cdev; + } + + pr_info("%s initialized %s, major: %d, base-minor: %d\n", + OMAP_RPROC_NAME, + pdata->name, + MAJOR(omap_rproc_dev), + minor); + return 0; + +clean_cdev: + cdev_del(&rproc->cdev); +free_rproc: + kfree(rproc); +out: + return ret; +} + +static int omap_rproc_remove(struct platform_device *pdev) +{ + int major = MAJOR(omap_rproc_dev); + struct device *dev = &pdev->dev; + struct omap_rproc_platform_data *pdata = dev->platform_data; + struct omap_rproc *rproc = platform_get_drvdata(pdev); + + if (!pdata || !rproc) + return -EINVAL; + + dev_info(dev, "%s removing %s, major: %d, base-minor: %d\n", + OMAP_RPROC_NAME, + pdata->name, + major, + rproc->minor); + + device_destroy(omap_rproc_class, MKDEV(major, rproc->minor)); + cdev_del(&rproc->cdev); + + return 0; +} + +#ifndef CONFIG_PM +#define omap_rproc_suspend NULL +#define omap_rproc_resume NULL +#define omap_rproc_runtime_suspend NULL +#define omap_rproc_runtime_resume NULL +#endif + + +const static struct dev_pm_ops omap_rproc_dev_pm_ops = { + .suspend = omap_rproc_suspend, + .resume = omap_rproc_resume, + .runtime_suspend = omap_rproc_runtime_suspend, + .runtime_resume = omap_rproc_runtime_resume, +}; + +static struct platform_driver omap_rproc_driver = { + .probe = omap_rproc_probe, + .remove = omap_rproc_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .pm = &omap_rproc_dev_pm_ops, + }, +}; + + +static int __init omap_rproc_init(void) +{ + int num = remoteproc_get_plat_data_size(); + int ret; + + ret = alloc_chrdev_region(&omap_rproc_dev, 0, num, OMAP_RPROC_NAME); + if (ret) { + pr_err("%s: alloc_chrdev_region failed: %d\n", __func__, ret); + goto out; + } + + omap_rproc_class = class_create(THIS_MODULE, OMAP_RPROC_NAME); + if (IS_ERR(omap_rproc_class)) { + ret = PTR_ERR(omap_rproc_class); + pr_err("%s: class_create failed: %d\n", __func__, ret); + goto unreg_region; + } + + atomic_set(&num_of_rprocs, 0); + + ret = platform_driver_register(&omap_rproc_driver); + if (ret) { + pr_err("%s: platform_driver_register failed: %d\n", + __func__, ret); + goto out; + } + return 0; +unreg_region: + unregister_chrdev_region(omap_rproc_dev, num); +out: + return ret; +} +module_init(omap_rproc_init); + +static void __exit omap_rproc_exit(void) +{ + int num = remoteproc_get_plat_data_size(); + pr_info("%s\n", __func__); + class_destroy(omap_rproc_class); + unregister_chrdev_region(omap_rproc_dev, num); +} +module_exit(omap_rproc_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("OMAP Remote Processor driver"); +MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>"); +MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>"); |