diff options
Diffstat (limited to 'arch')
349 files changed, 21550 insertions, 2127 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e02b893fb909..8b9ea63a9cad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -253,6 +253,14 @@ config ARCH_CLPS711X help Support for Cirrus Logic 711x/721x based boards. +config ARCH_GEMINI + bool "Cortina Systems Gemini" + select CPU_FA526 + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Support for the Cortina Systems Gemini family SoCs + config ARCH_EBSA110 bool "EBSA-110" select CPU_SA110 @@ -276,14 +284,6 @@ config ARCH_EP93XX help This enables support for the Cirrus EP93xx series of CPUs. -config ARCH_GEMINI - bool "Cortina Systems Gemini" - select CPU_FA526 - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - help - Support for the Cortina Systems Gemini family SoCs - config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 @@ -292,6 +292,29 @@ config ARCH_FOOTBRIDGE Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. +config ARCH_MXC + bool "Freescale MXC/iMX-based" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select ARCH_MTD_XIP + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Support for Freescale MXC/iMX-based family of processors + +config ARCH_STMP3XXX + bool "Freescale STMP3xxx" + select CPU_ARM926T + select HAVE_CLK + select COMMON_CLKDEV + select ARCH_REQUIRE_GPIOLIB + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select GENERIC_GPIO + select USB_ARCH_HAS_EHCI + help + Support for systems based on the Freescale 3xxx CPUs. + config ARCH_NETX bool "Hilscher NetX based" select CPU_ARM926T @@ -404,28 +427,6 @@ config ARCH_KIRKWOOD Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281. -config ARCH_KS8695 - bool "Micrel/Kendin KS8695" - select CPU_ARM922T - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - help - Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based - System-on-Chip devices. - -config ARCH_NS9XXX - bool "NetSilicon NS9xxx" - select CPU_ARM926T - select GENERIC_GPIO - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - select HAVE_CLK - help - Say Y here if you intend to run this kernel on a NetSilicon NS9xxx - System. - - <http://www.digi.com/products/microprocessors/index.jsp> - config ARCH_LOKI bool "Marvell Loki (88RC8480)" select CPU_FEROCEON @@ -447,16 +448,6 @@ config ARCH_MV78XX0 Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0. -config ARCH_MXC - bool "Freescale MXC/iMX-based" - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - select ARCH_MTD_XIP - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - help - Support for Freescale MXC/iMX-based family of processors - config ARCH_ORION5X bool "Marvell Orion" depends on MMU @@ -471,6 +462,49 @@ config ARCH_ORION5X Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), Orion-2 (5281), Orion-1-90 (6183). +config ARCH_MMP + bool "Marvell PXA168/910" + depends on MMU + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select TICK_ONESHOT + select PLAT_PXA + help + Support for Marvell's PXA168/910 processor line. + +config ARCH_KS8695 + bool "Micrel/Kendin KS8695" + select CPU_ARM922T + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based + System-on-Chip devices. + +config ARCH_NS9XXX + bool "NetSilicon NS9xxx" + select CPU_ARM926T + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select HAVE_CLK + help + Say Y here if you intend to run this kernel on a NetSilicon NS9xxx + System. + + <http://www.digi.com/products/microprocessors/index.jsp> + +config ARCH_W90X900 + bool "Nuvoton W90X900 CPU" + select CPU_ARM926T + help + Support for Nuvoton (Winbond logic dept.) ARM9 processor,You + can login www.mcuos.com or www.nuvoton.com to know more. + config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" select CPU_ARM926T @@ -495,19 +529,16 @@ config ARCH_PXA help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. -config ARCH_MMP - bool "Marvell PXA168/910" - depends on MMU - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK - select COMMON_CLKDEV +config ARCH_MSM + bool "Qualcomm MSM" + select CPU_V6 select GENERIC_TIME select GENERIC_CLOCKEVENTS - select TICK_ONESHOT - select PLAT_PXA help - Support for Marvell's PXA168/910 processor line. + Support for Qualcomm MSM7K based systems. This runs on the ARM11 + apps processor of the MSM7K and depends on a shared memory + interface to the ARM9 modem processor which runs the baseband stack + and controls some vital subsystems (clock and power control, etc). config ARCH_RPC bool "RiscPC" @@ -576,6 +607,20 @@ config ARCH_LH7A40X core with a wide array of integrated devices for hand-held and low-power applications. +config ARCH_U300 + bool "ST-Ericsson U300 Series" + depends on MMU + select CPU_ARM926T + select ARM_AMBA + select ARM_VIC + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_GPIO + help + Support for ST-Ericsson U300 series mobile platforms. + config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926T @@ -585,6 +630,8 @@ config ARCH_DAVINCI select ARCH_REQUIRE_GPIOLIB select HAVE_CLK select ZONE_DMA + select HAVE_IDE + select COMMON_CLKDEV help Support for TI's DaVinci platform. @@ -598,24 +645,6 @@ config ARCH_OMAP help Support for TI's OMAP platform (OMAP1 and OMAP2). -config ARCH_MSM - bool "Qualcomm MSM" - select CPU_V6 - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - help - Support for Qualcomm MSM7K based systems. This runs on the ARM11 - apps processor of the MSM7K and depends on a shared memory - interface to the ARM9 modem processor which runs the baseband stack - and controls some vital subsystems (clock and power control, etc). - -config ARCH_W90X900 - bool "Nuvoton W90X900 CPU" - select CPU_ARM926T - help - Support for Nuvoton (Winbond logic dept.) ARM9 processor,You - can login www.mcuos.com or www.nuvoton.com to know more. - endchoice source "arch/arm/mach-clps711x/Kconfig" @@ -679,6 +708,8 @@ source "arch/arm/mach-s3c6400/Kconfig" source "arch/arm/mach-s3c6410/Kconfig" endif +source "arch/arm/plat-stmp3xxx/Kconfig" + source "arch/arm/mach-lh7a40x/Kconfig" source "arch/arm/mach-imx/Kconfig" @@ -705,6 +736,8 @@ source "arch/arm/mach-ks8695/Kconfig" source "arch/arm/mach-msm/Kconfig" +source "arch/arm/mach-u300/Kconfig" + source "arch/arm/mach-w90x900/Kconfig" # Definitions to make life easier diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e84729bf13d4..a4f86e3d4cf0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -99,64 +99,73 @@ CHECKFLAGS += -D__arm__ #Default value head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o textofs-y := 0x00008000 - - machine-$(CONFIG_ARCH_RPC) := rpc - machine-$(CONFIG_ARCH_EBSA110) := ebsa110 - machine-$(CONFIG_FOOTBRIDGE) := footbridge - machine-$(CONFIG_ARCH_SHARK) := shark - machine-$(CONFIG_ARCH_SA1100) := sa1100 -ifeq ($(CONFIG_ARCH_SA1100),y) +textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory - textofs-$(CONFIG_SA1111) := 0x00208000 +ifeq ($(CONFIG_ARCH_SA1100),y) +textofs-$(CONFIG_SA1111) := 0x00208000 endif - machine-$(CONFIG_ARCH_PXA) := pxa - machine-$(CONFIG_ARCH_MMP) := mmp - plat-$(CONFIG_PLAT_PXA) := pxa - machine-$(CONFIG_ARCH_L7200) := l7200 - machine-$(CONFIG_ARCH_INTEGRATOR) := integrator - machine-$(CONFIG_ARCH_GEMINI) := gemini - textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 - machine-$(CONFIG_ARCH_CLPS711X) := clps711x - machine-$(CONFIG_ARCH_IOP32X) := iop32x - machine-$(CONFIG_ARCH_IOP33X) := iop33x - machine-$(CONFIG_ARCH_IOP13XX) := iop13xx - plat-$(CONFIG_PLAT_IOP) := iop - machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx - machine-$(CONFIG_ARCH_IXP2000) := ixp2000 - machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx - machine-$(CONFIG_ARCH_OMAP1) := omap1 - machine-$(CONFIG_ARCH_OMAP2) := omap2 - machine-$(CONFIG_ARCH_OMAP3) := omap2 - plat-$(CONFIG_ARCH_OMAP) := omap - machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 - machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 - plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c - machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 - plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c - machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x - machine-$(CONFIG_ARCH_VERSATILE) := versatile - machine-$(CONFIG_ARCH_IMX) := imx - machine-$(CONFIG_ARCH_H720X) := h720x - machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 - machine-$(CONFIG_ARCH_REALVIEW) := realview - machine-$(CONFIG_ARCH_AT91) := at91 - machine-$(CONFIG_ARCH_EP93XX) := ep93xx - machine-$(CONFIG_ARCH_PNX4008) := pnx4008 - machine-$(CONFIG_ARCH_NETX) := netx - machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx - machine-$(CONFIG_ARCH_DAVINCI) := davinci - machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood - machine-$(CONFIG_ARCH_KS8695) := ks8695 - plat-$(CONFIG_ARCH_MXC) := mxc - machine-$(CONFIG_ARCH_MX2) := mx2 - machine-$(CONFIG_ARCH_MX3) := mx3 - machine-$(CONFIG_ARCH_MX1) := mx1 - machine-$(CONFIG_ARCH_ORION5X) := orion5x - plat-$(CONFIG_PLAT_ORION) := orion - machine-$(CONFIG_ARCH_MSM) := msm - machine-$(CONFIG_ARCH_LOKI) := loki - machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 - machine-$(CONFIG_ARCH_W90X900) := w90x900 + +# Machine directory name. This list is sorted alphanumerically +# by CONFIG_* macro name. +machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 +machine-$(CONFIG_ARCH_AT91) := at91 +machine-$(CONFIG_ARCH_CLPS711X) := clps711x +machine-$(CONFIG_ARCH_DAVINCI) := davinci +machine-$(CONFIG_ARCH_EBSA110) := ebsa110 +machine-$(CONFIG_ARCH_EP93XX) := ep93xx +machine-$(CONFIG_ARCH_GEMINI) := gemini +machine-$(CONFIG_ARCH_H720X) := h720x +machine-$(CONFIG_ARCH_IMX) := imx +machine-$(CONFIG_ARCH_INTEGRATOR) := integrator +machine-$(CONFIG_ARCH_IOP13XX) := iop13xx +machine-$(CONFIG_ARCH_IOP32X) := iop32x +machine-$(CONFIG_ARCH_IOP33X) := iop33x +machine-$(CONFIG_ARCH_IXP2000) := ixp2000 +machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx +machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx +machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood +machine-$(CONFIG_ARCH_KS8695) := ks8695 +machine-$(CONFIG_ARCH_L7200) := l7200 +machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x +machine-$(CONFIG_ARCH_LOKI) := loki +machine-$(CONFIG_ARCH_MMP) := mmp +machine-$(CONFIG_ARCH_MSM) := msm +machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 +machine-$(CONFIG_ARCH_MX1) := mx1 +machine-$(CONFIG_ARCH_MX2) := mx2 +machine-$(CONFIG_ARCH_MX3) := mx3 +machine-$(CONFIG_ARCH_NETX) := netx +machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx +machine-$(CONFIG_ARCH_OMAP1) := omap1 +machine-$(CONFIG_ARCH_OMAP2) := omap2 +machine-$(CONFIG_ARCH_OMAP3) := omap2 +machine-$(CONFIG_ARCH_ORION5X) := orion5x +machine-$(CONFIG_ARCH_PNX4008) := pnx4008 +machine-$(CONFIG_ARCH_PXA) := pxa +machine-$(CONFIG_ARCH_REALVIEW) := realview +machine-$(CONFIG_ARCH_RPC) := rpc +machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 +machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 +machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 +machine-$(CONFIG_ARCH_SA1100) := sa1100 +machine-$(CONFIG_ARCH_SHARK) := shark +machine-$(CONFIG_ARCH_STMP378X) := stmp378x +machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx +machine-$(CONFIG_ARCH_U300) := u300 +machine-$(CONFIG_ARCH_VERSATILE) := versatile +machine-$(CONFIG_ARCH_W90X900) := w90x900 +machine-$(CONFIG_FOOTBRIDGE) := footbridge + +# Platform directory name. This list is sorted alphanumerically +# by CONFIG_* macro name. +plat-$(CONFIG_ARCH_MXC) := mxc +plat-$(CONFIG_ARCH_OMAP) := omap +plat-$(CONFIG_PLAT_IOP) := iop +plat-$(CONFIG_PLAT_ORION) := orion +plat-$(CONFIG_PLAT_PXA) := pxa +plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c +plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c +plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig new file mode 100644 index 000000000000..eb2738b5be5f --- /dev/null +++ b/arch/arm/configs/davinci_all_defconfig @@ -0,0 +1,1784 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc2 +# Wed Apr 15 08:16:53 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +CONFIG_ARCH_DAVINCI=y +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set + +# +# TI DaVinci Implementations +# + +# +# DaVinci Core Type +# +CONFIG_ARCH_DAVINCI_DM644x=y + +# +# DaVinci Board Type +# +CONFIG_MACH_DAVINCI_EVM=y +CONFIG_DAVINCI_MUX=y +CONFIG_DAVINCI_MUX_DEBUG=y +CONFIG_DAVINCI_MUX_WARNINGS=y +CONFIG_DAVINCI_RESET_CLOCKS=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=m +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=m +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=m +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=m +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_DAVINCI=m +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=m + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_TIMINGS=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=m +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y +CONFIG_BLK_DEV_PALMCHIP_BK3710=m +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_LXT_PHY=y +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +CONFIG_LSI_ET1011C_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=m +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_XTKBD=m +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_DAVINCI=y +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +CONFIG_GPIO_PCF857X=m + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_DAVINCI_WATCHDOG=m + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_V4L_USB_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=m +# CONFIG_SND_DAVINCI_SOC is not set +CONFIG_SND_SOC_I2C_AND_SPI=m +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=m +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +# CONFIG_DRAGONRISE_FF is not set +CONFIG_HID_EZKEY=m +# CONFIG_HID_KYE is not set +CONFIG_HID_GYRATION=m +# CONFIG_HID_KENSINGTON is not set +CONFIG_HID_LOGITECH=m +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +# CONFIG_HID_NTRIG is not set +CONFIG_HID_PANTHERLORD=m +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SUNPLUS=m +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=m +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_SOC=y + +# +# DaVinci 35x and 644x USB support +# +# CONFIG_USB_MUSB_HOST is not set +CONFIG_USB_MUSB_PERIPHERAL=y +# CONFIG_USB_MUSB_OTG is not set +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_MUSB_PIO_ONLY=y +# CONFIG_USB_MUSB_DEBUG is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_DEBUG_FS=y +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=m +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=m + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig new file mode 100644 index 000000000000..44461f197a17 --- /dev/null +++ b/arch/arm/configs/stmp378x_defconfig @@ -0,0 +1,1141 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc2 +# Thu Apr 23 02:44:13 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="-default" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_INITRAMFS_COMPRESSION_NONE is not set +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_MARKERS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set +CONFIG_ARCH_STMP3XXX=y + +# +# Freescale STMP3xxx implementations +# +# CONFIG_ARCH_STMP37XX is not set +CONFIG_ARCH_STMP378X=y +# CONFIG_MACH_STMP37XX is not set +CONFIG_MACH_STMP378X=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HIGHMEM=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set + +# +# Classification +# +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set +# CONFIG_MTD_TESTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +CONFIG_MTD_UBI_GLUEBI=y + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=6144 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_VIDEO_ALLOW_V4L1 is not set +# CONFIG_VIDEO_V4L1_COMPAT is not set +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# + +# +# RDS decoders +# + +# +# Video decoders +# + +# +# Video and audio decoders +# + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# + +# +# Video improvement chips +# +# CONFIG_VIDEO_VIVI is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_OBJECTS_SELFTEST=y +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 +CONFIG_DEBUG_SLAB=y +CONFIG_DEBUG_SLAB_LEAK=y +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_LOCK_ALLOC=y +CONFIG_PROVE_LOCKING=y +CONFIG_LOCKDEP=y +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_LOCKDEP is not set +CONFIG_TRACE_IRQFLAGS=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +CONFIG_DEBUG_KOBJECT=y +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +CONFIG_FUNCTION_TRACER=y +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +CONFIG_CONTEXT_SWITCH_TRACER=y +# CONFIG_EVENT_TRACER is not set +CONFIG_BOOT_TRACER=y +# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_STACK_TRACER=y +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set +# CONFIG_SECURITY_PATH is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig new file mode 100644 index 000000000000..401279d531d5 --- /dev/null +++ b/arch/arm/configs/stmp37xx_defconfig @@ -0,0 +1,1002 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29.1 +# Mon Apr 20 04:41:26 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="-default" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_MARKERS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +CONFIG_LBD=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set +CONFIG_ARCH_STMP3XXX=y + +# +# Freescale STMP3xxx implementations +# +CONFIG_ARCH_STMP37XX=y +# CONFIG_ARCH_STMP378X is not set +CONFIG_MACH_STMP37XX=y +# CONFIG_MACH_STMP378X is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set + +# +# Classification +# +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=6144 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_UINPUT is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_STMP_DBG is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_VIDEO_ALLOW_V4L1 is not set +# CONFIG_VIDEO_V4L1_COMPAT is not set +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# + +# +# Video decoders +# + +# +# Video and audio decoders +# + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# + +# +# Video improvement chips +# +# CONFIG_VIDEO_VIVI is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_TRACING=y + +# +# Tracers +# +CONFIG_FUNCTION_TRACER=y +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_BOOT_TRACER=y +# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_STACK_TRACER=y +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set +# CONFIG_SECURITY_PATH is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 110295c5461d..1cd2d6416bda 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -342,7 +342,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) return __va(ptr); } -#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) +#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) /* * Conversion functions: convert a page and protection to a page entry, diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index e4345106ee57..bac578fe0d3d 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -43,6 +43,25 @@ #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) +/* + * Chips have some kind of clocks : group them by functionality + */ +#define cpu_has_utmi() ( cpu_is_at91cap9() \ + || cpu_is_at91sam9rl()) + +#define cpu_has_800M_plla() (cpu_is_at91sam9g20()) + +#define cpu_has_pllb() (!cpu_is_at91sam9rl()) + +#define cpu_has_upll() (0) + +/* USB host HS & FS */ +#define cpu_has_uhp() (!cpu_is_at91sam9rl()) + +/* USB device FS only */ +#define cpu_has_udpfs() (!cpu_is_at91sam9rl()) + + static LIST_HEAD(clocks); static DEFINE_SPINLOCK(clk_lock); @@ -140,7 +159,7 @@ static struct clk utmi_clk = { }; static struct clk uhpck = { .name = "uhpck", - .parent = &pllb, + /*.parent = ... we choose parent at runtime */ .mode = pmc_sys_mode, }; @@ -173,7 +192,11 @@ static struct clk __init *at91_css_to_clk(unsigned long css) case AT91_PMC_CSS_PLLA: return &plla; case AT91_PMC_CSS_PLLB: - return &pllb; + if (cpu_has_upll()) + /* CSS_PLLB == CSS_UPLL */ + return &utmi_clk; + else if (cpu_has_pllb()) + return &pllb; } return NULL; @@ -322,7 +345,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) u32 pckr; pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); - pckr &= AT91_PMC_CSS_PLLB; /* clock selection */ + pckr &= AT91_PMC_CSS; /* clock selection */ pckr |= prescale << 2; at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); clk->rate_hz = actual; @@ -361,7 +384,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) } EXPORT_SYMBOL(clk_set_parent); -/* establish PCK0..PCK3 parentage and rate */ +/* establish PCK0..PCKN parentage and rate */ static void __init init_programmable_clock(struct clk *clk) { struct clk *parent; @@ -389,11 +412,13 @@ static int at91_clk_show(struct seq_file *s, void *unused) seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); - if (!cpu_is_at91sam9rl()) + if (cpu_has_pllb()) seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); - if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) + if (cpu_has_utmi()) seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); + if (cpu_has_upll()) + seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB)); seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); seq_printf(s, "\n"); @@ -554,16 +579,60 @@ static struct clk *const standard_pmc_clocks[] __initdata = { &clk32k, &main_clk, &plla, - &pllb, - - /* PLLB children (USB) */ - &udpck, - &uhpck, /* MCK */ &mck }; +/* PLLB generated USB full speed clock init */ +static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) +{ + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + uhpck.parent = &pllb; + + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); + if (cpu_is_at91rm9200()) { + uhpck.pmc_mask = AT91RM9200_PMC_UHP; + udpck.pmc_mask = AT91RM9200_PMC_UDP; + at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); + } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { + uhpck.pmc_mask = AT91SAM926x_PMC_UHP; + udpck.pmc_mask = AT91SAM926x_PMC_UDP; + } else if (cpu_is_at91cap9()) { + uhpck.pmc_mask = AT91CAP9_PMC_UHP; + } + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); +} + +/* UPLL generated USB full speed clock init */ +static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) +{ + /* + * USB clock init: choose 480 MHz from UPLL, + */ + unsigned int usbr = AT91_PMC_USBS_UPLL; + + /* Setup divider by 10 to reach 48 MHz */ + usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; + + at91_sys_write(AT91_PMC_USB, usbr); + + /* Now set uhpck values */ + uhpck.parent = &utmi_clk; + uhpck.pmc_mask = AT91SAM926x_PMC_UHP; + uhpck.rate_hz = utmi_clk.parent->rate_hz; + uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); +} + int __init at91_clock_init(unsigned long main_clock) { unsigned tmp, freq, mckr; @@ -585,43 +654,37 @@ int __init at91_clock_init(unsigned long main_clock) /* report if PLLA is more than mildly overclocked */ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000) - || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000)) + if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000) + || (cpu_has_800M_plla() && plla.rate_hz > 800000000)) pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - if (cpu_is_at91rm9200()) { - uhpck.pmc_mask = AT91RM9200_PMC_UHP; - udpck.pmc_mask = AT91RM9200_PMC_UDP; - at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); - } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { - uhpck.pmc_mask = AT91SAM926x_PMC_UHP; - udpck.pmc_mask = AT91SAM926x_PMC_UDP; - } else if (cpu_is_at91cap9()) { - uhpck.pmc_mask = AT91CAP9_PMC_UHP; + + if (cpu_has_upll() && !cpu_has_pllb()) { + /* setup UTMI clock as the fourth primary clock + * (instead of pllb) */ + utmi_clk.type |= CLK_TYPE_PRIMARY; + utmi_clk.id = 3; } - at91_sys_write(AT91_CKGR_PLLBR, 0); - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); /* * USB HS clock init */ - if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) { + if (cpu_has_utmi()) /* * multiplier is hard-wired to 40 * (obtain the USB High Speed 480 MHz when input is 12 MHz) */ utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; - } + + /* + * USB FS clock init + */ + if (cpu_has_pllb()) + at91_pllb_usbfs_clock_init(main_clock); + if (cpu_has_upll()) + /* assumes that we choose UPLL for USB and not PLLA */ + at91_upll_usbfs_clock_init(main_clock); /* * MCK and CPU derive from one of those primary clocks. @@ -631,21 +694,31 @@ int __init at91_clock_init(unsigned long main_clock) mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); freq = mck.parent->rate_hz; freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - if (cpu_is_at91rm9200()) + if (cpu_is_at91rm9200()) { mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - else if (cpu_is_at91sam9g20()) { + } else if (cpu_is_at91sam9g20()) { mck.rate_hz = (mckr & AT91_PMC_MDIV) ? freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ if (mckr & AT91_PMC_PDIV) freq /= 2; /* processor clock division */ - } else + } else { mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + } /* Register the PMC's standard clocks */ for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) list_add_tail(&standard_pmc_clocks[i]->node, &clocks); - if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) + if (cpu_has_pllb()) + list_add_tail(&pllb.node, &clocks); + + if (cpu_has_uhp()) + list_add_tail(&uhpck.node, &clocks); + + if (cpu_has_udpfs()) + list_add_tail(&udpck.node, &clocks); + + if (cpu_has_utmi()) list_add_tail(&utmi_clk.node, &clocks); /* MCK and CPU clock are "always on" */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 9561e33b8a9a..64589eaaaee8 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -23,7 +23,7 @@ #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ @@ -39,11 +39,11 @@ #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ @@ -72,6 +72,7 @@ #define AT91_PMC_CSS_MAIN (1 << 0) #define AT91_PMC_CSS_PLLA (2 << 0) #define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ #define AT91_PMC_PRES_1 (0 << 2) #define AT91_PMC_PRES_2 (1 << 2) @@ -88,12 +89,25 @@ #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ #define AT91SAM9_PMC_MDIV_2 (1 << 8) #define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ +#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ #define AT91_PMC_PDIV_1 (0 << 12) #define AT91_PMC_PDIV_2 (1 << 12) +#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ +#define AT91_PMC_PLLADIV2_OFF (0 << 12) +#define AT91_PMC_PLLADIV2_ON (1 << 12) -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ +#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ +#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ +#define AT91_PMC_USBS_PLLA (0 << 0) +#define AT91_PMC_USBS_UPLL (1 << 0) +#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ + +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ +#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ +#define AT91_PMC_CSSMCK_CSS (0 << 8) +#define AT91_PMC_CSSMCK_MCK (1 << 8) #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ @@ -102,7 +116,7 @@ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ #define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index bac988e7a4c3..a9c78bc72b84 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -4,19 +4,56 @@ menu "TI DaVinci Implementations" comment "DaVinci Core Type" -config ARCH_DAVINCI644x - default y +config ARCH_DAVINCI_DM644x bool "DaVinci 644x based system" comment "DaVinci Board Type" config MACH_DAVINCI_EVM - bool "TI DaVinci EVM" + bool "TI DM644x EVM" default y - depends on ARCH_DAVINCI644x + depends on ARCH_DAVINCI_DM644x help Configure this option to specify the whether the board used - for development is a DaVinci EVM + for development is a DM644x EVM + + +config DAVINCI_MUX + bool "DAVINCI multiplexing support" + depends on ARCH_DAVINCI + default y + help + Pin multiplexing support for DAVINCI boards. If your bootloader + sets the multiplexing correctly, say N. Otherwise, or if unsure, + say Y. + +config DAVINCI_MUX_DEBUG + bool "Multiplexing debug output" + depends on DAVINCI_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. + +config DAVINCI_MUX_WARNINGS + bool "Warn about pins the bootloader didn't set up" + depends on DAVINCI_MUX + help + Choose Y here to warn whenever driver initialization logic needs + to change the pin multiplexing setup. When there are no warnings + printed, it's safe to deselect DAVINCI_MUX for your product. + +config DAVINCI_RESET_CLOCKS + bool "Reset unused clocks during boot" + depends on ARCH_DAVINCI + help + Say Y if you want to reset unused clocks during boot. + This option saves power, but assumes all drivers are + using the clock framework. Broken drivers that do not + yet use clock framework may not work with this option. + If you are booting from another operating system, you + probably do not want this option enabled until your + device drivers work properly. endmenu diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 4dc458597f40..1674661942f3 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,7 +5,12 @@ # Common objects obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ - gpio.o mux.o devices.o usb.o + gpio.o devices.o dma.o usb.o + +obj-$(CONFIG_DAVINCI_MUX) += mux.o + +# Chip specific +obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o # Board specific -obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o +obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 0b97a528902b..c039674fe99e 100644 --- a/arch/arm/mach-davinci/board-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -15,15 +15,20 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/leds.h> +#include <linux/memory.h> +#include <linux/etherdevice.h> #include <linux/i2c.h> #include <linux/i2c/pcf857x.h> #include <linux/i2c/at24.h> #include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/io.h> +#include <linux/phy.h> +#include <linux/clk.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -32,25 +37,34 @@ #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <mach/hardware.h> +#include <mach/dm644x.h> #include <mach/common.h> #include <mach/i2c.h> +#include <mach/serial.h> +#include <mach/mux.h> +#include <mach/psc.h> +#include <mach/nand.h> -/* other misc. init functions */ -void __init davinci_psc_init(void); -void __init davinci_irq_init(void); -void __init davinci_map_common_io(void); -void __init davinci_init_common_hw(void); +#define DM644X_EVM_PHY_MASK (0x2) +#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ -#if defined(CONFIG_MTD_PHYSMAP) || \ - defined(CONFIG_MTD_PHYSMAP_MODULE) +#define DAVINCI_CFC_ATA_BASE 0x01C66000 + +#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 + +#define LXT971_PHY_ID (0x001378e2) +#define LXT971_PHY_MASK (0xfffffff0) static struct mtd_partition davinci_evm_norflash_partitions[] = { - /* bootloader (U-Boot, etc) in first 4 sectors */ + /* bootloader (UBL, U-Boot, etc) in first 5 sectors */ { .name = "bootloader", .offset = 0, - .size = 4 * SZ_64K, + .size = 5 * SZ_64K, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, /* bootloader params in the next 1 sectors */ @@ -100,10 +114,89 @@ static struct platform_device davinci_evm_norflash_device = { .resource = &davinci_evm_norflash_resource, }; -#endif +/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks). + * It may used instead of the (default) NOR chip to boot, using TI's + * tools to install the secondary boot loader (UBL) and U-Boot. + */ +struct mtd_partition davinci_evm_nandflash_partition[] = { + /* Bootloader layout depends on whose u-boot is installed, but we + * can hide all the details. + * - block 0 for u-boot environment ... in mainline u-boot + * - block 1 for UBL (plus up to four backup copies in blocks 2..5) + * - blocks 6...? for u-boot + * - blocks 16..23 for u-boot environment ... in TI's u-boot + */ + { + .name = "bootloader", + .offset = 0, + .size = SZ_256K + SZ_128K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* Kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, + /* File system (older GIT kernels started this on the 5MB mark) */ + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* A few blocks at end hold a flash BBT ... created by TI's CCS + * using flashwriter_nand.out, but ignored by TI's versions of + * Linux and u-boot. We boot faster by using them. + */ +}; -#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ - defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) +static struct davinci_nand_pdata davinci_evm_nandflash_data = { + .parts = davinci_evm_nandflash_partition, + .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT, +}; + +static struct resource davinci_evm_nandflash_resource[] = { + { + .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, + .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, + .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device davinci_evm_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &davinci_evm_nandflash_data, + }, + .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource), + .resource = davinci_evm_nandflash_resource, +}; + +static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device davinci_fb_device = { + .name = "davincifb", + .id = -1, + .dev = { + .dma_mask = &davinci_fb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = 0, +}; + +static struct platform_device rtc_dev = { + .name = "rtc_davinci_evm", + .id = -1, +}; static struct resource ide_resources[] = { { @@ -118,7 +211,7 @@ static struct resource ide_resources[] = { }, }; -static u64 ide_dma_mask = DMA_BIT_MASK(32); +static u64 ide_dma_mask = DMA_32BIT_MASK; static struct platform_device ide_dev = { .name = "palm_bk3710", @@ -127,12 +220,10 @@ static struct platform_device ide_dev = { .num_resources = ARRAY_SIZE(ide_resources), .dev = { .dma_mask = &ide_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), + .coherent_dma_mask = DMA_32BIT_MASK, }, }; -#endif - /*----------------------------------------------------------------------*/ /* @@ -311,7 +402,9 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) gpio_request(gpio + 7, "nCF_SEL"); gpio_direction_output(gpio + 7, 1); - /* irlml6401 sustains over 3A, switches 5V in under 8 msec */ + /* irlml6401 switches over 1A, in under 8 msec; + * now it can be managed by nDRV_VBUS ... + */ setup_usb(500, 8); return 0; @@ -343,14 +436,120 @@ static struct pcf857x_platform_data pcf_data_u35 = { * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) * - ... newer boards may have more */ +static struct memory_accessor *at24_mem_acc; + +static void at24_setup(struct memory_accessor *mem_acc, void *context) +{ + DECLARE_MAC_BUF(mac_str); + char mac_addr[6]; + + at24_mem_acc = mem_acc; + + /* Read MAC addr from EEPROM */ + if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) { + printk(KERN_INFO "Read MAC addr from EEPROM: %s\n", + print_mac(mac_str, mac_addr)); + } +} + static struct at24_platform_data eeprom_info = { .byte_len = (256*1024) / 8, .page_size = 64, .flags = AT24_FLAG_ADDR16, + .setup = at24_setup, }; +int dm6446evm_eeprom_read(void *buf, off_t off, size_t count) +{ + if (at24_mem_acc) + return at24_mem_acc->read(at24_mem_acc, buf, off, count); + return -ENODEV; +} +EXPORT_SYMBOL(dm6446evm_eeprom_read); + +int dm6446evm_eeprom_write(void *buf, off_t off, size_t count) +{ + if (at24_mem_acc) + return at24_mem_acc->write(at24_mem_acc, buf, off, count); + return -ENODEV; +} +EXPORT_SYMBOL(dm6446evm_eeprom_write); + +/* + * MSP430 supports RTC, card detection, input from IR remote, and + * a bit more. It triggers interrupts on GPIO(7) from pressing + * buttons on the IR remote, and for card detect switches. + */ +static struct i2c_client *dm6446evm_msp; + +static int dm6446evm_msp_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + dm6446evm_msp = client; + return 0; +} + +static int dm6446evm_msp_remove(struct i2c_client *client) +{ + dm6446evm_msp = NULL; + return 0; +} + +static const struct i2c_device_id dm6446evm_msp_ids[] = { + { "dm6446evm_msp", 0, }, + { /* end of list */ }, +}; + +static struct i2c_driver dm6446evm_msp_driver = { + .driver.name = "dm6446evm_msp", + .id_table = dm6446evm_msp_ids, + .probe = dm6446evm_msp_probe, + .remove = dm6446evm_msp_remove, +}; + +static int dm6444evm_msp430_get_pins(void) +{ + static const char txbuf[2] = { 2, 4, }; + char buf[4]; + struct i2c_msg msg[2] = { + { + .addr = dm6446evm_msp->addr, + .flags = 0, + .len = 2, + .buf = (void __force *)txbuf, + }, + { + .addr = dm6446evm_msp->addr, + .flags = I2C_M_RD, + .len = 4, + .buf = buf, + }, + }; + int status; + + if (!dm6446evm_msp) + return -ENXIO; + + /* Command 4 == get input state, returns port 2 and port3 data + * S Addr W [A] len=2 [A] cmd=4 [A] + * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P + */ + status = i2c_transfer(dm6446evm_msp->adapter, msg, 2); + if (status < 0) + return status; + + dev_dbg(&dm6446evm_msp->dev, + "PINS: %02x %02x %02x %02x\n", + buf[0], buf[1], buf[2], buf[3]); + + return (buf[3] << 8) | buf[2]; +} + static struct i2c_board_info __initdata i2c_info[] = { { + I2C_BOARD_INFO("dm6446evm_msp", 0x23), + }, + { I2C_BOARD_INFO("pcf8574", 0x38), .platform_data = &pcf_data_u2, }, @@ -368,7 +567,6 @@ static struct i2c_board_info __initdata i2c_info[] = { }, /* ALSO: * - tvl320aic33 audio codec (0x1b) - * - msp430 microcontroller (0x23) * - tvp5146 video decoder (0x5d) */ }; @@ -384,51 +582,109 @@ static struct davinci_i2c_platform_data i2c_pdata = { static void __init evm_init_i2c(void) { davinci_init_i2c(&i2c_pdata); + i2c_add_driver(&dm6446evm_msp_driver); i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); } static struct platform_device *davinci_evm_devices[] __initdata = { -#if defined(CONFIG_MTD_PHYSMAP) || \ - defined(CONFIG_MTD_PHYSMAP_MODULE) - &davinci_evm_norflash_device, -#endif -#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ - defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) - &ide_dev, -#endif + &davinci_fb_device, + &rtc_dev, +}; + +static struct davinci_uart_config uart_config __initdata = { + .enabled_uarts = (1 << 0), }; static void __init davinci_evm_map_io(void) { davinci_map_common_io(); + dm644x_init(); } -static __init void davinci_evm_init(void) +static int davinci_phy_fixup(struct phy_device *phydev) { - davinci_psc_init(); + unsigned int control; + /* CRITICAL: Fix for increasing PHY signal drive strength for + * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY + * signal strength was low causing TX to fail randomly. The + * fix is to Set bit 11 (Increased MII drive strength) of PHY + * register 26 (Digital Config register) on this phy. */ + control = phy_read(phydev, 26); + phy_write(phydev, 26, (control | 0x800)); + return 0; +} #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) +#define HAS_ATA 1 +#else +#define HAS_ATA 0 +#endif + #if defined(CONFIG_MTD_PHYSMAP) || \ defined(CONFIG_MTD_PHYSMAP_MODULE) - printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, " - "but share pins.\n\t Disable IDE for NOR support.\n"); +#define HAS_NOR 1 +#else +#define HAS_NOR 0 #endif + +#if defined(CONFIG_MTD_NAND_DAVINCI) || \ + defined(CONFIG_MTD_NAND_DAVINCI_MODULE) +#define HAS_NAND 1 +#else +#define HAS_NAND 0 #endif +static __init void davinci_evm_init(void) +{ + struct clk *aemif_clk; + + aemif_clk = clk_get(NULL, "aemif"); + clk_enable(aemif_clk); + + if (HAS_ATA) { + if (HAS_NAND || HAS_NOR) + pr_warning("WARNING: both IDE and Flash are " + "enabled, but they share AEMIF pins.\n" + "\tDisable IDE for NAND/NOR support.\n"); + davinci_cfg_reg(DM644X_HPIEN_DISABLE); + davinci_cfg_reg(DM644X_ATAEN); + davinci_cfg_reg(DM644X_HDIREN); + platform_device_register(&ide_dev); + } else if (HAS_NAND || HAS_NOR) { + davinci_cfg_reg(DM644X_HPIEN_DISABLE); + davinci_cfg_reg(DM644X_ATAEN_DISABLE); + + /* only one device will be jumpered and detected */ + if (HAS_NAND) { + platform_device_register(&davinci_evm_nandflash_device); + evm_leds[7].default_trigger = "nand-disk"; + if (HAS_NOR) + pr_warning("WARNING: both NAND and NOR flash " + "are enabled; disable one of them.\n"); + } else if (HAS_NOR) + platform_device_register(&davinci_evm_norflash_device); + } + platform_add_devices(davinci_evm_devices, ARRAY_SIZE(davinci_evm_devices)); evm_init_i2c(); + + davinci_serial_init(&uart_config); + + /* Register the fixup for PHY on DaVinci */ + phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, + davinci_phy_fixup); + } static __init void davinci_evm_irq_init(void) { - davinci_init_common_hw(); davinci_irq_init(); } -MACHINE_START(DAVINCI_EVM, "DaVinci EVM") +MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") /* Maintainer: MontaVista Software <source@mvista.com> */ .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index abb92b7eca0c..f0baaa15a57e 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -1,7 +1,8 @@ /* - * TI DaVinci clock config file + * Clock and PLL control for DaVinci devices * - * Copyright (C) 2006 Texas Instruments. + * Copyright (C) 2006-2007 Texas Instruments. + * Copyright (C) 2008-2009 Deep Root Systems, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,6 +14,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/errno.h> +#include <linux/clk.h> #include <linux/err.h> #include <linux/mutex.h> #include <linux/platform_device.h> @@ -21,98 +23,50 @@ #include <mach/hardware.h> #include <mach/psc.h> +#include <mach/cputype.h> #include "clock.h" -/* PLL/Reset register offsets */ -#define PLLM 0x110 - static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clockfw_lock); -static unsigned int commonrate; -static unsigned int armrate; -static unsigned int fixedrate = 27000000; /* 27 MHZ */ - -extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable); - -/* - * Returns a clock. Note that we first try to use device id on the bus - * and clock name. If this fails, we try to use clock name only. - */ -struct clk *clk_get(struct device *dev, const char *id) +static unsigned psc_domain(struct clk *clk) { - struct clk *p, *clk = ERR_PTR(-ENOENT); - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(p, &clocks, node) { - if (p->id == idno && - strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - goto found; - } - } - - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - break; - } - } - -found: - mutex_unlock(&clocks_mutex); - - return clk; + return (clk->flags & PSC_DSP) + ? DAVINCI_GPSC_DSPDOMAIN + : DAVINCI_GPSC_ARMDOMAIN; } -EXPORT_SYMBOL(clk_get); -void clk_put(struct clk *clk) +static void __clk_enable(struct clk *clk) { - if (clk && !IS_ERR(clk)) - module_put(clk->owner); -} -EXPORT_SYMBOL(clk_put); - -static int __clk_enable(struct clk *clk) -{ - if (clk->flags & ALWAYS_ENABLED) - return 0; - - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1); - return 0; + if (clk->parent) + __clk_enable(clk->parent); + if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) + davinci_psc_config(psc_domain(clk), clk->lpsc, 1); } static void __clk_disable(struct clk *clk) { - if (clk->usecount) + if (WARN_ON(clk->usecount == 0)) return; - - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0); + if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) + davinci_psc_config(psc_domain(clk), clk->lpsc, 0); + if (clk->parent) + __clk_disable(clk->parent); } int clk_enable(struct clk *clk) { unsigned long flags; - int ret = 0; if (clk == NULL || IS_ERR(clk)) return -EINVAL; - if (clk->usecount++ == 0) { - spin_lock_irqsave(&clockfw_lock, flags); - ret = __clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - } + spin_lock_irqsave(&clockfw_lock, flags); + __clk_enable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); - return ret; + return 0; } EXPORT_SYMBOL(clk_enable); @@ -123,11 +77,9 @@ void clk_disable(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return; - if (clk->usecount > 0 && !(--clk->usecount)) { - spin_lock_irqsave(&clockfw_lock, flags); - __clk_disable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - } + spin_lock_irqsave(&clockfw_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); } EXPORT_SYMBOL(clk_disable); @@ -136,7 +88,7 @@ unsigned long clk_get_rate(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return -EINVAL; - return *(clk->rate); + return clk->rate; } EXPORT_SYMBOL(clk_get_rate); @@ -145,7 +97,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) if (clk == NULL || IS_ERR(clk)) return -EINVAL; - return *(clk->rate); + return clk->rate; } EXPORT_SYMBOL(clk_round_rate); @@ -164,10 +116,23 @@ int clk_register(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return -EINVAL; + if (WARN(clk->parent && !clk->parent->rate, + "CLK: %s parent %s has no rate!\n", + clk->name, clk->parent->name)) + return -EINVAL; + mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); + list_add_tail(&clk->node, &clocks); mutex_unlock(&clocks_mutex); + /* If rate is already set, use it */ + if (clk->rate) + return 0; + + /* Otherwise, default to parent rate */ + if (clk->parent) + clk->rate = clk->parent->rate; + return 0; } EXPORT_SYMBOL(clk_register); @@ -183,84 +148,150 @@ void clk_unregister(struct clk *clk) } EXPORT_SYMBOL(clk_unregister); -static struct clk davinci_clks[] = { - { - .name = "ARMCLK", - .rate = &armrate, - .lpsc = -1, - .flags = ALWAYS_ENABLED, - }, - { - .name = "UART", - .rate = &fixedrate, - .lpsc = DAVINCI_LPSC_UART0, - }, - { - .name = "EMACCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, - }, - { - .name = "I2CCLK", - .rate = &fixedrate, - .lpsc = DAVINCI_LPSC_I2C, - }, - { - .name = "IDECLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_ATA, - }, - { - .name = "McBSPCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_McBSP, - }, - { - .name = "MMCSDCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_MMC_SD, - }, - { - .name = "SPICLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_SPI, - }, - { - .name = "gpio", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_GPIO, - }, - { - .name = "usb", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_USB, - }, - { - .name = "AEMIFCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_AEMIF, - .usecount = 1, +#ifdef CONFIG_DAVINCI_RESET_CLOCKS +/* + * Disable any unused clocks left on by the bootloader + */ +static int __init clk_disable_unused(void) +{ + struct clk *ck; + + spin_lock_irq(&clockfw_lock); + list_for_each_entry(ck, &clocks, node) { + if (ck->usecount > 0) + continue; + if (!(ck->flags & CLK_PSC)) + continue; + + /* ignore if in Disabled or SwRstDisable states */ + if (!davinci_psc_is_clk_active(ck->lpsc)) + continue; + + pr_info("Clocks: disable unused %s\n", ck->name); + davinci_psc_config(psc_domain(ck), ck->lpsc, 0); } -}; + spin_unlock_irq(&clockfw_lock); + + return 0; +} +late_initcall(clk_disable_unused); +#endif -int __init davinci_clk_init(void) +static void clk_sysclk_recalc(struct clk *clk) { - struct clk *clkp; - int count = 0; - u32 pll_mult; - - pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); - commonrate = ((pll_mult + 1) * 27000000) / 6; - armrate = ((pll_mult + 1) * 27000000) / 2; - - for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks); - count++, clkp++) { - clk_register(clkp); - - /* Turn on clocks that have been enabled in the - * table above */ - if (clkp->usecount) - clk_enable(clkp); + u32 v, plldiv; + struct pll_data *pll; + + /* If this is the PLL base clock, no more calculations needed */ + if (clk->pll_data) + return; + + if (WARN_ON(!clk->parent)) + return; + + clk->rate = clk->parent->rate; + + /* Otherwise, the parent must be a PLL */ + if (WARN_ON(!clk->parent->pll_data)) + return; + + pll = clk->parent->pll_data; + + /* If pre-PLL, source clock is before the multiplier and divider(s) */ + if (clk->flags & PRE_PLL) + clk->rate = pll->input_rate; + + if (!clk->div_reg) + return; + + v = __raw_readl(pll->base + clk->div_reg); + if (v & PLLDIV_EN) { + plldiv = (v & PLLDIV_RATIO_MASK) + 1; + if (plldiv) + clk->rate /= plldiv; + } +} + +static void __init clk_pll_init(struct clk *clk) +{ + u32 ctrl, mult = 1, prediv = 1, postdiv = 1; + u8 bypass; + struct pll_data *pll = clk->pll_data; + + pll->base = IO_ADDRESS(pll->phys_base); + ctrl = __raw_readl(pll->base + PLLCTL); + clk->rate = pll->input_rate = clk->parent->rate; + + if (ctrl & PLLCTL_PLLEN) { + bypass = 0; + mult = __raw_readl(pll->base + PLLM); + mult = (mult & PLLM_PLLM_MASK) + 1; + } else + bypass = 1; + + if (pll->flags & PLL_HAS_PREDIV) { + prediv = __raw_readl(pll->base + PREDIV); + if (prediv & PLLDIV_EN) + prediv = (prediv & PLLDIV_RATIO_MASK) + 1; + else + prediv = 1; + } + + /* pre-divider is fixed, but (some?) chips won't report that */ + if (cpu_is_davinci_dm355() && pll->num == 1) + prediv = 8; + + if (pll->flags & PLL_HAS_POSTDIV) { + postdiv = __raw_readl(pll->base + POSTDIV); + if (postdiv & PLLDIV_EN) + postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; + else + postdiv = 1; + } + + if (!bypass) { + clk->rate /= prediv; + clk->rate *= mult; + clk->rate /= postdiv; + } + + pr_debug("PLL%d: input = %lu MHz [ ", + pll->num, clk->parent->rate / 1000000); + if (bypass) + pr_debug("bypass "); + if (prediv > 1) + pr_debug("/ %d ", prediv); + if (mult > 1) + pr_debug("* %d ", mult); + if (postdiv > 1) + pr_debug("/ %d ", postdiv); + pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000); +} + +int __init davinci_clk_init(struct davinci_clk *clocks) + { + struct davinci_clk *c; + struct clk *clk; + + for (c = clocks; c->lk.clk; c++) { + clk = c->lk.clk; + + if (clk->pll_data) + clk_pll_init(clk); + + /* Calculate rates for PLL-derived clocks */ + else if (clk->flags & CLK_PLL) + clk_sysclk_recalc(clk); + + if (clk->lpsc) + clk->flags |= CLK_PSC; + + clkdev_add(&c->lk); + clk_register(clk); + + /* Turn on clocks that Linux doesn't otherwise manage */ + if (clk->flags & ALWAYS_ENABLED) + clk_enable(clk); } return 0; @@ -285,12 +316,52 @@ static void davinci_ck_stop(struct seq_file *m, void *v) { } -static int davinci_ck_show(struct seq_file *m, void *v) +#define CLKNAME_MAX 10 /* longest clock name */ +#define NEST_DELTA 2 +#define NEST_MAX 4 + +static void +dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) { - struct clk *cp; + char *state; + char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; + struct clk *clk; + unsigned i; + + if (parent->flags & CLK_PLL) + state = "pll"; + else if (parent->flags & CLK_PSC) + state = "psc"; + else + state = ""; + + /* <nest spaces> name <pad to end> */ + memset(buf, ' ', sizeof(buf) - 1); + buf[sizeof(buf) - 1] = 0; + i = strlen(parent->name); + memcpy(buf + nest, parent->name, + min(i, (unsigned)(sizeof(buf) - 1 - nest))); + + seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", + buf, parent->usecount, state, clk_get_rate(parent)); + /* REVISIT show device associations too */ + + /* cost is now small, but not linear... */ + list_for_each_entry(clk, &clocks, node) { + if (clk->parent == parent) + dump_clock(s, nest + NEST_DELTA, clk); + } +} - list_for_each_entry(cp, &clocks, node) - seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount); +static int davinci_ck_show(struct seq_file *m, void *v) +{ + /* Show clock tree; we know the main oscillator is first. + * We trust nonzero usecounts equate to PSC enables... + */ + mutex_lock(&clocks_mutex); + if (!list_empty(&clocks)) + dump_clock(m, 0, list_first_entry(&clocks, struct clk, node)); + mutex_unlock(&clocks_mutex); return 0; } @@ -321,4 +392,4 @@ static int __init davinci_ck_proc_init(void) } __initcall(davinci_ck_proc_init); -#endif /* CONFIG_DEBUG_PROC_FS */ +#endif /* CONFIG_DEBUG_PROC_FS */ diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index ed47079a52e4..35736ec202f8 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -1,7 +1,8 @@ /* * TI DaVinci clock definitions * - * Copyright (C) 2006 Texas Instruments. + * Copyright (C) 2006-2007 Texas Instruments. + * Copyright (C) 2008-2009 Deep Root Systems, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -11,23 +12,85 @@ #ifndef __ARCH_ARM_DAVINCI_CLOCK_H #define __ARCH_ARM_DAVINCI_CLOCK_H +#include <linux/list.h> +#include <asm/clkdev.h> + +#define DAVINCI_PLL1_BASE 0x01c40800 +#define DAVINCI_PLL2_BASE 0x01c40c00 +#define MAX_PLL 2 + +/* PLL/Reset register offsets */ +#define PLLCTL 0x100 +#define PLLCTL_PLLEN BIT(0) +#define PLLCTL_CLKMODE BIT(8) + +#define PLLM 0x110 +#define PLLM_PLLM_MASK 0xff + +#define PREDIV 0x114 +#define PLLDIV1 0x118 +#define PLLDIV2 0x11c +#define PLLDIV3 0x120 +#define POSTDIV 0x128 +#define BPDIV 0x12c +#define PLLCMD 0x138 +#define PLLSTAT 0x13c +#define PLLALNCTL 0x140 +#define PLLDCHANGE 0x144 +#define PLLCKEN 0x148 +#define PLLCKSTAT 0x14c +#define PLLSYSTAT 0x150 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16c +#define PLLDIV8 0x170 +#define PLLDIV9 0x174 +#define PLLDIV_EN BIT(15) +#define PLLDIV_RATIO_MASK 0x1f + +struct pll_data { + u32 phys_base; + void __iomem *base; + u32 num; + u32 flags; + u32 input_rate; +}; +#define PLL_HAS_PREDIV 0x01 +#define PLL_HAS_POSTDIV 0x02 + struct clk { struct list_head node; struct module *owner; const char *name; - unsigned int *rate; - int id; - __s8 usecount; - __u8 flags; - __u8 lpsc; + unsigned long rate; + u8 usecount; + u8 flags; + u8 lpsc; + struct clk *parent; + struct pll_data *pll_data; + u32 div_reg; }; /* Clock flags */ -#define RATE_CKCTL 1 -#define RATE_FIXED 2 -#define RATE_PROPAGATES 4 -#define VIRTUAL_CLOCK 8 -#define ALWAYS_ENABLED 16 -#define ENABLE_REG_32BIT 32 +#define ALWAYS_ENABLED BIT(1) +#define CLK_PSC BIT(2) +#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ +#define CLK_PLL BIT(4) /* PLL-derived clock */ +#define PRE_PLL BIT(5) /* source is before PLL mult/div */ + +struct davinci_clk { + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck) \ + { \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } +int davinci_clk_init(struct davinci_clk *clocks); #endif diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 808633f9f03c..a31370b93dd2 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -21,6 +21,10 @@ #include <mach/hardware.h> #include <mach/i2c.h> #include <mach/irqs.h> +#include <mach/cputype.h> +#include <mach/mux.h> + +#define DAVINCI_I2C_BASE 0x01C21000 static struct resource i2c_resources[] = { { @@ -43,6 +47,9 @@ static struct platform_device davinci_i2c_device = { void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) { + if (cpu_is_davinci_dm644x()) + davinci_cfg_reg(DM644X_I2C); + davinci_i2c_device.dev.platform_data = pdata; (void) platform_device_register(&davinci_i2c_device); } diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c new file mode 100644 index 000000000000..d428ef192eac --- /dev/null +++ b/arch/arm/mach-davinci/dm644x.c @@ -0,0 +1,461 @@ +/* + * TI DaVinci DM644x chip specific setup + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <mach/dm644x.h> +#include <mach/clock.h> +#include <mach/cputype.h> +#include <mach/edma.h> +#include <mach/irqs.h> +#include <mach/psc.h> +#include <mach/mux.h> + +#include "clock.h" +#include "mux.h" + +/* + * Device specific clocks + */ +#define DM644X_REF_FREQ 27000000 + +static struct pll_data pll1_data = { + .num = 1, + .phys_base = DAVINCI_PLL1_BASE, +}; + +static struct pll_data pll2_data = { + .num = 2, + .phys_base = DAVINCI_PLL2_BASE, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DM644X_REF_FREQ, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .pll_data = &pll1_data, + .flags = CLK_PLL, +}; + +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk pll2_clk = { + .name = "pll2", + .parent = &ref_clk, + .pll_data = &pll2_data, + .flags = CLK_PLL, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll2_sysclk2 = { + .name = "pll2_sysclk2", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll2_sysclkbp = { + .name = "pll2_sysclkbp", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk dsp_clk = { + .name = "dsp", + .parent = &pll1_sysclk1, + .lpsc = DAVINCI_LPSC_GEM, + .flags = PSC_DSP, + .usecount = 1, /* REVISIT how to disable? */ +}; + +static struct clk arm_clk = { + .name = "arm", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk vicp_clk = { + .name = "vicp", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_IMCOP, + .flags = PSC_DSP, + .usecount = 1, /* REVISIT how to disable? */ +}; + +static struct clk vpss_master_clk = { + .name = "vpss_master", + .parent = &pll1_sysclk3, + .lpsc = DAVINCI_LPSC_VPSSMSTR, + .flags = CLK_PSC, +}; + +static struct clk vpss_slave_clk = { + .name = "vpss_slave", + .parent = &pll1_sysclk3, + .lpsc = DAVINCI_LPSC_VPSSSLV, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART2, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, +}; + +static struct clk i2c_clk = { + .name = "i2c", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_I2C, +}; + +static struct clk ide_clk = { + .name = "ide", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_ATA, +}; + +static struct clk asp_clk = { + .name = "asp0", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_McBSP, +}; + +static struct clk mmcsd_clk = { + .name = "mmcsd", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_MMC_SD, +}; + +static struct clk spi_clk = { + .name = "spi", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_SPI, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_GPIO, +}; + +static struct clk usb_clk = { + .name = "usb", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_USB, +}; + +static struct clk vlynq_clk = { + .name = "vlynq", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_VLYNQ, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll1_sysclk5, + .lpsc = DAVINCI_LPSC_AEMIF, +}; + +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM0, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM1, +}; + +static struct clk pwm2_clk = { + .name = "pwm2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM2, +}; + +static struct clk timer0_clk = { + .name = "timer0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER0, +}; + +static struct clk timer1_clk = { + .name = "timer1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER1, +}; + +static struct clk timer2_clk = { + .name = "timer2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER2, + .usecount = 1, /* REVISIT: why cant' this be disabled? */ +}; + +struct davinci_clk dm644x_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), + CLK(NULL, "pll2", &pll2_clk), + CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), + CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), + CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), + CLK(NULL, "dsp", &dsp_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "vicp", &vicp_clk), + CLK(NULL, "vpss_master", &vpss_master_clk), + CLK(NULL, "vpss_slave", &vpss_slave_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK("i2c_davinci.1", NULL, &i2c_clk), + CLK("palm_bk3710", NULL, &ide_clk), + CLK("soc-audio.0", NULL, &asp_clk), + CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK(NULL, "spi", &spi_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK(NULL, "usb", &usb_clk), + CLK(NULL, "vlynq", &vlynq_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, "pwm0", &pwm0_clk), + CLK(NULL, "pwm1", &pwm1_clk), + CLK(NULL, "pwm2", &pwm2_clk), + CLK(NULL, "timer0", &timer0_clk), + CLK(NULL, "timer1", &timer1_clk), + CLK("watchdog", NULL, &timer2_clk), + CLK(NULL, NULL, NULL), +}; + +#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) + +static struct resource dm644x_emac_resources[] = { + { + .start = DM644X_EMAC_BASE, + .end = DM644X_EMAC_BASE + 0x47ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_EMACINT, + .end = IRQ_EMACINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dm644x_emac_device = { + .name = "davinci_emac", + .id = 1, + .num_resources = ARRAY_SIZE(dm644x_emac_resources), + .resource = dm644x_emac_resources, +}; + +#endif + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config dm644x_pins[] = { +MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) +MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) +MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) + +MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) + +MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) + +MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) + +MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false) + +MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false) + +MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true) +MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true) + +MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false) + +MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false) + +MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false) + +MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false) +MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false) +MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false) + +MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true) + +MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true) + +MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true) +MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false) +MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false) +MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true) + +MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) + +MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) +MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) +}; + + +/*----------------------------------------------------------------------*/ + +static const s8 dma_chan_dm644x_no_event[] = { + 0, 1, 12, 13, 14, + 15, 25, 30, 31, 45, + 46, 47, 55, 56, 57, + 58, 59, 60, 61, 62, + 63, + -1 +}; + +static struct edma_soc_info dm644x_edma_info = { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .noevent = dma_chan_dm644x_no_event, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc", + .start = 0x01c00000, + .end = 0x01c00000 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = 0x01c10000, + .end = 0x01c10000 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = 0x01c10400, + .end = 0x01c10400 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CCINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CCERRINT, + .flags = IORESOURCE_IRQ, + }, + /* not using TC*_ERR */ +}; + +static struct platform_device dm644x_edma_device = { + .name = "edma", + .id = -1, + .dev.platform_data = &dm644x_edma_info, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, +}; + +/*----------------------------------------------------------------------*/ +void __init dm644x_init(void) +{ + davinci_clk_init(dm644x_clks); + davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins)); +} + +static int __init dm644x_init_devices(void) +{ + if (!cpu_is_davinci_dm644x()) + return 0; + + platform_device_register(&dm644x_edma_device); + return 0; +} +postcore_initcall(dm644x_init_devices); diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c new file mode 100644 index 000000000000..15e9eb158bb7 --- /dev/null +++ b/arch/arm/mach-davinci/dma.c @@ -0,0 +1,1135 @@ +/* + * EDMA3 support for DaVinci + * + * Copyright (C) 2006-2009 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/compiler.h> +#include <linux/io.h> + +#include <mach/cputype.h> +#include <mach/memory.h> +#include <mach/hardware.h> +#include <mach/irqs.h> +#include <mach/edma.h> +#include <mach/mux.h> + + +/* Offsets matching "struct edmacc_param" */ +#define PARM_OPT 0x00 +#define PARM_SRC 0x04 +#define PARM_A_B_CNT 0x08 +#define PARM_DST 0x0c +#define PARM_SRC_DST_BIDX 0x10 +#define PARM_LINK_BCNTRLD 0x14 +#define PARM_SRC_DST_CIDX 0x18 +#define PARM_CCNT 0x1c + +#define PARM_SIZE 0x20 + +/* Offsets for EDMA CC global channel registers and their shadows */ +#define SH_ER 0x00 /* 64 bits */ +#define SH_ECR 0x08 /* 64 bits */ +#define SH_ESR 0x10 /* 64 bits */ +#define SH_CER 0x18 /* 64 bits */ +#define SH_EER 0x20 /* 64 bits */ +#define SH_EECR 0x28 /* 64 bits */ +#define SH_EESR 0x30 /* 64 bits */ +#define SH_SER 0x38 /* 64 bits */ +#define SH_SECR 0x40 /* 64 bits */ +#define SH_IER 0x50 /* 64 bits */ +#define SH_IECR 0x58 /* 64 bits */ +#define SH_IESR 0x60 /* 64 bits */ +#define SH_IPR 0x68 /* 64 bits */ +#define SH_ICR 0x70 /* 64 bits */ +#define SH_IEVAL 0x78 +#define SH_QER 0x80 +#define SH_QEER 0x84 +#define SH_QEECR 0x88 +#define SH_QEESR 0x8c +#define SH_QSER 0x90 +#define SH_QSECR 0x94 +#define SH_SIZE 0x200 + +/* Offsets for EDMA CC global registers */ +#define EDMA_REV 0x0000 +#define EDMA_CCCFG 0x0004 +#define EDMA_QCHMAP 0x0200 /* 8 registers */ +#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ +#define EDMA_QDMAQNUM 0x0260 +#define EDMA_QUETCMAP 0x0280 +#define EDMA_QUEPRI 0x0284 +#define EDMA_EMR 0x0300 /* 64 bits */ +#define EDMA_EMCR 0x0308 /* 64 bits */ +#define EDMA_QEMR 0x0310 +#define EDMA_QEMCR 0x0314 +#define EDMA_CCERR 0x0318 +#define EDMA_CCERRCLR 0x031c +#define EDMA_EEVAL 0x0320 +#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ +#define EDMA_QRAE 0x0380 /* 4 registers */ +#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ +#define EDMA_QSTAT 0x0600 /* 2 registers */ +#define EDMA_QWMTHRA 0x0620 +#define EDMA_QWMTHRB 0x0624 +#define EDMA_CCSTAT 0x0640 + +#define EDMA_M 0x1000 /* global channel registers */ +#define EDMA_ECR 0x1008 +#define EDMA_ECRH 0x100C +#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ +#define EDMA_PARM 0x4000 /* 128 param entries */ + +#define DAVINCI_DMA_3PCC_BASE 0x01C00000 + +#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) + +#define EDMA_MAX_DMACH 64 +#define EDMA_MAX_PARAMENTRY 512 +#define EDMA_MAX_EVQUE 2 /* FIXME too small */ + + +/*****************************************************************************/ + +static void __iomem *edmacc_regs_base; + +static inline unsigned int edma_read(int offset) +{ + return (unsigned int)__raw_readl(edmacc_regs_base + offset); +} + +static inline void edma_write(int offset, int val) +{ + __raw_writel(val, edmacc_regs_base + offset); +} +static inline void edma_modify(int offset, unsigned and, unsigned or) +{ + unsigned val = edma_read(offset); + val &= and; + val |= or; + edma_write(offset, val); +} +static inline void edma_and(int offset, unsigned and) +{ + unsigned val = edma_read(offset); + val &= and; + edma_write(offset, val); +} +static inline void edma_or(int offset, unsigned or) +{ + unsigned val = edma_read(offset); + val |= or; + edma_write(offset, val); +} +static inline unsigned int edma_read_array(int offset, int i) +{ + return edma_read(offset + (i << 2)); +} +static inline void edma_write_array(int offset, int i, unsigned val) +{ + edma_write(offset + (i << 2), val); +} +static inline void edma_modify_array(int offset, int i, + unsigned and, unsigned or) +{ + edma_modify(offset + (i << 2), and, or); +} +static inline void edma_or_array(int offset, int i, unsigned or) +{ + edma_or(offset + (i << 2), or); +} +static inline void edma_or_array2(int offset, int i, int j, unsigned or) +{ + edma_or(offset + ((i*2 + j) << 2), or); +} +static inline void edma_write_array2(int offset, int i, int j, unsigned val) +{ + edma_write(offset + ((i*2 + j) << 2), val); +} +static inline unsigned int edma_shadow0_read(int offset) +{ + return edma_read(EDMA_SHADOW0 + offset); +} +static inline unsigned int edma_shadow0_read_array(int offset, int i) +{ + return edma_read(EDMA_SHADOW0 + offset + (i << 2)); +} +static inline void edma_shadow0_write(int offset, unsigned val) +{ + edma_write(EDMA_SHADOW0 + offset, val); +} +static inline void edma_shadow0_write_array(int offset, int i, unsigned val) +{ + edma_write(EDMA_SHADOW0 + offset + (i << 2), val); +} +static inline unsigned int edma_parm_read(int offset, int param_no) +{ + return edma_read(EDMA_PARM + offset + (param_no << 5)); +} +static inline void edma_parm_write(int offset, int param_no, unsigned val) +{ + edma_write(EDMA_PARM + offset + (param_no << 5), val); +} +static inline void edma_parm_modify(int offset, int param_no, + unsigned and, unsigned or) +{ + edma_modify(EDMA_PARM + offset + (param_no << 5), and, or); +} +static inline void edma_parm_and(int offset, int param_no, unsigned and) +{ + edma_and(EDMA_PARM + offset + (param_no << 5), and); +} +static inline void edma_parm_or(int offset, int param_no, unsigned or) +{ + edma_or(EDMA_PARM + offset + (param_no << 5), or); +} + +/*****************************************************************************/ + +/* actual number of DMA channels and slots on this silicon */ +static unsigned num_channels; +static unsigned num_slots; + +static struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; +} intr_data[EDMA_MAX_DMACH]; + +/* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ +static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + +/* The edma_noevent bit for each channel is clear unless + * it doesn't trigger DMA events on this platform. It uses a + * bit of SOC-specific initialization code. + */ +static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); + +/* dummy param set used to (re)initialize parameter RAM slots */ +static const struct edmacc_param dummy_paramset = { + .link_bcntrld = 0xffff, + .ccnt = 1, +}; + +static const int __initconst +queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = { +/* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1} +}; + +static const int __initconst +queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1} +}; + +/*****************************************************************************/ + +static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no) +{ + int bit = (ch_no & 0x7) * 4; + + /* default to low priority queue */ + if (queue_no == EVENTQ_DEFAULT) + queue_no = EVENTQ_1; + + queue_no &= 7; + edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3), + ~(0x7 << bit), queue_no << bit); +} + +static void __init map_queue_tc(int queue_no, int tc_no) +{ + int bit = queue_no * 4; + edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); +} + +static void __init assign_priority_to_queue(int queue_no, int priority) +{ + int bit = queue_no * 4; + edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); +} + +static inline void +setup_dma_interrupt(unsigned lch, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data) +{ + if (!callback) { + edma_shadow0_write_array(SH_IECR, lch >> 5, + (1 << (lch & 0x1f))); + } + + intr_data[lch].callback = callback; + intr_data[lch].data = data; + + if (callback) { + edma_shadow0_write_array(SH_ICR, lch >> 5, + (1 << (lch & 0x1f))); + edma_shadow0_write_array(SH_IESR, lch >> 5, + (1 << (lch & 0x1f))); + } +} + +/****************************************************************************** + * + * DMA interrupt handler + * + *****************************************************************************/ +static irqreturn_t dma_irq_handler(int irq, void *data) +{ + int i; + unsigned int cnt = 0; + + dev_dbg(data, "dma_irq_handler\n"); + + if ((edma_shadow0_read_array(SH_IPR, 0) == 0) + && (edma_shadow0_read_array(SH_IPR, 1) == 0)) + return IRQ_NONE; + + while (1) { + int j; + if (edma_shadow0_read_array(SH_IPR, 0)) + j = 0; + else if (edma_shadow0_read_array(SH_IPR, 1)) + j = 1; + else + break; + dev_dbg(data, "IPR%d %08x\n", j, + edma_shadow0_read_array(SH_IPR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) { + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(SH_ICR, j, (1 << i)); + if (intr_data[k].callback) { + intr_data[k].callback(k, DMA_COMPLETE, + intr_data[k].data); + } + } + } + cnt++; + if (cnt > 10) + break; + } + edma_shadow0_write(SH_IEVAL, 1); + return IRQ_HANDLED; +} + +/****************************************************************************** + * + * DMA error interrupt handler + * + *****************************************************************************/ +static irqreturn_t dma_ccerr_handler(int irq, void *data) +{ + int i; + unsigned int cnt = 0; + + dev_dbg(data, "dma_ccerr_handler\n"); + + if ((edma_read_array(EDMA_EMR, 0) == 0) && + (edma_read_array(EDMA_EMR, 1) == 0) && + (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0)) + return IRQ_NONE; + + while (1) { + int j = -1; + if (edma_read_array(EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + dev_dbg(data, "EMR%d %08x\n", j, + edma_read_array(EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if (edma_read_array(EDMA_EMR, j) & (1 << i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(EDMA_EMCR, j, 1 << i); + /* Clear any SER */ + edma_shadow0_write_array(SH_SECR, j, + (1 << i)); + if (intr_data[k].callback) { + intr_data[k].callback(k, + DMA_CC_ERROR, + intr_data + [k].data); + } + } + } + } else if (edma_read(EDMA_QEMR)) { + dev_dbg(data, "QEMR %02x\n", + edma_read(EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(EDMA_QEMR) & (1 << i)) { + /* Clear the corresponding IPR bits */ + edma_write(EDMA_QEMCR, 1 << i); + edma_shadow0_write(SH_QSECR, (1 << i)); + + /* NOTE: not reported!! */ + } + } + } else if (edma_read(EDMA_CCERR)) { + dev_dbg(data, "CCERR %08x\n", + edma_read(EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... + */ + for (i = 0; i < 8; i++) { + if (edma_read(EDMA_CCERR) & (1 << i)) { + /* Clear the corresponding IPR bits */ + edma_write(EDMA_CCERRCLR, 1 << i); + + /* NOTE: not reported!! */ + } + } + } + if ((edma_read_array(EDMA_EMR, 0) == 0) + && (edma_read_array(EDMA_EMR, 1) == 0) + && (edma_read(EDMA_QEMR) == 0) + && (edma_read(EDMA_CCERR) == 0)) { + break; + } + cnt++; + if (cnt > 10) + break; + } + edma_write(EDMA_EEVAL, 1); + return IRQ_HANDLED; +} + +/****************************************************************************** + * + * Transfer controller error interrupt handlers + * + *****************************************************************************/ + +#define tc_errs_handled false /* disabled as long as they're NOPs */ + +static irqreturn_t dma_tc0err_handler(int irq, void *data) +{ + dev_dbg(data, "dma_tc0err_handler\n"); + return IRQ_HANDLED; +} + +static irqreturn_t dma_tc1err_handler(int irq, void *data) +{ + dev_dbg(data, "dma_tc1err_handler\n"); + return IRQ_HANDLED; +} + +/*-----------------------------------------------------------------------*/ + +/* Resource alloc/free: dma channels, parameter RAM slots */ + +/** + * edma_alloc_channel - allocate DMA channel and paired parameter RAM + * @channel: specific channel to allocate; negative for "any unmapped channel" + * @callback: optional; to be issued on DMA completion or errors + * @data: passed to callback + * @eventq_no: an EVENTQ_* constant, used to choose which Transfer + * Controller (TC) executes requests using this channel. Use + * EVENTQ_DEFAULT unless you really need a high priority queue. + * + * This allocates a DMA channel and its associated parameter RAM slot. + * The parameter RAM is initialized to hold a dummy transfer. + * + * Normal use is to pass a specific channel number as @channel, to make + * use of hardware events mapped to that channel. When the channel will + * be used only for software triggering or event chaining, channels not + * mapped to hardware events (or mapped to unused events) are preferable. + * + * DMA transfers start from a channel using edma_start(), or by + * chaining. When the transfer described in that channel's parameter RAM + * slot completes, that slot's data may be reloaded through a link. + * + * DMA errors are only reported to the @callback associated with the + * channel driving that transfer, but transfer completion callbacks can + * be sent to another channel under control of the TCC field in + * the option word of the transfer's parameter RAM set. Drivers must not + * use DMA transfer completion callbacks for channels they did not allocate. + * (The same applies to TCC codes used in transfer chaining.) + * + * Returns the number of the channel, else negative errno. + */ +int edma_alloc_channel(int channel, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data, + enum dma_event_q eventq_no) +{ + if (channel < 0) { + channel = 0; + for (;;) { + channel = find_next_bit(edma_noevent, + num_channels, channel); + if (channel == num_channels) + return -ENOMEM; + if (!test_and_set_bit(channel, edma_inuse)) + break; + channel++; + } + } else if (channel >= num_channels) { + return -EINVAL; + } else if (test_and_set_bit(channel, edma_inuse)) { + return -EBUSY; + } + + /* ensure access through shadow region 0 */ + edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); + + /* ensure no events are pending */ + edma_stop(channel); + memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), + &dummy_paramset, PARM_SIZE); + + if (callback) + setup_dma_interrupt(channel, callback, data); + + map_dmach_queue(channel, eventq_no); + + return channel; +} +EXPORT_SYMBOL(edma_alloc_channel); + + +/** + * edma_free_channel - deallocate DMA channel + * @channel: dma channel returned from edma_alloc_channel() + * + * This deallocates the DMA channel and associated parameter RAM slot + * allocated by edma_alloc_channel(). + * + * Callers are responsible for ensuring the channel is inactive, and + * will not be reactivated by linking, chaining, or software calls to + * edma_start(). + */ +void edma_free_channel(unsigned channel) +{ + if (channel >= num_channels) + return; + + setup_dma_interrupt(channel, NULL, NULL); + /* REVISIT should probably take out of shadow region 0 */ + + memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), + &dummy_paramset, PARM_SIZE); + clear_bit(channel, edma_inuse); +} +EXPORT_SYMBOL(edma_free_channel); + +/** + * edma_alloc_slot - allocate DMA parameter RAM + * @slot: specific slot to allocate; negative for "any unused slot" + * + * This allocates a parameter RAM slot, initializing it to hold a + * dummy transfer. Slots allocated using this routine have not been + * mapped to a hardware DMA channel, and will normally be used by + * linking to them from a slot associated with a DMA channel. + * + * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific + * slots may be allocated on behalf of DSP firmware. + * + * Returns the number of the slot, else negative errno. + */ +int edma_alloc_slot(int slot) +{ + if (slot < 0) { + slot = num_channels; + for (;;) { + slot = find_next_zero_bit(edma_inuse, + num_slots, slot); + if (slot == num_slots) + return -ENOMEM; + if (!test_and_set_bit(slot, edma_inuse)) + break; + } + } else if (slot < num_channels || slot >= num_slots) { + return -EINVAL; + } else if (test_and_set_bit(slot, edma_inuse)) { + return -EBUSY; + } + + memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), + &dummy_paramset, PARM_SIZE); + + return slot; +} +EXPORT_SYMBOL(edma_alloc_slot); + +/** + * edma_free_slot - deallocate DMA parameter RAM + * @slot: parameter RAM slot returned from edma_alloc_slot() + * + * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). + * Callers are responsible for ensuring the slot is inactive, and will + * not be activated. + */ +void edma_free_slot(unsigned slot) +{ + if (slot < num_channels || slot >= num_slots) + return; + + memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), + &dummy_paramset, PARM_SIZE); + clear_bit(slot, edma_inuse); +} +EXPORT_SYMBOL(edma_free_slot); + +/*-----------------------------------------------------------------------*/ + +/* Parameter RAM operations (i) -- read/write partial slots */ + +/** + * edma_set_src - set initial DMA source address in parameter RAM slot + * @slot: parameter RAM slot being configured + * @src_port: physical address of source (memory, controller FIFO, etc) + * @addressMode: INCR, except in very rare cases + * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * + * Note that the source address is modified during the DMA transfer + * according to edma_set_src_index(). + */ +void edma_set_src(unsigned slot, dma_addr_t src_port, + enum address_mode mode, enum fifo_width width) +{ + if (slot < num_slots) { + unsigned int i = edma_parm_read(PARM_OPT, slot); + + if (mode) { + /* set SAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); + } else { + /* clear SAM */ + i &= ~SAM; + } + edma_parm_write(PARM_OPT, slot, i); + + /* set the source port address + in source register of param structure */ + edma_parm_write(PARM_SRC, slot, src_port); + } +} +EXPORT_SYMBOL(edma_set_src); + +/** + * edma_set_dest - set initial DMA destination address in parameter RAM slot + * @slot: parameter RAM slot being configured + * @dest_port: physical address of destination (memory, controller FIFO, etc) + * @addressMode: INCR, except in very rare cases + * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * + * Note that the destination address is modified during the DMA transfer + * according to edma_set_dest_index(). + */ +void edma_set_dest(unsigned slot, dma_addr_t dest_port, + enum address_mode mode, enum fifo_width width) +{ + if (slot < num_slots) { + unsigned int i = edma_parm_read(PARM_OPT, slot); + + if (mode) { + /* set DAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); + } else { + /* clear DAM */ + i &= ~DAM; + } + edma_parm_write(PARM_OPT, slot, i); + /* set the destination port address + in dest register of param structure */ + edma_parm_write(PARM_DST, slot, dest_port); + } +} +EXPORT_SYMBOL(edma_set_dest); + +/** + * edma_get_position - returns the current transfer points + * @slot: parameter RAM slot being examined + * @src: pointer to source port position + * @dst: pointer to destination port position + * + * Returns current source and destination addresses for a particular + * parameter RAM slot. Its channel should not be active when this is called. + */ +void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) +{ + struct edmacc_param temp; + + edma_read_slot(slot, &temp); + if (src != NULL) + *src = temp.src; + if (dst != NULL) + *dst = temp.dst; +} +EXPORT_SYMBOL(edma_get_position); + +/** + * edma_set_src_index - configure DMA source address indexing + * @slot: parameter RAM slot being configured + * @src_bidx: byte offset between source arrays in a frame + * @src_cidx: byte offset between source frames in a block + * + * Offsets are specified to support either contiguous or discontiguous + * memory transfers, or repeated access to a hardware register, as needed. + * When accessing hardware registers, both offsets are normally zero. + */ +void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) +{ + if (slot < num_slots) { + edma_parm_modify(PARM_SRC_DST_BIDX, slot, + 0xffff0000, src_bidx); + edma_parm_modify(PARM_SRC_DST_CIDX, slot, + 0xffff0000, src_cidx); + } +} +EXPORT_SYMBOL(edma_set_src_index); + +/** + * edma_set_dest_index - configure DMA destination address indexing + * @slot: parameter RAM slot being configured + * @dest_bidx: byte offset between destination arrays in a frame + * @dest_cidx: byte offset between destination frames in a block + * + * Offsets are specified to support either contiguous or discontiguous + * memory transfers, or repeated access to a hardware register, as needed. + * When accessing hardware registers, both offsets are normally zero. + */ +void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) +{ + if (slot < num_slots) { + edma_parm_modify(PARM_SRC_DST_BIDX, slot, + 0x0000ffff, dest_bidx << 16); + edma_parm_modify(PARM_SRC_DST_CIDX, slot, + 0x0000ffff, dest_cidx << 16); + } +} +EXPORT_SYMBOL(edma_set_dest_index); + +/** + * edma_set_transfer_params - configure DMA transfer parameters + * @slot: parameter RAM slot being configured + * @acnt: how many bytes per array (at least one) + * @bcnt: how many arrays per frame (at least one) + * @ccnt: how many frames per block (at least one) + * @bcnt_rld: used only for A-Synchronized transfers; this specifies + * the value to reload into bcnt when it decrements to zero + * @sync_mode: ASYNC or ABSYNC + * + * See the EDMA3 documentation to understand how to configure and link + * transfers using the fields in PaRAM slots. If you are not doing it + * all at once with edma_write_slot(), you will use this routine + * plus two calls each for source and destination, setting the initial + * address and saying how to index that address. + * + * An example of an A-Synchronized transfer is a serial link using a + * single word shift register. In that case, @acnt would be equal to + * that word size; the serial controller issues a DMA synchronization + * event to transfer each word, and memory access by the DMA transfer + * controller will be word-at-a-time. + * + * An example of an AB-Synchronized transfer is a device using a FIFO. + * In that case, @acnt equals the FIFO width and @bcnt equals its depth. + * The controller with the FIFO issues DMA synchronization events when + * the FIFO threshold is reached, and the DMA transfer controller will + * transfer one frame to (or from) the FIFO. It will probably use + * efficient burst modes to access memory. + */ +void edma_set_transfer_params(unsigned slot, + u16 acnt, u16 bcnt, u16 ccnt, + u16 bcnt_rld, enum sync_dimension sync_mode) +{ + if (slot < num_slots) { + edma_parm_modify(PARM_LINK_BCNTRLD, slot, + 0x0000ffff, bcnt_rld << 16); + if (sync_mode == ASYNC) + edma_parm_and(PARM_OPT, slot, ~SYNCDIM); + else + edma_parm_or(PARM_OPT, slot, SYNCDIM); + /* Set the acount, bcount, ccount registers */ + edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt); + edma_parm_write(PARM_CCNT, slot, ccnt); + } +} +EXPORT_SYMBOL(edma_set_transfer_params); + +/** + * edma_link - link one parameter RAM slot to another + * @from: parameter RAM slot originating the link + * @to: parameter RAM slot which is the link target + * + * The originating slot should not be part of any active DMA transfer. + */ +void edma_link(unsigned from, unsigned to) +{ + if (from >= num_slots) + return; + if (to >= num_slots) + return; + edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to)); +} +EXPORT_SYMBOL(edma_link); + +/** + * edma_unlink - cut link from one parameter RAM slot + * @from: parameter RAM slot originating the link + * + * The originating slot should not be part of any active DMA transfer. + * Its link is set to 0xffff. + */ +void edma_unlink(unsigned from) +{ + if (from >= num_slots) + return; + edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff); +} +EXPORT_SYMBOL(edma_unlink); + +/*-----------------------------------------------------------------------*/ + +/* Parameter RAM operations (ii) -- read/write whole parameter sets */ + +/** + * edma_write_slot - write parameter RAM data for slot + * @slot: number of parameter RAM slot being modified + * @param: data to be written into parameter RAM slot + * + * Use this to assign all parameters of a transfer at once. This + * allows more efficient setup of transfers than issuing multiple + * calls to set up those parameters in small pieces, and provides + * complete control over all transfer options. + */ +void edma_write_slot(unsigned slot, const struct edmacc_param *param) +{ + if (slot >= num_slots) + return; + memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE); +} +EXPORT_SYMBOL(edma_write_slot); + +/** + * edma_read_slot - read parameter RAM data from slot + * @slot: number of parameter RAM slot being copied + * @param: where to store copy of parameter RAM data + * + * Use this to read data from a parameter RAM slot, perhaps to + * save them as a template for later reuse. + */ +void edma_read_slot(unsigned slot, struct edmacc_param *param) +{ + if (slot >= num_slots) + return; + memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE); +} +EXPORT_SYMBOL(edma_read_slot); + +/*-----------------------------------------------------------------------*/ + +/* Various EDMA channel control operations */ + +/** + * edma_pause - pause dma on a channel + * @channel: on which edma_start() has been called + * + * This temporarily disables EDMA hardware events on the specified channel, + * preventing them from triggering new transfers on its behalf + */ +void edma_pause(unsigned channel) +{ + if (channel < num_channels) { + unsigned int mask = (1 << (channel & 0x1f)); + + edma_shadow0_write_array(SH_EECR, channel >> 5, mask); + } +} +EXPORT_SYMBOL(edma_pause); + +/** + * edma_resume - resumes dma on a paused channel + * @channel: on which edma_pause() has been called + * + * This re-enables EDMA hardware events on the specified channel. + */ +void edma_resume(unsigned channel) +{ + if (channel < num_channels) { + unsigned int mask = (1 << (channel & 0x1f)); + + edma_shadow0_write_array(SH_EESR, channel >> 5, mask); + } +} +EXPORT_SYMBOL(edma_resume); + +/** + * edma_start - start dma on a channel + * @channel: channel being activated + * + * Channels with event associations will be triggered by their hardware + * events, and channels without such associations will be triggered by + * software. (At this writing there is no interface for using software + * triggers except with channels that don't support hardware triggers.) + * + * Returns zero on success, else negative errno. + */ +int edma_start(unsigned channel) +{ + if (channel < num_channels) { + int j = channel >> 5; + unsigned int mask = (1 << (channel & 0x1f)); + + /* EDMA channels without event association */ + if (test_bit(channel, edma_noevent)) { + pr_debug("EDMA: ESR%d %08x\n", j, + edma_shadow0_read_array(SH_ESR, j)); + edma_shadow0_write_array(SH_ESR, j, mask); + return 0; + } + + /* EDMA channel with event association */ + pr_debug("EDMA: ER%d %08x\n", j, + edma_shadow0_read_array(SH_ER, j)); + /* Clear any pending error */ + edma_write_array(EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(SH_SECR, j, mask); + edma_shadow0_write_array(SH_EESR, j, mask); + pr_debug("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(SH_EER, j)); + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL(edma_start); + +/** + * edma_stop - stops dma on the channel passed + * @channel: channel being deactivated + * + * When @lch is a channel, any active transfer is paused and + * all pending hardware events are cleared. The current transfer + * may not be resumed, and the channel's Parameter RAM should be + * reinitialized before being reused. + */ +void edma_stop(unsigned channel) +{ + if (channel < num_channels) { + int j = channel >> 5; + unsigned int mask = (1 << (channel & 0x1f)); + + edma_shadow0_write_array(SH_EECR, j, mask); + edma_shadow0_write_array(SH_ECR, j, mask); + edma_shadow0_write_array(SH_SECR, j, mask); + edma_write_array(EDMA_EMCR, j, mask); + + pr_debug("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(SH_EER, j)); + + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ + } +} +EXPORT_SYMBOL(edma_stop); + +/****************************************************************************** + * + * It cleans ParamEntry qand bring back EDMA to initial state if media has + * been removed before EDMA has finished.It is usedful for removable media. + * Arguments: + * ch_no - channel no + * + * Return: zero on success, or corresponding error no on failure + * + * FIXME this should not be needed ... edma_stop() should suffice. + * + *****************************************************************************/ + +void edma_clean_channel(unsigned channel) +{ + if (channel < num_channels) { + int j = (channel >> 5); + unsigned int mask = 1 << (channel & 0x1f); + + pr_debug("EDMA: EMR%d %08x\n", j, + edma_read_array(EDMA_EMR, j)); + edma_shadow0_write_array(SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(SH_SECR, j, mask); + edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3); + } +} +EXPORT_SYMBOL(edma_clean_channel); + +/* + * edma_clear_event - clear an outstanding event on the DMA channel + * Arguments: + * channel - channel number + */ +void edma_clear_event(unsigned channel) +{ + if (channel >= num_channels) + return; + if (channel < 32) + edma_write(EDMA_ECR, 1 << channel); + else + edma_write(EDMA_ECRH, 1 << (channel - 32)); +} +EXPORT_SYMBOL(edma_clear_event); + +/*-----------------------------------------------------------------------*/ + +static int __init edma_probe(struct platform_device *pdev) +{ + struct edma_soc_info *info = pdev->dev.platform_data; + int i; + int status; + const s8 *noevent; + int irq = 0, err_irq = 0; + struct resource *r; + resource_size_t len; + + if (!info) + return -ENODEV; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc"); + if (!r) + return -ENODEV; + + len = r->end - r->start + 1; + + r = request_mem_region(r->start, len, r->name); + if (!r) + return -EBUSY; + + edmacc_regs_base = ioremap(r->start, len); + if (!edmacc_regs_base) { + status = -EBUSY; + goto fail1; + } + + num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH); + num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY); + + dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base); + + for (i = 0; i < num_slots; i++) + memcpy_toio(edmacc_regs_base + PARM_OFFSET(i), + &dummy_paramset, PARM_SIZE); + + noevent = info->noevent; + if (noevent) { + while (*noevent != -1) + set_bit(*noevent++, edma_noevent); + } + + irq = platform_get_irq(pdev, 0); + status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + irq, status); + goto fail; + } + + err_irq = platform_get_irq(pdev, 1); + status = request_irq(err_irq, dma_ccerr_handler, 0, + "edma_error", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + err_irq, status); + goto fail; + } + + if (tc_errs_handled) { + status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0, + "edma_tc0", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + IRQ_TCERRINT0, status); + return status; + } + status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0, + "edma_tc1", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d --> %d\n", + IRQ_TCERRINT, status); + return status; + } + } + + /* Everything lives on transfer controller 1 until otherwise specified. + * This way, long transfers on the low priority queue + * started by the codec engine will not cause audio defects. + */ + for (i = 0; i < num_channels; i++) + map_dmach_queue(i, EVENTQ_1); + + /* Event queue to TC mapping */ + for (i = 0; queue_tc_mapping[i][0] != -1; i++) + map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]); + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + for (i = 0; i < info->n_region; i++) { + edma_write_array2(EDMA_DRAE, i, 0, 0x0); + edma_write_array2(EDMA_DRAE, i, 1, 0x0); + edma_write_array(EDMA_QRAE, i, 0x0); + } + + return 0; + +fail: + if (err_irq) + free_irq(err_irq, NULL); + if (irq) + free_irq(irq, NULL); + iounmap(edmacc_regs_base); +fail1: + release_mem_region(r->start, len); + return status; +} + + +static struct platform_driver edma_driver = { + .driver.name = "edma", +}; + +static int __init edma_init(void) +{ + return platform_driver_probe(&edma_driver, edma_probe); +} +arch_initcall(edma_init); + diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index b49e9d092aab..1aba41c6351e 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -20,6 +20,7 @@ #include <linux/irq.h> #include <linux/bitops.h> +#include <mach/cputype.h> #include <mach/irqs.h> #include <mach/hardware.h> #include <mach/gpio.h> @@ -36,9 +37,10 @@ struct davinci_gpio { static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; +static unsigned __initdata ngpio; /* create a non-inlined version */ -static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio) +static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) { return __gpio_to_controller(gpio); } @@ -114,9 +116,30 @@ static int __init davinci_gpio_setup(void) { int i, base; - for (i = 0, base = 0; - i < ARRAY_SIZE(chips); - i++, base += 32) { + /* The gpio banks conceptually expose a segmented bitmap, + * and "ngpio" is one more than the largest zero-based + * bit index that's valid. + */ + if (cpu_is_davinci_dm355()) { /* or dm335() */ + ngpio = 104; + } else if (cpu_is_davinci_dm644x()) { /* or dm337() */ + ngpio = 71; + } else if (cpu_is_davinci_dm646x()) { + /* NOTE: each bank has several "reserved" bits, + * unusable as GPIOs. Only 33 of the GPIO numbers + * are usable, and we're not rejecting the others. + */ + ngpio = 43; + } else { + /* if cpu_is_davinci_dm643x() ngpio = 111 */ + pr_err("GPIO setup: how many GPIOs?\n"); + return -EINVAL; + } + + if (WARN_ON(DAVINCI_N_GPIO < ngpio)) + ngpio = DAVINCI_N_GPIO; + + for (i = 0, base = 0; base < ngpio; i++, base += 32) { chips[i].chip.label = "DaVinci"; chips[i].chip.direction_input = davinci_direction_in; @@ -125,7 +148,7 @@ static int __init davinci_gpio_setup(void) chips[i].chip.set = davinci_gpio_set; chips[i].chip.base = base; - chips[i].chip.ngpio = DAVINCI_N_GPIO - base; + chips[i].chip.ngpio = ngpio - base; if (chips[i].chip.ngpio > 32) chips[i].chip.ngpio = 32; @@ -143,11 +166,11 @@ pure_initcall(davinci_gpio_setup); * We expect irqs will normally be set up as input pins, but they can also be * used as output pins ... which is convenient for testing. * - * NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition - * to their GPIOBNK0 irq (but with a bit less overhead). But we don't have - * a good way to hook those up ... + * NOTE: The first few GPIOs also have direct INTC hookups in addition + * to their GPIOBNK0 irq, with a bit less overhead but less flexibility + * on triggering (e.g. no edge options). We don't try to use those. * - * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also + * All those INTC hookups (direct, plus several IRQ banks) can also * serve as EDMA event triggers. */ @@ -235,29 +258,42 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) } /* - * NOTE: for suspend/resume, probably best to make a sysdev (and class) - * with its suspend/resume calls hooking into the results of the set_wake() + * NOTE: for suspend/resume, probably best to make a platform_device with + * suspend_late/resume_resume calls hooking into results of the set_wake() * calls ... so if no gpios are wakeup events the clock can be disabled, * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 - * can be set appropriately for GPIOV33 pins. + * (dm6446) can be set appropriately for GPIOV33 pins. */ static int __init davinci_gpio_irq_setup(void) { unsigned gpio, irq, bank; + unsigned bank_irq; struct clk *clk; + u32 binten = 0; + + if (cpu_is_davinci_dm355()) { /* or dm335() */ + bank_irq = IRQ_DM355_GPIOBNK0; + } else if (cpu_is_davinci_dm644x()) { + bank_irq = IRQ_GPIOBNK0; + } else if (cpu_is_davinci_dm646x()) { + bank_irq = IRQ_DM646X_GPIOBNK0; + } else { + printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); + return -EINVAL; + } clk = clk_get(NULL, "gpio"); if (IS_ERR(clk)) { printk(KERN_ERR "Error %ld getting gpio clock?\n", PTR_ERR(clk)); - return 0; + return PTR_ERR(clk); } - clk_enable(clk); - for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0; - gpio < DAVINCI_N_GPIO; bank++) { + for (gpio = 0, irq = gpio_to_irq(0), bank = 0; + gpio < ngpio; + bank++, bank_irq++) { struct gpio_controller *__iomem g = gpio2controller(gpio); unsigned i; @@ -265,28 +301,28 @@ static int __init davinci_gpio_irq_setup(void) __raw_writel(~0, &g->clr_rising); /* set up all irqs in this bank */ - set_irq_chained_handler(bank, gpio_irq_handler); - set_irq_chip_data(bank, g); - set_irq_data(bank, (void *)irq); + set_irq_chained_handler(bank_irq, gpio_irq_handler); + set_irq_chip_data(bank_irq, g); + set_irq_data(bank_irq, (void *)irq); - for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO; - i++, irq++, gpio++) { + for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { set_irq_chip(irq, &gpio_irqchip); set_irq_chip_data(irq, g); set_irq_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); } + + binten |= BIT(bank); } /* BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ - __raw_writel(0x1f, (void *__iomem) + __raw_writel(binten, (void *__iomem) IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); return 0; } - arch_initcall(davinci_gpio_irq_setup); diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c index bf067d604918..018b994cd794 100644 --- a/arch/arm/mach-davinci/id.c +++ b/arch/arm/mach-davinci/id.c @@ -15,7 +15,9 @@ #include <linux/init.h> #include <linux/io.h> -#define JTAG_ID_BASE 0x01c40028 +#define JTAG_ID_BASE IO_ADDRESS(0x01c40028) + +static unsigned int davinci_revision; struct davinci_id { u8 variant; /* JTAG ID bits 31:28 */ @@ -33,6 +35,20 @@ static struct davinci_id davinci_ids[] __initdata = { .manufacturer = 0x017, .type = 0x64460000, }, + { + /* DM646X */ + .part_no = 0xb770, + .variant = 0x0, + .manufacturer = 0x017, + .type = 0x64670000, + }, + { + /* DM355 */ + .part_no = 0xb73b, + .variant = 0x0, + .manufacturer = 0x00f, + .type = 0x03550000, + }, }; /* @@ -42,7 +58,7 @@ static u16 __init davinci_get_part_no(void) { u32 dev_id, part_no; - dev_id = davinci_readl(JTAG_ID_BASE); + dev_id = __raw_readl(JTAG_ID_BASE); part_no = ((dev_id >> 12) & 0xffff); @@ -56,13 +72,19 @@ static u8 __init davinci_get_variant(void) { u32 variant; - variant = davinci_readl(JTAG_ID_BASE); + variant = __raw_readl(JTAG_ID_BASE); variant = (variant >> 28) & 0xf; return variant; } +unsigned int davinci_rev(void) +{ + return davinci_revision >> 16; +} +EXPORT_SYMBOL(davinci_rev); + void __init davinci_check_revision(void) { int i; @@ -75,7 +97,7 @@ void __init davinci_check_revision(void) /* First check only the major version in a safe way */ for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { if (part_no == (davinci_ids[i].part_no)) { - system_rev = davinci_ids[i].type; + davinci_revision = davinci_ids[i].type; break; } } @@ -84,10 +106,11 @@ void __init davinci_check_revision(void) for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { if (part_no == davinci_ids[i].part_no && variant == davinci_ids[i].variant) { - system_rev = davinci_ids[i].type; + davinci_revision = davinci_ids[i].type; break; } } - printk("DaVinci DM%04x variant 0x%x\n", system_rev >> 16, variant); + printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n", + davinci_rev(), variant); } diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h new file mode 100644 index 000000000000..3216f21c1238 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h @@ -0,0 +1,20 @@ +/* + * DaVinci DM6446 EVM board specific headers + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or ifndef. + */ + +#ifndef _MACH_DAVINCI_DM6446EVM_H +#define _MACH_DAVINCI_DM6446EVM_H + +#include <linux/types.h> + +int dm6446evm_eeprom_read(char *buf, off_t off, size_t count); +int dm6446evm_eeprom_write(char *buf, off_t off, size_t count); + +#endif diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h new file mode 100644 index 000000000000..730c49d1ebd8 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/clkdev.h @@ -0,0 +1,13 @@ +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h index 38bdd49bc181..a3b040219876 100644 --- a/arch/arm/mach-davinci/include/mach/clock.h +++ b/arch/arm/mach-davinci/include/mach/clock.h @@ -17,6 +17,5 @@ struct clk; extern int clk_register(struct clk *clk); extern void clk_unregister(struct clk *clk); -extern int davinci_clk_init(void); #endif diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 4b522e5c70ec..191770976250 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -16,6 +16,12 @@ struct sys_timer; extern struct sys_timer davinci_timer; +extern void davinci_irq_init(void); +extern void davinci_map_common_io(void); + +/* parameters describe VBUS sourcing for host mode */ +extern void setup_usb(unsigned mA, unsigned potpgt_msec); + /* parameters describe VBUS sourcing for host mode */ extern void setup_usb(unsigned mA, unsigned potpgt_msec); diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h new file mode 100644 index 000000000000..27cfb1b3a662 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -0,0 +1,49 @@ +/* + * DaVinci CPU type detection + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Defines the cpu_is_*() macros for runtime detection of DaVinci + * device type. In addtion, if support for a given device is not + * compiled in to the kernel, the macros return 0 so that + * resulting code can be optimized out. + * + * 2009 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef _ASM_ARCH_CPU_H +#define _ASM_ARCH_CPU_H + +extern unsigned int davinci_rev(void); + +#define IS_DAVINCI_CPU(type, id) \ +static inline int is_davinci_dm ##type(void) \ +{ \ + return (davinci_rev() == (id)) ? 1 : 0; \ +} + +IS_DAVINCI_CPU(644x, 0x6446) +IS_DAVINCI_CPU(646x, 0x6467) +IS_DAVINCI_CPU(355, 0x355) + +#ifdef CONFIG_ARCH_DAVINCI_DM644x +#define cpu_is_davinci_dm644x() is_davinci_dm644x() +#else +#define cpu_is_davinci_dm644x() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DM646x +#define cpu_is_davinci_dm646x() is_davinci_dm646x() +#else +#define cpu_is_davinci_dm646x() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DM355 +#define cpu_is_davinci_dm355() is_davinci_dm355() +#else +#define cpu_is_davinci_dm355() 0 +#endif + +#endif diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h new file mode 100644 index 000000000000..3dcb9f4e58b4 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -0,0 +1,37 @@ +/* + * This file contains the processor specific definitions + * of the TI DM644x. + * + * Copyright (C) 2008 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __ASM_ARCH_DM644X_H +#define __ASM_ARCH_DM644X_H + +#include <linux/platform_device.h> +#include <mach/hardware.h> + +#define DM644X_EMAC_BASE (0x01C80000) +#define DM644X_EMAC_CNTRL_OFFSET (0x0000) +#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000) +#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000) +#define DM644X_EMAC_MDIO_OFFSET (0x4000) +#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) + +void __init dm644x_init(void); + +#endif /* __ASM_ARCH_DM644X_H */ diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h new file mode 100644 index 000000000000..f6fc5396dafc --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -0,0 +1,228 @@ +/* + * TI DAVINCI dma definitions + * + * Copyright (C) 2006-2009 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +/* + * This EDMA3 programming framework exposes two basic kinds of resource: + * + * Channel Triggers transfers, usually from a hardware event but + * also manually or by "chaining" from DMA completions. + * Each channel is coupled to a Parameter RAM (PaRAM) slot. + * + * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM + * "set"), source and destination addresses, a link to a + * next PaRAM slot (if any), options for the transfer, and + * instructions for updating those addresses. There are + * more than twice as many slots as event channels. + * + * Each PaRAM set describes a sequence of transfers, either for one large + * buffer or for several discontiguous smaller buffers. An EDMA transfer + * is driven only from a channel, which performs the transfers specified + * in its PaRAM slot until there are no more transfers. When that last + * transfer completes, the "link" field may be used to reload the channel's + * PaRAM slot with a new transfer descriptor. + * + * The EDMA Channel Controller (CC) maps requests from channels into physical + * Transfer Controller (TC) requests when the channel triggers (by hardware + * or software events, or by chaining). The two physical DMA channels provided + * by the TCs are thus shared by many logical channels. + * + * DaVinci hardware also has a "QDMA" mechanism which is not currently + * supported through this interface. (DSP firmware uses it though.) + */ + +#ifndef EDMA_H_ +#define EDMA_H_ + +/* PaRAM slots are laid out like this */ +struct edmacc_param { + unsigned int opt; + unsigned int src; + unsigned int a_b_cnt; + unsigned int dst; + unsigned int src_dst_bidx; + unsigned int link_bcntrld; + unsigned int src_dst_cidx; + unsigned int ccnt; +}; + +#define CCINT0_INTERRUPT 16 +#define CCERRINT_INTERRUPT 17 +#define TCERRINT0_INTERRUPT 18 +#define TCERRINT1_INTERRUPT 19 + +/* fields in edmacc_param.opt */ +#define SAM BIT(0) +#define DAM BIT(1) +#define SYNCDIM BIT(2) +#define STATIC BIT(3) +#define EDMA_FWID (0x07 << 8) +#define TCCMODE BIT(11) +#define EDMA_TCC(t) ((t) << 12) +#define TCINTEN BIT(20) +#define ITCINTEN BIT(21) +#define TCCHEN BIT(22) +#define ITCCHEN BIT(23) + +#define TRWORD (0x7<<2) +#define PAENTRY (0x1ff<<5) + +/* Drivers should avoid using these symbolic names for dm644x + * channels, and use platform_device IORESOURCE_DMA resources + * instead. (Other DaVinci chips have different peripherals + * and thus have different DMA channel mappings.) + */ +#define DAVINCI_DMA_MCBSP_TX 2 +#define DAVINCI_DMA_MCBSP_RX 3 +#define DAVINCI_DMA_VPSS_HIST 4 +#define DAVINCI_DMA_VPSS_H3A 5 +#define DAVINCI_DMA_VPSS_PRVU 6 +#define DAVINCI_DMA_VPSS_RSZ 7 +#define DAVINCI_DMA_IMCOP_IMXINT 8 +#define DAVINCI_DMA_IMCOP_VLCDINT 9 +#define DAVINCI_DMA_IMCO_PASQINT 10 +#define DAVINCI_DMA_IMCOP_DSQINT 11 +#define DAVINCI_DMA_SPI_SPIX 16 +#define DAVINCI_DMA_SPI_SPIR 17 +#define DAVINCI_DMA_UART0_URXEVT0 18 +#define DAVINCI_DMA_UART0_UTXEVT0 19 +#define DAVINCI_DMA_UART1_URXEVT1 20 +#define DAVINCI_DMA_UART1_UTXEVT1 21 +#define DAVINCI_DMA_UART2_URXEVT2 22 +#define DAVINCI_DMA_UART2_UTXEVT2 23 +#define DAVINCI_DMA_MEMSTK_MSEVT 24 +#define DAVINCI_DMA_MMCRXEVT 26 +#define DAVINCI_DMA_MMCTXEVT 27 +#define DAVINCI_DMA_I2C_ICREVT 28 +#define DAVINCI_DMA_I2C_ICXEVT 29 +#define DAVINCI_DMA_GPIO_GPINT0 32 +#define DAVINCI_DMA_GPIO_GPINT1 33 +#define DAVINCI_DMA_GPIO_GPINT2 34 +#define DAVINCI_DMA_GPIO_GPINT3 35 +#define DAVINCI_DMA_GPIO_GPINT4 36 +#define DAVINCI_DMA_GPIO_GPINT5 37 +#define DAVINCI_DMA_GPIO_GPINT6 38 +#define DAVINCI_DMA_GPIO_GPINT7 39 +#define DAVINCI_DMA_GPIO_GPBNKINT0 40 +#define DAVINCI_DMA_GPIO_GPBNKINT1 41 +#define DAVINCI_DMA_GPIO_GPBNKINT2 42 +#define DAVINCI_DMA_GPIO_GPBNKINT3 43 +#define DAVINCI_DMA_GPIO_GPBNKINT4 44 +#define DAVINCI_DMA_TIMER0_TINT0 48 +#define DAVINCI_DMA_TIMER1_TINT1 49 +#define DAVINCI_DMA_TIMER2_TINT2 50 +#define DAVINCI_DMA_TIMER3_TINT3 51 +#define DAVINCI_DMA_PWM0 52 +#define DAVINCI_DMA_PWM1 53 +#define DAVINCI_DMA_PWM2 54 + +/*ch_status paramater of callback function possible values*/ +#define DMA_COMPLETE 1 +#define DMA_CC_ERROR 2 +#define DMA_TC1_ERROR 3 +#define DMA_TC2_ERROR 4 + +enum address_mode { + INCR = 0, + FIFO = 1 +}; + +enum fifo_width { + W8BIT = 0, + W16BIT = 1, + W32BIT = 2, + W64BIT = 3, + W128BIT = 4, + W256BIT = 5 +}; + +enum dma_event_q { + EVENTQ_0 = 0, + EVENTQ_1 = 1, + EVENTQ_DEFAULT = -1 +}; + +enum sync_dimension { + ASYNC = 0, + ABSYNC = 1 +}; + +#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ +#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ + +/* alloc/free DMA channels and their dedicated parameter RAM slots */ +int edma_alloc_channel(int channel, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data, enum dma_event_q); +void edma_free_channel(unsigned channel); + +/* alloc/free parameter RAM slots */ +int edma_alloc_slot(int slot); +void edma_free_slot(unsigned slot); + +/* calls that operate on part of a parameter RAM slot */ +void edma_set_src(unsigned slot, dma_addr_t src_port, + enum address_mode mode, enum fifo_width); +void edma_set_dest(unsigned slot, dma_addr_t dest_port, + enum address_mode mode, enum fifo_width); +void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst); +void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); +void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); +void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, + u16 bcnt_rld, enum sync_dimension sync_mode); +void edma_link(unsigned from, unsigned to); +void edma_unlink(unsigned from); + +/* calls that operate on an entire parameter RAM slot */ +void edma_write_slot(unsigned slot, const struct edmacc_param *params); +void edma_read_slot(unsigned slot, struct edmacc_param *params); + +/* channel control operations */ +int edma_start(unsigned channel); +void edma_stop(unsigned channel); +void edma_clean_channel(unsigned channel); +void edma_clear_event(unsigned channel); +void edma_pause(unsigned channel); +void edma_resume(unsigned channel); + +/* UNRELATED TO DMA */ +int davinci_alloc_iram(unsigned size); +void davinci_free_iram(unsigned addr, unsigned size); + +/* platform_data for EDMA driver */ +struct edma_soc_info { + + /* how many dma resources of each type */ + unsigned n_channel; + unsigned n_region; + unsigned n_slot; + unsigned n_tc; + + /* list of channels with no even trigger; terminated by "-1" */ + const s8 *noevent; +}; + +#endif diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index b456f079f43f..efe3281364e6 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -15,9 +15,11 @@ #include <linux/io.h> #include <asm-generic/gpio.h> -#include <mach/hardware.h> + #include <mach/irqs.h> +#define DAVINCI_GPIO_BASE 0x01C67000 + /* * basic gpio routines * @@ -26,23 +28,18 @@ * go through boot loaders. * * the gpio clock will be turned on when gpios are used, and you may also - * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are + * need to pay attention to PINMUX registers to be sure those pins are * used as gpios, not with other peripherals. * * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, - * and maybe for later updates, code should write GPIO(N) or: - * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) - * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) - * - * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc - * for now, that's != GPIO(N) + * and maybe for later updates, code may write GPIO(N). These may be + * all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip + * may not support all the GPIOs in that range. * * GPIOs can also be on external chips, numbered after the ones built-in * to the DaVinci chip. For now, they won't be usable as IRQ sources. */ -#define GPIO(X) (X) /* 0 <= X <= 70 */ -#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ -#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ +#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ struct gpio_controller { u32 dir; @@ -71,12 +68,14 @@ __gpio_to_controller(unsigned gpio) { void *__iomem ptr; - if (gpio < 32) + if (gpio < 32 * 1) ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); - else if (gpio < 64) + else if (gpio < 32 * 2) ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); - else if (gpio < DAVINCI_N_GPIO) + else if (gpio < 32 * 3) ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); + else if (gpio < 32 * 4) + ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88); else ptr = NULL; return ptr; diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index a2e8969afaca..48c77934d519 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -1,9 +1,9 @@ /* - * Common hardware definitions + * Hardware definitions common to all DaVinci family processors * - * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * Author: Kevin Hilman, Deep Root Systems, LLC * - * 2007 (c) MontaVista Software, Inc. This file is licensed under + * 2007 (c) Deep Root Systems, LLC. This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. @@ -12,41 +12,16 @@ #define __ASM_ARCH_HARDWARE_H /* - * Base register addresses + * Before you add anything to ths file: + * + * This header is for defines common to ALL DaVinci family chips. + * Anything that is chip specific should go in <chipname>.h, + * and the chip/board init code should then explicitly include + * <chipname>.h */ -#define DAVINCI_DMA_3PCC_BASE (0x01C00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) -#define DAVINCI_I2C_BASE (0x01C21000) -#define DAVINCI_PWM0_BASE (0x01C22000) -#define DAVINCI_PWM1_BASE (0x01C22400) -#define DAVINCI_PWM2_BASE (0x01C22800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) -#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) -#define DAVINCI_IEEE1394_BASE (0x01C60000) -#define DAVINCI_USB_OTG_BASE (0x01C64000) -#define DAVINCI_CFC_ATA_BASE (0x01C66000) -#define DAVINCI_SPI_BASE (0x01C66800) -#define DAVINCI_GPIO_BASE (0x01C67000) -#define DAVINCI_UHPI_BASE (0x01C67800) -#define DAVINCI_VPSS_REGS_BASE (0x01C70000) -#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) -#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) -#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) -#define DAVINCI_IMCOP_BASE (0x01CC0000) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) -#define DAVINCI_VLYNQ_BASE (0x01E01000) -#define DAVINCI_MCBSP_BASE (0x01E02000) -#define DAVINCI_MMC_SD_BASE (0x01E10000) -#define DAVINCI_MS_BASE (0x01E20000) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) +#define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000 + +/* System control register offsets */ +#define DM64XX_VDD3P3V_PWDN 0x48 #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h index a48795fd2417..2479785405af 100644 --- a/arch/arm/mach-davinci/include/mach/io.h +++ b/arch/arm/mach-davinci/include/mach/io.h @@ -40,22 +40,12 @@ #else #define IOMEM(x) ((void __force __iomem *)(x)) -/* - * Functions to access the DaVinci IO region - * - * NOTE: - Use davinci_read/write[bwl] for physical register addresses - * - Use __raw_read/write[bwl]() for virtual register addresses - * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses - * - DO NOT use hardcoded virtual addresses to allow changing the - * IO address space again if needed - */ -#define davinci_readb(a) __raw_readb(IO_ADDRESS(a)) -#define davinci_readw(a) __raw_readw(IO_ADDRESS(a)) -#define davinci_readl(a) __raw_readl(IO_ADDRESS(a)) +#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) +#define __arch_iounmap(v) davinci_iounmap(v) -#define davinci_writeb(v, a) __raw_writeb(v, IO_ADDRESS(a)) -#define davinci_writew(v, a) __raw_writew(v, IO_ADDRESS(a)) -#define davinci_writel(v, a) __raw_writel(v, IO_ADDRESS(a)) +void __iomem *davinci_ioremap(unsigned long phys, size_t size, + unsigned int type); +void davinci_iounmap(volatile void __iomem *addr); #endif /* __ASSEMBLER__ */ #endif /* __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index f4c5ca6da9f4..18066074c995 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -96,10 +96,111 @@ #define IRQ_EMUINT 63 #define DAVINCI_N_AINTC_IRQ 64 -#define DAVINCI_N_GPIO 71 +#define DAVINCI_N_GPIO 104 #define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 +/* DaVinci DM6467-specific Interrupts */ +#define IRQ_DM646X_VP_VERTINT0 0 +#define IRQ_DM646X_VP_VERTINT1 1 +#define IRQ_DM646X_VP_VERTINT2 2 +#define IRQ_DM646X_VP_VERTINT3 3 +#define IRQ_DM646X_VP_ERRINT 4 +#define IRQ_DM646X_RESERVED_1 5 +#define IRQ_DM646X_RESERVED_2 6 +#define IRQ_DM646X_WDINT 7 +#define IRQ_DM646X_CRGENINT0 8 +#define IRQ_DM646X_CRGENINT1 9 +#define IRQ_DM646X_TSIFINT0 10 +#define IRQ_DM646X_TSIFINT1 11 +#define IRQ_DM646X_VDCEINT 12 +#define IRQ_DM646X_USBINT 13 +#define IRQ_DM646X_USBDMAINT 14 +#define IRQ_DM646X_PCIINT 15 +#define IRQ_DM646X_TCERRINT2 20 +#define IRQ_DM646X_TCERRINT3 21 +#define IRQ_DM646X_IDE 22 +#define IRQ_DM646X_HPIINT 23 +#define IRQ_DM646X_EMACRXTHINT 24 +#define IRQ_DM646X_EMACRXINT 25 +#define IRQ_DM646X_EMACTXINT 26 +#define IRQ_DM646X_EMACMISCINT 27 +#define IRQ_DM646X_MCASP0TXINT 28 +#define IRQ_DM646X_MCASP0RXINT 29 +#define IRQ_DM646X_RESERVED_3 31 +#define IRQ_DM646X_MCASP1TXINT 32 +#define IRQ_DM646X_VLQINT 38 +#define IRQ_DM646X_UARTINT2 42 +#define IRQ_DM646X_SPINT0 43 +#define IRQ_DM646X_SPINT1 44 +#define IRQ_DM646X_DSP2ARMINT 45 +#define IRQ_DM646X_RESERVED_4 46 +#define IRQ_DM646X_PSCINT 47 +#define IRQ_DM646X_GPIO0 48 +#define IRQ_DM646X_GPIO1 49 +#define IRQ_DM646X_GPIO2 50 +#define IRQ_DM646X_GPIO3 51 +#define IRQ_DM646X_GPIO4 52 +#define IRQ_DM646X_GPIO5 53 +#define IRQ_DM646X_GPIO6 54 +#define IRQ_DM646X_GPIO7 55 +#define IRQ_DM646X_GPIOBNK0 56 +#define IRQ_DM646X_GPIOBNK1 57 +#define IRQ_DM646X_GPIOBNK2 58 +#define IRQ_DM646X_DDRINT 59 +#define IRQ_DM646X_AEMIFINT 60 + +/* DaVinci DM355-specific Interrupts */ +#define IRQ_DM355_CCDC_VDINT0 0 +#define IRQ_DM355_CCDC_VDINT1 1 +#define IRQ_DM355_CCDC_VDINT2 2 +#define IRQ_DM355_IPIPE_HST 3 +#define IRQ_DM355_H3AINT 4 +#define IRQ_DM355_IPIPE_SDR 5 +#define IRQ_DM355_IPIPEIFINT 6 +#define IRQ_DM355_OSDINT 7 +#define IRQ_DM355_VENCINT 8 +#define IRQ_DM355_IMCOPINT 11 +#define IRQ_DM355_RTOINT 13 +#define IRQ_DM355_TINT4 13 +#define IRQ_DM355_TINT2_TINT12 13 +#define IRQ_DM355_UARTINT2 14 +#define IRQ_DM355_TINT5 14 +#define IRQ_DM355_TINT2_TINT34 14 +#define IRQ_DM355_TINT6 15 +#define IRQ_DM355_TINT3_TINT12 15 +#define IRQ_DM355_SPINT1_0 17 +#define IRQ_DM355_SPINT1_1 18 +#define IRQ_DM355_SPINT2_0 19 +#define IRQ_DM355_SPINT2_1 21 +#define IRQ_DM355_TINT7 22 +#define IRQ_DM355_TINT3_TINT34 22 +#define IRQ_DM355_SDIOINT0 23 +#define IRQ_DM355_MMCINT0 26 +#define IRQ_DM355_MSINT 26 +#define IRQ_DM355_MMCINT1 27 +#define IRQ_DM355_PWMINT3 28 +#define IRQ_DM355_SDIOINT1 31 +#define IRQ_DM355_SPINT0_0 42 +#define IRQ_DM355_SPINT0_1 43 +#define IRQ_DM355_GPIO0 44 +#define IRQ_DM355_GPIO1 45 +#define IRQ_DM355_GPIO2 46 +#define IRQ_DM355_GPIO3 47 +#define IRQ_DM355_GPIO4 48 +#define IRQ_DM355_GPIO5 49 +#define IRQ_DM355_GPIO6 50 +#define IRQ_DM355_GPIO7 51 +#define IRQ_DM355_GPIO8 52 +#define IRQ_DM355_GPIO9 53 +#define IRQ_DM355_GPIOBNK0 54 +#define IRQ_DM355_GPIOBNK1 55 +#define IRQ_DM355_GPIOBNK2 56 +#define IRQ_DM355_GPIOBNK3 57 +#define IRQ_DM355_GPIOBNK4 58 +#define IRQ_DM355_GPIOBNK5 59 +#define IRQ_DM355_GPIOBNK6 60 + #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index c24b6782804d..bae22cb3e27b 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -1,55 +1,183 @@ /* - * DaVinci pin multiplexing defines + * Table of the DAVINCI register configurations for the PINMUX combinations * * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> * + * Based on linux/include/asm-arm/arch-omap/mux.h: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * * 2007 (c) MontaVista Software, Inc. This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. + * + * Copyright (C) 2008 Texas Instruments. */ -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -#define DAVINCI_MUX_AEAW0 0 -#define DAVINCI_MUX_AEAW1 1 -#define DAVINCI_MUX_AEAW2 2 -#define DAVINCI_MUX_AEAW3 3 -#define DAVINCI_MUX_AEAW4 4 -#define DAVINCI_MUX_AECS4 10 -#define DAVINCI_MUX_AECS5 11 -#define DAVINCI_MUX_VLYNQWD0 12 -#define DAVINCI_MUX_VLYNQWD1 13 -#define DAVINCI_MUX_VLSCREN 14 -#define DAVINCI_MUX_VLYNQEN 15 -#define DAVINCI_MUX_HDIREN 16 -#define DAVINCI_MUX_ATAEN 17 -#define DAVINCI_MUX_RGB666 22 -#define DAVINCI_MUX_RGB888 23 -#define DAVINCI_MUX_LOEEN 24 -#define DAVINCI_MUX_LFLDEN 25 -#define DAVINCI_MUX_CWEN 26 -#define DAVINCI_MUX_CFLDEN 27 -#define DAVINCI_MUX_HPIEN 29 -#define DAVINCI_MUX_1394EN 30 -#define DAVINCI_MUX_EMACEN 31 - -#define DAVINCI_MUX_LEVEL2 32 -#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) -#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) -#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) -#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) -#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) -#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) -#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) -#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) -#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) -#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) -#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) -#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) -#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) -#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) - -extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); - -#endif /* __ASM_ARCH_MUX_H */ + +#ifndef __INC_MACH_MUX_H +#define __INC_MACH_MUX_H + +/* System module registers */ +#define PINMUX0 0x00 +#define PINMUX1 0x04 +/* dm355 only */ +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define INTMUX 0x18 +#define EVTMUX 0x1c + +struct mux_config { + const char *name; + const char *mux_reg_name; + const unsigned char mux_reg; + const unsigned char mask_offset; + const unsigned char mask; + const unsigned char mode; + bool debug; +}; + +enum davinci_dm644x_index { + /* ATA and HDDIR functions */ + DM644X_HDIREN, + DM644X_ATAEN, + DM644X_ATAEN_DISABLE, + + /* HPI functions */ + DM644X_HPIEN_DISABLE, + + /* AEAW functions */ + DM644X_AEAW, + + /* Memory Stick */ + DM644X_MSTK, + + /* I2C */ + DM644X_I2C, + + /* ASP function */ + DM644X_MCBSP, + + /* UART1 */ + DM644X_UART1, + + /* UART2 */ + DM644X_UART2, + + /* PWM0 */ + DM644X_PWM0, + + /* PWM1 */ + DM644X_PWM1, + + /* PWM2 */ + DM644X_PWM2, + + /* VLYNQ function */ + DM644X_VLYNQEN, + DM644X_VLSCREN, + DM644X_VLYNQWD, + + /* EMAC and MDIO function */ + DM644X_EMACEN, + + /* GPIO3V[0:16] pins */ + DM644X_GPIO3V, + + /* GPIO pins */ + DM644X_GPIO0, + DM644X_GPIO3, + DM644X_GPIO43_44, + DM644X_GPIO46_47, + + /* VPBE */ + DM644X_RGB666, + + /* LCD */ + DM644X_LOEEN, + DM644X_LFLDEN, +}; + +enum davinci_dm646x_index { + /* ATA function */ + DM646X_ATAEN, + + /* AUDIO Clock */ + DM646X_AUDCK1, + DM646X_AUDCK0, + + /* CRGEN Control */ + DM646X_CRGMUX, + + /* VPIF Control */ + DM646X_STSOMUX_DISABLE, + DM646X_STSIMUX_DISABLE, + DM646X_PTSOMUX_DISABLE, + DM646X_PTSIMUX_DISABLE, + + /* TSIF Control */ + DM646X_STSOMUX, + DM646X_STSIMUX, + DM646X_PTSOMUX_PARALLEL, + DM646X_PTSIMUX_PARALLEL, + DM646X_PTSOMUX_SERIAL, + DM646X_PTSIMUX_SERIAL, +}; + +enum davinci_dm355_index { + /* MMC/SD 0 */ + DM355_MMCSD0, + + /* MMC/SD 1 */ + DM355_SD1_CLK, + DM355_SD1_CMD, + DM355_SD1_DATA3, + DM355_SD1_DATA2, + DM355_SD1_DATA1, + DM355_SD1_DATA0, + + /* I2C */ + DM355_I2C_SDA, + DM355_I2C_SCL, + + /* ASP0 function */ + DM355_MCBSP0_BDX, + DM355_MCBSP0_X, + DM355_MCBSP0_BFSX, + DM355_MCBSP0_BDR, + DM355_MCBSP0_R, + DM355_MCBSP0_BFSR, + + /* SPI0 */ + DM355_SPI0_SDI, + DM355_SPI0_SDENA0, + DM355_SPI0_SDENA1, + + /* IRQ muxing */ + DM355_INT_EDMA_CC, + DM355_INT_EDMA_TC0_ERR, + DM355_INT_EDMA_TC1_ERR, + + /* EDMA event muxing */ + DM355_EVT8_ASP1_TX, + DM355_EVT9_ASP1_RX, + DM355_EVT26_MMC0_RX, +}; + +#ifdef CONFIG_DAVINCI_MUX +/* setup pin muxing */ +extern void davinci_mux_init(void); +extern int davinci_mux_register(const struct mux_config *pins, + unsigned long size); +extern int davinci_cfg_reg(unsigned long reg_cfg); +#else +/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ +static inline void davinci_mux_init(void) {} +static inline int davinci_mux_register(const struct mux_config *pins, + unsigned long size) { return 0; } +static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } +#endif + +#endif /* __INC_MACH_MUX_H */ diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 4977aa071e1e..55a90d419fac 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -38,8 +38,6 @@ #define DAVINCI_LPSC_TPTC1 4 #define DAVINCI_LPSC_EMAC 5 #define DAVINCI_LPSC_EMAC_WRAPPER 6 -#define DAVINCI_LPSC_MDIO 7 -#define DAVINCI_LPSC_IEEE1394 8 #define DAVINCI_LPSC_USB 9 #define DAVINCI_LPSC_ATA 10 #define DAVINCI_LPSC_VLYNQ 11 @@ -47,7 +45,6 @@ #define DAVINCI_LPSC_DDR_EMIF 13 #define DAVINCI_LPSC_AEMIF 14 #define DAVINCI_LPSC_MMC_SD 15 -#define DAVINCI_LPSC_MEMSTICK 16 #define DAVINCI_LPSC_McBSP 17 #define DAVINCI_LPSC_I2C 18 #define DAVINCI_LPSC_UART0 19 @@ -73,4 +70,54 @@ #define DAVINCI_LPSC_GEM 39 #define DAVINCI_LPSC_IMCOP 40 +#define DM355_LPSC_TIMER3 5 +#define DM355_LPSC_SPI1 6 +#define DM355_LPSC_MMC_SD1 7 +#define DM355_LPSC_McBSP1 8 +#define DM355_LPSC_PWM3 10 +#define DM355_LPSC_SPI2 11 +#define DM355_LPSC_RTO 12 +#define DM355_LPSC_VPSS_DAC 41 + +/* + * LPSC Assignments + */ +#define DM646X_LPSC_ARM 0 +#define DM646X_LPSC_C64X_CPU 1 +#define DM646X_LPSC_HDVICP0 2 +#define DM646X_LPSC_HDVICP1 3 +#define DM646X_LPSC_TPCC 4 +#define DM646X_LPSC_TPTC0 5 +#define DM646X_LPSC_TPTC1 6 +#define DM646X_LPSC_TPTC2 7 +#define DM646X_LPSC_TPTC3 8 +#define DM646X_LPSC_PCI 13 +#define DM646X_LPSC_EMAC 14 +#define DM646X_LPSC_VDCE 15 +#define DM646X_LPSC_VPSSMSTR 16 +#define DM646X_LPSC_VPSSSLV 17 +#define DM646X_LPSC_TSIF0 18 +#define DM646X_LPSC_TSIF1 19 +#define DM646X_LPSC_DDR_EMIF 20 +#define DM646X_LPSC_AEMIF 21 +#define DM646X_LPSC_McASP0 22 +#define DM646X_LPSC_McASP1 23 +#define DM646X_LPSC_CRGEN0 24 +#define DM646X_LPSC_CRGEN1 25 +#define DM646X_LPSC_UART0 26 +#define DM646X_LPSC_UART1 27 +#define DM646X_LPSC_UART2 28 +#define DM646X_LPSC_PWM0 29 +#define DM646X_LPSC_PWM1 30 +#define DM646X_LPSC_I2C 31 +#define DM646X_LPSC_SPI 32 +#define DM646X_LPSC_GPIO 33 +#define DM646X_LPSC_TIMER0 34 +#define DM646X_LPSC_TIMER1 35 +#define DM646X_LPSC_ARM_INTC 45 + +extern int davinci_psc_is_clk_active(unsigned int id); +extern void davinci_psc_config(unsigned int domain, unsigned int id, + char enable); + #endif /* __ASM_ARCH_PSC_H */ diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index fb8cb229bfd2..632847d74a1c 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -13,8 +13,23 @@ #include <mach/io.h> -#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) -#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) -#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) +#define DAVINCI_MAX_NR_UARTS 3 +#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) +#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) +#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) + +#define DM355_UART2_BASE (IO_PHYS + 0x206000) + +/* DaVinci UART register offsets */ +#define UART_DAVINCI_PWREMU 0x0c +#define UART_DM646X_SCR 0x10 +#define UART_DM646X_SCR_TX_WATERMARK 0x08 + +struct davinci_uart_config { + /* Bit field of UARTs present; bit 0 --> UART1 */ + unsigned int enabled_uarts; +}; + +extern void davinci_serial_init(struct davinci_uart_config *); #endif /* __ASM_ARCH_SERIAL_H */ diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c index 299515f70b8b..a548abb513e2 100644 --- a/arch/arm/mach-davinci/io.c +++ b/arch/arm/mach-davinci/io.c @@ -51,7 +51,26 @@ void __init davinci_map_common_io(void) davinci_check_revision(); } -void __init davinci_init_common_hw(void) +#define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) +#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst))) + +/* + * Intercept ioremap() requests for addresses in our fixed mapping regions. + */ +void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type) +{ + if (BETWEEN(p, IO_PHYS, IO_SIZE)) + return XLATE(p, IO_PHYS, IO_VIRT); + + return __arm_ioremap(p, size, type); +} +EXPORT_SYMBOL(davinci_ioremap); + +void davinci_iounmap(volatile void __iomem *addr) { - davinci_clk_init(); + unsigned long virt = (unsigned long)addr; + + if (virt >= VMALLOC_START && virt < VMALLOC_END) + __iounmap(addr); } +EXPORT_SYMBOL(davinci_iounmap); diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 38021af8359a..5a324c90e291 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -25,6 +25,7 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <mach/cputype.h> #include <asm/mach/irq.h> #define IRQ_BIT(irq) ((irq) & 0x1f) @@ -40,14 +41,18 @@ #define IRQ_INTPRI0_REG_OFFSET 0x0030 #define IRQ_INTPRI7_REG_OFFSET 0x004C +const u8 *davinci_def_priorities; + +#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE) + static inline unsigned int davinci_irq_readl(int offset) { - return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); + return __raw_readl(INTC_BASE + offset); } static inline void davinci_irq_writel(unsigned long value, int offset) { - davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); + __raw_writel(value, INTC_BASE + offset); } /* Disable interrupt */ @@ -108,9 +113,8 @@ static struct irq_chip davinci_irq_chip_0 = { .unmask = davinci_unmask_irq, }; - /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ -static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { +static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { [IRQ_VDINT0] = 2, [IRQ_VDINT1] = 6, [IRQ_VDINT2] = 6, @@ -177,11 +181,149 @@ static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { [IRQ_EMUINT] = 7, }; +static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_DM646X_VP_VERTINT0] = 7, + [IRQ_DM646X_VP_VERTINT1] = 7, + [IRQ_DM646X_VP_VERTINT2] = 7, + [IRQ_DM646X_VP_VERTINT3] = 7, + [IRQ_DM646X_VP_ERRINT] = 7, + [IRQ_DM646X_RESERVED_1] = 7, + [IRQ_DM646X_RESERVED_2] = 7, + [IRQ_DM646X_WDINT] = 7, + [IRQ_DM646X_CRGENINT0] = 7, + [IRQ_DM646X_CRGENINT1] = 7, + [IRQ_DM646X_TSIFINT0] = 7, + [IRQ_DM646X_TSIFINT1] = 7, + [IRQ_DM646X_VDCEINT] = 7, + [IRQ_DM646X_USBINT] = 7, + [IRQ_DM646X_USBDMAINT] = 7, + [IRQ_DM646X_PCIINT] = 7, + [IRQ_CCINT0] = 7, /* dma */ + [IRQ_CCERRINT] = 7, /* dma */ + [IRQ_TCERRINT0] = 7, /* dma */ + [IRQ_TCERRINT] = 7, /* dma */ + [IRQ_DM646X_TCERRINT2] = 7, + [IRQ_DM646X_TCERRINT3] = 7, + [IRQ_DM646X_IDE] = 7, + [IRQ_DM646X_HPIINT] = 7, + [IRQ_DM646X_EMACRXTHINT] = 7, + [IRQ_DM646X_EMACRXINT] = 7, + [IRQ_DM646X_EMACTXINT] = 7, + [IRQ_DM646X_EMACMISCINT] = 7, + [IRQ_DM646X_MCASP0TXINT] = 7, + [IRQ_DM646X_MCASP0RXINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_DM646X_RESERVED_3] = 7, + [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ + [IRQ_TINT0_TINT34] = 7, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_DM646X_VLQINT] = 7, + [IRQ_I2C] = 7, + [IRQ_UARTINT0] = 7, + [IRQ_UARTINT1] = 7, + [IRQ_DM646X_UARTINT2] = 7, + [IRQ_DM646X_SPINT0] = 7, + [IRQ_DM646X_SPINT1] = 7, + [IRQ_DM646X_DSP2ARMINT] = 7, + [IRQ_DM646X_RESERVED_4] = 7, + [IRQ_DM646X_PSCINT] = 7, + [IRQ_DM646X_GPIO0] = 7, + [IRQ_DM646X_GPIO1] = 7, + [IRQ_DM646X_GPIO2] = 7, + [IRQ_DM646X_GPIO3] = 7, + [IRQ_DM646X_GPIO4] = 7, + [IRQ_DM646X_GPIO5] = 7, + [IRQ_DM646X_GPIO6] = 7, + [IRQ_DM646X_GPIO7] = 7, + [IRQ_DM646X_GPIOBNK0] = 7, + [IRQ_DM646X_GPIOBNK1] = 7, + [IRQ_DM646X_GPIOBNK2] = 7, + [IRQ_DM646X_DDRINT] = 7, + [IRQ_DM646X_AEMIFINT] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + +static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_DM355_CCDC_VDINT0] = 2, + [IRQ_DM355_CCDC_VDINT1] = 6, + [IRQ_DM355_CCDC_VDINT2] = 6, + [IRQ_DM355_IPIPE_HST] = 6, + [IRQ_DM355_H3AINT] = 6, + [IRQ_DM355_IPIPE_SDR] = 6, + [IRQ_DM355_IPIPEIFINT] = 6, + [IRQ_DM355_OSDINT] = 7, + [IRQ_DM355_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_DM355_RTOINT] = 4, + [IRQ_DM355_UARTINT2] = 7, + [IRQ_DM355_TINT6] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_CCERRINT] = 5, /* dma */ + [IRQ_TCERRINT0] = 5, /* dma */ + [IRQ_TCERRINT] = 5, /* dma */ + [IRQ_DM355_SPINT2_1] = 7, + [IRQ_DM355_TINT7] = 4, + [IRQ_DM355_SDIOINT0] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_DM355_MMCINT1] = 7, + [IRQ_DM355_PWMINT3] = 7, + [IRQ_DDRINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_DM355_SDIOINT1] = 4, + [IRQ_TINT0_TINT12] = 2, /* clockevent */ + [IRQ_TINT0_TINT34] = 2, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_PWMINT2] = 7, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM355_SPINT0_0] = 3, + [IRQ_DM355_SPINT0_1] = 3, + [IRQ_DM355_GPIO0] = 3, + [IRQ_DM355_GPIO1] = 7, + [IRQ_DM355_GPIO2] = 4, + [IRQ_DM355_GPIO3] = 4, + [IRQ_DM355_GPIO4] = 7, + [IRQ_DM355_GPIO5] = 7, + [IRQ_DM355_GPIO6] = 7, + [IRQ_DM355_GPIO7] = 7, + [IRQ_DM355_GPIO8] = 7, + [IRQ_DM355_GPIO9] = 7, + [IRQ_DM355_GPIOBNK0] = 7, + [IRQ_DM355_GPIOBNK1] = 7, + [IRQ_DM355_GPIOBNK2] = 7, + [IRQ_DM355_GPIOBNK3] = 7, + [IRQ_DM355_GPIOBNK4] = 7, + [IRQ_DM355_GPIOBNK5] = 7, + [IRQ_DM355_GPIOBNK6] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + /* ARM Interrupt Controller Initialization */ void __init davinci_irq_init(void) { unsigned i; - const u8 *priority = default_priorities; + + if (cpu_is_davinci_dm644x()) + davinci_def_priorities = dm644x_default_priorities; + else if (cpu_is_davinci_dm646x()) + davinci_def_priorities = dm646x_default_priorities; + else if (cpu_is_davinci_dm355()) + davinci_def_priorities = dm355_default_priorities; /* Clear all interrupt requests */ davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); @@ -209,8 +351,8 @@ void __init davinci_irq_init(void) unsigned j; u32 pri; - for (j = 0, pri = 0; j < 32; j += 4, priority++) - pri |= (*priority & 0x07) << j; + for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++) + pri |= (*davinci_def_priorities & 0x07) << j; davinci_irq_writel(pri, i); } diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index 8ff9d8aca60b..bbba0b247a44 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c @@ -1,41 +1,103 @@ /* - * DaVinci pin multiplexing configurations + * Utility to set the DAVINCI MUX register from a table in mux.h * * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> * + * Based on linux/arch/arm/plat-omap/mux.c: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * * 2007 (c) MontaVista Software, Inc. This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. + * + * Copyright (C) 2008 Texas Instruments. */ #include <linux/io.h> +#include <linux/module.h> #include <linux/spinlock.h> #include <mach/hardware.h> - #include <mach/mux.h> -/* System control register offsets */ -#define PINMUX0 0x00 -#define PINMUX1 0x04 +static const struct mux_config *mux_table; +static unsigned long pin_table_sz; + +int __init davinci_mux_register(const struct mux_config *pins, + unsigned long size) +{ + mux_table = pins; + pin_table_sz = size; -static DEFINE_SPINLOCK(mux_lock); + return 0; +} -void davinci_mux_peripheral(unsigned int mux, unsigned int enable) +/* + * Sets the DAVINCI MUX register based on the table + */ +int __init_or_module davinci_cfg_reg(const unsigned long index) { - u32 pinmux, muxreg = PINMUX0; + static DEFINE_SPINLOCK(mux_spin_lock); + void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); + unsigned long flags; + const struct mux_config *cfg; + unsigned int reg_orig = 0, reg = 0; + unsigned int mask, warn = 0; + + if (!mux_table) + BUG(); + + if (index >= pin_table_sz) { + printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", + index, pin_table_sz); + dump_stack(); + return -ENODEV; + } + + cfg = &mux_table[index]; + + if (cfg->name == NULL) { + printk(KERN_ERR "No entry for the specified index\n"); + return -ENODEV; + } + + /* Update the mux register in question */ + if (cfg->mask) { + unsigned tmp1, tmp2; + + spin_lock_irqsave(&mux_spin_lock, flags); + reg_orig = __raw_readl(base + cfg->mux_reg); + + mask = (cfg->mask << cfg->mask_offset); + tmp1 = reg_orig & mask; + reg = reg_orig & ~mask; + + tmp2 = (cfg->mode << cfg->mask_offset); + reg |= tmp2; + + if (tmp1 != tmp2) + warn = 1; + + __raw_writel(reg, base + cfg->mux_reg); + spin_unlock_irqrestore(&mux_spin_lock, flags); + } + + if (warn) { +#ifdef CONFIG_DAVINCI_MUX_WARNINGS + printk(KERN_WARNING "MUX: initialized %s\n", cfg->name); +#endif + } - if (mux >= DAVINCI_MUX_LEVEL2) { - muxreg = PINMUX1; - mux -= DAVINCI_MUX_LEVEL2; +#ifdef CONFIG_DAVINCI_MUX_DEBUG + if (cfg->debug || warn) { + printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name); + printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n", + cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); } +#endif - spin_lock(&mux_lock); - pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg); - if (enable) - pinmux |= (1 << mux); - else - pinmux &= ~(1 << mux); - davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg); - spin_unlock(&mux_lock); + return 0; } +EXPORT_SYMBOL(davinci_cfg_reg); diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h new file mode 100644 index 000000000000..adc869413371 --- /dev/null +++ b/arch/arm/mach-davinci/mux.h @@ -0,0 +1,51 @@ +/* + * Pin-multiplex helper macros for TI DaVinci family devices + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2008 Texas Instruments. + */ +#ifndef _MACH_DAVINCI_MUX_H_ +#define _MACH_DAVINCI_MUX_H_ + +#include <mach/mux.h> + +#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "PINMUX"#muxreg, \ + .mux_reg = PINMUX##muxreg, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "INTMUX", \ + .mux_reg = INTMUX, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ +[soc##_##desc] = { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "EVTMUX", \ + .mux_reg = EVTMUX, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#endif /* _MACH_DAVINCI_MUX_H */ diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 58754f066d5b..84171abf5f7b 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -23,10 +23,13 @@ #include <linux/init.h> #include <linux/io.h> +#include <mach/cputype.h> #include <mach/hardware.h> #include <mach/psc.h> #include <mach/mux.h> +#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 + /* PSC register offsets */ #define EPCPR 0x070 #define PTCMD 0x120 @@ -36,102 +39,61 @@ #define MDSTAT 0x800 #define MDCTL 0xA00 -/* System control register offsets */ -#define VDD3P3V_PWDN 0x48 +#define MDSTAT_STATE_MASK 0x1f -static void davinci_psc_mux(unsigned int id) +/* Return nonzero iff the domain's clock is active */ +int __init davinci_psc_is_clk_active(unsigned int id) { - switch (id) { - case DAVINCI_LPSC_ATA: - davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1); - davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1); - break; - case DAVINCI_LPSC_MMC_SD: - /* VDD power manupulations are done in U-Boot for CPMAC - * so applies to MMC as well - */ - /*Set up the pull regiter for MMC */ - davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN); - davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0); - break; - case DAVINCI_LPSC_I2C: - davinci_mux_peripheral(DAVINCI_MUX_I2C, 1); - break; - case DAVINCI_LPSC_McBSP: - davinci_mux_peripheral(DAVINCI_MUX_ASP, 1); - break; - default: - break; - } + void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); + u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); + + /* if clocked, state can be "Enable" or "SyncReset" */ + return mdstat & BIT(12); } /* Enable or disable a PSC domain */ void davinci_psc_config(unsigned int domain, unsigned int id, char enable) { - u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask; + u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; + void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); + u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */ - mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); - if (enable) - mdctl |= 0x00000003; /* Enable Module */ - else - mdctl &= 0xFFFFFFF2; /* Disable Module */ - davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); + mdctl = __raw_readl(psc_base + MDCTL + 4 * id); + mdctl &= ~MDSTAT_STATE_MASK; + mdctl |= next_state; + __raw_writel(mdctl, psc_base + MDCTL + 4 * id); - pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT); + pdstat = __raw_readl(psc_base + PDSTAT); if ((pdstat & 0x00000001) == 0) { - pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + pdctl1 = __raw_readl(psc_base + PDCTL1); pdctl1 |= 0x1; - davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + __raw_writel(pdctl1, psc_base + PDCTL1); ptcmd = 1 << domain; - davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); + __raw_writel(ptcmd, psc_base + PTCMD); do { - epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - EPCPR); + epcpr = __raw_readl(psc_base + EPCPR); } while ((((epcpr >> domain) & 1) == 0)); - pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + pdctl1 = __raw_readl(psc_base + PDCTL1); pdctl1 |= 0x100; - davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); + __raw_writel(pdctl1, psc_base + PDCTL1); do { - ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + + ptstat = __raw_readl(psc_base + PTSTAT); } while (!(((ptstat >> domain) & 1) == 0)); } else { ptcmd = 1 << domain; - davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); + __raw_writel(ptcmd, psc_base + PTCMD); do { - ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - PTSTAT); + ptstat = __raw_readl(psc_base + PTSTAT); } while (!(((ptstat >> domain) & 1) == 0)); } - if (enable) - mdstat_mask = 0x3; - else - mdstat_mask = 0x2; - do { - mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - MDSTAT + 4 * id); - } while (!((mdstat & 0x0000001F) == mdstat_mask)); - - if (enable) - davinci_psc_mux(id); -} - -void __init davinci_psc_init(void) -{ - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1); - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1); - - /* Turn on WatchDog timer LPSC. Needed for RESET to work */ - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1); + mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); + } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); } diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c index 3010f9971255..695075796522 100644 --- a/arch/arm/mach-davinci/serial.c +++ b/arch/arm/mach-davinci/serial.c @@ -32,32 +32,47 @@ #include <mach/hardware.h> #include <mach/serial.h> #include <mach/irqs.h> +#include <mach/cputype.h> +#include "clock.h" -#define UART_DAVINCI_PWREMU 0x0c - -static inline unsigned int davinci_serial_in(struct plat_serial8250_port *up, - int offset) +static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, + int offset) { offset <<= up->regshift; - return (unsigned int)__raw_readb(up->membase + offset); + return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset); } -static inline void davinci_serial_outp(struct plat_serial8250_port *p, - int offset, int value) +static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, + int value) { offset <<= p->regshift; - __raw_writeb(value, p->membase + offset); + __raw_writel(value, IO_ADDRESS(p->mapbase) + offset); } static struct plat_serial8250_port serial_platform_data[] = { { - .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE), - .mapbase = (unsigned long)DAVINCI_UART0_BASE, + .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART1_BASE, + .irq = IRQ_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART2_BASE, + .irq = IRQ_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = 27000000, }, { .flags = 0 @@ -74,22 +89,68 @@ static struct platform_device serial_device = { static void __init davinci_serial_reset(struct plat_serial8250_port *p) { - /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ unsigned int pwremu = 0; - davinci_serial_outp(p, UART_IER, 0); /* disable all interrupts */ + serial_write_reg(p, UART_IER, 0); /* disable all interrupts */ - davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); + /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ + serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); mdelay(10); pwremu |= (0x3 << 13); pwremu |= 0x1; - davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu); + serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); + + if (cpu_is_davinci_dm646x()) + serial_write_reg(p, UART_DM646X_SCR, + UART_DM646X_SCR_TX_WATERMARK); +} + +void __init davinci_serial_init(struct davinci_uart_config *info) +{ + int i; + char name[16]; + struct clk *uart_clk; + struct device *dev = &serial_device.dev; + + /* + * Make sure the serial ports are muxed on at this point. + * You have to mux them off in device drivers later on + * if not needed. + */ + for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) { + struct plat_serial8250_port *p = serial_platform_data + i; + + if (!(info->enabled_uarts & (1 << i))) { + p->flags = 0; + continue; + } + + if (cpu_is_davinci_dm646x()) + p->iotype = UPIO_MEM32; + + if (cpu_is_davinci_dm355()) { + if (i == 2) { + p->mapbase = (unsigned long)DM355_UART2_BASE; + p->irq = IRQ_DM355_UARTINT2; + } + } + + sprintf(name, "uart%d", i); + uart_clk = clk_get(dev, name); + if (IS_ERR(uart_clk)) + printk(KERN_ERR "%s:%d: failed to get UART%d clock\n", + __func__, __LINE__, i); + else { + clk_enable(uart_clk); + p->uartclk = clk_get_rate(uart_clk); + davinci_serial_reset(p); + } + } } static int __init davinci_init(void) { - davinci_serial_reset(&serial_platform_data[0]); return platform_device_register(&serial_device); } diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 6c227d4ba998..494e01bff5c3 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -16,6 +16,9 @@ #include <linux/clockchips.h> #include <linux/spinlock.h> #include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/device.h> #include <mach/hardware.h> #include <asm/system.h> @@ -24,8 +27,11 @@ #include <asm/mach/time.h> #include <asm/errno.h> #include <mach/io.h> +#include <mach/cputype.h> +#include "clock.h" static struct clock_event_device clockevent_davinci; +static unsigned int davinci_clock_tick_rate; #define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) #define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) @@ -99,9 +105,9 @@ struct timer_s { unsigned int id; unsigned long period; unsigned long opts; - unsigned long reg_base; - unsigned long tim_reg; - unsigned long prd_reg; + void __iomem *base; + unsigned long tim_off; + unsigned long prd_off; unsigned long enamode_shift; struct irqaction irqaction; }; @@ -114,15 +120,15 @@ static struct timer_s timers[]; static int timer32_config(struct timer_s *t) { - u32 tcr = davinci_readl(t->reg_base + TCR); + u32 tcr = __raw_readl(t->base + TCR); /* disable timer */ tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); - davinci_writel(tcr, t->reg_base + TCR); + __raw_writel(tcr, t->base + TCR); /* reset counter to zero, set new period */ - davinci_writel(0, t->tim_reg); - davinci_writel(t->period, t->prd_reg); + __raw_writel(0, t->base + t->tim_off); + __raw_writel(t->period, t->base + t->prd_off); /* Set enable mode */ if (t->opts & TIMER_OPTS_ONESHOT) { @@ -131,13 +137,13 @@ static int timer32_config(struct timer_s *t) tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; } - davinci_writel(tcr, t->reg_base + TCR); + __raw_writel(tcr, t->base + TCR); return 0; } static inline u32 timer32_read(struct timer_s *t) { - return davinci_readl(t->tim_reg); + return __raw_readl(t->base + t->tim_off); } static irqreturn_t timer_interrupt(int irq, void *dev_id) @@ -176,51 +182,54 @@ static struct timer_s timers[] = { static void __init timer_init(void) { - u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; + u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; int i; /* Global init of each 64-bit timer as a whole */ for(i=0; i<2; i++) { - u32 tgcr, base = bases[i]; + u32 tgcr; + void __iomem *base = IO_ADDRESS(phys_bases[i]); /* Disabled, Internal clock source */ - davinci_writel(0, base + TCR); + __raw_writel(0, base + TCR); /* reset both timers, no pre-scaler for timer34 */ tgcr = 0; - davinci_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base + TGCR); /* Set both timers to unchained 32-bit */ tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; - davinci_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base + TGCR); /* Unreset timers */ tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - davinci_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base + TGCR); /* Init both counters to zero */ - davinci_writel(0, base + TIM12); - davinci_writel(0, base + TIM34); + __raw_writel(0, base + TIM12); + __raw_writel(0, base + TIM34); } /* Init of each timer as a 32-bit timer */ for (i=0; i< ARRAY_SIZE(timers); i++) { struct timer_s *t = &timers[i]; + u32 phys_base; if (t->name) { t->id = i; - t->reg_base = (IS_TIMER1(t->id) ? + phys_base = (IS_TIMER1(t->id) ? DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); + t->base = IO_ADDRESS(phys_base); if (IS_TIMER_BOT(t->id)) { t->enamode_shift = 6; - t->tim_reg = t->reg_base + TIM12; - t->prd_reg = t->reg_base + PRD12; + t->tim_off = TIM12; + t->prd_off = PRD12; } else { t->enamode_shift = 22; - t->tim_reg = t->reg_base + TIM34; - t->prd_reg = t->reg_base + PRD34; + t->tim_off = TIM34; + t->prd_off = PRD34; } /* Register interrupt */ @@ -274,7 +283,7 @@ static void davinci_set_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - t->period = CLOCK_TICK_RATE / (HZ); + t->period = davinci_clock_tick_rate / (HZ); t->opts = TIMER_OPTS_PERIODIC; timer32_config(t); break; @@ -301,21 +310,29 @@ static struct clock_event_device clockevent_davinci = { static void __init davinci_timer_init(void) { + struct clk *timer_clk; + static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; /* init timer hw */ timer_init(); + timer_clk = clk_get(NULL, "timer0"); + BUG_ON(IS_ERR(timer_clk)); + clk_enable(timer_clk); + + davinci_clock_tick_rate = clk_get_rate(timer_clk); + /* setup clocksource */ clocksource_davinci.mult = - clocksource_khz2mult(CLOCK_TICK_RATE/1000, + clocksource_khz2mult(davinci_clock_tick_rate/1000, clocksource_davinci.shift); if (clocksource_register(&clocksource_davinci)) printk(err, clocksource_davinci.name); /* setup clockevent */ - clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, + clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC, clockevent_davinci.shift); clockevent_davinci.max_delta_ns = clockevent_delta2ns(0xfffffffe, &clockevent_davinci); @@ -333,42 +350,52 @@ struct sys_timer davinci_timer = { /* reset board using watchdog timer */ void davinci_watchdog_reset(void) { - u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE; + u32 tgcr, wdtcr; + void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE); + struct device dev; + struct clk *wd_clk; + char *name = "watchdog"; + + dev_set_name(&dev, name); + wd_clk = clk_get(&dev, NULL); + if (WARN_ON(IS_ERR(wd_clk))) + return; + clk_enable(wd_clk); /* disable, internal clock source */ - davinci_writel(0, base + TCR); + __raw_writel(0, base + TCR); /* reset timer, set mode to 64-bit watchdog, and unreset */ tgcr = 0; - davinci_writel(tgcr, base + TCR); + __raw_writel(tgcr, base + TCR); tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - davinci_writel(tgcr, base + TCR); + __raw_writel(tgcr, base + TCR); /* clear counter and period regs */ - davinci_writel(0, base + TIM12); - davinci_writel(0, base + TIM34); - davinci_writel(0, base + PRD12); - davinci_writel(0, base + PRD34); + __raw_writel(0, base + TIM12); + __raw_writel(0, base + TIM34); + __raw_writel(0, base + PRD12); + __raw_writel(0, base + PRD34); /* enable */ - wdtcr = davinci_readl(base + WDTCR); + wdtcr = __raw_readl(base + WDTCR); wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; - davinci_writel(wdtcr, base + WDTCR); + __raw_writel(wdtcr, base + WDTCR); /* put watchdog in pre-active state */ wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); + __raw_writel(wdtcr, base + WDTCR); /* put watchdog in active state */ wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); + __raw_writel(wdtcr, base + WDTCR); /* write an invalid value to the WDKEY field to trigger * a watchdog reset */ wdtcr = 0x00004000; - davinci_writel(wdtcr, base + WDTCR); + __raw_writel(wdtcr, base + WDTCR); } diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index 2429b79f6da2..abedb6337182 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c @@ -14,6 +14,8 @@ #include <mach/hardware.h> #include <mach/irqs.h> +#define DAVINCI_USB_OTG_BASE 0x01C64000 + #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) static struct musb_hdrc_eps_bits musb_eps[] = { { "ep1_tx", 8, }, diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index ae24486f858a..c535e8805a3b 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -450,10 +450,19 @@ static struct amba_device uart3_device = { }; +static struct resource ep93xx_rtc_resource[] = { + { + .start = EP93XX_RTC_PHYS_BASE, + .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1, + .flags = IORESOURCE_MEM, + }, +}; + static struct platform_device ep93xx_rtc_device = { - .name = "ep93xx-rtc", - .id = -1, - .num_resources = 0, + .name = "ep93xx-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(ep93xx_rtc_resource), + .resource = ep93xx_rtc_resource, }; diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index f66be12b856e..78ac1bddc8bc 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h @@ -147,6 +147,7 @@ #define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) #define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) +#define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000) #define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index e83e45ebf7a4..16295cfd5e29 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -52,6 +52,7 @@ /* * Interrupt numbers for PXA910 */ +#define IRQ_PXA910_NONE (-1) #define IRQ_PXA910_AIRQ 0 #define IRQ_PXA910_SSP3 1 #define IRQ_PXA910_SSP2 2 diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h index d0bdb6e3682b..d4bd393a26b0 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h @@ -248,6 +248,10 @@ #define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1) #define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1) +/* I2C */ +#define GPIO105_CI2C_SDA MFP_CFG(GPIO105, AF1) +#define GPIO106_CI2C_SCL MFP_CFG(GPIO106, AF1) + /* I2S */ #define GPIO113_I2S_MCLK MFP_CFG(GPIO113,AF6) #define GPIO114_I2S_FRM MFP_CFG(GPIO114,AF1) @@ -255,4 +259,27 @@ #define GPIO116_I2S_RXD MFP_CFG(GPIO116,AF2) #define GPIO117_I2S_TXD MFP_CFG(GPIO117,AF2) +/* PWM */ +#define GPIO96_PWM3_OUT MFP_CFG(GPIO96, AF1) +#define GPIO97_PWM2_OUT MFP_CFG(GPIO97, AF1) +#define GPIO98_PWM1_OUT MFP_CFG(GPIO98, AF1) +#define GPIO104_PWM4_OUT MFP_CFG(GPIO104, AF1) +#define GPIO106_PWM2_OUT MFP_CFG(GPIO106, AF2) +#define GPIO74_PWM4_OUT MFP_CFG(GPIO74, AF2) +#define GPIO75_PWM3_OUT MFP_CFG(GPIO75, AF2) +#define GPIO76_PWM2_OUT MFP_CFG(GPIO76, AF2) +#define GPIO77_PWM1_OUT MFP_CFG(GPIO77, AF2) +#define GPIO82_PWM4_OUT MFP_CFG(GPIO82, AF2) +#define GPIO83_PWM3_OUT MFP_CFG(GPIO83, AF2) +#define GPIO84_PWM2_OUT MFP_CFG(GPIO84, AF2) +#define GPIO85_PWM1_OUT MFP_CFG(GPIO85, AF2) +#define GPIO84_PWM1_OUT MFP_CFG(GPIO84, AF4) +#define GPIO122_PWM3_OUT MFP_CFG(GPIO122, AF3) +#define GPIO123_PWM1_OUT MFP_CFG(GPIO123, AF1) +#define GPIO124_PWM2_OUT MFP_CFG(GPIO124, AF1) +#define GPIO125_PWM3_OUT MFP_CFG(GPIO125, AF1) +#define GPIO126_PWM4_OUT MFP_CFG(GPIO126, AF1) +#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2) +#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3) + #endif /* __ASM_MACH_MFP_PXA168_H */ diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h index 48a1cbc7c56b..1f1a53ea5817 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h @@ -154,4 +154,12 @@ #define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM) #define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM) +/* PWM */ +#define GPIO27 PWM3 AF2 MFP_CFG(GPIO27, AF2) +#define GPIO51_PWM2_OUT MFP_CFG(GPIO51, AF2) +#define GPIO117_PWM1_OUT MFP_CFG(GPIO117, AF2) +#define GPIO118_PWM2_OUT MFP_CFG(GPIO118, AF2) +#define GPIO119_PWM3_OUT MFP_CFG(GPIO119, AF2) +#define GPIO120_PWM4_OUT MFP_CFG(GPIO120, AF2) + #endif /* __ASM_MACH MFP_PXA910_H */ diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index ef0a8a2076e9..6bf1f0eefcd1 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -1,10 +1,18 @@ #ifndef __ASM_MACH_PXA168_H #define __ASM_MACH_PXA168_H +#include <linux/i2c.h> #include <mach/devices.h> +#include <plat/i2c.h> extern struct pxa_device_desc pxa168_device_uart1; extern struct pxa_device_desc pxa168_device_uart2; +extern struct pxa_device_desc pxa168_device_twsi0; +extern struct pxa_device_desc pxa168_device_twsi1; +extern struct pxa_device_desc pxa168_device_pwm1; +extern struct pxa_device_desc pxa168_device_pwm2; +extern struct pxa_device_desc pxa168_device_pwm3; +extern struct pxa_device_desc pxa168_device_pwm4; static inline int pxa168_add_uart(int id) { @@ -20,4 +28,40 @@ static inline int pxa168_add_uart(int id) return pxa_register_device(d, NULL, 0); } + +static inline int pxa168_add_twsi(int id, struct i2c_pxa_platform_data *data, + struct i2c_board_info *info, unsigned size) +{ + struct pxa_device_desc *d = NULL; + int ret; + + switch (id) { + case 0: d = &pxa168_device_twsi0; break; + case 1: d = &pxa168_device_twsi1; break; + default: + return -EINVAL; + } + + ret = i2c_register_board_info(id, info, size); + if (ret) + return ret; + + return pxa_register_device(d, data, sizeof(*data)); +} + +static inline int pxa168_add_pwm(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &pxa168_device_pwm1; break; + case 2: d = &pxa168_device_pwm2; break; + case 3: d = &pxa168_device_pwm3; break; + case 4: d = &pxa168_device_pwm4; break; + default: + return -EINVAL; + } + + return pxa_register_device(d, NULL, 0); +} #endif /* __ASM_MACH_PXA168_H */ diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index b7aeaf574c36..6ae1ed7a0a9f 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -1,10 +1,18 @@ #ifndef __ASM_MACH_PXA910_H #define __ASM_MACH_PXA910_H +#include <linux/i2c.h> #include <mach/devices.h> +#include <plat/i2c.h> extern struct pxa_device_desc pxa910_device_uart1; extern struct pxa_device_desc pxa910_device_uart2; +extern struct pxa_device_desc pxa910_device_twsi0; +extern struct pxa_device_desc pxa910_device_twsi1; +extern struct pxa_device_desc pxa910_device_pwm1; +extern struct pxa_device_desc pxa910_device_pwm2; +extern struct pxa_device_desc pxa910_device_pwm3; +extern struct pxa_device_desc pxa910_device_pwm4; static inline int pxa910_add_uart(int id) { @@ -20,4 +28,40 @@ static inline int pxa910_add_uart(int id) return pxa_register_device(d, NULL, 0); } + +static inline int pxa910_add_twsi(int id, struct i2c_pxa_platform_data *data, + struct i2c_board_info *info, unsigned size) +{ + struct pxa_device_desc *d = NULL; + int ret; + + switch (id) { + case 0: d = &pxa910_device_twsi0; break; + case 1: d = &pxa910_device_twsi1; break; + default: + return -EINVAL; + } + + ret = i2c_register_board_info(id, info, size); + if (ret) + return ret; + + return pxa_register_device(d, data, sizeof(*data)); +} + +static inline int pxa910_add_pwm(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &pxa910_device_pwm1; break; + case 2: d = &pxa910_device_pwm2; break; + case 3: d = &pxa910_device_pwm3; break; + case 4: d = &pxa910_device_pwm4; break; + default: + return -EINVAL; + } + + return pxa_register_device(d, NULL, 0); +} #endif /* __ASM_MACH_PXA910_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index c6b8c9dc2026..98ccbee4bd0c 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -22,8 +22,10 @@ #define APBC_PXA168_UART1 APBC_REG(0x000) #define APBC_PXA168_UART2 APBC_REG(0x004) #define APBC_PXA168_GPIO APBC_REG(0x008) -#define APBC_PXA168_PWM0 APBC_REG(0x00c) -#define APBC_PXA168_PWM1 APBC_REG(0x010) +#define APBC_PXA168_PWM1 APBC_REG(0x00c) +#define APBC_PXA168_PWM2 APBC_REG(0x010) +#define APBC_PXA168_PWM3 APBC_REG(0x014) +#define APBC_PXA168_PWM4 APBC_REG(0x018) #define APBC_PXA168_SSP1 APBC_REG(0x01c) #define APBC_PXA168_SSP2 APBC_REG(0x020) #define APBC_PXA168_RTC APBC_REG(0x028) @@ -48,10 +50,10 @@ #define APBC_PXA910_UART0 APBC_REG(0x000) #define APBC_PXA910_UART1 APBC_REG(0x004) #define APBC_PXA910_GPIO APBC_REG(0x008) -#define APBC_PXA910_PWM0 APBC_REG(0x00c) -#define APBC_PXA910_PWM1 APBC_REG(0x010) -#define APBC_PXA910_PWM2 APBC_REG(0x014) -#define APBC_PXA910_PWM3 APBC_REG(0x018) +#define APBC_PXA910_PWM1 APBC_REG(0x00c) +#define APBC_PXA910_PWM2 APBC_REG(0x010) +#define APBC_PXA910_PWM3 APBC_REG(0x014) +#define APBC_PXA910_PWM4 APBC_REG(0x018) #define APBC_PXA910_SSP1 APBC_REG(0x01c) #define APBC_PXA910_SSP2 APBC_REG(0x020) #define APBC_PXA910_IPC APBC_REG(0x024) diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index ae924468658c..71b1ae338753 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -65,11 +65,23 @@ void __init pxa168_init_irq(void) /* APB peripheral clocks */ static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); +static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); +static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); +static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); +static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); +static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); +static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); /* device and clock bindings */ static struct clk_lookup pxa168_clkregs[] = { INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), + INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), + INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), + INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), }; static int __init pxa168_init(void) @@ -109,3 +121,9 @@ struct sys_timer pxa168_timer = { /* on-chip devices */ PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); +PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); +PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); +PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); +PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); +PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); +PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 453f8f7758bf..5882ca6b49fb 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -103,11 +103,23 @@ void __init pxa910_init_irq(void) /* APB peripheral clocks */ static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); +static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); +static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); +static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000); +static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); +static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); +static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); /* device and clock bindings */ static struct clk_lookup pxa910_clkregs[] = { INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), + INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), + INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), + INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), }; static int __init pxa910_init(void) @@ -156,3 +168,9 @@ struct sys_timer pxa910_timer = { */ PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22); PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24); +PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); +PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); +PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10); +PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10); +PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10); +PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10); diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index 44d4a966bed9..46098f546824 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c @@ -26,19 +26,13 @@ static int mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { - if (power_on) - gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 1); - else - gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 0); - + gpio_set_value(H2_TPS_GPIO_MMC_PWR_EN, power_on); return 0; } static int mmc_late_init(struct device *dev) { - int ret; - - ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power"); + int ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power"); if (ret < 0) return ret; @@ -47,7 +41,7 @@ static int mmc_late_init(struct device *dev) return ret; } -static void mmc_shutdown(struct device *dev) +static void mmc_cleanup(struct device *dev) { gpio_free(H2_TPS_GPIO_MMC_PWR_EN); } @@ -60,7 +54,7 @@ static void mmc_shutdown(struct device *dev) static struct omap_mmc_platform_data mmc1_data = { .nr_slots = 1, .init = mmc_late_init, - .shutdown = mmc_shutdown, + .cleanup = mmc_cleanup, .dma_mask = 0xffffffff, .slots[0] = { .set_power = mmc_set_power, diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index 0d8a3c195e2e..5e8877ce35e0 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c @@ -26,11 +26,7 @@ static int mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { - if (power_on) - gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 1); - else - gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 0); - + gpio_set_value(H3_TPS_GPIO_MMC_PWR_EN, power_on); return 0; } diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 4695965114c4..f597968733b4 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -39,12 +39,10 @@ #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <mach/gpioexpander.h> #include <mach/irqs.h> #include <mach/mux.h> #include <mach/tc.h> #include <mach/nand.h> -#include <mach/irda.h> #include <mach/usb.h> #include <mach/keypad.h> #include <mach/dma.h> @@ -276,104 +274,6 @@ static struct platform_device h3_kp_device = { .resource = h3_kp_resources, }; - -/* Select between the IrDA and aGPS module - */ -static int h3_select_irda(struct device *dev, int state) -{ - unsigned char expa; - int err = 0; - - if ((err = read_gpio_expa(&expa, 0x26))) { - printk(KERN_ERR "Error reading from I/O EXPANDER \n"); - return err; - } - - /* 'P6' enable/disable IRDA_TX and IRDA_RX */ - if (state & IR_SEL) { /* IrDA */ - if ((err = write_gpio_expa(expa | 0x40, 0x26))) { - printk(KERN_ERR "Error writing to I/O EXPANDER \n"); - return err; - } - } else { - if ((err = write_gpio_expa(expa & ~0x40, 0x26))) { - printk(KERN_ERR "Error writing to I/O EXPANDER \n"); - return err; - } - } - return err; -} - -static void set_trans_mode(struct work_struct *work) -{ - struct omap_irda_config *irda_config = - container_of(work, struct omap_irda_config, gpio_expa.work); - int mode = irda_config->mode; - unsigned char expa; - int err = 0; - - if ((err = read_gpio_expa(&expa, 0x27)) != 0) { - printk(KERN_ERR "Error reading from I/O expander\n"); - } - - expa &= ~0x03; - - if (mode & IR_SIRMODE) { - expa |= 0x01; - } else { /* MIR/FIR */ - expa |= 0x03; - } - - if ((err = write_gpio_expa(expa, 0x27)) != 0) { - printk(KERN_ERR "Error writing to I/O expander\n"); - } -} - -static int h3_transceiver_mode(struct device *dev, int mode) -{ - struct omap_irda_config *irda_config = dev->platform_data; - - irda_config->mode = mode; - cancel_delayed_work(&irda_config->gpio_expa); - PREPARE_DELAYED_WORK(&irda_config->gpio_expa, set_trans_mode); - schedule_delayed_work(&irda_config->gpio_expa, 0); - - return 0; -} - -static struct omap_irda_config h3_irda_data = { - .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, - .transceiver_mode = h3_transceiver_mode, - .select_irda = h3_select_irda, - .rx_channel = OMAP_DMA_UART3_RX, - .tx_channel = OMAP_DMA_UART3_TX, - .dest_start = UART3_THR, - .src_start = UART3_RHR, - .tx_trigger = 0, - .rx_trigger = 0, -}; - -static struct resource h3_irda_resources[] = { - [0] = { - .start = INT_UART3, - .end = INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 irda_dmamask = 0xffffffff; - -static struct platform_device h3_irda_device = { - .name = "omapirda", - .id = 0, - .dev = { - .platform_data = &h3_irda_data, - .dma_mask = &irda_dmamask, - }, - .num_resources = ARRAY_SIZE(h3_irda_resources), - .resource = h3_irda_resources, -}; - static struct platform_device h3_lcd_device = { .name = "lcd_h3", .id = -1, @@ -395,7 +295,6 @@ static struct platform_device *devices[] __initdata = { &nand_device, &smc91x_device, &intlat_device, - &h3_irda_device, &h3_kp_device, &h3_lcd_device, }; diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 7bc7a3cb9c51..d1ed1365319e 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -181,11 +181,7 @@ static struct omap_usb_config nokia770_usb_config __initdata = { static int nokia770_mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { - if (power_on) - gpio_set_value(NOKIA770_GPIO_MMC_POWER, 1); - else - gpio_set_value(NOKIA770_GPIO_MMC_POWER, 0); - + gpio_set_value(NOKIA770_GPIO_MMC_POWER, power_on); return 0; } diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index d040c3f1027f..a2d7814896be 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -40,8 +40,8 @@ static void omap1_mcbsp_request(unsigned int id) */ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { if (dsp_use++ == 0) { - api_clk = clk_get(NULL, "api_clk"); - dsp_clk = clk_get(NULL, "dsp_clk"); + api_clk = clk_get(NULL, "api_ck"); + dsp_clk = clk_get(NULL, "dsp_ck"); if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) { clk_enable(api_clk); clk_enable(dsp_clk); diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index a0267a9ab466..e7d017cdc438 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -33,10 +33,8 @@ #include <mach/control.h> #include <mach/gpio.h> -#include <mach/gpioexpander.h> #include <mach/mux.h> #include <mach/usb.h> -#include <mach/irda.h> #include <mach/board.h> #include <mach/common.h> #include <mach/keypad.h> @@ -138,98 +136,6 @@ static struct platform_device h4_flash_device = { .resource = &h4_flash_resource, }; -/* Select between the IrDA and aGPS module - */ -static int h4_select_irda(struct device *dev, int state) -{ - unsigned char expa; - int err = 0; - - if ((err = read_gpio_expa(&expa, 0x21))) { - printk(KERN_ERR "Error reading from I/O expander\n"); - return err; - } - - /* 'P6' enable/disable IRDA_TX and IRDA_RX */ - if (state & IR_SEL) { /* IrDa */ - if ((err = write_gpio_expa(expa | 0x01, 0x21))) { - printk(KERN_ERR "Error writing to I/O expander\n"); - return err; - } - } else { - if ((err = write_gpio_expa(expa & ~0x01, 0x21))) { - printk(KERN_ERR "Error writing to I/O expander\n"); - return err; - } - } - return err; -} - -static void set_trans_mode(struct work_struct *work) -{ - struct omap_irda_config *irda_config = - container_of(work, struct omap_irda_config, gpio_expa.work); - int mode = irda_config->mode; - unsigned char expa; - int err = 0; - - if ((err = read_gpio_expa(&expa, 0x20)) != 0) { - printk(KERN_ERR "Error reading from I/O expander\n"); - } - - expa &= ~0x01; - - if (!(mode & IR_SIRMODE)) { /* MIR/FIR */ - expa |= 0x01; - } - - if ((err = write_gpio_expa(expa, 0x20)) != 0) { - printk(KERN_ERR "Error writing to I/O expander\n"); - } -} - -static int h4_transceiver_mode(struct device *dev, int mode) -{ - struct omap_irda_config *irda_config = dev->platform_data; - - irda_config->mode = mode; - cancel_delayed_work(&irda_config->gpio_expa); - PREPARE_DELAYED_WORK(&irda_config->gpio_expa, set_trans_mode); - schedule_delayed_work(&irda_config->gpio_expa, 0); - - return 0; -} - -static struct omap_irda_config h4_irda_data = { - .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, - .transceiver_mode = h4_transceiver_mode, - .select_irda = h4_select_irda, - .rx_channel = OMAP24XX_DMA_UART3_RX, - .tx_channel = OMAP24XX_DMA_UART3_TX, - .dest_start = OMAP_UART3_BASE, - .src_start = OMAP_UART3_BASE, - .tx_trigger = OMAP24XX_DMA_UART3_TX, - .rx_trigger = OMAP24XX_DMA_UART3_RX, -}; - -static struct resource h4_irda_resources[] = { - [0] = { - .start = INT_24XX_UART3_IRQ, - .end = INT_24XX_UART3_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device h4_irda_device = { - .name = "omapirda", - .id = -1, - .dev = { - .platform_data = &h4_irda_data, - }, - .num_resources = 1, - .resource = h4_irda_resources, -}; - static struct omap_kp_platform_data h4_kp_data = { .rows = 6, .cols = 7, @@ -255,7 +161,6 @@ static struct platform_device h4_lcd_device = { static struct platform_device *h4_devices[] __initdata = { &h4_flash_device, - &h4_irda_device, &h4_kp_device, &h4_lcd_device, }; diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 744740ae1b9c..3a7a29d1f9a7 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -42,6 +42,7 @@ #include <mach/nand.h> #include <mach/mux.h> #include <mach/usb.h> +#include <mach/timer-gp.h> #include "mmc-twl4030.h" @@ -186,6 +187,9 @@ static void __init omap3_beagle_init_irq(void) { omap2_init_common_hw(NULL); omap_init_irq(); +#ifdef CONFIG_OMAP_32K_TIMER + omap2_gp_clockevent_set_gptimer(12); +#endif omap_gpio_init(); } diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 3a0daac6c839..374ff63c3eb2 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -15,7 +15,6 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> -#include <linux/delay.h> #include <linux/gpio.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 1e839c5a28c5..efc59c49341b 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -60,12 +60,13 @@ struct omap_clk { }, \ } -#define CK_243X (1 << 0) -#define CK_242X (1 << 1) +#define CK_243X RATE_IN_243X +#define CK_242X RATE_IN_242X static struct omap_clk omap24xx_clks[] = { /* external root sources */ CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), @@ -711,7 +712,7 @@ int __init omap2_clk_init(void) { struct prcm_config *prcm; struct omap_clk *c; - u32 clkrate, cpu_mask; + u32 clkrate; if (cpu_is_omap242x()) cpu_mask = RATE_IN_242X; @@ -720,21 +721,15 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); + for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) + clk_init_one(c->lk.clk); + osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); propagate_rate(&osc_ck); sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); propagate_rate(&sys_ck); for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) - clk_init_one(c->lk.clk); - - cpu_mask = 0; - if (cpu_is_omap2420()) - cpu_mask |= CK_242X; - if (cpu_is_omap2430()) - cpu_mask |= CK_243X; - - for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) if (c->cpu & cpu_mask) { clkdev_add(&c->lk); clk_register(c->lk.clk); diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 33c3e5b14323..88c5acb40fcf 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -625,6 +625,14 @@ static struct clk func_32k_ck = { .clkdm_name = "wkup_clkdm", }; +static struct clk secure_32k_ck = { + .name = "secure_32k_ck", + .ops = &clkops_null, + .rate = 32768, + .flags = RATE_FIXED, + .clkdm_name = "wkup_clkdm", +}; + /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ .name = "osc_ck", @@ -1790,7 +1798,7 @@ static struct clk gpt12_ick = { static struct clk gpt12_fck = { .name = "gpt12_fck", .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, + .parent = &secure_32k_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 70ec10deb654..6763b8f73028 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -2052,7 +2052,7 @@ static struct clk dss_ick = { static struct clk cam_mclk = { .name = "cam_mclk", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &dpll4_m5x2_ck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, @@ -2063,7 +2063,7 @@ static struct clk cam_mclk = { static struct clk cam_ick = { /* Handles both L3 and L4 clocks */ .name = "cam_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), @@ -2074,7 +2074,7 @@ static struct clk cam_ick = { static struct clk csi2_96m_fck = { .name = "csi2_96m_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &core_96m_fck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), @@ -2901,7 +2901,6 @@ static struct clk sr_l4_ick = { /* SECURE_32K_FCK clocks */ -/* XXX This clock no longer exists in 3430 TRM rev F */ static struct clk gpt12_fck = { .name = "gpt12_fck", .ops = &clkops_null, diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index d6b4b2f8722f..496983ade97e 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -25,7 +25,6 @@ #include <mach/board.h> #include <mach/mux.h> #include <mach/gpio.h> -#include <mach/eac.h> #include <mach/mmc.h> #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) @@ -366,38 +365,6 @@ static void omap_init_mcspi(void) static inline void omap_init_mcspi(void) {} #endif -#ifdef CONFIG_SND_OMAP24XX_EAC - -#define OMAP2_EAC_BASE 0x48090000 - -static struct resource omap2_eac_resources[] = { - { - .start = OMAP2_EAC_BASE, - .end = OMAP2_EAC_BASE + 0x109, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_eac_device = { - .name = "omap24xx-eac", - .id = -1, - .num_resources = ARRAY_SIZE(omap2_eac_resources), - .resource = omap2_eac_resources, - .dev = { - .platform_data = NULL, - }, -}; - -void omap_init_eac(struct eac_platform_data *pdata) -{ - omap2_eac_device.dev.platform_data = pdata; - platform_device_register(&omap2_eac_device); -} - -#else -void omap_init_eac(struct eac_platform_data *pdata) {} -#endif - #ifdef CONFIG_OMAP_SHA1_MD5 static struct resource sha1_md5_resources[] = { { diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 9ba20d985dda..998c5c45587e 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -73,9 +73,9 @@ static int omap_check_spurious(unsigned int irq) u32 sir, spurious; sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR); - spurious = sir >> 6; + spurious = sir >> 7; - if (spurious > 1) { + if (spurious) { printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush " "posted write for irq %i\n", irq, sir, previous_irq); diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 1cb2c0909c2b..f36aba12090e 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -3,6 +3,8 @@ * * OMAP2 GP timer support. * + * Copyright (C) 2009 Nokia Corporation + * * Update to use new clocksource/clockevent layers * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> * Copyright (C) 2007 MontaVista Software, Inc. @@ -36,8 +38,13 @@ #include <asm/mach/time.h> #include <mach/dmtimer.h> +/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ +#define MAX_GPTIMER_ID 12 + static struct omap_dm_timer *gptimer; static struct clock_event_device clockevent_gpt; +static u8 __initdata gptimer_id = 1; +static u8 __initdata inited; static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { @@ -95,20 +102,53 @@ static struct clock_event_device clockevent_gpt = { .set_mode = omap2_gp_timer_set_mode, }; +/** + * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents + * @id: GPTIMER to use (1..MAX_GPTIMER_ID) + * + * Define the GPTIMER that the system should use for the tick timer. + * Meant to be called from board-*.c files in the event that GPTIMER1, the + * default, is unsuitable. Returns -EINVAL on error or 0 on success. + */ +int __init omap2_gp_clockevent_set_gptimer(u8 id) +{ + if (id < 1 || id > MAX_GPTIMER_ID) + return -EINVAL; + + BUG_ON(inited); + + gptimer_id = id; + + return 0; +} + static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; + int src; + + inited = 1; - gptimer = omap_dm_timer_request_specific(1); + gptimer = omap_dm_timer_request_specific(gptimer_id); BUG_ON(gptimer == NULL); #if defined(CONFIG_OMAP_32K_TIMER) - omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); + src = OMAP_TIMER_SRC_32_KHZ; #else - omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); + src = OMAP_TIMER_SRC_SYS_CLK; + WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the " + "secure 32KiHz clock source\n"); #endif + + if (gptimer_id != 12) + WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)), + "timer-gp: omap_dm_timer_set_source() failed\n"); + tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); + pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", + gptimer_id, tick_rate); + omap2_gp_timer_irq.dev_id = (void *)gptimer; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); @@ -125,6 +165,8 @@ static void __init omap2_gp_clockevent_init(void) clockevents_register_device(&clockevent_gpt); } +/* Clocksource code */ + #ifdef CONFIG_OMAP_32K_TIMER /* * When 32k-timer is enabled, don't use GPTimer for clocksource diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 15e509013def..8df55f40f4c0 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -187,7 +187,7 @@ int tusb6010_platform_retime(unsigned is_refclk) unsigned sysclk_ps; int status; - if (!refclk_psec) + if (!refclk_psec || sysclk_ps == 0) return -ENODEV; sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60; diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 3e66d9099eab..816e0cb2b2e0 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -280,6 +280,7 @@ config MACH_ZYLONITE select PXA3xx select PXA_SSP select HAVE_PWM + select PXA_HAVE_BOARD_IRQS config MACH_LITTLETON bool "PXA3xx Form Factor Platform (aka Littleton)" @@ -505,12 +506,6 @@ config PXA_SSP help Enable support for PXA2xx SSP ports -config PXA_PWM - tristate - default BACKLIGHT_PWM - help - Enable support for PXA2xx/PXA3xx PWM controllers - config TOSA_BT tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" depends on MACH_TOSA diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 682dbf4e14b0..47d01572a04d 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -15,7 +15,6 @@ endif # Generic drivers that other drivers may depend upon obj-$(CONFIG_PXA_SSP) += ssp.o -obj-$(CONFIG_PXA_PWM) += pwm.o # SoC-specific code obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index a9f48b1cb54a..a97f87a90d0d 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -32,7 +32,7 @@ #include <mach/pxafb.h> #include <mach/mmc.h> #include <mach/ohci.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/pxa3xx_nand.h> #include <asm/mach/map.h> diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index cdf21dd135b4..7ea84954c7b3 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -42,7 +42,7 @@ #include <asm/mach/irq.h> #include <mach/pxa25x.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/irda.h> #include <mach/mmc.h> #include <mach/udc.h> @@ -435,13 +435,8 @@ static struct ads7846_platform_data corgi_ads7846_info = { .gpio_pendown = CORGI_GPIO_TP_INT, }; -static void corgi_ads7846_cs(u32 command) -{ - gpio_set_value(CORGI_GPIO_ADS7846_CS, !(command == PXA2XX_CS_ASSERT)); -} - static struct pxa2xx_spi_chip corgi_ads7846_chip = { - .cs_control = corgi_ads7846_cs, + .gpio_cs = CORGI_GPIO_ADS7846_CS, }; static void corgi_bl_kick_battery(void) @@ -465,22 +460,12 @@ static struct corgi_lcd_platform_data corgi_lcdcon_info = { .kick_battery = corgi_bl_kick_battery, }; -static void corgi_lcdcon_cs(u32 command) -{ - gpio_set_value(CORGI_GPIO_LCDCON_CS, !(command == PXA2XX_CS_ASSERT)); -} - static struct pxa2xx_spi_chip corgi_lcdcon_chip = { - .cs_control = corgi_lcdcon_cs, + .gpio_cs = CORGI_GPIO_LCDCON_CS, }; -static void corgi_max1111_cs(u32 command) -{ - gpio_set_value(CORGI_GPIO_MAX1111_CS, !(command == PXA2XX_CS_ASSERT)); -} - static struct pxa2xx_spi_chip corgi_max1111_chip = { - .cs_control = corgi_max1111_cs, + .gpio_cs = CORGI_GPIO_MAX1111_CS, }; static struct spi_board_info corgi_spi_devices[] = { @@ -510,32 +495,8 @@ static struct spi_board_info corgi_spi_devices[] = { static void __init corgi_init_spi(void) { - int err; - - err = gpio_request(CORGI_GPIO_ADS7846_CS, "ADS7846_CS"); - if (err) - return; - - err = gpio_request(CORGI_GPIO_LCDCON_CS, "LCDCON_CS"); - if (err) - goto err_free_1; - - err = gpio_request(CORGI_GPIO_MAX1111_CS, "MAX1111_CS"); - if (err) - goto err_free_2; - - gpio_direction_output(CORGI_GPIO_ADS7846_CS, 1); - gpio_direction_output(CORGI_GPIO_LCDCON_CS, 1); - gpio_direction_output(CORGI_GPIO_MAX1111_CS, 1); - pxa2xx_set_spi_info(1, &corgi_spi_info); spi_register_board_info(ARRAY_AND_SIZE(corgi_spi_devices)); - return; - -err_free_2: - gpio_free(CORGI_GPIO_LCDCON_CS); -err_free_1: - gpio_free(CORGI_GPIO_ADS7846_CS); } #else static inline void corgi_init_spi(void) {} diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 2b289f83a61a..a7854e44d618 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -16,15 +16,17 @@ #include <linux/mtd/physmap.h> #include <linux/mtd/partitions.h> #include <linux/sm501.h> +#include <linux/smsc911x.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/csb726.h> #include <mach/mfp-pxa27x.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/ohci.h> #include <mach/pxa2xx-regs.h> +#include <mach/audio.h> #include "generic.h" #include "devices.h" @@ -275,13 +277,22 @@ static struct resource csb726_lan_resources[] = { { .start = CSB726_IRQ_LAN, .end = CSB726_IRQ_LAN, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; +struct smsc911x_platform_config csb726_lan_config = { + .irq_type = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + + static struct platform_device csb726_lan = { - .name = "smc911x", + .name = "smsc911x", .id = -1, + .platform_data = &csb726_lan_config, .num_resources = ARRAY_SIZE(csb726_lan_resources), .resource = csb726_lan_resources, }; @@ -303,6 +314,7 @@ static void __init csb726_init(void) pxa27x_set_i2c_power_info(NULL); pxa_set_mci_info(&csb726_mci); pxa_set_ohci_info(&csb726_ohci_platform_data); + pxa_set_ac97_info(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index d245e59c51b1..d3c3b7b025ae 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -8,7 +8,7 @@ #include <mach/pxafb.h> #include <mach/mmc.h> #include <mach/irda.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/ohci.h> #include <mach/pxa27x_keypad.h> #include <mach/pxa2xx_spi.h> @@ -287,7 +287,7 @@ static struct resource pxa3xx_resources_i2c_power[] = { }; struct platform_device pxa3xx_device_i2c_power = { - .name = "pxa2xx-i2c", + .name = "pxa3xx-pwri2c", .id = 1, .resource = pxa3xx_resources_i2c_power, .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index bc0f73fbd4ca..3503f523070b 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -41,7 +41,7 @@ #include <mach/ohci.h> #include <mach/mmc.h> #include <mach/pxa27x_keypad.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/camera.h> #include <mach/pxa2xx_spi.h> diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 92ba16e1b6fc..afc214a417bb 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -25,7 +25,7 @@ #include <mach/pxa27x.h> #include <mach/pxafb.h> #include <mach/ohci.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/hardware.h> #include <mach/pxa27x_keypad.h> diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c index 2121309b2474..3ef98d43d303 100644 --- a/arch/arm/mach-pxa/imote2.c +++ b/arch/arm/mach-pxa/imote2.c @@ -29,7 +29,7 @@ #include <asm/mach/flash.h> #include <mach/pxa27x.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/udc.h> #include <mach/mmc.h> #include <mach/pxa2xx_spi.h> @@ -456,25 +456,12 @@ static struct pxa2xx_spi_master pxa_ssp_master_2_info = { .num_chipselect = 1, }; -/* Patch posted by Eric Miao <eric.miao@marvell.com> will remove - * the need for these functions. - */ -static void spi1control(u32 command) -{ - gpio_set_value(24, command & PXA2XX_CS_ASSERT ? 0 : 1); -}; - -static void spi3control(u32 command) -{ - gpio_set_value(39, command & PXA2XX_CS_ASSERT ? 0 : 1); -}; - static struct pxa2xx_spi_chip staccel_chip_info = { .tx_threshold = 8, .rx_threshold = 8, .dma_burst_size = 8, .timeout = 235, - .cs_control = spi1control, + .gpio_cs = 24, }; static struct pxa2xx_spi_chip cc2420_info = { @@ -482,7 +469,7 @@ static struct pxa2xx_spi_chip cc2420_info = { .rx_threshold = 8, .dma_burst_size = 8, .timeout = 235, - .cs_control = spi3control, + .gpio_cs = 39, }; static struct spi_board_info spi_board_info[] __initdata = { @@ -538,8 +525,6 @@ static void __init imote2_init(void) /* SPI chip select directions - all other directions should * be handled by drivers.*/ gpio_direction_output(37, 0); - gpio_direction_output(24, 0); - gpio_direction_output(39, 0); platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices)); diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 32bb4a2eb7f1..ebf38bbb347f 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -91,13 +91,21 @@ #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) /* - * The next 16 interrupts are for board specific purposes. Since + * The following interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use - * these. If you need more, increase IRQ_BOARD_END, but keep it - * within sensible limits. + * these. There will be 16 IRQs by default. If it is not enough, + * IRQ_BOARD_END is allowed be customized for each board, but keep + * the numbers within sensible limits and in descending order, so + * when multiple config options are selected, the maximum will be + * used. */ #define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) + +#if defined(CONFIG_MACH_ZYLONITE) +#define IRQ_BOARD_END (IRQ_BOARD_START + 32) +#else #define IRQ_BOARD_END (IRQ_BOARD_START + 16) +#endif #define IRQ_SA1111_START (IRQ_BOARD_END) #define IRQ_GPAIN0 (IRQ_BOARD_END + 0) @@ -188,8 +196,6 @@ #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) #elif defined(CONFIG_PXA_HAVE_BOARD_IRQS) #define NR_IRQS (IRQ_BOARD_END) -#elif defined(CONFIG_MACH_ZYLONITE) -#define NR_IRQS (IRQ_BOARD_START + 32) #else #define NR_IRQS (IRQ_BOARD_START) #endif diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index e13f6a81c223..e3526bfffd5a 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -43,7 +43,7 @@ #include <mach/pxafb.h> #include <mach/ssp.h> #include <mach/pxa2xx_spi.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/pxa27x_keypad.h> #include <mach/pxa3xx_nand.h> #include <mach/littleton.h> @@ -179,15 +179,10 @@ static struct pxa2xx_spi_master littleton_spi_info = { .num_chipselect = 1, }; -static void littleton_tdo24m_cs(u32 cmd) -{ - gpio_set_value(LITTLETON_GPIO_LCD_CS, !(cmd == PXA2XX_CS_ASSERT)); -} - static struct pxa2xx_spi_chip littleton_tdo24m_chip = { .rx_threshold = 1, .tx_threshold = 1, - .cs_control = littleton_tdo24m_cs, + .gpio_cs = LITTLETON_GPIO_LCD_CS, }; static struct spi_board_info littleton_spi_devices[] __initdata = { @@ -202,16 +197,6 @@ static struct spi_board_info littleton_spi_devices[] __initdata = { static void __init littleton_init_spi(void) { - int err; - - err = gpio_request(LITTLETON_GPIO_LCD_CS, "LCD_CS"); - if (err) { - pr_warning("failed to request GPIO for LCS CS\n"); - return; - } - - gpio_direction_output(LITTLETON_GPIO_LCD_CS, 1); - pxa2xx_set_spi_info(2, &littleton_spi_info); spi_register_board_info(ARRAY_AND_SIZE(littleton_spi_devices)); } diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index c899bbd94dc0..34046c8bfaf5 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -36,7 +36,7 @@ #include <mach/pxa27x.h> #include <mach/magician.h> #include <mach/pxafb.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/irda.h> #include <mach/ohci.h> @@ -745,6 +745,14 @@ static struct platform_device strataflash = { }; /* + * I2C + */ + +static struct i2c_pxa_platform_data i2c_info = { + .fast_mode = 1, +}; + +/* * Platform devices */ @@ -779,7 +787,7 @@ static void __init magician_init(void) pxa_set_ficp_info(&magician_ficp_info); } pxa27x_set_i2c_power_info(NULL); - pxa_set_i2c_info(NULL); + pxa_set_i2c_info(&i2c_info); pxa_set_mci_info(&magician_mci_info); pxa_set_ohci_info(&magician_ohci_info); diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index a6c8429e975f..f4dabf0273ca 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -46,7 +46,7 @@ #include <mach/mainstone.h> #include <mach/audio.h> #include <mach/pxafb.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/irda.h> #include <mach/ohci.h> diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index ff8052ce0a05..804c25c4a064 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -48,7 +48,7 @@ #include <mach/mmc.h> #include <mach/udc.h> #include <mach/pxa27x-udc.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/camera.h> #include <mach/audio.h> #include <media/soc_camera.h> diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 30662363907b..1a1d8208b73d 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -26,6 +26,7 @@ #include <linux/gpio.h> #include <linux/wm97xx_batt.h> #include <linux/power_supply.h> +#include <linux/usb/gpio_vbus.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -342,11 +343,18 @@ static struct pxaficp_platform_data palmt5_ficp_platform_data = { /****************************************************************************** * UDC ******************************************************************************/ -static struct pxa2xx_udc_mach_info palmt5_udc_info __initdata = { +static struct gpio_vbus_mach_info palmt5_udc_info = { .gpio_vbus = GPIO_NR_PALMT5_USB_DETECT_N, .gpio_vbus_inverted = 1, .gpio_pullup = GPIO_NR_PALMT5_USB_PULLUP, - .gpio_pullup_inverted = 0, +}; + +static struct platform_device palmt5_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &palmt5_udc_info, + }, }; /****************************************************************************** @@ -499,6 +507,7 @@ static struct platform_device *devices[] __initdata = { &palmt5_backlight, &power_supply, &palmt5_asoc, + &palmt5_gpio_vbus, }; /* setup udc GPIOs initial state */ @@ -518,7 +527,6 @@ static void __init palmt5_init(void) pxa_set_mci_info(&palmt5_mci_platform_data); palmt5_udc_init(); pxa_set_ac97_info(&palmt5_ac97_pdata); - pxa_set_udc_info(&palmt5_udc_info); pxa_set_ficp_info(&palmt5_ficp_platform_data); pxa_set_keypad_info(&palmt5_keypad_platform_data); wm97xx_bat_set_pdata(&wm97xx_batt_pdata); diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 43fcf2e86887..d823b09801df 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -25,6 +25,7 @@ #include <linux/gpio.h> #include <linux/wm97xx_batt.h> #include <linux/power_supply.h> +#include <linux/usb/gpio_vbus.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -37,6 +38,7 @@ #include <mach/mfp-pxa25x.h> #include <mach/irda.h> #include <mach/udc.h> +#include <mach/palmasoc.h> #include "generic.h" #include "devices.h" @@ -107,6 +109,7 @@ static unsigned long palmte2_pin_config[] __initdata = { GPIO1_RST, /* reset */ GPIO4_GPIO, /* Hotsync button */ GPIO9_GPIO, /* power detect */ + GPIO15_GPIO, /* earphone detect */ GPIO37_GPIO, /* LCD power */ GPIO56_GPIO, /* Backlight power */ }; @@ -318,11 +321,18 @@ static struct pxaficp_platform_data palmte2_ficp_platform_data = { /****************************************************************************** * UDC ******************************************************************************/ -static struct pxa2xx_udc_mach_info palmte2_udc_info __initdata = { +static struct gpio_vbus_mach_info palmte2_udc_info = { .gpio_vbus = GPIO_NR_PALMTE2_USB_DETECT_N, .gpio_vbus_inverted = 1, .gpio_pullup = GPIO_NR_PALMTE2_USB_PULLUP, - .gpio_pullup_inverted = 0, +}; + +static struct platform_device palmte2_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &palmte2_udc_info, + }, }; /****************************************************************************** @@ -395,6 +405,21 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = { }; /****************************************************************************** + * aSoC audio + ******************************************************************************/ +static struct palm27x_asoc_info palmte2_asoc_pdata = { + .jack_gpio = GPIO_NR_PALMTE2_EARPHONE_DETECT, +}; + +static struct platform_device palmte2_asoc = { + .name = "palm27x-asoc", + .id = -1, + .dev = { + .platform_data = &palmte2_asoc_pdata, + }, +}; + +/****************************************************************************** * Framebuffer ******************************************************************************/ static struct pxafb_mode_info palmte2_lcd_modes[] = { @@ -429,6 +454,8 @@ static struct platform_device *devices[] __initdata = { #endif &palmte2_backlight, &power_supply, + &palmte2_asoc, + &palmte2_gpio_vbus, }; /* setup udc GPIOs initial state */ @@ -447,7 +474,6 @@ static void __init palmte2_init(void) set_pxa_fb_info(&palmte2_lcd_screen); pxa_set_mci_info(&palmte2_mci_platform_data); palmte2_udc_init(); - pxa_set_udc_info(&palmte2_udc_info); pxa_set_ac97_info(NULL); pxa_set_ficp_info(&palmte2_ficp_platform_data); wm97xx_bat_set_pdata(&wm97xx_batt_pdata); diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index e2d44b1a8a9b..81da4396fb07 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -27,6 +27,7 @@ #include <linux/gpio.h> #include <linux/wm97xx_batt.h> #include <linux/power_supply.h> +#include <linux/usb/gpio_vbus.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -358,11 +359,18 @@ static struct pxaficp_platform_data palmtx_ficp_platform_data = { /****************************************************************************** * UDC ******************************************************************************/ -static struct pxa2xx_udc_mach_info palmtx_udc_info __initdata = { +static struct gpio_vbus_mach_info palmtx_udc_info = { .gpio_vbus = GPIO_NR_PALMTX_USB_DETECT_N, .gpio_vbus_inverted = 1, .gpio_pullup = GPIO_NR_PALMTX_USB_PULLUP, - .gpio_pullup_inverted = 0, +}; + +static struct platform_device palmtx_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &palmtx_udc_info, + }, }; /****************************************************************************** @@ -516,6 +524,7 @@ static struct platform_device *devices[] __initdata = { &palmtx_backlight, &power_supply, &palmtx_asoc, + &palmtx_gpio_vbus, }; static struct map_desc palmtx_io_desc[] __initdata = { @@ -551,7 +560,6 @@ static void __init palmtx_init(void) pxa_set_mci_info(&palmtx_mci_platform_data); palmtx_udc_init(); pxa_set_ac97_info(&palmtx_ac97_pdata); - pxa_set_udc_info(&palmtx_udc_info); pxa_set_ficp_info(&palmtx_ficp_platform_data); pxa_set_keypad_info(&palmtx_keypad_platform_data); wm97xx_bat_set_pdata(&wm97xx_batt_pdata); diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 6c12b5a3132f..095521e9ee24 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -28,7 +28,7 @@ #include <media/soc_camera.h> #include <asm/gpio.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/camera.h> #include <asm/mach/map.h> #include <mach/pxa27x.h> diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 036bbde4d221..ac431ed10399 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -39,7 +39,7 @@ #include <mach/pxa25x.h> #include <mach/mmc.h> #include <mach/udc.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/irda.h> #include <mach/poodle.h> #include <mach/pxafb.h> @@ -214,13 +214,8 @@ static struct ads7846_platform_data poodle_ads7846_info = { .gpio_pendown = POODLE_GPIO_TP_INT, }; -static void ads7846_cs(u32 command) -{ - gpio_set_value(POODLE_GPIO_TP_CS, !(command == PXA2XX_CS_ASSERT)); -} - static struct pxa2xx_spi_chip poodle_ads7846_chip = { - .cs_control = ads7846_cs, + .gpio_cs = POODLE_GPIO_TP_CS, }; static struct spi_board_info poodle_spi_devices[] = { @@ -236,14 +231,6 @@ static struct spi_board_info poodle_spi_devices[] = { static void __init poodle_init_spi(void) { - int err; - - err = gpio_request(POODLE_GPIO_TP_CS, "ADS7846_CS"); - if (err) - return; - - gpio_direction_output(POODLE_GPIO_TP_CS, 1); - pxa2xx_set_spi_info(1, &poodle_spi_info); spi_register_board_info(ARRAY_AND_SIZE(poodle_spi_devices)); } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index a425ec71e657..c54ad8b3343c 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -27,7 +27,7 @@ #include <mach/ohci.h> #include <mach/pm.h> #include <mach/dma.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index b02d4544dc95..6f678d93bf4e 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -30,7 +30,7 @@ #include <mach/pm.h> #include <mach/dma.h> #include <mach/ssp.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include "generic.h" #include "devices.h" @@ -552,7 +552,7 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) } static struct platform_device *devices[] __initdata = { -/* &pxa_device_udc, The UDC driver is PXA25x only */ + &pxa27x_device_udc, &pxa_device_ffuart, &pxa_device_btuart, &pxa_device_stuart, diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index ff8239991430..8241a63ea589 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -27,7 +27,7 @@ #include <asm/mach/arch.h> #include <mach/pxa930.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/pxafb.h> #include "devices.h" diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 8c61ddac119e..47b27f174ab9 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -47,7 +47,7 @@ #include <mach/pxa27x.h> #include <mach/pxa27x-udc.h> #include <mach/reset.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/irda.h> #include <mach/mmc.h> #include <mach/ohci.h> @@ -307,13 +307,8 @@ static struct ads7846_platform_data spitz_ads7846_info = { .gpio_pendown = SPITZ_GPIO_TP_INT, }; -static void spitz_ads7846_cs(u32 command) -{ - gpio_set_value(SPITZ_GPIO_ADS7846_CS, !(command == PXA2XX_CS_ASSERT)); -} - static struct pxa2xx_spi_chip spitz_ads7846_chip = { - .cs_control = spitz_ads7846_cs, + .gpio_cs = SPITZ_GPIO_ADS7846_CS, }; static void spitz_bl_kick_battery(void) @@ -337,22 +332,12 @@ static struct corgi_lcd_platform_data spitz_lcdcon_info = { .kick_battery = spitz_bl_kick_battery, }; -static void spitz_lcdcon_cs(u32 command) -{ - gpio_set_value(SPITZ_GPIO_LCDCON_CS, !(command == PXA2XX_CS_ASSERT)); -} - static struct pxa2xx_spi_chip spitz_lcdcon_chip = { - .cs_control = spitz_lcdcon_cs, + .gpio_cs = SPITZ_GPIO_LCDCON_CS, }; -static void spitz_max1111_cs(u32 command) -{ - gpio_set_value(SPITZ_GPIO_MAX1111_CS, !(command == PXA2XX_CS_ASSERT)); -} - static struct pxa2xx_spi_chip spitz_max1111_chip = { - .cs_control = spitz_max1111_cs, + .gpio_cs = SPITZ_GPIO_MAX1111_CS, }; static struct spi_board_info spitz_spi_devices[] = { @@ -382,30 +367,6 @@ static struct spi_board_info spitz_spi_devices[] = { static void __init spitz_init_spi(void) { - int err; - - err = gpio_request(SPITZ_GPIO_ADS7846_CS, "ADS7846_CS"); - if (err) - return; - - err = gpio_request(SPITZ_GPIO_LCDCON_CS, "LCDCON_CS"); - if (err) - goto err_free_1; - - err = gpio_request(SPITZ_GPIO_MAX1111_CS, "MAX1111_CS"); - if (err) - goto err_free_2; - - err = gpio_direction_output(SPITZ_GPIO_ADS7846_CS, 1); - if (err) - goto err_free_3; - err = gpio_direction_output(SPITZ_GPIO_LCDCON_CS, 1); - if (err) - goto err_free_3; - err = gpio_direction_output(SPITZ_GPIO_MAX1111_CS, 1); - if (err) - goto err_free_3; - if (machine_is_akita()) { spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT; spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; @@ -413,14 +374,6 @@ static void __init spitz_init_spi(void) pxa2xx_set_spi_info(2, &spitz_spi_info); spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices)); - return; - -err_free_3: - gpio_free(SPITZ_GPIO_MAX1111_CS); -err_free_2: - gpio_free(SPITZ_GPIO_LCDCON_CS); -err_free_1: - gpio_free(SPITZ_GPIO_ADS7846_CS); } #else static inline void spitz_init_spi(void) {} diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index afac5b6d3d78..196eebf06279 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -40,7 +40,7 @@ #include <mach/pxa25x.h> #include <mach/reset.h> #include <mach/irda.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/mmc.h> #include <mach/udc.h> #include <mach/tosa_bt.h> diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index f79c9cb70ae4..825f540176d2 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -47,7 +47,7 @@ #include <mach/mmc.h> #include <mach/irda.h> #include <mach/ohci.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 0e65344e9f53..af7c303171d7 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -45,7 +45,7 @@ #include <mach/pxa25x.h> #include <mach/audio.h> #include <mach/pxafb.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/viper.h> #include <asm/setup.h> diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index c1f73205d078..cfd666036e9e 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -21,7 +21,7 @@ #include <linux/gpio.h> #include <mach/pxa300.h> -#include <mach/i2c.h> +#include <plat/i2c.h> #include <mach/zylonite.h> #include "generic.h" diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c index 0cd52692d2f7..1f940df0e5af 100644 --- a/arch/arm/mach-sa1100/lart.c +++ b/arch/arm/mach-sa1100/lart.c @@ -9,6 +9,7 @@ #include <mach/hardware.h> #include <asm/setup.h> #include <asm/mach-types.h> +#include <asm/page.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile new file mode 100644 index 000000000000..d156f76b379f --- /dev/null +++ b/arch/arm/mach-stmp378x/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o +obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot new file mode 100644 index 000000000000..1568ad404d59 --- /dev/null +++ b/arch/arm/mach-stmp378x/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S new file mode 100644 index 000000000000..731a92286da2 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/entry-macro.S @@ -0,0 +1,35 @@ +/* + * Low-level IRQ helper macros for Freescale STMP378X + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + mov \base, #0xf0000000 @ vm address of IRQ controller + ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT + cmp \irqnr, #0x7f + moveqs \irqnr, #0 @ Zero flag set for no IRQ + + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h new file mode 100644 index 000000000000..cc59673becdd --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/irqs.h @@ -0,0 +1,95 @@ +/* + * Freescale STMP378X interrupts + * + * Copyright (C) 2005 Sigmatel Inc + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#define IRQ_DEBUG_UART 0 +#define IRQ_COMMS_RX 1 +#define IRQ_COMMS_TX 1 +#define IRQ_SSP2_ERROR 2 +#define IRQ_VDD5V 3 +#define IRQ_HEADPHONE_SHORT 4 +#define IRQ_DAC_DMA 5 +#define IRQ_DAC_ERROR 6 +#define IRQ_ADC_DMA 7 +#define IRQ_ADC_ERROR 8 +#define IRQ_SPDIF_DMA 9 +#define IRQ_SAIF2_DMA 9 +#define IRQ_SPDIF_ERROR 10 +#define IRQ_SAIF1_IRQ 10 +#define IRQ_SAIF2_IRQ 10 +#define IRQ_USB_CTRL 11 +#define IRQ_USB_WAKEUP 12 +#define IRQ_GPMI_DMA 13 +#define IRQ_SSP1_DMA 14 +#define IRQ_SSP_ERROR 15 +#define IRQ_GPIO0 16 +#define IRQ_GPIO1 17 +#define IRQ_GPIO2 18 +#define IRQ_SAIF1_DMA 19 +#define IRQ_SSP2_DMA 20 +#define IRQ_ECC8_IRQ 21 +#define IRQ_RTC_ALARM 22 +#define IRQ_UARTAPP_TX_DMA 23 +#define IRQ_UARTAPP_INTERNAL 24 +#define IRQ_UARTAPP_RX_DMA 25 +#define IRQ_I2C_DMA 26 +#define IRQ_I2C_ERROR 27 +#define IRQ_TIMER0 28 +#define IRQ_TIMER1 29 +#define IRQ_TIMER2 30 +#define IRQ_TIMER3 31 +#define IRQ_BATT_BRNOUT 32 +#define IRQ_VDDD_BRNOUT 33 +#define IRQ_VDDIO_BRNOUT 34 +#define IRQ_VDD18_BRNOUT 35 +#define IRQ_TOUCH_DETECT 36 +#define IRQ_LRADC_CH0 37 +#define IRQ_LRADC_CH1 38 +#define IRQ_LRADC_CH2 39 +#define IRQ_LRADC_CH3 40 +#define IRQ_LRADC_CH4 41 +#define IRQ_LRADC_CH5 42 +#define IRQ_LRADC_CH6 43 +#define IRQ_LRADC_CH7 44 +#define IRQ_LCDIF_DMA 45 +#define IRQ_LCDIF_ERROR 46 +#define IRQ_DIGCTL_DEBUG_TRAP 47 +#define IRQ_RTC_1MSEC 48 +#define IRQ_DRI_DMA 49 +#define IRQ_DRI_ATTENTION 50 +#define IRQ_GPMI_ATTENTION 51 +#define IRQ_IR 52 +#define IRQ_DCP_VMI 53 +#define IRQ_DCP 54 +#define IRQ_BCH 56 +#define IRQ_PXP 57 +#define IRQ_UARTAPP2_TX_DMA 58 +#define IRQ_UARTAPP2_INTERNAL 59 +#define IRQ_UARTAPP2_RX_DMA 60 +#define IRQ_VDAC_DETECT 61 +#define IRQ_VDD5V_DROOP 64 +#define IRQ_DCDC4P2_BO 65 + + +#define NR_REAL_IRQS 128 +#define NR_IRQS (NR_REAL_IRQS + 32 * 3) + +/* All interrupts are FIQ capable */ +#define FIQ_START IRQ_DEBUG_UART + +/* Hard disk IRQ is a GPMI attention IRQ */ +#define IRQ_HARDDISK IRQ_GPMI_ATTENTION diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h new file mode 100644 index 000000000000..93f952d35969 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/pins.h @@ -0,0 +1,151 @@ +/* + * Freescale STMP378X SoC pin multiplexing + * + * Author: Vladislav Buzov <vbuzov@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_PINS_H +#define __ASM_ARCH_PINS_H + +/* + * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware + * interface this pin belongs to. + */ + +/* Bank 0 */ +#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) +#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) +#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) +#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) +#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) +#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) +#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) +#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) +#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) +#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) +#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) +#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) +#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) +#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) +#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) +#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) +#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16) +#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17) +#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18) +#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) +#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20) +#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21) +#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22) +#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23) +#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) +#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) +#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26) +#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27) +#define PINID_AUART1_RX STMP3XXX_PINID(0, 28) +#define PINID_AUART1_TX STMP3XXX_PINID(0, 29) +#define PINID_I2C_SCL STMP3XXX_PINID(0, 30) +#define PINID_I2C_SDA STMP3XXX_PINID(0, 31) + +/* Bank 1 */ +#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) +#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) +#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) +#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) +#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) +#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) +#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) +#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) +#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) +#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) +#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) +#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) +#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) +#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) +#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) +#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) +#define PINID_LCD_D16 STMP3XXX_PINID(1, 16) +#define PINID_LCD_D17 STMP3XXX_PINID(1, 17) +#define PINID_LCD_RESET STMP3XXX_PINID(1, 18) +#define PINID_LCD_RS STMP3XXX_PINID(1, 19) +#define PINID_LCD_WR STMP3XXX_PINID(1, 20) +#define PINID_LCD_CS STMP3XXX_PINID(1, 21) +#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22) +#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23) +#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24) +#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25) +#define PINID_PWM0 STMP3XXX_PINID(1, 26) +#define PINID_PWM1 STMP3XXX_PINID(1, 27) +#define PINID_PWM2 STMP3XXX_PINID(1, 28) +#define PINID_PWM3 STMP3XXX_PINID(1, 29) +#define PINID_PWM4 STMP3XXX_PINID(1, 30) + +/* Bank 2 */ +#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0) +#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1) +#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2) +#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3) +#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4) +#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5) +#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6) +#define PINID_ROTARYA STMP3XXX_PINID(2, 7) +#define PINID_ROTARYB STMP3XXX_PINID(2, 8) +#define PINID_EMI_A00 STMP3XXX_PINID(2, 9) +#define PINID_EMI_A01 STMP3XXX_PINID(2, 10) +#define PINID_EMI_A02 STMP3XXX_PINID(2, 11) +#define PINID_EMI_A03 STMP3XXX_PINID(2, 12) +#define PINID_EMI_A04 STMP3XXX_PINID(2, 13) +#define PINID_EMI_A05 STMP3XXX_PINID(2, 14) +#define PINID_EMI_A06 STMP3XXX_PINID(2, 15) +#define PINID_EMI_A07 STMP3XXX_PINID(2, 16) +#define PINID_EMI_A08 STMP3XXX_PINID(2, 17) +#define PINID_EMI_A09 STMP3XXX_PINID(2, 18) +#define PINID_EMI_A10 STMP3XXX_PINID(2, 19) +#define PINID_EMI_A11 STMP3XXX_PINID(2, 20) +#define PINID_EMI_A12 STMP3XXX_PINID(2, 21) +#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22) +#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23) +#define PINID_EMI_CASN STMP3XXX_PINID(2, 24) +#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25) +#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26) +#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27) +#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28) +#define PINID_EMI_CKE STMP3XXX_PINID(2, 29) +#define PINID_EMI_RASN STMP3XXX_PINID(2, 30) +#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) + +/* Bank 3 */ +#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) +#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) +#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) +#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) +#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) +#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) +#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) +#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) +#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) +#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) +#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) +#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) +#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) +#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) +#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) +#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) +#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16) +#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17) +#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18) +#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19) +#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) +#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) + +#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h new file mode 100644 index 000000000000..db63b041e4f0 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h @@ -0,0 +1,88 @@ +/* + * STMP APBH Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_APBH_BASE (REGS_BASE + 0x4000) +#define REGS_APBH_BASE_PHYS (0x80004000) +#define REGS_APBH_SIZE 0x00002000 +HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00000000) +#define HW_APBH_CTRL0_ADDR (REGS_APBH_BASE + 0x00000000) +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000 +#define BP_APBH_CTRL0_RESET_CHANNEL 16 +#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 +#define BF_APBH_CTRL0_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CTRL0_RESET_CHANNEL) +HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x00000010) +#define HW_APBH_CTRL1_ADDR (REGS_APBH_BASE + 0x00000010) +HW_REGISTER(HW_APBH_CTRL2, REGS_APBH_BASE, 0x00000020) +HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x00000030) +HW_REGISTER_0_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x00000040, 0x70) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) +HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x00000050, 0x70) +HW_REGISTER_0_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x00000060, 0x70) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 +HW_REGISTER_0_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x00000070, 0x70) +HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x00000080, 0x70) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) +HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x00000090, 0x70) +HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0x000000a0, 0x70) +HW_REGISTER_0(HW_APBH_VERSION, REGS_APBH_BASE, 0x000003f0) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h new file mode 100644 index 000000000000..d0e8e9fe1cce --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h @@ -0,0 +1,79 @@ +/* + * STMP APBX Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ARCH_ARM___APBX_H +#define __ARCH_ARM___APBX_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_APBX_BASE (REGS_BASE + 0x24000) +#define REGS_APBX_BASE_PHYS (0x80024000) +#define REGS_APBX_SIZE 0x00002000 +HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00000000) +#define HW_APBX_CTRL0_ADDR (REGS_APBX_BASE + 0x00000000) +#define BM_APBX_CTRL0_SFTRST 0x80000000 +#define BM_APBX_CTRL0_CLKGATE 0x40000000 +HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x00000010) +HW_REGISTER(HW_APBX_CTRL2, REGS_APBX_BASE, 0x00000020) +HW_REGISTER(HW_APBX_CHANNEL_CTRL, REGS_APBX_BASE, 0x00000030) +#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL) & \ + BM_APBX_CHANNEL_CTRL_RESET_CHANNEL) +HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x00000040) +HW_REGISTER_0_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x00000100, 0x70) +HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x00000110, 0x70) +HW_REGISTER_0_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x00000120, 0x70) +#define BP_APBX_CHn_CMD_XFER_COUNT 16 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBX_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT) +#define BP_APBX_CHn_CMD_CMDWORDS 12 +#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBX_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS) +#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBX_CHn_CMD_CHAIN 0x00000004 +#define BP_APBX_CHn_CMD_COMMAND 0 +#define BM_APBX_CHn_CMD_COMMAND 0x00000003 +#define BF_APBX_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBX_CHn_CMD_COMMAND) +#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 +HW_REGISTER_0_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x00000130, 0x70) +HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x00000140, 0x70) +#define BP_APBX_CHn_SEMA_PHORE 16 +#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBX_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBX_CHn_SEMA_PHORE) +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA) +HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x00000150, 0x70) +HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0x00000160, 0x70) +HW_REGISTER_0(HW_APBX_VERSION, REGS_APBX_BASE, 0x00000800) +#endif /* __ARCH_ARM___APBX_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h new file mode 100644 index 000000000000..a421d9e0cbff --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h @@ -0,0 +1,276 @@ +/* + * STMP CLKCTRL Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM___CLKCTRL_H +#define __ARCH_ARM___CLKCTRL_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_CLKCTRL_BASE (REGS_BASE + 0x40000) +#define REGS_CLKCTRL_BASE_PHYS (0x80040000) +#define REGS_CLKCTRL_SIZE 0x00002000 +HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00000000) +#define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00000000) +#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL) +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL) +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL) +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 +HW_REGISTER_0(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x00000010) +#define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x00000010) +#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT) +HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x00000020) +#define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x00000020) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) +HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x00000030) +#define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x00000030) +#define BM_CLKCTRL_HBUS_BUSY 0x20000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) +HW_REGISTER_0(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x00000040) +#define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x00000040) +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) +HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x00000050) +#define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x00000050) +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 +#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) +HW_REGISTER_0(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x00000060) +#define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x00000060) +#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 +#define BM_CLKCTRL_PIX_BUSY 0x20000000 +#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 +#define BP_CLKCTRL_PIX_DIV 0 +#define BM_CLKCTRL_PIX_DIV 0x00000FFF +#define BF_CLKCTRL_PIX_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_PIX_DIV) +HW_REGISTER_0(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x00000070) +#define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x00000070) +#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP_BUSY 0x20000000 +#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP_DIV 0 +#define BM_CLKCTRL_SSP_DIV 0x000001FF +#define BF_CLKCTRL_SSP_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP_DIV) +HW_REGISTER_0(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x00000080) +#define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x00000080) +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) +HW_REGISTER_0(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x00000090) +#define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x00000090) +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +HW_REGISTER_0(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0x000000a0) +#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0x000000a0) +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) +HW_REGISTER_0(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0x000000b0) +#define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0x000000b0) +#define BM_CLKCTRL_IR_CLKGATE 0x80000000 +#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 +#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 +#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 +#define BP_CLKCTRL_IR_IROV_DIV 16 +#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 +#define BF_CLKCTRL_IR_IROV_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) +#define BP_CLKCTRL_IR_IR_DIV 0 +#define BM_CLKCTRL_IR_IR_DIV 0x000003FF +#define BF_CLKCTRL_IR_IR_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_IR_IR_DIV) +HW_REGISTER_0(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0x000000c0) +#define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0x000000c0) +#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF_BUSY 0x20000000 +#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF_DIV 0 +#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF_DIV) +HW_REGISTER_0(HW_CLKCTRL_TV, REGS_CLKCTRL_BASE, 0x000000d0) +#define HW_CLKCTRL_TV_ADDR (REGS_CLKCTRL_BASE + 0x000000d0) +#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 +#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 +HW_REGISTER_0(HW_CLKCTRL_ETM, REGS_CLKCTRL_BASE, 0x000000e0) +#define HW_CLKCTRL_ETM_ADDR (REGS_CLKCTRL_BASE + 0x000000e0) +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000003F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) +HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0x000000f0) +#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0x000000f0) +#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 +#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC_IOFRAC 24 +#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 +#define BF_CLKCTRL_FRAC_IOFRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 +#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC_PIXFRAC 16 +#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC_PIXFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC_EMIFRAC 8 +#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC) +#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC_CPUFRAC 0 +#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC) +HW_REGISTER(HW_CLKCTRL_FRAC1, REGS_CLKCTRL_BASE, 0x00000100) +#define HW_CLKCTRL_FRAC1_ADDR (REGS_CLKCTRL_BASE + 0x00000100) +#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 +#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 +HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0x00000110) +#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0x00000110) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 +#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 +HW_REGISTER_0(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0x00000120) +#define HW_CLKCTRL_RESET_ADDR (REGS_CLKCTRL_BASE + 0x00000120) +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 +HW_REGISTER_0(HW_CLKCTRL_STATUS, REGS_CLKCTRL_BASE, 0x00000130) +#define HW_CLKCTRL_STATUS_ADDR (REGS_CLKCTRL_BASE + 0x00000130) +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +HW_REGISTER_0(HW_CLKCTRL_VERSION, REGS_CLKCTRL_BASE, 0x00000140) +#define HW_CLKCTRL_VERSION_ADDR (REGS_CLKCTRL_BASE + 0x00000140) +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) +#endif /* __ARCH_ARM___CLKCTRL_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h new file mode 100644 index 000000000000..a5a530c6440d --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h @@ -0,0 +1,213 @@ +/* + * STMP ICOLL Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM___ICOLL_H +#define __ARCH_ARM___ICOLL_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_ICOLL_BASE (REGS_BASE + 0x0) +#define REGS_ICOLL_BASE_PHYS (0x80000000) +#define REGS_ICOLL_SIZE 0x00002000 +HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00000000) +#define HW_ICOLL_VECTOR_ADDR (REGS_ICOLL_BASE + 0x00000000) +#define BP_ICOLL_VECTOR_IRQVECTOR 2 +#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC +#define BF_ICOLL_VECTOR_IRQVECTOR(v) \ + (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR) +HW_REGISTER_0(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x00000010) +#define HW_ICOLL_LEVELACK_ADDR (REGS_ICOLL_BASE + 0x00000010) +#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 +#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F +#define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \ + (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK) +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 +HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x00000020) +#define HW_ICOLL_CTRL_ADDR (REGS_ICOLL_BASE + 0x00000020) +#define BM_ICOLL_CTRL_SFTRST 0x80000000 +#define BV_ICOLL_CTRL_SFTRST__RUN 0x0 +#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 +#define BM_ICOLL_CTRL_CLKGATE 0x40000000 +#define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 +#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 +#define BP_ICOLL_CTRL_VECTOR_PITCH 21 +#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000 +#define BF_ICOLL_CTRL_VECTOR_PITCH(v) \ + (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH) +#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 +#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000 +#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 +#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 +#define BM_ICOLL_CTRL_NO_NESTING 0x00080000 +#define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 +#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 +#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000 +#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 +#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 +HW_REGISTER(HW_ICOLL_VBASE, REGS_ICOLL_BASE, 0x00000040) +#define HW_ICOLL_VBASE_ADDR (REGS_ICOLL_BASE + 0x00000040) +#define BP_ICOLL_VBASE_TABLE_ADDRESS 2 +#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC +#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \ + (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS) +HW_REGISTER_0(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x00000070) +#define HW_ICOLL_STAT_ADDR (REGS_ICOLL_BASE + 0x00000070) +#define BP_ICOLL_STAT_VECTOR_NUMBER 0 +#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F +#define BF_ICOLL_STAT_VECTOR_NUMBER(v) \ + (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER) +/* + * multi-register-define name HW_ICOLL_RAWn + * base 0x000000A0 + * count 4 + * offset 0x10 + */ +HW_REGISTER_0_INDEXED(HW_ICOLL_RAWn, REGS_ICOLL_BASE, 0x000000a0, 0x10) +#define BP_ICOLL_RAWn_RAW_IRQS 0 +#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF +#define BF_ICOLL_RAWn_RAW_IRQS(v) (v) +/* + * multi-register-define name HW_ICOLL_INTERRUPTn + * base 0x00000120 + * count 128 + * offset 0x10 + */ +HW_REGISTER_INDEXED(HW_ICOLL_INTERRUPTn, REGS_ICOLL_BASE, 0x00000120, 0x10) +#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010 +#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 +#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 +#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 +#define BP_ICOLL_INTERRUPTn_PRIORITY 0 +#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003 +#define BF_ICOLL_INTERRUPTn_PRIORITY(v) \ + (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY) +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 +HW_REGISTER(HW_ICOLL_DEBUG, REGS_ICOLL_BASE, 0x00001120) +#define HW_ICOLL_DEBUG_ADDR (REGS_ICOLL_BASE + 0x00001120) +#define BP_ICOLL_DEBUG_INSERVICE 28 +#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000 +#define BF_ICOLL_DEBUG_INSERVICE(v) \ + (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE) +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 +#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000 +#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \ + (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS) +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 +#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000 +#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \ + (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL) +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 +#define BM_ICOLL_DEBUG_FIQ 0x00020000 +#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 +#define BM_ICOLL_DEBUG_IRQ 0x00010000 +#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 +#define BP_ICOLL_DEBUG_VECTOR_FSM 0 +#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF +#define BF_ICOLL_DEBUG_VECTOR_FSM(v) \ + (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM) +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 +HW_REGISTER(HW_ICOLL_DBGREAD0, REGS_ICOLL_BASE, 0x00001130) +#define HW_ICOLL_DBGREAD0_ADDR (REGS_ICOLL_BASE + 0x00001130) +#define BP_ICOLL_DBGREAD0_VALUE 0 +#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD0_VALUE(v) (v) +HW_REGISTER(HW_ICOLL_DBGREAD1, REGS_ICOLL_BASE, 0x00001140) +#define HW_ICOLL_DBGREAD1_ADDR (REGS_ICOLL_BASE + 0x00001140) +#define BP_ICOLL_DBGREAD1_VALUE 0 +#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD1_VALUE(v) (v) +HW_REGISTER(HW_ICOLL_DBGFLAG, REGS_ICOLL_BASE, 0x00001150) +#define HW_ICOLL_DBGFLAG_ADDR (REGS_ICOLL_BASE + 0x00001150) +#define BP_ICOLL_DBGFLAG_FLAG 0 +#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF +#define BF_ICOLL_DBGFLAG_FLAG(v) \ + (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG) +/* + * multi-register-define name HW_ICOLL_DBGREQUESTn + * base 0x00001160 + * count 4 + * offset 0x10 + */ +HW_REGISTER_0_INDEXED(HW_ICOLL_DBGREQUESTn, REGS_ICOLL_BASE, 0x00001160, + 0x10) +#define BP_ICOLL_DBGREQUESTn_BITS 0 +#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF +#define BF_ICOLL_DBGREQUESTn_BITS(v) (v) +HW_REGISTER_0(HW_ICOLL_VERSION, REGS_ICOLL_BASE, 0x000011e0) +#define HW_ICOLL_VERSION_ADDR (REGS_ICOLL_BASE + 0x000011e0) +#define BP_ICOLL_VERSION_MAJOR 24 +#define BM_ICOLL_VERSION_MAJOR 0xFF000000 +#define BF_ICOLL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ICOLL_VERSION_MAJOR) +#define BP_ICOLL_VERSION_MINOR 16 +#define BM_ICOLL_VERSION_MINOR 0x00FF0000 +#define BF_ICOLL_VERSION_MINOR(v) \ + (((v) << 16) & BM_ICOLL_VERSION_MINOR) +#define BP_ICOLL_VERSION_STEP 0 +#define BM_ICOLL_VERSION_STEP 0x0000FFFF +#define BF_ICOLL_VERSION_STEP(v) \ + (((v) << 0) & BM_ICOLL_VERSION_STEP) +#endif /* __ARCH_ARM___ICOLL_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h new file mode 100644 index 000000000000..6c42d2a47c19 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h @@ -0,0 +1,143 @@ +/* + * STMP PINCTRL Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_PINCTRL_BASE (REGS_BASE + 0x18000) +#define REGS_PINCTRL_BASE_PHYS (0x80018000) +#define REGS_PINCTRL_SIZE 0x00002000 +HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0x00000000) +#define HW_PINCTRL_CTRL_ADDR (REGS_PINCTRL_BASE + 0x00000000) +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BM_PINCTRL_CTRL_PRESENT3 0x08000000 +#define BM_PINCTRL_CTRL_PRESENT2 0x04000000 +#define BM_PINCTRL_CTRL_PRESENT1 0x02000000 +#define BM_PINCTRL_CTRL_PRESENT0 0x01000000 +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 +HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x00000100) +#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x00000100) +HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x00000110) +#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x00000110) +HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x00000120) +#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x00000120) +HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x00000130) +#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x00000130) +HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x00000140) +#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x00000140) +HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x00000150) +#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x00000150) +HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x00000160) +#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x00000160) +HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x00000170) +#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x00000170) +HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x00000200) +#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x00000200) +HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x00000210) +#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x00000210) +HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x00000220) +#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x00000220) +HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x00000230) +#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x00000230) +HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x00000240) +#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x00000240) +HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x00000250) +#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x00000250) +HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x00000260) +#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x00000260) +HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x00000270) +#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x00000270) +HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x00000280) +#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x00000280) +HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x00000290) +#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x00000290) +HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x000002a0) +#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x000002a0) +HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x000002b0) +#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x000002b0) +HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x000002c0) +#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x000002c0) +HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x000002d0) +#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x000002d0) +HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x000002e0) +#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x000002e0) +HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x00000400) +#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x00000400) +HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x00000410) +#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x00000410) +HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x00000420) +#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x00000420) +HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x00000430) +#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x00000430) +HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x00000500) +#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x00000500) +HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x00000510) +#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x00000510) +HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x00000520) +#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x00000520) +HW_REGISTER(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x00000600) +#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x00000600) +HW_REGISTER(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x00000610) +#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x00000610) +HW_REGISTER(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x00000620) +#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x00000620) +HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x00000700) +#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x00000700) +HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x00000710) +#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x00000710) +HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x00000720) +#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x00000720) +HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x00000800) +#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x00000800) +HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x00000810) +#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x00000810) +HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x00000820) +#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x00000820) +HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x00000900) +#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x00000900) +HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x00000910) +#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x00000910) +HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x00000920) +#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x00000920) +HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x00000a00) +#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x00000a00) +HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x00000a10) +#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x00000a10) +HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x00000a20) +#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x00000a20) +HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0x00000b00) +#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0x00000b00) +HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0x00000b10) +#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0x00000b10) +HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0x00000b20) +#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0x00000b20) +HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0x00000c00) +#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0x00000c00) +HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0x00000c10) +#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0x00000c10) +HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0x00000c20) +#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0x00000c20) +#endif /* __ARCH_ARM___PINCTRL_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h new file mode 100644 index 000000000000..1c81afeed531 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-power.h @@ -0,0 +1,32 @@ +/* + * STMP POWER Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM___POWER_H +#define __ARCH_ARM___POWER_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_POWER_BASE (void __iomem *)(REGS_BASE + 0x44000) +#define REGS_POWER_BASE_PHYS (0x80044000) +#define REGS_POWER_SIZE 0x00002000 +HW_REGISTER(HW_POWER_MINPWR, REGS_POWER_BASE, 0x00000020) +HW_REGISTER(HW_POWER_CHARGE, REGS_POWER_BASE, 0x00000030) +#endif /* __ARCH_ARM___POWER_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h new file mode 100644 index 000000000000..bb6355acdfd1 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h @@ -0,0 +1,216 @@ +/* + * STMP TIMROT Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_TIMROT_BASE (REGS_BASE + 0x68000) +#define REGS_TIMROT_BASE_PHYS (0x80068000) +#define REGS_TIMROT_SIZE 0x00002000 +HW_REGISTER(HW_TIMROT_ROTCTRL, REGS_TIMROT_BASE, 0x00000000) +#define HW_TIMROT_ROTCTRL_ADDR (REGS_TIMROT_BASE + 0x00000000) +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 +HW_REGISTER_0(HW_TIMROT_ROTCOUNT, REGS_TIMROT_BASE, 0x00000010) +#define HW_TIMROT_ROTCOUNT_ADDR (REGS_TIMROT_BASE + 0x00000010) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x20 + */ +HW_REGISTER_INDEXED(HW_TIMROT_TIMCTRLn, REGS_TIMROT_BASE, 0x00000020, 0x20) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xC +/* + * multi-register-define name HW_TIMROT_TIMCOUNTn + * base 0x00000030 + * count 3 + * offset 0x20 + */ +HW_REGISTER_0_INDEXED(HW_TIMROT_TIMCOUNTn, REGS_TIMROT_BASE, 0x00000030, + 0x20) +#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 +#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xFFFF0000 +#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) \ + (((v) << 16) & BM_TIMROT_TIMCOUNTn_RUNNING_COUNT) +#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 +#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0x0000FFFF +#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) \ + (((v) << 0) & BM_TIMROT_TIMCOUNTn_FIXED_COUNT) +HW_REGISTER(HW_TIMROT_TIMCTRL3, REGS_TIMROT_BASE, 0x00000080) +#define HW_TIMROT_TIMCTRL3_ADDR (REGS_TIMROT_BASE + 0x00000080) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xC +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xC +HW_REGISTER_0(HW_TIMROT_TIMCOUNT3, REGS_TIMROT_BASE, 0x00000090) +#define HW_TIMROT_TIMCOUNT3_ADDR (REGS_TIMROT_BASE + 0x00000090) +#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 +#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xFFFF0000 +#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) \ + (((v) << 16) & BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT) +#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0x0000FFFF +#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) \ + (((v) << 0) & BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT) +HW_REGISTER_0(HW_TIMROT_VERSION, REGS_TIMROT_BASE, 0x000000a0) +#define HW_TIMROT_VERSION_ADDR (REGS_TIMROT_BASE + 0x000000a0) +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c new file mode 100644 index 000000000000..f156ec7306c0 --- /dev/null +++ b/arch/arm/mach-stmp378x/stmp378x.c @@ -0,0 +1,225 @@ +/* + * Freescale STMP378X platform support + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <asm/dma.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <asm/mach/irq.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> + +#include <mach/pins.h> +#include <mach/pinmux.h> +#include <mach/dma.h> +#include <mach/hardware.h> +#include <mach/system.h> +#include <mach/platform.h> +#include <mach/stmp3xxx.h> +#include <mach/regs-icoll.h> +#include <mach/regs-apbh.h> +#include <mach/regs-apbx.h> + +#include "stmp378x.h" +/* + * IRQ handling + */ +static void stmp378x_ack_irq(unsigned int irq) +{ + /* Tell ICOLL to release IRQ line */ + HW_ICOLL_VECTOR_WR(0x0); + + /* ACK current interrupt */ + HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0); + + /* Barrier */ + (void) HW_ICOLL_STAT_RD(); +} + +static void stmp378x_mask_irq(unsigned int irq) +{ + /* IRQ disable */ + HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE); +} + +static void stmp378x_unmask_irq(unsigned int irq) +{ + /* IRQ enable */ + HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE); +} + +static struct irq_chip stmp378x_chip = { + .ack = stmp378x_ack_irq, + .mask = stmp378x_mask_irq, + .unmask = stmp378x_unmask_irq, +}; + +void __init stmp378x_init_irq(void) +{ + stmp3xxx_init_irq(&stmp378x_chip); +} + +/* + * DMA interrupt handling + */ +void stmp3xxx_arch_dma_enable_interrupt(int channel) +{ + int dmabus = channel / 16; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL1_SET(1 << (16 + (channel % 16))); + HW_APBH_CTRL2_SET(1 << (16 + (channel % 16))); + break; + + case STMP3XXX_BUS_APBX: + HW_APBX_CTRL1_SET(1 << (16 + (channel % 16))); + HW_APBX_CTRL2_SET(1 << (16 + (channel % 16))); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); + +void stmp3xxx_arch_dma_clear_interrupt(int channel) +{ + int dmabus = channel / 16; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL1_CLR(1 << (channel % 16)); + HW_APBH_CTRL2_CLR(1 << (channel % 16)); + break; + + case STMP3XXX_BUS_APBX: + HW_APBX_CTRL1_CLR(1 << (channel % 16)); + HW_APBX_CTRL2_CLR(1 << (channel % 16)); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); + +int stmp3xxx_arch_dma_is_interrupt(int channel) +{ + int dmabus = channel / 16; + int r = 0; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + r = HW_APBH_CTRL1_RD() & (1 << (channel % 16)); + break; + + case STMP3XXX_BUS_APBX: + r = HW_APBX_CTRL1_RD() & (1 << (channel % 16)); + break; + } + return r; +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); + +void stmp3xxx_arch_dma_reset_channel(int channel) +{ + int dmabus = channel / 16; + unsigned chbit = 1 << (channel % 16); + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + /* Reset channel and wait for it to complete */ + HW_APBH_CTRL0_SET(chbit << + BP_APBH_CTRL0_RESET_CHANNEL); + while (HW_APBH_CTRL0_RD() & + (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) + continue; + break; + + case STMP3XXX_BUS_APBX: + /* Reset channel and wait for it to complete */ + HW_APBX_CHANNEL_CTRL_SET( + BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit)); + while (HW_APBX_CHANNEL_CTRL_RD() & + BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit)) + continue; + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); + +void stmp3xxx_arch_dma_freeze(int channel) +{ + int dmabus = channel / 16; + unsigned chbit = 1 << (channel % 16); + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL0_SET(1<<chbit); + break; + case STMP3XXX_BUS_APBX: + HW_APBX_CHANNEL_CTRL_SET(1<<chbit); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze); + +void stmp3xxx_arch_dma_unfreeze(int channel) +{ + int dmabus = channel / 16; + unsigned chbit = 1 << (channel % 16); + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL0_CLR(1<<chbit); + break; + case STMP3XXX_BUS_APBX: + HW_APBX_CHANNEL_CTRL_CLR(1<<chbit); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze); + +/* + * The registers are all very closely mapped, so we might as well map them all + * with a single mapping + * + * Logical Physical + * f0000000 80000000 On-chip registers + * f1000000 00000000 256k on-chip SRAM + */ + +static struct map_desc stmp378x_io_desc[] __initdata = { + { + .virtual = (u32)STMP3XXX_REGS_BASE, + .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE), + .length = STMP3XXX_REGS_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = (u32)STMP3XXX_OCRAM_BASE, + .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE), + .length = STMP3XXX_OCRAM_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init stmp378x_map_io(void) +{ + iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc)); +} diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h new file mode 100644 index 000000000000..473de64cf8f7 --- /dev/null +++ b/arch/arm/mach-stmp378x/stmp378x.h @@ -0,0 +1,24 @@ +/* + * Freescale STMP37XX/STMP378X internal functions and data declarations + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_STMP378X_H +#define __MACH_STMP378X_H + +void stmp378x_map_io(void); +void stmp378x_init_irq(void); + +#endif /* __MACH_STMP378X_COMMON_H */ diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c new file mode 100644 index 000000000000..bc643f686b11 --- /dev/null +++ b/arch/arm/mach-stmp378x/stmp378x_devb.c @@ -0,0 +1,80 @@ +/* + * Freescale STMP378X development board support + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/pins.h> +#include <mach/pinmux.h> +#include <mach/stmp3xxx.h> + +#include "stmp378x.h" + +static struct platform_device *devices[] = { + &stmp3xxx_dbguart, +}; + +static struct pin_desc dbguart_pins_0[] = { + { PINID_PWM0, PIN_FUN3, }, + { PINID_PWM1, PIN_FUN3, }, +}; + +static struct pin_group dbguart_pins[] = { + [0] = { + .pins = dbguart_pins_0, + .nr_pins = ARRAY_SIZE(dbguart_pins_0), + }, +}; + +static int dbguart_pins_control(int id, int request) +{ + int r = 0; + + if (request) + r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart"); + else + stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart"); + return r; +} + +static void __init stmp378x_devb_init(void) +{ + stmp3xxx_pinmux_init(NR_REAL_IRQS); + + /* init stmp3xxx platform */ + stmp3xxx_init(); + + stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; + + /* add board's devices */ + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +MACHINE_START(STMP378X, "STMP378X") + .phys_io = 0x80000000, + .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, + .boot_params = 0x40000100, + .map_io = stmp378x_map_io, + .init_irq = stmp378x_init_irq, + .timer = &stmp3xxx_timer, + .init_machine = stmp378x_devb_init, +MACHINE_END diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile new file mode 100644 index 000000000000..57deffd09fbf --- /dev/null +++ b/arch/arm/mach-stmp37xx/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o +obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot new file mode 100644 index 000000000000..1568ad404d59 --- /dev/null +++ b/arch/arm/mach-stmp37xx/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S new file mode 100644 index 000000000000..fed2787b6c34 --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S @@ -0,0 +1,37 @@ +/* + * Low-level IRQ helper macros for Freescale STMP37XX + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + mov \base, #0xf0000000 @ vm address of IRQ controller + ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT + cmp \irqnr, #0x3f + movne \irqstat, #0 @ Ack this IRQ + strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR + moveqs \irqnr, #0 @ Zero flag set for no IRQ + + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h new file mode 100644 index 000000000000..98f12938550d --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/irqs.h @@ -0,0 +1,99 @@ +/* + * Freescale STMP37XX interrupts + * + * Copyright (C) 2005 Sigmatel Inc + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef _ASM_ARCH_IRQS_H +#define _ASM_ARCH_IRQS_H + +#define IRQ_DEBUG_UART 0 +#define IRQ_COMMS_RX 1 +#define IRQ_COMMS_TX 1 +#define IRQ_SSP2_ERROR 2 +#define IRQ_VDD5V 3 +#define IRQ_HEADPHONE_SHORT 4 +#define IRQ_DAC_DMA 5 +#define IRQ_DAC_ERROR 6 +#define IRQ_ADC_DMA 7 +#define IRQ_ADC_ERROR 8 +#define IRQ_SPDIF_DMA 9 +#define IRQ_SAIF2_DMA 9 +#define IRQ_SPDIF_ERROR 10 +#define IRQ_SAIF1_IRQ 10 +#define IRQ_SAIF2_IRQ 10 +#define IRQ_USB_CTRL 11 +#define IRQ_USB_WAKEUP 12 +#define IRQ_GPMI_DMA 13 +#define IRQ_SSP1_DMA 14 +#define IRQ_SSP_ERROR 15 +#define IRQ_GPIO0 16 +#define IRQ_GPIO1 17 +#define IRQ_GPIO2 18 +#define IRQ_SAIF1_DMA 19 +#define IRQ_SSP2_DMA 20 +#define IRQ_ECC8_IRQ 21 +#define IRQ_RTC_ALARM 22 +#define IRQ_UARTAPP_TX_DMA 23 +#define IRQ_UARTAPP_INTERNAL 24 +#define IRQ_UARTAPP_RX_DMA 25 +#define IRQ_I2C_DMA 26 +#define IRQ_I2C_ERROR 27 +#define IRQ_TIMER0 28 +#define IRQ_TIMER1 29 +#define IRQ_TIMER2 30 +#define IRQ_TIMER3 31 +#define IRQ_BATT_BRNOUT 32 +#define IRQ_VDDD_BRNOUT 33 +#define IRQ_VDDIO_BRNOUT 34 +#define IRQ_VDD18_BRNOUT 35 +#define IRQ_TOUCH_DETECT 36 +#define IRQ_LRADC_CH0 37 +#define IRQ_LRADC_CH1 38 +#define IRQ_LRADC_CH2 39 +#define IRQ_LRADC_CH3 40 +#define IRQ_LRADC_CH4 41 +#define IRQ_LRADC_CH5 42 +#define IRQ_LRADC_CH6 43 +#define IRQ_LRADC_CH7 44 +#define IRQ_LCDIF_DMA 45 +#define IRQ_LCDIF_ERROR 46 +#define IRQ_DIGCTL_DEBUG_TRAP 47 +#define IRQ_RTC_1MSEC 48 +#define IRQ_DRI_DMA 49 +#define IRQ_DRI_ATTENTION 50 +#define IRQ_GPMI_ATTENTION 51 +#define IRQ_IR 52 +#define IRQ_DCP_VMI 53 +#define IRQ_DCP 54 +#define IRQ_RESERVED_55 55 +#define IRQ_RESERVED_56 56 +#define IRQ_RESERVED_57 57 +#define IRQ_RESERVED_58 58 +#define IRQ_RESERVED_59 59 +#define SW_IRQ_60 60 +#define SW_IRQ_61 61 +#define SW_IRQ_62 62 +#define SW_IRQ_63 63 + +#define NR_REAL_IRQS 64 +#define NR_IRQS (NR_REAL_IRQS + 32 * 3) + +/* TIMER and BRNOUT are FIQ capable */ +#define FIQ_START IRQ_TIMER0 + +/* Hard disk IRQ is a GPMI attention IRQ */ +#define IRQ_HARDDISK IRQ_GPMI_ATTENTION + +#endif /* _ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h new file mode 100644 index 000000000000..d56de0c471d8 --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/pins.h @@ -0,0 +1,147 @@ +/* + * Freescale STMP37XX SoC pin multiplexing + * + * Author: Vladislav Buzov <vbuzov@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_PINS_H +#define __ASM_ARCH_PINS_H + +/* + * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware + * interface this pin belongs to. + */ + +/* Bank 0 */ +#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) +#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) +#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) +#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) +#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) +#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) +#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) +#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) +#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) +#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) +#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) +#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) +#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) +#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) +#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) +#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) +#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16) +#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17) +#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18) +#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) +#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20) +#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21) +#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22) +#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23) +#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) +#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) +#define PINID_UART2_CTS STMP3XXX_PINID(0, 26) +#define PINID_UART2_RTS STMP3XXX_PINID(0, 27) +#define PINID_UART2_RX STMP3XXX_PINID(0, 28) +#define PINID_UART2_TX STMP3XXX_PINID(0, 29) + +/* Bank 1 */ +#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) +#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) +#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) +#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) +#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) +#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) +#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) +#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) +#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) +#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) +#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) +#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) +#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) +#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) +#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) +#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) +#define PINID_LCD_RESET STMP3XXX_PINID(1, 16) +#define PINID_LCD_RS STMP3XXX_PINID(1, 17) +#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18) +#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19) +#define PINID_LCD_CS STMP3XXX_PINID(1, 20) +#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21) +#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22) +#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23) +#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24) +#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25) +#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26) +#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27) +#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28) + +/* Bank 2 */ +#define PINID_PWM0 STMP3XXX_PINID(2, 0) +#define PINID_PWM1 STMP3XXX_PINID(2, 1) +#define PINID_PWM2 STMP3XXX_PINID(2, 2) +#define PINID_PWM3 STMP3XXX_PINID(2, 3) +#define PINID_PWM4 STMP3XXX_PINID(2, 4) +#define PINID_I2C_SCL STMP3XXX_PINID(2, 5) +#define PINID_I2C_SDA STMP3XXX_PINID(2, 6) +#define PINID_ROTTARYA STMP3XXX_PINID(2, 7) +#define PINID_ROTTARYB STMP3XXX_PINID(2, 8) +#define PINID_EMI_CKE STMP3XXX_PINID(2, 9) +#define PINID_EMI_RASN STMP3XXX_PINID(2, 10) +#define PINID_EMI_CASN STMP3XXX_PINID(2, 11) +#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12) +#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13) +#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14) +#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15) +#define PINID_EMI_A00 STMP3XXX_PINID(2, 16) +#define PINID_EMI_A01 STMP3XXX_PINID(2, 17) +#define PINID_EMI_A02 STMP3XXX_PINID(2, 18) +#define PINID_EMI_A03 STMP3XXX_PINID(2, 19) +#define PINID_EMI_A04 STMP3XXX_PINID(2, 20) +#define PINID_EMI_A05 STMP3XXX_PINID(2, 21) +#define PINID_EMI_A06 STMP3XXX_PINID(2, 22) +#define PINID_EMI_A07 STMP3XXX_PINID(2, 23) +#define PINID_EMI_A08 STMP3XXX_PINID(2, 24) +#define PINID_EMI_A09 STMP3XXX_PINID(2, 25) +#define PINID_EMI_A10 STMP3XXX_PINID(2, 26) +#define PINID_EMI_A11 STMP3XXX_PINID(2, 27) +#define PINID_EMI_A12 STMP3XXX_PINID(2, 28) +#define PINID_EMI_A13 STMP3XXX_PINID(2, 29) +#define PINID_EMI_A14 STMP3XXX_PINID(2, 30) +#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) + +/* Bank 3 */ +#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) +#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) +#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) +#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) +#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) +#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) +#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) +#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) +#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) +#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) +#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) +#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) +#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) +#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) +#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) +#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) +#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16) +#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17) +#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18) +#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19) +#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) +#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) + +#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h new file mode 100644 index 000000000000..3044c20ad90c --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h @@ -0,0 +1,102 @@ +/* + * STMP APBH Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H +#define _INCLUDE_ASM_ARCH_REGS_APBH_H + +#include <mach/stmp3xxx_regs.h> + +#ifndef REGS_APBH_BASE +#define REGS_APBH_BASE (REGS_BASE + 0x00004000) +#endif + +HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00) +#define BP_APBH_CTRL0_SFTRST 31 +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BP_APBH_CTRL0_CLKGATE 30 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BP_APBH_CTRL0_RESET_CHANNEL 16 +#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 +#define BF_APBH_CTRL0_RESET_CHANNEL(v) \ + (((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL) +HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10) +#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 9 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00000200 +#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 8 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00000100 +#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ 7 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ 1 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 +#define BP_APBH_CTRL1_CH1_ERR_IRQ 17 +#define BM_APBH_CTRL1_CH1_ERR_IRQ 0x00020000 +HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20) +HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70) +HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v) +HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70) +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS) +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BP_APBH_CHn_CMD_SEMAPHORE 6 +#define BF_APBH_CHn_CMD_SEMAPHORE(v) \ + (((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE) +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BP_APBH_CHn_CMD_NANDLOCK 4 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BF_APBH_CHn_CMD_NANDLOCK(v) \ + (((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK) +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BM_APBH_CHn_CMD_DMA_READ 0x00000003 +#define BP_APBH_CHn_CMD_DMA_READ 0 +#define BF_APBH_CHn_CMD_DMA_READ(v) \ + (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ) +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 +HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70) +HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \ + BM_APBH_CHn_SEMA_INCREMENT_SEMA) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70) +HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70) +HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0) + +#endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h new file mode 100644 index 000000000000..a14ddb97639a --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h @@ -0,0 +1,109 @@ +/* + * STMP APBX Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _INCLUDE_ASM_ARCH_REGS_APBX_H +#define _INCLUDE_ASM_ARCH_REGS_APBX_H + +#include <mach/stmp3xxx_regs.h> + +#ifndef REGS_APBX_BASE +#define REGS_APBX_BASE (REGS_BASE + 0x00024000) +#endif + +HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00) +#define BP_APBX_CTRL0_SFTRST 31 +#define BM_APBX_CTRL0_SFTRST 0x80000000 +#define BP_APBX_CTRL0_CLKGATE 30 +#define BM_APBX_CTRL0_CLKGATE 0x40000000 +#define BP_APBX_CTRL0_RESET_CHANNEL 16 +#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000 +#define BF_APBX_CTRL0_RESET_CHANNEL(v) \ + (((v) << BP_APBX_CTRL0_RESET_CHANNEL) & BM_APBX_CTRL0_RESET_CHANNEL) +HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x10) +HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x20) +#define BP_APBX_DEVSEL_CH7 28 +#define BM_APBX_DEVSEL_CH7 0xF0000000 +#define BF_APBX_DEVSEL_CH7(v) \ + (((v) << BP_APBX_DEVSEL_CH7) & BM_APBX_DEVSEL_CH7) +#define BV_APBX_DEVSEL_CH7__USE_UART 0x0 +#define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 +#define BP_APBX_DEVSEL_CH6 24 +#define BM_APBX_DEVSEL_CH6 0x0F000000 +#define BF_APBX_DEVSEL_CH6(v) \ + (((v) << BP_APBX_DEVSEL_CH6) & BM_APBX_DEVSEL_CH6) +#define BV_APBX_DEVSEL_CH6__USE_UART 0x0 +#define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 +#define BP_APBX_CTRL1_CH7_AHB_ERROR_IRQ 23 +#define BM_APBX_CTRL1_CH7_AHB_ERROR_IRQ 0x00800000 +#define BP_APBX_CTRL1_CH6_AHB_ERROR_IRQ 22 +#define BM_APBX_CTRL1_CH6_AHB_ERROR_IRQ 0x00400000 +#define BP_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 15 +#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00008000 +#define BP_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 14 +#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00004000 + +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x40, 0x70) +HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x50, 0x70) +#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v) +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x60, 0x70) +#define BP_APBX_CHn_CMD_XFER_COUNT 16 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBX_CHn_CMD_XFER_COUNT(v) \ + (((v) << BP_APBX_CHn_CMD_XFER_COUNT) & BM_APBX_CHn_CMD_XFER_COUNT) +#define BP_APBX_CHn_CMD_CMDWORDS 12 +#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBX_CHn_CMD_CMDWORDS(v) \ + (((v) << BP_APBX_CHn_CMD_CMDWORDS) & BM_APBX_CHn_CMD_CMDWORDS) +#define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BP_APBX_CHn_CMD_SEMAPHORE 6 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 +#define BP_APBX_CHn_CMD_IRQONCMPLT 3 +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 +#define BP_APBX_CHn_CMD_CHAIN 2 +#define BM_APBX_CHn_CMD_CHAIN 0x00000004 +#define BM_APBX_CHn_CMD_DMA_READ 0x00000003 +#define BP_APBX_CHn_CMD_DMA_READ 0 +#define BF_APBX_CHn_CMD_DMA_READ(v) \ + (((v) << BP_APBX_CHn_CMD_DMA_READ) & BM_APBX_CHn_CMD_DMA_READ) +#define BP_APBX_CHn_CMD_COMMAND 0 +#define BM_APBX_CHn_CMD_COMMAND 0x00000003 +#define BF_APBX_CHn_CMD_COMMAND(v) \ + (((v) << BP_APBX_CHn_CMD_COMMAND) & BM_APBX_CHn_CMD_COMMAND) +#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 + +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x70, 0x70) +HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x80, 0x70) +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << BP_APBX_CHn_SEMA_INCREMENT_SEMA) & \ + BM_APBX_CHn_SEMA_INCREMENT_SEMA) +#define BP_APBX_CHn_SEMA_PHORE 16 +#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x90, 0x70) +HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0xA0, 0x70) +HW_REGISTER_RO(HW_APBX_VERSION, REGS_APBX_BASE, 0x3F0) + +#endif /* _INCLUDE_ASM_ARCH_REGS_APBX_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h new file mode 100644 index 000000000000..229ee75f90d9 --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h @@ -0,0 +1,85 @@ +#ifndef _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H +#define _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H + +#include <mach/stmp3xxx_regs.h> + +#define REGS_CLKCTRL_BASE (REGS_BASE + 0x00040000) + +#define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00) +HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00) +#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 +#define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x10) +HW_REGISTER(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x10) + +#define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x20) +HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x20) +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x30) +HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x30) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0 /* for compatitibility */ +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) +#define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x40) +HW_REGISTER(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x40) +#define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x50) +HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x50) +#define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x60) +HW_REGISTER(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x60) +#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 +#define BM_CLKCTRL_PIX_BUSY 0x20000000 +#define BM_CLKCTRL_PIX_DIV 0x00007FFF +#define BP_CLKCTRL_PIX_DIV 0 +#define BF_CLKCTRL_PIX_DIV(v) \ + (((v) << BP_CLKCTRL_PIX_DIV) & BM_CLKCTRL_PIX_DIV) +#define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x70) +HW_REGISTER(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x70) +#define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x80) +HW_REGISTER(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x80) +#define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x90) +HW_REGISTER(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x90) +#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0xA0) +HW_REGISTER(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0xA0) +#define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0xB0) +HW_REGISTER(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0xB0) +#define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0xC0) +HW_REGISTER(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0xC0) +#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0xD0) +HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0xD0) +#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 +#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 +#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 +#define BP_CLKCTRL_FRAC_IOFRAC 24 +#define BF_CLKCTRL_FRAC_IOFRAC(v) \ + (((v) << BP_CLKCTRL_FRAC_IOFRAC) & BM_CLKCTRL_FRAC_IOFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 +#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 +#define BP_CLKCTRL_FRAC_PIXFRAC 16 +#define BF_CLKCTRL_FRAC_PIXFRAC(v) \ + (((v) << BP_CLKCTRL_FRAC_PIXFRAC) & BM_CLKCTRL_FRAC_PIXFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 +#define BP_CLKCTRL_FRAC_EMIFRAC 8 +#define BF_CLKCTRL_FRAC_EMIFRAC(v) \ + (((v) << BP_CLKCTRL_FRAC_EMIFRAC) & BM_CLKCTRL_FRAC_EMIFRAC) +#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F +#define BP_CLKCTRL_FRAC_CPUFRAC 0 +#define BF_CLKCTRL_FRAC_CPUFRAC(v) \ + (((v) << BP_CLKCTRL_FRAC_CPUFRAC) & BM_CLKCTRL_FRAC_CPUFRAC) +#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0xE0) +HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0xE0) +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 +#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 +HW_REGISTER_WO(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0xF0) +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 +#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h new file mode 100644 index 000000000000..8a92f923f6bd --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h @@ -0,0 +1,36 @@ +/* + * Freescale STMP378X: clock registers definitions + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _INCLUDE_ASM_ARCH_REGS_ICOLL_H +#define _INCLUDE_ASM_ARCH_REGS_ICOLL_H + + +#include <mach/stmp3xxx_regs.h> + +#define REGS_ICOLL_BASE (REGS_BASE + 0x00000000) + +HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00) +HW_REGISTER_WO(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x10) +HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x20) +#define BM_ICOLL_CTRL_CLKGATE 0x40000000 +#define BM_ICOLL_CTRL_SFTRST 0x80000000 +HW_REGISTER_RO(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x30) + +HW_REGISTER_INDEXED(HW_ICOLL_PRIORITYn, REGS_ICOLL_BASE, 0x60, 0x10) + +#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h new file mode 100644 index 000000000000..b114ecd9a5eb --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h @@ -0,0 +1,159 @@ +/* + * STMP pinmux register definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _INCLUDE_ASM_ARCH_REGS_PINCTRL_H +#define _INCLUDE_ASM_ARCH_REGS_PINCTRL_H + +#include <mach/stmp3xxx_regs.h> + +#ifndef REGS_PINCTRL_BASE +#define REGS_PINCTRL_BASE (REGS_BASE + 0x00018000) +#endif /* REGS_PINCTRL_BASE */ + +HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0) + +#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x100) +HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x100) +#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x110) +HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x110) +#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x120) +HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x120) +#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x130) +HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x130) +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x140) +HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x140) +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x150) +HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x150) +#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x160) +HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x160) +#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x170) +HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x170) + +HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x200) +#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x200) +HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x210) +#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x210) +HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x220) +#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x220) +HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x230) +#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x230) +HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x240) +#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x240) +HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x250) +#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x250) +HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x260) +#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x260) +HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x270) +#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x270) +HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x280) +#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x280) +HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x290) +#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x290) +HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x2a0) +#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x2a0) +HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x2b0) +#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x2b0) +HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x2c0) +#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x2c0) +HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x2d0) +#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x2d0) +HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x2e0) +#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x2e0) + + +HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x300) +#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x300) +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x310) +#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x310) +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000 +#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000 +#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000 +#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000 +HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x320) +#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x320) +HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x330) +#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x330) + +#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x400) +HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x400) +#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x410) +HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x410) +#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x420) +HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x420) + +#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x500) +HW_REGISTER_RO(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x500) +#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x510) +HW_REGISTER_RO(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x510) +#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x520) +HW_REGISTER_RO(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x520) + +#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x600) +HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x600) +#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x610) +HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x610) +#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x620) +HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x620) + +HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x700) +#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x700) +HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x710) +#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x710) +HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x720) +#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x720) + +HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x800) +#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x800) +HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x810) +#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x810) +HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x820) +#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x820) + +HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x900) +#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x900) +HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x910) +#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x910) +HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x920) +#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x920) + +HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0xA00) +#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0xa00) +HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0xA10) +#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0xa10) +HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0xA20) +#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0xa20) + +HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0xB00) +#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0xb00) +HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0xB10) +#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0xb10) +HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0xB20) +#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0xb20) + +#endif /* _INCLUDE_ASM_ARCH_REGS_PINCTRL_H */ + diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h new file mode 100644 index 000000000000..d15cd6601e7f --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-power.h @@ -0,0 +1,31 @@ +/* + * STMP POWER Register Definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM___POWER_H +#define __ARCH_ARM___POWER_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_POWER_BASE (void __iomem *)(REGS_BASE + 0x44000) +#define REGS_POWER_BASE_PHYS (0x80044000) +#define REGS_POWER_SIZE 0x00002000 +HW_REGISTER(HW_POWER_MINPWR, REGS_POWER_BASE, 0x00000020) +HW_REGISTER(HW_POWER_CHARGE, REGS_POWER_BASE, 0x00000030) +#endif /* __ARCH_ARM___POWER_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h new file mode 100644 index 000000000000..7f000306e890 --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h @@ -0,0 +1,52 @@ +/* + * include/asm-arm/arch-stmp3xxx/regstimer.h + * + * Copyright (c) 2008 SigmaTel Inc + * Copyright (c) 2008 Embedded Alley Solutions, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ARCH_ARM_REGS_TIMROT_H +#define __ARCH_ARM_REGS_TIMROT_H + +#include <mach/stmp3xxx_regs.h> + +#define REGS_TIMROT_BASE (REGS_BASE + 0x00068000) + +HW_REGISTER(HW_TIMROT_ROTCTRL, REGS_TIMROT_BASE, 0) +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 + +HW_REGISTER_INDEXED(HW_TIMROT_TIMCTRLn, REGS_TIMROT_BASE, 0x20, 0x20) +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & BM_TIMROT_TIMCTRLn_RELOAD) +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & BM_TIMROT_TIMCTRLn_UPDATE) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BF_TIMROT_TIMCTRLn_POLARITY(v) \ + (((v) << 8) & BM_TIMROT_TIMCTRLn_POLARITY) +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BF_TIMROT_TIMCTRLn_IRQ_EN(v) \ + (((v) << 14) & BM_TIMROT_TIMCTRLn_IRQ_EN) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & BM_TIMROT_TIMCTRLn_IRQ) +HW_REGISTER_0_INDEXED(HW_TIMROT_TIMCOUNTn, REGS_TIMROT_BASE, 0x30, 0x20) + +#endif /* __ARCH_ARM_REGSTIMER_H */ diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c new file mode 100644 index 000000000000..83a41c90c252 --- /dev/null +++ b/arch/arm/mach-stmp37xx/stmp37xx.c @@ -0,0 +1,217 @@ +/* + * Freescale STMP37XX platform support + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <asm/mach/irq.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> + +#include <mach/stmp3xxx.h> +#include <mach/dma.h> + +#include <mach/regs-icoll.h> +#include <mach/regs-apbh.h> +#include <mach/regs-apbx.h> +#include "stmp37xx.h" + +/* + * IRQ handling + */ +static void stmp37xx_ack_irq(unsigned int irq) +{ + /* Disable IRQ */ + HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8)); + + /* ACK current interrupt */ + HW_ICOLL_LEVELACK_WR(1); + + /* Barrier */ + (void) HW_ICOLL_STAT_RD(); +} + +static void stmp37xx_mask_irq(unsigned int irq) +{ + /* IRQ disable */ + HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8)); +} + +static void stmp37xx_unmask_irq(unsigned int irq) +{ + /* IRQ enable */ + HW_ICOLL_PRIORITYn_SET(irq / 4, 0x04 << ((irq % 4) * 8)); +} + +static struct irq_chip stmp37xx_chip = { + .ack = stmp37xx_ack_irq, + .mask = stmp37xx_mask_irq, + .unmask = stmp37xx_unmask_irq, +}; + +void __init stmp37xx_init_irq(void) +{ + stmp3xxx_init_irq(&stmp37xx_chip); +} + +/* + * DMA interrupt handling + */ +void stmp3xxx_arch_dma_enable_interrupt(int channel) +{ + int dmabus = channel / 16; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL1_SET(1 << (8 + (channel % 16))); + break; + + case STMP3XXX_BUS_APBX: + HW_APBX_CTRL1_SET(1 << (8 + (channel % 16))); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); + +void stmp3xxx_arch_dma_clear_interrupt(int channel) +{ + int dmabus = channel / 16; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL1_CLR(1 << (channel % 16)); + break; + + case STMP3XXX_BUS_APBX: + HW_APBX_CTRL1_CLR(1 << (channel % 16)); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); + +int stmp3xxx_arch_dma_is_interrupt(int channel) +{ + int r = 0; + + int dmabus = channel / 16; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + r = HW_APBH_CTRL1_RD() & (1 << (channel % 16)); + break; + + case STMP3XXX_BUS_APBX: + r = HW_APBX_CTRL1_RD() & (1 << (channel % 16)); + break; + } + return r; +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); + +void stmp3xxx_arch_dma_reset_channel(int channel) +{ + int dmabus = channel / 16; + unsigned chbit = 1 << (channel % 16); + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + /* Reset channel and wait for it to complete */ + HW_APBH_CTRL0_SET(chbit << BP_APBH_CTRL0_RESET_CHANNEL); + while (HW_APBH_CTRL0_RD() & + (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) + continue; + break; + + case STMP3XXX_BUS_APBX: + /* Reset channel and wait for it to complete */ + HW_APBX_CTRL0_SET(chbit << BP_APBX_CTRL0_RESET_CHANNEL); + while (HW_APBX_CTRL0_RD() & + (chbit << BP_APBX_CTRL0_RESET_CHANNEL)) + continue; + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); + +void stmp3xxx_arch_dma_freeze(int channel) +{ + int dmabus = channel / 16; + unsigned chbit = 1 << (channel % 16); + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL0_SET(1<<chbit); + break; + case STMP3XXX_BUS_APBX: + HW_APBX_CTRL0_SET(1<<chbit); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze); + +void stmp3xxx_arch_dma_unfreeze(int channel) +{ + int dmabus = channel / 16; + unsigned chbit = 1 << (channel % 16); + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL0_CLR(1<<chbit); + break; + case STMP3XXX_BUS_APBX: + HW_APBX_CTRL0_CLR(1<<chbit); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze); + +/* + * The registers are all very closely mapped, so we might as well map them all + * with a single mapping + * + * Logical Physical + * f0000000 80000000 On-chip registers + * f1000000 00000000 256k on-chip SRAM + */ +static struct map_desc stmp37xx_io_desc[] __initdata = { + { + .virtual = (u32)STMP3XXX_REGS_BASE, + .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE), + .length = SZ_1M, + .type = MT_DEVICE + }, + { + .virtual = (u32)STMP3XXX_OCRAM_BASE, + .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE), + .length = STMP3XXX_OCRAM_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init stmp37xx_map_io(void) +{ + iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc)); +} diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h new file mode 100644 index 000000000000..0b75fb796a64 --- /dev/null +++ b/arch/arm/mach-stmp37xx/stmp37xx.h @@ -0,0 +1,24 @@ +/* + * Freescale STMP37XX/STMP378X internal functions and data declarations + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_STMP37XX_H +#define __MACH_STMP37XX_H + +void stmp37xx_map_io(void); +void stmp37xx_init_irq(void); + +#endif /* __MACH_STMP37XX_H */ diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c new file mode 100644 index 000000000000..adfbdc7f8e27 --- /dev/null +++ b/arch/arm/mach-stmp37xx/stmp37xx_devb.c @@ -0,0 +1,83 @@ +/* + * Freescale STMP37XX development board support + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/stmp3xxx.h> +#include <mach/pins.h> +#include <mach/pinmux.h> +#include "stmp37xx.h" + +/* + * List of STMP37xx development board specific devices + */ +static struct platform_device *stmp37xx_devb_devices[] = { + &stmp3xxx_dbguart, +}; + +static struct pin_desc dbguart_pins_0[] = { + { PINID_PWM0, PIN_FUN3, }, + { PINID_PWM1, PIN_FUN3, }, +}; + +static struct pin_group dbguart_pins[] = { + [0] = { + .pins = dbguart_pins_0, + .nr_pins = ARRAY_SIZE(dbguart_pins_0), + }, +}; + +static int dbguart_pins_control(int id, int request) +{ + int r = 0; + + if (request) + r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart"); + else + stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart"); + return r; +} + + +static void __init stmp37xx_devb_init(void) +{ + stmp3xxx_pinmux_init(NR_REAL_IRQS); + + /* Init STMP3xxx platform */ + stmp3xxx_init(); + + stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; + /* Add STMP37xx development board devices */ + platform_add_devices(stmp37xx_devb_devices, + ARRAY_SIZE(stmp37xx_devb_devices)); +} + +MACHINE_START(STMP37XX, "STMP37XX") + .phys_io = 0x80000000, + .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, + .boot_params = 0x40000100, + .map_io = stmp37xx_map_io, + .init_irq = stmp37xx_init_irq, + .timer = &stmp3xxx_timer, + .init_machine = stmp37xx_devb_init, +MACHINE_END diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig new file mode 100644 index 000000000000..337b9aabce49 --- /dev/null +++ b/arch/arm/mach-u300/Kconfig @@ -0,0 +1,105 @@ +if ARCH_U300 + +menu "ST-Ericsson AB U300/U330/U335/U365 Platform" + +comment "ST-Ericsson Mobile Platform Products" + +config MACH_U300 + bool "U300" + +comment "ST-Ericsson U300/U330/U335/U365 Feature Selections" + +choice + prompt "U300/U330/U335/U365 system type" + default MACH_U300_BS2X + ---help--- + You need to select the target system, i.e. the + U300/U330/U335/U365 board that you want to compile your kernel + for. + +config MACH_U300_BS2X + bool "S26/S26/B25/B26 Test Products" + depends on MACH_U300 + help + Select this if you're developing on the + S26/S25 test products. (Also works on + B26/B25 big boards.) + +config MACH_U300_BS330 + bool "S330/B330 Test Products" + depends on MACH_U300 + help + Select this if you're developing on the + S330/B330 test products. + +config MACH_U300_BS335 + bool "S335/B335 Test Products" + depends on MACH_U300 + help + Select this if you're developing on the + S335/B335 test products. + +config MACH_U300_BS365 + bool "S365/B365 Test Products" + depends on MACH_U300 + help + Select this if you're developing on the + S365/B365 test products. + +endchoice + +choice + prompt "Memory configuration" + default MACH_U300_SINGLE_RAM + ---help--- + You have to config the kernel according to the physical memory + configuration. + +config MACH_U300_SINGLE_RAM + bool "Single RAM" + help + Select this if you want support for Single RAM phones. + +config MACH_U300_DUAL_RAM + bool "Dual RAM" + help + Select this if you want support for Dual RAM phones. + This is two RAM memorys on different EMIFs. +endchoice + +config U300_DEBUG + bool "Debug support for U300" + depends on PM + help + Debug support for U300 in sysfs, procfs etc. + +config MACH_U300_SEMI_IS_SHARED + bool "The SEMI is used by both the access and application side" + depends on MACH_U300 + help + This makes it possible to use the SEMI (Shared External + Memory Interface) from both from access and application + side. + +comment "All the settings below must match the bootloader's settings" + +config MACH_U300_ACCESS_MEM_SIZE + int "Access CPU memory allocation" + range 7 25 + depends on MACH_U300_SINGLE_RAM + default 13 + help + How much memory in MiB that the Access side CPU has allocated + +config MACH_U300_2MB_ALIGNMENT_FIX + bool "2MiB alignment fix" + depends on MACH_U300_SINGLE_RAM + default y + help + If yes and the Access side CPU has allocated an odd size in + MiB, this fix gives you one MiB extra that would otherwise be + lost due to Linux 2 MiB alignment policy. + +endmenu + +endif diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile new file mode 100644 index 000000000000..24950e0df4b4 --- /dev/null +++ b/arch/arm/mach-u300/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for the linux kernel, U300 machine. +# + +obj-y := core.o clock.o timer.o gpio.o padmux.o +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_ARCH_U300) += u300.o +obj-$(CONFIG_MMC) += mmc.o diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c new file mode 100644 index 000000000000..d6f8232757ff --- /dev/null +++ b/arch/arm/mach-u300/clock.c @@ -0,0 +1,1487 @@ +/* + * + * arch/arm/mach-u300/clock.c + * + * + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Define clocks in the app platform. + * Author: Linus Walleij <linus.walleij@stericsson.com> + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + * + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/string.h> +#include <linux/clk.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/debugfs.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/timer.h> +#include <linux/io.h> + +#include <asm/clkdev.h> +#include <mach/hardware.h> +#include <mach/syscon.h> + +#include "clock.h" + +/* + * TODO: + * - move all handling of the CCR register into this file and create + * a spinlock for the CCR register + * - switch to the clkdevice lookup mechanism that maps clocks to + * device ID:s instead when it becomes available in kernel 2.6.29. + * - implement rate get/set for all clocks that need it. + */ + +/* + * Syscon clock I/O registers lock so clock requests don't collide + * NOTE: this is a local lock only used to lock access to clock and + * reset registers in syscon. + */ +static DEFINE_SPINLOCK(syscon_clkreg_lock); +static DEFINE_SPINLOCK(syscon_resetreg_lock); + +/* + * The clocking hierarchy currently looks like this. + * NOTE: the idea is NOT to show how the clocks are routed on the chip! + * The ideas is to show dependencies, so a clock higher up in the + * hierarchy has to be on in order for another clock to be on. Now, + * both CPU and DMA can actually be on top of the hierarchy, and that + * is not modeled currently. Instead we have the backbone AMBA bus on + * top. This bus cannot be programmed in any way but conceptually it + * needs to be active for the bridges and devices to transport data. + * + * Please be aware that a few clocks are hw controlled, which mean that + * the hw itself can turn on/off or change the rate of the clock when + * needed! + * + * AMBA bus + * | + * +- CPU + * +- NANDIF NAND Flash interface + * +- SEMI Shared Memory interface + * +- ISP Image Signal Processor (U335 only) + * +- CDS (U335 only) + * +- DMA Direct Memory Access Controller + * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL) + * +- APEX + * +- VIDEO_ENC AVE2/3 Video Encoder + * +- XGAM Graphics Accelerator Controller + * +- AHB + * | + * +- ahb:0 AHB Bridge + * | | + * | +- ahb:1 INTCON Interrupt controller + * | +- ahb:3 MSPRO Memory Stick Pro controller + * | +- ahb:4 EMIF External Memory interface + * | + * +- fast:0 FAST bridge + * | | + * | +- fast:1 MMCSD MMC/SD card reader controller + * | +- fast:2 I2S0 PCM I2S channel 0 controller + * | +- fast:3 I2S1 PCM I2S channel 1 controller + * | +- fast:4 I2C0 I2C channel 0 controller + * | +- fast:5 I2C1 I2C channel 1 controller + * | +- fast:6 SPI SPI controller + * | +- fast:7 UART1 Secondary UART (U335 only) + * | + * +- slow:0 SLOW bridge + * | + * +- slow:1 SYSCON (not possible to control) + * +- slow:2 WDOG Watchdog + * +- slow:3 UART0 primary UART + * +- slow:4 TIMER_APP Application timer - used in Linux + * +- slow:5 KEYPAD controller + * +- slow:6 GPIO controller + * +- slow:7 RTC controller + * +- slow:8 BT Bus Tracer (not used currently) + * +- slow:9 EH Event Handler (not used currently) + * +- slow:a TIMER_ACC Access style timer (not used currently) + * +- slow:b PPM (U335 only, what is that?) + */ + +/* + * Reset control functions. We remember if a block has been + * taken out of reset and don't remove the reset assertion again + * and vice versa. Currently we only remove resets so the + * enablement function is defined out. + */ +static void syscon_block_reset_enable(struct clk *clk) +{ + u16 val; + unsigned long iflags; + + /* Not all blocks support resetting */ + if (!clk->res_reg || !clk->res_mask) + return; + spin_lock_irqsave(&syscon_resetreg_lock, iflags); + val = readw(clk->res_reg); + val |= clk->res_mask; + writew(val, clk->res_reg); + spin_unlock_irqrestore(&syscon_resetreg_lock, iflags); + clk->reset = true; +} + +static void syscon_block_reset_disable(struct clk *clk) +{ + u16 val; + unsigned long iflags; + + /* Not all blocks support resetting */ + if (!clk->res_reg || !clk->res_mask) + return; + spin_lock_irqsave(&syscon_resetreg_lock, iflags); + val = readw(clk->res_reg); + val &= ~clk->res_mask; + writew(val, clk->res_reg); + spin_unlock_irqrestore(&syscon_resetreg_lock, iflags); + clk->reset = false; +} + +int __clk_get(struct clk *clk) +{ + u16 val; + + /* The MMC and MSPRO clocks need some special set-up */ + if (!strcmp(clk->name, "MCLK")) { + /* Set default MMC clock divisor to 18.9 MHz */ + writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R); + val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR); + /* Disable the MMC feedback clock */ + val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE; + /* Disable MSPRO frequency */ + val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR); + } + if (!strcmp(clk->name, "MSPRO")) { + val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR); + /* Disable the MMC feedback clock */ + val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE; + /* Enable MSPRO frequency */ + val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR); + } + return 1; +} +EXPORT_SYMBOL(__clk_get); + +void __clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(__clk_put); + +static void syscon_clk_disable(struct clk *clk) +{ + unsigned long iflags; + + /* Don't touch the hardware controlled clocks */ + if (clk->hw_ctrld) + return; + + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR); + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); +} + +static void syscon_clk_enable(struct clk *clk) +{ + unsigned long iflags; + + /* Don't touch the hardware controlled clocks */ + if (clk->hw_ctrld) + return; + + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER); + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); +} + +static u16 syscon_clk_get_rate(void) +{ + u16 val; + unsigned long iflags; + + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); + val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); + return val; +} + +#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER +static void enable_i2s0_vcxo(void) +{ + u16 val; + unsigned long iflags; + + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + /* Set I2S0 to use the VCXO 26 MHz clock */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); + val |= U300_SYSCON_CCR_TURN_VCXO_ON; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + val |= U300_SYSCON_CCR_I2S0_USE_VCXO; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); + val |= U300_SYSCON_CEFR_I2S0_CLK_EN; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR); + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); +} + +static void enable_i2s1_vcxo(void) +{ + u16 val; + unsigned long iflags; + + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + /* Set I2S1 to use the VCXO 26 MHz clock */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); + val |= U300_SYSCON_CCR_TURN_VCXO_ON; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + val |= U300_SYSCON_CCR_I2S1_USE_VCXO; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); + val |= U300_SYSCON_CEFR_I2S1_CLK_EN; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR); + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); +} + +static void disable_i2s0_vcxo(void) +{ + u16 val; + unsigned long iflags; + + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + /* Disable I2S0 use of the VCXO 26 MHz clock */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); + val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + /* Deactivate VCXO if noone else is using VCXO */ + if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO)) + val &= ~U300_SYSCON_CCR_TURN_VCXO_ON; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); + val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR); + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); +} + +static void disable_i2s1_vcxo(void) +{ + u16 val; + unsigned long iflags; + + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + /* Disable I2S1 use of the VCXO 26 MHz clock */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); + val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + /* Deactivate VCXO if noone else is using VCXO */ + if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO)) + val &= ~U300_SYSCON_CCR_TURN_VCXO_ON; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR); + val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR); + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); +} +#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */ + + +static void syscon_clk_rate_set_mclk(unsigned long rate) +{ + u16 val; + u32 reg; + unsigned long iflags; + + switch (rate) { + case 18900000: + val = 0x0054; + break; + case 20800000: + val = 0x0044; + break; + case 23100000: + val = 0x0043; + break; + case 26000000: + val = 0x0033; + break; + case 29700000: + val = 0x0032; + break; + case 34700000: + val = 0x0022; + break; + case 41600000: + val = 0x0021; + break; + case 52000000: + val = 0x0011; + break; + case 104000000: + val = 0x0000; + break; + default: + printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n", + rate); + return; + } + + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) & + ~U300_SYSCON_MMF0R_MASK; + writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R); + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); +} + +void syscon_clk_rate_set_cpuclk(unsigned long rate) +{ + u16 val; + unsigned long iflags; + + switch (rate) { + case 13000000: + val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER; + break; + case 52000000: + val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE; + break; + case 104000000: + val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH; + break; + case 208000000: + val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST; + break; + default: + return; + } + spin_lock_irqsave(&syscon_clkreg_lock, iflags); + val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) & + ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + spin_unlock_irqrestore(&syscon_clkreg_lock, iflags); +} +EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk); + +void clk_disable(struct clk *clk) +{ + unsigned long iflags; + + spin_lock_irqsave(&clk->lock, iflags); + if (clk->usecount > 0 && !(--clk->usecount)) { + /* some blocks lack clocking registers and cannot be disabled */ + if (clk->disable) + clk->disable(clk); + if (likely((u32)clk->parent)) + clk_disable(clk->parent); + } +#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER + if (unlikely(!strcmp(clk->name, "I2S0"))) + disable_i2s0_vcxo(); + if (unlikely(!strcmp(clk->name, "I2S1"))) + disable_i2s1_vcxo(); +#endif + spin_unlock_irqrestore(&clk->lock, iflags); +} +EXPORT_SYMBOL(clk_disable); + +int clk_enable(struct clk *clk) +{ + int ret = 0; + unsigned long iflags; + + spin_lock_irqsave(&clk->lock, iflags); + if (clk->usecount++ == 0) { + if (likely((u32)clk->parent)) + ret = clk_enable(clk->parent); + + if (unlikely(ret != 0)) + clk->usecount--; + else { + /* remove reset line (we never enable reset again) */ + syscon_block_reset_disable(clk); + /* clocks without enable function are always on */ + if (clk->enable) + clk->enable(clk); +#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER + if (unlikely(!strcmp(clk->name, "I2S0"))) + enable_i2s0_vcxo(); + if (unlikely(!strcmp(clk->name, "I2S1"))) + enable_i2s1_vcxo(); +#endif + } + } + spin_unlock_irqrestore(&clk->lock, iflags); + return ret; + +} +EXPORT_SYMBOL(clk_enable); + +/* Returns the clock rate in Hz */ +static unsigned long clk_get_rate_cpuclk(struct clk *clk) +{ + u16 val; + + val = syscon_clk_get_rate(); + + switch (val) { + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: + return 13000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: + return 52000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: + return 104000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: + return 208000000; + default: + break; + } + return clk->rate; +} + +static unsigned long clk_get_rate_ahb_clk(struct clk *clk) +{ + u16 val; + + val = syscon_clk_get_rate(); + + switch (val) { + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: + return 6500000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: + return 26000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: + return 52000000; + default: + break; + } + return clk->rate; + +} + +static unsigned long clk_get_rate_emif_clk(struct clk *clk) +{ + u16 val; + + val = syscon_clk_get_rate(); + + switch (val) { + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: + return 13000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: + return 52000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: + return 104000000; + default: + break; + } + return clk->rate; + +} + +static unsigned long clk_get_rate_xgamclk(struct clk *clk) +{ + u16 val; + + val = syscon_clk_get_rate(); + + switch (val) { + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: + return 6500000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: + return 26000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: + return 52000000; + default: + break; + } + + return clk->rate; +} + +static unsigned long clk_get_rate_mclk(struct clk *clk) +{ + u16 val; + + val = syscon_clk_get_rate(); + + switch (val) { + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: + /* + * Here, the 208 MHz PLL gets shut down and the always + * on 13 MHz PLL used for RTC etc kicks into use + * instead. + */ + return 13000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: + { + /* + * This clock is under program control. The register is + * divided in two nybbles, bit 7-4 gives cycles-1 to count + * high, bit 3-0 gives cycles-1 to count low. Distribute + * these with no more than 1 cycle difference between + * low and high and add low and high to get the actual + * divisor. The base PLL is 208 MHz. Writing 0x00 will + * divide by 1 and 1 so the highest frequency possible + * is 104 MHz. + * + * e.g. 0x54 => + * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz + */ + u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) & + U300_SYSCON_MMF0R_MASK; + switch (val) { + case 0x0054: + return 18900000; + case 0x0044: + return 20800000; + case 0x0043: + return 23100000; + case 0x0033: + return 26000000; + case 0x0032: + return 29700000; + case 0x0022: + return 34700000; + case 0x0021: + return 41600000; + case 0x0011: + return 52000000; + case 0x0000: + return 104000000; + default: + break; + } + } + default: + break; + } + + return clk->rate; +} + +static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk) +{ + u16 val; + + val = syscon_clk_get_rate(); + + switch (val) { + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: + return 13000000; + case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: + case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: + return 26000000; + default: + break; + } + + return clk->rate; +} + +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk->get_rate) + return clk->get_rate(clk); + else + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate) +{ + if (rate >= 18900000) + return 18900000; + if (rate >= 20800000) + return 20800000; + if (rate >= 23100000) + return 23100000; + if (rate >= 26000000) + return 26000000; + if (rate >= 29700000) + return 29700000; + if (rate >= 34700000) + return 34700000; + if (rate >= 41600000) + return 41600000; + if (rate >= 52000000) + return 52000000; + return -EINVAL; +} + +static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate) +{ + if (rate >= 13000000) + return 13000000; + if (rate >= 52000000) + return 52000000; + if (rate >= 104000000) + return 104000000; + if (rate >= 208000000) + return 208000000; + return -EINVAL; +} + +/* + * This adjusts a requested rate to the closest exact rate + * a certain clock can provide. For a fixed clock it's + * mostly clk->rate. + */ +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */ + /* Else default to fixed value */ + + if (clk->round_rate) { + return (long) clk->round_rate(clk, rate); + } else { + printk(KERN_ERR "clock: Failed to round rate of %s\n", + clk->name); + } + return (long) clk->rate; +} +EXPORT_SYMBOL(clk_round_rate); + +static int clk_set_rate_mclk(struct clk *clk, unsigned long rate) +{ + syscon_clk_rate_set_mclk(clk_round_rate(clk, rate)); + return 0; +} + +static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate) +{ + syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate)); + return 0; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + /* TODO: set for EMIFCLK and AHBCLK */ + /* Else assume the clock is fixed and fail */ + if (clk->set_rate) { + return clk->set_rate(clk, rate); + } else { + printk(KERN_ERR "clock: Failed to set %s to %ld hz\n", + clk->name, rate); + return -1; + } +} +EXPORT_SYMBOL(clk_set_rate); + +/* + * Clock definitions. The clock parents are set to respective + * bridge and the clock framework makes sure that the clocks have + * parents activated and are brought out of reset when in use. + * + * Clocks that have hw_ctrld = true are hw controlled, and the hw + * can by itself turn these clocks on and off. + * So in other words, we don't really have to care about them. + */ + +static struct clk amba_clk = { + .name = "AMBA", + .rate = 52000000, /* this varies! */ + .hw_ctrld = true, + .reset = false, +}; + +/* + * These blocks are connected directly to the AMBA bus + * with no bridge. + */ + +static struct clk cpu_clk = { + .name = "CPU", + .parent = &amba_clk, + .rate = 208000000, /* this varies! */ + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_CPU_RESET_EN, + .set_rate = clk_set_rate_cpuclk, + .get_rate = clk_get_rate_cpuclk, + .round_rate = clk_round_rate_cpuclk, +}; + +static struct clk nandif_clk = { + .name = "NANDIF", + .parent = &amba_clk, + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_NANDIF_RESET_EN, + .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk semi_clk = { + .name = "SEMI", + .parent = &amba_clk, + .rate = 0, /* FIXME */ + /* It is not possible to reset SEMI */ + .hw_ctrld = false, + .reset = false, + .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +#ifdef CONFIG_MACH_U300_BS335 +static struct clk isp_clk = { + .name = "ISP", + .parent = &amba_clk, + .rate = 0, /* FIXME */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_ISP_RESET_EN, + .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk cds_clk = { + .name = "CDS", + .parent = &amba_clk, + .rate = 0, /* FIXME */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_CDS_RESET_EN, + .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; +#endif + +static struct clk dma_clk = { + .name = "DMA", + .parent = &amba_clk, + .rate = 52000000, /* this varies! */ + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_DMAC_RESET_EN, + .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk aaif_clk = { + .name = "AAIF", + .parent = &amba_clk, + .rate = 52000000, /* this varies! */ + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_AAIF_RESET_EN, + .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk apex_clk = { + .name = "APEX", + .parent = &amba_clk, + .rate = 0, /* FIXME */ + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_APEX_RESET_EN, + .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk video_enc_clk = { + .name = "VIDEO_ENC", + .parent = &amba_clk, + .rate = 208000000, /* this varies! */ + .hw_ctrld = false, + .reset = false, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + /* This has XGAM in the name but refers to the video encoder */ + .res_mask = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN, + .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk xgam_clk = { + .name = "XGAMCLK", + .parent = &amba_clk, + .rate = 52000000, /* this varies! */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_XGAM_RESET_EN, + .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN, + .get_rate = clk_get_rate_xgamclk, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +/* This clock is used to activate the video encoder */ +static struct clk ahb_clk = { + .name = "AHB", + .parent = &amba_clk, + .rate = 52000000, /* this varies! */ + .hw_ctrld = false, /* This one is set to false due to HW bug */ + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_AHB_RESET_EN, + .clk_val = U300_SYSCON_SBCER_AHB_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, + .get_rate = clk_get_rate_ahb_clk, +}; + + +/* + * Clocks on the AHB bridge + */ + +static struct clk ahb_subsys_clk = { + .name = "AHB_SUBSYS", + .parent = &amba_clk, + .rate = 52000000, /* this varies! */ + .hw_ctrld = true, + .reset = false, + .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, + .get_rate = clk_get_rate_ahb_clk, +}; + +static struct clk intcon_clk = { + .name = "INTCON", + .parent = &ahb_subsys_clk, + .rate = 52000000, /* this varies! */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN, + /* INTCON can be reset but not clock-gated */ +}; + +static struct clk mspro_clk = { + .name = "MSPRO", + .parent = &ahb_subsys_clk, + .rate = 0, /* FIXME */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_MSPRO_RESET_EN, + .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk emif_clk = { + .name = "EMIF", + .parent = &ahb_subsys_clk, + .rate = 104000000, /* this varies! */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR, + .res_mask = U300_SYSCON_RRR_EMIF_RESET_EN, + .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, + .get_rate = clk_get_rate_emif_clk, +}; + + +/* + * Clocks on the FAST bridge + */ +static struct clk fast_clk = { + .name = "FAST_BRIDGE", + .parent = &amba_clk, + .rate = 13000000, /* this varies! */ + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, + .res_mask = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE, + .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk mmcsd_clk = { + .name = "MCLK", + .parent = &fast_clk, + .rate = 18900000, /* this varies! */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, + .res_mask = U300_SYSCON_RFR_MMC_RESET_ENABLE, + .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN, + .get_rate = clk_get_rate_mclk, + .set_rate = clk_set_rate_mclk, + .round_rate = clk_round_rate_mclk, + .disable = syscon_clk_disable, + .enable = syscon_clk_enable, +}; + +static struct clk i2s0_clk = { + .name = "i2s0", + .parent = &fast_clk, + .rate = 26000000, /* this varies! */ + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, + .res_mask = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE, + .clk_val = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, + .get_rate = clk_get_rate_i2s_i2c_spi, +}; + +static struct clk i2s1_clk = { + .name = "i2s1", + .parent = &fast_clk, + .rate = 26000000, /* this varies! */ + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, + .res_mask = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE, + .clk_val = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, + .get_rate = clk_get_rate_i2s_i2c_spi, +}; + +static struct clk i2c0_clk = { + .name = "I2C0", + .parent = &fast_clk, + .rate = 26000000, /* this varies! */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, + .res_mask = U300_SYSCON_RFR_I2C0_RESET_ENABLE, + .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, + .get_rate = clk_get_rate_i2s_i2c_spi, +}; + +static struct clk i2c1_clk = { + .name = "I2C1", + .parent = &fast_clk, + .rate = 26000000, /* this varies! */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, + .res_mask = U300_SYSCON_RFR_I2C1_RESET_ENABLE, + .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, + .get_rate = clk_get_rate_i2s_i2c_spi, +}; + +static struct clk spi_clk = { + .name = "SPI", + .parent = &fast_clk, + .rate = 26000000, /* this varies! */ + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, + .res_mask = U300_SYSCON_RFR_SPI_RESET_ENABLE, + .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, + .get_rate = clk_get_rate_i2s_i2c_spi, +}; + +#ifdef CONFIG_MACH_U300_BS335 +static struct clk uart1_clk = { + .name = "UART1", + .parent = &fast_clk, + .rate = 13000000, + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, + .res_mask = U300_SYSCON_RFR_UART1_RESET_ENABLE, + .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; +#endif + + +/* + * Clocks on the SLOW bridge + */ +static struct clk slow_clk = { + .name = "SLOW_BRIDGE", + .parent = &amba_clk, + .rate = 13000000, + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN, + .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +/* TODO: implement SYSCON clock? */ + +static struct clk wdog_clk = { + .name = "WDOG", + .parent = &slow_clk, + .hw_ctrld = false, + .rate = 32768, + .reset = false, + /* This is always on, cannot be enabled/disabled or reset */ +}; + +/* This one is hardwired to PLL13 */ +static struct clk uart_clk = { + .name = "UARTCLK", + .parent = &slow_clk, + .rate = 13000000, + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_UART_RESET_EN, + .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk keypad_clk = { + .name = "KEYPAD", + .parent = &slow_clk, + .rate = 32768, + .hw_ctrld = false, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_KEYPAD_RESET_EN, + .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk gpio_clk = { + .name = "GPIO", + .parent = &slow_clk, + .rate = 13000000, + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_GPIO_RESET_EN, + .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk rtc_clk = { + .name = "RTC", + .parent = &slow_clk, + .rate = 32768, + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_RTC_RESET_EN, + /* This clock is always on, cannot be enabled/disabled */ +}; + +static struct clk bustr_clk = { + .name = "BUSTR", + .parent = &slow_clk, + .rate = 13000000, + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_BTR_RESET_EN, + .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk evhist_clk = { + .name = "EVHIST", + .parent = &slow_clk, + .rate = 13000000, + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_EH_RESET_EN, + .clk_val = U300_SYSCON_SBCER_EH_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk timer_clk = { + .name = "TIMER", + .parent = &slow_clk, + .rate = 13000000, + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_ACC_TMR_RESET_EN, + .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +static struct clk app_timer_clk = { + .name = "TIMER_APP", + .parent = &slow_clk, + .rate = 13000000, + .hw_ctrld = true, + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_APP_TMR_RESET_EN, + .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; + +#ifdef CONFIG_MACH_U300_BS335 +static struct clk ppm_clk = { + .name = "PPM", + .parent = &slow_clk, + .rate = 0, /* FIXME */ + .hw_ctrld = true, /* TODO: Look up if it is hw ctrld or not */ + .reset = true, + .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, + .res_mask = U300_SYSCON_RSR_PPM_RESET_EN, + .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN, + .enable = syscon_clk_enable, + .disable = syscon_clk_disable, +}; +#endif + +#define DEF_LOOKUP(devid, clkref) \ + { \ + .dev_id = devid, \ + .clk = clkref, \ + } + +/* + * Here we only define clocks that are meaningful to + * look up through clockdevice. + */ +static struct clk_lookup lookups[] = { + /* Connected directly to the AMBA bus */ + DEF_LOOKUP("amba", &amba_clk), + DEF_LOOKUP("cpu", &cpu_clk), + DEF_LOOKUP("nandif", &nandif_clk), + DEF_LOOKUP("semi", &semi_clk), +#ifdef CONFIG_MACH_U300_BS335 + DEF_LOOKUP("isp", &isp_clk), + DEF_LOOKUP("cds", &cds_clk), +#endif + DEF_LOOKUP("dma", &dma_clk), + DEF_LOOKUP("aaif", &aaif_clk), + DEF_LOOKUP("apex", &apex_clk), + DEF_LOOKUP("video_enc", &video_enc_clk), + DEF_LOOKUP("xgam", &xgam_clk), + DEF_LOOKUP("ahb", &ahb_clk), + /* AHB bridge clocks */ + DEF_LOOKUP("ahb", &ahb_subsys_clk), + DEF_LOOKUP("intcon", &intcon_clk), + DEF_LOOKUP("mspro", &mspro_clk), + DEF_LOOKUP("pl172", &emif_clk), + /* FAST bridge clocks */ + DEF_LOOKUP("fast", &fast_clk), + DEF_LOOKUP("mmci", &mmcsd_clk), + /* + * The .0 and .1 identifiers on these comes from the platform device + * .id field and are assigned when the platform devices are registered. + */ + DEF_LOOKUP("i2s.0", &i2s0_clk), + DEF_LOOKUP("i2s.1", &i2s1_clk), + DEF_LOOKUP("stddci2c.0", &i2c0_clk), + DEF_LOOKUP("stddci2c.1", &i2c1_clk), + DEF_LOOKUP("pl022", &spi_clk), +#ifdef CONFIG_MACH_U300_BS335 + DEF_LOOKUP("uart1", &uart1_clk), +#endif + /* SLOW bridge clocks */ + DEF_LOOKUP("slow", &slow_clk), + DEF_LOOKUP("wdog", &wdog_clk), + DEF_LOOKUP("uart0", &uart_clk), + DEF_LOOKUP("apptimer", &app_timer_clk), + DEF_LOOKUP("keypad", &keypad_clk), + DEF_LOOKUP("u300-gpio", &gpio_clk), + DEF_LOOKUP("rtc0", &rtc_clk), + DEF_LOOKUP("bustr", &bustr_clk), + DEF_LOOKUP("evhist", &evhist_clk), + DEF_LOOKUP("timer", &timer_clk), +#ifdef CONFIG_MACH_U300_BS335 + DEF_LOOKUP("ppm", &ppm_clk), +#endif +}; + +static void __init clk_register(void) +{ + int i; + + /* Register the lookups */ + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); +} + +/* + * These are the clocks for cells registered as primecell drivers + * on the AMBA bus. These must be on during AMBA device registration + * since the bus probe will attempt to read magic configuration + * registers for these devices. If they are deactivated these probes + * will fail. + * + * + * Please note that on emif, both RAM and NAND is connected in dual + * RAM phones. On single RAM phones, ram is on semi and NAND on emif. + * + */ +void u300_clock_primecells(void) +{ + clk_enable(&intcon_clk); + clk_enable(&uart_clk); +#ifdef CONFIG_MACH_U300_BS335 + clk_enable(&uart1_clk); +#endif + clk_enable(&spi_clk); + + clk_enable(&mmcsd_clk); + +} +EXPORT_SYMBOL(u300_clock_primecells); + +void u300_unclock_primecells(void) +{ + + clk_disable(&intcon_clk); + clk_disable(&uart_clk); +#ifdef CONFIG_MACH_U300_BS335 + clk_disable(&uart1_clk); +#endif + clk_disable(&spi_clk); + clk_disable(&mmcsd_clk); + +} +EXPORT_SYMBOL(u300_unclock_primecells); + +/* + * The interrupt controller is enabled before the clock API is registered. + */ +void u300_enable_intcon_clock(void) +{ + clk_enable(&intcon_clk); +} +EXPORT_SYMBOL(u300_enable_intcon_clock); + +/* + * The timer is enabled before the clock API is registered. + */ +void u300_enable_timer_clock(void) +{ + clk_enable(&app_timer_clk); +} +EXPORT_SYMBOL(u300_enable_timer_clock); + +#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) +/* + * The following makes it possible to view the status (especially + * reference count and reset status) for the clocks in the platform + * by looking into the special file <debugfs>/u300_clocks + */ + +/* A list of all clocks in the platform */ +static struct clk *clks[] = { + /* Top node clock for the AMBA bus */ + &amba_clk, + /* Connected directly to the AMBA bus */ + &cpu_clk, + &nandif_clk, + &semi_clk, +#ifdef CONFIG_MACH_U300_BS335 + &isp_clk, + &cds_clk, +#endif + &dma_clk, + &aaif_clk, + &apex_clk, + &video_enc_clk, + &xgam_clk, + &ahb_clk, + + /* AHB bridge clocks */ + &ahb_subsys_clk, + &intcon_clk, + &mspro_clk, + &emif_clk, + /* FAST bridge clocks */ + &fast_clk, + &mmcsd_clk, + &i2s0_clk, + &i2s1_clk, + &i2c0_clk, + &i2c1_clk, + &spi_clk, +#ifdef CONFIG_MACH_U300_BS335 + &uart1_clk, +#endif + /* SLOW bridge clocks */ + &slow_clk, + &wdog_clk, + &uart_clk, + &app_timer_clk, + &keypad_clk, + &gpio_clk, + &rtc_clk, + &bustr_clk, + &evhist_clk, + &timer_clk, +#ifdef CONFIG_MACH_U300_BS335 + &ppm_clk, +#endif +}; + +static int u300_clocks_show(struct seq_file *s, void *data) +{ + struct clk *clk; + int i; + + seq_printf(s, "CLOCK DEVICE RESET STATE\t" \ + "ACTIVE\tUSERS\tHW CTRL FREQ\n"); + seq_printf(s, "---------------------------------------------" \ + "-----------------------------------------\n"); + for (i = 0; i < ARRAY_SIZE(clks); i++) { + clk = clks[i]; + if (clk != ERR_PTR(-ENOENT)) { + /* Format clock and device name nicely */ + char cdp[33]; + int chars; + + chars = snprintf(&cdp[0], 17, "%s", clk->name); + while (chars < 16) { + cdp[chars] = ' '; + chars++; + } + chars = snprintf(&cdp[16], 17, "%s", clk->dev ? + dev_name(clk->dev) : "N/A"); + while (chars < 16) { + cdp[chars+16] = ' '; + chars++; + } + cdp[32] = '\0'; + if (clk->get_rate) + seq_printf(s, + "%s%s\t%s\t%d\t%s\t%lu Hz\n", + &cdp[0], + clk->reset ? + "ASSERTED" : "RELEASED", + clk->usecount ? "ON" : "OFF", + clk->usecount, + clk->hw_ctrld ? "YES" : "NO ", + clk->get_rate(clk)); + else + seq_printf(s, + "%s%s\t%s\t%d\t%s\t" \ + "(unknown rate)\n", + &cdp[0], + clk->reset ? + "ASSERTED" : "RELEASED", + clk->usecount ? "ON" : "OFF", + clk->usecount, + clk->hw_ctrld ? "YES" : "NO "); + } + } + return 0; +} + +static int u300_clocks_open(struct inode *inode, struct file *file) +{ + return single_open(file, u300_clocks_show, NULL); +} + +static const struct file_operations u300_clocks_operations = { + .open = u300_clocks_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void init_clk_read_procfs(void) +{ + /* Expose a simple debugfs interface to view all clocks */ + (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO, + NULL, NULL, &u300_clocks_operations); +} +#else +static inline void init_clk_read_procfs(void) +{ +} +#endif + +static int __init u300_clock_init(void) +{ + u16 val; + + /* + * FIXME: shall all this powermanagement stuff really live here??? + */ + + /* Set system to run at PLL208, max performance, a known state. */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); + val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + /* Wait for the PLL208 to lock if not locked in yet */ + while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) & + U300_SYSCON_CSR_PLL208_LOCK_IND)); + + /* Power management enable */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR); + val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR); + + clk_register(); + + init_clk_read_procfs(); + + /* + * Some of these may be on when we boot the system so make sure they + * are turned OFF. + */ + syscon_block_reset_enable(&timer_clk); + timer_clk.disable(&timer_clk); + + /* + * These shall be turned on by default when we boot the system + * so make sure they are ON. (Adding CPU here is a bit too much.) + * These clocks will be claimed by drivers later. + */ + syscon_block_reset_disable(&semi_clk); + syscon_block_reset_disable(&emif_clk); + semi_clk.enable(&semi_clk); + emif_clk.enable(&emif_clk); + + return 0; +} +/* initialize clocking early to be available later in the boot */ +core_initcall(u300_clock_init); diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h new file mode 100644 index 000000000000..fc6d9ccfe7e3 --- /dev/null +++ b/arch/arm/mach-u300/clock.h @@ -0,0 +1,53 @@ +/* + * arch/arm/mach-u300/include/mach/clock.h + * + * Copyright (C) 2004 - 2005 Nokia corporation + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> + * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc + * Copyright (C) 2007-2009 ST-Ericsson AB + * Adopted to ST-Ericsson U300 platforms by + * Jonas Aaberg <jonas.aberg@stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __MACH_CLOCK_H +#define __MACH_CLOCK_H + +#include <linux/clk.h> + +struct clk { + struct list_head node; + struct module *owner; + struct device *dev; + const char *name; + struct clk *parent; + + spinlock_t lock; + unsigned long rate; + bool reset; + __u16 clk_val; + __s8 usecount; + __u32 res_reg; + __u16 res_mask; + + bool hw_ctrld; + + void (*recalc) (struct clk *); + int (*set_rate) (struct clk *, unsigned long); + unsigned long (*get_rate) (struct clk *); + unsigned long (*round_rate) (struct clk *, unsigned long); + void (*init) (struct clk *); + void (*enable) (struct clk *); + void (*disable) (struct clk *); +}; + +void u300_clock_primecells(void); +void u300_unclock_primecells(void); +void u300_enable_intcon_clock(void); +void u300_enable_timer_clock(void); + +#endif diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c new file mode 100644 index 000000000000..1f2ed21a0ab1 --- /dev/null +++ b/arch/arm/mach-u300/core.c @@ -0,0 +1,649 @@ +/* + * + * arch/arm/mach-u300/core.c + * + * + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Core platform support, IRQ handling and device definitions. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/interrupt.h> +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/mm.h> +#include <linux/termios.h> +#include <linux/amba/bus.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> + +#include <asm/types.h> +#include <asm/setup.h> +#include <asm/memory.h> +#include <asm/hardware/vic.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <mach/syscon.h> + +#include "clock.h" +#include "mmc.h" + +/* + * Static I/O mappings that are needed for booting the U300 platforms. The + * only things we need are the areas where we find the timer, syscon and + * intcon, since the remaining device drivers will map their own memory + * physical to virtual as the need arise. + */ +static struct map_desc u300_io_desc[] __initdata = { + { + .virtual = U300_SLOW_PER_VIRT_BASE, + .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE), + .length = SZ_64K, + .type = MT_DEVICE, + }, + { + .virtual = U300_AHB_PER_VIRT_BASE, + .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE), + .length = SZ_32K, + .type = MT_DEVICE, + }, + { + .virtual = U300_FAST_PER_VIRT_BASE, + .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE), + .length = SZ_32K, + .type = MT_DEVICE, + }, + { + .virtual = 0xffff2000, /* TCM memory */ + .pfn = __phys_to_pfn(0xffff2000), + .length = SZ_16K, + .type = MT_DEVICE, + }, + + /* + * This overlaps with the IRQ vectors etc at 0xffff0000, so these + * may have to be moved to 0x00000000 in order to use the ROM. + */ + /* + { + .virtual = U300_BOOTROM_VIRT_BASE, + .pfn = __phys_to_pfn(U300_BOOTROM_PHYS_BASE), + .length = SZ_64K, + .type = MT_ROM, + }, + */ +}; + +void __init u300_map_io(void) +{ + iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); +} + +/* + * Declaration of devices found on the U300 board and + * their respective memory locations. + */ +static struct amba_device uart0_device = { + .dev = { + .init_name = "uart0", /* Slow device at 0x3000 offset */ + .platform_data = NULL, + }, + .res = { + .start = U300_UART0_BASE, + .end = U300_UART0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = { IRQ_U300_UART0, NO_IRQ }, +}; + +/* The U335 have an additional UART1 on the APP CPU */ +#ifdef CONFIG_MACH_U300_BS335 +static struct amba_device uart1_device = { + .dev = { + .init_name = "uart1", /* Fast device at 0x7000 offset */ + .platform_data = NULL, + }, + .res = { + .start = U300_UART1_BASE, + .end = U300_UART1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = { IRQ_U300_UART1, NO_IRQ }, +}; +#endif + +static struct amba_device pl172_device = { + .dev = { + .init_name = "pl172", /* AHB device at 0x4000 offset */ + .platform_data = NULL, + }, + .res = { + .start = U300_EMIF_CFG_BASE, + .end = U300_EMIF_CFG_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + + +/* + * Everything within this next ifdef deals with external devices connected to + * the APP SPI bus. + */ +static struct amba_device pl022_device = { + .dev = { + .coherent_dma_mask = ~0, + .init_name = "pl022", /* Fast device at 0x6000 offset */ + }, + .res = { + .start = U300_SPI_BASE, + .end = U300_SPI_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_U300_SPI, NO_IRQ }, + /* + * This device has a DMA channel but the Linux driver does not use + * it currently. + */ +}; + +static struct amba_device mmcsd_device = { + .dev = { + .init_name = "mmci", /* Fast device at 0x1000 offset */ + .platform_data = NULL, /* Added later */ + }, + .res = { + .start = U300_MMCSD_BASE, + .end = U300_MMCSD_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }, + /* + * This device has a DMA channel but the Linux driver does not use + * it currently. + */ +}; + +/* + * The order of device declaration may be important, since some devices + * have dependencies on other devices being initialized first. + */ +static struct amba_device *amba_devs[] __initdata = { + &uart0_device, +#ifdef CONFIG_MACH_U300_BS335 + &uart1_device, +#endif + &pl022_device, + &pl172_device, + &mmcsd_device, +}; + +/* Here follows a list of all hw resources that the platform devices + * allocate. Note, clock dependencies are not included + */ + +static struct resource gpio_resources[] = { + { + .start = U300_GPIO_BASE, + .end = (U300_GPIO_BASE + SZ_4K - 1), + .flags = IORESOURCE_MEM, + }, + { + .name = "gpio0", + .start = IRQ_U300_GPIO_PORT0, + .end = IRQ_U300_GPIO_PORT0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "gpio1", + .start = IRQ_U300_GPIO_PORT1, + .end = IRQ_U300_GPIO_PORT1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "gpio2", + .start = IRQ_U300_GPIO_PORT2, + .end = IRQ_U300_GPIO_PORT2, + .flags = IORESOURCE_IRQ, + }, +#ifdef U300_COH901571_3 + { + .name = "gpio3", + .start = IRQ_U300_GPIO_PORT3, + .end = IRQ_U300_GPIO_PORT3, + .flags = IORESOURCE_IRQ, + }, + { + .name = "gpio4", + .start = IRQ_U300_GPIO_PORT4, + .end = IRQ_U300_GPIO_PORT4, + .flags = IORESOURCE_IRQ, + }, +#ifdef CONFIG_MACH_U300_BS335 + { + .name = "gpio5", + .start = IRQ_U300_GPIO_PORT5, + .end = IRQ_U300_GPIO_PORT5, + .flags = IORESOURCE_IRQ, + }, + { + .name = "gpio6", + .start = IRQ_U300_GPIO_PORT6, + .end = IRQ_U300_GPIO_PORT6, + .flags = IORESOURCE_IRQ, + }, +#endif /* CONFIG_MACH_U300_BS335 */ +#endif /* U300_COH901571_3 */ +}; + +static struct resource keypad_resources[] = { + { + .start = U300_KEYPAD_BASE, + .end = U300_KEYPAD_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "coh901461-press", + .start = IRQ_U300_KEYPAD_KEYBF, + .end = IRQ_U300_KEYPAD_KEYBF, + .flags = IORESOURCE_IRQ, + }, + { + .name = "coh901461-release", + .start = IRQ_U300_KEYPAD_KEYBR, + .end = IRQ_U300_KEYPAD_KEYBR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource rtc_resources[] = { + { + .start = U300_RTC_BASE, + .end = U300_RTC_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_U300_RTC, + .end = IRQ_U300_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +/* + * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2) + * but these are not yet used by the driver. + */ +static struct resource fsmc_resources[] = { + { + .start = U300_NAND_IF_PHYS_BASE, + .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource i2c0_resources[] = { + { + .start = U300_I2C0_BASE, + .end = U300_I2C0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_U300_I2C0, + .end = IRQ_U300_I2C0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c1_resources[] = { + { + .start = U300_I2C1_BASE, + .end = U300_I2C1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_U300_I2C1, + .end = IRQ_U300_I2C1, + .flags = IORESOURCE_IRQ, + }, + +}; + +static struct resource wdog_resources[] = { + { + .start = U300_WDOG_BASE, + .end = U300_WDOG_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_U300_WDOG, + .end = IRQ_U300_WDOG, + .flags = IORESOURCE_IRQ, + } +}; + +/* TODO: These should be protected by suitable #ifdef's */ +static struct resource ave_resources[] = { + { + .name = "AVE3e I/O Area", + .start = U300_VIDEOENC_BASE, + .end = U300_VIDEOENC_BASE + SZ_512K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "AVE3e IRQ0", + .start = IRQ_U300_VIDEO_ENC_0, + .end = IRQ_U300_VIDEO_ENC_0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "AVE3e IRQ1", + .start = IRQ_U300_VIDEO_ENC_1, + .end = IRQ_U300_VIDEO_ENC_1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "AVE3e Physmem Area", + .start = 0, /* 0 will be remapped to reserved memory */ + .end = SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + /* + * The AVE3e requires two regions of 256MB that it considers + * "invisible". The hardware will not be able to access these + * adresses, so they should never point to system RAM. + */ + { + .name = "AVE3e Reserved 0", + .start = 0xd0000000, + .end = 0xd0000000 + SZ_256M - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "AVE3e Reserved 1", + .start = 0xe0000000, + .end = 0xe0000000 + SZ_256M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device wdog_device = { + .name = "wdog", + .id = -1, + .num_resources = ARRAY_SIZE(wdog_resources), + .resource = wdog_resources, +}; + +static struct platform_device i2c0_device = { + .name = "stddci2c", + .id = 0, + .num_resources = ARRAY_SIZE(i2c0_resources), + .resource = i2c0_resources, +}; + +static struct platform_device i2c1_device = { + .name = "stddci2c", + .id = 1, + .num_resources = ARRAY_SIZE(i2c1_resources), + .resource = i2c1_resources, +}; + +static struct platform_device gpio_device = { + .name = "u300-gpio", + .id = -1, + .num_resources = ARRAY_SIZE(gpio_resources), + .resource = gpio_resources, +}; + +static struct platform_device keypad_device = { + .name = "keypad", + .id = -1, + .num_resources = ARRAY_SIZE(keypad_resources), + .resource = keypad_resources, +}; + +static struct platform_device rtc_device = { + .name = "rtc0", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +static struct platform_device fsmc_device = { + .name = "nandif", + .id = -1, + .num_resources = ARRAY_SIZE(fsmc_resources), + .resource = fsmc_resources, +}; + +static struct platform_device ave_device = { + .name = "video_enc", + .id = -1, + .num_resources = ARRAY_SIZE(ave_resources), + .resource = ave_resources, +}; + +/* + * Notice that AMBA devices are initialized before platform devices. + * + */ +static struct platform_device *platform_devs[] __initdata = { + &i2c0_device, + &i2c1_device, + &keypad_device, + &rtc_device, + &gpio_device, + &fsmc_device, + &wdog_device, + &ave_device +}; + + +/* + * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected + * together so some interrupts are connected to the first one and some + * to the second one. + */ +void __init u300_init_irq(void) +{ + u32 mask[2] = {0, 0}; + int i; + + for (i = 0; i < NR_IRQS; i++) + set_bit(i, (unsigned long *) &mask[0]); + u300_enable_intcon_clock(); + vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0]); + vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1]); +} + + +/* + * U300 platforms peripheral handling + */ +struct db_chip { + u16 chipid; + const char *name; +}; + +/* + * This is a list of the Digital Baseband chips used in the U300 platform. + */ +static struct db_chip db_chips[] __initdata = { + { + .chipid = 0xb800, + .name = "DB3000", + }, + { + .chipid = 0xc000, + .name = "DB3100", + }, + { + .chipid = 0xc800, + .name = "DB3150", + }, + { + .chipid = 0xd800, + .name = "DB3200", + }, + { + .chipid = 0xe000, + .name = "DB3250", + }, + { + .chipid = 0xe800, + .name = "DB3210", + }, + { + .chipid = 0xf000, + .name = "DB3350 P1x", + }, + { + .chipid = 0xf100, + .name = "DB3350 P2x", + }, + { + .chipid = 0x0000, /* List terminator */ + .name = NULL, + } +}; + +static void u300_init_check_chip(void) +{ + + u16 val; + struct db_chip *chip; + const char *chipname; + const char unknown[] = "UNKNOWN"; + + /* Read out and print chip ID */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR); + /* This is in funky bigendian order... */ + val = (val & 0xFFU) << 8 | (val >> 8); + chip = db_chips; + chipname = unknown; + + for ( ; chip->chipid; chip++) { + if (chip->chipid == (val & 0xFF00U)) { + chipname = chip->name; + break; + } + } + printk(KERN_INFO "Initializing U300 system on %s baseband chip " \ + "(chip ID 0x%04x)\n", chipname, val); + +#ifdef CONFIG_MACH_U300_BS26 + if ((val & 0xFF00U) != 0xc800) { + printk(KERN_ERR "Platform configured for BS25/BS26 " \ + "with DB3150 but %s detected, expect problems!", + chipname); + } +#endif +#ifdef CONFIG_MACH_U300_BS330 + if ((val & 0xFF00U) != 0xd800) { + printk(KERN_ERR "Platform configured for BS330 " \ + "with DB3200 but %s detected, expect problems!", + chipname); + } +#endif +#ifdef CONFIG_MACH_U300_BS335 + if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { + printk(KERN_ERR "Platform configured for BS365 " \ + " with DB3350 but %s detected, expect problems!", + chipname); + } +#endif +#ifdef CONFIG_MACH_U300_BS365 + if ((val & 0xFF00U) != 0xe800) { + printk(KERN_ERR "Platform configured for BS365 " \ + "with DB3210 but %s detected, expect problems!", + chipname); + } +#endif + + +} + +/* + * Some devices and their resources require reserved physical memory from + * the end of the available RAM. This function traverses the list of devices + * and assigns actual adresses to these. + */ +static void __init u300_assign_physmem(void) +{ + unsigned long curr_start = __pa(high_memory); + int i, j; + + for (i = 0; i < ARRAY_SIZE(platform_devs); i++) { + for (j = 0; j < platform_devs[i]->num_resources; j++) { + struct resource *const res = + &platform_devs[i]->resource[j]; + + if (IORESOURCE_MEM == res->flags && + 0 == res->start) { + res->start = curr_start; + res->end += curr_start; + curr_start += (res->end - res->start + 1); + + printk(KERN_INFO "core.c: Mapping RAM " \ + "%#x-%#x to device %s:%s\n", + res->start, res->end, + platform_devs[i]->name, res->name); + } + } + } +} + +void __init u300_init_devices(void) +{ + int i; + u16 val; + + /* Check what platform we run and print some status information */ + u300_init_check_chip(); + + /* Set system to run at PLL208, max performance, a known state. */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); + val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); + /* Wait for the PLL208 to lock if not locked in yet */ + while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) & + U300_SYSCON_CSR_PLL208_LOCK_IND)); + + /* Register the AMBA devices in the AMBA bus abstraction layer */ + u300_clock_primecells(); + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + u300_unclock_primecells(); + + u300_assign_physmem(); + + /* Register the platform devices */ + platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); + +#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED + /* + * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when + * both subsystems are requesting this mode. + * If we not share the Acc SDRAM, this is never the case. Therefore + * enable it here from the App side. + */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) | + U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR); +#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */ +} + +static int core_module_init(void) +{ + /* + * This needs to be initialized later: it needs the input framework + * to be initialized first. + */ + return mmc_init(&mmcsd_device); +} +module_init(core_module_init); diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c new file mode 100644 index 000000000000..2d5ae8ecb8c8 --- /dev/null +++ b/arch/arm/mach-u300/gpio.c @@ -0,0 +1,701 @@ +/* + * + * arch/arm/mach-u300/gpio.c + * + * + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * U300 GPIO module. + * This can driver either of the two basic GPIO cores + * available in the U300 platforms: + * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0) + * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) + * Notice that you also have inline macros in <asm-arch/gpio.h> + * Author: Linus Walleij <linus.walleij@stericsson.com> + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + * + */ +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> + +/* Need access to SYSCON registers for PADmuxing */ +#include <mach/syscon.h> + +#include "padmux.h" + +/* Reference to GPIO block clock */ +static struct clk *clk; + +/* Memory resource */ +static struct resource *memres; +static void __iomem *virtbase; + +struct u300_gpio_port { + const char *name; + int irq; + int number; +}; + + +static struct u300_gpio_port gpio_ports[] = { + { + .name = "gpio0", + .number = 0, + }, + { + .name = "gpio1", + .number = 1, + }, + { + .name = "gpio2", + .number = 2, + }, +#ifdef U300_COH901571_3 + { + .name = "gpio3", + .number = 3, + }, + { + .name = "gpio4", + .number = 4, + }, +#ifdef CONFIG_MACH_U300_BS335 + { + .name = "gpio5", + .number = 5, + }, + { + .name = "gpio6", + .number = 6, + }, +#endif +#endif + +}; + + +#ifdef U300_COH901571_3 + +/* Default input value */ +#define DEFAULT_OUTPUT_LOW 0 +#define DEFAULT_OUTPUT_HIGH 1 + +/* GPIO Pull-Up status */ +#define DISABLE_PULL_UP 0 +#define ENABLE_PULL_UP 1 + +#define GPIO_NOT_USED 0 +#define GPIO_IN 1 +#define GPIO_OUT 2 + +struct u300_gpio_configuration_data { + unsigned char pin_usage; + unsigned char default_output_value; + unsigned char pull_up; +}; + +/* Initial configuration */ +const struct u300_gpio_configuration_data +u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { +#ifdef CONFIG_MACH_U300_BS335 + /* Port 0, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} + }, + /* Port 1, pins 0-7 */ + { + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} + }, + /* Port 2, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} + }, + /* Port 3, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} + }, + /* Port 4, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} + }, + /* Port 5, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} + }, + /* Port 6, pind 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} + } +#endif + +#ifdef CONFIG_MACH_U300_BS365 + /* Port 0, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} + }, + /* Port 1, pins 0-7 */ + { + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} + }, + /* Port 2, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} + }, + /* Port 3, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} + }, + /* Port 4, pins 0-7 */ + { + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + /* These 4 pins doesn't exist on DB3210 */ + {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, + {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} + } +#endif +}; +#endif + + +/* No users == we can power down GPIO */ +static int gpio_users; + +struct gpio_struct { + int (*callback)(void *); + void *data; + int users; +}; + +static struct gpio_struct gpio_pin[U300_GPIO_MAX]; + +/* + * Let drivers register callback in order to get notified when there is + * an interrupt on the gpio pin + */ +int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data) +{ + if (gpio_pin[gpio].callback) + printk(KERN_WARNING "GPIO: %s: WARNING: callback already " \ + "registered for gpio pin#%d\n", __func__, gpio); + gpio_pin[gpio].callback = func; + gpio_pin[gpio].data = data; + + return 0; +} +EXPORT_SYMBOL(gpio_register_callback); + +int gpio_unregister_callback(unsigned gpio) +{ + if (!gpio_pin[gpio].callback) + printk(KERN_WARNING "GPIO: %s: WARNING: callback already " \ + "unregistered for gpio pin#%d\n", __func__, gpio); + gpio_pin[gpio].callback = NULL; + gpio_pin[gpio].data = NULL; + + return 0; +} +EXPORT_SYMBOL(gpio_unregister_callback); + +int gpio_request(unsigned gpio, const char *label) +{ + if (gpio_pin[gpio].users) + return -EINVAL; + else + gpio_pin[gpio].users++; + + gpio_users++; + + return 0; +} +EXPORT_SYMBOL(gpio_request); + +void gpio_free(unsigned gpio) +{ + gpio_users--; + gpio_pin[gpio].users--; + if (unlikely(gpio_pin[gpio].users < 0)) { + printk(KERN_WARNING "GPIO: Warning: gpio#%d release mismatch\n", + gpio); + gpio_pin[gpio].users = 0; + } + + return; +} +EXPORT_SYMBOL(gpio_free); + +/* This returns zero or nonzero */ +int gpio_get_value(unsigned gpio) +{ + return readl(virtbase + U300_GPIO_PXPDIR + + PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07)); +} +EXPORT_SYMBOL(gpio_get_value); + +/* + * We hope that the compiler will optimize away the unused branch + * in case "value" is a constant + */ +void gpio_set_value(unsigned gpio, int value) +{ + u32 val; + unsigned long flags; + + local_irq_save(flags); + if (value) { + /* set */ + val = readl(virtbase + U300_GPIO_PXPDOR + + PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) + & (1 << (gpio & 0x07)); + writel(val | (1 << (gpio & 0x07)), virtbase + + U300_GPIO_PXPDOR + + PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING); + } else { + /* clear */ + val = readl(virtbase + U300_GPIO_PXPDOR + + PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) + & (1 << (gpio & 0x07)); + writel(val & ~(1 << (gpio & 0x07)), virtbase + + U300_GPIO_PXPDOR + + PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_set_value); + +int gpio_direction_input(unsigned gpio) +{ + unsigned long flags; + u32 val; + + if (gpio > U300_GPIO_MAX) + return -EINVAL; + + local_irq_save(flags); + val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + /* Mask out this pin*/ + val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1)); + /* This is not needed since it sets the bits to zero.*/ + /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */ + writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + local_irq_restore(flags); + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned gpio, int value) +{ + unsigned long flags; + u32 val; + + if (gpio > U300_GPIO_MAX) + return -EINVAL; + + local_irq_save(flags); + val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + /* Mask out this pin */ + val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1)); + /* + * FIXME: configure for push/pull, open drain or open source per pin + * in setup. The current driver will only support push/pull. + */ + val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL + << ((gpio & 0x07) << 1)); + writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + gpio_set_value(gpio, value); + local_irq_restore(flags); + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + +/* + * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0). + */ +void enable_irq_on_gpio_pin(unsigned gpio, int edge) +{ + u32 val; + unsigned long flags; + local_irq_save(flags); + + val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + val |= (1 << (gpio & 0x07)); + writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + if (edge) + val |= (1 << (gpio & 0x07)); + else + val &= ~(1 << (gpio & 0x07)); + writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + local_irq_restore(flags); +} +EXPORT_SYMBOL(enable_irq_on_gpio_pin); + +void disable_irq_on_gpio_pin(unsigned gpio) +{ + u32 val; + unsigned long flags; + + local_irq_save(flags); + val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + val &= ~(1 << (gpio & 0x07)); + writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + local_irq_restore(flags); +} +EXPORT_SYMBOL(disable_irq_on_gpio_pin); + +/* Enable (value == 0) or disable (value == 1) internal pullup */ +void gpio_pullup(unsigned gpio, int value) +{ + u32 val; + unsigned long flags; + + local_irq_save(flags); + if (value) { + val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER + + PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING); + } else { + val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) * + U300_GPIO_PORTX_SPACING); + writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER + + PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_pullup); + +static irqreturn_t gpio_irq_handler(int irq, void *dev_id) +{ + struct u300_gpio_port *port = dev_id; + u32 val; + int pin; + + /* Read event register */ + val = readl(virtbase + U300_GPIO_PXIEV + port->number * + U300_GPIO_PORTX_SPACING); + /* Mask with enable register */ + val &= readl(virtbase + U300_GPIO_PXIEV + port->number * + U300_GPIO_PORTX_SPACING); + /* Mask relevant bits */ + val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK; + /* ACK IRQ (clear event) */ + writel(val, virtbase + U300_GPIO_PXIEV + port->number * + U300_GPIO_PORTX_SPACING); + /* Print message */ + while (val != 0) { + unsigned gpio; + + pin = __ffs(val); + /* mask off this pin */ + val &= ~(1 << pin); + gpio = (port->number << 3) + pin; + + if (gpio_pin[gpio].callback) + (void)gpio_pin[gpio].callback(gpio_pin[gpio].data); + else + printk(KERN_DEBUG "GPIO: Stray GPIO IRQ on line %d\n", + gpio); + } + return IRQ_HANDLED; +} + +static void gpio_set_initial_values(void) +{ +#ifdef U300_COH901571_3 + int i, j; + unsigned long flags; + u32 val; + + /* Write default values to all pins */ + for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { + val = 0; + for (j = 0; j < 8; j++) + val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j; + local_irq_save(flags); + writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING); + local_irq_restore(flags); + } + + /* + * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED' + * to output and 'GPIO_IN' to input for each port. And initalize + * default value on outputs. + */ + for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { + for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) { + local_irq_save(flags); + val = readl(virtbase + U300_GPIO_PXPCR + + i * U300_GPIO_PORTX_SPACING); + /* Mask out this pin */ + val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1)); + + if (u300_gpio_config[i][j].pin_usage != GPIO_IN) + val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1)); + writel(val, virtbase + U300_GPIO_PXPCR + + i * U300_GPIO_PORTX_SPACING); + local_irq_restore(flags); + } + } + + /* Enable or disable the internal pull-ups in the GPIO ASIC block */ + for (i = 0; i < U300_GPIO_MAX; i++) { + val = 0; + for (j = 0; j < 8; j++) + val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j; + local_irq_save(flags); + writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING); + local_irq_restore(flags); + } +#endif +} + +static int __devinit gpio_probe(struct platform_device *pdev) +{ + u32 val; + int err = 0; + int i; + int num_irqs; + + memset(gpio_pin, 0, sizeof(gpio_pin)); + + /* Get GPIO clock */ + clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + err = PTR_ERR(clk); + printk(KERN_ERR "GPIO: could not get GPIO clock\n"); + goto err_no_clk; + } + err = clk_enable(clk); + if (err) { + printk(KERN_ERR "GPIO: could not enable GPIO clock\n"); + goto err_no_clk_enable; + } + + memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!memres) + goto err_no_resource; + + if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller") + == NULL) { + err = -ENODEV; + goto err_no_ioregion; + } + + virtbase = ioremap(memres->start, memres->end - memres->start + 1); + if (!virtbase) { + err = -ENOMEM; + goto err_no_ioremap; + } + +#ifdef U300_COH901335 + printk(KERN_INFO "GPIO: Initializing GPIO Controller COH 901 335\n"); + /* Turn on the GPIO block */ + writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR); +#endif + +#ifdef U300_COH901571_3 + printk(KERN_INFO "GPIO: Initializing GPIO Controller COH 901 571/3\n"); + val = readl(virtbase + U300_GPIO_CR); + printk(KERN_INFO "GPIO: COH901571/3 block version: %d, " \ + "number of cores: %d\n", + ((val & 0x0000FE00) >> 9), + ((val & 0x000001FC) >> 2)); + writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR); +#endif + + /* Set up some padmuxing here */ +#ifdef CONFIG_MMC + pmx_set_mission_mode_mmc(); +#endif +#ifdef CONFIG_SPI_PL022 + pmx_set_mission_mode_spi(); +#endif + + gpio_set_initial_values(); + + for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) { + + gpio_ports[num_irqs].irq = + platform_get_irq_byname(pdev, + gpio_ports[num_irqs].name); + + err = request_irq(gpio_ports[num_irqs].irq, + gpio_irq_handler, IRQF_DISABLED, + gpio_ports[num_irqs].name, + &gpio_ports[num_irqs]); + if (err) { + printk(KERN_CRIT "GPIO: Cannot allocate IRQ for %s!\n", + gpio_ports[num_irqs].name); + goto err_no_irq; + } + /* Turns off PortX_irq_force */ + writel(0x0, virtbase + U300_GPIO_PXIFR + + num_irqs * U300_GPIO_PORTX_SPACING); + } + printk(KERN_INFO "GPIO: U300 gpio module loaded\n"); + + return 0; + + err_no_irq: + for (i = 0; i < num_irqs; i++) + free_irq(gpio_ports[i].irq, &gpio_ports[i]); + iounmap(virtbase); + err_no_ioremap: + release_mem_region(memres->start, memres->end - memres->start); + err_no_ioregion: + err_no_resource: + clk_disable(clk); + err_no_clk_enable: + clk_put(clk); + err_no_clk: + printk(KERN_INFO "GPIO: module ERROR:%d\n", err); + return err; +} + +static int __devexit gpio_remove(struct platform_device *pdev) +{ + int i; + + /* Turn off the GPIO block */ + writel(0x00000000U, virtbase + U300_GPIO_CR); + for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++) + free_irq(gpio_ports[i].irq, &gpio_ports[i]); + iounmap(virtbase); + release_mem_region(memres->start, memres->end - memres->start); + clk_disable(clk); + clk_put(clk); + return 0; +} + +static struct platform_driver gpio_driver = { + .driver = { + .name = "u300-gpio", + }, + .probe = gpio_probe, + .remove = __devexit_p(gpio_remove), +}; + + +static int __init u300_gpio_init(void) +{ + return platform_driver_register(&gpio_driver); +} + +static void __exit u300_gpio_exit(void) +{ + platform_driver_unregister(&gpio_driver); +} + +arch_initcall(u300_gpio_init); +module_exit(u300_gpio_exit); + +MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); + +#ifdef U300_COH901571_3 +MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver"); +#endif + +#ifdef U300_COH901335 +MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver"); +#endif + +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h new file mode 100644 index 000000000000..92e3cc872c66 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +int __clk_get(struct clk *clk); +void __clk_put(struct clk *clk); + +#endif diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S new file mode 100644 index 000000000000..f3a1cbbeeab3 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/debug-macro.S @@ -0,0 +1,22 @@ +/* + * + * arch-arm/mach-u300/include/mach/debug-macro.S + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Debugging macro include header. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#include <mach/hardware.h> + + .macro addruart,rx + /* If we move the adress using MMU, use this. */ + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address + ldrne \rx, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address + orr \rx, \rx, #0x00003000 + .endm + +#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S new file mode 100644 index 000000000000..20731ae39d38 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/entry-macro.S @@ -0,0 +1,40 @@ +/* + * + * arch-arm/mach-u300/include/mach/entry-macro.S + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Low-level IRQ helper macros for ST-Ericsson U300 + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#include <mach/hardware.h> +#include <asm/hardware/vic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON0_BASE + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status + mov \irqnr, #0 + teq \irqstat, #0 + bne 1002f +1001: ldr \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON1_BASE + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status + mov \irqnr, #32 + teq \irqstat, #0 + beq 1003f +1002: tst \irqstat, #1 + bne 1003f + add \irqnr, \irqnr, #1 + movs \irqstat, \irqstat, lsr #1 + bne 1002b +1003: /* EQ will be set if no irqs pending */ + .endm diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h new file mode 100644 index 000000000000..c8174128d7eb --- /dev/null +++ b/arch/arm/mach-u300/include/mach/gpio.h @@ -0,0 +1,290 @@ +/* + * + * arch/arm/mach-u300/include/mach/gpio.h + * + * + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * GPIO block resgister definitions and inline macros for + * U300 GPIO COH 901 335 or COH 901 571/3 + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ + +#ifndef __MACH_U300_GPIO_H +#define __MACH_U300_GPIO_H + +#include <linux/kernel.h> +#include <linux/io.h> +#include <mach/hardware.h> +#include <asm/irq.h> + +/* Switch type depending on platform/chip variant */ +#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) +#define U300_COH901335 +#endif +#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335) +#define U300_COH901571_3 +#endif + +/* Get base address for regs here */ +#include "u300-regs.h" +/* IRQ numbers */ +#include "irqs.h" + +/* + * This is the GPIO block definitions. GPIO (General Purpose I/O) can be + * used for anything, and often is. The event/enable etc figures are for + * the lowermost pin (pin 0 on each port), shift this left to match your + * pin if you're gonna use these values. + */ +#ifdef U300_COH901335 +#define U300_GPIO_PORTX_SPACING (0x1C) +/* Port X Pin Data Register 32bit, this is both input and output (R/W) */ +#define U300_GPIO_PXPDIR (0x00) +#define U300_GPIO_PXPDOR (0x00) +/* Port X Pin Config Register 32bit (R/W) */ +#define U300_GPIO_PXPCR (0x04) +#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) +#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) +#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) +#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) +#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) +#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) +#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) +/* Port X Interrupt Event Register 32bit (R/W) */ +#define U300_GPIO_PXIEV (0x08) +#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL) +#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL) +/* Port X Interrupt Enable Register 32bit (R/W) */ +#define U300_GPIO_PXIEN (0x0C) +#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL) +#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL) +/* Port X Interrupt Force Register 32bit (R/W) */ +#define U300_GPIO_PXIFR (0x10) +#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL) +#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL) +/* Port X Interrupt Config Register 32bit (R/W) */ +#define U300_GPIO_PXICR (0x14) +#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) +#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) +#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) +#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) +/* Port X Pull-up Enable Register 32bit (R/W) */ +#define U300_GPIO_PXPER (0x18) +#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) +#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) +/* Control Register 32bit (R/W) */ +#define U300_GPIO_CR (0x54) +#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE (0x00000001UL) +/* three ports of 8 bits each = GPIO pins 0..23 */ +#define U300_GPIO_NUM_PORTS 3 +#define U300_GPIO_PINS_PER_PORT 8 +#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1) +#endif + +#ifdef U300_COH901571_3 +/* + * Control Register 32bit (R/W) + * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores + * gives the number of GPIO pins. + * bit 8-2 (mask 0x000001FC) contains the core version ID. + */ +#define U300_GPIO_CR (0x00) +#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) +#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) +#define U300_GPIO_PORTX_SPACING (0x30) +/* Port X Pin Data INPUT Register 32bit (R/W) */ +#define U300_GPIO_PXPDIR (0x04) +/* Port X Pin Data OUTPUT Register 32bit (R/W) */ +#define U300_GPIO_PXPDOR (0x08) +/* Port X Pin Config Register 32bit (R/W) */ +#define U300_GPIO_PXPCR (0x0C) +#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) +#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) +#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) +#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) +#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) +#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) +#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) +/* Port X Pull-up Enable Register 32bit (R/W) */ +#define U300_GPIO_PXPER (0x10) +#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) +#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) +/* Port X Interrupt Event Register 32bit (R/W) */ +#define U300_GPIO_PXIEV (0x14) +#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL) +#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL) +/* Port X Interrupt Enable Register 32bit (R/W) */ +#define U300_GPIO_PXIEN (0x18) +#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL) +#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL) +/* Port X Interrupt Force Register 32bit (R/W) */ +#define U300_GPIO_PXIFR (0x1C) +#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL) +#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL) +/* Port X Interrupt Config Register 32bit (R/W) */ +#define U300_GPIO_PXICR (0x20) +#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) +#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) +#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) +#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) +#ifdef CONFIG_MACH_U300_BS335 +/* seven ports of 8 bits each = GPIO pins 0..55 */ +#define U300_GPIO_NUM_PORTS 7 +#else +/* five ports of 8 bits each = GPIO pins 0..39 */ +#define U300_GPIO_NUM_PORTS 5 +#endif +#define U300_GPIO_PINS_PER_PORT 8 +#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1) +#endif + +/* + * Individual pin assignments for the B26/S26. Notice that the + * actual usage of these pins depends on the PAD MUX settings, that + * is why the same number can potentially appear several times. + * In the reference design each pin is only used for one purpose. + * These were determined by inspecting the B26/S26 schematic: + * 2/1911-ROA 128 1603 + */ +#ifdef CONFIG_MACH_U300_BS2X +#define U300_GPIO_PIN_UART_RX 0 +#define U300_GPIO_PIN_UART_TX 1 +#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */ +#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */ +#define U300_GPIO_PIN_CAM_SLEEP 4 +#define U300_GPIO_PIN_CAM_REG_EN 5 +#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */ +#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */ +#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */ +#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */ +#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ +#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ +#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */ +#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */ +#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */ +#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */ +#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */ +#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */ +#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ +#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ +#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ +#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ +#endif + +/* + * Individual pin assignments for the B330/S330 and B365/S365. + * Notice that the actual usage of these pins depends on the + * PAD MUX settings, that is why the same number can potentially + * appear several times. In the reference design each pin is only + * used for one purpose. These were determined by inspecting the + * S365 schematic. + */ +#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \ + defined(CONFIG_MACH_U300_BS335) +#define U300_GPIO_PIN_UART_RX 0 +#define U300_GPIO_PIN_UART_TX 1 +#define U300_GPIO_PIN_UART_CTS 2 +#define U300_GPIO_PIN_UART_RTS 3 +#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */ +#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */ +#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */ +#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */ + +#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */ +#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */ +#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */ +#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ +#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ +#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */ +#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */ +#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */ +#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */ +#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */ +#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */ +#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ +#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ +#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ +#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */ +#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */ +#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */ +#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */ +#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */ +#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */ +#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */ +#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */ +#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */ +#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */ +#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */ +#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */ +#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */ +#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */ +#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */ + +#ifdef CONFIG_MACH_U300_BS335 + +#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */ +#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */ +#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */ +#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */ +#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */ +#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */ +#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */ +#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */ + +#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */ +#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */ +#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */ +#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */ +#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */ +#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */ +#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */ +#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */ +#endif + +#endif + +/* translates a pin number to a port number */ +#define PIN_TO_PORT(val) (val >> 3) + +/* These can be found in arch/arm/mach-u300/gpio.c */ +extern int gpio_request(unsigned gpio, const char *label); +extern void gpio_free(unsigned gpio); +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); +extern int gpio_register_callback(unsigned gpio, + int (*func)(void *arg), + void *); +extern int gpio_unregister_callback(unsigned gpio); +extern void enable_irq_on_gpio_pin(unsigned gpio, int edge); +extern void disable_irq_on_gpio_pin(unsigned gpio); +extern void gpio_pullup(unsigned gpio, int value); +extern int gpio_get_value(unsigned gpio); +extern void gpio_set_value(unsigned gpio, int value); + +/* wrappers to sleep-enable the previous two functions */ +static inline unsigned gpio_to_irq(unsigned gpio) +{ + return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0; +} + +static inline unsigned irq_to_gpio(unsigned irq) +{ + /* + * FIXME: This is no 1-1 mapping at all, it points to the + * whole block of 8 pins. + */ + return (irq - IRQ_U300_GPIO_PORT0) << 3; +} + +#endif diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h new file mode 100644 index 000000000000..b99d4ce0ac2b --- /dev/null +++ b/arch/arm/mach-u300/include/mach/hardware.h @@ -0,0 +1,5 @@ +/* + * arch/arm/mach-u300/include/mach/hardware.h + */ +#include <asm/sizes.h> +#include <mach/u300-regs.h> diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h new file mode 100644 index 000000000000..5d6b4c13b3a0 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/io.h @@ -0,0 +1,20 @@ +/* + * + * arch/arm/mach-u300/include/mach/io.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Dummy IO map for being able to use writew()/readw(), + * writel()/readw() and similar accessor functions. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#ifndef __MACH_IO_H +#define __MACH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h new file mode 100644 index 000000000000..a6867b12773e --- /dev/null +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -0,0 +1,114 @@ +/* + * + * arch/arm/mach-u300/include/mach/irqs.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * IRQ channel definitions for the U300 platforms. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define IRQ_U300_INTCON0_START 0 +#define IRQ_U300_INTCON1_START 32 +/* These are on INTCON0 - 30 lines */ +#define IRQ_U300_IRQ0_EXT 0 +#define IRQ_U300_IRQ1_EXT 1 +#define IRQ_U300_DMA 2 +#define IRQ_U300_VIDEO_ENC_0 3 +#define IRQ_U300_VIDEO_ENC_1 4 +#define IRQ_U300_AAIF_RX 5 +#define IRQ_U300_AAIF_TX 6 +#define IRQ_U300_AAIF_VGPIO 7 +#define IRQ_U300_AAIF_WAKEUP 8 +#define IRQ_U300_PCM_I2S0_FRAME 9 +#define IRQ_U300_PCM_I2S0_FIFO 10 +#define IRQ_U300_PCM_I2S1_FRAME 11 +#define IRQ_U300_PCM_I2S1_FIFO 12 +#define IRQ_U300_XGAM_GAMCON 13 +#define IRQ_U300_XGAM_CDI 14 +#define IRQ_U300_XGAM_CDICON 15 +#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) +/* MMIACC not used on the DB3210 or DB3350 chips */ +#define IRQ_U300_XGAM_MMIACC 16 +#endif +#define IRQ_U300_XGAM_PDI 17 +#define IRQ_U300_XGAM_PDICON 18 +#define IRQ_U300_XGAM_GAMEACC 19 +#define IRQ_U300_XGAM_MCIDCT 20 +#define IRQ_U300_APEX 21 +#define IRQ_U300_UART0 22 +#define IRQ_U300_SPI 23 +#define IRQ_U300_TIMER_APP_OS 24 +#define IRQ_U300_TIMER_APP_DD 25 +#define IRQ_U300_TIMER_APP_GP1 26 +#define IRQ_U300_TIMER_APP_GP2 27 +#define IRQ_U300_TIMER_OS 28 +#define IRQ_U300_TIMER_MS 29 +#define IRQ_U300_KEYPAD_KEYBF 30 +#define IRQ_U300_KEYPAD_KEYBR 31 +/* These are on INTCON1 - 32 lines */ +#define IRQ_U300_GPIO_PORT0 32 +#define IRQ_U300_GPIO_PORT1 33 +#define IRQ_U300_GPIO_PORT2 34 + +#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ + defined(CONFIG_MACH_U300_BS335) +/* These are for DB3150, DB3200 and DB3350 */ +#define IRQ_U300_WDOG 35 +#define IRQ_U300_EVHIST 36 +#define IRQ_U300_MSPRO 37 +#define IRQ_U300_MMCSD_MCIINTR0 38 +#define IRQ_U300_MMCSD_MCIINTR1 39 +#define IRQ_U300_I2C0 40 +#define IRQ_U300_I2C1 41 +#define IRQ_U300_RTC 42 +#define IRQ_U300_NFIF 43 +#define IRQ_U300_NFIF2 44 +#endif + +/* DB3150 and DB3200 have only 45 IRQs */ +#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) +#define U300_NR_IRQS 45 +#endif + +/* The DB3350-specific interrupt lines */ +#ifdef CONFIG_MACH_U300_BS335 +#define IRQ_U300_ISP_F0 45 +#define IRQ_U300_ISP_F1 46 +#define IRQ_U300_ISP_F2 47 +#define IRQ_U300_ISP_F3 48 +#define IRQ_U300_ISP_F4 49 +#define IRQ_U300_GPIO_PORT3 50 +#define IRQ_U300_SYSCON_PLL_LOCK 51 +#define IRQ_U300_UART1 52 +#define IRQ_U300_GPIO_PORT4 53 +#define IRQ_U300_GPIO_PORT5 54 +#define IRQ_U300_GPIO_PORT6 55 +#define U300_NR_IRQS 56 +#endif + +/* The DB3210-specific interrupt lines */ +#ifdef CONFIG_MACH_U300_BS365 +#define IRQ_U300_GPIO_PORT3 35 +#define IRQ_U300_GPIO_PORT4 36 +#define IRQ_U300_WDOG 37 +#define IRQ_U300_EVHIST 38 +#define IRQ_U300_MSPRO 39 +#define IRQ_U300_MMCSD_MCIINTR0 40 +#define IRQ_U300_MMCSD_MCIINTR1 41 +#define IRQ_U300_I2C0 42 +#define IRQ_U300_I2C1 43 +#define IRQ_U300_RTC 44 +#define IRQ_U300_NFIF 45 +#define IRQ_U300_NFIF2 46 +#define IRQ_U300_SYSCON_PLL_LOCK 47 +#define U300_NR_IRQS 48 +#endif + +#define NR_IRQS U300_NR_IRQS + +#endif diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h new file mode 100644 index 000000000000..bf134bcc129d --- /dev/null +++ b/arch/arm/mach-u300/include/mach/memory.h @@ -0,0 +1,42 @@ +/* + * + * arch/arm/mach-u300/include/mach/memory.h + * + * + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Memory virtual/physical mapping constants. + * Author: Linus Walleij <linus.walleij@stericsson.com> + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + */ + +#ifndef __MACH_MEMORY_H +#define __MACH_MEMORY_H + +#ifdef CONFIG_MACH_U300_DUAL_RAM + +#define PHYS_OFFSET UL(0x48000000) +#define BOOT_PARAMS_OFFSET (PHYS_OFFSET + 0x100) + +#else + +#ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX +#define PHYS_OFFSET (0x28000000 + \ + (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \ + (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) +#else +#define PHYS_OFFSET (0x28000000 + \ + (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \ + (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) +#endif +#define BOOT_PARAMS_OFFSET (0x28000000 + \ + (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \ + (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024 + 0x100) +#endif + +/* + * We enable a real big DMA buffer if need be. + */ +#define CONSISTENT_DMA_SIZE SZ_4M + +#endif diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h new file mode 100644 index 000000000000..77d9210a82e2 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/platform.h @@ -0,0 +1,19 @@ +/* + * + * arch/arm/mach-u300/include/mach/platform.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Basic platform init and mapping functions. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ + +#ifndef __ASSEMBLY__ + +void u300_map_io(void); +void u300_init_irq(void); +void u300_init_devices(void); +extern struct sys_timer u300_timer; + +#endif diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h new file mode 100644 index 000000000000..1c90d1b1ccb6 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/syscon.h @@ -0,0 +1,644 @@ +/* + * + * arch/arm/mach-u300/include/mach/syscon.h + * + * + * Copyright (C) 2008 ST-Ericsson AB + * + * Author: Rickard Andersson <rickard.andersson@stericsson.com> + */ + +#ifndef __MACH_SYSCON_H +#define __MACH_SYSCON_H + +/* + * All register defines for SYSCON registers that concerns individual + * block clocks and reset lines are registered here. This is because + * we don't want any other file to try to fool around with this stuff. + */ + +/* APP side SYSCON registers */ +/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */ +/* CLK Control Register 16bit (R/W) */ +#define U300_SYSCON_CCR (0x0000) +#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) +#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) +#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) +/* CLK Status Register 16bit (R/W) */ +#define U300_SYSCON_CSR (0x0004) +#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) +#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) +/* Reset lines for SLOW devices 16bit (R/W) */ +#define U300_SYSCON_RSR (0x0014) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) +#endif +#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) +#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) +#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) +#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) +#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) +#define U300_SYSCON_RSR_EH_RESET_EN (0x0008) +#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) +#define U300_SYSCON_RSR_UART_RESET_EN (0x0002) +#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) +/* Reset lines for FAST devices 16bit (R/W) */ +#define U300_SYSCON_RFR (0x0018) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) +#endif +#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) +#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) +#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) +#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) +#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) +#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) +#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) +/* Reset lines for the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_RRR (0x001c) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) +#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) +#endif +#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) +#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) +#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) +#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) +#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) +#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) +#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) +#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) +#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) +#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) +#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) +/* Clock enable for SLOW peripherals 16bit (R/W) */ +#define U300_SYSCON_CESR (0x0020) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) +#endif +#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) +#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) +#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) +#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) +#define U300_SYSCON_CESR_EH_CLK_EN (0x0008) +#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) +#define U300_SYSCON_CESR_UART_CLK_EN (0x0002) +#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) +/* Clock enable for FAST peripherals 16bit (R/W) */ +#define U300_SYSCON_CEFR (0x0024) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) +#endif +#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) +#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) +#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) +#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) +#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) +#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) +#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) +#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) +#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) +/* Clock enable for the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_CERR (0x0028) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) +#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) +#endif +#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) +#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) +#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) +#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) +#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) +#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) +#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) +#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) +#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) +#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) +#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) +#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) +/* Single block clock enable 16bit (-/W) */ +#define U300_SYSCON_SBCER (0x002c) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) +#endif +#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) +#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) +#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) +#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) +#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) +#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) +#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) +#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) +#endif +#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) +#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) +#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) +#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) +#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) +#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) +#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) +#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) +#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) +#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) +#endif +#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) +#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) +#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) +#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) +#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) +#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) +#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) +#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) +#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) +#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) +#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) +#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) +/* Single block clock disable 16bit (-/W) */ +#define U300_SYSCON_SBCDR (0x0030) +/* Same values as above for SBCER */ +/* Clock force SLOW peripherals 16bit (R/W) */ +#define U300_SYSCON_CFSR (0x003c) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) +#endif +#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) +#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) +#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) +#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) +#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) +#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) +#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) +#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) +/* Clock force FAST peripherals 16bit (R/W) */ +#define U300_SYSCON_CFFR (0x40) +/* Values not defined. Define if you want to use them. */ +/* Clock force the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_CFRR (0x44) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) +#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) +#endif +#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) +#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) +#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) +#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) +#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) +#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) +#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) +#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) +#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) +#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) +#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) +#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) +/* PLL208 Frequency Control 16bit (R/W) */ +#define U300_SYSCON_PFCR (0x48) +#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) +/* Power Management Control 16bit (R/W) */ +#define U300_SYSCON_PMCR (0x50) +#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) +#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) +/* + * All other clocking registers moved to clock.c! + */ +/* Reset Out 16bit (R/W) */ +#define U300_SYSCON_RCR (0x6c) +#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) +/* EMIF Slew Rate Control 16bit (R/W) */ +#define U300_SYSCON_SRCLR (0x70) +#define U300_SYSCON_SRCLR_MASK (0x03FF) +#define U300_SYSCON_SRCLR_VALUE (0x03FF) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) +/* EMIF Clock Control Register 16bit (R/W) */ +#define U300_SYSCON_ECCR (0x0078) +#define U300_SYSCON_ECCR_MASK (0x000F) +#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) +#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) +#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) +#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) +/* PAD MUX Control register 1 (LOW) 16bit (R/W) */ +#define U300_SYSCON_PMC1LR (0x007C) +#define U300_SYSCON_PMC1LR_MASK (0xFFFF) +#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000) +#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000) +#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000) +#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000) +#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000) +#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000) +#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000) +#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000) +#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00) +#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000) +#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400) +#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800) +#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00) +#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300) +#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000) +#define U300_SYSCON_PMC1LR_ETM_APP (0x0100) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003) +#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002) +#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003) +/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ +#define U300_SYSCON_PMC1HR (0x007E) +#define U300_SYSCON_PMC1HR_MASK (0xFFFF) +#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000) +#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000) +#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000) +#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030) +#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010) +#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020) +#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030) +#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004) +#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008) +#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003) +#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001) +#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003) +/* Step one for killing the applications system 16bit (-/W) */ +#define U300_SYSCON_KA1R (0x0080) +#define U300_SYSCON_KA1R_MASK (0xFFFF) +#define U300_SYSCON_KA1R_VALUE (0xFFFF) +/* Step two for killing the application system 16bit (-/W) */ +#define U300_SYSCON_KA2R (0x0084) +#define U300_SYSCON_KA2R_MASK (0xFFFF) +#define U300_SYSCON_KA2R_VALUE (0xFFFF) +/* MMC/MSPRO frequency divider register 0 16bit (R/W) */ +#define U300_SYSCON_MMF0R (0x90) +#define U300_SYSCON_MMF0R_MASK (0x00FF) +#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) +#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) +/* MMC/MSPRO frequency divider register 1 16bit (R/W) */ +#define U300_SYSCON_MMF1R (0x94) +#define U300_SYSCON_MMF1R_MASK (0x00FF) +#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) +#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) +/* AAIF control register 16 bit (R/W) */ +#define U300_SYSCON_AAIFCR (0x98) +#define U300_SYSCON_AAIFCR_MASK (0x0003) +#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003) +#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000) +#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001) +#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002) +#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003) +/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ +#define U300_SYSCON_MMCR (0x9C) +#define U300_SYSCON_MMCR_MASK (0x0003) +#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) +#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) + +/* TODO: More SYSCON registers missing */ +#define U300_SYSCON_PMC3R (0x10c) +#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000) +#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000) +#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000) +#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000) +/* TODO: Missing other configs, I just added the SPI stuff */ + +/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ +#define U300_SYSCON_S0CCR (0x120) +#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) +#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ +#define U300_SYSCON_S1CCR (0x124) +#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) +#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ +#define U300_SYSCON_S2CCR (0x128) +#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) +#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) +#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */ +#define U300_SYSCON_MCR (0x12c) +#define U300_SYSCON_MCR_FIELD_MASK (0x00FF) +#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0) +#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000) +#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040) +#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0) +#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030) +#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000) +#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010) +#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020) +#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030) +#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C) +#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000) +#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004) +#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008) +#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C) +#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002) +#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001) +/* Clock activity observability register 0 */ +#define U300_SYSCON_C0OAR (0x140) +#define U300_SYSCON_C0OAR_MASK (0xFFFF) +#define U300_SYSCON_C0OAR_VALUE (0xFFFF) +#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) +#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) +#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) +#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) +#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) +#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) +#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) +#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) +#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) +#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) +#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) +#define U300_SYSCON_C0OAR_APEX_CLK (0x0010) +#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) +#define U300_SYSCON_C0OAR_AHB_CLK (0x0004) +#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) +#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) +/* Clock activity observability register 1 */ +#define U300_SYSCON_C1OAR (0x144) +#define U300_SYSCON_C1OAR_MASK (0x3FFE) +#define U300_SYSCON_C1OAR_VALUE (0x3FFE) +#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) +#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) +#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) +#define U300_SYSCON_C1OAR_MMC_CLK (0x0400) +#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) +#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) +#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) +#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) +#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) +#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) +#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) +#define U300_SYSCON_C1OAR_PPM_CLK (0x0004) +#define U300_SYSCON_C1OAR_DMA_CLK (0x0002) +/* Clock activity observability register 2 */ +#define U300_SYSCON_C2OAR (0x148) +#define U300_SYSCON_C2OAR_MASK (0x0FFF) +#define U300_SYSCON_C2OAR_VALUE (0x0FFF) +#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) +#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) +#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) +#define U300_SYSCON_C2OAR_VC_CLK (0x0100) +#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) +#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) +#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) +#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) +#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) +#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) +#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) +#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) + +/* Chip ID register 16bit (R/-) */ +#define U300_SYSCON_CIDR (0x400) +/* Video IRQ clear 16bit (R/W) */ +#define U300_SYSCON_VICR (0x404) +#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002) +#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001) +/* SMCR */ +#define U300_SYSCON_SMCR (0x4d0) +#define U300_SYSCON_SMCR_FIELD_MASK (0x000e) +#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008) +#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004) +#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002) +/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */ +#define U300_SYSCON_CSDR (0x4f0) +#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001) +/* PRINT_CONTROL Print Control 16bit (R/-) */ +#define U300_SYSCON_PCR (0x4f8) +#define U300_SYSCON_PCR_SERV_IND (0x0001) +/* BOOT_CONTROL 16bit (R/-) */ +#define U300_SYSCON_BCR (0x4fc) +#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400) +#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200) +#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC) +#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003) + + +/* CPU clock defines */ +/** + * CPU high frequency in MHz + */ +#define SYSCON_CPU_CLOCK_HIGH 208 +/** + * CPU medium frequency in MHz + */ +#define SYSCON_CPU_CLOCK_MEDIUM 104 +/** + * CPU low frequency in MHz + */ +#define SYSCON_CPU_CLOCK_LOW 13 + +/* EMIF clock defines */ +/** + * EMIF high frequency in MHz + */ +#define SYSCON_EMIF_CLOCK_HIGH 104 +/** + * EMIF medium frequency in MHz + */ +#define SYSCON_EMIF_CLOCK_MEDIUM 104 +/** + * EMIF low frequency in MHz + */ +#define SYSCON_EMIF_CLOCK_LOW 13 + +/* AHB clock defines */ +/** + * AHB high frequency in MHz + */ +#define SYSCON_AHB_CLOCK_HIGH 52 +/** + * AHB medium frequency in MHz + */ +#define SYSCON_AHB_CLOCK_MEDIUM 52 +/** + * AHB low frequency in MHz + */ +#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */ + +enum syscon_busmaster { + SYSCON_BM_DMAC, + SYSCON_BM_XGAM, + SYSCON_BM_VIDEO_ENC +}; + +/* + * Note that this array must match the order of the array "clk_reg" + * in syscon.c + */ +enum syscon_clk { + SYSCON_CLKCONTROL_SLOW_BRIDGE, + SYSCON_CLKCONTROL_UART, + SYSCON_CLKCONTROL_BTR, + SYSCON_CLKCONTROL_EH, + SYSCON_CLKCONTROL_GPIO, + SYSCON_CLKCONTROL_KEYPAD, + SYSCON_CLKCONTROL_APP_TIMER, + SYSCON_CLKCONTROL_ACC_TIMER, + SYSCON_CLKCONTROL_FAST_BRIDGE, + SYSCON_CLKCONTROL_I2C0, + SYSCON_CLKCONTROL_I2C1, + SYSCON_CLKCONTROL_I2S0, + SYSCON_CLKCONTROL_I2S1, + SYSCON_CLKCONTROL_MMC, + SYSCON_CLKCONTROL_SPI, + SYSCON_CLKCONTROL_I2S0_CORE, + SYSCON_CLKCONTROL_I2S1_CORE, + SYSCON_CLKCONTROL_AAIF, + SYSCON_CLKCONTROL_AHB, + SYSCON_CLKCONTROL_APEX, + SYSCON_CLKCONTROL_CPU, + SYSCON_CLKCONTROL_DMA, + SYSCON_CLKCONTROL_EMIF, + SYSCON_CLKCONTROL_NAND_IF, + SYSCON_CLKCONTROL_VIDEO_ENC, + SYSCON_CLKCONTROL_XGAM, + SYSCON_CLKCONTROL_SEMI, + SYSCON_CLKCONTROL_AHB_SUBSYS, + SYSCON_CLKCONTROL_MSPRO +}; + +enum syscon_sysclk_mode { + SYSCON_SYSCLK_DISABLED, + SYSCON_SYSCLK_M_CLK, + SYSCON_SYSCLK_ACC_FSM, + SYSCON_SYSCLK_PLL60_48, + SYSCON_SYSCLK_PLL60_60, + SYSCON_SYSCLK_ACC_PLL208, + SYSCON_SYSCLK_APP_PLL13, + SYSCON_SYSCLK_APP_FSM, + SYSCON_SYSCLK_RTC, + SYSCON_SYSCLK_APP_PLL208 +}; + +enum syscon_sysclk_req { + SYSCON_SYSCLKREQ_DISABLED, + SYSCON_SYSCLKREQ_ACTIVE_LOW +}; + +enum syscon_clk_mode { + SYSCON_CLKMODE_OFF, + SYSCON_CLKMODE_DEFAULT, + SYSCON_CLKMODE_LOW, + SYSCON_CLKMODE_MEDIUM, + SYSCON_CLKMODE_HIGH, + SYSCON_CLKMODE_PERMANENT, + SYSCON_CLKMODE_ON, +}; + +enum syscon_call_mode { + SYSCON_CLKCALL_NOWAIT, + SYSCON_CLKCALL_WAIT, +}; + +int syscon_dc_on(bool keep_power_on); +int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster, + bool active); +bool syscon_get_busmaster_active_state(void); +int syscon_set_sleep_mask(enum syscon_clk, + bool sleep_ctrl); +int syscon_config_sysclk(u32 sysclk, + enum syscon_sysclk_mode sysclkmode, + bool inverse, + u32 divisor, + enum syscon_sysclk_req sysclkreq); +bool syscon_can_turn_off_semi_clock(void); + +/* This function is restricted to core.c */ +int syscon_request_normal_power(bool req); + +/* This function is restricted to be used by platform_speed.c */ +int syscon_speed_request(enum syscon_call_mode wait_mode, + enum syscon_clk_mode req_clk_mode); +#endif /* __MACH_SYSCON_H */ diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h new file mode 100644 index 000000000000..8daf13634ce0 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/system.h @@ -0,0 +1,42 @@ +/* + * + * arch/arm/mach-u300/include/mach/system.h + * + * + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * System shutdown and reset functions. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#include <mach/hardware.h> +#include <asm/io.h> +#include <asm/hardware/vic.h> +#include <asm/irq.h> + +/* Forward declare this function from the watchdog */ +void coh901327_watchdog_reset(void); + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static void arch_reset(char mode, const char *cmd) +{ + switch (mode) { + case 's': + case 'h': + printk(KERN_CRIT "RESET: shutting down/rebooting system\n"); + /* Disable interrupts */ + local_irq_disable(); +#ifdef CONFIG_COH901327_WATCHDOG + coh901327_watchdog_reset(); +#endif + break; + default: + /* Do nothing */ + break; + } + /* Wait for system do die/reset. */ + while (1); +} diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h new file mode 100644 index 000000000000..f233b72633f6 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/timex.h @@ -0,0 +1,17 @@ +/* + * + * arch/arm/mach-u300/include/mach/timex.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Platform tick rate definition. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#ifndef __MACH_TIMEX_H +#define __MACH_TIMEX_H + +/* This is for the APP OS GP1 (General Purpose 1) timer */ +#define CLOCK_TICK_RATE 1000000 + +#endif diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h new file mode 100644 index 000000000000..88333dfb19fc --- /dev/null +++ b/arch/arm/mach-u300/include/mach/u300-regs.h @@ -0,0 +1,187 @@ +/* + * + * arch/arm/mach-u300/include/mach/u300-regs.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Basic register address definitions in physical memory and + * some block defintions for core devices like the timer. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ + +#ifndef __MACH_U300_REGS_H +#define __MACH_U300_REGS_H + +/* + * These are the large blocks of memory allocated for I/O. + * the defines are used for setting up the I/O memory mapping. + */ + +/* NAND Flash CS0 */ +#define U300_NAND_CS0_PHYS_BASE 0x80000000 +#define U300_NAND_CS0_VIRT_BASE 0xff040000 + +/* NFIF */ +#define U300_NAND_IF_PHYS_BASE 0x9f800000 +#define U300_NAND_IF_VIRT_BASE 0xff030000 + +/* AHB Peripherals */ +#define U300_AHB_PER_PHYS_BASE 0xa0000000 +#define U300_AHB_PER_VIRT_BASE 0xff010000 + +/* FAST Peripherals */ +#define U300_FAST_PER_PHYS_BASE 0xc0000000 +#define U300_FAST_PER_VIRT_BASE 0xff020000 + +/* SLOW Peripherals */ +#define U300_SLOW_PER_PHYS_BASE 0xc0010000 +#define U300_SLOW_PER_VIRT_BASE 0xff000000 + +/* Boot ROM */ +#define U300_BOOTROM_PHYS_BASE 0xffff0000 +#define U300_BOOTROM_VIRT_BASE 0xffff0000 + +/* SEMI config base */ +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SEMI_CONFIG_BASE 0x2FFE0000 +#else +#define U300_SEMI_CONFIG_BASE 0x30000000 +#endif + +/* + * All the following peripherals are specified at their PHYSICAL address, + * so if you need to access them (in the kernel), you MUST use the macros + * defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST() + * etc. + */ + +/* + * AHB peripherals + */ + +/* AHB Peripherals Bridge Controller */ +#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000) + +/* Vectored Interrupt Controller 0, servicing 32 interrupts */ +#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) +#define U300_INTCON0_VBASE (U300_AHB_PER_VIRT_BASE+0x1000) + +/* Vectored Interrupt Controller 1, servicing 32 interrupts */ +#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) +#define U300_INTCON1_VBASE (U300_AHB_PER_VIRT_BASE+0x2000) + +/* Memory Stick Pro (MSPRO) controller */ +#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) + +/* EMIF Configuration Area */ +#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000) + + +/* + * FAST peripherals + */ + +/* FAST bridge control */ +#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000) + +/* MMC/SD controller */ +#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000) + +/* PCM I2S0 controller */ +#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000) + +/* PCM I2S1 controller */ +#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000) + +/* I2C0 controller */ +#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000) + +/* I2C1 controller */ +#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000) + +/* SPI controller */ +#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) + +#ifdef CONFIG_MACH_U300_BS335 +/* Fast UART1 on U335 only */ +#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) +#endif + +/* + * SLOW peripherals + */ + +/* SLOW bridge control */ +#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE) + +/* SYSCON */ +#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) +#define U300_SYSCON_VBASE (U300_SLOW_PER_VIRT_BASE+0x1000) + +/* Watchdog */ +#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) + +/* UART0 */ +#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000) + +/* APP side special timer */ +#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) +#define U300_TIMER_APP_VBASE (U300_SLOW_PER_VIRT_BASE+0x4000) + +/* Keypad */ +#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) + +/* GPIO */ +#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000) + +/* RTC */ +#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) + +/* Bus tracer */ +#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000) + +/* Event handler (hardware queue) */ +#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000) + +/* Genric Timer */ +#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000) + +/* PPM */ +#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000) + + +/* + * REST peripherals + */ + +/* ISP (image signal processor) is only available in U335 */ +#ifdef CONFIG_MACH_U300_BS335 +#define U300_ISP_BASE (0xA0008000) +#endif + +/* DMA Controller base */ +#define U300_DMAC_BASE (0xC0020000) + +/* MSL Base */ +#define U300_MSL_BASE (0xc0022000) + +/* APEX Base */ +#define U300_APEX_BASE (0xc0030000) + +/* Video Encoder Base */ +#ifdef CONFIG_MACH_U300_BS335 +#define U300_VIDEOENC_BASE (0xc0080000) +#else +#define U300_VIDEOENC_BASE (0xc0040000) +#endif + +/* XGAM Base */ +#define U300_XGAM_BASE (0xd0000000) + +/* + * Virtual accessor macros for static devices + */ + + +#endif diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h new file mode 100644 index 000000000000..29acb718acf7 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/uncompress.h @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-u300/include/mach/uncompress.h + * + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000) +#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C) +#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030) +#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018) + +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + while (AMBA_UART_FR & (1 << 5)) + barrier(); + + AMBA_UART_DR = c; +} + +static inline void flush(void) +{ + while (AMBA_UART_FR & (1 << 3)) + barrier(); +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h new file mode 100644 index 000000000000..b00c51a66fbe --- /dev/null +++ b/arch/arm/mach-u300/include/mach/vmalloc.h @@ -0,0 +1,12 @@ +/* + * + * arch/arm/mach-u300/include/mach/vmalloc.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Virtual memory allocations + * End must be above the I/O registers and on an even 2MiB boundary. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#define VMALLOC_END 0xfe800000 diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c new file mode 100644 index 000000000000..3138d3955c9e --- /dev/null +++ b/arch/arm/mach-u300/mmc.c @@ -0,0 +1,216 @@ +/* + * + * arch/arm/mach-u300/mmc.c + * + * + * Copyright (C) 2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * + * Author: Linus Walleij <linus.walleij@stericsson.com> + * Author: Johan Lundin <johan.lundin@stericsson.com> + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + */ +#include <linux/device.h> +#include <linux/amba/bus.h> +#include <linux/mmc/host.h> +#include <linux/input.h> +#include <linux/workqueue.h> +#include <linux/delay.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/machine.h> +#include <linux/gpio.h> + +#include <asm/mach/mmc.h> +#include "mmc.h" + +struct mmci_card_event { + struct input_dev *mmc_input; + int mmc_inserted; + struct work_struct workq; + struct mmc_platform_data mmc0_plat_data; +}; + +static unsigned int mmc_status(struct device *dev) +{ + struct mmci_card_event *mmci_card = container_of( + dev->platform_data, + struct mmci_card_event, mmc0_plat_data); + + return mmci_card->mmc_inserted; +} + +/* + * Here follows a large chunk of code which will only be enabled if you + * have both the AB3100 chip mounted and the MMC subsystem activated. + */ + +static u32 mmc_translate_vdd(struct device *dev, unsigned int voltage) +{ + int v; + + /* + * MMC Spec: + * bit 7: 1.70 - 1.95V + * bit 8 - 14: 2.0 - 2.6V + * bit 15 - 23: 2.7 - 3.6V + * + * ab3100 voltages: + * 000 - 2.85V + * 001 - 2.75V + * 010 - 1.8V + * 011 - 1.5V + */ + switch (voltage) { + case 8: + v = 3; + break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + v = 1; + break; + case 16: + v = 1; + break; + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + v = 0; + break; + default: + v = 0; + break; + } + + /* PL180 voltage register bits */ + return v << 2; +} + + + +static int mmci_callback(void *data) +{ + struct mmci_card_event *mmci_card = data; + + disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD); + schedule_work(&mmci_card->workq); + + return 0; +} + + +static ssize_t gpio_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mmci_card_event *mmci_card = container_of( + dev->platform_data, + struct mmci_card_event, mmc0_plat_data); + + + return sprintf(buf, "%d\n", !mmci_card->mmc_inserted); +} + +static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL); + +static void _mmci_callback(struct work_struct *ws) +{ + + struct mmci_card_event *mmci_card = container_of( + ws, + struct mmci_card_event, workq); + + mdelay(20); + + mmci_card->mmc_inserted = !!gpio_get_value(U300_GPIO_PIN_MMC_CD); + + input_report_switch(mmci_card->mmc_input, KEY_INSERT, + !mmci_card->mmc_inserted); + input_sync(mmci_card->mmc_input); + + pr_debug("MMC/SD card was %s\n", + mmci_card->mmc_inserted ? "removed" : "inserted"); + + enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, !mmci_card->mmc_inserted); +} + +int __devinit mmc_init(struct amba_device *adev) +{ + struct mmci_card_event *mmci_card; + struct device *mmcsd_device = &adev->dev; + int ret = 0; + + mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL); + if (!mmci_card) + return -ENOMEM; + + /* Nominally 2.85V on our platform */ + mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29; + mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd; + mmci_card->mmc0_plat_data.status = mmc_status; + + mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data; + + INIT_WORK(&mmci_card->workq, _mmci_callback); + + ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection"); + if (ret) { + printk(KERN_CRIT "Could not allocate MMC card detection " \ + "GPIO pin\n"); + goto out; + } + + ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD); + if (ret) { + printk(KERN_CRIT "Invalid GPIO pin requested\n"); + goto out; + } + + ret = sysfs_create_file(&mmcsd_device->kobj, + &dev_attr_mmc_inserted.attr); + if (ret) + goto out; + + mmci_card->mmc_input = input_allocate_device(); + if (!mmci_card->mmc_input) { + printk(KERN_CRIT "Could not allocate MMC input device\n"); + return -ENOMEM; + } + + mmci_card->mmc_input->name = "MMC insert notification"; + mmci_card->mmc_input->id.bustype = BUS_HOST; + mmci_card->mmc_input->id.vendor = 0; + mmci_card->mmc_input->id.product = 0; + mmci_card->mmc_input->id.version = 0x0100; + mmci_card->mmc_input->dev.parent = mmcsd_device; + input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT); + + /* + * Since this must always be compiled into the kernel, this input + * is never unregistered or free:ed. + */ + ret = input_register_device(mmci_card->mmc_input); + if (ret) { + input_free_device(mmci_card->mmc_input); + goto out; + } + + input_set_drvdata(mmci_card->mmc_input, mmci_card); + + ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback, + mmci_card); + + schedule_work(&mmci_card->workq); + + printk(KERN_INFO "Registered MMC insert/remove notification\n"); +out: + return ret; +} diff --git a/arch/arm/mach-u300/mmc.h b/arch/arm/mach-u300/mmc.h new file mode 100644 index 000000000000..92b85125abb3 --- /dev/null +++ b/arch/arm/mach-u300/mmc.h @@ -0,0 +1,18 @@ +/* + * + * arch/arm/mach-u300/mmc.h + * + * + * Copyright (C) 2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + */ +#ifndef MMC_H +#define MMC_H + +#include <linux/amba/bus.h> + +int __devinit mmc_init(struct amba_device *adev); + +#endif diff --git a/arch/arm/mach-u300/padmux.c b/arch/arm/mach-u300/padmux.c new file mode 100644 index 000000000000..f3664564f086 --- /dev/null +++ b/arch/arm/mach-u300/padmux.c @@ -0,0 +1,58 @@ +/* + * + * arch/arm/mach-u300/padmux.c + * + * + * Copyright (C) 2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * U300 PADMUX functions + * Author: Linus Walleij <linus.walleij@stericsson.com> + * + */ +#include <linux/io.h> +#include <linux/err.h> +#include <mach/u300-regs.h> +#include <mach/syscon.h> + +#include "padmux.h" + +/* Set the PAD MUX to route the MMC reader correctly to GPIO0. */ +void pmx_set_mission_mode_mmc(void) +{ + u16 val; + + val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1LR); + val &= ~U300_SYSCON_PMC1LR_MMCSD_MASK; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1LR); + val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR); + val &= ~U300_SYSCON_PMC1HR_APP_GPIO_1_MASK; + val |= U300_SYSCON_PMC1HR_APP_GPIO_1_MMC; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR); +} + +void pmx_set_mission_mode_spi(void) +{ + u16 val; + + /* Set up padmuxing so the SPI port and its chipselects are active */ + val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR); + /* + * Activate the SPI port (disable the use of these pins for generic + * GPIO, DSP, AAIF + */ + val &= ~U300_SYSCON_PMC1HR_APP_SPI_2_MASK; + val |= U300_SYSCON_PMC1HR_APP_SPI_2_SPI; + /* + * Use GPIO pin SPI CS1 for CS1 actually (it can be used for other + * things also) + */ + val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK; + val |= U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI; + /* + * Use GPIO pin SPI CS2 for CS2 actually (it can be used for other + * things also) + */ + val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK; + val |= U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI; + writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR); +} diff --git a/arch/arm/mach-u300/padmux.h b/arch/arm/mach-u300/padmux.h new file mode 100644 index 000000000000..8c2099ac5046 --- /dev/null +++ b/arch/arm/mach-u300/padmux.h @@ -0,0 +1,19 @@ +/* + * + * arch/arm/mach-u300/padmux.h + * + * + * Copyright (C) 2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * U300 PADMUX API + * Author: Linus Walleij <linus.walleij@stericsson.com> + * + */ + +#ifndef __MACH_U300_PADMUX_H +#define __MACH_U300_PADMUX_H + +void pmx_set_mission_mode_mmc(void); +void pmx_set_mission_mode_spi(void); + +#endif diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c new file mode 100644 index 000000000000..57b5351b1816 --- /dev/null +++ b/arch/arm/mach-u300/timer.c @@ -0,0 +1,422 @@ +/* + * + * arch/arm/mach-u300/timer.c + * + * + * Copyright (C) 2007-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Timer COH 901 328, runs the OS timer interrupt. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#include <linux/interrupt.h> +#include <linux/time.h> +#include <linux/timex.h> +#include <linux/clockchips.h> +#include <linux/clocksource.h> +#include <linux/types.h> +#include <linux/io.h> + +#include <mach/hardware.h> + +/* Generic stuff */ +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/mach/irq.h> + +#include "clock.h" + +/* + * APP side special timer registers + * This timer contains four timers which can fire an interrupt each. + * OS (operating system) timer @ 32768 Hz + * DD (device driver) timer @ 1 kHz + * GP1 (general purpose 1) timer @ 1MHz + * GP2 (general purpose 2) timer @ 1MHz + */ + +/* Reset OS Timer 32bit (-/W) */ +#define U300_TIMER_APP_ROST (0x0000) +#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000) +/* Enable OS Timer 32bit (-/W) */ +#define U300_TIMER_APP_EOST (0x0004) +#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000) +/* Disable OS Timer 32bit (-/W) */ +#define U300_TIMER_APP_DOST (0x0008) +#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000) +/* OS Timer Mode Register 32bit (-/W) */ +#define U300_TIMER_APP_SOSTM (0x000c) +#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000) +#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001) +/* OS Timer Status Register 32bit (R/-) */ +#define U300_TIMER_APP_OSTS (0x0010) +#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F) +#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001) +#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002) +#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010) +#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020) +#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000) +#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020) +#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040) +#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080) +/* OS Timer Current Count Register 32bit (R/-) */ +#define U300_TIMER_APP_OSTCC (0x0014) +/* OS Timer Terminal Count Register 32bit (R/W) */ +#define U300_TIMER_APP_OSTTC (0x0018) +/* OS Timer Interrupt Enable Register 32bit (-/W) */ +#define U300_TIMER_APP_OSTIE (0x001c) +#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000) +#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001) +/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */ +#define U300_TIMER_APP_OSTIA (0x0020) +#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080) + +/* Reset DD Timer 32bit (-/W) */ +#define U300_TIMER_APP_RDDT (0x0040) +#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000) +/* Enable DD Timer 32bit (-/W) */ +#define U300_TIMER_APP_EDDT (0x0044) +#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000) +/* Disable DD Timer 32bit (-/W) */ +#define U300_TIMER_APP_DDDT (0x0048) +#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000) +/* DD Timer Mode Register 32bit (-/W) */ +#define U300_TIMER_APP_SDDTM (0x004c) +#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000) +#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001) +/* DD Timer Status Register 32bit (R/-) */ +#define U300_TIMER_APP_DDTS (0x0050) +#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F) +#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001) +#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002) +#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010) +#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020) +#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000) +#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020) +#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040) +#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080) +/* DD Timer Current Count Register 32bit (R/-) */ +#define U300_TIMER_APP_DDTCC (0x0054) +/* DD Timer Terminal Count Register 32bit (R/W) */ +#define U300_TIMER_APP_DDTTC (0x0058) +/* DD Timer Interrupt Enable Register 32bit (-/W) */ +#define U300_TIMER_APP_DDTIE (0x005c) +#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000) +#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001) +/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */ +#define U300_TIMER_APP_DDTIA (0x0060) +#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080) + +/* Reset GP1 Timer 32bit (-/W) */ +#define U300_TIMER_APP_RGPT1 (0x0080) +#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000) +/* Enable GP1 Timer 32bit (-/W) */ +#define U300_TIMER_APP_EGPT1 (0x0084) +#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000) +/* Disable GP1 Timer 32bit (-/W) */ +#define U300_TIMER_APP_DGPT1 (0x0088) +#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000) +/* GP1 Timer Mode Register 32bit (-/W) */ +#define U300_TIMER_APP_SGPT1M (0x008c) +#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000) +#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001) +/* GP1 Timer Status Register 32bit (R/-) */ +#define U300_TIMER_APP_GPT1S (0x0090) +#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F) +#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001) +#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002) +#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010) +#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020) +#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000) +#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020) +#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040) +#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080) +/* GP1 Timer Current Count Register 32bit (R/-) */ +#define U300_TIMER_APP_GPT1CC (0x0094) +/* GP1 Timer Terminal Count Register 32bit (R/W) */ +#define U300_TIMER_APP_GPT1TC (0x0098) +/* GP1 Timer Interrupt Enable Register 32bit (-/W) */ +#define U300_TIMER_APP_GPT1IE (0x009c) +#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000) +#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001) +/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */ +#define U300_TIMER_APP_GPT1IA (0x00a0) +#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080) + +/* Reset GP2 Timer 32bit (-/W) */ +#define U300_TIMER_APP_RGPT2 (0x00c0) +#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000) +/* Enable GP2 Timer 32bit (-/W) */ +#define U300_TIMER_APP_EGPT2 (0x00c4) +#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000) +/* Disable GP2 Timer 32bit (-/W) */ +#define U300_TIMER_APP_DGPT2 (0x00c8) +#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000) +/* GP2 Timer Mode Register 32bit (-/W) */ +#define U300_TIMER_APP_SGPT2M (0x00cc) +#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000) +#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001) +/* GP2 Timer Status Register 32bit (R/-) */ +#define U300_TIMER_APP_GPT2S (0x00d0) +#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F) +#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001) +#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002) +#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010) +#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020) +#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000) +#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020) +#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040) +#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080) +/* GP2 Timer Current Count Register 32bit (R/-) */ +#define U300_TIMER_APP_GPT2CC (0x00d4) +/* GP2 Timer Terminal Count Register 32bit (R/W) */ +#define U300_TIMER_APP_GPT2TC (0x00d8) +/* GP2 Timer Interrupt Enable Register 32bit (-/W) */ +#define U300_TIMER_APP_GPT2IE (0x00dc) +#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000) +#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001) +/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */ +#define U300_TIMER_APP_GPT2IA (0x00e0) +#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080) + +/* Clock request control register - all four timers */ +#define U300_TIMER_APP_CRC (0x100) +#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001) + +#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) +#define US_PER_TICK ((1000000 + (HZ/2)) / HZ) + +/* + * The u300_set_mode() function is always called first, if we + * have oneshot timer active, the oneshot scheduling function + * u300_set_next_event() is called immediately after. + */ +static void u300_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* Disable interrupts on GPT1 */ + writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + /* Disable GP1 while we're reprogramming it. */ + writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + /* + * Set the periodic mode to a certain number of ticks per + * jiffy. + */ + writel(TICKS_PER_JIFFY, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + /* + * Set continuous mode, so the timer keeps triggering + * interrupts. + */ + writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, + U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + /* Enable timer interrupts */ + writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + /* Then enable the OS timer again */ + writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* Just break; here? */ + /* + * The actual event will be programmed by the next event hook, + * so we just set a dummy value somewhere at the end of the + * universe here. + */ + /* Disable interrupts on GPT1 */ + writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + /* Disable GP1 while we're reprogramming it. */ + writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + /* + * Expire far in the future, u300_set_next_event() will be + * called soon... + */ + writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + /* We run one shot per tick here! */ + writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, + U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + /* Enable interrupts for this timer */ + writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + /* Enable timer */ + writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + /* Disable interrupts on GP1 */ + writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + /* Disable GP1 */ + writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + break; + case CLOCK_EVT_MODE_RESUME: + /* Ignore this call */ + break; + } +} + +/* + * The app timer in one shot mode obviously has to be reprogrammed + * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace + * the interrupt disable + timer disable commands with a reset command, + * it will fail miserably. Apparently (and I found this the hard way) + * the timer is very sensitive to the instruction order, though you don't + * get that impression from the data sheet. + */ +static int u300_set_next_event(unsigned long cycles, + struct clock_event_device *evt) + +{ + /* Disable interrupts on GPT1 */ + writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + /* Disable GP1 while we're reprogramming it. */ + writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + /* Reset the General Purpose timer 1. */ + writel(U300_TIMER_APP_RGPT1_TIMER_RESET, + U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); + /* IRQ in n * cycles */ + writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + /* + * We run one shot per tick here! (This is necessary to reconfigure, + * the timer will tilt if you don't!) + */ + writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, + U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + /* Enable timer interrupts */ + writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + /* Then enable the OS timer again */ + writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + return 0; +} + + +/* Use general purpose timer 1 as clock event */ +static struct clock_event_device clockevent_u300_1mhz = { + .name = "GPT1", + .rating = 300, /* Reasonably fast and accurate clock event */ + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + /* 22 calculated using the algorithm in arch/mips/kernel/time.c */ + .shift = 22, + .set_next_event = u300_set_next_event, + .set_mode = u300_set_mode, +}; + +/* Clock event timer interrupt handler */ +static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_u300_1mhz; + /* ACK/Clear timer IRQ for the APP GPT1 Timer */ + writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA); + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static struct irqaction u300_timer_irq = { + .name = "U300 Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = u300_timer_interrupt, +}; + +/* Use general purpose timer 2 as clock source */ +static cycle_t u300_get_cycles(void) +{ + return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); +} + +static struct clocksource clocksource_u300_1mhz = { + .name = "GPT2", + .rating = 300, /* Reasonably fast and accurate clock source */ + .read = u300_get_cycles, + .mask = CLOCKSOURCE_MASK(32), /* 32 bits */ + /* 22 calculated using the algorithm in arch/mips/kernel/time.c */ + .shift = 22, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + + +/* + * This sets up the system timers, clock source and clock event. + */ +static void __init u300_timer_init(void) +{ + u300_enable_timer_clock(); + /* + * Disable the "OS" and "DD" timers - these are designed for Symbian! + * Example usage in cnh1601578 cpu subsystem pd_timer_app.c + */ + writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC); + writel(U300_TIMER_APP_ROST_TIMER_RESET, + U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST); + writel(U300_TIMER_APP_DOST_TIMER_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST); + writel(U300_TIMER_APP_RDDT_TIMER_RESET, + U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT); + writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT); + + /* Reset the General Purpose timer 1. */ + writel(U300_TIMER_APP_RGPT1_TIMER_RESET, + U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); + + /* Set up the IRQ handler */ + setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq); + + /* Reset the General Purpose timer 2 */ + writel(U300_TIMER_APP_RGPT2_TIMER_RESET, + U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2); + /* Set this timer to run around forever */ + writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC); + /* Set continuous mode so it wraps around */ + writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, + U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M); + /* Disable timer interrupts */ + writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE); + /* Then enable the GP2 timer to use as a free running us counter */ + writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, + U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); + + /* This is a pure microsecond clock source */ + clocksource_u300_1mhz.mult = + clocksource_khz2mult(1000, clocksource_u300_1mhz.shift); + if (clocksource_register(&clocksource_u300_1mhz)) + printk(KERN_ERR "timer: failed to initialize clock " + "source %s\n", clocksource_u300_1mhz.name); + + clockevent_u300_1mhz.mult = + div_sc(1000000, NSEC_PER_SEC, clockevent_u300_1mhz.shift); + /* 32bit counter, so 32bits delta is max */ + clockevent_u300_1mhz.max_delta_ns = + clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz); + /* This timer is slow enough to set for 1 cycle == 1 MHz */ + clockevent_u300_1mhz.min_delta_ns = + clockevent_delta2ns(1, &clockevent_u300_1mhz); + clockevent_u300_1mhz.cpumask = cpumask_of(0); + clockevents_register_device(&clockevent_u300_1mhz); + /* + * TODO: init and register the rest of the timers too, they can be + * used by hrtimers! + */ +} + +/* + * Very simple system timer that only register the clock event and + * clock source. + */ +struct sys_timer u300_timer = { + .init = u300_timer_init, +}; diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c new file mode 100644 index 000000000000..d2a0b8847a18 --- /dev/null +++ b/arch/arm/mach-u300/u300.c @@ -0,0 +1,55 @@ +/* + * + * arch/arm/mach-u300/u300.c + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Platform machine definition. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <mach/hardware.h> +#include <mach/platform.h> +#include <mach/memory.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +static void __init u300_init_machine(void) +{ + u300_init_devices(); +} + +#ifdef CONFIG_MACH_U300_BS2X +#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board" +#endif + +#ifdef CONFIG_MACH_U300_BS330 +#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board" +#endif + +#ifdef CONFIG_MACH_U300_BS335 +#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board" +#endif + +#ifdef CONFIG_MACH_U300_BS365 +#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board" +#endif + +MACHINE_START(U300, MACH_U300_STRING) + /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ + .phys_io = U300_AHB_PER_PHYS_BASE, + .io_pg_offst = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = BOOT_PARAMS_OFFSET, + .map_io = u300_map_io, + .init_irq = u300_init_irq, + .timer = &u300_timer, + .init_machine = u300_init_machine, +MACHINE_END diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e6344ece00ce..39fca4e416e2 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -839,6 +839,20 @@ void __init reserve_node_zero(pg_data_t *pgdat) reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, BOOTMEM_EXCLUSIVE); + /* + * U300 - This platform family can share physical memory + * between two ARM cpus, one running Linux and the other + * running another OS. + */ + if (machine_is_u300()) { +#ifdef CONFIG_MACH_U300_SINGLE_RAM +#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \ + CONFIG_MACH_U300_2MB_ALIGNMENT_FIX + res_size = 0x00100000; +#endif +#endif + } + #ifdef CONFIG_SA1111 /* * Because of the SA1111 DMA bug, we want to preserve our diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index f0cc599facb7..087e239704df 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -10,6 +10,7 @@ * * This is the "shell" of the ARMv6 processor support. */ +#include <linux/init.h> #include <linux/linkage.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> @@ -132,7 +133,7 @@ cpu_v6_name: .asciz "ARMv6-compatible processor" .align - .section ".text.init", #alloc, #execinstr + __INIT /* * __v6_setup diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index d1ebec42521d..c221e26ac1d3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -9,6 +9,7 @@ * * This is the "shell" of the ARMv7 processor support. */ +#include <linux/init.h> #include <linux/linkage.h> #include <asm/assembler.h> #include <asm/asm-offsets.h> @@ -153,7 +154,7 @@ cpu_v7_name: .ascii "ARMv7 Processor" .align - .section ".text.init", #alloc, #execinstr + __INIT /* * __v7_setup diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S index 20f84bbaa9bb..73d7d89b04c4 100644 --- a/arch/arm/mm/tlb-v6.S +++ b/arch/arm/mm/tlb-v6.S @@ -10,6 +10,7 @@ * ARM architecture version 6 TLB handling functions. * These assume a split I/D TLB. */ +#include <linux/init.h> #include <linux/linkage.h> #include <asm/asm-offsets.h> #include <asm/page.h> @@ -87,7 +88,7 @@ ENTRY(v6wbi_flush_kern_tlb_range) mcr p15, 0, r2, c7, c5, 4 @ prefetch flush mov pc, lr - .section ".text.init", #alloc, #execinstr + __INIT .type v6wbi_tlb_fns, #object ENTRY(v6wbi_tlb_fns) diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S index 24ba5109f2e7..b637e7380ab7 100644 --- a/arch/arm/mm/tlb-v7.S +++ b/arch/arm/mm/tlb-v7.S @@ -11,6 +11,7 @@ * ARM architecture version 6 TLB handling functions. * These assume a split I/D TLB. */ +#include <linux/init.h> #include <linux/linkage.h> #include <asm/asm-offsets.h> #include <asm/page.h> @@ -80,7 +81,7 @@ ENTRY(v7wbi_flush_kern_tlb_range) mov pc, lr ENDPROC(v7wbi_flush_kern_tlb_range) - .section ".text.init", #alloc, #execinstr + __INIT .type v7wbi_tlb_fns, #object ENTRY(v7wbi_tlb_fns) diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 2e0614552ac8..29efc279287a 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -239,6 +239,13 @@ void recalculate_root_clocks(void) } } +/** + * clk_init_one - initialize any fields in the struct clk before clk init + * @clk: struct clk * to initialize + * + * Initialize any struct clk fields needed before normal clk initialization + * can run. No return value. + */ void clk_init_one(struct clk *clk) { INIT_LIST_HEAD(&clk->children); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 21cc0142b97a..7fc8c045ad5d 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -760,19 +760,12 @@ void omap_free_dma(int lch) { unsigned long flags; - spin_lock_irqsave(&dma_chan_lock, flags); if (dma_chan[lch].dev_id == -1) { pr_err("omap_dma: trying to free unallocated DMA channel %d\n", lch); - spin_unlock_irqrestore(&dma_chan_lock, flags); return; } - dma_chan[lch].dev_id = -1; - dma_chan[lch].next_lch = -1; - dma_chan[lch].callback = NULL; - spin_unlock_irqrestore(&dma_chan_lock, flags); - if (cpu_class_is_omap1()) { /* Disable all DMA interrupts for the channel. */ dma_write(0, CICR(lch)); @@ -798,6 +791,12 @@ void omap_free_dma(int lch) dma_write(0, CCR(lch)); omap_clear_dma(lch); } + + spin_lock_irqsave(&dma_chan_lock, flags); + dma_chan[lch].dev_id = -1; + dma_chan[lch].next_lch = -1; + dma_chan[lch].callback = NULL; + spin_unlock_irqrestore(&dma_chan_lock, flags); } EXPORT_SYMBOL(omap_free_dma); diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index bfd47570cc91..55bb99631292 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -238,7 +238,7 @@ static struct omap_dm_timer omap3_dm_timers[] = { { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 }, { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, - { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 }, + { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ }, }; static const char *omap3_dm_source_names[] __initdata = { @@ -321,11 +321,9 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer) l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ /* - * Enable wake-up only for GPT1 on OMAP2 CPUs. - * FIXME: All timers should have wake-up enabled and clear - * PRCM status. + * Enable wake-up on OMAP2 CPUs. */ - if (cpu_class_is_omap2() && (timer == &dm_timers[0])) + if (cpu_class_is_omap2()) l |= 1 << 2; omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l); @@ -511,7 +509,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop); #ifdef CONFIG_ARCH_OMAP1 -void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { int n = (timer - dm_timers) << 1; u32 l; @@ -519,23 +517,31 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); l |= source << n; omap_writel(l, MOD_CONF_CTRL_1); + + return 0; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); #else -void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { + int ret = -EINVAL; + if (source < 0 || source >= 3) - return; + return -EINVAL; clk_disable(timer->fclk); - clk_set_parent(timer->fclk, dm_source_clocks[source]); + ret = clk_set_parent(timer->fclk, dm_source_clocks[source]); clk_enable(timer->fclk); - /* When the functional clock disappears, too quick writes seem to - * cause an abort. */ + /* + * When the functional clock disappears, too quick writes seem + * to cause an abort. XXX Is this still necessary? + */ __delay(150000); + + return ret; } EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d3fa41e3d8c5..17d7afe42b83 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -758,8 +758,12 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) /* Workaround for clearing DSP GPIO interrupts to allow retention */ #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) + reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; if (cpu_is_omap24xx() || cpu_is_omap34xx()) - __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); + __raw_writel(gpio_mask, reg); + + /* Flush posted write for the irq status to avoid spurious interrupts */ + __raw_readl(reg); #endif } @@ -921,13 +925,10 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) case METHOD_MPUIO: case METHOD_GPIO_1610: spin_lock_irqsave(&bank->lock, flags); - if (enable) { + if (enable) bank->suspend_wakeup |= (1 << gpio); - enable_irq_wake(bank->irq); - } else { - disable_irq_wake(bank->irq); + else bank->suspend_wakeup &= ~(1 << gpio); - } spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif @@ -940,13 +941,10 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) return -EINVAL; } spin_lock_irqsave(&bank->lock, flags); - if (enable) { + if (enable) bank->suspend_wakeup |= (1 << gpio); - enable_irq_wake(bank->irq); - } else { - disable_irq_wake(bank->irq); + else bank->suspend_wakeup &= ~(1 << gpio); - } spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif diff --git a/arch/arm/plat-omap/include/mach/dmtimer.h b/arch/arm/plat-omap/include/mach/dmtimer.h index 6dc703138210..20f1054c0a80 100644 --- a/arch/arm/plat-omap/include/mach/dmtimer.h +++ b/arch/arm/plat-omap/include/mach/dmtimer.h @@ -64,7 +64,7 @@ void omap_dm_timer_trigger(struct omap_dm_timer *timer); void omap_dm_timer_start(struct omap_dm_timer *timer); void omap_dm_timer_stop(struct omap_dm_timer *timer); -void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); diff --git a/arch/arm/plat-omap/include/mach/eac.h b/arch/arm/plat-omap/include/mach/eac.h deleted file mode 100644 index 9e62cf030270..000000000000 --- a/arch/arm/plat-omap/include/mach/eac.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach2/eac.h - * - * Defines for Enhanced Audio Controller - * - * Contact: Jarkko Nikula <jarkko.nikula@nokia.com> - * - * Copyright (C) 2006 Nokia Corporation - * Copyright (C) 2004 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H -#define __ASM_ARM_ARCH_OMAP2_EAC_H - -#include <mach/io.h> -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <sound/core.h> - -/* master codec clock source */ -#define EAC_MCLK_EXT_MASK 0x100 -enum eac_mclk_src { - EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */ - EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK, - EAC_MCLK_EXT_12288000, - EAC_MCLK_EXT_2x11289600, - EAC_MCLK_EXT_2x12288000, -}; - -/* codec port interface mode */ -enum eac_codec_mode { - EAC_CODEC_PCM, - EAC_CODEC_AC97, - EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */ - EAC_CODEC_I2S_SLAVE, -}; - -/* configuration structure for I2S mode */ -struct eac_i2s_conf { - /* if enabled, then first data slot (left channel) is signaled as - * positive level of frame sync EAC.AC_FS */ - unsigned polarity_changed_mode:1; - /* if enabled, then serial data starts one clock cycle after the - * of EAC.AC_FS for first audio slot */ - unsigned sync_delay_enable:1; -}; - -/* configuration structure for EAC codec port */ -struct eac_codec { - enum eac_mclk_src mclk_src; - - enum eac_codec_mode codec_mode; - union { - struct eac_i2s_conf i2s; - } codec_conf; - - int default_rate; /* audio sampling rate */ - - int (* set_power)(void *private_data, int dac, int adc); - int (* register_controls)(void *private_data, - struct snd_card *card); - const char *short_name; - - void *private_data; -}; - -/* structure for passing platform dependent data to the EAC driver */ -struct eac_platform_data { - int (* init)(struct device *eac_dev); - void (* cleanup)(struct device *eac_dev); - /* these callbacks are used to configure & control external MCLK - * source. NULL if not used */ - int (* enable_ext_clocks)(struct device *eac_dev); - void (* disable_ext_clocks)(struct device *eac_dev); -}; - -extern void omap_init_eac(struct eac_platform_data *pdata); - -extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec); -extern void eac_unregister_codec(struct device *eac_dev); - -extern int eac_set_mode(struct device *eac_dev, int play, int rec); - -#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */ diff --git a/arch/arm/plat-omap/include/mach/gpioexpander.h b/arch/arm/plat-omap/include/mach/gpioexpander.h deleted file mode 100644 index 90444a0d6b1a..000000000000 --- a/arch/arm/plat-omap/include/mach/gpioexpander.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/gpioexpander.h - * - * - * Copyright (C) 2004 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H -#define __ASM_ARCH_OMAP_GPIOEXPANDER_H - -/* Function Prototypes for GPIO Expander functions */ - -#ifdef CONFIG_GPIOEXPANDER_OMAP -int read_gpio_expa(u8 *, int); -int write_gpio_expa(u8 , int); -#else -static inline int read_gpio_expa(u8 *val, int addr) -{ - return 0; -} -static inline int write_gpio_expa(u8 val, int addr) -{ - return 0; -} -#endif - -#endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */ diff --git a/arch/arm/plat-omap/include/mach/irda.h b/arch/arm/plat-omap/include/mach/irda.h index 8372a00d8e0b..40f60339d1c6 100644 --- a/arch/arm/plat-omap/include/mach/irda.h +++ b/arch/arm/plat-omap/include/mach/irda.h @@ -21,10 +21,6 @@ struct omap_irda_config { int transceiver_cap; int (*transceiver_mode)(struct device *dev, int mode); int (*select_irda)(struct device *dev, int state); - /* Very specific to the needs of some platforms (h3,h4) - * having calls which can sleep in irda_set_speed. - */ - struct delayed_work gpio_expa; int rx_channel; int tx_channel; unsigned long dest_start; diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h index 4435bd434e17..81d5b36534b3 100644 --- a/arch/arm/plat-omap/include/mach/mmc.h +++ b/arch/arm/plat-omap/include/mach/mmc.h @@ -79,7 +79,6 @@ struct omap_mmc_platform_data { /* use the internal clock */ unsigned internal_clock:1; - s16 power_pin; int switch_pin; /* gpio (card detect) */ int gpio_wp; /* gpio (write protect) */ diff --git a/arch/arm/plat-omap/include/mach/timer-gp.h b/arch/arm/plat-omap/include/mach/timer-gp.h new file mode 100644 index 000000000000..c88d346b59d9 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/timer-gp.h @@ -0,0 +1,17 @@ +/* + * OMAP2/3 GPTIMER support.headers + * + * Copyright (C) 2009 Nokia Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H + +int __init omap2_gp_clockevent_set_gptimer(u8 id); + +#endif + diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index 8f2c4c7fbd48..0264bfb0ca4f 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile @@ -7,3 +7,5 @@ obj-y := dma.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PXA3xx) += mfp.o obj-$(CONFIG_ARCH_MMP) += mfp.o + +obj-$(CONFIG_HAVE_PWM) += pwm.o diff --git a/arch/arm/mach-pxa/include/mach/i2c.h b/arch/arm/plat-pxa/include/plat/i2c.h index 1a9f65e6ec0f..1a9f65e6ec0f 100644 --- a/arch/arm/mach-pxa/include/mach/i2c.h +++ b/arch/arm/plat-pxa/include/plat/i2c.h diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c index fcdd374437a8..a9eabdcfa163 100644 --- a/arch/arm/mach-pxa/pwm.c +++ b/arch/arm/plat-pxa/pwm.c @@ -21,6 +21,19 @@ #include <asm/div64.h> +#define HAS_SECONDARY_PWM 0x10 +#define PWM_ID_BASE(d) ((d) & 0xf) + +static const struct platform_device_id pwm_id_table[] = { + /* PWM has_secondary_pwm? */ + { "pxa25x-pwm", 0 }, + { "pxa27x-pwm", 0 | HAS_SECONDARY_PWM }, + { "pxa168-pwm", 1 }, + { "pxa910-pwm", 1 }, + { }, +}; +MODULE_DEVICE_TABLE(platform, pwm_id_table); + /* PWM registers and bits definitions */ #define PWMCR (0x00) #define PWMDCR (0x04) @@ -31,7 +44,8 @@ struct pwm_device { struct list_head node; - struct platform_device *pdev; + struct pwm_device *secondary; + struct platform_device *pdev; const char *label; struct clk *clk; @@ -159,17 +173,17 @@ static inline void __add_pwm(struct pwm_device *pwm) mutex_unlock(&pwm_lock); } -static struct pwm_device *pwm_probe(struct platform_device *pdev, - unsigned int pwm_id, struct pwm_device *parent_pwm) +static int __devinit pwm_probe(struct platform_device *pdev) { - struct pwm_device *pwm; + struct platform_device_id *id = platform_get_device_id(pdev); + struct pwm_device *pwm, *secondary = NULL; struct resource *r; int ret = 0; pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); if (pwm == NULL) { dev_err(&pdev->dev, "failed to allocate memory\n"); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } pwm->clk = clk_get(&pdev->dev, NULL); @@ -180,16 +194,9 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev, pwm->clk_enabled = 0; pwm->use_count = 0; - pwm->pwm_id = pwm_id; + pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id; pwm->pdev = pdev; - if (parent_pwm != NULL) { - /* registers for the second PWM has offset of 0x10 */ - pwm->mmio_base = parent_pwm->mmio_base + 0x10; - __add_pwm(pwm); - return pwm; - } - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (r == NULL) { dev_err(&pdev->dev, "no memory resource defined\n"); @@ -211,9 +218,27 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev, goto err_free_mem; } + if (id->driver_data & HAS_SECONDARY_PWM) { + secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); + if (secondary == NULL) { + ret = -ENOMEM; + goto err_free_mem; + } + + *secondary = *pwm; + pwm->secondary = secondary; + + /* registers for the second PWM has offset of 0x10 */ + secondary->mmio_base = pwm->mmio_base + 0x10; + secondary->pwm_id = pdev->id + 2; + } + __add_pwm(pwm); + if (secondary) + __add_pwm(secondary); + platform_set_drvdata(pdev, pwm); - return pwm; + return 0; err_free_mem: release_mem_region(r->start, r->end - r->start + 1); @@ -221,32 +246,7 @@ err_free_clk: clk_put(pwm->clk); err_free: kfree(pwm); - return ERR_PTR(ret); -} - -static int __devinit pxa25x_pwm_probe(struct platform_device *pdev) -{ - struct pwm_device *pwm = pwm_probe(pdev, pdev->id, NULL); - - if (IS_ERR(pwm)) - return PTR_ERR(pwm); - - return 0; -} - -static int __devinit pxa27x_pwm_probe(struct platform_device *pdev) -{ - struct pwm_device *pwm; - - pwm = pwm_probe(pdev, pdev->id, NULL); - if (IS_ERR(pwm)) - return PTR_ERR(pwm); - - pwm = pwm_probe(pdev, pdev->id + 2, pwm); - if (IS_ERR(pwm)) - return PTR_ERR(pwm); - - return 0; + return ret; } static int __devexit pwm_remove(struct platform_device *pdev) @@ -259,6 +259,12 @@ static int __devexit pwm_remove(struct platform_device *pdev) return -ENODEV; mutex_lock(&pwm_lock); + + if (pwm->secondary) { + list_del(&pwm->secondary->node); + kfree(pwm->secondary); + } + list_del(&pwm->node); mutex_unlock(&pwm_lock); @@ -272,46 +278,25 @@ static int __devexit pwm_remove(struct platform_device *pdev) return 0; } -static struct platform_driver pxa25x_pwm_driver = { +static struct platform_driver pwm_driver = { .driver = { .name = "pxa25x-pwm", + .owner = THIS_MODULE, }, - .probe = pxa25x_pwm_probe, - .remove = __devexit_p(pwm_remove), -}; - -static struct platform_driver pxa27x_pwm_driver = { - .driver = { - .name = "pxa27x-pwm", - }, - .probe = pxa27x_pwm_probe, + .probe = pwm_probe, .remove = __devexit_p(pwm_remove), + .id_table = pwm_id_table, }; static int __init pwm_init(void) { - int ret = 0; - - ret = platform_driver_register(&pxa25x_pwm_driver); - if (ret) { - printk(KERN_ERR "failed to register pxa25x_pwm_driver\n"); - return ret; - } - - ret = platform_driver_register(&pxa27x_pwm_driver); - if (ret) { - printk(KERN_ERR "failed to register pxa27x_pwm_driver\n"); - return ret; - } - - return ret; + return platform_driver_register(&pwm_driver); } arch_initcall(pwm_init); static void __exit pwm_exit(void) { - platform_driver_unregister(&pxa25x_pwm_driver); - platform_driver_unregister(&pxa27x_pwm_driver); + platform_driver_unregister(&pwm_driver); } module_exit(pwm_exit); diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig new file mode 100644 index 000000000000..2cf37c35951b --- /dev/null +++ b/arch/arm/plat-stmp3xxx/Kconfig @@ -0,0 +1,37 @@ +if ARCH_STMP3XXX + +menu "Freescale STMP3xxx implementations" + +choice + prompt "Select STMP3xxx chip family" + +config ARCH_STMP37XX + bool "Freescale SMTP37xx" + select CPU_ARM926T + ---help--- + STMP37xx refers to 3700 through 3769 chips + +config ARCH_STMP378X + bool "Freescale STMP378x" + select CPU_ARM926T + ---help--- + STMP378x refers to 3780 through 3789 chips + +endchoice + +choice + prompt "Select STMP3xxx board type" + +config MACH_STMP37XX + depends on ARCH_STMP37XX + bool "Freescale STMP37xx development board" + +config MACH_STMP378X + depends on ARCH_STMP378X + bool "Freescale STMP378x development board" + +endchoice + +endmenu + +endif diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile new file mode 100644 index 000000000000..b63480066d6b --- /dev/null +++ b/arch/arm/plat-stmp3xxx/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the linux kernel. +# +# Object file lists. +obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c new file mode 100644 index 000000000000..9a1d46b470cd --- /dev/null +++ b/arch/arm/plat-stmp3xxx/clock.c @@ -0,0 +1,1112 @@ +/* + * Clock manipulation routines for Freescale STMP37XX/STMP378X + * + * Author: Vitaly Wool <vital@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/io.h> + +#include <asm/mach-types.h> +#include <asm/clkdev.h> +#include <mach/regs-clkctrl.h> + +#include "clock.h" + +static DEFINE_SPINLOCK(clocks_lock); + +static struct clk osc_24M; +static struct clk pll_clk; +static struct clk cpu_clk; +static struct clk hclk; + +static int propagate_rate(struct clk *); + +static inline int clk_is_busy(struct clk *clk) +{ + return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit); +} + +static inline int clk_good(struct clk *clk) +{ + return clk && !IS_ERR(clk) && clk->ops; +} + +static int std_clk_enable(struct clk *clk) +{ + if (clk->enable_reg) { + u32 clk_reg = __raw_readl(clk->enable_reg); + if (clk->enable_negate) + clk_reg &= ~(1 << clk->enable_shift); + else + clk_reg |= (1 << clk->enable_shift); + __raw_writel(clk_reg, clk->enable_reg); + if (clk->enable_wait) + udelay(clk->enable_wait); + return 0; + } else + return -EINVAL; +} + +static int std_clk_disable(struct clk *clk) +{ + if (clk->enable_reg) { + u32 clk_reg = __raw_readl(clk->enable_reg); + if (clk->enable_negate) + clk_reg |= (1 << clk->enable_shift); + else + clk_reg &= ~(1 << clk->enable_shift); + __raw_writel(clk_reg, clk->enable_reg); + return 0; + } else + return -EINVAL; +} + +static int io_set_rate(struct clk *clk, u32 rate) +{ + u32 reg_frac, clkctrl_frac; + int i, ret = 0, mask = 0x1f; + + clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate; + + if (clkctrl_frac < 18 || clkctrl_frac > 35) { + ret = -EINVAL; + goto out; + } + + reg_frac = __raw_readl(clk->scale_reg); + reg_frac &= ~(mask << clk->scale_shift); + __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift), + clk->scale_reg); + if (clk->busy_reg) { + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) + ret = -ETIMEDOUT; + else + ret = 0; + } +out: + return ret; +} + +static long io_get_rate(struct clk *clk) +{ + long rate = clk->parent->rate * 18; + int mask = 0x1f; + + rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; + clk->rate = rate; + + return rate; +} + +static long per_get_rate(struct clk *clk) +{ + long rate = clk->parent->rate; + long div; + const int mask = 0xff; + + if (clk->enable_reg && + !(__raw_readl(clk->enable_reg) & clk->enable_shift)) + clk->rate = 0; + else { + div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; + if (div) + rate /= div; + clk->rate = rate; + } + + return clk->rate; +} + +static int per_set_rate(struct clk *clk, u32 rate) +{ + int ret = -EINVAL; + int div = (clk->parent->rate + rate - 1) / rate; + u32 reg_frac; + const int mask = 0xff; + int try = 10; + int i = -1; + + if (div == 0 || div > mask) + goto out; + + reg_frac = __raw_readl(clk->scale_reg); + reg_frac &= ~(mask << clk->scale_shift); + + while (try--) { + __raw_writel(reg_frac | (div << clk->scale_shift), + clk->scale_reg); + + if (clk->busy_reg) { + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + } + if (i) + break; + } + + if (!i) + ret = -ETIMEDOUT; + else + ret = 0; + +out: + if (ret != 0) + printk(KERN_ERR "%s: error %d\n", __func__, ret); + return ret; +} + +static long lcdif_get_rate(struct clk *clk) +{ + long rate = clk->parent->rate; + long div; + const int mask = 0xff; + + div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; + if (div) { + rate /= div; + div = (HW_CLKCTRL_FRAC_RD() & BM_CLKCTRL_FRAC_PIXFRAC) >> + BP_CLKCTRL_FRAC_PIXFRAC; + rate /= div; + } + clk->rate = rate; + + return rate; +} + +static int lcdif_set_rate(struct clk *clk, u32 rate) +{ + int ret = 0; + /* + * On 3700, we can get most timings exact by modifying ref_pix + * and the divider, but keeping the phase timings at 1 (2 + * phases per cycle). + * + * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz, + * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns. + * + * ns_cycle >= 2*18e3/(18*480) = 25/6 + * ns_cycle <= 2*35e3/(18*480) = 875/108 + * + * Multiply the ns_cycle by 'div' to lengthen it until it fits the + * bounds. This is the divider we'll use after ref_pix. + * + * 6 * ns_cycle >= 25 * div + * 108 * ns_cycle <= 875 * div + */ + u32 ns_cycle = 1000000 / rate; + u32 div, reg_val; + u32 lowest_result = (u32) -1; + u32 lowest_div = 0, lowest_fracdiv = 0; + + for (div = 1; div < 256; ++div) { + u32 fracdiv; + u32 ps_result; + int lower_bound = 6 * ns_cycle >= 25 * div; + int upper_bound = 108 * ns_cycle <= 875 * div; + if (!lower_bound) + break; + if (!upper_bound) + continue; + /* + * Found a matching div. Calculate fractional divider needed, + * rounded up. + */ + fracdiv = ((clk->parent->rate / 1000 * 18 / 2) * + ns_cycle + 1000 * div - 1) / + (1000 * div); + if (fracdiv < 18 || fracdiv > 35) { + ret = -EINVAL; + goto out; + } + /* Calculate the actual cycle time this results in */ + ps_result = 6250 * div * fracdiv / 27; + + /* Use the fastest result that doesn't break ns_cycle */ + if (ps_result <= lowest_result) { + lowest_result = ps_result; + lowest_div = div; + lowest_fracdiv = fracdiv; + } + } + + if (div >= 256 || lowest_result == (u32) -1) { + ret = -EINVAL; + goto out; + } + pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz " + "PIXCLK=%uMHz cycle=%u.%03uns\n", + lowest_fracdiv, lowest_div, + 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div, + lowest_result / 1000, lowest_result % 1000); + + /* Program ref_pix phase fractional divider */ + HW_CLKCTRL_FRAC_WR((HW_CLKCTRL_FRAC_RD() & ~BM_CLKCTRL_FRAC_PIXFRAC) | + BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv)); + /* Ungate PFD */ + HW_CLKCTRL_FRAC_CLR(BM_CLKCTRL_FRAC_CLKGATEPIX); + + /* Program pix divider */ + reg_val = __raw_readl(clk->scale_reg); + reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); + reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div); + __raw_writel(reg_val, clk->scale_reg); + + /* Wait for divider update */ + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + ret = -ETIMEDOUT; + goto out; + } + } + + /* Switch to ref_pix source */ + HW_CLKCTRL_CLKSEQ_CLR(BM_CLKCTRL_CLKSEQ_BYPASS_PIX); + +out: + return ret; +} + + +static int cpu_set_rate(struct clk *clk, u32 rate) +{ + if (rate < 24000) + return -EINVAL; + else if (rate == 24000) { + /* switch to the 24M source */ + clk_set_parent(clk, &osc_24M); + } else { + int i; + u32 clkctrl_cpu = 1; + u32 c = clkctrl_cpu; + u32 clkctrl_frac = 1; + u32 val; + for ( ; c < 0x40; c++) { + u32 f = (pll_clk.rate*18/c + rate/2) / rate; + int s1, s2; + + if (f < 18 || f > 35) + continue; + s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate; + s2 = pll_clk.rate*18/c/f - rate; + pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2); + if (abs(s1) > abs(s2)) { + clkctrl_cpu = c; + clkctrl_frac = f; + } + if (s2 == 0) + break; + }; + pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__, + clkctrl_cpu, clkctrl_frac); + if (c == 0x40) { + int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - + rate; + if (abs(d) > 100 || + clkctrl_frac < 18 || clkctrl_frac > 35) + return -EINVAL; + } + + /* 4.6.2 */ + val = __raw_readl(clk->scale_reg); + val &= ~(0x3f << clk->scale_shift); + val |= clkctrl_frac; + clk_set_parent(clk, &osc_24M); + udelay(10); + __raw_writel(val, clk->scale_reg); + /* ungate */ + __raw_writel(1<<7, clk->scale_reg + 8); + /* write clkctrl_cpu */ + clk->saved_div = clkctrl_cpu; + HW_CLKCTRL_CPU_WR((HW_CLKCTRL_CPU_RD() & ~0x3f) | clkctrl_cpu); + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up CPU divisor\n"); + return -ETIMEDOUT; + } + clk_set_parent(clk, &pll_clk); + clk->saved_div = 0; + udelay(10); + } + return 0; +} + +static long cpu_get_rate(struct clk *clk) +{ + long rate = clk->parent->rate * 18; + + rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; + rate /= HW_CLKCTRL_CPU_RD() & 0x3f; + rate = ((rate + 9) / 10) * 10; + clk->rate = rate; + + return rate; +} + +static long cpu_round_rate(struct clk *clk, u32 rate) +{ + unsigned long r = 0; + + if (rate <= 24000) + r = 24000; + else { + u32 clkctrl_cpu = 1; + u32 clkctrl_frac; + do { + clkctrl_frac = + (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate; + if (clkctrl_frac > 35) + continue; + if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 == + rate / 10) + break; + } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate); + if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate) + clkctrl_cpu--; + pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__, + clkctrl_cpu, clkctrl_frac); + if (clkctrl_frac < 18) + clkctrl_frac = 18; + if (clkctrl_frac > 35) + clkctrl_frac = 35; + + r = pll_clk.rate * 18; + r /= clkctrl_frac; + r /= clkctrl_cpu; + r = 10 * ((r + 9) / 10); + } + return r; +} + +static long emi_get_rate(struct clk *clk) +{ + long rate = clk->parent->rate * 18; + + rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; + rate /= HW_CLKCTRL_EMI_RD() & 0x3f; + clk->rate = rate; + + return rate; +} + +static int clkseq_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + int shift = 8; + + /* bypass? */ + if (parent == &osc_24M) + shift = 4; + + if (clk->bypass_reg) { + u32 hbus_mask = BM_CLKCTRL_HBUS_DIV_FRAC_EN | + BM_CLKCTRL_HBUS_DIV; + + if (clk == &cpu_clk && shift == 4) { + u32 hbus_val = HW_CLKCTRL_HBUS_RD(); + u32 cpu_val = HW_CLKCTRL_CPU_RD(); + hbus_val &= ~hbus_mask; + hbus_val |= 1; + clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; + cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; + cpu_val |= 1; + __raw_writel(1 << clk->bypass_shift, + clk->bypass_reg + shift); + if (machine_is_stmp378x()) { + HW_CLKCTRL_HBUS_WR(hbus_val); + HW_CLKCTRL_CPU_WR(cpu_val); + hclk.rate = 0; + } + } else if (clk == &cpu_clk && shift == 8) { + u32 hbus_val = HW_CLKCTRL_HBUS_RD(); + u32 cpu_val = HW_CLKCTRL_CPU_RD(); + hbus_val &= ~hbus_mask; + hbus_val |= 2; + cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; + if (clk->saved_div) + cpu_val |= clk->saved_div; + else + cpu_val |= 2; + if (machine_is_stmp378x()) { + HW_CLKCTRL_HBUS_WR(hbus_val); + HW_CLKCTRL_CPU_WR(cpu_val); + hclk.rate = 0; + } + __raw_writel(1 << clk->bypass_shift, + clk->bypass_reg + shift); + } else + __raw_writel(1 << clk->bypass_shift, + clk->bypass_reg + shift); + + ret = 0; + } + + return ret; +} + +static int hbus_set_rate(struct clk *clk, u32 rate) +{ + u8 div = 0; + int is_frac = 0; + u32 clkctrl_hbus; + struct clk *parent = clk->parent; + + pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, + parent->rate); + + if (rate > parent->rate) + return -EINVAL; + + if (((parent->rate + rate/2) / rate) * rate != parent->rate && + parent->rate / rate < 32) { + pr_debug("%s: switching to fractional mode\n", __func__); + is_frac = 1; + } + + if (is_frac) + div = (32 * rate + parent->rate / 2) / parent->rate; + else + div = (parent->rate + rate - 1) / rate; + pr_debug("%s: div calculated is %d\n", __func__, div); + if (!div || div > 0x1f) + return -EINVAL; + + clk_set_parent(&cpu_clk, &osc_24M); + udelay(10); + clkctrl_hbus = __raw_readl(clk->scale_reg); + clkctrl_hbus &= ~0x3f; + clkctrl_hbus |= div; + clkctrl_hbus |= (is_frac << 5); + + __raw_writel(clkctrl_hbus, clk->scale_reg); + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up CPU divisor\n"); + return -ETIMEDOUT; + } + } + clk_set_parent(&cpu_clk, &pll_clk); + __raw_writel(clkctrl_hbus, clk->scale_reg); + udelay(10); + return 0; +} + +static long hbus_get_rate(struct clk *clk) +{ + long rate = clk->parent->rate; + + if (__raw_readl(clk->scale_reg) & 0x20) { + rate *= __raw_readl(clk->scale_reg) & 0x1f; + rate /= 32; + } else + rate /= __raw_readl(clk->scale_reg) & 0x1f; + clk->rate = rate; + + return rate; +} + +static int xbus_set_rate(struct clk *clk, u32 rate) +{ + u16 div = 0; + u32 clkctrl_xbus; + + pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, + clk->parent->rate); + + div = (clk->parent->rate + rate - 1) / rate; + pr_debug("%s: div calculated is %d\n", __func__, div); + if (!div || div > 0x3ff) + return -EINVAL; + + clkctrl_xbus = __raw_readl(clk->scale_reg); + clkctrl_xbus &= ~0x3ff; + clkctrl_xbus |= div; + __raw_writel(clkctrl_xbus, clk->scale_reg); + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up xbus divisor\n"); + return -ETIMEDOUT; + } + } + return 0; +} + +static long xbus_get_rate(struct clk *clk) +{ + long rate = clk->parent->rate; + + rate /= __raw_readl(clk->scale_reg) & 0x3ff; + clk->rate = rate; + + return rate; +} + + +/* Clock ops */ + +static struct clk_ops std_ops = { + .enable = std_clk_enable, + .disable = std_clk_disable, + .get_rate = per_get_rate, + .set_rate = per_set_rate, + .set_parent = clkseq_set_parent, +}; + +static struct clk_ops min_ops = { + .enable = std_clk_enable, + .disable = std_clk_disable, +}; + +static struct clk_ops cpu_ops = { + .enable = std_clk_enable, + .disable = std_clk_disable, + .get_rate = cpu_get_rate, + .set_rate = cpu_set_rate, + .round_rate = cpu_round_rate, + .set_parent = clkseq_set_parent, +}; + +static struct clk_ops io_ops = { + .enable = std_clk_enable, + .disable = std_clk_disable, + .get_rate = io_get_rate, + .set_rate = io_set_rate, +}; + +static struct clk_ops hbus_ops = { + .get_rate = hbus_get_rate, + .set_rate = hbus_set_rate, +}; + +static struct clk_ops xbus_ops = { + .get_rate = xbus_get_rate, + .set_rate = xbus_set_rate, +}; + +static struct clk_ops lcdif_ops = { + .enable = std_clk_enable, + .disable = std_clk_disable, + .get_rate = lcdif_get_rate, + .set_rate = lcdif_set_rate, + .set_parent = clkseq_set_parent, +}; + +static struct clk_ops emi_ops = { + .get_rate = emi_get_rate, +}; + +/* List of on-chip clocks */ + +static struct clk osc_24M = { + .flags = FIXED_RATE | ENABLED, + .rate = 24000, +}; + +static struct clk pll_clk = { + .parent = &osc_24M, + .enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR, + .enable_shift = 16, + .enable_wait = 10, + .flags = FIXED_RATE | ENABLED, + .rate = 480000, + .ops = &min_ops, +}; + +static struct clk cpu_clk = { + .parent = &pll_clk, + .scale_reg = HW_CLKCTRL_FRAC_ADDR, + .scale_shift = 0, + .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_shift = 7, + .busy_reg = HW_CLKCTRL_CPU_ADDR, + .busy_bit = 28, + .flags = RATE_PROPAGATES | ENABLED, + .ops = &cpu_ops, +}; + +static struct clk io_clk = { + .parent = &pll_clk, + .enable_reg = HW_CLKCTRL_FRAC_ADDR, + .enable_shift = 31, + .enable_negate = 1, + .scale_reg = HW_CLKCTRL_FRAC_ADDR, + .scale_shift = 24, + .flags = RATE_PROPAGATES | ENABLED, + .ops = &io_ops, +}; + +static struct clk hclk = { + .parent = &cpu_clk, + .scale_reg = HW_CLKCTRL_HBUS_ADDR, + .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_shift = 7, + .busy_reg = HW_CLKCTRL_HBUS_ADDR, + .busy_bit = 29, + .flags = RATE_PROPAGATES | ENABLED, + .ops = &hbus_ops, +}; + +static struct clk xclk = { + .parent = &osc_24M, + .scale_reg = HW_CLKCTRL_XBUS_ADDR, + .busy_reg = HW_CLKCTRL_XBUS_ADDR, + .busy_bit = 31, + .flags = RATE_PROPAGATES | ENABLED, + .ops = &xbus_ops, +}; + +static struct clk uart_clk = { + .parent = &xclk, + .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_shift = 31, + .enable_negate = 1, + .flags = ENABLED, + .ops = &min_ops, +}; + +static struct clk audio_clk = { + .parent = &xclk, + .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_shift = 30, + .enable_negate = 1, + .ops = &min_ops, +}; + +static struct clk pwm_clk = { + .parent = &xclk, + .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_shift = 29, + .enable_negate = 1, + .ops = &min_ops, +}; + +static struct clk dri_clk = { + .parent = &xclk, + .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_shift = 28, + .enable_negate = 1, + .ops = &min_ops, +}; + +static struct clk digctl_clk = { + .parent = &xclk, + .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_shift = 27, + .enable_negate = 1, + .ops = &min_ops, +}; + +static struct clk timer_clk = { + .parent = &xclk, + .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_shift = 26, + .enable_negate = 1, + .flags = ENABLED, + .ops = &min_ops, +}; + +static struct clk lcdif_clk = { + .parent = &pll_clk, + .scale_reg = HW_CLKCTRL_PIX_ADDR, + .busy_reg = HW_CLKCTRL_PIX_ADDR, + .busy_bit = 29, + .enable_reg = HW_CLKCTRL_PIX_ADDR, + .enable_shift = 31, + .enable_negate = 1, + .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_shift = 1, + .flags = NEEDS_SET_PARENT, + .ops = &lcdif_ops, +}; + +static struct clk ssp_clk = { + .parent = &io_clk, + .scale_reg = HW_CLKCTRL_SSP_ADDR, + .busy_reg = HW_CLKCTRL_SSP_ADDR, + .busy_bit = 29, + .enable_reg = HW_CLKCTRL_SSP_ADDR, + .enable_shift = 31, + .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_shift = 5, + .enable_negate = 1, + .flags = NEEDS_SET_PARENT, + .ops = &std_ops, +}; + +static struct clk gpmi_clk = { + .parent = &io_clk, + .scale_reg = HW_CLKCTRL_GPMI_ADDR, + .busy_reg = HW_CLKCTRL_GPMI_ADDR, + .busy_bit = 29, + .enable_reg = HW_CLKCTRL_GPMI_ADDR, + .enable_shift = 31, + .enable_negate = 1, + .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_shift = 4, + .flags = NEEDS_SET_PARENT, + .ops = &std_ops, +}; + +static struct clk spdif_clk = { + .parent = &pll_clk, + .enable_reg = HW_CLKCTRL_SPDIF_ADDR, + .enable_shift = 31, + .enable_negate = 1, + .ops = &min_ops, +}; + +static struct clk emi_clk = { + .parent = &pll_clk, + .enable_reg = HW_CLKCTRL_EMI_ADDR, + .enable_shift = 31, + .enable_negate = 1, + .scale_reg = HW_CLKCTRL_FRAC_ADDR, + .scale_shift = 8, + .busy_reg = HW_CLKCTRL_EMI_ADDR, + .busy_bit = 28, + .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_shift = 6, + .flags = ENABLED, + .ops = &emi_ops, +}; + +static struct clk ir_clk = { + .parent = &io_clk, + .enable_reg = HW_CLKCTRL_IR_ADDR, + .enable_shift = 31, + .enable_negate = 1, + .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_shift = 3, + .ops = &min_ops, +}; + +static struct clk saif_clk = { + .parent = &pll_clk, + .scale_reg = HW_CLKCTRL_SAIF_ADDR, + .busy_reg = HW_CLKCTRL_SAIF_ADDR, + .busy_bit = 29, + .enable_reg = HW_CLKCTRL_SAIF_ADDR, + .enable_shift = 31, + .enable_negate = 1, + .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_shift = 0, + .ops = &std_ops, +}; + +static struct clk usb_clk = { + .parent = &pll_clk, + .enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR, + .enable_shift = 18, + .enable_negate = 1, + .ops = &min_ops, +}; + +/* list of all the clocks */ +static __initdata struct clk_lookup onchip_clks[] = { + { + .con_id = "osc_24M", + .clk = &osc_24M, + }, { + .con_id = "pll", + .clk = &pll_clk, + }, { + .con_id = "cpu", + .clk = &cpu_clk, + }, { + .con_id = "hclk", + .clk = &hclk, + }, { + .con_id = "xclk", + .clk = &xclk, + }, { + .con_id = "io", + .clk = &io_clk, + }, { + .con_id = "uart", + .clk = &uart_clk, + }, { + .con_id = "audio", + .clk = &audio_clk, + }, { + .con_id = "pwm", + .clk = &pwm_clk, + }, { + .con_id = "dri", + .clk = &dri_clk, + }, { + .con_id = "digctl", + .clk = &digctl_clk, + }, { + .con_id = "timer", + .clk = &timer_clk, + }, { + .con_id = "lcdif", + .clk = &lcdif_clk, + }, { + .con_id = "ssp", + .clk = &ssp_clk, + }, { + .con_id = "gpmi", + .clk = &gpmi_clk, + }, { + .con_id = "spdif", + .clk = &spdif_clk, + }, { + .con_id = "emi", + .clk = &emi_clk, + }, { + .con_id = "ir", + .clk = &ir_clk, + }, { + .con_id = "saif", + .clk = &saif_clk, + }, { + .con_id = "usb", + .clk = &usb_clk, + }, +}; + +static int __init propagate_rate(struct clk *clk) +{ + struct clk_lookup *cl; + + for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks); + cl++) { + if (unlikely(!clk_good(cl->clk))) + continue; + if (cl->clk->parent == clk && cl->clk->ops->get_rate) { + cl->clk->ops->get_rate(cl->clk); + if (cl->clk->flags & RATE_PROPAGATES) + propagate_rate(cl->clk); + } + } + + return 0; +} + +/* Exported API */ +unsigned long clk_get_rate(struct clk *clk) +{ + if (unlikely(!clk_good(clk))) + return 0; + + if (clk->rate != 0) + return clk->rate; + + if (clk->ops->get_rate != NULL) + return clk->ops->get_rate(clk); + + return clk_get_rate(clk->parent); +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (unlikely(!clk_good(clk))) + return 0; + + if (clk->ops->round_rate) + return clk->ops->round_rate(clk, rate); + + return 0; +} +EXPORT_SYMBOL(clk_round_rate); + +static inline int close_enough(long rate1, long rate2) +{ + return rate1 && !((rate2 - rate1) * 1000 / rate1); +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + + if (unlikely(!clk_good(clk))) + goto out; + + if (clk->flags & FIXED_RATE || !clk->ops->set_rate) + goto out; + + else if (!close_enough(clk->rate, rate)) { + ret = clk->ops->set_rate(clk, rate); + if (ret < 0) + goto out; + clk->rate = rate; + if (clk->flags & RATE_PROPAGATES) + propagate_rate(clk); + } else + ret = 0; + +out: + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_enable(struct clk *clk) +{ + unsigned long clocks_flags; + + if (unlikely(!clk_good(clk))) + return -EINVAL; + + if (clk->parent) + clk_enable(clk->parent); + + spin_lock_irqsave(&clocks_lock, clocks_flags); + + clk->usage++; + if (clk->ops && clk->ops->enable) + clk->ops->enable(clk); + + spin_unlock_irqrestore(&clocks_lock, clocks_flags); + return 0; +} +EXPORT_SYMBOL(clk_enable); + +static void local_clk_disable(struct clk *clk) +{ + if (unlikely(!clk_good(clk))) + return; + + if (clk->usage == 0 && clk->ops->disable) + clk->ops->disable(clk); + + if (clk->parent) + local_clk_disable(clk->parent); +} + +void clk_disable(struct clk *clk) +{ + unsigned long clocks_flags; + + if (unlikely(!clk_good(clk))) + return; + + spin_lock_irqsave(&clocks_lock, clocks_flags); + + if ((--clk->usage) == 0 && clk->ops->disable) + clk->ops->disable(clk); + + spin_unlock_irqrestore(&clocks_lock, clocks_flags); + if (clk->parent) + clk_disable(clk->parent); +} +EXPORT_SYMBOL(clk_disable); + +/* Some additional API */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -ENODEV; + unsigned long clocks_flags; + + if (unlikely(!clk_good(clk))) + goto out; + + if (!clk->ops->set_parent) + goto out; + + spin_lock_irqsave(&clocks_lock, clocks_flags); + + ret = clk->ops->set_parent(clk, parent); + if (!ret) { + /* disable if usage count is 0 */ + local_clk_disable(parent); + + parent->usage += clk->usage; + clk->parent->usage -= clk->usage; + + /* disable if new usage count is 0 */ + local_clk_disable(clk->parent); + + clk->parent = parent; + } + spin_unlock_irqrestore(&clocks_lock, clocks_flags); + +out: + return ret; +} +EXPORT_SYMBOL(clk_set_parent); + +struct clk *clk_get_parent(struct clk *clk) +{ + if (unlikely(!clk_good(clk))) + return NULL; + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +static int __init clk_init(void) +{ + struct clk_lookup *cl; + struct clk_ops *ops; + + spin_lock_init(&clocks_lock); + + for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks); + cl++) { + if (cl->clk->flags & ENABLED) + clk_enable(cl->clk); + else + local_clk_disable(cl->clk); + + ops = cl->clk->ops; + + if ((cl->clk->flags & NEEDS_INITIALIZATION) && + ops && ops->set_rate) + ops->set_rate(cl->clk, cl->clk->rate); + + if (cl->clk->flags & FIXED_RATE) { + if (cl->clk->flags & RATE_PROPAGATES) + propagate_rate(cl->clk); + } else { + if (ops && ops->get_rate) + ops->get_rate(cl->clk); + } + + if (cl->clk->flags & NEEDS_SET_PARENT) { + if (ops && ops->set_parent) + ops->set_parent(cl->clk, cl->clk->parent); + } + + clkdev_add(cl); + } + return 0; +} + +arch_initcall(clk_init); diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h new file mode 100644 index 000000000000..a6611e1a3510 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/clock.h @@ -0,0 +1,61 @@ +/* + * Clock control driver for Freescale STMP37XX/STMP378X - internal header file + * + * Author: Vitaly Wool <vital@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__ +#define __ARCH_ARM_STMX3XXX_CLOCK_H__ + +#ifndef __ASSEMBLER__ + +struct clk_ops { + int (*enable) (struct clk *); + int (*disable) (struct clk *); + long (*get_rate) (struct clk *); + long (*round_rate) (struct clk *, u32); + int (*set_rate) (struct clk *, u32); + int (*set_parent) (struct clk *, struct clk *); +}; + +struct clk { + struct clk *parent; + u32 rate; + u32 flags; + u8 scale_shift; + u8 enable_shift; + u8 bypass_shift; + u8 busy_bit; + s8 usage; + int enable_wait; + int enable_negate; + u32 saved_div; + void __iomem *enable_reg; + void __iomem *scale_reg; + void __iomem *bypass_reg; + void __iomem *busy_reg; + struct clk_ops *ops; +}; + +#endif /* __ASSEMBLER__ */ + +/* Flags */ +#define RATE_PROPAGATES (1<<0) +#define NEEDS_INITIALIZATION (1<<1) +#define PARENT_SET_RATE (1<<2) +#define FIXED_RATE (1<<3) +#define ENABLED (1<<4) +#define NEEDS_SET_PARENT (1<<5) + +#endif diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c new file mode 100644 index 000000000000..6e2fef1639b0 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/core.c @@ -0,0 +1,127 @@ +/* + * Freescale STMP37XX/STMP378X core routines + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <mach/stmp3xxx.h> +#include <mach/dma.h> +#include <mach/regs-clkctrl.h> + +static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable) +{ + u32 c; + int timeout; + + /* the process of software reset of IP block is done + in several steps: + + - clear SFTRST and wait for block is enabled; + - clear clock gating (CLKGATE bit); + - set the SFTRST again and wait for block is in reset; + - clear SFTRST and wait for reset completion. + */ + c = __raw_readl(hwreg); + c &= ~(1<<31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1<<31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR"%s(%p): timeout when enabling\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1<<30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + + if (!just_enable) { + c = __raw_readl(hwreg); + c |= (1<<31); /* now again set SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* poll until CLKGATE set */ + if (__raw_readl(hwreg) & (1<<30)) + break; + if (timeout <= 0) { + printk(KERN_ERR"%s(%p): timeout when resetting\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1<<31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1<<31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR"%s(%p): timeout when enabling " + "after reset\n", __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1<<30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + } + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1<<30)) == 0) + break; + + if (timeout <= 0) { + printk(KERN_ERR"%s(%p): timeout when unclockgating\n", + __func__, hwreg); + return -ETIME; + } + + return 0; +} + +int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable) +{ + int try = 10; + int r; + + while (try--) { + r = __stmp3xxx_reset_block(hwreg, just_enable); + if (!r) + break; + pr_debug("%s: try %d failed\n", __func__, 10 - try); + } + return r; +} +EXPORT_SYMBOL(stmp3xxx_reset_block); + +struct platform_device stmp3xxx_dbguart = { + .name = "stmp3xxx-dbguart", + .id = -1, +}; + +void __init stmp3xxx_init(void) +{ + /* Turn off auto-slow and other tricks */ + HW_CLKCTRL_HBUS_CLR(0x07f00000U); + + stmp3xxx_dma_init(); +} diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c new file mode 100644 index 000000000000..cf42de05e568 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/dma.c @@ -0,0 +1,462 @@ +/* + * DMA helper routines for Freescale STMP37XX/STMP378X + * + * Author: dmitry pervushin <dpervushin@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/dmapool.h> +#include <linux/sysdev.h> +#include <linux/cpufreq.h> + +#include <asm/page.h> + +#include <mach/dma.h> +#include <mach/regs-apbx.h> +#include <mach/regs-apbh.h> + +static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command); +static const size_t pool_alignment = 8; +static struct stmp3xxx_dma_user { + void *pool; + int inuse; + const char *name; +} channels[MAX_DMA_CHANNELS]; + +static inline int dmach(int ch) +{ + return ch % 16; +} + +static inline int dmabus(int ch) +{ + return ch / 16; +} + +#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS) +#define IS_USED(ch) (channels[ch].inuse) + +int stmp3xxx_dma_request(int ch, struct device *dev, const char *name) +{ + struct stmp3xxx_dma_user *user; + int err = 0; + + user = channels + ch; + if (!IS_VALID_CHANNEL(ch)) { + err = -ENODEV; + goto out; + } + if (IS_USED(ch)) { + err = -EBUSY; + goto out; + } + /* Create a pool to allocate dma commands from */ + user->pool = dma_pool_create(name, dev, pool_item_size, + pool_alignment, PAGE_SIZE); + if (user->pool == NULL) { + err = -ENOMEM; + goto out; + } + user->name = name; + user->inuse++; +out: + return err; +} +EXPORT_SYMBOL(stmp3xxx_dma_request); + +int stmp3xxx_dma_release(int ch) +{ + struct stmp3xxx_dma_user *user = channels + ch; + int err = 0; + + if (!IS_VALID_CHANNEL(ch)) { + err = -ENODEV; + goto out; + } + if (!IS_USED(ch)) { + err = -EBUSY; + goto out; + } + BUG_ON(user->pool == NULL); + dma_pool_destroy(user->pool); + user->inuse--; +out: + return err; +} +EXPORT_SYMBOL(stmp3xxx_dma_release); + +int stmp3xxx_dma_read_semaphore(int channel) +{ + int sem = -1; + + switch (dmabus(channel)) { + case STMP3XXX_BUS_APBH: + sem = + (HW_APBH_CHn_SEMA_RD(dmach(channel)) & + BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; + break; + + case STMP3XXX_BUS_APBX: + sem = + (HW_APBX_CHn_SEMA_RD(dmach(channel)) & + BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE; + break; + default: + BUG(); + } + return sem; +} +EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore); + +int stmp3xxx_dma_allocate_command(int channel, + struct stmp3xxx_dma_descriptor *descriptor) +{ + struct stmp3xxx_dma_user *user = channels + channel; + int err = 0; + + if (!IS_VALID_CHANNEL(channel)) { + err = -ENODEV; + goto out; + } + if (!IS_USED(channel)) { + err = -EBUSY; + goto out; + } + if (descriptor == NULL) { + err = -EINVAL; + goto out; + } + + /* Allocate memory for a command from the buffer */ + descriptor->command = + dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle); + + /* Check it worked */ + if (!descriptor->command) { + err = -ENOMEM; + goto out; + } + + memset(descriptor->command, 0, pool_item_size); +out: + WARN_ON(err); + return err; +} +EXPORT_SYMBOL(stmp3xxx_dma_allocate_command); + +int stmp3xxx_dma_free_command(int channel, + struct stmp3xxx_dma_descriptor *descriptor) +{ + int err = 0; + + if (!IS_VALID_CHANNEL(channel)) { + err = -ENODEV; + goto out; + } + if (!IS_USED(channel)) { + err = -EBUSY; + goto out; + } + + /* Return the command memory to the pool */ + dma_pool_free(channels[channel].pool, descriptor->command, + descriptor->handle); + + /* Initialise descriptor so we're not tempted to use it */ + descriptor->command = NULL; + descriptor->handle = 0; + descriptor->virtual_buf_ptr = NULL; + descriptor->next_descr = NULL; + + WARN_ON(err); +out: + return err; +} +EXPORT_SYMBOL(stmp3xxx_dma_free_command); + +void stmp3xxx_dma_go(int channel, + struct stmp3xxx_dma_descriptor *head, u32 semaphore) +{ + int ch = dmach(channel); + + switch (dmabus(channel)) { + case STMP3XXX_BUS_APBH: + /* Set next command */ + HW_APBH_CHn_NXTCMDAR_WR(ch, head->handle); + /* Set counting semaphore (kicks off transfer). Assumes + peripheral has been set up correctly */ + HW_APBH_CHn_SEMA_WR(ch, semaphore); + break; + + case STMP3XXX_BUS_APBX: + /* Set next command */ + HW_APBX_CHn_NXTCMDAR_WR(ch, head->handle); + /* Set counting semaphore (kicks off transfer). Assumes + peripheral has been set up correctly */ + HW_APBX_CHn_SEMA_WR(ch, semaphore); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_dma_go); + +int stmp3xxx_dma_running(int channel) +{ + switch (dmabus(channel)) { + case STMP3XXX_BUS_APBH: + return HW_APBH_CHn_SEMA_RD(dmach(channel)) & + BM_APBH_CHn_SEMA_PHORE; + + case STMP3XXX_BUS_APBX: + return HW_APBX_CHn_SEMA_RD(dmach(channel)) & + BM_APBX_CHn_SEMA_PHORE; + + default: + BUG(); + return 0; + } +} +EXPORT_SYMBOL(stmp3xxx_dma_running); + +/* + * Circular dma chain management + */ +void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain) +{ + int i; + + for (i = 0; i < chain->total_count; i++) + stmp3xxx_dma_free_command( + STMP3xxx_DMA(chain->channel, chain->bus), + &chain->chain[i]); +} +EXPORT_SYMBOL(stmp3xxx_dma_free_chain); + +int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, + struct stmp3xxx_dma_descriptor descriptors[], + unsigned items) +{ + int i; + int err = 0; + + if (items == 0) + return err; + + for (i = 0; i < items; i++) { + err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]); + if (err) { + WARN_ON(err); + /* + * Couldn't allocate the whole chain. + * deallocate what has been allocated + */ + if (i) { + do { + stmp3xxx_dma_free_command(ch, + &descriptors + [i]); + } while (i-- >= 0); + } + return err; + } + + /* link them! */ + if (i > 0) { + descriptors[i - 1].next_descr = &descriptors[i]; + descriptors[i - 1].command->next = + descriptors[i].handle; + } + } + + /* make list circular */ + descriptors[items - 1].next_descr = &descriptors[0]; + descriptors[items - 1].command->next = descriptors[0].handle; + + chain->total_count = items; + chain->chain = descriptors; + chain->free_index = 0; + chain->active_index = 0; + chain->cooked_index = 0; + chain->free_count = items; + chain->active_count = 0; + chain->cooked_count = 0; + chain->bus = dmabus(ch); + chain->channel = dmach(ch); + return err; +} +EXPORT_SYMBOL(stmp3xxx_dma_make_chain); + +void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain) +{ + BUG_ON(stmp3xxx_dma_running(STMP3xxx_DMA(chain->channel, chain->bus)) > + 0); + chain->free_index = 0; + chain->active_index = 0; + chain->cooked_index = 0; + chain->free_count = chain->total_count; + chain->active_count = 0; + chain->cooked_count = 0; +} +EXPORT_SYMBOL(stmp37xx_circ_clear_chain); + +void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain, + unsigned count) +{ + BUG_ON(chain->cooked_count < count); + + chain->cooked_count -= count; + chain->cooked_index += count; + chain->cooked_index %= chain->total_count; + chain->free_count += count; +} +EXPORT_SYMBOL(stmp37xx_circ_advance_free); + +void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, + unsigned count) +{ + BUG_ON(chain->free_count < count); + + chain->free_count -= count; + chain->free_index += count; + chain->free_index %= chain->total_count; + chain->active_count += count; + + switch (chain->bus) { + case STMP3XXX_BUS_APBH: + /* Set counting semaphore (kicks off transfer). Assumes + peripheral has been set up correctly */ + HW_APBH_CHn_SEMA_CLR(chain->channel, + BM_APBH_CHn_SEMA_INCREMENT_SEMA); + HW_APBH_CHn_SEMA_SET(chain->channel, + BF_APBH_CHn_SEMA_INCREMENT_SEMA(count)); + break; + + case STMP3XXX_BUS_APBX: + /* Set counting semaphore (kicks off transfer). Assumes + peripheral has been set up correctly */ + HW_APBX_CHn_SEMA_CLR(chain->channel, + BM_APBX_CHn_SEMA_INCREMENT_SEMA); + HW_APBX_CHn_SEMA_SET(chain->channel, + BF_APBX_CHn_SEMA_INCREMENT_SEMA(count)); + break; + + default: + BUG(); + } +} +EXPORT_SYMBOL(stmp37xx_circ_advance_active); + +unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain) +{ + unsigned cooked; + + cooked = chain->active_count - + stmp3xxx_dma_read_semaphore(STMP3xxx_DMA(chain->channel, chain->bus)); + + chain->active_count -= cooked; + chain->active_index += cooked; + chain->active_index %= chain->total_count; + + chain->cooked_count += cooked; + + return cooked; +} +EXPORT_SYMBOL(stmp37xx_circ_advance_cooked); + +void stmp3xxx_dma_set_alt_target(int channel, int function) +{ +#if defined(CONFIG_ARCH_STMP37XX) + unsigned bits = 4; +#elif defined(CONFIG_ARCH_STMP378X) + unsigned bits = 2; +#else +#error wrong arch +#endif + int shift = dmach(channel) * bits; + unsigned mask = (1<<bits) - 1; + + BUG_ON(function < 0 || function >= (1<<bits)); + pr_debug("%s: channel = %d, using mask %x, " + "shift = %d\n", __func__, channel, mask, shift); + + switch (dmabus(channel)) { + case STMP3XXX_BUS_APBH: + HW_APBH_DEVSEL_CLR(mask<<shift); + HW_APBH_DEVSEL_SET(function<<shift); + break; + case STMP3XXX_BUS_APBX: + HW_APBX_DEVSEL_CLR(mask<<shift); + HW_APBX_DEVSEL_SET(function<<shift); + break; + default: + BUG(); + } +} +EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target); + +void stmp3xxx_dma_suspend(void) +{ + HW_APBH_CTRL0_SET(BM_APBH_CTRL0_CLKGATE); + HW_APBX_CTRL0_SET(BM_APBX_CTRL0_CLKGATE); +} + +void stmp3xxx_dma_resume(void) +{ + HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST); + HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST); +} + +#ifdef CONFIG_CPU_FREQ + +struct dma_notifier_block { + struct notifier_block nb; + void *data; +}; + +static int dma_cpufreq_notifier(struct notifier_block *self, + unsigned long phase, void *p) +{ + switch (phase) { + case CPUFREQ_POSTCHANGE: + stmp3xxx_dma_resume(); + break; + + case CPUFREQ_PRECHANGE: + stmp3xxx_dma_suspend(); + break; + + default: + break; + } + + return NOTIFY_DONE; +} + +static struct dma_notifier_block dma_cpufreq_nb = { + .nb = { + .notifier_call = dma_cpufreq_notifier, + }, +}; +#endif /* CONFIG_CPU_FREQ */ + +void __init stmp3xxx_dma_init(void) +{ + HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST); + HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST); +#ifdef CONFIG_CPU_FREQ + cpufreq_register_notifier(&dma_cpufreq_nb.nb, + CPUFREQ_TRANSITION_NOTIFIER); +#endif /* CONFIG_CPU_FREQ */ + +} diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h new file mode 100644 index 000000000000..f9c39772d7c5 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h @@ -0,0 +1,18 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h new file mode 100644 index 000000000000..b4e205b95f2c --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/cputype.h @@ -0,0 +1,33 @@ +/* + * Freescale STMP37XX/STMP378X CPU type detection + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_CPU_H +#define __ASM_PLAT_CPU_H + +#ifdef CONFIG_ARCH_STMP37XX +#define cpu_is_stmp37xx() (1) +#else +#define cpu_is_stmp37xx() (0) +#endif + +#ifdef CONFIG_ARCH_STMP378X +#define cpu_is_stmp378x() (1) +#else +#define cpu_is_stmp378x() (0) +#endif + +#endif /* __ASM_PLAT_CPU_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S new file mode 100644 index 000000000000..fb3b969bf0a2 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S @@ -0,0 +1,42 @@ +/* + * Debugging macro include header + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x80000000 @ physical base address + addeq \rx, \rx, #0x00070000 + movne \rx, #0xf0000000 @ virtual base + addne \rx, \rx, #0x00070000 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #0] @ data register at 0 + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full + bne 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy + bne 1001b + .endm diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h new file mode 100644 index 000000000000..1e305b2bfe73 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/dma.h @@ -0,0 +1,155 @@ +/* + * Freescale STMP37XX/STMP378X DMA helper interface + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_STMP3XXX_DMA_H +#define __ASM_PLAT_STMP3XXX_DMA_H + +#include <linux/platform_device.h> +#include <linux/dmapool.h> + +#if !defined(MAX_PIO_WORDS) +#define MAX_PIO_WORDS (15) +#endif + +#define STMP3XXX_BUS_APBH 0 +#define STMP3XXX_BUS_APBX 1 +#define STMP3XXX_DMA_MAX_CHANNEL 16 + + +#define STMP3xxx_DMA(channel, bus) ((bus) * 16 + (channel)) + +#define MAX_DMA_ADDRESS 0xffffffff + +#define MAX_DMA_CHANNELS 32 + +struct stmp3xxx_dma_command { + u32 next; + u32 cmd; + union { + u32 buf_ptr; + u32 alternate; + }; + u32 pio_words[MAX_PIO_WORDS]; +}; + +struct stmp3xxx_dma_descriptor { + struct stmp3xxx_dma_command *command; + dma_addr_t handle; + + /* The virtual address of the buffer pointer */ + void *virtual_buf_ptr; + /* The next descriptor in a the DMA chain (optional) */ + struct stmp3xxx_dma_descriptor *next_descr; +}; + +struct stmp37xx_circ_dma_chain { + unsigned total_count; + struct stmp3xxx_dma_descriptor *chain; + + unsigned free_index; + unsigned free_count; + unsigned active_index; + unsigned active_count; + unsigned cooked_index; + unsigned cooked_count; + + int bus; + unsigned channel; +}; + +static inline struct stmp3xxx_dma_descriptor + *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain) +{ + return &(chain->chain[chain->free_index]); +} + +static inline struct stmp3xxx_dma_descriptor + *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain) +{ + return &(chain->chain[chain->cooked_index]); +} + +int stmp3xxx_dma_request(int ch, struct device *dev, const char *name); +int stmp3xxx_dma_release(int ch); +int stmp3xxx_dma_allocate_command(int ch, + struct stmp3xxx_dma_descriptor *descriptor); +int stmp3xxx_dma_free_command(int ch, + struct stmp3xxx_dma_descriptor *descriptor); +void stmp3xxx_dma_continue(int channel, u32 semaphore); +void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head, + u32 semaphore); +int stmp3xxx_dma_running(int ch); +int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, + struct stmp3xxx_dma_descriptor descriptors[], + unsigned items); +void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain); +void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain); +void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain, + unsigned count); +void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, + unsigned count); +unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain); +int stmp3xxx_dma_read_semaphore(int ch); +void stmp3xxx_dma_init(void); +void stmp3xxx_dma_set_alt_target(int ch, int target); +void stmp3xxx_dma_suspend(void); +void stmp3xxx_dma_resume(void); + +/* + * STMP37xx and STMP378x have different DMA control + * registers layout + */ + +void stmp3xxx_arch_dma_freeze(int ch); +void stmp3xxx_arch_dma_unfreeze(int ch); +void stmp3xxx_arch_dma_reset_channel(int ch); +void stmp3xxx_arch_dma_enable_interrupt(int ch); +void stmp3xxx_arch_dma_clear_interrupt(int ch); +int stmp3xxx_arch_dma_is_interrupt(int ch); + +static inline void stmp3xxx_dma_reset_channel(int ch) +{ + stmp3xxx_arch_dma_reset_channel(ch); +} + + +static inline void stmp3xxx_dma_freeze(int ch) +{ + stmp3xxx_arch_dma_freeze(ch); +} + +static inline void stmp3xxx_dma_unfreeze(int ch) +{ + stmp3xxx_arch_dma_unfreeze(ch); +} + +static inline void stmp3xxx_dma_enable_interrupt(int ch) +{ + stmp3xxx_arch_dma_enable_interrupt(ch); +} + +static inline void stmp3xxx_dma_clear_interrupt(int ch) +{ + stmp3xxx_arch_dma_clear_interrupt(ch); +} + +static inline int stmp3xxx_dma_is_interrupt(int ch) +{ + return stmp3xxx_arch_dma_is_interrupt(ch); +} + +#endif /* __ASM_PLAT_STMP3XXX_DMA_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h new file mode 100644 index 000000000000..a8b579256170 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/gpio.h @@ -0,0 +1,28 @@ +/* + * Freescale STMP37XX/STMP378X GPIO interface + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_GPIO_H +#define __ASM_PLAT_GPIO_H + +#define ARCH_NR_GPIOS (32 * 3) +#define gpio_to_irq(gpio) __gpio_to_irq(gpio) +#define gpio_get_value(gpio) __gpio_get_value(gpio) +#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value) + +#include <asm-generic/gpio.h> + +#endif /* __ASM_PLAT_GPIO_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h new file mode 100644 index 000000000000..47b8978405bc --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/hardware.h @@ -0,0 +1,32 @@ +/* + * This file contains the hardware definitions of the Freescale STMP3XXX + * + * Copyright (C) 2005 Sigmatel Inc + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Where in virtual memory the IO devices (timers, system controllers + * and so on) + */ +#define IO_BASE 0xF0000000 /* VA of IO */ +#define IO_SIZE 0x00100000 /* How much? */ +#define IO_START 0x80000000 /* PA of IO */ + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE) + +#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h new file mode 100644 index 000000000000..d08b1b7f3d1c --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/io.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2005 Sigmatel Inc + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h new file mode 100644 index 000000000000..7b875a07a1a7 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/memory.h @@ -0,0 +1,22 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x40000000) + +#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h new file mode 100644 index 000000000000..526c068d7c44 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h @@ -0,0 +1,158 @@ +/* + * Freescale STMP37XX/STMP378X Pin Multiplexing + * + * Author: Vladislav Buzov <vbuzov@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __PINMUX_H +#define __PINMUX_H + +#include <linux/spinlock.h> +#include <linux/types.h> +#include <linux/gpio.h> +#include <asm-generic/gpio.h> + +/* Pin definitions */ +#include "pins.h" +#include <mach/pins.h> + +/* + * Each pin may be routed up to four different HW interfaces + * including GPIO + */ +enum pin_fun { + PIN_FUN1 = 0, + PIN_FUN2, + PIN_FUN3, + PIN_GPIO, +}; + +/* + * Each pin may have different output drive strength in range from + * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths. + */ +enum pin_strength { + PIN_4MA = 0, + PIN_8MA, + PIN_12MA, + PIN_16MA, + PIN_20MA, +}; + +/* + * Each pin can be programmed for 1.8V or 3.3V + */ +enum pin_voltage { + PIN_1_8V = 0, + PIN_3_3V, +}; + +/* + * Structure to define a group of pins and their parameters + */ +struct pin_desc { + unsigned id; + enum pin_fun fun; + enum pin_strength strength; + enum pin_voltage voltage; + unsigned pullup:1; +}; + +struct pin_group { + struct pin_desc *pins; + int nr_pins; +}; + +/* Set pin drive strength */ +void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, + const char *label); + +/* Set pin voltage */ +void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, + const char *label); + +/* Enable pull-up resistor for a pin */ +void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label); + +/* + * Request a pin ownership, only one module (identified by @label) + * may own a pin. + */ +int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label); + +/* Release pin */ +void stmp3xxx_release_pin(unsigned id, const char *label); + +void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun); + +/* + * Each bank is associated with a number of registers to control + * pin function, drive strength, voltage and pull-up reigster. The + * number of registers of a given type depends on the number of bits + * describin particular pin. + */ +#define HW_MUXSEL_NUM 2 /* registers per bank */ +#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */ +#define HW_MUXSEL_PIN_NUM 16 /* pins per register */ +#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */ +#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */ + +#define HW_DRIVE_NUM 4 /* registers per bank */ +#define HW_DRIVE_PIN_LEN 4 /* bits per pin */ +#define HW_DRIVE_PIN_NUM 8 /* pins per register */ +#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */ +#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */ +#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */ + + +struct stmp3xxx_pinmux_bank { + struct gpio_chip chip; + + /* Pins allocation map */ + unsigned long pin_map; + + /* Pin owner names */ + const char *pin_labels[32]; + + /* Bank registers */ + void __iomem *hw_muxsel[HW_MUXSEL_NUM]; + void __iomem *hw_drive[HW_DRIVE_NUM]; + void __iomem *hw_pull; + + void __iomem *pin2irq, + *irqlevel, + *irqpolarity, + *irqen, + *irqstat; + + /* HW MUXSEL register function bit values */ + u8 functions[HW_MUXSEL_PINFUN_NUM]; + + /* + * HW DRIVE register strength bit values: + * 0xff - requested strength is not supported for this bank + */ + u8 strengths[HW_DRIVE_PINDRV_NUM]; + + /* GPIO things */ + void __iomem *hw_gpio_read, + *hw_gpio_set, + *hw_gpio_clr, + *hw_gpio_doe; + int irq, virq; +}; + +int __init stmp3xxx_pinmux_init(int virtual_irq_start); + +#endif /* __PINMUX_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h new file mode 100644 index 000000000000..c573318e1caa --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/pins.h @@ -0,0 +1,30 @@ +/* + * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions + * + * Author: Vladislav Buzov <vbuzov@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_PINS_H +#define __ASM_PLAT_PINS_H + +#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin) +#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32) +#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32) + +/* + * Special invalid pin identificator to show a pin doesn't exist + */ +#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF) + +#endif /* __ASM_PLAT_PINS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h new file mode 100644 index 000000000000..525c41379bbe --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/platform.h @@ -0,0 +1,47 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_PLATFORM_H +#define __ASM_PLAT_PLATFORM_H + +#include <asm/sizes.h> + +/* Virtual address where registers are mapped */ +#define STMP3XXX_REGS_PHBASE 0x80000000 +#ifdef __ASSEMBLER__ +#define STMP3XXX_REGS_BASE 0xF0000000 +#else +#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000 +#endif +#define STMP3XXX_REGS_SIZE SZ_1M + +/* Virtual address where OCRAM is mapped */ +#define STMP3XXX_OCRAM_PHBASE 0x00000000 +#ifdef __ASSEMBLER__ +#define STMP3XXX_OCRAM_BASE 0xf1000000 +#else +#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000 +#endif +#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K) + +#ifdef CONFIG_ARCH_STMP37XX +#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD +#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR +#endif + +#ifdef CONFIG_ARCH_STMP378X +#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD +#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR +#endif + +#endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h new file mode 100644 index 000000000000..78cf1be75519 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h @@ -0,0 +1,34 @@ +/* + * Freescale STMP37XX/STMP378X core structure and function declarations + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_STMP3XXX_H +#define __ASM_PLAT_STMP3XXX_H + +#include <linux/irq.h> + +extern struct sys_timer stmp3xxx_timer; + +void stmp3xxx_init_irq(struct irq_chip *chip); +void stmp3xxx_init(void); +int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable); +extern struct platform_device stmp3xxx_dbguart; + +struct pin_group; +void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label); +int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label); + +#endif /* __ASM_PLAT_STMP3XXX_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h new file mode 100644 index 000000000000..47797b2b36af --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h @@ -0,0 +1,195 @@ +/* + * Freescale STMP37XX/STMP378X SoC register access interfaces + * + * The SoC registers may be accessed via: + * + * - single 32 bit address, or + * - four 32 bit addresses - general purpose, set, clear and toggle bits + * + * Multiple IP blocks (e.g. SSP, UART) provide identical register sets per + * each module + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_STMP3XXX_REGS_H +#define __ASM_PLAT_STMP3XXX_REGS_H + +#ifndef __ASSEMBLER__ +#include <linux/io.h> +#endif + +#include "platform.h" + +#define REGS_BASE STMP3XXX_REGS_BASE + +#define HW_STMP3xxx_SET 0x04 +#define HW_STMP3xxx_CLR 0x08 +#define HW_STMP3xxx_TOG 0x0c + +#ifndef __ASSEMBLER__ +#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) \ + static const u32 id##_OFFSET = offset; \ + static inline u32 id##_RD_NB(const void __iomem *regbase) { \ + if (!rd) \ + printk(KERN_ERR"%s: cannot READ at %p+%x\n", \ + #id, regbase, offset); \ + return __raw_readl(regbase + offset); \ + } \ + static inline void id##_WR_NB(void __iomem *regbase, u32 v) { \ + if (!wr) \ + printk(KERN_ERR"%s: cannot WRITE at %p+%x\n", \ + #id, regbase, offset); \ + __raw_writel(v, regbase + offset); \ + } \ + static inline void id##_SET_NB(void __iomem *regbase, u32 v) { \ + if (!wr) \ + printk(KERN_ERR"%s: cannot SET at %p+%x\n", \ + #id, regbase, offset); \ + if (regset) \ + __raw_writel(v, regbase + \ + offset + HW_STMP3xxx_SET); \ + else \ + __raw_writel(v | __raw_readl(regbase + offset), \ + regbase + offset); \ + } \ + static inline void id##_CLR_NB(void __iomem *regbase, u32 v) { \ + if (!wr) \ + printk(KERN_ERR"%s: cannot CLR at %p+%x\n", \ + #id, regbase, offset); \ + if (regset) \ + __raw_writel(v, regbase + \ + offset + HW_STMP3xxx_CLR); \ + else \ + __raw_writel( \ + ~v & __raw_readl(regbase + offset), \ + regbase + offset); \ + } \ + static inline void id##_TOG_NB(void __iomem *regbase, u32 v) { \ + if (!wr) \ + printk(KERN_ERR"%s: cannot TOG at %p+%x\n", \ + #id, regbase, offset); \ + if (regset) \ + __raw_writel(v, regbase + \ + offset + HW_STMP3xxx_TOG); \ + else \ + __raw_writel(v ^ __raw_readl(regbase + offset), \ + regbase + offset); \ + } \ + static inline u32 id##_RD(void) { return id##_RD_NB(base); } \ + static inline void id##_WR(u32 v) { id##_WR_NB(base, v); } \ + static inline void id##_SET(u32 v) { id##_SET_NB(base, v); } \ + static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); } \ + static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); } + +#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\ + static inline u32 id##_OFFSET(int i) { \ + return offset + i * step; \ + } \ + static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\ + if (!rd) \ + printk(KERN_ERR"%s(%d): can't READ at %p+%x\n", \ + #id, i, regbase, offset + i * step); \ + return __raw_readl(regbase + offset + i * step); \ + } \ + static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\ + if (!wr) \ + printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\ + #id, i, regbase, offset + i * step); \ + __raw_writel(v, regbase + offset + i * step); \ + } \ + static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\ + if (!wr) \ + printk(KERN_ERR"%s(%d): can't SET at %p+%x\n", \ + #id, i, regbase, offset + i * step); \ + if (regset) \ + __raw_writel(v, regbase + offset + \ + i * step + HW_STMP3xxx_SET); \ + else \ + __raw_writel(v | __raw_readl(regbase + \ + offset + i * step), \ + regbase + offset + i * step); \ + } \ + static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\ + if (!wr) \ + printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n", \ + #id, i, regbase, offset + i * step); \ + if (regset) \ + __raw_writel(v, regbase + offset + \ + i * step + HW_STMP3xxx_CLR); \ + else \ + __raw_writel(~v & __raw_readl(regbase + \ + offset + i * step), \ + regbase + offset + i * step); \ + } \ + static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\ + if (!wr) \ + printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n", \ + #id, i, regbase, offset + i * step); \ + if (regset) \ + __raw_writel(v, regbase + offset + \ + i * step + HW_STMP3xxx_TOG); \ + else \ + __raw_writel(v ^ __raw_readl(regbase + offset \ + + i * step), \ + regbase + offset + i * step); \ + } \ + static inline u32 id##_RD(int i) \ + { \ + return id##_RD_NB(base, i); \ + } \ + static inline void id##_WR(int i, u32 v) \ + { \ + id##_WR_NB(base, i, v); \ + } \ + static inline void id##_SET(int i, u32 v) \ + { \ + id##_SET_NB(base, i, v); \ + } \ + static inline void id##_CLR(int i, u32 v) \ + { \ + id##_CLR_NB(base, i, v); \ + } \ + static inline void id##_TOG(int i, u32 v) \ + { \ + id##_TOG_NB(base, i, v); \ + } + +#define HW_REGISTER_WO(id, base, offset)\ + HW_REGISTER_FUNCS(id, base, offset, 1, 0, 1) +#define HW_REGISTER_RO(id, base, offset)\ + HW_REGISTER_FUNCS(id, base, offset, 1, 1, 0) +#define HW_REGISTER(id, base, offset) \ + HW_REGISTER_FUNCS(id, base, offset, 1, 1, 1) +#define HW_REGISTER_0(id, base, offset) \ + HW_REGISTER_FUNCS(id, base, offset, 0, 1, 1) +#define HW_REGISTER_INDEXED(id, base, offset, step) \ + HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 1, step) +#define HW_REGISTER_RO_INDEXED(id, base, offset, step) \ + HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 0, step) +#define HW_REGISTER_0_INDEXED(id, base, offset, step) \ + HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0, 1, 1, step) +#else /* __ASSEMBLER__ */ +#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) +#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step) +#define HW_REGISTER_WO(id, base, offset) +#define HW_REGISTER_RO(id, base, offset) +#define HW_REGISTER(id, base, offset) +#define HW_REGISTER_0(id, base, offset) +#define HW_REGISTER_INDEXED(id, base, offset, step) +#define HW_REGISTER_RO_INDEXED(id, base, offset, step) +#define HW_REGISTER_0_INDEXED(id, base, offset, step) +#endif /* __ASSEMBLER__ */ + +#endif /* __ASM_PLAT_STMP3XXX_REGS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h new file mode 100644 index 000000000000..dac48d267148 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/system.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2005 Sigmatel Inc + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <asm/proc-fns.h> +#include <mach/regs-clkctrl.h> +#include <mach/regs-power.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + /* Set BATTCHRG to default value */ + HW_POWER_CHARGE_WR(0x00010000); + + /* Set MINPWR to default value */ + HW_POWER_MINPWR_WR(0); + + /* Reset digital side of chip (but not power or RTC) */ + HW_CLKCTRL_RESET_WR(BM_CLKCTRL_RESET_DIG); + + /* Should not return */ +} + +#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h new file mode 100644 index 000000000000..3373985d7a8e --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/timex.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 1999 ARM Limited + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * System time clock is sourced from the 32k clock + */ +#define CLOCK_TICK_RATE (32768) diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h new file mode 100644 index 000000000000..f79f5ee56cd4 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h @@ -0,0 +1,53 @@ +/* + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_UNCOMPRESS_H +#define __ASM_PLAT_UNCOMPRESS_H + +/* + * Register includes are for when the MMU enabled; we need to define our + * own stuff here for pre-MMU use + */ +#define UARTDBG_BASE 0x80070000 +#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c]) + +/* + * This does not append a newline + */ +static void putc(char c) +{ + /* Wait for TX fifo empty */ + while ((UART(6) & (1<<7)) == 0) + continue; + + /* Write byte */ + UART(0) = c; + + /* Wait for last bit to exit the UART */ + while (UART(6) & (1<<3)) + continue; +} + +static void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() + +#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h new file mode 100644 index 000000000000..541b880c1863 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#define VMALLOC_END (0xF0000000) diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c new file mode 100644 index 000000000000..cb3659096681 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/irq.c @@ -0,0 +1,59 @@ +/* + * Freescale STMP37XX/STMP378X common interrupt handling code + * + * Author: Vladislav Buzov <vbuzov@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/irq.h> +#include <linux/sysdev.h> + +#include <mach/stmp3xxx.h> +#include <mach/regs-icoll.h> + +void __init stmp3xxx_init_irq(struct irq_chip *chip) +{ + unsigned int i; + + /* Reset the interrupt controller */ + HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_CLKGATE); + udelay(10); + HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST); + udelay(10); + HW_ICOLL_CTRL_SET(BM_ICOLL_CTRL_SFTRST); + while (!(HW_ICOLL_CTRL_RD() & BM_ICOLL_CTRL_CLKGATE)) + continue; + HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_CLKGATE); + + /* Disable all interrupts initially */ + for (i = 0; i < NR_REAL_IRQS; i++) { + chip->mask(i); + set_irq_chip(i, chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } + + /* Ensure vector is cleared */ + HW_ICOLL_LEVELACK_WR(1); + HW_ICOLL_LEVELACK_WR(2); + HW_ICOLL_LEVELACK_WR(4); + HW_ICOLL_LEVELACK_WR(8); + + HW_ICOLL_VECTOR_WR(0); + /* Barrier */ + (void) HW_ICOLL_STAT_RD(); +} + diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c new file mode 100644 index 000000000000..9b28cc83f31c --- /dev/null +++ b/arch/arm/plat-stmp3xxx/pinmux.c @@ -0,0 +1,545 @@ +/* + * Freescale STMP378X/STMP378X Pin Multiplexing + * + * Author: Vladislav Buzov <vbuzov@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/sysdev.h> +#include <linux/string.h> +#include <linux/bitops.h> +#include <linux/sysdev.h> +#include <linux/irq.h> + +#include <mach/hardware.h> +#include <mach/regs-pinctrl.h> +#include <mach/pins.h> +#include <mach/pinmux.h> + +#define NR_BANKS ARRAY_SIZE(pinmux_banks) +static struct stmp3xxx_pinmux_bank pinmux_banks[] = { + [0] = { + .hw_muxsel = { + HW_PINCTRL_MUXSEL0_ADDR, + HW_PINCTRL_MUXSEL1_ADDR + }, + .hw_drive = { + HW_PINCTRL_DRIVE0_ADDR, + HW_PINCTRL_DRIVE1_ADDR, + HW_PINCTRL_DRIVE2_ADDR, + HW_PINCTRL_DRIVE3_ADDR + }, + .hw_pull = HW_PINCTRL_PULL0_ADDR, + .functions = { 0x0, 0x1, 0x2, 0x3 }, + .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, + + .hw_gpio_read = HW_PINCTRL_DIN0_ADDR, + .hw_gpio_set = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_SET, + .hw_gpio_clr = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_CLR, + .hw_gpio_doe = HW_PINCTRL_DOE0_ADDR, + .irq = IRQ_GPIO0, + + .pin2irq = HW_PINCTRL_PIN2IRQ0_ADDR, + .irqstat = HW_PINCTRL_IRQSTAT0_ADDR, + .irqlevel = HW_PINCTRL_IRQLEVEL0_ADDR, + .irqpolarity = HW_PINCTRL_IRQPOL0_ADDR, + .irqen = HW_PINCTRL_IRQEN0_ADDR, + }, + [1] = { + .hw_muxsel = { + HW_PINCTRL_MUXSEL2_ADDR, + HW_PINCTRL_MUXSEL3_ADDR + }, + .hw_drive = { + HW_PINCTRL_DRIVE4_ADDR, + HW_PINCTRL_DRIVE5_ADDR, + HW_PINCTRL_DRIVE6_ADDR, + HW_PINCTRL_DRIVE7_ADDR + }, + .hw_pull = HW_PINCTRL_PULL1_ADDR, + .functions = { 0x0, 0x1, 0x2, 0x3 }, + .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, + + .hw_gpio_read = HW_PINCTRL_DIN1_ADDR, + .hw_gpio_set = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_SET, + .hw_gpio_clr = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_CLR, + .hw_gpio_doe = HW_PINCTRL_DOE1_ADDR, + .irq = IRQ_GPIO1, + + .pin2irq = HW_PINCTRL_PIN2IRQ1_ADDR, + .irqstat = HW_PINCTRL_IRQSTAT1_ADDR, + .irqlevel = HW_PINCTRL_IRQLEVEL1_ADDR, + .irqpolarity = HW_PINCTRL_IRQPOL1_ADDR, + .irqen = HW_PINCTRL_IRQEN1_ADDR, + }, + [2] = { + .hw_muxsel = { + HW_PINCTRL_MUXSEL4_ADDR, + HW_PINCTRL_MUXSEL5_ADDR, + }, + .hw_drive = { + HW_PINCTRL_DRIVE8_ADDR, + HW_PINCTRL_DRIVE9_ADDR, + HW_PINCTRL_DRIVE10_ADDR, + HW_PINCTRL_DRIVE11_ADDR, + }, + .hw_pull = HW_PINCTRL_PULL2_ADDR, + .functions = { 0x0, 0x1, 0x2, 0x3 }, + .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 }, + + .hw_gpio_read = HW_PINCTRL_DIN2_ADDR, + .hw_gpio_set = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_SET, + .hw_gpio_clr = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_CLR, + .hw_gpio_doe = HW_PINCTRL_DOE2_ADDR, + .irq = IRQ_GPIO2, + + .pin2irq = HW_PINCTRL_PIN2IRQ2_ADDR, + .irqstat = HW_PINCTRL_IRQSTAT2_ADDR, + .irqlevel = HW_PINCTRL_IRQLEVEL2_ADDR, + .irqpolarity = HW_PINCTRL_IRQPOL2_ADDR, + .irqen = HW_PINCTRL_IRQEN2_ADDR, + }, + [3] = { + .hw_muxsel = { + HW_PINCTRL_MUXSEL6_ADDR, + HW_PINCTRL_MUXSEL7_ADDR, + }, + .hw_drive = { + HW_PINCTRL_DRIVE12_ADDR, + HW_PINCTRL_DRIVE13_ADDR, + HW_PINCTRL_DRIVE14_ADDR, + NULL, + }, + .hw_pull = HW_PINCTRL_PULL3_ADDR, + .functions = {0x0, 0x1, 0x2, 0x3}, + .strengths = {0x0, 0x1, 0x2, 0x3, 0xff}, + }, +}; + +static inline struct stmp3xxx_pinmux_bank * +stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin) +{ + unsigned b, p; + + b = STMP3XXX_PINID_TO_BANK(id); + p = STMP3XXX_PINID_TO_PINNUM(id); + BUG_ON(b >= NR_BANKS); + if (bank) + *bank = b; + if (pin) + *pin = p; + return &pinmux_banks[b]; +} + +/* Check if requested pin is owned by caller */ +static int stmp3xxx_check_pin(unsigned id, const char *label) +{ + unsigned pin; + struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin); + + if (!test_bit(pin, &pm->pin_map)) { + printk(KERN_WARNING + "%s: Accessing free pin %x, caller %s\n", + __func__, id, label); + + return -EINVAL; + } + + if (label && pm->pin_labels[pin] && + strcmp(label, pm->pin_labels[pin])) { + printk(KERN_WARNING + "%s: Wrong pin owner %x, caller %s owner %s\n", + __func__, id, label, pm->pin_labels[pin]); + + return -EINVAL; + } + return 0; +} + +void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, + const char *label) +{ + struct stmp3xxx_pinmux_bank *pbank; + void __iomem *hwdrive; + u32 shift, val; + u32 bank, pin; + + pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); + pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label, + bank, pin, strength); + + hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM]; + shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN; + val = pbank->strengths[strength]; + if (val == 0xff) { + printk(KERN_WARNING + "%s: strength is not supported for bank %d, caller %s", + __func__, bank, label); + return; + } + + if (stmp3xxx_check_pin(id, label)) + return; + + pr_debug("%s: writing 0x%x to 0x%p register\n", __func__, + val << shift, hwdrive); + __raw_writel(HW_DRIVE_PINDRV_MASK << shift, hwdrive + HW_STMP3xxx_CLR); + __raw_writel(val << shift, hwdrive + HW_STMP3xxx_SET); +} + +void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, + const char *label) +{ + struct stmp3xxx_pinmux_bank *pbank; + void __iomem *hwdrive; + u32 shift; + u32 bank, pin; + + pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); + pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label, + bank, pin, voltage); + + hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM]; + shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN; + + if (stmp3xxx_check_pin(id, label)) + return; + + pr_debug("%s: changing 0x%x bit in 0x%p register\n", + __func__, HW_DRIVE_PINV_MASK << shift, hwdrive); + if (voltage == PIN_1_8V) + __raw_writel(HW_DRIVE_PINV_MASK << shift, + hwdrive + HW_STMP3xxx_CLR); + else + __raw_writel(HW_DRIVE_PINV_MASK << shift, + hwdrive + HW_STMP3xxx_SET); +} + +void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label) +{ + struct stmp3xxx_pinmux_bank *pbank; + void __iomem *hwpull; + u32 bank, pin; + + pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); + pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label, + bank, pin, enable); + + hwpull = pbank->hw_pull; + + if (stmp3xxx_check_pin(id, label)) + return; + + pr_debug("%s: changing 0x%x bit in 0x%p register\n", + __func__, 1 << pin, hwpull); + __raw_writel(1 << pin, + hwpull + (enable ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); +} + +int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label) +{ + struct stmp3xxx_pinmux_bank *pbank; + u32 bank, pin; + int ret = 0; + + pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); + pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label, + bank, pin, fun); + + if (test_bit(pin, &pbank->pin_map)) { + printk(KERN_WARNING + "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n", + __func__, bank, pin, label, pbank->pin_labels[pin]); + return -EBUSY; + } + + set_bit(pin, &pbank->pin_map); + pbank->pin_labels[pin] = label; + + stmp3xxx_set_pin_type(id, fun); + + return ret; +} + +void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun) +{ + struct stmp3xxx_pinmux_bank *pbank; + void __iomem *hwmux; + u32 shift, val; + u32 bank, pin; + + pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); + + hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM]; + shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; + + val = pbank->functions[fun]; + shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; + pr_debug("%s: writing 0x%x to 0x%p register\n", + __func__, val << shift, hwmux); + __raw_writel(HW_MUXSEL_PINFUN_MASK << shift, hwmux + HW_STMP3xxx_CLR); + __raw_writel(val << shift, hwmux + HW_STMP3xxx_SET); +} + +void stmp3xxx_release_pin(unsigned id, const char *label) +{ + struct stmp3xxx_pinmux_bank *pbank; + u32 bank, pin; + + pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); + pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin); + + if (stmp3xxx_check_pin(id, label)) + return; + + clear_bit(pin, &pbank->pin_map); + pbank->pin_labels[pin] = NULL; +} + +int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label) +{ + struct pin_desc *pin; + int p; + int err = 0; + + /* Allocate and configure pins */ + for (p = 0; p < pin_group->nr_pins; p++) { + pr_debug("%s: #%d\n", __func__, p); + pin = &pin_group->pins[p]; + + err = stmp3xxx_request_pin(pin->id, pin->fun, label); + if (err) + goto out_err; + + stmp3xxx_pin_strength(pin->id, pin->strength, label); + stmp3xxx_pin_voltage(pin->id, pin->voltage, label); + stmp3xxx_pin_pullup(pin->id, pin->pullup, label); + } + + return 0; + +out_err: + /* Release allocated pins in case of error */ + while (--p >= 0) { + pr_debug("%s: releasing #%d\n", __func__, p); + stmp3xxx_release_pin(pin_group->pins[p].id, label); + } + return err; +} +EXPORT_SYMBOL(stmp3xxx_request_pin_group); + +void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label) +{ + struct pin_desc *pin; + int p; + + for (p = 0; p < pin_group->nr_pins; p++) { + pin = &pin_group->pins[p]; + stmp3xxx_release_pin(pin->id, label); + } +} +EXPORT_SYMBOL(stmp3xxx_release_pin_group); + +static int stmp3xxx_irq_to_gpio(int irq, + struct stmp3xxx_pinmux_bank **bank, unsigned *gpio) +{ + struct stmp3xxx_pinmux_bank *pm; + + for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++) + if (pm->virq <= irq && irq < pm->virq + 32) { + *bank = pm; + *gpio = irq - pm->virq; + return 0; + } + return -ENOENT; +} + +static int stmp3xxx_set_irqtype(unsigned irq, unsigned type) +{ + struct stmp3xxx_pinmux_bank *pm; + unsigned gpio; + int l, p; + + stmp3xxx_irq_to_gpio(irq, &pm, &gpio); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + l = 0; p = 1; break; + case IRQ_TYPE_EDGE_FALLING: + l = 0; p = 0; break; + case IRQ_TYPE_LEVEL_HIGH: + l = 1; p = 1; break; + case IRQ_TYPE_LEVEL_LOW: + l = 1; p = 0; break; + default: + pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", + __func__, type); + return -ENXIO; + } + __raw_writel(1 << gpio, + pm->irqlevel + (l ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); + __raw_writel(1 << gpio, + pm->irqpolarity + (p ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); + return 0; +} + +static void stmp3xxx_pin_ack_irq(unsigned irq) +{ + u32 stat; + struct stmp3xxx_pinmux_bank *pm; + unsigned gpio; + + stmp3xxx_irq_to_gpio(irq, &pm, &gpio); + stat = __raw_readl(pm->irqstat) & (1<<gpio); + __raw_writel(stat, pm->irqstat + HW_STMP3xxx_CLR); +} + +static void stmp3xxx_pin_mask_irq(unsigned irq) +{ + struct stmp3xxx_pinmux_bank *pm; + unsigned gpio; + + stmp3xxx_irq_to_gpio(irq, &pm, &gpio); + __raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_CLR); + __raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_CLR); +} + +static void stmp3xxx_pin_unmask_irq(unsigned irq) +{ + struct stmp3xxx_pinmux_bank *pm; + unsigned gpio; + + stmp3xxx_irq_to_gpio(irq, &pm, &gpio); + __raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_SET); + __raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_SET); +} + +static inline +struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip) +{ + return container_of(chip, struct stmp3xxx_pinmux_bank, chip); +} + +static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); + return pm->virq + offset; +} + +static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); + unsigned v; + + v = __raw_readl(pm->hw_gpio_read) & (1 << offset); + return v ? 1 : 0; +} + +static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v) +{ + struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); + + __raw_writel(1 << offset, v ? pm->hw_gpio_set : pm->hw_gpio_clr); +} + +static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v) +{ + struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); + + __raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_SET); + stmp3xxx_gpio_set(chip, offset, v); + return 0; +} + +static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset) +{ + struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); + + __raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_CLR); + return 0; +} + +static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio"); +} + +static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + stmp3xxx_release_pin(chip->base + offset, "gpio"); +} + +static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) +{ + struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq); + int gpio_irq = pm->virq; + u32 stat = __raw_readl(pm->irqstat); + + while (stat) { + if (stat & 1) + irq_desc[gpio_irq].handle_irq(gpio_irq, + &irq_desc[gpio_irq]); + gpio_irq++; + stat >>= 1; + } +} + +static struct irq_chip gpio_irq_chip = { + .ack = stmp3xxx_pin_ack_irq, + .mask = stmp3xxx_pin_mask_irq, + .unmask = stmp3xxx_pin_unmask_irq, + .set_type = stmp3xxx_set_irqtype, +}; + +int __init stmp3xxx_pinmux_init(int virtual_irq_start) +{ + int b, r = 0; + struct stmp3xxx_pinmux_bank *pm; + int virq; + + for (b = 0; b < 3; b++) { + /* only banks 0,1,2 are allowed to GPIO */ + pm = pinmux_banks + b; + pm->chip.base = 32 * b; + pm->chip.ngpio = 32; + pm->chip.owner = THIS_MODULE; + pm->chip.can_sleep = 1; + pm->chip.exported = 1; + pm->chip.to_irq = stmp3xxx_gpio_to_irq; + pm->chip.direction_input = stmp3xxx_gpio_input; + pm->chip.direction_output = stmp3xxx_gpio_output; + pm->chip.get = stmp3xxx_gpio_get; + pm->chip.set = stmp3xxx_gpio_set; + pm->chip.request = stmp3xxx_gpio_request; + pm->chip.free = stmp3xxx_gpio_free; + pm->virq = virtual_irq_start + b * 32; + + for (virq = pm->virq; virq < pm->virq; virq++) { + gpio_irq_chip.mask(virq); + set_irq_chip(virq, &gpio_irq_chip); + set_irq_handler(virq, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); + } + r = gpiochip_add(&pm->chip); + if (r < 0) + break; + set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq); + set_irq_data(pm->irq, pm); + } + return r; +} + +MODULE_AUTHOR("Vladislav Buzov"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c new file mode 100644 index 000000000000..c916068f0cab --- /dev/null +++ b/arch/arm/plat-stmp3xxx/timer.c @@ -0,0 +1,172 @@ +/* + * System timer for Freescale STMP37XX/STMP378X + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/interrupt.h> + +#include <asm/mach/time.h> +#include <mach/stmp3xxx.h> +#include <mach/regs-timrot.h> + +static irqreturn_t +stmp3xxx_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + + if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) { + HW_TIMROT_TIMCTRLn_CLR(0, (1<<15)); + c->event_handler(c); + } else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) { + HW_TIMROT_TIMCTRLn_CLR(1, (1<<15)); + HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN); + HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); + } + + return IRQ_HANDLED; +} + +static cycle_t stmp3xxx_clock_read(void) +{ + return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16); +} + +static int +stmp3xxx_timrot_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */ + return 0; +} + +static void +stmp3xxx_timrot_set_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ +} + +static struct clock_event_device ckevt_timrot = { + .name = "timrot", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = stmp3xxx_timrot_set_next_event, + .set_mode = stmp3xxx_timrot_set_mode, +}; + +static struct clocksource cksrc_stmp3xxx = { + .name = "cksrc_stmp3xxx", + .rating = 250, + .read = stmp3xxx_clock_read, + .mask = CLOCKSOURCE_MASK(16), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static struct irqaction stmp3xxx_timer_irq = { + .name = "stmp3xxx_timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = stmp3xxx_timer_interrupt, + .dev_id = &ckevt_timrot, +}; + + +/* + * Set up timer interrupt, and return the current time in seconds. + */ +static void __init stmp3xxx_init_timer(void) +{ + cksrc_stmp3xxx.mult = clocksource_hz2mult(CLOCK_TICK_RATE, + cksrc_stmp3xxx.shift); + ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, + ckevt_timrot.shift); + ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); + ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); + ckevt_timrot.cpumask = cpumask_of(0); + + HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST | + BM_TIMROT_ROTCTRL_CLKGATE); + HW_TIMROT_TIMCOUNTn_WR(0, 0); + HW_TIMROT_TIMCOUNTn_WR(1, 0); + + HW_TIMROT_TIMCTRLn_WR(0, + (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ + BF_TIMROT_TIMCTRLn_PRESCALE(0) | + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN)); + HW_TIMROT_TIMCTRLn_WR(1, + (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ + BF_TIMROT_TIMCTRLn_PRESCALE(0) | + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE)); + + HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1); + HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */ + + setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); + + clocksource_register(&cksrc_stmp3xxx); + clockevents_register_device(&ckevt_timrot); +} + +#ifdef CONFIG_PM + +void stmp3xxx_suspend_timer(void) +{ + HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN); + HW_TIMROT_TIMCTRLn_CLR(0, (1<<15)); + HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE); +} + +void stmp3xxx_resume_timer(void) +{ + HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST | + BM_TIMROT_ROTCTRL_CLKGATE); + + + HW_TIMROT_TIMCTRLn_WR(0, + (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ + BF_TIMROT_TIMCTRLn_PRESCALE(0) | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN)); + HW_TIMROT_TIMCTRLn_WR(1, + (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ + BF_TIMROT_TIMCTRLn_PRESCALE(0) | + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE)); + + HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1); + HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */ +} + +#else + +#define stmp3xxx_suspend_timer NULL +#define stmp3xxx_resume_timer NULL + +#endif /* CONFIG_PM */ + +struct sys_timer stmp3xxx_timer = { + .init = stmp3xxx_init_timer, + .suspend = stmp3xxx_suspend_timer, + .resume = stmp3xxx_resume_timer, +}; diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile index 0b97e14f73f6..c21a3290d542 100644 --- a/arch/avr32/Makefile +++ b/arch/avr32/Makefile @@ -43,8 +43,6 @@ core-y += arch/avr32/mm/ drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/ libs-y += arch/avr32/lib/ -CLEAN_FILES += include/asm-avr32/.arch include/asm-avr32/arch - BOOT_TARGETS := vmlinux.elf vmlinux.bin uImage uImage.srec .PHONY: $(BOOT_TARGETS) install diff --git a/arch/avr32/boards/merisc/setup.c b/arch/avr32/boards/merisc/setup.c index 20b300cf105a..623b077594fc 100644 --- a/arch/avr32/boards/merisc/setup.c +++ b/arch/avr32/boards/merisc/setup.c @@ -94,9 +94,10 @@ static struct spi_board_info __initdata spi0_board_info[] = { static struct mci_platform_data __initdata mci0_data = { .slot[0] = { - .bus_width = 4, - .detect_pin = GPIO_PIN_PE(19), - .wp_pin = GPIO_PIN_PE(20), + .bus_width = 4, + .detect_pin = GPIO_PIN_PE(19), + .wp_pin = GPIO_PIN_PE(20), + .detect_is_active_high = true, }, }; diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index d54c8283825c..09e1c7a32b44 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -128,10 +128,6 @@ KBUILD_CFLAGS += -Iarch/$(ARCH)/mach-$(MACHINE)/include KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) -CLEAN_FILES += \ - arch/$(ARCH)/include/asm/asm-offsets.h \ - arch/$(ARCH)/kernel/asm-offsets.s \ - archclean: $(Q)$(MAKE) $(clean)=$(boot) diff --git a/arch/cris/Makefile b/arch/cris/Makefile index 3662cfb7b61d..71e17d3eeddb 100644 --- a/arch/cris/Makefile +++ b/arch/cris/Makefile @@ -70,7 +70,7 @@ SRC_ARCH = $(srctree)/arch/cris # cris object files path OBJ_ARCH = $(objtree)/arch/cris -boot := arch/cris/$(SARCH)/boot +boot := arch/cris/boot MACHINE := arch/cris/$(SARCH) all: zImage @@ -81,15 +81,15 @@ zImage Image: vmlinux archprepare: archclean: - $(Q)if [ -e arch/cris/$(SARCH)/boot ]; then \ - $(MAKE) $(clean)=arch/cris/$(SARCH)/boot; \ + $(Q)if [ -e arch/cris/boot ]; then \ + $(MAKE) $(clean)=arch/cris/boot; \ fi CLEAN_FILES += \ - $(MACHINE)/boot/zImage \ - $(MACHINE)/boot/compressed/decompress.bin \ - $(MACHINE)/boot/compressed/piggy.gz \ - $(MACHINE)/boot/rescue/rescue.bin + $(boot)/zImage \ + $(boot)/compressed/decompress.bin \ + $(boot)/compressed/piggy.gz \ + $(boot)/rescue/rescue.bin # MRPROPER_FILES += diff --git a/arch/cris/arch-v10/boot/Makefile b/arch/cris/arch-v10/boot/Makefile deleted file mode 100644 index 217203014433..000000000000 --- a/arch/cris/arch-v10/boot/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# arch/cris/arch-v10/boot/Makefile -# - -OBJCOPYFLAGS = -O binary --remove-section=.bss - -subdir- := compressed rescue -targets := Image - -$(obj)/Image: vmlinux FORCE - $(call if_changed,objcopy) - @echo ' Kernel: $@ is ready' - -$(obj)/compressed/vmlinux: $(obj)/Image FORCE - $(Q)$(MAKE) $(build)=$(obj)/compressed $@ - $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin - -$(obj)/zImage: $(obj)/compressed/vmlinux - @cp $< $@ - @echo ' Kernel: $@ is ready' diff --git a/arch/cris/arch-v10/boot/compressed/README b/arch/cris/arch-v10/boot/compressed/README deleted file mode 100644 index 48b3db9924b9..000000000000 --- a/arch/cris/arch-v10/boot/compressed/README +++ /dev/null @@ -1,25 +0,0 @@ -Creation of the self-extracting compressed kernel image (vmlinuz) ------------------------------------------------------------------ -$Id: README,v 1.1 2001/12/17 13:59:27 bjornw Exp $ - -This can be slightly confusing because it's a process with many steps. - -The kernel object built by the arch/etrax100/Makefile, vmlinux, is split -by that makefile into text and data binary files, vmlinux.text and -vmlinux.data. - -Those files together with a ROM filesystem can be catted together and -burned into a flash or executed directly at the DRAM origin. - -They can also be catted together and compressed with gzip, which is what -happens in this makefile. Together they make up piggy.img. - -The decompressor is built into the file decompress.o. It is turned into -the binary file decompress.bin, which is catted together with piggy.img -into the file vmlinuz. It can be executed in an arbitrary place in flash. - -Be careful - it assumes some things about free locations in DRAM. It -assumes the DRAM starts at 0x40000000 and that it is at least 8 MB, -so it puts its code at 0x40700000, and initial stack at 0x40800000. - --Bjorn diff --git a/arch/cris/arch-v10/boot/compressed/misc.c b/arch/cris/arch-v10/boot/compressed/misc.c deleted file mode 100644 index a4db1507d3b1..000000000000 --- a/arch/cris/arch-v10/boot/compressed/misc.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * misc.c - * - * This is a collection of several routines from gzip-1.0.3 - * adapted for Linux. - * - * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 - * puts by Nick Holloway 1993, better puts by Martin Mares 1995 - * adaptation for Linux/CRIS Axis Communications AB, 1999 - * - */ - -/* where the piggybacked kernel image expects itself to live. - * it is the same address we use when we network load an uncompressed - * image into DRAM, and it is the address the kernel is linked to live - * at by vmlinux.lds.S - */ - -#define KERNEL_LOAD_ADR 0x40004000 - - -#include <linux/types.h> -#include <arch/svinto.h> - -/* - * gzip declarations - */ - -#define OF(args) args -#define STATIC static - -void *memset(void *s, int c, size_t n); -void *memcpy(void *__dest, __const void *__src, size_t __n); - -#define memzero(s, n) memset((s), 0, (n)) - -typedef unsigned char uch; -typedef unsigned short ush; -typedef unsigned long ulg; - -#define WSIZE 0x8000 /* Window size must be at least 32k, */ - /* and a power of two */ - -static uch *inbuf; /* input buffer */ -static uch window[WSIZE]; /* Sliding window buffer */ - -unsigned inptr = 0; /* index of next byte to be processed in inbuf - * After decompression it will contain the - * compressed size, and head.S will read it. - */ - -static unsigned outcnt = 0; /* bytes in output buffer */ - -/* gzip flag byte */ -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */ -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ -#define COMMENT 0x10 /* bit 4 set: file comment present */ -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ -#define RESERVED 0xC0 /* bit 6,7: reserved */ - -#define get_byte() (inbuf[inptr++]) - -/* Diagnostic functions */ -#ifdef DEBUG -# define Assert(cond, msg) do { \ - if (!(cond)) \ - error(msg); \ - } while (0) -# define Trace(x) fprintf x -# define Tracev(x) do { \ - if (verbose) \ - fprintf x; \ - } while (0) -# define Tracevv(x) do { \ - if (verbose > 1) \ - fprintf x; \ - } while (0) -# define Tracec(c, x) do { \ - if (verbose && (c)) \ - fprintf x; \ - } while (0) -# define Tracecv(c, x) do { \ - if (verbose > 1 && (c)) \ - fprintf x; \ - } while (0) -#else -# define Assert(cond, msg) -# define Trace(x) -# define Tracev(x) -# define Tracevv(x) -# define Tracec(c, x) -# define Tracecv(c, x) -#endif - -static void flush_window(void); -static void error(char *m); - -extern char *input_data; /* lives in head.S */ - -static long bytes_out = 0; -static uch *output_data; -static unsigned long output_ptr = 0; -static void puts(const char *); - -/* the "heap" is put directly after the BSS ends, at end */ - -extern int _end; -static long free_mem_ptr = (long)&_end; -static long free_mem_end_ptr; - -#include "../../../../../lib/inflate.c" - -/* decompressor info and error messages to serial console */ - -static void -puts(const char *s) -{ -#ifndef CONFIG_ETRAX_DEBUG_PORT_NULL - while (*s) { -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - while (!(*R_SERIAL0_STATUS & (1 << 5))) ; - *R_SERIAL0_TR_DATA = *s++; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT1 - while (!(*R_SERIAL1_STATUS & (1 << 5))) ; - *R_SERIAL1_TR_DATA = *s++; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT2 - while (!(*R_SERIAL2_STATUS & (1 << 5))) ; - *R_SERIAL2_TR_DATA = *s++; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT3 - while (!(*R_SERIAL3_STATUS & (1 << 5))) ; - *R_SERIAL3_TR_DATA = *s++; -#endif - } -#endif -} - -void *memset(void *s, int c, size_t n) -{ - int i; - char *ss = (char *)s; - - for (i = 0; i < n; i++) - ss[i] = c; - - return s; -} - -void *memcpy(void *__dest, __const void *__src, size_t __n) -{ - int i; - char *d = (char *)__dest, *s = (char *)__src; - - for (i = 0; i < __n; i++) - d[i] = s[i]; - - return __dest; -} - -/* =========================================================================== - * Write the output window window[0..outcnt-1] and update crc and bytes_out. - * (Used for the decompressed data only.) - */ - -static void flush_window(void) -{ - ulg c = crc; /* temporary variable */ - unsigned n; - uch *in, *out, ch; - - in = window; - out = &output_data[output_ptr]; - for (n = 0; n < outcnt; n++) { - ch = *out = *in; - out++; - in++; - c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8); - } - crc = c; - bytes_out += (ulg)outcnt; - output_ptr += (ulg)outcnt; - outcnt = 0; -} - -static void error(char *x) -{ - puts("\n\n"); - puts(x); - puts("\n\n -- System halted\n"); - - while (1); /* Halt */ -} - -void setup_normal_output_buffer(void) -{ - output_data = (char *)KERNEL_LOAD_ADR; -} - -void decompress_kernel(void) -{ - char revision; - - /* input_data is set in head.S */ - inbuf = input_data; - -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - *R_SERIAL0_XOFF = 0; - *R_SERIAL0_BAUD = 0x99; - *R_SERIAL0_TR_CTRL = 0x40; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT1 - *R_SERIAL1_XOFF = 0; - *R_SERIAL1_BAUD = 0x99; - *R_SERIAL1_TR_CTRL = 0x40; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT2 - *R_GEN_CONFIG = 0x08; - *R_SERIAL2_XOFF = 0; - *R_SERIAL2_BAUD = 0x99; - *R_SERIAL2_TR_CTRL = 0x40; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT3 - *R_GEN_CONFIG = 0x100; - *R_SERIAL3_XOFF = 0; - *R_SERIAL3_BAUD = 0x99; - *R_SERIAL3_TR_CTRL = 0x40; -#endif - - setup_normal_output_buffer(); - - makecrc(); - - __asm__ volatile ("move $vr,%0" : "=rm" (revision)); - if (revision < 10) { - puts("You need an ETRAX 100LX to run linux 2.6\n"); - while (1); - } - - puts("Uncompressing Linux...\n"); - gunzip(); - puts("Done. Now booting the kernel.\n"); -} diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S index 72f5cd319b97..2c18d08cd913 100644 --- a/arch/cris/arch-v10/kernel/entry.S +++ b/arch/cris/arch-v10/kernel/entry.S @@ -536,10 +536,10 @@ multiple_interrupt: movem $r13, [$sp] push $r10 ; push orig_r10 clear.d [$sp=$sp-4] ; frametype == 0, normal frame - + move.d $sp, $r10 jsr do_multiple_IRQ - + jump ret_from_intr do_sigtrap: @@ -585,7 +585,7 @@ _ugdb_handle_breakpoint: pop $r0 ; Restore r0. ba do_sigtrap ; SIGTRAP the offending process. pop $dccr ; Restore dccr in delay slot. - + .global kernel_execve kernel_execve: move.d __NR_execve, $r9 @@ -929,6 +929,14 @@ sys_call_table: .long sys_fallocate .long sys_timerfd_settime /* 325 */ .long sys_timerfd_gettime + .long sys_signalfd4 + .long sys_eventfd2 + .long sys_epoll_create1 + .long sys_dup3 /* 330 */ + .long sys_pipe2 + .long sys_inotify_init1 + .long sys_preadv + .long sys_pwritev /* * NOTE!! This doesn't have to be exact - we just have diff --git a/arch/cris/arch-v32/boot/compressed/Makefile b/arch/cris/arch-v32/boot/compressed/Makefile deleted file mode 100644 index e176b8b69d92..000000000000 --- a/arch/cris/arch-v32/boot/compressed/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# arch/cris/arch-v32/boot/compressed/Makefile -# - -asflags-y += -I$(srctree)/include/asm/mach/ -I$(srctree)/include/asm/arch -ccflags-y += -O2 -I$(srctree)/include/asm/mach/ -I$(srctree)/include/asm/arch -ldflags-y += -T$(srctree)/$(src)/decompress.lds -OBJECTS = $(obj)/head.o $(obj)/misc.o -OBJCOPYFLAGS = -O binary --remove-section=.bss - -quiet_cmd_image = BUILD $@ -cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@ - -targets := vmlinux piggy.gz decompress.o decompress.bin - -$(obj)/decompress.o: $(OBJECTS) FORCE - $(call if_changed,ld) - -$(obj)/decompress.bin: $(obj)/decompress.o FORCE - $(call if_changed,objcopy) - -$(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE - $(call if_changed,image) - -$(obj)/piggy.gz: $(obj)/../Image FORCE - $(call if_changed,gzip) diff --git a/arch/cris/arch-v32/boot/rescue/Makefile b/arch/cris/arch-v32/boot/rescue/Makefile deleted file mode 100644 index 566aac663a38..000000000000 --- a/arch/cris/arch-v32/boot/rescue/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# Makefile for rescue (bootstrap) code -# - -CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE) -ccflags-y += -O2 -I $(srctree)/include/asm/arch/mach/ \ - -I $(srctree)/include/asm/arch -asflags-y += -I $(srctree)/include/asm/arch/mach/ -I $(srctree)/include/asm/arch -LD = gcc-cris -mlinux -march=v32 -nostdlib -ldflags-y += -T $(srctree)/$(src)/rescue.lds -LDPOSTFLAGS = -lgcc -OBJCOPYFLAGS = -O binary --remove-section=.bss -obj-$(CONFIG_ETRAX_AXISFLASHMAP) = head.o -OBJECT := $(obj)/head.o - -targets := rescue.o rescue.bin - -quiet_cmd_ldlibgcc = LD $@ -cmd_ldlibgcc = $(LD) $(LDFLAGS) $(filter-out FORCE,$^) $(LDPOSTFLAGS) -o $@ - -$(obj)/rescue.o: $(OBJECTS) FORCE - $(call if_changed,ldlibgcc) - -$(obj)/rescue.bin: $(obj)/rescue.o FORCE - $(call if_changed,objcopy) - cp -p $(obj)/rescue.bin $(objtree) diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c index 7a87bc0ae2e8..97357cfd17bb 100644 --- a/arch/cris/arch-v32/drivers/mach-a3/gpio.c +++ b/arch/cris/arch-v32/drivers/mach-a3/gpio.c @@ -681,7 +681,7 @@ static int virtual_gpio_ioctl(struct file *file, unsigned int cmd, shadow |= ~readl(dir_oe[priv->minor]) | (arg & changeable_bits[priv->minor]); i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); - spin_lock_irqrestore(&gpio_lock, flags); + spin_unlock_irqrestore(&gpio_lock, flags); break; case IO_CLRBITS: spin_lock_irqsave(&gpio_lock, flags); @@ -690,7 +690,7 @@ static int virtual_gpio_ioctl(struct file *file, unsigned int cmd, shadow |= ~readl(dir_oe[priv->minor]) & ~(arg & changeable_bits[priv->minor]); i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); - spin_lock_irqrestore(&gpio_lock, flags); + spin_unlock_irqrestore(&gpio_lock, flags); break; case IO_HIGHALARM: /* Set alarm when bits with 1 in arg go high. */ diff --git a/arch/cris/arch-v32/kernel/Makefile b/arch/cris/arch-v32/kernel/Makefile index 993d987b0078..40358355d0cb 100644 --- a/arch/cris/arch-v32/kernel/Makefile +++ b/arch/cris/arch-v32/kernel/Makefile @@ -9,8 +9,6 @@ obj-y := entry.o traps.o irq.o debugport.o \ process.o ptrace.o setup.o signal.o traps.o time.o \ cache.o cacheflush.o -obj-$(CONFIG_ETRAXFS_SIM) += vcs_hook.o - obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S index 5e674c8f7c51..435b9671bd4b 100644 --- a/arch/cris/arch-v32/kernel/entry.S +++ b/arch/cris/arch-v32/kernel/entry.S @@ -852,6 +852,14 @@ sys_call_table: .long sys_fallocate .long sys_timerfd_settime /* 325 */ .long sys_timerfd_gettime + .long sys_signalfd4 + .long sys_eventfd2 + .long sys_epoll_create1 + .long sys_dup3 /* 330 */ + .long sys_pipe2 + .long sys_inotify_init1 + .long sys_preadv + .long sys_pwritev /* * NOTE!! This doesn't have to be exact - we just have diff --git a/arch/cris/arch-v10/boot/.gitignore b/arch/cris/boot/.gitignore index 171a0853caf8..171a0853caf8 100644 --- a/arch/cris/arch-v10/boot/.gitignore +++ b/arch/cris/boot/.gitignore diff --git a/arch/cris/arch-v32/boot/Makefile b/arch/cris/boot/Makefile index 99896ad60b30..144f3afa0119 100644 --- a/arch/cris/arch-v32/boot/Makefile +++ b/arch/cris/boot/Makefile @@ -1,8 +1,12 @@ # -# arch/cris/arch-v32/boot/Makefile +# arch/cris/boot/Makefile # -OBJCOPYFLAGS = -O binary -R .note -R .comment +objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment +objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss + +OBJCOPYFLAGS = -O binary $(objcopyflags-y) + subdir- := compressed rescue targets := Image diff --git a/arch/cris/arch-v10/boot/compressed/Makefile b/arch/cris/boot/compressed/Makefile index 6fe0ffaf3be6..8fe9338c1775 100644 --- a/arch/cris/arch-v10/boot/compressed/Makefile +++ b/arch/cris/boot/compressed/Makefile @@ -1,11 +1,23 @@ # -# arch/cris/arch-v10/boot/compressed/Makefile +# arch/cris/boot/compressed/Makefile # asflags-y += $(LINUXINCLUDE) ccflags-y += -O2 $(LINUXINCLUDE) -ldflags-y += -T $(srctree)/$(src)/decompress.lds -OBJECTS = $(obj)/head.o $(obj)/misc.o + +# asflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/mach \ +# -I$(srctree)/include/asm/arch +# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -O2 -I$(srctree)/include/asm/mach +# -I$(srctree)/include/asm/arch + +arch-$(CONFIG_ETRAX_ARCH_V10) = v10 +arch-$(CONFIG_ETRAX_ARCH_V32) = v32 + +ldflags-y += -T $(srctree)/$(src)/decompress_$(arch-y).lds + +OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o +OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o +OBJECTS= $(OBJECTS-y) $(obj)/misc.o OBJCOPYFLAGS = -O binary --remove-section=.bss quiet_cmd_image = BUILD $@ @@ -24,4 +36,3 @@ $(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE $(obj)/piggy.gz: $(obj)/../Image FORCE $(call if_changed,gzip) - diff --git a/arch/cris/arch-v32/boot/compressed/README b/arch/cris/boot/compressed/README index 182c5d75784b..182c5d75784b 100644 --- a/arch/cris/arch-v32/boot/compressed/README +++ b/arch/cris/boot/compressed/README diff --git a/arch/cris/arch-v10/boot/compressed/decompress.lds b/arch/cris/boot/compressed/decompress_v10.lds index e80f4594d543..e80f4594d543 100644 --- a/arch/cris/arch-v10/boot/compressed/decompress.lds +++ b/arch/cris/boot/compressed/decompress_v10.lds diff --git a/arch/cris/arch-v32/boot/compressed/decompress.lds b/arch/cris/boot/compressed/decompress_v32.lds index 3c837feca3ac..3c837feca3ac 100644 --- a/arch/cris/arch-v32/boot/compressed/decompress.lds +++ b/arch/cris/boot/compressed/decompress_v32.lds diff --git a/arch/cris/arch-v10/boot/compressed/head.S b/arch/cris/boot/compressed/head_v10.S index 0bb4dcc29254..9edb8ade7e1f 100644 --- a/arch/cris/arch-v10/boot/compressed/head.S +++ b/arch/cris/boot/compressed/head_v10.S @@ -30,7 +30,7 @@ beq dram_init_finished nop -#include "../../lib/dram_init.S" +#include "../../arch-v10/lib/dram_init.S" dram_init_finished: @@ -123,4 +123,4 @@ _cmd_line_magic: .dword 0 _cmd_line_addr: .dword 0 -#include "../../lib/hw_settings.S" +#include "../../arch-v10/lib/hw_settings.S" diff --git a/arch/cris/arch-v32/boot/compressed/head.S b/arch/cris/boot/compressed/head_v32.S index a4a65c5c669e..f483005f3d48 100644 --- a/arch/cris/arch-v32/boot/compressed/head.S +++ b/arch/cris/boot/compressed/head_v32.S @@ -17,7 +17,7 @@ .globl input_data .text -_start: +start: di ;; Start clocks for used blocks. @@ -29,9 +29,9 @@ _start: nop #if defined CONFIG_ETRAXFS -#include "../../mach-fs/dram_init.S" +#include "../../arch-v32/mach-fs/dram_init.S" #elif defined CONFIG_CRIS_MACH_ARTPEC3 -#include "../../mach-a3/dram_init.S" +#include "../../arch-v32/mach-a3/dram_init.S" #else #error Only ETRAXFS and ARTPEC-3 supported! #endif @@ -137,9 +137,9 @@ _boot_source: .dword 0 #if defined CONFIG_ETRAXFS -#include "../../mach-fs/hw_settings.S" +#include "../../arch-v32/mach-fs/hw_settings.S" #elif defined CONFIG_CRIS_MACH_ARTPEC3 -#include "../../mach-a3/hw_settings.S" +#include "../../arch-v32/mach-a3/hw_settings.S" #else #error Only ETRAXFS and ARTPEC-3 supported! #endif diff --git a/arch/cris/arch-v32/boot/compressed/misc.c b/arch/cris/boot/compressed/misc.c index 3595e16e82bc..47bc190ba6d4 100644 --- a/arch/cris/arch-v32/boot/compressed/misc.c +++ b/arch/cris/boot/compressed/misc.c @@ -18,8 +18,9 @@ #define KERNEL_LOAD_ADR 0x40004000 - #include <linux/types.h> + +#ifdef CONFIG_ETRAX_ARCH_V32 #include <hwregs/reg_rdwr.h> #include <hwregs/reg_map.h> #include <hwregs/ser_defs.h> @@ -27,6 +28,9 @@ #ifdef CONFIG_CRIS_MACH_ARTPEC3 #include <hwregs/clkgen_defs.h> #endif +#else +#include <arch/svinto.h> +#endif /* * gzip declarations @@ -35,12 +39,10 @@ #define OF(args) args #define STATIC static -void* memset(void* s, int c, size_t n); -void* memcpy(void* __dest, __const void* __src, - size_t __n); - -#define memzero(s, n) memset ((s), 0, (n)) +void *memset(void *s, int c, size_t n); +void *memcpy(void *__dest, __const void *__src, size_t __n); +#define memzero(s, n) memset((s), 0, (n)) typedef unsigned char uch; typedef unsigned short ush; @@ -68,27 +70,43 @@ static unsigned outcnt = 0; /* bytes in output buffer */ #define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ #define RESERVED 0xC0 /* bit 6,7: reserved */ -#define get_byte() inbuf[inptr++] +#define get_byte() (inbuf[inptr++]) /* Diagnostic functions */ #ifdef DEBUG -# define Assert(cond,msg) {if(!(cond)) error(msg);} +# define Assert(cond, msg) do { \ + if (!(cond)) \ + error(msg); \ + } while (0) # define Trace(x) fprintf x -# define Tracev(x) {if (verbose) fprintf x ;} -# define Tracevv(x) {if (verbose>1) fprintf x ;} -# define Tracec(c,x) {if (verbose && (c)) fprintf x ;} -# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} +# define Tracev(x) do { \ + if (verbose) \ + fprintf x; \ + } while (0) +# define Tracevv(x) do { \ + if (verbose > 1) \ + fprintf x; \ + } while (0) +# define Tracec(c, x) do { \ + if (verbose && (c)) \ + fprintf x; \ + } while (0) +# define Tracecv(c, x) do { \ + if (verbose > 1 && (c)) \ + fprintf x; \ + } while (0) #else -# define Assert(cond,msg) +# define Assert(cond, msg) # define Trace(x) # define Tracev(x) # define Tracevv(x) -# define Tracec(c,x) -# define Tracecv(c,x) +# define Tracec(c, x) +# define Tracecv(c, x) #endif static void flush_window(void); static void error(char *m); +static void puts(const char *); extern char *input_data; /* lives in head.S */ @@ -96,10 +114,6 @@ static long bytes_out; static uch *output_data; static unsigned long output_ptr; -static void error(char *m); - -static void puts(const char *); - /* the "heap" is put directly after the BSS ends, at end */ extern int _end; @@ -110,8 +124,8 @@ static long free_mem_end_ptr; /* decompressor info and error messages to serial console */ -static inline void -serout(const char *s, reg_scope_instances regi_ser) +#ifdef CONFIG_ETRAX_ARCH_V32 +static inline void serout(const char *s, reg_scope_instances regi_ser) { reg_ser_rs_stat_din rs; reg_ser_rw_dout dout = {.data = *s}; @@ -123,23 +137,47 @@ serout(const char *s, reg_scope_instances regi_ser) REG_WR(ser, regi_ser, rw_dout, dout); } +#endif -static void -puts(const char *s) +static void puts(const char *s) { #ifndef CONFIG_ETRAX_DEBUG_PORT_NULL while (*s) { #ifdef CONFIG_ETRAX_DEBUG_PORT0 +#ifdef CONFIG_ETRAX_ARCH_V32 serout(s, regi_ser0); +#else + while (!(*R_SERIAL0_STATUS & (1 << 5))) + ; + *R_SERIAL0_TR_DATA = *s++; +#endif #endif #ifdef CONFIG_ETRAX_DEBUG_PORT1 +#ifdef CONFIG_ETRAX_ARCH_V32 serout(s, regi_ser1); +#else + while (!(*R_SERIAL1_STATUS & (1 << 5))) + ; + *R_SERIAL1_TR_DATA = *s++; +#endif #endif #ifdef CONFIG_ETRAX_DEBUG_PORT2 +#ifdef CONFIG_ETRAX_ARCH_V32 serout(s, regi_ser2); +#else + while (!(*R_SERIAL2_STATUS & (1 << 5))) + ; + *R_SERIAL2_TR_DATA = *s++; +#endif #endif #ifdef CONFIG_ETRAX_DEBUG_PORT3 +#ifdef CONFIG_ETRAX_ARCH_V32 serout(s, regi_ser3); +#else + while (!(*R_SERIAL3_STATUS & (1 << 5))) + ; + *R_SERIAL3_TR_DATA = *s++; +#endif #endif *s++; } @@ -147,8 +185,7 @@ puts(const char *s) #endif } -void* -memset(void* s, int c, size_t n) +void *memset(void *s, int c, size_t n) { int i; char *ss = (char*)s; @@ -158,14 +195,13 @@ memset(void* s, int c, size_t n) return s; } -void* -memcpy(void* __dest, __const void* __src, - size_t __n) +void *memcpy(void *__dest, __const void *__src, size_t __n) { int i; char *d = (char *)__dest, *s = (char *)__src; - for (i=0;i<__n;i++) d[i] = s[i]; + for (i = 0; i < __n; i++) + d[i] = s[i]; return __dest; } @@ -175,43 +211,42 @@ memcpy(void* __dest, __const void* __src, * (Used for the decompressed data only.) */ -static void -flush_window() +static void flush_window(void) { - ulg c = crc; /* temporary variable */ - unsigned n; - uch *in, *out, ch; - - in = window; - out = &output_data[output_ptr]; - for (n = 0; n < outcnt; n++) { - ch = *out++ = *in++; - c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8); - } - crc = c; - bytes_out += (ulg)outcnt; - output_ptr += (ulg)outcnt; - outcnt = 0; + ulg c = crc; /* temporary variable */ + unsigned n; + uch *in, *out, ch; + + in = window; + out = &output_data[output_ptr]; + for (n = 0; n < outcnt; n++) { + ch = *out = *in; + out++; + in++; + c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8); + } + crc = c; + bytes_out += (ulg)outcnt; + output_ptr += (ulg)outcnt; + outcnt = 0; } -static void -error(char *x) +static void error(char *x) { - puts("\r\n\n"); + puts("\n\n"); puts(x); - puts("\r\n\n -- System halted\n"); + puts("\n\n -- System halted\n"); while(1); /* Halt */ } -void -setup_normal_output_buffer(void) +void setup_normal_output_buffer(void) { output_data = (char *)KERNEL_LOAD_ADR; } -static inline void -serial_setup(reg_scope_instances regi_ser) +#ifdef CONFIG_ETRAX_ARCH_V32 +static inline void serial_setup(reg_scope_instances regi_ser) { reg_ser_rw_xoff xoff; reg_ser_rw_tr_ctrl tr_ctrl; @@ -252,12 +287,16 @@ serial_setup(reg_scope_instances regi_ser) REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud); } +#endif -void -decompress_kernel(void) +void decompress_kernel(void) { char revision; + char compile_rev; +#ifdef CONFIG_ETRAX_ARCH_V32 + /* Need at least a CRISv32 to run. */ + compile_rev = 32; #if defined(CONFIG_ETRAX_DEBUG_PORT1) || \ defined(CONFIG_ETRAX_DEBUG_PORT2) || \ defined(CONFIG_ETRAX_DEBUG_PORT3) @@ -277,6 +316,7 @@ decompress_kernel(void) hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); #endif + #ifdef CONFIG_ETRAX_DEBUG_PORT0 serial_setup(regi_ser0); #endif @@ -300,19 +340,52 @@ decompress_kernel(void) /* input_data is set in head.S */ inbuf = input_data; +#else /* CRISv10 */ + /* Need at least a crisv10 to run. */ + compile_rev = 10; + + /* input_data is set in head.S */ + inbuf = input_data; + +#ifdef CONFIG_ETRAX_DEBUG_PORT0 + *R_SERIAL0_XOFF = 0; + *R_SERIAL0_BAUD = 0x99; + *R_SERIAL0_TR_CTRL = 0x40; +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT1 + *R_SERIAL1_XOFF = 0; + *R_SERIAL1_BAUD = 0x99; + *R_SERIAL1_TR_CTRL = 0x40; +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT2 + *R_GEN_CONFIG = 0x08; + *R_SERIAL2_XOFF = 0; + *R_SERIAL2_BAUD = 0x99; + *R_SERIAL2_TR_CTRL = 0x40; +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT3 + *R_GEN_CONFIG = 0x100; + *R_SERIAL3_XOFF = 0; + *R_SERIAL3_BAUD = 0x99; + *R_SERIAL3_TR_CTRL = 0x40; +#endif +#endif setup_normal_output_buffer(); makecrc(); __asm__ volatile ("move $vr,%0" : "=rm" (revision)); - if (revision < 32) - { - puts("You need an ETRAX FS to run Linux 2.6/crisv32.\r\n"); + if (revision < compile_rev) { +#ifdef CONFIG_ETRAX_ARCH_V32 + puts("You need an ETRAX FS to run Linux 2.6/crisv32\n"); +#else + puts("You need an ETRAX 100LX to run linux 2.6\n"); +#endif while(1); } - puts("Uncompressing Linux...\r\n"); + puts("Uncompressing Linux...\n"); gunzip(); - puts("Done. Now booting the kernel.\r\n"); + puts("Done. Now booting the kernel\n"); } diff --git a/arch/cris/arch-v10/boot/rescue/Makefile b/arch/cris/boot/rescue/Makefile index 82ab59b968e5..52bd0bd1dd22 100644 --- a/arch/cris/arch-v10/boot/rescue/Makefile +++ b/arch/cris/boot/rescue/Makefile @@ -2,16 +2,26 @@ # Makefile for rescue (bootstrap) code # -ccflags-y += -O2 $(LINUXINCLUDE) +# CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE) +# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/arch/mach/ \ +# -I$(srctree)/include/asm/arch +# asflags-y += -I $(srctree)/include/asm/arch/mach/ -I $(srctree)/include/asm/arch +# LD = gcc-cris -mlinux -march=v32 -nostdlib + asflags-y += $(LINUXINCLUDE) -ldflags-y += -T $(srctree)/$(src)/rescue.lds +ccflags-y += -O2 $(LINUXINCLUDE) +arch-$(CONFIG_ETRAX_ARCH_V10) = v10 +arch-$(CONFIG_ETRAX_ARCH_V32) = v32 + +ldflags-y += -T $(srctree)/$(src)/rescue_$(arch-y).lds OBJCOPYFLAGS = -O binary --remove-section=.bss -obj-$(CONFIG_ETRAX_AXISFLASHMAP) = head.o -OBJECT := $(obj)/head.o +obj-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o +obj-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o +OBJECTS := $(obj-y) targets := rescue.o rescue.bin -$(obj)/rescue.o: $(OBJECT) FORCE +$(obj)/rescue.o: $(OBJECTS) FORCE $(call if_changed,ld) $(obj)/rescue.bin: $(obj)/rescue.o FORCE @@ -26,6 +36,7 @@ $(obj)/testrescue.bin: $(obj)/testrescue.o dd if=testrescue_tmp.bin of=$(obj)/testrescue.bin bs=1 count=784 rm tr.bin tmp2423 testrescue_tmp.bin + $(obj)/kimagerescue.bin: $(obj)/kimagerescue.o $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/kimagerescue.o ktr.bin # Pad it to 784 bytes, that's what the rescue loader expects @@ -33,3 +44,4 @@ $(obj)/kimagerescue.bin: $(obj)/kimagerescue.o cat ktr.bin tmp2423 >kimagerescue_tmp.bin dd if=kimagerescue_tmp.bin of=$(obj)/kimagerescue.bin bs=1 count=784 rm ktr.bin tmp2423 kimagerescue_tmp.bin + diff --git a/arch/cris/arch-v10/boot/rescue/head.S b/arch/cris/boot/rescue/head_v10.S index fb503d1eeea4..2fafe247a25b 100644 --- a/arch/cris/arch-v10/boot/rescue/head.S +++ b/arch/cris/boot/rescue/head_v10.S @@ -155,7 +155,7 @@ no_newjump: #endif ;; We need to setup the bus registers before we start using the DRAM -#include "../../lib/dram_init.S" +#include "../../../arch-v10/lib/dram_init.S" ;; we now should go through the checksum-table and check the listed ;; partitions for errors. diff --git a/arch/cris/arch-v32/boot/rescue/head.S b/arch/cris/boot/rescue/head_v32.S index 5f846b7700a3..5f846b7700a3 100644 --- a/arch/cris/arch-v32/boot/rescue/head.S +++ b/arch/cris/boot/rescue/head_v32.S diff --git a/arch/cris/arch-v10/boot/rescue/kimagerescue.S b/arch/cris/boot/rescue/kimagerescue.S index 6f7b3e61260b..6f7b3e61260b 100644 --- a/arch/cris/arch-v10/boot/rescue/kimagerescue.S +++ b/arch/cris/boot/rescue/kimagerescue.S diff --git a/arch/cris/arch-v10/boot/rescue/rescue.lds b/arch/cris/boot/rescue/rescue_v10.lds index 0b52a9490db6..0b52a9490db6 100644 --- a/arch/cris/arch-v10/boot/rescue/rescue.lds +++ b/arch/cris/boot/rescue/rescue_v10.lds diff --git a/arch/cris/arch-v32/boot/rescue/rescue.lds b/arch/cris/boot/rescue/rescue_v32.lds index 8ac646bc1a2b..8ac646bc1a2b 100644 --- a/arch/cris/arch-v32/boot/rescue/rescue.lds +++ b/arch/cris/boot/rescue/rescue_v32.lds diff --git a/arch/cris/arch-v10/boot/rescue/testrescue.S b/arch/cris/boot/rescue/testrescue.S index fc7ec674eca5..fc7ec674eca5 100644 --- a/arch/cris/arch-v10/boot/rescue/testrescue.S +++ b/arch/cris/boot/rescue/testrescue.S diff --git a/arch/cris/arch-v10/boot/tools/build.c b/arch/cris/boot/tools/build.c index c8adef364160..c8adef364160 100644 --- a/arch/cris/arch-v10/boot/tools/build.c +++ b/arch/cris/boot/tools/build.c diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h index 235d076379d5..c17079388bb9 100644 --- a/arch/cris/include/asm/unistd.h +++ b/arch/cris/include/asm/unistd.h @@ -281,7 +281,7 @@ #define __NR_mbind 274 #define __NR_get_mempolicy 275 #define __NR_set_mempolicy 276 -#define __NR_mq_open 277 +#define __NR_mq_open 277 #define __NR_mq_unlink (__NR_mq_open+1) #define __NR_mq_timedsend (__NR_mq_open+2) #define __NR_mq_timedreceive (__NR_mq_open+3) @@ -331,10 +331,18 @@ #define __NR_fallocate 324 #define __NR_timerfd_settime 325 #define __NR_timerfd_gettime 326 +#define __NR_signalfd4 327 +#define __NR_eventfd2 328 +#define __NR_epoll_create1 329 +#define __NR_dup3 330 +#define __NR_pipe2 331 +#define __NR_inotify_init1 332 +#define __NR_preadv 333 +#define __NR_pwritev 334 #ifdef __KERNEL__ -#define NR_syscalls 327 +#define NR_syscalls 335 #include <arch/unistd.h> diff --git a/arch/frv/include/asm/bug.h b/arch/frv/include/asm/bug.h index 6b1b44d71028..2e054508a2f6 100644 --- a/arch/frv/include/asm/bug.h +++ b/arch/frv/include/asm/bug.h @@ -30,7 +30,7 @@ extern void __debug_bug_printk(const char *file, unsigned line); do { \ __debug_bug_trap(signr); \ asm volatile("nop"); \ -} while(0) +} while(1) #define HAVE_ARCH_BUG #define BUG() \ @@ -46,7 +46,8 @@ do { \ #define HAVE_ARCH_KGDB_BAD_PAGE #define kgdb_bad_page(page) do { kgdb_raise(SIGABRT); } while(0) #endif -#endif + +#endif /* CONFIG_BUG */ #include <asm-generic/bug.h> diff --git a/arch/frv/include/asm/init.h b/arch/frv/include/asm/init.h deleted file mode 100644 index 8b15838de216..000000000000 --- a/arch/frv/include/asm/init.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_INIT_H -#define _ASM_INIT_H - -#define __init __attribute__ ((__section__ (".text.init"))) -#define __initdata __attribute__ ((__section__ (".data.init"))) -/* For assembly routines */ -#define __INIT .section ".text.init",#alloc,#execinstr -#define __FINIT .previous -#define __INITDATA .section ".data.init",#alloc,#write - -#endif - diff --git a/arch/frv/include/asm/unistd.h b/arch/frv/include/asm/unistd.h index edcfaf5f0414..96d78d5d2c41 100644 --- a/arch/frv/include/asm/unistd.h +++ b/arch/frv/include/asm/unistd.h @@ -339,10 +339,12 @@ #define __NR_dup3 330 #define __NR_pipe2 331 #define __NR_inotify_init1 332 +#define __NR_preadv 333 +#define __NR_pwritev 334 #ifdef __KERNEL__ -#define NR_syscalls 333 +#define NR_syscalls 335 #define __ARCH_WANT_IPC_PARSE_VERSION /* #define __ARCH_WANT_OLD_READDIR */ diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S index 99060ab507ee..1da523b3298e 100644 --- a/arch/frv/kernel/entry.S +++ b/arch/frv/kernel/entry.S @@ -1525,5 +1525,7 @@ sys_call_table: .long sys_dup3 /* 330 */ .long sys_pipe2 .long sys_inotify_init1 + .long sys_preadv + .long sys_pwritev syscall_table_size = (. - sys_call_table) diff --git a/arch/frv/kernel/head-mmu-fr451.S b/arch/frv/kernel/head-mmu-fr451.S index c8f210d84ff5..98f87d586e59 100644 --- a/arch/frv/kernel/head-mmu-fr451.S +++ b/arch/frv/kernel/head-mmu-fr451.S @@ -9,6 +9,7 @@ * 2 of the License, or (at your option) any later version. */ +#include <linux/init.h> #include <linux/threads.h> #include <linux/linkage.h> #include <asm/ptrace.h> @@ -31,7 +32,7 @@ #define __400_LCR 0xfe000100 #define __400_LSBR 0xfe000c00 - .section .text.init,"ax" + __INIT .balign 4 ############################################################################### diff --git a/arch/frv/kernel/head-uc-fr401.S b/arch/frv/kernel/head-uc-fr401.S index ee282be20fff..438643cfa38e 100644 --- a/arch/frv/kernel/head-uc-fr401.S +++ b/arch/frv/kernel/head-uc-fr401.S @@ -9,6 +9,7 @@ * 2 of the License, or (at your option) any later version. */ +#include <linux/init.h> #include <linux/threads.h> #include <linux/linkage.h> #include <asm/ptrace.h> @@ -30,7 +31,7 @@ #define __400_LCR 0xfe000100 #define __400_LSBR 0xfe000c00 - .section .text.init,"ax" + __INIT .balign 4 ############################################################################### diff --git a/arch/frv/kernel/head-uc-fr451.S b/arch/frv/kernel/head-uc-fr451.S index b10d9c8295d2..b2a76c4a1786 100644 --- a/arch/frv/kernel/head-uc-fr451.S +++ b/arch/frv/kernel/head-uc-fr451.S @@ -9,6 +9,7 @@ * 2 of the License, or (at your option) any later version. */ +#include <linux/init.h> #include <linux/threads.h> #include <linux/linkage.h> #include <asm/ptrace.h> @@ -30,7 +31,7 @@ #define __400_LCR 0xfe000100 #define __400_LSBR 0xfe000c00 - .section .text.init,"ax" + __INIT .balign 4 ############################################################################### diff --git a/arch/frv/kernel/head-uc-fr555.S b/arch/frv/kernel/head-uc-fr555.S index 39937c19b460..5497aaf34f77 100644 --- a/arch/frv/kernel/head-uc-fr555.S +++ b/arch/frv/kernel/head-uc-fr555.S @@ -9,6 +9,7 @@ * 2 of the License, or (at your option) any later version. */ +#include <linux/init.h> #include <linux/threads.h> #include <linux/linkage.h> #include <asm/ptrace.h> @@ -29,7 +30,7 @@ #define __551_LCR 0xfeff1100 #define __551_LSBR 0xfeff1c00 - .section .text.init,"ax" + __INIT .balign 4 ############################################################################### diff --git a/arch/m68k/kernel/sun3-head.S b/arch/m68k/kernel/sun3-head.S index 9e5c3e57c598..43036bf4aeed 100644 --- a/arch/m68k/kernel/sun3-head.S +++ b/arch/m68k/kernel/sun3-head.S @@ -1,4 +1,5 @@ #include <linux/linkage.h> +#include <linux/init.h> #include <asm/entry.h> #include <asm/page.h> diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 5c878436f348..325b310573b9 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -158,21 +158,33 @@ void ibm440spe_fixup_memsize(void) #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) -void ibm4xx_denali_fixup_memsize(void) +/* + * Some U-Boot versions set the number of chipselects to two + * for Sequoia/Rainier boards while they only have one chipselect + * hardwired. Hardcode the number of chipselects to one + * for sequioa/rainer board models or read the actual value + * from the memory controller register DDR0_10 otherwise. + */ +static inline u32 ibm4xx_denali_get_cs(void) { - u32 val, max_cs, max_col, max_row; - u32 cs, col, row, bank, dpath; - unsigned long memsize; + void *devp; + char model[64]; + u32 val, cs; - val = SDRAM0_READ(DDR0_02); - if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) - fatal("DDR controller is not initialized\n"); + devp = finddevice("/"); + if (!devp) + goto read_cs; - /* get maximum cs col and row values */ - max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); - max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); - max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); + if (getprop(devp, "model", model, sizeof(model)) <= 0) + goto read_cs; + model[sizeof(model)-1] = 0; + + if (!strcmp(model, "amcc,sequoia") || + !strcmp(model, "amcc,rainier")) + return 1; + +read_cs: /* get CS value */ val = SDRAM0_READ(DDR0_10); @@ -183,7 +195,25 @@ void ibm4xx_denali_fixup_memsize(void) cs++; val = val >> 1; } + return cs; +} + +void ibm4xx_denali_fixup_memsize(void) +{ + u32 val, max_cs, max_col, max_row; + u32 cs, col, row, bank, dpath; + unsigned long memsize; + + val = SDRAM0_READ(DDR0_02); + if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) + fatal("DDR controller is not initialized\n"); + /* get maximum cs col and row values */ + max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); + max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); + max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); + + cs = ibm4xx_denali_get_cs(); if (!cs) fatal("No memory installed\n"); if (cs > max_cs) @@ -193,9 +223,9 @@ void ibm4xx_denali_fixup_memsize(void) val = SDRAM0_READ(DDR0_14); if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) - dpath = 8; /* 64 bits */ - else dpath = 4; /* 32 bits */ + else + dpath = 8; /* 64 bits */ /* get address pins (rows) */ val = SDRAM0_READ(DDR0_42); diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts index d47ad0718759..38dd0052f6c9 100644 --- a/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -161,11 +161,25 @@ #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <2>; + device_type = "soc"; compatible = "fsl,mpc8641-soc", "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts index 1569117e5ddc..155776ceac25 100644 --- a/arch/powerpc/boot/dts/gef_sbc310.dts +++ b/arch/powerpc/boot/dts/gef_sbc310.dts @@ -166,6 +166,19 @@ reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index 6582dbd36da7..6898d7e87fba 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -131,6 +131,19 @@ reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index c9cfd374bffb..bdb7fc0fa332 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts @@ -56,6 +56,19 @@ ranges = <0x00000000 0xfdf00000 0x00100000>; bus-frequency = <0>; /* Fixed by bootwrapper */ + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index 57c595bf1071..6b319f58262f 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -369,7 +369,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x11 AD17 */ diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 4319bd70a580..4c0c249b475d 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -327,7 +327,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 AD16 (USB) */ diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts index 1ae38f0ddef8..e3eeaeda9187 100644 --- a/arch/powerpc/boot/dts/mpc8349emitx.dts +++ b/arch/powerpc/boot/dts/mpc8349emitx.dts @@ -278,7 +278,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 - SATA */ @@ -301,7 +300,6 @@ }; pci1: pci@e0008600 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0E - MiniPCI Slot */ diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts index 662abe1fb804..eb732115f016 100644 --- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts +++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts @@ -227,7 +227,6 @@ }; pci0: pci@e0008600 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0F - PCI Slot */ diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index d9f0a2325fa4..a2553a6f9009 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -286,7 +286,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < @@ -348,7 +347,6 @@ }; pci1: pci@e0008600 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 6e34f170fa62..1207ec870e52 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -410,7 +410,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index 963708017e6c..67bb372c9451 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts @@ -383,7 +383,6 @@ }; pci0: pci@e0008500 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts index 651ff2f9db2d..a955a577db81 100644 --- a/arch/powerpc/boot/dts/mpc8378_mds.dts +++ b/arch/powerpc/boot/dts/mpc8378_mds.dts @@ -367,7 +367,6 @@ }; pci0: pci@e0008500 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts index d6f208b8297a..d266ddbfc28d 100644 --- a/arch/powerpc/boot/dts/mpc8379_mds.dts +++ b/arch/powerpc/boot/dts/mpc8379_mds.dts @@ -397,7 +397,6 @@ }; pci0: pci@e0008500 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts index b31c5041350b..b6fd8564c0e3 100644 --- a/arch/powerpc/boot/dts/mpc8536ds.dts +++ b/arch/powerpc/boot/dts/mpc8536ds.dts @@ -54,6 +54,19 @@ reg = <0xffe00000 0x1000>; bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8536-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8536-memory-controller"; reg = <0x2000 0x1000>; @@ -321,7 +334,6 @@ }; pci0: pci@ffe08000 { - cell-index = <0>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; @@ -346,7 +358,6 @@ }; pci1: pcie@ffe09000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -383,7 +394,6 @@ }; pci2: pcie@ffe0a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -420,7 +430,6 @@ }; pci3: pcie@ffe0b000 { - cell-index = <3>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index ddd67be10b03..7c8b1093b0b8 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -58,6 +58,19 @@ reg = <0xe0000000 0x100000>; // CCSRBAR 1M bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8540-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8540-memory-controller"; reg = <0x2000 0x1000>; @@ -258,7 +271,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index e45097f44fbd..de9d8b55391b 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -58,6 +58,19 @@ reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8541-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8541-memory-controller"; reg = <0x2000 0x1000>; @@ -272,7 +285,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; interrupt-map = < @@ -344,7 +356,6 @@ }; pci1: pci@e0009000 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 7c6932be0197..9819d6c2275c 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -60,6 +60,19 @@ reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8544-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8544-memory-controller"; reg = <0x2000 0x1000>; @@ -274,7 +287,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; @@ -306,7 +318,6 @@ }; pci1: pcie@e0009000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -343,7 +354,6 @@ }; pci2: pcie@e000a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -380,7 +390,6 @@ }; pci3: pcie@e000b000 { - cell-index = <3>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 804e90353293..6e40db7e2b15 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -63,6 +63,19 @@ reg = <0xe0000000 0x1000>; // CCSRBAR bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8548-memory-controller"; reg = <0x2000 0x1000>; @@ -328,7 +341,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x4 (PCIX Slot 2) */ @@ -478,7 +490,6 @@ }; pci1: pci@e0009000 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < @@ -503,7 +514,6 @@ }; pci2: pcie@e000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 9484f0729b10..6291497721ba 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -58,6 +58,19 @@ reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8555-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8555-memory-controller"; reg = <0x2000 0x1000>; @@ -272,7 +285,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; interrupt-map = < @@ -344,7 +356,6 @@ }; pci1: pci@e0009000 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index cc2acf87d02f..a2347b57a2a2 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -58,6 +58,19 @@ reg = <0xe0000000 0x200>; bus-frequency = <330000000>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8540-memory-controller"; reg = <0x2000 0x1000>; @@ -291,7 +304,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 9d52e3b25047..d2fb639c26e7 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -65,6 +65,19 @@ reg = <0xe0000000 0x1000>; bus-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8568-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,8568-memory-controller"; reg = <0x2000 0x1000>; @@ -459,7 +472,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x12 AD18 */ @@ -490,7 +502,6 @@ /* PCI Express */ pci1: pcie@e000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 6e79a4169088..3f9a62313f29 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -185,6 +185,19 @@ reg = <0 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8572-memory-controller"; reg = <0x2000 0x1000>; @@ -514,7 +527,6 @@ }; pci0: pcie@ffe08000 { - cell-index = <0>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -724,7 +736,6 @@ }; pci1: pcie@ffe09000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -761,7 +772,6 @@ }; pci2: pcie@ffe0a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts index dbd81a764742..fee17f35f7a0 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_36b.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts @@ -185,6 +185,19 @@ reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8572-memory-controller"; reg = <0x2000 0x1000>; @@ -514,7 +527,6 @@ }; pci0: pcie@fffe08000 { - cell-index = <0>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -724,7 +736,6 @@ }; pci1: pcie@fffe09000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -761,7 +772,6 @@ }; pci2: pcie@fffe0a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts index 2bc0c7189653..abb1730d15ad 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts @@ -62,6 +62,19 @@ reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed bus-frequency = <0>; // Filled out by uboot. + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,mpc8572-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8572-memory-controller"; reg = <0x2000 0x1000>; @@ -238,7 +251,6 @@ }; pci0: pcie@ffe08000 { - cell-index = <0>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -448,7 +460,6 @@ }; pci1: pcie@ffe09000 { - cell-index = <1>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts index 159cb3a875f0..0ded4a622136 100644 --- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts +++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts @@ -196,7 +196,6 @@ }; pci2: pcie@ffe0a000 { - cell-index = <2>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 1bd3ebe11437..252db6e4e031 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -115,6 +115,19 @@ reg = <0xe0000000 0x1000>; bus-frequency = <0>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8610-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -316,7 +329,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; compatible = "fsl,mpc8610-pci"; device_type = "pci"; #interrupt-cells = <1>; @@ -346,7 +358,6 @@ }; pci1: pcie@e000a000 { - cell-index = <1>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index d72beb192460..8bcccd7b5d70 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -117,6 +117,19 @@ reg = <0xffe00000 0x00001000>; // CCSRBAR bus-frequency = <0>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -357,7 +370,6 @@ }; pci0: pcie@ffe08000 { - cell-index = <0>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -566,7 +578,6 @@ }; pci1: pcie@ffe09000 { - cell-index = <1>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts new file mode 100644 index 000000000000..d4c909d1c00c --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts @@ -0,0 +1,610 @@ +/* + * MPC8641 HPCN Device Tree Source + * + * Copyright 2008-2009 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "MPC8641HPCN"; + compatible = "fsl,mpc8641hpcn"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8641@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <32768>; // L1, 32K + i-cache-size = <32768>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + }; + PowerPC,8641@1 { + device_type = "cpu"; + reg = <1>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <32768>; // L1, 32K + i-cache-size = <32768>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0 + }; + + localbus@fffe05000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8641-localbus", "simple-bus"; + reg = <0x0f 0xffe05000 0x0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + + ranges = <0 0 0xf 0xef800000 0x00800000 + 2 0 0xf 0xffdf8000 0x00008000 + 3 0 0xf 0xffdf0000 0x00008000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x00800000>; + bank-width = <2>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x00300000>; + }; + partition@300000 { + label = "firmware b"; + reg = <0x00300000 0x00100000>; + read-only; + }; + partition@400000 { + label = "fs"; + reg = <0x00400000 0x00300000>; + }; + partition@700000 { + label = "firmware a"; + reg = <0x00700000 0x00100000>; + read-only; + }; + }; + }; + + soc8641@fffe00000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x00000000 0x0f 0xffe00000 0x00100000>; + reg = <0x0f 0xffe00000 0x0 0x00001000>; // CCSRBAR + bus-frequency = <0>; + + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8641-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <0>; + device_type = "ethernet-phy"; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + phy2: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <2>; + device_type = "ethernet-phy"; + }; + phy3: ethernet-phy@3 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <3>; + device_type = "ethernet-phy"; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet2: ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi2>; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet3: ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + tbi-handle = <&tbi3>; + phy-handle = <&phy3>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi3: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <28 2>; + interrupt-parent = <&mpic>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + global-utilities@e0000 { + compatible = "fsl,mpc8641-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + }; + + pci0: pcie@fffe08000 { + cell-index = <0>; + compatible = "fsl,mpc8641-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x0f 0xffe08000 0x0 0x1000>; + bus-range = <0x0 0xff>; + ranges = <0x02000000 0x0 0xc0000000 0x0c 0x00000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <24 2>; + interrupt-map-mask = <0xff00 0 0 7>; + interrupt-map = < + /* IDSEL 0x11 func 0 - PCI slot 1 */ + 0x8800 0 0 1 &mpic 2 1 + 0x8800 0 0 2 &mpic 3 1 + 0x8800 0 0 3 &mpic 4 1 + 0x8800 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 1 - PCI slot 1 */ + 0x8900 0 0 1 &mpic 2 1 + 0x8900 0 0 2 &mpic 3 1 + 0x8900 0 0 3 &mpic 4 1 + 0x8900 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 2 - PCI slot 1 */ + 0x8a00 0 0 1 &mpic 2 1 + 0x8a00 0 0 2 &mpic 3 1 + 0x8a00 0 0 3 &mpic 4 1 + 0x8a00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 3 - PCI slot 1 */ + 0x8b00 0 0 1 &mpic 2 1 + 0x8b00 0 0 2 &mpic 3 1 + 0x8b00 0 0 3 &mpic 4 1 + 0x8b00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 4 - PCI slot 1 */ + 0x8c00 0 0 1 &mpic 2 1 + 0x8c00 0 0 2 &mpic 3 1 + 0x8c00 0 0 3 &mpic 4 1 + 0x8c00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 5 - PCI slot 1 */ + 0x8d00 0 0 1 &mpic 2 1 + 0x8d00 0 0 2 &mpic 3 1 + 0x8d00 0 0 3 &mpic 4 1 + 0x8d00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 6 - PCI slot 1 */ + 0x8e00 0 0 1 &mpic 2 1 + 0x8e00 0 0 2 &mpic 3 1 + 0x8e00 0 0 3 &mpic 4 1 + 0x8e00 0 0 4 &mpic 1 1 + + /* IDSEL 0x11 func 7 - PCI slot 1 */ + 0x8f00 0 0 1 &mpic 2 1 + 0x8f00 0 0 2 &mpic 3 1 + 0x8f00 0 0 3 &mpic 4 1 + 0x8f00 0 0 4 &mpic 1 1 + + /* IDSEL 0x12 func 0 - PCI slot 2 */ + 0x9000 0 0 1 &mpic 3 1 + 0x9000 0 0 2 &mpic 4 1 + 0x9000 0 0 3 &mpic 1 1 + 0x9000 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 1 - PCI slot 2 */ + 0x9100 0 0 1 &mpic 3 1 + 0x9100 0 0 2 &mpic 4 1 + 0x9100 0 0 3 &mpic 1 1 + 0x9100 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 2 - PCI slot 2 */ + 0x9200 0 0 1 &mpic 3 1 + 0x9200 0 0 2 &mpic 4 1 + 0x9200 0 0 3 &mpic 1 1 + 0x9200 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 3 - PCI slot 2 */ + 0x9300 0 0 1 &mpic 3 1 + 0x9300 0 0 2 &mpic 4 1 + 0x9300 0 0 3 &mpic 1 1 + 0x9300 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 4 - PCI slot 2 */ + 0x9400 0 0 1 &mpic 3 1 + 0x9400 0 0 2 &mpic 4 1 + 0x9400 0 0 3 &mpic 1 1 + 0x9400 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 5 - PCI slot 2 */ + 0x9500 0 0 1 &mpic 3 1 + 0x9500 0 0 2 &mpic 4 1 + 0x9500 0 0 3 &mpic 1 1 + 0x9500 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 6 - PCI slot 2 */ + 0x9600 0 0 1 &mpic 3 1 + 0x9600 0 0 2 &mpic 4 1 + 0x9600 0 0 3 &mpic 1 1 + 0x9600 0 0 4 &mpic 2 1 + + /* IDSEL 0x12 func 7 - PCI slot 2 */ + 0x9700 0 0 1 &mpic 3 1 + 0x9700 0 0 2 &mpic 4 1 + 0x9700 0 0 3 &mpic 1 1 + 0x9700 0 0 4 &mpic 2 1 + + // IDSEL 0x1c USB + 0xe000 0 0 1 &i8259 12 2 + 0xe100 0 0 2 &i8259 9 2 + 0xe200 0 0 3 &i8259 10 2 + 0xe300 0 0 4 &i8259 11 2 + + // IDSEL 0x1d Audio + 0xe800 0 0 1 &i8259 6 2 + + // IDSEL 0x1e Legacy + 0xf000 0 0 1 &i8259 7 2 + 0xf100 0 0 1 &i8259 7 2 + + // IDSEL 0x1f IDE/SATA + 0xf800 0 0 1 &i8259 14 2 + 0xf900 0 0 1 &i8259 5 2 + >; + + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0x0 0xc0000000 + 0x02000000 0x0 0xc0000000 + 0x0 0x20000000 + + 0x01000000 0x0 0x00000000 + 0x01000000 0x0 0x00000000 + 0x0 0x00010000>; + uli1575@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + ranges = <0x02000000 0x0 0xc0000000 + 0x02000000 0x0 0xc0000000 + 0x0 0x20000000 + 0x01000000 0x0 0x00000000 + 0x01000000 0x0 0x00000000 + 0x0 0x00010000>; + isa@1e { + device_type = "isa"; + #interrupt-cells = <2>; + #size-cells = <1>; + #address-cells = <2>; + reg = <0xf000 0 0 0 0>; + ranges = <1 0 0x01000000 0 0 + 0x00001000>; + interrupt-parent = <&i8259>; + + i8259: interrupt-controller@20 { + reg = <1 0x20 2 + 1 0xa0 2 + 1 0x4d0 2>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; + interrupts = <9 2>; + interrupt-parent = <&mpic>; + }; + + i8042@60 { + #size-cells = <0>; + #address-cells = <1>; + reg = <1 0x60 1 1 0x64 1>; + interrupts = <1 3 12 3>; + interrupt-parent = + <&i8259>; + + keyboard@0 { + reg = <0>; + compatible = "pnpPNP,303"; + }; + + mouse@1 { + reg = <1>; + compatible = "pnpPNP,f03"; + }; + }; + + rtc@70 { + compatible = + "pnpPNP,b00"; + reg = <1 0x70 2>; + }; + + gpio@400 { + reg = <1 0x400 0x80>; + }; + }; + }; + }; + + }; + + pci1: pcie@fffe09000 { + cell-index = <1>; + compatible = "fsl,mpc8641-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x0f 0xffe09000 0x0 0x1000>; + bus-range = <0x0 0xff>; + ranges = <0x02000000 0x0 0xc0000000 0x0c 0x20000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0000 0 0 1 &mpic 4 1 + 0x0000 0 0 2 &mpic 5 1 + 0x0000 0 0 3 &mpic 6 1 + 0x0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0x0 0xc0000000 + 0x02000000 0x0 0xc0000000 + 0x0 0x20000000 + + 0x01000000 0x0 0x00000000 + 0x01000000 0x0 0x00000000 + 0x0 0x00010000>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts index a36dbbc48694..5fb6f6684b0e 100644 --- a/arch/powerpc/boot/dts/sbc8349.dts +++ b/arch/powerpc/boot/dts/sbc8349.dts @@ -278,7 +278,6 @@ }; pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index b1f1416ac998..66c9165eeb7a 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -155,6 +155,19 @@ bus-frequency = <0>; compatible = "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; @@ -350,7 +363,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x01 (PCI-X slot) @66MHz */ @@ -380,7 +392,6 @@ }; pci2: pcie@e000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index c4564b81e473..ff6a52270a9b 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts @@ -60,6 +60,19 @@ reg = <0xff700000 0x00100000>; clock-frequency = <0>; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8560-memory-controller"; reg = <0x2000 0x1000>; @@ -296,7 +309,6 @@ }; pci0: pci@ff708000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts index e3e914e78caa..aa8f931a0e9b 100644 --- a/arch/powerpc/boot/dts/sbc8641d.dts +++ b/arch/powerpc/boot/dts/sbc8641d.dts @@ -129,6 +129,19 @@ reg = <0xf8000000 0x00001000>; // CCSRBAR bus-frequency = <0>; + mcm-law@0 { + compatible = "fsl,mcm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + mcm@1000 { + compatible = "fsl,mpc8641-mcm", "fsl,mcm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + i2c@3000 { #address-cells = <1>; #size-cells = <0>; @@ -371,7 +384,6 @@ }; pci0: pcie@f8008000 { - cell-index = <0>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; @@ -410,7 +422,6 @@ }; pci1: pcie@f8009000 { - cell-index = <1>; compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts index 7a6ae75a1e57..779876a8867e 100644 --- a/arch/powerpc/boot/dts/socrates.dts +++ b/arch/powerpc/boot/dts/socrates.dts @@ -59,6 +59,19 @@ bus-frequency = <0>; // Filled in by U-Boot compatible = "fsl,mpc8544-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8544-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8544-memory-controller"; reg = <0x2000 0x1000>; @@ -314,7 +327,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index ea6b15152de3..ce35e89a6655 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -56,6 +56,19 @@ bus-frequency = <0>; compatible = "fsl,mpc8560-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -251,7 +264,6 @@ }; pci0: pci@fdf08000 { - cell-index = <0>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index b6f1fc6eb960..5e9eecc33a41 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -58,6 +58,19 @@ bus-frequency = <0>; compatible = "fsl,mpc8540-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8540-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -266,7 +279,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index fa6a3d54a8a5..3c8d5c1000d6 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -57,6 +57,19 @@ bus-frequency = <0>; compatible = "fsl,mpc8541-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8541-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -288,7 +301,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts index 00f7ed7a2455..435d2b240eb9 100644 --- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts +++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts @@ -59,6 +59,19 @@ bus-frequency = <0>; compatible = "fsl,mpc8548-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; @@ -419,7 +432,6 @@ }; pci0: pci@a0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -441,7 +453,6 @@ }; pci1: pcie@a000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 (PEX) */ diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts index 673e4a778ac8..3b8af5bd6adf 100644 --- a/arch/powerpc/boot/dts/tqm8548.dts +++ b/arch/powerpc/boot/dts/tqm8548.dts @@ -59,6 +59,19 @@ bus-frequency = <0>; compatible = "fsl,mpc8548-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8548-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; @@ -419,7 +432,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -441,7 +453,6 @@ }; pci1: pcie@e000a000 { - cell-index = <2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 (PEX) */ diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index 6a99f1eef7ad..a820bbeb2f7d 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -57,6 +57,19 @@ bus-frequency = <0>; compatible = "fsl,mpc8555-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8555-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -288,7 +301,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index b6c2d71defd3..fa7355062525 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -59,6 +59,19 @@ bus-frequency = <0>; compatible = "fsl,mpc8560-immr", "simple-bus"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <8>; + }; + + ecm@1000 { + compatible = "fsl,mpc8560-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + memory-controller@2000 { compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; @@ -359,7 +372,6 @@ }; pci0: pci@e0008000 { - cell-index = <0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/configs/40x/acadia_defconfig b/arch/powerpc/configs/40x/acadia_defconfig index a32ec8d323a0..173a5bb77ca1 100644 --- a/arch/powerpc/configs/40x/acadia_defconfig +++ b/arch/powerpc/configs/40x/acadia_defconfig @@ -252,7 +252,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/40x/ep405_defconfig b/arch/powerpc/configs/40x/ep405_defconfig index 4e9d85f39da0..e9b8495cde0c 100644 --- a/arch/powerpc/configs/40x/ep405_defconfig +++ b/arch/powerpc/configs/40x/ep405_defconfig @@ -254,7 +254,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig index 9917a09bad3a..cc3e7b785ac4 100644 --- a/arch/powerpc/configs/40x/kilauea_defconfig +++ b/arch/powerpc/configs/40x/kilauea_defconfig @@ -252,7 +252,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/40x/makalu_defconfig b/arch/powerpc/configs/40x/makalu_defconfig index 58bf2ac2e0dd..50c7cc174568 100644 --- a/arch/powerpc/configs/40x/makalu_defconfig +++ b/arch/powerpc/configs/40x/makalu_defconfig @@ -252,7 +252,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig index f5698f962e58..416e79ac0711 100644 --- a/arch/powerpc/configs/40x/virtex_defconfig +++ b/arch/powerpc/configs/40x/virtex_defconfig @@ -258,7 +258,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/arches_defconfig b/arch/powerpc/configs/44x/arches_defconfig index 1d72b0ac3f25..f7fd32c09424 100644 --- a/arch/powerpc/configs/44x/arches_defconfig +++ b/arch/powerpc/configs/44x/arches_defconfig @@ -258,7 +258,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/bamboo_defconfig b/arch/powerpc/configs/44x/bamboo_defconfig index 959bdc43a491..e57f1e4c1795 100644 --- a/arch/powerpc/configs/44x/bamboo_defconfig +++ b/arch/powerpc/configs/44x/bamboo_defconfig @@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig index f9a08ee49b96..5e85412eb9fa 100644 --- a/arch/powerpc/configs/44x/canyonlands_defconfig +++ b/arch/powerpc/configs/44x/canyonlands_defconfig @@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set @@ -716,7 +716,7 @@ CONFIG_SSB_POSSIBLE=y # # Multimedia drivers # -CONFIG_DAB=y +# CONFIG_DAB is not set # CONFIG_USB_DABUSB is not set # @@ -725,7 +725,7 @@ CONFIG_DAB=y # CONFIG_AGP is not set # CONFIG_DRM is not set # CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set diff --git a/arch/powerpc/configs/44x/ebony_defconfig b/arch/powerpc/configs/44x/ebony_defconfig index be64aa644d15..b652f7dcab5a 100644 --- a/arch/powerpc/configs/44x/ebony_defconfig +++ b/arch/powerpc/configs/44x/ebony_defconfig @@ -261,7 +261,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/katmai_defconfig b/arch/powerpc/configs/44x/katmai_defconfig index f67250b24ec5..c23a4ef13e45 100644 --- a/arch/powerpc/configs/44x/katmai_defconfig +++ b/arch/powerpc/configs/44x/katmai_defconfig @@ -256,7 +256,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/rainier_defconfig b/arch/powerpc/configs/44x/rainier_defconfig index 9348c12bd7a6..b25fad1343dc 100644 --- a/arch/powerpc/configs/44x/rainier_defconfig +++ b/arch/powerpc/configs/44x/rainier_defconfig @@ -260,7 +260,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/redwood_defconfig b/arch/powerpc/configs/44x/redwood_defconfig index e665433762ba..ed31d4f17b5a 100644 --- a/arch/powerpc/configs/44x/redwood_defconfig +++ b/arch/powerpc/configs/44x/redwood_defconfig @@ -265,7 +265,7 @@ CONFIG_PCIEAER=y # CONFIG_PCIEASPM is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/sam440ep_defconfig b/arch/powerpc/configs/44x/sam440ep_defconfig index 70d5c3fa3283..e14e89a5e06b 100644 --- a/arch/powerpc/configs/44x/sam440ep_defconfig +++ b/arch/powerpc/configs/44x/sam440ep_defconfig @@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set diff --git a/arch/powerpc/configs/44x/sequoia_defconfig b/arch/powerpc/configs/44x/sequoia_defconfig index a921fe3c3711..cb98da046d3d 100644 --- a/arch/powerpc/configs/44x/sequoia_defconfig +++ b/arch/powerpc/configs/44x/sequoia_defconfig @@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/taishan_defconfig b/arch/powerpc/configs/44x/taishan_defconfig index 826700872d26..ef32cc4f82eb 100644 --- a/arch/powerpc/configs/44x/taishan_defconfig +++ b/arch/powerpc/configs/44x/taishan_defconfig @@ -260,7 +260,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig index 1bf0a63614b1..2518b8568c70 100644 --- a/arch/powerpc/configs/44x/virtex5_defconfig +++ b/arch/powerpc/configs/44x/virtex5_defconfig @@ -263,7 +263,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set -CONFIG_PCI_LEGACY=y +# CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCCARD is not set diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h index 087c22f1d368..d6b4a12cdeff 100644 --- a/arch/powerpc/include/asm/elf.h +++ b/arch/powerpc/include/asm/elf.h @@ -260,6 +260,7 @@ do { \ #else # define SET_PERSONALITY(ex) \ set_personality(PER_LINUX | (current->personality & (~PER_MASK))) +# define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X) #endif /* __powerpc64__ */ extern int dcache_bsize; diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 86d2366ab6a1..cbf154387091 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -52,12 +52,6 @@ */ #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) -/* This indicates that the processor uses the wrong opcode for tlbilx - * instructions. During the ISA 2.06 development the opcode for tlbilx - * changed and some early implementations used to old opcode - */ -#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000) - #ifndef __ASSEMBLY__ #include <asm/cputable.h> diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ef4da37f3c10..640ccbbc0977 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -44,7 +44,6 @@ #define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWX 0x7c00052a #define PPC_INST_TLBILX 0x7c000024 -#define PPC_INST_TLBILX_EARLY 0x7c000626 #define PPC_INST_WAIT 0x7c00007c /* macros to insert fields into opcodes */ @@ -64,18 +63,10 @@ #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ - __PPC_T_TLB(t) | \ - __PPC_RA(a) | __PPC_RB(b)) + __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) - -#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \ - __PPC_T_TLB(t) | \ - __PPC_RA(a) | __PPC_RB(b)) -#define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b) -#define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b) -#define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b) #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ __PPC_WC(w)) diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index f59a66684aed..384d90c9c272 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -4,6 +4,7 @@ #ifndef _ASM_POWERPC_PPC_ASM_H #define _ASM_POWERPC_PPC_ASM_H +#include <linux/init.h> #include <linux/stringify.h> #include <asm/asm-compat.h> #include <asm/processor.h> @@ -189,7 +190,7 @@ name: \ GLUE(.,name): #define _INIT_GLOBAL(name) \ - .section ".text.init.refok"; \ + __REF; \ .align 2 ; \ .globl name; \ .globl GLUE(.,name); \ @@ -229,7 +230,7 @@ name: \ GLUE(.,name): #define _INIT_STATIC(name) \ - .section ".text.init.refok"; \ + __REF; \ .align 2 ; \ .section ".opd","aw"; \ name: \ diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 57db50f40289..cd1b687544f3 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_features = CPU_FTRS_E500MC, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | - MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE, + MMU_FTR_USE_TLBILX, .icache_bsize = 64, .dcache_bsize = 64, .num_pmcs = 4, diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index d7425fffbc1c..a047a6cfca4d 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -54,7 +54,8 @@ SECTIONS ALIGN_FUNCTION(); HEAD_TEXT _text = .; - *(.text .fixup .text.init.refok .exit.text.refok __ftr_alt_*) + /* careful! __ftr_alt_* sections need to be close to .text */ + *(.text .fixup __ftr_alt_* .ref.text) SCHED_TEXT LOCK_TEXT KPROBES_TEXT diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index 45fed3698349..3037911279b1 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -138,11 +138,7 @@ BEGIN_MMU_FTR_SECTION andi. r3,r3,MMUCSR0_TLBFI@l bne 1b MMU_FTR_SECTION_ELSE - BEGIN_MMU_FTR_SECTION_NESTED(96) - PPC_TLBILX_ALL(0,r3) - MMU_FTR_SECTION_ELSE_NESTED(96) - PPC_TLBILX_ALL_EARLY(0,r3) - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) + PPC_TLBILX_ALL(0,0) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync @@ -155,11 +151,7 @@ BEGIN_MMU_FTR_SECTION wrteei 0 mfspr r4,SPRN_MAS6 /* save MAS6 */ mtspr SPRN_MAS6,r3 - BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_PID(0,0) - MMU_FTR_SECTION_ELSE_NESTED(96) - PPC_TLBILX_PID_EARLY(0,0) - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) mtspr SPRN_MAS6,r4 /* restore MAS6 */ wrtee r10 MMU_FTR_SECTION_ELSE @@ -193,16 +185,12 @@ BEGIN_MMU_FTR_SECTION mtspr SPRN_MAS1,r4 tlbwe MMU_FTR_SECTION_ELSE - BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_VA(0,r3) - MMU_FTR_SECTION_ELSE_NESTED(96) - PPC_TLBILX_VA_EARLY(0,r3) - ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync 1: wrtee r10 blr -#elif +#else #error Unsupported processor type ! #endif diff --git a/arch/powerpc/oprofile/op_model_fsl_emb.c b/arch/powerpc/oprofile/op_model_fsl_emb.c index 91596f6ba1f4..62312abffa28 100644 --- a/arch/powerpc/oprofile/op_model_fsl_emb.c +++ b/arch/powerpc/oprofile/op_model_fsl_emb.c @@ -228,20 +228,6 @@ static void pmc_stop_ctrs(void) mtpmr(PMRN_PMGC0, pmgc0); } -static void dump_pmcs(void) -{ - printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0)); - printk("pmc\t\tpmlca\t\tpmlcb\n"); - printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0), - mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0)); - printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1), - mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1)); - printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2), - mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2)); - printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3), - mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3)); -} - static int fsl_emb_cpu_setup(struct op_counter_config *ctr) { int i; diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig index 40e24c39ad06..50f17bdd3c16 100644 --- a/arch/powerpc/platforms/cell/Kconfig +++ b/arch/powerpc/platforms/cell/Kconfig @@ -13,7 +13,6 @@ config PPC_CELL_COMMON config PPC_CELL_NATIVE bool select PPC_CELL_COMMON - select PPC_OF_PLATFORM_PCI select MPIC select IBM_NEW_EMAC_EMAC4 select IBM_NEW_EMAC_RGMII @@ -25,6 +24,8 @@ config PPC_IBM_CELL_BLADE bool "IBM Cell Blade" depends on PPC64 && PPC_BOOK3S select PPC_CELL_NATIVE + select PPC_OF_PLATFORM_PCI + select PCI select MMIO_NVRAM select PPC_UDBG_16550 select UDBG_RTAS_CONSOLE @@ -33,6 +34,8 @@ config PPC_CELLEB bool "Toshiba's Cell Reference Set 'Celleb' Architecture" depends on PPC64 && PPC_BOOK3S select PPC_CELL_NATIVE + select PPC_OF_PLATFORM_PCI + select PCI select HAS_TXX9_SERIAL select PPC_UDBG_BEAT select USB_OHCI_BIG_ENDIAN_MMIO diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c index 65a35f38e062..df83dc972531 100644 --- a/arch/powerpc/platforms/fsl_uli1575.c +++ b/arch/powerpc/platforms/fsl_uli1575.c @@ -51,13 +51,19 @@ u8 uli_pirq_to_irq[8] = { ULI_8259_NONE, /* PIRQH */ }; +static inline bool is_quirk_valid(void) +{ + return (machine_is(mpc86xx_hpcn) || + machine_is(mpc8544_ds) || + machine_is(mpc8572_ds)); +} + /* Bridge */ static void __devinit early_uli5249(struct pci_dev *dev) { unsigned char temp; - if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && - !machine_is(mpc8572_ds)) + if (!is_quirk_valid()) return; pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | @@ -80,8 +86,7 @@ static void __devinit quirk_uli1575(struct pci_dev *dev) { int i; - if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && - !machine_is(mpc8572_ds)) + if (!is_quirk_valid()) return; /* @@ -149,8 +154,7 @@ static void __devinit quirk_final_uli1575(struct pci_dev *dev) * IRQ 14: Edge * IRQ 15: Edge */ - if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && - !machine_is(mpc8572_ds)) + if (!is_quirk_valid()) return; outb(0xfa, 0x4d0); @@ -176,8 +180,7 @@ static void __devinit quirk_uli5288(struct pci_dev *dev) unsigned char c; unsigned int d; - if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && - !machine_is(mpc8572_ds)) + if (!is_quirk_valid()) return; /* read/write lock */ @@ -201,8 +204,7 @@ static void __devinit quirk_uli5229(struct pci_dev *dev) { unsigned short temp; - if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) && - !machine_is(mpc8572_ds)) + if (!is_quirk_valid()) return; pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | @@ -270,7 +272,6 @@ static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev) static void __devinit hpcd_quirk_uli5288(struct pci_dev *dev) { unsigned char c; - unsigned short temp; if (!machine_is(mpc86xx_hpcd)) return; diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c index 66181821322a..1a7b5ae0c83e 100644 --- a/arch/powerpc/platforms/ps3/setup.c +++ b/arch/powerpc/platforms/ps3/setup.c @@ -45,10 +45,6 @@ DEFINE_MUTEX(ps3_gpu_mutex); EXPORT_SYMBOL_GPL(ps3_gpu_mutex); -#if !defined(CONFIG_SMP) -static void smp_send_stop(void) {} -#endif - static union ps3_firmware_version ps3_firmware_version; void ps3_get_firmware_version(union ps3_firmware_version *v) diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index afe8dbc964aa..bd1b74dad739 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c @@ -425,16 +425,10 @@ static int __init setup_rstcr(void) struct device_node *np; np = of_find_node_by_name(NULL, "global-utilities"); if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) { - const u32 *prop = of_get_property(np, "reg", NULL); - if (prop) { - /* map reset control register - * 0xE00B0 is offset of reset control register - */ - rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff); - if (!rstcr) - printk (KERN_EMERG "Error: reset control " - "register not mapped!\n"); - } + rstcr = of_iomap(np, 0) + 0xb0; + if (!rstcr) + printk (KERN_EMERG "Error: reset control register " + "not mapped!\n"); } else printk (KERN_INFO "rstcr compatible register does not exist!\n"); if (np) diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 2eca5fe0e75b..1094787e97e5 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -567,6 +567,24 @@ bool "s390 guest support for KVM (EXPERIMENTAL)" the KVM hypervisor. This will add detection for KVM as well as a virtio transport. If KVM is detected, the virtio console will be the default console. + +config SECCOMP + bool "Enable seccomp to safely compute untrusted bytecode" + depends on PROC_FS + default y + help + This kernel feature is useful for number crunching applications + that may need to compute untrusted bytecode during their + execution. By using pipes or other transports made available to + the process as file descriptors supporting the read/write + syscalls, it's possible to isolate those applications in + their own address space using seccomp. Once seccomp is + enabled via /proc/<pid>/seccomp, it cannot be disabled + and the task is only allowed to execute a few safe syscalls + defined by each seccomp mode. + + If unsure, say Y. + endmenu source "net/Kconfig" diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h index de065b32381a..01a08020bc0e 100644 --- a/arch/s390/include/asm/compat.h +++ b/arch/s390/include/asm/compat.h @@ -5,6 +5,7 @@ */ #include <linux/types.h> #include <linux/sched.h> +#include <linux/thread_info.h> #define PSW32_MASK_PER 0x40000000UL #define PSW32_MASK_DAT 0x04000000UL @@ -163,12 +164,28 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr) return (u32)(unsigned long)uptr; } +#ifdef CONFIG_COMPAT + +static inline int is_compat_task(void) +{ + return test_thread_flag(TIF_31BIT); +} + +#else + +static inline int is_compat_task(void) +{ + return 0; +} + +#endif + static inline void __user *compat_alloc_user_space(long len) { unsigned long stack; stack = KSTK_ESP(current); - if (test_thread_flag(TIF_31BIT)) + if (is_compat_task()) stack &= 0x7fffffffUL; return (void __user *) (stack - len); } diff --git a/arch/s390/include/asm/cpu.h b/arch/s390/include/asm/cpu.h deleted file mode 100644 index d60a2eefb17b..000000000000 --- a/arch/s390/include/asm/cpu.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * include/asm-s390/cpu.h - * - * Copyright IBM Corp. 2007 - * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com> - */ - -#ifndef _ASM_S390_CPU_H_ -#define _ASM_S390_CPU_H_ - -#include <linux/types.h> -#include <linux/percpu.h> -#include <linux/spinlock.h> - -struct s390_idle_data { - spinlock_t lock; - unsigned long long idle_count; - unsigned long long idle_enter; - unsigned long long idle_time; -}; - -DECLARE_PER_CPU(struct s390_idle_data, s390_idle); - -void vtime_start_cpu(void); - -static inline void s390_idle_check(void) -{ - if ((&__get_cpu_var(s390_idle))->idle_enter != 0ULL) - vtime_start_cpu(); -} - -#endif /* _ASM_S390_CPU_H_ */ diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h index 941384fbd39c..ec917d42ee6d 100644 --- a/arch/s390/include/asm/cputime.h +++ b/arch/s390/include/asm/cputime.h @@ -9,6 +9,9 @@ #ifndef _S390_CPUTIME_H #define _S390_CPUTIME_H +#include <linux/types.h> +#include <linux/percpu.h> +#include <linux/spinlock.h> #include <asm/div64.h> /* We want to use full resolution of the CPU timer: 2**-12 micro-seconds. */ @@ -174,8 +177,24 @@ cputime64_to_clock_t(cputime64_t cputime) return __div(cputime, 4096000000ULL / USER_HZ); } +struct s390_idle_data { + spinlock_t lock; + unsigned long long idle_count; + unsigned long long idle_enter; + unsigned long long idle_time; +}; + +DECLARE_PER_CPU(struct s390_idle_data, s390_idle); + +void vtime_start_cpu(void); cputime64_t s390_get_idle_time(int cpu); #define arch_idle_time(cpu) s390_get_idle_time(cpu) +static inline void s390_idle_check(void) +{ + if ((&__get_cpu_var(s390_idle))->idle_enter != 0ULL) + vtime_start_cpu(); +} + #endif /* _S390_CPUTIME_H */ diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h index 3aeca492b147..713fe9fb1fcc 100644 --- a/arch/s390/include/asm/lowcore.h +++ b/arch/s390/include/asm/lowcore.h @@ -30,6 +30,7 @@ #define __LC_SUBCHANNEL_NR 0x00ba #define __LC_IO_INT_PARM 0x00bc #define __LC_IO_INT_WORD 0x00c0 +#define __LC_STFL_FAC_LIST 0x00c8 #define __LC_MCCK_CODE 0x00e8 #define __LC_DUMP_REIPL 0x0e00 diff --git a/arch/s390/include/asm/seccomp.h b/arch/s390/include/asm/seccomp.h new file mode 100644 index 000000000000..781a9cf9b002 --- /dev/null +++ b/arch/s390/include/asm/seccomp.h @@ -0,0 +1,16 @@ +#ifndef _ASM_S390_SECCOMP_H +#define _ASM_S390_SECCOMP_H + +#include <linux/unistd.h> + +#define __NR_seccomp_read __NR_read +#define __NR_seccomp_write __NR_write +#define __NR_seccomp_exit __NR_exit +#define __NR_seccomp_sigreturn __NR_sigreturn + +#define __NR_seccomp_read_32 __NR_read +#define __NR_seccomp_write_32 __NR_write +#define __NR_seccomp_exit_32 __NR_exit +#define __NR_seccomp_sigreturn_32 __NR_sigreturn + +#endif /* _ASM_S390_SECCOMP_H */ diff --git a/arch/s390/include/asm/spinlock.h b/arch/s390/include/asm/spinlock.h index f3861b09ebb0..c9af0d19c7ab 100644 --- a/arch/s390/include/asm/spinlock.h +++ b/arch/s390/include/asm/spinlock.h @@ -122,8 +122,10 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lp) #define __raw_write_can_lock(x) ((x)->lock == 0) extern void _raw_read_lock_wait(raw_rwlock_t *lp); +extern void _raw_read_lock_wait_flags(raw_rwlock_t *lp, unsigned long flags); extern int _raw_read_trylock_retry(raw_rwlock_t *lp); extern void _raw_write_lock_wait(raw_rwlock_t *lp); +extern void _raw_write_lock_wait_flags(raw_rwlock_t *lp, unsigned long flags); extern int _raw_write_trylock_retry(raw_rwlock_t *lp); static inline void __raw_read_lock(raw_rwlock_t *rw) @@ -134,6 +136,14 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) _raw_read_lock_wait(rw); } +static inline void __raw_read_lock_flags(raw_rwlock_t *rw, unsigned long flags) +{ + unsigned int old; + old = rw->lock & 0x7fffffffU; + if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old) + _raw_read_lock_wait_flags(rw, flags); +} + static inline void __raw_read_unlock(raw_rwlock_t *rw) { unsigned int old, cmp; @@ -151,6 +161,12 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) _raw_write_lock_wait(rw); } +static inline void __raw_write_lock_flags(raw_rwlock_t *rw, unsigned long flags) +{ + if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0)) + _raw_write_lock_wait_flags(rw, flags); +} + static inline void __raw_write_unlock(raw_rwlock_t *rw) { _raw_compare_and_swap(&rw->lock, 0x80000000, 0); @@ -172,9 +188,6 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) return _raw_write_trylock_retry(rw); } -#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock) -#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock) - #define _raw_read_relax(lock) cpu_relax() #define _raw_write_relax(lock) cpu_relax() diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h index 461f2abd2e6f..2f86653dda69 100644 --- a/arch/s390/include/asm/thread_info.h +++ b/arch/s390/include/asm/thread_info.h @@ -83,14 +83,15 @@ static inline struct thread_info *current_thread_info(void) /* * thread information flags bit numbers */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ #define TIF_NOTIFY_RESUME 1 /* callback before returning to user */ #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_RESTART_SVC 4 /* restart svc with new svc number */ -#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ #define TIF_SINGLE_STEP 6 /* deliver sigtrap on return to user */ #define TIF_MCCK_PENDING 7 /* machine check handling is pending */ +#define TIF_SYSCALL_TRACE 8 /* syscall trace active */ +#define TIF_SYSCALL_AUDIT 9 /* syscall auditing active */ +#define TIF_SECCOMP 10 /* secure computing */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ @@ -99,15 +100,16 @@ static inline struct thread_info *current_thread_info(void) #define TIF_RESTORE_SIGMASK 20 /* restore signal mask in do_signal() */ #define TIF_FREEZE 21 /* thread is freezing for suspend */ -#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) #define _TIF_RESTART_SVC (1<<TIF_RESTART_SVC) -#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) #define _TIF_SINGLE_STEP (1<<TIF_SINGLE_STEP) #define _TIF_MCCK_PENDING (1<<TIF_MCCK_PENDING) +#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) +#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) +#define _TIF_SECCOMP (1<<TIF_SECCOMP) #define _TIF_USEDFPU (1<<TIF_USEDFPU) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) #define _TIF_31BIT (1<<TIF_31BIT) diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index f3e275934213..db25cdc21e12 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -53,6 +53,7 @@ _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP ) _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ _TIF_MCCK_PENDING) +_TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | _TIF_SECCOMP>>8) STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER STACK_SIZE = 1 << STACK_SHIFT @@ -265,7 +266,7 @@ sysc_do_restart: sth %r7,SP_SVCNR(%r15) sll %r7,2 # svc number *4 l %r8,BASED(.Lsysc_table) - tm __TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) + tm __TI_flags+2(%r9),_TIF_SYSCALL l %r8,0(%r7,%r8) # get system call addr. bnz BASED(sysc_tracesys) basr %r14,%r8 # call sys_xxxx @@ -405,7 +406,7 @@ sysc_tracego: basr %r14,%r8 # call sys_xxx st %r2,SP_R2(%r15) # store return value sysc_tracenogo: - tm __TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) + tm __TI_flags+2(%r9),_TIF_SYSCALL bz BASED(sysc_return) l %r1,BASED(.Ltrace_exit) la %r2,SP_PTREGS(%r15) # load pt_regs diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index 84a105838e03..3cec9b504f5f 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -56,6 +56,7 @@ _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP ) _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ _TIF_MCCK_PENDING) +_TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | _TIF_SECCOMP>>8) #define BASED(name) name-system_call(%r13) @@ -260,7 +261,7 @@ sysc_do_restart: larl %r10,sys_call_table_emu # use 31 bit emulation system calls sysc_noemu: #endif - tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) + tm __TI_flags+6(%r9),_TIF_SYSCALL lgf %r8,0(%r7,%r10) # load address of system call routine jnz sysc_tracesys basr %r14,%r8 # call sys_xxxx @@ -391,7 +392,7 @@ sysc_tracego: basr %r14,%r8 # call sys_xxx stg %r2,SP_R2(%r15) # store return value sysc_tracenogo: - tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT) + tm __TI_flags+6(%r9),_TIF_SYSCALL jz sysc_return la %r2,SP_PTREGS(%r15) # load pt_regs larl %r14,sysc_return # return point is sysc_return diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S index 22596d70fc2e..bf8cf1caeffc 100644 --- a/arch/s390/kernel/head.S +++ b/arch/s390/kernel/head.S @@ -479,27 +479,46 @@ startup:basr %r13,0 # get base mvc __LC_LAST_UPDATE_TIMER(8),6f-.LPG0(%r13) mvc __LC_EXIT_TIMER(8),5f-.LPG0(%r13) #ifndef CONFIG_MARCH_G5 - # check processor version against MARCH_{G5,Z900,Z990,Z9_109,Z10} - stidp __LC_CPUID # store cpuid - lhi %r0,(3f-2f) / 2 - la %r1,2f-.LPG0(%r13) -0: clc __LC_CPUID+4(2),0(%r1) - jne 3f - lpsw 1f-.LPG0(13) # machine type not good enough, crash + # check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10} + xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST + stfl __LC_STFL_FAC_LIST # store facility list + tm __LC_STFL_FAC_LIST,0x01 # stfle available ? + jz 0f + la %r0,0 + .insn s,0xb2b00000,__LC_STFL_FAC_LIST # store facility list extended +0: l %r0,__LC_STFL_FAC_LIST + n %r0,2f+8-.LPG0(%r13) + cl %r0,2f+8-.LPG0(%r13) + jne 1f + l %r0,__LC_STFL_FAC_LIST+4 + n %r0,2f+12-.LPG0(%r13) + cl %r0,2f+12-.LPG0(%r13) + je 3f +1: lpsw 2f-.LPG0(13) # machine type not good enough, crash .align 16 -1: .long 0x000a0000,0x00000000 -2: +2: .long 0x000a0000,0x8badcccc +#if defined(CONFIG_64BIT) +#if defined(CONFIG_MARCH_Z10) + .long 0xc100efe3, 0xf0680000 +#elif defined(CONFIG_MARCH_Z9_109) + .long 0xc100efc3, 0x00000000 +#elif defined(CONFIG_MARCH_Z990) + .long 0xc0002000, 0x00000000 +#elif defined(CONFIG_MARCH_Z900) + .long 0xc0000000, 0x00000000 +#endif +#else #if defined(CONFIG_MARCH_Z10) - .short 0x9672, 0x2064, 0x2066, 0x2084, 0x2086, 0x2094, 0x2096 + .long 0x8100c880, 0x00000000 #elif defined(CONFIG_MARCH_Z9_109) - .short 0x9672, 0x2064, 0x2066, 0x2084, 0x2086 + .long 0x8100c880, 0x00000000 #elif defined(CONFIG_MARCH_Z990) - .short 0x9672, 0x2064, 0x2066 + .long 0x80002000, 0x00000000 #elif defined(CONFIG_MARCH_Z900) - .short 0x9672 + .long 0x80000000, 0x00000000 +#endif #endif -3: la %r1,2(%r1) - brct %r0,0b +3: #endif l %r13,4f-.LPG0(%r13) diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c index 28cf196ba775..015e27da40eb 100644 --- a/arch/s390/kernel/nmi.c +++ b/arch/s390/kernel/nmi.c @@ -16,7 +16,7 @@ #include <asm/lowcore.h> #include <asm/smp.h> #include <asm/etr.h> -#include <asm/cpu.h> +#include <asm/cputime.h> #include <asm/nmi.h> #include <asm/crw.h> diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index a3acd8e60aff..355f7a30c3f1 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -32,6 +32,7 @@ #include <linux/elfcore.h> #include <linux/kernel_stat.h> #include <linux/syscalls.h> +#include <asm/compat.h> #include <asm/uaccess.h> #include <asm/pgtable.h> #include <asm/system.h> @@ -204,7 +205,7 @@ int copy_thread(unsigned long clone_flags, unsigned long new_stackp, save_fp_regs(&p->thread.fp_regs); /* Set a new TLS ? */ if (clone_flags & CLONE_SETTLS) { - if (test_thread_flag(TIF_31BIT)) { + if (is_compat_task()) { p->thread.acrs[0] = (unsigned int) regs->gprs[6]; } else { p->thread.acrs[0] = (unsigned int)(regs->gprs[6] >> 32); diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 75c496f4f16d..b6fc1ae2ffcb 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -36,7 +36,8 @@ #include <linux/elf.h> #include <linux/regset.h> #include <linux/tracehook.h> - +#include <linux/seccomp.h> +#include <asm/compat.h> #include <asm/segment.h> #include <asm/page.h> #include <asm/pgtable.h> @@ -69,7 +70,7 @@ FixPerRegisters(struct task_struct *task) if (per_info->single_step) { per_info->control_regs.bits.starting_addr = 0; #ifdef CONFIG_COMPAT - if (test_thread_flag(TIF_31BIT)) + if (is_compat_task()) per_info->control_regs.bits.ending_addr = 0x7fffffffUL; else #endif @@ -482,8 +483,7 @@ static int peek_user_compat(struct task_struct *child, { __u32 tmp; - if (!test_thread_flag(TIF_31BIT) || - (addr & 3) || addr > sizeof(struct user) - 3) + if (!is_compat_task() || (addr & 3) || addr > sizeof(struct user) - 3) return -EIO; tmp = __peek_user_compat(child, addr); @@ -584,8 +584,7 @@ static int __poke_user_compat(struct task_struct *child, static int poke_user_compat(struct task_struct *child, addr_t addr, addr_t data) { - if (!test_thread_flag(TIF_31BIT) || - (addr & 3) || addr > sizeof(struct user32) - 3) + if (!is_compat_task() || (addr & 3) || addr > sizeof(struct user32) - 3) return -EIO; return __poke_user_compat(child, addr, data); @@ -642,6 +641,9 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) { long ret; + /* Do the secure computing check first. */ + secure_computing(regs->gprs[2]); + /* * The sysc_tracesys code in entry.S stored the system * call number to gprs[2]. @@ -660,7 +662,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs) } if (unlikely(current->audit_context)) - audit_syscall_entry(test_thread_flag(TIF_31BIT) ? + audit_syscall_entry(is_compat_task() ? AUDIT_ARCH_S390 : AUDIT_ARCH_S390X, regs->gprs[2], regs->orig_gpr2, regs->gprs[3], regs->gprs[4], diff --git a/arch/s390/kernel/s390_ext.c b/arch/s390/kernel/s390_ext.c index a0d2d55d7fb3..6b0686d78fc7 100644 --- a/arch/s390/kernel/s390_ext.c +++ b/arch/s390/kernel/s390_ext.c @@ -13,7 +13,7 @@ #include <linux/errno.h> #include <linux/kernel_stat.h> #include <linux/interrupt.h> -#include <asm/cpu.h> +#include <asm/cputime.h> #include <asm/lowcore.h> #include <asm/s390_ext.h> #include <asm/irq_regs.h> diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index 3cf74c3ccb69..062bd64e65fa 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c @@ -26,6 +26,7 @@ #include <linux/binfmts.h> #include <linux/tracehook.h> #include <linux/syscalls.h> +#include <linux/compat.h> #include <asm/ucontext.h> #include <asm/uaccess.h> #include <asm/lowcore.h> @@ -482,7 +483,7 @@ void do_signal(struct pt_regs *regs) /* Whee! Actually deliver the signal. */ int ret; #ifdef CONFIG_COMPAT - if (test_thread_flag(TIF_31BIT)) { + if (is_compat_task()) { ret = handle_signal32(signr, &ka, &info, oldset, regs); } else diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index a985a3ba4401..0af302ceac2d 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -47,7 +47,7 @@ #include <asm/timer.h> #include <asm/lowcore.h> #include <asm/sclp.h> -#include <asm/cpu.h> +#include <asm/cputime.h> #include <asm/vdso.h> #include "entry.h" diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c index 89b2e7f1b7a9..dacb09ed8672 100644 --- a/arch/s390/kernel/vdso.c +++ b/arch/s390/kernel/vdso.c @@ -22,7 +22,7 @@ #include <linux/elf.h> #include <linux/security.h> #include <linux/bootmem.h> - +#include <linux/compat.h> #include <asm/pgtable.h> #include <asm/system.h> #include <asm/processor.h> @@ -203,7 +203,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) vdso_pagelist = vdso64_pagelist; vdso_pages = vdso64_pages; #ifdef CONFIG_COMPAT - if (test_thread_flag(TIF_31BIT)) { + if (is_compat_task()) { vdso_pagelist = vdso32_pagelist; vdso_pages = vdso32_pages; } diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c index c87f59bd8246..c8eb7255332b 100644 --- a/arch/s390/kernel/vtime.c +++ b/arch/s390/kernel/vtime.c @@ -23,7 +23,7 @@ #include <asm/s390_ext.h> #include <asm/timer.h> #include <asm/irq_regs.h> -#include <asm/cpu.h> +#include <asm/cputime.h> static ext_int_info_t ext_int_info_timer; diff --git a/arch/s390/lib/spinlock.c b/arch/s390/lib/spinlock.c index e41f4008afc5..f7e0d30250b7 100644 --- a/arch/s390/lib/spinlock.c +++ b/arch/s390/lib/spinlock.c @@ -124,6 +124,27 @@ void _raw_read_lock_wait(raw_rwlock_t *rw) } EXPORT_SYMBOL(_raw_read_lock_wait); +void _raw_read_lock_wait_flags(raw_rwlock_t *rw, unsigned long flags) +{ + unsigned int old; + int count = spin_retry; + + local_irq_restore(flags); + while (1) { + if (count-- <= 0) { + _raw_yield(); + count = spin_retry; + } + if (!__raw_read_can_lock(rw)) + continue; + old = rw->lock & 0x7fffffffU; + local_irq_disable(); + if (_raw_compare_and_swap(&rw->lock, old, old + 1) == old) + return; + } +} +EXPORT_SYMBOL(_raw_read_lock_wait_flags); + int _raw_read_trylock_retry(raw_rwlock_t *rw) { unsigned int old; @@ -157,6 +178,25 @@ void _raw_write_lock_wait(raw_rwlock_t *rw) } EXPORT_SYMBOL(_raw_write_lock_wait); +void _raw_write_lock_wait_flags(raw_rwlock_t *rw, unsigned long flags) +{ + int count = spin_retry; + + local_irq_restore(flags); + while (1) { + if (count-- <= 0) { + _raw_yield(); + count = spin_retry; + } + if (!__raw_write_can_lock(rw)) + continue; + local_irq_disable(); + if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0) + return; + } +} +EXPORT_SYMBOL(_raw_write_lock_wait_flags); + int _raw_write_trylock_retry(raw_rwlock_t *rw) { int count = spin_retry; diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 833e8366c351..220a152c836c 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -19,6 +19,7 @@ #include <linux/ptrace.h> #include <linux/mman.h> #include <linux/mm.h> +#include <linux/compat.h> #include <linux/smp.h> #include <linux/kdebug.h> #include <linux/smp_lock.h> @@ -239,7 +240,7 @@ static int signal_return(struct mm_struct *mm, struct pt_regs *regs, up_read(&mm->mmap_sem); clear_tsk_thread_flag(current, TIF_SINGLE_STEP); #ifdef CONFIG_COMPAT - compat = test_tsk_thread_flag(current, TIF_31BIT); + compat = is_compat_task(); if (compat && instruction == 0x0a77) sys32_sigreturn(); else if (compat && instruction == 0x0aad) diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c index e008d236cc15..f4558ccf02b9 100644 --- a/arch/s390/mm/mmap.c +++ b/arch/s390/mm/mmap.c @@ -28,6 +28,7 @@ #include <linux/mm.h> #include <linux/module.h> #include <asm/pgalloc.h> +#include <asm/compat.h> /* * Top of mmap area (just below the process stack). @@ -55,7 +56,7 @@ static inline int mmap_is_legacy(void) /* * Force standard allocation for 64 bit programs. */ - if (!test_thread_flag(TIF_31BIT)) + if (!is_compat_task()) return 1; #endif return sysctl_legacy_va_layout || @@ -91,7 +92,7 @@ EXPORT_SYMBOL_GPL(arch_pick_mmap_layout); int s390_mmap_check(unsigned long addr, unsigned long len) { - if (!test_thread_flag(TIF_31BIT) && + if (!is_compat_task() && len >= TASK_SIZE && TASK_SIZE < (1UL << 53)) return crst_table_upgrade(current->mm, 1UL << 53); return 0; @@ -108,8 +109,7 @@ s390_get_unmapped_area(struct file *filp, unsigned long addr, area = arch_get_unmapped_area(filp, addr, len, pgoff, flags); if (!(area & ~PAGE_MASK)) return area; - if (area == -ENOMEM && - !test_thread_flag(TIF_31BIT) && TASK_SIZE < (1UL << 53)) { + if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < (1UL << 53)) { /* Upgrade the page table to 4 levels and retry. */ rc = crst_table_upgrade(mm, 1UL << 53); if (rc) @@ -131,8 +131,7 @@ s390_get_unmapped_area_topdown(struct file *filp, const unsigned long addr, area = arch_get_unmapped_area_topdown(filp, addr, len, pgoff, flags); if (!(area & ~PAGE_MASK)) return area; - if (area == -ENOMEM && - !test_thread_flag(TIF_31BIT) && TASK_SIZE < (1UL << 53)) { + if (area == -ENOMEM && !is_compat_task() && TASK_SIZE < (1UL << 53)) { /* Upgrade the page table to 4 levels and retry. */ rc = crst_table_upgrade(mm, 1UL << 53); if (rc) diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h index d3f6caa936b0..68e20ff9aa9b 100644 --- a/arch/sh/include/asm/ptrace.h +++ b/arch/sh/include/asm/ptrace.h @@ -9,7 +9,7 @@ struct pt_regs { unsigned long long pc; unsigned long long sr; - unsigned long long syscall_nr; + long long syscall_nr; unsigned long long regs[63]; unsigned long long tregs[8]; unsigned long long pad[2]; diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S index e640c63d5811..7e49cb812f8b 100644 --- a/arch/sh/kernel/cpu/sh5/entry.S +++ b/arch/sh/kernel/cpu/sh5/entry.S @@ -10,6 +10,7 @@ * for more details. */ #include <linux/errno.h> +#include <linux/init.h> #include <linux/sys.h> #include <cpu/registers.h> #include <asm/processor.h> @@ -2058,10 +2059,10 @@ asm_uaccess_end: /* - * --- .text.init Section + * --- .init.text Section */ - .section .text.init, "ax" + __INIT /* * void trap_init (void) diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S index e91f01a57598..6b4d8acc4c83 100644 --- a/arch/sparc/kernel/head_32.S +++ b/arch/sparc/kernel/head_32.S @@ -735,7 +735,7 @@ go_to_highmem: nop /* The code above should be at beginning and we have to take care about - * short jumps, as branching to .text.init section from .text is usually + * short jumps, as branching to .init.text section from .text is usually * impossible */ __INIT /* Acquire boot time privileged register values, this will help debugging. diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S index 3a1b7bf03cff..91bf4c7f79b9 100644 --- a/arch/sparc/kernel/head_64.S +++ b/arch/sparc/kernel/head_64.S @@ -467,7 +467,7 @@ jump_to_sun4u_init: jmpl %g2 + %g0, %g0 nop - .section .text.init.refok + __REF sun4u_init: BRANCH_IF_SUN4V(g1, sun4v_init) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c9086e6307a5..df9e885eee14 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -277,6 +277,7 @@ config SPARSE_IRQ config NUMA_MIGRATE_IRQ_DESC bool "Move irq desc when changing irq smp_affinity" depends on SPARSE_IRQ && NUMA + depends on BROKEN default n ---help--- This enables moving irq_desc to cpu/node that irq will use handled. @@ -664,6 +665,7 @@ config MAXSMP config NR_CPUS int "Maximum number of CPUs" if SMP && !MAXSMP + range 2 8 if SMP && X86_32 && !X86_BIGSMP range 2 512 if SMP && !MAXSMP default "1" if !SMP default "4096" if MAXSMP diff --git a/arch/x86/Makefile b/arch/x86/Makefile index f05d8c91d9e5..8c86b72afdc2 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -153,7 +153,7 @@ endif boot := arch/x86/boot -BOOT_TARGETS = bzlilo bzdisk fdimage fdimage144 fdimage288 isoimage install +BOOT_TARGETS = bzlilo bzdisk fdimage fdimage144 fdimage288 isoimage PHONY += bzImage $(BOOT_TARGETS) @@ -171,6 +171,10 @@ bzImage: vmlinux $(BOOT_TARGETS): vmlinux $(Q)$(MAKE) $(build)=$(boot) $@ +PHONY += install +install: + $(Q)$(MAKE) $(build)=$(boot) $@ + PHONY += vdso_install vdso_install: $(Q)$(MAKE) $(build)=arch/x86/vdso $@ diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 892b119dba6f..f44b49abca49 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -200,7 +200,7 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) } struct pci_bus; -void set_pci_bus_resources_arch_default(struct pci_bus *b); +void x86_pci_root_bus_res_quirks(struct pci_bus *b); #ifdef CONFIG_SMP #define mc_capable() (cpumask_weight(cpu_core_mask(0)) != nr_cpu_ids) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index a2789e42e162..30da617d18e4 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -3670,12 +3670,14 @@ int arch_setup_hpet_msi(unsigned int irq) { int ret; struct msi_msg msg; + struct irq_desc *desc = irq_to_desc(irq); ret = msi_compose_msg(NULL, irq, &msg); if (ret < 0) return ret; hpet_msi_write(irq, &msg); + desc->status |= IRQ_MOVE_PCNTXT; set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, "edge"); diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c index d6bd62407152..ce4fbfa315a1 100644 --- a/arch/x86/kernel/apic/nmi.c +++ b/arch/x86/kernel/apic/nmi.c @@ -138,7 +138,7 @@ int __init check_nmi_watchdog(void) if (!prev_nmi_count) goto error; - alloc_cpumask_var(&backtrace_mask, GFP_KERNEL); + alloc_cpumask_var(&backtrace_mask, GFP_KERNEL|__GFP_ZERO); printk(KERN_INFO "Testing NMI watchdog ... "); #ifdef CONFIG_SMP @@ -414,7 +414,8 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason) touched = 1; } - if (cpumask_test_cpu(cpu, backtrace_mask)) { + /* We can be called before check_nmi_watchdog, hence NULL check. */ + if (backtrace_mask != NULL && cpumask_test_cpu(cpu, backtrace_mask)) { static DEFINE_SPINLOCK(lock); /* Serialise the printks */ spin_lock(&lock); diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index de1a50af807b..2bda69352976 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -19,6 +19,7 @@ #include <linux/timer.h> #include <linux/cpu.h> #include <linux/init.h> +#include <linux/io.h> #include <asm/uv/uv_mmrs.h> #include <asm/uv/uv_hub.h> @@ -34,6 +35,17 @@ DEFINE_PER_CPU(int, x2apic_extra_bits); static enum uv_system_type uv_system_type; +static int early_get_nodeid(void) +{ + union uvh_node_id_u node_id; + unsigned long *mmr; + + mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr)); + node_id.v = *mmr; + early_iounmap(mmr, sizeof(*mmr)); + return node_id.s.node_id; +} + static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) { if (!strcmp(oem_id, "SGI")) { @@ -42,6 +54,8 @@ static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) else if (!strcmp(oem_table_id, "UVX")) uv_system_type = UV_X2APIC; else if (!strcmp(oem_table_id, "UVH")) { + __get_cpu_var(x2apic_extra_bits) = + early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1); uv_system_type = UV_NON_UNIQUE_APIC; return 1; } @@ -638,6 +652,7 @@ void __init uv_system_init(void) if (uv_node_to_blade[nid] >= 0) continue; paddr = node_start_pfn(nid) << PAGE_SHIFT; + paddr = uv_soc_phys_ram_to_gpa(paddr); pnode = (paddr >> m_val) & pnode_mask; blade = boot_pnode_to_blade(pnode); uv_node_to_blade[nid] = blade; diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c index 6ac55bd341ae..869615193720 100644 --- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c +++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c @@ -168,6 +168,7 @@ static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c) case 0x0E: /* Core */ case 0x0F: /* Core Duo */ case 0x16: /* Celeron Core */ + case 0x1C: /* Atom */ p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE); case 0x0D: /* Pentium M (Dothan) */ diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c index 3c28ccd49742..a8363e5be4ef 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c @@ -168,10 +168,12 @@ static int check_powernow(void) return 1; } +#ifdef CONFIG_X86_POWERNOW_K7_ACPI static void invalidate_entry(unsigned int entry) { powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID; } +#endif static int get_ranges(unsigned char *pst) { diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index a331ec38af9e..38946c6e8433 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S @@ -1410,7 +1410,10 @@ ENTRY(paranoid_exit) paranoid_swapgs: TRACE_IRQS_IRETQ 0 SWAPGS_UNSAFE_STACK + RESTORE_ALL 8 + jmp irq_return paranoid_restore: + TRACE_IRQS_IRETQ 0 RESTORE_ALL 8 jmp irq_return paranoid_userspace: diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 3f0019e0a229..81408b93f887 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -236,6 +236,10 @@ static void hpet_stop_counter(void) unsigned long cfg = hpet_readl(HPET_CFG); cfg &= ~HPET_CFG_ENABLE; hpet_writel(cfg, HPET_CFG); +} + +static void hpet_reset_counter(void) +{ hpet_writel(0, HPET_COUNTER); hpet_writel(0, HPET_COUNTER + 4); } @@ -250,6 +254,7 @@ static void hpet_start_counter(void) static void hpet_restart_counter(void) { hpet_stop_counter(); + hpet_reset_counter(); hpet_start_counter(); } @@ -309,7 +314,7 @@ static int hpet_setup_msi_irq(unsigned int irq); static void hpet_set_mode(enum clock_event_mode mode, struct clock_event_device *evt, int timer) { - unsigned long cfg; + unsigned long cfg, cmp, now; uint64_t delta; switch (mode) { @@ -317,12 +322,23 @@ static void hpet_set_mode(enum clock_event_mode mode, hpet_stop_counter(); delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; delta >>= evt->shift; + now = hpet_readl(HPET_COUNTER); + cmp = now + (unsigned long) delta; cfg = hpet_readl(HPET_Tn_CFG(timer)); /* Make sure we use edge triggered interrupts */ cfg &= ~HPET_TN_LEVEL; cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | HPET_TN_32BIT; hpet_writel(cfg, HPET_Tn_CFG(timer)); + hpet_writel(cmp, HPET_Tn_CMP(timer)); + udelay(1); + /* + * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL + * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL + * bit is automatically cleared after the first write. + * (See AMD-8111 HyperTransport I/O Hub Data Sheet, + * Publication # 24674) + */ hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); hpet_start_counter(); hpet_print_config(); diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index e95022e4f5d5..7563b31b4f03 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c @@ -261,8 +261,6 @@ static void old_ich_force_enable_hpet_user(struct pci_dev *dev) { if (hpet_force_user) old_ich_force_enable_hpet(dev); - else - hpet_print_force_info(); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, diff --git a/arch/x86/kernel/uv_time.c b/arch/x86/kernel/uv_time.c index 2ffb6c53326e..583f11d5c480 100644 --- a/arch/x86/kernel/uv_time.c +++ b/arch/x86/kernel/uv_time.c @@ -29,7 +29,7 @@ #define RTC_NAME "sgi_rtc" -static cycle_t uv_read_rtc(void); +static cycle_t uv_read_rtc(struct clocksource *cs); static int uv_rtc_next_event(unsigned long, struct clock_event_device *); static void uv_rtc_timer_setup(enum clock_event_mode, struct clock_event_device *); @@ -123,7 +123,7 @@ static int uv_setup_intr(int cpu, u64 expires) /* Initialize comparator value */ uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires); - return (expires < uv_read_rtc() && !uv_intr_pending(pnode)); + return (expires < uv_read_rtc(NULL) && !uv_intr_pending(pnode)); } /* @@ -256,7 +256,7 @@ static int uv_rtc_unset_timer(int cpu) spin_lock_irqsave(&head->lock, flags); - if (head->next_cpu == bcpu && uv_read_rtc() >= *t) + if (head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) rc = 1; *t = ULLONG_MAX; @@ -278,7 +278,7 @@ static int uv_rtc_unset_timer(int cpu) /* * Read the RTC. */ -static cycle_t uv_read_rtc(void) +static cycle_t uv_read_rtc(struct clocksource *cs) { return (cycle_t)uv_read_local_mmr(UVH_RTC); } @@ -291,7 +291,7 @@ static int uv_rtc_next_event(unsigned long delta, { int ced_cpu = cpumask_first(ced->cpumask); - return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc()); + return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL)); } /* diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c index 0a5b04aa98f1..c5ee17e8c6d9 100644 --- a/arch/x86/kernel/xsave.c +++ b/arch/x86/kernel/xsave.c @@ -89,7 +89,7 @@ int save_i387_xstate(void __user *buf) if (!used_math()) return 0; - clear_used_math(); /* trigger finit */ + if (task_thread_info(tsk)->status & TS_USEDFPU) { /* * Start with clearing the user buffer. This will present a @@ -114,6 +114,8 @@ int save_i387_xstate(void __user *buf) return -1; } + clear_used_math(); /* trigger finit */ + if (task_thread_info(tsk)->status & TS_XSAVE) { struct _fpstate __user *fx = buf; struct _xstate __user *x = buf; diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c index 3daefa04ace5..d2530062fe00 100644 --- a/arch/x86/mm/numa_32.c +++ b/arch/x86/mm/numa_32.c @@ -257,7 +257,7 @@ void resume_map_numa_kva(pgd_t *pgd_base) } #endif -static unsigned long calculate_numa_remap_pages(void) +static __init unsigned long calculate_numa_remap_pages(void) { int nid; unsigned long size, reserve_pages = 0; diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c index d73aaa892371..2d05a12029dc 100644 --- a/arch/x86/mm/numa_64.c +++ b/arch/x86/mm/numa_64.c @@ -188,6 +188,9 @@ void __init setup_node_bootmem(int nodeid, unsigned long start, const int pgdat_size = roundup(sizeof(pg_data_t), PAGE_SIZE); int nid; + if (!end) + return; + start = roundup(start, ZONE_ALIGN); printk(KERN_INFO "Bootmem setup node %d %016lx-%016lx\n", nodeid, diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c index c7d272b8574c..33c5fa57e43d 100644 --- a/arch/x86/mm/srat_64.c +++ b/arch/x86/mm/srat_64.c @@ -28,6 +28,7 @@ int acpi_numa __initdata; static struct acpi_table_slit *acpi_slit; static nodemask_t nodes_parsed __initdata; +static nodemask_t cpu_nodes_parsed __initdata; static struct bootnode nodes[MAX_NUMNODES] __initdata; static struct bootnode nodes_add[MAX_NUMNODES]; static int found_add_area __initdata; @@ -141,6 +142,7 @@ acpi_numa_x2apic_affinity_init(struct acpi_srat_x2apic_cpu_affinity *pa) apic_id = pa->apic_id; apicid_to_node[apic_id] = node; + node_set(node, cpu_nodes_parsed); acpi_numa = 1; printk(KERN_INFO "SRAT: PXM %u -> APIC %u -> Node %u\n", pxm, apic_id, node); @@ -174,6 +176,7 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *pa) else apic_id = pa->apic_id; apicid_to_node[apic_id] = node; + node_set(node, cpu_nodes_parsed); acpi_numa = 1; printk(KERN_INFO "SRAT: PXM %u -> APIC %u -> Node %u\n", pxm, apic_id, node); @@ -402,7 +405,8 @@ int __init acpi_scan_nodes(unsigned long start, unsigned long end) return -1; } - node_possible_map = nodes_parsed; + /* Account for nodes with cpus and no memory */ + nodes_or(node_possible_map, nodes_parsed, cpu_nodes_parsed); /* Finally register nodes */ for_each_node_mask(i, node_possible_map) diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c index 9bb09823b362..f893d6a6e803 100644 --- a/arch/x86/pci/amd_bus.c +++ b/arch/x86/pci/amd_bus.c @@ -94,12 +94,16 @@ struct pci_root_info { static int pci_root_num; static struct pci_root_info pci_root_info[PCI_ROOT_NR]; -void set_pci_bus_resources_arch_default(struct pci_bus *b) +void x86_pci_root_bus_res_quirks(struct pci_bus *b) { int i; int j; struct pci_root_info *info; + /* don't go for it if _CRS is used */ + if (pci_probe & PCI_USE__CRS) + return; + /* if only one root bus, don't need to anything */ if (pci_root_num < 2) return; diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 8c362b96b644..2202b6257b82 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -147,10 +147,13 @@ static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) * are examined. */ -void __devinit pcibios_fixup_bus(struct pci_bus *b) +void __devinit pcibios_fixup_bus(struct pci_bus *b) { struct pci_dev *dev; + /* root bus? */ + if (!b->parent) + x86_pci_root_bus_res_quirks(b); pci_read_bridge_bases(b); list_for_each_entry(dev, &b->devices, bus_list) pcibios_fixup_device_resources(dev); diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index f1817f71e009..a85bef20a3b9 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c @@ -238,6 +238,10 @@ void __init pcibios_resource_survey(void) */ fs_initcall(pcibios_assign_resources); +void __weak x86_pci_root_bus_res_quirks(struct pci_bus *b) +{ +} + /* * If we set up a device for bus mastering, we need to check the latency * timer as certain crappy BIOSes forget to set it properly. diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 905bb526b133..5fa10bb9604f 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -375,7 +375,7 @@ static acpi_status __init check_mcfg_resource(struct acpi_resource *res, if (!fixmem32) return AE_OK; if ((mcfg_res->start >= fixmem32->address) && - (mcfg_res->end < (fixmem32->address + + (mcfg_res->end <= (fixmem32->address + fixmem32->address_length))) { mcfg_res->flags = 1; return AE_CTRL_TERMINATE; @@ -392,7 +392,7 @@ static acpi_status __init check_mcfg_resource(struct acpi_resource *res, return AE_OK; if ((mcfg_res->start >= address.minimum) && - (mcfg_res->end < (address.minimum + address.address_length))) { + (mcfg_res->end <= (address.minimum + address.address_length))) { mcfg_res->flags = 1; return AE_CTRL_TERMINATE; } @@ -439,7 +439,7 @@ static int __init is_mmconf_reserved(check_reserved_t is_reserved, u64 old_size = size; int valid = 0; - while (!is_reserved(addr, addr + size - 1, E820_RESERVED)) { + while (!is_reserved(addr, addr + size, E820_RESERVED)) { size >>= 1; if (size < (16UL<<20)) break; |