diff options
Diffstat (limited to 'arch')
463 files changed, 8735 insertions, 6825 deletions
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c index 376f22130791..326f0a2d56e5 100644 --- a/arch/alpha/kernel/osf_sys.c +++ b/arch/alpha/kernel/osf_sys.c @@ -409,7 +409,7 @@ SYSCALL_DEFINE2(osf_getdomainname, char __user *, name, int, namelen) return -EFAULT; len = namelen; - if (namelen > 32) + if (len > 32) len = 32; down_read(&uts_sem); @@ -594,7 +594,7 @@ SYSCALL_DEFINE3(osf_sysinfo, int, command, char __user *, buf, long, count) down_read(&uts_sem); res = sysinfo_table[offset]; len = strlen(res)+1; - if (len > count) + if ((unsigned long)len > (unsigned long)count) len = count; if (copy_to_user(buf, res, len)) err = -EFAULT; @@ -649,7 +649,7 @@ SYSCALL_DEFINE5(osf_getsysinfo, unsigned long, op, void __user *, buffer, return 1; case GSI_GET_HWRPB: - if (nbytes < sizeof(*hwrpb)) + if (nbytes > sizeof(*hwrpb)) return -EINVAL; if (copy_to_user(buffer, hwrpb, nbytes) != 0) return -EFAULT; @@ -1008,6 +1008,7 @@ SYSCALL_DEFINE4(osf_wait4, pid_t, pid, int __user *, ustatus, int, options, { struct rusage r; long ret, err; + unsigned int status = 0; mm_segment_t old_fs; if (!ur) @@ -1016,13 +1017,15 @@ SYSCALL_DEFINE4(osf_wait4, pid_t, pid, int __user *, ustatus, int, options, old_fs = get_fs(); set_fs (KERNEL_DS); - ret = sys_wait4(pid, ustatus, options, (struct rusage __user *) &r); + ret = sys_wait4(pid, (unsigned int __user *) &status, options, + (struct rusage __user *) &r); set_fs (old_fs); if (!access_ok(VERIFY_WRITE, ur, sizeof(*ur))) return -EFAULT; err = 0; + err |= put_user(status, ustatus); err |= __put_user(r.ru_utime.tv_sec, &ur->ru_utime.tv_sec); err |= __put_user(r.ru_utime.tv_usec, &ur->ru_utime.tv_usec); err |= __put_user(r.ru_stime.tv_sec, &ur->ru_stime.tv_sec); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9adc278a22ab..071b82b583d4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -37,6 +37,9 @@ config ARM Europe. There is an ARM Linux project with a web page at <http://www.arm.linux.org.uk/>. +config ARM_HAS_SG_CHAIN + bool + config HAVE_PWM bool @@ -376,6 +379,7 @@ config ARCH_MXC select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO + select GENERIC_IRQ_CHIP select HAVE_SCHED_CLOCK help Support for Freescale MXC/iMX-based family of processors @@ -682,6 +686,7 @@ config ARCH_S3C2410 select GENERIC_GPIO select ARCH_HAS_CPUFREQ select HAVE_CLK + select CLKDEV_LOOKUP select ARCH_USES_GETTIMEOFFSET select HAVE_S3C2410_I2C if I2C help @@ -699,6 +704,7 @@ config ARCH_S3C64XX select CPU_V6 select ARM_VIC select HAVE_CLK + select CLKDEV_LOOKUP select NO_IOPORT select ARCH_USES_GETTIMEOFFSET select ARCH_HAS_CPUFREQ @@ -723,6 +729,7 @@ config ARCH_S5P64X0 select CPU_V6 select GENERIC_GPIO select HAVE_CLK + select CLKDEV_LOOKUP select HAVE_S3C2410_WATCHDOG if WATCHDOG select GENERIC_CLOCKEVENTS select HAVE_SCHED_CLOCK @@ -736,6 +743,7 @@ config ARCH_S5PC100 bool "Samsung S5PC100" select GENERIC_GPIO select HAVE_CLK + select CLKDEV_LOOKUP select CPU_V7 select ARM_L1_CACHE_SHIFT_6 select ARCH_USES_GETTIMEOFFSET @@ -751,6 +759,7 @@ config ARCH_S5PV210 select ARCH_SPARSEMEM_ENABLE select GENERIC_GPIO select HAVE_CLK + select CLKDEV_LOOKUP select ARM_L1_CACHE_SHIFT_6 select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS @@ -767,6 +776,7 @@ config ARCH_EXYNOS4 select ARCH_SPARSEMEM_ENABLE select GENERIC_GPIO select HAVE_CLK + select CLKDEV_LOOKUP select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS select HAVE_S3C_RTC if RTC_CLASS @@ -879,6 +889,20 @@ config ARCH_VT8500 select HAVE_PWM help Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. + +config ARCH_ZYNQ + bool "Xilinx Zynq ARM Cortex A9 Platform" + select CPU_V7 + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select CLKDEV_LOOKUP + select ARM_GIC + select ARM_AMBA + select ICST + select USE_OF + help + Support for Xilinx Zynq ARM Cortex A9 Platform + endchoice # @@ -1765,7 +1789,7 @@ endchoice config XIP_KERNEL bool "Kernel Execute-In-Place from ROM" - depends on !ZBOOT_ROM + depends on !ZBOOT_ROM && !ARM_LPAE help Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM diff --git a/arch/arm/Makefile b/arch/arm/Makefile index f5b2b390c8f2..999c17aa8571 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -196,6 +196,7 @@ machine-$(CONFIG_MACH_SPEAR300) := spear3xx machine-$(CONFIG_MACH_SPEAR310) := spear3xx machine-$(CONFIG_MACH_SPEAR320) := spear3xx machine-$(CONFIG_MACH_SPEAR600) := spear6xx +machine-$(CONFIG_ARCH_ZYNQ) := zynq # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. @@ -203,6 +204,7 @@ plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_S3C64XX) := samsung plat-$(CONFIG_ARCH_TCC_926) := tcc +plat-$(CONFIG_ARCH_ZYNQ) := versatile plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_ORION) := orion diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index f9da41921c52..897d257dfa28 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -550,6 +550,7 @@ __armv7_mmu_cache_on: mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control #endif + mcr p15, 0, r0, c7, c5, 4 @ ISB mcr p15, 0, r0, c1, c0, 0 @ load control register mrc p15, 0, r0, c1, c0, 0 @ and read it back mov r0, #0 @@ -691,9 +692,9 @@ proc_types: .word 0x41069260 @ ARM926EJ-S (v5TEJ) .word 0xff0ffff0 - b __arm926ejs_mmu_cache_on - b __armv4_mmu_cache_off - b __armv5tej_mmu_cache_flush + W(b) __arm926ejs_mmu_cache_on + W(b) __armv4_mmu_cache_off + W(b) __armv5tej_mmu_cache_flush .word 0x00007000 @ ARM7 IDs .word 0x0000f000 diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts new file mode 100644 index 000000000000..37ca192fb193 --- /dev/null +++ b/arch/arm/boot/dts/zynq-ep107.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/ { + model = "Xilinx Zynq EP107"; + compatible = "xlnx,zynq-ep107"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk"; + linux,stdout-path = &uart0; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f8f01000 { + interrupt-controller; + compatible = "arm,gic"; + reg = <0xF8F01000 0x1000>; + #interrupt-cells = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + reg = <0xE0000000 0x1000>; + interrupts = <59 0>; + clock = <50000000>; + }; + }; +}; diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 889922ad229c..67b5abb6f857 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -157,7 +157,7 @@ CONFIG_LEDS_GPIO=m CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_XFS_FS=m diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig index 0ace16cba9b5..88c5802a2351 100644 --- a/arch/arm/configs/mx51_defconfig +++ b/arch/arm/configs/mx51_defconfig @@ -106,6 +106,7 @@ CONFIG_GPIO_SYSFS=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_BLOCK=m CONFIG_MMC_SDHCI=m @@ -145,7 +146,7 @@ CONFIG_ROOT_NFS=y CONFIG_NLS_DEFAULT="cp437" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y CONFIG_MAGIC_SYSRQ=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 2bf224310fb4..db2cb7d180dc 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -22,6 +22,8 @@ CONFIG_BLK_DEV_INTEGRITY=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_MXS=y +CONFIG_MACH_MX23EVK=y +CONFIG_MACH_MX28EVK=y CONFIG_MACH_STMP378X_DEVB=y CONFIG_MACH_TX28=y # CONFIG_ARM_THUMB is not set @@ -89,7 +91,7 @@ CONFIG_DISPLAY_SUPPORT=m # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_MXS=y -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=m CONFIG_DMADEVICES=y CONFIG_MXS_DMA=y diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig index 316af5479d90..9c0ad7993986 100644 --- a/arch/arm/configs/netx_defconfig +++ b/arch/arm/configs/netx_defconfig @@ -60,7 +60,7 @@ CONFIG_FB_ARMCLCD=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index a5cce242a775..e1d602029a4d 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -67,7 +67,11 @@ CONFIG_AB8500_CORE=y CONFIG_REGULATOR=y CONFIG_REGULATOR_AB8500=y # CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_GADGET=y +CONFIG_AB8500_USB=y CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y CONFIG_NEW_LEDS=y diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig index 8b0c717378fa..1d01ddd33122 100644 --- a/arch/arm/configs/viper_defconfig +++ b/arch/arm/configs/viper_defconfig @@ -142,7 +142,7 @@ CONFIG_USB_GADGETFS=m CONFIG_USB_FILE_STORAGE=m CONFIG_USB_G_SERIAL=m CONFIG_USB_G_PRINTER=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_SA1100=m CONFIG_EXT2_FS=m diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig index 5b5504143647..721832ffe2d7 100644 --- a/arch/arm/configs/xcep_defconfig +++ b/arch/arm/configs/xcep_defconfig @@ -73,7 +73,7 @@ CONFIG_SENSORS_MAX6650=m # CONFIG_VGA_CONSOLE is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_SA1100=m CONFIG_DMADEVICES=y # CONFIG_DNOTIFY is not set diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig index 960f65514d88..59577ad3f4ef 100644 --- a/arch/arm/configs/zeus_defconfig +++ b/arch/arm/configs/zeus_defconfig @@ -158,7 +158,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_ISL1208=m CONFIG_RTC_DRV_PXA=m CONFIG_EXT2_FS=y diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index bc2d2d75f706..2bcc456b6879 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -184,6 +184,17 @@ #endif /* + * Instruction barrier + */ + .macro instr_sync +#if __LINUX_ARM_ARCH__ >= 7 + isb +#elif __LINUX_ARM_ARCH__ == 6 + mcr p15, 0, r0, c7, c5, 4 +#endif + .endm + +/* * SMP data memory barrier */ .macro smp_dmb mode diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 4fff837363ed..385f0b3a10d2 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -230,8 +230,7 @@ int dma_mmap_coherent(struct device *, struct vm_area_struct *, extern void *dma_alloc_writecombine(struct device *, size_t, dma_addr_t *, gfp_t); -#define dma_free_writecombine(dev,size,cpu_addr,handle) \ - dma_free_coherent(dev,size,cpu_addr,handle) +extern void dma_free_writecombine(struct device *, size_t, void *, dma_addr_t); int dma_mmap_writecombine(struct device *, struct vm_area_struct *, void *, dma_addr_t, size_t); diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index d2fedb5aeb1f..3845215404dd 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -29,6 +29,8 @@ struct map_desc { #define MT_MEMORY_NONCACHED 11 #define MT_MEMORY_DTCM 12 #define MT_MEMORY_ITCM 13 +#define MT_DMA_COHERENT 14 +#define MT_WC_COHERENT 15 #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index af44a8fb3480..bbb7c49d4b61 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -88,6 +88,13 @@ #define CONSISTENT_END (0xffe00000UL) #define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) +#ifndef CONSISTENT_WC_SIZE +#define CONSISTENT_WC_SIZE SZ_2M +#endif + +#define CONSISTENT_WC_END CONSISTENT_BASE +#define CONSISTENT_WC_BASE (CONSISTENT_WC_END - CONSISTENT_WC_SIZE) + #else /* CONFIG_MMU */ /* @@ -194,8 +201,8 @@ static inline unsigned long __phys_to_virt(unsigned long x) return t; } #else -#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) -#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) +#define __virt_to_phys(x) ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((unsigned long)(x) - PHYS_OFFSET + PAGE_OFFSET) #endif #endif diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index ac75d0848889..97b440c25c58 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -151,47 +151,11 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from, #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) extern void copy_page(void *to, const void *from); -typedef unsigned long pteval_t; - -#undef STRICT_MM_TYPECHECKS - -#ifdef STRICT_MM_TYPECHECKS -/* - * These are used to make use of C type-checking.. - */ -typedef struct { pteval_t pte; } pte_t; -typedef struct { unsigned long pmd; } pmd_t; -typedef struct { unsigned long pgd[2]; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((x).pmd) -#define pgd_val(x) ((x).pgd[0]) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - +#ifdef CONFIG_ARM_LPAE +#include <asm/pgtable-3level-types.h> #else -/* - * .. while these make it easier on the compiler - */ -typedef pteval_t pte_t; -typedef unsigned long pmd_t; -typedef unsigned long pgd_t[2]; -typedef unsigned long pgprot_t; - -#define pte_val(x) (x) -#define pmd_val(x) (x) -#define pgd_val(x) ((x)[0]) -#define pgprot_val(x) (x) - -#define __pte(x) (x) -#define __pmd(x) (x) -#define __pgprot(x) (x) - -#endif /* STRICT_MM_TYPECHECKS */ +#include <asm/pgtable-2level-types.h> +#endif #endif /* CONFIG_MMU */ diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index 22de005f159c..943504f53f57 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h @@ -25,12 +25,34 @@ #define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER)) #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) +#ifdef CONFIG_ARM_LPAE + +static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) +{ + return (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT); +} + +static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd) +{ + BUG_ON((unsigned long)pmd & (PAGE_SIZE-1)); + free_page((unsigned long)pmd); +} + +static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) +{ + set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE)); +} + +#else /* !CONFIG_ARM_LPAE */ + /* * Since we have only two-level page tables, these are trivial */ #define pmd_alloc_one(mm,addr) ({ BUG(); ((pmd_t *)2); }) #define pmd_free(mm, pmd) do { } while (0) -#define pgd_populate(mm,pmd,pte) BUG() +#define pud_populate(mm,pmd,pte) BUG() + +#endif /* CONFIG_ARM_LPAE */ extern pgd_t *pgd_alloc(struct mm_struct *mm); extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); @@ -105,11 +127,13 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t pte) } static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte, - unsigned long prot) + pmdval_t prot) { - unsigned long pmdval = (pte + PTE_HWTABLE_OFF) | prot; + pmdval_t pmdval = (pte + PTE_HWTABLE_OFF) | prot; pmdp[0] = __pmd(pmdval); +#ifndef CONFIG_ARM_LPAE pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); +#endif flush_pmd_entry(pmdp); } diff --git a/arch/arm/include/asm/pgtable-2level-hwdef.h b/arch/arm/include/asm/pgtable-2level-hwdef.h new file mode 100644 index 000000000000..5cfba15cb401 --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level-hwdef.h @@ -0,0 +1,93 @@ +/* + * arch/arm/include/asm/pgtable-2level-hwdef.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ASM_PGTABLE_2LEVEL_HWDEF_H +#define _ASM_PGTABLE_2LEVEL_HWDEF_H + +/* + * Hardware page table definitions. + * + * + Level 1 descriptor (PMD) + * - common + */ +#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) +#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) +#define PMD_TYPE_TABLE (_AT(pmdval_t, 1) << 0) +#define PMD_TYPE_SECT (_AT(pmdval_t, 2) << 0) +#define PMD_BIT4 (_AT(pmdval_t, 1) << 4) +#define PMD_DOMAIN(x) (_AT(pmdval_t, (x)) << 5) +#define PMD_PROTECTION (_AT(pmdval_t, 1) << 9) /* v5 */ +/* + * - section + */ +#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) +#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) +#define PMD_SECT_XN (_AT(pmdval_t, 1) << 4) /* v6 */ +#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 1) << 10) +#define PMD_SECT_AP_READ (_AT(pmdval_t, 1) << 11) +#define PMD_SECT_TEX(x) (_AT(pmdval_t, (x)) << 12) /* v5 */ +#define PMD_SECT_APX (_AT(pmdval_t, 1) << 15) /* v6 */ +#define PMD_SECT_S (_AT(pmdval_t, 1) << 16) /* v6 */ +#define PMD_SECT_nG (_AT(pmdval_t, 1) << 17) /* v6 */ +#define PMD_SECT_SUPER (_AT(pmdval_t, 1) << 18) /* v6 */ +#define PMD_SECT_AF (_AT(pmdval_t, 0)) + +#define PMD_SECT_UNCACHED (_AT(pmdval_t, 0)) +#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) +#define PMD_SECT_WT (PMD_SECT_CACHEABLE) +#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) +#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) +#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) + +/* + * - coarse table (not used) + */ + +/* + * + Level 2 descriptor (PTE) + * - common + */ +#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) +#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) +#define PTE_TYPE_LARGE (_AT(pteval_t, 1) << 0) +#define PTE_TYPE_SMALL (_AT(pteval_t, 2) << 0) +#define PTE_TYPE_EXT (_AT(pteval_t, 3) << 0) /* v5 */ +#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) +#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) + +/* + * - extended small page/tiny page + */ +#define PTE_EXT_XN (_AT(pteval_t, 1) << 0) /* v6 */ +#define PTE_EXT_AP_MASK (_AT(pteval_t, 3) << 4) +#define PTE_EXT_AP0 (_AT(pteval_t, 1) << 4) +#define PTE_EXT_AP1 (_AT(pteval_t, 2) << 4) +#define PTE_EXT_AP_UNO_SRO (_AT(pteval_t, 0) << 4) +#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) +#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) +#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) +#define PTE_EXT_TEX(x) (_AT(pteval_t, (x)) << 6) /* v5 */ +#define PTE_EXT_APX (_AT(pteval_t, 1) << 9) /* v6 */ +#define PTE_EXT_COHERENT (_AT(pteval_t, 1) << 9) /* XScale3 */ +#define PTE_EXT_SHARED (_AT(pteval_t, 1) << 10) /* v6 */ +#define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* v6 */ + +/* + * - small page + */ +#define PTE_SMALL_AP_MASK (_AT(pteval_t, 0xff) << 4) +#define PTE_SMALL_AP_UNO_SRO (_AT(pteval_t, 0x00) << 4) +#define PTE_SMALL_AP_UNO_SRW (_AT(pteval_t, 0x55) << 4) +#define PTE_SMALL_AP_URO_SRW (_AT(pteval_t, 0xaa) << 4) +#define PTE_SMALL_AP_URW_SRW (_AT(pteval_t, 0xff) << 4) + +#define PHYS_MASK (~0UL) + +#endif diff --git a/arch/arm/include/asm/pgtable-2level-types.h b/arch/arm/include/asm/pgtable-2level-types.h new file mode 100644 index 000000000000..ad999ed61b8e --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level-types.h @@ -0,0 +1,69 @@ +/* + * arch/arm/include/asm/pgtable-2level-types.h + * + * Copyright (C) 1995-2003 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _ASM_PGTABLE_2LEVEL_TYPES_H +#define _ASM_PGTABLE_2LEVEL_TYPES_H + +#include <asm/types.h> + +typedef u32 pteval_t; +typedef u32 pmdval_t; +typedef u32 pgdval_t; +typedef u32 pgprotval_t; + +#undef STRICT_MM_TYPECHECKS + +#ifdef STRICT_MM_TYPECHECKS +/* + * These are used to make use of C type-checking.. + */ +typedef struct { pteval_t pte; } pte_t; +typedef struct { pmdval_t pmd; } pmd_t; +typedef struct { pgdval_t pgd[2]; } pgd_t; +typedef struct { pgprotval_t pgprot; } pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((x).pmd) +#define pgd_val(x) ((x).pgd[0]) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +#else +/* + * .. while these make it easier on the compiler + */ +typedef pteval_t pte_t; +typedef pmdval_t pmd_t; +typedef pgdval_t pgd_t[2]; +typedef pgprotval_t pgprot_t; + +#define pte_val(x) (x) +#define pmd_val(x) (x) +#define pgd_val(x) ((x)[0]) +#define pgprot_val(x) (x) + +#define __pte(x) (x) +#define __pmd(x) (x) +#define __pgprot(x) (x) + +#endif /* STRICT_MM_TYPECHECKS */ + +#endif /* _ASM_PGTABLE_2LEVEL_TYPES_H */ diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h new file mode 100644 index 000000000000..470457e1cfc5 --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level.h @@ -0,0 +1,143 @@ +/* + * arch/arm/include/asm/pgtable-2level.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ASM_PGTABLE_2LEVEL_H +#define _ASM_PGTABLE_2LEVEL_H + +/* + * Hardware-wise, we have a two level page table structure, where the first + * level has 4096 entries, and the second level has 256 entries. Each entry + * is one 32-bit word. Most of the bits in the second level entry are used + * by hardware, and there aren't any "accessed" and "dirty" bits. + * + * Linux on the other hand has a three level page table structure, which can + * be wrapped to fit a two level page table structure easily - using the PGD + * and PTE only. However, Linux also expects one "PTE" table per page, and + * at least a "dirty" bit. + * + * Therefore, we tweak the implementation slightly - we tell Linux that we + * have 2048 entries in the first level, each of which is 8 bytes (iow, two + * hardware pointers to the second level.) The second level contains two + * hardware PTE tables arranged contiguously, preceded by Linux versions + * which contain the state information Linux needs. We, therefore, end up + * with 512 entries in the "PTE" level. + * + * This leads to the page tables having the following layout: + * + * pgd pte + * | | + * +--------+ + * | | +------------+ +0 + * +- - - - + | Linux pt 0 | + * | | +------------+ +1024 + * +--------+ +0 | Linux pt 1 | + * | |-----> +------------+ +2048 + * +- - - - + +4 | h/w pt 0 | + * | |-----> +------------+ +3072 + * +--------+ +8 | h/w pt 1 | + * | | +------------+ +4096 + * + * See L_PTE_xxx below for definitions of bits in the "Linux pt", and + * PTE_xxx for definitions of bits appearing in the "h/w pt". + * + * PMD_xxx definitions refer to bits in the first level page table. + * + * The "dirty" bit is emulated by only granting hardware write permission + * iff the page is marked "writable" and "dirty" in the Linux PTE. This + * means that a write to a clean page will cause a permission fault, and + * the Linux MM layer will mark the page dirty via handle_pte_fault(). + * For the hardware to notice the permission change, the TLB entry must + * be flushed, and ptep_set_access_flags() does that for us. + * + * The "accessed" or "young" bit is emulated by a similar method; we only + * allow accesses to the page if the "young" bit is set. Accesses to the + * page will cause a fault, and handle_pte_fault() will set the young bit + * for us as long as the page is marked present in the corresponding Linux + * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is + * up to date. + * + * However, when the "young" bit is cleared, we deny access to the page + * by clearing the hardware PTE. Currently Linux does not flush the TLB + * for us in this case, which means the TLB will retain the transation + * until either the TLB entry is evicted under pressure, or a context + * switch which changes the user space mapping occurs. + */ +#define PTRS_PER_PTE 512 +#define PTRS_PER_PMD 1 +#define PTRS_PER_PGD 2048 + +#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) +#define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) +#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) + +/* + * PMD_SHIFT determines the size of the area a second-level page table can map + * PGDIR_SHIFT determines what a third-level page table entry can map + */ +#define PMD_SHIFT 21 +#define PGDIR_SHIFT 21 + +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * section address mask and size definitions. + */ +#define SECTION_SHIFT 20 +#define SECTION_SIZE (1UL << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) + +/* + * ARMv6 supersection address mask and size definitions. + */ +#define SUPERSECTION_SHIFT 24 +#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) +#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) + +#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) + +/* + * "Linux" PTE definitions. + * + * We keep two sets of PTEs - the hardware and the linux version. + * This allows greater flexibility in the way we map the Linux bits + * onto the hardware tables, and allows us to have YOUNG and DIRTY + * bits. + * + * The PTE table pointer refers to the hardware entries; the "Linux" + * entries are stored 1024 bytes below. + */ +#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) +#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) +#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ +#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) +#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) +#define L_PTE_USER (_AT(pteval_t, 1) << 8) +#define L_PTE_XN (_AT(pteval_t, 1) << 9) +#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */ + +/* + * These are the memory types, defined to be compatible with + * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB + */ +#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */ +#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ +#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ +#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ +#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ +#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ +#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ +#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ +#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ +#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) + +#endif /* _ASM_PGTABLE_2LEVEL_H */ diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h new file mode 100644 index 000000000000..7c238a3b48cc --- /dev/null +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h @@ -0,0 +1,82 @@ +/* + * arch/arm/include/asm/pgtable-3level-hwdef.h + * + * Copyright (C) 2011 ARM Ltd. + * Author: Catalin Marinas <catalin.marinas@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H +#define _ASM_PGTABLE_3LEVEL_HWDEF_H + +/* + * Hardware page table definitions. + * + * + Level 1/2 descriptor + * - common + */ +#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) +#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) +#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) +#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) +#define PMD_BIT4 (_AT(pmdval_t, 0)) +#define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) + +/* + * - section + */ +#define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) +#define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) +#define PMD_SECT_S (_AT(pmdval_t, 3) << 8) +#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) +#define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) +#ifdef __ASSEMBLY__ +/* avoid 'shift count out of range' warning */ +#define PMD_SECT_XN (0) +#else +#define PMD_SECT_XN ((pmdval_t)1 << 54) +#endif +#define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) +#define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) +#define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) + +/* + * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). + */ +#define PMD_SECT_UNCACHED (_AT(pmdval_t, 0) << 2) /* strongly ordered */ +#define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */ +#define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) /* normal inner write-through */ +#define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) /* normal inner write-back */ +#define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */ + +/* + * + Level 3 descriptor (PTE) + */ +#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) +#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) +#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) +#define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ +#define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ +#define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ +#define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ +#define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ +#define PTE_EXT_XN (_AT(pteval_t, 1) << 54) /* XN */ + +/* + * 40-bit physical address supported. + */ +#define PHYS_MASK_SHIFT (40) +#define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1) + +#endif diff --git a/arch/arm/include/asm/pgtable-3level-types.h b/arch/arm/include/asm/pgtable-3level-types.h new file mode 100644 index 000000000000..f2fc134980fe --- /dev/null +++ b/arch/arm/include/asm/pgtable-3level-types.h @@ -0,0 +1,71 @@ +/* + * arch/arm/include/asm/pgtable-3level-types.h + * + * Copyright (C) 2011 ARM Ltd. + * Author: Catalin Marinas <catalin.marinas@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _ASM_PGTABLE_3LEVEL_TYPES_H +#define _ASM_PGTABLE_3LEVEL_TYPES_H + +#include <asm/types.h> + +typedef u64 pteval_t; +typedef u64 pmdval_t; +typedef u64 pgdval_t; +typedef u64 pgprotval_t; + +#undef STRICT_MM_TYPECHECKS + +#ifdef STRICT_MM_TYPECHECKS + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { pteval_t pte; } pte_t; +typedef struct { pmdval_t pmd; } pmd_t; +typedef struct { pgdval_t pgd; } pgd_t; +typedef struct { pgprotval_t pgprot; } pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((x).pmd) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +#else /* !STRICT_MM_TYPECHECKS */ + +typedef pteval_t pte_t; +typedef pmdval_t pmd_t; +typedef pgdval_t pgd_t; +typedef pgprotval_t pgprot_t; + +#define pte_val(x) (x) +#define pmd_val(x) (x) +#define pgd_val(x) (x) +#define pgprot_val(x) (x) + +#define __pte(x) (x) +#define __pmd(x) (x) +#define __pgd(x) (x) +#define __pgprot(x) (x) + +#endif /* STRICT_MM_TYPECHECKS */ + +#endif /* _ASM_PGTABLE_3LEVEL_TYPES_H */ diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h new file mode 100644 index 000000000000..a6261f517973 --- /dev/null +++ b/arch/arm/include/asm/pgtable-3level.h @@ -0,0 +1,107 @@ +/* + * arch/arm/include/asm/pgtable-3level.h + * + * Copyright (C) 2011 ARM Ltd. + * Author: Catalin Marinas <catalin.marinas@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _ASM_PGTABLE_3LEVEL_H +#define _ASM_PGTABLE_3LEVEL_H + +/* + * With LPAE, there are 3 levels of page tables. Each level has 512 entries of + * 8 bytes each, occupying a 4K page. The first level table covers a range of + * 512GB, each entry representing 1GB. Since we are limited to 4GB input + * address range, only 4 entries in the PGD are used. + * + * There are enough spare bits in a page table entry for the kernel specific + * state. + */ +#define PTRS_PER_PTE 512 +#define PTRS_PER_PMD 512 +#define PTRS_PER_PGD 4 + +#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) +#define PTE_HWTABLE_OFF (0) +#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) + +/* + * PGDIR_SHIFT determines the size a top-level page table entry can map. + */ +#define PGDIR_SHIFT 30 + +/* + * PMD_SHIFT determines the size a middle-level page table entry can map. + */ +#define PMD_SHIFT 21 + +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * section address mask and size definitions. + */ +#define SECTION_SHIFT 21 +#define SECTION_SIZE (1UL << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) + +#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE) + +/* + * "Linux" PTE definitions for LPAE. + * + * These bits overlap with the hardware bits but the naming is preserved for + * consistency with the classic page table format. + */ +#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Valid */ +#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ +#define L_PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ +#define L_PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ +#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ +#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ +#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ +#define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ +#define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ +#define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) /* unused */ +#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */ + +/* + * To be used in assembly code with the upper page attributes. + */ +#define L_PTE_XN_HIGH (1 << (54 - 32)) +#define L_PTE_DIRTY_HIGH (1 << (55 - 32)) + +/* + * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). + */ +#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ +#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ +#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ +#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ +#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ +#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ +#define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ +#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ +#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) + +/* + * Software PGD flags. + */ +#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */ + +#endif /* _ASM_PGTABLE_3LEVEL_H */ diff --git a/arch/arm/include/asm/pgtable-hwdef.h b/arch/arm/include/asm/pgtable-hwdef.h index fd1521d5cb9d..8426229ba292 100644 --- a/arch/arm/include/asm/pgtable-hwdef.h +++ b/arch/arm/include/asm/pgtable-hwdef.h @@ -10,81 +10,10 @@ #ifndef _ASMARM_PGTABLE_HWDEF_H #define _ASMARM_PGTABLE_HWDEF_H -/* - * Hardware page table definitions. - * - * + Level 1 descriptor (PMD) - * - common - */ -#define PMD_TYPE_MASK (3 << 0) -#define PMD_TYPE_FAULT (0 << 0) -#define PMD_TYPE_TABLE (1 << 0) -#define PMD_TYPE_SECT (2 << 0) -#define PMD_BIT4 (1 << 4) -#define PMD_DOMAIN(x) ((x) << 5) -#define PMD_PROTECTION (1 << 9) /* v5 */ -/* - * - section - */ -#define PMD_SECT_BUFFERABLE (1 << 2) -#define PMD_SECT_CACHEABLE (1 << 3) -#define PMD_SECT_XN (1 << 4) /* v6 */ -#define PMD_SECT_AP_WRITE (1 << 10) -#define PMD_SECT_AP_READ (1 << 11) -#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ -#define PMD_SECT_APX (1 << 15) /* v6 */ -#define PMD_SECT_S (1 << 16) /* v6 */ -#define PMD_SECT_nG (1 << 17) /* v6 */ -#define PMD_SECT_SUPER (1 << 18) /* v6 */ - -#define PMD_SECT_UNCACHED (0) -#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) -#define PMD_SECT_WT (PMD_SECT_CACHEABLE) -#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) -#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) -#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) - -/* - * - coarse table (not used) - */ - -/* - * + Level 2 descriptor (PTE) - * - common - */ -#define PTE_TYPE_MASK (3 << 0) -#define PTE_TYPE_FAULT (0 << 0) -#define PTE_TYPE_LARGE (1 << 0) -#define PTE_TYPE_SMALL (2 << 0) -#define PTE_TYPE_EXT (3 << 0) /* v5 */ -#define PTE_BUFFERABLE (1 << 2) -#define PTE_CACHEABLE (1 << 3) - -/* - * - extended small page/tiny page - */ -#define PTE_EXT_XN (1 << 0) /* v6 */ -#define PTE_EXT_AP_MASK (3 << 4) -#define PTE_EXT_AP0 (1 << 4) -#define PTE_EXT_AP1 (2 << 4) -#define PTE_EXT_AP_UNO_SRO (0 << 4) -#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) -#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) -#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) -#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ -#define PTE_EXT_APX (1 << 9) /* v6 */ -#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */ -#define PTE_EXT_SHARED (1 << 10) /* v6 */ -#define PTE_EXT_NG (1 << 11) /* v6 */ - -/* - * - small page - */ -#define PTE_SMALL_AP_MASK (0xff << 4) -#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) -#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) -#define PTE_SMALL_AP_URO_SRW (0xaa << 4) -#define PTE_SMALL_AP_URW_SRW (0xff << 4) +#ifdef CONFIG_ARM_LPAE +#include <asm/pgtable-3level-hwdef.h> +#else +#include <asm/pgtable-2level-hwdef.h> +#endif #endif diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 5750704e0271..9645e52f5585 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -11,19 +11,26 @@ #define _ASMARM_PGTABLE_H #include <linux/const.h> -#include <asm-generic/4level-fixup.h> #include <asm/proc-fns.h> #ifndef CONFIG_MMU +#include <asm-generic/4level-fixup.h> #include "pgtable-nommu.h" #else +#include <asm-generic/pgtable-nopud.h> #include <asm/memory.h> #include <mach/vmalloc.h> #include <asm/pgtable-hwdef.h> +#ifdef CONFIG_ARM_LPAE +#include <asm/pgtable-3level.h> +#else +#include <asm/pgtable-2level.h> +#endif + /* * Just any arbitrary offset to the start of the vmalloc VM area: the * current 8MB value just means that there will be a 8MB "hole" after the @@ -41,79 +48,6 @@ #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #endif -/* - * Hardware-wise, we have a two level page table structure, where the first - * level has 4096 entries, and the second level has 256 entries. Each entry - * is one 32-bit word. Most of the bits in the second level entry are used - * by hardware, and there aren't any "accessed" and "dirty" bits. - * - * Linux on the other hand has a three level page table structure, which can - * be wrapped to fit a two level page table structure easily - using the PGD - * and PTE only. However, Linux also expects one "PTE" table per page, and - * at least a "dirty" bit. - * - * Therefore, we tweak the implementation slightly - we tell Linux that we - * have 2048 entries in the first level, each of which is 8 bytes (iow, two - * hardware pointers to the second level.) The second level contains two - * hardware PTE tables arranged contiguously, preceded by Linux versions - * which contain the state information Linux needs. We, therefore, end up - * with 512 entries in the "PTE" level. - * - * This leads to the page tables having the following layout: - * - * pgd pte - * | | - * +--------+ - * | | +------------+ +0 - * +- - - - + | Linux pt 0 | - * | | +------------+ +1024 - * +--------+ +0 | Linux pt 1 | - * | |-----> +------------+ +2048 - * +- - - - + +4 | h/w pt 0 | - * | |-----> +------------+ +3072 - * +--------+ +8 | h/w pt 1 | - * | | +------------+ +4096 - * - * See L_PTE_xxx below for definitions of bits in the "Linux pt", and - * PTE_xxx for definitions of bits appearing in the "h/w pt". - * - * PMD_xxx definitions refer to bits in the first level page table. - * - * The "dirty" bit is emulated by only granting hardware write permission - * iff the page is marked "writable" and "dirty" in the Linux PTE. This - * means that a write to a clean page will cause a permission fault, and - * the Linux MM layer will mark the page dirty via handle_pte_fault(). - * For the hardware to notice the permission change, the TLB entry must - * be flushed, and ptep_set_access_flags() does that for us. - * - * The "accessed" or "young" bit is emulated by a similar method; we only - * allow accesses to the page if the "young" bit is set. Accesses to the - * page will cause a fault, and handle_pte_fault() will set the young bit - * for us as long as the page is marked present in the corresponding Linux - * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is - * up to date. - * - * However, when the "young" bit is cleared, we deny access to the page - * by clearing the hardware PTE. Currently Linux does not flush the TLB - * for us in this case, which means the TLB will retain the transation - * until either the TLB entry is evicted under pressure, or a context - * switch which changes the user space mapping occurs. - */ -#define PTRS_PER_PTE 512 -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD 2048 - -#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) -#define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) -#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) - -/* - * PMD_SHIFT determines the size of the area a second-level page table can map - * PGDIR_SHIFT determines what a third-level page table entry can map - */ -#define PMD_SHIFT 21 -#define PGDIR_SHIFT 21 - #define LIBRARY_TEXT_START 0x0c000000 #ifndef __ASSEMBLY__ @@ -124,12 +58,6 @@ extern void __pgd_error(const char *file, int line, pgd_t); #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte) #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd) #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd) -#endif /* !__ASSEMBLY__ */ - -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) /* * This is the lowest virtual address we can permit any user space @@ -138,60 +66,6 @@ extern void __pgd_error(const char *file, int line, pgd_t); */ #define FIRST_USER_ADDRESS PAGE_SIZE -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) - -/* - * section address mask and size definitions. - */ -#define SECTION_SHIFT 20 -#define SECTION_SIZE (1UL << SECTION_SHIFT) -#define SECTION_MASK (~(SECTION_SIZE-1)) - -/* - * ARMv6 supersection address mask and size definitions. - */ -#define SUPERSECTION_SHIFT 24 -#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) -#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) - -/* - * "Linux" PTE definitions. - * - * We keep two sets of PTEs - the hardware and the linux version. - * This allows greater flexibility in the way we map the Linux bits - * onto the hardware tables, and allows us to have YOUNG and DIRTY - * bits. - * - * The PTE table pointer refers to the hardware entries; the "Linux" - * entries are stored 1024 bytes below. - */ -#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) -#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) -#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ -#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) -#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) -#define L_PTE_USER (_AT(pteval_t, 1) << 8) -#define L_PTE_XN (_AT(pteval_t, 1) << 9) -#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */ - -/* - * These are the memory types, defined to be compatible with - * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB - */ -#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */ -#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ -#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ -#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ -#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ -#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ -#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ -#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ -#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ -#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ -#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) - -#ifndef __ASSEMBLY__ - /* * The pgprot_* and protection_map entries will be fixed up in runtime * to include the cachable and bufferable bits based on memory policy, @@ -291,24 +165,79 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) +#ifdef CONFIG_ARM_LPAE + +#define pud_none(pud) (!pud_val(pud)) +#define pud_bad(pud) (!(pud_val(pud) & 2)) +#define pud_present(pud) (pud_val(pud)) + +#define pud_clear(pudp) \ + do { \ + *pudp = __pud(0); \ + clean_pmd_entry(pudp); \ + } while (0) + +#define set_pud(pudp, pud) \ + do { \ + *pudp = pud; \ + flush_pmd_entry(pudp); \ + } while (0) + +static inline pmd_t *pud_page_vaddr(pud_t pud) +{ + return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); +} + +#else /* !CONFIG_ARM_LPAE */ + /* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) + * The "pud_xxx()" functions here are trivial when the pmd is folded into + * the pud: the pud entry is never bad, always exists, and can't be set or + * cleared. */ -#define pgd_none(pgd) (0) -#define pgd_bad(pgd) (0) -#define pgd_present(pgd) (1) -#define pgd_clear(pgdp) do { } while (0) -#define set_pgd(pgd,pgdp) do { } while (0) +#define pud_none(pud) (0) +#define pud_bad(pud) (0) +#define pud_present(pud) (1) +#define pud_clear(pudp) do { } while (0) #define set_pud(pud,pudp) do { } while (0) +#endif /* CONFIG_ARM_LPAE */ /* Find an entry in the second-level page table.. */ -#define pmd_offset(dir, addr) ((pmd_t *)(dir)) +#ifdef CONFIG_ARM_LPAE +#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) +static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) +{ + return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); +} +#else +static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) +{ + return (pmd_t *)pud; +} +#endif #define pmd_none(pmd) (!pmd_val(pmd)) #define pmd_present(pmd) (pmd_val(pmd)) + +#ifdef CONFIG_ARM_LPAE + +#define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) + +#define copy_pmd(pmdpd,pmdps) \ + do { \ + *pmdpd = *pmdps; \ + flush_pmd_entry(pmdpd); \ + } while (0) + +#define pmd_clear(pmdp) \ + do { \ + *pmdp = __pmd(0); \ + clean_pmd_entry(pmdp); \ + } while (0) + +#else /* !CONFIG_ARM_LPAE */ + #define pmd_bad(pmd) (pmd_val(pmd) & 2) #define copy_pmd(pmdpd,pmdps) \ @@ -325,16 +254,14 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; clean_pmd_entry(pmdp); \ } while (0) +#endif /* CONFIG_ARM_LPAE */ + static inline pte_t *pmd_page_vaddr(pmd_t pmd) { - return __va(pmd_val(pmd) & PAGE_MASK); + return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); } -#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) - -/* we don't need complex calculations here as the pmd is folded into the pgd */ -#define pmd_addr_end(addr,end) (end) - +#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) #ifndef CONFIG_HIGHPTE #define __pte_map(pmd) pmd_page_vaddr(*(pmd)) @@ -351,15 +278,20 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) #define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr)) #define pte_unmap(pte) __pte_unmap(pte) -#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) +#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) #define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot)) #define pte_page(pte) pfn_to_page(pte_pfn(pte)) #define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot) -#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) +#ifdef CONFIG_ARM_LPAE +#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext))) +#else +#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) +#endif + #if __LINUX_ARM_ARCH__ < 6 static inline void __sync_icache_dcache(pte_t pteval) { diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index 8ec535e11fd7..b5db4f415efd 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@ -65,7 +65,11 @@ extern struct processor { * Set a possibly extended PTE. Non-extended PTEs should * ignore 'ext'. */ +#ifdef CONFIG_ARM_LPAE + void (*set_pte_ext)(pte_t *ptep, pte_t pte); +#else void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext); +#endif /* Suspend/resume */ unsigned int suspend_size; @@ -79,7 +83,11 @@ extern void cpu_proc_fin(void); extern int cpu_do_idle(void); extern void cpu_dcache_clean_area(void *, int); extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); +#ifdef CONFIG_ARM_LPAE +extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte); +#else extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); +#endif extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); #else #define cpu_proc_init() processor._proc_init() @@ -87,7 +95,11 @@ extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); #define cpu_reset(addr) processor.reset(addr) #define cpu_do_idle() processor._do_idle() #define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz) +#ifdef CONFIG_ARM_LPAE +#define cpu_set_pte_ext(ptep,pte) processor.set_pte_ext(ptep,pte) +#else #define cpu_set_pte_ext(ptep,pte,ext) processor.set_pte_ext(ptep,pte,ext) +#endif #define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm) #endif @@ -99,6 +111,18 @@ extern void cpu_resume(void); #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm) +#ifdef CONFIG_ARM_LPAE +#define cpu_get_pgd() \ + ({ \ + unsigned long pg, pg2; \ + __asm__("mrrc p15, 0, %0, %1, c2" \ + : "=r" (pg), "=r" (pg2) \ + : \ + : "cc"); \ + pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \ + (pgd_t *)phys_to_virt(pg); \ + }) +#else #define cpu_get_pgd() \ ({ \ unsigned long pg; \ @@ -107,6 +131,7 @@ extern void cpu_resume(void); pg &= ~0x3fff; \ (pgd_t *)phys_to_virt(pg); \ }) +#endif #endif diff --git a/arch/arm/include/asm/scatterlist.h b/arch/arm/include/asm/scatterlist.h index 2f87870d9347..cefdb8f898a1 100644 --- a/arch/arm/include/asm/scatterlist.h +++ b/arch/arm/include/asm/scatterlist.h @@ -1,6 +1,10 @@ #ifndef _ASMARM_SCATTERLIST_H #define _ASMARM_SCATTERLIST_H +#ifdef CONFIG_ARM_HAS_SG_CHAIN +#define ARCH_HAS_SG_CHAIN +#endif + #include <asm/memory.h> #include <asm/types.h> #include <asm-generic/scatterlist.h> diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index ee2ad8ae07af..8423a058fb62 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -43,6 +43,13 @@ struct tag_mem32 { __u32 start; /* physical start address */ }; +#define ATAG_MEM64 0x54420002 + +struct tag_mem64 { + __u64 size; + __u64 start; /* physical start address */ +}; + /* VGA text type displays */ #define ATAG_VIDEOTEXT 0x54410003 @@ -148,6 +155,7 @@ struct tag { union { struct tag_core core; struct tag_mem32 mem; + struct tag_mem64 mem64; struct tag_videotext videotext; struct tag_ramdisk ramdisk; struct tag_initrd initrd; diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index 265f908c4a6e..5d3ed7e38561 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -202,8 +202,18 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, tlb_remove_page(tlb, pte); } +static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, + unsigned long addr) +{ +#ifdef CONFIG_ARM_LPAE + tlb_add_flush(tlb, addr); + tlb_remove_page(tlb, virt_to_page(pmdp)); +#endif +} + #define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr) -#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp) +#define pmd_free_tlb(tlb, pmdp, addr) __pmd_free_tlb(tlb, pmdp, addr) +#define pud_free_tlb(tlb, pudp, addr) pud_free((tlb)->mm, pudp) #define tlb_migrate_finish(mm) do { } while (0) diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index d2005de383b8..2a495685698a 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -509,7 +509,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) * these operations. This is typically used when we are removing * PMD entries. */ -static inline void flush_pmd_entry(pmd_t *pmd) +static inline void flush_pmd_entry(void *pmd) { const unsigned int __tlb_flag = __cpu_tlb_flags; @@ -525,7 +525,7 @@ static inline void flush_pmd_entry(pmd_t *pmd) dsb(); } -static inline void clean_pmd_entry(pmd_t *pmd) +static inline void clean_pmd_entry(void *pmd) { const unsigned int __tlb_flag = __cpu_tlb_flags; diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 48192ac3a23a..dc1bdbb301c9 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -1,17 +1,8 @@ #ifndef __ASM_ARM_TYPES_H #define __ASM_ARM_TYPES_H -#include <asm-generic/int-ll64.h> +#include <asm-generic/types.h> -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ #ifdef __KERNEL__ #define BITS_PER_LONG 32 diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index a701e4226a6c..0cdd7b456cb2 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -76,6 +76,9 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) unsigned long dt_root; const char *model; + if (!dt_phys) + return NULL; + devtree = phys_to_virt(dt_phys); /* check device tree validity */ diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index e8d885676807..90c62cd51ca9 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -435,6 +435,10 @@ __irq_usr: usr_entry kuser_cmpxchg_check +#ifdef CONFIG_IRQSOFF_TRACER + bl trace_hardirqs_off +#endif + get_thread_info tsk #ifdef CONFIG_PREEMPT ldr r8, [tsk, #TI_PREEMPT] @ get preempt count @@ -453,7 +457,7 @@ __irq_usr: #endif mov why, #0 - b ret_to_user + b ret_to_user_from_irq UNWIND(.fnend ) ENDPROC(__irq_usr) diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 1e7b04a40a31..b2a27b6b0046 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -64,6 +64,7 @@ work_resched: ENTRY(ret_to_user) ret_slow_syscall: disable_irq @ disable interrupts +ENTRY(ret_to_user_from_irq) ldr r1, [tsk, #TI_FLAGS] tst r1, #_TIF_WORK_MASK bne work_pending @@ -75,6 +76,7 @@ no_work_pending: arch_ret_to_user r1, lr restore_user_regs fast = 0, offset = 0 +ENDPROC(ret_to_user_from_irq) ENDPROC(ret_to_user) /* diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 278c1b0ebb2e..4866e1305837 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -21,6 +21,7 @@ #include <asm/memory.h> #include <asm/thread_info.h> #include <asm/system.h> +#include <asm/pgtable.h> #ifdef CONFIG_DEBUG_LL #include <mach/debug-macro.S> @@ -38,11 +39,20 @@ #error KERNEL_RAM_VADDR must start at 0xXXXX8000 #endif +#ifdef CONFIG_ARM_LPAE + /* LPAE requires an additional page for the PGD */ +#define PG_DIR_SIZE 0x5000 +#define PMD_ORDER 3 +#else +#define PG_DIR_SIZE 0x4000 +#define PMD_ORDER 2 +#endif + .globl swapper_pg_dir - .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 + .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE .macro pgtbl, rd, phys - add \rd, \phys, #TEXT_OFFSET - 0x4000 + add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE .endm #ifdef CONFIG_XIP_KERNEL @@ -140,11 +150,11 @@ __create_page_tables: pgtbl r4, r8 @ page table address /* - * Clear the 16K level 1 swapper page table + * Clear the swapper page table */ mov r0, r4 mov r3, #0 - add r6, r0, #0x4000 + add r6, r0, #PG_DIR_SIZE 1: str r3, [r0], #4 str r3, [r0], #4 str r3, [r0], #4 @@ -152,6 +162,25 @@ __create_page_tables: teq r0, r6 bne 1b +#ifdef CONFIG_ARM_LPAE + /* + * Build the PGD table (first level) to point to the PMD table. A PGD + * entry is 64-bit wide. + */ + mov r0, r4 + add r3, r4, #0x1000 @ first PMD table address + orr r3, r3, #3 @ PGD block type + mov r6, #4 @ PTRS_PER_PGD + mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER +1: str r3, [r0], #4 @ set bottom PGD entry bits + str r7, [r0], #4 @ set top PGD entry bits + add r3, r3, #0x1000 @ next PMD table + subs r6, r6, #1 + bne 1b + + add r4, r4, #0x1000 @ point to the PMD tables +#endif + ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags /* @@ -163,30 +192,30 @@ __create_page_tables: sub r0, r0, r3 @ virt->phys offset add r5, r5, r0 @ phys __enable_mmu add r6, r6, r0 @ phys __enable_mmu_end - mov r5, r5, lsr #20 - mov r6, r6, lsr #20 + mov r5, r5, lsr #SECTION_SHIFT + mov r6, r6, lsr #SECTION_SHIFT -1: orr r3, r7, r5, lsl #20 @ flags + kernel base - str r3, [r4, r5, lsl #2] @ identity mapping - teq r5, r6 - addne r5, r5, #1 @ next section - bne 1b +1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base + str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping + cmp r5, r6 + addlo r5, r5, #SECTION_SHIFT >> 20 @ next section + blo 1b /* * Now setup the pagetables for our kernel direct * mapped region. */ mov r3, pc - mov r3, r3, lsr #20 - orr r3, r7, r3, lsl #20 - add r0, r4, #(KERNEL_START & 0xff000000) >> 18 - str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! + mov r3, r3, lsr #SECTION_SHIFT + orr r3, r7, r3, lsl #SECTION_SHIFT + add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) + str r3, [r0, #(KERNEL_START & 0x00e00000) >> (SECTION_SHIFT - PMD_ORDER)]! ldr r6, =(KERNEL_END - 1) - add r0, r0, #4 - add r6, r4, r6, lsr #18 + add r0, r0, #1 << PMD_ORDER + add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 1: cmp r0, r6 - add r3, r3, #1 << 20 - strls r3, [r0], #4 + add r3, r3, #1 << SECTION_SHIFT + strls r3, [r0], #1 << PMD_ORDER bls 1b #ifdef CONFIG_XIP_KERNEL @@ -195,11 +224,11 @@ __create_page_tables: */ add r3, r8, #TEXT_OFFSET orr r3, r3, r7 - add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 - str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! + add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) + str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]! ldr r6, =(_end - 1) add r0, r0, #4 - add r6, r4, r6, lsr #18 + add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 1: cmp r0, r6 add r3, r3, #1 << 20 strls r3, [r0], #4 @@ -207,15 +236,15 @@ __create_page_tables: #endif /* - * Then map boot params address in r2 or - * the first 1MB of ram if boot params address is not specified. + * Then map boot params address in r2 or the first 1MB (2MB with LPAE) + * of ram if boot params address is not specified. */ - mov r0, r2, lsr #20 - movs r0, r0, lsl #20 + mov r0, r2, lsr #SECTION_SHIFT + movs r0, r0, lsl #SECTION_SHIFT moveq r0, r8 sub r3, r0, r8 add r3, r3, #PAGE_OFFSET - add r3, r4, r3, lsr #18 + add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) orr r6, r7, r0 str r6, [r3] @@ -228,21 +257,27 @@ __create_page_tables: */ addruart r7, r3 - mov r3, r3, lsr #20 - mov r3, r3, lsl #2 + mov r3, r3, lsr #SECTION_SHIFT + mov r3, r3, lsl #PMD_ORDER add r0, r4, r3 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) cmp r3, #0x0800 @ limit to 512MB movhi r3, #0x0800 add r6, r0, r3 - mov r3, r7, lsr #20 + mov r3, r7, lsr #SECTION_SHIFT ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags - orr r3, r7, r3, lsl #20 + orr r3, r7, r3, lsl #SECTION_SHIFT +#ifdef CONFIG_ARM_LPAE + mov r7, #1 << (54 - 32) @ XN +#endif 1: str r3, [r0], #4 - add r3, r3, #1 << 20 - teq r0, r6 - bne 1b +#ifdef CONFIG_ARM_LPAE + str r7, [r0], #4 +#endif + add r3, r3, #1 << SECTION_SHIFT + cmp r0, r6 + blo 1b #else /* CONFIG_DEBUG_ICEDCC */ /* we don't need any serial debugging mappings for ICEDCC */ @@ -254,7 +289,7 @@ __create_page_tables: * If we're using the NetWinder or CATS, we also need to map * in the 16550-type serial port for the debug messages */ - add r0, r4, #0xff000000 >> 18 + add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) orr r3, r7, #0x7c000000 str r3, [r0] #endif @@ -264,13 +299,16 @@ __create_page_tables: * Similar reasons here - for debug. This is * only for Acorn RiscPC architectures. */ - add r0, r4, #0x02000000 >> 18 + add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) orr r3, r7, #0x02000000 str r3, [r0] - add r0, r4, #0xd8000000 >> 18 + add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) str r3, [r0] #endif #endif +#ifdef CONFIG_ARM_LPAE + sub r4, r4, #0x1000 @ point to the PGD table +#endif mov pc, lr ENDPROC(__create_page_tables) .ltorg @@ -362,12 +400,17 @@ __enable_mmu: #ifdef CONFIG_CPU_ICACHE_DISABLE bic r0, r0, #CR_I #endif +#ifdef CONFIG_ARM_LPAE + mov r5, #0 + mcrr p15, 0, r4, r5, c2 @ load TTBR0 +#else mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ domain_val(DOMAIN_IO, DOMAIN_CLIENT)) mcr p15, 0, r5, c3, c0, 0 @ load domain access register mcr p15, 0, r4, c2, c0, 0 @ load page table pointer +#endif b __turn_mmu_on ENDPROC(__enable_mmu) @@ -388,8 +431,10 @@ ENDPROC(__enable_mmu) .align 5 __turn_mmu_on: mov r0, r0 + instr_sync mcr p15, 0, r0, c1, c0, 0 @ write control reg mrc p15, 0, r3, c0, c0, 0 @ read id reg + instr_sync mov r3, r3 mov r3, r13 mov pc, r3 diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index fee7c36349eb..116016dc8156 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -33,7 +33,7 @@ * recompiling the whole kernel when CONFIG_XIP_KERNEL is turned on/off. */ #undef MODULES_VADDR -#define MODULES_VADDR (((unsigned long)_etext + ~PGDIR_MASK) & PGDIR_MASK) +#define MODULES_VADDR (((unsigned long)_etext + ~PMD_MASK) & PMD_MASK) #endif #ifdef CONFIG_MMU diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index ed11fb08b05a..3ae8e6bab960 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -605,6 +605,16 @@ static int __init parse_tag_mem32(const struct tag *tag) __tagtable(ATAG_MEM, parse_tag_mem32); +#ifdef CONFIG_PHYS_ADDR_T_64BIT +static int __init parse_tag_mem64(const struct tag *tag) +{ + /* We only use 32-bits for the size. */ + return arm_add_memory(tag->u.mem64.start, (unsigned long)tag->u.mem64.size); +} + +__tagtable(ATAG_MEM64, parse_tag_mem64); +#endif /* CONFIG_PHYS_ADDR_T_64BIT */ + #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) struct screen_info screen_info = { .orig_video_lines = 30, diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index 6398ead9d1c0..e19ed66173e2 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -10,61 +10,52 @@ /* * Save CPU state for a suspend * r1 = v:p offset - * r3 = virtual return function - * Note: sp is decremented to allocate space for CPU state on stack - * r0-r3,r9,r10,lr corrupted + * r2 = suspend function arg0 + * r3 = suspend function + * Note: does not return until system resumes */ ENTRY(cpu_suspend) - mov r9, lr + stmfd sp!, {r4 - r11, lr} #ifdef MULTI_CPU ldr r10, =processor - mov r2, sp @ current virtual SP - ldr r0, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state + ldr r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function - sub sp, sp, r0 @ allocate CPU state on stack +#else + ldr r5, =cpu_suspend_size + ldr ip, =cpu_do_resume +#endif + mov r6, sp @ current virtual SP + sub sp, sp, r5 @ allocate CPU state on stack mov r0, sp @ save pointer add ip, ip, r1 @ convert resume fn to phys - stmfd sp!, {r1, r2, r3, ip} @ save v:p, virt SP, retfn, phys resume fn - ldr r3, =sleep_save_sp - add r2, sp, r1 @ convert SP to phys + stmfd sp!, {r1, r6, ip} @ save v:p, virt SP, phys resume fn + ldr r5, =sleep_save_sp + add r6, sp, r1 @ convert SP to phys + stmfd sp!, {r2, r3} @ save suspend func arg and pointer #ifdef CONFIG_SMP ALT_SMP(mrc p15, 0, lr, c0, c0, 5) ALT_UP(mov lr, #0) and lr, lr, #15 - str r2, [r3, lr, lsl #2] @ save phys SP + str r6, [r5, lr, lsl #2] @ save phys SP #else - str r2, [r3] @ save phys SP + str r6, [r5] @ save phys SP #endif +#ifdef MULTI_CPU mov lr, pc ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state #else - mov r2, sp @ current virtual SP - ldr r0, =cpu_suspend_size - sub sp, sp, r0 @ allocate CPU state on stack - mov r0, sp @ save pointer - stmfd sp!, {r1, r2, r3} @ save v:p, virt SP, return fn - ldr r3, =sleep_save_sp - add r2, sp, r1 @ convert SP to phys -#ifdef CONFIG_SMP - ALT_SMP(mrc p15, 0, lr, c0, c0, 5) - ALT_UP(mov lr, #0) - and lr, lr, #15 - str r2, [r3, lr, lsl #2] @ save phys SP -#else - str r2, [r3] @ save phys SP -#endif bl cpu_do_suspend #endif @ flush data cache #ifdef MULTI_CACHE ldr r10, =cpu_cache - mov lr, r9 + mov lr, pc ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] #else - mov lr, r9 - b __cpuc_flush_kern_all + bl __cpuc_flush_kern_all #endif + ldmfd sp!, {r0, pc} @ call suspend fn ENDPROC(cpu_suspend) .ltorg @@ -88,8 +79,10 @@ ENDPROC(cpu_resume_mmu) .ltorg .align 5 cpu_resume_turn_mmu_on: + instr_sync mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc mrc p15, 0, r1, c0, c0, 0 @ read id reg + instr_sync mov r1, r1 mov r1, r1 mov pc, r3 @ jump to virtual address @@ -97,7 +90,7 @@ ENDPROC(cpu_resume_turn_mmu_on) cpu_resume_after_mmu: str r5, [r2, r4, lsl #2] @ restore old mapping mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache - mov pc, lr + ldmfd sp!, {r4 - r11, pc} ENDPROC(cpu_resume_after_mmu) /* @@ -120,20 +113,11 @@ ENTRY(cpu_resume) ldr r0, sleep_save_sp @ stack phys addr #endif setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off -#ifdef MULTI_CPU - @ load v:p, stack, return fn, resume fn - ARM( ldmia r0!, {r1, sp, lr, pc} ) -THUMB( ldmia r0!, {r1, r2, r3, r4} ) + @ load v:p, stack, resume fn + ARM( ldmia r0!, {r1, sp, pc} ) +THUMB( ldmia r0!, {r1, r2, r3} ) THUMB( mov sp, r2 ) -THUMB( mov lr, r3 ) -THUMB( bx r4 ) -#else - @ load v:p, stack, return fn - ARM( ldmia r0!, {r1, sp, lr} ) -THUMB( ldmia r0!, {r1, r2, lr} ) -THUMB( mov sp, r2 ) - b cpu_do_resume -#endif +THUMB( bx r3 ) ENDPROC(cpu_resume) sleep_save_sp: diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index d52eec268b47..6807cb1e76dd 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -139,7 +139,7 @@ static void dump_instr(const char *lvl, struct pt_regs *regs) fs = get_fs(); set_fs(KERNEL_DS); - for (i = -4; i < 1; i++) { + for (i = -4; i < 1 + !!thumb; i++) { unsigned int val, bad; if (thumb) @@ -563,7 +563,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) if (!pmd_present(*pmd)) goto bad_access; pte = pte_offset_map_lock(mm, pmd, addr, &ptl); - if (!pte_present(*pte) || !pte_dirty(*pte)) { + if (!pte_present(*pte) || !pte_write(*pte) || !pte_dirty(*pte)) { pte_unmap_unlock(pte, ptl); goto bad_access; } diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 96966231920c..bf57e8b1c9d0 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o gpio.o +obj-y := irq.o gpio.o setup.o obj-m := obj-n := obj- := diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c index 17fae4a42ab5..b5d37b562f33 100644 --- a/arch/arm/mach-at91/at91cap9.c +++ b/arch/arm/mach-at91/at91cap9.c @@ -25,23 +25,10 @@ #include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91cap9_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE, - .pfn = __phys_to_pfn(AT91CAP9_SRAM_BASE), - .length = AT91CAP9_SRAM_SIZE, - .type = MT_DEVICE, - }, -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -339,24 +326,17 @@ static void at91cap9_poweroff(void) * AT91CAP9 processor initialization * -------------------------------------------------------------------- */ -void __init at91cap9_map_io(void) +static void __init at91cap9_map_io(void) { - /* Map peripherals */ - iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc)); + at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE); } -void __init at91cap9_initialize(unsigned long main_clock) +static void __init at91cap9_initialize(void) { at91_arch_reset = at91cap9_reset; pm_power_off = at91cap9_poweroff; at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1); - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91cap9_register_clocks(); - /* Register GPIO subsystem */ at91_gpio_init(at91cap9_gpio, 4); @@ -409,14 +389,9 @@ static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; -void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91cap9_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} +struct at91_soc __initdata at91cap9_soc = { + .map_io = at91cap9_map_io, + .default_irq_priority = at91cap9_default_irq_priority, + .register_clocks = at91cap9_register_clocks, + .init = at91cap9_initialize, +}; diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index b228ce9e21a1..9a701a09817e 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -20,25 +20,16 @@ #include <mach/at91_st.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h" static struct map_desc at91rm9200_io_desc[] __initdata = { { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = AT91_VA_BASE_EMAC, .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), .length = SZ_16K, .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE, - .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE), - .length = AT91RM9200_SRAM_SIZE, - .type = MT_DEVICE, }, }; @@ -304,24 +295,17 @@ static void at91rm9200_reset(void) at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); } -int rm9200_type; -EXPORT_SYMBOL(rm9200_type); - -void __init at91rm9200_set_type(int type) -{ - rm9200_type = type; -} - /* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ -void __init at91rm9200_map_io(void) +static void __init at91rm9200_map_io(void) { /* Map peripherals */ + at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); } -void __init at91rm9200_initialize(unsigned long main_clock) +static void __init at91rm9200_initialize(void) { at91_arch_reset = at91rm9200_reset; at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) @@ -329,12 +313,6 @@ void __init at91rm9200_initialize(unsigned long main_clock) | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) | (1 << AT91RM9200_ID_IRQ6); - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91rm9200_register_clocks(); - /* Initialize GPIO subsystem */ at91_gpio_init(at91rm9200_gpio, cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP); @@ -383,14 +361,9 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { 0 /* Advanced Interrupt Controller (IRQ6) */ }; -void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91rm9200_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} +struct at91_soc __initdata at91rm9200_soc = { + .map_io = at91rm9200_map_io, + .default_irq_priority = at91rm9200_default_irq_priority, + .register_clocks = at91rm9200_register_clocks, + .init = at91rm9200_initialize, +}; diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 7d606b04d313..a7386e1e6823 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -17,58 +17,16 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/cpu.h> +#include <mach/at91_dbgu.h> #include <mach/at91sam9260.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91sam9260_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, - } -}; - -static struct map_desc at91sam9260_sram_desc[] __initdata = { - { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE, - .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE), - .length = AT91SAM9260_SRAM0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE, - .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE), - .length = AT91SAM9260_SRAM1_SIZE, - .type = MT_DEVICE, - } -}; - -static struct map_desc at91sam9g20_sram_desc[] __initdata = { - { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE, - .pfn = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE), - .length = AT91SAM9G20_SRAM0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE, - .pfn = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE), - .length = AT91SAM9G20_SRAM1_SIZE, - .type = MT_DEVICE, - } -}; - -static struct map_desc at91sam9xe_sram_desc[] __initdata = { - { - .pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE), - .type = MT_DEVICE, - } -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -330,11 +288,9 @@ static void at91sam9260_poweroff(void) static void __init at91sam9xe_map_io(void) { - unsigned long cidr, sram_size; - - cidr = at91_sys_read(AT91_DBGU_CIDR); + unsigned long sram_size; - switch (cidr & AT91_CIDR_SRAMSIZ) { + switch (at91_soc_data.cidr & AT91_CIDR_SRAMSIZ) { case AT91_CIDR_SRAMSIZ_32K: sram_size = 2 * SZ_16K; break; @@ -343,38 +299,29 @@ static void __init at91sam9xe_map_io(void) sram_size = SZ_16K; } - at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size; - at91sam9xe_sram_desc->length = sram_size; - - iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc)); + at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size); } -void __init at91sam9260_map_io(void) +static void __init at91sam9260_map_io(void) { - /* Map peripherals */ - iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc)); - - if (cpu_is_at91sam9xe()) + if (cpu_is_at91sam9xe()) { at91sam9xe_map_io(); - else if (cpu_is_at91sam9g20()) - iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc)); - else - iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); + } else if (cpu_is_at91sam9g20()) { + at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE); + at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE); + } else { + at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE); + at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE); + } } -void __init at91sam9260_initialize(unsigned long main_clock) +static void __init at91sam9260_initialize(void) { at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9260_poweroff; at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) | (1 << AT91SAM9260_ID_IRQ2); - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91sam9260_register_clocks(); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9260_gpio, 3); } @@ -421,14 +368,9 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91sam9260_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} +struct at91_soc __initdata at91sam9260_soc = { + .map_io = at91sam9260_map_io, + .default_irq_priority = at91sam9260_default_irq_priority, + .register_clocks = at91sam9260_register_clocks, + .init = at91sam9260_initialize, +}; diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index c1483168c97a..3c76e05bd914 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -22,36 +22,10 @@ #include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91sam9261_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc at91sam9261_sram_desc[] __initdata = { - { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE, - .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE), - .length = AT91SAM9261_SRAM_SIZE, - .type = MT_DEVICE, - }, -}; - -static struct map_desc at91sam9g10_sram_desc[] __initdata = { - { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE, - .pfn = __phys_to_pfn(AT91SAM9G10_SRAM_BASE), - .length = AT91SAM9G10_SRAM_SIZE, - .type = MT_DEVICE, - }, -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -302,30 +276,21 @@ static void at91sam9261_poweroff(void) * AT91SAM9261 processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9261_map_io(void) +static void __init at91sam9261_map_io(void) { - /* Map peripherals */ - iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc)); - if (cpu_is_at91sam9g10()) - iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc)); + at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE); else - iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc)); + at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE); } -void __init at91sam9261_initialize(unsigned long main_clock) +static void __init at91sam9261_initialize(void) { at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9261_poweroff; at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) | (1 << AT91SAM9261_ID_IRQ2); - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91sam9261_register_clocks(); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9261_gpio, 3); } @@ -372,14 +337,9 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91sam9261_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} +struct at91_soc __initdata at91sam9261_soc = { + .map_io = at91sam9261_map_io, + .default_irq_priority = at91sam9261_default_irq_priority, + .register_clocks = at91sam9261_register_clocks, + .init = at91sam9261_initialize, +}; diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index dc28477d14ff..8a7bfd2d5f91 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -21,28 +21,10 @@ #include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91sam9263_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE, - .pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE), - .length = AT91SAM9263_SRAM0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE, - .pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE), - .length = AT91SAM9263_SRAM1_SIZE, - .type = MT_DEVICE, - }, -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -313,24 +295,18 @@ static void at91sam9263_poweroff(void) * AT91SAM9263 processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9263_map_io(void) +static void __init at91sam9263_map_io(void) { - /* Map peripherals */ - iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc)); + at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE); + at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE); } -void __init at91sam9263_initialize(unsigned long main_clock) +static void __init at91sam9263_initialize(void) { at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9263_poweroff; at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91sam9263_register_clocks(); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9263_gpio, 5); } @@ -377,14 +353,9 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; -void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91sam9263_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} +struct at91_soc __initdata at91sam9263_soc = { + .map_io = at91sam9263_map_io, + .default_irq_priority = at91sam9263_default_irq_priority, + .register_clocks = at91sam9263_register_clocks, + .init = at91sam9263_initialize, +}; diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 2bb6ff9af1c7..0a060992ce73 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -22,23 +22,10 @@ #include <mach/at91_shdwc.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91sam9g45_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE, - .pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE), - .length = AT91SAM9G45_SRAM_SIZE, - .type = MT_DEVICE, - } -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -329,24 +316,17 @@ static void at91sam9g45_poweroff(void) * AT91SAM9G45 processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9g45_map_io(void) +static void __init at91sam9g45_map_io(void) { - /* Map peripherals */ - iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc)); + at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE); } -void __init at91sam9g45_initialize(unsigned long main_clock) +static void __init at91sam9g45_initialize(void) { at91_arch_reset = at91sam9g45_reset; pm_power_off = at91sam9g45_poweroff; at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91sam9g45_register_clocks(); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9g45_gpio, 5); } @@ -393,14 +373,9 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ0) */ }; -void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91sam9g45_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} +struct at91_soc __initdata at91sam9g45_soc = { + .map_io = at91sam9g45_map_io, + .default_irq_priority = at91sam9g45_default_irq_priority, + .register_clocks = at91sam9g45_register_clocks, + .init = at91sam9g45_initialize, +}; diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 1a40f16b66c8..0b4d64ee8774 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -16,30 +16,16 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/cpu.h> +#include <mach/at91_dbgu.h> #include <mach/at91sam9rl.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91sam9rl_io_desc[] __initdata = { - { - .virtual = AT91_VA_BASE_SYS, - .pfn = __phys_to_pfn(AT91_BASE_SYS), - .length = SZ_16K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc at91sam9rl_sram_desc[] __initdata = { - { - .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE), - .type = MT_DEVICE, - } -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -287,16 +273,11 @@ static void at91sam9rl_poweroff(void) * AT91SAM9RL processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9rl_map_io(void) +static void __init at91sam9rl_map_io(void) { - unsigned long cidr, sram_size; - - /* Map peripherals */ - iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc)); - - cidr = at91_sys_read(AT91_DBGU_CIDR); + unsigned long sram_size; - switch (cidr & AT91_CIDR_SRAMSIZ) { + switch (at91_soc_data.cidr & AT91_CIDR_SRAMSIZ) { case AT91_CIDR_SRAMSIZ_32K: sram_size = 2 * SZ_16K; break; @@ -305,25 +286,16 @@ void __init at91sam9rl_map_io(void) sram_size = SZ_16K; } - at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size; - at91sam9rl_sram_desc->length = sram_size; - /* Map SRAM */ - iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc)); + at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size); } -void __init at91sam9rl_initialize(unsigned long main_clock) +static void __init at91sam9rl_initialize(void) { at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9rl_poweroff; at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91sam9rl_register_clocks(); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9rl_gpio, 4); } @@ -370,14 +342,9 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS]) -{ - if (!priority) - priority = at91sam9rl_default_irq_priority; - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* Enable GPIO interrupts */ - at91_gpio_irq_setup(); -} +struct at91_soc __initdata at91sam9rl_soc = { + .map_io = at91sam9rl_map_io, + .default_irq_priority = at91sam9rl_default_irq_priority, + .register_clocks = at91sam9rl_register_clocks, + .init = at91sam9rl_initialize, +}; diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c index ab1d463aa47d..5aa58851eb39 100644 --- a/arch/arm/mach-at91/board-1arm.c +++ b/arch/arm/mach-at91/board-1arm.c @@ -46,7 +46,7 @@ static void __init onearm_init_early(void) at91rm9200_set_type(ARCH_REVISON_9200_PQFP); /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -63,11 +63,6 @@ static void __init onearm_init_early(void) at91_set_serial_console(0); } -static void __init onearm_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata onearm_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, @@ -97,8 +92,8 @@ static void __init onearm_board_init(void) MACHINE_START(ONEARM, "Ajeco 1ARM single board computer") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = onearm_init_early, - .init_irq = onearm_init_irq, + .init_irq = at91_init_irq_default, .init_machine = onearm_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index a4924de48c36..b0c796d42e49 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c @@ -51,7 +51,7 @@ static void __init afeb9260_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -70,12 +70,6 @@ static void __init afeb9260_init_early(void) at91_set_serial_console(0); } -static void __init afeb9260_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -219,9 +213,9 @@ static void __init afeb9260_board_init(void) MACHINE_START(AFEB9260, "Custom afeb9260 board") /* Maintainer: Sergey Lapin <slapin@ossfans.org> */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = afeb9260_init_early, - .init_irq = afeb9260_init_irq, + .init_irq = at91_init_irq_default, .init_machine = afeb9260_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index 148fccb9a25a..d1abd5898e85 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -48,7 +48,7 @@ static void __init cam60_init_early(void) { /* Initialize processor: 10 MHz crystal */ - at91sam9260_initialize(10000000); + at91_initialize(10000000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -57,12 +57,6 @@ static void __init cam60_init_early(void) at91_set_serial_console(0); } -static void __init cam60_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * USB Host */ @@ -199,8 +193,8 @@ static void __init cam60_board_init(void) MACHINE_START(CAM60, "KwikByte CAM60") /* Maintainer: KwikByte */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = cam60_init_early, - .init_irq = cam60_init_irq, + .init_irq = at91_init_irq_default, .init_machine = cam60_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c index 1904fdf87613..b78c4a34e08f 100644 --- a/arch/arm/mach-at91/board-cap9adk.c +++ b/arch/arm/mach-at91/board-cap9adk.c @@ -53,7 +53,7 @@ static void __init cap9adk_init_early(void) { /* Initialize processor: 12 MHz crystal */ - at91cap9_initialize(12000000); + at91_initialize(12000000); /* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */ at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11); @@ -65,12 +65,6 @@ static void __init cap9adk_init_early(void) at91_set_serial_console(0); } -static void __init cap9adk_init_irq(void) -{ - at91cap9_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -397,8 +391,8 @@ static void __init cap9adk_board_init(void) MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK") /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */ .timer = &at91sam926x_timer, - .map_io = at91cap9_map_io, + .map_io = at91_map_io, .init_early = cap9adk_init_early, - .init_irq = cap9adk_init_irq, + .init_irq = at91_init_irq_default, .init_machine = cap9adk_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index f36b18687494..c578c5d90728 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -43,7 +43,7 @@ static void __init carmeva_init_early(void) { /* Initialize processor: 20.000 MHz crystal */ - at91rm9200_initialize(20000000); + at91_initialize(20000000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -57,11 +57,6 @@ static void __init carmeva_init_early(void) at91_set_serial_console(0); } -static void __init carmeva_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata carmeva_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, @@ -163,8 +158,8 @@ static void __init carmeva_board_init(void) MACHINE_START(CARMEVA, "Carmeva") /* Maintainer: Conitec Datasystems */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = carmeva_init_early, - .init_irq = carmeva_init_irq, + .init_irq = at91_init_irq_default, .init_machine = carmeva_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c index 980511084fe4..f4da8a16d5dc 100644 --- a/arch/arm/mach-at91/board-cpu9krea.c +++ b/arch/arm/mach-at91/board-cpu9krea.c @@ -50,7 +50,7 @@ static void __init cpu9krea_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* DGBU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -81,11 +81,6 @@ static void __init cpu9krea_init_early(void) at91_set_serial_console(0); } -static void __init cpu9krea_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - /* * USB Host port */ @@ -376,8 +371,8 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20") #endif /* Maintainer: Eric Benard - EUKREA Electromatique */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = cpu9krea_init_early, - .init_irq = cpu9krea_init_irq, + .init_irq = at91_init_irq_default, .init_machine = cpu9krea_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c index 6daabe3907a1..2d919f5a4f57 100644 --- a/arch/arm/mach-at91/board-cpuat91.c +++ b/arch/arm/mach-at91/board-cpuat91.c @@ -57,7 +57,7 @@ static void __init cpuat91_init_early(void) at91rm9200_set_type(ARCH_REVISON_9200_PQFP); /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -82,11 +82,6 @@ static void __init cpuat91_init_early(void) at91_set_serial_console(0); } -static void __init cpuat91_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata cpuat91_eth_data = { .is_rmii = 1, }; @@ -180,8 +175,8 @@ static void __init cpuat91_board_init(void) MACHINE_START(CPUAT91, "Eukrea") /* Maintainer: Eric Benard - EUKREA Electromatique */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = cpuat91_init_early, - .init_irq = cpuat91_init_irq, + .init_irq = at91_init_irq_default, .init_machine = cpuat91_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index d98bcec1dfe0..17654d5e94e6 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c @@ -46,7 +46,7 @@ static void __init csb337_init_early(void) { /* Initialize processor: 3.6864 MHz crystal */ - at91rm9200_initialize(3686400); + at91_initialize(3686400); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); @@ -58,11 +58,6 @@ static void __init csb337_init_early(void) at91_set_serial_console(0); } -static void __init csb337_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata csb337_eth_data = { .phy_irq_pin = AT91_PIN_PC2, .is_rmii = 0, @@ -258,8 +253,8 @@ static void __init csb337_board_init(void) MACHINE_START(CSB337, "Cogent CSB337") /* Maintainer: Bill Gatliff */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = csb337_init_early, - .init_irq = csb337_init_irq, + .init_irq = at91_init_irq_default, .init_machine = csb337_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index 019aab4e20b0..72b55674616c 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c @@ -43,7 +43,7 @@ static void __init csb637_init_early(void) { /* Initialize processor: 3.6864 MHz crystal */ - at91rm9200_initialize(3686400); + at91_initialize(3686400); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -52,11 +52,6 @@ static void __init csb637_init_early(void) at91_set_serial_console(0); } -static void __init csb637_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata csb637_eth_data = { .phy_irq_pin = AT91_PIN_PC0, .is_rmii = 0, @@ -139,8 +134,8 @@ static void __init csb637_board_init(void) MACHINE_START(CSB637, "Cogent CSB637") /* Maintainer: Bill Gatliff */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = csb637_init_early, - .init_irq = csb637_init_irq, + .init_irq = at91_init_irq_default, .init_machine = csb637_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c index e9484535cbc8..01170a2766a8 100644 --- a/arch/arm/mach-at91/board-eb9200.c +++ b/arch/arm/mach-at91/board-eb9200.c @@ -43,7 +43,7 @@ static void __init eb9200_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -60,11 +60,6 @@ static void __init eb9200_init_early(void) at91_set_serial_console(0); } -static void __init eb9200_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata eb9200_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, @@ -121,8 +116,8 @@ static void __init eb9200_board_init(void) MACHINE_START(ATEB9200, "Embest ATEB9200") .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = eb9200_init_early, - .init_irq = eb9200_init_irq, + .init_irq = at91_init_irq_default, .init_machine = eb9200_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c index a6f57faa10a7..7c0313c51f26 100644 --- a/arch/arm/mach-at91/board-ecbat91.c +++ b/arch/arm/mach-at91/board-ecbat91.c @@ -49,7 +49,7 @@ static void __init ecb_at91init_early(void) at91rm9200_set_type(ARCH_REVISON_9200_PQFP); /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); @@ -64,11 +64,6 @@ static void __init ecb_at91init_early(void) at91_set_serial_console(0); } -static void __init ecb_at91init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata ecb_at91eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 0, @@ -173,8 +168,8 @@ static void __init ecb_at91board_init(void) MACHINE_START(ECBAT91, "emQbit's ECB_AT91") /* Maintainer: emQbit.com */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = ecb_at91init_early, - .init_irq = ecb_at91init_irq, + .init_irq = at91_init_irq_default, .init_machine = ecb_at91board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c index bfc0062d1483..8252c722607b 100644 --- a/arch/arm/mach-at91/board-eco920.c +++ b/arch/arm/mach-at91/board-eco920.c @@ -35,7 +35,7 @@ static void __init eco920_init_early(void) /* Set cpu type: PQFP */ at91rm9200_set_type(ARCH_REVISON_9200_PQFP); - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); @@ -47,11 +47,6 @@ static void __init eco920_init_early(void) at91_set_serial_console(0); } -static void __init eco920_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata eco920_eth_data = { .phy_irq_pin = AT91_PIN_PC2, .is_rmii = 1, @@ -135,8 +130,8 @@ static void __init eco920_board_init(void) MACHINE_START(ECO920, "eco920") /* Maintainer: Sascha Hauer */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = eco920_init_early, - .init_irq = eco920_init_irq, + .init_irq = at91_init_irq_default, .init_machine = eco920_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c index 466c063b8d21..4c3f65d9c59b 100644 --- a/arch/arm/mach-at91/board-flexibity.c +++ b/arch/arm/mach-at91/board-flexibity.c @@ -40,7 +40,7 @@ static void __init flexibity_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -49,11 +49,6 @@ static void __init flexibity_init_early(void) at91_set_serial_console(0); } -static void __init flexibity_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - /* USB Host port */ static struct at91_usbh_data __initdata flexibity_usbh_data = { .ports = 2, @@ -155,8 +150,8 @@ static void __init flexibity_board_init(void) MACHINE_START(FLEXIBITY, "Flexibity Connect") /* Maintainer: Maxim Osipov */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = flexibity_init_early, - .init_irq = flexibity_init_irq, + .init_irq = at91_init_irq_default, .init_machine = flexibity_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c index e2d1dc9eff45..f27d1a780cfa 100644 --- a/arch/arm/mach-at91/board-foxg20.c +++ b/arch/arm/mach-at91/board-foxg20.c @@ -60,7 +60,7 @@ static void __init foxg20_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -101,12 +101,6 @@ static void __init foxg20_init_early(void) } -static void __init foxg20_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -267,8 +261,8 @@ static void __init foxg20_board_init(void) MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20") /* Maintainer: Sergio Tanzilli */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = foxg20_init_early, - .init_irq = foxg20_init_irq, + .init_irq = at91_init_irq_default, .init_machine = foxg20_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index 1d4f36b3cb27..34d27127c4d4 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c @@ -75,11 +75,6 @@ static void __init gsia18s_init_early(void) at91_register_uart(AT91SAM9260_ID_US4, 5, 0); } -static void __init init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - /* * Two USB Host ports */ @@ -577,7 +572,7 @@ static void __init gsia18s_board_init(void) MACHINE_START(GSIA18S, "GS_IA18_S") .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = gsia18s_init_early, .init_irq = init_irq, .init_machine = gsia18s_board_init, diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c index 9b003ff744ba..4a170890b3b1 100644 --- a/arch/arm/mach-at91/board-kafa.c +++ b/arch/arm/mach-at91/board-kafa.c @@ -46,7 +46,7 @@ static void __init kafa_init_early(void) at91rm9200_set_type(ARCH_REVISON_9200_PQFP); /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* Set up the LEDs */ at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); @@ -61,11 +61,6 @@ static void __init kafa_init_early(void) at91_set_serial_console(0); } -static void __init kafa_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata kafa_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 0, @@ -99,8 +94,8 @@ static void __init kafa_board_init(void) MACHINE_START(KAFA, "Sperry-Sun KAFA") /* Maintainer: Sergei Sharonov */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = kafa_init_early, - .init_irq = kafa_init_irq, + .init_irq = at91_init_irq_default, .init_machine = kafa_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index a813a74b65f9..9dc8d496ead1 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c @@ -48,7 +48,7 @@ static void __init kb9202_init_early(void) at91rm9200_set_type(ARCH_REVISON_9200_PQFP); /* Initialize processor: 10 MHz crystal */ - at91rm9200_initialize(10000000); + at91_initialize(10000000); /* Set up the LEDs */ at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); @@ -69,11 +69,6 @@ static void __init kb9202_init_early(void) at91_set_serial_console(0); } -static void __init kb9202_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata kb9202_eth_data = { .phy_irq_pin = AT91_PIN_PB29, .is_rmii = 0, @@ -140,8 +135,8 @@ static void __init kb9202_board_init(void) MACHINE_START(KB9200, "KB920x") /* Maintainer: KwikByte, Inc. */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = kb9202_init_early, - .init_irq = kb9202_init_irq, + .init_irq = at91_init_irq_default, .init_machine = kb9202_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c index 961e805db68c..9bc6ab32e0ac 100644 --- a/arch/arm/mach-at91/board-neocore926.c +++ b/arch/arm/mach-at91/board-neocore926.c @@ -54,7 +54,7 @@ static void __init neocore926_init_early(void) { /* Initialize processor: 20 MHz crystal */ - at91sam9263_initialize(20000000); + at91_initialize(20000000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -66,12 +66,6 @@ static void __init neocore926_init_early(void) at91_set_serial_console(0); } -static void __init neocore926_init_irq(void) -{ - at91sam9263_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -388,8 +382,8 @@ static void __init neocore926_board_init(void) MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926") /* Maintainer: ADENEO */ .timer = &at91sam926x_timer, - .map_io = at91sam9263_map_io, + .map_io = at91_map_io, .init_early = neocore926_init_early, - .init_irq = neocore926_init_irq, + .init_irq = at91_init_irq_default, .init_machine = neocore926_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index 21a21af25878..23785e2c470d 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c @@ -53,13 +53,6 @@ static void __init pcontrol_g20_init_early(void) at91_register_uart(AT91SAM9260_ID_US4, 3, 0); } - -static void __init init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { .ncs_read_setup = 16, .nrd_setup = 18, @@ -223,7 +216,7 @@ static void __init pcontrol_g20_board_init(void) MACHINE_START(PCONTROL_G20, "PControl G20") /* Maintainer: pgsellmann@portner-elektronik.at */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = pcontrol_g20_init_early, .init_irq = init_irq, .init_machine = pcontrol_g20_board_init, diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c index 756cc2a745dd..b7b8390e8a00 100644 --- a/arch/arm/mach-at91/board-picotux200.c +++ b/arch/arm/mach-at91/board-picotux200.c @@ -46,7 +46,7 @@ static void __init picotux200_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -60,11 +60,6 @@ static void __init picotux200_init_early(void) at91_set_serial_console(0); } -static void __init picotux200_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata picotux200_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, @@ -124,8 +119,8 @@ static void __init picotux200_board_init(void) MACHINE_START(PICOTUX2XX, "picotux 200") /* Maintainer: Kleinhenz Elektronik GmbH */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = picotux200_init_early, - .init_irq = picotux200_init_irq, + .init_irq = at91_init_irq_default, .init_machine = picotux200_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c index d1a6001b0bd8..81f911033681 100644 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ b/arch/arm/mach-at91/board-qil-a9260.c @@ -51,7 +51,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ - at91sam9260_initialize(12000000); + at91_initialize(12000000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -72,12 +72,6 @@ static void __init ek_init_early(void) } -static void __init ek_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -269,8 +263,8 @@ static void __init ek_board_init(void) MACHINE_START(QIL_A9260, "CALAO QIL_A9260") /* Maintainer: calao-systems */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c index aef9627710b0..6f08faadb474 100644 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ b/arch/arm/mach-at91/board-rm9200dk.c @@ -48,7 +48,7 @@ static void __init dk_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); @@ -65,11 +65,6 @@ static void __init dk_init_early(void) at91_set_serial_console(0); } -static void __init dk_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata dk_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, @@ -228,8 +223,8 @@ static void __init dk_board_init(void) MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") /* Maintainer: SAN People/Atmel */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = dk_init_early, - .init_irq = dk_init_irq, + .init_irq = at91_init_irq_default, .init_machine = dk_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index 015a02183080..85bcccd7b9e4 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c @@ -48,7 +48,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); @@ -65,11 +65,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - static struct at91_eth_data __initdata ek_eth_data = { .phy_irq_pin = AT91_PIN_PC4, .is_rmii = 1, @@ -194,8 +189,8 @@ static void __init ek_board_init(void) MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") /* Maintainer: SAN People/Atmel */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index aaf1bf0989b3..4d3a02f1289e 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c @@ -47,7 +47,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); @@ -67,12 +67,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -213,8 +207,8 @@ static void __init ek_board_init(void) MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260") /* Maintainer: Olimex */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index d600dc123227..12f75a31301c 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -53,7 +53,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -70,12 +70,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -354,8 +348,8 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") /* Maintainer: Atmel */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index f897f84d43dc..785b48433836 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -57,7 +57,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9261_initialize(18432000); + at91_initialize(18432000); /* Setup the LEDs */ at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); @@ -69,12 +69,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9261_init_interrupts(NULL); -} - - /* * DM9000 ethernet device */ @@ -621,8 +615,8 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") #endif /* Maintainer: Atmel */ .timer = &at91sam926x_timer, - .map_io = at91sam9261_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 605b26f40a4c..70e5646a1445 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -56,7 +56,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 16.367 MHz crystal */ - at91sam9263_initialize(16367660); + at91_initialize(16367660); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -68,12 +68,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9263_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -452,8 +446,8 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK") /* Maintainer: Atmel */ .timer = &at91sam926x_timer, - .map_io = at91sam9263_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 7624cf0d006b..c08a1e79528d 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -64,7 +64,7 @@ static int inline ek_have_2mmc(void) static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -81,12 +81,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -404,17 +398,17 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") /* Maintainer: Atmel */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") /* Maintainer: Atmel */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 063c95d0e8f0..7851efd41a09 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -50,7 +50,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ - at91sam9g45_initialize(12000000); + at91_initialize(12000000); /* DGBU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -63,12 +63,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9g45_init_interrupts(NULL); -} - - /* * USB HS Host port (common to OHCI & EHCI) */ @@ -422,8 +416,8 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") /* Maintainer: Atmel */ .timer = &at91sam926x_timer, - .map_io = at91sam9g45_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index effb399a80a6..4f14b54b93a8 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -41,7 +41,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ - at91sam9rl_initialize(12000000); + at91_initialize(12000000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -53,12 +53,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9rl_init_interrupts(NULL); -} - - /* * USB HS Device port */ @@ -330,8 +324,8 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") /* Maintainer: Atmel */ .timer = &at91sam926x_timer, - .map_io = at91sam9rl_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index 3eb0a1153cc8..25cd3ffce1ee 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -42,7 +42,7 @@ static void __init snapper9260_init_early(void) { - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* Debug on ttyS0 */ at91_register_uart(0, 0, 0); @@ -55,11 +55,6 @@ static void __init snapper9260_init_early(void) at91_register_uart(AT91SAM9260_ID_US2, 3, 0); } -static void __init snapper9260_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - static struct at91_usbh_data __initdata snapper9260_usbh_data = { .ports = 2, }; @@ -179,9 +174,9 @@ static void __init snapper9260_board_init(void) MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = snapper9260_init_early, - .init_irq = snapper9260_init_irq, + .init_irq = at91_init_irq_default, .init_machine = snapper9260_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index 5e5c85688f5f..9821be2fab97 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c @@ -35,7 +35,7 @@ void __init stamp9g20_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); + at91_initialize(18432000); /* DGBU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -76,12 +76,6 @@ static void __init portuxg20_init_early(void) at91_register_uart(AT91SAM9260_ID_US5, 6, 0); } -static void __init init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * NAND flash */ @@ -299,7 +293,7 @@ static void __init stamp9g20evb_board_init(void) MACHINE_START(PORTUXG20, "taskit PortuxG20") /* Maintainer: taskit GmbH */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = portuxg20_init_early, .init_irq = init_irq, .init_machine = portuxg20_board_init, @@ -308,7 +302,7 @@ MACHINE_END MACHINE_START(STAMP9G20, "taskit Stamp9G20") /* Maintainer: taskit GmbH */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = stamp9g20evb_init_early, .init_irq = init_irq, .init_machine = stamp9g20evb_board_init, diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c index 0e784e6fedec..8c4c1a02c4be 100644 --- a/arch/arm/mach-at91/board-usb-a9260.c +++ b/arch/arm/mach-at91/board-usb-a9260.c @@ -51,7 +51,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ - at91sam9260_initialize(12000000); + at91_initialize(12000000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -60,12 +60,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -229,8 +223,8 @@ static void __init ek_board_init(void) MACHINE_START(USB_A9260, "CALAO USB_A9260") /* Maintainer: calao-systems */ .timer = &at91sam926x_timer, - .map_io = at91sam9260_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c index cf626dd14b2c..25e793782a4e 100644 --- a/arch/arm/mach-at91/board-usb-a9263.c +++ b/arch/arm/mach-at91/board-usb-a9263.c @@ -50,7 +50,7 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.00 MHz crystal */ - at91sam9263_initialize(12000000); + at91_initialize(12000000); /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); @@ -59,12 +59,6 @@ static void __init ek_init_early(void) at91_set_serial_console(0); } -static void __init ek_init_irq(void) -{ - at91sam9263_init_interrupts(NULL); -} - - /* * USB Host port */ @@ -245,8 +239,8 @@ static void __init ek_board_init(void) MACHINE_START(USB_A9263, "CALAO USB_A9263") /* Maintainer: calao-systems */ .timer = &at91sam926x_timer, - .map_io = at91sam9263_map_io, + .map_io = at91_map_io, .init_early = ek_init_early, - .init_irq = ek_init_irq, + .init_irq = at91_init_irq_default, .init_machine = ek_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c index c208cc334d7d..95edcbd2aec6 100644 --- a/arch/arm/mach-at91/board-yl-9200.c +++ b/arch/arm/mach-at91/board-yl-9200.c @@ -56,7 +56,7 @@ static void __init yl9200_init_early(void) at91rm9200_set_type(ARCH_REVISON_9200_PQFP); /* Initialize processor: 18.432 MHz crystal */ - at91rm9200_initialize(18432000); + at91_initialize(18432000); /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); @@ -79,12 +79,6 @@ static void __init yl9200_init_early(void) at91_set_serial_console(0); } -static void __init yl9200_init_irq(void) -{ - at91rm9200_init_interrupts(NULL); -} - - /* * LEDs */ @@ -599,8 +593,8 @@ static void __init yl9200_board_init(void) MACHINE_START(YL9200, "uCdragon YL-9200") /* Maintainer: S.Birtles */ .timer = &at91rm9200_timer, - .map_io = at91rm9200_map_io, + .map_io = at91_map_io, .init_early = yl9200_init_early, - .init_irq = yl9200_init_irq, + .init_irq = at91_init_irq_default, .init_machine = yl9200_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 8ff3418f3430..938b34f57741 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -11,35 +11,19 @@ #include <linux/clkdev.h> /* Map io */ -extern void __init at91rm9200_map_io(void); -extern void __init at91sam9260_map_io(void); -extern void __init at91sam9261_map_io(void); -extern void __init at91sam9263_map_io(void); -extern void __init at91sam9rl_map_io(void); -extern void __init at91sam9g45_map_io(void); -extern void __init at91x40_map_io(void); -extern void __init at91cap9_map_io(void); +extern void __init at91_map_io(void); +extern void __init at91_init_sram(int bank, unsigned long base, + unsigned int length); /* Processors */ extern void __init at91rm9200_set_type(int type); -extern void __init at91rm9200_initialize(unsigned long main_clock); -extern void __init at91sam9260_initialize(unsigned long main_clock); -extern void __init at91sam9261_initialize(unsigned long main_clock); -extern void __init at91sam9263_initialize(unsigned long main_clock); -extern void __init at91sam9rl_initialize(unsigned long main_clock); -extern void __init at91sam9g45_initialize(unsigned long main_clock); +extern void __init at91_initialize(unsigned long main_clock); extern void __init at91x40_initialize(unsigned long main_clock); -extern void __init at91cap9_initialize(unsigned long main_clock); /* Interrupts */ -extern void __init at91rm9200_init_interrupts(unsigned int priority[]); -extern void __init at91sam9260_init_interrupts(unsigned int priority[]); -extern void __init at91sam9261_init_interrupts(unsigned int priority[]); -extern void __init at91sam9263_init_interrupts(unsigned int priority[]); -extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); -extern void __init at91sam9g45_init_interrupts(unsigned int priority[]); +extern void __init at91_init_irq_default(void); +extern void __init at91_init_interrupts(unsigned int priority[]); extern void __init at91x40_init_interrupts(unsigned int priority[]); -extern void __init at91cap9_init_interrupts(unsigned int priority[]); extern void __init at91_aic_init(unsigned int priority[]); /* Timer */ @@ -49,7 +33,6 @@ extern struct sys_timer at91sam926x_timer; extern struct sys_timer at91x40_timer; /* Clocks */ -extern int __init at91_clock_init(unsigned long main_clock); /* * function to specify the clock of the default console. As we do not * use the device/driver bus, the dev_name is not intialize. So we need @@ -62,6 +45,11 @@ extern void __init at91sam9263_set_console_clock(int id); extern void __init at91sam9rl_set_console_clock(int id); extern void __init at91sam9g45_set_console_clock(int id); extern void __init at91cap9_set_console_clock(int id); +#ifdef CONFIG_AT91_PMC_UNIT +extern int __init at91_clock_init(unsigned long main_clock); +#else +static int inline at91_clock_init(unsigned long main_clock) { return 0; } +#endif struct device; /* Power Management */ diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h index 6dcaa7716871..bacf3e86d075 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h @@ -16,22 +16,25 @@ #ifndef AT91_DBGU_H #define AT91_DBGU_H +#define dbgu_readl(dbgu, field) \ + __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBUG_ ## field) + #ifdef AT91_DBGU -#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ -#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ -#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ +#define AT91_DBGU_CR (0x00) /* Control Register */ +#define AT91_DBGU_MR (0x04) /* Mode Register */ +#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ -#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ -#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ -#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ -#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ -#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ +#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */ +#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */ +#define AT91_DBGU_SR (0x14) /* Status Register */ +#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */ +#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ +#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */ -#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ -#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ -#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ +#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */ +#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */ +#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ #endif /* AT91_DBGU */ diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h index 665993849a7b..c5df1e8f1955 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/arch/arm/mach-at91/include/mach/at91cap9.h @@ -75,7 +75,6 @@ #define AT91CAP9_BASE_EMAC 0xfffbc000 #define AT91CAP9_BASE_ADC 0xfffc0000 #define AT91CAP9_BASE_ISI 0xfffc4000 -#define AT91_BASE_SYS 0xffffe200 /* * System Peripherals (offset from AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index 99e0f8d02d7b..e4037b500302 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h @@ -74,7 +74,6 @@ #define AT91RM9200_BASE_SSC1 0xfffd4000 #define AT91RM9200_BASE_SSC2 0xfffd8000 #define AT91RM9200_BASE_SPI 0xfffe0000 -#define AT91_BASE_SYS 0xfffff000 /* diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 8b6bf835cd73..9a791165913f 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -76,7 +76,6 @@ #define AT91SAM9260_BASE_TC4 0xfffdc040 #define AT91SAM9260_BASE_TC5 0xfffdc080 #define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800 /* * System Peripherals (offset from AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index eafbddaf523c..ce596204cefa 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -60,7 +60,6 @@ #define AT91SAM9261_BASE_SSC2 0xfffc4000 #define AT91SAM9261_BASE_SPI0 0xfffc8000 #define AT91SAM9261_BASE_SPI1 0xfffcc000 -#define AT91_BASE_SYS 0xffffea00 /* diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index e2d348213a7b..f1b92961a2b1 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -70,7 +70,6 @@ #define AT91SAM9263_BASE_EMAC 0xfffbc000 #define AT91SAM9263_BASE_ISI 0xfffc4000 #define AT91SAM9263_BASE_2DGE 0xfffc8000 -#define AT91_BASE_SYS 0xffffe000 /* * System Peripherals (offset from AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 659304aa73d9..2c611b9a0138 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -82,7 +82,6 @@ #define AT91SAM9G45_BASE_TC3 0xfffd4000 #define AT91SAM9G45_BASE_TC4 0xfffd4040 #define AT91SAM9G45_BASE_TC5 0xfffd4080 -#define AT91_BASE_SYS 0xffffe200 /* * System Peripherals (offset from AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 41dbbe61055c..1aabacd315d4 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -64,7 +64,6 @@ #define AT91SAM9RL_BASE_TSC 0xfffd0000 #define AT91SAM9RL_BASE_UDPHS 0xfffd4000 #define AT91SAM9RL_BASE_AC97C 0xfffd8000 -#define AT91_BASE_SYS 0xffffc000 /* diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index df966c2bc2d4..c44f99bb5e69 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -1,7 +1,8 @@ /* * arch/arm/mach-at91/include/mach/cpu.h * - * Copyright (C) 2006 SAN People + * Copyright (C) 2006 SAN People + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,12 +11,8 @@ * */ -#ifndef __ASM_ARCH_CPU_H -#define __ASM_ARCH_CPU_H - -#include <mach/hardware.h> -#include <mach/at91_dbgu.h> - +#ifndef __MACH_CPU_H__ +#define __MACH_CPU_H__ #define ARCH_ID_AT91RM9200 0x09290780 #define ARCH_ID_AT91SAM9260 0x019803a0 @@ -39,16 +36,6 @@ #define ARCH_ID_AT91M40807 0x14080745 #define ARCH_ID_AT91R40008 0x44000840 -static inline unsigned long at91_cpu_identify(void) -{ - return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); -} - -static inline unsigned long at91_cpu_fully_identify(void) -{ - return at91_sys_read(AT91_DBGU_CIDR); -} - #define ARCH_EXID_AT91SAM9M11 0x00000001 #define ARCH_EXID_AT91SAM9M10 0x00000002 #define ARCH_EXID_AT91SAM9G46 0x00000003 @@ -60,40 +47,80 @@ static inline unsigned long at91_cpu_fully_identify(void) #define ARCH_EXID_AT91SAM9G25 0x00000003 #define ARCH_EXID_AT91SAM9X25 0x00000004 -static inline unsigned long at91_exid_identify(void) -{ - return at91_sys_read(AT91_DBGU_EXID); -} - - #define ARCH_FAMILY_AT91X92 0x09200000 #define ARCH_FAMILY_AT91SAM9 0x01900000 #define ARCH_FAMILY_AT91SAM9XE 0x02900000 -static inline unsigned long at91_arch_identify(void) -{ - return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); -} - -#ifdef CONFIG_ARCH_AT91CAP9 -#include <mach/at91_pmc.h> - +/* PMC revision */ #define ARCH_REVISION_CAP9_B 0x399 #define ARCH_REVISION_CAP9_C 0x601 -static inline unsigned long at91cap9_rev_identify(void) +/* RM9200 type */ +#define ARCH_REVISON_9200_BGA (0 << 0) +#define ARCH_REVISON_9200_PQFP (1 << 0) + +enum at91_soc_type { + /* 920T */ + AT91_SOC_RM9200, + + /* CAP */ + AT91_SOC_CAP9, + + /* SAM92xx */ + AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, + + /* SAM9Gxx */ + AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45, + + /* SAM9RL */ + AT91_SOC_SAM9RL, + + /* SAM9X5 */ + AT91_SOC_SAM9X5, + + /* Unknown type */ + AT91_SOC_NONE +}; + +enum at91_soc_subtype { + /* RM9200 */ + AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, + + /* CAP9 */ + AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C, + + /* SAM9260 */ + AT91_SOC_SAM9XE, + + /* SAM9G45 */ + AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11, + + /* SAM9X5 */ + AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, + AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, + + /* Unknown subtype */ + AT91_SOC_SUBTYPE_NONE +}; + +struct at91_socinfo { + unsigned int type, subtype; + unsigned int cidr, exid; +}; + +extern struct at91_socinfo at91_soc_data; +const char *at91_get_soc_type(struct at91_socinfo *c); +const char *at91_get_soc_subtype(struct at91_socinfo *c); + +static inline int at91_soc_is_detected(void) { - return (at91_sys_read(AT91_PMC_VER)); + return at91_soc_data.type != AT91_SOC_NONE; } -#endif #ifdef CONFIG_ARCH_AT91RM9200 -extern int rm9200_type; -#define ARCH_REVISON_9200_BGA (0 << 0) -#define ARCH_REVISON_9200_PQFP (1 << 0) -#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) -#define cpu_is_at91rm9200_bga() (!cpu_is_at91rm9200_pqfp()) -#define cpu_is_at91rm9200_pqfp() (cpu_is_at91rm9200() && rm9200_type & ARCH_REVISON_9200_PQFP) +#define cpu_is_at91rm9200() (at91_soc_data.type == AT91_SOC_RM9200) +#define cpu_is_at91rm9200_bga() (at91_soc_data.subtype == AT91_SOC_RM9200_BGA) +#define cpu_is_at91rm9200_pqfp() (at91_soc_data.subtype == AT91_SOC_RM9200_PQFP) #else #define cpu_is_at91rm9200() (0) #define cpu_is_at91rm9200_bga() (0) @@ -101,52 +128,49 @@ extern int rm9200_type; #endif #ifdef CONFIG_ARCH_AT91SAM9260 -#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE) -#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe()) +#define cpu_is_at91sam9xe() (at91_soc_data.subtype == AT91_SOC_SAM9XE) +#define cpu_is_at91sam9260() (at91_soc_data.type == AT91_SOC_SAM9260) #else #define cpu_is_at91sam9xe() (0) #define cpu_is_at91sam9260() (0) #endif #ifdef CONFIG_ARCH_AT91SAM9G20 -#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20) +#define cpu_is_at91sam9g20() (at91_soc_data.type == AT91_SOC_SAM9G20) #else #define cpu_is_at91sam9g20() (0) #endif #ifdef CONFIG_ARCH_AT91SAM9261 -#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) +#define cpu_is_at91sam9261() (at91_soc_data.type == AT91_SOC_SAM9261) #else #define cpu_is_at91sam9261() (0) #endif #ifdef CONFIG_ARCH_AT91SAM9G10 -#define cpu_is_at91sam9g10() ((at91_cpu_identify() & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) +#define cpu_is_at91sam9g10() (at91_soc_data.type == AT91_SOC_SAM9G10) #else #define cpu_is_at91sam9g10() (0) #endif #ifdef CONFIG_ARCH_AT91SAM9263 -#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) +#define cpu_is_at91sam9263() (at91_soc_data.type == AT91_SOC_SAM9263) #else #define cpu_is_at91sam9263() (0) #endif #ifdef CONFIG_ARCH_AT91SAM9RL -#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) +#define cpu_is_at91sam9rl() (at91_soc_data.type == AT91_SOC_SAM9RL) #else #define cpu_is_at91sam9rl() (0) #endif #ifdef CONFIG_ARCH_AT91SAM9G45 -#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) -#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES) -#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9M10)) -#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G46)) -#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9M11)) +#define cpu_is_at91sam9g45() (at91_soc_data.type == AT91_SOC_SAM9G45) +#define cpu_is_at91sam9g45es() (at91_soc_data.subtype == AT91_SOC_SAM9G45ES) +#define cpu_is_at91sam9m10() (at91_soc_data.subtype == AT91_SOC_SAM9M10) +#define cpu_is_at91sam9g46() (at91_soc_data.subtype == AT91_SOC_SAM9G46) +#define cpu_is_at91sam9m11() (at91_soc_data.subtype == AT91_SOC_SAM9M11) #else #define cpu_is_at91sam9g45() (0) #define cpu_is_at91sam9g45es() (0) @@ -156,17 +180,12 @@ extern int rm9200_type; #endif #ifdef CONFIG_ARCH_AT91SAM9X5 -#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5) -#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G15)) -#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G35)) -#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9X35)) -#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9G25)) -#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \ - (at91_exid_identify() == ARCH_EXID_AT91SAM9X25)) +#define cpu_is_at91sam9x5() (at91_soc_data.type == AT91_SOC_SAM9X5) +#define cpu_is_at91sam9g15() (at91_soc_data.subtype == AT91_SOC_SAM9G15) +#define cpu_is_at91sam9g35() (at91_soc_data.subtype == AT91_SOC_SAM9G35) +#define cpu_is_at91sam9x35() (at91_soc_data.subtype == AT91_SOC_SAM9X35) +#define cpu_is_at91sam9g25() (at91_soc_data.subtype == AT91_SOC_SAM9G25) +#define cpu_is_at91sam9x25() (at91_soc_data.subtype == AT91_SOC_SAM9X25) #else #define cpu_is_at91sam9x5() (0) #define cpu_is_at91sam9g15() (0) @@ -177,9 +196,9 @@ extern int rm9200_type; #endif #ifdef CONFIG_ARCH_AT91CAP9 -#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) -#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) -#define cpu_is_at91cap9_revC() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_C) +#define cpu_is_at91cap9() (at91_soc_data.type == AT91_SOC_CAP9) +#define cpu_is_at91cap9_revB() (at91_soc_data.subtype == AT91_SOC_CAP9_REV_B) +#define cpu_is_at91cap9_revC() (at91_soc_data.subtype == AT91_SOC_CAP9_REV_C) #else #define cpu_is_at91cap9() (0) #define cpu_is_at91cap9_revB() (0) @@ -192,4 +211,4 @@ extern int rm9200_type; */ #define cpu_is_at32ap7000() (0) -#endif +#endif /* __MACH_CPU_H__ */ diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S index 0f959faf74a9..bc1e0b2e2f4f 100644 --- a/arch/arm/mach-at91/include/mach/debug-macro.S +++ b/arch/arm/mach-at91/include/mach/debug-macro.S @@ -15,23 +15,23 @@ #include <mach/at91_dbgu.h> .macro addruart, rp, rv - ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) - ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) + ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) + ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) .endm .macro senduart,rd,rx - strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register + strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register .endm .macro waituart,rd,rx -1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register - tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit +1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register + tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit beq 1001b .endm .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register - tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete +1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register + tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete beq 1001b .endm diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 1008b9fb5074..483478d8be6b 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -36,6 +36,20 @@ #error "Unsupported AT91 processor" #endif +#if !defined(CONFIG_ARCH_AT91X40) +/* + * On all at91 except rm9200 and x40 have the System Controller starts + * at address 0xffffc000 and has a size of 16KiB. + * + * On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting + * at 0xfffff000 + * + * Removes the individual definitions of AT91_BASE_SYS and + * replaces them with a common version at base 0xfffffc000 and size 16KiB + * and map the same memory space + */ +#define AT91_BASE_SYS 0xffffc000 +#endif /* * Peripheral identifiers/interrupts. diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h index 0b0cccc46e68..6ffc53b8cd71 100644 --- a/arch/arm/mach-at91/include/mach/io.h +++ b/arch/arm/mach-at91/include/mach/io.h @@ -21,14 +21,28 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H +#include <mach/hardware.h> + #define IO_SPACE_LIMIT 0xFFFFFFFF #define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) - #ifndef __ASSEMBLY__ +#ifndef CONFIG_ARCH_AT91X40 +#define __arch_ioremap at91_ioremap +#define __arch_iounmap at91_iounmap +#endif + +void __iomem *at91_ioremap(unsigned long phys, size_t size, unsigned int type); +void at91_iounmap(volatile void __iomem *addr); + +static inline unsigned int at91_readl(unsigned int pa) +{ + return __raw_readl((void __iomem *)AT91_IO_P2V(pa)); +} + static inline unsigned int at91_sys_read(unsigned int reg_offset) { void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c new file mode 100644 index 000000000000..f2ad787f4e7c --- /dev/null +++ b/arch/arm/mach-at91/setup.c @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2007 Atmel Corporation. + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <linux/module.h> +#include <linux/io.h> +#include <linux/mm.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/cpu.h> +#include <mach/at91_dbgu.h> +#include <mach/at91_pmc.h> + +#include "soc.h" +#include "generic.h" + +struct at91_soc __initdata at91_boot_soc; + +struct at91_socinfo at91_soc_data; +EXPORT_SYMBOL(at91_soc_data); + +void __init at91rm9200_set_type(int type) +{ + if (type == ARCH_REVISON_9200_PQFP) + at91_soc_data.subtype = AT91_SOC_RM9200_BGA; + else + at91_soc_data.subtype = AT91_SOC_RM9200_PQFP; +} + +void __init at91_init_irq_default(void) +{ + at91_init_interrupts(at91_boot_soc.default_irq_priority); +} + +void __init at91_init_interrupts(unsigned int *priority) +{ + /* Initialize the AIC interrupt controller */ + at91_aic_init(priority); + + /* Enable GPIO interrupts */ + at91_gpio_irq_setup(); +} + +static struct map_desc sram_desc[2] __initdata; + +void __init at91_init_sram(int bank, unsigned long base, unsigned int length) +{ + struct map_desc *desc = &sram_desc[bank]; + + desc->virtual = AT91_IO_VIRT_BASE - length; + if (bank > 0) + desc->virtual -= sram_desc[bank - 1].length; + + desc->pfn = __phys_to_pfn(base); + desc->length = length; + desc->type = MT_DEVICE; + + pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n", + base, length, desc->virtual); + + iotable_init(desc, 1); +} + +static struct map_desc at91_io_desc __initdata = { + .virtual = AT91_VA_BASE_SYS, + .pfn = __phys_to_pfn(AT91_BASE_SYS), + .length = SZ_16K, + .type = MT_DEVICE, +}; + +void __iomem *at91_ioremap(unsigned long p, size_t size, unsigned int type) +{ + if (p >= AT91_BASE_SYS && p <= (AT91_BASE_SYS + SZ_16K - 1)) + return (void __iomem *)AT91_IO_P2V(p); + + return __arm_ioremap_caller(p, size, type, __builtin_return_address(0)); +} +EXPORT_SYMBOL(at91_ioremap); + +void at91_iounmap(volatile void __iomem *addr) +{ + unsigned long virt = (unsigned long)addr; + + if (virt >= VMALLOC_START && virt < VMALLOC_END) + __iounmap(addr); +} +EXPORT_SYMBOL(at91_iounmap); + +#define AT91_DBGU0 0xfffff200 +#define AT91_DBGU1 0xffffee00 + +static void soc_detect(u32 dbgu_base) +{ + u32 cidr, socid; + + cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR); + socid = cidr & ~AT91_CIDR_VERSION; + + switch (socid) { + case ARCH_ID_AT91CAP9: { +#ifdef CONFIG_AT91_PMC_UNIT + u32 pmc_ver = at91_sys_read(AT91_PMC_VER); + + if (pmc_ver == ARCH_REVISION_CAP9_B) + at91_soc_data.subtype = AT91_SOC_CAP9_REV_B; + else if (pmc_ver == ARCH_REVISION_CAP9_C) + at91_soc_data.subtype = AT91_SOC_CAP9_REV_C; +#endif + at91_soc_data.type = AT91_SOC_CAP9; + at91_boot_soc = at91cap9_soc; + break; + } + + case ARCH_ID_AT91RM9200: + at91_soc_data.type = AT91_SOC_RM9200; + at91_boot_soc = at91rm9200_soc; + break; + + case ARCH_ID_AT91SAM9260: + at91_soc_data.type = AT91_SOC_SAM9260; + at91_boot_soc = at91sam9260_soc; + break; + + case ARCH_ID_AT91SAM9261: + at91_soc_data.type = AT91_SOC_SAM9261; + at91_boot_soc = at91sam9261_soc; + break; + + case ARCH_ID_AT91SAM9263: + at91_soc_data.type = AT91_SOC_SAM9263; + at91_boot_soc = at91sam9263_soc; + break; + + case ARCH_ID_AT91SAM9G20: + at91_soc_data.type = AT91_SOC_SAM9G20; + at91_boot_soc = at91sam9260_soc; + break; + + case ARCH_ID_AT91SAM9G45: + at91_soc_data.type = AT91_SOC_SAM9G45; + if (cidr == ARCH_ID_AT91SAM9G45ES) + at91_soc_data.subtype = AT91_SOC_SAM9G45ES; + at91_boot_soc = at91sam9g45_soc; + break; + + case ARCH_ID_AT91SAM9RL64: + at91_soc_data.type = AT91_SOC_SAM9RL; + at91_boot_soc = at91sam9rl_soc; + break; + + case ARCH_ID_AT91SAM9X5: + at91_soc_data.type = AT91_SOC_SAM9X5; + at91_boot_soc = at91sam9x5_soc; + break; + } + + /* at91sam9g10 */ + if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { + at91_soc_data.type = AT91_SOC_SAM9G10; + at91_boot_soc = at91sam9261_soc; + } + /* at91sam9xe */ + else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { + at91_soc_data.type = AT91_SOC_SAM9260; + at91_soc_data.subtype = AT91_SOC_SAM9XE; + at91_boot_soc = at91sam9260_soc; + } + + if (!at91_soc_is_detected()) + return; + + at91_soc_data.cidr = cidr; + + /* sub version of soc */ + at91_soc_data.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID); + + if (at91_soc_data.type == AT91_SOC_SAM9G45) { + switch (at91_soc_data.exid) { + case ARCH_EXID_AT91SAM9M10: + at91_soc_data.subtype = AT91_SOC_SAM9M10; + break; + case ARCH_EXID_AT91SAM9G46: + at91_soc_data.subtype = AT91_SOC_SAM9G46; + break; + case ARCH_EXID_AT91SAM9M11: + at91_soc_data.subtype = AT91_SOC_SAM9M11; + break; + } + } + + if (at91_soc_data.type == AT91_SOC_SAM9X5) { + switch (at91_soc_data.exid) { + case ARCH_EXID_AT91SAM9G15: + at91_soc_data.subtype = AT91_SOC_SAM9G15; + break; + case ARCH_EXID_AT91SAM9G35: + at91_soc_data.subtype = AT91_SOC_SAM9G35; + break; + case ARCH_EXID_AT91SAM9X35: + at91_soc_data.subtype = AT91_SOC_SAM9X35; + break; + case ARCH_EXID_AT91SAM9G25: + at91_soc_data.subtype = AT91_SOC_SAM9G25; + break; + case ARCH_EXID_AT91SAM9X25: + at91_soc_data.subtype = AT91_SOC_SAM9X25; + break; + } + } +} + +static const char *soc_name[] = { + [AT91_SOC_RM9200] = "at91rm9200", + [AT91_SOC_CAP9] = "at91cap9", + [AT91_SOC_SAM9260] = "at91sam9260", + [AT91_SOC_SAM9261] = "at91sam9261", + [AT91_SOC_SAM9263] = "at91sam9263", + [AT91_SOC_SAM9G10] = "at91sam9g10", + [AT91_SOC_SAM9G20] = "at91sam9g20", + [AT91_SOC_SAM9G45] = "at91sam9g45", + [AT91_SOC_SAM9RL] = "at91sam9rl", + [AT91_SOC_SAM9X5] = "at91sam9x5", + [AT91_SOC_NONE] = "Unknown" +}; + +const char *at91_get_soc_type(struct at91_socinfo *c) +{ + return soc_name[c->type]; +} +EXPORT_SYMBOL(at91_get_soc_type); + +static const char *soc_subtype_name[] = { + [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA", + [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP", + [AT91_SOC_CAP9_REV_B] = "at91cap9 revB", + [AT91_SOC_CAP9_REV_C] = "at91cap9 revC", + [AT91_SOC_SAM9XE] = "at91sam9xe", + [AT91_SOC_SAM9G45ES] = "at91sam9g45es", + [AT91_SOC_SAM9M10] = "at91sam9m10", + [AT91_SOC_SAM9G46] = "at91sam9g46", + [AT91_SOC_SAM9M11] = "at91sam9m11", + [AT91_SOC_SAM9G15] = "at91sam9g15", + [AT91_SOC_SAM9G35] = "at91sam9g35", + [AT91_SOC_SAM9X35] = "at91sam9x35", + [AT91_SOC_SAM9G25] = "at91sam9g25", + [AT91_SOC_SAM9X25] = "at91sam9x25", + [AT91_SOC_SUBTYPE_NONE] = "Unknown" +}; + +const char *at91_get_soc_subtype(struct at91_socinfo *c) +{ + return soc_subtype_name[c->subtype]; +} +EXPORT_SYMBOL(at91_get_soc_subtype); + +void __init at91_map_io(void) +{ + /* Map peripherals */ + iotable_init(&at91_io_desc, 1); + + at91_soc_data.type = AT91_SOC_NONE; + at91_soc_data.subtype = AT91_SOC_SUBTYPE_NONE; + + soc_detect(AT91_DBGU0); + if (!at91_soc_is_detected()) + soc_detect(AT91_DBGU1); + + if (!at91_soc_is_detected()) + panic("AT91: Impossible to detect the SOC type"); + + pr_info("AT91: Detected soc type: %s\n", at91_get_soc_type(&at91_soc_data)); + pr_info("AT91: Detected soc subtype: %s\n", at91_get_soc_subtype(&at91_soc_data)); + + if (!at91_soc_is_enabled()) + panic("AT91: Soc not enabled"); + + if (at91_boot_soc.map_io) + at91_boot_soc.map_io(); +} + +void __init at91_initialize(unsigned long main_clock) +{ + /* Init clock subsystem */ + at91_clock_init(main_clock); + + /* Register the processor-specific clocks */ + at91_boot_soc.register_clocks(); + + at91_boot_soc.init(); +} diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h new file mode 100644 index 000000000000..4c365d12e899 --- /dev/null +++ b/arch/arm/mach-at91/soc.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +struct at91_soc { + unsigned int *default_irq_priority; + void (*map_io)(void); + void (*register_clocks)(void); + void (*init)(void); +}; + +extern struct at91_soc at91_boot_soc; +extern struct at91_soc at91cap9_soc; +extern struct at91_soc at91rm9200_soc; +extern struct at91_soc at91sam9260_soc; +extern struct at91_soc at91sam9261_soc; +extern struct at91_soc at91sam9263_soc; +extern struct at91_soc at91sam9g45_soc; +extern struct at91_soc at91sam9rl_soc; +extern struct at91_soc at91sam9x5_soc; + +static inline int at91_soc_is_enabled(void) +{ + return at91_boot_soc.init != NULL; +} + +#if !defined(CONFIG_ARCH_AT91CAP9) +#define at91cap9_soc at91_boot_soc +#endif + +#if !defined(CONFIG_ARCH_AT91RM9200) +#define at91rm9200_soc at91_boot_soc +#endif + +#if !(defined(CONFIG_ARCH_AT91SAM9260) && defined(CONFIG_ARCH_AT91SAM9G20)) +#define at91sam9260_soc at91_boot_soc +#endif + +#if !(defined(CONFIG_ARCH_AT91SAM9261) && defined(CONFIG_ARCH_AT91SAM9G10)) +#define at91sam9261_soc at91_boot_soc +#endif + +#if !defined(CONFIG_ARCH_AT91SAM9263) +#define at91sam9263_soc at91_boot_soc +#endif + +#if !defined(CONFIG_ARCH_AT91SAM9G45) +#define at91sam9g45_soc at91_boot_soc +#endif + +#if !defined(CONFIG_ARCH_AT91SAM9RL) +#define at91sam9rl_soc at91_boot_soc +#endif + +#if !defined(CONFIG_ARCH_AT91SAM9X5) +#define at91sam9x5_soc at91_boot_soc +#endif diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 4e66881c7aee..fc4e98ea7543 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -494,7 +494,7 @@ static struct platform_device da850_mcasp_device = { .resource = da850_mcasp_resources, }; -struct platform_device davinci_pcm_device = { +static struct platform_device davinci_pcm_device = { .name = "davinci-pcm-audio", .id = -1, }; diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 8f4f736aa267..806a2f02b980 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -298,7 +298,7 @@ static void davinci_init_wdt(void) /*-------------------------------------------------------------------------*/ -struct platform_device davinci_pcm_device = { +static struct platform_device davinci_pcm_device = { .name = "davinci-pcm-audio", .id = -1, }; diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index a0b838894ac9..e7221398e5af 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -252,9 +252,11 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct davinci_gpio_regs __iomem *g = irq2regs(irq); + struct davinci_gpio_regs __iomem *g; u32 mask = 0xffff; + g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc); + /* we only care about one bank */ if (irq & 1) mask <<= 16; @@ -422,8 +424,7 @@ static int __init davinci_gpio_irq_setup(void) /* set up all irqs in this bank */ irq_set_chained_handler(bank_irq, gpio_irq_handler); - irq_set_chip_data(bank_irq, (__force void *)g); - irq_set_handler_data(bank_irq, (void *)irq); + irq_set_handler_data(bank_irq, (__force void *)g); for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { irq_set_chip(irq, &gpio_irqchip); diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 871f9d508fde..937335a37722 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -23,28 +23,45 @@ #include <mach/map.h> #include <mach/regs-clock.h> +#include <mach/regs-audss.h> #include <mach/sysmmu.h> static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", - .id = -1, .rate = 27000000, }; static struct clk clk_sclk_hdmiphy = { .name = "sclk_hdmiphy", - .id = -1, }; static struct clk clk_sclk_usbphy0 = { .name = "sclk_usbphy0", - .id = -1, .rate = 27000000, }; static struct clk clk_sclk_usbphy1 = { .name = "sclk_usbphy1", - .id = -1, +}; + +static struct clk clk_sclk_xxti = { + .name = "sclk_usbphy1", +}; + +static struct clk clk_sclk_xusbxti = { + .name = "sclk_usbphy1", +}; + +static struct clk clk_audiocdclk0 = { + .name = "audiocdclk", +}; + +static struct clk clk_audiocdclk1 = { + .name = "audiocdclk", +}; + +static struct clk clk_audiocdclk2 = { + .name = "audiocdclk", }; static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) @@ -127,12 +144,21 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); } +static int exynos4_clksrc_mask_maudio_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_MAUDIO, clk, enable); +} + +static int exynos4_clk_audss_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_AUDSS, clk, enable); +} + /* Core list of CMU_CPU side */ static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", - .id = -1, }, .sources = &clk_src_apll, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, @@ -141,7 +167,6 @@ static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_sclk_apll = { .clk = { .name = "sclk_apll", - .id = -1, .parent = &clk_mout_apll.clk, }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, @@ -150,7 +175,6 @@ static struct clksrc_clk clk_sclk_apll = { static struct clksrc_clk clk_mout_epll = { .clk = { .name = "mout_epll", - .id = -1, }, .sources = &clk_src_epll, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, @@ -159,7 +183,6 @@ static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_mpll = { .clk = { .name = "mout_mpll", - .id = -1, }, .sources = &clk_src_mpll, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, @@ -178,7 +201,6 @@ static struct clksrc_sources clkset_moutcore = { static struct clksrc_clk clk_moutcore = { .clk = { .name = "moutcore", - .id = -1, }, .sources = &clkset_moutcore, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, @@ -187,7 +209,6 @@ static struct clksrc_clk clk_moutcore = { static struct clksrc_clk clk_coreclk = { .clk = { .name = "core_clk", - .id = -1, .parent = &clk_moutcore.clk, }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, @@ -196,7 +217,6 @@ static struct clksrc_clk clk_coreclk = { static struct clksrc_clk clk_armclk = { .clk = { .name = "armclk", - .id = -1, .parent = &clk_coreclk.clk, }, }; @@ -204,7 +224,6 @@ static struct clksrc_clk clk_armclk = { static struct clksrc_clk clk_aclk_corem0 = { .clk = { .name = "aclk_corem0", - .id = -1, .parent = &clk_coreclk.clk, }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, @@ -213,7 +232,6 @@ static struct clksrc_clk clk_aclk_corem0 = { static struct clksrc_clk clk_aclk_cores = { .clk = { .name = "aclk_cores", - .id = -1, .parent = &clk_coreclk.clk, }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, @@ -222,7 +240,6 @@ static struct clksrc_clk clk_aclk_cores = { static struct clksrc_clk clk_aclk_corem1 = { .clk = { .name = "aclk_corem1", - .id = -1, .parent = &clk_coreclk.clk, }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, @@ -231,7 +248,6 @@ static struct clksrc_clk clk_aclk_corem1 = { static struct clksrc_clk clk_periphclk = { .clk = { .name = "periphclk", - .id = -1, .parent = &clk_coreclk.clk, }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, @@ -252,7 +268,6 @@ static struct clksrc_sources clkset_mout_corebus = { static struct clksrc_clk clk_mout_corebus = { .clk = { .name = "mout_corebus", - .id = -1, }, .sources = &clkset_mout_corebus, .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, @@ -261,7 +276,6 @@ static struct clksrc_clk clk_mout_corebus = { static struct clksrc_clk clk_sclk_dmc = { .clk = { .name = "sclk_dmc", - .id = -1, .parent = &clk_mout_corebus.clk, }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, @@ -270,7 +284,6 @@ static struct clksrc_clk clk_sclk_dmc = { static struct clksrc_clk clk_aclk_cored = { .clk = { .name = "aclk_cored", - .id = -1, .parent = &clk_sclk_dmc.clk, }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, @@ -279,7 +292,6 @@ static struct clksrc_clk clk_aclk_cored = { static struct clksrc_clk clk_aclk_corep = { .clk = { .name = "aclk_corep", - .id = -1, .parent = &clk_aclk_cored.clk, }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, @@ -288,7 +300,6 @@ static struct clksrc_clk clk_aclk_corep = { static struct clksrc_clk clk_aclk_acp = { .clk = { .name = "aclk_acp", - .id = -1, .parent = &clk_mout_corebus.clk, }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, @@ -297,7 +308,6 @@ static struct clksrc_clk clk_aclk_acp = { static struct clksrc_clk clk_pclk_acp = { .clk = { .name = "pclk_acp", - .id = -1, .parent = &clk_aclk_acp.clk, }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, @@ -318,7 +328,6 @@ static struct clksrc_sources clkset_aclk = { static struct clksrc_clk clk_aclk_200 = { .clk = { .name = "aclk_200", - .id = -1, }, .sources = &clkset_aclk, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, @@ -328,7 +337,6 @@ static struct clksrc_clk clk_aclk_200 = { static struct clksrc_clk clk_aclk_100 = { .clk = { .name = "aclk_100", - .id = -1, }, .sources = &clkset_aclk, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, @@ -338,7 +346,6 @@ static struct clksrc_clk clk_aclk_100 = { static struct clksrc_clk clk_aclk_160 = { .clk = { .name = "aclk_160", - .id = -1, }, .sources = &clkset_aclk, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, @@ -348,7 +355,6 @@ static struct clksrc_clk clk_aclk_160 = { static struct clksrc_clk clk_aclk_133 = { .clk = { .name = "aclk_133", - .id = -1, }, .sources = &clkset_aclk, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, @@ -368,7 +374,6 @@ static struct clksrc_sources clkset_vpllsrc = { static struct clksrc_clk clk_vpllsrc = { .clk = { .name = "vpll_src", - .id = -1, .enable = exynos4_clksrc_mask_top_ctrl, .ctrlbit = (1 << 0), }, @@ -389,7 +394,6 @@ static struct clksrc_sources clkset_sclk_vpll = { static struct clksrc_clk clk_sclk_vpll = { .clk = { .name = "sclk_vpll", - .id = -1, }, .sources = &clkset_sclk_vpll, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, @@ -398,161 +402,151 @@ static struct clksrc_clk clk_sclk_vpll = { static struct clk init_clocks_off[] = { { .name = "timers", - .id = -1, .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1<<24), }, { .name = "csis", - .id = 0, + .devname = "s5p-mipi-csis.0", .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 4), }, { .name = "csis", - .id = 1, + .devname = "s5p-mipi-csis.1", .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 5), }, { .name = "fimc", - .id = 0, + .devname = "exynos4-fimc.0", .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 0), }, { .name = "fimc", - .id = 1, + .devname = "exynos4-fimc.1", .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 1), }, { .name = "fimc", - .id = 2, + .devname = "exynos4-fimc.2", .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 2), }, { .name = "fimc", - .id = 3, + .devname = "exynos4-fimc.3", .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 3), }, { .name = "fimd", - .id = 0, + .devname = "s5pv310-fb.0", .enable = exynos4_clk_ip_lcd0_ctrl, .ctrlbit = (1 << 0), }, { .name = "fimd", - .id = 1, + .devname = "s5pv310-fb.1", .enable = exynos4_clk_ip_lcd1_ctrl, .ctrlbit = (1 << 0), }, { .name = "sataphy", - .id = -1, .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 3), }, { .name = "hsmmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 5), }, { .name = "hsmmc", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 6), }, { .name = "hsmmc", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), }, { .name = "hsmmc", - .id = 3, + .devname = "s3c-sdhci.3", .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 8), }, { - .name = "hsmmc", - .id = 4, + .name = "dwmmc", .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 9), }, { .name = "sata", - .id = -1, .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 10), }, { .name = "pdma", - .id = 0, + .devname = "s3c-pl330.0", .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 0), }, { .name = "pdma", - .id = 1, + .devname = "s3c-pl330.1", .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 1), }, { .name = "adc", - .id = -1, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 15), }, { .name = "keypad", - .id = -1, .enable = exynos4_clk_ip_perir_ctrl, .ctrlbit = (1 << 16), }, { .name = "rtc", - .id = -1, .enable = exynos4_clk_ip_perir_ctrl, .ctrlbit = (1 << 15), }, { .name = "watchdog", - .id = -1, .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_perir_ctrl, .ctrlbit = (1 << 14), }, { .name = "usbhost", - .id = -1, .enable = exynos4_clk_ip_fsys_ctrl , .ctrlbit = (1 << 12), }, { .name = "otg", - .id = -1, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 13), }, { .name = "spi", - .id = 0, + .devname = "s3c64xx-spi.0", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 16), }, { .name = "spi", - .id = 1, + .devname = "s3c64xx-spi.1", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 17), }, { .name = "spi", - .id = 2, + .devname = "s3c64xx-spi.2", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 18), }, { .name = "iis", - .id = 0, + .devname = "samsung-i2s.0", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 19), }, { .name = "iis", - .id = 1, + .devname = "samsung-i2s.1", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 20), }, { .name = "iis", - .id = 2, + .devname = "samsung-i2s.2", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 21), }, { @@ -561,160 +555,247 @@ static struct clk init_clocks_off[] = { .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 27), }, { + .name = "pcm", + .devname = "samsung-pcm.0", + .enable = exynos4_clk_audss_ctrl, + .ctrlbit = S5P_AUDSS_CLKGATE_PCMSPECIAL, + }, { + .name = "pcm", + .devname = "samsung-pcm.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 22), + }, { + .name = "pcm", + .devname = "samsung-pcm.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 23), + }, { .name = "fimg2d", - .id = -1, .enable = exynos4_clk_ip_image_ctrl, .ctrlbit = (1 << 0), }, { .name = "i2c", - .id = 0, + .devname = "s3c2440-i2c.0", .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 6), }, { .name = "i2c", - .id = 1, + .devname = "s3c2440-i2c.1", .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 7), }, { .name = "i2c", - .id = 2, + .devname = "s3c2440-i2c.2", .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 8), }, { .name = "i2c", - .id = 3, + .devname = "s3c2440-i2c.3", .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 9), }, { .name = "i2c", - .id = 4, + .devname = "s3c2440-i2c.4", .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 10), }, { .name = "i2c", - .id = 5, + .devname = "s3c2440-i2c.5", .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 11), }, { .name = "i2c", - .id = 6, + .devname = "s3c2440-i2c.6", .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 12), }, { .name = "i2c", - .id = 7, + .devname = "s3c2440-i2c.7", .parent = &clk_aclk_100.clk, .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 13), }, { .name = "SYSMMU_MDMA", - .id = -1, .enable = exynos4_clk_ip_image_ctrl, .ctrlbit = (1 << 5), }, { .name = "SYSMMU_FIMC0", - .id = -1, .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 7), }, { .name = "SYSMMU_FIMC1", - .id = -1, .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 8), }, { .name = "SYSMMU_FIMC2", - .id = -1, .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 9), }, { .name = "SYSMMU_FIMC3", - .id = -1, .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 10), }, { .name = "SYSMMU_JPEG", - .id = -1, .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 11), }, { .name = "SYSMMU_FIMD0", - .id = -1, .enable = exynos4_clk_ip_lcd0_ctrl, .ctrlbit = (1 << 4), }, { .name = "SYSMMU_FIMD1", - .id = -1, .enable = exynos4_clk_ip_lcd1_ctrl, .ctrlbit = (1 << 4), }, { .name = "SYSMMU_PCIe", - .id = -1, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 18), }, { .name = "SYSMMU_G2D", - .id = -1, .enable = exynos4_clk_ip_image_ctrl, .ctrlbit = (1 << 3), }, { .name = "SYSMMU_ROTATOR", - .id = -1, .enable = exynos4_clk_ip_image_ctrl, .ctrlbit = (1 << 4), }, { .name = "SYSMMU_TV", - .id = -1, .enable = exynos4_clk_ip_tv_ctrl, .ctrlbit = (1 << 4), }, { .name = "SYSMMU_MFC_L", - .id = -1, .enable = exynos4_clk_ip_mfc_ctrl, .ctrlbit = (1 << 1), }, { .name = "SYSMMU_MFC_R", - .id = -1, .enable = exynos4_clk_ip_mfc_ctrl, .ctrlbit = (1 << 2), } }; +static struct clk *clkset_sclk_audio0_list[] = { + [0] = &clk_audiocdclk0, + [1] = NULL, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_xxti, + [5] = &clk_sclk_xusbxti, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_sclk_audio0 = { + .sources = clkset_sclk_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), +}; + +static struct clksrc_clk clk_sclk_audio0 = { + .clk = { + .name = "audio-bus", + .devname = "samsung-pcm.0", + .enable = exynos4_clksrc_mask_maudio_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_sclk_audio0, + .reg_src = { .reg = S5P_CLKSRC_MAUDIO, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_MAUDIO, .shift = 0, .size = 4 }, +}; + +static struct clk *clkset_sclk_audio1_list[] = { + [0] = &clk_audiocdclk1, + [1] = NULL, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_xxti, + [5] = &clk_sclk_xusbxti, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_sclk_audio1 = { + .sources = clkset_sclk_audio1_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list), +}; + +static struct clksrc_clk clk_sclk_audio1 = { + .clk = { + .name = "audio-bus", + .devname = "samsung-pcm.1", + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_sclk_audio1, + .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL4, .shift = 4, .size = 8 }, +}; + +static struct clk *clkset_sclk_audio2_list[] = { + [0] = &clk_audiocdclk2, + [1] = NULL, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_xxti, + [5] = &clk_sclk_xusbxti, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_sclk_audio2 = { + .sources = clkset_sclk_audio2_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list), +}; + +static struct clksrc_clk clk_sclk_audio2 = { + .clk = { + .name = "audio-bus", + .devname = "samsung-pcm.2", + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_sclk_audio2, + .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL4, .shift = 16, .size = 4 }, +}; + static struct clk init_clocks[] = { { .name = "uart", - .id = 0, + .devname = "s5pv210-uart.0", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 0), }, { .name = "uart", - .id = 1, + .devname = "s5pv210-uart.1", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 1), }, { .name = "uart", - .id = 2, + .devname = "s5pv210-uart.2", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 2), }, { .name = "uart", - .id = 3, + .devname = "s5pv210-uart.3", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 3), }, { .name = "uart", - .id = 4, + .devname = "s5pv210-uart.4", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 4), }, { .name = "uart", - .id = 5, + .devname = "s5pv210-uart.5", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 5), } @@ -750,7 +831,6 @@ static struct clksrc_sources clkset_mout_g2d0 = { static struct clksrc_clk clk_mout_g2d0 = { .clk = { .name = "mout_g2d0", - .id = -1, }, .sources = &clkset_mout_g2d0, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, @@ -769,7 +849,6 @@ static struct clksrc_sources clkset_mout_g2d1 = { static struct clksrc_clk clk_mout_g2d1 = { .clk = { .name = "mout_g2d1", - .id = -1, }, .sources = &clkset_mout_g2d1, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, @@ -788,7 +867,6 @@ static struct clksrc_sources clkset_mout_g2d = { static struct clksrc_clk clk_dout_mmc0 = { .clk = { .name = "dout_mmc0", - .id = -1, }, .sources = &clkset_group, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, @@ -798,7 +876,6 @@ static struct clksrc_clk clk_dout_mmc0 = { static struct clksrc_clk clk_dout_mmc1 = { .clk = { .name = "dout_mmc1", - .id = -1, }, .sources = &clkset_group, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, @@ -808,7 +885,6 @@ static struct clksrc_clk clk_dout_mmc1 = { static struct clksrc_clk clk_dout_mmc2 = { .clk = { .name = "dout_mmc2", - .id = -1, }, .sources = &clkset_group, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, @@ -818,7 +894,6 @@ static struct clksrc_clk clk_dout_mmc2 = { static struct clksrc_clk clk_dout_mmc3 = { .clk = { .name = "dout_mmc3", - .id = -1, }, .sources = &clkset_group, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, @@ -828,7 +903,6 @@ static struct clksrc_clk clk_dout_mmc3 = { static struct clksrc_clk clk_dout_mmc4 = { .clk = { .name = "dout_mmc4", - .id = -1, }, .sources = &clkset_group, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, @@ -839,7 +913,7 @@ static struct clksrc_clk clksrcs[] = { { .clk = { .name = "uclk1", - .id = 0, + .devname = "s5pv210-uart.0", .enable = exynos4_clksrc_mask_peril0_ctrl, .ctrlbit = (1 << 0), }, @@ -849,7 +923,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 1, + .devname = "s5pv210-uart.1", .enable = exynos4_clksrc_mask_peril0_ctrl, .ctrlbit = (1 << 4), }, @@ -859,7 +933,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 2, + .devname = "s5pv210-uart.2", .enable = exynos4_clksrc_mask_peril0_ctrl, .ctrlbit = (1 << 8), }, @@ -869,7 +943,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 3, + .devname = "s5pv210-uart.3", .enable = exynos4_clksrc_mask_peril0_ctrl, .ctrlbit = (1 << 12), }, @@ -879,7 +953,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_pwm", - .id = -1, .enable = exynos4_clksrc_mask_peril0_ctrl, .ctrlbit = (1 << 24), }, @@ -889,7 +962,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_csis", - .id = 0, + .devname = "s5p-mipi-csis.0", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 24), }, @@ -899,7 +972,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_csis", - .id = 1, + .devname = "s5p-mipi-csis.1", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 28), }, @@ -909,7 +982,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_cam", - .id = 0, + .devname = "exynos4-fimc.0", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 16), }, @@ -919,7 +992,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_cam", - .id = 1, + .devname = "exynos4-fimc.1", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 20), }, @@ -929,7 +1002,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 0, + .devname = "exynos4-fimc.0", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 0), }, @@ -939,7 +1012,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 1, + .devname = "exynos4-fimc.1", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 4), }, @@ -949,7 +1022,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 2, + .devname = "exynos4-fimc.2", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 8), }, @@ -959,7 +1032,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 3, + .devname = "exynos4-fimc.3", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 12), }, @@ -969,7 +1042,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimd", - .id = 0, + .devname = "s5pv310-fb.0", .enable = exynos4_clksrc_mask_lcd0_ctrl, .ctrlbit = (1 << 0), }, @@ -979,7 +1052,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimd", - .id = 1, + .devname = "s5pv310-fb.1", .enable = exynos4_clksrc_mask_lcd1_ctrl, .ctrlbit = (1 << 0), }, @@ -989,7 +1062,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_sata", - .id = -1, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 24), }, @@ -999,7 +1071,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 0, + .devname = "s3c64xx-spi.0", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 16), }, @@ -1009,7 +1081,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 1, + .devname = "s3c64xx-spi.1", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 20), }, @@ -1019,7 +1091,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 2, + .devname = "s3c64xx-spi.2", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 24), }, @@ -1029,7 +1101,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimg2d", - .id = -1, }, .sources = &clkset_mout_g2d, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, @@ -1037,7 +1108,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_dout_mmc0.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -1046,7 +1117,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_dout_mmc1.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -1055,7 +1126,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_dout_mmc2.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1064,7 +1135,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 3, + .devname = "s3c-sdhci.3", .parent = &clk_dout_mmc3.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -1072,14 +1143,34 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }, { .clk = { - .name = "sclk_mmc", - .id = 4, + .name = "sclk_dwmmc", .parent = &clk_dout_mmc4.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 16), }, .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, - } + }, { + .clk = { + .name = "sclk_pcm", + .devname = "samsung-pcm.0", + .parent = &clk_sclk_audio0.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_MAUDIO, .shift = 4, .size = 8 }, + }, { + .clk = { + .name = "sclk_pcm", + .devname = "samsung-pcm.1", + .parent = &clk_sclk_audio1.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_PERIL4, .shift = 4, .size = 8 }, + }, { + .clk = { + .name = "sclk_pcm", + .devname = "samsung-pcm.2", + .parent = &clk_sclk_audio2.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_PERIL4, .shift = 20, .size = 8 }, + }, }; /* Clock initialization code */ @@ -1112,6 +1203,9 @@ static struct clksrc_clk *sysclks[] = { &clk_dout_mmc2, &clk_dout_mmc3, &clk_dout_mmc4, + &clk_sclk_audio0, + &clk_sclk_audio1, + &clk_sclk_audio2, }; static int xtal_rate; @@ -1191,10 +1285,13 @@ void __init_or_cpufreq exynos4_setup_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); + + clk_audiocdclk0.rate = PCM_EXTCLK0; + clk_set_parent(&clk_sclk_audio0.clk, &clk_audiocdclk0); } static struct clk *clks[] __initdata = { - /* Nothing here yet */ + &clk_audiocdclk0, }; void __init exynos4_register_clocks(void) diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 9babe4473e88..1196f3958d8d 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -102,7 +102,12 @@ static struct map_desc exynos4_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), .length = SZ_4K, .type = MT_DEVICE, - } + }, { + .virtual = (unsigned long)S5P_VA_AUDSS, + .pfn = __phys_to_pfn(EXYNOS4_PA_AUDSS), + .length = SZ_1K, + .type = MT_DEVICE, + }, }; static void exynos4_idle(void) diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c index 1eed5f9f7bd3..63475947432b 100644 --- a/arch/arm/mach-exynos4/dev-audio.c +++ b/arch/arm/mach-exynos4/dev-audio.c @@ -187,6 +187,11 @@ static int exynos4_pcm_cfg_gpio(struct platform_device *pdev) static struct s3c_audio_pdata s3c_pcm_pdata = { .cfg_gpio = exynos4_pcm_cfg_gpio, + .type = { + .pcm = { + .quirks = QUIRK_NO_DIV, + }, + }, }; static struct resource exynos4_pcm0_resource[] = { diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do {} while (0) + +#endif diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h index 0009e77a05fc..57d807433928 100644 --- a/arch/arm/mach-exynos4/include/mach/map.h +++ b/arch/arm/mach-exynos4/include/mach/map.h @@ -30,6 +30,8 @@ #define EXYNOS4_PA_FIMC2 0x11820000 #define EXYNOS4_PA_FIMC3 0x11830000 +#define EXYNOS4_PA_AUDSS 0x03810000 + #define EXYNOS4_PA_I2S0 0x03830000 #define EXYNOS4_PA_I2S1 0xE3100000 #define EXYNOS4_PA_I2S2 0xE2A00000 @@ -147,6 +149,7 @@ #define S5P_PA_SYSCON EXYNOS4_PA_SYSCON #define S5P_PA_TIMER EXYNOS4_PA_TIMER #define S5P_PA_EHCI EXYNOS4_PA_EHCI +#define S5P_PA_AUDSS EXYNOS4_PA_AUDSS #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h index f26e46bc06ca..1df3b81f96e8 100644 --- a/arch/arm/mach-exynos4/include/mach/pm-core.h +++ b/arch/arm/mach-exynos4/include/mach/pm-core.h @@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, { /* nothing here yet */ } + +static inline void s3c_pm_restored_gpios(void) +{ + /* nothing here yet */ +} + +static inline void s3c_pm_saved_gpios(void) +{ + /* nothing here yet */ +} diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos4/include/mach/regs-audss.h new file mode 100644 index 000000000000..3a797b81fa58 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/regs-audss.h @@ -0,0 +1,25 @@ +/* arch/arm/mach-exynos4/include/mach/regs-audss.h + * + * Copyright (c) 2011 Samsung Electronics + * http://www.samsung.com + * + * Exynos4 Audio SubSystem clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_AUDSS_H +#define __PLAT_REGS_AUDSS_H __FILE__ + +#define S5P_AUDSSREG(x) (S5P_VA_AUDSS + (x)) + +#define S5P_CLKGATE_AUDSS S5P_AUDSSREG(0x8) + +#define PCM_EXTCLK0 16934400 + +/* IP Clock Gate 0 Registers */ +#define S5P_AUDSS_CLKGATE_PCMSPECIAL (1<<5) + +#endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/mach-exynos4/init.c b/arch/arm/mach-exynos4/init.c index cf91f50e43ab..a8a83e3881a4 100644 --- a/arch/arm/mach-exynos4/init.c +++ b/arch/arm/mach-exynos4/init.c @@ -35,6 +35,7 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) tcfg->clocks = exynos4_serial_clocks; tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks); } + tcfg->flags |= NO_NEED_CHECK_CLKSRC; } s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c index e645f7a955f0..ac53e4998e9c 100644 --- a/arch/arm/mach-exynos4/mach-smdkc210.c +++ b/arch/arm/mach-exynos4/mach-smdkc210.c @@ -142,6 +142,11 @@ static struct platform_device smdkc210_smsc911x = { }, }; +static struct platform_device smdkc210_pcm_device = { + .name = "samsung-smdk-pcm", + .id = -1, +}; + static struct i2c_board_info i2c_devs1[] __initdata = { {I2C_BOARD_INFO("wm8994", 0x1a),}, }; @@ -156,6 +161,7 @@ static struct platform_device *smdkc210_devices[] __initdata = { &s3c_device_wdt, &exynos4_device_ac97, &exynos4_device_i2s0, + &exynos4_device_pcm0, &exynos4_device_pd[PD_MFC], &exynos4_device_pd[PD_G3D], &exynos4_device_pd[PD_LCD0], @@ -166,6 +172,7 @@ static struct platform_device *smdkc210_devices[] __initdata = { &exynos4_device_sysmmu, &samsung_asoc_dma, &smdkc210_smsc911x, + &smdkc210_pcm_device, }; static void __init smdkc210_smsc911x_init(void) diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c index 152676471b67..7e3ee6c80da3 100644 --- a/arch/arm/mach-exynos4/mach-smdkv310.c +++ b/arch/arm/mach-exynos4/mach-smdkv310.c @@ -163,6 +163,11 @@ static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = { .cols = 8, }; +static struct platform_device smdkv310_pcm_device = { + .name = "samsung-smdk-pcm", + .id = -1, +}; + static struct i2c_board_info i2c_devs1[] __initdata = { {I2C_BOARD_INFO("wm8994", 0x1a),}, }; @@ -186,8 +191,10 @@ static struct platform_device *smdkv310_devices[] __initdata = { &exynos4_device_pd[PD_TV], &exynos4_device_pd[PD_GPS], &exynos4_device_sysmmu, + &exynos4_device_pcm0, &samsung_asoc_dma, &smdkv310_smsc911x, + &smdkv310_pcm_device, }; static void __init smdkv310_smsc911x_init(void) diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S index 6b62425417a6..b56a4914985c 100644 --- a/arch/arm/mach-exynos4/sleep.S +++ b/arch/arm/mach-exynos4/sleep.S @@ -40,18 +40,14 @@ */ ENTRY(s3c_cpu_save) + adr r3, BSYM(exynos4_finish_suspend) + b cpu_suspend - stmfd sp!, { r3 - r12, lr } - ldr r3, =resume_with_mmu - bl cpu_suspend - +exynos4_finish_suspend: ldr r0, =pm_cpu_sleep ldr r0, [ r0 ] mov pc, r0 -resume_with_mmu: - ldmfd sp!, { r3 - r12, pc } - .ltorg /* diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c index ebb8f38d5405..9a742944fc9c 100644 --- a/arch/arm/mach-exynos4/time.c +++ b/arch/arm/mach-exynos4/time.c @@ -264,6 +264,7 @@ static void __init exynos4_timer_resources(void) clk_enable(timerclk); tmpdev.id = 2; + tmpdev.dev.init_name = "s3c24xx-pwm.2"; tin2 = clk_get(&tmpdev.dev, "pwm-tin"); if (IS_ERR(tin2)) panic("failed to get pwm-tin2 clock for system timer"); @@ -274,6 +275,7 @@ static void __init exynos4_timer_resources(void) clk_enable(tin2); tmpdev.id = 4; + tmpdev.dev.init_name = "s3c24xx-pwm.4"; tin4 = clk_get(&tmpdev.dev, "pwm-tin"); if (IS_ERR(tin4)) panic("failed to get pwm-tin4 clock for system timer"); diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index 5f1f9867fc70..121ad1d4fa39 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -103,6 +103,7 @@ static void __init footbridge_timer_init(void) clockevents_calc_mult_shift(ce, mem_fclk_21285, 5); ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce); ce->min_delta_ns = clockevent_delta2ns(0x000004, ce); + ce->cpumask = cpumask_of(smp_processor_id()); clockevents_register_device(ce); } diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S index 30b971d65815..1be2eeb7a0a0 100644 --- a/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S @@ -26,6 +26,7 @@ #include <asm/hardware/debug-8250.S> #else +#include <mach/hardware.h> /* For EBSA285 debugging */ .equ dc21285_high, ARMCSR_BASE & 0xff000000 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff @@ -36,8 +37,8 @@ .else mov \rp, #0 .endif - orr \rv, \rp, #0x42000000 - orr \rp, \rp, #dc21285_high + orr \rv, \rp, #dc21285_high + orr \rp, \rp, #0x42000000 .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 59c97a331136..e8dd22fa7d61 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -167,6 +167,7 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD bool "Eukrea MBIMXSD development board" select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX_SSI + select LEDS_GPIO_REGISTER help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. @@ -265,6 +266,7 @@ config MACH_EUKREA_MBIMX27_BASEBOARD select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX + select LEDS_GPIO_REGISTER help This adds board specific devices that can be found on Eukrea's MBIMX27 evaluation board. @@ -403,6 +405,7 @@ config MACH_MX31LITE select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_MXC_RTC select IMX_HAVE_PLATFORM_SPI_IMX + select LEDS_GPIO_REGISTER help Include support for MX31 LITEKIT platform. This includes specific configurations for the board and its peripherals. @@ -471,6 +474,7 @@ config MACH_MX31MOBOARD select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX + select LEDS_GPIO_REGISTER select MXC_ULPI if USB_ULPI help Include support for mx31moboard platform. This includes specific @@ -577,6 +581,7 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IPU_CORE + select LEDS_GPIO_REGISTER help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c index 236f1495efad..4d76f67f270f 100644 --- a/arch/arm/mach-imx/dma-v1.c +++ b/arch/arm/mach-imx/dma-v1.c @@ -475,7 +475,6 @@ void imx_dma_enable(int channel) imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); -#ifdef CONFIG_ARCH_MX2 if ((cpu_is_mx21() || cpu_is_mx27()) && imxdma->sg && imx_dma_hw_chain(imxdma)) { imxdma->sg = sg_next(imxdma->sg); @@ -487,7 +486,6 @@ void imx_dma_enable(int channel) DMA_CCR(channel)); } } -#endif imxdma->in_use = 1; local_irq_restore(flags); @@ -518,7 +516,6 @@ void imx_dma_disable(int channel) } EXPORT_SYMBOL(imx_dma_disable); -#ifdef CONFIG_ARCH_MX2 static void imx_dma_watchdog(unsigned long chno) { struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; @@ -530,7 +527,6 @@ static void imx_dma_watchdog(unsigned long chno) if (imxdma->err_handler) imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT); } -#endif static irqreturn_t dma_err_handler(int irq, void *dev_id) { @@ -654,10 +650,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) { int i, disr; -#ifdef CONFIG_ARCH_MX2 if (cpu_is_mx21() || cpu_is_mx27()) dma_err_handler(irq, dev_id); -#endif disr = imx_dmav1_readl(DMA_DISR); @@ -703,7 +697,6 @@ int imx_dma_request(int channel, const char *name) imxdma->name = name; local_irq_restore(flags); /* request_irq() can block */ -#ifdef CONFIG_ARCH_MX2 if (cpu_is_mx21() || cpu_is_mx27()) { ret = request_irq(MX2x_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA", NULL); @@ -717,7 +710,6 @@ int imx_dma_request(int channel, const char *name) imxdma->watchdog.function = &imx_dma_watchdog; imxdma->watchdog.data = channel; } -#endif return ret; } @@ -744,10 +736,8 @@ void imx_dma_free(int channel) imx_dma_disable(channel); imxdma->name = NULL; -#ifdef CONFIG_ARCH_MX2 if (cpu_is_mx21() || cpu_is_mx27()) free_irq(MX2x_INT_DMACH0 + channel, NULL); -#endif local_irq_restore(flags); } @@ -803,21 +793,13 @@ static int __init imx_dma_init(void) int ret = 0; int i; -#ifdef CONFIG_ARCH_MX1 if (cpu_is_mx1()) imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); - else -#endif -#ifdef CONFIG_MACH_MX21 - if (cpu_is_mx21()) + else if (cpu_is_mx21()) imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); - else -#endif -#ifdef CONFIG_MACH_MX27 - if (cpu_is_mx27()) + else if (cpu_is_mx27()) imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); else -#endif return 0; dma_clk = clk_get(NULL, "dma"); @@ -828,7 +810,6 @@ static int __init imx_dma_init(void) /* reset DMA module */ imx_dmav1_writel(DCR_DRST, DMA_DCR); -#ifdef CONFIG_ARCH_MX1 if (cpu_is_mx1()) { ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL); if (ret) { @@ -843,7 +824,7 @@ static int __init imx_dma_init(void) return ret; } } -#endif + /* enable DMA module */ imx_dmav1_writel(DCR_DEN, DMA_DCR); diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 5911281da5f5..5db3e1463af7 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -112,7 +112,7 @@ eukrea_mbimx27_keymap_data __initconst = { .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), }; -static struct gpio_led gpio_leds[] = { +static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = { { .name = "led1", .default_trigger = "heartbeat", @@ -127,17 +127,10 @@ static struct gpio_led gpio_leds[] = { }, }; -static struct gpio_led_platform_data gpio_led_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &gpio_led_info, - }, +static const struct gpio_led_platform_data + eukrea_mbimx27_gpio_led_info __initconst = { + .leds = eukrea_mbimx27_gpio_leds, + .num_leds = ARRAY_SIZE(eukrea_mbimx27_gpio_leds), }; static struct imx_fb_videomode eukrea_mbimx27_modes[] = { @@ -293,10 +286,6 @@ static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = { }, }; -static struct platform_device *platform_devices[] __initdata = { - &leds_gpio, -}; - static const struct imxmmc_platform_data sdhc_pdata __initconst = { .dat3_card_detect = 1, }; @@ -377,5 +366,5 @@ void __init eukrea_mbimx27_baseboard_init(void) imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info); } diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index f9ef04acdab1..01ebcb31e482 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c @@ -173,7 +173,7 @@ static struct platform_device eukrea_mbimxsd_lcd_powerdev = { .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, }; -static struct gpio_led eukrea_mbimxsd_leds[] = { +static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = { { .name = "led1", .default_trigger = "heartbeat", @@ -182,19 +182,12 @@ static struct gpio_led eukrea_mbimxsd_leds[] = { }, }; -static struct gpio_led_platform_data eukrea_mbimxsd_led_info = { +static const struct gpio_led_platform_data + eukrea_mbimxsd_led_info __initconst = { .leds = eukrea_mbimxsd_leds, .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), }; -static struct platform_device eukrea_mbimxsd_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &eukrea_mbimxsd_led_info, - }, -}; - static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { { .gpio = GPIO_SWITCH1, @@ -212,7 +205,6 @@ static const struct gpio_keys_platform_data }; static struct platform_device *platform_devices[] __initdata = { - &eukrea_mbimxsd_leds_gpio, &eukrea_mbimxsd_lcd_powerdev, }; @@ -287,5 +279,6 @@ void __init eukrea_mbimxsd25_baseboard_init(void) ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); imx_add_gpio_keys(&eukrea_mbimxsd_button_data); } diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c index 4909ea05855a..558eb526ba56 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c @@ -193,19 +193,12 @@ static struct gpio_led eukrea_mbimxsd_leds[] = { }, }; -static struct gpio_led_platform_data eukrea_mbimxsd_led_info = { +static const struct gpio_led_platform_data + eukrea_mbimxsd_led_info __initconst = { .leds = eukrea_mbimxsd_leds, .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), }; -static struct platform_device eukrea_mbimxsd_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &eukrea_mbimxsd_led_info, - }, -}; - static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { { .gpio = GPIO_SWITCH1, @@ -223,7 +216,6 @@ static const struct gpio_keys_platform_data }; static struct platform_device *platform_devices[] __initdata = { - &eukrea_mbimxsd_leds_gpio, &eukrea_mbimxsd_lcd_powerdev, }; @@ -299,5 +291,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void) ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); imx_add_gpio_keys(&eukrea_mbimxsd_button_data); } diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c index 15e45c84e371..a404c89485ca 100644 --- a/arch/arm/mach-imx/mach-apf9328.c +++ b/arch/arm/mach-imx/mach-apf9328.c @@ -99,11 +99,6 @@ static struct platform_device dm9000x_device = { } }; -/* --- SERIAL RESSOURCE --- */ -static const struct imxuart_platform_data uart0_pdata __initconst = { - .flags = 0, -}; - static const struct imxuart_platform_data uart1_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -115,11 +110,13 @@ static struct platform_device *devices[] __initdata = { static void __init apf9328_init(void) { + imx1_soc_init(); + mxc_gpio_setup_multiple_pins(apf9328_pins, ARRAY_SIZE(apf9328_pins), "APF9328"); - imx1_add_imx_uart0(&uart0_pdata); + imx1_add_imx_uart0(NULL); imx1_add_imx_uart1(&uart1_pdata); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index ffb40ff619b1..ede2710f8b76 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c @@ -490,6 +490,8 @@ static struct platform_device *devices[] __initdata = { */ static void __init armadillo5x0_init(void) { + imx31_soc_init(); + mxc_iomux_setup_multiple_pins(armadillo5x0_pins, ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c index 42e4f078a19c..f49470553bdf 100644 --- a/arch/arm/mach-imx/mach-bug.c +++ b/arch/arm/mach-imx/mach-bug.c @@ -42,6 +42,8 @@ static const unsigned int bug_pins[] __initconst = { static void __init bug_board_init(void) { + imx31_soc_init(); + mxc_iomux_setup_multiple_pins(bug_pins, ARRAY_SIZE(bug_pins), "uart-4"); imx31_add_imx_uart4(&uart_pdata); diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 46a2e41d43d2..87887ac5806b 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -250,6 +250,8 @@ __setup("otg_mode=", eukrea_cpuimx27_otg_mode); static void __init eukrea_cpuimx27_init(void) { + imx27_soc_init(); + mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins, ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27"); diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 3f8ef825fa6f..f39a478ba1a6 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c @@ -156,6 +156,8 @@ __setup("otg_mode=", eukrea_cpuimx35_otg_mode); */ static void __init eukrea_cpuimx35_init(void) { + imx35_soc_init(); + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, ARRAY_SIZE(eukrea_cpuimx35_pads)); diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index 148cff2819b9..da36da52969d 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c @@ -125,6 +125,8 @@ __setup("otg_mode=", eukrea_cpuimx25_otg_mode); static void __init eukrea_cpuimx25_init(void) { + imx25_soc_init(); + if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, ARRAY_SIZE(eukrea_cpuimx25_pads))) printk(KERN_ERR "error setting cpuimx25 pads !\n"); diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 7ae43b1ec517..6707de0ab716 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -34,7 +34,7 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/common.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include "devices-imx27.h" @@ -231,6 +231,8 @@ static void __init visstrim_m10_board_init(void) { int ret; + imx27_soc_init(); + ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins, ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10"); if (ret) diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c index 9be6cd6fbf8c..272f793e9247 100644 --- a/arch/arm/mach-imx/mach-imx27ipcam.c +++ b/arch/arm/mach-imx/mach-imx27ipcam.c @@ -50,6 +50,8 @@ static const int mx27ipcam_pins[] __initconst = { static void __init mx27ipcam_init(void) { + imx27_soc_init(); + mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins), "mx27ipcam"); diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index 841140516ede..d81a769fe895 100644 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c @@ -59,6 +59,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = { static void __init mx27lite_init(void) { + imx27_soc_init(); + mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), "imx27lite"); imx27_add_imx_uart0(&uart_pdata); diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c index 1ecae20cf4e3..e472a1d88058 100644 --- a/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c @@ -223,6 +223,8 @@ static int kzm_pins[] __initdata = { */ static void __init kzm_board_init(void) { + imx31_soc_init(); + mxc_iomux_setup_multiple_pins(kzm_pins, ARRAY_SIZE(kzm_pins), "kzm"); kzm_init_ext_uart(); diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 38ec5cbbda9b..5cd8bee46960 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -115,6 +115,8 @@ static struct i2c_board_info mx1ads_i2c_devices[] = { */ static void __init mx1ads_init(void) { + imx1_soc_init(); + mxc_gpio_setup_multiple_pins(mx1ads_pins, ARRAY_SIZE(mx1ads_pins), "mx1ads"); diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 74ac88978ddd..d389ecf9b5a8 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -279,6 +279,8 @@ static struct platform_device *platform_devices[] __initdata = { static void __init mx21ads_board_init(void) { + imx21_soc_init(); + mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), "mx21ads"); diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index 58ea3fdf0911..01534bb61305 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -219,6 +219,8 @@ static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = { static void __init mx25pdk_init(void) { + imx25_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, ARRAY_SIZE(mx25pdk_pads)); diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 6e1accf93f81..09ec03653b2c 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -45,7 +45,7 @@ #define SD1_EN_GPIO (GPIO_PORTB + 25) #define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23) #define SPI2_SS0 (GPIO_PORTD + 21) -#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTC + 28) +#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28)) static const int mx27pdk_pins[] __initconst = { /* UART1 */ @@ -267,6 +267,8 @@ static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { static void __init mx27pdk_init(void) { + imx27_soc_init(); + mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), "mx27pdk"); mx27_3ds_sdhc1_enable_level_translator(); diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 1db79506f5e4..fc26ed71b9ed 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -288,6 +288,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = { static void __init mx27ads_board_init(void) { + imx27_soc_init(); + mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), "mx27ads"); diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 9b982449cb52..ab2a6268b50b 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -689,6 +689,8 @@ static void __init mx31_3ds_init(void) { int ret; + imx31_soc_init(); + mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds"); diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c index f4dee0254634..0ce49478a479 100644 --- a/arch/arm/mach-imx/mach-mx31ads.c +++ b/arch/arm/mach-imx/mach-mx31ads.c @@ -516,6 +516,8 @@ static void __init mx31ads_init_irq(void) static void __init mx31ads_init(void) { + imx31_soc_init(); + mxc_init_extuart(); mxc_init_imx_uart(); mxc_init_i2c(); diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c index 410e676ae087..750368ddf0f9 100644 --- a/arch/arm/mach-imx/mach-mx31lilly.c +++ b/arch/arm/mach-imx/mach-mx31lilly.c @@ -243,6 +243,8 @@ core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444); static void __init mx31lilly_board_init(void) { + imx31_soc_init(); + switch (mx31lilly_baseboard) { case MX31LILLY_NOBOARD: break; diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index ac9b4cad320e..4b47fd9fdd89 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c @@ -230,6 +230,8 @@ static void __init mx31lite_init(void) { int ret; + imx31_soc_init(); + switch (mx31lite_baseboard) { case MX31LITE_NOBOARD: break; diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index eaa51e49ca95..b358383120e7 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c @@ -425,7 +425,7 @@ static int __init moboard_usbh2_init(void) return 0; } -static struct gpio_led mx31moboard_leds[] = { +static const struct gpio_led mx31moboard_leds[] __initconst = { { .name = "coreboard-led-0:red:running", .default_trigger = "heartbeat", @@ -442,26 +442,17 @@ static struct gpio_led mx31moboard_leds[] = { }, }; -static struct gpio_led_platform_data mx31moboard_led_pdata = { +static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = { .num_leds = ARRAY_SIZE(mx31moboard_leds), .leds = mx31moboard_leds, }; -static struct platform_device mx31moboard_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &mx31moboard_led_pdata, - }, -}; - static const struct ipu_platform_data mx3_ipu_data __initconst = { .irq_base = MXC_IPU_IRQ_START, }; static struct platform_device *devices[] __initdata = { &mx31moboard_flash, - &mx31moboard_leds_device, }; static struct mx3_camera_pdata camera_pdata __initdata = { @@ -507,10 +498,13 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); */ static void __init mx31moboard_init(void) { + imx31_soc_init(); + mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), "moboard"); platform_add_devices(devices, ARRAY_SIZE(devices)); + gpio_led_register_device(-1, &mx31moboard_led_pdata); imx31_add_imx_uart0(&uart0_pdata); imx31_add_imx_uart4(&uart4_pdata); diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index 882880ac1bbc..b3b9bd8ac2a3 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c @@ -43,7 +43,7 @@ #include "devices-imx35.h" -#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1) +#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1)) static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, @@ -179,6 +179,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = { */ static void __init mx35_3ds_init(void) { + imx35_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); imx35_add_fec(NULL); diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index 2774541511e7..c85876fed663 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -233,6 +233,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = { static void __init mxt_td60_board_init(void) { + imx27_soc_init(); + mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins), "MXT_TD60"); diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index bbddc5a11c43..71083aa16038 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -357,6 +357,8 @@ static void __init pca100_init(void) { int ret; + imx27_soc_init(); + /* SSI unit */ mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0, MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */ diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 89c213b81295..f45b7cd72c8a 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -576,6 +576,8 @@ static void __init pcm037_init(void) { int ret; + imx31_soc_init(); + mxc_iomux_set_gpr(MUX_PGP_UH2, 1); mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 853bb871c7ed..2d6a64bbac44 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -295,6 +295,8 @@ static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { static void __init pcm038_init(void) { + imx27_soc_init(); + mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), "PCM038"); diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index 026441628dfa..163cc318cafb 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c @@ -356,6 +356,8 @@ static struct esdhc_platform_data sd1_pdata = { */ static void __init pcm043_init(void) { + imx35_soc_init(); + mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); mxc_audmux_v2_configure_port(3, diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c index c16328715939..3626f486498a 100644 --- a/arch/arm/mach-imx/mach-qong.c +++ b/arch/arm/mach-imx/mach-qong.c @@ -244,6 +244,8 @@ static void __init qong_init_fpga(void) */ static void __init qong_init(void) { + imx31_soc_init(); + mxc_init_imx_uart(); qong_init_nor_mtd(); qong_init_fpga(); diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index dcaee043628e..82805260e19c 100644 --- a/arch/arm/mach-imx/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c @@ -129,6 +129,8 @@ static struct platform_device *devices[] __initdata = { */ static void __init scb9328_init(void) { + imx1_soc_init(); + imx1_add_imx_uart0(&uart_pdata); printk(KERN_INFO"Scb9328: Adding devices\n"); diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index d74e3473d236..7d8e012a6335 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -267,6 +267,8 @@ static struct platform_device *devices[] __initdata = { */ static void __init vpr200_board_init(void) { + imx35_soc_init(); + mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); imx35_add_fec(NULL); diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index 2e482ba5a0e7..b486595701b7 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -23,7 +23,6 @@ #include <mach/common.h> #include <mach/hardware.h> -#include <mach/gpio.h> #include <mach/irqs.h> #include <mach/iomux-v1.h> @@ -44,15 +43,15 @@ void __init imx1_init_early(void) MX1_NUM_GPIO_PORT); } -static struct mxc_gpio_port imx1_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), - DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), -}; - void __init mx1_init_irq(void) { mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); - mxc_gpio_init(imx1_gpio_ports, ARRAY_SIZE(imx1_gpio_ports)); +} + +void __init imx1_soc_init(void) +{ + mxc_register_gpio(0, MX1_GPIO1_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTA, 0); + mxc_register_gpio(1, MX1_GPIO2_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTB, 0); + mxc_register_gpio(2, MX1_GPIO3_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTC, 0); + mxc_register_gpio(3, MX1_GPIO4_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTD, 0); } diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 7a0c500ac2c8..f0fb8bcce6f9 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -24,7 +24,6 @@ #include <mach/common.h> #include <asm/pgtable.h> #include <asm/mach/map.h> -#include <mach/gpio.h> #include <mach/irqs.h> #include <mach/iomux-v1.h> @@ -70,17 +69,17 @@ void __init imx21_init_early(void) MX21_NUM_GPIO_PORT); } -static struct mxc_gpio_port imx21_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), - DEFINE_IMX_GPIO_PORT(MX21, 1, 2), - DEFINE_IMX_GPIO_PORT(MX21, 2, 3), - DEFINE_IMX_GPIO_PORT(MX21, 3, 4), - DEFINE_IMX_GPIO_PORT(MX21, 4, 5), - DEFINE_IMX_GPIO_PORT(MX21, 5, 6), -}; - void __init mx21_init_irq(void) { mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); - mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); +} + +void __init imx21_soc_init(void) +{ + mxc_register_gpio(0, MX21_GPIO1_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); + mxc_register_gpio(1, MX21_GPIO2_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); + mxc_register_gpio(2, MX21_GPIO3_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); + mxc_register_gpio(3, MX21_GPIO4_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); + mxc_register_gpio(4, MX21_GPIO5_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); + mxc_register_gpio(5, MX21_GPIO6_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); } diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c index 02f7b5c7fa8e..1b6d583f750a 100644 --- a/arch/arm/mach-imx/mm-imx25.c +++ b/arch/arm/mach-imx/mm-imx25.c @@ -27,7 +27,6 @@ #include <mach/hardware.h> #include <mach/mx25.h> #include <mach/iomux-v3.h> -#include <mach/gpio.h> #include <mach/irqs.h> /* @@ -57,16 +56,15 @@ void __init imx25_init_early(void) mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); } -static struct mxc_gpio_port imx25_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), - DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), - DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), - DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), -}; - void __init mx25_init_irq(void) { mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); - mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports)); } +void __init imx25_soc_init(void) +{ + mxc_register_gpio(0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0); + mxc_register_gpio(1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0); + mxc_register_gpio(2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); + mxc_register_gpio(3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); +} diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index a6761a39f08c..d3700cec8ec5 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -24,7 +24,6 @@ #include <mach/common.h> #include <asm/pgtable.h> #include <asm/mach/map.h> -#include <mach/gpio.h> #include <mach/irqs.h> #include <mach/iomux-v1.h> @@ -70,17 +69,17 @@ void __init imx27_init_early(void) MX27_NUM_GPIO_PORT); } -static struct mxc_gpio_port imx27_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), - DEFINE_IMX_GPIO_PORT(MX27, 1, 2), - DEFINE_IMX_GPIO_PORT(MX27, 2, 3), - DEFINE_IMX_GPIO_PORT(MX27, 3, 4), - DEFINE_IMX_GPIO_PORT(MX27, 4, 5), - DEFINE_IMX_GPIO_PORT(MX27, 5, 6), -}; - void __init mx27_init_irq(void) { mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); - mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); +} + +void __init imx27_soc_init(void) +{ + mxc_register_gpio(0, MX27_GPIO1_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0); + mxc_register_gpio(1, MX27_GPIO2_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0); + mxc_register_gpio(2, MX27_GPIO3_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0); + mxc_register_gpio(3, MX27_GPIO4_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0); + mxc_register_gpio(4, MX27_GPIO5_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0); + mxc_register_gpio(5, MX27_GPIO6_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0); } diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c index 86b9b45864d2..cb16ac661776 100644 --- a/arch/arm/mach-imx/mm-imx31.c +++ b/arch/arm/mach-imx/mm-imx31.c @@ -26,7 +26,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-v3.h> -#include <mach/gpio.h> #include <mach/irqs.h> static struct map_desc mx31_io_desc[] __initdata = { @@ -53,14 +52,14 @@ void __init imx31_init_early(void) mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); } -static struct mxc_gpio_port imx31_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), -}; - void __init mx31_init_irq(void) { mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); - mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports)); +} + +void __init imx31_soc_init(void) +{ + mxc_register_gpio(0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); + mxc_register_gpio(1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); + mxc_register_gpio(2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); } diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c index c880e6d1ae55..648bfca0163e 100644 --- a/arch/arm/mach-imx/mm-imx35.c +++ b/arch/arm/mach-imx/mm-imx35.c @@ -27,7 +27,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-v3.h> -#include <mach/gpio.h> #include <mach/irqs.h> static struct map_desc mx35_io_desc[] __initdata = { @@ -50,14 +49,14 @@ void __init imx35_init_early(void) mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); } -static struct mxc_gpio_port imx35_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), -}; - void __init mx35_init_irq(void) { mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); - mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports)); +} + +void __init imx35_soc_init(void) +{ + mxc_register_gpio(0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); + mxc_register_gpio(1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); + mxc_register_gpio(2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); } diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c index 5aa053edc17c..bf0fb87946ba 100644 --- a/arch/arm/mach-imx/mx31lite-db.c +++ b/arch/arm/mach-imx/mx31lite-db.c @@ -161,7 +161,7 @@ static const struct spi_imx_master spi0_pdata __initconst = { /* GPIO LEDs */ -static struct gpio_led litekit_leds[] = { +static const struct gpio_led litekit_leds[] __initconst = { { .name = "GPIO0", .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE), @@ -176,19 +176,12 @@ static struct gpio_led litekit_leds[] = { } }; -static struct gpio_led_platform_data litekit_led_platform_data = { +static const struct gpio_led_platform_data + litekit_led_platform_data __initconst = { .leds = litekit_leds, .num_leds = ARRAY_SIZE(litekit_leds), }; -static struct platform_device litekit_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &litekit_led_platform_data, - }, -}; - void __init mx31lite_db_init(void) { mxc_iomux_setup_multiple_pins(litekit_db_board_pins, @@ -197,7 +190,7 @@ void __init mx31lite_db_init(void) imx31_add_imx_uart0(&uart_pdata); imx31_add_mxc_mmc(0, &mmc_pdata); imx31_add_spi_imx0(&spi0_pdata); - platform_device_register(&litekit_led_device); + gpio_led_register_device(-1, &litekit_led_platform_data); imx31_add_imx2_wdt(NULL); imx31_add_mxc_rtc(NULL); } diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 9519fd28a025..c72cb8e0e690 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,5 +1,6 @@ obj-y += io.o idle.o timer.o obj-y += clock.o +obj-y += clock-dummy.o obj-$(CONFIG_DEBUG_FS) += clock-debug.o obj-$(CONFIG_MSM_VIC) += irq-vic.o @@ -8,6 +9,8 @@ obj-$(CONFIG_MSM_IOMMU) += iommu.o iommu_dev.o devices-iommu.o obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o +obj-$(CONFIG_ARCH_MSM8X60) += dma.o +obj-$(CONFIG_ARCH_MSM8960) += dma.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o @@ -23,7 +26,7 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o -obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o +obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o devices-msm8x60.o obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c index 805d4ee53f7e..30f4ace13a46 100644 --- a/arch/arm/mach-msm/acpuclock-arm11.c +++ b/arch/arm/mach-msm/acpuclock-arm11.c @@ -376,7 +376,7 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse) } #if PERF_SWITCH_STEP_DEBUG printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n", - __FUNCTION__, cur_s->a11clk_khz, cur_s->pll); + __func__, cur_s->a11clk_khz, cur_s->pll); #endif if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO && !(plls_enabled & (1 << cur_s->pll))) { diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 18a3c97bc863..4d264eb9a3b1 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -59,6 +59,7 @@ static struct platform_device smc91x_device = { static struct platform_device *devices[] __initdata = { &msm_device_uart3, + &msm_device_dmov, &msm_device_smd, &msm_device_nand, &msm_device_hsusb, diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index 7a9a03eb189c..db3201ad8652 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c @@ -44,6 +44,7 @@ static struct platform_device *devices[] __initdata = { #if !defined(CONFIG_MSM_SERIAL_DEBUGGER) &msm_device_uart1, #endif + &msm_device_dmov, &msm_device_uart_dm1, &msm_device_nand, }; diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index b7a84966b711..8d21769d288e 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -79,6 +79,7 @@ static struct platform_device *devices[] __initdata = { #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) &msm_device_uart2, #endif + &msm_device_dmov, &msm_device_smd, &msm_device_otg, &msm_device_hsusb, diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 35c7ceeb3f29..8294692c27d7 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c @@ -35,6 +35,11 @@ static void __init msm8960_map_io(void) msm_map_msm8960_io(); } +static void __init msm8960_init_early(void) +{ + msm_clock_init(msm_clocks_8960, msm_num_clocks_8960); +} + static void __init msm8960_init_irq(void) { unsigned int i; @@ -65,18 +70,30 @@ static struct platform_device *rumi3_devices[] __initdata = { &msm8960_device_uart_gsbi5, }; +static struct platform_device *devices[] __initdata = { + &msm8960_device_dmov, +}; + +static void __init msm8960_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + static void __init msm8960_sim_init(void) { + msm8960_init(); platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices)); } static void __init msm8960_rumi3_init(void) { + msm8960_init(); platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices)); } MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") .map_io = msm8960_map_io, + .init_early = msm8960_init_early, .init_irq = msm8960_init_irq, .timer = &msm_timer, .init_machine = msm8960_sim_init, @@ -84,6 +101,7 @@ MACHINE_END MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") .map_io = msm8960_map_io, + .init_early = msm8960_init_early, .init_irq = msm8960_init_irq, .timer = &msm_timer, .init_machine = msm8960_rumi3_init, diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 1163b6fd05d2..98c47ce517fb 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,6 +27,7 @@ #include <mach/board.h> #include <mach/msm_iomap.h> +#include "devices.h" static void __init msm8x60_map_io(void) @@ -34,6 +35,11 @@ static void __init msm8x60_map_io(void) msm_map_msm8x60_io(); } +static struct platform_device *devices[] __initdata = { + &msm_device_dmov_adm0, + &msm_device_dmov_adm1, +}; + static void __init msm8x60_init_irq(void) { unsigned int i; @@ -62,6 +68,7 @@ static void __init msm8x60_init_irq(void) static void __init msm8x60_init(void) { + platform_add_devices(devices, ARRAY_SIZE(devices)); } MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 6a96911b0ad5..491fe76687b1 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -93,6 +93,7 @@ static struct msm_otg_platform_data msm_otg_pdata = { static struct platform_device *devices[] __initdata = { &msm_device_uart3, + &msm_device_dmov, &msm_device_smd, &msm_device_otg, &msm_device_hsusb, diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 814386772c66..5831ce573739 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -35,6 +35,7 @@ extern int trout_init_mmc(unsigned int); static struct platform_device *devices[] __initdata = { &msm_device_uart3, + &msm_device_dmov, &msm_device_smd, &msm_device_nand, &msm_device_hsusb, diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c new file mode 100644 index 000000000000..8ae376867a51 --- /dev/null +++ b/arch/arm/mach-msm/clock-dummy.c @@ -0,0 +1,81 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "clock.h" + +static int dummy_clk_enable(unsigned id) +{ + return 0; +} + +static void dummy_clk_disable(unsigned id) +{ +} + +static int dummy_clk_reset(unsigned id, enum clk_reset_action action) +{ + return 0; +} + +static int dummy_clk_set_rate(unsigned id, unsigned rate) +{ + return 0; +} + +static int dummy_clk_set_min_rate(unsigned id, unsigned rate) +{ + return 0; +} + +static int dummy_clk_set_max_rate(unsigned id, unsigned rate) +{ + return 0; +} + +static int dummy_clk_set_flags(unsigned id, unsigned flags) +{ + return 0; +} + +static unsigned dummy_clk_get_rate(unsigned id) +{ + return 0; +} + +static unsigned dummy_clk_is_enabled(unsigned id) +{ + return 0; +} + +static long dummy_clk_round_rate(unsigned id, unsigned rate) +{ + return rate; +} + +static bool dummy_clk_is_local(unsigned id) +{ + return true; +} + +struct clk_ops clk_ops_dummy = { + .enable = dummy_clk_enable, + .disable = dummy_clk_disable, + .reset = dummy_clk_reset, + .set_rate = dummy_clk_set_rate, + .set_min_rate = dummy_clk_set_min_rate, + .set_max_rate = dummy_clk_set_max_rate, + .set_flags = dummy_clk_set_flags, + .get_rate = dummy_clk_get_rate, + .is_enabled = dummy_clk_is_enabled, + .round_rate = dummy_clk_round_rate, + .is_local = dummy_clk_is_local, +}; diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h index 2c007f606d29..1e6207463e6d 100644 --- a/arch/arm/mach-msm/clock.h +++ b/arch/arm/mach-msm/clock.h @@ -69,4 +69,15 @@ static inline int __init clock_debug_init(void) { return 0; } static inline int __init clock_debug_add(struct clk *clock) { return 0; } #endif +extern struct clk_ops clk_ops_dummy; + +#define CLK_DUMMY(clk_name, clk_id, clk_dev) { \ + .con_id = clk_name, \ + .dev_id = clk_dev, \ + .clk = &(struct clk){ \ + .dbg_name = #clk_id, \ + .ops = &clk_ops_dummy, \ + }, \ + } + #endif diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index c4f5e26feb4d..3ef38a53c508 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -418,8 +418,27 @@ struct platform_device msm_device_mdp = { .resource = resources_mdp, }; +static struct resource resources_dmov[] = { + { + .start = MSM7X00_DMOV_PHYS, + .end = MSM7X00_DMOV_PHYS + MSM7X00_DMOV_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_ADM_AARM, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_dmov = { + .name = "msm_dmov", + .id = -1, + .num_resources = ARRAY_SIZE(resources_dmov), + .resource = resources_dmov, +}; + struct clk_lookup msm_clocks_7x01a[] = { - CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), + CLK_PCOM("adm_clk", ADM_CLK, "msm_dmov", 0), CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0), CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index 09b4f1403824..f803fcd380d0 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c @@ -130,8 +130,27 @@ struct platform_device msm_device_hsusb_host = { }, }; +static struct resource resources_dmov[] = { + { + .start = MSM7X30_DMOV_PHYS, + .end = MSM7X30_DMOV_PHYS + MSM7X30_DMOV_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_ADM_AARM, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_dmov = { + .name = "msm_dmov", + .id = -1, + .num_resources = ARRAY_SIZE(resources_dmov), + .resource = resources_dmov, +}; + struct clk_lookup msm_clocks_7x30[] = { - CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), + CLK_PCOM("adm_clk", ADM_CLK, "msm_dmov", 0), CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0), CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF), diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c index d9e1f26475de..2e17ac6f1f04 100644 --- a/arch/arm/mach-msm/devices-msm8960.c +++ b/arch/arm/mach-msm/devices-msm8960.c @@ -21,8 +21,11 @@ #include <linux/dma-mapping.h> #include <mach/irqs-8960.h> #include <mach/board.h> +#include <mach/msm_iomap.h> +#include <mach/irqs.h> #include "devices.h" +#include "clock.h" #define MSM_GSBI2_PHYS 0x16100000 #define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000) @@ -83,3 +86,181 @@ struct platform_device msm8960_device_uart_gsbi5 = { .num_resources = ARRAY_SIZE(resources_uart_gsbi5), .resource = resources_uart_gsbi5, }; + +static struct resource resources_dmov[] = { + { + .start = MSM8960_DMOV_PHYS, + .end = MSM8960_DMOV_PHYS + MSM8960_DMOV_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_ADM0_SCSS_0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm8960_device_dmov = { + .name = "msm_dmov", + .id = -1, + .num_resources = ARRAY_SIZE(resources_dmov), + .resource = resources_dmov, +}; + +struct clk_lookup msm_clocks_8960[] = { + CLK_DUMMY("gsbi_uart_clk", GSBI1_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI2_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI3_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI4_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI5_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI6_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI7_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI8_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI9_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI10_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI11_UART_CLK, NULL), + CLK_DUMMY("gsbi_uart_clk", GSBI12_UART_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI1_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI2_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI3_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI4_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI5_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI6_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI7_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI8_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI9_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI10_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI11_QUP_CLK, NULL), + CLK_DUMMY("gsbi_qup_clk", GSBI12_QUP_CLK, NULL), + CLK_DUMMY("pdm_clk", PDM_CLK, NULL), + CLK_DUMMY("pmem_clk", PMEM_CLK, NULL), + CLK_DUMMY("prng_clk", PRNG_CLK, NULL), + CLK_DUMMY("sdc_clk", SDC1_CLK, NULL), + CLK_DUMMY("sdc_clk", SDC2_CLK, NULL), + CLK_DUMMY("sdc_clk", SDC3_CLK, NULL), + CLK_DUMMY("sdc_clk", SDC4_CLK, NULL), + CLK_DUMMY("sdc_clk", SDC5_CLK, NULL), + CLK_DUMMY("tsif_ref_clk", TSIF_REF_CLK, NULL), + CLK_DUMMY("tssc_clk", TSSC_CLK, NULL), + CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL), + CLK_DUMMY("usb_phy_clk", USB_PHY0_CLK, NULL), + CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL), + CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL), + CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL), + CLK_DUMMY("usb_fs_src_clk", USB_FS2_SRC_CLK, NULL), + CLK_DUMMY("usb_fs_clk", USB_FS2_XCVR_CLK, NULL), + CLK_DUMMY("usb_fs_sys_clk", USB_FS2_SYS_CLK, NULL), + CLK_DUMMY("ce_clk", CE2_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI1_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI2_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI3_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI4_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI5_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI6_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI7_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI8_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI9_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI10_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI11_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL), + CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL), + CLK_DUMMY("ppss_pclk", PPSS_P_CLK, NULL), + CLK_DUMMY("tsif_pclk", TSIF_P_CLK, NULL), + CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL), + CLK_DUMMY("usb_fs_pclk", USB_FS2_P_CLK, NULL), + CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL), + CLK_DUMMY("sdc_pclk", SDC1_P_CLK, NULL), + CLK_DUMMY("sdc_pclk", SDC2_P_CLK, NULL), + CLK_DUMMY("sdc_pclk", SDC3_P_CLK, NULL), + CLK_DUMMY("sdc_pclk", SDC4_P_CLK, NULL), + CLK_DUMMY("sdc_pclk", SDC5_P_CLK, NULL), + CLK_DUMMY("adm_clk", ADM0_CLK, NULL), + CLK_DUMMY("adm_pclk", ADM0_P_CLK, NULL), + CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL), + CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL), + CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL), + CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL), + CLK_DUMMY("amp_clk", AMP_CLK, NULL), + CLK_DUMMY("cam_clk", CAM0_CLK, NULL), + CLK_DUMMY("cam_clk", CAM1_CLK, NULL), + CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL), + CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL), + CLK_DUMMY("csi_clk", CSI0_CLK, NULL), + CLK_DUMMY("csi_clk", CSI1_CLK, NULL), + CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL), + CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL), + CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL), + CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL), + CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL), + CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, NULL), + CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, NULL), + CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, NULL), + CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, NULL), + CLK_DUMMY("gfx2d0_clk", GFX2D0_CLK, NULL), + CLK_DUMMY("gfx2d1_clk", GFX2D1_CLK, NULL), + CLK_DUMMY("gfx3d_clk", GFX3D_CLK, NULL), + CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL), + CLK_DUMMY("imem_axi_clk", IMEM_AXI_CLK, NULL), + CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL), + CLK_DUMMY("mdp_clk", MDP_CLK, NULL), + CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL), + CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL), + CLK_DUMMY("rot_clk", ROT_CLK, NULL), + CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL), + CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL), + CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL), + CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL), + CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL), + CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL), + CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL), + CLK_DUMMY("vpe_clk", VPE_CLK, NULL), + CLK_DUMMY("vfe_clk", VFE_CLK, NULL), + CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL), + CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL), + CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL), + CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL), + CLK_DUMMY("rot_axi_clk", ROT_AXI_CLK, NULL), + CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL), + CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL), + CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL), + CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL), + CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL), + CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL), + CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, NULL), + CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, NULL), + CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, NULL), + CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, NULL), + CLK_DUMMY("gfx2d0_pclk", GFX2D0_P_CLK, NULL), + CLK_DUMMY("gfx2d1_pclk", GFX2D1_P_CLK, NULL), + CLK_DUMMY("gfx3d_pclk", GFX3D_P_CLK, NULL), + CLK_DUMMY("hdmi_m_pclk", HDMI_M_P_CLK, NULL), + CLK_DUMMY("hdmi_s_pclk", HDMI_S_P_CLK, NULL), + CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL), + CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL), + CLK_DUMMY("imem_pclk", IMEM_P_CLK, NULL), + CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL), + CLK_DUMMY("smmu_pclk", SMMU_P_CLK, NULL), + CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL), + CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL), + CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL), + CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL), + CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL), + CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL), + CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL), + CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL), + CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL), + CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL), + CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL), + CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL), + CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL), + CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL), + CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL), + CLK_DUMMY("pcm_clk", PCM_CLK, NULL), + CLK_DUMMY("iommu_clk", JPEGD_AXI_CLK, NULL), + CLK_DUMMY("iommu_clk", VFE_AXI_CLK, NULL), + CLK_DUMMY("iommu_clk", VCODEC_AXI_CLK, NULL), + CLK_DUMMY("iommu_clk", GFX3D_CLK, NULL), + CLK_DUMMY("iommu_clk", GFX2D0_CLK, NULL), + CLK_DUMMY("iommu_clk", GFX2D1_CLK, NULL), +}; + +unsigned msm_num_clocks_8960 = ARRAY_SIZE(msm_clocks_8960); diff --git a/arch/arm/mach-msm/devices-msm8x60.c b/arch/arm/mach-msm/devices-msm8x60.c new file mode 100644 index 000000000000..33c236ce7cf2 --- /dev/null +++ b/arch/arm/mach-msm/devices-msm8x60.c @@ -0,0 +1,56 @@ +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/board.h> +#include <mach/msm_iomap.h> +#include <mach/dma.h> + +static struct resource resources_dmov_adm0[] = { + { + .start = MSM8X60_DMOV_ADM0_PHYS, + .end = MSM8X60_DMOV_ADM0_PHYS + MSM8X60_DMOV_ADM0_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_ADM0_AARM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource resources_dmov_adm1[] = { + { + .start = MSM8X60_DMOV_ADM1_PHYS, + .end = MSM8X60_DMOV_ADM1_PHYS + MSM8X60_DMOV_ADM1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_ADM1_AARM, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_dmov_adm0 = { + .name = "msm_dmov", + .id = 0, + .num_resources = ARRAY_SIZE(resources_dmov_adm0), + .resource = resources_dmov_adm0, +}; + +struct platform_device msm_device_dmov_adm1 = { + .name = "msm_dmov", + .id = 1, + .num_resources = ARRAY_SIZE(resources_dmov_adm1), + .resource = resources_dmov_adm1, +}; diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index 12d8deb78d9c..730982fe5902 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -315,8 +315,27 @@ int __init msm_add_sdcc(unsigned int controller, return platform_device_register(pdev); } +static struct resource resources_dmov[] = { + { + .start = QSD8X50_DMOV_PHYS, + .end = QSD8X50_DMOV_PHYS + QSD8X50_DMOV_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_ADM_AARM, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_dmov = { + .name = "msm_dmov", + .id = -1, + .num_resources = ARRAY_SIZE(resources_dmov), + .resource = resources_dmov, +}; + struct clk_lookup msm_clocks_8x50[] = { - CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), + CLK_PCOM("adm_clk", ADM_CLK, "msm_dmov", 0), CLK_PCOM("ce_clk", CE_CLK, NULL, 0), CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 9545c196c6e8..e38fc8610f39 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h @@ -40,6 +40,11 @@ extern struct platform_device msm_device_i2c; extern struct platform_device msm_device_smd; +extern struct platform_device msm_device_dmov; +extern struct platform_device msm8960_device_dmov; +extern struct platform_device msm_device_dmov_adm0; +extern struct platform_device msm_device_dmov_adm1; + extern struct platform_device msm_device_nand; extern struct platform_device msm_device_mddi0; @@ -55,4 +60,7 @@ extern unsigned msm_num_clocks_7x30; extern struct clk_lookup msm_clocks_8x50[]; extern unsigned msm_num_clocks_8x50; +extern struct clk_lookup msm_clocks_8960[]; +extern unsigned msm_num_clocks_8960; + #endif diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c index 02cae5e2951c..16b40344d98c 100644 --- a/arch/arm/mach-msm/dma.c +++ b/arch/arm/mach-msm/dma.c @@ -1,6 +1,7 @@ /* linux/arch/arm/mach-msm/dma.c * * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -18,9 +19,15 @@ #include <linux/io.h> #include <linux/interrupt.h> #include <linux/completion.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/slab.h> #include <mach/dma.h> #define MSM_DMOV_CHANNEL_COUNT 16 +#define MSM_DMOV_MAX_ADMS 2 + +#define MODULE_NAME "msm_dmov" enum { MSM_DMOV_PRINT_ERRORS = 1, @@ -28,13 +35,55 @@ enum { MSM_DMOV_PRINT_FLOW = 4 }; -static DEFINE_SPINLOCK(msm_dmov_lock); -static struct clk *msm_dmov_clk; -static unsigned int channel_active; -static struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT]; -static struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT]; unsigned int msm_dmov_print_mask = MSM_DMOV_PRINT_ERRORS; +struct msm_dmov_conf { + void __iomem *base; + int channel_active; + struct list_head ready_commands[MSM_DMOV_CHANNEL_COUNT]; + struct list_head active_commands[MSM_DMOV_CHANNEL_COUNT]; + spinlock_t lock; + unsigned irq; + struct clk *clk; + struct clk *pclk; +}; + +static struct msm_dmov_conf dmov_conf[MSM_DMOV_MAX_ADMS]; +static int nr_adms; + +#if defined(CONFIG_ARCH_MSM7X30) +#define DMOV_SD_AARM DMOV_SD2 +#define DMOV_SD_SIZE 0x400 +#elif defined(CONFIG_ARCH_MSM8X60) +#define DMOV_SD_AARM DMOV_SD1 +#define DMOV_SD_SIZE 0x800 +#elif defined(CONFIG_ARCH_MSM8960) +#define DMOV_SD_AARM DMOV_SD0 +#define DMOV_SD_SIZE 0x800 +#else +#define DMOV_SD_AARM DMOV_SD3 +#define DMOV_SD_SIZE 0x400 +#endif + +#define DMOV_ADDR(sd, off, ch) (((sd) * DMOV_SD_SIZE) + (off) + ((ch) << 2)) + +#define DMOV_SD0(off, ch) DMOV_ADDR(0, off, ch) +#define DMOV_SD1(off, ch) DMOV_ADDR(1, off, ch) +#define DMOV_SD2(off, ch) DMOV_ADDR(2, off, ch) +#define DMOV_SD3(off, ch) DMOV_ADDR(3, off, ch) + +#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch) +#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch) +#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch) +#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch) +#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch) +#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch) +#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch) +#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch) +#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch) +#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch) +#define DMOV_ISR DMOV_SD_AARM(0x380, 0) + #define MSM_DMOV_DPRINTF(mask, format, args...) \ do { \ if ((mask) & msm_dmov_print_mask) \ @@ -47,48 +96,121 @@ unsigned int msm_dmov_print_mask = MSM_DMOV_PRINT_ERRORS; #define PRINT_FLOW(format, args...) \ MSM_DMOV_DPRINTF(MSM_DMOV_PRINT_FLOW, format, args); -void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) +static inline unsigned dmov_readl(unsigned addr, int adm) +{ + return readl(dmov_conf[adm].base + addr); +} + +static inline void dmov_writel(unsigned val, unsigned addr, int adm) +{ + writel(val, dmov_conf[adm].base + addr); +} + +#define DMOV_ID_TO_ADM(id) ((id) / MSM_DMOV_CHANNEL_COUNT) +#define DMOV_ID_TO_CHAN(id) ((id) % MSM_DMOV_CHANNEL_COUNT) +#define DMOV_CHAN_ADM_TO_ID(ch, adm) ((ch) + (adm) * MSM_DMOV_CHANNEL_COUNT) + +int msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) +{ + int adm = DMOV_ID_TO_ADM(id); + int ch = DMOV_ID_TO_CHAN(id); + + if (!dmov_conf[adm].base) + return -ENODEV; + + dmov_writel((graceful << 31), DMOV_FLUSH0(ch), adm); + + return 0; +} +EXPORT_SYMBOL(msm_dmov_stop_cmd); + +static int msm_dmov_clocks_on(int adm) +{ + int ret = 0; + + if (!IS_ERR(dmov_conf[adm].clk)) { + ret = clk_enable(dmov_conf[adm].clk); + if (ret) + return ret; + if (!IS_ERR(dmov_conf[adm].pclk)) { + ret = clk_enable(dmov_conf[adm].pclk); + if (ret) + clk_disable(dmov_conf[adm].clk); + } + } + return ret; +} + +static void msm_dmov_clocks_off(int adm) { - writel((graceful << 31), DMOV_FLUSH0(id)); + if (!IS_ERR(dmov_conf[adm].clk)) + clk_disable(dmov_conf[adm].clk); + if (!IS_ERR(dmov_conf[adm].pclk)) + clk_disable(dmov_conf[adm].pclk); } -void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) +int msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { unsigned long irq_flags; unsigned int status; + int adm = DMOV_ID_TO_ADM(id); + int ch = DMOV_ID_TO_CHAN(id); + + if (!dmov_conf[adm].base) + return -ENODEV; - spin_lock_irqsave(&msm_dmov_lock, irq_flags); - if (!channel_active) - clk_enable(msm_dmov_clk); + spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags); + if (!dmov_conf[adm].channel_active) + msm_dmov_clocks_on(adm); dsb(); - status = readl(DMOV_STATUS(id)); - if (list_empty(&ready_commands[id]) && + status = dmov_readl(DMOV_STATUS(ch), adm); + if (list_empty(&dmov_conf[adm].ready_commands[ch]) && (status & DMOV_STATUS_CMD_PTR_RDY)) { -#if 0 - if (list_empty(&active_commands[id])) { - PRINT_FLOW("msm_dmov_enqueue_cmd(%d), enable interrupt\n", id); - writel(DMOV_CONFIG_IRQ_EN, DMOV_CONFIG(id)); - } -#endif if (cmd->execute_func) cmd->execute_func(cmd); - PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n", id, status); - list_add_tail(&cmd->list, &active_commands[id]); - if (!channel_active) - enable_irq(INT_ADM_AARM); - channel_active |= 1U << id; - writel(cmd->cmdptr, DMOV_CMD_PTR(id)); + PRINT_IO("msm_dmov_enqueue_cmd(%d), start command, status %x\n", + id, status); + list_add_tail(&cmd->list, &dmov_conf[adm].active_commands[ch]); + if (!dmov_conf[adm].channel_active) + enable_irq(dmov_conf[adm].irq); + dmov_conf[adm].channel_active |= 1U << ch; + dmov_writel(cmd->cmdptr, DMOV_CMD_PTR(ch), adm); } else { - if (!channel_active) - clk_disable(msm_dmov_clk); - if (list_empty(&active_commands[id])) - PRINT_ERROR("msm_dmov_enqueue_cmd(%d), error datamover stalled, status %x\n", id, status); + if (!dmov_conf[adm].channel_active) + msm_dmov_clocks_off(adm); + if (list_empty(&dmov_conf[adm].active_commands[ch])) + PRINT_ERROR("msm_dmov_enqueue_cmd(%d), error datamover " + "stalled, status %x\n", id, status); + PRINT_IO("msm_dmov_enqueue_cmd(%d), enqueue command, status " + "%x\n", id, status); + list_add_tail(&cmd->list, &dmov_conf[adm].ready_commands[ch]); + } + spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags); - PRINT_IO("msm_dmov_enqueue_cmd(%d), enqueue command, status %x\n", id, status); - list_add_tail(&cmd->list, &ready_commands[id]); + return 0; +} +EXPORT_SYMBOL(msm_dmov_enqueue_cmd); + +int msm_dmov_flush(unsigned int id) +{ + unsigned long flags; + int ch = DMOV_ID_TO_CHAN(id); + int adm = DMOV_ID_TO_ADM(id); + + if (!dmov_conf[adm].base) + return -ENODEV; + + spin_lock_irqsave(&dmov_conf[adm].lock, flags); + /* XXX not checking if flush cmd sent already */ + if (!list_empty(&dmov_conf[adm].active_commands[ch])) { + PRINT_IO("msm_dmov_flush(%d), send flush cmd\n", id); + dmov_writel(DMOV_FLUSH_GRACEFUL, DMOV_FLUSH0(ch), adm); } - spin_unlock_irqrestore(&msm_dmov_lock, irq_flags); + spin_unlock_irqrestore(&dmov_conf[adm].lock, flags); + + return 0; } +EXPORT_SYMBOL(msm_dmov_flush); struct msm_dmov_exec_cmdptr_cmd { struct msm_dmov_cmd dmov_cmd; @@ -114,6 +236,10 @@ dmov_exec_cmdptr_complete_func(struct msm_dmov_cmd *_cmd, int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { struct msm_dmov_exec_cmdptr_cmd cmd; + int adm = DMOV_ID_TO_ADM(id); + + if (!dmov_conf[adm].base) + return -ENODEV; PRINT_FLOW("dmov_exec_cmdptr(%d, %x)\n", id, cmdptr); @@ -135,41 +261,68 @@ int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) PRINT_FLOW("dmov_exec_cmdptr(%d, %x) done\n", id, cmdptr); return 0; } +EXPORT_SYMBOL(msm_dmov_exec_cmd); +static void msm_dmov_fill_errdata(struct msm_dmov_errdata *errdata, int ch, + int adm) +{ + errdata->flush[0] = dmov_readl(DMOV_FLUSH0(ch), adm); + errdata->flush[1] = dmov_readl(DMOV_FLUSH1(ch), adm); + errdata->flush[2] = dmov_readl(DMOV_FLUSH2(ch), adm); + errdata->flush[3] = dmov_readl(DMOV_FLUSH3(ch), adm); + errdata->flush[4] = dmov_readl(DMOV_FLUSH4(ch), adm); + errdata->flush[5] = dmov_readl(DMOV_FLUSH5(ch), adm); +} + +static int msm_dmov_irq_to_adm(unsigned irq) +{ + int i; + for (i = 0; i < nr_adms; i++) + if (dmov_conf[i].irq == irq) + return i; + PRINT_ERROR("msm_dmov_irq_to_adm: can't match ADM to IRQ %d\n", irq); + return -EINVAL; +} static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) { unsigned int int_status, mask, id; unsigned long irq_flags; + unsigned int ch; unsigned int ch_status; unsigned int ch_result; struct msm_dmov_cmd *cmd; + int adm = msm_dmov_irq_to_adm(irq); - spin_lock_irqsave(&msm_dmov_lock, irq_flags); + spin_lock_irqsave(&dmov_conf[adm].lock, irq_flags); - int_status = readl(DMOV_ISR); /* read and clear interrupt */ + int_status = dmov_readl(DMOV_ISR, adm); /* read and clear interrupt */ PRINT_FLOW("msm_datamover_irq_handler: DMOV_ISR %x\n", int_status); while (int_status) { mask = int_status & -int_status; - id = fls(mask) - 1; + ch = fls(mask) - 1; + id = DMOV_CHAN_ADM_TO_ID(ch, adm); PRINT_FLOW("msm_datamover_irq_handler %08x %08x id %d\n", int_status, mask, id); int_status &= ~mask; - ch_status = readl(DMOV_STATUS(id)); + ch_status = dmov_readl(DMOV_STATUS(ch), adm); if (!(ch_status & DMOV_STATUS_RSLT_VALID)) { PRINT_FLOW("msm_datamover_irq_handler id %d, result not valid %x\n", id, ch_status); continue; } do { - ch_result = readl(DMOV_RSLT(id)); - if (list_empty(&active_commands[id])) { + ch_result = dmov_readl(DMOV_RSLT(ch), adm); + if (list_empty(&dmov_conf[adm].active_commands[ch])) { PRINT_ERROR("msm_datamover_irq_handler id %d, got result " "with no active command, status %x, result %x\n", id, ch_status, ch_result); cmd = NULL; } else - cmd = list_entry(active_commands[id].next, typeof(*cmd), list); - PRINT_FLOW("msm_datamover_irq_handler id %d, status %x, result %x\n", id, ch_status, ch_result); + cmd = list_entry(dmov_conf[adm]. + active_commands[ch].next, typeof(*cmd), + list); + PRINT_FLOW("msm_datamover_irq_handler id %d, status %x," + " result %x\n", id, ch_status, ch_result); if (ch_result & DMOV_RSLT_DONE) { PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); @@ -184,12 +337,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) if (ch_result & DMOV_RSLT_FLUSH) { struct msm_dmov_errdata errdata; - errdata.flush[0] = readl(DMOV_FLUSH0(id)); - errdata.flush[1] = readl(DMOV_FLUSH1(id)); - errdata.flush[2] = readl(DMOV_FLUSH2(id)); - errdata.flush[3] = readl(DMOV_FLUSH3(id)); - errdata.flush[4] = readl(DMOV_FLUSH4(id)); - errdata.flush[5] = readl(DMOV_FLUSH5(id)); + msm_dmov_fill_errdata(&errdata, ch, adm); PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); PRINT_FLOW("msm_datamover_irq_handler id %d, flush, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]); if (cmd) { @@ -201,13 +349,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) if (ch_result & DMOV_RSLT_ERROR) { struct msm_dmov_errdata errdata; - errdata.flush[0] = readl(DMOV_FLUSH0(id)); - errdata.flush[1] = readl(DMOV_FLUSH1(id)); - errdata.flush[2] = readl(DMOV_FLUSH2(id)); - errdata.flush[3] = readl(DMOV_FLUSH3(id)); - errdata.flush[4] = readl(DMOV_FLUSH4(id)); - errdata.flush[5] = readl(DMOV_FLUSH5(id)); - + msm_dmov_fill_errdata(&errdata, ch, adm); PRINT_ERROR("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); PRINT_ERROR("msm_datamover_irq_handler id %d, error, result %x, flush0 %x\n", id, ch_result, errdata.flush[0]); if (cmd) { @@ -217,55 +359,148 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) } /* this does not seem to work, once we get an error */ /* the datamover will no longer accept commands */ - writel(0, DMOV_FLUSH0(id)); + dmov_writel(0, DMOV_FLUSH0(ch), adm); } - ch_status = readl(DMOV_STATUS(id)); + ch_status = dmov_readl(DMOV_STATUS(ch), adm); PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); - if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { - cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); + if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && + !list_empty(&dmov_conf[adm].ready_commands[ch])) { + cmd = list_entry(dmov_conf[adm]. + ready_commands[ch].next, typeof(*cmd), + list); list_del(&cmd->list); - list_add_tail(&cmd->list, &active_commands[id]); + list_add_tail(&cmd->list, &dmov_conf[adm]. + active_commands[ch]); if (cmd->execute_func) cmd->execute_func(cmd); PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); - writel(cmd->cmdptr, DMOV_CMD_PTR(id)); + dmov_writel(cmd->cmdptr, DMOV_CMD_PTR(ch), adm); } } while (ch_status & DMOV_STATUS_RSLT_VALID); - if (list_empty(&active_commands[id]) && list_empty(&ready_commands[id])) - channel_active &= ~(1U << id); + if (list_empty(&dmov_conf[adm].active_commands[ch]) && + list_empty(&dmov_conf[adm].ready_commands[ch])) + dmov_conf[adm].channel_active &= ~(1U << ch); PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); } - if (!channel_active) { - disable_irq_nosync(INT_ADM_AARM); - clk_disable(msm_dmov_clk); + if (!dmov_conf[adm].channel_active) { + disable_irq_nosync(dmov_conf[adm].irq); + msm_dmov_clocks_off(adm); } - spin_unlock_irqrestore(&msm_dmov_lock, irq_flags); + spin_unlock_irqrestore(&dmov_conf[adm].lock, irq_flags); return IRQ_HANDLED; } -static int __init msm_init_datamover(void) +static void __init msm_dmov_deinit_clocks(int adm) +{ + if (!IS_ERR(dmov_conf[adm].clk)) + clk_put(dmov_conf[adm].clk); + if (!IS_ERR(dmov_conf[adm].pclk)) + clk_put(dmov_conf[adm].pclk); +} + +#define PDEV_TO_ADM(pdev) \ +({ \ + typeof(pdev) _pdev = pdev; \ + (_pdev->id == -1) ? 0 : _pdev->id; \ +}) + +static int __devinit msm_dmov_init_clocks(struct platform_device *pdev) +{ + int ret = 0; + int adm = PDEV_TO_ADM(pdev); + + dmov_conf[adm].clk = clk_get(&pdev->dev, "adm_clk"); + if (IS_ERR(dmov_conf[adm].clk)) { + PRINT_ERROR("%s: Error getting adm_clk\n", __func__); + ret = PTR_ERR(dmov_conf[adm].clk); + } + + dmov_conf[adm].pclk = clk_get(&pdev->dev, "adm_pclk"); + /* pclk not present on all SoCs, don't return error on failure */ + + return ret; +} + +static int __devinit msm_dmov_conf_init(struct platform_device *pdev) { int i; - int ret; - struct clk *clk; + int adm = PDEV_TO_ADM(pdev); + struct resource *irqres = + platform_get_resource(pdev, IORESOURCE_IRQ, 0); + struct resource *memres = + platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!irqres || !memres || !irqres->start) + return -EINVAL; + + dmov_conf[adm].irq = irqres->start; + + dmov_conf[adm].base = + ioremap_nocache(memres->start, resource_size(memres)); + if (!dmov_conf[adm].base) + return -ENOMEM; + + dmov_conf[adm].lock = __SPIN_LOCK_UNLOCKED(dmov_lock); for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) { - INIT_LIST_HEAD(&ready_commands[i]); - INIT_LIST_HEAD(&active_commands[i]); - writel(DMOV_CONFIG_IRQ_EN | DMOV_CONFIG_FORCE_TOP_PTR_RSLT | DMOV_CONFIG_FORCE_FLUSH_RSLT, DMOV_CONFIG(i)); + INIT_LIST_HEAD(&dmov_conf[adm].ready_commands[i]); + INIT_LIST_HEAD(&dmov_conf[adm].active_commands[i]); } - clk = clk_get(NULL, "adm_clk"); - if (IS_ERR(clk)) - return PTR_ERR(clk); - msm_dmov_clk = clk; - ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL); + return 0; +} + +static inline void __devinit msm_dmov_conf_free(int adm) +{ + iounmap(dmov_conf[adm].base); + dmov_conf[adm].base = NULL; +} + +static int __devinit msm_dmov_probe(struct platform_device *pdev) +{ + int i; + int ret; + int adm = PDEV_TO_ADM(pdev); + + ret = msm_dmov_conf_init(pdev); if (ret) return ret; - disable_irq(INT_ADM_AARM); + + for (i = 0; i < MSM_DMOV_CHANNEL_COUNT; i++) + dmov_writel(DMOV_CONFIG_IRQ_EN | DMOV_CONFIG_FORCE_TOP_PTR_RSLT + | DMOV_CONFIG_FORCE_FLUSH_RSLT, DMOV_CONFIG(i), adm); + + ret = msm_dmov_init_clocks(pdev); + if (ret) + goto out_conf; + + ret = request_irq(dmov_conf[adm].irq, msm_datamover_irq_handler, 0, + "msmdatamover", NULL); + if (ret) + goto out_clock; + disable_irq(dmov_conf[adm].irq); + nr_adms++; + return 0; + +out_clock: + msm_dmov_deinit_clocks(adm); +out_conf: + msm_dmov_conf_free(adm); + return ret; } -arch_initcall(msm_init_datamover); +static struct platform_driver msm_dmov_driver = { + .probe = msm_dmov_probe, + .driver = { + .name = MODULE_NAME, + .owner = THIS_MODULE, + }, +}; +static int __init msm_init_datamover(void) +{ + return platform_driver_register(&msm_dmov_driver); +} + +arch_initcall(msm_init_datamover); diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h index 05583f569524..3d677731eda3 100644 --- a/arch/arm/mach-msm/include/mach/dma.h +++ b/arch/arm/mach-msm/include/mach/dma.h @@ -1,6 +1,7 @@ /* linux/include/asm-arm/arch-msm/dma.h * * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -14,6 +15,7 @@ */ #ifndef __ASM_ARCH_MSM_DMA_H +#define __ASM_ARCH_MSM_DMA_H #include <linux/list.h> #include <mach/msm_iomap.h> @@ -32,67 +34,75 @@ struct msm_dmov_cmd { void *data; }; -#ifndef CONFIG_ARCH_MSM8X60 -void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd); -void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful); +int msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd); +int msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful); int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr); -#else -static inline -void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { } -static inline -void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { } -static inline -int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; } -#endif - - -#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2)) -#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2)) -#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) -#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) - -#if defined(CONFIG_ARCH_MSM7X30) -#define DMOV_SD_AARM DMOV_SD2 -#else -#define DMOV_SD_AARM DMOV_SD3 -#endif +int msm_dmov_flush(unsigned int id); -#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch) #define DMOV_CMD_LIST (0 << 29) /* does not work */ #define DMOV_CMD_PTR_LIST (1 << 29) /* works */ #define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ #define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ #define DMOV_CMD_ADDR(addr) ((addr) >> 3) -#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch) #define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ #define DMOV_RSLT_ERROR (1 << 3) #define DMOV_RSLT_FLUSH (1 << 2) #define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ #define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ -#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch) -#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch) -#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch) -#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch) -#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch) -#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch) +#define DMOV_FLUSH_GRACEFUL (1 << 31) -#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch) #define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) #define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) #define DMOV_STATUS_RSLT_VALID (1 << 1) #define DMOV_STATUS_CMD_PTR_RDY (1 << 0) -#define DMOV_ISR DMOV_SD_AARM(0x380, 0) - -#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch) #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) #define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) #define DMOV_CONFIG_IRQ_EN (1 << 0) -/* channel assignments */ +#define DMOV_8X60_GP_CHAN 16 + +#define DMOV_8X60_CE_IN_CHAN 2 +#define DMOV_8X60_CE_IN_CRCI 4 + +#define DMOV_8X60_CE_OUT_CHAN 3 +#define DMOV_8X60_CE_OUT_CRCI 5 + +#define DMOV_8X60_CE_HASH_CRCI 15 + +#define DMOV_8X60_SDC1_CHAN 18 +#define DMOV_8X60_SDC1_CRCI 1 + +#define DMOV_8X60_SDC2_CHAN 19 +#define DMOV_8X60_SDC2_CRCI 4 + +#define DMOV_8X60_SDC3_CHAN 20 +#define DMOV_8X60_SDC3_CRCI 2 + +#define DMOV_8X60_SDC4_CHAN 21 +#define DMOV_8X60_SDC4_CRCI 5 + +#define DMOV_8X60_SDC5_CHAN 21 +#define DMOV_8X60_SDC5_CRCI 14 + +#define DMOV_8X60_TSIF_CHAN 4 +#define DMOV_8X60_TSIF_CRCI 6 + +#define DMOV_8X60_HSUART1_TX_CHAN 22 +#define DMOV_8X60_HSUART1_TX_CRCI 8 + +#define DMOV_8X60_HSUART1_RX_CHAN 23 +#define DMOV_8X60_HSUART1_RX_CRCI 9 + +#define DMOV_8X60_HSUART2_TX_CHAN 8 +#define DMOV_8X60_HSUART2_TX_CRCI 13 + +#define DMOV_8X60_HSUART2_RX_CHAN 8 +#define DMOV_8X60_HSUART2_RX_CRCI 14 +/* channel assignments before 8x60 */ #define DMOV_NAND_CHAN 7 #define DMOV_NAND_CRCI_CMD 5 #define DMOV_NAND_CRCI_DATA 4 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 8f99d97615a0..d6540e1192eb 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -51,9 +51,8 @@ #define MSM7X00_CSR_PHYS 0xC0100000 #define MSM7X00_CSR_SIZE SZ_4K -#define MSM_DMOV_BASE IOMEM(0xE0002000) -#define MSM_DMOV_PHYS 0xA9700000 -#define MSM_DMOV_SIZE SZ_4K +#define MSM7X00_DMOV_PHYS 0xA9700000 +#define MSM7X00_DMOV_SIZE SZ_4K #define MSM_GPIO1_BASE IOMEM(0xE0003000) #define MSM_GPIO1_PHYS 0xA9200000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 4d84be15955e..23912e541cdb 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h @@ -42,9 +42,8 @@ #define MSM7X30_CSR_PHYS 0xC0100000 #define MSM7X30_CSR_SIZE SZ_4K -#define MSM_DMOV_BASE IOMEM(0xE0002000) -#define MSM_DMOV_PHYS 0xAC400000 -#define MSM_DMOV_SIZE SZ_4K +#define MSM7X30_DMOV_PHYS 0xAC400000 +#define MSM7X30_DMOV_SIZE SZ_4K #define MSM_GPIO1_BASE IOMEM(0xE0003000) #define MSM_GPIO1_PHYS 0xAC001000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index 3c9d9602a318..b251ba63b3e2 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h @@ -45,4 +45,7 @@ #define MSM8960_TMR0_PHYS 0x0208A000 #define MSM8960_TMR0_SIZE SZ_4K +#define MSM8960_DMOV_PHYS 0x18300000 +#define MSM8960_DMOV_SIZE SZ_1M + #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index d4143201999f..fc36b82d41b3 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -42,9 +42,8 @@ #define QSD8X50_CSR_PHYS 0xAC100000 #define QSD8X50_CSR_SIZE SZ_4K -#define MSM_DMOV_BASE IOMEM(0xE0002000) -#define MSM_DMOV_PHYS 0xA9700000 -#define MSM_DMOV_SIZE SZ_4K +#define QSD8X50_DMOV_PHYS 0xA9700000 +#define QSD8X50_DMOV_SIZE SZ_4K #define MSM_GPIO1_BASE IOMEM(0xE0003000) #define MSM_GPIO1_PHYS 0xA9000000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 3b19b8f244b8..87a26c6ed98f 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -56,6 +56,12 @@ #define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) #define MSM_SHARED_RAM_SIZE SZ_1M +#define MSM8X60_DMOV_ADM0_PHYS 0x18320000 +#define MSM8X60_DMOV_ADM0_SIZE SZ_1M + +#define MSM8X60_DMOV_ADM1_PHYS 0x18420000 +#define MSM8X60_DMOV_ADM1_SIZE SZ_1M + #define MSM8X60_TMR_PHYS 0x02000000 #define MSM8X60_TMR_SIZE SZ_4K diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index cec6ed1c91d3..1c86cda45d3b 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -42,7 +42,6 @@ static struct map_desc msm_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_CHIP_DEVICE(CSR, MSM7X00), - MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), MSM_DEVICE(CLK_CTL), @@ -75,7 +74,6 @@ void __init msm_map_common_io(void) static struct map_desc qsd8x50_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_CHIP_DEVICE(CSR, QSD8X50), - MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), MSM_DEVICE(CLK_CTL), @@ -134,7 +132,6 @@ void __init msm_map_msm8960_io(void) static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_CHIP_DEVICE(CSR, MSM7X30), - MSM_DEVICE(DMOV), MSM_DEVICE(GPIO1), MSM_DEVICE(GPIO2), MSM_DEVICE(CLK_CTL), diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 799fbc40e53c..695cdf017c5e 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -109,6 +109,7 @@ config MACH_EUKREA_MBIMX51_BASEBOARD bool select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select LEDS_GPIO_REGISTER help This adds board specific devices that can be found on Eukrea's MBIMX51 evaluation board. @@ -135,6 +136,7 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD prompt "Eukrea MBIMXSD development board" bool select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select LEDS_GPIO_REGISTER help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. @@ -151,6 +153,7 @@ config MX51_EFIKA_COMMON config MACH_MX51_EFIKAMX bool "Support MX51 Genesi Efika MX nettop" + select LEDS_GPIO_REGISTER select MX51_EFIKA_COMMON help Include support for Genesi Efika MX nettop. This includes specific @@ -158,6 +161,7 @@ config MACH_MX51_EFIKAMX config MACH_MX51_EFIKASB bool "Support MX51 Genesi Efika Smartbook" + select LEDS_GPIO_REGISTER select MX51_EFIKA_COMMON help Include support for Genesi Efika Smartbook. This includes specific @@ -176,6 +180,7 @@ config MACH_MX53_EVK select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX + select LEDS_GPIO_REGISTER help Include support for MX53 EVK platform. This includes specific configurations for the board and its peripherals. @@ -199,10 +204,19 @@ config MACH_MX53_LOCO select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_GPIO_KEYS + select LEDS_GPIO_REGISTER help Include support for MX53 LOCO platform. This includes specific configurations for the board and its peripherals. +config MACH_MX53_ARD + bool "Support MX53 ARD platforms" + select SOC_IMX53 + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for MX53 ARD platform. This includes specific + configurations for the board and its peripherals. + endif # ARCH_MX53_SUPPORTED endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 0b9338cec516..df67fefdc6cb 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o +obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index 4efa02ee1639..7c893fa70266 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -43,10 +43,6 @@ #define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25) #define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26) #define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27) -#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) -#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) -#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) -#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO) #define CPUIMX51_QUART_XTAL 14745600 #define CPUIMX51_QUART_REGSHIFT 17 @@ -61,7 +57,7 @@ static struct plat_serial8250_port serial_platform_data[] = { { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), - .irq = CPUIMX51_QUARTA_IRQ, + .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO), .irqflags = IRQF_TRIGGER_HIGH, .uartclk = CPUIMX51_QUART_XTAL, .regshift = CPUIMX51_QUART_REGSHIFT, @@ -69,7 +65,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), - .irq = CPUIMX51_QUARTB_IRQ, + .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO), .irqflags = IRQF_TRIGGER_HIGH, .uartclk = CPUIMX51_QUART_XTAL, .regshift = CPUIMX51_QUART_REGSHIFT, @@ -77,7 +73,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), - .irq = CPUIMX51_QUARTC_IRQ, + .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO), .irqflags = IRQF_TRIGGER_HIGH, .uartclk = CPUIMX51_QUART_XTAL, .regshift = CPUIMX51_QUART_REGSHIFT, @@ -85,7 +81,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), - .irq = CPUIMX51_QUARTD_IRQ, + .irq = irq_to_gpio(CPUIMX51_QUARTD_GPIO), .irqflags = IRQF_TRIGGER_HIGH, .uartclk = CPUIMX51_QUART_XTAL, .regshift = CPUIMX51_QUART_REGSHIFT, @@ -245,6 +241,8 @@ __setup("otg_mode=", eukrea_cpuimx51_otg_mode); */ static void __init eukrea_cpuimx51_init(void) { + imx51_soc_init(); + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads)); diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 5ef25a596143..ff096d587299 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -264,6 +264,8 @@ static struct platform_device *platform_devices[] __initdata = { static void __init eukrea_cpuimx51sd_init(void) { + imx51_soc_init(); + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, ARRAY_SIZE(eukrea_cpuimx51sd_pads)); diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c index 11210e1ae42a..7de25c6712eb 100644 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-mx5/board-mx50_rdp.c @@ -192,6 +192,8 @@ static const struct imxi2c_platform_data i2c_data __initconst = { */ static void __init mx50_rdp_board_init(void) { + imx50_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads, ARRAY_SIZE(mx50_rdp_pads)); diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 63dfbeafbc1e..07a38154da21 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -13,6 +13,7 @@ #include <linux/irq.h> #include <linux/platform_device.h> #include <linux/spi/spi.h> +#include <linux/gpio.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -26,7 +27,7 @@ #include "devices-imx51.h" #include "devices.h" -#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) +#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6)) #define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) static iomux_v3_cfg_t mx51_3ds_pads[] = { @@ -135,6 +136,8 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = { */ static void __init mx51_3ds_init(void) { + imx51_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, ARRAY_SIZE(mx51_3ds_pads)); diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index c7b3fabf50f9..15c600026aee 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -36,11 +36,15 @@ #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) #define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27) -#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5) +#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5) #define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14) #define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) #define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) #define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) +#define BABBAGE_SD1_CD IMX_GPIO_NR(1, 0) +#define BABBAGE_SD1_WP IMX_GPIO_NR(1, 1) +#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6) +#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5) /* USB_CTRL_1 */ #define MX51_USB_CTRL_1_OFFSET 0x10 @@ -110,6 +114,9 @@ static iomux_v3_cfg_t mx51babbage_pads[] = { /* USB HUB reset line*/ MX51_PAD_GPIO1_7__GPIO1_7, + /* USB PHY reset line */ + MX51_PAD_EIM_D21__GPIO2_5, + /* FEC */ MX51_PAD_EIM_EB2__FEC_MDIO, MX51_PAD_EIM_EB3__FEC_RDATA1, @@ -139,6 +146,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = { MX51_PAD_SD1_DATA1__SD1_DATA1, MX51_PAD_SD1_DATA2__SD1_DATA2, MX51_PAD_SD1_DATA3__SD1_DATA3, + MX51_PAD_GPIO1_0__GPIO1_0, + MX51_PAD_GPIO1_1__GPIO1_1, /* SD 2 */ MX51_PAD_SD2_CMD__SD2_CMD, @@ -147,6 +156,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = { MX51_PAD_SD2_DATA1__SD2_DATA1, MX51_PAD_SD2_DATA2__SD2_DATA2, MX51_PAD_SD2_DATA3__SD2_DATA3, + MX51_PAD_GPIO1_6__GPIO1_6, + MX51_PAD_GPIO1_5__GPIO1_5, /* eCSPI1 */ MX51_PAD_CSPI1_MISO__ECSPI1_MISO, @@ -169,34 +180,31 @@ static struct imxi2c_platform_data babbage_hsi2c_data = { .bitrate = 400000, }; +static struct gpio mx51_babbage_usbh1_gpios[] = { + { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" }, + { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" }, +}; + static int gpio_usbh1_active(void) { iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27; - iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5; int ret; /* Set USBH1_STP to GPIO and toggle it */ mxc_iomux_v3_setup_pad(usbh1stp_gpio); - ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp"); + ret = gpio_request_array(mx51_babbage_usbh1_gpios, + ARRAY_SIZE(mx51_babbage_usbh1_gpios)); if (ret) { - pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret); + pr_debug("failed to get USBH1 pins: %d\n", ret); return ret; } - gpio_direction_output(BABBAGE_USBH1_STP, 0); - gpio_set_value(BABBAGE_USBH1_STP, 1); - msleep(100); - gpio_free(BABBAGE_USBH1_STP); - - /* De-assert USB PHY RESETB */ - mxc_iomux_v3_setup_pad(phyreset_gpio); - ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset"); - if (ret) { - pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret); - return ret; - } - gpio_direction_output(BABBAGE_PHY_RESET, 1); + msleep(100); + gpio_set_value(BABBAGE_USBH1_STP, 1); + gpio_set_value(BABBAGE_USB_PHY_RESET, 1); + gpio_free_array(mx51_babbage_usbh1_gpios, + ARRAY_SIZE(mx51_babbage_usbh1_gpios)); return 0; } @@ -331,6 +339,16 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), }; +static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = { + .cd_gpio = BABBAGE_SD1_CD, + .wp_gpio = BABBAGE_SD1_WP, +}; + +static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = { + .cd_gpio = BABBAGE_SD2_CD, + .wp_gpio = BABBAGE_SD2_WP, +}; + /* * Board specific initialization. */ @@ -340,6 +358,8 @@ static void __init mx51_babbage_init(void) iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP); + imx51_soc_init(); + #if defined(CONFIG_CPU_FREQ_IMX) get_cpu_op = mx51_get_cpu_op; #endif @@ -374,8 +394,8 @@ static void __init mx51_babbage_init(void) mxc_iomux_v3_setup_pad(usbh1stp); babbage_usbhub_reset(); - imx51_add_sdhci_esdhc_imx(0, NULL); - imx51_add_sdhci_esdhc_imx(1, NULL); + imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data); + imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data); spi_register_board_info(mx51_babbage_spi_board_info, ARRAY_SIZE(mx51_babbage_spi_board_info)); diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index 6e362315291b..f70700dc0ec1 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -139,7 +139,7 @@ static void __init mx51_efikamx_board_id(void) } } -static struct gpio_led mx51_efikamx_leds[] = { +static struct gpio_led mx51_efikamx_leds[] __initdata = { { .name = "efikamx:green", .default_trigger = "default-on", @@ -157,19 +157,12 @@ static struct gpio_led mx51_efikamx_leds[] = { }, }; -static struct gpio_led_platform_data mx51_efikamx_leds_data = { +static const struct gpio_led_platform_data + mx51_efikamx_leds_data __initconst = { .leds = mx51_efikamx_leds, .num_leds = ARRAY_SIZE(mx51_efikamx_leds), }; -static struct platform_device mx51_efikamx_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &mx51_efikamx_leds_data, - }, -}; - static struct gpio_keys_button mx51_efikamx_powerkey[] = { { .code = KEY_POWER, @@ -236,6 +229,8 @@ late_initcall(mx51_efikamx_power_init); static void __init mx51_efikamx_init(void) { + imx51_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, ARRAY_SIZE(mx51efikamx_pads)); efika_board_common_init(); @@ -248,7 +243,7 @@ static void __init mx51_efikamx_init(void) mx51_efikamx_leds[2].default_trigger = "mmc1"; } - platform_device_register(&mx51_efikamx_leds_device); + gpio_led_register_device(-1, &mx51_efikamx_leds_data); imx_add_gpio_keys(&mx51_efikamx_powerkey_data); if (system_rev == 0x11) { diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c index 474fc6e4c6df..2e4d9d32a87c 100644 --- a/arch/arm/mach-mx5/board-mx51_efikasb.c +++ b/arch/arm/mach-mx5/board-mx51_efikasb.c @@ -132,7 +132,7 @@ static void __init mx51_efikasb_usb(void) mxc_register_device(&mxc_usbh2_device, &usbh2_config); } -static struct gpio_led mx51_efikasb_leds[] = { +static const struct gpio_led mx51_efikasb_leds[] __initconst = { { .name = "efikasb:green", .default_trigger = "default-on", @@ -146,19 +146,12 @@ static struct gpio_led mx51_efikasb_leds[] = { }, }; -static struct gpio_led_platform_data mx51_efikasb_leds_data = { +static const struct gpio_led_platform_data + mx51_efikasb_leds_data __initconst = { .leds = mx51_efikasb_leds, .num_leds = ARRAY_SIZE(mx51_efikasb_leds), }; -static struct platform_device mx51_efikasb_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &mx51_efikasb_leds_data, - }, -}; - static struct gpio_keys_button mx51_efikasb_keys[] = { { .code = KEY_POWER, @@ -248,6 +241,8 @@ static void __init mx51_efikasb_board_id(void) static void __init efikasb_board_init(void) { + imx51_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads, ARRAY_SIZE(mx51efikasb_pads)); efika_board_common_init(); @@ -256,9 +251,8 @@ static void __init efikasb_board_init(void) mx51_efikasb_usb(); imx51_add_sdhci_esdhc_imx(1, NULL); - platform_device_register(&mx51_efikasb_leds_device); + gpio_led_register_device(-1, &mx51_efikasb_leds_data); imx_add_gpio_keys(&mx51_efikasb_keys_data); - } static void __init mx51_efikasb_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c new file mode 100644 index 000000000000..7e1859ba5f83 --- /dev/null +++ b/arch/arm/mach-mx5/board-mx53_ard.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/smsc911x.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/iomux-mx53.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "crm_regs.h" +#include "devices-imx53.h" + +#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) + +static iomux_v3_cfg_t mx53_ard_pads[] = { + /* UART1 */ + MX53_PAD_PATA_DIOW__UART1_TXD_MUX, + MX53_PAD_PATA_DMACK__UART1_RXD_MUX, + /* WEIM for CS1 */ + MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */ + MX53_PAD_EIM_D16__EMI_WEIM_D_16, + MX53_PAD_EIM_D17__EMI_WEIM_D_17, + MX53_PAD_EIM_D18__EMI_WEIM_D_18, + MX53_PAD_EIM_D19__EMI_WEIM_D_19, + MX53_PAD_EIM_D20__EMI_WEIM_D_20, + MX53_PAD_EIM_D21__EMI_WEIM_D_21, + MX53_PAD_EIM_D22__EMI_WEIM_D_22, + MX53_PAD_EIM_D23__EMI_WEIM_D_23, + MX53_PAD_EIM_D24__EMI_WEIM_D_24, + MX53_PAD_EIM_D25__EMI_WEIM_D_25, + MX53_PAD_EIM_D26__EMI_WEIM_D_26, + MX53_PAD_EIM_D27__EMI_WEIM_D_27, + MX53_PAD_EIM_D28__EMI_WEIM_D_28, + MX53_PAD_EIM_D29__EMI_WEIM_D_29, + MX53_PAD_EIM_D30__EMI_WEIM_D_30, + MX53_PAD_EIM_D31__EMI_WEIM_D_31, + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, + MX53_PAD_EIM_OE__EMI_WEIM_OE, + MX53_PAD_EIM_RW__EMI_WEIM_RW, + MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, +}; + +static struct resource ard_smsc911x_resources[] = { + { + .start = MX53_CS1_64MB_BASE_ADDR, + .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = gpio_to_irq(ARD_ETHERNET_INT_B), + .end = gpio_to_irq(ARD_ETHERNET_INT_B), + .flags = IORESOURCE_IRQ, + }, +}; + +struct smsc911x_platform_config ard_smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device ard_smsc_lan9220_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(ard_smsc911x_resources), + .resource = ard_smsc911x_resources, + .dev = { + .platform_data = &ard_smsc911x_config, + }, +}; + +static void __init mx53_ard_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads, + ARRAY_SIZE(mx53_ard_pads)); + + gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); + gpio_direction_input(ARD_ETHERNET_INT_B); +} + + /* Config CS1 settings for ethernet controller */ +static int weim_cs_config(void) +{ + u32 reg; + void __iomem *weim_base, *iomuxc_base; + + weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K); + if (!weim_base) + return -ENOMEM; + + iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); + if (!iomuxc_base) + return -ENOMEM; + + /* CS1 timings for LAN9220 */ + writel(0x20001, (weim_base + 0x18)); + writel(0x0, (weim_base + 0x1C)); + writel(0x16000202, (weim_base + 0x20)); + writel(0x00000002, (weim_base + 0x24)); + writel(0x16002082, (weim_base + 0x28)); + writel(0x00000000, (weim_base + 0x2C)); + writel(0x00000000, (weim_base + 0x90)); + + /* specify 64 MB on CS1 and CS0 on GPR1 */ + reg = readl(iomuxc_base + 0x4); + reg &= ~0x3F; + reg |= 0x1B; + writel(reg, (iomuxc_base + 0x4)); + + iounmap(iomuxc_base); + iounmap(weim_base); + + return 0; +} + +static struct platform_device *devices[] __initdata = { + &ard_smsc_lan9220_device, +}; + +static void __init mx53_ard_board_init(void) +{ + imx53_soc_init(); + imx53_add_imx_uart(0, NULL); + + mx53_ard_io_init(); + weim_cs_config(); + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init mx53_ard_timer_init(void) +{ + mx53_clocks_init(32768, 24000000, 22579200, 0); +} + +static struct sys_timer mx53_ard_timer = { + .init = mx53_ard_timer_init, +}; + +MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") + .map_io = mx53_map_io, + .init_early = imx53_init_early, + .init_irq = mx53_init_irq, + .timer = &mx53_ard_timer, + .init_machine = mx53_ard_board_init, +MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index f87d571882c6..1b417b06b736 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -35,6 +35,7 @@ #define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) +#define MX53EVK_LED IMX_GPIO_NR(7, 7) #include "crm_regs.h" #include "devices-imx53.h" @@ -58,12 +59,27 @@ static iomux_v3_cfg_t mx53_evk_pads[] = { /* ecspi chip select lines */ MX53_PAD_EIM_EB2__GPIO2_30, MX53_PAD_EIM_D19__GPIO3_19, + /* LED */ + MX53_PAD_PATA_DA_1__GPIO7_7, }; static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static const struct gpio_led mx53evk_leds[] __initconst = { + { + .name = "green", + .default_trigger = "heartbeat", + .gpio = MX53EVK_LED, + }, +}; + +static const struct gpio_led_platform_data mx53evk_leds_data __initconst = { + .leds = mx53evk_leds, + .num_leds = ARRAY_SIZE(mx53evk_leds), +}; + static inline void mx53_evk_init_uart(void) { imx53_add_imx_uart(0, NULL); @@ -117,6 +133,8 @@ static const struct spi_imx_master mx53_evk_spi_data __initconst = { static void __init mx53_evk_board_init(void) { + imx53_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, ARRAY_SIZE(mx53_evk_pads)); mx53_evk_init_uart(); @@ -133,6 +151,7 @@ static void __init mx53_evk_board_init(void) ARRAY_SIZE(mx53_evk_spi_board_info)); imx53_add_ecspi(0, &mx53_evk_spi_data); imx53_add_imx2_wdt(0, NULL); + gpio_led_register_device(-1, &mx53evk_leds_data); } static void __init mx53_evk_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 1b947e8c9c0c..54be525e2bd7 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -38,6 +38,10 @@ #define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) #define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define LOCO_LED IMX_GPIO_NR(7, 7) +#define LOCO_SD3_CD IMX_GPIO_NR(3, 11) +#define LOCO_SD3_WP IMX_GPIO_NR(3, 12) +#define LOCO_SD1_CD IMX_GPIO_NR(3, 13) static iomux_v3_cfg_t mx53_loco_pads[] = { /* FEC */ @@ -70,6 +74,8 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { MX53_PAD_SD1_DATA1__ESDHC1_DAT1, MX53_PAD_SD1_DATA2__ESDHC1_DAT2, MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + /* SD1_CD */ + MX53_PAD_EIM_DA13__GPIO3_13, /* SD3 */ MX53_PAD_PATA_DATA8__ESDHC3_DAT0, MX53_PAD_PATA_DATA9__ESDHC3_DAT1, @@ -163,7 +169,7 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { MX53_PAD_GPIO_7__SPDIF_PLOCK, MX53_PAD_GPIO_17__SPDIF_OUT1, /* GPIO */ - MX53_PAD_PATA_DA_1__GPIO7_7, + MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */ MX53_PAD_PATA_DA_2__GPIO7_8, MX53_PAD_PATA_DATA5__GPIO2_5, MX53_PAD_PATA_DATA6__GPIO2_6, @@ -202,6 +208,15 @@ static const struct gpio_keys_platform_data loco_button_data __initconst = { .nbuttons = ARRAY_SIZE(loco_buttons), }; +static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = { + .cd_gpio = LOCO_SD1_CD, +}; + +static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = { + .cd_gpio = LOCO_SD3_CD, + .wp_gpio = LOCO_SD3_WP, +}; + static inline void mx53_loco_fec_reset(void) { int ret; @@ -225,8 +240,23 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { .bitrate = 100000, }; +static const struct gpio_led mx53loco_leds[] __initconst = { + { + .name = "green", + .default_trigger = "heartbeat", + .gpio = LOCO_LED, + }, +}; + +static const struct gpio_led_platform_data mx53loco_leds_data __initconst = { + .leds = mx53loco_leds, + .num_leds = ARRAY_SIZE(mx53loco_leds), +}; + static void __init mx53_loco_board_init(void) { + imx53_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, ARRAY_SIZE(mx53_loco_pads)); imx53_add_imx_uart(0, NULL); @@ -235,9 +265,10 @@ static void __init mx53_loco_board_init(void) imx53_add_imx2_wdt(0, NULL); imx53_add_imx_i2c(0, &mx53_loco_i2c_data); imx53_add_imx_i2c(1, &mx53_loco_i2c_data); - imx53_add_sdhci_esdhc_imx(0, NULL); - imx53_add_sdhci_esdhc_imx(2, NULL); + imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); + imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); imx_add_gpio_keys(&loco_button_data); + gpio_led_register_device(-1, &mx53loco_leds_data); } static void __init mx53_loco_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 817c08938f55..bc02894eafef 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -113,6 +113,8 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { static void __init mx53_smd_board_init(void) { + imx53_soc_init(); + mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, ARRAY_SIZE(mx53_smd_pads)); mx53_smd_init_uart(); diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 153ada53e575..371ca8c8414c 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -12,7 +12,6 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> -#include <linux/gpio.h> #include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/irqs.h> @@ -119,66 +118,3 @@ struct platform_device mxc_usbh2_device = { .coherent_dma_mask = DMA_BIT_MASK(32), }, }; - -static struct mxc_gpio_port mxc_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR), - .irq = MX51_MXC_INT_GPIO1_LOW, - .irq_high = MX51_MXC_INT_GPIO1_HIGH, - .virtual_irq_start = MXC_GPIO_IRQ_START - }, - { - .chip.label = "gpio-1", - .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR), - .irq = MX51_MXC_INT_GPIO2_LOW, - .irq_high = MX51_MXC_INT_GPIO2_HIGH, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 - }, - { - .chip.label = "gpio-2", - .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR), - .irq = MX51_MXC_INT_GPIO3_LOW, - .irq_high = MX51_MXC_INT_GPIO3_HIGH, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 - }, - { - .chip.label = "gpio-3", - .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR), - .irq = MX51_MXC_INT_GPIO4_LOW, - .irq_high = MX51_MXC_INT_GPIO4_HIGH, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 - }, - { - .chip.label = "gpio-4", - .base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR), - .irq = MX53_INT_GPIO5_LOW, - .irq_high = MX53_INT_GPIO5_HIGH, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 - }, - { - .chip.label = "gpio-5", - .base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR), - .irq = MX53_INT_GPIO6_LOW, - .irq_high = MX53_INT_GPIO6_HIGH, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5 - }, - { - .chip.label = "gpio-6", - .base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR), - .irq = MX53_INT_GPIO7_LOW, - .irq_high = MX53_INT_GPIO7_HIGH, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6 - }, -}; - -int __init imx51_register_gpios(void) -{ - return mxc_gpio_init(mxc_gpio_ports, 4); -} - -int __init imx53_register_gpios(void) -{ - return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); -} - diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index 97292d20f1f3..bbf4564bd050 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -31,13 +31,12 @@ #include "devices.h" #define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30) -#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO) #define MBIMX51_LED0 IMX_GPIO_NR(3, 5) #define MBIMX51_LED1 IMX_GPIO_NR(3, 6) #define MBIMX51_LED2 IMX_GPIO_NR(3, 7) #define MBIMX51_LED3 IMX_GPIO_NR(3, 8) -static struct gpio_led mbimx51_leds[] = { +static const struct gpio_led mbimx51_leds[] __initconst = { { .name = "led0", .default_trigger = "heartbeat", @@ -64,23 +63,11 @@ static struct gpio_led mbimx51_leds[] = { }, }; -static struct gpio_led_platform_data mbimx51_leds_info = { +static const struct gpio_led_platform_data mbimx51_leds_info __initconst = { .leds = mbimx51_leds, .num_leds = ARRAY_SIZE(mbimx51_leds), }; -static struct platform_device mbimx51_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &mbimx51_leds_info, - }, -}; - -static struct platform_device *devices[] __initdata = { - &mbimx51_leds_gpio, -}; - static iomux_v3_cfg_t mbimx51_pads[] = { /* UART2 */ MX51_PAD_UART2_RXD__UART2_RXD, @@ -173,7 +160,7 @@ struct tsc2007_platform_data tsc2007_data = { static struct i2c_board_info mbimx51_i2c_devices[] = { { I2C_BOARD_INFO("tsc2007", 0x49), - .irq = MBIMX51_TSC2007_IRQ, + .irq = gpio_to_irq(MBIMX51_TSC2007_GPIO), .platform_data = &tsc2007_data, }, { I2C_BOARD_INFO("tlv320aic23", 0x1a), @@ -204,13 +191,14 @@ void __init eukrea_mbimx51_baseboard_init(void) gpio_direction_output(MBIMX51_LED3, 1); gpio_free(MBIMX51_LED3); - platform_add_devices(devices, ARRAY_SIZE(devices)); + gpio_led_register_device(-1, &mbimx51_leds_info); imx51_add_imx_keypad(&mbimx51_map_data); gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); gpio_direction_input(MBIMX51_TSC2007_GPIO); - irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); + irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO), + IRQF_TRIGGER_FALLING); i2c_register_board_info(1, mbimx51_i2c_devices, ARRAY_SIZE(mbimx51_i2c_devices)); diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index 31c871ec46a6..261923997643 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c @@ -74,7 +74,7 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { #define GPIO_LED1 IMX_GPIO_NR(3, 30) #define GPIO_SWITCH1 IMX_GPIO_NR(3, 31) -static struct gpio_led eukrea_mbimxsd_leds[] = { +static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = { { .name = "led1", .default_trigger = "heartbeat", @@ -83,19 +83,12 @@ static struct gpio_led eukrea_mbimxsd_leds[] = { }, }; -static struct gpio_led_platform_data eukrea_mbimxsd_led_info = { +static const struct gpio_led_platform_data + eukrea_mbimxsd_led_info __initconst = { .leds = eukrea_mbimxsd_leds, .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), }; -static struct platform_device eukrea_mbimxsd_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &eukrea_mbimxsd_led_info, - }, -}; - static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { { .gpio = GPIO_SWITCH1, @@ -112,10 +105,6 @@ static const struct gpio_keys_platform_data .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), }; -static struct platform_device *platform_devices[] __initdata = { - &eukrea_mbimxsd_leds_gpio, -}; - static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -154,6 +143,6 @@ void __init eukrea_mbimxsd51_baseboard_init(void) i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); imx_add_gpio_keys(&eukrea_mbimxsd_button_data); } diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c index b9c363b514a9..28c3f60f734f 100644 --- a/arch/arm/mach-mx5/mm-mx50.c +++ b/arch/arm/mach-mx5/mm-mx50.c @@ -26,7 +26,6 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/iomux-v3.h> -#include <mach/gpio.h> #include <mach/irqs.h> /* @@ -56,17 +55,17 @@ void __init imx50_init_early(void) mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); } -static struct mxc_gpio_port imx50_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), -}; - void __init mx50_init_irq(void) { tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); - mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports)); +} + +void __init imx50_soc_init(void) +{ + mxc_register_gpio(0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); + mxc_register_gpio(1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); + mxc_register_gpio(2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); + mxc_register_gpio(3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); + mxc_register_gpio(4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); + mxc_register_gpio(5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); } diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index ff557301b42b..800bb8b21081 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -69,8 +69,6 @@ void __init imx53_init_early(void) mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); } -int imx51_register_gpios(void); - void __init mx51_init_irq(void) { unsigned long tzic_addr; @@ -86,11 +84,8 @@ void __init mx51_init_irq(void) panic("unable to map TZIC interrupt controller\n"); tzic_init_irq(tzic_virt); - imx51_register_gpios(); } -int imx53_register_gpios(void); - void __init mx53_init_irq(void) { unsigned long tzic_addr; @@ -103,5 +98,23 @@ void __init mx53_init_irq(void) panic("unable to map TZIC interrupt controller\n"); tzic_init_irq(tzic_virt); - imx53_register_gpios(); +} + +void __init imx51_soc_init(void) +{ + mxc_register_gpio(0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH); + mxc_register_gpio(1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH); + mxc_register_gpio(2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH); + mxc_register_gpio(3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH); +} + +void __init imx53_soc_init(void) +{ + mxc_register_gpio(0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); + mxc_register_gpio(1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); + mxc_register_gpio(2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); + mxc_register_gpio(3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); + mxc_register_gpio(4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); + mxc_register_gpio(5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); + mxc_register_gpio(6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); } diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index f114960622e0..1d3985f37858 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -41,6 +41,7 @@ config MACH_MX23EVK config MACH_MX28EVK bool "Support MX28EVK Platform" select SOC_IMX28 + select LEDS_GPIO_REGISTER select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_AUART select MXS_HAVE_PLATFORM_FEC @@ -55,6 +56,7 @@ config MACH_MX28EVK config MODULE_TX28 bool select SOC_IMX28 + select LEDS_GPIO_REGISTER select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_AUART select MXS_HAVE_PLATFORM_FEC diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 58e892376bf2..6c38262a3aaa 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -1,5 +1,5 @@ # Common support -obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o +obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o obj-$(CONFIG_MXS_OCOTP) += ocotp.o obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c index cfdb6b284702..fe3e847930c9 100644 --- a/arch/arm/mach-mxs/devices.c +++ b/arch/arm/mach-mxs/devices.c @@ -88,3 +88,14 @@ int __init mxs_add_amba_device(const struct amba_device *dev) return amba_device_register(adev, &iomem_resource); } + +struct device mxs_apbh_bus = { + .init_name = "mxs_apbh", + .parent = &platform_bus, +}; + +static int __init mxs_device_init(void) +{ + return device_register(&mxs_apbh_bus); +} +core_initcall(mxs_device_init); diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 324f2824d38d..351915c683ff 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -6,4 +6,5 @@ obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o +obj-y += platform-gpio-mxs.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c new file mode 100644 index 000000000000..ed0885e414e0 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c @@ -0,0 +1,53 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/compiler.h> +#include <linux/err.h> +#include <linux/init.h> + +#include <mach/mx23.h> +#include <mach/mx28.h> +#include <mach/devices-common.h> + +struct platform_device *__init mxs_add_gpio( + int id, resource_size_t iobase, int irq) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return platform_device_register_resndata(&mxs_apbh_bus, + "gpio-mxs", id, res, ARRAY_SIZE(res), NULL, 0); +} + +static int __init mxs_add_mxs_gpio(void) +{ + if (cpu_is_mx23()) { + mxs_add_gpio(0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0); + mxs_add_gpio(1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1); + mxs_add_gpio(2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2); + } + + if (cpu_is_mx28()) { + mxs_add_gpio(0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0); + mxs_add_gpio(1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1); + mxs_add_gpio(2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2); + mxs_add_gpio(3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3); + mxs_add_gpio(4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4); + } + + return 0; +} +postcore_initcall(mxs_add_mxs_gpio); diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c deleted file mode 100644 index 2c950fef71a8..000000000000 --- a/arch/arm/mach-mxs/gpio.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * Based on code from Freescale, - * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <asm-generic/bug.h> - -#include "gpio.h" - -static struct mxs_gpio_port *mxs_gpio_ports; -static int gpio_table_size; - -#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10) -#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10) -#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10) -#define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10) -#define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10) -#define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10) -#define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10) -#define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10) - -#define GPIO_INT_FALL_EDGE 0x0 -#define GPIO_INT_LOW_LEV 0x1 -#define GPIO_INT_RISE_EDGE 0x2 -#define GPIO_INT_HIGH_LEV 0x3 -#define GPIO_INT_LEV_MASK (1 << 0) -#define GPIO_INT_POL_MASK (1 << 1) - -/* Note: This driver assumes 32 GPIOs are handled in one register */ - -static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index) -{ - __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id)); -} - -static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index, - int enable) -{ - if (enable) { - __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id)); - __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id)); - } else { - __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id)); - } -} - -static void mxs_gpio_ack_irq(struct irq_data *d) -{ - u32 gpio = irq_to_gpio(d->irq); - clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f); -} - -static void mxs_gpio_mask_irq(struct irq_data *d) -{ - u32 gpio = irq_to_gpio(d->irq); - set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0); -} - -static void mxs_gpio_unmask_irq(struct irq_data *d) -{ - u32 gpio = irq_to_gpio(d->irq); - set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1); -} - -static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset); - -static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) -{ - u32 gpio = irq_to_gpio(d->irq); - u32 pin_mask = 1 << (gpio & 31); - struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; - void __iomem *pin_addr; - int edge; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - edge = GPIO_INT_RISE_EDGE; - break; - case IRQ_TYPE_EDGE_FALLING: - edge = GPIO_INT_FALL_EDGE; - break; - case IRQ_TYPE_LEVEL_LOW: - edge = GPIO_INT_LOW_LEV; - break; - case IRQ_TYPE_LEVEL_HIGH: - edge = GPIO_INT_HIGH_LEV; - break; - default: - return -EINVAL; - } - - /* set level or edge */ - pin_addr = port->base + PINCTRL_IRQLEV(port->id); - if (edge & GPIO_INT_LEV_MASK) - __mxs_setl(pin_mask, pin_addr); - else - __mxs_clrl(pin_mask, pin_addr); - - /* set polarity */ - pin_addr = port->base + PINCTRL_IRQPOL(port->id); - if (edge & GPIO_INT_POL_MASK) - __mxs_setl(pin_mask, pin_addr); - else - __mxs_clrl(pin_mask, pin_addr); - - clear_gpio_irqstatus(port, gpio & 0x1f); - - return 0; -} - -/* MXS has one interrupt *per* gpio port */ -static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) -{ - u32 irq_stat; - struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq); - u32 gpio_irq_no_base = port->virtual_irq_start; - - desc->irq_data.chip->irq_ack(&desc->irq_data); - - irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) & - __raw_readl(port->base + PINCTRL_IRQEN(port->id)); - - while (irq_stat != 0) { - int irqoffset = fls(irq_stat) - 1; - generic_handle_irq(gpio_irq_no_base + irqoffset); - irq_stat &= ~(1 << irqoffset); - } -} - -/* - * Set interrupt number "irq" in the GPIO as a wake-up source. - * While system is running, all registered GPIO interrupts need to have - * wake-up enabled. When system is suspended, only selected GPIO interrupts - * need to have wake-up enabled. - * @param irq interrupt source number - * @param enable enable as wake-up if equal to non-zero - * @return This function returns 0 on success. - */ -static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable) -{ - u32 gpio = irq_to_gpio(d->irq); - u32 gpio_idx = gpio & 0x1f; - struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; - - if (enable) { - if (port->irq_high && (gpio_idx >= 16)) - enable_irq_wake(port->irq_high); - else - enable_irq_wake(port->irq); - } else { - if (port->irq_high && (gpio_idx >= 16)) - disable_irq_wake(port->irq_high); - else - disable_irq_wake(port->irq); - } - - return 0; -} - -static struct irq_chip gpio_irq_chip = { - .name = "mxs gpio", - .irq_ack = mxs_gpio_ack_irq, - .irq_mask = mxs_gpio_mask_irq, - .irq_unmask = mxs_gpio_unmask_irq, - .irq_set_type = mxs_gpio_set_irq_type, - .irq_set_wake = mxs_gpio_set_wake_irq, -}; - -static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset, - int dir) -{ - struct mxs_gpio_port *port = - container_of(chip, struct mxs_gpio_port, chip); - void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id); - - if (dir) - __mxs_setl(1 << offset, pin_addr); - else - __mxs_clrl(1 << offset, pin_addr); -} - -static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct mxs_gpio_port *port = - container_of(chip, struct mxs_gpio_port, chip); - - return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1; -} - -static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct mxs_gpio_port *port = - container_of(chip, struct mxs_gpio_port, chip); - void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id); - - if (value) - __mxs_setl(1 << offset, pin_addr); - else - __mxs_clrl(1 << offset, pin_addr); -} - -static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct mxs_gpio_port *port = - container_of(chip, struct mxs_gpio_port, chip); - - return port->virtual_irq_start + offset; -} - -static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - mxs_set_gpio_direction(chip, offset, 0); - return 0; -} - -static int mxs_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - mxs_gpio_set(chip, offset, value); - mxs_set_gpio_direction(chip, offset, 1); - return 0; -} - -int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) -{ - int i, j; - - /* save for local usage */ - mxs_gpio_ports = port; - gpio_table_size = cnt; - - pr_info("MXS GPIO hardware\n"); - - for (i = 0; i < cnt; i++) { - /* disable the interrupt and clear the status */ - __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i)); - __raw_writel(0, port[i].base + PINCTRL_IRQEN(i)); - - /* clear address has to be used to clear IRQSTAT bits */ - __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i)); - - for (j = port[i].virtual_irq_start; - j < port[i].virtual_irq_start + 32; j++) { - irq_set_chip_and_handler(j, &gpio_irq_chip, - handle_level_irq); - set_irq_flags(j, IRQF_VALID); - } - - /* setup one handler for each entry */ - irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler); - irq_set_handler_data(port[i].irq, &port[i]); - - /* register gpio chip */ - port[i].chip.direction_input = mxs_gpio_direction_input; - port[i].chip.direction_output = mxs_gpio_direction_output; - port[i].chip.get = mxs_gpio_get; - port[i].chip.set = mxs_gpio_set; - port[i].chip.to_irq = mxs_gpio_to_irq; - port[i].chip.base = i * 32; - port[i].chip.ngpio = 32; - - /* its a serious configuration bug when it fails */ - BUG_ON(gpiochip_add(&port[i].chip) < 0); - } - - return 0; -} - -#define MX23_GPIO_BASE MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR) -#define MX28_GPIO_BASE MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR) - -#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id) \ - { \ - .chip.label = "gpio-" #_id, \ - .id = _id, \ - .irq = _irq, \ - .base = _base, \ - .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ - } - -#ifdef CONFIG_SOC_IMX23 -static struct mxs_gpio_port mx23_gpio_ports[] = { - DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0), - DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1), - DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2), -}; - -int __init mx23_register_gpios(void) -{ - return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports)); -} -#endif - -#ifdef CONFIG_SOC_IMX28 -static struct mxs_gpio_port mx28_gpio_ports[] = { - DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0), - DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1), - DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2), - DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3), - DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4), -}; - -int __init mx28_register_gpios(void) -{ - return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports)); -} -#endif diff --git a/arch/arm/mach-mxs/gpio.h b/arch/arm/mach-mxs/gpio.h deleted file mode 100644 index 005bb06630b1..000000000000 --- a/arch/arm/mach-mxs/gpio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MXS_GPIO_H__ -#define __MXS_GPIO_H__ - -struct mxs_gpio_port { - void __iomem *base; - int id; - int irq; - int irq_high; - int virtual_irq_start; - struct gpio_chip chip; -}; - -int mxs_gpio_init(struct mxs_gpio_port*, int); - -#endif /* __MXS_GPIO_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index 7a37469ed5bf..812d7a813a78 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -11,6 +11,8 @@ #include <linux/init.h> #include <linux/amba/bus.h> +extern struct device mxs_apbh_bus; + struct platform_device *mxs_add_platform_device_dmamask( const char *name, int id, const struct resource *res, unsigned int num_resources, diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index eacdc6b0e70a..eaaf6ff28990 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -15,6 +15,7 @@ #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/gpio.h> +#include <linux/leds.h> #include <linux/irq.h> #include <linux/clk.h> @@ -26,10 +27,10 @@ #include <mach/iomux-mx28.h> #include "devices-mx28.h" -#include "gpio.h" #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) +#define MX28EVK_GPIO_LED MXS_GPIO_NR(3, 5) #define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) @@ -179,6 +180,23 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { /* slot power enable */ MX28_PAD_PWM4__GPIO_3_29 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + + /* led */ + MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL, +}; + +/* led */ +static const struct gpio_led mx28evk_leds[] __initconst = { + { + .name = "GPIO-LED", + .default_trigger = "heartbeat", + .gpio = MX28EVK_GPIO_LED, + }, +}; + +static const struct gpio_led_platform_data mx28evk_led_data __initconst = { + .leds = mx28evk_leds, + .num_leds = ARRAY_SIZE(mx28evk_leds), }; /* fec */ @@ -386,6 +404,8 @@ static void __init mx28evk_init(void) if (ret) pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); + + gpio_led_register_device(0, &mx28evk_led_data); } static void __init mx28evk_timer_init(void) diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c index b65e3719cbc4..fff6b17f0183 100644 --- a/arch/arm/mach-mxs/mach-tx28.c +++ b/arch/arm/mach-mxs/mach-tx28.c @@ -117,7 +117,7 @@ static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = { (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; -static struct gpio_led tx28_stk5v3_leds[] = { +static const struct gpio_led tx28_stk5v3_leds[] __initconst = { { .name = "GPIO-LED", .default_trigger = "heartbeat", @@ -159,8 +159,7 @@ static void __init tx28_stk5v3_init(void) /* spi via ssp will be added when available */ spi_register_board_info(tx28_spi_board_info, ARRAY_SIZE(tx28_spi_board_info)); - mxs_add_platform_device("leds-gpio", 0, NULL, 0, - &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data)); + gpio_led_register_device(0, &tx28_stk5v3_led_data); mx28_add_mxs_i2c(0); i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c index 5148cd64a6b7..1b2345ac1a87 100644 --- a/arch/arm/mach-mxs/mm-mx23.c +++ b/arch/arm/mach-mxs/mm-mx23.c @@ -41,5 +41,4 @@ void __init mx23_map_io(void) void __init mx23_init_irq(void) { icoll_init_irq(); - mx23_register_gpios(); } diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c index 7e4cea32ebc6..b6e18ddb92c0 100644 --- a/arch/arm/mach-mxs/mm-mx28.c +++ b/arch/arm/mach-mxs/mm-mx28.c @@ -41,5 +41,4 @@ void __init mx28_map_io(void) void __init mx28_init_irq(void) { icoll_init_irq(); - mx28_register_gpios(); } diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c index 65157a35dbba..54add60f94c9 100644 --- a/arch/arm/mach-mxs/ocotp.c +++ b/arch/arm/mach-mxs/ocotp.c @@ -16,6 +16,8 @@ #include <linux/err.h> #include <linux/mutex.h> +#include <asm/processor.h> /* for cpu_relax() */ + #include <mach/mxs.h> #define OCOTP_WORD_OFFSET 0x20 diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index af98117043d2..5b114d1558c8 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -4,14 +4,14 @@ # Common support obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o -obj-y += clock.o clock_data.o opp_data.o reset.o +obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # Power Management -obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o +obj-$(CONFIG_PM) += pm.o sleep.o # DSP obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c index fe31d933f0ed..334fb8871bc3 100644 --- a/arch/arm/mach-omap1/pm_bus.c +++ b/arch/arm/mach-omap1/pm_bus.c @@ -56,9 +56,13 @@ static struct dev_power_domain default_power_domain = { USE_PLATFORM_PM_SLEEP_OPS }, }; +#define OMAP1_PWR_DOMAIN (&default_power_domain) +#else +#define OMAP1_PWR_DOMAIN NULL +#endif /* CONFIG_PM_RUNTIME */ static struct pm_clk_notifier_block platform_bus_notifier = { - .pwr_domain = &default_power_domain, + .pwr_domain = OMAP1_PWR_DOMAIN, .con_ids = { "ick", "fck", NULL, }, }; @@ -72,4 +76,4 @@ static int __init omap1_pm_runtime_init(void) return 0; } core_initcall(omap1_pm_runtime_init); -#endif /* CONFIG_PM_RUNTIME */ + diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 2a0bb4818cae..23f71d40883e 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -84,7 +84,8 @@ static struct mtd_partition omap3pandora_nand_partitions[] = { static struct omap_nand_platform_data pandora_nand_data = { .cs = 0, - .devsize = 1, /* '0' for 8-bit, '1' for 16-bit device */ + .devsize = NAND_BUSWIDTH_16, + .xfer_type = NAND_OMAP_PREFETCH_DMA, .parts = omap3pandora_nand_partitions, .nr_parts = ARRAY_SIZE(omap3pandora_nand_partitions), }; diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index a5a83b358ddd..e01da45c0537 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -189,7 +189,7 @@ static struct dentry *pm_dbg_dir; static int pm_dbg_init_done; -static int __init pm_dbg_init(void); +static int pm_dbg_init(void); enum { DEBUG_FILE_COUNTERS = 0, @@ -595,7 +595,7 @@ static int option_set(void *data, u64 val) DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n"); -static int __init pm_dbg_init(void) +static int pm_dbg_init(void) { int i; struct dentry *d; diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 6f5368899d84..cd392934d51b 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -33,11 +33,17 @@ ENTRY(pxa3xx_cpu_suspend) #ifndef CONFIG_IWMMXT mra r2, r3, acc0 #endif - stmfd sp!, {r2 - r12, lr} @ save registers on stack + stmfd sp!, {r2, r3, lr} @ save registers on stack mov r1, r0 - ldr r3, =pxa_cpu_resume @ resume function + adr r3, BSYM(pxa3xx_finish_suspend) bl cpu_suspend + ldmfd sp!, {r2, r3, lr} +#ifndef CONFIG_IWMMXT + mar acc0, r2, r3 +#endif + mov pc, lr +pxa3xx_finish_suspend: mov r0, #0x06 @ S2D3C4 mode mcr p14, 0, r0, c7, c0, 0 @ enter sleep @@ -58,16 +64,22 @@ ENTRY(pxa27x_cpu_suspend) #ifndef CONFIG_IWMMXT mra r2, r3, acc0 #endif - stmfd sp!, {r2 - r12, lr} @ save registers on stack - mov r4, r0 @ save sleep mode - ldr r3, =pxa_cpu_resume @ resume function + stmfd sp!, {r2, r3, lr} @ save registers on stack + mov r2, r0 @ save sleep mode + adr r3, BSYM(pxa27x_finish_suspend) bl cpu_suspend + ldmfd sp!, {r2, r3, lr} +#ifndef CONFIG_IWMMXT + mar acc0, r2, r3 +#endif + mov pc, lr +pxa27x_finish_suspend: @ Put the processor to sleep @ (also workaround for sighting 28071) @ prepare value for sleep mode - mov r1, r4 @ sleep mode + mov r1, r0 @ sleep mode @ prepare pointer to physical address 0 (virtual mapping in generic.c) mov r2, #UNCACHED_PHYS_0 @@ -108,12 +120,13 @@ ENTRY(pxa27x_cpu_suspend) */ ENTRY(pxa25x_cpu_suspend) - stmfd sp!, {r2 - r12, lr} @ save registers on stack - mov r4, r0 @ save sleep mode - ldr r3, =pxa_cpu_resume @ resume function - bl cpu_suspend + mov r2, r0 @ save sleep mode + adr r3, BSYM(pxa25x_finish_suspend) + b cpu_suspend + +pxa25x_finish_suspend: @ prepare value for sleep mode - mov r1, r4 @ sleep mode + mov r1, r0 @ sleep mode @ prepare pointer to physical address 0 (virtual mapping in generic.c) mov r2, #UNCACHED_PHYS_0 @@ -195,16 +208,3 @@ pxa_cpu_do_suspend: mcr p14, 0, r1, c7, c0, 0 @ PWRMODE 20: b 20b @ loop waiting for sleep - -/* - * pxa_cpu_resume() - * - * entry point from bootloader into kernel during resume - */ - .align 5 -pxa_cpu_resume: - ldmfd sp!, {r2, r3} -#ifndef CONFIG_IWMMXT - mar acc0, r2, r3 -#endif - ldmfd sp!, {r4 - r12, pc} @ return to caller diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 7fe74067d85f..094279aefe9c 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/delay.h> +#include <linux/gpio.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/apm-emulation.h> diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h index 70a83b209e25..45eea5210c87 100644 --- a/arch/arm/mach-s3c2410/include/mach/pm-core.h +++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h @@ -62,3 +62,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save) { } + +static inline void s3c_pm_restored_gpios(void) { } +static inline void s3c_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index 0c0505b025cb..140711db6c89 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c @@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable) static struct clk clk_erefclk = { .name = "erefclk", - .id = -1, }; static struct clk clk_urefclk = { .name = "urefclk", - .id = -1, }; static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) @@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) static struct clk clk_usysclk = { .name = "usysclk", - .id = -1, .parent = &clk_xtal, .ops = &(struct clk_ops) { .set_parent = s3c2412_setparent_usysclk, @@ -132,13 +129,11 @@ static struct clk clk_usysclk = { static struct clk clk_mrefclk = { .name = "mrefclk", .parent = &clk_xtal, - .id = -1, }; static struct clk clk_mdivclk = { .name = "mdivclk", .parent = &clk_xtal, - .id = -1, }; static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) @@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) static struct clk clk_usbsrc = { .name = "usbsrc", - .id = -1, .ops = &(struct clk_ops) { .get_rate = s3c2412_getrate_usbsrc, .set_rate = s3c2412_setrate_usbsrc, @@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) static struct clk clk_msysclk = { .name = "msysclk", - .id = -1, .ops = &(struct clk_ops) { .set_parent = s3c2412_setparent_msysclk, }, @@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) static struct clk clk_armclk = { .name = "armclk", - .id = -1, .parent = &clk_msysclk, .ops = &(struct clk_ops) { .set_parent = s3c2412_setparent_armclk, @@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) static struct clk clk_uart = { .name = "uartclk", - .id = -1, .ops = &(struct clk_ops) { .get_rate = s3c2412_getrate_uart, .set_rate = s3c2412_setrate_uart, @@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) static struct clk clk_i2s = { .name = "i2sclk", - .id = -1, .ops = &(struct clk_ops) { .get_rate = s3c2412_getrate_i2s, .set_rate = s3c2412_setrate_i2s, @@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) static struct clk clk_cam = { .name = "camif-upll", /* same as 2440 name */ - .id = -1, .ops = &(struct clk_ops) { .get_rate = s3c2412_getrate_cam, .set_rate = s3c2412_setrate_cam, @@ -463,37 +452,31 @@ static struct clk clk_cam = { static struct clk init_clocks_disable[] = { { .name = "nand", - .id = -1, .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_NAND, }, { .name = "sdi", - .id = -1, .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_SDI, }, { .name = "adc", - .id = -1, .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_ADC, }, { .name = "i2c", - .id = -1, .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_IIC, }, { .name = "iis", - .id = -1, .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_IIS, }, { .name = "spi", - .id = -1, .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_SPI, @@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = { static struct clk init_clocks[] = { { .name = "dma", - .id = 0, .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_DMA0, }, { .name = "dma", - .id = 1, .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_DMA1, }, { .name = "dma", - .id = 2, .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_DMA2, }, { .name = "dma", - .id = 3, .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_DMA3, }, { .name = "lcd", - .id = -1, .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_LCDC, }, { .name = "gpio", - .id = -1, .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_GPIO, }, { .name = "usb-host", - .id = -1, .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_USBH, }, { .name = "usb-device", - .id = -1, .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_USBD, }, { .name = "timers", - .id = -1, .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_PWMT, }, { .name = "uart", - .id = 0, + .devname = "s3c2412-uart.0", .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_UART0, }, { .name = "uart", - .id = 1, + .devname = "s3c2412-uart.1", .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_UART1, }, { .name = "uart", - .id = 2, + .devname = "s3c2412-uart.2", .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_UART2, }, { .name = "rtc", - .id = -1, .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_RTC, }, { .name = "watchdog", - .id = -1, .parent = &clk_p, .ctrlbit = 0, }, { .name = "usb-bus-gadget", - .id = -1, .parent = &clk_usb_bus, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_USB_DEV48, }, { .name = "usb-bus-host", - .id = -1, .parent = &clk_usb_bus, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_USB_HOST48, diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 3b02d8506e25..21a5e81f0ab5 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c @@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = { [0] = { .clk = { .name = "hsmmc-div", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, @@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = { [1] = { .clk = { .name = "hsmmc-div", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, @@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = { static struct clksrc_clk hsmmc_mux[] = { [0] = { .clk = { - .id = 0, .name = "hsmmc-if", + .devname = "s3c-sdhci.0", .ctrlbit = (1 << 6), .enable = s3c2443_clkcon_enable_s, }, @@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = { }, [1] = { .clk = { - .id = 1, .name = "hsmmc-if", + .devname = "s3c-sdhci.1", .ctrlbit = (1 << 12), .enable = s3c2443_clkcon_enable_s, }, @@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = { static struct clk hsmmc0_clk = { .name = "hsmmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2416_HCLKCON_HSMMC0, diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c index 3dc2426e2345..554e0d3ec70b 100644 --- a/arch/arm/mach-s3c2440/clock.c +++ b/arch/arm/mach-s3c2440/clock.c @@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) static struct clk s3c2440_clk_cam = { .name = "camif", - .id = -1, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2440_CLKCON_CAMERA, }; static struct clk s3c2440_clk_cam_upll = { .name = "camif-upll", - .id = -1, .ops = &(struct clk_ops) { .set_rate = s3c2440_camif_upll_setrate, .round_rate = s3c2440_camif_upll_round, @@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = { static struct clk s3c2440_clk_ac97 = { .name = "ac97", - .id = -1, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2440_CLKCON_CAMERA, }; diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index f4ec6d5715c8..a1a7176675b9 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -59,7 +59,6 @@ static struct clk clk_i2s_ext = { .name = "i2s-ext", - .id = -1, }; /* armdiv @@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) static struct clk clk_armdiv = { .name = "armdiv", - .id = -1, .parent = &clk_msysclk.clk, .ops = &(struct clk_ops) { .round_rate = s3c2443_armclk_roundrate, @@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = { static struct clksrc_clk clk_arm = { .clk = { .name = "armclk", - .id = -1, }, .sources = &(struct clksrc_sources) { .sources = clk_arm_sources, @@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = { static struct clksrc_clk clk_hsspi = { .clk = { .name = "hsspi", - .id = -1, .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_HSSPICLK, .enable = s3c2443_clkcon_enable_s, @@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = { static struct clksrc_clk clk_hsmmc_div = { .clk = { .name = "hsmmc-div", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, @@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable) static struct clk clk_hsmmc = { .name = "hsmmc-if", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_hsmmc_div.clk, .enable = s3c2443_enable_hsmmc, .ops = &(struct clk_ops) { @@ -248,7 +244,6 @@ static struct clk clk_hsmmc = { static struct clksrc_clk clk_i2s_eplldiv = { .clk = { .name = "i2s-eplldiv", - .id = -1, .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, @@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = { static struct clksrc_clk clk_i2s = { .clk = { .name = "i2s-if", - .id = -1, .ctrlbit = S3C2443_SCLKCON_I2SCLK, .enable = s3c2443_clkcon_enable_s, @@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = { static struct clk init_clocks_off[] = { { .name = "sdi", - .id = -1, .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_SDI, }, { .name = "iis", - .id = -1, .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_IIS, }, { .name = "spi", - .id = 0, + .devname = "s3c2410-spi.0", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_SPI0, }, { .name = "spi", - .id = 1, + .devname = "s3c2410-spi.1", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_SPI1, diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index e4177e22557b..4e2c371ff3d7 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -266,3 +266,26 @@ config MACH_SMARTQ7 select MACH_SMARTQ help Machine support for the SmartQ 7 + +config MACH_WLF_CRAGG_6410 + bool "Wolfson Cragganmore 6410" + select CPU_S3C6410 + select S3C64XX_SETUP_SDHCI + select S3C64XX_SETUP_I2C1 + select S3C64XX_SETUP_IDE + select S3C64XX_SETUP_FB_24BPP + select S3C64XX_SETUP_KEYPAD + select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_KEYPAD + select S3C_DEV_USB_HOST + select S3C_DEV_USB_HSOTG + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_I2C1 + select S3C_DEV_WDT + select S3C_DEV_RTC + select S3C64XX_DEV_SPI + select S3C24XX_GPIO_EXTRA128 + help + Machine support for the Wolfson Cragganmore S3C6410 variant. diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 4657363f0674..88d7fd22ef18 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o +obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o # device support diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index fdfc4d5e37a1..8cf39e33579e 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -39,7 +39,6 @@ static struct clk clk_ext_xtal_mux = { .name = "ext_xtal", - .id = -1, }; #define clk_fin_apll clk_ext_xtal_mux @@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = { struct clk clk_h2 = { .name = "hclk2", - .id = -1, .rate = 0, }; struct clk clk_27m = { .name = "clk_27m", - .id = -1, .rate = 27000000, }; @@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable) struct clk clk_48m = { .name = "clk_48m", - .id = -1, .rate = 48000000, .enable = clk_48m_ctrl, }; struct clk clk_xusbxti = { .name = "xusbxti", - .id = -1, .rate = 48000000, }; @@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable) static struct clk init_clocks_off[] = { { .name = "nand", - .id = -1, .parent = &clk_h, }, { .name = "rtc", - .id = -1, .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_RTC, }, { .name = "adc", - .id = -1, .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_TSADC, }, { .name = "i2c", - .id = -1, .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_IIC, }, { .name = "i2c", - .id = 1, + .devname = "s3c2440-i2c.1", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, }, { .name = "iis", - .id = 0, + .devname = "samsung-i2s.0", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_IIS0, }, { .name = "iis", - .id = 1, + .devname = "samsung-i2s.1", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_IIS1, }, { #ifdef CONFIG_CPU_S3C6410 .name = "iis", - .id = -1, /* There's only one IISv4 port */ .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, }, { #endif .name = "keypad", - .id = -1, .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, }, { .name = "spi", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI0, }, { .name = "spi", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI1, }, { .name = "spi_48m", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, }, { .name = "spi_48m", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, }, { .name = "48m", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, }, { .name = "48m", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, }, { .name = "48m", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, }, { .name = "dma0", - .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_DMA0, }, { .name = "dma1", - .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_DMA1, @@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = { static struct clk init_clocks[] = { { .name = "lcd", - .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_LCD, }, { .name = "gpio", - .id = -1, .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_GPIO, }, { .name = "usb-host", - .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_UHOST, }, { .name = "hsmmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, }, { .name = "hsmmc", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, }, { .name = "hsmmc", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, }, { .name = "otg", - .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_USB, }, { .name = "timers", - .id = -1, .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_PWM, }, { .name = "uart", - .id = 0, + .devname = "s3c6400-uart.0", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_UART0, }, { .name = "uart", - .id = 1, + .devname = "s3c6400-uart.1", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_UART1, }, { .name = "uart", - .id = 2, + .devname = "s3c6400-uart.2", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_UART2, }, { .name = "uart", - .id = 3, + .devname = "s3c6400-uart.3", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_UART3, }, { .name = "watchdog", - .id = -1, .parent = &clk_p, .ctrlbit = S3C_CLKCON_PCLK_WDT, }, { .name = "ac97", - .id = -1, .parent = &clk_p, .ctrlbit = S3C_CLKCON_PCLK_AC97, }, { .name = "cfcon", - .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, .ctrlbit = S3C_CLKCON_HCLK_IHOST, @@ -334,7 +313,6 @@ static struct clk init_clocks[] = { static struct clk clk_fout_apll = { .name = "fout_apll", - .id = -1, }; static struct clk *clk_src_apll_list[] = { @@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = { static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", - .id = -1, }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, .sources = &clk_src_apll, @@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = { static struct clksrc_clk clk_mout_epll = { .clk = { .name = "mout_epll", - .id = -1, }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, .sources = &clk_src_epll, @@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = { static struct clksrc_clk clk_mout_mpll = { .clk = { .name = "mout_mpll", - .id = -1, }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, .sources = &clk_src_mpll, @@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) static struct clk clk_arm = { .name = "armclk", - .id = -1, .parent = &clk_mout_apll.clk, .ops = &(struct clk_ops) { .get_rate = s3c64xx_clk_arm_get_rate, @@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = { static struct clk clk_dout_mpll = { .name = "dout_mpll", - .id = -1, .parent = &clk_mout_mpll.clk, .ops = &clk_dout_ops, }; @@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = { static struct clk clk_iis_cd0 = { .name = "iis_cdclk0", - .id = -1, }; static struct clk clk_iis_cd1 = { .name = "iis_cdclk1", - .id = -1, }; static struct clk clk_iisv4_cd = { .name = "iis_cdclk_v4", - .id = -1, }; static struct clk clk_pcm_cd = { .name = "pcm_cdclk", - .id = -1, }; static struct clk *clkset_audio0_list[] = { @@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = { { .clk = { .name = "mmc_bus", - .id = 0, + .devname = "s3c-sdhci.0", .ctrlbit = S3C_CLKCON_SCLK_MMC0, .enable = s3c64xx_sclk_ctrl, }, @@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "mmc_bus", - .id = 1, + .devname = "s3c-sdhci.1", .ctrlbit = S3C_CLKCON_SCLK_MMC1, .enable = s3c64xx_sclk_ctrl, }, @@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "mmc_bus", - .id = 2, + .devname = "s3c-sdhci.2", .ctrlbit = S3C_CLKCON_SCLK_MMC2, .enable = s3c64xx_sclk_ctrl, }, @@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "usb-bus-host", - .id = -1, .ctrlbit = S3C_CLKCON_SCLK_UHOST, .enable = s3c64xx_sclk_ctrl, }, @@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = -1, .ctrlbit = S3C_CLKCON_SCLK_UART, .enable = s3c64xx_sclk_ctrl, }, @@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = { /* Where does UCLK0 come from? */ .clk = { .name = "spi-bus", - .id = 0, + .devname = "s3c64xx-spi.0", .ctrlbit = S3C_CLKCON_SCLK_SPI0, .enable = s3c64xx_sclk_ctrl, }, @@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "spi-bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_SPI1, + .devname = "s3c64xx-spi.1", .enable = s3c64xx_sclk_ctrl, }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, @@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "audio-bus", - .id = 0, + .devname = "samsung-i2s.0", .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, .enable = s3c64xx_sclk_ctrl, }, @@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "audio-bus", - .id = 1, + .devname = "samsung-i2s.1", .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, .enable = s3c64xx_sclk_ctrl, }, @@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "audio-bus", - .id = 2, + .devname = "samsung-i2s.2", .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, .enable = s3c64xx_sclk_ctrl, }, @@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "irda-bus", - .id = 0, .ctrlbit = S3C_CLKCON_SCLK_IRDA, .enable = s3c64xx_sclk_ctrl, }, @@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "camera", - .id = -1, .ctrlbit = S3C_CLKCON_SCLK_CAM, .enable = s3c64xx_sclk_ctrl, }, diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do {} while (0) + +#endif diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index 8e2df26cf14a..ddb63a1863ab 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -198,7 +198,9 @@ * interrupt controllers). */ #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) -#ifdef CONFIG_SMDK6410_WM1190_EV1 +#ifdef CONFIG_MACH_WLF_CRAGG_6410 +#define IRQ_BOARD_NR 128 +#elif defined(CONFIG_SMDK6410_WM1190_EV1) #define IRQ_BOARD_NR 64 #elif defined(CONFIG_SMDK6410_WM1192_EV1) #define IRQ_BOARD_NR 64 diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h index 1e9f20f0bb7b..38659bebe4b1 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h @@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void) * the IRQ wake controls depending on the CPU we are running on */ #define s3c_irqwake_eintallow ((1 << 28) - 1) -#define s3c_irqwake_intallow (0) +#define s3c_irqwake_intallow (~0) static inline void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save) @@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, save->ucon = new_ucon; } } + +static inline void s3c_pm_restored_gpios(void) +{ + /* ensure sleep mode has been cleared from the system */ + + __raw_writel(0, S3C64XX_SLPEN); +} + +static inline void s3c_pm_saved_gpios(void) +{ + /* turn on the sleep mode and keep it there, as it seems that during + * suspend the xCON registers get re-set and thus you can end up with + * problems between going to sleep and resuming. + */ + + __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); +} diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c index 97660c8141ae..75d9a0e49193 100644 --- a/arch/arm/mach-s3c64xx/irq.c +++ b/arch/arm/mach-s3c64xx/irq.c @@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = { }, }; +/* setup the sources the vic should advertise resume for, even though it + * is not doing the wake (set_irq_wake needs to be valid) */ +#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) +#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \ + 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE)) void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ - vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); - vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); + vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); + vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); /* add the timer sub-irqs */ s3c_init_vic_timer_irq(5, IRQ_TIMER0); diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c new file mode 100644 index 000000000000..35088ce791ca --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -0,0 +1,574 @@ +/* linux/arch/arm/mach-s3c64xx/mach-crag6410.c + * + * Copyright 2011 Wolfson Microelectronics plc + * Mark Brown <broonie@opensource.wolfsonmicro.com> + * + * Copyright 2011 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/fb.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/regulator/machine.h> +#include <linux/pwm_backlight.h> +#include <linux/dm9000.h> +#include <linux/gpio_keys.h> +#include <linux/basic_mmio_gpio.h> +#include <linux/spi/spi.h> + +#include <linux/i2c/pca953x.h> + +#include <video/platform_lcd.h> + +#include <linux/mfd/wm831x/core.h> +#include <linux/mfd/wm831x/pdata.h> +#include <linux/mfd/wm831x/gpio.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <mach/hardware.h> +#include <mach/map.h> + +#include <mach/s3c6410.h> +#include <mach/regs-fb.h> +#include <mach/regs-sys.h> +#include <mach/regs-gpio.h> +#include <mach/regs-modem.h> + +#include <mach/gpio-bank-o.h> +#include <mach/regs-gpio-memport.h> + +#include <plat/regs-serial.h> +#include <plat/fb.h> +#include <plat/sdhci.h> +#include <plat/gpio-cfg.h> +#include <plat/s3c64xx-spi.h> + +#include <plat/keypad.h> +#include <plat/clock.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/adc.h> +#include <plat/iic.h> +#include <plat/pm.h> + +#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START + +#define PCA935X_GPIO_BASE GPIO_BOARD_START +#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8) + +/* serial port setup */ + +#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) +#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) +#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) + +static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, +}; + +static struct platform_pwm_backlight_data crag6410_backlight_data = { + .pwm_id = 0, + .max_brightness = 1000, + .dft_brightness = 600, + .pwm_period_ns = 100000, /* about 1kHz */ +}; + +static struct platform_device crag6410_backlight_device = { + .name = "pwm-backlight", + .id = -1, + .dev = { + .parent = &s3c_device_timer[0].dev, + .platform_data = &crag6410_backlight_data, + }, +}; + +static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) +{ + pr_debug("%s: setting power %d\n", __func__, power); + + if (power) { + gpio_set_value(S3C64XX_GPB(0), 1); + msleep(1); + s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2)); + } else { + gpio_direction_output(S3C64XX_GPF(14), 0); + gpio_set_value(S3C64XX_GPB(0), 0); + } +} + +static struct platform_device crag6410_lcd_powerdev = { + .name = "platform-lcd", + .id = -1, + .dev.parent = &s3c_device_fb.dev, + .dev.platform_data = &(struct plat_lcd_data) { + .set_power = crag6410_lcd_power_set, + }, +}; + +/* 640x480 URT */ +static struct s3c_fb_pd_win crag6410_fb_win0 = { + /* this is to ensure we use win0 */ + .win_mode = { + .left_margin = 150, + .right_margin = 80, + .upper_margin = 40, + .lower_margin = 5, + .hsync_len = 40, + .vsync_len = 5, + .xres = 640, + .yres = 480, + }, + .max_bpp = 32, + .default_bpp = 16, + .virtual_y = 480 * 2, + .virtual_x = 640, +}; + +/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ +static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = { + .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, + .win[0] = &crag6410_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, +}; + +/* 2x6 keypad */ + +static uint32_t crag6410_keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(0, 0, KEY_VOLUMEUP), + KEY(0, 1, KEY_HOME), + KEY(0, 2, KEY_VOLUMEDOWN), + KEY(0, 3, KEY_HELP), + KEY(0, 4, KEY_MENU), + KEY(0, 5, KEY_MEDIA), + KEY(1, 0, 232), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_LEFT), + KEY(1, 3, KEY_UP), + KEY(1, 4, KEY_RIGHT), + KEY(1, 5, KEY_CAMERA), +}; + +static struct matrix_keymap_data crag6410_keymap_data __initdata = { + .keymap = crag6410_keymap, + .keymap_size = ARRAY_SIZE(crag6410_keymap), +}; + +static struct samsung_keypad_platdata crag6410_keypad_data __initdata = { + .keymap_data = &crag6410_keymap_data, + .rows = 2, + .cols = 6, +}; + +static struct gpio_keys_button crag6410_gpio_keys[] = { + [0] = { + .code = KEY_SUSPEND, + .gpio = S3C64XX_GPL(10), /* EINT 18 */ + .type = EV_SW, + .wakeup = 1, + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data crag6410_gpio_keydata = { + .buttons = crag6410_gpio_keys, + .nbuttons = ARRAY_SIZE(crag6410_gpio_keys), +}; + +static struct platform_device crag6410_gpio_keydev = { + .name = "gpio-keys", + .id = 0, + .dev.platform_data = &crag6410_gpio_keydata, +}; + +static struct resource crag6410_dm9k_resource[] = { + [0] = { + .start = S3C64XX_PA_XM0CSN5, + .end = S3C64XX_PA_XM0CSN5 + 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S3C64XX_PA_XM0CSN5 + (1 << 8), + .end = S3C64XX_PA_XM0CSN5 + (1 << 8) + 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = S3C_EINT(17), + .end = S3C_EINT(17), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct dm9000_plat_data mini6410_dm9k_pdata = { + .flags = DM9000_PLATF_16BITONLY, +}; + +static struct platform_device crag6410_dm9k_device = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(crag6410_dm9k_resource), + .resource = crag6410_dm9k_resource, + .dev.platform_data = &mini6410_dm9k_pdata, +}; + +static struct resource crag6410_mmgpio_resource[] = { + [0] = { + .start = S3C64XX_PA_XM0CSN4 + 1, + .end = S3C64XX_PA_XM0CSN4 + 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device crag6410_mmgpio = { + .name = "basic-mmio-gpio", + .id = -1, + .resource = crag6410_mmgpio_resource, + .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource), + .dev.platform_data = &(struct bgpio_pdata) { + .base = -1, + }, +}; + +static struct platform_device *crag6410_devices[] __initdata = { + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_fb, + &s3c_device_ohci, + &s3c_device_usb_hsotg, + &s3c_device_adc, + &s3c_device_rtc, + &s3c_device_ts, + &s3c_device_timer[0], + &s3c64xx_device_iis0, + &s3c64xx_device_iis1, + &samsung_asoc_dma, + &samsung_device_keypad, + &crag6410_gpio_keydev, + &crag6410_dm9k_device, + &s3c64xx_device_spi0, + &crag6410_mmgpio, + &crag6410_lcd_powerdev, + &crag6410_backlight_device, +}; + +static struct pca953x_platform_data crag6410_pca_data = { + .gpio_base = PCA935X_GPIO_BASE, + .irq_base = 0, +}; + +static struct regulator_consumer_supply vddarm_consumers[] __initdata = { + REGULATOR_SUPPLY("vddarm", NULL), +}; + +static struct regulator_init_data vddarm __initdata = { + .constraints = { + .name = "VDDARM", + .min_uV = 1000000, + .max_uV = 1300000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers), + .consumer_supplies = vddarm_consumers, +}; + +static struct regulator_init_data vddint __initdata = { + .constraints = { + .name = "VDDINT", + .min_uV = 1000000, + .max_uV = 1200000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, +}; + +static struct regulator_init_data vddmem __initdata = { + .constraints = { + .name = "VDDMEM", + .always_on = 1, + }, +}; + +static struct regulator_init_data vddsys __initdata = { + .constraints = { + .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS", + .always_on = 1, + }, +}; + +static struct regulator_consumer_supply vddmmc_consumers[] __initdata = { + REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), + REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"), + REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), +}; + +static struct regulator_init_data vddmmc __initdata = { + .constraints = { + .name = "VDDMMC,UH", + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers), + .consumer_supplies = vddmmc_consumers, +}; + +static struct regulator_init_data vddotgi __initdata = { + .constraints = { + .name = "VDDOTGi", + .always_on = 1, + }, +}; + +static struct regulator_init_data vddotg __initdata = { + .constraints = { + .name = "VDDOTG", + .always_on = 1, + }, +}; + +static struct regulator_init_data vddhi __initdata = { + .constraints = { + .name = "VDDHI", + .always_on = 1, + }, +}; + +static struct regulator_init_data vddadc __initdata = { + .constraints = { + .name = "VDDADC,VDDDAC", + .always_on = 1, + }, +}; + +static struct regulator_init_data vddmem0 __initdata = { + .constraints = { + .name = "VDDMEM0", + .always_on = 1, + }, +}; + +static struct regulator_init_data vddpll __initdata = { + .constraints = { + .name = "VDDPLL", + .always_on = 1, + }, +}; + +static struct regulator_init_data vddlcd __initdata = { + .constraints = { + .name = "VDDLCD", + .always_on = 1, + }, +}; + +static struct regulator_init_data vddalive __initdata = { + .constraints = { + .name = "VDDALIVE", + .always_on = 1, + }, +}; + +static struct wm831x_status_pdata banff_red_led __initdata = { + .name = "banff:red:", + .default_src = WM831X_STATUS_MANUAL, +}; + +static struct wm831x_status_pdata banff_green_led __initdata = { + .name = "banff:green:", + .default_src = WM831X_STATUS_MANUAL, +}; + +static struct wm831x_touch_pdata touch_pdata __initdata = { + .data_irq = S3C_EINT(26), +}; + +static __init int crag_pmic_pre_init(struct wm831x *wm831x) +{ + /* Touchscreen data IRQ - CMOS, DBVDD, active high*/ + wm831x_reg_write(wm831x, WM831X_GPIO11_CONTROL, + WM831X_GPN_POL | WM831X_GPN_ENA | 0x6); + + /* Touchscreen pen down IRQ - CMOS, DBVDD, active high*/ + wm831x_reg_write(wm831x, WM831X_GPIO12_CONTROL, + WM831X_GPN_POL | WM831X_GPN_ENA | 0x7); + + return 0; +} + +static struct wm831x_pdata crag_pmic_pdata __initdata = { + .pre_init = crag_pmic_pre_init, + + .irq_base = BANFF_PMIC_IRQ_BASE, + .gpio_base = GPIO_BOARD_START + 8, + + .dcdc = { + &vddarm, /* DCDC1 */ + &vddint, /* DCDC2 */ + &vddmem, /* DCDC3 */ + }, + + .ldo = { + &vddsys, /* LDO1 */ + &vddmmc, /* LDO2 */ + NULL, /* LDO3 */ + &vddotgi, /* LDO4 */ + &vddotg, /* LDO5 */ + &vddhi, /* LDO6 */ + &vddadc, /* LDO7 */ + &vddmem0, /* LDO8 */ + &vddpll, /* LDO9 */ + &vddlcd, /* LDO10 */ + &vddalive, /* LDO11 */ + }, + + .status = { + &banff_green_led, + &banff_red_led, + }, + + .touch = &touch_pdata, +}; + +static struct i2c_board_info i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("24c08", 0x50), }, + { I2C_BOARD_INFO("tca6408", 0x20), + .platform_data = &crag6410_pca_data, + }, + { I2C_BOARD_INFO("wm8312", 0x34), + .platform_data = &crag_pmic_pdata, + .irq = S3C_EINT(23), + }, +}; + +static struct s3c2410_platform_i2c i2c0_pdata = { + .frequency = 400000, +}; + +static struct i2c_board_info i2c_devs1[] __initdata = { + { I2C_BOARD_INFO("wm8311", 0x34), + .platform_data = &glenfarclas_pmic_pdata, + }, +}; + +static void __init crag6410_map_io(void) +{ + s3c64xx_init_io(NULL, 0); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); + + /* LCD type and Bypass set by bootloader */ +} + +static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_PERMANENT, +}; + +static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S3C64XX_GPF(11), +}; + +static void crag6410_cfg_sdhci0(struct platform_device *dev, int width) +{ + /* Set all the necessary GPG pins to special-function 2 */ + s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); + + /* force card-detected for prototype 0 */ + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN); +} + +static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_INTERNAL, + .cfg_gpio = crag6410_cfg_sdhci0, +}; + +static void __init crag6410_machine_init(void) +{ + /* Open drain IRQs need pullups */ + s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP); + + gpio_request(S3C64XX_GPB(0), "LCD power"); + gpio_direction_output(S3C64XX_GPB(0), 0); + + gpio_request(S3C64XX_GPF(14), "LCD PWM"); + gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */ + + gpio_request(S3C64XX_GPB(1), "SD power"); + gpio_direction_output(S3C64XX_GPB(1), 0); + + gpio_request(S3C64XX_GPF(10), "nRESETSEL"); + gpio_direction_output(S3C64XX_GPF(10), 1); + + s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata); + s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata); + s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata); + + s3c_i2c0_set_platdata(&i2c0_pdata); + s3c_i2c1_set_platdata(NULL); + s3c_fb_set_platdata(&crag6410_lcd_pdata); + + i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); + i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + + samsung_keypad_set_platdata(&crag6410_keypad_data); + + platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); + + s3c_pm_init(); +} + +MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") + /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */ + .boot_params = S3C64XX_PA_SDRAM + 0x100, + .init_irq = s3c6410_init_irq, + .map_io = crag6410_map_io, + .init_machine = crag6410_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 2c0353a80906..e0521e0fa762 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -209,17 +209,9 @@ static struct platform_device smdk6410_smsc911x = { }; #ifdef CONFIG_REGULATOR -static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = { - { - /* WM8580 */ - .supply = "PVDD", - .dev_name = "0-001b", - }, - { - /* WM8580 */ - .supply = "AVDD", - .dev_name = "0-001b", - }, +static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] __initdata = { + REGULATOR_SUPPLY("PVDD", "0-001b"), + REGULATOR_SUPPLY("AVDD", "0-001b"), }; static struct regulator_init_data smdk6410_b_pwr_5v_data = { @@ -344,9 +336,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { #ifdef CONFIG_REGULATOR /* ARM core */ static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = { - { - .supply = "vddarm", - } + REGULATOR_SUPPLY("vddarm", NULL), }; /* VDDARM, BUCK1 on J5 */ @@ -484,11 +474,7 @@ static struct regulator_init_data wm8350_dcdc3_data = { /* USB, EXT, PCM, ADC/DAC, USB, MMC */ static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = { - { - /* WM8580 */ - .supply = "DVDD", - .dev_name = "0-001b", - }, + REGULATOR_SUPPLY("DVDD", "0-001b"), }; static struct regulator_init_data wm8350_dcdc4_data = { @@ -599,7 +585,7 @@ static struct regulator_init_data wm1192_dcdc3 = { }; static struct regulator_consumer_supply wm1192_ldo1_consumers[] = { - { .supply = "DVDD", .dev_name = "0-001b", }, /* WM8580 */ + REGULATOR_SUPPLY("DVDD", "0-001b"), /* WM8580 */ }; static struct regulator_init_data wm1192_ldo1 = { diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S index 1f87732b2320..2fd343332838 100644 --- a/arch/arm/mach-s3c64xx/sleep.S +++ b/arch/arm/mach-s3c64xx/sleep.S @@ -35,19 +35,14 @@ */ ENTRY(s3c_cpu_save) - stmfd sp!, { r4 - r12, lr } - ldr r3, =resume_with_mmu - bl cpu_suspend + adr r3, BSYM(s3c64xx_finish_suspend) + b cpu_suspend +s3c64xx_finish_suspend: @@ call final suspend code ldr r0, =pm_cpu_sleep ldr pc, [r0] - @@ return to the caller, after the MMU is turned on. - @@ restore the last bits of the stack and return. -resume_with_mmu: - ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save - /* Sleep magic, the word before the resume entry point so that the * bootloader can check for a resumeable image. */ diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index 9f12c2ebf416..0e9cd3092dd2 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = { static struct clksrc_clk clk_hclk = { .clk = { .name = "clk_hclk", - .id = -1, .parent = &clk_armclk.clk, }, .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, @@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = { static struct clksrc_clk clk_pclk = { .clk = { .name = "clk_pclk", - .id = -1, .parent = &clk_hclk.clk, }, .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, @@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = { static struct clksrc_clk clk_hclk_low = { .clk = { .name = "clk_hclk_low", - .id = -1, }, .sources = &clkset_hclk_low, .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, @@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = { static struct clksrc_clk clk_pclk_low = { .clk = { .name = "clk_pclk_low", - .id = -1, .parent = &clk_hclk_low.clk, }, .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, @@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = { static struct clk init_clocks_off[] = { { .name = "nand", - .id = -1, .parent = &clk_hclk.clk, .enable = s5p64x0_mem_ctrl, .ctrlbit = (1 << 2), }, { .name = "post", - .id = -1, .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 5) }, { .name = "2d", - .id = -1, .parent = &clk_hclk.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 8), }, { .name = "pdma", - .id = -1, .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 12), }, { .name = "hsmmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 17), }, { .name = "hsmmc", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 18), }, { .name = "hsmmc", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 19), }, { .name = "otg", - .id = -1, .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 20) }, { .name = "irom", - .id = -1, .parent = &clk_hclk.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 25), }, { .name = "lcd", - .id = -1, .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk1_ctrl, .ctrlbit = (1 << 1), }, { .name = "hclk_fimgvg", - .id = -1, .parent = &clk_hclk.clk, .enable = s5p64x0_hclk1_ctrl, .ctrlbit = (1 << 2), }, { .name = "tsi", - .id = -1, .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk1_ctrl, .ctrlbit = (1 << 0), }, { .name = "watchdog", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 5), }, { .name = "rtc", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 6), }, { .name = "timers", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 7), }, { .name = "pcm", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 8), }, { .name = "adc", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 12), }, { .name = "i2c", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 17), }, { .name = "spi", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 21), }, { .name = "spi", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 22), }, { .name = "gps", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 25), }, { .name = "iis", - .id = 0, + .devname = "samsung-i2s.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 26), }, { .name = "dsim", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 28), }, { .name = "etm", - .id = -1, .parent = &clk_pclk.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 29), }, { .name = "dmc0", - .id = -1, .parent = &clk_pclk.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 30), }, { .name = "pclk_fimgvg", - .id = -1, .parent = &clk_pclk.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 31), }, { .name = "sclk_spi_48", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_48m, .enable = s5p64x0_sclk_ctrl, .ctrlbit = (1 << 22), }, { .name = "sclk_spi_48", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_48m, .enable = s5p64x0_sclk_ctrl, .ctrlbit = (1 << 23), }, { .name = "mmc_48m", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_48m, .enable = s5p64x0_sclk_ctrl, .ctrlbit = (1 << 27), }, { .name = "mmc_48m", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_48m, .enable = s5p64x0_sclk_ctrl, .ctrlbit = (1 << 28), }, { .name = "mmc_48m", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_48m, .enable = s5p64x0_sclk_ctrl, .ctrlbit = (1 << 29), @@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = { static struct clk init_clocks[] = { { .name = "intc", - .id = -1, .parent = &clk_hclk.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 1), }, { .name = "mem", - .id = -1, .parent = &clk_hclk.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 21), }, { .name = "uart", - .id = 0, + .devname = "s3c6400-uart.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 1), }, { .name = "uart", - .id = 1, + .devname = "s3c6400-uart.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 2), }, { .name = "uart", - .id = 2, + .devname = "s3c6400-uart.2", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 3), }, { .name = "uart", - .id = 3, + .devname = "s3c6400-uart.3", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 4), }, { .name = "gpio", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 18), @@ -374,12 +347,10 @@ static struct clk init_clocks[] = { static struct clk clk_iis_cd_v40 = { .name = "iis_cdclk_v40", - .id = -1, }; static struct clk clk_pcm_cd = { .name = "pcm_cdclk", - .id = -1, }; static struct clk *clkset_group1_list[] = { @@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = { { .clk = { .name = "sclk_mmc", - .id = 0, + .devname = "s3c-sdhci.0", .ctrlbit = (1 << 24), .enable = s5p64x0_sclk_ctrl, }, @@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 1, + .devname = "s3c-sdhci.1", .ctrlbit = (1 << 25), .enable = s5p64x0_sclk_ctrl, }, @@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 2, + .devname = "s3c-sdhci.2", .ctrlbit = (1 << 26), .enable = s5p64x0_sclk_ctrl, }, @@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = -1, .ctrlbit = (1 << 5), .enable = s5p64x0_sclk_ctrl, }, @@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 0, + .devname = "s3c64xx-spi.0", .ctrlbit = (1 << 20), .enable = s5p64x0_sclk_ctrl, }, @@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 1, + .devname = "s3c64xx-spi.1", .ctrlbit = (1 << 21), .enable = s5p64x0_sclk_ctrl, }, @@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_post", - .id = -1, .ctrlbit = (1 << 10), .enable = s5p64x0_sclk_ctrl, }, @@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_dispcon", - .id = -1, .ctrlbit = (1 << 1), .enable = s5p64x0_sclk1_ctrl, }, @@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimgvg", - .id = -1, .ctrlbit = (1 << 2), .enable = s5p64x0_sclk1_ctrl, }, @@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_audio2", - .id = -1, .ctrlbit = (1 << 11), .enable = s5p64x0_sclk_ctrl, }, diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 4eec457ddccc..d9dc16cde109 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -36,7 +36,6 @@ static struct clksrc_clk clk_mout_dpll = { .clk = { .name = "mout_dpll", - .id = -1, }, .sources = &clk_src_dpll, .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 }, @@ -96,7 +95,6 @@ static struct clk_ops s5p6450_epll_ops = { static struct clksrc_clk clk_dout_epll = { .clk = { .name = "dout_epll", - .id = -1, .parent = &clk_mout_epll.clk, }, .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 }, @@ -105,7 +103,6 @@ static struct clksrc_clk clk_dout_epll = { static struct clksrc_clk clk_mout_hclk_sel = { .clk = { .name = "mout_hclk_sel", - .id = -1, }, .sources = &clkset_hclk_low, .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 }, @@ -124,7 +121,6 @@ static struct clksrc_sources clkset_hclk = { static struct clksrc_clk clk_hclk = { .clk = { .name = "clk_hclk", - .id = -1, }, .sources = &clkset_hclk, .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 }, @@ -134,7 +130,6 @@ static struct clksrc_clk clk_hclk = { static struct clksrc_clk clk_pclk = { .clk = { .name = "clk_pclk", - .id = -1, .parent = &clk_hclk.clk, }, .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, @@ -142,7 +137,6 @@ static struct clksrc_clk clk_pclk = { static struct clksrc_clk clk_dout_pwm_ratio0 = { .clk = { .name = "clk_dout_pwm_ratio0", - .id = -1, .parent = &clk_mout_hclk_sel.clk, }, .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 }, @@ -151,7 +145,6 @@ static struct clksrc_clk clk_dout_pwm_ratio0 = { static struct clksrc_clk clk_pclk_to_wdt_pwm = { .clk = { .name = "clk_pclk_to_wdt_pwm", - .id = -1, .parent = &clk_dout_pwm_ratio0.clk, }, .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 }, @@ -160,7 +153,6 @@ static struct clksrc_clk clk_pclk_to_wdt_pwm = { static struct clksrc_clk clk_hclk_low = { .clk = { .name = "clk_hclk_low", - .id = -1, }, .sources = &clkset_hclk_low, .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 }, @@ -170,7 +162,6 @@ static struct clksrc_clk clk_hclk_low = { static struct clksrc_clk clk_pclk_low = { .clk = { .name = "clk_pclk_low", - .id = -1, .parent = &clk_hclk_low.clk, }, .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, @@ -184,109 +175,101 @@ static struct clksrc_clk clk_pclk_low = { static struct clk init_clocks_off[] = { { .name = "usbhost", - .id = -1, .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 3), }, { .name = "pdma", - .id = -1, .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 12), }, { .name = "hsmmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 17), }, { .name = "hsmmc", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 18), }, { .name = "hsmmc", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 19), }, { .name = "usbotg", - .id = -1, .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 20), }, { .name = "lcd", - .id = -1, .parent = &clk_h, .enable = s5p64x0_hclk1_ctrl, .ctrlbit = (1 << 1), }, { .name = "watchdog", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 5), }, { .name = "rtc", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 6), }, { .name = "adc", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 12), }, { .name = "i2c", - .id = 0, + .devname = "s3c2440-i2c.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 17), }, { .name = "spi", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 21), }, { .name = "spi", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 22), }, { .name = "iis", - .id = 0, + .devname = "samsung-i2s.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 26), }, { .name = "iis", - .id = 1, + .devname = "samsung-i2s.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 15), }, { .name = "iis", - .id = 2, + .devname = "samsung-i2s.2", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 16), }, { .name = "i2c", - .id = 1, + .devname = "s3c2440-i2c.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 27), }, { .name = "dmc0", - .id = -1, .parent = &clk_pclk.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 30), @@ -299,49 +282,45 @@ static struct clk init_clocks_off[] = { static struct clk init_clocks[] = { { .name = "intc", - .id = -1, .parent = &clk_hclk.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 1), }, { .name = "mem", - .id = -1, .parent = &clk_hclk.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 21), }, { .name = "uart", - .id = 0, + .devname = "s3c6400-uart.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 1), }, { .name = "uart", - .id = 1, + .devname = "s3c6400-uart.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 2), }, { .name = "uart", - .id = 2, + .devname = "s3c6400-uart.2", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 3), }, { .name = "uart", - .id = 3, + .devname = "s3c6400-uart.3", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 4), }, { .name = "timers", - .id = -1, .parent = &clk_pclk_to_wdt_pwm.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 7), }, { .name = "gpio", - .id = -1, .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 18), @@ -421,7 +400,6 @@ static struct clksrc_sources clkset_sclk_audio0 = { static struct clksrc_clk clk_sclk_audio0 = { .clk = { .name = "audio-bus", - .id = -1, .enable = s5p64x0_sclk_ctrl, .ctrlbit = (1 << 8), .parent = &clk_dout_epll.clk, @@ -435,7 +413,7 @@ static struct clksrc_clk clksrcs[] = { { .clk = { .name = "sclk_mmc", - .id = 0, + .devname = "s3c-sdhci.0", .ctrlbit = (1 << 24), .enable = s5p64x0_sclk_ctrl, }, @@ -445,7 +423,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 1, + .devname = "s3c-sdhci.1", .ctrlbit = (1 << 25), .enable = s5p64x0_sclk_ctrl, }, @@ -455,7 +433,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 2, + .devname = "s3c-sdhci.2", .ctrlbit = (1 << 26), .enable = s5p64x0_sclk_ctrl, }, @@ -465,7 +443,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = -1, .ctrlbit = (1 << 5), .enable = s5p64x0_sclk_ctrl, }, @@ -475,7 +452,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 0, + .devname = "s3c64xx-spi.0", .ctrlbit = (1 << 20), .enable = s5p64x0_sclk_ctrl, }, @@ -485,7 +462,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 1, + .devname = "s3c64xx-spi.1", .ctrlbit = (1 << 21), .enable = s5p64x0_sclk_ctrl, }, @@ -495,7 +472,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = -1, .ctrlbit = (1 << 10), .enable = s5p64x0_sclk_ctrl, }, @@ -505,7 +481,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "aclk_mali", - .id = -1, .ctrlbit = (1 << 2), .enable = s5p64x0_sclk1_ctrl, }, @@ -515,7 +490,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_2d", - .id = -1, .ctrlbit = (1 << 12), .enable = s5p64x0_sclk_ctrl, }, @@ -525,7 +499,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_usi", - .id = -1, .ctrlbit = (1 << 7), .enable = s5p64x0_sclk_ctrl, }, @@ -535,7 +508,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_camif", - .id = -1, .ctrlbit = (1 << 6), .enable = s5p64x0_sclk_ctrl, }, @@ -545,7 +517,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_dispcon", - .id = -1, .ctrlbit = (1 << 1), .enable = s5p64x0_sclk1_ctrl, }, @@ -555,7 +526,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_hsmmc44", - .id = -1, .ctrlbit = (1 << 30), .enable = s5p64x0_sclk_ctrl, }, diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-s5p64x0/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do {} while (0) + +#endif diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 0305e9b8282d..cd248e681377 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -31,7 +31,6 @@ static struct clk s5p_clk_otgphy = { .name = "otg_phy", - .id = -1, }; static struct clk *clk_src_mout_href_list[] = { @@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = { static struct clksrc_clk clk_mout_href = { .clk = { .name = "mout_href", - .id = -1, }, .sources = &clk_src_mout_href, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, @@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = { static struct clksrc_clk clk_mout_48m = { .clk = { .name = "mout_48m", - .id = -1, }, .sources = &clk_src_mout_48m, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, @@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = { static struct clksrc_clk clk_mout_mpll = { .clk = { .name = "mout_mpll", - .id = -1, }, .sources = &clk_src_mpll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, @@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = { static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", - .id = -1, }, .sources = &clk_src_apll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, @@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_epll = { .clk = { .name = "mout_epll", - .id = -1, }, .sources = &clk_src_epll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, @@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = { static struct clksrc_clk clk_mout_hpll = { .clk = { .name = "mout_hpll", - .id = -1, }, .sources = &clk_src_mout_hpll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, @@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = { static struct clksrc_clk clk_div_apll = { .clk = { .name = "div_apll", - .id = -1, .parent = &clk_mout_apll.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, @@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = { static struct clksrc_clk clk_div_arm = { .clk = { .name = "div_arm", - .id = -1, .parent = &clk_div_apll.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, @@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = { static struct clksrc_clk clk_div_d0_bus = { .clk = { .name = "div_d0_bus", - .id = -1, .parent = &clk_div_arm.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, @@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = { static struct clksrc_clk clk_div_pclkd0 = { .clk = { .name = "div_pclkd0", - .id = -1, .parent = &clk_div_d0_bus.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, @@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = { static struct clksrc_clk clk_div_secss = { .clk = { .name = "div_secss", - .id = -1, .parent = &clk_div_d0_bus.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, @@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = { static struct clksrc_clk clk_div_apll2 = { .clk = { .name = "div_apll2", - .id = -1, .parent = &clk_mout_apll.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, @@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = { static struct clksrc_clk clk_mout_am = { .clk = { .name = "mout_am", - .id = -1, }, .sources = &clk_src_mout_am, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, @@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = { static struct clksrc_clk clk_div_d1_bus = { .clk = { .name = "div_d1_bus", - .id = -1, .parent = &clk_mout_am.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, @@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = { static struct clksrc_clk clk_div_mpll2 = { .clk = { .name = "div_mpll2", - .id = -1, .parent = &clk_mout_am.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, @@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = { static struct clksrc_clk clk_div_mpll = { .clk = { .name = "div_mpll", - .id = -1, .parent = &clk_mout_am.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, @@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = { static struct clksrc_clk clk_mout_onenand = { .clk = { .name = "mout_onenand", - .id = -1, }, .sources = &clk_src_mout_onenand, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, @@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = { static struct clksrc_clk clk_div_onenand = { .clk = { .name = "div_onenand", - .id = -1, .parent = &clk_mout_onenand.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, @@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = { static struct clksrc_clk clk_div_pclkd1 = { .clk = { .name = "div_pclkd1", - .id = -1, .parent = &clk_div_d1_bus.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, @@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = { static struct clksrc_clk clk_div_cam = { .clk = { .name = "div_cam", - .id = -1, .parent = &clk_div_mpll2.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, @@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = { static struct clksrc_clk clk_div_hdmi = { .clk = { .name = "div_hdmi", - .id = -1, .parent = &clk_mout_hpll.clk, }, .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, @@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable) static struct clk init_clocks_off[] = { { .name = "cssys", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_0_ctrl, .ctrlbit = (1 << 6), }, { .name = "secss", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_0_ctrl, .ctrlbit = (1 << 5), }, { .name = "g2d", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_0_ctrl, .ctrlbit = (1 << 4), }, { .name = "mdma", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_0_ctrl, .ctrlbit = (1 << 3), }, { .name = "cfcon", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_0_ctrl, .ctrlbit = (1 << 2), }, { .name = "nfcon", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_1_ctrl, .ctrlbit = (1 << 3), }, { .name = "onenandc", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_1_ctrl, .ctrlbit = (1 << 2), }, { .name = "sdm", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_2_ctrl, .ctrlbit = (1 << 2), }, { .name = "seckey", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_2_ctrl, .ctrlbit = (1 << 1), }, { .name = "hsmmc", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 7), }, { .name = "hsmmc", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 6), }, { .name = "hsmmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 5), }, { .name = "modemif", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 4), }, { .name = "otg", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 3), }, { .name = "usbhost", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 2), }, { .name = "pdma", - .id = 1, + .devname = "s3c-pl330.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 1), }, { .name = "pdma", - .id = 0, + .devname = "s3c-pl330.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 0), }, { .name = "lcd", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_1_ctrl, .ctrlbit = (1 << 0), }, { .name = "rotator", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_1_ctrl, .ctrlbit = (1 << 1), }, { .name = "fimc", - .id = 0, + .devname = "s5p-fimc.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_1_ctrl, .ctrlbit = (1 << 2), }, { .name = "fimc", - .id = 1, + .devname = "s5p-fimc.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_1_ctrl, .ctrlbit = (1 << 3), }, { .name = "fimc", - .id = 2, - .parent = &clk_div_d1_bus.clk, + .devname = "s5p-fimc.2", .enable = s5pc100_d1_1_ctrl, .ctrlbit = (1 << 4), }, { .name = "jpeg", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_1_ctrl, .ctrlbit = (1 << 5), }, { .name = "mipi-dsim", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_1_ctrl, .ctrlbit = (1 << 6), }, { .name = "mipi-csis", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_1_ctrl, .ctrlbit = (1 << 7), }, { .name = "g3d", - .id = 0, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 8), }, { .name = "tv", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_2_ctrl, .ctrlbit = (1 << 0), }, { .name = "vp", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_2_ctrl, .ctrlbit = (1 << 1), }, { .name = "mixer", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_2_ctrl, .ctrlbit = (1 << 2), }, { .name = "hdmi", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_2_ctrl, .ctrlbit = (1 << 3), }, { .name = "mfc", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_2_ctrl, .ctrlbit = (1 << 4), }, { .name = "apc", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 2), }, { .name = "iec", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 3), }, { .name = "systimer", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 7), }, { .name = "watchdog", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 8), }, { .name = "rtc", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 9), }, { .name = "i2c", - .id = 0, + .devname = "s3c2440-i2c.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 4), }, { .name = "i2c", - .id = 1, + .devname = "s3c2440-i2c.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 5), }, { .name = "spi", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 6), }, { .name = "spi", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 7), }, { .name = "spi", - .id = 2, + .devname = "s3c64xx-spi.2", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 8), }, { .name = "irda", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 9), }, { .name = "ccan", - .id = 0, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 10), }, { .name = "ccan", - .id = 1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 11), }, { .name = "hsitx", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 12), }, { .name = "hsirx", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 13), }, { .name = "iis", - .id = 0, + .devname = "samsung-i2s.0", .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 0), }, { .name = "iis", - .id = 1, + .devname = "samsung-i2s.1", .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 1), }, { .name = "iis", - .id = 2, + .devname = "samsung-i2s.2", .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 2), }, { .name = "ac97", - .id = -1, .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 3), }, { .name = "pcm", - .id = 0, + .devname = "samsung-pcm.0", .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 4), }, { .name = "pcm", - .id = 1, + .devname = "samsung-pcm.1", .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 5), }, { .name = "spdif", - .id = -1, .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 6), }, { .name = "adc", - .id = -1, .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 7), }, { .name = "keypad", - .id = -1, .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 8), }, { .name = "spi_48m", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 7), }, { .name = "spi_48m", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 8), }, { .name = "spi_48m", - .id = 2, + .devname = "s3c64xx-spi.2", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 9), }, { .name = "mmc_48m", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 15), }, { .name = "mmc_48m", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 16), }, { .name = "mmc_48m", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 17), @@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = { static struct clk clk_vclk54m = { .name = "vclk_54m", - .id = -1, .rate = 54000000, }; static struct clk clk_i2scdclk0 = { .name = "i2s_cdclk0", - .id = -1, }; static struct clk clk_i2scdclk1 = { .name = "i2s_cdclk1", - .id = -1, }; static struct clk clk_i2scdclk2 = { .name = "i2s_cdclk2", - .id = -1, }; static struct clk clk_pcmcdclk0 = { .name = "pcm_cdclk0", - .id = -1, }; static struct clk clk_pcmcdclk1 = { .name = "pcm_cdclk1", - .id = -1, }; static struct clk *clk_src_group1_list[] = { @@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = { static struct clksrc_clk clk_sclk_audio0 = { .clk = { .name = "sclk_audio", - .id = 0, + .devname = "samsung-pcm.0", .ctrlbit = (1 << 8), .enable = s5pc100_sclk1_ctrl, }, @@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = { static struct clksrc_clk clk_sclk_audio1 = { .clk = { .name = "sclk_audio", - .id = 1, + .devname = "samsung-pcm.1", .ctrlbit = (1 << 9), .enable = s5pc100_sclk1_ctrl, }, @@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = { static struct clksrc_clk clk_sclk_audio2 = { .clk = { .name = "sclk_audio", - .id = 2, + .devname = "samsung-pcm.2", .ctrlbit = (1 << 10), .enable = s5pc100_sclk1_ctrl, }, @@ -1014,7 +948,6 @@ static struct clk_ops s5pc100_sclk_spdif_ops = { static struct clksrc_clk clk_sclk_spdif = { .clk = { .name = "sclk_spdif", - .id = -1, .ctrlbit = (1 << 11), .enable = s5pc100_sclk1_ctrl, .ops = &s5pc100_sclk_spdif_ops, @@ -1027,7 +960,7 @@ static struct clksrc_clk clksrcs[] = { { .clk = { .name = "sclk_spi", - .id = 0, + .devname = "s3c64xx-spi.0", .ctrlbit = (1 << 4), .enable = s5pc100_sclk0_ctrl, @@ -1038,7 +971,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 1, + .devname = "s3c64xx-spi.1", .ctrlbit = (1 << 5), .enable = s5pc100_sclk0_ctrl, @@ -1049,7 +982,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 2, + .devname = "s3c64xx-spi.2", .ctrlbit = (1 << 6), .enable = s5pc100_sclk0_ctrl, @@ -1060,7 +993,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = -1, .ctrlbit = (1 << 3), .enable = s5pc100_sclk0_ctrl, @@ -1071,7 +1003,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mixer", - .id = -1, .ctrlbit = (1 << 6), .enable = s5pc100_sclk0_ctrl, @@ -1081,7 +1012,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_lcd", - .id = -1, .ctrlbit = (1 << 0), .enable = s5pc100_sclk1_ctrl, @@ -1092,7 +1022,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 0, + .devname = "s5p-fimc.0", .ctrlbit = (1 << 1), .enable = s5pc100_sclk1_ctrl, @@ -1103,7 +1033,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 1, + .devname = "s5p-fimc.1", .ctrlbit = (1 << 2), .enable = s5pc100_sclk1_ctrl, @@ -1114,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 2, + .devname = "s5p-fimc.2", .ctrlbit = (1 << 3), .enable = s5pc100_sclk1_ctrl, @@ -1125,7 +1055,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 0, + .devname = "s3c-sdhci.0", .ctrlbit = (1 << 12), .enable = s5pc100_sclk1_ctrl, @@ -1136,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 1, + .devname = "s3c-sdhci.1", .ctrlbit = (1 << 13), .enable = s5pc100_sclk1_ctrl, @@ -1147,7 +1077,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 2, + .devname = "s3c-sdhci.2", .ctrlbit = (1 << 14), .enable = s5pc100_sclk1_ctrl, @@ -1158,7 +1088,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_irda", - .id = 2, .ctrlbit = (1 << 10), .enable = s5pc100_sclk0_ctrl, @@ -1169,7 +1098,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_irda", - .id = -1, .ctrlbit = (1 << 10), .enable = s5pc100_sclk0_ctrl, @@ -1180,7 +1108,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_pwi", - .id = -1, .ctrlbit = (1 << 1), .enable = s5pc100_sclk0_ctrl, @@ -1191,7 +1118,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_uhost", - .id = -1, .ctrlbit = (1 << 11), .enable = s5pc100_sclk0_ctrl, @@ -1291,79 +1217,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) static struct clk init_clocks[] = { { .name = "tzic", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_0_ctrl, .ctrlbit = (1 << 1), }, { .name = "intc", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_0_ctrl, .ctrlbit = (1 << 0), }, { .name = "ebi", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_1_ctrl, .ctrlbit = (1 << 5), }, { .name = "intmem", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_1_ctrl, .ctrlbit = (1 << 4), }, { .name = "sromc", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_1_ctrl, .ctrlbit = (1 << 1), }, { .name = "dmc", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_1_ctrl, .ctrlbit = (1 << 0), }, { .name = "chipid", - .id = -1, .parent = &clk_div_d0_bus.clk, .enable = s5pc100_d0_1_ctrl, .ctrlbit = (1 << 0), }, { .name = "gpio", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 1), }, { .name = "uart", - .id = 0, + .devname = "s3c6400-uart.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 0), }, { .name = "uart", - .id = 1, + .devname = "s3c6400-uart.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 1), }, { .name = "uart", - .id = 2, + .devname = "s3c6400-uart.2", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 2), }, { .name = "uart", - .id = 3, + .devname = "s3c6400-uart.3", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 3), }, { .name = "timers", - .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 6), diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do {} while (0) + +#endif diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 2d599499cefe..b5c95e663c53 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -36,7 +36,6 @@ static unsigned long xtal; static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", - .id = -1, }, .sources = &clk_src_apll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, @@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_epll = { .clk = { .name = "mout_epll", - .id = -1, }, .sources = &clk_src_epll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, @@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_mpll = { .clk = { .name = "mout_mpll", - .id = -1, }, .sources = &clk_src_mpll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, @@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = { static struct clksrc_clk clk_armclk = { .clk = { .name = "armclk", - .id = -1, }, .sources = &clkset_armclk, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, @@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = { static struct clksrc_clk clk_hclk_msys = { .clk = { .name = "hclk_msys", - .id = -1, .parent = &clk_armclk.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, @@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = { static struct clksrc_clk clk_pclk_msys = { .clk = { .name = "pclk_msys", - .id = -1, .parent = &clk_hclk_msys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, @@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = { static struct clksrc_clk clk_sclk_a2m = { .clk = { .name = "sclk_a2m", - .id = -1, .parent = &clk_mout_apll.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, @@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = { static struct clksrc_clk clk_hclk_dsys = { .clk = { .name = "hclk_dsys", - .id = -1, }, .sources = &clkset_hclk_sys, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, @@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = { static struct clksrc_clk clk_pclk_dsys = { .clk = { .name = "pclk_dsys", - .id = -1, .parent = &clk_hclk_dsys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, @@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = { static struct clksrc_clk clk_hclk_psys = { .clk = { .name = "hclk_psys", - .id = -1, }, .sources = &clkset_hclk_sys, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, @@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = { static struct clksrc_clk clk_pclk_psys = { .clk = { .name = "pclk_psys", - .id = -1, .parent = &clk_hclk_psys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, @@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", - .id = -1, .rate = 27000000, }; static struct clk clk_sclk_hdmiphy = { .name = "sclk_hdmiphy", - .id = -1, }; static struct clk clk_sclk_usbphy0 = { .name = "sclk_usbphy0", - .id = -1, }; static struct clk clk_sclk_usbphy1 = { .name = "sclk_usbphy1", - .id = -1, }; static struct clk clk_pcmcdclk0 = { .name = "pcmcdclk", - .id = -1, }; static struct clk clk_pcmcdclk1 = { .name = "pcmcdclk", - .id = -1, }; static struct clk clk_pcmcdclk2 = { .name = "pcmcdclk", - .id = -1, }; static struct clk *clkset_vpllsrc_list[] = { @@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = { static struct clksrc_clk clk_vpllsrc = { .clk = { .name = "vpll_src", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 7), }, @@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = { static struct clksrc_clk clk_sclk_vpll = { .clk = { .name = "sclk_vpll", - .id = -1, }, .sources = &clkset_sclk_vpll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, @@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = { static struct clksrc_clk clk_mout_dmc0 = { .clk = { .name = "mout_dmc0", - .id = -1, }, .sources = &clkset_moutdmc0src, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, @@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = { static struct clksrc_clk clk_sclk_dmc0 = { .clk = { .name = "sclk_dmc0", - .id = -1, .parent = &clk_mout_dmc0.clk, }, .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, @@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = { static struct clk init_clocks_off[] = { { .name = "pdma", - .id = 0, + .devname = "s3c-pl330.0", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 3), }, { .name = "pdma", - .id = 1, + .devname = "s3c-pl330.1", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 4), }, { .name = "rot", - .id = -1, .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1<<29), }, { .name = "fimc", - .id = 0, + .devname = "s5pv210-fimc.0", .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 24), }, { .name = "fimc", - .id = 1, + .devname = "s5pv210-fimc.1", .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 25), }, { .name = "fimc", - .id = 2, + .devname = "s5pv210-fimc.2", .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 26), }, { .name = "otg", - .id = -1, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<16), }, { .name = "usb-host", - .id = -1, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<17), }, { .name = "lcd", - .id = -1, .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<0), }, { .name = "cfcon", - .id = 0, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<25), }, { .name = "hsmmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<16), }, { .name = "hsmmc", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<17), }, { .name = "hsmmc", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<18), }, { .name = "hsmmc", - .id = 3, + .devname = "s3c-sdhci.3", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<19), }, { .name = "systimer", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<16), }, { .name = "watchdog", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<22), }, { .name = "rtc", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<15), }, { .name = "i2c", - .id = 0, + .devname = "s3c2440-i2c.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<7), }, { .name = "i2c", - .id = 1, + .devname = "s3c2440-i2c.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 10), }, { .name = "i2c", - .id = 2, + .devname = "s3c2440-i2c.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<9), }, { .name = "spi", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<12), }, { .name = "spi", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<13), }, { .name = "spi", - .id = 2, + .devname = "s3c64xx-spi.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<14), }, { .name = "timers", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<23), }, { .name = "adc", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<24), }, { .name = "keypad", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<21), }, { .name = "iis", - .id = 0, + .devname = "samsung-i2s.0", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<4), }, { .name = "iis", - .id = 1, + .devname = "samsung-i2s.1", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 5), }, { .name = "iis", - .id = 2, + .devname = "samsung-i2s.2", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 6), }, { .name = "spdif", - .id = -1, .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 0), @@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = { static struct clk init_clocks[] = { { .name = "hclk_imem", - .id = -1, .parent = &clk_hclk_msys.clk, .ctrlbit = (1 << 5), .enable = s5pv210_clk_ip0_ctrl, .ops = &clk_hclk_imem_ops, }, { .name = "uart", - .id = 0, + .devname = "s5pv210-uart.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 17), }, { .name = "uart", - .id = 1, + .devname = "s5pv210-uart.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 18), }, { .name = "uart", - .id = 2, + .devname = "s5pv210-uart.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 19), }, { .name = "uart", - .id = 3, + .devname = "s5pv210-uart.3", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 20), }, { .name = "sromc", - .id = -1, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1 << 26), @@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = { static struct clksrc_clk clk_sclk_dac = { .clk = { .name = "sclk_dac", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 2), }, @@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = { static struct clksrc_clk clk_sclk_pixel = { .clk = { .name = "sclk_pixel", - .id = -1, .parent = &clk_sclk_vpll.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, @@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = { static struct clksrc_clk clk_sclk_hdmi = { .clk = { .name = "sclk_hdmi", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 0), }, @@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = { static struct clksrc_clk clk_sclk_audio0 = { .clk = { .name = "sclk_audio", - .id = 0, + .devname = "soc-audio.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 24), }, @@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = { static struct clksrc_clk clk_sclk_audio1 = { .clk = { .name = "sclk_audio", - .id = 1, + .devname = "soc-audio.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 25), }, @@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = { static struct clksrc_clk clk_sclk_audio2 = { .clk = { .name = "sclk_audio", - .id = 2, + .devname = "soc-audio.2", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 26), }, @@ -763,7 +724,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = { static struct clksrc_clk clk_sclk_spdif = { .clk = { .name = "sclk_spdif", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 27), .ops = &s5pv210_sclk_spdif_ops, @@ -793,7 +753,6 @@ static struct clksrc_clk clksrcs[] = { { .clk = { .name = "sclk_dmc", - .id = -1, }, .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, @@ -801,7 +760,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_onenand", - .id = -1, }, .sources = &clkset_sclk_onenand, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, @@ -809,7 +767,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 0, + .devname = "s5pv210-uart.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 12), }, @@ -819,7 +777,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 1, + .devname = "s5pv210-uart.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 13), }, @@ -829,7 +787,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 2, + .devname = "s5pv210-uart.2", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 14), }, @@ -839,7 +797,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 3, + .devname = "s5pv210-uart.3", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 15), }, @@ -849,7 +807,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mixer", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 1), }, @@ -858,7 +815,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 0, + .devname = "s5pv210-fimc.0", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 2), }, @@ -868,7 +825,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 1, + .devname = "s5pv210-fimc.1", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 3), }, @@ -878,7 +835,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 2, + .devname = "s5pv210-fimc.2", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 4), }, @@ -888,7 +845,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_cam", - .id = 0, + .devname = "s5pv210-fimc.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 3), }, @@ -898,7 +855,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_cam", - .id = 1, + .devname = "s5pv210-fimc.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 4), }, @@ -908,7 +865,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimd", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 5), }, @@ -918,7 +874,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 0, + .devname = "s3c-sdhci.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 8), }, @@ -928,7 +884,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 1, + .devname = "s3c-sdhci.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 9), }, @@ -938,7 +894,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 2, + .devname = "s3c-sdhci.2", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 10), }, @@ -948,7 +904,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 3, + .devname = "s3c-sdhci.3", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 11), }, @@ -958,7 +914,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mfc", - .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 16), }, @@ -968,7 +923,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_g2d", - .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 12), }, @@ -978,7 +932,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_g3d", - .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 8), }, @@ -988,7 +941,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_csis", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 6), }, @@ -998,7 +950,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 0, + .devname = "s3c64xx-spi.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 16), }, @@ -1008,7 +960,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 1, + .devname = "s3c64xx-spi.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 17), }, @@ -1018,7 +970,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_pwi", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 29), }, @@ -1028,7 +979,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_pwm", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 19), }, diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do {} while (0) + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h index e8d394f8b057..3e22109e1b7b 100644 --- a/arch/arm/mach-s5pv210/include/mach/pm-core.h +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h @@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, { /* nothing here yet */ } + +static inline void s3c_pm_restored_gpios(void) { } +static inline void s3c_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S index a3d649466fb1..28dfeff342b8 100644 --- a/arch/arm/mach-s5pv210/sleep.S +++ b/arch/arm/mach-s5pv210/sleep.S @@ -39,18 +39,14 @@ */ ENTRY(s3c_cpu_save) + adr r3, BSYM(s5pv210_finish_suspend) + b cpu_suspend - stmfd sp!, { r3 - r12, lr } - ldr r3, =resume_with_mmu - bl cpu_suspend - +s5pv210_finish_suspend: ldr r0, =pm_cpu_sleep ldr r0, [ r0 ] mov pc, r0 -resume_with_mmu: - ldmfd sp!, { r3 - r12, pc } - .ltorg /* sleep magic, to allow the bootloader to check for an valid diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S index 04f2a618d4ef..e814b603c710 100644 --- a/arch/arm/mach-sa1100/sleep.S +++ b/arch/arm/mach-sa1100/sleep.S @@ -29,11 +29,14 @@ */ ENTRY(sa1100_cpu_suspend) - stmfd sp!, {r4 - r12, lr} @ save registers on stack + mov r9, lr mov r1, r0 - ldr r3, =sa1100_cpu_resume @ return function + adr r3, BSYM(sa1100_finish_suspend) bl cpu_suspend + mcr p15, 0, r1, c15, c1, 2 @ enable clock switching + mov pc, r9 @ return to caller +sa1100_finish_suspend: @ disable clock switching mcr p15, 0, r1, c15, c2, 2 @@ -139,13 +142,3 @@ sa1110_sdram_controller_fix: str r13, [r12] 20: b 20b @ loop waiting for sleep - -/* - * cpu_sa1100_resume() - * - * entry point from bootloader into kernel during resume - */ - .align 5 -sa1100_cpu_resume: - mcr p15, 0, r1, c15, c1, 2 @ enable clock switching - ldmfd sp!, {r4 - r12, pc} @ return to caller diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index c95258c274c1..1e2aba23e0d6 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -382,10 +382,8 @@ void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state) } static struct sh_mobile_sdhi_info sh_sdhi1_platdata = { - .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, - .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, - .tmio_caps = MMC_CAP_NONREMOVABLE, + .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ, .tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .set_pwr = ag5evm_sdhi1_set_pwr, }; diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 776f20560e72..7e1d37584321 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -126,7 +126,7 @@ * ------+--------------------+--------------------+------- * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High - * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Tuch Panel | Low + * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Touch Panel | Low * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High @@ -165,10 +165,10 @@ * USB1 can become Host by r8a66597, and become Function by renesas_usbhs. * But don't select both drivers in same time. * These uses same IRQ number for request_irq(), and aren't supporting - * IRQF_SHARD / IORESOURCE_IRQ_SHAREABLE. + * IRQF_SHARED / IORESOURCE_IRQ_SHAREABLE. * * Actually these are old/new version of USB driver. - * This mean its register will be broken if it supports SHARD IRQ, + * This mean its register will be broken if it supports shared IRQ, */ /* @@ -562,7 +562,121 @@ out: clk_put(hdmi_ick); } -/* USB1 (Host) */ +/* USBHS0 is connected to CN22 which takes a USB Mini-B plug + * + * The sh7372 SoC has IRQ7 set aside for USBHS0 hotplug, + * but on this particular board IRQ7 is already used by + * the touch screen. This leaves us with software polling. + */ +#define USBHS0_POLL_INTERVAL (HZ * 5) + +struct usbhs_private { + unsigned int usbphyaddr; + unsigned int usbcrcaddr; + struct renesas_usbhs_platform_info info; + struct delayed_work work; + struct platform_device *pdev; +}; + +#define usbhs_get_priv(pdev) \ + container_of(renesas_usbhs_get_info(pdev), \ + struct usbhs_private, info) + +#define usbhs_is_connected(priv) \ + (!((1 << 7) & __raw_readw(priv->usbcrcaddr))) + +static int usbhs_get_vbus(struct platform_device *pdev) +{ + return usbhs_is_connected(usbhs_get_priv(pdev)); +} + +static void usbhs_phy_reset(struct platform_device *pdev) +{ + struct usbhs_private *priv = usbhs_get_priv(pdev); + + /* init phy */ + __raw_writew(0x8a0a, priv->usbcrcaddr); +} + +static int usbhs0_get_id(struct platform_device *pdev) +{ + return USBHS_GADGET; +} + +static void usbhs0_work_function(struct work_struct *work) +{ + struct usbhs_private *priv = container_of(work, struct usbhs_private, + work.work); + + renesas_usbhs_call_notify_hotplug(priv->pdev); + schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL); +} + +static int usbhs0_hardware_init(struct platform_device *pdev) +{ + struct usbhs_private *priv = usbhs_get_priv(pdev); + + priv->pdev = pdev; + INIT_DELAYED_WORK(&priv->work, usbhs0_work_function); + schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL); + return 0; +} + +static void usbhs0_hardware_exit(struct platform_device *pdev) +{ + struct usbhs_private *priv = usbhs_get_priv(pdev); + + cancel_delayed_work_sync(&priv->work); +} + +static struct usbhs_private usbhs0_private = { + .usbcrcaddr = 0xe605810c, /* USBCR2 */ + .info = { + .platform_callback = { + .hardware_init = usbhs0_hardware_init, + .hardware_exit = usbhs0_hardware_exit, + .phy_reset = usbhs_phy_reset, + .get_id = usbhs0_get_id, + .get_vbus = usbhs_get_vbus, + }, + .driver_param = { + .buswait_bwait = 4, + }, + }, +}; + +static struct resource usbhs0_resources[] = { + [0] = { + .name = "USBHS0", + .start = 0xe6890000, + .end = 0xe68900e6 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x1ca0) /* USB0_USB0I0 */, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usbhs0_device = { + .name = "renesas_usbhs", + .id = 0, + .dev = { + .platform_data = &usbhs0_private.info, + }, + .num_resources = ARRAY_SIZE(usbhs0_resources), + .resource = usbhs0_resources, +}; + +/* USBHS1 is connected to CN31 which takes a USB Mini-AB plug + * + * Use J30 to select between Host and Function. This setting + * can however not be detected by software. Hotplug of USBHS1 + * is provided via IRQ8. + */ +#define IRQ8 evt2irq(0x0300) + +/* USBHS1 USB Host support via r8a66597_hcd */ static void usb1_host_port_power(int port, int power) { if (!power) /* only power-on is supported for now */ @@ -579,9 +693,9 @@ static struct r8a66597_platdata usb1_host_data = { static struct resource usb1_host_resources[] = { [0] = { - .name = "USBHS", - .start = 0xE68B0000, - .end = 0xE68B00E6 - 1, + .name = "USBHS1", + .start = 0xe68b0000, + .end = 0xe68b00e6 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -602,37 +716,14 @@ static struct platform_device usb1_host_device = { .resource = usb1_host_resources, }; -/* USB1 (Function) */ +/* USBHS1 USB Function support via renesas_usbhs */ + #define USB_PHY_MODE (1 << 4) #define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) #define USB_PHY_ON (1 << 1) #define USB_PHY_OFF (1 << 0) #define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF) -struct usbhs_private { - unsigned int irq; - unsigned int usbphyaddr; - unsigned int usbcrcaddr; - struct renesas_usbhs_platform_info info; -}; - -#define usbhs_get_priv(pdev) \ - container_of(renesas_usbhs_get_info(pdev), \ - struct usbhs_private, info) - -#define usbhs_is_connected(priv) \ - (!((1 << 7) & __raw_readw(priv->usbcrcaddr))) - -static int usbhs1_get_id(struct platform_device *pdev) -{ - return USBHS_GADGET; -} - -static int usbhs1_get_vbus(struct platform_device *pdev) -{ - return usbhs_is_connected(usbhs_get_priv(pdev)); -} - static irqreturn_t usbhs1_interrupt(int irq, void *data) { struct platform_device *pdev = data; @@ -654,12 +745,10 @@ static int usbhs1_hardware_init(struct platform_device *pdev) struct usbhs_private *priv = usbhs_get_priv(pdev); int ret; - irq_set_irq_type(priv->irq, IRQ_TYPE_LEVEL_HIGH); - /* clear interrupt status */ __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr); - ret = request_irq(priv->irq, usbhs1_interrupt, 0, + ret = request_irq(IRQ8, usbhs1_interrupt, IRQF_TRIGGER_HIGH, dev_name(&pdev->dev), pdev); if (ret) { dev_err(&pdev->dev, "request_irq err\n"); @@ -679,15 +768,12 @@ static void usbhs1_hardware_exit(struct platform_device *pdev) /* clear interrupt status */ __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr); - free_irq(priv->irq, pdev); + free_irq(IRQ8, pdev); } -static void usbhs1_phy_reset(struct platform_device *pdev) +static int usbhs1_get_id(struct platform_device *pdev) { - struct usbhs_private *priv = usbhs_get_priv(pdev); - - /* init phy */ - __raw_writew(0x8a0a, priv->usbcrcaddr); + return USBHS_GADGET; } static u32 usbhs1_pipe_cfg[] = { @@ -710,16 +796,15 @@ static u32 usbhs1_pipe_cfg[] = { }; static struct usbhs_private usbhs1_private = { - .irq = evt2irq(0x0300), /* IRQ8 */ - .usbphyaddr = 0xE60581E2, /* USBPHY1INTAP */ - .usbcrcaddr = 0xE6058130, /* USBCR4 */ + .usbphyaddr = 0xe60581e2, /* USBPHY1INTAP */ + .usbcrcaddr = 0xe6058130, /* USBCR4 */ .info = { .platform_callback = { .hardware_init = usbhs1_hardware_init, .hardware_exit = usbhs1_hardware_exit, - .phy_reset = usbhs1_phy_reset, .get_id = usbhs1_get_id, - .get_vbus = usbhs1_get_vbus, + .phy_reset = usbhs_phy_reset, + .get_vbus = usbhs_get_vbus, }, .driver_param = { .buswait_bwait = 4, @@ -731,9 +816,9 @@ static struct usbhs_private usbhs1_private = { static struct resource usbhs1_resources[] = { [0] = { - .name = "USBHS", - .start = 0xE68B0000, - .end = 0xE68B00E6 - 1, + .name = "USBHS1", + .start = 0xe68b0000, + .end = 0xe68b00e6 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -752,7 +837,6 @@ static struct platform_device usbhs1_device = { .resource = usbhs1_resources, }; - /* LED */ static struct gpio_led mackerel_leds[] = { { @@ -1203,6 +1287,7 @@ static struct platform_device *mackerel_devices[] __initdata = { &nor_flash_device, &smc911x_device, &lcdc_device, + &usbhs0_device, &usb1_host_device, &usbhs1_device, &leds_device, @@ -1301,6 +1386,7 @@ static void __init mackerel_map_io(void) #define GPIO_PORT9CR 0xE6051009 #define GPIO_PORT10CR 0xE605100A +#define GPIO_PORT167CR 0xE60520A7 #define GPIO_PORT168CR 0xE60520A8 #define SRCR4 0xe61580bc #define USCCR1 0xE6058144 @@ -1354,17 +1440,17 @@ static void __init mackerel_init(void) gpio_request(GPIO_PORT151, NULL); /* LCDDON */ gpio_direction_output(GPIO_PORT151, 1); - /* USB enable */ - gpio_request(GPIO_FN_VBUS0_1, NULL); - gpio_request(GPIO_FN_IDIN_1_18, NULL); - gpio_request(GPIO_FN_PWEN_1_115, NULL); - gpio_request(GPIO_FN_OVCN_1_114, NULL); - gpio_request(GPIO_FN_EXTLP_1, NULL); - gpio_request(GPIO_FN_OVCN2_1, NULL); - gpio_pull_down(GPIO_PORT168CR); - - /* setup USB phy */ - __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ + /* USBHS0 */ + gpio_request(GPIO_FN_VBUS0_0, NULL); + gpio_pull_down(GPIO_PORT168CR); /* VBUS0_0 pull down */ + + /* USBHS1 */ + gpio_request(GPIO_FN_VBUS0_1, NULL); + gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */ + gpio_request(GPIO_FN_IDIN_1_113, NULL); + + /* USB phy tweak to make the r8a66597_hcd host driver work */ + __raw_writew(0x8a0a, 0xe6058130); /* USBCR4 */ /* enable FSI2 port A (ak4643) */ gpio_request(GPIO_FN_FSIAIBT, NULL); diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index 5d0e1503ece6..a911a60e7719 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -250,6 +250,11 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id) return IRQ_HANDLED; } +static int sh73a0_set_wake(struct irq_data *data, unsigned int on) +{ + return 0; /* always allow wakeup */ +} + void __init sh73a0_init_irq(void) { void __iomem *gic_dist_base = __io(0xf0001000); @@ -257,6 +262,7 @@ void __init sh73a0_init_irq(void) void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); gic_init(0, 29, gic_dist_base, gic_cpu_base); + gic_arch_extn.irq_set_wake = sh73a0_set_wake; register_intc_controller(&intcs_desc); diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c index 2c10190dbb55..e546017f15de 100644 --- a/arch/arm/mach-shmobile/setup-sh7367.c +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@ -38,7 +38,7 @@ static struct plat_sci_port scif0_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIF, + .type = PORT_SCIFA, .irqs = { evt2irq(0xc00), evt2irq(0xc00), evt2irq(0xc00), evt2irq(0xc00) }, }; @@ -57,7 +57,7 @@ static struct plat_sci_port scif1_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIF, + .type = PORT_SCIFA, .irqs = { evt2irq(0xc20), evt2irq(0xc20), evt2irq(0xc20), evt2irq(0xc20) }, }; @@ -76,7 +76,7 @@ static struct plat_sci_port scif2_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIF, + .type = PORT_SCIFA, .irqs = { evt2irq(0xc40), evt2irq(0xc40), evt2irq(0xc40), evt2irq(0xc40) }, }; @@ -95,7 +95,7 @@ static struct plat_sci_port scif3_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIF, + .type = PORT_SCIFA, .irqs = { evt2irq(0xc60), evt2irq(0xc60), evt2irq(0xc60), evt2irq(0xc60) }, }; @@ -114,7 +114,7 @@ static struct plat_sci_port scif4_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIF, + .type = PORT_SCIFA, .irqs = { evt2irq(0xd20), evt2irq(0xd20), evt2irq(0xd20), evt2irq(0xd20) }, }; @@ -133,7 +133,7 @@ static struct plat_sci_port scif5_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIF, + .type = PORT_SCIFA, .irqs = { evt2irq(0xd40), evt2irq(0xd40), evt2irq(0xd40), evt2irq(0xd40) }, }; @@ -152,7 +152,7 @@ static struct plat_sci_port scif6_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, - .type = PORT_SCIF, + .type = PORT_SCIFB, .irqs = { evt2irq(0xd60), evt2irq(0xd60), evt2irq(0xd60), evt2irq(0xd60) }, }; diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h index c34f3ea3017c..4f50ca8f901e 100644 --- a/arch/arm/mach-u300/clock.h +++ b/arch/arm/mach-u300/clock.h @@ -31,7 +31,7 @@ struct clk { bool reset; __u16 clk_val; __s8 usecount; - __u32 res_reg; + void __iomem * res_reg; __u16 res_mask; bool hw_ctrld; diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h index 8b85df4c8d8f..035fdc9dbdb0 100644 --- a/arch/arm/mach-u300/include/mach/u300-regs.h +++ b/arch/arm/mach-u300/include/mach/u300-regs.h @@ -18,6 +18,12 @@ * the defines are used for setting up the I/O memory mapping. */ +#ifdef __ASSEMBLER__ +#define IOMEM(a) (a) +#else +#define IOMEM(a) (void __iomem *) a +#endif + /* NAND Flash CS0 */ #define U300_NAND_CS0_PHYS_BASE 0x80000000 @@ -48,13 +54,6 @@ #endif /* - * All the following peripherals are specified at their PHYSICAL address, - * so if you need to access them (in the kernel), you MUST use the macros - * defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST() - * etc. - */ - -/* * AHB peripherals */ @@ -63,11 +62,11 @@ /* Vectored Interrupt Controller 0, servicing 32 interrupts */ #define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) -#define U300_INTCON0_VBASE (U300_AHB_PER_VIRT_BASE+0x1000) +#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000) /* Vectored Interrupt Controller 1, servicing 32 interrupts */ #define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) -#define U300_INTCON1_VBASE (U300_AHB_PER_VIRT_BASE+0x2000) +#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000) /* Memory Stick Pro (MSPRO) controller */ #define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) @@ -115,7 +114,7 @@ /* SYSCON */ #define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) -#define U300_SYSCON_VBASE (U300_SLOW_PER_VIRT_BASE+0x1000) +#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000) /* Watchdog */ #define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) @@ -125,7 +124,7 @@ /* APP side special timer */ #define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) -#define U300_TIMER_APP_VBASE (U300_SLOW_PER_VIRT_BASE+0x4000) +#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000) /* Keypad */ #define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) @@ -181,5 +180,4 @@ * Virtual accessor macros for static devices */ - #endif diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 891cf44591e0..18d7fa0603c2 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -411,8 +411,7 @@ static void __init u300_timer_init(void) /* Use general purpose timer 2 as clock source */ if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) - printk(KERN_ERR "timer: failed to initialize clock " - "source %s\n", clocksource_u300_1mhz.name); + pr_err("timer: failed to initialize U300 clock source\n"); clockevents_calc_mult_shift(&clockevent_u300_1mhz, rate, APPTIMER_MIN_RANGE); diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index f8b9392ee347..96d546cef062 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -20,7 +20,7 @@ config UX500_SOC_DB8500 endmenu -menu "Ux500 target platform" +menu "Ux500 target platform (boards)" config MACH_U8500 bool "U8500 Development platform" @@ -29,6 +29,12 @@ config MACH_U8500 help Include support for the mop500 development platform. +config MACH_HREFV60 + bool "U85000 Development platform, HREFv60 version" + depends on UX500_SOC_DB8500 + help + Include support for the HREFv60 new development platform. + config MACH_U5500 bool "U5500 Development platform" depends on UX500_SOC_DB5500 diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index fd4cf1ca5efd..70cdbd60596a 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -110,10 +110,18 @@ static pin_cfg_t mop500_pins_common[] = { GPIO168_KP_O0, /* UART */ - GPIO0_U0_CTSn | PIN_INPUT_PULLUP, - GPIO1_U0_RTSn | PIN_OUTPUT_HIGH, - GPIO2_U0_RXD | PIN_INPUT_PULLUP, - GPIO3_U0_TXD | PIN_OUTPUT_HIGH, + /* uart-0 pins gpio configuration should be + * kept intact to prevent glitch in tx line + * when tty dev is opened. Later these pins + * are configured to uart mop500_pins_uart0 + * + * It will be replaced with uart configuration + * once the issue is solved. + */ + GPIO0_GPIO | PIN_INPUT_PULLUP, + GPIO1_GPIO | PIN_OUTPUT_HIGH, + GPIO2_GPIO | PIN_INPUT_PULLUP, + GPIO3_GPIO | PIN_OUTPUT_HIGH, GPIO29_U2_RXD | PIN_INPUT_PULLUP, GPIO30_U2_TXD | PIN_OUTPUT_HIGH, diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 9ed0f90cfe23..c0bc833df903 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -272,7 +272,14 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { .max_uV = 2900000, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, /* must be on for display */ + .boot_on = 1, /* display is on at boot */ + /* + * This voltage cannot be disabled right now because + * it is somehow affecting the external MMC + * functionality, though that typically will use + * AUX3. + */ + .always_on = 1, }, .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), .consumer_supplies = ab8500_vaux1_consumers, diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 7c6cb4fa47a9..5fbd6bc63cb1 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -32,13 +32,32 @@ #define MCI_DATA31DIREN (1 << 5) #define MCI_FBCLKEN (1 << 7) +/* GPIO pins used by the sdi0 level shifter */ +static int sdi0_en = -1; +static int sdi0_vsel = -1; + static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd, unsigned char power_mode) { - if (power_mode == MMC_POWER_UP) - gpio_set_value_cansleep(GPIO_SDMMC_EN, 1); - else if (power_mode == MMC_POWER_OFF) - gpio_set_value_cansleep(GPIO_SDMMC_EN, 0); + switch (power_mode) { + case MMC_POWER_UP: + case MMC_POWER_ON: + /* + * Level shifter voltage should depend on vdd to when deciding + * on either 1.8V or 2.9V. Once the decision has been made the + * level shifter must be disabled and re-enabled with a changed + * select signal in order to switch the voltage. Since there is + * no framework support yet for indicating 1.8V in vdd, use the + * default 2.9V. + */ + gpio_direction_output(sdi0_vsel, 0); + gpio_direction_output(sdi0_en, 1); + break; + case MMC_POWER_OFF: + gpio_direction_output(sdi0_vsel, 0); + gpio_direction_output(sdi0_en, 0); + break; + } return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN | MCI_DATA2DIREN | MCI_DATA31DIREN; @@ -67,8 +86,10 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { static struct mmci_platform_data mop500_sdi0_data = { .vdd_handler = mop500_sdi0_vdd_handler, .ocr_mask = MMC_VDD_29_30, - .f_max = 100000000, - .capabilities = MMC_CAP_4_BIT_DATA, + .f_max = 50000000, + .capabilities = MMC_CAP_4_BIT_DATA | + MMC_CAP_SD_HIGHSPEED | + MMC_CAP_MMC_HIGHSPEED, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, @@ -77,10 +98,6 @@ static struct mmci_platform_data mop500_sdi0_data = { #endif }; -/* GPIO pins used by the sdi0 level shifter */ -static int sdi0_en = -1; -static int sdi0_vsel = -1; - static void sdi0_configure(void) { int ret; @@ -140,7 +157,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { static struct mmci_platform_data mop500_sdi2_data = { .ocr_mask = MMC_VDD_165_195, - .f_max = 100000000, + .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_cd = -1, .gpio_wp = -1, @@ -177,7 +194,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { static struct mmci_platform_data mop500_sdi4_data = { .ocr_mask = MMC_VDD_29_30, - .f_max = 100000000, + .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED, .gpio_cd = -1, @@ -210,6 +227,7 @@ void __init mop500_sdi_init(void) sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; sdi0_configure(); } + /* * On boards with the TC35892 GPIO expander, sdi0 will finally * be added when the TC35892 initializes and calls diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index bb26f40493e6..096c41641aa7 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -27,18 +27,21 @@ #include <linux/leds-lp5521.h> #include <linux/input.h> #include <linux/gpio_keys.h> +#include <linux/delay.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <plat/i2c.h> #include <plat/ste_dma40.h> +#include <plat/pincfg.h> #include <mach/hardware.h> #include <mach/setup.h> #include <mach/devices.h> #include <mach/irqs.h> +#include "pins-db8500.h" #include "ste-dma40-db8500.h" #include "devices-db8500.h" #include "board-mop500.h" @@ -393,12 +396,63 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = { }; #endif + +static pin_cfg_t mop500_pins_uart0[] = { + GPIO0_U0_CTSn | PIN_INPUT_PULLUP, + GPIO1_U0_RTSn | PIN_OUTPUT_HIGH, + GPIO2_U0_RXD | PIN_INPUT_PULLUP, + GPIO3_U0_TXD | PIN_OUTPUT_HIGH, +}; + +#define PRCC_K_SOFTRST_SET 0x18 +#define PRCC_K_SOFTRST_CLEAR 0x1C +static void ux500_uart0_reset(void) +{ + void __iomem *prcc_rst_set, *prcc_rst_clr; + + prcc_rst_set = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE + + PRCC_K_SOFTRST_SET); + prcc_rst_clr = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE + + PRCC_K_SOFTRST_CLEAR); + + /* Activate soft reset PRCC_K_SOFTRST_CLEAR */ + writel((readl(prcc_rst_clr) | 0x1), prcc_rst_clr); + udelay(1); + + /* Release soft reset PRCC_K_SOFTRST_SET */ + writel((readl(prcc_rst_set) | 0x1), prcc_rst_set); + udelay(1); +} + +static void ux500_uart0_init(void) +{ + int ret; + + ret = nmk_config_pins(mop500_pins_uart0, + ARRAY_SIZE(mop500_pins_uart0)); + if (ret < 0) + pr_err("pl011: uart pins_enable failed\n"); +} + +static void ux500_uart0_exit(void) +{ + int ret; + + ret = nmk_config_pins_sleep(mop500_pins_uart0, + ARRAY_SIZE(mop500_pins_uart0)); + if (ret < 0) + pr_err("pl011: uart pins_disable failed\n"); +} + static struct amba_pl011_data uart0_plat = { #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &uart0_dma_cfg_rx, .dma_tx_param = &uart0_dma_cfg_tx, #endif + .init = ux500_uart0_init, + .exit = ux500_uart0_exit, + .reset = ux500_uart0_reset, }; static struct amba_pl011_data uart1_plat = { @@ -458,6 +512,9 @@ static void __init mop500_init_machine(void) i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(2, mop500_i2c2_devices, ARRAY_SIZE(mop500_i2c2_devices)); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); } MACHINE_START(U8500, "ST-Ericsson MOP500 platform") diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index c01bc19e3c5e..22705d246fc7 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -44,6 +44,7 @@ static struct map_desc u5500_io_desc[] __initdata = { __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K), __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K), __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), + __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), }; static struct resource db5500_pmu_resources[] = { diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 285edcd2da2a..9e6b93b1a043 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -46,12 +46,6 @@ static struct map_desc v2m_io_desc[] __initdata = { }, }; -static void __init v2m_init_early(void) -{ - ct_desc->init_early(); - versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000); -} - static void __init v2m_timer_init(void) { u32 scctrl; @@ -365,6 +359,13 @@ static struct clk_lookup v2m_lookups[] = { }, }; +static void __init v2m_init_early(void) +{ + ct_desc->init_early(); + clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups)); + versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000); +} + static void v2m_power_off(void) { if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0)) @@ -418,8 +419,6 @@ static void __init v2m_init(void) { int i; - clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups)); - platform_device_register(&v2m_pcie_i2c_device); platform_device_register(&v2m_ddc_i2c_device); platform_device_register(&v2m_flash_device); diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile new file mode 100644 index 000000000000..c550c67aa893 --- /dev/null +++ b/arch/arm/mach-zynq/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the linux kernel. +# + +# Common support +obj-y := common.o timer.o board_dt.o diff --git a/arch/arm/mach-zynq/Makefile.boot b/arch/arm/mach-zynq/Makefile.boot new file mode 100644 index 000000000000..67039c3e0c48 --- /dev/null +++ b/arch/arm/mach-zynq/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-zynq/board_dt.c b/arch/arm/mach-zynq/board_dt.c new file mode 100644 index 000000000000..5b4710d09258 --- /dev/null +++ b/arch/arm/mach-zynq/board_dt.c @@ -0,0 +1,37 @@ +/* + * This file contains code for boards with device tree support. + * + * Copyright (C) 2011 Xilinx + * + * based on arch/arm/mach-realview/core.c + * + * Copyright (C) 1999 - 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/of.h> +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include "common.h" + +static const char *xilinx_dt_match[] = { + "xlnx,zynq-ep107", + NULL +}; + +MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") + .map_io = xilinx_map_io, + .init_irq = xilinx_irq_init, + .init_machine = xilinx_init_machine, + .timer = &xttcpss_sys_timer, + .dt_compat = xilinx_dt_match, +MACHINE_END diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c new file mode 100644 index 000000000000..b3ac5c2e12dc --- /dev/null +++ b/arch/arm/mach-zynq/common.c @@ -0,0 +1,102 @@ +/* + * This file contains common code that is intended to be used across + * boards so that it's not replicated. + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/cpumask.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> + +#include <asm/mach/map.h> +#include <asm/page.h> +#include <asm/hardware/gic.h> +#include <asm/hardware/cache-l2x0.h> + +#include <mach/zynq_soc.h> +#include <mach/clkdev.h> +#include "common.h" + +static struct of_device_id zynq_of_bus_ids[] __initdata = { + { .compatible = "simple-bus", }, + {} +}; + +/** + * xilinx_init_machine() - System specific initialization, intended to be + * called from board specific initialization. + */ +void __init xilinx_init_machine(void) +{ +#ifdef CONFIG_CACHE_L2X0 + /* + * 64KB way size, 8-way associativity, parity disabled + */ + l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF); +#endif + + of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); +} + +/** + * xilinx_irq_init() - Interrupt controller initialization for the GIC. + */ +void __init xilinx_irq_init(void) +{ + gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); +} + +/* The minimum devices needed to be mapped before the VM system is up and + * running include the GIC, UART and Timer Counter. + */ + +static struct map_desc io_desc[] __initdata = { + { + .virtual = TTC0_VIRT, + .pfn = __phys_to_pfn(TTC0_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = SCU_PERIPH_VIRT, + .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), + .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = PL310_L2CC_VIRT, + .pfn = __phys_to_pfn(PL310_L2CC_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, + +#ifdef CONFIG_DEBUG_LL + { + .virtual = UART0_VIRT, + .pfn = __phys_to_pfn(UART0_PHYS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif + +}; + +/** + * xilinx_map_io() - Create memory mappings needed for early I/O. + */ +void __init xilinx_map_io(void) +{ + iotable_init(io_desc, ARRAY_SIZE(io_desc)); +} diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h new file mode 100644 index 000000000000..bca21968f80b --- /dev/null +++ b/arch/arm/mach-zynq/common.h @@ -0,0 +1,29 @@ +/* + * This file contains common function prototypes to avoid externs + * in the c files. + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_ZYNQ_COMMON_H__ +#define __MACH_ZYNQ_COMMON_H__ + +#include <linux/init.h> +#include <asm/mach/time.h> + +extern void xilinx_init_machine(void); +extern void xilinx_irq_init(void); +extern void xilinx_map_io(void); + +extern struct sys_timer xttcpss_sys_timer; + +#endif diff --git a/arch/arm/mach-zynq/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/clkdev.h new file mode 100644 index 000000000000..c6e73d81a459 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/clkdev.h @@ -0,0 +1,32 @@ +/* + * arch/arm/mach-zynq/include/mach/clkdev.h + * + * Copyright (C) 2011 Xilinx, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +#include <plat/clock.h> + +struct clk { + unsigned long rate; + const struct clk_ops *ops; + const struct icst_params *params; + void __iomem *vcoreg; +}; + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-zynq/include/mach/debug-macro.S b/arch/arm/mach-zynq/include/mach/debug-macro.S new file mode 100644 index 000000000000..9f664d5eb81d --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* arch/arm/mach-zynq/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/zynq_soc.h> +#include <mach/uart.h> + + .macro addruart, rp, rv + ldr \rp, =LL_UART_PADDR @ physical + ldr \rv, =LL_UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register + tst \rd, #UART_SR_TXFULL @ + bne 1002b @ wait if FIFO is full + .endm diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S new file mode 100644 index 000000000000..3cfc01b37461 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/entry-macro.S @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-zynq/include/mach/entry-macro.S + * + * Low-level IRQ helper macros + * + * Copyright (C) 2011 Xilinx + * + * based on arch/plat-mxc/include/mach/entry-macro.S + * + * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/hardware.h> +#include <asm/hardware/entry-macro-gic.S> + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h new file mode 100644 index 000000000000..d558d8a94be7 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-zynq/include/mach/hardware.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_HARDWARE_H__ +#define __MACH_HARDWARE_H__ + +#endif diff --git a/arch/arm/mach-zynq/include/mach/io.h b/arch/arm/mach-zynq/include/mach/io.h new file mode 100644 index 000000000000..39d9885e0e9a --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/io.h @@ -0,0 +1,33 @@ +/* arch/arm/mach-zynq/include/mach/io.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IO_H__ +#define __MACH_IO_H__ + +/* Allow IO space to be anywhere in the memory */ + +#define IO_SPACE_LIMIT 0xffff + +/* IO address mapping macros, nothing special at this time but required */ + +#ifdef __ASSEMBLER__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-zynq/include/mach/irqs.h b/arch/arm/mach-zynq/include/mach/irqs.h new file mode 100644 index 000000000000..5fb04fd3bac8 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/irqs.h @@ -0,0 +1,21 @@ +/* arch/arm/mach-zynq/include/mach/irqs.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define ARCH_NR_GPIOS 118 +#define NR_IRQS (128 + ARCH_NR_GPIOS) + +#endif diff --git a/arch/arm/mach-zynq/include/mach/memory.h b/arch/arm/mach-zynq/include/mach/memory.h new file mode 100644 index 000000000000..35a92634dcc1 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/memory.h @@ -0,0 +1,22 @@ +/* arch/arm/mach-zynq/include/mach/memory.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_MEMORY_H__ +#define __MACH_MEMORY_H__ + +#include <asm/sizes.h> + +#define PLAT_PHYS_OFFSET UL(0x0) + +#endif diff --git a/arch/arm/mach-zynq/include/mach/system.h b/arch/arm/mach-zynq/include/mach/system.h new file mode 100644 index 000000000000..1b84d705c675 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/system.h @@ -0,0 +1,28 @@ +/* arch/arm/mach-zynq/include/mach/system.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_SYSTEM_H__ +#define __MACH_SYSTEM_H__ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + /* Add architecture specific reset processing here */ +} + +#endif diff --git a/arch/arm/mach-zynq/include/mach/timex.h b/arch/arm/mach-zynq/include/mach/timex.h new file mode 100644 index 000000000000..6c0245e42a5e --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/timex.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-zynq/include/mach/timex.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_TIMEX_H__ +#define __MACH_TIMEX_H__ + +/* the following is needed for the system to build but will be removed + in the future, the value is not important but won't hurt +*/ +#define CLOCK_TICK_RATE (100 * HZ) + +#endif diff --git a/arch/arm/mach-zynq/include/mach/uart.h b/arch/arm/mach-zynq/include/mach/uart.h new file mode 100644 index 000000000000..5c47c97156f3 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/uart.h @@ -0,0 +1,25 @@ +/* arch/arm/mach-zynq/include/mach/uart.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UART_H__ +#define __MACH_UART_H__ + +#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ +#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ +#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ + +#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ + +#endif diff --git a/arch/arm/mach-zynq/include/mach/uncompress.h b/arch/arm/mach-zynq/include/mach/uncompress.h new file mode 100644 index 000000000000..af4e8447bfa3 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/uncompress.h @@ -0,0 +1,51 @@ +/* arch/arm/mach-zynq/include/mach/uncompress.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_UNCOMPRESS_H__ +#define __MACH_UNCOMPRESS_H__ + +#include <linux/io.h> +#include <asm/processor.h> +#include <mach/zynq_soc.h> +#include <mach/uart.h> + +void arch_decomp_setup(void) +{ +} + +static inline void flush(void) +{ + /* + * Wait while the FIFO is not empty + */ + while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXEMPTY)) + cpu_relax(); +} + +#define arch_decomp_wdog() + +static void putc(char ch) +{ + /* + * Wait for room in the FIFO, then write the char into the FIFO + */ + while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & + UART_SR_TXFULL) + cpu_relax(); + + __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET)); +} + +#endif diff --git a/arch/arm/mach-zynq/include/mach/vmalloc.h b/arch/arm/mach-zynq/include/mach/vmalloc.h new file mode 100644 index 000000000000..2398eff1e8b8 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* arch/arm/mach-zynq/include/mach/vmalloc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_VMALLOC_H__ +#define __MACH_VMALLOC_H__ + +#define VMALLOC_END 0xE0000000UL + +#endif diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h new file mode 100644 index 000000000000..d0d3f8fb06dd --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -0,0 +1,48 @@ +/* arch/arm/mach-zynq/include/mach/zynq_soc.h + * + * Copyright (C) 2011 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_XILINX_SOC_H__ +#define __MACH_XILINX_SOC_H__ + +#define PERIPHERAL_CLOCK_RATE 2500000 + +/* For now, all mappings are flat (physical = virtual) + */ +#define UART0_PHYS 0xE0000000 +#define UART0_VIRT UART0_PHYS + +#define TTC0_PHYS 0xF8001000 +#define TTC0_VIRT TTC0_PHYS + +#define PL310_L2CC_PHYS 0xF8F02000 +#define PL310_L2CC_VIRT PL310_L2CC_PHYS + +#define SCU_PERIPH_PHYS 0xF8F00000 +#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS + +/* The following are intended for the devices that are mapped early */ + +#define TTC0_BASE IOMEM(TTC0_VIRT) +#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) +#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) +#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) +#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) + +/* + * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical + */ +#define LL_UART_PADDR UART0_PHYS +#define LL_UART_VADDR UART0_VIRT + +#endif diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c new file mode 100644 index 000000000000..c2c96cc7d6e7 --- /dev/null +++ b/arch/arm/mach-zynq/timer.c @@ -0,0 +1,298 @@ +/* + * This file contains driver for the Xilinx PS Timer Counter IP. + * + * Copyright (C) 2011 Xilinx + * + * based on arch/mips/kernel/time.c timer driver + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/types.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/io.h> + +#include <asm/mach/time.h> +#include <mach/zynq_soc.h> +#include "common.h" + +#define IRQ_TIMERCOUNTER0 42 + +/* + * This driver configures the 2 16-bit count-up timers as follows: + * + * T1: Timer 1, clocksource for generic timekeeping + * T2: Timer 2, clockevent source for hrtimers + * T3: Timer 3, <unused> + * + * The input frequency to the timer module for emulation is 2.5MHz which is + * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, + * the timers are clocked at 78.125KHz (12.8 us resolution). + * + * The input frequency to the timer module in silicon will be 200MHz. With the + * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution). + */ +#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */ +#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */ + +#define XTTCPSS_TIMER_BASE TTC0_BASE +#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1) +/* + * Timer Register Offset Definitions of Timer 1, Increment base address by 4 + * and use same offsets for Timer 2 + */ +#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ +#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */ +#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */ +#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */ +#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ +#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ + +#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 + +/* Setup the timers to use pre-scaling */ + +#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32) + +/** + * struct xttcpss_timer - This definition defines local timer structure + * + * @base_addr: Base address of timer + **/ +struct xttcpss_timer { + void __iomem *base_addr; +}; + +static struct xttcpss_timer timers[2]; +static struct clock_event_device xttcpss_clockevent; + +/** + * xttcpss_set_interval - Set the timer interval value + * + * @timer: Pointer to the timer instance + * @cycles: Timer interval ticks + **/ +static void xttcpss_set_interval(struct xttcpss_timer *timer, + unsigned long cycles) +{ + u32 ctrl_reg; + + /* Disable the counter, set the counter value and re-enable counter */ + ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + + __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET); + + /* Reset the counter (0x10) so that it starts from 0, one-shot + mode makes this needed for timing to be right. */ + ctrl_reg |= 0x10; + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); +} + +/** + * xttcpss_clock_event_interrupt - Clock event timer interrupt handler + * + * @irq: IRQ number of the Timer + * @dev_id: void pointer to the xttcpss_timer instance + * + * returns: Always IRQ_HANDLED - success + **/ +static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &xttcpss_clockevent; + struct xttcpss_timer *timer = dev_id; + + /* Acknowledge the interrupt and call event handler */ + __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), + timer->base_addr + XTTCPSS_ISR_OFFSET); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction event_timer_irq = { + .name = "xttcpss clockevent", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = xttcpss_clock_event_interrupt, +}; + +/** + * xttcpss_timer_hardware_init - Initialize the timer hardware + * + * Initialize the hardware to start the clock source, get the clock + * event timer ready to use, and hook up the interrupt. + **/ +static void __init xttcpss_timer_hardware_init(void) +{ + /* Setup the clock source counter to be an incrementing counter + * with no interrupt and it rolls over at 0xFFFF. Pre-scale + it by 32 also. Let it start running now. + */ + timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE; + + __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_IER_OFFSET); + __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + + /* Setup the clock event timer to be an interval timer which + * is prescaled by 32 using the interval interrupt. Leave it + * disabled for now. + */ + + timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4; + + __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_CLK_CNTRL_OFFSET); + __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr + + XTTCPSS_IER_OFFSET); + + /* Setup IRQ the clock event timer */ + event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT]; + setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq); +} + +/** + * __raw_readl_cycles - Reads the timer counter register + * + * returns: Current timer counter register value + **/ +static cycle_t __raw_readl_cycles(struct clocksource *cs) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE]; + + return (cycle_t)__raw_readl(timer->base_addr + + XTTCPSS_COUNT_VAL_OFFSET); +} + + +/* + * Instantiate and initialize the clock source structure + */ +static struct clocksource clocksource_xttcpss = { + .name = "xttcpss_timer1", + .rating = 200, /* Reasonable clock source */ + .read = __raw_readl_cycles, + .mask = CLOCKSOURCE_MASK(16), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + + +/** + * xttcpss_set_next_event - Sets the time interval for next event + * + * @cycles: Timer interval ticks + * @evt: Address of clock event instance + * + * returns: Always 0 - success + **/ +static int xttcpss_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + + xttcpss_set_interval(timer, cycles); + return 0; +} + +/** + * xttcpss_set_mode - Sets the mode of timer + * + * @mode: Mode to be set + * @evt: Address of clock event instance + **/ +static void xttcpss_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; + u32 ctrl_reg; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + xttcpss_set_interval(timer, TIMER_RATE / HZ); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + ctrl_reg = __raw_readl(timer->base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, + timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + break; + case CLOCK_EVT_MODE_RESUME: + ctrl_reg = __raw_readl(timer->base_addr + + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, + timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + break; + } +} + +/* + * Instantiate and initialize the clock event structure + */ +static struct clock_event_device xttcpss_clockevent = { + .name = "xttcpss_timer2", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = xttcpss_set_next_event, + .set_mode = xttcpss_set_mode, + .rating = 200, +}; + +/** + * xttcpss_timer_init - Initialize the timer + * + * Initializes the timer hardware and register the clock source and clock event + * timers with Linux kernal timer framework + **/ +static void __init xttcpss_timer_init(void) +{ + xttcpss_timer_hardware_init(); + clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); + + /* Calculate the parameters to allow the clockevent to operate using + integer math + */ + clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4); + + xttcpss_clockevent.max_delta_ns = + clockevent_delta2ns(0xfffe, &xttcpss_clockevent); + xttcpss_clockevent.min_delta_ns = + clockevent_delta2ns(1, &xttcpss_clockevent); + + /* Indicate that clock event is on 1st CPU as SMP boot needs it */ + + xttcpss_clockevent.cpumask = cpumask_of(0); + clockevents_register_device(&xttcpss_clockevent); +} + +/* + * Instantiate and initialize the system timer structure + */ +struct sys_timer xttcpss_sys_timer = { + .init = xttcpss_timer_init, +}; diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 0074b8dba793..a8f38bc8a897 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -629,6 +629,19 @@ config IO_36 comment "Processor Features" +config ARM_LPAE + bool "Support for the Large Physical Address Extension" + depends on MMU && CPU_V7 + help + Say Y if you have an ARMv7 processor supporting the LPAE page table + format and you would like to access memory beyond the 4GB limit. + +config ARCH_PHYS_ADDR_T_64BIT + def_bool ARM_LPAE + +config ARCH_DMA_ADDR_T_64BIT + def_bool ARM_LPAE + config ARM_THUMB bool "Support Thumb user binaries" depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON @@ -821,7 +834,7 @@ config CACHE_L2X0 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \ ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \ - ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE + ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_ZYNQ default y select OUTER_CACHE select OUTER_CACHE_SYNC diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index bca7e61928c7..48639e71af4f 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -91,7 +91,11 @@ obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V6K) += proc-v6.o +ifeq ($(CONFIG_ARM_LPAE),y) +obj-$(CONFIG_CPU_V7) += proc-v7lpae.o +else obj-$(CONFIG_CPU_V7) += proc-v7.o +endif AFLAGS_proc-v6.o :=-Wa,-march=armv6 AFLAGS_proc-v7.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 724ba3bce72c..bc98a6ebe1bc 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -906,6 +906,12 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) return 0; } +#ifdef CONFIG_ARM_LPAE +#define ALIGNMENT_FAULT 33 +#else +#define ALIGNMENT_FAULT 1 +#endif + /* * This needs to be done after sysctl_init, otherwise sys/ will be * overwritten. Actually, this shouldn't be in sys/ at all since @@ -939,7 +945,7 @@ static int __init alignment_init(void) ai_usermode = UM_FIXUP; } - hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN, + hook_fault_code(ALIGNMENT_FAULT, do_alignment, SIGBUS, BUS_ADRALN, "alignment exception"); /* diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 8bfae964b133..fcdb1017cdc6 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -22,9 +22,26 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION; DEFINE_PER_CPU(struct mm_struct *, current_mm); #endif +#ifdef CONFIG_ARM_LPAE +#define cpu_set_asid(asid) { \ + unsigned long ttbl, ttbh; \ + asm volatile( \ + " mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \ + " mov %1, %2, lsl #(48 - 32) @ set ASID\n" \ + " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \ + : "=&r" (ttbl), "=&r" (ttbh) \ + : "r" (asid & ~ASID_MASK)); \ +} +#else +#define cpu_set_asid(asid) \ + asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid)) +#endif + /* * We fork()ed a process, and we need a new context for the child - * to run in. + * to run in. We reserve version 0 for initial tasks so we will + * always allocate an ASID. The ASID 0 is reserved for the TTBR + * register changing sequence. */ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) { @@ -34,11 +51,8 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) static void flush_context(void) { - u32 ttb; - /* Copy TTBR1 into TTBR0 */ - asm volatile("mrc p15, 0, %0, c2, c0, 1\n" - "mcr p15, 0, %0, c2, c0, 0" - : "=r" (ttb)); + /* set the reserved ASID before flushing the TLB */ + cpu_set_asid(0); isb(); local_flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { @@ -94,13 +108,13 @@ static void reset_context(void *info) return; smp_rmb(); - asid = cpu_last_asid + cpu; + asid = cpu_last_asid + cpu + 1; flush_context(); set_mm_context(mm, asid); /* set the new ASID */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id)); + cpu_set_asid(mm->context.id); isb(); } @@ -144,13 +158,13 @@ void __new_context(struct mm_struct *mm) * to start a new version and flush the TLB. */ if (unlikely((asid & ~ASID_MASK) == 0)) { - asid = cpu_last_asid + smp_processor_id(); + asid = cpu_last_asid + smp_processor_id() + 1; flush_context(); #ifdef CONFIG_SMP smp_wmb(); smp_call_function(reset_context, NULL, 1); #endif - cpu_last_asid += NR_CPUS - 1; + cpu_last_asid += NR_CPUS; } set_mm_context(mm, asid); diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 82a093cee09a..80894999dfbc 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -18,12 +18,16 @@ #include <linux/device.h> #include <linux/dma-mapping.h> #include <linux/highmem.h> +#include <linux/memblock.h> #include <asm/memory.h> #include <asm/highmem.h> #include <asm/cacheflush.h> #include <asm/tlbflush.h> #include <asm/sizes.h> +#include <asm/mach/map.h> + +#include "mm.h" static u64 get_coherent_dma_mask(struct device *dev) { @@ -115,93 +119,127 @@ static void __dma_free_buffer(struct page *page, size_t size) } #ifdef CONFIG_MMU -/* Sanity check size */ -#if (CONSISTENT_DMA_SIZE % SZ_2M) -#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" +/* Sanity check sizes */ +#if CONSISTENT_DMA_SIZE % SECTION_SIZE +#error "CONSISTENT_DMA_SIZE must be a multiple of the section size" +#endif +#if CONSISTENT_WC_SIZE % SECTION_SIZE +#error "CONSISTENT_WC_SIZE must be a multiple of the section size" +#endif +#if ((CONSISTENT_DMA_SIZE + CONSISTENT_WC_SIZE) % SZ_2M) +#error "Sum of CONSISTENT_DMA_SIZE and CONSISTENT_WC_SIZE must be multiple of 2MiB" #endif -#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) -#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) -#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) +#include "vmregion.h" -/* - * These are the page tables (2MB each) covering uncached, DMA consistent allocations - */ -static pte_t *consistent_pte[NUM_CONSISTENT_PTES]; +struct dma_coherent_area { + struct arm_vmregion_head vm; + unsigned long pfn; + unsigned int type; + const char *name; +}; -#include "vmregion.h" +static struct dma_coherent_area coherent_wc_head = { + .vm = { + .vm_start = CONSISTENT_WC_BASE, + .vm_end = CONSISTENT_WC_END, + }, + .type = MT_WC_COHERENT, + .name = "WC ", +}; -static struct arm_vmregion_head consistent_head = { - .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), - .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), - .vm_start = CONSISTENT_BASE, - .vm_end = CONSISTENT_END, +static struct dma_coherent_area coherent_dma_head = { + .vm = { + .vm_start = CONSISTENT_BASE, + .vm_end = CONSISTENT_END, + }, + .type = MT_DMA_COHERENT, + .name = "DMA coherent ", }; -#ifdef CONFIG_HUGETLB_PAGE -#error ARM Coherent DMA allocator does not (yet) support huge TLB -#endif +static struct dma_coherent_area *coherent_areas[2] __initdata = + { &coherent_wc_head, &coherent_dma_head }; -/* - * Initialise the consistent memory allocation. - */ -static int __init consistent_init(void) +static struct dma_coherent_area *coherent_map[2]; +#define coherent_wc_area coherent_map[0] +#define coherent_dma_area coherent_map[1] + +void dma_coherent_reserve(void) { - int ret = 0; - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - pte_t *pte; - int i = 0; - u32 base = CONSISTENT_BASE; + phys_addr_t base, max_addr; + unsigned long size; + int can_share, i; - do { - pgd = pgd_offset(&init_mm, base); + if (arch_is_coherent()) + return; - pud = pud_alloc(&init_mm, pgd, base); - if (!pud) { - printk(KERN_ERR "%s: no pud tables\n", __func__); - ret = -ENOMEM; - break; - } +#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE + /* ARMv6: only when DMA_MEM_BUFFERABLE is enabled */ + can_share = cpu_architecture() >= CPU_ARCH_ARMv6; +#else + /* ARMv7+: WC and DMA areas have the same properties, so can share */ + can_share = cpu_architecture() >= CPU_ARCH_ARMv7; +#endif + if (can_share) { + coherent_wc_head.name = "DMA coherent/WC "; + coherent_wc_head.vm.vm_end = coherent_dma_head.vm.vm_end; + coherent_dma_head.vm.vm_start = coherent_dma_head.vm.vm_end; + coherent_dma_area = coherent_wc_area = &coherent_wc_head; + } else { + memcpy(coherent_map, coherent_areas, sizeof(coherent_map)); + } - pmd = pmd_alloc(&init_mm, pud, base); - if (!pmd) { - printk(KERN_ERR "%s: no pmd tables\n", __func__); - ret = -ENOMEM; - break; - } - WARN_ON(!pmd_none(*pmd)); + max_addr = MEMBLOCK_ALLOC_ANYWHERE; + if (ISA_DMA_THRESHOLD != 0xffffffffULL) + max_addr = ISA_DMA_THRESHOLD; - pte = pte_alloc_kernel(pmd, base); - if (!pte) { - printk(KERN_ERR "%s: no pte tables\n", __func__); - ret = -ENOMEM; - break; - } + for (i = 0; i < ARRAY_SIZE(coherent_areas); i++) { + struct dma_coherent_area *area = coherent_areas[i]; + + size = area->vm.vm_end - area->vm.vm_start; + if (!size) + continue; - consistent_pte[i++] = pte; - base += (1 << PGDIR_SHIFT); - } while (base < CONSISTENT_END); + spin_lock_init(&area->vm.vm_lock); + INIT_LIST_HEAD(&area->vm.vm_list); - return ret; + base = memblock_alloc_base(size, SZ_1M, max_addr); + memblock_free(base, size); + memblock_remove(base, size); + + area->pfn = __phys_to_pfn(base); + + pr_info("DMA: %luMiB %smemory allocated at 0x%08llx phys\n", + size / 1048576, area->name, (unsigned long long)base); + } } -core_initcall(consistent_init); +void __init dma_coherent_mapping(void) +{ + struct map_desc map[ARRAY_SIZE(coherent_areas)]; + int nr; -static void * -__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot) + for (nr = 0; nr < ARRAY_SIZE(map); nr++) { + struct dma_coherent_area *area = coherent_areas[nr]; + + map[nr].pfn = area->pfn; + map[nr].virtual = area->vm.vm_start; + map[nr].length = area->vm.vm_end - area->vm.vm_start; + map[nr].type = area->type; + if (map[nr].length == 0) + break; + } + + iotable_init(map, nr); +} + +static void *dma_alloc_area(size_t size, unsigned long *pfn, gfp_t gfp, + struct dma_coherent_area *area) { struct arm_vmregion *c; size_t align; int bit; - if (!consistent_pte[0]) { - printk(KERN_ERR "%s: not initialised\n", __func__); - dump_stack(); - return NULL; - } - /* * Align the virtual region allocation - maximum alignment is * a section size, minimum is a page size. This helps reduce @@ -216,45 +254,21 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot) /* * Allocate a virtual address in the consistent mapping region. */ - c = arm_vmregion_alloc(&consistent_head, align, size, + c = arm_vmregion_alloc(&area->vm, align, size, gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); - if (c) { - pte_t *pte; - int idx = CONSISTENT_PTE_INDEX(c->vm_start); - u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); - - pte = consistent_pte[idx] + off; - c->vm_pages = page; - - do { - BUG_ON(!pte_none(*pte)); - - set_pte_ext(pte, mk_pte(page, prot), 0); - page++; - pte++; - off++; - if (off >= PTRS_PER_PTE) { - off = 0; - pte = consistent_pte[++idx]; - } - } while (size -= PAGE_SIZE); - - dsb(); + if (!c) + return NULL; - return (void *)c->vm_start; - } - return NULL; + memset((void *)c->vm_start, 0, size); + *pfn = area->pfn + ((c->vm_start - area->vm.vm_start) >> PAGE_SHIFT); + return (void *)c->vm_start; } -static void __dma_free_remap(void *cpu_addr, size_t size) +static void dma_free_area(void *cpu_addr, size_t size, struct dma_coherent_area *area) { struct arm_vmregion *c; - unsigned long addr; - pte_t *ptep; - int idx; - u32 off; - c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); + c = arm_vmregion_find_remove(&area->vm, (unsigned long)cpu_addr); if (!c) { printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n", __func__, cpu_addr); @@ -269,61 +283,62 @@ static void __dma_free_remap(void *cpu_addr, size_t size) size = c->vm_end - c->vm_start; } - idx = CONSISTENT_PTE_INDEX(c->vm_start); - off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); - ptep = consistent_pte[idx] + off; - addr = c->vm_start; - do { - pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); - - ptep++; - addr += PAGE_SIZE; - off++; - if (off >= PTRS_PER_PTE) { - off = 0; - ptep = consistent_pte[++idx]; - } + arm_vmregion_free(&area->vm, c); +} - if (pte_none(pte) || !pte_present(pte)) - printk(KERN_CRIT "%s: bad page in kernel page table\n", - __func__); - } while (size -= PAGE_SIZE); +#define nommu() (0) - flush_tlb_kernel_range(c->vm_start, c->vm_end); +#else /* !CONFIG_MMU */ - arm_vmregion_free(&consistent_head, c); -} +#define dma_alloc_area(size, pfn, gfp, area) ({ *(pfn) = 0; NULL }) +#define dma_free_area(addr, size, area) do { } while (0) -#else /* !CONFIG_MMU */ +#define nommu() (1) +#define coherent_wc_area NULL +#define coherent_dma_area NULL -#define __dma_alloc_remap(page, size, gfp, prot) page_address(page) -#define __dma_free_remap(addr, size) do { } while (0) +void dma_coherent_reserve(void) +{ +} #endif /* CONFIG_MMU */ static void * __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, - pgprot_t prot) + struct dma_coherent_area *area) { - struct page *page; - void *addr; + unsigned long pfn; + void *ret; *handle = ~0; size = PAGE_ALIGN(size); - page = __dma_alloc_buffer(dev, size, gfp); - if (!page) - return NULL; + if (arch_is_coherent() || nommu()) { + struct page *page = __dma_alloc_buffer(dev, size, gfp); + if (!page) + return NULL; + pfn = page_to_pfn(page); + ret = page_address(page); + } else { + ret = dma_alloc_area(size, &pfn, gfp, area); + } - if (!arch_is_coherent()) - addr = __dma_alloc_remap(page, size, gfp, prot); - else - addr = page_address(page); + if (ret) + *handle = pfn_to_dma(dev, pfn); - if (addr) - *handle = pfn_to_dma(dev, page_to_pfn(page)); + return ret; +} + +static void __dma_free(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t handle, struct dma_coherent_area *area) +{ + size = PAGE_ALIGN(size); - return addr; + if (arch_is_coherent() || nommu()) { + __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size); + } else { + dma_free_area(cpu_addr, size, area); + } } /* @@ -338,8 +353,7 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gf if (dma_alloc_from_coherent(dev, size, handle, &memory)) return memory; - return __dma_alloc(dev, size, handle, gfp, - pgprot_dmacoherent(pgprot_kernel)); + return __dma_alloc(dev, size, handle, gfp, coherent_dma_area); } EXPORT_SYMBOL(dma_alloc_coherent); @@ -350,13 +364,13 @@ EXPORT_SYMBOL(dma_alloc_coherent); void * dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) { - return __dma_alloc(dev, size, handle, gfp, - pgprot_writecombine(pgprot_kernel)); + return __dma_alloc(dev, size, handle, gfp, coherent_wc_area); } EXPORT_SYMBOL(dma_alloc_writecombine); static int dma_mmap(struct device *dev, struct vm_area_struct *vma, - void *cpu_addr, dma_addr_t dma_addr, size_t size) + void *cpu_addr, dma_addr_t dma_addr, size_t size, + struct dma_coherent_area *area) { int ret = -ENXIO; #ifdef CONFIG_MMU @@ -365,7 +379,7 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma, user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; - c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr); + c = arm_vmregion_find(&area->vm, (unsigned long)cpu_addr); if (c) { unsigned long off = vma->vm_pgoff; @@ -388,7 +402,7 @@ int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, dma_addr_t dma_addr, size_t size) { vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot); - return dma_mmap(dev, vma, cpu_addr, dma_addr, size); + return dma_mmap(dev, vma, cpu_addr, dma_addr, size, coherent_dma_area); } EXPORT_SYMBOL(dma_mmap_coherent); @@ -396,7 +410,7 @@ int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, dma_addr_t dma_addr, size_t size) { vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); - return dma_mmap(dev, vma, cpu_addr, dma_addr, size); + return dma_mmap(dev, vma, cpu_addr, dma_addr, size, coherent_wc_area); } EXPORT_SYMBOL(dma_mmap_writecombine); @@ -411,14 +425,18 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) return; - size = PAGE_ALIGN(size); + __dma_free(dev, size, cpu_addr, handle, coherent_dma_area); +} +EXPORT_SYMBOL(dma_free_coherent); - if (!arch_is_coherent()) - __dma_free_remap(cpu_addr, size); +void dma_free_writecombine(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t handle) +{ + WARN_ON(irqs_disabled()); - __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size); + __dma_free(dev, size, cpu_addr, handle, coherent_wc_area); } -EXPORT_SYMBOL(dma_free_coherent); +EXPORT_SYMBOL(dma_free_writecombine); /* * Make an area consistent for devices. diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index bc0e1d88fd3b..e06918b59e25 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -33,10 +33,15 @@ #define FSR_WRITE (1 << 11) #define FSR_FS4 (1 << 10) #define FSR_FS3_0 (15) +#define FSR_FS5_0 (0x3f) static inline int fsr_fs(unsigned int fsr) { +#ifdef CONFIG_ARM_LPAE + return fsr & FSR_FS5_0; +#else return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6; +#endif } #ifdef CONFIG_MMU @@ -94,7 +99,7 @@ void show_pte(struct mm_struct *mm, unsigned long addr) pud = pud_offset(pgd, addr); if (PTRS_PER_PUD != 1) - printk(", *pud=%08lx", pud_val(*pud)); + printk(", *pud=%08llx", (long long)pud_val(*pud)); if (pud_none(*pud)) break; @@ -122,8 +127,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr) pte = pte_offset_map(pmd, addr); printk(", *pte=%08llx", (long long)pte_val(*pte)); +#ifndef CONFIG_ARM_LPAE printk(", *ppte=%08llx", (long long)pte_val(pte[PTE_HWTABLE_PTRS])); +#endif pte_unmap(pte); } while(0); @@ -490,6 +497,72 @@ static struct fsr_info { int code; const char *name; } fsr_info[] = { +#ifdef CONFIG_ARM_LPAE + { do_bad, SIGBUS, 0, "unknown 0" }, + { do_bad, SIGBUS, 0, "unknown 1" }, + { do_bad, SIGBUS, 0, "unknown 2" }, + { do_bad, SIGBUS, 0, "unknown 3" }, + { do_bad, SIGBUS, 0, "reserved translation fault" }, + { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, + { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, + { do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, + { do_bad, SIGBUS, 0, "reserved access flag fault" }, + { do_bad, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, + { do_bad, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, + { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, + { do_bad, SIGBUS, 0, "reserved permission fault" }, + { do_bad, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, + { do_sect_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, + { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, + { do_bad, SIGBUS, 0, "synchronous external abort" }, + { do_bad, SIGBUS, 0, "asynchronous external abort" }, + { do_bad, SIGBUS, 0, "unknown 18" }, + { do_bad, SIGBUS, 0, "unknown 19" }, + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" }, + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" }, + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" }, + { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" }, + { do_bad, SIGBUS, 0, "synchronous parity error" }, + { do_bad, SIGBUS, 0, "asynchronous parity error" }, + { do_bad, SIGBUS, 0, "unknown 26" }, + { do_bad, SIGBUS, 0, "unknown 27" }, + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" }, + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" }, + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" }, + { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" }, + { do_bad, SIGBUS, 0, "unknown 32" }, + { do_bad, SIGBUS, BUS_ADRALN, "alignment fault" }, + { do_bad, SIGBUS, 0, "debug event" }, + { do_bad, SIGBUS, 0, "unknown 35" }, + { do_bad, SIGBUS, 0, "unknown 36" }, + { do_bad, SIGBUS, 0, "unknown 37" }, + { do_bad, SIGBUS, 0, "unknown 38" }, + { do_bad, SIGBUS, 0, "unknown 39" }, + { do_bad, SIGBUS, 0, "unknown 40" }, + { do_bad, SIGBUS, 0, "unknown 41" }, + { do_bad, SIGBUS, 0, "unknown 42" }, + { do_bad, SIGBUS, 0, "unknown 43" }, + { do_bad, SIGBUS, 0, "unknown 44" }, + { do_bad, SIGBUS, 0, "unknown 45" }, + { do_bad, SIGBUS, 0, "unknown 46" }, + { do_bad, SIGBUS, 0, "unknown 47" }, + { do_bad, SIGBUS, 0, "unknown 48" }, + { do_bad, SIGBUS, 0, "unknown 49" }, + { do_bad, SIGBUS, 0, "unknown 50" }, + { do_bad, SIGBUS, 0, "unknown 51" }, + { do_bad, SIGBUS, 0, "implementation fault (lockdown abort)" }, + { do_bad, SIGBUS, 0, "unknown 53" }, + { do_bad, SIGBUS, 0, "unknown 54" }, + { do_bad, SIGBUS, 0, "unknown 55" }, + { do_bad, SIGBUS, 0, "unknown 56" }, + { do_bad, SIGBUS, 0, "unknown 57" }, + { do_bad, SIGBUS, 0, "implementation fault (coprocessor abort)" }, + { do_bad, SIGBUS, 0, "unknown 59" }, + { do_bad, SIGBUS, 0, "unknown 60" }, + { do_bad, SIGBUS, 0, "unknown 61" }, + { do_bad, SIGBUS, 0, "unknown 62" }, + { do_bad, SIGBUS, 0, "unknown 63" }, +#else /* !CONFIG_ARM_LPAE */ /* * The following are the standard ARMv3 and ARMv4 aborts. ARMv5 * defines these to be "precise" aborts. @@ -531,6 +604,7 @@ static struct fsr_info { { do_bad, SIGBUS, 0, "unknown 29" }, { do_bad, SIGBUS, 0, "unknown 30" }, { do_bad, SIGBUS, 0, "unknown 31" } +#endif /* CONFIG_ARM_LPAE */ }; void __init @@ -569,6 +643,9 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) } +#ifdef CONFIG_ARM_LPAE +#define ifsr_info fsr_info +#else /* !CONFIG_ARM_LPAE */ static struct fsr_info ifsr_info[] = { { do_bad, SIGBUS, 0, "unknown 0" }, { do_bad, SIGBUS, 0, "unknown 1" }, @@ -603,6 +680,7 @@ static struct fsr_info ifsr_info[] = { { do_bad, SIGBUS, 0, "unknown 30" }, { do_bad, SIGBUS, 0, "unknown 31" }, }; +#endif /* CONFIG_ARM_LPAE */ void __init hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), @@ -638,6 +716,7 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs) static int __init exceptions_init(void) { +#ifndef CONFIG_ARM_LPAE if (cpu_architecture() >= CPU_ARCH_ARMv6) { hook_fault_code(4, do_translation_fault, SIGSEGV, SEGV_MAPERR, "I-cache maintenance fault"); @@ -653,6 +732,7 @@ static int __init exceptions_init(void) hook_fault_code(6, do_bad, SIGSEGV, SEGV_MAPERR, "section access flag fault"); } +#endif return 0; } diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c index 2be9139a4ef3..24e06555bee4 100644 --- a/arch/arm/mm/idmap.c +++ b/arch/arm/mm/idmap.c @@ -1,9 +1,36 @@ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include <linux/kernel.h> #include <asm/cputype.h> #include <asm/pgalloc.h> #include <asm/pgtable.h> +#ifdef CONFIG_ARM_LPAE +static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end, + unsigned long prot) +{ + pmd_t *pmd; + unsigned long next; + + if (pud_none_or_clear_bad(pud) || (pud_val(*pud) & L_PGD_SWAPPER)) { + pmd = pmd_alloc_one(NULL, addr); + if (!pmd) { + pr_warning("Failed to allocate identity pmd.\n"); + return; + } + pud_populate(NULL, pud, pmd); + pmd += pmd_index(addr); + } else + pmd = pmd_offset(pud, addr); + + do { + next = pmd_addr_end(addr, end); + *pmd = __pmd((addr & PMD_MASK) | prot); + flush_pmd_entry(pmd); + } while (pmd++, addr = next, addr != end); +} +#else /* !CONFIG_ARM_LPAE */ static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end, unsigned long prot) { @@ -15,6 +42,7 @@ static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end, pmd[1] = __pmd(addr); flush_pmd_entry(pmd); } +#endif /* CONFIG_ARM_LPAE */ static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end, unsigned long prot) @@ -32,7 +60,7 @@ void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end) { unsigned long prot, next; - prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE; + prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF; if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) prot |= PMD_BIT4; @@ -46,7 +74,11 @@ void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end) #ifdef CONFIG_SMP static void idmap_del_pmd(pud_t *pud, unsigned long addr, unsigned long end) { - pmd_t *pmd = pmd_offset(pud, addr); + pmd_t *pmd; + + if (pud_none_or_clear_bad(pud)) + return; + pmd = pmd_offset(pud, addr); pmd_clear(pmd); } diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 2c2cce9cd8c8..b9671a831709 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -331,6 +331,12 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc) #endif #ifdef CONFIG_BLK_DEV_INITRD if (phys_initrd_size && + !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) { + pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n", + phys_initrd_start, phys_initrd_size); + phys_initrd_start = phys_initrd_size = 0; + } + if (phys_initrd_size && memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) { pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n", phys_initrd_start, phys_initrd_size); @@ -347,6 +353,7 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc) arm_mm_memblock_reserve(); arm_dt_memblock_reserve(); + dma_coherent_reserve(); /* reserve any platform specific memblock areas */ if (mdesc->reserve) @@ -635,7 +642,8 @@ void __init mem_init(void) " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" " .init : 0x%p" " - 0x%p" " (%4d kB)\n" " .text : 0x%p" " - 0x%p" " (%4d kB)\n" - " .data : 0x%p" " - 0x%p" " (%4d kB)\n", + " .data : 0x%p" " - 0x%p" " (%4d kB)\n" + " .bss : 0x%p" " - 0x%p" " (%4d kB)\n", MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + (PAGE_SIZE)), @@ -657,7 +665,8 @@ void __init mem_init(void) MLK_ROUNDUP(__init_begin, __init_end), MLK_ROUNDUP(_text, _etext), - MLK_ROUNDUP(_sdata, _edata)); + MLK_ROUNDUP(_sdata, _edata), + MLK_ROUNDUP(__bss_start, __bss_stop)); #undef MLK #undef MLM diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index ab506272b2d3..3a5a9c272c96 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -64,7 +64,7 @@ void __check_kvm_seq(struct mm_struct *mm) } while (seq != init_mm.context.kvm_seq); } -#ifndef CONFIG_SMP +#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) /* * Section support is unsafe on SMP - If you iounmap and ioremap a region, * the other CPUs will not see this change until their next context switch. @@ -83,7 +83,8 @@ static void unmap_area_sections(unsigned long virt, unsigned long size) flush_cache_vunmap(addr, end); pgd = pgd_offset_k(addr); do { - pmd_t pmd, *pmdp = pmd_offset(pgd, addr); + pud_t *pud = pud_offset(pgd, addr); + pmd_t pmd, *pmdp = pmd_offset(pud, addr); pmd = *pmdp; if (!pmd_none(pmd)) { @@ -133,7 +134,8 @@ remap_area_sections(unsigned long virt, unsigned long pfn, pgd = pgd_offset_k(addr); do { - pmd_t *pmd = pmd_offset(pgd, addr); + pud_t *pud = pud_offset(pgd, addr); + pmd_t *pmd = pmd_offset(pud, addr); pmd[0] = __pmd(__pfn_to_phys(pfn) | type->prot_sect); pfn += SZ_1M >> PAGE_SHIFT; @@ -170,7 +172,8 @@ remap_area_supersections(unsigned long virt, unsigned long pfn, super_pmd_val |= ((pfn >> (32 - PAGE_SHIFT)) & 0xf) << 20; for (i = 0; i < 8; i++) { - pmd_t *pmd = pmd_offset(pgd, addr); + pud_t *pud = pud_offset(pgd, addr); + pmd_t *pmd = pmd_offset(pud, addr); pmd[0] = __pmd(super_pmd_val); pmd[1] = __pmd(super_pmd_val); @@ -195,11 +198,13 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, unsigned long addr; struct vm_struct * area; +#ifndef CONFIG_ARM_LPAE /* * High mappings must be supersection aligned */ if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK)) return NULL; +#endif /* * Don't allow RAM to be mapped - this causes problems with ARMv6+ @@ -221,7 +226,7 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, return NULL; addr = (unsigned long)area->addr; -#ifndef CONFIG_SMP +#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) if (DOMAIN_IO == 0 && (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) || cpu_is_xsc3()) && pfn >= 0x100000 && @@ -292,7 +297,7 @@ EXPORT_SYMBOL(__arm_ioremap); void __iounmap(volatile void __iomem *io_addr) { void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr); -#ifndef CONFIG_SMP +#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) struct vm_struct **p, *tmp; /* diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 5b3d7d543659..0d41a9e42b52 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -12,8 +12,8 @@ static inline pmd_t *pmd_off_k(unsigned long virt) struct mem_type { pteval_t prot_pte; - unsigned int prot_l1; - unsigned int prot_sect; + pgprotval_t prot_l1; + pgprotval_t prot_sect; unsigned int domain; }; @@ -25,3 +25,5 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page void __init bootmem_init(void); void arm_mm_memblock_reserve(void); +void dma_coherent_reserve(void); +void dma_coherent_mapping(void); diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 9d9e736c2b4f..7a2ca65b1d44 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -60,7 +60,7 @@ EXPORT_SYMBOL(pgprot_kernel); struct cachepolicy { const char policy[16]; unsigned int cr_mask; - unsigned int pmd; + pmdval_t pmd; pteval_t pte; }; @@ -150,6 +150,7 @@ static int __init early_nowrite(char *__unused) } early_param("nowb", early_nowrite); +#ifndef CONFIG_ARM_LPAE static int __init early_ecc(char *p) { if (memcmp(p, "on", 2) == 0) @@ -159,6 +160,7 @@ static int __init early_ecc(char *p) return 0; } early_param("ecc", early_ecc); +#endif static int __init noalign_setup(char *__unused) { @@ -228,10 +230,12 @@ static struct mem_type mem_types[] = { .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, .domain = DOMAIN_KERNEL, }, +#ifndef CONFIG_ARM_LPAE [MT_MINICLEAN] = { .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, .domain = DOMAIN_KERNEL, }, +#endif [MT_LOW_VECTORS] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_RDONLY, @@ -273,6 +277,16 @@ static struct mem_type mem_types[] = { .prot_l1 = PMD_TYPE_TABLE, .domain = DOMAIN_KERNEL, }, + [MT_DMA_COHERENT] = { + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | + PMD_SECT_S, + .domain = DOMAIN_IO, + }, + [MT_WC_COHERENT] = { + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | + PMD_SECT_S, + .domain = DOMAIN_IO, + }, }; const struct mem_type *get_mem_type(unsigned int type) @@ -288,7 +302,7 @@ static void __init build_mem_type_table(void) { struct cachepolicy *cp; unsigned int cr = get_cr(); - unsigned int user_pgprot, kern_pgprot, vecs_pgprot; + pgprotval_t user_pgprot, kern_pgprot, vecs_pgprot; int cpu_arch = cpu_architecture(); int i; @@ -353,6 +367,7 @@ static void __init build_mem_type_table(void) mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; + mem_types[MT_DMA_COHERENT].prot_sect |= PMD_SECT_XN; } if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { /* @@ -421,6 +436,7 @@ static void __init build_mem_type_table(void) * ARMv6 and above have extended page tables. */ if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { +#ifndef CONFIG_ARM_LPAE /* * Mark cache clean areas and XIP ROM read only * from SVC mode and no access from userspace. @@ -428,6 +444,7 @@ static void __init build_mem_type_table(void) mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; +#endif if (is_smp()) { /* @@ -457,15 +474,38 @@ static void __init build_mem_type_table(void) /* Non-cacheable Normal is XCB = 001 */ mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERED; + mem_types[MT_WC_COHERENT].prot_sect |= + PMD_SECT_BUFFERED; + mem_types[MT_DMA_COHERENT].prot_sect |= + PMD_SECT_BUFFERED; } else { /* For both ARMv6 and non-TEX-remapping ARMv7 */ mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_TEX(1); + mem_types[MT_WC_COHERENT].prot_sect |= + PMD_SECT_TEX(1); +#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE + mem_types[MT_DMA_COHERENT].prot_sect |= + PMD_SECT_TEX(1); +#endif } } else { mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; + mem_types[MT_WC_COHERENT].prot_sect |= PMD_SECT_BUFFERED; } +#ifdef CONFIG_ARM_LPAE + /* + * Do not generate access flag faults for the kernel mappings. + */ + for (i = 0; i < ARRAY_SIZE(mem_types); i++) { + mem_types[i].prot_pte |= PTE_EXT_AF; + mem_types[i].prot_sect |= PMD_SECT_AF; + } + kern_pgprot |= PTE_EXT_AF; + vecs_pgprot |= PTE_EXT_AF; +#endif + for (i = 0; i < 16; i++) { unsigned long v = pgprot_val(protection_map[i]); protection_map[i] = __pgprot(v | user_pgprot); @@ -595,6 +635,7 @@ static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, } while (pud++, addr = next, addr != end); } +#ifndef CONFIG_ARM_LPAE static void __init create_36bit_mapping(struct map_desc *md, const struct mem_type *type) { @@ -654,6 +695,7 @@ static void __init create_36bit_mapping(struct map_desc *md, pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; } while (addr != end); } +#endif /* !CONFIG_ARM_LPAE */ /* * Create the page directory entries and any necessary @@ -685,6 +727,7 @@ static void __init create_mapping(struct map_desc *md) type = &mem_types[md->type]; +#ifndef CONFIG_ARM_LPAE /* * Catch 36-bit addresses */ @@ -692,6 +735,7 @@ static void __init create_mapping(struct map_desc *md) create_36bit_mapping(md, type); return; } +#endif addr = md->virtual & PAGE_MASK; phys = __pfn_to_phys(md->pfn); @@ -768,7 +812,8 @@ static void __init sanity_check_meminfo(void) *bank = meminfo.bank[i]; #ifdef CONFIG_HIGHMEM - if (__va(bank->start) >= vmalloc_min || + if (bank->start > ULONG_MAX || + __va(bank->start) >= vmalloc_min || __va(bank->start) < (void *)PAGE_OFFSET) highmem = 1; @@ -778,7 +823,7 @@ static void __init sanity_check_meminfo(void) * Split those memory banks which are partially overlapping * the vmalloc area greatly simplifying things later. */ - if (__va(bank->start) < vmalloc_min && + if (!highmem && __va(bank->start) < vmalloc_min && bank->size > vmalloc_min - __va(bank->start)) { if (meminfo.nr_banks >= NR_BANKS) { printk(KERN_CRIT "NR_BANKS too low, " @@ -863,14 +908,14 @@ static inline void prepare_page_table(void) /* * Clear out all the mappings below the kernel image. */ - for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE) + for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); #ifdef CONFIG_XIP_KERNEL /* The XIP kernel is mapped in the module area -- skip over it */ - addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK; + addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; #endif - for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) + for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); /* @@ -885,10 +930,18 @@ static inline void prepare_page_table(void) * memory bank, up to the end of the vmalloc region. */ for (addr = __phys_to_virt(end); - addr < VMALLOC_END; addr += PGDIR_SIZE) + addr < VMALLOC_END; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); } +#ifdef CONFIG_ARM_LPAE +/* the first page is reserved for pgd */ +#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ + PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) +#else +#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) +#endif + /* * Reserve the special regions of memory */ @@ -898,7 +951,7 @@ void __init arm_mm_memblock_reserve(void) * Reserve the page tables. These are already in use, * and can only be in node 0. */ - memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); + memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); #ifdef CONFIG_SA1111 /* @@ -926,7 +979,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc) */ vectors_page = early_alloc(PAGE_SIZE); - for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) + for (addr = VMALLOC_END; addr; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); /* @@ -976,6 +1029,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc) create_mapping(&map); } + dma_coherent_mapping(); + /* * Ask the machine support to map in the statically mapped devices. */ diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index b2027c154b2a..a3e78ccabd65 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -10,6 +10,7 @@ #include <linux/mm.h> #include <linux/gfp.h> #include <linux/highmem.h> +#include <linux/slab.h> #include <asm/pgalloc.h> #include <asm/page.h> @@ -17,6 +18,14 @@ #include "mm.h" +#ifdef CONFIG_ARM_LPAE +#define __pgd_alloc() kmalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL) +#define __pgd_free(pgd) kfree(pgd) +#else +#define __pgd_alloc() (pgd_t *)__get_free_pages(GFP_KERNEL, 2) +#define __pgd_free(pgd) free_pages((unsigned long)pgd, 2) +#endif + /* * need to get a 16k page for level 1 */ @@ -27,7 +36,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm) pmd_t *new_pmd, *init_pmd; pte_t *new_pte, *init_pte; - new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2); + new_pgd = __pgd_alloc(); if (!new_pgd) goto no_pgd; @@ -42,10 +51,25 @@ pgd_t *pgd_alloc(struct mm_struct *mm) clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t)); +#ifdef CONFIG_ARM_LPAE + /* + * Allocate PMD table for modules and pkmap mappings. + */ + new_pud = pud_alloc(mm, new_pgd + pgd_index(MODULES_VADDR), + MODULES_VADDR); + if (!new_pud) + goto no_pud; + + new_pmd = pmd_alloc(mm, new_pud, 0); + if (!new_pmd) + goto no_pmd; +#endif + if (!vectors_high()) { /* * On ARM, first page must always be allocated since it - * contains the machine vectors. + * contains the machine vectors. The vectors are always high + * with LPAE. */ new_pud = pud_alloc(mm, new_pgd, 0); if (!new_pud) @@ -74,7 +98,7 @@ no_pte: no_pmd: pud_free(mm, new_pud); no_pud: - free_pages((unsigned long)new_pgd, 2); + __pgd_free(new_pgd); no_pgd: return NULL; } @@ -111,5 +135,24 @@ no_pud: pgd_clear(pgd); pud_free(mm, pud); no_pgd: - free_pages((unsigned long) pgd_base, 2); +#ifdef CONFIG_ARM_LPAE + /* + * Free modules/pkmap or identity pmd tables. + */ + for (pgd = pgd_base; pgd < pgd_base + PTRS_PER_PGD; pgd++) { + if (pgd_none_or_clear_bad(pgd)) + continue; + if (pgd_val(*pgd) & L_PGD_SWAPPER) + continue; + pud = pud_offset(pgd, 0); + if (pud_none_or_clear_bad(pud)) + continue; + pmd = pmd_offset(pud, 0); + pud_clear(pud); + pmd_free(mm, pmd); + pgd_clear(pgd); + pud_free(mm, pud); + } +#endif + __pgd_free(pgd_base); } diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index e4c165ca6696..537ffcb0646d 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S @@ -146,7 +146,7 @@ __arm7tdmi_proc_info: .long 0 .long 0 .long v4_cache_fns - .size __arm7tdmi_proc_info, . - __arm7dmi_proc_info + .size __arm7tdmi_proc_info, . - __arm7tdmi_proc_info .type __triscenda7_proc_info, #object __triscenda7_proc_info: diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 7b7ebd4d096d..546b54da1005 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S @@ -116,7 +116,7 @@ __arm9tdmi_proc_info: .long 0 .long 0 .long v4_cache_fns - .size __arm9tdmi_proc_info, . - __arm9dmi_proc_info + .size __arm9tdmi_proc_info, . - __arm9tdmi_proc_info .type __p2001_proc_info, #object __p2001_proc_info: diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 34261f9486b9..48b85f672bdd 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -91,8 +91,9 @@ #if L_PTE_SHARED != PTE_EXT_SHARED #error PTE shared bit mismatch #endif -#if (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\ - L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED +#if !defined (CONFIG_ARM_LPAE) && \ + (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\ + L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED #error Invalid Linux PTE bit settings #endif #endif /* CONFIG_MMU */ diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b3b566ec83d3..ac72d89683df 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -101,23 +101,31 @@ ENDPROC(cpu_v7_dcache_clean_area) */ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU - mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id + mov r2, #0 +#ifdef CONFIG_ARM_LPAE + and r3, r1, #0xff + mov r3, r3, lsl #(48 - 32) @ ASID + mcrr p15, 0, r0, r3, c2 @ set TTB 0 +#else /* !CONFIG_ARM_LPAE */ ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) #ifdef CONFIG_ARM_ERRATA_430973 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB #endif - mrc p15, 0, r2, c2, c0, 1 @ load TTB 1 - mcr p15, 0, r2, c2, c0, 0 @ into TTB 0 - isb #ifdef CONFIG_ARM_ERRATA_754322 dsb #endif - mcr p15, 0, r1, c13, c0, 1 @ set context ID + mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 isb +#ifdef CONFIG_ARM_ERRATA_754322 + dsb +#endif + mcr p15, 0, r1, c13, c0, 1 @ set context ID +#endif /* CONFIG_ARM_LPAE */ + isb #endif mov pc, lr ENDPROC(cpu_v7_switch_mm) diff --git a/arch/arm/mm/proc-v7lpae.S b/arch/arm/mm/proc-v7lpae.S new file mode 100644 index 000000000000..0bee21308d20 --- /dev/null +++ b/arch/arm/mm/proc-v7lpae.S @@ -0,0 +1,422 @@ +/* + * arch/arm/mm/proc-v7lpae.S + * + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright (C) 2011 ARM Ltd. + * Author: Catalin Marinas <catalin.marinas@arm.com> + * based on arch/arm/mm/proc-v7.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/asm-offsets.h> +#include <asm/hwcap.h> +#include <asm/pgtable-hwdef.h> +#include <asm/pgtable.h> + +#include "proc-macros.S" + +#define TTB_IRGN_NC (0 << 8) +#define TTB_IRGN_WBWA (1 << 8) +#define TTB_IRGN_WT (2 << 8) +#define TTB_IRGN_WB (3 << 8) +#define TTB_RGN_NC (0 << 10) +#define TTB_RGN_OC_WBWA (1 << 10) +#define TTB_RGN_OC_WT (2 << 10) +#define TTB_RGN_OC_WB (3 << 10) +#define TTB_S (3 << 12) +#define TTB_EAE (1 << 31) + +/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ +#define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB) +#define PMD_FLAGS_UP (PMD_SECT_WB) + +/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ +#define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA) +#define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S) + +ENTRY(cpu_v7_proc_init) + mov pc, lr +ENDPROC(cpu_v7_proc_init) + +ENTRY(cpu_v7_proc_fin) + mrc p15, 0, r0, c1, c0, 0 @ ctrl register + bic r0, r0, #0x1000 @ ...i............ + bic r0, r0, #0x0006 @ .............ca. + mcr p15, 0, r0, c1, c0, 0 @ disable caches + mov pc, lr +ENDPROC(cpu_v7_proc_fin) + +/* + * cpu_v7_reset(loc) + * + * Perform a soft reset of the system. Put the CPU into the + * same state as it would be if it had been reset, and branch + * to what would be the reset vector. + * + * - loc - location to jump to for soft reset + */ + .align 5 +ENTRY(cpu_v7_reset) + mov pc, r0 +ENDPROC(cpu_v7_reset) + +/* + * cpu_v7_do_idle() + * + * Idle the processor (eg, wait for interrupt). + * + * IRQs are already disabled. + */ +ENTRY(cpu_v7_do_idle) + dsb @ WFI may enter a low-power mode + wfi + mov pc, lr +ENDPROC(cpu_v7_do_idle) + +ENTRY(cpu_v7_dcache_clean_area) +#ifndef TLB_CAN_READ_FROM_L1_CACHE + dcache_line_size r2, r3 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, r2 + subs r1, r1, r2 + bhi 1b + dsb +#endif + mov pc, lr +ENDPROC(cpu_v7_dcache_clean_area) + +/* + * cpu_v7_switch_mm(pgd_phys, tsk) + * + * Set the translation table base pointer to be pgd_phys + * + * - pgd_phys - physical address of new TTB + * + * It is assumed that: + * - we are not using split page tables + */ +ENTRY(cpu_v7_switch_mm) +#ifdef CONFIG_MMU + ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id + mov r2, #0 + and r3, r1, #0xff + mov r3, r3, lsl #(48 - 32) @ ASID + mcrr p15, 0, r0, r3, c2 @ set TTB 0 + isb +#endif + mov pc, lr +ENDPROC(cpu_v7_switch_mm) + +/* + * cpu_v7_set_pte_ext(ptep, pte) + * + * Set a level 2 translation table entry. + * + * - ptep - pointer to level 2 translation table entry + * (hardware version is stored at +2048 bytes) + * - pte - PTE value to store + * - ext - value for extended PTE bits + */ +ENTRY(cpu_v7_set_pte_ext) +#ifdef CONFIG_MMU + tst r2, #L_PTE_PRESENT + beq 1f + tst r3, #1 << (55 - 32) @ L_PTE_DIRTY + orreq r2, #L_PTE_RDONLY +1: strd r2, r3, [r0] + mcr p15, 0, r0, c7, c10, 1 @ flush_pte +#endif + mov pc, lr +ENDPROC(cpu_v7_set_pte_ext) + +cpu_v7_name: + .ascii "ARMv7 Processor" + .align + + /* + * Memory region attributes for LPAE (defined in pgtable-3level.h): + * + * n = AttrIndx[2:0] + * + * n MAIR + * UNCACHED 000 00000000 + * BUFFERABLE 001 01000100 + * DEV_WC 001 01000100 + * WRITETHROUGH 010 10101010 + * WRITEBACK 011 11101110 + * DEV_CACHED 011 11101110 + * DEV_SHARED 100 00000100 + * DEV_NONSHARED 100 00000100 + * unused 101 + * unused 110 + * WRITEALLOC 111 11111111 + */ +.equ MAIR0, 0xeeaa4400 @ MAIR0 +.equ MAIR1, 0xff000004 @ MAIR1 + +/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ +.globl cpu_v7_suspend_size +.equ cpu_v7_suspend_size, 4 * 10 +#ifdef CONFIG_PM_SLEEP +ENTRY(cpu_v7_do_suspend) + stmfd sp!, {r4 - r11, lr} + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID + mrc p15, 0, r5, c13, c0, 1 @ Context ID + mrc p15, 0, r6, c3, c0, 0 @ Domain ID + mrrc p15, 0, r7, r8, c2 @ TTB 0 + mrrc p15, 1, r2, r3, c2 @ TTB 1 + mrc p15, 0, r9, c1, c0, 0 @ Control register + mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control + stmia r0, {r2 - r11} + ldmfd sp!, {r4 - r11, pc} +ENDPROC(cpu_v7_do_suspend) + +ENTRY(cpu_v7_do_resume) + mov ip, #0 + mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + ldmia r0, {r2 - r11} + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID + mcr p15, 0, r5, c13, c0, 1 @ Context ID + mcr p15, 0, r6, c3, c0, 0 @ Domain ID + mcrr p15, 0, r7, r8, c2 @ TTB 0 + mcrr p15, 1, r2, r3, c2 @ TTB 1 + mcr p15, 0, ip, c2, c0, 2 @ TTB control register + mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control + ldr r4, =MAIR0 + ldr r5, =MAIR1 + mcr p15, 0, r4, c10, c2, 0 @ write MAIR0 + mcr p15, 0, r5, c10, c2, 1 @ write MAIR1 + isb + mov r0, r9 @ control register + mov r2, r7, lsr #14 @ get TTB0 base + mov r2, r2, lsl #14 + ldr r3, cpu_resume_l1_flags + b cpu_resume_mmu +ENDPROC(cpu_v7_do_resume) +cpu_resume_l1_flags: + ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) + ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) +#else +#define cpu_v7_do_suspend 0 +#define cpu_v7_do_resume 0 +#endif + + __CPUINIT + +/* + * __v7_setup + * + * Initialise TLB, Caches, and MMU state ready to switch the MMU + * on. Return in r0 the new CP15 C1 control register setting. + * + * This should be able to cover all ARMv7 cores with LPAE. + * + * It is assumed that: + * - cache type register is implemented + */ +__v7_ca15mp_setup: + mov r10, #0 +1: +#ifdef CONFIG_SMP + ALT_SMP(mrc p15, 0, r0, c1, c0, 1) + ALT_UP(mov r0, #(1 << 6)) @ fake it for UP + tst r0, #(1 << 6) @ SMP/nAMP mode enabled? + orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode + orreq r0, r0, r10 @ Enable CPU-specific SMP bits + mcreq p15, 0, r0, c1, c0, 1 +#endif +__v7_setup: + adr r12, __v7_setup_stack @ the local stack + stmia r12, {r0-r5, r7, r9, r11, lr} + bl v7_flush_dcache_all + ldmia r12, {r0-r5, r7, r9, r11, lr} + + mov r10, #0 + mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate + dsb +#ifdef CONFIG_MMU + mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs + mov r5, #TTB_EAE + ALT_SMP(orr r5, r5, #TTB_FLAGS_SMP) + ALT_SMP(orr r5, r5, #TTB_FLAGS_SMP << 16) + ALT_UP(orr r5, r5, #TTB_FLAGS_UP) + ALT_UP(orr r5, r5, #TTB_FLAGS_UP << 16) + mrc p15, 0, r10, c2, c0, 2 + orr r10, r10, r5 +#if PHYS_OFFSET <= PAGE_OFFSET + /* + * TTBR0/TTBR1 split (PAGE_OFFSET): + * 0x40000000: T0SZ = 2, T1SZ = 0 (not used) + * 0x80000000: T0SZ = 0, T1SZ = 1 + * 0xc0000000: T0SZ = 0, T1SZ = 2 + * + * Only use this feature if PAGE_OFFSET <= PAGE_OFFSET, otherwise + * booting secondary CPUs would end up using TTBR1 for the identity + * mapping set up in TTBR0. + */ + orr r10, r10, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ +#endif + mcr p15, 0, r10, c2, c0, 2 @ TTB control register + mov r5, #0 +#if defined CONFIG_VMSPLIT_2G + /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */ + add r6, r8, #1 << 4 @ skip two L1 entries +#elif defined CONFIG_VMSPLIT_3G + /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */ + add r6, r8, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd +#else + mov r6, r8 +#endif + mcrr p15, 1, r6, r5, c2 @ load TTBR1 + ldr r5, =MAIR0 + ldr r6, =MAIR1 + mcr p15, 0, r5, c10, c2, 0 @ write MAIR0 + mcr p15, 0, r6, c10, c2, 1 @ write MAIR1 +#endif + adr r5, v7_crval + ldmia r5, {r5, r6} +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r6, r6, #1 << 25 @ big-endian page tables +#endif +#ifdef CONFIG_SWP_EMULATE + orr r5, r5, #(1 << 10) @ set SW bit in "clear" + bic r6, r6, #(1 << 10) @ clear it in "mmuset" +#endif + mrc p15, 0, r0, c1, c0, 0 @ read control register + bic r0, r0, r5 @ clear bits them + orr r0, r0, r6 @ set them + THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions + mov pc, lr @ return to head.S:__ret +ENDPROC(__v7_setup) + + /* AT + * TFR EV X F IHD LR S + * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM + * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced + * 11 0 110 1 0011 1100 .111 1101 < we want + */ + .type v7_crval, #object +v7_crval: + crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c + +__v7_setup_stack: + .space 4 * 11 @ 11 registers + + __INITDATA + + .type v7_processor_functions, #object +ENTRY(v7_processor_functions) + .word v7_early_abort + .word v7_pabort + .word cpu_v7_proc_init + .word cpu_v7_proc_fin + .word cpu_v7_reset + .word cpu_v7_do_idle + .word cpu_v7_dcache_clean_area + .word cpu_v7_switch_mm + .word cpu_v7_set_pte_ext + .word 0 + .word 0 + .word 0 + .size v7_processor_functions, . - v7_processor_functions + + .section ".rodata" + + .type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv7" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v7" + .size cpu_elf_name, . - cpu_elf_name + .align + + .section ".proc.info.init", #alloc, #execinstr + + .type __v7_ca15mp_proc_info, #object +__v7_ca15mp_proc_info: + .long 0x410fc0f0 @ Required ID value + .long 0xff0ffff0 @ Mask for ID + ALT_SMP(.long \ + PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_SECT_AF | \ + PMD_FLAGS_SMP) + ALT_UP(.long \ + PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_SECT_AF | \ + PMD_FLAGS_UP) + /* PMD_SECT_XN is set explicitly in head.S for LPAE */ + .long PMD_TYPE_SECT | \ + PMD_SECT_XN | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_SECT_AF + b __v7_ca15mp_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS + .long cpu_v7_name + .long v7_processor_functions + .long v7wbi_tlb_fns + .long v6_user_fns + .long v7_cache_fns + .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info + + /* + * Match any ARMv7 processor core. + */ + .type __v7_proc_info, #object +__v7_proc_info: + .long 0x000f0000 @ Required ID value + .long 0x000f0000 @ Mask for ID + ALT_SMP(.long \ + PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_SECT_AF | \ + PMD_FLAGS_SMP) + ALT_UP(.long \ + PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_SECT_AF | \ + PMD_FLAGS_UP) + /* PMD_SECT_XN is set explicitly in head.S for LPAE */ + .long PMD_TYPE_SECT | \ + PMD_SECT_XN | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_SECT_AF + W(b) __v7_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS + .long cpu_v7_name + .long v7_processor_functions + .long v7wbi_tlb_fns + .long v6_user_fns + .long v7_cache_fns + .size __v7_proc_info, . - __v7_proc_info diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index a1387875a491..d53c35fe2ea7 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o +obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o # MX51 uses the TZIC interrupt controller, older platforms use AVIC obj-$(CONFIG_MXC_TZIC) += tzic.o diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index 09e2bd0fcdca..55d2534ec727 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c @@ -46,6 +46,8 @@ #define AVIC_FIPNDH 0x60 /* fast int pending high */ #define AVIC_FIPNDL 0x64 /* fast int pending low */ +#define AVIC_NUM_IRQS 64 + void __iomem *avic_base; #ifdef CONFIG_MXC_IRQ_PRIOR @@ -54,7 +56,7 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio) unsigned int temp; unsigned int mask = 0x0F << irq % 8 * 4; - if (irq >= MXC_INTERNAL_IRQS) + if (irq >= AVIC_NUM_IRQS) return -EINVAL;; temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); @@ -72,14 +74,14 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type) { unsigned int irqt; - if (irq >= MXC_INTERNAL_IRQS) + if (irq >= AVIC_NUM_IRQS) return -EINVAL; - if (irq < MXC_INTERNAL_IRQS / 2) { + if (irq < AVIC_NUM_IRQS / 2) { irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); } else { - irq -= MXC_INTERNAL_IRQS / 2; + irq -= AVIC_NUM_IRQS / 2; irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); } @@ -138,7 +140,7 @@ void __init mxc_init_irq(void __iomem *irqbase) /* all IRQ no FIQ */ __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); - for (i = 0; i < MXC_INTERNAL_IRQS; i++) { + for (i = 0; i < AVIC_NUM_IRQS; i++) { irq_set_chip_and_handler(i, &mxc_avic_chip.base, handle_level_irq); set_irq_flags(i, IRQF_VALID); diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index eee1b6096a08..fb166b20f60f 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -89,3 +89,14 @@ err: return pdev; } + +struct device mxc_aips_bus = { + .init_name = "mxc_aips", + .parent = &platform_bus, +}; + +static int __init mxc_device_init(void) +{ + return device_register(&mxc_aips_bus); +} +core_initcall(mxc_device_init); diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index ad2922acf480..b41bf972b54b 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o +obj-y += platform-gpio-mxc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o diff --git a/arch/arm/plat-mxc/devices/platform-gpio-mxc.c b/arch/arm/plat-mxc/devices/platform-gpio-mxc.c new file mode 100644 index 000000000000..cf1b7fdfa20d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-gpio-mxc.c @@ -0,0 +1,32 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/devices-common.h> + +struct platform_device *__init mxc_register_gpio(int id, + resource_size_t iobase, resource_size_t iosize, int irq, int irq_high) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, { + .start = irq_high, + .end = irq_high, + .flags = IORESOURCE_IRQ, + }, + }; + + return platform_device_register_resndata(&mxc_aips_bus, + "gpio-mxc", id, res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 3538b85ede91..b130f60ca6b7 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -139,7 +139,7 @@ static struct sdma_script_start_addrs addr_imx35_to2 = { #endif #ifdef CONFIG_SOC_IMX51 -static struct sdma_script_start_addrs addr_imx51_to1 = { +static struct sdma_script_start_addrs addr_imx51 = { .ap_2_ap_addr = 642, .uart_2_mcu_addr = 817, .mcu_2_app_addr = 747, @@ -196,7 +196,9 @@ static int __init imxXX_add_imx_dma(void) #if defined(CONFIG_SOC_IMX51) if (cpu_is_mx51()) { - imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; + int to_version = mx51_revision() >> 4; + imx51_imx_sdma_data.pdata.to_version = to_version; + imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51; ret = imx_add_imx_sdma(&imx51_imx_sdma_data); } else #endif diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c deleted file mode 100644 index 6cd6d7f686f6..000000000000 --- a/arch/arm/plat-mxc/gpio.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * Based on code from Freescale, - * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <mach/hardware.h> -#include <asm-generic/bug.h> - -static struct mxc_gpio_port *mxc_gpio_ports; -static int gpio_table_size; - -#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2()) - -#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00) -#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04) -#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08) -#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C) -#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) -#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) -#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) - -#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) -#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) -#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2) -#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3) -#define GPIO_INT_NONE 0x4 - -/* Note: This driver assumes 32 GPIOs are handled in one register */ - -static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) -{ - __raw_writel(1 << index, port->base + GPIO_ISR); -} - -static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index, - int enable) -{ - u32 l; - - l = __raw_readl(port->base + GPIO_IMR); - l = (l & (~(1 << index))) | (!!enable << index); - __raw_writel(l, port->base + GPIO_IMR); -} - -static void gpio_ack_irq(struct irq_data *d) -{ - u32 gpio = irq_to_gpio(d->irq); - _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f); -} - -static void gpio_mask_irq(struct irq_data *d) -{ - u32 gpio = irq_to_gpio(d->irq); - _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0); -} - -static void gpio_unmask_irq(struct irq_data *d) -{ - u32 gpio = irq_to_gpio(d->irq); - _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1); -} - -static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset); - -static int gpio_set_irq_type(struct irq_data *d, u32 type) -{ - u32 gpio = irq_to_gpio(d->irq); - struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32]; - u32 bit, val; - int edge; - void __iomem *reg = port->base; - - port->both_edges &= ~(1 << (gpio & 31)); - switch (type) { - case IRQ_TYPE_EDGE_RISING: - edge = GPIO_INT_RISE_EDGE; - break; - case IRQ_TYPE_EDGE_FALLING: - edge = GPIO_INT_FALL_EDGE; - break; - case IRQ_TYPE_EDGE_BOTH: - val = mxc_gpio_get(&port->chip, gpio & 31); - if (val) { - edge = GPIO_INT_LOW_LEV; - pr_debug("mxc: set GPIO %d to low trigger\n", gpio); - } else { - edge = GPIO_INT_HIGH_LEV; - pr_debug("mxc: set GPIO %d to high trigger\n", gpio); - } - port->both_edges |= 1 << (gpio & 31); - break; - case IRQ_TYPE_LEVEL_LOW: - edge = GPIO_INT_LOW_LEV; - break; - case IRQ_TYPE_LEVEL_HIGH: - edge = GPIO_INT_HIGH_LEV; - break; - default: - return -EINVAL; - } - - reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ - bit = gpio & 0xf; - val = __raw_readl(reg) & ~(0x3 << (bit << 1)); - __raw_writel(val | (edge << (bit << 1)), reg); - _clear_gpio_irqstatus(port, gpio & 0x1f); - - return 0; -} - -static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) -{ - void __iomem *reg = port->base; - u32 bit, val; - int edge; - - reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ - bit = gpio & 0xf; - val = __raw_readl(reg); - edge = (val >> (bit << 1)) & 3; - val &= ~(0x3 << (bit << 1)); - if (edge == GPIO_INT_HIGH_LEV) { - edge = GPIO_INT_LOW_LEV; - pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); - } else if (edge == GPIO_INT_LOW_LEV) { - edge = GPIO_INT_HIGH_LEV; - pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); - } else { - pr_err("mxc: invalid configuration for GPIO %d: %x\n", - gpio, edge); - return; - } - __raw_writel(val | (edge << (bit << 1)), reg); -} - -/* handle 32 interrupts in one status register */ -static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) -{ - u32 gpio_irq_no_base = port->virtual_irq_start; - - while (irq_stat != 0) { - int irqoffset = fls(irq_stat) - 1; - - if (port->both_edges & (1 << irqoffset)) - mxc_flip_edge(port, irqoffset); - - generic_handle_irq(gpio_irq_no_base + irqoffset); - - irq_stat &= ~(1 << irqoffset); - } -} - -/* MX1 and MX3 has one interrupt *per* gpio port */ -static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) -{ - u32 irq_stat; - struct mxc_gpio_port *port = irq_get_handler_data(irq); - - irq_stat = __raw_readl(port->base + GPIO_ISR) & - __raw_readl(port->base + GPIO_IMR); - - mxc_gpio_irq_handler(port, irq_stat); -} - -/* MX2 has one interrupt *for all* gpio ports */ -static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) -{ - int i; - u32 irq_msk, irq_stat; - struct mxc_gpio_port *port = irq_get_handler_data(irq); - - /* walk through all interrupt status registers */ - for (i = 0; i < gpio_table_size; i++) { - irq_msk = __raw_readl(port[i].base + GPIO_IMR); - if (!irq_msk) - continue; - - irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk; - if (irq_stat) - mxc_gpio_irq_handler(&port[i], irq_stat); - } -} - -/* - * Set interrupt number "irq" in the GPIO as a wake-up source. - * While system is running, all registered GPIO interrupts need to have - * wake-up enabled. When system is suspended, only selected GPIO interrupts - * need to have wake-up enabled. - * @param irq interrupt source number - * @param enable enable as wake-up if equal to non-zero - * @return This function returns 0 on success. - */ -static int gpio_set_wake_irq(struct irq_data *d, u32 enable) -{ - u32 gpio = irq_to_gpio(d->irq); - u32 gpio_idx = gpio & 0x1F; - struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32]; - - if (enable) { - if (port->irq_high && (gpio_idx >= 16)) - enable_irq_wake(port->irq_high); - else - enable_irq_wake(port->irq); - } else { - if (port->irq_high && (gpio_idx >= 16)) - disable_irq_wake(port->irq_high); - else - disable_irq_wake(port->irq); - } - - return 0; -} - -static struct irq_chip gpio_irq_chip = { - .name = "GPIO", - .irq_ack = gpio_ack_irq, - .irq_mask = gpio_mask_irq, - .irq_unmask = gpio_unmask_irq, - .irq_set_type = gpio_set_irq_type, - .irq_set_wake = gpio_set_wake_irq, -}; - -static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, - int dir) -{ - struct mxc_gpio_port *port = - container_of(chip, struct mxc_gpio_port, chip); - u32 l; - unsigned long flags; - - spin_lock_irqsave(&port->lock, flags); - l = __raw_readl(port->base + GPIO_GDIR); - if (dir) - l |= 1 << offset; - else - l &= ~(1 << offset); - __raw_writel(l, port->base + GPIO_GDIR); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct mxc_gpio_port *port = - container_of(chip, struct mxc_gpio_port, chip); - void __iomem *reg = port->base + GPIO_DR; - u32 l; - unsigned long flags; - - spin_lock_irqsave(&port->lock, flags); - l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset); - __raw_writel(l, reg); - spin_unlock_irqrestore(&port->lock, flags); -} - -static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct mxc_gpio_port *port = - container_of(chip, struct mxc_gpio_port, chip); - - return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1; -} - -static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - _set_gpio_direction(chip, offset, 0); - return 0; -} - -static int mxc_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - mxc_gpio_set(chip, offset, value); - _set_gpio_direction(chip, offset, 1); - return 0; -} - -/* - * This lock class tells lockdep that GPIO irqs are in a different - * category than their parents, so it won't report false recursion. - */ -static struct lock_class_key gpio_lock_class; - -int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) -{ - int i, j; - - /* save for local usage */ - mxc_gpio_ports = port; - gpio_table_size = cnt; - - printk(KERN_INFO "MXC GPIO hardware\n"); - - for (i = 0; i < cnt; i++) { - /* disable the interrupt and clear the status */ - __raw_writel(0, port[i].base + GPIO_IMR); - __raw_writel(~0, port[i].base + GPIO_ISR); - for (j = port[i].virtual_irq_start; - j < port[i].virtual_irq_start + 32; j++) { - irq_set_lockdep_class(j, &gpio_lock_class); - irq_set_chip_and_handler(j, &gpio_irq_chip, - handle_level_irq); - set_irq_flags(j, IRQF_VALID); - } - - /* register gpio chip */ - port[i].chip.direction_input = mxc_gpio_direction_input; - port[i].chip.direction_output = mxc_gpio_direction_output; - port[i].chip.get = mxc_gpio_get; - port[i].chip.set = mxc_gpio_set; - port[i].chip.base = i * 32; - port[i].chip.ngpio = 32; - - spin_lock_init(&port[i].lock); - - /* its a serious configuration bug when it fails */ - BUG_ON( gpiochip_add(&port[i].chip) < 0 ); - - if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { - /* setup one handler for each entry */ - irq_set_chained_handler(port[i].irq, - mx3_gpio_irq_handler); - irq_set_handler_data(port[i].irq, &port[i]); - if (port[i].irq_high) { - /* setup handler for GPIO 16 to 31 */ - irq_set_chained_handler(port[i].irq_high, - mx3_gpio_irq_handler); - irq_set_handler_data(port[i].irq_high, - &port[i]); - } - } - } - - if (cpu_is_mx2()) { - /* setup one handler for all GPIO interrupts */ - irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler); - irq_set_handler_data(port[0].irq, port); - } - - return 0; -} diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index da7991832af6..91fa2632aa5e 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -43,6 +43,15 @@ extern void mx35_init_irq(void); extern void mx50_init_irq(void); extern void mx51_init_irq(void); extern void mx53_init_irq(void); +extern void imx1_soc_init(void); +extern void imx21_soc_init(void); +extern void imx25_soc_init(void); +extern void imx27_soc_init(void); +extern void imx31_soc_init(void); +extern void imx35_soc_init(void); +extern void imx50_soc_init(void); +extern void imx51_soc_init(void); +extern void imx53_soc_init(void); extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); @@ -55,7 +64,8 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); -extern int mxc_register_gpios(void); +extern struct platform_device *mxc_register_gpio(int id, + resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); extern void mxc_arch_reset_init(void __iomem *); diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index fa8477337f91..03f626645374 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -10,6 +10,8 @@ #include <linux/platform_device.h> #include <linux/init.h> +extern struct device mxc_aips_bus; + struct platform_device *imx_add_platform_device_dmamask( const char *name, int id, const struct resource *res, unsigned int num_resources, diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index a2747f12813e..31c820c1b796 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -36,31 +36,4 @@ #define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio)) #define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) -struct mxc_gpio_port { - void __iomem *base; - int irq; - int irq_high; - int virtual_irq_start; - struct gpio_chip chip; - u32 both_edges; - spinlock_t lock; -}; - -#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \ - { \ - .chip.label = "gpio-" #_id, \ - .irq = _irq, \ - .irq_high = _irq_high, \ - .base = soc ## _IO_ADDRESS( \ - soc ## _GPIO ## _hwid ## _BASE_ADDR), \ - .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ - } - -#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ - DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0) -#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ - DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) - -int mxc_gpio_init(struct mxc_gpio_port*, int); - #endif diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 67d3e2bed065..a8bfd565dcad 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -97,35 +97,17 @@ #include <mach/mxc.h> -#ifdef CONFIG_ARCH_MX5 #include <mach/mx50.h> #include <mach/mx51.h> #include <mach/mx53.h> -#endif - -#ifdef CONFIG_ARCH_MX3 #include <mach/mx3x.h> #include <mach/mx31.h> #include <mach/mx35.h> -#endif - -#ifdef CONFIG_ARCH_MX2 -# include <mach/mx2x.h> -# ifdef CONFIG_MACH_MX21 -# include <mach/mx21.h> -# endif -# ifdef CONFIG_MACH_MX27 -# include <mach/mx27.h> -# endif -#endif - -#ifdef CONFIG_ARCH_MX1 -# include <mach/mx1.h> -#endif - -#ifdef CONFIG_ARCH_MX25 -# include <mach/mx25.h> -#endif +#include <mach/mx2x.h> +#include <mach/mx21.h> +#include <mach/mx27.h> +#include <mach/mx1.h> +#include <mach/mx25.h> #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index e95d9cb8aeb7..50b88a404fe4 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -958,12 +958,12 @@ #define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0) #define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0) #define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0) #define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) -#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0) +#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0) #define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0) #define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0) #define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0) diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h index c07d30210c57..a7fc51e5a041 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v1.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h @@ -85,9 +85,6 @@ #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) -/* decode irq number to use with IMR(x), ISR(x) and friends */ -#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) - #define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h deleted file mode 100644 index 3d226d7e7be2..000000000000 --- a/arch/arm/plat-mxc/include/mach/iomux.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __MACH_IOMUX_H__ -#define __MACH_IOMUX_H__ - -/* This file will go away, please include mach/iomux-mx... directly */ - -#ifdef CONFIG_ARCH_MX1 -#include <mach/iomux-mx1.h> -#endif -#ifdef CONFIG_ARCH_MX2 -#include <mach/iomux-mx2x.h> -#ifdef CONFIG_MACH_MX21 -#include <mach/iomux-mx21.h> -#endif -#ifdef CONFIG_MACH_MX27 -#include <mach/iomux-mx27.h> -#endif -#endif - -#endif /* __MACH_IOMUX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 9d2a1ef84de2..e14a4f04c696 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -145,14 +145,14 @@ /* * Memory regions and CS */ -#define MX53_CSD0_BASE_ADDR 0x90000000 -#define MX53_CSD1_BASE_ADDR 0xA0000000 -#define MX53_CS0_BASE_ADDR 0xB0000000 -#define MX53_CS1_BASE_ADDR 0xB8000000 -#define MX53_CS2_BASE_ADDR 0xC0000000 -#define MX53_CS3_BASE_ADDR 0xC8000000 -#define MX53_CS4_BASE_ADDR 0xCC000000 -#define MX53_CS5_BASE_ADDR 0xCE000000 +#define MX53_CSD0_BASE_ADDR 0x70000000 +#define MX53_CSD1_BASE_ADDR 0xB0000000 +#define MX53_CS0_BASE_ADDR 0xF0000000 +#define MX53_CS1_32MB_BASE_ADDR 0xF2000000 +#define MX53_CS1_64MB_BASE_ADDR 0xF4000000 +#define MX53_CS2_64MB_BASE_ADDR 0xF4000000 +#define MX53_CS2_96MB_BASE_ADDR 0xF6000000 +#define MX53_CS3_BASE_ADDR 0xF6000000 #define MX53_IO_P2V(x) IMX_IO_P2V(x) #define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 4ac53ce97c24..09879235a9f5 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -68,7 +68,7 @@ extern unsigned int __mxc_cpu_type; #endif -#ifdef CONFIG_ARCH_MX1 +#ifdef CONFIG_SOC_IMX1 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -80,7 +80,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx1() (0) #endif -#ifdef CONFIG_MACH_MX21 +#ifdef CONFIG_SOC_IMX21 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -92,7 +92,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx21() (0) #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -104,7 +104,7 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx25() (0) #endif -#ifdef CONFIG_MACH_MX27 +#ifdef CONFIG_SOC_IMX27 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index d61d5c74817c..10343d1f87e1 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -16,16 +16,7 @@ #ifndef __ASM_ARCH_MXC_TIMEX_H__ #define __ASM_ARCH_MXC_TIMEX_H__ -#if defined CONFIG_ARCH_MX1 -#define CLOCK_TICK_RATE 16000000 -#elif defined CONFIG_ARCH_MX2 -#define CLOCK_TICK_RATE 13300000 -#elif defined CONFIG_ARCH_MX3 -#define CLOCK_TICK_RATE 16625000 -#elif defined CONFIG_ARCH_MX25 -#define CLOCK_TICK_RATE 16000000 -#elif defined CONFIG_ARCH_MX5 -#define CLOCK_TICK_RATE 8000000 -#endif +/* Bogus value */ +#define CLOCK_TICK_RATE 12345678 #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index d85e2d1c0324..88fd40452567 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -117,6 +117,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MX53_EVK: case MACH_TYPE_MX53_LOCO: case MACH_TYPE_MX53_SMD: + case MACH_TYPE_MX53_ARD: uart_base = MX53_UART1_BASE_ADDR; break; default: diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c index e1c6eff7258a..96953e2e4f11 100644 --- a/arch/arm/plat-mxc/irq-common.c +++ b/arch/arm/plat-mxc/irq-common.c @@ -42,17 +42,16 @@ EXPORT_SYMBOL(imx_irq_set_priority); int mxc_set_irq_fiq(unsigned int irq, unsigned int type) { - struct mxc_irq_chip *chip; - struct irq_chip *base; + struct irq_chip_generic *gc; + int (*set_irq_fiq)(unsigned int, unsigned int); int ret; ret = -ENOSYS; - base = irq_get_chip(irq); - if (base) { - chip = container_of(base, struct mxc_irq_chip, base); - if (chip->set_irq_fiq) - ret = chip->set_irq_fiq(irq, type); + gc = irq_get_chip_data(irq); + if (gc && gc->private) { + set_irq_fiq = gc->private; + ret = set_irq_fiq(irq, type); } return ret; diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index 7a61ef8f471a..761c3c940a68 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -214,14 +214,14 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) goto err_free_clk; } - r = request_mem_region(r->start, r->end - r->start + 1, pdev->name); + r = request_mem_region(r->start, resource_size(r), pdev->name); if (r == NULL) { dev_err(&pdev->dev, "failed to request memory resource\n"); ret = -EBUSY; goto err_free_clk; } - pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); + pwm->mmio_base = ioremap(r->start, resource_size(r)); if (pwm->mmio_base == NULL) { dev_err(&pdev->dev, "failed to ioremap() registers\n"); ret = -ENODEV; @@ -236,7 +236,7 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) return 0; err_free_mem: - release_mem_region(r->start, r->end - r->start + 1); + release_mem_region(r->start, resource_size(r)); err_free_clk: clk_put(pwm->clk); err_free: @@ -260,7 +260,7 @@ static int __devexit mxc_pwm_remove(struct platform_device *pdev) iounmap(pwm->mmio_base); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(r->start, r->end - r->start + 1); + release_mem_region(r->start, resource_size(r)); clk_put(pwm->clk); diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 57f9395f87ce..f257fccdc394 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -49,6 +49,8 @@ void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ +#define TZIC_NUM_IRQS 128 + #ifdef CONFIG_FIQ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) { @@ -66,78 +68,34 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) return 0; } +#else +#define tzic_set_irq_fiq NULL #endif -/** - * tzic_mask_irq() - Disable interrupt source "d" in the TZIC - * - * @param d interrupt source - */ -static void tzic_mask_irq(struct irq_data *d) -{ - int index, off; - - index = d->irq >> 5; - off = d->irq & 0x1F; - __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); -} +static unsigned int *wakeup_intr[4]; -/** - * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC - * - * @param d interrupt source - */ -static void tzic_unmask_irq(struct irq_data *d) +static __init void tzic_init_gc(unsigned int irq_start) { - int index, off; - - index = d->irq >> 5; - off = d->irq & 0x1F; - __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + int idx = irq_start >> 5; + + gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, + handle_level_irq); + gc->private = tzic_set_irq_fiq; + gc->wake_enabled = IRQ_MSK(32); + wakeup_intr[idx] = &gc->wake_active; + + ct = gc->chip_types; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + ct->chip.irq_set_wake = irq_gc_set_wake; + ct->regs.disable = TZIC_ENCLEAR0(idx); + ct->regs.enable = TZIC_ENSET0(idx); + + irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); } -static unsigned int wakeup_intr[4]; - -/** - * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source. - * - * @param d interrupt source - * @param enable enable as wake-up if equal to non-zero - * disble as wake-up if equal to zero - * - * @return This function returns 0 on success. - */ -static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable) -{ - unsigned int index, off; - - index = d->irq >> 5; - off = d->irq & 0x1F; - - if (index > 3) - return -EINVAL; - - if (enable) - wakeup_intr[index] |= (1 << off); - else - wakeup_intr[index] &= ~(1 << off); - - return 0; -} - -static struct mxc_irq_chip mxc_tzic_chip = { - .base = { - .name = "MXC_TZIC", - .irq_ack = tzic_mask_irq, - .irq_mask = tzic_mask_irq, - .irq_unmask = tzic_unmask_irq, - .irq_set_wake = tzic_set_wake_irq, - }, -#ifdef CONFIG_FIQ - .set_irq_fiq = tzic_set_irq_fiq, -#endif -}; - /* * This function initializes the TZIC hardware and disables all the * interrupts. It registers the interrupt enable and disable functions @@ -166,11 +124,8 @@ void __init tzic_init_irq(void __iomem *irqbase) /* all IRQ no FIQ Warning :: No selection */ - for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - irq_set_chip_and_handler(i, &mxc_tzic_chip.base, - handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } + for (i = 0; i < TZIC_NUM_IRQS; i += 32) + tzic_init_gc(i); #ifdef CONFIG_FIQ /* Initialize FIQ */ @@ -197,7 +152,7 @@ int tzic_enable_wake(int is_idle) for (i = 0; i < 4; i++) { v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : - wakeup_intr[i]; + *wakeup_intr[i]; __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); } diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index a37b8eb65b76..49fc0df0c21f 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -84,6 +84,7 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/clkdev.h> +#include <linux/pm_runtime.h> #include <plat/omap_device.h> #include <plat/omap_hwmod.h> @@ -539,20 +540,34 @@ int omap_early_device_register(struct omap_device *od) static int _od_runtime_suspend(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); + int ret; + + ret = pm_generic_runtime_suspend(dev); + + if (!ret) + omap_device_idle(pdev); + + return ret; +} - return omap_device_idle(pdev); +static int _od_runtime_idle(struct device *dev) +{ + return pm_generic_runtime_idle(dev); } static int _od_runtime_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); - return omap_device_enable(pdev); + omap_device_enable(pdev); + + return pm_generic_runtime_resume(dev); } static struct dev_power_domain omap_device_power_domain = { .ops = { .runtime_suspend = _od_runtime_suspend, + .runtime_idle = _od_runtime_idle, .runtime_resume = _od_runtime_resume, USE_PLATFORM_PM_SLEEP_OPS } diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c index cf97caafe56b..f95d3268ae1f 100644 --- a/arch/arm/plat-s3c24xx/clock-dclk.c +++ b/arch/arm/plat-s3c24xx/clock-dclk.c @@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = { struct clk s3c24xx_dclk0 = { .name = "dclk0", - .id = -1, .ctrlbit = S3C2410_DCLKCON_DCLK0EN, .enable = s3c24xx_dclk_enable, .ops = &dclk_ops, @@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = { struct clk s3c24xx_dclk1 = { .name = "dclk1", - .id = -1, .ctrlbit = S3C2410_DCLKCON_DCLK1EN, .enable = s3c24xx_dclk_enable, .ops = &dclk_ops, @@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = { struct clk s3c24xx_clkout0 = { .name = "clkout0", - .id = -1, .ops = &clkout_ops, }; struct clk s3c24xx_clkout1 = { .name = "clkout1", - .id = -1, .ops = &clkout_ops, }; diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do {} while (0) + +#endif diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c index 9ecc5d913679..def76aa3825a 100644 --- a/arch/arm/plat-s3c24xx/s3c2410-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c @@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable) static struct clk init_clocks_off[] = { { .name = "nand", - .id = -1, .parent = &clk_h, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_NAND, }, { .name = "sdi", - .id = -1, .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_SDI, }, { .name = "adc", - .id = -1, .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_ADC, }, { .name = "i2c", - .id = -1, .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_IIC, }, { .name = "iis", - .id = -1, .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_IIS, }, { .name = "spi", - .id = -1, .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_SPI, @@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = { static struct clk init_clocks[] = { { .name = "lcd", - .id = -1, .parent = &clk_h, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_LCDC, }, { .name = "gpio", - .id = -1, .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_GPIO, }, { .name = "usb-host", - .id = -1, .parent = &clk_h, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_USBH, }, { .name = "usb-device", - .id = -1, .parent = &clk_h, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_USBD, }, { .name = "timers", - .id = -1, .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_PWMT, }, { .name = "uart", - .id = 0, + .devname = "s3c2410-uart.0", .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_UART0, }, { .name = "uart", - .id = 1, + .devname = "s3c2410-uart.1", .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_UART1, }, { .name = "uart", - .id = 2, + .devname = "s3c2410-uart.2", .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_UART2, }, { .name = "rtc", - .id = -1, .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit = S3C2410_CLKCON_RTC, }, { .name = "watchdog", - .id = -1, .parent = &clk_p, .ctrlbit = 0, }, { .name = "usb-bus-host", - .id = -1, .parent = &clk_usb_bus, }, { .name = "usb-bus-gadget", - .id = -1, .parent = &clk_usb_bus, }, }; diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 82f2d4a39291..59552c0ea5fb 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable) struct clk clk_mpllref = { .name = "mpllref", .parent = &clk_xtal, - .id = -1, }; static struct clk *clk_epllref_sources[] = { @@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = { struct clksrc_clk clk_epllref = { .clk = { .name = "epllref", - .id = -1, }, .sources = &(struct clksrc_sources) { .sources = clk_epllref_sources, @@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = { .clk = { .name = "esysclk", .parent = &clk_epll, - .id = -1, }, .sources = &(struct clksrc_sources) { .sources = clk_sysclk_sources, @@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) static struct clk clk_mdivclk = { .name = "mdivclk", .parent = &clk_mpllref, - .id = -1, .ops = &(struct clk_ops) { .get_rate = s3c2443_getrate_mdivclk, }, @@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = { .clk = { .name = "msysclk", .parent = &clk_xtal, - .id = -1, }, .sources = &(struct clksrc_sources) { .sources = clk_msysclk_sources, @@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk) static struct clk clk_prediv = { .name = "prediv", - .id = -1, .parent = &clk_msysclk.clk, .ops = &(struct clk_ops) { .get_rate = s3c2443_prediv_getrate, @@ -174,7 +168,6 @@ static struct clk clk_prediv = { static struct clksrc_clk clk_usb_bus_host = { .clk = { .name = "usb-bus-host-parent", - .id = -1, .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_USBHOST, .enable = s3c2443_clkcon_enable_s, @@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = { /* ART baud-rate clock sourced from esysclk via a divisor */ .clk = { .name = "uartclk", - .id = -1, .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, @@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = { /* camera interface bus-clock, divided down from esysclk */ .clk = { .name = "camif-upll", /* same as 2440 name */ - .id = -1, .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_CAMCLK, .enable = s3c2443_clkcon_enable_s, @@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = { }, { .clk = { .name = "display-if", - .id = -1, .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_DISPCLK, .enable = s3c2443_clkcon_enable_s, @@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = { static struct clk init_clocks_off[] = { { .name = "adc", - .id = -1, .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_ADC, }, { .name = "i2c", - .id = -1, .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_IIC, @@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = { static struct clk init_clocks[] = { { .name = "dma", - .id = 0, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA0, }, { .name = "dma", - .id = 1, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA1, }, { .name = "dma", - .id = 2, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA2, }, { .name = "dma", - .id = 3, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA3, }, { .name = "dma", - .id = 4, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA4, }, { .name = "dma", - .id = 5, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA5, }, { .name = "hsmmc", - .id = 1, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_HSMMC, }, { .name = "gpio", - .id = -1, .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_GPIO, }, { .name = "usb-host", - .id = -1, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_USBH, }, { .name = "usb-device", - .id = -1, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_USBD, }, { .name = "lcd", - .id = -1, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_LCDC, }, { .name = "timers", - .id = -1, .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_PWMT, }, { .name = "cfc", - .id = -1, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_CFC, }, { .name = "ssmc", - .id = -1, .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_SSMC, }, { .name = "uart", - .id = 0, + .devname = "s3c2440-uart.0", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_UART0, }, { .name = "uart", - .id = 1, + .devname = "s3c2440-uart.1", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_UART1, }, { .name = "uart", - .id = 2, + .devname = "s3c2440-uart.2", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_UART2, }, { .name = "uart", - .id = 3, + .devname = "s3c2440-uart.3", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_UART3, }, { .name = "rtc", - .id = -1, .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_RTC, }, { .name = "watchdog", - .id = -1, .parent = &clk_p, .ctrlbit = S3C2443_PCLKCON_WDT, }, { .name = "ac97", - .id = -1, .parent = &clk_p, .ctrlbit = S3C2443_PCLKCON_AC97, }, { .name = "nand", - .id = -1, .parent = &clk_h, }, { .name = "usb-bus-host", - .id = -1, .parent = &clk_usb_bus_host.clk, } }; diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index fd7032f84ae7..6ada459498a8 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -48,22 +48,16 @@ */ ENTRY(s3c_cpu_save) - stmfd sp!, { r4 - r12, lr } - ldr r3, =resume_with_mmu - bl cpu_suspend + adr r3, BSYM(s3c24xx_finish_suspend) + b cpu_suspend +s3c24xx_finish_suspend: @@ jump to final code to send system to sleep ldr r0, =pm_cpu_sleep @@ldr pc, [ r0 ] ldr r0, [ r0 ] mov pc, r0 - @@ return to the caller, after having the MMU - @@ turned on, this restores the last bits from the - @@ stack -resume_with_mmu: - ldmfd sp!, { r4 - r12, pc } - .ltorg /* sleep magic, to allow the bootloader to check for an valid diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index e98f5c5c7879..7f9ff2afffd9 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -39,6 +39,7 @@ config S5P_GPIO_INT config S5P_HRT bool + select SAMSUNG_DEV_PWM help Use the High Resolution timer support diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index d973d39666a3..daa4a4452c67 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -40,6 +40,7 @@ #define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) #define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000) +#define S5P_VA_AUDSS S3C_ADDR(0x02A00000) #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c index 899a8cc011ff..b08667515237 100644 --- a/arch/arm/plat-s5p/s5p-time.c +++ b/arch/arm/plat-s5p/s5p-time.c @@ -384,6 +384,7 @@ static void __init s5p_timer_resources(void) unsigned long event_id = timer_source.event_id; unsigned long source_id = timer_source.source_id; + char devname[15]; timerclk = clk_get(NULL, "timers"); if (IS_ERR(timerclk)) @@ -391,6 +392,10 @@ static void __init s5p_timer_resources(void) clk_enable(timerclk); + sprintf(devname, "s3c24xx-pwm.%lu", event_id); + s3c_device_timer[event_id].id = event_id; + s3c_device_timer[event_id].dev.init_name = devname; + tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin"); if (IS_ERR(tin_event)) panic("failed to get pwm-tin clock for event timer"); @@ -401,6 +406,10 @@ static void __init s5p_timer_resources(void) clk_enable(tin_event); + sprintf(devname, "s3c24xx-pwm.%lu", source_id); + s3c_device_timer[source_id].id = source_id; + s3c_device_timer[source_id].dev.init_name = devname; + tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin"); if (IS_ERR(tin_source)) panic("failed to get pwm-tin clock for source timer"); diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 772892826ffc..aecf9e90d4fc 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable) return 0; } -static int dev_is_s3c_uart(struct device *dev) -{ - struct platform_device **pdev = s3c24xx_uart_devs; - int i; - for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++) - if (*pdev && dev == &(*pdev)->dev) - return 1; - return 0; -} - -/* - * Serial drivers call get_clock() very early, before platform bus - * has been set up, this requires a special check to let them get - * a proper clock - */ - -static int dev_is_platform_device(struct device *dev) -{ - return dev->bus == &platform_bus_type || - (dev->bus == NULL && dev_is_s3c_uart(dev)); -} - -/* Clock API calls */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p; - struct clk *clk = ERR_PTR(-ENOENT); - int idno; - - if (dev == NULL || !dev_is_platform_device(dev)) - idno = -1; - else - idno = to_platform_device(dev)->id; - - spin_lock(&clocks_lock); - - list_for_each_entry(p, &clocks, list) { - if (p->id == idno && - strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - - /* check for the case where a device was supplied, but the - * clock that was being searched for is not device specific */ - - if (IS_ERR(clk)) { - list_for_each_entry(p, &clocks, list) { - if (p->id == -1 && strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - } - - spin_unlock(&clocks_lock); - return clk; -} - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); -} - int clk_enable(struct clk *clk) { if (IS_ERR(clk) || clk == NULL) @@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent) return ret; } -EXPORT_SYMBOL(clk_get); -EXPORT_SYMBOL(clk_put); EXPORT_SYMBOL(clk_enable); EXPORT_SYMBOL(clk_disable); EXPORT_SYMBOL(clk_get_rate); @@ -265,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = { struct clk clk_xtal = { .name = "xtal", - .id = -1, .rate = 0, .parent = NULL, .ctrlbit = 0, @@ -273,30 +202,25 @@ struct clk clk_xtal = { struct clk clk_ext = { .name = "ext", - .id = -1, }; struct clk clk_epll = { .name = "epll", - .id = -1, }; struct clk clk_mpll = { .name = "mpll", - .id = -1, .ops = &clk_ops_def_setrate, }; struct clk clk_upll = { .name = "upll", - .id = -1, .parent = NULL, .ctrlbit = 0, }; struct clk clk_f = { .name = "fclk", - .id = -1, .rate = 0, .parent = &clk_mpll, .ctrlbit = 0, @@ -304,7 +228,6 @@ struct clk clk_f = { struct clk clk_h = { .name = "hclk", - .id = -1, .rate = 0, .parent = NULL, .ctrlbit = 0, @@ -313,7 +236,6 @@ struct clk clk_h = { struct clk clk_p = { .name = "pclk", - .id = -1, .rate = 0, .parent = NULL, .ctrlbit = 0, @@ -322,7 +244,6 @@ struct clk clk_p = { struct clk clk_usb_bus = { .name = "usb-bus", - .id = -1, .rate = 0, .parent = &clk_upll, }; @@ -330,7 +251,6 @@ struct clk clk_usb_bus = { struct clk s3c24xx_uclk = { .name = "uclk", - .id = -1, }; /* initialise the clock system */ @@ -346,14 +266,11 @@ int s3c24xx_register_clock(struct clk *clk) if (clk->enable == NULL) clk->enable = clk_null_enable; - /* add to the list of available clocks */ - - /* Quick check to see if this clock has already been registered. */ - BUG_ON(clk->list.prev != clk->list.next); - - spin_lock(&clocks_lock); - list_add(&clk->list, &clocks); - spin_unlock(&clocks_lock); + /* fill up the clk_lookup structure and register it*/ + clk->lookup.dev_id = clk->devname; + clk->lookup.con_id = clk->name; + clk->lookup.clk = clk; + clkdev_add(&clk->lookup); return 0; } @@ -463,10 +380,7 @@ static int clk_debugfs_register_one(struct clk *c) char s[255]; char *p = s; - p += sprintf(p, "%s", c->name); - - if (c->id >= 0) - sprintf(p, ":%d", c->id); + p += sprintf(p, "%s", c->devname); d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); if (!d) diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h index a0826ed2f9fe..5cee22577dd3 100644 --- a/arch/arm/plat-samsung/include/plat/audio.h +++ b/arch/arm/plat-samsung/include/plat/audio.h @@ -46,6 +46,13 @@ struct samsung_i2s { const char **src_clk; }; +struct samsung_pcm { +/* If the PCM block has no internal prescalar or MUX */ +#define QUIRK_NO_DIV (1 << 0) + /* Quirks of the PCM controller */ + u32 quirks; +}; + /** * struct s3c_audio_pdata - common platform data for audio device drivers * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode @@ -54,5 +61,6 @@ struct s3c_audio_pdata { int (*cfg_gpio)(struct platform_device *); union { struct samsung_i2s i2s; + struct samsung_pcm pcm; } type; }; diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 983c578b8276..87d5b38a86fb 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -10,6 +10,7 @@ */ #include <linux/spinlock.h> +#include <linux/clkdev.h> struct clk; @@ -40,6 +41,7 @@ struct clk { struct module *owner; struct clk *parent; const char *name; + const char *devname; int id; int usage; unsigned long rate; @@ -47,6 +49,7 @@ struct clk { struct clk_ops *ops; int (*enable)(struct clk *, int enable); + struct clk_lookup lookup; #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) struct dentry *dent; /* For visible tree hierarchy */ #endif diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index c151c5f94a87..116edfe120b9 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -224,6 +224,8 @@ #define S5PV210_UFSTAT_RXMASK (255<<0) #define S5PV210_UFSTAT_RXSHIFT (0) +#define NO_NEED_CHECK_CLKSRC 1 + #ifndef __ASSEMBLY__ /* struct s3c24xx_uart_clksrc diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 5c0a440d6e16..4f9a9515beae 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -268,6 +268,7 @@ static int s3c_pm_enter(suspend_state_t state) /* save all necessary core registers not covered by the drivers */ s3c_pm_save_gpios(); + s3c_pm_saved_gpios(); s3c_pm_save_uarts(); s3c_pm_save_core(); @@ -309,6 +310,7 @@ static int s3c_pm_enter(suspend_state_t state) s3c_pm_restore_core(); s3c_pm_restore_uarts(); s3c_pm_restore_gpios(); + s3c_pm_restored_gpios(); s3c_pm_debug_init(); diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c index 46c9381e083b..f1bba88ed2f5 100644 --- a/arch/arm/plat-samsung/pwm-clock.c +++ b/arch/arm/plat-samsung/pwm-clock.c @@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [0] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.0", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[0], }, @@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [1] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.1", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[0], } @@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [2] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.2", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[1], }, @@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [3] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.3", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[1], }, @@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [4] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.4", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[1], }, @@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = { static struct clk clk_tin[] = { [0] = { .name = "pwm-tin", + .devname = "s3c24xx-pwm.0", .id = 0, .ops = &clk_tin_ops, }, [1] = { .name = "pwm-tin", + .devname = "s3c24xx-pwm.1", .id = 1, .ops = &clk_tin_ops, }, [2] = { .name = "pwm-tin", + .devname = "s3c24xx-pwm.2", .id = 2, .ops = &clk_tin_ops, }, [3] = { .name = "pwm-tin", + .devname = "s3c24xx-pwm.3", .id = 3, .ops = &clk_tin_ops, }, [4] = { .name = "pwm-tin", + .devname = "s3c24xx-pwm.4", .id = 4, .ops = &clk_tin_ops, }, diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c index 2231d80ad817..e3bb806bbafe 100644 --- a/arch/arm/plat-samsung/time.c +++ b/arch/arm/plat-samsung/time.c @@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void) clk_enable(timerclk); if (!use_tclk1_12()) { + tmpdev.id = 4; + tmpdev.dev.init_name = "s3c24xx-pwm.4"; tin = clk_get(&tmpdev.dev, "pwm-tin"); if (IS_ERR(tin)) panic("failed to get pwm-tin clock for system timer"); diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig index 6f9ca56de1f6..a06bfccc2840 100644 --- a/arch/avr32/configs/atngw100_defconfig +++ b/arch/avr32/configs/atngw100_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atngw100_evklcd100_defconfig b/arch/avr32/configs/atngw100_evklcd100_defconfig index 7eece0af34c9..d8f1fe80d210 100644 --- a/arch/avr32/configs/atngw100_evklcd100_defconfig +++ b/arch/avr32/configs/atngw100_evklcd100_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atngw100_evklcd101_defconfig b/arch/avr32/configs/atngw100_evklcd101_defconfig index 387eb9d6e423..d4c5b19ec950 100644 --- a/arch/avr32/configs/atngw100_evklcd101_defconfig +++ b/arch/avr32/configs/atngw100_evklcd101_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atngw100_mrmt_defconfig b/arch/avr32/configs/atngw100_mrmt_defconfig index 19f6ceeeff7b..77ca4f905d2c 100644 --- a/arch/avr32/configs/atngw100_mrmt_defconfig +++ b/arch/avr32/configs/atngw100_mrmt_defconfig @@ -7,6 +7,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_SLUB_DEBUG is not set @@ -109,7 +110,7 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_S35390A=m CONFIG_RTC_DRV_AT32AP700X=m CONFIG_DMADEVICES=y diff --git a/arch/avr32/configs/atngw100mkii_defconfig b/arch/avr32/configs/atngw100mkii_defconfig index f0fe237133a9..6e0dca4d3131 100644 --- a/arch/avr32/configs/atngw100mkii_defconfig +++ b/arch/avr32/configs/atngw100mkii_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig index e4a7c1dc8380..7f2a344a5fa8 100644 --- a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig +++ b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig index 6f37f70c2c37..085eeba88f67 100644 --- a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig +++ b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig index 4fb01f5ab42f..d1a887e64055 100644 --- a/arch/avr32/configs/atstk1002_defconfig +++ b/arch/avr32/configs/atstk1002_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atstk1003_defconfig b/arch/avr32/configs/atstk1003_defconfig index 9faaf9b900f2..956f2819ad45 100644 --- a/arch/avr32/configs/atstk1003_defconfig +++ b/arch/avr32/configs/atstk1003_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atstk1004_defconfig b/arch/avr32/configs/atstk1004_defconfig index 3d2a5d85f970..40c69f38c61a 100644 --- a/arch/avr32/configs/atstk1004_defconfig +++ b/arch/avr32/configs/atstk1004_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig index 1ed8f22d4fe2..511eb8af356d 100644 --- a/arch/avr32/configs/atstk1006_defconfig +++ b/arch/avr32/configs/atstk1006_defconfig @@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/favr-32_defconfig b/arch/avr32/configs/favr-32_defconfig index aeadc955db32..19973b06170c 100644 --- a/arch/avr32/configs/favr-32_defconfig +++ b/arch/avr32/configs/favr-32_defconfig @@ -6,6 +6,7 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/hammerhead_defconfig b/arch/avr32/configs/hammerhead_defconfig index 1692beeb7ed3..6f45681196d1 100644 --- a/arch/avr32/configs/hammerhead_defconfig +++ b/arch/avr32/configs/hammerhead_defconfig @@ -7,6 +7,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/configs/merisc_defconfig b/arch/avr32/configs/merisc_defconfig index 8b670a6530bf..3befab966827 100644 --- a/arch/avr32/configs/merisc_defconfig +++ b/arch/avr32/configs/merisc_defconfig @@ -7,6 +7,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set CONFIG_MODULES=y diff --git a/arch/avr32/configs/mimc200_defconfig b/arch/avr32/configs/mimc200_defconfig index 5a51f2e7ffb9..1bee51f22154 100644 --- a/arch/avr32/configs/mimc200_defconfig +++ b/arch/avr32/configs/mimc200_defconfig @@ -7,6 +7,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_BASE_FULL is not set # CONFIG_COMPAT_BRK is not set diff --git a/arch/avr32/include/asm/processor.h b/arch/avr32/include/asm/processor.h index 49a88f5a9d2f..108502bc6770 100644 --- a/arch/avr32/include/asm/processor.h +++ b/arch/avr32/include/asm/processor.h @@ -131,7 +131,6 @@ struct thread_struct { */ #define start_thread(regs, new_pc, new_sp) \ do { \ - set_fs(USER_DS); \ memset(regs, 0, sizeof(*regs)); \ regs->sr = MODE_USER; \ regs->pc = new_pc & ~1; \ diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c index aa677e2a3823..7fbf0dcb9afe 100644 --- a/arch/avr32/mach-at32ap/at32ap700x.c +++ b/arch/avr32/mach-at32ap/at32ap700x.c @@ -1043,8 +1043,9 @@ void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags) data->regs = (void __iomem *)pdev->resource[0].start; } + pdev->id = line; pdata = pdev->dev.platform_data; - pdata->num = portnr; + pdata->num = line; at32_usarts[line] = pdev; } diff --git a/arch/avr32/mach-at32ap/include/mach/cpu.h b/arch/avr32/mach-at32ap/include/mach/cpu.h index 9c96a130f3a8..8181293115e4 100644 --- a/arch/avr32/mach-at32ap/include/mach/cpu.h +++ b/arch/avr32/mach-at32ap/include/mach/cpu.h @@ -31,8 +31,20 @@ #define cpu_is_at91sam9263() (0) #define cpu_is_at91sam9rl() (0) #define cpu_is_at91cap9() (0) +#define cpu_is_at91cap9_revB() (0) +#define cpu_is_at91cap9_revC() (0) #define cpu_is_at91sam9g10() (0) +#define cpu_is_at91sam9g20() (0) #define cpu_is_at91sam9g45() (0) #define cpu_is_at91sam9g45es() (0) +#define cpu_is_at91sam9m10() (0) +#define cpu_is_at91sam9g46() (0) +#define cpu_is_at91sam9m11() (0) +#define cpu_is_at91sam9x5() (0) +#define cpu_is_at91sam9g15() (0) +#define cpu_is_at91sam9g35() (0) +#define cpu_is_at91sam9x35() (0) +#define cpu_is_at91sam9g25() (0) +#define cpu_is_at91sam9x25() (0) #endif /* __ASM_ARCH_CPU_H */ diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c index 3e3646186c9f..c9ac2f8e8f64 100644 --- a/arch/avr32/mach-at32ap/intc.c +++ b/arch/avr32/mach-at32ap/intc.c @@ -167,14 +167,12 @@ static int intc_suspend(void) return 0; } -static int intc_resume(void) +static void intc_resume(void) { int i; for (i = 0; i < 64; i++) intc_writel(&intc0, INTPR0 + 4 * i, intc0.saved_ipr[i]); - - return 0; } #else #define intc_suspend NULL diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index d619b17c4413..c7476295de80 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -953,6 +953,16 @@ config BFIN_GPTIMERS To compile this driver as a module, choose M here: the module will be called gptimers. +config HAVE_PWM + tristate "Enable PWM API support" + depends on BFIN_GPTIMERS + help + Enable support for the Pulse Width Modulation framework (as + found in linux/pwm.h). + + To compile this driver as a module, choose M here: the module + will be called pwm. + choice prompt "Uncached DMA region" default DMA_UNCACHED_1M diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 1c0a82a10591..d7ff2aee3fbc 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -58,13 +58,13 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=m +CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=m -CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_RAM=y CONFIG_MTD_ROM=m -CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index 31d954216c05..9f1d08401fca 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig @@ -112,7 +112,7 @@ CONFIG_USB_G_SERIAL=m CONFIG_USB_G_PRINTER=m CONFIG_MMC=m CONFIG_SDH_BFIN=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_BFIN=m CONFIG_EXT2_FS=m # CONFIG_DNOTIFY is not set diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h index 38657dac1235..38bddcb190c8 100644 --- a/arch/blackfin/include/asm/gptimers.h +++ b/arch/blackfin/include/asm/gptimers.h @@ -193,6 +193,16 @@ uint16_t get_enabled_gptimers(void); uint32_t get_gptimer_status(unsigned int group); void set_gptimer_status(unsigned int group, uint32_t value); +static inline void enable_gptimer(unsigned int timer_id) +{ + enable_gptimers(1 << timer_id); +} + +static inline void disable_gptimer(unsigned int timer_id) +{ + disable_gptimers(1 << timer_id); +} + /* * All Blackfin system MMRs are padded to 32bits even if the register * itself is only 16bits. So use a helper macro to streamline this. @@ -209,6 +219,15 @@ struct bfin_gptimer_regs { u32 width; }; +/* + * bfin group timer registers layout + */ +struct bfin_gptimer_group_regs { + __BFP(enable); + __BFP(disable); + u32 status; +}; + #undef __BFP #endif diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h index f726e3a80ad0..ff6101aa2c71 100644 --- a/arch/blackfin/include/asm/mutex.h +++ b/arch/blackfin/include/asm/mutex.h @@ -1,76 +1 @@ -/* - * Pull in the generic implementation for the mutex fastpath. - * - * TODO: implement optimized primitives instead, or leave the generic - * implementation in place, or pick the atomic_xchg() based generic - * implementation. (see asm-generic/mutex-xchg.h for details) - * - * Copyright 2006-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _ASM_MUTEX_H -#define _ASM_MUTEX_H - -#ifndef CONFIG_SMP -#include <asm-generic/mutex.h> -#else - -static inline void -__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) -{ - if (unlikely(atomic_dec_return(count) < 0)) - fail_fn(count); - else - smp_mb(); -} - -static inline int -__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) -{ - if (unlikely(atomic_dec_return(count) < 0)) - return fail_fn(count); - else { - smp_mb(); - return 0; - } -} - -static inline void -__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) -{ - smp_mb(); - if (unlikely(atomic_inc_return(count) <= 0)) - fail_fn(count); -} - -#define __mutex_slowpath_needs_to_unlock() 1 - -static inline int -__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) -{ - /* - * We have two variants here. The cmpxchg based one is the best one - * because it never induce a false contention state. It is included - * here because architectures using the inc/dec algorithms over the - * xchg ones are much more likely to support cmpxchg natively. - * - * If not we fall back to the spinlock based variant - that is - * just as efficient (and simpler) as a 'destructive' probing of - * the mutex state would be. - */ -#ifdef __HAVE_ARCH_CMPXCHG - if (likely(atomic_cmpxchg(count, 1, 0) == 1)) { - smp_mb(); - return 1; - } - return 0; -#else - return fail_fn(count); -#endif -} - -#endif - -#endif +#include <asm-generic/mutex-dec.h> diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h index d49bb261d9b7..28c2498c9c98 100644 --- a/arch/blackfin/include/asm/pda.h +++ b/arch/blackfin/include/asm/pda.h @@ -54,6 +54,16 @@ struct blackfin_pda { /* Per-processor Data Area */ #endif }; +struct blackfin_initial_pda { + void *retx; +#ifdef CONFIG_DEBUG_DOUBLEFAULT + void *dcplb_doublefault_addr; + void *icplb_doublefault_addr; + void *retx_doublefault; + unsigned seqstat_doublefault; +#endif +}; + extern struct blackfin_pda cpu_pda[]; #endif /* __ASSEMBLY__ */ diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index d550b24d9e9b..b7bdc42fe1a3 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o CFLAGS_REMOVE_ftrace.o = -pg +obj-$(CONFIG_HAVE_PWM) += pwm.o obj-$(CONFIG_IPIPE) += ipipe.o obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o obj-$(CONFIG_CPLB_INFO) += cplbinfo.o diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c index bd32c09b9349..17e35465a416 100644 --- a/arch/blackfin/kernel/asm-offsets.c +++ b/arch/blackfin/kernel/asm-offsets.c @@ -138,6 +138,16 @@ int main(void) DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault)); DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault)); #endif + + /* PDA initial management */ + DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx)); +#ifdef CONFIG_DEBUG_DOUBLEFAULT + DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr)); + DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr)); + DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault)); + DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault)); +#endif + #ifdef CONFIG_SMP /* Inter-core lock (in L2 SRAM) */ DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot)); diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c index fce4807ceef9..8e3b88b7500d 100644 --- a/arch/blackfin/kernel/debug-mmrs.c +++ b/arch/blackfin/kernel/debug-mmrs.c @@ -27,7 +27,7 @@ #define PORT_MUX BFIN_PORT_MUX #endif -#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr) +#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr)) #define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR) #define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR) #define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR) @@ -277,6 +277,32 @@ bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num) } #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num) +#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr) +#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname) +static void __init __maybe_unused +bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num) +{ + char buf[32], *_buf; + + if (num == -1) { + _buf = buf + sprintf(buf, "TIMER_"); + __GPTIMER_GROUP(ENABLE, enable); + __GPTIMER_GROUP(DISABLE, disable); + __GPTIMER_GROUP(STATUS, status); + } else { + /* These MMRs are a bit odd as the group # is a suffix */ + _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num); + d(buf, 16, base + GPTIMER_GROUP_OFF(enable)); + + _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num); + d(buf, 16, base + GPTIMER_GROUP_OFF(disable)); + + _buf = buf + sprintf(buf, "TIMER_STATUS%i", num); + d(buf, 32, base + GPTIMER_GROUP_OFF(status)); + } +} +#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num) + /* * Handshake MDMA */ @@ -747,7 +773,7 @@ static int __init bfin_debug_mmrs_init(void) #endif parent = debugfs_create_dir("dmac", top); -#ifdef DMA_TC_CNT +#ifdef DMAC_TC_CNT D16(DMAC_TC_CNT); D16(DMAC_TC_PER); #endif @@ -1005,29 +1031,19 @@ static int __init bfin_debug_mmrs_init(void) #endif parent = debugfs_create_dir("gptimer", top); -#ifdef TIMER_DISABLE - D16(TIMER_DISABLE); - D16(TIMER_ENABLE); - D32(TIMER_STATUS); +#ifdef TIMER_ENABLE + GPTIMER_GROUP(TIMER_ENABLE, -1); #endif -#ifdef TIMER_DISABLE0 - D16(TIMER_DISABLE0); - D16(TIMER_ENABLE0); - D32(TIMER_STATUS0); +#ifdef TIMER_ENABLE0 + GPTIMER_GROUP(TIMER_ENABLE0, 0); #endif -#ifdef TIMER_DISABLE1 - D16(TIMER_DISABLE1); - D16(TIMER_ENABLE1); - D32(TIMER_STATUS1); +#ifdef TIMER_ENABLE1 + GPTIMER_GROUP(TIMER_ENABLE1, 1); #endif /* XXX: Should convert BF561 MMR names */ #ifdef TMRS4_DISABLE - D16(TMRS4_DISABLE); - D16(TMRS4_ENABLE); - D32(TMRS4_STATUS); - D16(TMRS8_DISABLE); - D16(TMRS8_ENABLE); - D32(TMRS8_STATUS); + GPTIMER_GROUP(TMRS4_ENABLE, 0); + GPTIMER_GROUP(TMRS8_ENABLE, 1); #endif GPTIMER(0); GPTIMER(1); diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c index 8b81dc04488a..06459f4bf43a 100644 --- a/arch/blackfin/kernel/gptimers.c +++ b/arch/blackfin/kernel/gptimers.c @@ -25,49 +25,33 @@ #define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1) -typedef struct { - uint16_t config; - uint16_t __pad; - uint32_t counter; - uint32_t period; - uint32_t width; -} GPTIMER_timer_regs; - -typedef struct { - uint16_t enable; - uint16_t __pad0; - uint16_t disable; - uint16_t __pad1; - uint32_t status; -} GPTIMER_group_regs; - -static volatile GPTIMER_timer_regs *const timer_regs[MAX_BLACKFIN_GPTIMERS] = +static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] = { - (GPTIMER_timer_regs *)TIMER0_CONFIG, - (GPTIMER_timer_regs *)TIMER1_CONFIG, - (GPTIMER_timer_regs *)TIMER2_CONFIG, + (void *)TIMER0_CONFIG, + (void *)TIMER1_CONFIG, + (void *)TIMER2_CONFIG, #if (MAX_BLACKFIN_GPTIMERS > 3) - (GPTIMER_timer_regs *)TIMER3_CONFIG, - (GPTIMER_timer_regs *)TIMER4_CONFIG, - (GPTIMER_timer_regs *)TIMER5_CONFIG, - (GPTIMER_timer_regs *)TIMER6_CONFIG, - (GPTIMER_timer_regs *)TIMER7_CONFIG, + (void *)TIMER3_CONFIG, + (void *)TIMER4_CONFIG, + (void *)TIMER5_CONFIG, + (void *)TIMER6_CONFIG, + (void *)TIMER7_CONFIG, # if (MAX_BLACKFIN_GPTIMERS > 8) - (GPTIMER_timer_regs *)TIMER8_CONFIG, - (GPTIMER_timer_regs *)TIMER9_CONFIG, - (GPTIMER_timer_regs *)TIMER10_CONFIG, + (void *)TIMER8_CONFIG, + (void *)TIMER9_CONFIG, + (void *)TIMER10_CONFIG, # if (MAX_BLACKFIN_GPTIMERS > 11) - (GPTIMER_timer_regs *)TIMER11_CONFIG, + (void *)TIMER11_CONFIG, # endif # endif #endif }; -static volatile GPTIMER_group_regs *const group_regs[BFIN_TIMER_NUM_GROUP] = +static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] = { - (GPTIMER_group_regs *)TIMER0_GROUP_REG, + (void *)TIMER0_GROUP_REG, #if (MAX_BLACKFIN_GPTIMERS > 8) - (GPTIMER_group_regs *)TIMER8_GROUP_REG, + (void *)TIMER8_GROUP_REG, #endif }; @@ -140,7 +124,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] = void set_gptimer_pwidth(unsigned int timer_id, uint32_t value) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - timer_regs[timer_id]->width = value; + bfin_write(&timer_regs[timer_id]->width, value); SSYNC(); } EXPORT_SYMBOL(set_gptimer_pwidth); @@ -148,14 +132,14 @@ EXPORT_SYMBOL(set_gptimer_pwidth); uint32_t get_gptimer_pwidth(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return timer_regs[timer_id]->width; + return bfin_read(&timer_regs[timer_id]->width); } EXPORT_SYMBOL(get_gptimer_pwidth); void set_gptimer_period(unsigned int timer_id, uint32_t period) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - timer_regs[timer_id]->period = period; + bfin_write(&timer_regs[timer_id]->period, period); SSYNC(); } EXPORT_SYMBOL(set_gptimer_period); @@ -163,71 +147,76 @@ EXPORT_SYMBOL(set_gptimer_period); uint32_t get_gptimer_period(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return timer_regs[timer_id]->period; + return bfin_read(&timer_regs[timer_id]->period); } EXPORT_SYMBOL(get_gptimer_period); uint32_t get_gptimer_count(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return timer_regs[timer_id]->counter; + return bfin_read(&timer_regs[timer_id]->counter); } EXPORT_SYMBOL(get_gptimer_count); uint32_t get_gptimer_status(unsigned int group) { tassert(group < BFIN_TIMER_NUM_GROUP); - return group_regs[group]->status; + return bfin_read(&group_regs[group]->status); } EXPORT_SYMBOL(get_gptimer_status); void set_gptimer_status(unsigned int group, uint32_t value) { tassert(group < BFIN_TIMER_NUM_GROUP); - group_regs[group]->status = value; + bfin_write(&group_regs[group]->status, value); SSYNC(); } EXPORT_SYMBOL(set_gptimer_status); +static uint32_t read_gptimer_status(unsigned int timer_id) +{ + return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status); +} + int get_gptimer_intr(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]); + return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_intr); void clear_gptimer_intr(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id]; + bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]); } EXPORT_SYMBOL(clear_gptimer_intr); int get_gptimer_over(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]); + return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_over); void clear_gptimer_over(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id]; + bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]); } EXPORT_SYMBOL(clear_gptimer_over); int get_gptimer_run(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]); + return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_run); void set_gptimer_config(unsigned int timer_id, uint16_t config) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - timer_regs[timer_id]->config = config; + bfin_write(&timer_regs[timer_id]->config, config); SSYNC(); } EXPORT_SYMBOL(set_gptimer_config); @@ -235,7 +224,7 @@ EXPORT_SYMBOL(set_gptimer_config); uint16_t get_gptimer_config(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - return timer_regs[timer_id]->config; + return bfin_read(&timer_regs[timer_id]->config); } EXPORT_SYMBOL(get_gptimer_config); @@ -244,7 +233,7 @@ void enable_gptimers(uint16_t mask) int i; tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0); for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) { - group_regs[i]->enable = mask & 0xFF; + bfin_write(&group_regs[i]->enable, mask & 0xFF); mask >>= 8; } SSYNC(); @@ -257,7 +246,7 @@ static void _disable_gptimers(uint16_t mask) uint16_t m = mask; tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0); for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) { - group_regs[i]->disable = m & 0xFF; + bfin_write(&group_regs[i]->disable, m & 0xFF); m >>= 8; } } @@ -268,7 +257,7 @@ void disable_gptimers(uint16_t mask) _disable_gptimers(mask); for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i) if (mask & (1 << i)) - group_regs[BFIN_TIMER_OCTET(i)]->status = trun_mask[i]; + bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]); SSYNC(); } EXPORT_SYMBOL(disable_gptimers); @@ -283,7 +272,7 @@ EXPORT_SYMBOL(disable_gptimers_sync); void set_gptimer_pulse_hi(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - timer_regs[timer_id]->config |= TIMER_PULSE_HI; + bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI); SSYNC(); } EXPORT_SYMBOL(set_gptimer_pulse_hi); @@ -291,7 +280,7 @@ EXPORT_SYMBOL(set_gptimer_pulse_hi); void clear_gptimer_pulse_hi(unsigned int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); - timer_regs[timer_id]->config &= ~TIMER_PULSE_HI; + bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI); SSYNC(); } EXPORT_SYMBOL(clear_gptimer_pulse_hi); @@ -301,7 +290,7 @@ uint16_t get_enabled_gptimers(void) int i; uint16_t result = 0; for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) - result |= (group_regs[i]->enable << (i << 3)); + result |= (bfin_read(&group_regs[i]->enable) << (i << 3)); return result; } EXPORT_SYMBOL(get_enabled_gptimers); diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 6a660fa921b5..6a80a9e9fc4a 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -140,7 +140,6 @@ EXPORT_SYMBOL(kernel_thread); */ void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) { - set_fs(USER_DS); regs->pc = new_ip; if (current->mm) regs->p5 = current->mm->start_data; diff --git a/arch/blackfin/kernel/pwm.c b/arch/blackfin/kernel/pwm.c new file mode 100644 index 000000000000..33f5942733bd --- /dev/null +++ b/arch/blackfin/kernel/pwm.c @@ -0,0 +1,100 @@ +/* + * Blackfin Pulse Width Modulation (PWM) core + * + * Copyright (c) 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/module.h> +#include <linux/pwm.h> +#include <linux/slab.h> + +#include <asm/gptimers.h> +#include <asm/portmux.h> + +struct pwm_device { + unsigned id; + unsigned short pin; +}; + +static const unsigned short pwm_to_gptimer_per[] = { + P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5, + P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11, +}; + +struct pwm_device *pwm_request(int pwm_id, const char *label) +{ + struct pwm_device *pwm; + int ret; + + /* XXX: pwm_id really should be unsigned */ + if (pwm_id < 0) + return NULL; + + pwm = kzalloc(sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return pwm; + + pwm->id = pwm_id; + if (pwm->id >= ARRAY_SIZE(pwm_to_gptimer_per)) + goto err; + + pwm->pin = pwm_to_gptimer_per[pwm->id]; + ret = peripheral_request(pwm->pin, label); + if (ret) + goto err; + + return pwm; + err: + kfree(pwm); + return NULL; +} +EXPORT_SYMBOL(pwm_request); + +void pwm_free(struct pwm_device *pwm) +{ + peripheral_free(pwm->pin); + kfree(pwm); +} +EXPORT_SYMBOL(pwm_free); + +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) +{ + unsigned long period, duty; + unsigned long long val; + + if (duty_ns < 0 || duty_ns > period_ns) + return -EINVAL; + + val = (unsigned long long)get_sclk() * period_ns; + do_div(val, NSEC_PER_SEC); + period = val; + + val = (unsigned long long)period * duty_ns; + do_div(val, period_ns); + duty = period - val; + + if (duty >= period) + duty = period - 1; + + set_gptimer_config(pwm->id, TIMER_MODE_PWM | TIMER_PERIOD_CNT); + set_gptimer_pwidth(pwm->id, duty); + set_gptimer_period(pwm->id, period); + + return 0; +} +EXPORT_SYMBOL(pwm_config); + +int pwm_enable(struct pwm_device *pwm) +{ + enable_gptimer(pwm->id); + return 0; +} +EXPORT_SYMBOL(pwm_enable); + +void pwm_disable(struct pwm_device *pwm) +{ + disable_gptimer(pwm->id); +} +EXPORT_SYMBOL(pwm_disable); diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 536bd9d7e0cf..dfa2525a442d 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c @@ -54,8 +54,7 @@ EXPORT_SYMBOL(mtd_size); #endif char __initdata command_line[COMMAND_LINE_SIZE]; -void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat, - *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr; +struct blackfin_initial_pda __initdata initial_pda; /* boot memmap, for parsing "memmap=" */ #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */ @@ -957,13 +956,16 @@ void __init setup_arch(char **cmdline_p) printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); #ifdef CONFIG_DEBUG_DOUBLEFAULT /* We assume the crashing kernel, and the current symbol table match */ - printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", - (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx); - printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr); - printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr); + printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n", + initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE, + initial_pda.retx_doublefault); + printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", + initial_pda.dcplb_doublefault_addr); + printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", + initial_pda.icplb_doublefault_addr); #endif printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", - init_retx); + initial_pda.retx); } else if (_bfin_swrst & RESET_WDOG) printk(KERN_INFO "Recovering from Watchdog event\n"); else if (_bfin_swrst & RESET_SOFTWARE) diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index 8d73724c0092..ceb2bf63dfe2 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c @@ -51,7 +51,7 @@ void __init setup_core_timer(void) u32 tcount; /* power up the timer, but don't enable it just yet */ - bfin_write_TCNTL(1); + bfin_write_TCNTL(TMPWR); CSYNC(); /* the TSCALE prescaler counter */ @@ -64,7 +64,7 @@ void __init setup_core_timer(void) /* now enable the timer */ CSYNC(); - bfin_write_TCNTL(7); + bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR); } #endif diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 3ac5b66d14aa..ba35864b2b74 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -155,6 +155,7 @@ SECTIONS SECURITY_INITCALL INIT_RAM_FS + . = ALIGN(PAGE_SIZE); ___per_cpu_load = .; PERCPU_INPUT(32) diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index c0ccadcfa44e..235703788e86 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c @@ -187,43 +187,16 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) -#if defined(CONFIG_NET_DSA_KSZ8893M) \ - || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) -/* SPI SWITCH CHIP */ -static struct bfin5xx_spi_chip spi_switch_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif -#endif - #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -247,13 +220,6 @@ static struct bfin5xx_spi_chip spi_wm8731_chip_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -269,18 +235,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) #if defined(CONFIG_NET_DSA_KSZ8893M) \ || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) @@ -290,7 +244,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .bus_num = 0, .chip_select = 1, .platform_data = NULL, - .controller_data = &spi_switch_info, .mode = SPI_MODE_3, }, #endif @@ -314,7 +267,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &spi_ad7877_chip_info, }, #endif #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ @@ -334,7 +286,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) @@ -343,7 +294,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c index 50fc5c89e379..4ae95e235b51 100644 --- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c +++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c @@ -138,32 +138,16 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -187,13 +171,6 @@ static struct bfin5xx_spi_chip spi_wm8731_chip_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -209,18 +186,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) { .modalias = "mmc_spi", @@ -239,7 +204,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &spi_ad7877_chip_info, }, #endif #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ @@ -259,7 +223,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) @@ -268,7 +231,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index d2f076fbbc9e..56383f7cbc07 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h @@ -11,10 +11,9 @@ */ /* This file should be up to date with: - * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List */ -/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ #if __SILICON_REVISION__ < 0 # error will not work on BF518 silicon version #endif @@ -77,19 +76,29 @@ /* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* PLL Latches Incorrect Settings During Reset */ -#define ANOMALY_05000469 (1) +#define ANOMALY_05000462 (__SILICON_REVISION__ < 2) /* Incorrect Default MSEL Value in PLL_CTL */ -#define ANOMALY_05000472 (1) +#define ANOMALY_05000472 (__SILICON_REVISION__ < 2) /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL Latches Incorrect Settings During Reset */ +#define ANOMALY_05000482 (__SILICON_REVISION__ < 2) +/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ +#define ANOMALY_05000485 (__SILICON_REVISION__ < 2) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -157,6 +166,5 @@ #define ANOMALY_05000474 (0) #define ANOMALY_05000475 (0) #define ANOMALY_05000480 (0) -#define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c index ccab4c689dc3..d5b6ca239516 100644 --- a/arch/blackfin/mach-bf527/boards/ad7160eval.c +++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c @@ -265,7 +265,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif @@ -280,14 +279,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -347,7 +338,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif }; diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index c9d6dc88f0e6..c64515efba49 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -354,16 +354,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -378,16 +368,10 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -411,13 +395,6 @@ static struct bfin5xx_spi_chip spi_wm8731_chip_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -433,18 +410,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { @@ -473,7 +438,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &spi_ad7877_chip_info, }, #endif #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ @@ -493,7 +457,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif }; diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index b7101aa6e3aa..15806e9eac13 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -253,32 +253,16 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (sst25wf040) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -311,13 +295,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) -static struct bfin5xx_spi_chip spi_ad7879_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ && defined(CONFIG_SND_SOC_WM8731_SPI) static struct bfin5xx_spi_chip spi_wm8731_chip_info = { @@ -326,20 +303,6 @@ static struct bfin5xx_spi_chip spi_wm8731_chip_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) -static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -355,18 +318,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) { .modalias = "mmc_spi", @@ -385,7 +336,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &spi_ad7877_chip_info, }, #endif #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) @@ -396,7 +346,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 5, - .controller_data = &spi_ad7879_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -417,7 +366,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) @@ -426,7 +374,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index e67ac7720668..7de13ac6fe4e 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -409,6 +409,9 @@ static struct resource net2272_bfin_resources[] = { .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, }, { + .start = 1, + .flags = IORESOURCE_BUS, + }, { .start = IRQ_PF7, .end = IRQ_PF7, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -448,16 +451,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -472,16 +465,10 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -513,20 +500,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) -static struct bfin5xx_spi_chip spi_ad7879_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) @@ -605,13 +578,6 @@ static struct platform_device bfin_tdm = { }; #endif -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) -static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -627,18 +593,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { @@ -670,7 +624,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &spi_ad7877_chip_info, }, #endif #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) @@ -681,7 +634,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 3, - .controller_data = &spi_ad7879_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -691,7 +643,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) @@ -700,7 +651,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 7, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c index 18d303dd5627..ec4bc7429c9f 100644 --- a/arch/blackfin/mach-bf527/boards/tll6527m.c +++ b/arch/blackfin/mach-bf527/boards/tll6527m.c @@ -314,29 +314,12 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -/* - * tll6527m V1.0 does not support native spi slave selects - * hence DMA mode will not be useful since the ADC needs - * CS to toggle for each sample and cs_change_per_word - * seems to be removed from spi_bfin5xx.c - */ - .bits_per_word = 16, }; #endif #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -359,21 +342,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \ - || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) -static struct bfin5xx_spi_chip spi_ad7879_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) static struct platform_device bfin_i2s = { .name = "bfin-i2s", @@ -382,24 +350,7 @@ static struct platform_device bfin_i2s = { }; #endif -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) -static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - #if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE) -static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; - -static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; - #include <linux/spi/mcp23s08.h> static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = { .chip[0].is_present = true, @@ -429,22 +380,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) - || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", - /* Name of spi_driver for this device */ - .max_speed_hz = 10000000, - /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS, - /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - .mode = SPI_MODE_0, - }, -#endif - #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) { .modalias = "mmc_spi", @@ -470,7 +405,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS, - .controller_data = &spi_ad7879_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -482,7 +416,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .bus_num = 0, .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS, .mode = SPI_CPHA | SPI_CPOL, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) @@ -491,7 +424,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, .bus_num = 0, .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -502,7 +434,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS, - .controller_data = &spi_mcp23s08_sys_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, { @@ -511,7 +442,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS, - .controller_data = &spi_mcp23s08_usr_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index e66a7e89cd3c..688470611e15 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h @@ -11,8 +11,8 @@ */ /* This file should be up to date with: - * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List + * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -57,7 +57,7 @@ /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) /* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000330 (_ANOMALY_BF527(< 2)) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ @@ -135,7 +135,7 @@ /* Incorrect Default Internal Voltage Regulator Setting */ #define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) +#define ANOMALY_05000411 (_ANOMALY_BF526(< 1)) /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) /* DEB2_URGENT Bit Not Functional */ @@ -181,11 +181,11 @@ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* The WURESET Bit in the SYSCR Register is not Functional */ -#define ANOMALY_05000445 (1) -/* USB DMA Mode 1 Short Packet Data Corruption */ +#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0)) +/* USB DMA Short Packet Data Corruption */ #define ANOMALY_05000450 (1) /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ -#define ANOMALY_05000451 (1) +#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0)) /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ @@ -198,19 +198,19 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* USB Rx DMA hang */ +/* USB Rx DMA Hang */ #define ANOMALY_05000465 (1) /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ #define ANOMALY_05000466 (1) -/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ #define ANOMALY_05000467 (1) /* PLL Latches Incorrect Settings During Reset */ #define ANOMALY_05000469 (1) /* Incorrect Default MSEL Value in PLL_CTL */ #define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) @@ -219,11 +219,19 @@ /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ #define ANOMALY_05000483 (1) /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) +#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0)) /* The CODEC Zero-Cross Detect Feature is not Functional */ #define ANOMALY_05000487 (1) -/* IFLUSH sucks at life */ +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index d4bfcea56828..8000af0b8a03 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c @@ -159,15 +159,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -195,17 +186,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */ - .bus_num = 1, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { .modalias = "ad183x", diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c index 87b5af3693c1..b0ec825fb4ec 100644 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ b/arch/blackfin/mach-bf533/boards/blackstamp.c @@ -102,21 +102,12 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -151,7 +142,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 7, - .controller_data = &spidev_chip_info, }, #endif }; diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index 4d5604eaa7c2..022b53174532 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c @@ -59,15 +59,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -/* SPI ADC chip */ -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -81,7 +72,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -99,17 +89,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { .modalias = "ad183x", diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index b67b91d82242..be29314a6061 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -210,15 +210,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -229,13 +220,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) { @@ -250,17 +234,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { .modalias = "ad183x", @@ -276,7 +249,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif }; diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c index a377d8afea03..fbee77fa9211 100644 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/arch/blackfin/mach-bf533/boards/ip0x.c @@ -110,7 +110,6 @@ static struct platform_device dm9000_device2 = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, /* if 1 - block!!! */ - .bits_per_word = 8, }; #endif diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 43224ef00b8c..7170b004788e 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -80,6 +80,9 @@ static struct resource net2272_bfin_resources[] = { .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, }, { + .start = 1, + .flags = IORESOURCE_BUS, + }, { .start = IRQ_PF10, .end = IRQ_PF10, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -172,15 +175,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -191,13 +185,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) #define MMC_SPI_CARD_DETECT_INT IRQ_PF5 static int bfin_mmc_spi_init(struct device *dev, @@ -221,7 +208,6 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, .pio_interrupt = 0, }; #endif @@ -240,17 +226,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { .modalias = "ad183x", @@ -269,7 +244,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) @@ -659,6 +633,41 @@ static struct platform_device *stamp_devices[] __initdata = { #endif }; +static int __init net2272_init(void) +{ +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) + int ret; + + /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */ + ret = gpio_request(GPIO_PF0, "net2272"); + if (ret) + return ret; + + ret = gpio_request(GPIO_PF1, "net2272"); + if (ret) { + gpio_free(GPIO_PF0); + return ret; + } + + ret = gpio_request(GPIO_PF11, "net2272"); + if (ret) { + gpio_free(GPIO_PF0); + gpio_free(GPIO_PF1); + return ret; + } + + gpio_direction_output(GPIO_PF0, 0); + gpio_direction_output(GPIO_PF1, 1); + + /* Reset the USB chip */ + gpio_direction_output(GPIO_PF11, 0); + mdelay(2); + gpio_set_value(GPIO_PF11, 1); +#endif + + return 0; +} + static int __init stamp_init(void) { int ret; @@ -685,6 +694,9 @@ static int __init stamp_init(void) } #endif + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); return 0; } diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 72aa59440f82..03f2b40912a3 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h @@ -11,7 +11,7 @@ */ /* This file should be up to date with: - * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -152,7 +152,7 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) @@ -210,18 +210,25 @@ #define ANOMALY_05000462 (1) /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ #define ANOMALY_05000471 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) -/* These anomalies have been "phased" out of analog.com anomaly sheets and are +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. */ diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c index d582b810e7a7..a6a1c9e990c2 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c @@ -61,15 +61,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -83,7 +74,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -101,17 +91,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { .modalias = "ad183x", @@ -766,6 +745,24 @@ static struct platform_device *cm_bf537e_devices[] __initdata = { #endif }; +static int __init net2272_init(void) +{ +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) + int ret; + + ret = gpio_request(GPIO_30, "net2272"); + if (ret) + return ret; + + /* Reset USB Chip, PG14 */ + gpio_direction_output(GPIO_30, 0); + mdelay(2); + gpio_set_value(GPIO_30, 1); +#endif + + return 0; +} + static int __init cm_bf537e_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); @@ -777,6 +774,10 @@ static int __init cm_bf537e_init(void) #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif + + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + return 0; } diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index cbb8098604c5..8897ff1a2793 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c @@ -62,15 +62,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -84,7 +75,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -102,17 +92,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { .modalias = "ad183x", @@ -731,6 +710,36 @@ static struct platform_device *cm_bf537u_devices[] __initdata = { #endif }; +static int __init net2272_init(void) +{ +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) + int ret; + + ret = gpio_request(GPIO_47, driver_name); + if (ret) + return ret; + + ret = gpio_request(GPIO_45, "net2272"); + if (ret) { + gpio_free(GPIO_47); + return ret; + } + + /* Set PH15 Low make /AMS2 work properly */ + gpio_direction_output(GPIO_47, 0); + + /* enable CLKBUF output */ + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); + + /* Reset the USB chip */ + gpio_direction_output(GPIO_45, 0); + mdelay(2); + gpio_set_value(GPIO_45, 1); +#endif + + return 0; +} + static int __init cm_bf537u_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); @@ -742,6 +751,10 @@ static int __init cm_bf537u_init(void) #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif + + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + return 0; } diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c index 6b4ff4605bff..8bc951de979d 100644 --- a/arch/blackfin/mach-bf537/boards/dnp5370.c +++ b/arch/blackfin/mach-bf537/boards/dnp5370.c @@ -130,7 +130,6 @@ static struct platform_device asmb_flash_device = { static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, /* use no dma transfer with this chip*/ - .bits_per_word = 8, }; #endif @@ -161,7 +160,6 @@ static struct flash_platform_data bfin_spi_dataflash_data = { static struct bfin5xx_spi_chip spi_dataflash_chip_info = { .enable_dma = 0, /* use no dma transfer with this chip*/ - .bits_per_word = 8, }; #endif diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index bfb3671a78da..c62f9dccd9f7 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c @@ -159,14 +159,12 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 9389f03e3b0a..17d0bbde91c2 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -184,16 +184,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -208,16 +198,10 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -248,18 +232,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { @@ -288,7 +260,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 5, - .controller_data = &spi_ad7877_chip_info, }, #endif diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 76db1d483173..c80bc6758a40 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -367,6 +367,9 @@ static struct resource net2272_bfin_resources[] = { .end = 0x20300000 + 0x100, .flags = IORESOURCE_MEM, }, { + .start = 1, + .flags = IORESOURCE_BUS, + }, { .start = IRQ_PF7, .end = IRQ_PF7, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, @@ -533,16 +536,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -554,28 +547,8 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { }; #endif -#if defined(CONFIG_SND_BF5XX_SOC_AD193X) \ - || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE) -static struct bfin5xx_spi_chip ad1938_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \ - || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE) -static struct bfin5xx_spi_chip adav801_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - #if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) #include <linux/input/ad714x.h> -static struct bfin5xx_spi_chip ad7147_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; static struct ad714x_slider_plat ad7147_spi_slider_plat[] = { { @@ -714,7 +687,6 @@ static unsigned short ad2s1210_platform_data[] = { static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -735,7 +707,6 @@ static unsigned short ad7816_platform_data[] = { static struct bfin5xx_spi_chip ad7816_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -749,7 +720,6 @@ static unsigned long adt7310_platform_data[3] = { static struct bfin5xx_spi_chip adt7310_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -758,11 +728,6 @@ static unsigned short ad7298_platform_data[] = { GPIO_PF7, /* busy_pin */ 0, }; - -static struct bfin5xx_spi_chip ad7298_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; #endif #if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE) @@ -773,7 +738,6 @@ static unsigned long adt7316_spi_data[2] = { static struct bfin5xx_spi_chip adt7316_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -800,18 +764,12 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, .pio_interrupt = 0, }; #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) #include <linux/spi/ad7877.h> -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -883,31 +841,9 @@ static const struct adxl34x_platform_data adxl34x_info = { }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) -static struct bfin5xx_spi_chip spi_ad7879_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) -static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { .enable_dma = 1, - .bits_per_word = 8, }; #endif @@ -959,10 +895,6 @@ static inline void adf702x_mac_init(void) {} #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) #include <linux/spi/ads7846.h> -static struct bfin5xx_spi_chip ad7873_spi_chip_info = { - .bits_per_word = 8, -}; - static int ads7873_get_pendown_state(void) { return gpio_get_value(GPIO_PF6); @@ -1009,21 +941,12 @@ static struct flash_platform_data bfin_spi_dataflash_data = { /* DataFlash chip */ static struct bfin5xx_spi_chip data_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) -static struct bfin5xx_spi_chip spi_adxl34x_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif #if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE) static struct bfin5xx_spi_chip spi_ad7476_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif @@ -1053,17 +976,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) \ - || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) @@ -1084,7 +996,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 5, - .controller_data = &ad1938_spi_chip_info, .mode = SPI_MODE_3, }, #endif @@ -1095,7 +1006,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &adav801_spi_chip_info, .mode = SPI_MODE_3, }, #endif @@ -1109,7 +1019,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .chip_select = 5, .mode = SPI_MODE_3, .platform_data = &ad7147_spi_platform_data, - .controller_data = &ad7147_spi_chip_info, }, #endif @@ -1188,7 +1097,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .bus_num = 0, .chip_select = 4, /* CS, change it for your board */ .platform_data = ad7298_platform_data, - .controller_data = &ad7298_spi_chip_info, .mode = SPI_MODE_3, }, #endif @@ -1225,7 +1133,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spi_ad7877_chip_info, }, #endif #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) @@ -1236,7 +1143,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spi_ad7879_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -1246,7 +1152,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) @@ -1255,7 +1160,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -1278,7 +1182,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &spi_adxl34x_chip_info, .mode = SPI_MODE_3, }, #endif @@ -1300,7 +1203,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .bus_num = 0, .irq = IRQ_PF6, .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ - .controller_data = &ad7873_spi_chip_info, .platform_data = &ad7873_pdata, .mode = SPI_MODE_0, }, @@ -2916,6 +2818,24 @@ static struct platform_device *stamp_devices[] __initdata = { #endif }; +static int __init net2272_init(void) +{ +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) + int ret; + + ret = gpio_request(GPIO_PF6, "net2272"); + if (ret) + return ret; + + /* Reset the USB chip */ + gpio_direction_output(GPIO_PF6, 0); + mdelay(2); + gpio_set_value(GPIO_PF6, 1); +#endif + + return 0; +} + static int __init stamp_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); @@ -2926,6 +2846,9 @@ static int __init stamp_init(void) ARRAY_SIZE(bfin_i2c_board_info)); spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + return 0; } diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 164a7e02c022..254168592ff0 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c @@ -62,15 +62,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -84,7 +75,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -102,17 +92,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { .modalias = "ad183x", @@ -733,6 +712,24 @@ static struct platform_device *cm_bf537_devices[] __initdata = { #endif }; +static int __init net2272_init(void) +{ +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) + int ret; + + ret = gpio_request(GPIO_30, "net2272"); + if (ret) + return ret; + + /* Reset USB Chip, PG14 */ + gpio_direction_output(GPIO_30, 0); + mdelay(2); + gpio_set_value(GPIO_30, 1); +#endif + + return 0; +} + static int __init tcm_bf537_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); @@ -744,6 +741,10 @@ static int __init tcm_bf537_init(void) #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif + + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + return 0; } diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index 7f8e5a9f5db6..543cd3fb305e 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h @@ -11,7 +11,7 @@ */ /* This file should be up to date with: - * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -44,18 +44,12 @@ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Instruction Cache Is Not Functional */ -#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Buffered CLKIN Output Is Disabled by Default */ -#define ANOMALY_05000247 (1) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) /* EMAC TX DMA Error After an Early Frame Abort */ @@ -98,7 +92,7 @@ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) @@ -162,9 +156,9 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) @@ -172,8 +166,26 @@ #define ANOMALY_05000480 (__SILICON_REVISION__ < 3) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) +/* Instruction Cache Is Not Functional */ +#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) +/* Buffered CLKIN Output Is Disabled by Default */ +#define ANOMALY_05000247 (__SILICON_REVISION__ < 2) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c index e61424ef35eb..629f3c333415 100644 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/arch/blackfin/mach-bf538/boards/ezkit.c @@ -502,7 +502,6 @@ static struct flash_platform_data bfin_spi_flash_data = { static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif @@ -523,13 +522,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { }; #endif -#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) -static struct bfin5xx_spi_chip spi_ad7879_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; -#endif - #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) #include <asm/bfin-lq035q1.h> @@ -559,20 +551,6 @@ static struct platform_device bfin_lq035q1_device = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) -static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bf538_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -595,7 +573,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spi_ad7879_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -605,7 +582,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &lq035q1_spi_chip_info, .mode = SPI_CPHA | SPI_CPOL, }, #endif @@ -615,7 +591,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif }; diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index 55e7d0712a94..b6ca99788710 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h @@ -11,8 +11,8 @@ */ /* This file should be up to date with: - * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List - * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List + * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List + * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -56,25 +56,21 @@ #define ANOMALY_05000229 (1) /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ #define ANOMALY_05000233 (1) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (1) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) +#define ANOMALY_05000272 (ANOMALY_BF538) /* Writes to Synchronous SDRAM Memory May Be Lost */ #define ANOMALY_05000273 (__SILICON_REVISION__ < 4) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) @@ -102,8 +98,10 @@ #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) +/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */ +#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */ /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ -#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) +#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */ /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (__SILICON_REVISION__ < 5) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ @@ -134,16 +132,32 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index d11502ac5623..212b9e0a08c8 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c @@ -861,16 +861,10 @@ static struct flash_platform_data bfin_spi_flash_data = { static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -886,13 +880,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bf54x_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -915,7 +902,6 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &spi_ad7877_chip_info, }, #endif #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) @@ -924,7 +910,6 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif }; diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 311bf9970fe7..cc2eae361b8f 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -1018,7 +1018,6 @@ static struct flash_platform_data bfin_spi_flash_data = { static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, }; #endif @@ -1031,11 +1030,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { #endif #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) -static struct bfin5xx_spi_chip spi_ad7877_chip_info = { - .enable_dma = 0, - .bits_per_word = 16, -}; - static const struct ad7877_platform_data bfin_ad7877_ts_info = { .model = 7877, .vref_delay_usecs = 50, /* internal, no capacitor */ @@ -1051,20 +1045,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) -static struct bfin5xx_spi_chip spi_adxl34x_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -1097,7 +1077,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 2, - .controller_data = &spi_ad7877_chip_info, }, #endif #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) @@ -1106,7 +1085,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) @@ -1117,7 +1095,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 1, .chip_select = 2, - .controller_data = &spi_adxl34x_chip_info, .mode = SPI_MODE_3, }, #endif diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 9e70785bdde3..ac96ee83b00e 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -11,7 +11,7 @@ */ /* This file should be up to date with: - * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -29,117 +29,37 @@ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ -#define ANOMALY_05000220 (1) +#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) -/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) -/* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) /* FIFO Boot Mode Not Functional */ #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) -/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ -#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) -/* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) -/* Synchronous Burst Flash Boot Mode Is Not Functional */ -#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) -/* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) -/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ -#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) -/* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) -/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ -#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) -/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) -/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) -/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ -#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) -/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ -#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) -/* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) -/* USB Calibration Value to use */ -#define ANOMALY_05000346_value 0x5411 -/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) -/* Data Lost when Core Reads SDH Data FIFO */ -#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) -/* PLL Status Register Is Inaccurate */ -#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ /* * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing * shows that the fix itself does not cover all cases. */ #define ANOMALY_05000353 (1) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) -/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ -#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) /* External Memory Read Access Hangs Core With PLL Bypass */ #define ANOMALY_05000360 (1) /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ #define ANOMALY_05000365 (1) -/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ -#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) /* Addressing Conflict between Boot ROM and Asynchronous Memory */ #define ANOMALY_05000369 (1) -/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ -#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) -/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ -#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ #define ANOMALY_05000379 (1) -/* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) -/* Some ATAPI Modes Are Not Functional */ -#define ANOMALY_05000383 (1) -/* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) -/* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) -/* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) -/* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) -/* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) -/* Changed Meaning of BCODE Field in SYSCR Register */ -#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) -/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ -#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) -/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) -/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) -/* Log Buffer Not Functional */ -#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) -/* Hook Routine Not Functional */ -#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) -/* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) -/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) /* Lockbox SESR Disallows Certain User Interrupts */ #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ @@ -161,7 +81,7 @@ /* Speculative Fetches Can Cause Undesired External FIFO Operations */ #define ANOMALY_05000416 (1) /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) +#define ANOMALY_05000425 (__SILICON_REVISION__ < 4) /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ @@ -174,8 +94,6 @@ #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ #define ANOMALY_05000434 (1) -/* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ @@ -186,34 +104,32 @@ #define ANOMALY_05000448 (__SILICON_REVISION__ == 1) /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) -/* USB DMA Mode 1 Short Packet Data Corruption */ +/* USB DMA Short Packet Data Corruption */ #define ANOMALY_05000450 (1) -/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ #define ANOMALY_05000456 (1) /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ #define ANOMALY_05000457 (1) /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ -#define ANOMALY_05000460 (1) +#define ANOMALY_05000460 (__SILICON_REVISION__ < 4) /* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) +#define ANOMALY_05000462 (__SILICON_REVISION__ < 4) /* USB DMA RX Data Corruption */ -#define ANOMALY_05000463 (1) +#define ANOMALY_05000463 (__SILICON_REVISION__ < 4) /* USB TX DMA Hang */ -#define ANOMALY_05000464 (1) -/* USB Rx DMA hang */ +#define ANOMALY_05000464 (__SILICON_REVISION__ < 4) +/* USB Rx DMA Hang */ #define ANOMALY_05000465 (1) /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ -#define ANOMALY_05000466 (1) -/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ -#define ANOMALY_05000467 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000466 (__SILICON_REVISION__ < 4) +/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ +#define ANOMALY_05000467 (__SILICON_REVISION__ < 4) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ -#define ANOMALY_05000474 (1) +/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */ +#define ANOMALY_05000474 (__SILICON_REVISION__ < 4) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ @@ -223,9 +139,111 @@ /* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */ #define ANOMALY_05000484 (__SILICON_REVISION__ < 3) /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) -/* IFLUSH sucks at life */ +#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4) +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */ +#define ANOMALY_05000500 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) +/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */ +#define ANOMALY_05000502 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* False Hardware Error when ISR Context Is Not Restored */ +#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) +/* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) +/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ +#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) +/* Incorrect Access of OTP_STATUS During otp_write() Function */ +#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) +/* Synchronous Burst Flash Boot Mode Is Not Functional */ +#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) +/* Host DMA Boot Modes Are Not Functional */ +#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) +/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ +#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) +/* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) +/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ +#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) +/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ +#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) +/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ +#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) +/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ +#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) +/* USB Calibration Value Is Not Initialized */ +#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) +/* USB Calibration Value to use */ +#define ANOMALY_05000346_value 0x5411 +/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ +#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) +/* Data Lost when Core Reads SDH Data FIFO */ +#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) +/* PLL Status Register Is Inaccurate */ +#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) +/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ +#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) +/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ +#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) +/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ +#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) +/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ +#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) +/* 8-Bit NAND Flash Boot Mode Not Functional */ +#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) +/* Boot from OTP Memory Not Functional */ +#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) +/* bfrom_SysControl() Firmware Routine Not Functional */ +#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) +/* Programmable Preboot Settings Not Functional */ +#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) +/* CRC32 Checksum Support Not Functional */ +#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) +/* Reset Vector Must Not Be in SDRAM Memory Space */ +#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) +/* Changed Meaning of BCODE Field in SYSCR Register */ +#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) +/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ +#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) +/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) +/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) +/* Log Buffer Not Functional */ +#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) +/* Hook Routine Not Functional */ +#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) +/* Header Indirect Bit Not Functional */ +#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) +/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ +#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) +/* OTP Write Accesses Not Supported */ +#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) +/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c index 9231a942892b..972e1347c6bc 100644 --- a/arch/blackfin/mach-bf561/boards/acvilon.c +++ b/arch/blackfin/mach-bf561/boards/acvilon.c @@ -364,14 +364,6 @@ static struct flash_platform_data bfin_spi_dataflash_data = { /* DataFlash chip */ static struct bfin5xx_spi_chip data_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip */ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, }; #endif @@ -420,7 +412,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 3, - .controller_data = &spidev_chip_info, }, #endif #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index 87595cd38afe..e1c136e57dd2 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -60,15 +60,6 @@ static struct flash_platform_data bfin_spi_flash_data = { /* SPI flash chip (m25p64) */ static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) -/* SPI ADC chip */ -static struct bfin5xx_spi_chip spi_adc_chip_info = { - .enable_dma = 1, /* use dma transfer with this chip*/ - .bits_per_word = 16, }; #endif @@ -79,13 +70,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { }; #endif -#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) { @@ -100,17 +84,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) - { - .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ - .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. */ - .platform_data = NULL, /* No spi_driver specific config */ - .controller_data = &spi_adc_chip_info, - }, -#endif - #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { .modalias = "ad183x", @@ -126,7 +99,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &mmc_spi_chip_info, .mode = SPI_MODE_3, }, #endif @@ -532,6 +504,24 @@ static struct platform_device *cm_bf561_devices[] __initdata = { #endif }; +static int __init net2272_init(void) +{ +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) + int ret; + + ret = gpio_request(GPIO_PF46, "net2272"); + if (ret) + return ret; + + /* Reset USB Chip, PF46 */ + gpio_direction_output(GPIO_PF46, 0); + mdelay(2); + gpio_set_value(GPIO_PF46, 1); +#endif + + return 0; +} + static int __init cm_bf561_init(void) { printk(KERN_INFO "%s(): registering device resources\n", __func__); @@ -543,6 +533,10 @@ static int __init cm_bf561_init(void) #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); #endif + + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + return 0; } diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 5067984a62e7..343f32a6c0ed 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -108,6 +108,9 @@ static struct resource net2272_bfin_resources[] = { .end = 0x2C000000 + 0x7F, .flags = IORESOURCE_MEM, }, { + .start = 1, + .flags = IORESOURCE_BUS, + }, { .start = IRQ_PF10, .end = IRQ_PF10, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, @@ -291,13 +294,6 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { }; #endif -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* SPI (0) */ static struct resource bfin_spi0_resource[] = { @@ -355,7 +351,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, .chip_select = 1, - .controller_data = &spidev_chip_info, }, #endif }; @@ -516,6 +511,24 @@ static struct platform_device *ezkit_devices[] __initdata = { #endif }; +static int __init net2272_init(void) +{ +#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) + int ret; + + ret = gpio_request(GPIO_PF11, "net2272"); + if (ret) + return ret; + + /* Reset the USB chip */ + gpio_direction_output(GPIO_PF11, 0); + mdelay(2); + gpio_set_value(GPIO_PF11, 1); +#endif + + return 0; +} + static int __init ezkit_init(void) { int ret; @@ -542,6 +555,9 @@ static int __init ezkit_init(void) udelay(400); #endif + if (net2272_init()) + pr_warning("unable to configure net2272; it probably won't work\n"); + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); return 0; } diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 22b5ab773027..836baeed303a 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -11,7 +11,7 @@ */ /* This file should be up to date with: - * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -26,62 +26,16 @@ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous Exception when Enabling Cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) /* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) -/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ -#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) -/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ -#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) -/* Stall in multi-unit DMA operations */ -#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) /* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) -/* DMA engine may lose data due to incorrect handshaking */ -#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) -/* DMA stalls when all three controllers read data from the same source */ -#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) -/* Execution stall when executing in L2 and doing external accesses */ -#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) -/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ -#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL<12> is not set on Reset */ -#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ @@ -92,10 +46,6 @@ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) -/* DSPID register values incorrect */ -#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) /* Cache Fill Buffer Data lost */ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ @@ -124,8 +74,6 @@ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) /* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ @@ -217,10 +165,10 @@ /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) +#define ANOMALY_05000277 (__SILICON_REVISION__ < 5) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ /* Temporarily walk around for bug 5423 till this issue is confirmed by * official anomaly document. It looks 05000281 still exists on bf561 * v0.5. @@ -274,8 +222,6 @@ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ @@ -298,16 +244,82 @@ #define ANOMALY_05000462 (1) /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ #define ANOMALY_05000471 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ +#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) +/* Erroneous Exception when Enabling Cache */ +#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) +/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ +#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) +/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ +#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) +/* Stall in multi-unit DMA operations */ +#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) +/* Allowing the SPORT RX FIFO to fill will cause an overflow */ +#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ +#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) +/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ +#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) +/* DMA and TESTSET conflict when both are accessing external memory */ +#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) +/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ +#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) +/* MDMA may lose the first few words of a descriptor chain */ +#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) +/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ +#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) +/* DMA engine may lose data due to incorrect handshaking */ +#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) +/* DMA stalls when all three controllers read data from the same source */ +#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) +/* Execution stall when executing in L2 and doing external accesses */ +#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) +/* Frame Delay in SPORT Multichannel Mode */ +#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) +/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ +#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) +/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ +#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) +/* A read from external memory may return a wrong value with data cache enabled */ +#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) +/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ +#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) +/* DMEM_CONTROL<12> is not set on Reset */ +#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ +#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) +/* DSPID register values incorrect */ +#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) +/* DMA vs Core accesses to external memory */ +#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) +/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ +#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000119 (0) diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S index 4c462838f4e1..01e5408620ac 100644 --- a/arch/blackfin/mach-bf561/secondary.S +++ b/arch/blackfin/mach-bf561/secondary.S @@ -23,108 +23,78 @@ #define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) ENTRY(_coreb_trampoline_start) - /* Set the SYSCFG register */ - R0 = 0x36; - SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/ - R0 = 0; - - /*Clear Out All the data and pointer Registers*/ - R1 = R0; - R2 = R0; - R3 = R0; - R4 = R0; - R5 = R0; - R6 = R0; - R7 = R0; - - P0 = R0; - P1 = R0; - P2 = R0; - P3 = R0; - P4 = R0; - P5 = R0; - - LC0 = r0; - LC1 = r0; - L0 = r0; - L1 = r0; - L2 = r0; - L3 = r0; - - /* Clear Out All the DAG Registers*/ - B0 = r0; - B1 = r0; - B2 = r0; - B3 = r0; - - I0 = r0; - I1 = r0; - I2 = r0; - I3 = r0; - - M0 = r0; - M1 = r0; - M2 = r0; - M3 = r0; + /* Enable Cycle Counter and Nesting Of Interrupts */ +#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES + R0 = SYSCFG_SNEN; +#else + R0 = SYSCFG_SNEN | SYSCFG_CCEN; +#endif + SYSCFG = R0; - trace_buffer_init(p0,r0); + /* Optimization register tricks: keep a base value in the + * reserved P registers so we use the load/store with an + * offset syntax. R0 = [P5 + <constant>]; + * P5 - core MMR base + * R6 - 0 + */ + r6 = 0; + p5.l = 0; + p5.h = hi(COREMMR_BASE); - /* Turn off the icache */ - p0.l = LO(IMEM_CONTROL); - p0.h = HI(IMEM_CONTROL); - R1 = [p0]; - R0 = ~ENICPLB; - R0 = R0 & R1; + /* Zero out registers required by Blackfin ABI */ - /* Disabling of CPLBs should be proceeded by a CSYNC */ + /* Disable circular buffers */ + L0 = r6; + L1 = r6; + L2 = r6; + L3 = r6; + + /* Disable hardware loops in case we were started by 'go' */ + LC0 = r6; + LC1 = r6; + + /* + * Clear ITEST_COMMAND and DTEST_COMMAND registers, + * Leaving these as non-zero can confuse the emulator + */ + [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6; + [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6; CSYNC; - [p0] = R0; + + trace_buffer_init(p0,r0); + + /* Turn off the icache */ + r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)]; + BITCLR (r1, ENICPLB_P); + [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1; SSYNC; /* Turn off the dcache */ - p0.l = LO(DMEM_CONTROL); - p0.h = HI(DMEM_CONTROL); - R1 = [p0]; - R0 = ~ENDCPLB; - R0 = R0 & R1; - - /* Disabling of CPLBs should be proceeded by a CSYNC */ - CSYNC; - [p0] = R0; + r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)]; + BITCLR (r1, ENDCPLB_P); + [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1; SSYNC; /* in case of double faults, save a few things */ - p0.l = _init_retx_coreb; - p0.h = _init_retx_coreb; - R0 = RETX; - [P0] = R0; - + p1.l = _initial_pda_coreb; + p1.h = _initial_pda_coreb; + r4 = RETX; #ifdef CONFIG_DEBUG_DOUBLEFAULT /* Only save these if we are storing them, * This happens here, since L1 gets clobbered * below */ GET_PDA(p0, r0); - r7 = [p0 + PDA_DF_RETX]; - p1.l = _init_saved_retx_coreb; - p1.h = _init_saved_retx_coreb; - [p1] = r7; - - r7 = [p0 + PDA_DF_DCPLB]; - p1.l = _init_saved_dcplb_fault_addr_coreb; - p1.h = _init_saved_dcplb_fault_addr_coreb; - [p1] = r7; - - r7 = [p0 + PDA_DF_ICPLB]; - p1.l = _init_saved_icplb_fault_addr_coreb; - p1.h = _init_saved_icplb_fault_addr_coreb; - [p1] = r7; - - r7 = [p0 + PDA_DF_SEQSTAT]; - p1.l = _init_saved_seqstat_coreb; - p1.h = _init_saved_seqstat_coreb; - [p1] = r7; + r0 = [p0 + PDA_DF_RETX]; + r1 = [p0 + PDA_DF_DCPLB]; + r2 = [p0 + PDA_DF_ICPLB]; + r3 = [p0 + PDA_DF_SEQSTAT]; + [p1 + PDA_INIT_DF_RETX] = r0; + [p1 + PDA_INIT_DF_DCPLB] = r1; + [p1 + PDA_INIT_DF_ICPLB] = r2; + [p1 + PDA_INIT_DF_SEQSTAT] = r3; #endif + [p1 + PDA_INIT_RETX] = r4; /* Initialize stack pointer */ sp.l = lo(INITIAL_STACK); @@ -138,19 +108,13 @@ ENTRY(_coreb_trampoline_start) /* EVT15 = _real_start */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); p1.l = _coreb_start; p1.h = _coreb_start; - [p0] = p1; + [p5 + (EVT15 - COREMMR_BASE)] = p1; csync; - p0.l = lo(IMASK); - p0.h = hi(IMASK); - p1.l = IMASK_IVG15; - p1.h = 0x0; - [p0] = p1; - csync; + r0 = EVT_IVG15 (z); + sti r0; raise 15; p0.l = .LWAIT_HERE; diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S index 76de5724c1e3..8b4d98854403 100644 --- a/arch/blackfin/mach-common/head.S +++ b/arch/blackfin/mach-common/head.S @@ -85,37 +85,25 @@ ENTRY(__start) SSYNC; /* in case of double faults, save a few things */ - p0.l = _init_retx; - p0.h = _init_retx; - R0 = RETX; - [P0] = R0; - + p1.l = _initial_pda; + p1.h = _initial_pda; + r4 = RETX; #ifdef CONFIG_DEBUG_DOUBLEFAULT /* Only save these if we are storing them, * This happens here, since L1 gets clobbered * below */ GET_PDA(p0, r0); - r5 = [p0 + PDA_DF_RETX]; - p1.l = _init_saved_retx; - p1.h = _init_saved_retx; - [p1] = r5; - - r5 = [p0 + PDA_DF_DCPLB]; - p1.l = _init_saved_dcplb_fault_addr; - p1.h = _init_saved_dcplb_fault_addr; - [p1] = r5; - - r5 = [p0 + PDA_DF_ICPLB]; - p1.l = _init_saved_icplb_fault_addr; - p1.h = _init_saved_icplb_fault_addr; - [p1] = r5; - - r5 = [p0 + PDA_DF_SEQSTAT]; - p1.l = _init_saved_seqstat; - p1.h = _init_saved_seqstat; - [p1] = r5; + r0 = [p0 + PDA_DF_RETX]; + r1 = [p0 + PDA_DF_DCPLB]; + r2 = [p0 + PDA_DF_ICPLB]; + r3 = [p0 + PDA_DF_SEQSTAT]; + [p1 + PDA_INIT_DF_RETX] = r0; + [p1 + PDA_INIT_DF_DCPLB] = r1; + [p1 + PDA_INIT_DF_ICPLB] = r2; + [p1 + PDA_INIT_DF_SEQSTAT] = r3; #endif + [p1 + PDA_INIT_RETX] = r4; /* Initialize stack pointer */ sp.l = _init_thread_union + THREAD_SIZE; diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 35e7e1eb0188..1c143a4de5f5 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c @@ -45,9 +45,7 @@ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); unsigned long blackfin_iflush_l1_entry[NR_CPUS]; #endif -void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, - *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, - *init_saved_dcplb_fault_addr_coreb; +struct blackfin_initial_pda __cpuinitdata initial_pda_coreb; #define BFIN_IPI_RESCHEDULE 0 #define BFIN_IPI_CALL_FUNC 1 @@ -369,13 +367,16 @@ void __cpuinit secondary_start_kernel(void) if (_bfin_swrst & SWRST_DBL_FAULT_B) { printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n"); #ifdef CONFIG_DEBUG_DOUBLEFAULT - printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", - (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb); - printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb); - printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb); + printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n", + initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE, + initial_pda_coreb.retx_doublefault); + printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", + initial_pda_coreb.dcplb_doublefault_addr); + printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", + initial_pda_coreb.icplb_doublefault_addr); #endif printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", - init_retx_coreb); + initial_pda_coreb.retx); } /* diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c index c03bc3bc30c2..f51b52432bae 100644 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ b/arch/cris/arch-v32/drivers/cryptocop.c @@ -1394,11 +1394,10 @@ static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH; - p = kmalloc(padlen, alloc_flag); + p = kzalloc(padlen, alloc_flag); if (!p) return -ENOMEM; *p = 0x80; - memset(p+1, 0, padlen - 1); DEBUG(printk("create_md5_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length)); @@ -1426,11 +1425,10 @@ static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, cha if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH; - p = kmalloc(padlen, alloc_flag); + p = kzalloc(padlen, alloc_flag); if (!p) return -ENOMEM; *p = 0x80; - memset(p+1, 0, padlen - 1); DEBUG(printk("create_sha1_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length)); diff --git a/arch/cris/arch-v32/kernel/ptrace.c b/arch/cris/arch-v32/kernel/ptrace.c index 511ece94a574..42ed6c797066 100644 --- a/arch/cris/arch-v32/kernel/ptrace.c +++ b/arch/cris/arch-v32/kernel/ptrace.c @@ -115,8 +115,6 @@ void user_disable_single_step(struct task_struct *child) void ptrace_disable(struct task_struct *child) { - unsigned long tmp; - /* Deconfigure SPC and S-bit. */ user_disable_single_step(child); put_reg(child, PT_SPC, 0); diff --git a/arch/cris/include/arch-v32/arch/cache.h b/arch/cris/include/arch-v32/arch/cache.h index 1de779f4f240..7caf25d58e6b 100644 --- a/arch/cris/include/arch-v32/arch/cache.h +++ b/arch/cris/include/arch-v32/arch/cache.h @@ -7,7 +7,7 @@ #define L1_CACHE_BYTES 32 #define L1_CACHE_SHIFT 5 -#define __read_mostly __attribute__((__section__(".data.read_mostly"))) +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) void flush_dma_list(dma_descr_data *descr); void flush_dma_descr(dma_descr_data *descr, int flush_buf); diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 38280ef4a2af..578701ea03d4 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -27,6 +27,7 @@ config IA64 select GENERIC_PENDING_IRQ if SMP select IRQ_PER_CPU select GENERIC_IRQ_SHOW + select ARCH_WANT_OPTIONAL_GPIOLIB default y help The Itanium Processor Family is Intel's 64-bit successor to @@ -89,6 +90,9 @@ config GENERIC_TIME_VSYSCALL config HAVE_SETUP_PER_CPU_AREA def_bool y +config GENERIC_GPIO + def_bool y + config DMI bool default y diff --git a/arch/ia64/include/asm/gpio.h b/arch/ia64/include/asm/gpio.h new file mode 100644 index 000000000000..590a20debc4e --- /dev/null +++ b/arch/ia64/include/asm/gpio.h @@ -0,0 +1,55 @@ +/* + * Generic GPIO API implementation for IA-64. + * + * A stright copy of that for PowerPC which was: + * + * Copyright (c) 2007-2008 MontaVista Software, Inc. + * + * Author: Anton Vorontsov <avorontsov@ru.mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _ASM_IA64_GPIO_H +#define _ASM_IA64_GPIO_H + +#include <linux/errno.h> +#include <asm-generic/gpio.h> + +#ifdef CONFIG_GPIOLIB + +/* + * We don't (yet) implement inlined/rapid versions for on-chip gpios. + * Just call gpiolib. + */ +static inline int gpio_get_value(unsigned int gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int value) +{ + __gpio_set_value(gpio, value); +} + +static inline int gpio_cansleep(unsigned int gpio) +{ + return __gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned int gpio) +{ + return __gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return -EINVAL; +} + +#endif /* CONFIG_GPIOLIB */ + +#endif /* _ASM_IA64_GPIO_H */ diff --git a/arch/m68k/Kconfig.nommu b/arch/m68k/Kconfig.nommu index fc98f9b9d4d2..b004dc1b1710 100644 --- a/arch/m68k/Kconfig.nommu +++ b/arch/m68k/Kconfig.nommu @@ -14,6 +14,33 @@ config GENERIC_CLOCKEVENTS bool default n +config M68000 + bool + help + The Freescale (was Motorola) 68000 CPU is the first generation of + the well known M68K family of processors. The CPU core as well as + being available as a stand alone CPU was also used in many + System-On-Chip devices (eg 68328, 68302, etc). It does not contain + a paging MMU. + +config MCPU32 + bool + help + The Freescale (was then Motorola) CPU32 is a CPU core that is + based on the 68020 processor. For the most part it is used in + System-On-Chip parts, and does not contain a paging MMU. + +config COLDFIRE + bool + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + The Freescale ColdFire family of processors is a modern derivitive + of the 68000 processor family. They are mainly targeted at embedded + applications, and are all System-On-Chip (SOC) devices, as opposed + to stand alone CPUs. They implement a subset of the original 68000 + processor instruction set. + config COLDFIRE_SW_A7 bool default n @@ -36,26 +63,31 @@ choice config M68328 bool "MC68328" + select M68000 help Motorola 68328 processor support. config M68EZ328 bool "MC68EZ328" + select M68000 help Motorola 68EX328 processor support. config M68VZ328 bool "MC68VZ328" + select M68000 help Motorola 68VZ328 processor support. config M68360 bool "MC68360" + select MCPU32 help Motorola 68360 processor support. config M5206 bool "MCF5206" + select COLDFIRE select COLDFIRE_SW_A7 select HAVE_MBAR help @@ -63,6 +95,7 @@ config M5206 config M5206e bool "MCF5206e" + select COLDFIRE select COLDFIRE_SW_A7 select HAVE_MBAR help @@ -70,6 +103,7 @@ config M5206e config M520x bool "MCF520x" + select COLDFIRE select GENERIC_CLOCKEVENTS select HAVE_CACHE_SPLIT help @@ -77,6 +111,7 @@ config M520x config M523x bool "MCF523x" + select COLDFIRE select GENERIC_CLOCKEVENTS select HAVE_CACHE_SPLIT select HAVE_IPSBAR @@ -85,6 +120,7 @@ config M523x config M5249 bool "MCF5249" + select COLDFIRE select COLDFIRE_SW_A7 select HAVE_MBAR help @@ -92,6 +128,7 @@ config M5249 config M5271 bool "MCF5271" + select COLDFIRE select HAVE_CACHE_SPLIT select HAVE_IPSBAR help @@ -99,6 +136,7 @@ config M5271 config M5272 bool "MCF5272" + select COLDFIRE select COLDFIRE_SW_A7 select HAVE_MBAR help @@ -106,6 +144,7 @@ config M5272 config M5275 bool "MCF5275" + select COLDFIRE select HAVE_CACHE_SPLIT select HAVE_IPSBAR help @@ -113,6 +152,7 @@ config M5275 config M528x bool "MCF528x" + select COLDFIRE select GENERIC_CLOCKEVENTS select HAVE_CACHE_SPLIT select HAVE_IPSBAR @@ -121,6 +161,7 @@ config M528x config M5307 bool "MCF5307" + select COLDFIRE select COLDFIRE_SW_A7 select HAVE_CACHE_CB select HAVE_MBAR @@ -129,12 +170,14 @@ config M5307 config M532x bool "MCF532x" + select COLDFIRE select HAVE_CACHE_CB help Freescale (Motorola) ColdFire 532x processor support. config M5407 bool "MCF5407" + select COLDFIRE select COLDFIRE_SW_A7 select HAVE_CACHE_CB select HAVE_MBAR @@ -143,6 +186,7 @@ config M5407 config M547x bool "MCF547x" + select COLDFIRE select HAVE_CACHE_CB select HAVE_MBAR help @@ -150,6 +194,7 @@ config M547x config M548x bool "MCF548x" + select COLDFIRE select HAVE_CACHE_CB select HAVE_MBAR help @@ -168,13 +213,6 @@ config M54xx depends on (M548x || M547x) default y -config COLDFIRE - bool - depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M54xx) - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - default y - config CLOCK_SET bool "Enable setting the CPU clock frequency" default n diff --git a/arch/m68k/Makefile_no b/arch/m68k/Makefile_no index 81652ab893e1..844d3f172264 100644 --- a/arch/m68k/Makefile_no +++ b/arch/m68k/Makefile_no @@ -13,7 +13,7 @@ platform-$(CONFIG_M68EZ328) := 68EZ328 platform-$(CONFIG_M68VZ328) := 68VZ328 platform-$(CONFIG_M68360) := 68360 platform-$(CONFIG_M5206) := 5206 -platform-$(CONFIG_M5206e) := 5206e +platform-$(CONFIG_M5206e) := 5206 platform-$(CONFIG_M520x) := 520x platform-$(CONFIG_M523x) := 523x platform-$(CONFIG_M5249) := 5249 diff --git a/arch/m68k/amiga/chipram.c b/arch/m68k/amiga/chipram.c index dd0447db1c90..99449fbf9a72 100644 --- a/arch/m68k/amiga/chipram.c +++ b/arch/m68k/amiga/chipram.c @@ -16,6 +16,7 @@ #include <linux/string.h> #include <linux/module.h> +#include <asm/atomic.h> #include <asm/page.h> #include <asm/amigahw.h> @@ -23,111 +24,100 @@ unsigned long amiga_chip_size; EXPORT_SYMBOL(amiga_chip_size); static struct resource chipram_res = { - .name = "Chip RAM", .start = CHIP_PHYSADDR + .name = "Chip RAM", .start = CHIP_PHYSADDR }; -static unsigned long chipavail; +static atomic_t chipavail; void __init amiga_chip_init(void) { - if (!AMIGAHW_PRESENT(CHIP_RAM)) - return; + if (!AMIGAHW_PRESENT(CHIP_RAM)) + return; - chipram_res.end = amiga_chip_size-1; - request_resource(&iomem_resource, &chipram_res); + chipram_res.end = CHIP_PHYSADDR + amiga_chip_size - 1; + request_resource(&iomem_resource, &chipram_res); - chipavail = amiga_chip_size; + atomic_set(&chipavail, amiga_chip_size); } void *amiga_chip_alloc(unsigned long size, const char *name) { - struct resource *res; + struct resource *res; + void *p; - /* round up */ - size = PAGE_ALIGN(size); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); + if (!res) + return NULL; -#ifdef DEBUG - printk("amiga_chip_alloc: allocate %ld bytes\n", size); -#endif - res = kzalloc(sizeof(struct resource), GFP_KERNEL); - if (!res) - return NULL; - res->name = name; + res->name = name; + p = amiga_chip_alloc_res(size, res); + if (!p) { + kfree(res); + return NULL; + } - if (allocate_resource(&chipram_res, res, size, 0, UINT_MAX, PAGE_SIZE, NULL, NULL) < 0) { - kfree(res); - return NULL; - } - chipavail -= size; -#ifdef DEBUG - printk("amiga_chip_alloc: returning %lx\n", res->start); -#endif - return (void *)ZTWO_VADDR(res->start); + return p; } EXPORT_SYMBOL(amiga_chip_alloc); - /* - * Warning: - * amiga_chip_alloc_res is meant only for drivers that need to allocate - * Chip RAM before kmalloc() is functional. As a consequence, those - * drivers must not free that Chip RAM afterwards. - */ + /* + * Warning: + * amiga_chip_alloc_res is meant only for drivers that need to + * allocate Chip RAM before kmalloc() is functional. As a consequence, + * those drivers must not free that Chip RAM afterwards. + */ -void * __init amiga_chip_alloc_res(unsigned long size, struct resource *res) +void *amiga_chip_alloc_res(unsigned long size, struct resource *res) { - unsigned long start; - - /* round up */ - size = PAGE_ALIGN(size); - /* dmesg into chipmem prefers memory at the safe end */ - start = CHIP_PHYSADDR + chipavail - size; - -#ifdef DEBUG - printk("amiga_chip_alloc_res: allocate %ld bytes\n", size); -#endif - if (allocate_resource(&chipram_res, res, size, start, UINT_MAX, PAGE_SIZE, NULL, NULL) < 0) { - printk("amiga_chip_alloc_res: first alloc failed!\n"); - if (allocate_resource(&chipram_res, res, size, 0, UINT_MAX, PAGE_SIZE, NULL, NULL) < 0) - return NULL; - } - chipavail -= size; -#ifdef DEBUG - printk("amiga_chip_alloc_res: returning %lx\n", res->start); -#endif - return (void *)ZTWO_VADDR(res->start); + int error; + + /* round up */ + size = PAGE_ALIGN(size); + + pr_debug("amiga_chip_alloc_res: allocate %lu bytes\n", size); + error = allocate_resource(&chipram_res, res, size, 0, UINT_MAX, + PAGE_SIZE, NULL, NULL); + if (error < 0) { + pr_err("amiga_chip_alloc_res: allocate_resource() failed %d!\n", + error); + return NULL; + } + + atomic_sub(size, &chipavail); + pr_debug("amiga_chip_alloc_res: returning %pR\n", res); + return (void *)ZTWO_VADDR(res->start); } void amiga_chip_free(void *ptr) { - unsigned long start = ZTWO_PADDR(ptr); - struct resource **p, *res; - unsigned long size; - - for (p = &chipram_res.child; (res = *p); p = &res->sibling) { - if (res->start != start) - continue; - *p = res->sibling; - size = res->end-start; -#ifdef DEBUG - printk("amiga_chip_free: free %ld bytes at %p\n", size, ptr); -#endif - chipavail += size; + unsigned long start = ZTWO_PADDR(ptr); + struct resource *res; + unsigned long size; + + res = lookup_resource(&chipram_res, start); + if (!res) { + pr_err("amiga_chip_free: trying to free nonexistent region at " + "%p\n", ptr); + return; + } + + size = resource_size(res); + pr_debug("amiga_chip_free: free %lu bytes at %p\n", size, ptr); + atomic_add(size, &chipavail); + release_resource(res); kfree(res); - return; - } - printk("amiga_chip_free: trying to free nonexistent region at %p\n", ptr); } EXPORT_SYMBOL(amiga_chip_free); unsigned long amiga_chip_avail(void) { -#ifdef DEBUG - printk("amiga_chip_avail : %ld bytes\n", chipavail); -#endif - return chipavail; + unsigned long n = atomic_read(&chipavail); + + pr_debug("amiga_chip_avail : %lu bytes\n", n); + return n; } EXPORT_SYMBOL(amiga_chip_avail); diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index ce163abddaba..3596e563ba2f 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -1,5 +1,521 @@ -#ifdef __uClinux__ -#include "bitops_no.h" +#ifndef _M68K_BITOPS_H +#define _M68K_BITOPS_H +/* + * Copyright 1992, Linus Torvalds. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef _LINUX_BITOPS_H +#error only <linux/bitops.h> can be included directly +#endif + +#include <linux/compiler.h> + +/* + * Bit access functions vary a across the ColdFire and 68k families. + * So we will break them out here, and then macro in the ones we want. + * + * ColdFire - supports standard bset/bclr/bchg with register operand only + * 68000 - supports standard bset/bclr/bchg with memory operand + * >= 68020 - also supports the bfset/bfclr/bfchg instructions + * + * Although it is possible to use only the bset/bclr/bchg with register + * operands on all platforms you end up with larger generated code. + * So we use the best form possible on a given platform. + */ + +static inline void bset_reg_set_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + + __asm__ __volatile__ ("bset %1,(%0)" + : + : "a" (p), "di" (nr & 7) + : "memory"); +} + +static inline void bset_mem_set_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + + __asm__ __volatile__ ("bset %1,%0" + : "+m" (*p) + : "di" (nr & 7)); +} + +static inline void bfset_mem_set_bit(int nr, volatile unsigned long *vaddr) +{ + __asm__ __volatile__ ("bfset %1{%0:#1}" + : + : "d" (nr ^ 31), "o" (*vaddr) + : "memory"); +} + +#if defined(CONFIG_COLDFIRE) +#define set_bit(nr,vaddr) bset_reg_set_bit(nr,vaddr) +#elif defined(CONFIG_M68000) || defined(CONFIG_MCPU32) +#define set_bit(nr,vaddr) bset_mem_set_bit(nr,vaddr) +#else +#define set_bit(nr,vaddr) (__builtin_constant_p(nr) ? \ + bset_mem_set_bit(nr,vaddr) : \ + bfset_mem_set_bit(nr,vaddr)) +#endif + +#define __set_bit(nr,vaddr) set_bit(nr,vaddr) + + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +static inline void bclr_reg_clear_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + + __asm__ __volatile__ ("bclr %1,(%0)" + : + : "a" (p), "di" (nr & 7) + : "memory"); +} + +static inline void bclr_mem_clear_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + + __asm__ __volatile__ ("bclr %1,%0" + : "+m" (*p) + : "di" (nr & 7)); +} + +static inline void bfclr_mem_clear_bit(int nr, volatile unsigned long *vaddr) +{ + __asm__ __volatile__ ("bfclr %1{%0:#1}" + : + : "d" (nr ^ 31), "o" (*vaddr) + : "memory"); +} + +#if defined(CONFIG_COLDFIRE) +#define clear_bit(nr,vaddr) bclr_reg_clear_bit(nr,vaddr) +#elif defined(CONFIG_M68000) || defined(CONFIG_MCPU32) +#define clear_bit(nr,vaddr) bclr_mem_clear_bit(nr,vaddr) +#else +#define clear_bit(nr,vaddr) (__builtin_constant_p(nr) ? \ + bclr_mem_clear_bit(nr, vaddr) : \ + bfclr_mem_clear_bit(nr, vaddr)) +#endif + +#define __clear_bit(nr,vaddr) clear_bit(nr,vaddr) + + +static inline void bchg_reg_change_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + + __asm__ __volatile__ ("bchg %1,(%0)" + : + : "a" (p), "di" (nr & 7) + : "memory"); +} + +static inline void bchg_mem_change_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + + __asm__ __volatile__ ("bchg %1,%0" + : "+m" (*p) + : "di" (nr & 7)); +} + +static inline void bfchg_mem_change_bit(int nr, volatile unsigned long *vaddr) +{ + __asm__ __volatile__ ("bfchg %1{%0:#1}" + : + : "d" (nr ^ 31), "o" (*vaddr) + : "memory"); +} + +#if defined(CONFIG_COLDFIRE) +#define change_bit(nr,vaddr) bchg_reg_change_bit(nr,vaddr) +#elif defined(CONFIG_M68000) || defined(CONFIG_MCPU32) +#define change_bit(nr,vaddr) bchg_mem_change_bit(nr,vaddr) +#else +#define change_bit(nr,vaddr) (__builtin_constant_p(nr) ? \ + bchg_mem_change_bit(nr,vaddr) : \ + bfchg_mem_change_bit(nr,vaddr)) +#endif + +#define __change_bit(nr,vaddr) change_bit(nr,vaddr) + + +static inline int test_bit(int nr, const unsigned long *vaddr) +{ + return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0; +} + + +static inline int bset_reg_test_and_set_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + char retval; + + __asm__ __volatile__ ("bset %2,(%1); sne %0" + : "=d" (retval) + : "a" (p), "di" (nr & 7) + : "memory"); + return retval; +} + +static inline int bset_mem_test_and_set_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + char retval; + + __asm__ __volatile__ ("bset %2,%1; sne %0" + : "=d" (retval), "+m" (*p) + : "di" (nr & 7)); + return retval; +} + +static inline int bfset_mem_test_and_set_bit(int nr, volatile unsigned long *vaddr) +{ + char retval; + + __asm__ __volatile__ ("bfset %2{%1:#1}; sne %0" + : "=d" (retval) + : "d" (nr ^ 31), "o" (*vaddr) + : "memory"); + return retval; +} + +#if defined(CONFIG_COLDFIRE) +#define test_and_set_bit(nr,vaddr) bset_reg_test_and_set_bit(nr,vaddr) +#elif defined(CONFIG_M68000) || defined(CONFIG_MCPU32) +#define test_and_set_bit(nr,vaddr) bset_mem_test_and_set_bit(nr,vaddr) +#else +#define test_and_set_bit(nr,vaddr) (__builtin_constant_p(nr) ? \ + bset_mem_test_and_set_bit(nr,vaddr) : \ + bfset_mem_test_and_set_bit(nr,vaddr)) +#endif + +#define __test_and_set_bit(nr,vaddr) test_and_set_bit(nr,vaddr) + + +static inline int bclr_reg_test_and_clear_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + char retval; + + __asm__ __volatile__ ("bclr %2,(%1); sne %0" + : "=d" (retval) + : "a" (p), "di" (nr & 7) + : "memory"); + return retval; +} + +static inline int bclr_mem_test_and_clear_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + char retval; + + __asm__ __volatile__ ("bclr %2,%1; sne %0" + : "=d" (retval), "+m" (*p) + : "di" (nr & 7)); + return retval; +} + +static inline int bfclr_mem_test_and_clear_bit(int nr, volatile unsigned long *vaddr) +{ + char retval; + + __asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0" + : "=d" (retval) + : "d" (nr ^ 31), "o" (*vaddr) + : "memory"); + return retval; +} + +#if defined(CONFIG_COLDFIRE) +#define test_and_clear_bit(nr,vaddr) bclr_reg_test_and_clear_bit(nr,vaddr) +#elif defined(CONFIG_M68000) || defined(CONFIG_MCPU32) +#define test_and_clear_bit(nr,vaddr) bclr_mem_test_and_clear_bit(nr,vaddr) +#else +#define test_and_clear_bit(nr,vaddr) (__builtin_constant_p(nr) ? \ + bclr_mem_test_and_clear_bit(nr,vaddr) : \ + bfclr_mem_test_and_clear_bit(nr,vaddr)) +#endif + +#define __test_and_clear_bit(nr,vaddr) test_and_clear_bit(nr,vaddr) + + +static inline int bchg_reg_test_and_change_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + char retval; + + __asm__ __volatile__ ("bchg %2,(%1); sne %0" + : "=d" (retval) + : "a" (p), "di" (nr & 7) + : "memory"); + return retval; +} + +static inline int bchg_mem_test_and_change_bit(int nr, volatile unsigned long *vaddr) +{ + char *p = (char *)vaddr + (nr ^ 31) / 8; + char retval; + + __asm__ __volatile__ ("bchg %2,%1; sne %0" + : "=d" (retval), "+m" (*p) + : "di" (nr & 7)); + return retval; +} + +static inline int bfchg_mem_test_and_change_bit(int nr, volatile unsigned long *vaddr) +{ + char retval; + + __asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0" + : "=d" (retval) + : "d" (nr ^ 31), "o" (*vaddr) + : "memory"); + return retval; +} + +#if defined(CONFIG_COLDFIRE) +#define test_and_change_bit(nr,vaddr) bchg_reg_test_and_change_bit(nr,vaddr) +#elif defined(CONFIG_M68000) || defined(CONFIG_MCPU32) +#define test_and_change_bit(nr,vaddr) bchg_mem_test_and_change_bit(nr,vaddr) +#else +#define test_and_change_bit(nr,vaddr) (__builtin_constant_p(nr) ? \ + bchg_mem_test_and_change_bit(nr,vaddr) : \ + bfchg_mem_test_and_change_bit(nr,vaddr)) +#endif + +#define __test_and_change_bit(nr,vaddr) test_and_change_bit(nr,vaddr) + + +/* + * The true 68020 and more advanced processors support the "bfffo" + * instruction for finding bits. ColdFire and simple 68000 parts + * (including CPU32) do not support this. They simply use the generic + * functions. + */ +#if defined(CONFIG_M68000) || defined(CONFIG_MCPU32) || defined(CONFIG_COLDFIRE) +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ffz.h> +#else + +static inline int find_first_zero_bit(const unsigned long *vaddr, + unsigned size) +{ + const unsigned long *p = vaddr; + int res = 32; + unsigned int words; + unsigned long num; + + if (!size) + return 0; + + words = (size + 31) >> 5; + while (!(num = ~*p++)) { + if (!--words) + goto out; + } + + __asm__ __volatile__ ("bfffo %1{#0,#0},%0" + : "=d" (res) : "d" (num & -num)); + res ^= 31; +out: + res += ((long)p - (long)vaddr - 4) * 8; + return res < size ? res : size; +} +#define find_first_zero_bit find_first_zero_bit + +static inline int find_next_zero_bit(const unsigned long *vaddr, int size, + int offset) +{ + const unsigned long *p = vaddr + (offset >> 5); + int bit = offset & 31UL, res; + + if (offset >= size) + return size; + + if (bit) { + unsigned long num = ~*p++ & (~0UL << bit); + offset -= bit; + + /* Look for zero in first longword */ + __asm__ __volatile__ ("bfffo %1{#0,#0},%0" + : "=d" (res) : "d" (num & -num)); + if (res < 32) { + offset += res ^ 31; + return offset < size ? offset : size; + } + offset += 32; + + if (offset >= size) + return size; + } + /* No zero yet, search remaining full bytes for a zero */ + return offset + find_first_zero_bit(p, size - offset); +} +#define find_next_zero_bit find_next_zero_bit + +static inline int find_first_bit(const unsigned long *vaddr, unsigned size) +{ + const unsigned long *p = vaddr; + int res = 32; + unsigned int words; + unsigned long num; + + if (!size) + return 0; + + words = (size + 31) >> 5; + while (!(num = *p++)) { + if (!--words) + goto out; + } + + __asm__ __volatile__ ("bfffo %1{#0,#0},%0" + : "=d" (res) : "d" (num & -num)); + res ^= 31; +out: + res += ((long)p - (long)vaddr - 4) * 8; + return res < size ? res : size; +} +#define find_first_bit find_first_bit + +static inline int find_next_bit(const unsigned long *vaddr, int size, + int offset) +{ + const unsigned long *p = vaddr + (offset >> 5); + int bit = offset & 31UL, res; + + if (offset >= size) + return size; + + if (bit) { + unsigned long num = *p++ & (~0UL << bit); + offset -= bit; + + /* Look for one in first longword */ + __asm__ __volatile__ ("bfffo %1{#0,#0},%0" + : "=d" (res) : "d" (num & -num)); + if (res < 32) { + offset += res ^ 31; + return offset < size ? offset : size; + } + offset += 32; + + if (offset >= size) + return size; + } + /* No one yet, search remaining full bytes for a one */ + return offset + find_first_bit(p, size - offset); +} +#define find_next_bit find_next_bit + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) +{ + int res; + + __asm__ __volatile__ ("bfffo %1{#0,#0},%0" + : "=d" (res) : "d" (~word & -~word)); + return res ^ 31; +} + +#endif + +#ifdef __KERNEL__ + +#if defined(CONFIG_M68000) || defined(CONFIG_MCPU32) || defined(CONFIG_COLDFIRE) + +/* + * The newer ColdFire family members support a "bitrev" instruction + * and we can use that to implement a fast ffs. Older Coldfire parts, + * and normal 68000 parts don't have anything special, so we use the + * generic functions for those. + */ +#if (defined(__mcfisaaplus__) || defined(__mcfisac__)) && \ + !defined(CONFIG_M68000) && !defined(CONFIG_MCPU32) +static inline int __ffs(int x) +{ + __asm__ __volatile__ ("bitrev %0; ff1 %0" + : "=d" (x) + : "0" (x)); + return x; +} + +static inline int ffs(int x) +{ + if (!x) + return 0; + return __ffs(x) + 1; +} + +#else +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/__ffs.h> +#endif + +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> + #else -#include "bitops_mm.h" + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static inline int ffs(int x) +{ + int cnt; + + __asm__ ("bfffo %1{#0:#0},%0" + : "=d" (cnt) + : "dm" (x & -x)); + return 32 - cnt; +} +#define __ffs(x) (ffs(x) - 1) + +/* + * fls: find last bit set. + */ +static inline int fls(int x) +{ + int cnt; + + __asm__ ("bfffo %1{#0,#0},%0" + : "=d" (cnt) + : "dm" (x)); + return 32 - cnt; +} + +static inline int __fls(int x) +{ + return fls(x) - 1; +} + #endif + +#include <asm-generic/bitops/ext2-atomic.h> +#include <asm-generic/bitops/le.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/sched.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/lock.h> +#endif /* __KERNEL__ */ + +#endif /* _M68K_BITOPS_H */ diff --git a/arch/m68k/include/asm/bitops_mm.h b/arch/m68k/include/asm/bitops_mm.h deleted file mode 100644 index 89cf5b814a4d..000000000000 --- a/arch/m68k/include/asm/bitops_mm.h +++ /dev/null @@ -1,501 +0,0 @@ -#ifndef _M68K_BITOPS_H -#define _M68K_BITOPS_H -/* - * Copyright 1992, Linus Torvalds. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _LINUX_BITOPS_H -#error only <linux/bitops.h> can be included directly -#endif - -#include <linux/compiler.h> - -/* - * Require 68020 or better. - * - * They use the standard big-endian m680x0 bit ordering. - */ - -#define test_and_set_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_test_and_set_bit(nr, vaddr) : \ - __generic_test_and_set_bit(nr, vaddr)) - -#define __test_and_set_bit(nr,vaddr) test_and_set_bit(nr,vaddr) - -static inline int __constant_test_and_set_bit(int nr, unsigned long *vaddr) -{ - char *p = (char *)vaddr + (nr ^ 31) / 8; - char retval; - - __asm__ __volatile__ ("bset %2,%1; sne %0" - : "=d" (retval), "+m" (*p) - : "di" (nr & 7)); - - return retval; -} - -static inline int __generic_test_and_set_bit(int nr, unsigned long *vaddr) -{ - char retval; - - __asm__ __volatile__ ("bfset %2{%1:#1}; sne %0" - : "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory"); - - return retval; -} - -#define set_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_set_bit(nr, vaddr) : \ - __generic_set_bit(nr, vaddr)) - -#define __set_bit(nr,vaddr) set_bit(nr,vaddr) - -static inline void __constant_set_bit(int nr, volatile unsigned long *vaddr) -{ - char *p = (char *)vaddr + (nr ^ 31) / 8; - __asm__ __volatile__ ("bset %1,%0" - : "+m" (*p) : "di" (nr & 7)); -} - -static inline void __generic_set_bit(int nr, volatile unsigned long *vaddr) -{ - __asm__ __volatile__ ("bfset %1{%0:#1}" - : : "d" (nr^31), "o" (*vaddr) : "memory"); -} - -#define test_and_clear_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_test_and_clear_bit(nr, vaddr) : \ - __generic_test_and_clear_bit(nr, vaddr)) - -#define __test_and_clear_bit(nr,vaddr) test_and_clear_bit(nr,vaddr) - -static inline int __constant_test_and_clear_bit(int nr, unsigned long *vaddr) -{ - char *p = (char *)vaddr + (nr ^ 31) / 8; - char retval; - - __asm__ __volatile__ ("bclr %2,%1; sne %0" - : "=d" (retval), "+m" (*p) - : "di" (nr & 7)); - - return retval; -} - -static inline int __generic_test_and_clear_bit(int nr, unsigned long *vaddr) -{ - char retval; - - __asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0" - : "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory"); - - return retval; -} - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -#define clear_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_clear_bit(nr, vaddr) : \ - __generic_clear_bit(nr, vaddr)) -#define __clear_bit(nr,vaddr) clear_bit(nr,vaddr) - -static inline void __constant_clear_bit(int nr, volatile unsigned long *vaddr) -{ - char *p = (char *)vaddr + (nr ^ 31) / 8; - __asm__ __volatile__ ("bclr %1,%0" - : "+m" (*p) : "di" (nr & 7)); -} - -static inline void __generic_clear_bit(int nr, volatile unsigned long *vaddr) -{ - __asm__ __volatile__ ("bfclr %1{%0:#1}" - : : "d" (nr^31), "o" (*vaddr) : "memory"); -} - -#define test_and_change_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_test_and_change_bit(nr, vaddr) : \ - __generic_test_and_change_bit(nr, vaddr)) - -#define __test_and_change_bit(nr,vaddr) test_and_change_bit(nr,vaddr) -#define __change_bit(nr,vaddr) change_bit(nr,vaddr) - -static inline int __constant_test_and_change_bit(int nr, unsigned long *vaddr) -{ - char *p = (char *)vaddr + (nr ^ 31) / 8; - char retval; - - __asm__ __volatile__ ("bchg %2,%1; sne %0" - : "=d" (retval), "+m" (*p) - : "di" (nr & 7)); - - return retval; -} - -static inline int __generic_test_and_change_bit(int nr, unsigned long *vaddr) -{ - char retval; - - __asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0" - : "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory"); - - return retval; -} - -#define change_bit(nr,vaddr) \ - (__builtin_constant_p(nr) ? \ - __constant_change_bit(nr, vaddr) : \ - __generic_change_bit(nr, vaddr)) - -static inline void __constant_change_bit(int nr, unsigned long *vaddr) -{ - char *p = (char *)vaddr + (nr ^ 31) / 8; - __asm__ __volatile__ ("bchg %1,%0" - : "+m" (*p) : "di" (nr & 7)); -} - -static inline void __generic_change_bit(int nr, unsigned long *vaddr) -{ - __asm__ __volatile__ ("bfchg %1{%0:#1}" - : : "d" (nr^31), "o" (*vaddr) : "memory"); -} - -static inline int test_bit(int nr, const unsigned long *vaddr) -{ - return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0; -} - -static inline int find_first_zero_bit(const unsigned long *vaddr, - unsigned size) -{ - const unsigned long *p = vaddr; - int res = 32; - unsigned int words; - unsigned long num; - - if (!size) - return 0; - - words = (size + 31) >> 5; - while (!(num = ~*p++)) { - if (!--words) - goto out; - } - - __asm__ __volatile__ ("bfffo %1{#0,#0},%0" - : "=d" (res) : "d" (num & -num)); - res ^= 31; -out: - res += ((long)p - (long)vaddr - 4) * 8; - return res < size ? res : size; -} -#define find_first_zero_bit find_first_zero_bit - -static inline int find_next_zero_bit(const unsigned long *vaddr, int size, - int offset) -{ - const unsigned long *p = vaddr + (offset >> 5); - int bit = offset & 31UL, res; - - if (offset >= size) - return size; - - if (bit) { - unsigned long num = ~*p++ & (~0UL << bit); - offset -= bit; - - /* Look for zero in first longword */ - __asm__ __volatile__ ("bfffo %1{#0,#0},%0" - : "=d" (res) : "d" (num & -num)); - if (res < 32) { - offset += res ^ 31; - return offset < size ? offset : size; - } - offset += 32; - - if (offset >= size) - return size; - } - /* No zero yet, search remaining full bytes for a zero */ - return offset + find_first_zero_bit(p, size - offset); -} -#define find_next_zero_bit find_next_zero_bit - -static inline int find_first_bit(const unsigned long *vaddr, unsigned size) -{ - const unsigned long *p = vaddr; - int res = 32; - unsigned int words; - unsigned long num; - - if (!size) - return 0; - - words = (size + 31) >> 5; - while (!(num = *p++)) { - if (!--words) - goto out; - } - - __asm__ __volatile__ ("bfffo %1{#0,#0},%0" - : "=d" (res) : "d" (num & -num)); - res ^= 31; -out: - res += ((long)p - (long)vaddr - 4) * 8; - return res < size ? res : size; -} -#define find_first_bit find_first_bit - -static inline int find_next_bit(const unsigned long *vaddr, int size, - int offset) -{ - const unsigned long *p = vaddr + (offset >> 5); - int bit = offset & 31UL, res; - - if (offset >= size) - return size; - - if (bit) { - unsigned long num = *p++ & (~0UL << bit); - offset -= bit; - - /* Look for one in first longword */ - __asm__ __volatile__ ("bfffo %1{#0,#0},%0" - : "=d" (res) : "d" (num & -num)); - if (res < 32) { - offset += res ^ 31; - return offset < size ? offset : size; - } - offset += 32; - - if (offset >= size) - return size; - } - /* No one yet, search remaining full bytes for a one */ - return offset + find_first_bit(p, size - offset); -} -#define find_next_bit find_next_bit - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - int res; - - __asm__ __volatile__ ("bfffo %1{#0,#0},%0" - : "=d" (res) : "d" (~word & -~word)); - return res ^ 31; -} - -#ifdef __KERNEL__ - -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -static inline int ffs(int x) -{ - int cnt; - - asm ("bfffo %1{#0:#0},%0" : "=d" (cnt) : "dm" (x & -x)); - - return 32 - cnt; -} -#define __ffs(x) (ffs(x) - 1) - -/* - * fls: find last bit set. - */ - -static inline int fls(int x) -{ - int cnt; - - asm ("bfffo %1{#0,#0},%0" : "=d" (cnt) : "dm" (x)); - - return 32 - cnt; -} - -static inline int __fls(int x) -{ - return fls(x) - 1; -} - -#include <asm-generic/bitops/fls64.h> -#include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/hweight.h> -#include <asm-generic/bitops/lock.h> - -/* Bitmap functions for the little endian bitmap. */ - -static inline void __set_bit_le(int nr, void *addr) -{ - __set_bit(nr ^ 24, addr); -} - -static inline void __clear_bit_le(int nr, void *addr) -{ - __clear_bit(nr ^ 24, addr); -} - -static inline int __test_and_set_bit_le(int nr, void *addr) -{ - return __test_and_set_bit(nr ^ 24, addr); -} - -static inline int test_and_set_bit_le(int nr, void *addr) -{ - return test_and_set_bit(nr ^ 24, addr); -} - -static inline int __test_and_clear_bit_le(int nr, void *addr) -{ - return __test_and_clear_bit(nr ^ 24, addr); -} - -static inline int test_and_clear_bit_le(int nr, void *addr) -{ - return test_and_clear_bit(nr ^ 24, addr); -} - -static inline int test_bit_le(int nr, const void *vaddr) -{ - const unsigned char *p = vaddr; - return (p[nr >> 3] & (1U << (nr & 7))) != 0; -} - -static inline int find_first_zero_bit_le(const void *vaddr, unsigned size) -{ - const unsigned long *p = vaddr, *addr = vaddr; - int res = 0; - unsigned int words; - - if (!size) - return 0; - - words = (size >> 5) + ((size & 31) > 0); - while (*p++ == ~0UL) { - if (--words == 0) - goto out; - } - - --p; - for (res = 0; res < 32; res++) - if (!test_bit_le(res, p)) - break; -out: - res += (p - addr) * 32; - return res < size ? res : size; -} -#define find_first_zero_bit_le find_first_zero_bit_le - -static inline unsigned long find_next_zero_bit_le(const void *addr, - unsigned long size, unsigned long offset) -{ - const unsigned long *p = addr; - int bit = offset & 31UL, res; - - if (offset >= size) - return size; - - p += offset >> 5; - - if (bit) { - offset -= bit; - /* Look for zero in first longword */ - for (res = bit; res < 32; res++) - if (!test_bit_le(res, p)) { - offset += res; - return offset < size ? offset : size; - } - p++; - offset += 32; - - if (offset >= size) - return size; - } - /* No zero yet, search remaining full bytes for a zero */ - return offset + find_first_zero_bit_le(p, size - offset); -} -#define find_next_zero_bit_le find_next_zero_bit_le - -static inline int find_first_bit_le(const void *vaddr, unsigned size) -{ - const unsigned long *p = vaddr, *addr = vaddr; - int res = 0; - unsigned int words; - - if (!size) - return 0; - - words = (size >> 5) + ((size & 31) > 0); - while (*p++ == 0UL) { - if (--words == 0) - goto out; - } - - --p; - for (res = 0; res < 32; res++) - if (test_bit_le(res, p)) - break; -out: - res += (p - addr) * 32; - return res < size ? res : size; -} -#define find_first_bit_le find_first_bit_le - -static inline unsigned long find_next_bit_le(const void *addr, - unsigned long size, unsigned long offset) -{ - const unsigned long *p = addr; - int bit = offset & 31UL, res; - - if (offset >= size) - return size; - - p += offset >> 5; - - if (bit) { - offset -= bit; - /* Look for one in first longword */ - for (res = bit; res < 32; res++) - if (test_bit_le(res, p)) { - offset += res; - return offset < size ? offset : size; - } - p++; - offset += 32; - - if (offset >= size) - return size; - } - /* No set bit yet, search remaining full bytes for a set bit */ - return offset + find_first_bit_le(p, size - offset); -} -#define find_next_bit_le find_next_bit_le - -/* Bitmap functions for the ext2 filesystem. */ - -#define ext2_set_bit_atomic(lock, nr, addr) \ - test_and_set_bit_le(nr, addr) -#define ext2_clear_bit_atomic(lock, nr, addr) \ - test_and_clear_bit_le(nr, addr) - -#endif /* __KERNEL__ */ - -#endif /* _M68K_BITOPS_H */ diff --git a/arch/m68k/include/asm/bitops_no.h b/arch/m68k/include/asm/bitops_no.h deleted file mode 100644 index 72e85acdd7bd..000000000000 --- a/arch/m68k/include/asm/bitops_no.h +++ /dev/null @@ -1,333 +0,0 @@ -#ifndef _M68KNOMMU_BITOPS_H -#define _M68KNOMMU_BITOPS_H - -/* - * Copyright 1992, Linus Torvalds. - */ - -#include <linux/compiler.h> -#include <asm/byteorder.h> /* swab32 */ - -#ifdef __KERNEL__ - -#ifndef _LINUX_BITOPS_H -#error only <linux/bitops.h> can be included directly -#endif - -#if defined (__mcfisaaplus__) || defined (__mcfisac__) -static inline int ffs(unsigned int val) -{ - if (!val) - return 0; - - asm volatile( - "bitrev %0\n\t" - "ff1 %0\n\t" - : "=d" (val) - : "0" (val) - ); - val++; - return val; -} - -static inline int __ffs(unsigned int val) -{ - asm volatile( - "bitrev %0\n\t" - "ff1 %0\n\t" - : "=d" (val) - : "0" (val) - ); - return val; -} - -#else -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/__ffs.h> -#endif - -#include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/ffz.h> - -static __inline__ void set_bit(int nr, volatile unsigned long * addr) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0", "cc"); -#else - __asm__ __volatile__ ("bset %1,%0" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - : "cc"); -#endif -} - -#define __set_bit(nr, addr) set_bit(nr, addr) - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -static __inline__ void clear_bit(int nr, volatile unsigned long * addr) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0", "cc"); -#else - __asm__ __volatile__ ("bclr %1,%0" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - : "cc"); -#endif -} - -#define __clear_bit(nr, addr) clear_bit(nr, addr) - -static __inline__ void change_bit(int nr, volatile unsigned long * addr) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0", "cc"); -#else - __asm__ __volatile__ ("bchg %1,%0" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - : "cc"); -#endif -} - -#define __change_bit(nr, addr) change_bit(nr, addr) - -static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bset %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr) - -static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bclr %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr) - -static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bchg %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr) - -/* - * This routine doesn't need to be atomic. - */ -static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr) -{ - return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; -} - -static __inline__ int __test_bit(int nr, const volatile unsigned long * addr) -{ - int * a = (int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); -} - -#define test_bit(nr,addr) \ -(__builtin_constant_p(nr) ? \ - __constant_test_bit((nr),(addr)) : \ - __test_bit((nr),(addr))) - -#include <asm-generic/bitops/find.h> -#include <asm-generic/bitops/hweight.h> -#include <asm-generic/bitops/lock.h> - -#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) - -static inline void __set_bit_le(int nr, void *addr) -{ - __set_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline void __clear_bit_le(int nr, void *addr) -{ - __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline int __test_and_set_bit_le(int nr, volatile void *addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bset %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -static inline int __test_and_clear_bit_le(int nr, volatile void *addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bclr %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#include <asm-generic/bitops/ext2-atomic.h> - -static inline int test_bit_le(int nr, const volatile void *addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0" - : "=d" (retval) - : "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("btst %2,%1; sne %0" - : "=d" (retval) - : "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define find_first_zero_bit_le(addr, size) \ - find_next_zero_bit_le((addr), (size), 0) - -static inline unsigned long find_next_zero_bit_le(void *addr, unsigned long size, unsigned long offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if(offset) { - /* We hold the little endian value in tmp, but then the - * shift is illegal. So we could keep a big endian value - * in tmp, like this: - * - * tmp = __swab32(*(p++)); - * tmp |= ~0UL >> (32-offset); - * - * but this would decrease performance, so we change the - * shift: - */ - tmp = *(p++); - tmp |= __swab32(~0UL >> (32-offset)); - if(size < 32) - goto found_first; - if(~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while(size & ~31UL) { - if(~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if(!size) - return result; - tmp = *p; - -found_first: - /* tmp is little endian, so we would have to swab the shift, - * see above. But then we have to swab tmp below for ffz, so - * we might as well do this here. - */ - return result + ffz(__swab32(tmp) | (~0UL << size)); -found_middle: - return result + ffz(__swab32(tmp)); -} -#define find_next_zero_bit_le find_next_zero_bit_le - -extern unsigned long find_next_bit_le(const void *addr, - unsigned long size, unsigned long offset); - -#endif /* __KERNEL__ */ - -#include <asm-generic/bitops/fls.h> -#include <asm-generic/bitops/__fls.h> -#include <asm-generic/bitops/fls64.h> - -#endif /* _M68KNOMMU_BITOPS_H */ diff --git a/arch/m68k/include/asm/entry_no.h b/arch/m68k/include/asm/entry_no.h index 627d69bacc58..68611e3dbb1d 100644 --- a/arch/m68k/include/asm/entry_no.h +++ b/arch/m68k/include/asm/entry_no.h @@ -96,11 +96,11 @@ .endm .macro RDUSP - movel sw_usp,%a2 + movel sw_usp,%a3 .endm .macro WRUSP - movel %a0,sw_usp + movel %a3,sw_usp .endm #else /* !CONFIG_COLDFIRE_SW_A7 */ @@ -127,13 +127,13 @@ .endm .macro RDUSP - /*move %usp,%a2*/ - .word 0x4e6a + /*move %usp,%a3*/ + .word 0x4e6b .endm .macro WRUSP - /*move %a0,%usp*/ - .word 0x4e60 + /*move %a3,%usp*/ + .word 0x4e63 .endm #endif /* !CONFIG_COLDFIRE_SW_A7 */ diff --git a/arch/m68k/include/asm/hardirq.h b/arch/m68k/include/asm/hardirq.h index 56d0d5db231c..870e5347155b 100644 --- a/arch/m68k/include/asm/hardirq.h +++ b/arch/m68k/include/asm/hardirq.h @@ -1,5 +1,34 @@ -#ifdef __uClinux__ -#include "hardirq_no.h" +#ifndef __M68K_HARDIRQ_H +#define __M68K_HARDIRQ_H + +#include <linux/threads.h> +#include <linux/cache.h> +#include <asm/irq.h> + +#define HARDIRQ_BITS 8 + +/* + * The hardirq mask has to be large enough to have + * space for potentially all IRQ sources in the system + * nesting on a single CPU: + */ +#if (1 << HARDIRQ_BITS) < NR_IRQS +# error HARDIRQ_BITS is too low! +#endif + +#ifdef CONFIG_MMU + +/* entry.S is sensitive to the offsets of these fields */ +typedef struct { + unsigned int __softirq_pending; +} ____cacheline_aligned irq_cpustat_t; + +#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ + #else -#include "hardirq_mm.h" + +#include <asm-generic/hardirq.h> + +#endif /* !CONFIG_MMU */ + #endif diff --git a/arch/m68k/include/asm/hardirq_mm.h b/arch/m68k/include/asm/hardirq_mm.h deleted file mode 100644 index 394ee946015c..000000000000 --- a/arch/m68k/include/asm/hardirq_mm.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __M68K_HARDIRQ_H -#define __M68K_HARDIRQ_H - -#include <linux/threads.h> -#include <linux/cache.h> - -/* entry.S is sensitive to the offsets of these fields */ -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ - -#define HARDIRQ_BITS 8 - -#endif diff --git a/arch/m68k/include/asm/hardirq_no.h b/arch/m68k/include/asm/hardirq_no.h deleted file mode 100644 index b44b14be87d9..000000000000 --- a/arch/m68k/include/asm/hardirq_no.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __M68K_HARDIRQ_H -#define __M68K_HARDIRQ_H - -#include <asm/irq.h> - -#define HARDIRQ_BITS 8 - -/* - * The hardirq mask has to be large enough to have - * space for potentially all IRQ sources in the system - * nesting on a single CPU: - */ -#if (1 << HARDIRQ_BITS) < NR_IRQS -# error HARDIRQ_BITS is too low! -#endif - -#include <asm-generic/hardirq.h> - -#endif /* __M68K_HARDIRQ_H */ diff --git a/arch/m68k/include/asm/irq.h b/arch/m68k/include/asm/irq.h index 907eff1edd2f..67c9738ce8e4 100644 --- a/arch/m68k/include/asm/irq.h +++ b/arch/m68k/include/asm/irq.h @@ -33,15 +33,6 @@ #include <linux/spinlock_types.h> /* - * The hardirq mask has to be large enough to have - * space for potentially all IRQ sources in the system - * nesting on a single CPU: - */ -#if (1 << HARDIRQ_BITS) < NR_IRQS -# error HARDIRQ_BITS is too low! -#endif - -/* * Interrupt source definitions * General interrupt sources are the level 1-7. * Adding an interrupt service routine for one of these sources diff --git a/arch/m68k/include/asm/module.h b/arch/m68k/include/asm/module.h index 5f21e11071bd..edffe66b7f49 100644 --- a/arch/m68k/include/asm/module.h +++ b/arch/m68k/include/asm/module.h @@ -1,46 +1,41 @@ #ifndef _ASM_M68K_MODULE_H #define _ASM_M68K_MODULE_H -#ifdef CONFIG_MMU +enum m68k_fixup_type { + m68k_fixup_memoffset, + m68k_fixup_vnode_shift, +}; + +struct m68k_fixup_info { + enum m68k_fixup_type type; + void *addr; +}; struct mod_arch_specific { struct m68k_fixup_info *fixup_start, *fixup_end; }; +#ifdef CONFIG_MMU + #define MODULE_ARCH_INIT { \ .fixup_start = __start_fixup, \ .fixup_end = __stop_fixup, \ } -enum m68k_fixup_type { - m68k_fixup_memoffset, - m68k_fixup_vnode_shift, -}; - -struct m68k_fixup_info { - enum m68k_fixup_type type; - void *addr; -}; - #define m68k_fixup(type, addr) \ " .section \".m68k_fixup\",\"aw\"\n" \ " .long " #type "," #addr "\n" \ " .previous\n" +#endif /* CONFIG_MMU */ + extern struct m68k_fixup_info __start_fixup[], __stop_fixup[]; struct module; extern void module_fixup(struct module *mod, struct m68k_fixup_info *start, struct m68k_fixup_info *end); -#else - -struct mod_arch_specific { -}; - -#endif /* CONFIG_MMU */ - #define Elf_Shdr Elf32_Shdr #define Elf_Sym Elf32_Sym #define Elf_Ehdr Elf32_Ehdr diff --git a/arch/m68k/include/asm/system.h b/arch/m68k/include/asm/system.h index ccea925ff4f5..47b01f4726bc 100644 --- a/arch/m68k/include/asm/system.h +++ b/arch/m68k/include/asm/system.h @@ -1,5 +1,193 @@ -#ifdef __uClinux__ -#include "system_no.h" +#ifndef _M68K_SYSTEM_H +#define _M68K_SYSTEM_H + +#include <linux/linkage.h> +#include <linux/kernel.h> +#include <linux/irqflags.h> +#include <asm/segment.h> +#include <asm/entry.h> + +#ifdef __KERNEL__ + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. This + * also clears the TS-flag if the task we switched to has used the + * math co-processor latest. + */ +/* + * switch_to() saves the extra registers, that are not saved + * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and + * a0-a1. Some of these are used by schedule() and its predecessors + * and so we might get see unexpected behaviors when a task returns + * with unexpected register values. + * + * syscall stores these registers itself and none of them are used + * by syscall after the function in the syscall has been called. + * + * Beware that resume now expects *next to be in d1 and the offset of + * tss to be in a1. This saves a few instructions as we no longer have + * to push them onto the stack and read them back right after. + * + * 02/17/96 - Jes Sorensen (jds@kom.auc.dk) + * + * Changed 96/09/19 by Andreas Schwab + * pass prev in a0, next in a1 + */ +asmlinkage void resume(void); +#define switch_to(prev,next,last) do { \ + register void *_prev __asm__ ("a0") = (prev); \ + register void *_next __asm__ ("a1") = (next); \ + register void *_last __asm__ ("d1"); \ + __asm__ __volatile__("jbsr resume" \ + : "=a" (_prev), "=a" (_next), "=d" (_last) \ + : "0" (_prev), "1" (_next) \ + : "d0", "d2", "d3", "d4", "d5"); \ + (last) = _last; \ +} while (0) + + +/* + * Force strict CPU ordering. + * Not really required on m68k... + */ +#define nop() do { asm volatile ("nop"); barrier(); } while (0) +#define mb() barrier() +#define rmb() barrier() +#define wmb() barrier() +#define read_barrier_depends() ((void)0) +#define set_mb(var, value) ({ (var) = (value); wmb(); }) + +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() ((void)0) + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((volatile struct __xchg_dummy *)(x)) + +#ifndef CONFIG_RMW_INSNS +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + unsigned long flags, tmp; + + local_irq_save(flags); + + switch (size) { + case 1: + tmp = *(u8 *)ptr; + *(u8 *)ptr = x; + x = tmp; + break; + case 2: + tmp = *(u16 *)ptr; + *(u16 *)ptr = x; + x = tmp; + break; + case 4: + tmp = *(u32 *)ptr; + *(u32 *)ptr = x; + x = tmp; + break; + default: + BUG(); + } + + local_irq_restore(flags); + return x; +} #else -#include "system_mm.h" +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + switch (size) { + case 1: + __asm__ __volatile__ + ("moveb %2,%0\n\t" + "1:\n\t" + "casb %0,%1,%2\n\t" + "jne 1b" + : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 2: + __asm__ __volatile__ + ("movew %2,%0\n\t" + "1:\n\t" + "casw %0,%1,%2\n\t" + "jne 1b" + : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 4: + __asm__ __volatile__ + ("movel %2,%0\n\t" + "1:\n\t" + "casl %0,%1,%2\n\t" + "jne 1b" + : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + } + return x; +} #endif + +#include <asm-generic/cmpxchg-local.h> + +#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ +#ifdef CONFIG_RMW_INSNS +#define __HAVE_ARCH_CMPXCHG 1 + +static inline unsigned long __cmpxchg(volatile void *p, unsigned long old, + unsigned long new, int size) +{ + switch (size) { + case 1: + __asm__ __volatile__ ("casb %0,%2,%1" + : "=d" (old), "=m" (*(char *)p) + : "d" (new), "0" (old), "m" (*(char *)p)); + break; + case 2: + __asm__ __volatile__ ("casw %0,%2,%1" + : "=d" (old), "=m" (*(short *)p) + : "d" (new), "0" (old), "m" (*(short *)p)); + break; + case 4: + __asm__ __volatile__ ("casl %0,%2,%1" + : "=d" (old), "=m" (*(int *)p) + : "d" (new), "0" (old), "m" (*(int *)p)); + break; + } + return old; +} + +#define cmpxchg(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ + (unsigned long)(n), sizeof(*(ptr)))) +#define cmpxchg_local(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ + (unsigned long)(n), sizeof(*(ptr)))) +#else + +/* + * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make + * them available. + */ +#define cmpxchg_local(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ + (unsigned long)(n), sizeof(*(ptr)))) + +#include <asm-generic/cmpxchg.h> + +#endif + +#define arch_align_stack(x) (x) + +#endif /* __KERNEL__ */ + +#endif /* _M68K_SYSTEM_H */ diff --git a/arch/m68k/include/asm/system_mm.h b/arch/m68k/include/asm/system_mm.h deleted file mode 100644 index 47b01f4726bc..000000000000 --- a/arch/m68k/include/asm/system_mm.h +++ /dev/null @@ -1,193 +0,0 @@ -#ifndef _M68K_SYSTEM_H -#define _M68K_SYSTEM_H - -#include <linux/linkage.h> -#include <linux/kernel.h> -#include <linux/irqflags.h> -#include <asm/segment.h> -#include <asm/entry.h> - -#ifdef __KERNEL__ - -/* - * switch_to(n) should switch tasks to task ptr, first checking that - * ptr isn't the current task, in which case it does nothing. This - * also clears the TS-flag if the task we switched to has used the - * math co-processor latest. - */ -/* - * switch_to() saves the extra registers, that are not saved - * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and - * a0-a1. Some of these are used by schedule() and its predecessors - * and so we might get see unexpected behaviors when a task returns - * with unexpected register values. - * - * syscall stores these registers itself and none of them are used - * by syscall after the function in the syscall has been called. - * - * Beware that resume now expects *next to be in d1 and the offset of - * tss to be in a1. This saves a few instructions as we no longer have - * to push them onto the stack and read them back right after. - * - * 02/17/96 - Jes Sorensen (jds@kom.auc.dk) - * - * Changed 96/09/19 by Andreas Schwab - * pass prev in a0, next in a1 - */ -asmlinkage void resume(void); -#define switch_to(prev,next,last) do { \ - register void *_prev __asm__ ("a0") = (prev); \ - register void *_next __asm__ ("a1") = (next); \ - register void *_last __asm__ ("d1"); \ - __asm__ __volatile__("jbsr resume" \ - : "=a" (_prev), "=a" (_next), "=d" (_last) \ - : "0" (_prev), "1" (_next) \ - : "d0", "d2", "d3", "d4", "d5"); \ - (last) = _last; \ -} while (0) - - -/* - * Force strict CPU ordering. - * Not really required on m68k... - */ -#define nop() do { asm volatile ("nop"); barrier(); } while (0) -#define mb() barrier() -#define rmb() barrier() -#define wmb() barrier() -#define read_barrier_depends() ((void)0) -#define set_mb(var, value) ({ (var) = (value); wmb(); }) - -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() ((void)0) - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((volatile struct __xchg_dummy *)(x)) - -#ifndef CONFIG_RMW_INSNS -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - unsigned long flags, tmp; - - local_irq_save(flags); - - switch (size) { - case 1: - tmp = *(u8 *)ptr; - *(u8 *)ptr = x; - x = tmp; - break; - case 2: - tmp = *(u16 *)ptr; - *(u16 *)ptr = x; - x = tmp; - break; - case 4: - tmp = *(u32 *)ptr; - *(u32 *)ptr = x; - x = tmp; - break; - default: - BUG(); - } - - local_irq_restore(flags); - return x; -} -#else -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - switch (size) { - case 1: - __asm__ __volatile__ - ("moveb %2,%0\n\t" - "1:\n\t" - "casb %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 2: - __asm__ __volatile__ - ("movew %2,%0\n\t" - "1:\n\t" - "casw %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 4: - __asm__ __volatile__ - ("movel %2,%0\n\t" - "1:\n\t" - "casl %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - } - return x; -} -#endif - -#include <asm-generic/cmpxchg-local.h> - -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -/* - * Atomic compare and exchange. Compare OLD with MEM, if identical, - * store NEW in MEM. Return the initial value in MEM. Success is - * indicated by comparing RETURN with OLD. - */ -#ifdef CONFIG_RMW_INSNS -#define __HAVE_ARCH_CMPXCHG 1 - -static inline unsigned long __cmpxchg(volatile void *p, unsigned long old, - unsigned long new, int size) -{ - switch (size) { - case 1: - __asm__ __volatile__ ("casb %0,%2,%1" - : "=d" (old), "=m" (*(char *)p) - : "d" (new), "0" (old), "m" (*(char *)p)); - break; - case 2: - __asm__ __volatile__ ("casw %0,%2,%1" - : "=d" (old), "=m" (*(short *)p) - : "d" (new), "0" (old), "m" (*(short *)p)); - break; - case 4: - __asm__ __volatile__ ("casl %0,%2,%1" - : "=d" (old), "=m" (*(int *)p) - : "d" (new), "0" (old), "m" (*(int *)p)); - break; - } - return old; -} - -#define cmpxchg(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ - (unsigned long)(n), sizeof(*(ptr)))) -#else - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ - (unsigned long)(n), sizeof(*(ptr)))) - -#include <asm-generic/cmpxchg.h> - -#endif - -#define arch_align_stack(x) (x) - -#endif /* __KERNEL__ */ - -#endif /* _M68K_SYSTEM_H */ diff --git a/arch/m68k/include/asm/system_no.h b/arch/m68k/include/asm/system_no.h deleted file mode 100644 index 6fe9f93bc3ff..000000000000 --- a/arch/m68k/include/asm/system_no.h +++ /dev/null @@ -1,153 +0,0 @@ -#ifndef _M68KNOMMU_SYSTEM_H -#define _M68KNOMMU_SYSTEM_H - -#include <linux/linkage.h> -#include <linux/irqflags.h> -#include <asm/segment.h> -#include <asm/entry.h> - -/* - * switch_to(n) should switch tasks to task ptr, first checking that - * ptr isn't the current task, in which case it does nothing. This - * also clears the TS-flag if the task we switched to has used the - * math co-processor latest. - */ -/* - * switch_to() saves the extra registers, that are not saved - * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and - * a0-a1. Some of these are used by schedule() and its predecessors - * and so we might get see unexpected behaviors when a task returns - * with unexpected register values. - * - * syscall stores these registers itself and none of them are used - * by syscall after the function in the syscall has been called. - * - * Beware that resume now expects *next to be in d1 and the offset of - * tss to be in a1. This saves a few instructions as we no longer have - * to push them onto the stack and read them back right after. - * - * 02/17/96 - Jes Sorensen (jds@kom.auc.dk) - * - * Changed 96/09/19 by Andreas Schwab - * pass prev in a0, next in a1, offset of tss in d1, and whether - * the mm structures are shared in d2 (to avoid atc flushing). - */ -asmlinkage void resume(void); -#define switch_to(prev,next,last) \ -{ \ - void *_last; \ - __asm__ __volatile__( \ - "movel %1, %%a0\n\t" \ - "movel %2, %%a1\n\t" \ - "jbsr resume\n\t" \ - "movel %%d1, %0\n\t" \ - : "=d" (_last) \ - : "d" (prev), "d" (next) \ - : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \ - (last) = _last; \ -} - -#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc") - -/* - * Force strict CPU ordering. - * Not really required on m68k... - */ -#define nop() asm volatile ("nop"::) -#define mb() asm volatile ("" : : :"memory") -#define rmb() asm volatile ("" : : :"memory") -#define wmb() asm volatile ("" : : :"memory") -#define set_mb(var, value) ({ (var) = (value); wmb(); }) - -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) - -#define read_barrier_depends() ((void)0) - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((volatile struct __xchg_dummy *)(x)) - -#ifndef CONFIG_RMW_INSNS -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - unsigned long tmp, flags; - - local_irq_save(flags); - - switch (size) { - case 1: - __asm__ __volatile__ - ("moveb %2,%0\n\t" - "moveb %1,%2" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 2: - __asm__ __volatile__ - ("movew %2,%0\n\t" - "movew %1,%2" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 4: - __asm__ __volatile__ - ("movel %2,%0\n\t" - "movel %1,%2" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - } - local_irq_restore(flags); - return tmp; -} -#else -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - switch (size) { - case 1: - __asm__ __volatile__ - ("moveb %2,%0\n\t" - "1:\n\t" - "casb %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 2: - __asm__ __volatile__ - ("movew %2,%0\n\t" - "1:\n\t" - "casw %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 4: - __asm__ __volatile__ - ("movel %2,%0\n\t" - "1:\n\t" - "casl %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - } - return x; -} -#endif - -#include <asm-generic/cmpxchg-local.h> - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#include <asm-generic/cmpxchg.h> - -#define arch_align_stack(x) (x) - - -#endif /* _M68KNOMMU_SYSTEM_H */ diff --git a/arch/m68k/kernel/m68k_ksyms.c b/arch/m68k/kernel/m68k_ksyms.c index 33f82769547c..1b7a14d1a000 100644 --- a/arch/m68k/kernel/m68k_ksyms.c +++ b/arch/m68k/kernel/m68k_ksyms.c @@ -14,8 +14,7 @@ EXPORT_SYMBOL(__ashrdi3); EXPORT_SYMBOL(__lshrdi3); EXPORT_SYMBOL(__muldi3); -#if !defined(__mc68020__) && !defined(__mc68030__) && \ - !defined(__mc68040__) && !defined(__mc68060__) && !defined(__mcpu32__) +#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE) /* * Simpler 68k and ColdFire parts also need a few other gcc functions. */ diff --git a/arch/m68k/kernel/module.c b/arch/m68k/kernel/module.c index 7ea203ce6b1a..146d646980ad 100644 --- a/arch/m68k/kernel/module.c +++ b/arch/m68k/kernel/module.c @@ -1,5 +1,156 @@ -#ifdef CONFIG_MMU -#include "module_mm.c" +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include <linux/moduleloader.h> +#include <linux/elf.h> +#include <linux/vmalloc.h> +#include <linux/fs.h> +#include <linux/string.h> +#include <linux/kernel.h> + +#if 0 +#define DEBUGP printk #else -#include "module_no.c" +#define DEBUGP(fmt...) +#endif + +#ifdef CONFIG_MODULES + +void *module_alloc(unsigned long size) +{ + if (size == 0) + return NULL; + return vmalloc(size); +} + + +/* Free memory returned from module_alloc */ +void module_free(struct module *mod, void *module_region) +{ + vfree(module_region); +} + +/* We don't need anything special. */ +int module_frob_arch_sections(Elf_Ehdr *hdr, + Elf_Shdr *sechdrs, + char *secstrings, + struct module *mod) +{ + return 0; +} + +int apply_relocate(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + unsigned int i; + Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr; + Elf32_Sym *sym; + uint32_t *location; + + DEBUGP("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to. Note that all + undefined symbols have been resolved. */ + sym = (Elf32_Sym *)sechdrs[symindex].sh_addr + + ELF32_R_SYM(rel[i].r_info); + + switch (ELF32_R_TYPE(rel[i].r_info)) { + case R_68K_32: + /* We add the value into the location given */ + *location += sym->st_value; + break; + case R_68K_PC32: + /* Add the value, subtract its postition */ + *location += sym->st_value - (uint32_t)location; + break; + default: + printk(KERN_ERR "module %s: Unknown relocation: %u\n", + me->name, ELF32_R_TYPE(rel[i].r_info)); + return -ENOEXEC; + } + } + return 0; +} + +int apply_relocate_add(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + unsigned int i; + Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; + Elf32_Sym *sym; + uint32_t *location; + + DEBUGP("Applying relocate_add section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[i].r_offset; + /* This is the symbol it is referring to. Note that all + undefined symbols have been resolved. */ + sym = (Elf32_Sym *)sechdrs[symindex].sh_addr + + ELF32_R_SYM(rel[i].r_info); + + switch (ELF32_R_TYPE(rel[i].r_info)) { + case R_68K_32: + /* We add the value into the location given */ + *location = rel[i].r_addend + sym->st_value; + break; + case R_68K_PC32: + /* Add the value, subtract its postition */ + *location = rel[i].r_addend + sym->st_value - (uint32_t)location; + break; + default: + printk(KERN_ERR "module %s: Unknown relocation: %u\n", + me->name, ELF32_R_TYPE(rel[i].r_info)); + return -ENOEXEC; + } + } + return 0; +} + +int module_finalize(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + struct module *mod) +{ + module_fixup(mod, mod->arch.fixup_start, mod->arch.fixup_end); + return 0; +} + +void module_arch_cleanup(struct module *mod) +{ +} + +#endif /* CONFIG_MODULES */ + +void module_fixup(struct module *mod, struct m68k_fixup_info *start, + struct m68k_fixup_info *end) +{ +#ifdef CONFIG_MMU + struct m68k_fixup_info *fixup; + + for (fixup = start; fixup < end; fixup++) { + switch (fixup->type) { + case m68k_fixup_memoffset: + *(u32 *)fixup->addr = m68k_memoffset; + break; + case m68k_fixup_vnode_shift: + *(u16 *)fixup->addr += m68k_virt_to_node_shift; + break; + } + } #endif +} diff --git a/arch/m68k/kernel/module_mm.c b/arch/m68k/kernel/module_mm.c deleted file mode 100644 index cd6bcb1c957e..000000000000 --- a/arch/m68k/kernel/module_mm.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include <linux/moduleloader.h> -#include <linux/elf.h> -#include <linux/vmalloc.h> -#include <linux/fs.h> -#include <linux/string.h> -#include <linux/kernel.h> - -#if 0 -#define DEBUGP printk -#else -#define DEBUGP(fmt...) -#endif - -#ifdef CONFIG_MODULES - -void *module_alloc(unsigned long size) -{ - if (size == 0) - return NULL; - return vmalloc(size); -} - - -/* Free memory returned from module_alloc */ -void module_free(struct module *mod, void *module_region) -{ - vfree(module_region); -} - -/* We don't need anything special. */ -int module_frob_arch_sections(Elf_Ehdr *hdr, - Elf_Shdr *sechdrs, - char *secstrings, - struct module *mod) -{ - return 0; -} - -int apply_relocate(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - - DEBUGP("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_68K_32: - /* We add the value into the location given */ - *location += sym->st_value; - break; - case R_68K_PC32: - /* Add the value, subtract its postition */ - *location += sym->st_value - (uint32_t)location; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - return 0; -} - -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - - DEBUGP("Applying relocate_add section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_68K_32: - /* We add the value into the location given */ - *location = rel[i].r_addend + sym->st_value; - break; - case R_68K_PC32: - /* Add the value, subtract its postition */ - *location = rel[i].r_addend + sym->st_value - (uint32_t)location; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - return 0; -} - -int module_finalize(const Elf_Ehdr *hdr, - const Elf_Shdr *sechdrs, - struct module *mod) -{ - module_fixup(mod, mod->arch.fixup_start, mod->arch.fixup_end); - - return 0; -} - -void module_arch_cleanup(struct module *mod) -{ -} - -#endif /* CONFIG_MODULES */ - -void module_fixup(struct module *mod, struct m68k_fixup_info *start, - struct m68k_fixup_info *end) -{ - struct m68k_fixup_info *fixup; - - for (fixup = start; fixup < end; fixup++) { - switch (fixup->type) { - case m68k_fixup_memoffset: - *(u32 *)fixup->addr = m68k_memoffset; - break; - case m68k_fixup_vnode_shift: - *(u16 *)fixup->addr += m68k_virt_to_node_shift; - break; - } - } -} diff --git a/arch/m68k/kernel/module_no.c b/arch/m68k/kernel/module_no.c deleted file mode 100644 index d11ffae7956a..000000000000 --- a/arch/m68k/kernel/module_no.c +++ /dev/null @@ -1,126 +0,0 @@ -#include <linux/moduleloader.h> -#include <linux/elf.h> -#include <linux/vmalloc.h> -#include <linux/fs.h> -#include <linux/string.h> -#include <linux/kernel.h> - -#if 0 -#define DEBUGP printk -#else -#define DEBUGP(fmt...) -#endif - -void *module_alloc(unsigned long size) -{ - if (size == 0) - return NULL; - return vmalloc(size); -} - - -/* Free memory returned from module_alloc */ -void module_free(struct module *mod, void *module_region) -{ - vfree(module_region); -} - -/* We don't need anything special. */ -int module_frob_arch_sections(Elf_Ehdr *hdr, - Elf_Shdr *sechdrs, - char *secstrings, - struct module *mod) -{ - return 0; -} - -int apply_relocate(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - - DEBUGP("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_68K_32: - /* We add the value into the location given */ - *location += sym->st_value; - break; - case R_68K_PC32: - /* Add the value, subtract its postition */ - *location += sym->st_value - (uint32_t)location; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - return 0; -} - -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - - DEBUGP("Applying relocate_add section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_68K_32: - /* We add the value into the location given */ - *location = rel[i].r_addend + sym->st_value; - break; - case R_68K_PC32: - /* Add the value, subtract its postition */ - *location = rel[i].r_addend + sym->st_value - (uint32_t)location; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - return 0; -} - -int module_finalize(const Elf_Ehdr *hdr, - const Elf_Shdr *sechdrs, - struct module *me) -{ - return 0; -} - -void module_arch_cleanup(struct module *mod) -{ -} diff --git a/arch/m68k/kernel/vmlinux.lds_no.S b/arch/m68k/kernel/vmlinux.lds_no.S index f4d715cdca0e..7dc4087a9545 100644 --- a/arch/m68k/kernel/vmlinux.lds_no.S +++ b/arch/m68k/kernel/vmlinux.lds_no.S @@ -84,52 +84,52 @@ SECTIONS { /* Kernel symbol table: Normal symbols */ . = ALIGN(4); __start___ksymtab = .; - *(__ksymtab) + *(SORT(___ksymtab+*)) __stop___ksymtab = .; /* Kernel symbol table: GPL-only symbols */ __start___ksymtab_gpl = .; - *(__ksymtab_gpl) + *(SORT(___ksymtab_gpl+*)) __stop___ksymtab_gpl = .; /* Kernel symbol table: Normal unused symbols */ __start___ksymtab_unused = .; - *(__ksymtab_unused) + *(SORT(___ksymtab_unused+*)) __stop___ksymtab_unused = .; /* Kernel symbol table: GPL-only unused symbols */ __start___ksymtab_unused_gpl = .; - *(__ksymtab_unused_gpl) + *(SORT(___ksymtab_unused_gpl+*)) __stop___ksymtab_unused_gpl = .; /* Kernel symbol table: GPL-future symbols */ __start___ksymtab_gpl_future = .; - *(__ksymtab_gpl_future) + *(SORT(___ksymtab_gpl_future+*)) __stop___ksymtab_gpl_future = .; /* Kernel symbol table: Normal symbols */ __start___kcrctab = .; - *(__kcrctab) + *(SORT(___kcrctab+*)) __stop___kcrctab = .; /* Kernel symbol table: GPL-only symbols */ __start___kcrctab_gpl = .; - *(__kcrctab_gpl) + *(SORT(___kcrctab_gpl+*)) __stop___kcrctab_gpl = .; /* Kernel symbol table: Normal unused symbols */ __start___kcrctab_unused = .; - *(__kcrctab_unused) + *(SORT(___kcrctab_unused+*)) __stop___kcrctab_unused = .; /* Kernel symbol table: GPL-only unused symbols */ __start___kcrctab_unused_gpl = .; - *(__kcrctab_unused_gpl) + *(SORT(___kcrctab_unused_gpl+*)) __stop___kcrctab_unused_gpl = .; /* Kernel symbol table: GPL-future symbols */ __start___kcrctab_gpl_future = .; - *(__kcrctab_gpl_future) + *(SORT(___kcrctab_gpl_future+*)) __stop___kcrctab_gpl_future = .; /* Kernel symbol table: strings */ diff --git a/arch/m68k/lib/memcpy.c b/arch/m68k/lib/memcpy.c index 62182c81e91c..064889316974 100644 --- a/arch/m68k/lib/memcpy.c +++ b/arch/m68k/lib/memcpy.c @@ -34,8 +34,10 @@ void *memcpy(void *to, const void *from, size_t n) if (temp) { long *lto = to; const long *lfrom = from; -#if defined(__mc68020__) || defined(__mc68030__) || \ - defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__) +#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE) + for (; temp; temp--) + *lto++ = *lfrom++; +#else asm volatile ( " movel %2,%3\n" " andw #7,%3\n" @@ -56,9 +58,6 @@ void *memcpy(void *to, const void *from, size_t n) " jpl 4b" : "=a" (lfrom), "=a" (lto), "=d" (temp), "=&d" (temp1) : "0" (lfrom), "1" (lto), "2" (temp)); -#else - for (; temp; temp--) - *lto++ = *lfrom++; #endif to = lto; from = lfrom; diff --git a/arch/m68k/lib/memset.c b/arch/m68k/lib/memset.c index f649e6a2e644..8a7639f0a2fe 100644 --- a/arch/m68k/lib/memset.c +++ b/arch/m68k/lib/memset.c @@ -32,8 +32,10 @@ void *memset(void *s, int c, size_t count) temp = count >> 2; if (temp) { long *ls = s; -#if defined(__mc68020__) || defined(__mc68030__) || \ - defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__) +#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE) + for (; temp; temp--) + *ls++ = c; +#else size_t temp1; asm volatile ( " movel %1,%2\n" @@ -55,9 +57,6 @@ void *memset(void *s, int c, size_t count) " jpl 1b" : "=a" (ls), "=d" (temp), "=&d" (temp1) : "d" (c), "0" (ls), "1" (temp)); -#else - for (; temp; temp--) - *ls++ = c; #endif s = ls; } diff --git a/arch/m68k/lib/muldi3.c b/arch/m68k/lib/muldi3.c index 079bafca073e..79e928a525d0 100644 --- a/arch/m68k/lib/muldi3.c +++ b/arch/m68k/lib/muldi3.c @@ -19,17 +19,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#if defined(__mc68020__) || defined(__mc68030__) || \ - defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__) - -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("mulu%.l %3,%1:%0" \ - : "=d" ((USItype)(w0)), \ - "=d" ((USItype)(w1)) \ - : "%0" ((USItype)(u)), \ - "dmi" ((USItype)(v))) - -#else +#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE) #define SI_TYPE_SIZE 32 #define __BITS4 (SI_TYPE_SIZE / 4) @@ -61,6 +51,15 @@ Boston, MA 02111-1307, USA. */ (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ } while (0) +#else + +#define umul_ppmm(w1, w0, u, v) \ + __asm__ ("mulu%.l %3,%1:%0" \ + : "=d" ((USItype)(w0)), \ + "=d" ((USItype)(w1)) \ + : "%0" ((USItype)(u)), \ + "dmi" ((USItype)(v))) + #endif #define __umulsidi3(u, v) \ diff --git a/arch/m68k/platform/5206/config.c b/arch/m68k/platform/5206/config.c index 9c335465e66d..6fa3f800277a 100644 --- a/arch/m68k/platform/5206/config.c +++ b/arch/m68k/platform/5206/config.c @@ -98,6 +98,12 @@ void m5206_cpu_reset(void) void __init config_BSP(char *commandp, int size) { +#if defined(CONFIG_NETtel) + /* Copy command line from FLASH to local buffer... */ + memcpy(commandp, (char *) 0xf0004000, size); + commandp[size-1] = 0; +#endif /* CONFIG_NETtel */ + mach_reset = m5206_cpu_reset; m5206_timers_init(); m5206_uarts_init(); diff --git a/arch/m68k/platform/5206e/Makefile b/arch/m68k/platform/5206e/Makefile deleted file mode 100644 index b5db05625cfa..000000000000 --- a/arch/m68k/platform/5206e/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o gpio.o - diff --git a/arch/m68k/platform/5206e/config.c b/arch/m68k/platform/5206e/config.c deleted file mode 100644 index 942397984c66..000000000000 --- a/arch/m68k/platform/5206e/config.c +++ /dev/null @@ -1,127 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/5206e/config.c - * - * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/init.h> -#include <linux/io.h> -#include <asm/machdep.h> -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfuart.h> -#include <asm/mcfdma.h> - -/***************************************************************************/ - -static struct mcf_platform_uart m5206e_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 73, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 74, - }, - { }, -}; - -static struct platform_device m5206e_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m5206e_uart_platform, -}; - -static struct platform_device *m5206e_devices[] __initdata = { - &m5206e_uart, -}; - -/***************************************************************************/ - -static void __init m5206e_uart_init_line(int line, int irq) -{ - if (line == 0) { - writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); - writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART0); - } else if (line == 1) { - writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); - writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); - mcf_mapirq2imr(irq, MCFINTC_UART1); - } -} - -static void __init m5206e_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m5206e_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m5206e_uart_init_line(line, m5206e_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void __init m5206e_timers_init(void) -{ - /* Timer1 is always used as system timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER1ICR); - mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); - -#ifdef CONFIG_HIGHPROFILE - /* Timer2 is to be used as a high speed profile timer */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, - MCF_MBAR + MCFSIM_TIMER2ICR); - mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); -#endif -} - -/***************************************************************************/ - -void m5206e_cpu_reset(void) -{ - local_irq_disable(); - /* Set watchdog to soft reset, and enabled */ - __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); - for (;;) - /* wait for watchdog to timeout */; -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ -#if defined(CONFIG_NETtel) - /* Copy command line from FLASH to local buffer... */ - memcpy(commandp, (char *) 0xf0004000, size); - commandp[size-1] = 0; -#endif /* CONFIG_NETtel */ - - mach_reset = m5206e_cpu_reset; - m5206e_timers_init(); - m5206e_uarts_init(); - - /* Only support the external interrupts on their primary level */ - mcf_mapirq2imr(25, MCFINTC_EINT1); - mcf_mapirq2imr(28, MCFINTC_EINT4); - mcf_mapirq2imr(31, MCFINTC_EINT7); -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68k/platform/5206e/gpio.c b/arch/m68k/platform/5206e/gpio.c deleted file mode 100644 index b9ab4a120f28..000000000000 --- a/arch/m68k/platform/5206e/gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Coldfire generic GPIO support - * - * (C) Copyright 2009, Steven King <sfking@fdwdc.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/coldfire.h> -#include <asm/mcfsim.h> -#include <asm/mcfgpio.h> - -static struct mcf_gpio_chip mcf_gpio_chips[] = { - { - .gpio_chip = { - .label = "PP", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value, - .ngpio = 8, - }, - .pddr = (void __iomem *) MCFSIM_PADDR, - .podr = (void __iomem *) MCFSIM_PADAT, - .ppdr = (void __iomem *) MCFSIM_PADAT, - }, -}; - -static int __init mcf_gpio_init(void) -{ - unsigned i = 0; - while (i < ARRAY_SIZE(mcf_gpio_chips)) - (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); - return 0; -} - -core_initcall(mcf_gpio_init); diff --git a/arch/m68k/platform/68328/entry.S b/arch/m68k/platform/68328/entry.S index f68dce766c0a..4ed7a65d5aa0 100644 --- a/arch/m68k/platform/68328/entry.S +++ b/arch/m68k/platform/68328/entry.S @@ -241,22 +241,21 @@ ENTRY(bad_interrupt) /* * Beware - when entering resume, prev (the current task) is - * in a0, next (the new task) is in a1,so don't change these + * in a0, next (the new task) is in a1, so don't change these * registers until their contents are no longer needed. */ ENTRY(resume) movel %a0,%d1 /* save prev thread in d1 */ movew %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */ - movel %usp,%a2 /* save usp */ - movel %a2,%a0@(TASK_THREAD+THREAD_USP) - SAVE_SWITCH_STACK movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */ + movel %usp,%a3 /* save usp */ + movel %a3,%a0@(TASK_THREAD+THREAD_USP) + + movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore user stack */ + movel %a3,%usp movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */ RESTORE_SWITCH_STACK - - movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore user stack */ - movel %a0,%usp movew %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */ rts diff --git a/arch/m68k/platform/68360/entry.S b/arch/m68k/platform/68360/entry.S index a07b14feed92..0ede6702127a 100644 --- a/arch/m68k/platform/68360/entry.S +++ b/arch/m68k/platform/68360/entry.S @@ -162,22 +162,21 @@ bad_interrupt: /* * Beware - when entering resume, prev (the current task) is - * in a0, next (the new task) is in a1,so don't change these + * in a0, next (the new task) is in a1, so don't change these * registers until their contents are no longer needed. */ ENTRY(resume) movel %a0,%d1 /* save prev thread in d1 */ movew %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */ - movel %usp,%a2 /* save usp */ - movel %a2,%a0@(TASK_THREAD+THREAD_USP) - SAVE_SWITCH_STACK movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */ + movel %usp,%a3 /* save usp */ + movel %a3,%a0@(TASK_THREAD+THREAD_USP) + + movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore user stack */ + movel %a3,%usp movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */ RESTORE_SWITCH_STACK - - movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore user stack */ - movel %a0,%usp movew %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */ rts diff --git a/arch/m68k/platform/coldfire/entry.S b/arch/m68k/platform/coldfire/entry.S index 27c2b001161e..bd27242c2f43 100644 --- a/arch/m68k/platform/coldfire/entry.S +++ b/arch/m68k/platform/coldfire/entry.S @@ -182,21 +182,23 @@ ENTRY(inthandler) /* * Beware - when entering resume, prev (the current task) is - * in a0, next (the new task) is in a1,so don't change these + * in a0, next (the new task) is in a1, so don't change these * registers until their contents are no longer needed. - * This is always called in supervisor mode, so don't bother to save - * and restore sr; user's process sr is actually in the stack. */ ENTRY(resume) - movel %a0, %d1 /* get prev thread in d1 */ - RDUSP - movel %a2,%a0@(TASK_THREAD+THREAD_USP) - + movew %sr,%d1 /* save current status */ + movew %d1,%a0@(TASK_THREAD+THREAD_SR) + movel %a0,%d1 /* get prev thread in d1 */ SAVE_SWITCH_STACK movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */ - movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */ + RDUSP /* movel %usp,%a3 */ + movel %a3,%a0@(TASK_THREAD+THREAD_USP) /* save thread user stack */ + + movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore thread user stack */ + WRUSP /* movel %a3,%usp */ + movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new kernel stack */ + movew %a1@(TASK_THREAD+THREAD_SR),%d7 /* restore new status */ + movew %d7,%sr RESTORE_SWITCH_STACK - - movel %a1@(TASK_THREAD+THREAD_USP),%a0 /* restore thread user stack */ - WRUSP rts + diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 37862b2ce363..807c97eed8a8 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -678,7 +678,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_TEST=m CONFIG_RTC_DRV_DS1307=m diff --git a/arch/powerpc/configs/52xx/pcm030_defconfig b/arch/powerpc/configs/52xx/pcm030_defconfig index 7f7e4a878602..22e719575c60 100644 --- a/arch/powerpc/configs/52xx/pcm030_defconfig +++ b/arch/powerpc/configs/52xx/pcm030_defconfig @@ -85,7 +85,7 @@ CONFIG_USB_OHCI_HCD=m CONFIG_USB_OHCI_HCD_PPC_OF_BE=y # CONFIG_USB_OHCI_HCD_PCI is not set CONFIG_USB_STORAGE=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PCF8563=m CONFIG_EXT2_FS=m CONFIG_EXT3_FS=m diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig index 6472322bf13b..185c292b0f1c 100644 --- a/arch/powerpc/configs/ps3_defconfig +++ b/arch/powerpc/configs/ps3_defconfig @@ -141,7 +141,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y # CONFIG_USB_EHCI_HCD_PPC_OF is not set CONFIG_USB_OHCI_HCD=m CONFIG_USB_STORAGE=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PS3=m CONFIG_EXT2_FS=m CONFIG_EXT3_FS=m diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index 3a32741cc0ac..513cb1a2e6c8 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -20,6 +20,7 @@ #include <linux/io.h> #include <linux/delay.h> #include <linux/usb/r8a66597.h> +#include <linux/usb/renesas_usbhs.h> #include <linux/i2c.h> #include <linux/i2c/tsc2007.h> #include <linux/spi/spi.h> @@ -232,6 +233,52 @@ static struct platform_device usb1_common_device = { .resource = usb1_common_resources, }; +/* + * USBHS + */ +static int usbhs_get_id(struct platform_device *pdev) +{ + return gpio_get_value(GPIO_PTB3); +} + +static struct renesas_usbhs_platform_info usbhs_info = { + .platform_callback = { + .get_id = usbhs_get_id, + }, + .driver_param = { + .buswait_bwait = 4, + .detection_delay = 5, + }, +}; + +static struct resource usbhs_resources[] = { + [0] = { + .start = 0xa4d90000, + .end = 0xa4d90124 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 66, + .end = 66, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usbhs_device = { + .name = "renesas_usbhs", + .id = 1, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usbhs_info, + }, + .num_resources = ARRAY_SIZE(usbhs_resources), + .resource = usbhs_resources, + .archdata = { + .hwblk_id = HWBLK_USB1, + }, +}; + /* LCDC */ const static struct fb_videomode ecovec_lcd_modes[] = { { @@ -897,6 +944,7 @@ static struct platform_device *ecovec_devices[] __initdata = { &sh_eth_device, &usb0_host_device, &usb1_common_device, + &usbhs_device, &lcdc_device, &ceu0_device, &ceu1_device, diff --git a/arch/sh/boot/compressed/Makefile b/arch/sh/boot/compressed/Makefile index 780e083e4d17..23bc849d9c64 100644 --- a/arch/sh/boot/compressed/Makefile +++ b/arch/sh/boot/compressed/Makefile @@ -27,8 +27,6 @@ IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \ $(CONFIG_BOOT_LINK_OFFSET)]') endif -LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) - ifeq ($(CONFIG_MCOUNT),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) @@ -37,7 +35,25 @@ endif LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(IMAGE_OFFSET) -e startup \ -T $(obj)/../../kernel/vmlinux.lds -$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(LIBGCC) FORCE +# +# Pull in the necessary libgcc bits from the in-kernel implementation. +# +lib1funcs-$(CONFIG_SUPERH32) := ashiftrt.S ashldi3.c ashrsi3.S ashlsi3.S \ + lshrsi3.S +lib1funcs-obj := \ + $(addsuffix .o, $(basename $(addprefix $(obj)/, $(lib1funcs-y)))) + +lib1funcs-dir := $(srctree)/arch/$(SRCARCH)/lib +ifeq ($(BITS),64) + lib1funcs-dir := $(addsuffix $(BITS), $(lib1funcs-dir)) +endif + +KBUILD_CFLAGS += -I$(lib1funcs-dir) + +$(addprefix $(obj)/,$(lib1funcs-y)): $(obj)/%: $(lib1funcs-dir)/% FORCE + $(call cmd,shipped) + +$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(lib1funcs-obj) FORCE $(call if_changed,ld) @: diff --git a/arch/sh/configs/titan_defconfig b/arch/sh/configs/titan_defconfig index 0f558914e760..e2cbd92d520b 100644 --- a/arch/sh/configs/titan_defconfig +++ b/arch/sh/configs/titan_defconfig @@ -227,7 +227,7 @@ CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_ARK3116=m CONFIG_USB_SERIAL_PL2303=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_SH=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y diff --git a/arch/sh/include/asm/cmpxchg-grb.h b/arch/sh/include/asm/cmpxchg-grb.h index 4676bf57693a..f848dec9e483 100644 --- a/arch/sh/include/asm/cmpxchg-grb.h +++ b/arch/sh/include/asm/cmpxchg-grb.h @@ -15,8 +15,9 @@ static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) " mov.l %2, @%1 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (retval), - "+r" (m) - : "r" (val) + "+r" (m), + "+r" (val) /* inhibit r15 overloading */ + : : "memory", "r0", "r1"); return retval; @@ -36,8 +37,9 @@ static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) " mov.b %2, @%1 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ : "=&r" (retval), - "+r" (m) - : "r" (val) + "+r" (m), + "+r" (val) /* inhibit r15 overloading */ + : : "memory" , "r0", "r1"); return retval; @@ -54,13 +56,14 @@ static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old, " nop \n\t" " mov r15, r1 \n\t" /* r1 = saved sp */ " mov #-8, r15 \n\t" /* LOGIN */ - " mov.l @%1, %0 \n\t" /* load old value */ - " cmp/eq %0, %2 \n\t" + " mov.l @%3, %0 \n\t" /* load old value */ + " cmp/eq %0, %1 \n\t" " bf 1f \n\t" /* if not equal */ - " mov.l %3, @%1 \n\t" /* store new value */ + " mov.l %2, @%3 \n\t" /* store new value */ "1: mov r1, r15 \n\t" /* LOGOUT */ - : "=&r" (retval) - : "r" (m), "r" (old), "r" (new) + : "=&r" (retval), + "+r" (old), "+r" (new) /* old or new can be r15 */ + : "r" (m) : "memory" , "r0", "r1", "t"); return retval; diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h index 2a541ddb5a1b..e25c4c7d6b63 100644 --- a/arch/sh/include/asm/processor_64.h +++ b/arch/sh/include/asm/processor_64.h @@ -150,7 +150,6 @@ struct thread_struct { #define SR_USER (SR_MMU | SR_FD) #define start_thread(_regs, new_pc, new_sp) \ - set_fs(USER_DS); \ _regs->sr = SR_USER; /* User mode. */ \ _regs->pc = new_pc - 4; /* Compensate syscall exit */ \ _regs->pc |= 1; /* Set SHmedia ! */ \ diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h index 3daef8ecbc63..cbc47e6bcab5 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7724.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h @@ -298,6 +298,14 @@ enum { SHDMA_SLAVE_SCIF4_RX, SHDMA_SLAVE_SCIF5_TX, SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_USB0D0_TX, + SHDMA_SLAVE_USB0D0_RX, + SHDMA_SLAVE_USB0D1_TX, + SHDMA_SLAVE_USB0D1_RX, + SHDMA_SLAVE_USB1D0_TX, + SHDMA_SLAVE_USB1D0_RX, + SHDMA_SLAVE_USB1D1_TX, + SHDMA_SLAVE_USB1D1_RX, SHDMA_SLAVE_SDHI0_TX, SHDMA_SLAVE_SDHI0_RX, SHDMA_SLAVE_SDHI1_TX, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 0333fe9e3881..134a397b1918 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -93,6 +93,46 @@ static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = { .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), .mid_rid = 0x36, }, { + .slave_id = SHDMA_SLAVE_USB0D0_TX, + .addr = 0xA4D80100, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0x73, + }, { + .slave_id = SHDMA_SLAVE_USB0D0_RX, + .addr = 0xA4D80100, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0x73, + }, { + .slave_id = SHDMA_SLAVE_USB0D1_TX, + .addr = 0xA4D80120, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0x77, + }, { + .slave_id = SHDMA_SLAVE_USB0D1_RX, + .addr = 0xA4D80120, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0x77, + }, { + .slave_id = SHDMA_SLAVE_USB1D0_TX, + .addr = 0xA4D90100, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xab, + }, { + .slave_id = SHDMA_SLAVE_USB1D0_RX, + .addr = 0xA4D90100, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xab, + }, { + .slave_id = SHDMA_SLAVE_USB1D1_TX, + .addr = 0xA4D90120, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xaf, + }, { + .slave_id = SHDMA_SLAVE_USB1D1_RX, + .addr = 0xA4D90120, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), + .mid_rid = 0xaf, + }, { .slave_id = SHDMA_SLAVE_SDHI0_TX, .addr = 0x04ce0030, .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c index b473f0c06fbc..aaf6d59c2012 100644 --- a/arch/sh/kernel/process_32.c +++ b/arch/sh/kernel/process_32.c @@ -102,8 +102,6 @@ EXPORT_SYMBOL(kernel_thread); void start_thread(struct pt_regs *regs, unsigned long new_pc, unsigned long new_sp) { - set_fs(USER_DS); - regs->pr = 0; regs->sr = SR_FD; regs->pc = new_pc; diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c index 52411462c409..115725198038 100644 --- a/arch/sh/mm/cache-debugfs.c +++ b/arch/sh/mm/cache-debugfs.c @@ -26,9 +26,9 @@ static int cache_seq_show(struct seq_file *file, void *iter) { unsigned int cache_type = (unsigned int)file->private; struct cache_info *cache; - unsigned int waysize, way, cache_size; - unsigned long ccr, base; - static unsigned long addrstart = 0; + unsigned int waysize, way; + unsigned long ccr; + unsigned long addrstart = 0; /* * Go uncached immediately so we don't skew the results any @@ -45,28 +45,13 @@ static int cache_seq_show(struct seq_file *file, void *iter) } if (cache_type == CACHE_TYPE_DCACHE) { - base = CACHE_OC_ADDRESS_ARRAY; + addrstart = CACHE_OC_ADDRESS_ARRAY; cache = ¤t_cpu_data.dcache; } else { - base = CACHE_IC_ADDRESS_ARRAY; + addrstart = CACHE_IC_ADDRESS_ARRAY; cache = ¤t_cpu_data.icache; } - /* - * Due to the amount of data written out (depending on the cache size), - * we may be iterated over multiple times. In this case, keep track of - * the entry position in addrstart, and rewind it when we've hit the - * end of the cache. - * - * Likewise, the same code is used for multiple caches, so care must - * be taken for bouncing addrstart back and forth so the appropriate - * cache is hit. - */ - cache_size = cache->ways * cache->sets * cache->linesz; - if (((addrstart & 0xff000000) != base) || - (addrstart & 0x00ffffff) > cache_size) - addrstart = base; - waysize = cache->sets; /* diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c index 1c9c80a1a86a..92700c1650c7 100644 --- a/arch/sparc/kernel/ioport.c +++ b/arch/sparc/kernel/ioport.c @@ -65,9 +65,6 @@ static inline void dma_make_coherent(unsigned long pa, unsigned long len) } #endif -static struct resource *_sparc_find_resource(struct resource *r, - unsigned long); - static void __iomem *_sparc_ioremap(struct resource *res, u32 bus, u32 pa, int sz); static void __iomem *_sparc_alloc_io(unsigned int busno, unsigned long phys, unsigned long size, char *name); @@ -143,7 +140,11 @@ void iounmap(volatile void __iomem *virtual) unsigned long vaddr = (unsigned long) virtual & PAGE_MASK; struct resource *res; - if ((res = _sparc_find_resource(&sparc_iomap, vaddr)) == NULL) { + /* + * XXX Too slow. Can have 8192 DVMA pages on sun4m in the worst case. + * This probably warrants some sort of hashing. + */ + if ((res = lookup_resource(&sparc_iomap, vaddr)) == NULL) { printk("free_io/iounmap: cannot free %lx\n", vaddr); return; } @@ -319,7 +320,7 @@ static void sbus_free_coherent(struct device *dev, size_t n, void *p, struct resource *res; struct page *pgv; - if ((res = _sparc_find_resource(&_sparc_dvma, + if ((res = lookup_resource(&_sparc_dvma, (unsigned long)p)) == NULL) { printk("sbus_free_consistent: cannot free %p\n", p); return; @@ -492,7 +493,7 @@ static void pci32_free_coherent(struct device *dev, size_t n, void *p, { struct resource *res; - if ((res = _sparc_find_resource(&_sparc_dvma, + if ((res = lookup_resource(&_sparc_dvma, (unsigned long)p)) == NULL) { printk("pci_free_consistent: cannot free %p\n", p); return; @@ -715,25 +716,6 @@ static const struct file_operations sparc_io_proc_fops = { }; #endif /* CONFIG_PROC_FS */ -/* - * This is a version of find_resource and it belongs to kernel/resource.c. - * Until we have agreement with Linus and Martin, it lingers here. - * - * XXX Too slow. Can have 8192 DVMA pages on sun4m in the worst case. - * This probably warrants some sort of hashing. - */ -static struct resource *_sparc_find_resource(struct resource *root, - unsigned long hit) -{ - struct resource *tmp; - - for (tmp = root->child; tmp != 0; tmp = tmp->sibling) { - if (tmp->start <= hit && tmp->end >= hit) - return tmp; - } - return NULL; -} - static void register_proc_sparc_ioport(void) { #ifdef CONFIG_PROC_FS diff --git a/arch/x86/include/asm/memblock.h b/arch/x86/include/asm/memblock.h index 19ae14ba6978..0cd3800f33b9 100644 --- a/arch/x86/include/asm/memblock.h +++ b/arch/x86/include/asm/memblock.h @@ -4,7 +4,6 @@ #define ARCH_DISCARD_MEMBLOCK u64 memblock_x86_find_in_range_size(u64 start, u64 *sizep, u64 align); -void memblock_x86_to_bootmem(u64 start, u64 end); void memblock_x86_reserve_range(u64 start, u64 end, char *name); void memblock_x86_free_range(u64 start, u64 end); @@ -19,5 +18,6 @@ u64 memblock_x86_hole_size(u64 start, u64 end); u64 memblock_x86_find_in_range_node(int nid, u64 start, u64 end, u64 size, u64 align); u64 memblock_x86_free_memory_in_range(u64 addr, u64 limit); u64 memblock_x86_memory_in_range(u64 addr, u64 limit); +bool memblock_x86_check_reserved_size(u64 *addrp, u64 *sizep, u64 align); #endif diff --git a/arch/x86/include/asm/pvclock.h b/arch/x86/include/asm/pvclock.h index 31d84acc1512..a518c0a45044 100644 --- a/arch/x86/include/asm/pvclock.h +++ b/arch/x86/include/asm/pvclock.h @@ -22,6 +22,8 @@ static inline u64 pvclock_scale_delta(u64 delta, u32 mul_frac, int shift) u64 product; #ifdef __i386__ u32 tmp1, tmp2; +#else + ulong tmp; #endif if (shift < 0) @@ -42,8 +44,11 @@ static inline u64 pvclock_scale_delta(u64 delta, u32 mul_frac, int shift) : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) ); #elif defined(__x86_64__) __asm__ ( - "mul %%rdx ; shrd $32,%%rdx,%%rax" - : "=a" (product) : "0" (delta), "d" ((u64)mul_frac) ); + "mul %[mul_frac] ; shrd $32, %[hi], %[lo]" + : [lo]"=a"(product), + [hi]"=d"(tmp) + : "0"(delta), + [mul_frac]"rm"((u64)mul_frac)); #else #error implement me! #endif diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index b511a011b7d0..adc66c3a1fef 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -632,14 +632,14 @@ late_initcall(uv_init_heartbeat); /* Direct Legacy VGA I/O traffic to designated IOH */ int uv_set_vga_state(struct pci_dev *pdev, bool decode, - unsigned int command_bits, bool change_bridge) + unsigned int command_bits, u32 flags) { int domain, bus, rc; - PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n", - pdev->devfn, decode, command_bits, change_bridge); + PR_DEVEL("devfn %x decode %d cmd %x flags %d\n", + pdev->devfn, decode, command_bits, flags); - if (!change_bridge) + if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) return 0; if ((command_bits & PCI_COMMAND_IO) == 0) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 2e4928d45a2d..e1ba8cb24e4e 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -337,7 +337,7 @@ EXPORT_SYMBOL(boot_option_idle_override); * Powermanagement idle function, if any.. */ void (*pm_idle)(void); -#if defined(CONFIG_APM_MODULE) && defined(CONFIG_APM_CPU_IDLE) +#ifdef CONFIG_APM_MODULE EXPORT_SYMBOL(pm_idle); #endif @@ -399,7 +399,7 @@ void default_idle(void) cpu_relax(); } } -#if defined(CONFIG_APM_MODULE) && defined(CONFIG_APM_CPU_IDLE) +#ifdef CONFIG_APM_MODULE EXPORT_SYMBOL(default_idle); #endif diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index bd14bb4c8594..aee38623b768 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -565,7 +565,7 @@ gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) { - return gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); + return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); } static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h index 6c4dc010c4cb..9d03ad4dd5ec 100644 --- a/arch/x86/kvm/paging_tmpl.h +++ b/arch/x86/kvm/paging_tmpl.h @@ -121,7 +121,7 @@ static int FNAME(walk_addr_generic)(struct guest_walker *walker, gva_t addr, u32 access) { pt_element_t pte; - pt_element_t __user *ptep_user; + pt_element_t __user *uninitialized_var(ptep_user); gfn_t table_gfn; unsigned index, pt_access, uninitialized_var(pte_access); gpa_t pte_gpa; diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 4c3fa0f67469..d48ec60ea421 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2047,7 +2047,8 @@ static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, unsigned long cr0, struct kvm_vcpu *vcpu) { - vmx_decache_cr3(vcpu); + if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) + vmx_decache_cr3(vcpu); if (!(cr0 & X86_CR0_PG)) { /* From paging/starting to nonpaging */ vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, diff --git a/arch/x86/mm/memblock.c b/arch/x86/mm/memblock.c index aa1169392b83..992da5ec5a64 100644 --- a/arch/x86/mm/memblock.c +++ b/arch/x86/mm/memblock.c @@ -8,7 +8,7 @@ #include <linux/range.h> /* Check for already reserved areas */ -static bool __init check_with_memblock_reserved_size(u64 *addrp, u64 *sizep, u64 align) +bool __init memblock_x86_check_reserved_size(u64 *addrp, u64 *sizep, u64 align) { struct memblock_region *r; u64 addr = *addrp, last; @@ -59,7 +59,7 @@ u64 __init memblock_x86_find_in_range_size(u64 start, u64 *sizep, u64 align) if (addr >= ei_last) continue; *sizep = ei_last - addr; - while (check_with_memblock_reserved_size(&addr, sizep, align)) + while (memblock_x86_check_reserved_size(&addr, sizep, align)) ; if (*sizep) diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index 0972315c3860..68c3c1395202 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -188,7 +188,7 @@ static bool resource_contains(struct resource *res, resource_size_t point) return false; } -static void coalesce_windows(struct pci_root_info *info, int type) +static void coalesce_windows(struct pci_root_info *info, unsigned long type) { int i, j; struct resource *res1, *res2; diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c index 0d3a4fa34560..474356b98ede 100644 --- a/arch/x86/platform/efi/efi.c +++ b/arch/x86/platform/efi/efi.c @@ -310,14 +310,31 @@ void __init efi_reserve_boot_services(void) for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { efi_memory_desc_t *md = p; - unsigned long long start = md->phys_addr; - unsigned long long size = md->num_pages << EFI_PAGE_SHIFT; + u64 start = md->phys_addr; + u64 size = md->num_pages << EFI_PAGE_SHIFT; if (md->type != EFI_BOOT_SERVICES_CODE && md->type != EFI_BOOT_SERVICES_DATA) continue; - - memblock_x86_reserve_range(start, start + size, "EFI Boot"); + /* Only reserve where possible: + * - Not within any already allocated areas + * - Not over any memory area (really needed, if above?) + * - Not within any part of the kernel + * - Not the bios reserved area + */ + if ((start+size >= virt_to_phys(_text) + && start <= virt_to_phys(_end)) || + !e820_all_mapped(start, start+size, E820_RAM) || + memblock_x86_check_reserved_size(&start, &size, + 1<<EFI_PAGE_SHIFT)) { + /* Could not reserve, skip it */ + md->num_pages = 0; + memblock_dbg(PFX "Could not reserve boot range " + "[0x%010llx-0x%010llx]\n", + start, start+size-1); + } else + memblock_x86_reserve_range(start, start+size, + "EFI Boot"); } } @@ -334,6 +351,10 @@ static void __init efi_free_boot_services(void) md->type != EFI_BOOT_SERVICES_DATA) continue; + /* Could not reserve boot area */ + if (!size) + continue; + free_bootmem_late(start, size); } } diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index dd7b88f2ec7a..5525163a0398 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -1033,6 +1033,13 @@ static void xen_machine_halt(void) xen_reboot(SHUTDOWN_poweroff); } +static void xen_machine_power_off(void) +{ + if (pm_power_off) + pm_power_off(); + xen_reboot(SHUTDOWN_poweroff); +} + static void xen_crash_shutdown(struct pt_regs *regs) { xen_reboot(SHUTDOWN_crash); @@ -1058,7 +1065,7 @@ int xen_panic_handler_init(void) static const struct machine_ops xen_machine_ops __initconst = { .restart = xen_restart, .halt = xen_machine_halt, - .power_off = xen_machine_halt, + .power_off = xen_machine_power_off, .shutdown = xen_machine_halt, .crash_shutdown = xen_crash_shutdown, .emergency_restart = xen_emergency_restart, diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c index dc708dcc62f1..673e968df3cf 100644 --- a/arch/x86/xen/mmu.c +++ b/arch/x86/xen/mmu.c @@ -59,6 +59,7 @@ #include <asm/page.h> #include <asm/init.h> #include <asm/pat.h> +#include <asm/smp.h> #include <asm/xen/hypercall.h> #include <asm/xen/hypervisor.h> @@ -1231,7 +1232,7 @@ static void xen_flush_tlb_others(const struct cpumask *cpus, { struct { struct mmuext_op op; - DECLARE_BITMAP(mask, NR_CPUS); + DECLARE_BITMAP(mask, num_processors); } *args; struct multicall_space mcs; @@ -1599,6 +1600,11 @@ static void __init xen_map_identity_early(pmd_t *pmd, unsigned long max_pfn) for (pteidx = 0; pteidx < PTRS_PER_PTE; pteidx++, pfn++) { pte_t pte; +#ifdef CONFIG_X86_32 + if (pfn > max_pfn_mapped) + max_pfn_mapped = pfn; +#endif + if (!pte_none(pte_page[pteidx])) continue; @@ -1766,7 +1772,9 @@ pgd_t * __init xen_setup_kernel_pagetable(pgd_t *pgd, initial_kernel_pmd = extend_brk(sizeof(pmd_t) * PTRS_PER_PMD, PAGE_SIZE); - max_pfn_mapped = PFN_DOWN(__pa(xen_start_info->mfn_list)); + max_pfn_mapped = PFN_DOWN(__pa(xen_start_info->pt_base) + + xen_start_info->nr_pt_frames * PAGE_SIZE + + 512*1024); kernel_pmd = m2v(pgd[KERNEL_PGD_BOUNDARY].pgd); memcpy(initial_kernel_pmd, kernel_pmd, sizeof(pmd_t) * PTRS_PER_PMD); diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index be1a464f6d66..60aeeb56948f 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -227,11 +227,7 @@ char * __init xen_memory_setup(void) memcpy(map_raw, map, sizeof(map)); e820.nr_map = 0; -#ifdef CONFIG_X86_32 xen_extra_mem_start = mem_end; -#else - xen_extra_mem_start = max((1ULL << 32), mem_end); -#endif for (i = 0; i < memmap.nr_entries; i++) { unsigned long long end; @@ -266,6 +262,12 @@ char * __init xen_memory_setup(void) if (map[i].size > 0) e820_add_region(map[i].addr, map[i].size, map[i].type); } + /* Align the balloon area so that max_low_pfn does not get set + * to be at the _end_ of the PCI gap at the far end (fee01000). + * Note that xen_extra_mem_start gets set in the loop above to be + * past the last E820 region. */ + if (xen_initial_domain() && (xen_extra_mem_start < (1ULL<<32))) + xen_extra_mem_start = (1ULL<<32); /* * In domU, the ISA region is normal, usable memory, but we diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c index 41038c01de40..b4533a86d7e4 100644 --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c @@ -205,11 +205,18 @@ static void __init xen_smp_prepare_boot_cpu(void) static void __init xen_smp_prepare_cpus(unsigned int max_cpus) { unsigned cpu; + unsigned int i; xen_init_lock_cpu(0); smp_store_cpu_info(0); cpu_data(0).x86_max_cores = 1; + + for_each_possible_cpu(i) { + zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); + zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); + zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); + } set_cpu_sibling_map(0); if (xen_smp_intr_init(0)) |