diff options
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/Kconfig | 13 | ||||
| -rw-r--r-- | drivers/fpga/Makefile | 2 | ||||
| -rw-r--r-- | drivers/fpga/fpga-bridge.c | 17 | ||||
| -rw-r--r-- | drivers/fpga/fpga-mgr.c | 2 | ||||
| -rw-r--r-- | drivers/fpga/fpga-region.c | 8 | ||||
| -rw-r--r-- | drivers/fpga/ice40-spi.c | 207 | ||||
| -rw-r--r-- | drivers/fpga/ts73xx-fpga.c | 156 | ||||
| -rw-r--r-- | drivers/fpga/zynq-fpga.c | 28 |
8 files changed, 415 insertions, 18 deletions
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index ce861a2853a4..dee470f9113f 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -20,6 +20,12 @@ config FPGA_REGION FPGA Regions allow loading FPGA images under control of the Device Tree. +config FPGA_MGR_ICE40_SPI + tristate "Lattice iCE40 SPI" + depends on OF && SPI + help + FPGA manager driver support for Lattice iCE40 FPGAs over SPI. + config FPGA_MGR_SOCFPGA tristate "Altera SOCFPGA FPGA Manager" depends on ARCH_SOCFPGA || COMPILE_TEST @@ -33,6 +39,13 @@ config FPGA_MGR_SOCFPGA_A10 help FPGA manager driver support for Altera Arria10 SoCFPGA. +config FPGA_MGR_TS73XX + tristate "Technologic Systems TS-73xx SBC FPGA Manager" + depends on ARCH_EP93XX && MACH_TS72XX + help + FPGA manager driver support for the Altera Cyclone II FPGA + present on the TS-73xx SBC boards. + config FPGA_MGR_ZYNQ_FPGA tristate "Xilinx Zynq FPGA" depends on ARCH_ZYNQ || COMPILE_TEST diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 8df07bcf42a6..a5ee3ffe8b18 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -6,8 +6,10 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Manager Drivers +obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o +obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o # FPGA Bridge Drivers diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c index 33ee83e6373c..9651aa56244a 100644 --- a/drivers/fpga/fpga-bridge.c +++ b/drivers/fpga/fpga-bridge.c @@ -27,7 +27,7 @@ static DEFINE_IDA(fpga_bridge_ida); static struct class *fpga_bridge_class; /* Lock for adding/removing bridges to linked lists*/ -spinlock_t bridge_list_lock; +static spinlock_t bridge_list_lock; static int fpga_bridge_of_node_match(struct device *dev, const void *data) { @@ -146,11 +146,9 @@ EXPORT_SYMBOL_GPL(fpga_bridge_put); int fpga_bridges_enable(struct list_head *bridge_list) { struct fpga_bridge *bridge; - struct list_head *node; int ret; - list_for_each(node, bridge_list) { - bridge = list_entry(node, struct fpga_bridge, node); + list_for_each_entry(bridge, bridge_list, node) { ret = fpga_bridge_enable(bridge); if (ret) return ret; @@ -172,11 +170,9 @@ EXPORT_SYMBOL_GPL(fpga_bridges_enable); int fpga_bridges_disable(struct list_head *bridge_list) { struct fpga_bridge *bridge; - struct list_head *node; int ret; - list_for_each(node, bridge_list) { - bridge = list_entry(node, struct fpga_bridge, node); + list_for_each_entry(bridge, bridge_list, node) { ret = fpga_bridge_disable(bridge); if (ret) return ret; @@ -196,13 +192,10 @@ EXPORT_SYMBOL_GPL(fpga_bridges_disable); */ void fpga_bridges_put(struct list_head *bridge_list) { - struct fpga_bridge *bridge; - struct list_head *node, *next; + struct fpga_bridge *bridge, *next; unsigned long flags; - list_for_each_safe(node, next, bridge_list) { - bridge = list_entry(node, struct fpga_bridge, node); - + list_for_each_entry_safe(bridge, next, bridge_list, node) { fpga_bridge_put(bridge); spin_lock_irqsave(&bridge_list_lock, flags); diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index 86d2cb203533..188ffefa3cc3 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -361,7 +361,7 @@ static struct attribute *fpga_mgr_attrs[] = { }; ATTRIBUTE_GROUPS(fpga_mgr); -struct fpga_manager *__fpga_mgr_get(struct device *dev) +static struct fpga_manager *__fpga_mgr_get(struct device *dev) { struct fpga_manager *mgr; int ret = -ENODEV; diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c index 3222fdbad75a..2fe2a52c66ca 100644 --- a/drivers/fpga/fpga-region.c +++ b/drivers/fpga/fpga-region.c @@ -337,8 +337,9 @@ static int child_regions_with_firmware(struct device_node *overlay) * The overlay must add either firmware-name or external-fpga-config property * to the FPGA Region. * - * firmware-name : program the FPGA - * external-fpga-config : FPGA is already programmed + * firmware-name : program the FPGA + * external-fpga-config : FPGA is already programmed + * encrypted-fpga-config : FPGA bitstream is encrypted * * The overlay can add other FPGA regions, but child FPGA regions cannot have a * firmware-name property since those regions don't exist yet. @@ -373,6 +374,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region, if (of_property_read_bool(nd->overlay, "external-fpga-config")) info->flags |= FPGA_MGR_EXTERNAL_CONFIG; + if (of_property_read_bool(nd->overlay, "encrypted-fpga-config")) + info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM; + of_property_read_string(nd->overlay, "firmware-name", &firmware_name); of_property_read_u32(nd->overlay, "region-unfreeze-timeout-us", diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c new file mode 100644 index 000000000000..7fca82023062 --- /dev/null +++ b/drivers/fpga/ice40-spi.c @@ -0,0 +1,207 @@ +/* + * FPGA Manager Driver for Lattice iCE40. + * + * Copyright (c) 2016 Joel Holdsworth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This driver adds support to the FPGA manager for configuring the SRAM of + * Lattice iCE40 FPGAs through slave SPI. + */ + +#include <linux/fpga/fpga-mgr.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/spi/spi.h> +#include <linux/stringify.h> + +#define ICE40_SPI_MAX_SPEED 25000000 /* Hz */ +#define ICE40_SPI_MIN_SPEED 1000000 /* Hz */ + +#define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */ +#define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */ + +#define ICE40_SPI_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8) + +struct ice40_fpga_priv { + struct spi_device *dev; + struct gpio_desc *reset; + struct gpio_desc *cdone; +}; + +static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr) +{ + struct ice40_fpga_priv *priv = mgr->priv; + + return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : + FPGA_MGR_STATE_UNKNOWN; +} + +static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct ice40_fpga_priv *priv = mgr->priv; + struct spi_device *dev = priv->dev; + struct spi_message message; + struct spi_transfer assert_cs_then_reset_delay = { + .cs_change = 1, + .delay_usecs = ICE40_SPI_RESET_DELAY + }; + struct spi_transfer housekeeping_delay_then_release_cs = { + .delay_usecs = ICE40_SPI_HOUSEKEEPING_DELAY + }; + int ret; + + if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { + dev_err(&dev->dev, + "Partial reconfiguration is not supported\n"); + return -ENOTSUPP; + } + + /* Lock the bus, assert CRESET_B and SS_B and delay >200ns */ + spi_bus_lock(dev->master); + + gpiod_set_value(priv->reset, 1); + + spi_message_init(&message); + spi_message_add_tail(&assert_cs_then_reset_delay, &message); + ret = spi_sync_locked(dev, &message); + + /* Come out of reset */ + gpiod_set_value(priv->reset, 0); + + /* Abort if the chip-select failed */ + if (ret) + goto fail; + + /* Check CDONE is de-asserted i.e. the FPGA is reset */ + if (gpiod_get_value(priv->cdone)) { + dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n"); + ret = -EIO; + goto fail; + } + + /* Wait for the housekeeping to complete, and release SS_B */ + spi_message_init(&message); + spi_message_add_tail(&housekeeping_delay_then_release_cs, &message); + ret = spi_sync_locked(dev, &message); + +fail: + spi_bus_unlock(dev->master); + + return ret; +} + +static int ice40_fpga_ops_write(struct fpga_manager *mgr, + const char *buf, size_t count) +{ + struct ice40_fpga_priv *priv = mgr->priv; + + return spi_write(priv->dev, buf, count); +} + +static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct ice40_fpga_priv *priv = mgr->priv; + struct spi_device *dev = priv->dev; + const u8 padding[ICE40_SPI_NUM_ACTIVATION_BYTES] = {0}; + + /* Check CDONE is asserted */ + if (!gpiod_get_value(priv->cdone)) { + dev_err(&dev->dev, + "CDONE was not asserted after firmware transfer\n"); + return -EIO; + } + + /* Send of zero-padding to activate the firmware */ + return spi_write(dev, padding, sizeof(padding)); +} + +static const struct fpga_manager_ops ice40_fpga_ops = { + .state = ice40_fpga_ops_state, + .write_init = ice40_fpga_ops_write_init, + .write = ice40_fpga_ops_write, + .write_complete = ice40_fpga_ops_write_complete, +}; + +static int ice40_fpga_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct ice40_fpga_priv *priv; + int ret; + + priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = spi; + + /* Check board setup data. */ + if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) { + dev_err(dev, "SPI speed is too high, maximum speed is " + __stringify(ICE40_SPI_MAX_SPEED) "\n"); + return -EINVAL; + } + + if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) { + dev_err(dev, "SPI speed is too low, minimum speed is " + __stringify(ICE40_SPI_MIN_SPEED) "\n"); + return -EINVAL; + } + + if (spi->mode & SPI_CPHA) { + dev_err(dev, "Bad SPI mode, CPHA not supported\n"); + return -EINVAL; + } + + /* Set up the GPIOs */ + priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN); + if (IS_ERR(priv->cdone)) { + ret = PTR_ERR(priv->cdone); + dev_err(dev, "Failed to get CDONE GPIO: %d\n", ret); + return ret; + } + + priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(priv->reset)) { + ret = PTR_ERR(priv->reset); + dev_err(dev, "Failed to get CRESET_B GPIO: %d\n", ret); + return ret; + } + + /* Register with the FPGA manager */ + return fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager", + &ice40_fpga_ops, priv); +} + +static int ice40_fpga_remove(struct spi_device *spi) +{ + fpga_mgr_unregister(&spi->dev); + return 0; +} + +static const struct of_device_id ice40_fpga_of_match[] = { + { .compatible = "lattice,ice40-fpga-mgr", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ice40_fpga_of_match); + +static struct spi_driver ice40_fpga_driver = { + .probe = ice40_fpga_probe, + .remove = ice40_fpga_remove, + .driver = { + .name = "ice40spi", + .of_match_table = of_match_ptr(ice40_fpga_of_match), + }, +}; + +module_spi_driver(ice40_fpga_driver); + +MODULE_AUTHOR("Joel Holdsworth <joel@airwebreathe.org.uk>"); +MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c new file mode 100644 index 000000000000..f6a96b42e2ca --- /dev/null +++ b/drivers/fpga/ts73xx-fpga.c @@ -0,0 +1,156 @@ +/* + * Technologic Systems TS-73xx SBC FPGA loader + * + * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> + * + * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on + * TS-7300, heavily based on load_fpga.c in their vendor tree. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/string.h> +#include <linux/iopoll.h> +#include <linux/fpga/fpga-mgr.h> + +#define TS73XX_FPGA_DATA_REG 0 +#define TS73XX_FPGA_CONFIG_REG 1 + +#define TS73XX_FPGA_WRITE_DONE 0x1 +#define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */ +#define TS73XX_FPGA_RESET 0x2 +#define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */ +#define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */ +#define TS73XX_FPGA_LOAD_OK 0x4 +#define TS73XX_FPGA_CONFIG_LOAD 0x8 + +struct ts73xx_fpga_priv { + void __iomem *io_base; + struct device *dev; +}; + +static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static int ts73xx_fpga_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct ts73xx_fpga_priv *priv = mgr->priv; + + /* Reset the FPGA */ + writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); + udelay(TS73XX_FPGA_RESET_LOW_DELAY); + writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); + udelay(TS73XX_FPGA_RESET_HIGH_DELAY); + + return 0; +} + +static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct ts73xx_fpga_priv *priv = mgr->priv; + size_t i = 0; + int ret; + u8 reg; + + while (count--) { + ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG, + reg, !(reg & TS73XX_FPGA_WRITE_DONE), + 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT); + if (ret < 0) + return ret; + + writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); + i++; + } + + return 0; +} + +static int ts73xx_fpga_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct ts73xx_fpga_priv *priv = mgr->priv; + u8 reg; + + usleep_range(1000, 2000); + reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); + reg |= TS73XX_FPGA_CONFIG_LOAD; + writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); + + usleep_range(1000, 2000); + reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); + reg &= ~TS73XX_FPGA_CONFIG_LOAD; + writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); + + reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); + if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK) + return -ETIMEDOUT; + + return 0; +} + +static const struct fpga_manager_ops ts73xx_fpga_ops = { + .state = ts73xx_fpga_state, + .write_init = ts73xx_fpga_write_init, + .write = ts73xx_fpga_write, + .write_complete = ts73xx_fpga_write_complete, +}; + +static int ts73xx_fpga_probe(struct platform_device *pdev) +{ + struct device *kdev = &pdev->dev; + struct ts73xx_fpga_priv *priv; + struct resource *res; + + priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = kdev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->io_base = devm_ioremap_resource(kdev, res); + if (IS_ERR(priv->io_base)) { + dev_err(kdev, "unable to remap registers\n"); + return PTR_ERR(priv->io_base); + } + + return fpga_mgr_register(kdev, "TS-73xx FPGA Manager", + &ts73xx_fpga_ops, priv); +} + +static int ts73xx_fpga_remove(struct platform_device *pdev) +{ + fpga_mgr_unregister(&pdev->dev); + + return 0; +} + +static struct platform_driver ts73xx_fpga_driver = { + .driver = { + .name = "ts73xx-fpga-mgr", + }, + .probe = ts73xx_fpga_probe, + .remove = ts73xx_fpga_remove, +}; +module_platform_driver(ts73xx_fpga_driver); + +MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>"); +MODULE_DESCRIPTION("TS-73xx FPGA Manager driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 34cb98139442..70b15b303471 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -72,6 +72,10 @@ #define CTRL_PCAP_PR_MASK BIT(27) /* Enable PCAP */ #define CTRL_PCAP_MODE_MASK BIT(26) +/* Lower rate to allow decrypt on the fly */ +#define CTRL_PCAP_RATE_EN_MASK BIT(25) +/* System booted in secure mode */ +#define CTRL_SEC_EN_MASK BIT(7) /* Miscellaneous Control Register bit definitions */ /* Internal PCAP loopback */ @@ -266,6 +270,17 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, if (err) return err; + /* check if bitstream is encrypted & and system's still secure */ + if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) { + ctrl = zynq_fpga_read(priv, CTRL_OFFSET); + if (!(ctrl & CTRL_SEC_EN_MASK)) { + dev_err(&mgr->dev, + "System not secure, can't use crypted bitstreams\n"); + err = -EINVAL; + goto out_err; + } + } + /* don't globally reset PL if we're doing partial reconfig */ if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { if (!zynq_fpga_has_sync(buf, count)) { @@ -337,12 +352,19 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, /* set configuration register with following options: * - enable PCAP interface - * - set throughput for maximum speed + * - set throughput for maximum speed (if bistream not crypted) * - set CPU in user mode */ ctrl = zynq_fpga_read(priv, CTRL_OFFSET); - zynq_fpga_write(priv, CTRL_OFFSET, - (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK | ctrl)); + if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) + zynq_fpga_write(priv, CTRL_OFFSET, + (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK + | CTRL_PCAP_RATE_EN_MASK | ctrl)); + else + zynq_fpga_write(priv, CTRL_OFFSET, + (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK + | ctrl)); + /* We expect that the command queue is empty right now. */ status = zynq_fpga_read(priv, STATUS_OFFSET); |