diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
7 files changed, 36 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index cf4027cc3f4c..812377d9e48f 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -335,4 +335,15 @@ struct bp_soc_bb_info { uint32_t dram_sr_enter_exit_latency_100ns; }; +struct bp_connector_speed_cap_info { + uint32_t DP_HBR2_EN:1; + uint32_t DP_HBR3_EN:1; + uint32_t HDMI_6GB_EN:1; + uint32_t DP_UHBR10_EN:1; + uint32_t DP_UHBR13_5_EN:1; + uint32_t DP_UHBR20_EN:1; + uint32_t DP_IS_USB_C:1; + uint32_t RESERVED:28; +}; + #endif /*__DAL_BIOS_PARSER_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 310f8779db67..ab06c7fc7452 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -221,10 +221,6 @@ enum { #ifndef ASICREV_IS_VANGOGH #define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN)) #endif -#define GREEN_SARDINE_A0 0xA1 -#ifndef ASICREV_IS_GREEN_SARDINE -#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) -#endif #define FAMILY_YELLOW_CARP 146 #define YELLOW_CARP_A0 0x01 @@ -247,6 +243,15 @@ enum { #define ASICREV_IS_GC_10_3_7(eChipRev) ((eChipRev >= GC_10_3_7_A0) && (eChipRev < GC_10_3_7_UNKNOWN)) +#define AMDGPU_FAMILY_GC_11_0_0 145 +#define AMDGPU_FAMILY_GC_11_0_2 148 +#define GC_11_0_0_A0 0x1 +#define GC_11_0_2_A0 0x10 +#define GC_11_UNKNOWN 0xFF + +#define ASICREV_IS_GC_11_0_0(eChipRev) (eChipRev < GC_11_0_2_A0) +#define ASICREV_IS_GC_11_0_2(eChipRev) (eChipRev >= GC_11_0_2_A0 && eChipRev < GC_11_UNKNOWN) + /* * ASIC chip ID */ @@ -280,6 +285,4 @@ enum { #define FAMILY_UNKNOWN 0xFF - - #endif /* __DAL_ASIC_ID_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index bf9085fc5105..d2427cf1155f 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -57,8 +57,11 @@ enum dce_version { DCN_VERSION_3_02, DCN_VERSION_3_03, DCN_VERSION_3_1, + DCN_VERSION_3_14, DCN_VERSION_3_15, DCN_VERSION_3_16, + DCN_VERSION_3_2, + DCN_VERSION_3_21, DCN_VERSION_MAX }; diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h index 20a3d4e23f66..05096c644a60 100644 --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h @@ -41,6 +41,10 @@ #define DP_DEVICE_ID_38EC11 0x38EC11 #define DP_FORCE_PSRSU_CAPABILITY 0x40F +#define DP_SINK_PSR_ACTIVE_VTOTAL 0x373 +#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE 0x375 +#define DP_SOURCE_PSR_ACTIVE_VTOTAL 0x376 + enum ddc_result { DDC_RESULT_UNKNOWN = 0, DDC_RESULT_SUCESSFULL, diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h index 22053d7ea6ce..ece97ae0e826 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -322,7 +322,7 @@ struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg); */ static inline struct fixed31_32 dc_fixpt_div_int(struct fixed31_32 arg1, long long arg2) { - return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int(arg2).value); + return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int((int)arg2).value); } /* diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h index 447a56286dd0..79fabc51c991 100644 --- a/drivers/gpu/drm/amd/display/include/link_service_types.h +++ b/drivers/gpu/drm/amd/display/include/link_service_types.h @@ -67,6 +67,8 @@ enum link_training_result { LINK_TRAINING_CR_FAIL_LANE23, /* CR DONE bit is cleared during EQ step */ LINK_TRAINING_EQ_FAIL_CR, + /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */ + LINK_TRAINING_EQ_FAIL_CR_PARTIAL, /* other failure during EQ step */ LINK_TRAINING_EQ_FAIL_EQ, LINK_TRAINING_LQA_FAIL, @@ -92,7 +94,6 @@ struct link_training_settings { /* TODO: turn lane settings below into mandatory fields * as initial lane configuration */ - struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; enum dc_voltage_swing *voltage_swing; enum dc_pre_emphasis *pre_emphasis; enum dc_post_cursor2 *post_cursor2; diff --git a/drivers/gpu/drm/amd/display/include/set_mode_types.h b/drivers/gpu/drm/amd/display/include/set_mode_types.h index 845fea8a387f..75f2c79492c0 100644 --- a/drivers/gpu/drm/amd/display/include/set_mode_types.h +++ b/drivers/gpu/drm/amd/display/include/set_mode_types.h @@ -84,10 +84,14 @@ union hdmi_info_packet { uint16_t bar_left; uint16_t bar_right; - uint8_t F140_F143:4; + uint8_t FR0_FR3:4; uint8_t ACE0_ACE3:4; - uint8_t reserved[13]; + uint8_t RID0_RID5:6; + uint8_t FR4:1; + uint8_t F157:1; + + uint8_t reserved[12]; } bits; struct info_packet_raw_data packet_raw_data; |