diff options
Diffstat (limited to 'include/ufs')
-rw-r--r-- | include/ufs/ufs.h | 4 | ||||
-rw-r--r-- | include/ufs/ufshcd.h | 9 | ||||
-rw-r--r-- | include/ufs/ufshci.h | 5 |
3 files changed, 14 insertions, 4 deletions
diff --git a/include/ufs/ufs.h b/include/ufs/ufs.h index 853e95957c31..e594abe5d05f 100644 --- a/include/ufs/ufs.h +++ b/include/ufs/ufs.h @@ -597,7 +597,7 @@ struct ufs_dev_info { }; /* - * This enum is used in string mapping in include/trace/events/ufs.h. + * This enum is used in string mapping in ufs_trace.h. */ enum ufs_trace_str_t { UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP, @@ -607,7 +607,7 @@ enum ufs_trace_str_t { /* * Transaction Specific Fields (TSF) type in the UPIU package, this enum is - * used in include/trace/events/ufs.h for UFS command trace. + * used in ufs_trace.h for UFS command trace. */ enum ufs_trace_tsf_t { UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index cac0cdb9a916..3f68ae3e4330 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -17,6 +17,7 @@ #include <linux/blk-mq.h> #include <linux/devfreq.h> #include <linux/fault-inject.h> +#include <linux/debugfs.h> #include <linux/msi.h> #include <linux/pm_runtime.h> #include <linux/dma-direction.h> @@ -676,6 +677,14 @@ enum ufshcd_quirks { * the standard best practice for managing keys). */ UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24, + + /* + * This quirk indicates that the controller reports the value 1 (not + * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the + * Controller Capabilities register although it supports the legacy + * single doorbell mode. + */ + UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25, }; enum ufshcd_caps { diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index 9917c7743d80..27364c4a6ef9 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -25,8 +25,9 @@ enum { REG_CONTROLLER_CAPABILITIES = 0x00, REG_MCQCAP = 0x04, REG_UFS_VERSION = 0x08, - REG_CONTROLLER_DEV_ID = 0x10, - REG_CONTROLLER_PROD_ID = 0x14, + REG_EXT_CONTROLLER_CAPABILITIES = 0x0C, + REG_CONTROLLER_PID = 0x10, + REG_CONTROLLER_MID = 0x14, REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, REG_INTERRUPT_STATUS = 0x20, REG_INTERRUPT_ENABLE = 0x24, |