diff options
Diffstat (limited to 'include')
602 files changed, 13223 insertions, 22301 deletions
diff --git a/include/Kbuild b/include/Kbuild index b52288774345..6ae595cda668 100644 --- a/include/Kbuild +++ b/include/Kbuild @@ -1,8 +1,8 @@ +# Top-level Makefile calls into asm-$(ARCH) + header-y += asm-generic/ header-y += linux/ header-y += sound/ header-y += mtd/ header-y += rdma/ header-y += video/ - -header-y += asm-$(ARCH)/ diff --git a/include/acpi/acconfig.h b/include/acpi/acconfig.h index 28fe8bae1037..67b3b5da85f4 100644 --- a/include/acpi/acconfig.h +++ b/include/acpi/acconfig.h @@ -63,7 +63,7 @@ /* Current ACPICA subsystem version in YYYYMMDD format */ -#define ACPI_CA_VERSION 0x20080321 +#define ACPI_CA_VERSION 0x20080609 /* * OS name, used for the _OS object. The _OS object is essentially obsolete, @@ -214,4 +214,4 @@ #define ACPI_DEBUGGER_COMMAND_PROMPT '-' #define ACPI_DEBUGGER_EXECUTE_PROMPT '%' -#endif /* _ACCONFIG_H */ +#endif /* _ACCONFIG_H */ diff --git a/include/acpi/acdebug.h b/include/acpi/acdebug.h index c5a1b50d8d94..ef1e50a1e5c0 100644 --- a/include/acpi/acdebug.h +++ b/include/acpi/acdebug.h @@ -220,4 +220,4 @@ struct acpi_namespace_node *acpi_db_local_ns_lookup(char *name); void acpi_db_uint32_to_hex_string(u32 value, char *buffer); -#endif /* __ACDEBUG_H__ */ +#endif /* __ACDEBUG_H__ */ diff --git a/include/acpi/acdisasm.h b/include/acpi/acdisasm.h index 788f88782012..16da38d79b67 100644 --- a/include/acpi/acdisasm.h +++ b/include/acpi/acdisasm.h @@ -162,6 +162,7 @@ extern struct acpi_dmtable_info acpi_dm_table_info_dmar_hdr[]; extern struct acpi_dmtable_info acpi_dm_table_info_dmar_scope[]; extern struct acpi_dmtable_info acpi_dm_table_info_dmar0[]; extern struct acpi_dmtable_info acpi_dm_table_info_dmar1[]; +extern struct acpi_dmtable_info acpi_dm_table_info_dmar2[]; extern struct acpi_dmtable_info acpi_dm_table_info_ecdt[]; extern struct acpi_dmtable_info acpi_dm_table_info_einj[]; extern struct acpi_dmtable_info acpi_dm_table_info_einj0[]; @@ -437,4 +438,4 @@ void acpi_dm_check_resource_reference(union acpi_parse_object *op, struct acpi_walk_state *walk_state); -#endif /* __ACDISASM_H__ */ +#endif /* __ACDISASM_H__ */ diff --git a/include/acpi/acdispat.h b/include/acpi/acdispat.h index 910f018d92c7..f4cf6e6fe38a 100644 --- a/include/acpi/acdispat.h +++ b/include/acpi/acdispat.h @@ -221,7 +221,7 @@ acpi_ds_method_error(acpi_status status, struct acpi_walk_state *walk_state); * dsinit */ acpi_status -acpi_ds_initialize_objects(acpi_native_uint table_index, +acpi_ds_initialize_objects(u32 table_index, struct acpi_namespace_node *start_node); /* @@ -342,4 +342,4 @@ acpi_status acpi_ds_result_push(union acpi_operand_object *object, struct acpi_walk_state *walk_state); -#endif /* _ACDISPAT_H_ */ +#endif /* _ACDISPAT_H_ */ diff --git a/include/acpi/acevents.h b/include/acpi/acevents.h index d5d099bf349c..73dc6d38b8c3 100644 --- a/include/acpi/acevents.h +++ b/include/acpi/acevents.h @@ -213,4 +213,4 @@ u32 acpi_ev_initialize_sCI(u32 program_sCI); void acpi_ev_terminate(void); -#endif /* __ACEVENTS_H__ */ +#endif /* __ACEVENTS_H__ */ diff --git a/include/acpi/acexcep.h b/include/acpi/acexcep.h index 1f591171bf31..18a2ced0e5ec 100644 --- a/include/acpi/acexcep.h +++ b/include/acpi/acexcep.h @@ -108,8 +108,9 @@ #define AE_BAD_HEX_CONSTANT (acpi_status) (0x0007 | AE_CODE_PROGRAMMER) #define AE_BAD_OCTAL_CONSTANT (acpi_status) (0x0008 | AE_CODE_PROGRAMMER) #define AE_BAD_DECIMAL_CONSTANT (acpi_status) (0x0009 | AE_CODE_PROGRAMMER) +#define AE_MISSING_ARGUMENTS (acpi_status) (0x000A | AE_CODE_PROGRAMMER) -#define AE_CODE_PGM_MAX 0x0009 +#define AE_CODE_PGM_MAX 0x000A /* * Acpi table exceptions @@ -225,6 +226,7 @@ char const *acpi_gbl_exception_names_env[] = { }; char const *acpi_gbl_exception_names_pgm[] = { + NULL, "AE_BAD_PARAMETER", "AE_BAD_CHARACTER", "AE_BAD_PATHNAME", @@ -233,10 +235,12 @@ char const *acpi_gbl_exception_names_pgm[] = { "AE_ALIGNMENT", "AE_BAD_HEX_CONSTANT", "AE_BAD_OCTAL_CONSTANT", - "AE_BAD_DECIMAL_CONSTANT" + "AE_BAD_DECIMAL_CONSTANT", + "AE_MISSING_ARGUMENTS" }; char const *acpi_gbl_exception_names_tbl[] = { + NULL, "AE_BAD_SIGNATURE", "AE_BAD_HEADER", "AE_BAD_CHECKSUM", @@ -246,6 +250,7 @@ char const *acpi_gbl_exception_names_tbl[] = { }; char const *acpi_gbl_exception_names_aml[] = { + NULL, "AE_AML_ERROR", "AE_AML_PARSE", "AE_AML_BAD_OPCODE", @@ -283,6 +288,7 @@ char const *acpi_gbl_exception_names_aml[] = { }; char const *acpi_gbl_exception_names_ctrl[] = { + NULL, "AE_CTRL_RETURN_VALUE", "AE_CTRL_PENDING", "AE_CTRL_TERMINATE", @@ -298,6 +304,6 @@ char const *acpi_gbl_exception_names_ctrl[] = { "AE_CTRL_PARSE_PENDING" }; -#endif /* ACPI GLOBALS */ +#endif /* ACPI GLOBALS */ -#endif /* __ACEXCEP_H__ */ +#endif /* __ACEXCEP_H__ */ diff --git a/include/acpi/acglobal.h b/include/acpi/acglobal.h index 74ad971241db..6bdf80a238b7 100644 --- a/include/acpi/acglobal.h +++ b/include/acpi/acglobal.h @@ -140,7 +140,7 @@ ACPI_EXTERN u32 acpi_gbl_trace_flags; */ ACPI_EXTERN struct acpi_internal_rsdt acpi_gbl_root_table_list; ACPI_EXTERN struct acpi_table_fadt acpi_gbl_FADT; -extern acpi_native_uint acpi_gbl_permanent_mmap; +extern u8 acpi_gbl_permanent_mmap; /* These addresses are calculated from FADT address values */ @@ -382,6 +382,6 @@ ACPI_EXTERN u32 acpi_gbl_size_of_method_trees; ACPI_EXTERN u32 acpi_gbl_size_of_node_entries; ACPI_EXTERN u32 acpi_gbl_size_of_acpi_objects; -#endif /* ACPI_DEBUGGER */ +#endif /* ACPI_DEBUGGER */ -#endif /* __ACGLOBAL_H__ */ +#endif /* __ACGLOBAL_H__ */ diff --git a/include/acpi/achware.h b/include/acpi/achware.h index d4fb9bbc903c..6d740a45c5d4 100644 --- a/include/acpi/achware.h +++ b/include/acpi/achware.h @@ -70,8 +70,7 @@ u32 acpi_hw_get_mode(void); */ struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id); -acpi_status -acpi_hw_register_read(u32 register_id, u32 * return_value); +acpi_status acpi_hw_register_read(u32 register_id, u32 * return_value); acpi_status acpi_hw_register_write(u32 register_id, u32 value); @@ -104,7 +103,7 @@ acpi_hw_clear_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info, acpi_status acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info, acpi_event_status * event_status); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ acpi_status acpi_hw_disable_all_gpes(void); @@ -126,6 +125,6 @@ acpi_status acpi_get_timer(u32 * ticks); acpi_status acpi_get_timer_duration(u32 start_ticks, u32 end_ticks, u32 * time_elapsed); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ -#endif /* __ACHWARE_H__ */ +#endif /* __ACHWARE_H__ */ diff --git a/include/acpi/acinterp.h b/include/acpi/acinterp.h index e249ce5d3300..3c0df439d0ea 100644 --- a/include/acpi/acinterp.h +++ b/include/acpi/acinterp.h @@ -366,17 +366,14 @@ void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth); void acpi_ex_dump_operands(union acpi_operand_object **operands, - acpi_interpreter_mode interpreter_mode, - char *ident, - u32 num_levels, - char *note, char *module_name, u32 line_number); + const char *opcode_name, u32 num_opcodes); #ifdef ACPI_FUTURE_USAGE void acpi_ex_dump_object_descriptor(union acpi_operand_object *object, u32 flags); void acpi_ex_dump_namespace_node(struct acpi_namespace_node *node, u32 flags); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ /* * exnames - AML namestring support @@ -529,4 +526,4 @@ acpi_ex_data_table_space_handler(u32 function, acpi_integer * value, void *handler_context, void *region_context); -#endif /* __INTERP_H__ */ +#endif /* __INTERP_H__ */ diff --git a/include/acpi/aclocal.h b/include/acpi/aclocal.h index c5cdc32ac2f8..df793b6a32a4 100644 --- a/include/acpi/aclocal.h +++ b/include/acpi/aclocal.h @@ -282,8 +282,8 @@ struct acpi_predefined_names { /* Info structure used to convert external<->internal namestrings */ struct acpi_namestring_info { - char *external_name; - char *next_external_char; + const char *external_name; + const char *next_external_char; char *internal_name; u32 length; u32 num_segments; @@ -964,4 +964,4 @@ struct acpi_memory_list { #endif }; -#endif /* __ACLOCAL_H__ */ +#endif /* __ACLOCAL_H__ */ diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h index fb41a3b802fc..d25ab698d2bf 100644 --- a/include/acpi/acmacros.h +++ b/include/acpi/acmacros.h @@ -80,12 +80,12 @@ */ #define ACPI_CAST_PTR(t, p) ((t *) (acpi_uintptr_t) (p)) #define ACPI_CAST_INDIRECT_PTR(t, p) ((t **) (acpi_uintptr_t) (p)) -#define ACPI_ADD_PTR(t,a,b) ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_native_uint)(b))) -#define ACPI_PTR_DIFF(a,b) (acpi_native_uint) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b))) +#define ACPI_ADD_PTR(t, a, b) ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_size)(b))) +#define ACPI_PTR_DIFF(a, b) (acpi_size) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b))) /* Pointer/Integer type conversions */ -#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void,(void *) NULL,(acpi_native_uint) i) +#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void, (void *) NULL, (acpi_size) i) #define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF (p,(void *) NULL) #define ACPI_OFFSET(d,f) (acpi_size) ACPI_PTR_DIFF (&(((d *)0)->f),(void *) NULL) #define ACPI_PHYSADDR_TO_PTR(i) ACPI_TO_POINTER(i) @@ -296,22 +296,22 @@ struct acpi_integer_overlay { /* * Rounding macros (Power of two boundaries only) */ -#define ACPI_ROUND_DOWN(value,boundary) (((acpi_native_uint)(value)) & \ - (~(((acpi_native_uint) boundary)-1))) +#define ACPI_ROUND_DOWN(value, boundary) (((acpi_size)(value)) & \ + (~(((acpi_size) boundary)-1))) -#define ACPI_ROUND_UP(value,boundary) ((((acpi_native_uint)(value)) + \ - (((acpi_native_uint) boundary)-1)) & \ - (~(((acpi_native_uint) boundary)-1))) +#define ACPI_ROUND_UP(value, boundary) ((((acpi_size)(value)) + \ + (((acpi_size) boundary)-1)) & \ + (~(((acpi_size) boundary)-1))) -/* Note: sizeof(acpi_native_uint) evaluates to either 2, 4, or 8 */ +/* Note: sizeof(acpi_size) evaluates to either 4 or 8 (32- vs 64-bit mode) */ #define ACPI_ROUND_DOWN_TO_32BIT(a) ACPI_ROUND_DOWN(a,4) #define ACPI_ROUND_DOWN_TO_64BIT(a) ACPI_ROUND_DOWN(a,8) -#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a) ACPI_ROUND_DOWN(a,sizeof(acpi_native_uint)) +#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a) ACPI_ROUND_DOWN(a,sizeof(acpi_size)) #define ACPI_ROUND_UP_TO_32BIT(a) ACPI_ROUND_UP(a,4) #define ACPI_ROUND_UP_TO_64BIT(a) ACPI_ROUND_UP(a,8) -#define ACPI_ROUND_UP_TO_NATIVE_WORD(a) ACPI_ROUND_UP(a,sizeof(acpi_native_uint)) +#define ACPI_ROUND_UP_TO_NATIVE_WORD(a) ACPI_ROUND_UP(a,sizeof(acpi_size)) #define ACPI_ROUND_BITS_UP_TO_BYTES(a) ACPI_DIV_8((a) + 7) #define ACPI_ROUND_BITS_DOWN_TO_BYTES(a) ACPI_DIV_8((a)) @@ -322,7 +322,7 @@ struct acpi_integer_overlay { #define ACPI_ROUND_UP_TO(value,boundary) (((value) + ((boundary)-1)) / (boundary)) -#define ACPI_IS_MISALIGNED(value) (((acpi_native_uint)value) & (sizeof(acpi_native_uint)-1)) +#define ACPI_IS_MISALIGNED(value) (((acpi_size)value) & (sizeof(acpi_size)-1)) /* * Bitmask creation @@ -414,7 +414,7 @@ struct acpi_integer_overlay { * error messages. The __FILE__ macro is not very useful for this, because it * often includes the entire pathname to the module */ -#define ACPI_MODULE_NAME(name) static char ACPI_UNUSED_VAR *_acpi_module_name = name; +#define ACPI_MODULE_NAME(name) static const char ACPI_UNUSED_VAR _acpi_module_name[] = name; #else #define ACPI_MODULE_NAME(name) #endif @@ -467,19 +467,17 @@ struct acpi_integer_overlay { /* * If ACPI_GET_FUNCTION_NAME was not defined in the compiler-dependent header, * define it now. This is the case where there the compiler does not support - * a __FUNCTION__ macro or equivalent. We save the function name on the - * local stack. + * a __FUNCTION__ macro or equivalent. */ #ifndef ACPI_GET_FUNCTION_NAME #define ACPI_GET_FUNCTION_NAME _acpi_function_name /* * The Name parameter should be the procedure name as a quoted string. - * This is declared as a local string ("MyFunctionName") so that it can - * be also used by the function exit macros below. + * The function name is also used by the function exit macros below. * Note: (const char) is used to be compatible with the debug interfaces * and macros such as __FUNCTION__. */ -#define ACPI_FUNCTION_NAME(name) const char *_acpi_function_name = #name; +#define ACPI_FUNCTION_NAME(name) static const char _acpi_function_name[] = #name; #else /* Compiler supports __FUNCTION__ (or equivalent) -- Ignore this macro */ @@ -550,7 +548,7 @@ struct acpi_integer_overlay { register u32 _s = (u32) (s); \ acpi_ut_value_exit (ACPI_DEBUG_PARAMETERS, (acpi_integer) _s); \ return (_s); }) -#else /* Use original less-safe macros */ +#else /* Use original less-safe macros */ #define return_ACPI_STATUS(s) ACPI_DO_WHILE0 ({ \ acpi_ut_status_exit (ACPI_DEBUG_PARAMETERS, (s)); \ @@ -564,7 +562,7 @@ struct acpi_integer_overlay { #define return_UINT8(s) return_VALUE(s) #define return_UINT32(s) return_VALUE(s) -#endif /* ACPI_SIMPLE_RETURN_MACROS */ +#endif /* ACPI_SIMPLE_RETURN_MACROS */ #else /* !CONFIG_ACPI_DEBUG_FUNC_TRACE */ @@ -599,7 +597,7 @@ struct acpi_integer_overlay { /* Stack and buffer dumping */ #define ACPI_DUMP_STACK_ENTRY(a) acpi_ex_dump_operand((a),0) -#define ACPI_DUMP_OPERANDS(a,b,c,d,e) acpi_ex_dump_operands(a,b,c,d,e,_acpi_module_name,__LINE__) +#define ACPI_DUMP_OPERANDS(a,b,c) acpi_ex_dump_operands(a,b,c) #define ACPI_DUMP_ENTRY(a,b) acpi_ns_dump_entry (a,b) #define ACPI_DUMP_PATHNAME(a,b,c,d) acpi_ns_dump_pathname(a,b,c,d) @@ -635,7 +633,7 @@ struct acpi_integer_overlay { #define ACPI_FUNCTION_VALUE_EXIT(s) do { } while(0) #define ACPI_FUNCTION_ENTRY() do { } while(0) #define ACPI_DUMP_STACK_ENTRY(a) do { } while(0) -#define ACPI_DUMP_OPERANDS(a,b,c,d,e) do { } while(0) +#define ACPI_DUMP_OPERANDS(a,b,c) do { } while(0) #define ACPI_DUMP_ENTRY(a,b) do { } while(0) #define ACPI_DUMP_TABLES(a,b) do { } while(0) #define ACPI_DUMP_PATHNAME(a,b,c,d) do { } while(0) @@ -703,6 +701,6 @@ struct acpi_integer_overlay { #define ACPI_FREE(a) acpi_ut_free_and_track(a,_COMPONENT,_acpi_module_name,__LINE__) #define ACPI_MEM_TRACKING(a) a -#endif /* ACPI_DBG_TRACK_ALLOCATIONS */ +#endif /* ACPI_DBG_TRACK_ALLOCATIONS */ -#endif /* ACMACROS_H */ +#endif /* ACMACROS_H */ diff --git a/include/acpi/acnames.h b/include/acpi/acnames.h index c1343a9265fa..ffee458507a2 100644 --- a/include/acpi/acnames.h +++ b/include/acpi/acnames.h @@ -80,4 +80,4 @@ #define ACPI_NS_ROOT_PATH "\\" #define ACPI_NS_SYSTEM_BUS "_SB_" -#endif /* __ACNAMES_H__ */ +#endif /* __ACNAMES_H__ */ diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h index 713b30903fe5..ef82cb267907 100644 --- a/include/acpi/acnamesp.h +++ b/include/acpi/acnamesp.h @@ -86,8 +86,7 @@ acpi_status acpi_ns_initialize_devices(void); acpi_status acpi_ns_load_namespace(void); acpi_status -acpi_ns_load_table(acpi_native_uint table_index, - struct acpi_namespace_node *node); +acpi_ns_load_table(u32 table_index, struct acpi_namespace_node *node); /* * nswalk - walk the namespace @@ -108,12 +107,11 @@ struct acpi_namespace_node *acpi_ns_get_next_node(acpi_object_type type, struct * nsparse - table parsing */ acpi_status -acpi_ns_parse_table(acpi_native_uint table_index, - struct acpi_namespace_node *start_node); +acpi_ns_parse_table(u32 table_index, struct acpi_namespace_node *start_node); acpi_status -acpi_ns_one_complete_parse(acpi_native_uint pass_number, - acpi_native_uint table_index, +acpi_ns_one_complete_parse(u32 pass_number, + u32 table_index, struct acpi_namespace_node *start_node); /* @@ -153,7 +151,7 @@ int acpi_ns_compare_names(char *name1, char *name2); */ #ifdef ACPI_FUTURE_USAGE void acpi_ns_dump_tables(acpi_handle search_base, u32 max_depth); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ void acpi_ns_dump_entry(acpi_handle handle, u32 debug_level); @@ -172,7 +170,7 @@ acpi_ns_dump_objects(acpi_object_type type, u8 display_type, u32 max_depth, acpi_owner_id owner_id, acpi_handle start_handle); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ /* * nseval - Namespace evaluation functions @@ -201,7 +199,7 @@ acpi_ns_pattern_match(struct acpi_namespace_node *obj_node, char *search_for); acpi_status acpi_ns_get_node(struct acpi_namespace_node *prefix_node, - char *external_pathname, + const char *external_pathname, u32 flags, struct acpi_namespace_node **out_node); acpi_size acpi_ns_get_pathname_length(struct acpi_namespace_node *node); @@ -265,28 +263,30 @@ acpi_object_type acpi_ns_get_type(struct acpi_namespace_node *node); u32 acpi_ns_local(acpi_object_type type); void -acpi_ns_report_error(char *module_name, +acpi_ns_report_error(const char *module_name, u32 line_number, - char *internal_name, acpi_status lookup_status); + const char *internal_name, acpi_status lookup_status); void -acpi_ns_report_method_error(char *module_name, +acpi_ns_report_method_error(const char *module_name, u32 line_number, - char *message, + const char *message, struct acpi_namespace_node *node, - char *path, acpi_status lookup_status); + const char *path, acpi_status lookup_status); -void acpi_ns_print_node_pathname(struct acpi_namespace_node *node, char *msg); +void +acpi_ns_print_node_pathname(struct acpi_namespace_node *node, const char *msg); acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info); void acpi_ns_get_internal_name_length(struct acpi_namestring_info *info); -acpi_status acpi_ns_internalize_name(char *dotted_name, char **converted_name); +acpi_status +acpi_ns_internalize_name(const char *dotted_name, char **converted_name); acpi_status acpi_ns_externalize_name(u32 internal_name_length, - char *internal_name, + const char *internal_name, u32 * converted_name_length, char **converted_name); struct acpi_namespace_node *acpi_ns_map_handle_to_node(acpi_handle handle); @@ -302,4 +302,4 @@ struct acpi_namespace_node *acpi_ns_get_next_valid_node(struct acpi_namespace_node *node); -#endif /* __ACNAMESP_H__ */ +#endif /* __ACNAMESP_H__ */ diff --git a/include/acpi/acobject.h b/include/acpi/acobject.h index e9657dac69b7..58f57b19501c 100644 --- a/include/acpi/acobject.h +++ b/include/acpi/acobject.h @@ -420,4 +420,4 @@ union acpi_descriptor { #pragma pack() -#endif /* _ACOBJECT_H */ +#endif /* _ACOBJECT_H */ diff --git a/include/acpi/acopcode.h b/include/acpi/acopcode.h index dfdf63327885..62bf10e98894 100644 --- a/include/acpi/acopcode.h +++ b/include/acpi/acopcode.h @@ -320,4 +320,4 @@ #define ARGI_WORD_OP ARGI_INVALID_OPCODE #define ARGI_ZERO_OP ARG_NONE -#endif /* __ACOPCODE_H__ */ +#endif /* __ACOPCODE_H__ */ diff --git a/include/acpi/acoutput.h b/include/acpi/acoutput.h index e17873defcec..3fdb7142b667 100644 --- a/include/acpi/acoutput.h +++ b/include/acpi/acoutput.h @@ -182,4 +182,4 @@ #define ACPI_NORMAL_DEFAULT (ACPI_LV_INIT | ACPI_LV_WARN | ACPI_LV_ERROR) #define ACPI_DEBUG_ALL (ACPI_LV_AML_DISASSEMBLE | ACPI_LV_ALL_EXCEPTIONS | ACPI_LV_ALL) -#endif /* __ACOUTPUT_H__ */ +#endif /* __ACOUTPUT_H__ */ diff --git a/include/acpi/acparser.h b/include/acpi/acparser.h index 23ee0fbf5619..6f2d8b576a8f 100644 --- a/include/acpi/acparser.h +++ b/include/acpi/acparser.h @@ -172,7 +172,7 @@ union acpi_parse_object *acpi_ps_get_arg(union acpi_parse_object *op, u32 argn); #ifdef ACPI_FUTURE_USAGE union acpi_parse_object *acpi_ps_get_depth_next(union acpi_parse_object *origin, union acpi_parse_object *op); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ /* * pswalk - parse tree walk routines @@ -214,7 +214,7 @@ u8 acpi_ps_is_prefix_char(u32 c); #ifdef ACPI_FUTURE_USAGE u32 acpi_ps_get_name(union acpi_parse_object *op); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ void acpi_ps_set_name(union acpi_parse_object *op, u32 name); @@ -231,4 +231,4 @@ acpi_ps_sprint_op(char *buffer_start, void acpi_ps_show(union acpi_parse_object *op); -#endif /* __ACPARSER_H__ */ +#endif /* __ACPARSER_H__ */ diff --git a/include/acpi/acpi.h b/include/acpi/acpi.h index c515ef6cc89e..d04bf99df8a2 100644 --- a/include/acpi/acpi.h +++ b/include/acpi/acpi.h @@ -66,4 +66,4 @@ #include "achware.h" /* Hardware defines and interfaces */ #include "acutils.h" /* Utility interfaces */ -#endif /* __ACPI_H__ */ +#endif /* __ACPI_H__ */ diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 2f1c68c7a727..1f6145663c60 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -131,7 +131,7 @@ struct acpi_device_ops { struct acpi_driver { char name[80]; char class[80]; - const struct acpi_device_id *ids; /* Supported Hardware IDs */ + const struct acpi_device_id *ids; /* Supported Hardware IDs */ struct acpi_device_ops ops; struct device_driver drv; struct module *owner; @@ -320,7 +320,7 @@ struct acpi_bus_event { }; extern struct kobject *acpi_kobj; -extern int acpi_bus_generate_netlink_event(const char*, const char*, u8, int); +extern int acpi_bus_generate_netlink_event(const char *, const char *, u8, int); void acpi_bus_private_data_handler(acpi_handle, u32, void *); int acpi_bus_get_private_data(acpi_handle, void **); extern int acpi_notifier_call_chain(struct acpi_device *, u32, u32); @@ -337,11 +337,15 @@ int acpi_bus_get_power(acpi_handle handle, int *state); int acpi_bus_set_power(acpi_handle handle, int state); #ifdef CONFIG_ACPI_PROC_EVENT int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data); -int acpi_bus_generate_proc_event4(const char *class, const char *bid, u8 type, int data); +int acpi_bus_generate_proc_event4(const char *class, const char *bid, u8 type, + int data); int acpi_bus_receive_event(struct acpi_bus_event *event); #else -static inline int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data) - { return 0; } +static inline int acpi_bus_generate_proc_event(struct acpi_device *device, + u8 type, int data) +{ + return 0; +} #endif int acpi_bus_register_driver(struct acpi_driver *driver); void acpi_bus_unregister_driver(struct acpi_driver *driver); @@ -376,9 +380,9 @@ acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int); #define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->archdata.acpi_handle)) #ifdef CONFIG_PM_SLEEP -int acpi_pm_device_sleep_state(struct device *, int, int *); +int acpi_pm_device_sleep_state(struct device *, int *); #else /* !CONFIG_PM_SLEEP */ -static inline int acpi_pm_device_sleep_state(struct device *d, int w, int *p) +static inline int acpi_pm_device_sleep_state(struct device *d, int *p) { if (p) *p = ACPI_STATE_D0; @@ -386,6 +390,6 @@ static inline int acpi_pm_device_sleep_state(struct device *d, int w, int *p) } #endif /* !CONFIG_PM_SLEEP */ -#endif /* CONFIG_ACPI */ +#endif /* CONFIG_ACPI */ #endif /*__ACPI_BUS_H__*/ diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index 9757a040a505..af53e66b5ee3 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -126,19 +126,23 @@ static inline int is_dock_device(acpi_handle handle) { return 0; } + static inline int register_dock_notifier(struct notifier_block *nb) { return -ENODEV; } + static inline void unregister_dock_notifier(struct notifier_block *nb) { } + static inline int register_hotplug_dock_device(acpi_handle handle, acpi_notify_handler handler, void *context) { return -ENODEV; } + static inline void unregister_hotplug_dock_device(acpi_handle handle) { } diff --git a/include/acpi/acpi_numa.h b/include/acpi/acpi_numa.h index 173972672175..9890e5a1d0f1 100644 --- a/include/acpi/acpi_numa.h +++ b/include/acpi/acpi_numa.h @@ -16,5 +16,5 @@ extern int node_to_pxm(int); extern void __acpi_map_pxm_to_node(int, int); extern int acpi_map_pxm_to_node(int); -#endif /* CONFIG_ACPI_NUMA */ -#endif /* __ACP_NUMA_H */ +#endif /* CONFIG_ACPI_NUMA */ +#endif /* __ACP_NUMA_H */ diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h index d4a560d2deb6..bacc4ec21937 100644 --- a/include/acpi/acpiosxf.h +++ b/include/acpi/acpiosxf.h @@ -143,8 +143,7 @@ void acpi_os_release_mutex(acpi_mutex handle); */ void *acpi_os_allocate(acpi_size size); -void __iomem *acpi_os_map_memory(acpi_physical_address where, - acpi_native_uint length); +void __iomem *acpi_os_map_memory(acpi_physical_address where, acpi_size length); void acpi_os_unmap_memory(void __iomem * logical_address, acpi_size size); @@ -222,7 +221,7 @@ acpi_os_write_memory(acpi_physical_address address, u32 value, u32 width); */ acpi_status acpi_os_read_pci_configuration(struct acpi_pci_id *pci_id, - u32 reg, u32 *value, u32 width); + u32 reg, u32 * value, u32 width); acpi_status acpi_os_write_pci_configuration(struct acpi_pci_id *pci_id, @@ -239,7 +238,7 @@ acpi_os_derive_pci_id(acpi_handle rhandle, * Miscellaneous */ acpi_status acpi_os_validate_interface(char *interface); -acpi_status acpi_osi_invalidate(char* interface); +acpi_status acpi_osi_invalidate(char *interface); acpi_status acpi_os_validate_address(u8 space_id, acpi_physical_address address, @@ -280,4 +279,4 @@ char *acpi_os_get_next_filename(void *dir_handle); void acpi_os_close_directory(void *dir_handle); -#endif /* __ACPIOSXF_H__ */ +#endif /* __ACPIOSXF_H__ */ diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index 2c3806e6546f..bcb1917451c6 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -98,7 +98,7 @@ void acpi_free(void *address); */ acpi_status acpi_reallocate_root_table(void); -acpi_status acpi_find_root_pointer(acpi_native_uint * rsdp_address); +acpi_status acpi_find_root_pointer(acpi_size * rsdp_address); acpi_status acpi_load_tables(void); @@ -108,19 +108,16 @@ acpi_status acpi_unload_table_id(acpi_owner_id id); acpi_status acpi_get_table_header(acpi_string signature, - acpi_native_uint instance, - struct acpi_table_header *out_table_header); + u32 instance, struct acpi_table_header *out_table_header); acpi_status acpi_get_table(acpi_string signature, - acpi_native_uint instance, struct acpi_table_header **out_table); + u32 instance, struct acpi_table_header **out_table); acpi_status -acpi_get_table_by_index(acpi_native_uint table_index, - struct acpi_table_header **out_table); +acpi_get_table_by_index(u32 table_index, struct acpi_table_header **out_table); -acpi_status -acpi_install_table_handler(acpi_tbl_handler handler, void *context); +acpi_status acpi_install_table_handler(acpi_tbl_handler handler, void *context); acpi_status acpi_remove_table_handler(acpi_tbl_handler handler); @@ -250,7 +247,7 @@ acpi_status acpi_clear_event(u32 event); #ifdef ACPI_FUTURE_USAGE acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ acpi_status acpi_set_gpe_type(acpi_handle gpe_device, u32 gpe_number, u8 type); @@ -265,7 +262,7 @@ acpi_status acpi_get_gpe_status(acpi_handle gpe_device, u32 gpe_number, u32 flags, acpi_event_status * event_status); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ acpi_status acpi_install_gpe_block(acpi_handle gpe_device, @@ -319,7 +316,7 @@ acpi_resource_to_address64(struct acpi_resource *resource, */ acpi_status acpi_get_register(u32 register_id, u32 * return_value); -acpi_status acpi_get_register_unlocked(u32 register_id, u32 *return_value); +acpi_status acpi_get_register_unlocked(u32 register_id, u32 * return_value); acpi_status acpi_set_register(u32 register_id, u32 value); @@ -344,4 +341,4 @@ acpi_status acpi_leave_sleep_state_prep(u8 sleep_state); acpi_status acpi_leave_sleep_state(u8 sleep_state); -#endif /* __ACXFACE_H__ */ +#endif /* __ACXFACE_H__ */ diff --git a/include/acpi/acresrc.h b/include/acpi/acresrc.h index eef5bd7a59fa..4b0daf38b86c 100644 --- a/include/acpi/acresrc.h +++ b/include/acpi/acresrc.h @@ -333,4 +333,4 @@ extern struct acpi_rsdump_info acpi_rs_dump_ext_irq[]; extern struct acpi_rsdump_info acpi_rs_dump_generic_reg[]; #endif -#endif /* __ACRESRC_H__ */ +#endif /* __ACRESRC_H__ */ diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h index a907c67d651e..7980a26bad35 100644 --- a/include/acpi/acstruct.h +++ b/include/acpi/acstruct.h @@ -108,7 +108,6 @@ struct acpi_walk_state { union acpi_operand_object **caller_return_desc; union acpi_generic_state *control_state; /* List of control states (nested IFs) */ struct acpi_namespace_node *deferred_node; /* Used when executing deferred opcodes */ - struct acpi_gpe_event_info *gpe_event_info; /* Info for GPE (_Lxx/_Exx methods only */ union acpi_operand_object *implicit_return_obj; struct acpi_namespace_node *method_call_node; /* Called method Node */ union acpi_parse_object *method_call_op; /* method_call Op if running a method */ @@ -143,7 +142,7 @@ struct acpi_init_walk_info { u16 package_init; u16 object_count; acpi_owner_id owner_id; - acpi_native_uint table_index; + u32 table_index; }; struct acpi_get_devices_info { @@ -189,17 +188,12 @@ struct acpi_evaluate_info { union acpi_operand_object **parameters; struct acpi_namespace_node *resolved_node; union acpi_operand_object *return_object; + u8 param_count; u8 pass_number; - u8 parameter_type; u8 return_object_type; u8 flags; }; -/* Types for parameter_type above */ - -#define ACPI_PARAM_ARGS 0 -#define ACPI_PARAM_GPE 1 - /* Values for Flags above */ #define ACPI_IGNORE_RETURN_VALUE 1 diff --git a/include/acpi/actables.h b/include/acpi/actables.h index 4b36a55b0b3b..bdef1465a1b6 100644 --- a/include/acpi/actables.h +++ b/include/acpi/actables.h @@ -49,7 +49,7 @@ acpi_status acpi_allocate_root_table(u32 initial_table_count); /* * tbfadt - FADT parse/convert/validate */ -void acpi_tb_parse_fadt(acpi_native_uint table_index, u8 flags); +void acpi_tb_parse_fadt(u32 table_index, u8 flags); void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length); @@ -58,8 +58,7 @@ void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length); */ acpi_status acpi_tb_find_table(char *signature, - char *oem_id, - char *oem_table_id, acpi_native_uint * table_index); + char *oem_id, char *oem_table_id, u32 * table_index); /* * tbinstal - Table removal and deletion @@ -69,30 +68,28 @@ acpi_status acpi_tb_resize_root_table_list(void); acpi_status acpi_tb_verify_table(struct acpi_table_desc *table_desc); acpi_status -acpi_tb_add_table(struct acpi_table_desc *table_desc, - acpi_native_uint * table_index); +acpi_tb_add_table(struct acpi_table_desc *table_desc, u32 * table_index); acpi_status acpi_tb_store_table(acpi_physical_address address, struct acpi_table_header *table, - u32 length, u8 flags, acpi_native_uint * table_index); + u32 length, u8 flags, u32 * table_index); void acpi_tb_delete_table(struct acpi_table_desc *table_desc); void acpi_tb_terminate(void); -void acpi_tb_delete_namespace_by_owner(acpi_native_uint table_index); +void acpi_tb_delete_namespace_by_owner(u32 table_index); -acpi_status acpi_tb_allocate_owner_id(acpi_native_uint table_index); +acpi_status acpi_tb_allocate_owner_id(u32 table_index); -acpi_status acpi_tb_release_owner_id(acpi_native_uint table_index); +acpi_status acpi_tb_release_owner_id(u32 table_index); -acpi_status -acpi_tb_get_owner_id(acpi_native_uint table_index, acpi_owner_id * owner_id); +acpi_status acpi_tb_get_owner_id(u32 table_index, acpi_owner_id * owner_id); -u8 acpi_tb_is_table_loaded(acpi_native_uint table_index); +u8 acpi_tb_is_table_loaded(u32 table_index); -void acpi_tb_set_table_loaded_flag(acpi_native_uint table_index, u8 is_loaded); +void acpi_tb_set_table_loaded_flag(u32 table_index, u8 is_loaded); /* * tbutils - table manager utilities @@ -103,16 +100,16 @@ void acpi_tb_print_table_header(acpi_physical_address address, struct acpi_table_header *header); -u8 acpi_tb_checksum(u8 * buffer, acpi_native_uint length); +u8 acpi_tb_checksum(u8 * buffer, u32 length); acpi_status acpi_tb_verify_checksum(struct acpi_table_header *table, u32 length); void acpi_tb_install_table(acpi_physical_address address, - u8 flags, char *signature, acpi_native_uint table_index); + u8 flags, char *signature, u32 table_index); acpi_status acpi_tb_parse_root_table(acpi_physical_address rsdp_address, u8 flags); -#endif /* __ACTABLES_H__ */ +#endif /* __ACTABLES_H__ */ diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h index 1ebbe883f786..2f33c365c379 100644 --- a/include/acpi/actbl.h +++ b/include/acpi/actbl.h @@ -293,4 +293,4 @@ enum acpi_prefered_pm_profiles { #include <acpi/actbl1.h> -#endif /* __ACTBL_H__ */ +#endif /* __ACTBL_H__ */ diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 9af239bd1153..2486f1447c99 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -300,6 +300,7 @@ struct acpi_table_dbgp { /******************************************************************************* * * DMAR - DMA Remapping table + * From "Intel Virtualization Technology for Directed I/O", Sept. 2007 * ******************************************************************************/ @@ -310,6 +311,10 @@ struct acpi_table_dmar { u8 reserved[10]; }; +/* Flags */ + +#define ACPI_DMAR_INTR_REMAP (1) + /* DMAR subtable header */ struct acpi_dmar_header { @@ -374,7 +379,7 @@ struct acpi_dmar_reserved_memory { struct acpi_dmar_header header; u16 reserved; u16 segment; - u64 base_address; /* 4_k aligned base address */ + u64 base_address; /* 4_k aligned base address */ u64 end_address; /* 4_k aligned limit address */ }; @@ -382,6 +387,19 @@ struct acpi_dmar_reserved_memory { #define ACPI_DMAR_ALLOW_ALL (1) +/* 2: Root Port ATS Capability Reporting Structure */ + +struct acpi_dmar_atsr { + struct acpi_dmar_header header; + u8 flags; + u8 reserved; + u16 segment; +}; + +/* Flags */ + +#define ACPI_DMAR_ALL_PORTS (1) + /******************************************************************************* * * ECDT - Embedded Controller Boot Resources Table @@ -1156,9 +1174,9 @@ struct acpi_srat_mem_affinity { u16 reserved; /* Reserved, must be zero */ u64 base_address; u64 length; - u32 memory_type; /* See acpi_address_range_id */ + u32 reserved1; u32 flags; - u64 reserved1; /* Reserved, must be zero */ + u64 reserved2; /* Reserved, must be zero */ }; /* Flags */ @@ -1281,4 +1299,4 @@ struct acpi_table_wdrt { #pragma pack() -#endif /* __ACTBL1_H__ */ +#endif /* __ACTBL1_H__ */ diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index dfea2d440488..41e619e91e64 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -110,10 +110,10 @@ * usually used for memory allocation, efficient loop counters, and array * indexes. The types are similar to the size_t type in the C library and are * required because there is no C type that consistently represents the native - * data width. + * data width. ACPI_SIZE is needed because there is no guarantee that a + * kernel-level C library is present. * * ACPI_SIZE 16/32/64-bit unsigned value - * ACPI_NATIVE_UINT 16/32/64-bit unsigned value * ACPI_NATIVE_INT 16/32/64-bit signed value * */ @@ -147,9 +147,9 @@ typedef int INT32; /*! [End] no source code translation !*/ -typedef u64 acpi_native_uint; typedef s64 acpi_native_int; +typedef u64 acpi_size; typedef u64 acpi_io_address; typedef u64 acpi_physical_address; @@ -186,9 +186,9 @@ typedef int INT32; /*! [End] no source code translation !*/ -typedef u32 acpi_native_uint; typedef s32 acpi_native_int; +typedef u32 acpi_size; typedef u32 acpi_io_address; typedef u32 acpi_physical_address; @@ -202,10 +202,6 @@ typedef u32 acpi_physical_address; #error unknown ACPI_MACHINE_WIDTH #endif -/* Variable-width type, used instead of clib size_t */ - -typedef acpi_native_uint acpi_size; - /******************************************************************************* * * OS-dependent and compiler-dependent types @@ -219,7 +215,7 @@ typedef acpi_native_uint acpi_size; /* Value returned by acpi_os_get_thread_id */ #ifndef acpi_thread_id -#define acpi_thread_id acpi_native_uint +#define acpi_thread_id acpi_size #endif /* Object returned from acpi_os_create_lock */ @@ -231,7 +227,7 @@ typedef acpi_native_uint acpi_size; /* Flags for acpi_os_acquire_lock/acpi_os_release_lock */ #ifndef acpi_cpu_flags -#define acpi_cpu_flags acpi_native_uint +#define acpi_cpu_flags acpi_size #endif /* Object returned from acpi_os_create_cache */ @@ -780,8 +776,7 @@ acpi_status(*acpi_exception_handler) (acpi_status aml_status, /* Table Event handler (Load, load_table etc) and types */ -typedef -acpi_status(*acpi_tbl_handler) (u32 event, void *table, void *context); +typedef acpi_status(*acpi_tbl_handler) (u32 event, void *table, void *context); /* Address Spaces (For Operation Regions) */ @@ -1243,4 +1238,4 @@ struct acpi_pci_routing_table { char source[4]; /* pad to 64 bits so sizeof() works in all cases */ }; -#endif /* __ACTYPES_H__ */ +#endif /* __ACTYPES_H__ */ diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h index b42cadf07302..e57d76f03c35 100644 --- a/include/acpi/acutils.h +++ b/include/acpi/acutils.h @@ -172,7 +172,7 @@ char *acpi_ut_strstr(char *string1, char *string2); void *acpi_ut_memcpy(void *dest, const void *src, acpi_size count); -void *acpi_ut_memset(void *dest, acpi_native_uint value, acpi_size count); +void *acpi_ut_memset(void *dest, u8 value, acpi_size count); int acpi_ut_to_upper(int c); @@ -199,7 +199,7 @@ extern const u8 _acpi_ctype[]; #define ACPI_IS_PRINT(c) (_acpi_ctype[(unsigned char)(c)] & (_ACPI_LO | _ACPI_UP | _ACPI_DI | _ACPI_SP | _ACPI_PU)) #define ACPI_IS_ALPHA(c) (_acpi_ctype[(unsigned char)(c)] & (_ACPI_LO | _ACPI_UP)) -#endif /* ACPI_USE_SYSTEM_CLIBRARY */ +#endif /* ACPI_USE_SYSTEM_CLIBRARY */ /* * utcopy - Object construction and conversion interfaces @@ -245,41 +245,45 @@ void acpi_ut_track_stack_ptr(void); void acpi_ut_trace(u32 line_number, - const char *function_name, char *module_name, u32 component_id); + const char *function_name, + const char *module_name, u32 component_id); void acpi_ut_trace_ptr(u32 line_number, const char *function_name, - char *module_name, u32 component_id, void *pointer); + const char *module_name, u32 component_id, void *pointer); void acpi_ut_trace_u32(u32 line_number, const char *function_name, - char *module_name, u32 component_id, u32 integer); + const char *module_name, u32 component_id, u32 integer); void acpi_ut_trace_str(u32 line_number, const char *function_name, - char *module_name, u32 component_id, char *string); + const char *module_name, u32 component_id, char *string); void acpi_ut_exit(u32 line_number, - const char *function_name, char *module_name, u32 component_id); + const char *function_name, + const char *module_name, u32 component_id); void acpi_ut_status_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, acpi_status status); + const char *module_name, + u32 component_id, acpi_status status); void acpi_ut_value_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, acpi_integer value); + const char *module_name, + u32 component_id, acpi_integer value); void acpi_ut_ptr_exit(u32 line_number, const char *function_name, - char *module_name, u32 component_id, u8 * ptr); + const char *module_name, u32 component_id, u8 * ptr); void acpi_ut_dump_buffer(u8 * buffer, u32 count, u32 display, u32 component_id); @@ -297,33 +301,35 @@ void ACPI_INTERNAL_VAR_XFACE acpi_ut_debug_print(u32 requested_debug_level, u32 line_number, const char *function_name, - char *module_name, - u32 component_id, char *format, ...) ACPI_PRINTF_LIKE(6); + const char *module_name, + u32 component_id, + const char *format, ...) ACPI_PRINTF_LIKE(6); void ACPI_INTERNAL_VAR_XFACE acpi_ut_debug_print_raw(u32 requested_debug_level, u32 line_number, const char *function_name, - char *module_name, + const char *module_name, u32 component_id, - char *format, ...) ACPI_PRINTF_LIKE(6); + const char *format, ...) ACPI_PRINTF_LIKE(6); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_error(char *module_name, - u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3); +acpi_ut_error(const char *module_name, + u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_exception(char *module_name, +acpi_ut_exception(const char *module_name, u32 line_number, - acpi_status status, char *format, ...) ACPI_PRINTF_LIKE(4); + acpi_status status, + const char *format, ...) ACPI_PRINTF_LIKE(4); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_warning(char *module_name, - u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3); +acpi_ut_warning(const char *module_name, + u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3); void ACPI_INTERNAL_VAR_XFACE -acpi_ut_info(char *module_name, - u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3); +acpi_ut_info(const char *module_name, + u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3); /* * utdelete - Object deletion and reference counts @@ -376,13 +382,14 @@ acpi_ut_execute_sxds(struct acpi_namespace_node *device_node, u8 * highest); /* * utobject - internal object create/delete/cache routines */ -union acpi_operand_object *acpi_ut_create_internal_object_dbg(char *module_name, +union acpi_operand_object *acpi_ut_create_internal_object_dbg(const char + *module_name, u32 line_number, u32 component_id, acpi_object_type type); -void *acpi_ut_allocate_object_desc_dbg(char *module_name, +void *acpi_ut_allocate_object_desc_dbg(const char *module_name, u32 line_number, u32 component_id); #define acpi_ut_create_internal_object(t) acpi_ut_create_internal_object_dbg (_acpi_module_name,__LINE__,_COMPONENT,t) @@ -433,7 +440,7 @@ acpi_ut_create_pkg_state_and_push(void *internal_object, void *external_object, u16 index, union acpi_generic_state **state_list); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ union acpi_generic_state *acpi_ut_create_control_state(void); @@ -476,7 +483,7 @@ u8 acpi_ut_valid_acpi_name(u32 name); acpi_name acpi_ut_repair_name(char *name); -u8 acpi_ut_valid_acpi_char(char character, acpi_native_uint position); +u8 acpi_ut_valid_acpi_char(char character, u32 position); acpi_status acpi_ut_strtoul64(char *string, u32 base, acpi_integer * ret_integer); @@ -543,26 +550,29 @@ acpi_status acpi_ut_initialize_buffer(struct acpi_buffer *buffer, acpi_size required_length); -void *acpi_ut_allocate(acpi_size size, u32 component, char *module, u32 line); +void *acpi_ut_allocate(acpi_size size, + u32 component, const char *module, u32 line); void *acpi_ut_allocate_zeroed(acpi_size size, - u32 component, char *module, u32 line); + u32 component, const char *module, u32 line); #ifdef ACPI_DBG_TRACK_ALLOCATIONS void *acpi_ut_allocate_and_track(acpi_size size, - u32 component, char *module, u32 line); + u32 component, const char *module, u32 line); void *acpi_ut_allocate_zeroed_and_track(acpi_size size, - u32 component, char *module, u32 line); + u32 component, + const char *module, u32 line); void -acpi_ut_free_and_track(void *address, u32 component, char *module, u32 line); +acpi_ut_free_and_track(void *address, + u32 component, const char *module, u32 line); #ifdef ACPI_FUTURE_USAGE void acpi_ut_dump_allocation_info(void); -#endif /* ACPI_FUTURE_USAGE */ +#endif /* ACPI_FUTURE_USAGE */ -void acpi_ut_dump_allocations(u32 component, char *module); +void acpi_ut_dump_allocations(u32 component, const char *module); acpi_status acpi_ut_create_list(char *list_name, @@ -570,4 +580,4 @@ acpi_ut_create_list(char *list_name, #endif -#endif /* _ACUTILS_H */ +#endif /* _ACUTILS_H */ diff --git a/include/acpi/amlcode.h b/include/acpi/amlcode.h index ff851c5df698..c1e03fa7c582 100644 --- a/include/acpi/amlcode.h +++ b/include/acpi/amlcode.h @@ -491,4 +491,4 @@ typedef enum { #define AML_METHOD_RESERVED1 0x02 #define AML_METHOD_RESERVED2 0x04 -#endif /* __AMLCODE_H__ */ +#endif /* __AMLCODE_H__ */ diff --git a/include/acpi/container.h b/include/acpi/container.h index a703f14e049e..cacab574f7ba 100644 --- a/include/acpi/container.h +++ b/include/acpi/container.h @@ -9,4 +9,4 @@ struct acpi_container { int state; }; -#endif /* __ACPI_CONTAINER_H */ +#endif /* __ACPI_CONTAINER_H */ diff --git a/include/acpi/pdc_intel.h b/include/acpi/pdc_intel.h index e72bfdd887f9..c9ac1b911237 100644 --- a/include/acpi/pdc_intel.h +++ b/include/acpi/pdc_intel.h @@ -30,4 +30,4 @@ ACPI_PDC_C_C1_FFH | \ ACPI_PDC_C_C2C3_FFH) -#endif /* __PDC_INTEL_H__ */ +#endif /* __PDC_INTEL_H__ */ diff --git a/include/acpi/platform/acenv.h b/include/acpi/platform/acenv.h index fcd2572e428c..ac6cc1c07d3b 100644 --- a/include/acpi/platform/acenv.h +++ b/include/acpi/platform/acenv.h @@ -197,7 +197,7 @@ #else #define DEBUGGER_THREADING DEBUGGER_MULTI_THREADED #endif -#endif /* !DEBUGGER_THREADING */ +#endif /* !DEBUGGER_THREADING */ /****************************************************************************** * @@ -221,7 +221,7 @@ #include <string.h> #include <ctype.h> -#endif /* ACPI_USE_STANDARD_HEADERS */ +#endif /* ACPI_USE_STANDARD_HEADERS */ /* * We will be linking to the standard Clib functions @@ -269,7 +269,7 @@ #ifndef _VALIST #define _VALIST typedef char *va_list; -#endif /* _VALIST */ +#endif /* _VALIST */ /* * Storage alignment properties @@ -285,7 +285,7 @@ typedef char *va_list; #define va_end(ap) (void) 0 #define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) -#endif /* va_arg */ +#endif /* va_arg */ #define ACPI_STRSTR(s1,s2) acpi_ut_strstr ((s1), (s2)) #define ACPI_STRCHR(s1,c) acpi_ut_strchr ((s1), (c)) @@ -303,7 +303,7 @@ typedef char *va_list; #define ACPI_TOUPPER acpi_ut_to_upper #define ACPI_TOLOWER acpi_ut_to_lower -#endif /* ACPI_USE_SYSTEM_CLIBRARY */ +#endif /* ACPI_USE_SYSTEM_CLIBRARY */ /****************************************************************************** * @@ -344,7 +344,7 @@ typedef char *va_list; #define ACPI_ACQUIRE_GLOBAL_LOCK(Glptr, acq) #define ACPI_RELEASE_GLOBAL_LOCK(Glptr, acq) -#endif /* ACPI_ASM_MACROS */ +#endif /* ACPI_ASM_MACROS */ #ifdef ACPI_APPLICATION @@ -360,4 +360,4 @@ typedef char *va_list; * headers. * *****************************************************************************/ -#endif /* __ACENV_H__ */ +#endif /* __ACENV_H__ */ diff --git a/include/acpi/platform/acgcc.h b/include/acpi/platform/acgcc.h index 8996dba90cd9..95a0ca679800 100644 --- a/include/acpi/platform/acgcc.h +++ b/include/acpi/platform/acgcc.h @@ -62,4 +62,4 @@ */ #define ACPI_UNUSED_VAR __attribute__ ((unused)) -#endif /* __ACGCC_H__ */ +#endif /* __ACGCC_H__ */ diff --git a/include/acpi/platform/aclinux.h b/include/acpi/platform/aclinux.h index 9af464598682..1a10930ef560 100644 --- a/include/acpi/platform/aclinux.h +++ b/include/acpi/platform/aclinux.h @@ -72,7 +72,7 @@ /* Full namespace pathname length limit - arbitrary */ #define ACPI_PATHNAME_MAX 256 -#else /* !__KERNEL__ */ +#else /* !__KERNEL__ */ #include <stdarg.h> #include <string.h> @@ -96,7 +96,7 @@ #endif #define ACPI_FLUSH_CPU_CACHE() -#endif /* __KERNEL__ */ +#endif /* __KERNEL__ */ /* Linux uses GCC */ @@ -122,6 +122,7 @@ static inline void *acpi_os_allocate(acpi_size size) { return kmalloc(size, irqs_disabled()? GFP_ATOMIC : GFP_KERNEL); } + static inline void *acpi_os_allocate_zeroed(acpi_size size) { return kzalloc(size, irqs_disabled()? GFP_ATOMIC : GFP_KERNEL); @@ -137,4 +138,4 @@ static inline void *acpi_os_acquire_object(acpi_cache_t * cache) #define ACPI_ALLOCATE_ZEROED(a) acpi_os_allocate_zeroed(a) #define ACPI_FREE(a) kfree(a) -#endif /* __ACLINUX_H__ */ +#endif /* __ACLINUX_H__ */ diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 06480bcabfdc..1a90506e763a 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -255,7 +255,7 @@ extern void acpi_processor_unregister_performance(struct int acpi_processor_notify_smm(struct module *calling_module); /* for communication between multiple parts of the processor kernel module */ -extern struct acpi_processor *processors[NR_CPUS]; +DECLARE_PER_CPU(struct acpi_processor *, processors); extern struct acpi_processor_errata errata; void arch_acpi_processor_init_pdc(struct acpi_processor *pr); @@ -275,6 +275,7 @@ static inline void acpi_processor_power_init_bm_check(struct flags->bm_check = 1; return; } + static inline int acpi_processor_ffh_cstate_probe(unsigned int cpu, struct acpi_processor_cx *cx, struct acpi_power_register @@ -282,6 +283,7 @@ static inline int acpi_processor_ffh_cstate_probe(unsigned int cpu, { return -1; } + static inline void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cstate) { @@ -300,10 +302,12 @@ static inline void acpi_processor_ppc_init(void) { return; } + static inline void acpi_processor_ppc_exit(void) { return; } + static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr) { static unsigned int printout = 1; @@ -316,9 +320,10 @@ static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr) } return 0; } -#endif /* CONFIG_CPU_FREQ */ +#endif /* CONFIG_CPU_FREQ */ /* in processor_throttling.c */ +int acpi_processor_tstate_has_changed(struct acpi_processor *pr); int acpi_processor_get_throttling_info(struct acpi_processor *pr); extern int acpi_processor_set_throttling(struct acpi_processor *pr, int state); extern struct file_operations acpi_processor_throttling_fops; @@ -329,8 +334,8 @@ int acpi_processor_power_init(struct acpi_processor *pr, int acpi_processor_cst_has_changed(struct acpi_processor *pr); int acpi_processor_power_exit(struct acpi_processor *pr, struct acpi_device *device); -int acpi_processor_suspend(struct acpi_device * device, pm_message_t state); -int acpi_processor_resume(struct acpi_device * device); +int acpi_processor_suspend(struct acpi_device *device, pm_message_t state); +int acpi_processor_resume(struct acpi_device *device); extern struct cpuidle_driver acpi_idle_driver; /* in processor_thermal.c */ @@ -345,6 +350,7 @@ static inline void acpi_thermal_cpufreq_init(void) { return; } + static inline void acpi_thermal_cpufreq_exit(void) { return; diff --git a/include/acpi/reboot.h b/include/acpi/reboot.h index 8857f57e0b78..fb2073c8c9ff 100644 --- a/include/acpi/reboot.h +++ b/include/acpi/reboot.h @@ -6,4 +6,3 @@ #ifndef acpi_reboot # define acpi_reboot() do { } while (0) #endif - diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h deleted file mode 100644 index 1e5a8caca2d1..000000000000 --- a/include/asm-arm/arch-at91/at91_ecc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-arm/arch-at91/at91_ecc.h - * - * Error Corrected Code Controller (ECC) - System peripherals regsters. - * Based on AT91SAM9260 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef AT91_ECC_H -#define AT91_ECC_H - -#define AT91_ECC_CR 0x00 /* Control register */ -#define AT91_ECC_RST (1 << 0) /* Reset parity */ - -#define AT91_ECC_MR 0x04 /* Mode register */ -#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ -#define AT91_ECC_PAGESIZE_528 (0) -#define AT91_ECC_PAGESIZE_1056 (1) -#define AT91_ECC_PAGESIZE_2112 (2) -#define AT91_ECC_PAGESIZE_4224 (3) - -#define AT91_ECC_SR 0x08 /* Status register */ -#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ -#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ -#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ - -#define AT91_ECC_PR 0x0c /* Parity register */ -#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ -#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ - -#define AT91_ECC_NPR 0x10 /* NParity register */ -#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ - -#endif diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index c2b13c280155..2001e81f2267 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -39,10 +39,14 @@ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ @@ -97,6 +101,7 @@ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index bac83adb5050..6f14d9053ac7 100644 --- a/include/asm-arm/arch-at91/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h @@ -118,7 +118,7 @@ #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ +#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */ #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h index a641686b6c3d..ddbd4873c842 100644 --- a/include/asm-arm/arch-at91/at91cap9_matrix.h +++ b/include/asm-arm/arch-at91/at91cap9_matrix.h @@ -106,6 +106,11 @@ #define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ #define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ +#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */ +#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */ +#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */ +#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */ + #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 16d2832f6c0a..622e56f81d42 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -110,6 +110,6 @@ #define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ +#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ #endif diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h index dc189f01c5b3..2070060c4cb0 100644 --- a/include/asm-arm/arch-at91/board.h +++ b/include/asm-arm/arch-at91/board.h @@ -36,6 +36,7 @@ #include <linux/i2c.h> #include <linux/leds.h> #include <linux/spi/spi.h> +#include <linux/usb/atmel_usba_udc.h> /* USB Device */ struct at91_udc_data { @@ -45,6 +46,9 @@ struct at91_udc_data { }; extern void __init at91_add_device_udc(struct at91_udc_data *data); + /* USB High Speed Device */ +extern void __init at91_add_device_usba(struct usba_platform_data *data); + /* Compact Flash */ struct at91_cf_data { u8 irq_pin; /* I/O IRQ */ @@ -85,7 +89,7 @@ struct at91_usbh_data { extern void __init at91_add_device_usbh(struct at91_usbh_data *data); /* NAND / SmartMedia */ -struct at91_nand_data { +struct atmel_nand_data { u8 enable_pin; /* chip enable */ u8 det_pin; /* card detect */ u8 rdy_pin; /* ready/busy */ @@ -94,7 +98,7 @@ struct at91_nand_data { u8 bus_width_16; /* buswidth is 16 bit */ struct mtd_partition* (*partition_info)(int, int*); }; -extern void __init at91_add_device_nand(struct at91_nand_data *data); +extern void __init at91_add_device_nand(struct atmel_nand_data *data); /* I2C*/ extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index 80073fd36b8e..f8beaa228467 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h @@ -21,8 +21,6 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#include <asm/io.h> - #define IO_SPACE_LIMIT 0xFFFFFFFF #define __io(a) ((void __iomem *)(a)) diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index f1933b0fa43f..6e084eb839d9 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -27,14 +27,29 @@ #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) -#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) +#elif defined(CONFIG_ARCH_AT91SAM9260) + +#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260) +#define AT91SAM9_MASTER_CLOCK 90000000 +#else +#define AT91SAM9_MASTER_CLOCK 99300000 +#endif + +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) + +#elif defined(CONFIG_ARCH_AT91SAM9261) #define AT91SAM9_MASTER_CLOCK 99300000 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) #elif defined(CONFIG_ARCH_AT91SAM9263) +#if defined(CONFIG_MACH_USB_A9263) +#define AT91SAM9_MASTER_CLOCK 90000000 +#else #define AT91SAM9_MASTER_CLOCK 99959500 +#endif + #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) #elif defined(CONFIG_ARCH_AT91SAM9RL) diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h index daad8ee2d194..74610c2c63d4 100644 --- a/include/asm-arm/arch-ebsa285/hardware.h +++ b/include/asm-arm/arch-ebsa285/hardware.h @@ -14,7 +14,6 @@ #include <asm/arch/memory.h> -#ifdef CONFIG_ARCH_FOOTBRIDGE /* Virtual Physical Size * 0xff800000 0x40000000 1MB X-Bus * 0xff000000 0x7c000000 1MB PCI I/O space @@ -50,31 +49,6 @@ #define PCIMEM_SIZE 0x01000000 #define PCIMEM_BASE 0xf0000000 -#elif defined(CONFIG_ARCH_CO285) -/* - * This is the COEBSA285 cut-down mapping - */ -#define PCIMEM_SIZE 0x80000000 -#define PCIMEM_BASE 0x80000000 - -#define WFLUSH_SIZE 0x01000000 -#define WFLUSH_BASE 0x7d000000 - -#define ARMCSR_SIZE 0x00100000 -#define ARMCSR_BASE 0x7cf00000 - -#define XBUS_SIZE 0x00020000 -#define XBUS_BASE 0x7cee0000 - -#define PCIO_SIZE 0x00010000 -#define PCIO_BASE 0x7ced0000 - -#else - -#error "Undefined footbridge architecture" - -#endif - #define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) #define XBUS_LED_AMBER (1 << 0) #define XBUS_LED_GREEN (1 << 1) diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h index cbd7ae64bcc9..9019a3bf5ab9 100644 --- a/include/asm-arm/arch-ebsa285/memory.h +++ b/include/asm-arm/arch-ebsa285/memory.h @@ -42,8 +42,6 @@ extern unsigned long __bus_to_virt(unsigned long); #endif -#if defined(CONFIG_ARCH_FOOTBRIDGE) - /* Task size and page offset at 3GB */ #define TASK_SIZE UL(0xbf000000) #define PAGE_OFFSET UL(0xc0000000) @@ -53,23 +51,6 @@ extern unsigned long __bus_to_virt(unsigned long); */ #define FLUSH_BASE 0xf9000000 -#elif defined(CONFIG_ARCH_CO285) - -/* Task size and page offset at 1.5GB */ -#define TASK_SIZE UL(0x5f000000) -#define PAGE_OFFSET UL(0x60000000) - -/* - * Cache flushing area. - */ -#define FLUSH_BASE 0x7e000000 - -#else - -#error "Undefined footbridge architecture" - -#endif - /* * Physical DRAM offset. */ diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h index 02598200997d..e487d7e8c8a6 100644 --- a/include/asm-arm/arch-ebsa285/vmalloc.h +++ b/include/asm-arm/arch-ebsa285/vmalloc.h @@ -7,8 +7,4 @@ */ -#ifdef CONFIG_ARCH_FOOTBRIDGE #define VMALLOC_END (PAGE_OFFSET + 0x30000000) -#else -#define VMALLOC_END (PAGE_OFFSET + 0x20000000) -#endif diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h new file mode 100644 index 000000000000..c0100cc7981c --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/fsg.h @@ -0,0 +1,50 @@ +/* + * include/asm-arm/arch-ixp4xx/fsg.h + * + * Freecom FSG-3 platform specific definitions + * + * Author: Rod Whitby <rod@whitby.id.au> + * Author: Tomasz Chmielewski <mangoo@wpkg.org> + * Maintainers: http://www.nslu2-linux.org + * + * Based on coyote.h by + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include <asm/hardware.h>" +#endif + +#define FSG_SDA_PIN 12 +#define FSG_SCL_PIN 13 + +/* + * FSG PCI IRQs + */ +#define FSG_PCI_MAX_DEV 3 +#define FSG_PCI_IRQ_LINES 3 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define FSG_PCI_INTA_PIN 6 +#define FSG_PCI_INTB_PIN 7 +#define FSG_PCI_INTC_PIN 5 + +/* Buttons */ + +#define FSG_SB_GPIO 4 /* sync button */ +#define FSG_RB_GPIO 9 /* reset button */ +#define FSG_UB_GPIO 10 /* usb button */ + +/* LEDs */ + +#define FSG_LED_WLAN_BIT 0 +#define FSG_LED_WAN_BIT 1 +#define FSG_LED_SATA_BIT 2 +#define FSG_LED_USB_BIT 4 +#define FSG_LED_RING_BIT 5 +#define FSG_LED_SYNC_BIT 7 diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h index 73e8dc36f6a4..fa723a627854 100644 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ b/include/asm-arm/arch-ixp4xx/hardware.h @@ -45,5 +45,6 @@ #include "nslu2.h" #include "nas100d.h" #include "dsmg600.h" +#include "fsg.h" #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h index 11801605047b..674af4a84147 100644 --- a/include/asm-arm/arch-ixp4xx/irqs.h +++ b/include/asm-arm/arch-ixp4xx/irqs.h @@ -128,4 +128,11 @@ #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 +/* + * Freecom FSG-3 Board IRQs + */ +#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 +#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 +#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 + #endif diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h index 0b7b34603f1c..0dca11ce21fc 100644 --- a/include/asm-arm/arch-ns9xxx/hardware.h +++ b/include/asm-arm/arch-ns9xxx/hardware.h @@ -66,13 +66,13 @@ __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) # define REGGETIM_IDX(var, reg, field, idx) \ - __REGGET(var, reg ## _ ## field((idx))) / \ + __REGGET(var, reg ## _ ## field((idx))) / \ __REGSHIFT(reg ## _ ## field((idx))) #else # define __REG(x) io_p2v(x) -# define __REG2(x, y) io_p2v((x) + (y)) +# define __REG2(x, y) io_p2v((x) + 4 * (y)) #endif diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h index 52bbe3bc25e1..f82f96dd1053 100644 --- a/include/asm-arm/arch-pxa/audio.h +++ b/include/asm-arm/arch-pxa/audio.h @@ -12,4 +12,6 @@ typedef struct { void *priv; } pxa2xx_audio_ops_t; +extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); + #endif diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index e25558faa5a4..de1210390b0a 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -192,18 +192,14 @@ extern int pxa_gpio_get_value(unsigned gpio); extern void pxa_gpio_set_value(unsigned gpio, int value); /* - * Routine to enable or disable CKEN + * return current memory and LCD clock frequency in units of 10kHz */ -static inline void __deprecated pxa_set_cken(int clock, int enable) -{ - extern void __pxa_set_cken(int clock, int enable); - __pxa_set_cken(clock, enable); -} +extern unsigned int get_memclk_frequency_10khz(void); /* - * return current memory and LCD clock frequency in units of 10kHz + * register GPIO as reset generator */ -extern unsigned int get_memclk_frequency_10khz(void); +extern int init_gpio_reset(int gpio); #endif diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index b6c8fe377683..fa05e76f64e8 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -180,6 +180,7 @@ #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) #elif defined(CONFIG_ARCH_LUBBOCK) || \ defined(CONFIG_MACH_LOGICPD_PXA270) || \ + defined(CONFIG_MACH_TOSA) || \ defined(CONFIG_MACH_MAINSTONE) || \ defined(CONFIG_MACH_PCM027) || \ defined(CONFIG_MACH_MAGICIAN) diff --git a/include/asm-arm/arch-pxa/mfp-pxa27x.h b/include/asm-arm/arch-pxa/mfp-pxa27x.h index eb6eaa174f8d..bc73ab84167c 100644 --- a/include/asm-arm/arch-pxa/mfp-pxa27x.h +++ b/include/asm-arm/arch-pxa/mfp-pxa27x.h @@ -112,6 +112,7 @@ #define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) #define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) #define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) +#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH) /* I2C */ #define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 4b2ea1e95c57..dce9308626b7 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -600,418 +600,6 @@ /* - * USB Device Controller - * PXA25x and PXA27x USB device controller registers are different. - */ -#if defined(CONFIG_PXA25x) - -#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ -#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ -#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ - -#define UDCCR __REG(0x40600000) /* UDC Control Register */ -#define UDCCR_UDE (1 << 0) /* UDC enable */ -#define UDCCR_UDA (1 << 1) /* UDC active */ -#define UDCCR_RSM (1 << 2) /* Device resume */ -#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ -#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ -#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ -#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ -#define UDCCR_REM (1 << 7) /* Reset interrupt mask */ - -#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ -#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ -#define UDCCS0_IPR (1 << 1) /* IN packet ready */ -#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ -#define UDCCS0_SST (1 << 4) /* Sent stall */ -#define UDCCS0_FST (1 << 5) /* Force stall */ -#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ -#define UDCCS0_SA (1 << 7) /* Setup active */ - -/* Bulk IN - Endpoint 1,6,11 */ -#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ -#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ -#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ - -#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_BI_SST (1 << 4) /* Sent stall */ -#define UDCCS_BI_FST (1 << 5) /* Force stall */ -#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ - -/* Bulk OUT - Endpoint 2,7,12 */ -#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ -#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ -#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ - -#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_BO_DME (1 << 3) /* DMA enable */ -#define UDCCS_BO_SST (1 << 4) /* Sent stall */ -#define UDCCS_BO_FST (1 << 5) /* Force stall */ -#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ - -/* Isochronous IN - Endpoint 3,8,13 */ -#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ -#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ -#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ - -#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ - -/* Isochronous OUT - Endpoint 4,9,14 */ -#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ -#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ -#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ - -#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ -#define UDCCS_IO_DME (1 << 3) /* DMA enable */ -#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ - -/* Interrupt IN - Endpoint 5,10,15 */ -#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ -#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ -#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ - -#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_INT_SST (1 << 4) /* Sent stall */ -#define UDCCS_INT_FST (1 << 5) /* Force stall */ -#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ - -#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ -#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ -#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ -#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ -#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ -#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ -#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ -#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ -#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ -#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ -#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ -#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ -#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ -#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ -#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ -#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ -#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ -#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ -#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ -#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ -#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ -#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ -#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ -#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ - -#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ - -#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ -#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ -#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ -#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ -#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ -#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ -#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ -#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ - -#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ - -#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ -#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ -#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ -#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ -#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ -#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ -#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ -#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ - -#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ - -#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ -#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ -#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ -#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ -#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ -#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ -#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ -#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ - -#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ - -#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ -#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ -#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ -#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ -#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ -#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ -#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ -#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ - -#elif defined(CONFIG_PXA27x) - -#define UDCCR __REG(0x40600000) /* UDC Control Register */ -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation - Protocol Port Support */ -#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol - Support */ -#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol - Enable */ -#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ -#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ -#define UDCCR_ACN_S 11 -#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ -#define UDCCR_AIN_S 8 -#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface - Setting Number */ -#define UDCCR_AAISN_S 5 -#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active - Configuration */ -#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration - Error */ -#define UDCCR_UDR (1 << 2) /* UDC Resume */ -#define UDCCR_UDA (1 << 1) /* UDC Active */ -#define UDCCR_UDE (1 << 0) /* UDC Enable */ - -#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ -#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ -#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ -#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ - -#define UDC_INT_FIFOERROR (0x2) -#define UDC_INT_PACKETCMP (0x1) - -#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ -#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ -#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ -#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ - -#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ -#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ -#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ -#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ -#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ -#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ -#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ - -#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ -#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ -#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ -#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt - Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt - Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge - Interrupt Enable */ -#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge - Interrupt Enable */ -#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge - Interrupt Enable */ -#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge - Interrupt Enable */ -#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge - Interrupt Enable */ -#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge - Interrupt Enable */ -#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising - Edge Interrupt Enable */ -#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling - Edge Interrupt Enable */ -#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge - Interrupt Enable */ -#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge - Interrupt Enable */ - -#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ - -#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ -#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ -#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ -#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ -#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ -#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ -#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ -#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ -#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ -#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ -#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ -#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ -#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ -#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ - -#define UDCCSN(x) __REG2(0x40600100, (x) << 2) -#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ -#define UDCCSR0_SA (1 << 7) /* Setup Active */ -#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ -#define UDCCSR0_FST (1 << 5) /* Force Stall */ -#define UDCCSR0_SST (1 << 4) /* Sent Stall */ -#define UDCCSR0_DME (1 << 3) /* DMA Enable */ -#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ -#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ -#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ - -#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ -#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ -#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ -#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ -#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ -#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ -#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ -#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ -#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ -#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ -#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ -#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ -#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ -#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ -#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ -#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ -#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ -#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ -#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ -#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ -#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ -#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ -#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ - -#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ -#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ -#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ -#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ -#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ -#define UDCCSR_FST (1 << 5) /* Force STALL */ -#define UDCCSR_SST (1 << 4) /* Sent STALL */ -#define UDCCSR_DME (1 << 3) /* DMA Enable */ -#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ -#define UDCCSR_PC (1 << 1) /* Packet Complete */ -#define UDCCSR_FS (1 << 0) /* FIFO needs service */ - -#define UDCBCN(x) __REG2(0x40600200, (x)<<2) -#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ -#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ -#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ -#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ -#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ -#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ -#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ -#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ -#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ -#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ -#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ -#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ -#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ -#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ -#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ -#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ -#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ -#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ -#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ -#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ -#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ -#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ -#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ -#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ - -#define UDCDN(x) __REG2(0x40600300, (x)<<2) -#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) -#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) -#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ -#define UDCDRA __REG(0x40600304) /* Data Register - EPA */ -#define UDCDRB __REG(0x40600308) /* Data Register - EPB */ -#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ -#define UDCDRD __REG(0x40600310) /* Data Register - EPD */ -#define UDCDRE __REG(0x40600314) /* Data Register - EPE */ -#define UDCDRF __REG(0x40600318) /* Data Register - EPF */ -#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ -#define UDCDRH __REG(0x40600320) /* Data Register - EPH */ -#define UDCDRI __REG(0x40600324) /* Data Register - EPI */ -#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ -#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ -#define UDCDRL __REG(0x40600330) /* Data Register - EPL */ -#define UDCDRM __REG(0x40600334) /* Data Register - EPM */ -#define UDCDRN __REG(0x40600338) /* Data Register - EPN */ -#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ -#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ -#define UDCDRR __REG(0x40600344) /* Data Register - EPR */ -#define UDCDRS __REG(0x40600348) /* Data Register - EPS */ -#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ -#define UDCDRU __REG(0x40600350) /* Data Register - EPU */ -#define UDCDRV __REG(0x40600354) /* Data Register - EPV */ -#define UDCDRW __REG(0x40600358) /* Data Register - EPW */ -#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ - -#define UDCCN(x) __REG2(0x40600400, (x)<<2) -#define UDCCRA __REG(0x40600404) /* Configuration register EPA */ -#define UDCCRB __REG(0x40600408) /* Configuration register EPB */ -#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ -#define UDCCRD __REG(0x40600410) /* Configuration register EPD */ -#define UDCCRE __REG(0x40600414) /* Configuration register EPE */ -#define UDCCRF __REG(0x40600418) /* Configuration register EPF */ -#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ -#define UDCCRH __REG(0x40600420) /* Configuration register EPH */ -#define UDCCRI __REG(0x40600424) /* Configuration register EPI */ -#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ -#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ -#define UDCCRL __REG(0x40600430) /* Configuration register EPL */ -#define UDCCRM __REG(0x40600434) /* Configuration register EPM */ -#define UDCCRN __REG(0x40600438) /* Configuration register EPN */ -#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ -#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ -#define UDCCRR __REG(0x40600444) /* Configuration register EPR */ -#define UDCCRS __REG(0x40600448) /* Configuration register EPS */ -#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ -#define UDCCRU __REG(0x40600450) /* Configuration register EPU */ -#define UDCCRV __REG(0x40600454) /* Configuration register EPV */ -#define UDCCRW __REG(0x40600458) /* Configuration register EPW */ -#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ - -#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ -#define UDCCONR_CN_S (25) -#define UDCCONR_IN (0x07 << 22) /* Interface Number */ -#define UDCCONR_IN_S (22) -#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ -#define UDCCONR_AISN_S (19) -#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ -#define UDCCONR_EN_S (15) -#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ -#define UDCCONR_ET_S (13) -#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ -#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ -#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ -#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ -#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ -#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ -#define UDCCONR_MPS_S (2) -#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ -#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ - - -#define UDC_INT_FIFOERROR (0x2) -#define UDC_INT_PACKETCMP (0x1) - -#define UDC_FNR_MASK (0x7ff) - -#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) -#define UDC_BCR_MASK (0x3ff) -#endif - -/* * Fast Infrared Communication Port */ @@ -1237,120 +825,9 @@ #endif /* - * Power Manager + * Power Manager - see pxa2xx-regs.h */ -#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ -#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ -#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ -#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ -#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ -#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ - -#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ -#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */ -#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */ -#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ -#define PCMD(x) __REG2(0x40F00080, (x)<<2) -#define PCMD0 __REG(0x40F00080 + 0 * 4) -#define PCMD1 __REG(0x40F00080 + 1 * 4) -#define PCMD2 __REG(0x40F00080 + 2 * 4) -#define PCMD3 __REG(0x40F00080 + 3 * 4) -#define PCMD4 __REG(0x40F00080 + 4 * 4) -#define PCMD5 __REG(0x40F00080 + 5 * 4) -#define PCMD6 __REG(0x40F00080 + 6 * 4) -#define PCMD7 __REG(0x40F00080 + 7 * 4) -#define PCMD8 __REG(0x40F00080 + 8 * 4) -#define PCMD9 __REG(0x40F00080 + 9 * 4) -#define PCMD10 __REG(0x40F00080 + 10 * 4) -#define PCMD11 __REG(0x40F00080 + 11 * 4) -#define PCMD12 __REG(0x40F00080 + 12 * 4) -#define PCMD13 __REG(0x40F00080 + 13 * 4) -#define PCMD14 __REG(0x40F00080 + 14 * 4) -#define PCMD15 __REG(0x40F00080 + 15 * 4) -#define PCMD16 __REG(0x40F00080 + 16 * 4) -#define PCMD17 __REG(0x40F00080 + 17 * 4) -#define PCMD18 __REG(0x40F00080 + 18 * 4) -#define PCMD19 __REG(0x40F00080 + 19 * 4) -#define PCMD20 __REG(0x40F00080 + 20 * 4) -#define PCMD21 __REG(0x40F00080 + 21 * 4) -#define PCMD22 __REG(0x40F00080 + 22 * 4) -#define PCMD23 __REG(0x40F00080 + 23 * 4) -#define PCMD24 __REG(0x40F00080 + 24 * 4) -#define PCMD25 __REG(0x40F00080 + 25 * 4) -#define PCMD26 __REG(0x40F00080 + 26 * 4) -#define PCMD27 __REG(0x40F00080 + 27 * 4) -#define PCMD28 __REG(0x40F00080 + 28 * 4) -#define PCMD29 __REG(0x40F00080 + 29 * 4) -#define PCMD30 __REG(0x40F00080 + 30 * 4) -#define PCMD31 __REG(0x40F00080 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -/* FIXME: PCMD_SQC need be checked. */ -#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, - bit 9 should be 0 all day. */ -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -#define PCFR_PI2C_EN (0x1 << 6) - -#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_STS (1 << 3) /* Standby Mode Status */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ - -#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ - -#define PCFR_RO (1 << 15) /* RDH Override */ -#define PCFR_PO (1 << 14) /* PH Override */ -#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ -#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ -#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ -#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ -#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ -#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ - -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ - -#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ -#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ -#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ -#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ -#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ -#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ -#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ -#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ -#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ -#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ -#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ -#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ -#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ -#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ -#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ -#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ -#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ -#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ - /* * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h */ @@ -1360,52 +837,9 @@ */ /* - * Core Clock + * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h */ -#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ -#define CKEN __REG(0x41300004) /* Clock Enable Register */ -#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ -#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ - -#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ -#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ -#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ -#define CKEN_MEMC (22) /* Memory Controller Clock Enable */ -#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ -#define CKEN_IM (20) /* Internal Memory Clock Enable */ -#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ -#define CKEN_USIM (18) /* USIM Unit Clock Enable */ -#define CKEN_MSL (17) /* MSL Unit Clock Enable */ -#define CKEN_LCD (16) /* LCD Unit Clock Enable */ -#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ -#define CKEN_I2C (14) /* I2C Unit Clock Enable */ -#define CKEN_FICP (13) /* FICP Unit Clock Enable */ -#define CKEN_MMC (12) /* MMC Unit Clock Enable */ -#define CKEN_USB (11) /* USB Unit Clock Enable */ -#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ -#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ -#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ -#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ -#define CKEN_I2S (8) /* I2S Unit Clock Enable */ -#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ -#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ -#define CKEN_STUART (5) /* STUART Unit Clock Enable */ -#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ -#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ -#define CKEN_SSP (3) /* SSP Unit Clock Enable */ -#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ -#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ -#define CKEN_PWM1 (1) /* PWM1 Clock Enable */ -#define CKEN_PWM0 (0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - #ifdef CONFIG_PXA27x /* Camera Interface */ diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h new file mode 100644 index 000000000000..840305916b6d --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa25x-udc.h @@ -0,0 +1,163 @@ +#ifndef _ASM_ARCH_PXA25X_UDC_H +#define _ASM_ARCH_PXA25X_UDC_H + +#ifdef _ASM_ARCH_PXA27X_UDC_H +#error You can't include both PXA25x and PXA27x UDC support +#endif + +#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ +#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ +#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ + +#define UDCCR __REG(0x40600000) /* UDC Control Register */ +#define UDCCR_UDE (1 << 0) /* UDC enable */ +#define UDCCR_UDA (1 << 1) /* UDC active */ +#define UDCCR_RSM (1 << 2) /* Device resume */ +#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ +#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ +#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ +#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ +#define UDCCR_REM (1 << 7) /* Reset interrupt mask */ + +#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ +#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ +#define UDCCS0_IPR (1 << 1) /* IN packet ready */ +#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ +#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ +#define UDCCS0_SST (1 << 4) /* Sent stall */ +#define UDCCS0_FST (1 << 5) /* Force stall */ +#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ +#define UDCCS0_SA (1 << 7) /* Setup active */ + +/* Bulk IN - Endpoint 1,6,11 */ +#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ +#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ +#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ + +#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ +#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ +#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ +#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ +#define UDCCS_BI_SST (1 << 4) /* Sent stall */ +#define UDCCS_BI_FST (1 << 5) /* Force stall */ +#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ + +/* Bulk OUT - Endpoint 2,7,12 */ +#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ +#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ +#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ + +#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ +#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ +#define UDCCS_BO_DME (1 << 3) /* DMA enable */ +#define UDCCS_BO_SST (1 << 4) /* Sent stall */ +#define UDCCS_BO_FST (1 << 5) /* Force stall */ +#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ +#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ + +/* Isochronous IN - Endpoint 3,8,13 */ +#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ +#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ +#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ + +#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ +#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ +#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ +#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ +#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ + +/* Isochronous OUT - Endpoint 4,9,14 */ +#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ +#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ +#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ + +#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ +#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ +#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ +#define UDCCS_IO_DME (1 << 3) /* DMA enable */ +#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ +#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ + +/* Interrupt IN - Endpoint 5,10,15 */ +#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ +#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ +#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ + +#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ +#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ +#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ +#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ +#define UDCCS_INT_SST (1 << 4) /* Sent stall */ +#define UDCCS_INT_FST (1 << 5) /* Force stall */ +#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ + +#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ +#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ +#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ +#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ +#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ +#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ +#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ +#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ +#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ +#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ +#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ +#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ +#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ +#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ +#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ +#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ +#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ +#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ +#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ +#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ +#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ +#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ +#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ +#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ + +#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ + +#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ +#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ +#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ +#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ +#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ +#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ +#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ +#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ + +#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ + +#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ +#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ +#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ +#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ +#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ +#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ +#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ +#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ + +#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ + +#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ +#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ +#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ +#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ +#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ +#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ +#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ +#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ + +#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ + +#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ +#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ +#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ +#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ +#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ +#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ +#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ +#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ + +#endif diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h new file mode 100644 index 000000000000..bc1cf7d0773a --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa27x-udc.h @@ -0,0 +1,257 @@ +#ifndef _ASM_ARCH_PXA27X_UDC_H +#define _ASM_ARCH_PXA27X_UDC_H + +#ifdef _ASM_ARCH_PXA25X_UDC_H +#error You cannot include both PXA25x and PXA27x UDC support +#endif + +#define UDCCR __REG(0x40600000) /* UDC Control Register */ +#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ +#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation + Protocol Port Support */ +#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol + Support */ +#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol + Enable */ +#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ +#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ +#define UDCCR_ACN_S 11 +#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ +#define UDCCR_AIN_S 8 +#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface + Setting Number */ +#define UDCCR_AAISN_S 5 +#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active + Configuration */ +#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration + Error */ +#define UDCCR_UDR (1 << 2) /* UDC Resume */ +#define UDCCR_UDA (1 << 1) /* UDC Active */ +#define UDCCR_UDE (1 << 0) /* UDC Enable */ + +#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ +#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ +#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ +#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ + +#define UDC_INT_FIFOERROR (0x2) +#define UDC_INT_PACKETCMP (0x1) + +#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) +#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ +#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ +#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ +#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ +#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ + +#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ +#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ +#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) +#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ +#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ +#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ +#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ +#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ + +#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ +#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ +#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ +#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt + Rising Edge Interrupt Enable */ +#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt + Falling Edge Interrupt Enable */ +#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising + Edge Interrupt Enable */ +#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling + Edge Interrupt Enable */ +#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge + Interrupt Enable */ + +#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ +#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */ + +#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ +#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ +#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ +#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ +#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ +#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ +#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ +#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ +#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ +#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ +#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ +#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ +#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ +#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ + +#define UDCCSN(x) __REG2(0x40600100, (x) << 2) +#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ +#define UDCCSR0_SA (1 << 7) /* Setup Active */ +#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define UDCCSR0_FST (1 << 5) /* Force Stall */ +#define UDCCSR0_SST (1 << 4) /* Sent Stall */ +#define UDCCSR0_DME (1 << 3) /* DMA Enable */ +#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ +#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ +#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ +#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ +#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ +#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ +#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ +#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ +#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ +#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ +#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ +#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ +#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ +#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ +#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ +#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ +#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ +#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ +#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ +#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ +#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ +#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ +#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ + +#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ +#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ +#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ +#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ +#define UDCCSR_FST (1 << 5) /* Force STALL */ +#define UDCCSR_SST (1 << 4) /* Sent STALL */ +#define UDCCSR_DME (1 << 3) /* DMA Enable */ +#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ +#define UDCCSR_PC (1 << 1) /* Packet Complete */ +#define UDCCSR_FS (1 << 0) /* FIFO needs service */ + +#define UDCBCN(x) __REG2(0x40600200, (x)<<2) +#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ +#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ +#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ +#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ +#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ +#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ +#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ +#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ +#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ +#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ +#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ +#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ +#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ +#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ +#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ +#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ +#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ +#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ +#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ +#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ +#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ +#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ +#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ +#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ + +#define UDCDN(x) __REG2(0x40600300, (x)<<2) +#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) +#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) +#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ +#define UDCDRA __REG(0x40600304) /* Data Register - EPA */ +#define UDCDRB __REG(0x40600308) /* Data Register - EPB */ +#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ +#define UDCDRD __REG(0x40600310) /* Data Register - EPD */ +#define UDCDRE __REG(0x40600314) /* Data Register - EPE */ +#define UDCDRF __REG(0x40600318) /* Data Register - EPF */ +#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ +#define UDCDRH __REG(0x40600320) /* Data Register - EPH */ +#define UDCDRI __REG(0x40600324) /* Data Register - EPI */ +#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ +#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ +#define UDCDRL __REG(0x40600330) /* Data Register - EPL */ +#define UDCDRM __REG(0x40600334) /* Data Register - EPM */ +#define UDCDRN __REG(0x40600338) /* Data Register - EPN */ +#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ +#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ +#define UDCDRR __REG(0x40600344) /* Data Register - EPR */ +#define UDCDRS __REG(0x40600348) /* Data Register - EPS */ +#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ +#define UDCDRU __REG(0x40600350) /* Data Register - EPU */ +#define UDCDRV __REG(0x40600354) /* Data Register - EPV */ +#define UDCDRW __REG(0x40600358) /* Data Register - EPW */ +#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ + +#define UDCCN(x) __REG2(0x40600400, (x)<<2) +#define UDCCRA __REG(0x40600404) /* Configuration register EPA */ +#define UDCCRB __REG(0x40600408) /* Configuration register EPB */ +#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ +#define UDCCRD __REG(0x40600410) /* Configuration register EPD */ +#define UDCCRE __REG(0x40600414) /* Configuration register EPE */ +#define UDCCRF __REG(0x40600418) /* Configuration register EPF */ +#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ +#define UDCCRH __REG(0x40600420) /* Configuration register EPH */ +#define UDCCRI __REG(0x40600424) /* Configuration register EPI */ +#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ +#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ +#define UDCCRL __REG(0x40600430) /* Configuration register EPL */ +#define UDCCRM __REG(0x40600434) /* Configuration register EPM */ +#define UDCCRN __REG(0x40600438) /* Configuration register EPN */ +#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ +#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ +#define UDCCRR __REG(0x40600444) /* Configuration register EPR */ +#define UDCCRS __REG(0x40600448) /* Configuration register EPS */ +#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ +#define UDCCRU __REG(0x40600450) /* Configuration register EPU */ +#define UDCCRV __REG(0x40600454) /* Configuration register EPV */ +#define UDCCRW __REG(0x40600458) /* Configuration register EPW */ +#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ + +#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ +#define UDCCONR_CN_S (25) +#define UDCCONR_IN (0x07 << 22) /* Interface Number */ +#define UDCCONR_IN_S (22) +#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ +#define UDCCONR_AISN_S (19) +#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ +#define UDCCONR_EN_S (15) +#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ +#define UDCCONR_ET_S (13) +#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ +#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ +#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ +#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ +#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ +#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ +#define UDCCONR_MPS_S (2) +#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ +#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ + + +#define UDC_INT_FIFOERROR (0x2) +#define UDC_INT_PACKETCMP (0x1) + +#define UDC_FNR_MASK (0x7ff) + +#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) +#define UDC_BCR_MASK (0x3ff) + +#endif diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h index 763313c5e6be..6ef1dd09970b 100644 --- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h +++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARCH_PXA2XX_GPIO_H #define __ASM_ARCH_PXA2XX_GPIO_H +#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h + /* GPIO alternate function assignments */ #define GPIO1_RST 1 /* reset */ @@ -134,7 +136,11 @@ #define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */ #define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */ #define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */ +#define GPIO96_FFRXD 96 /* FFUART recieve */ +#define GPIO98_FFRTS 98 /* FFUART request to send */ #define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */ +#define GPIO99_FFTXD 99 /* FFUART transmit data */ +#define GPIO100_FFCTS 100 /* FFUART Clear to send */ #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ #define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */ #define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */ @@ -316,6 +322,8 @@ #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) #define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) #define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) +#define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN) +#define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT) #define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN) #define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN) #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) @@ -324,8 +332,11 @@ #define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN) #define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) #define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) +#define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN) #define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) #define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN) +#define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT) +#define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT) #define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) #define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h index 9553b54fa5bc..73e0a329cf7f 100644 --- a/include/asm-arm/arch-pxa/pxa2xx-regs.h +++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h @@ -81,4 +81,166 @@ #endif + +/* + * Power Manager + */ + +#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ +#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ +#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ +#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ +#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ +#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ +#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ +#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ +#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ +#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ +#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ +#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ +#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ + +#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ +#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ +#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ +#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ +#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ +#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ +#define PCMD(x) __REG2(0x40F00080, (x)<<2) +#define PCMD0 __REG(0x40F00080 + 0 * 4) +#define PCMD1 __REG(0x40F00080 + 1 * 4) +#define PCMD2 __REG(0x40F00080 + 2 * 4) +#define PCMD3 __REG(0x40F00080 + 3 * 4) +#define PCMD4 __REG(0x40F00080 + 4 * 4) +#define PCMD5 __REG(0x40F00080 + 5 * 4) +#define PCMD6 __REG(0x40F00080 + 6 * 4) +#define PCMD7 __REG(0x40F00080 + 7 * 4) +#define PCMD8 __REG(0x40F00080 + 8 * 4) +#define PCMD9 __REG(0x40F00080 + 9 * 4) +#define PCMD10 __REG(0x40F00080 + 10 * 4) +#define PCMD11 __REG(0x40F00080 + 11 * 4) +#define PCMD12 __REG(0x40F00080 + 12 * 4) +#define PCMD13 __REG(0x40F00080 + 13 * 4) +#define PCMD14 __REG(0x40F00080 + 14 * 4) +#define PCMD15 __REG(0x40F00080 + 15 * 4) +#define PCMD16 __REG(0x40F00080 + 16 * 4) +#define PCMD17 __REG(0x40F00080 + 17 * 4) +#define PCMD18 __REG(0x40F00080 + 18 * 4) +#define PCMD19 __REG(0x40F00080 + 19 * 4) +#define PCMD20 __REG(0x40F00080 + 20 * 4) +#define PCMD21 __REG(0x40F00080 + 21 * 4) +#define PCMD22 __REG(0x40F00080 + 22 * 4) +#define PCMD23 __REG(0x40F00080 + 23 * 4) +#define PCMD24 __REG(0x40F00080 + 24 * 4) +#define PCMD25 __REG(0x40F00080 + 25 * 4) +#define PCMD26 __REG(0x40F00080 + 26 * 4) +#define PCMD27 __REG(0x40F00080 + 27 * 4) +#define PCMD28 __REG(0x40F00080 + 28 * 4) +#define PCMD29 __REG(0x40F00080 + 29 * 4) +#define PCMD30 __REG(0x40F00080 + 30 * 4) +#define PCMD31 __REG(0x40F00080 + 31 * 4) + +#define PCMD_MBC (1<<12) +#define PCMD_DCE (1<<11) +#define PCMD_LC (1<<10) +/* FIXME: PCMD_SQC need be checked. */ +#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, + bit 9 should be 0 all day. */ +#define PVCR_VCSA (0x1<<14) +#define PVCR_CommandDelay (0xf80) +#define PCFR_PI2C_EN (0x1 << 6) + +#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ +#define PSSR_RDH (1 << 5) /* Read Disable Hold */ +#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ +#define PSSR_STS (1 << 3) /* Standby Mode Status */ +#define PSSR_VFS (1 << 2) /* VDD Fault Status */ +#define PSSR_BFS (1 << 1) /* Battery Fault Status */ +#define PSSR_SSS (1 << 0) /* Software Sleep Status */ + +#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ + +#define PCFR_RO (1 << 15) /* RDH Override */ +#define PCFR_PO (1 << 14) /* PH Override */ +#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ +#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ +#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ +#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ +#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ +#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ +#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ +#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ +#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ +#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ + +#define RCSR_GPR (1 << 3) /* GPIO Reset */ +#define RCSR_SMR (1 << 2) /* Sleep Mode */ +#define RCSR_WDR (1 << 1) /* Watchdog Reset */ +#define RCSR_HWR (1 << 0) /* Hardware Reset */ + +#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ +#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ +#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ +#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ +#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ +#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ +#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ +#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ +#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ +#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ +#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ +#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ +#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ +#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ +#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ +#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ +#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ +#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ + +/* + * PXA2xx specific Core clock definitions + */ +#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ +#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ +#define CKEN __REG(0x41300004) /* Clock Enable Register */ +#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ + +#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ +#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ + +#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ +#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ +#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ +#define CKEN_MEMC (22) /* Memory Controller Clock Enable */ +#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ +#define CKEN_IM (20) /* Internal Memory Clock Enable */ +#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ +#define CKEN_USIM (18) /* USIM Unit Clock Enable */ +#define CKEN_MSL (17) /* MSL Unit Clock Enable */ +#define CKEN_LCD (16) /* LCD Unit Clock Enable */ +#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ +#define CKEN_I2C (14) /* I2C Unit Clock Enable */ +#define CKEN_FICP (13) /* FICP Unit Clock Enable */ +#define CKEN_MMC (12) /* MMC Unit Clock Enable */ +#define CKEN_USB (11) /* USB Unit Clock Enable */ +#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ +#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ +#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ +#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ +#define CKEN_I2S (8) /* I2S Unit Clock Enable */ +#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ +#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ +#define CKEN_STUART (5) /* STUART Unit Clock Enable */ +#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ +#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ +#define CKEN_SSP (3) /* SSP Unit Clock Enable */ +#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ +#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ +#define CKEN_PWM1 (1) /* PWM1 Clock Enable */ +#define CKEN_PWM0 (0) /* PWM0 Clock Enable */ + +#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ +#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ + #endif diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h index 3459fb26ce97..2206cb61a9f9 100644 --- a/include/asm-arm/arch-pxa/pxa2xx_spi.h +++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h @@ -41,4 +41,6 @@ struct pxa2xx_spi_chip { void (*cs_control)(u32 command); }; +extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); + #endif /*PXA2XX_SPI_H_*/ diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h index f762493f5141..3ba464c913a5 100644 --- a/include/asm-arm/arch-pxa/regs-lcd.h +++ b/include/asm-arm/arch-pxa/regs-lcd.h @@ -1,5 +1,8 @@ #ifndef __ASM_ARCH_REGS_LCD_H #define __ASM_ARCH_REGS_LCD_H + +#include <asm/arch/bitfield.h> + /* * LCD Controller Registers and Bits Definitions */ @@ -69,7 +72,7 @@ #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ #define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ +#define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ #define LCCR0_LCDT (1 << 22) /* LCD panel type */ #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h index 9aa6c2e939e8..6956fc5235f8 100644 --- a/include/asm-arm/arch-pxa/system.h +++ b/include/asm-arm/arch-pxa/system.h @@ -12,6 +12,7 @@ #include <asm/proc-fns.h> #include "hardware.h" +#include "pxa2xx-regs.h" #include "pxa-regs.h" static inline void arch_idle(void) @@ -20,19 +21,4 @@ static inline void arch_idle(void) } -static inline void arch_reset(char mode) -{ - if (cpu_is_pxa2xx()) - RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; - - if (mode == 's') { - /* Jump into ROM at address 0 */ - cpu_reset(0); - } else { - /* Initialize the watchdog and let it fire */ - OWER = OWER_WME; - OSSR = OSSR_M3; - OSMR3 = OSCR + 368640; /* ... in 100 ms */ - } -} - +void arch_reset(char mode); diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h index c5b6fde6907c..a16c103b7251 100644 --- a/include/asm-arm/arch-pxa/tosa.h +++ b/include/asm-arm/arch-pxa/tosa.h @@ -25,7 +25,7 @@ */ #define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 -#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 +#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1) #define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) #define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) #define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) @@ -35,11 +35,9 @@ #define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 /* GPIO Direction 1 : output mode / 0:input mode */ -#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ +#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \ TOSA_SCOOP_AUD_PWR_ON |\ - TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN ) -/* GPIO out put level when init 1: Hi */ -#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN ) + TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN) /* * SCOOP2 jacket GPIOs @@ -49,16 +47,34 @@ #define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) #define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) #define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3) -#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 -#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 +#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4) +#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5) #define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 #define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7) #define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 /* GPIO Direction 1 : output mode / 0:input mode */ -#define TOSA_SCOOP_JC_IO_DIR ( \ - TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ - TOSA_SCOOP_JC_CARD_LIMIT_SEL ) +#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL) + +/* + * TC6393XB GPIOs + */ +#define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12) +#define TOSA_TC6393XB_GPIO(i) (TOSA_TC6393XB_GPIO_BASE + (i)) +#define TOSA_TC6393XB_GPIO_BIT(gpio) (1 << (gpio - TOSA_TC6393XB_GPIO_BASE)) + +#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0) +#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1) +#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3) +#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4) +#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6) +#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7) +#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9) +#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10) +#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11) +#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12) +#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14) +#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15) /* * Timing Generator @@ -84,13 +100,13 @@ #define TOSA_GPIO_JACKET_DETECT (7) #define TOSA_GPIO_nSD_DETECT (9) #define TOSA_GPIO_nSD_INT (10) -#define TOSA_GPIO_TC6393_CLK (11) +#define TOSA_GPIO_TC6393XB_CLK (11) #define TOSA_GPIO_BAT1_CRG (12) #define TOSA_GPIO_CF_CD (13) #define TOSA_GPIO_BAT0_CRG (14) -#define TOSA_GPIO_TC6393_INT (15) +#define TOSA_GPIO_TC6393XB_INT (15) #define TOSA_GPIO_BAT0_LOW (17) -#define TOSA_GPIO_TC6393_RDY (18) +#define TOSA_GPIO_TC6393XB_RDY (18) #define TOSA_GPIO_ON_RESET (19) #define TOSA_GPIO_EAR_IN (20) #define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ @@ -99,6 +115,7 @@ #define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ #define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ #define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ +#define TOSA_GPIO_IRDA_TX (47) #define TOSA_GPIO_TG_SPI_SCLK (81) #define TOSA_GPIO_TG_SPI_CS (82) #define TOSA_GPIO_TG_SPI_MOSI (83) @@ -137,7 +154,7 @@ #define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) #define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) #define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) -#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT) +#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT) #define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) #define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) #define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h index 4881b80f0f90..de577de8d18c 100644 --- a/include/asm-arm/arch-pxa/zylonite.h +++ b/include/asm-arm/arch-pxa/zylonite.h @@ -15,7 +15,6 @@ struct platform_mmc_slot { extern struct platform_mmc_slot zylonite_mmc_slot[]; -extern int gpio_backlight; extern int gpio_eth_irq; extern int wm9713_irq; diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h index b4da08d7a336..6bd2295c0e01 100644 --- a/include/asm-arm/arch-rpc/io.h +++ b/include/asm-arm/arch-rpc/io.h @@ -126,7 +126,7 @@ static inline unsigned sz __in##fnsuffix (unsigned int port) \ return (unsigned sz)value; \ } -static inline void __iomem *__ioaddr(unsigned int port) +static inline void __iomem *__deprecated __ioaddr(unsigned int port) { void __iomem *ret; if (__PORT_PCIO(port)) @@ -232,8 +232,7 @@ DECLARE_IO(int,l,"") result; \ }) -#define __ioaddrc(port) \ - ((__PORT_PCIO(port) ? PCIO_BASE : IO_BASE) + ((port) << 2)) +#define __ioaddrc(port) __ioaddr(port) #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) diff --git a/include/asm-arm/dyntick.h b/include/asm-arm/dyntick.h deleted file mode 100644 index 19fab2d2b760..000000000000 --- a/include/asm-arm/dyntick.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASMARM_DYNTICK_H -#define _ASMARM_DYNTICK_H - -#include <asm/mach/time.h> - -#endif /* _ASMARM_DYNTICK_H */ diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 684fe0645239..5e22881a630d 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -85,19 +85,6 @@ #define MAX_ECARDS 9 -typedef enum { /* Cards address space */ - ECARD_IOC, - ECARD_MEMC, - ECARD_EASI -} card_type_t; - -typedef enum { /* Speed for ECARD_IOC space */ - ECARD_SLOW = 0, - ECARD_MEDIUM = 1, - ECARD_FAST = 2, - ECARD_SYNC = 3 -} card_speed_t; - struct ecard_id { /* Card ID structure */ unsigned short manufacturer; unsigned short product; @@ -190,16 +177,6 @@ struct in_chunk_dir { }; /* - * ecard_claim: claim an expansion card entry - */ -#define ecard_claim(ec) ((ec)->claimed = 1) - -/* - * ecard_release: release an expansion card entry - */ -#define ecard_release(ec) ((ec)->claimed = 0) - -/* * Read a chunk from an expansion card * cd : where to put read data * ec : expansion card info struct @@ -209,18 +186,6 @@ struct in_chunk_dir { extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num); /* - * Obtain the address of a card. This returns the "old style" address - * and should no longer be used. - */ -static inline unsigned int __deprecated -ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed) -{ - extern unsigned int __ecard_address(struct expansion_card *, - card_type_t, card_speed_t); - return __ecard_address(ec, type, speed); -} - -/* * Request and release ecard resources */ extern int ecard_request_resources(struct expansion_card *ec); diff --git a/include/asm-arm/hw_irq.h b/include/asm-arm/hw_irq.h index 98d594a973d6..f1a08a500604 100644 --- a/include/asm-arm/hw_irq.h +++ b/include/asm-arm/hw_irq.h @@ -6,15 +6,4 @@ #include <asm/mach/irq.h> -#if defined(CONFIG_NO_IDLE_HZ) -# include <asm/dyntick.h> -# define handle_dynamic_tick(action) \ - if (!(action->flags & IRQF_TIMER) && system_timer->dyn_tick) { \ - write_seqlock(&xtime_lock); \ - if (system_timer->dyn_tick->state & DYN_TICK_ENABLED) \ - system_timer->dyn_tick->handler(irq, NULL); \ - write_sequnlock(&xtime_lock); \ - } -#endif - #endif diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h index 47fe34d692da..c8986bb99ed5 100644 --- a/include/asm-arm/kexec.h +++ b/include/asm-arm/kexec.h @@ -14,8 +14,6 @@ #define KEXEC_ARCH KEXEC_ARCH_ARM -#define KEXEC_BOOT_PARAMS_SIZE 1536 - #define KEXEC_ARM_ATAGS_OFFSET 0x1000 #define KEXEC_ARM_ZIMAGE_OFFSET 0x8000 diff --git a/include/asm-arm/kprobes.h b/include/asm-arm/kprobes.h index c042194d3ab5..b1a37876942d 100644 --- a/include/asm-arm/kprobes.h +++ b/include/asm-arm/kprobes.h @@ -59,6 +59,7 @@ struct kprobe_ctlblk { }; void arch_remove_kprobe(struct kprobe *); +void kretprobe_trampoline(void); int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr); int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr); diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h index 5dc357013b79..2fd36ea0130d 100644 --- a/include/asm-arm/mach/time.h +++ b/include/asm-arm/mach/time.h @@ -41,30 +41,8 @@ struct sys_timer { #ifndef CONFIG_GENERIC_TIME unsigned long (*offset)(void); #endif - -#ifdef CONFIG_NO_IDLE_HZ - struct dyn_tick_timer *dyn_tick; -#endif -}; - -#ifdef CONFIG_NO_IDLE_HZ - -#define DYN_TICK_ENABLED (1 << 1) - -struct dyn_tick_timer { - spinlock_t lock; - unsigned int state; /* Current state */ - int (*enable)(void); /* Enables dynamic tick */ - int (*disable)(void); /* Disables dynamic tick */ - void (*reprogram)(unsigned long); /* Reprograms the timer */ - int (*handler)(int, void *); }; -void timer_dyn_reprogram(void); -#else -#define timer_dyn_reprogram() do { } while (0) -#endif - extern struct sys_timer *system_timer; extern void timer_tick(void); diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h index 2e5868bbe03b..386fcc10a973 100644 --- a/include/asm-arm/pgtable-nommu.h +++ b/include/asm-arm/pgtable-nommu.h @@ -16,7 +16,6 @@ #include <linux/slab.h> #include <asm/processor.h> #include <asm/page.h> -#include <asm/io.h> /* * Trivial page table functions. diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h deleted file mode 100644 index 1a5c9232a91e..000000000000 --- a/include/asm-arm/rtc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/include/asm-arm/rtc.h - * - * Copyright (C) 2003 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASMARM_RTC_H -#define ASMARM_RTC_H - -struct module; - -struct rtc_ops { - struct module *owner; - int (*open)(void); - void (*release)(void); - int (*ioctl)(unsigned int, unsigned long); - - int (*read_time)(struct rtc_time *); - int (*set_time)(struct rtc_time *); - int (*read_alarm)(struct rtc_wkalrm *); - int (*set_alarm)(struct rtc_wkalrm *); - int (*proc)(char *buf); -}; - -void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *); -void rtc_update(unsigned long, unsigned long); -int register_rtc(struct rtc_ops *); -void unregister_rtc(struct rtc_ops *); - -static inline int rtc_periodic_alarm(struct rtc_time *tm) -{ - return (tm->tm_year == -1) || - ((unsigned)tm->tm_mon >= 12) || - ((unsigned)(tm->tm_mday - 1) >= 31) || - ((unsigned)tm->tm_hour > 23) || - ((unsigned)tm->tm_min > 59) || - ((unsigned)tm->tm_sec > 59); -} - -#endif diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h index 800ba5254daf..2b41ebbfa7ff 100644 --- a/include/asm-arm/spinlock.h +++ b/include/asm-arm/spinlock.h @@ -142,7 +142,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) } /* write_can_lock - would write_trylock() succeed? */ -#define __raw_write_can_lock(x) ((x)->lock == 0x80000000) +#define __raw_write_can_lock(x) ((x)->lock == 0) /* * Read locks are a bit more hairy: diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h index a4e2d28bfb58..528e145a2e06 100644 --- a/include/asm-avr32/arch-at32ap/board.h +++ b/include/asm-avr32/arch-at32ap/board.h @@ -8,6 +8,12 @@ #define GPIO_PIN_NONE (-1) +/* + * Clock rates for various on-board oscillators. The number of entries + * in this array is chip-dependent. + */ +extern unsigned long at32_board_osc_rates[]; + /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */ void at32_add_system_devices(void); @@ -36,7 +42,8 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n); struct atmel_lcdfb_info; struct platform_device * at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, - unsigned long fbmem_start, unsigned long fbmem_len); + unsigned long fbmem_start, unsigned long fbmem_len, + unsigned int pin_config); struct usba_platform_data; struct platform_device * @@ -73,6 +80,7 @@ struct platform_device *at32_add_device_twi(unsigned int id, struct platform_device *at32_add_device_mci(unsigned int id); struct platform_device *at32_add_device_ac97c(unsigned int id); struct platform_device *at32_add_device_abdac(unsigned int id); +struct platform_device *at32_add_device_psif(unsigned int id); struct cf_platform_data { int detect_pin; @@ -85,4 +93,17 @@ struct platform_device * at32_add_device_cf(unsigned int id, unsigned int extint, struct cf_platform_data *data); +/* NAND / SmartMedia */ +struct atmel_nand_data { + int enable_pin; /* chip enable */ + int det_pin; /* card detect */ + int rdy_pin; /* ready/busy */ + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + u8 bus_width_16; /* buswidth is 16 bit */ + struct mtd_partition *(*partition_info)(int size, int *num_partitions); +}; +struct platform_device * +at32_add_device_nand(unsigned int id, struct atmel_nand_data *data); + #endif /* __ASM_ARCH_BOARD_H */ diff --git a/include/asm-avr32/pci.h b/include/asm-avr32/pci.h index 0f5f134b896a..a32a02372017 100644 --- a/include/asm-avr32/pci.h +++ b/include/asm-avr32/pci.h @@ -5,4 +5,6 @@ #define PCI_DMA_BUS_IS_PHYS (1) +#include <asm-generic/pci-dma-compat.h> + #endif /* __ASM_AVR32_PCI_H__ */ diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index a9248d883675..76033831eb35 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -105,13 +105,6 @@ extern int sram_free(const void*); extern void *sram_alloc_with_lsl(size_t, unsigned long); extern int sram_free_with_lsl(const void*); -extern void led_on(int); -extern void led_off(int); -extern void led_toggle(int); -extern void led_disp_num(int); -extern void led_toggle_num(int); -extern void init_leds(void); - extern const char bfin_board_name[]; extern unsigned long wall_jiffies; diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index 735fa02fafb2..4725268a5ada 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -15,12 +15,16 @@ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ @@ -92,7 +96,6 @@ #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) -#define ANOMALY_05000312 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000363 (0) diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index 26e3c8076b4e..96bd09e31e36 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -53,6 +53,12 @@ #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) +#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 5a6dcc5fa36c..8f7ea112fd3a 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -2,7 +2,7 @@ * File: include/asm-blackfin/mach-bf533/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -176,6 +176,21 @@ #define ANOMALY_05000315 (1) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ #define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* UART Break Signal Issues */ +#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) +/* PPI Does Not Start Properly In Specific Mode */ +#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) + /* These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. @@ -249,20 +264,6 @@ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) -/* UART Break Signal Issues */ -#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) -/* PPI Does Not Start Properly In Specific Mode */ -#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000266 (0) diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index d016603b6615..e924569ad1d8 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -53,6 +53,12 @@ #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) +#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index a6b08facb242..8460ab9c324f 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -2,7 +2,7 @@ * File: include/asm-blackfin/mach-bf537/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -132,8 +132,8 @@ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */ -#define ANOMALY_05000350 (__SILICON_REVISION__ < 3) +/* New Feature: UART Remains Enabled after UART Boot */ +#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ @@ -145,12 +145,10 @@ /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3) +#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) - - /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) #define ANOMALY_05000158 (0) diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index f79d1a0e9129..41d7b6490bb1 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -53,6 +53,12 @@ #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) +#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 49d3cebc5293..3ad59655881a 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -75,6 +75,8 @@ #define ANOMALY_05000365 (1) /* Addressing Conflict between Boot ROM and Asynchronous Memory */ #define ANOMALY_05000369 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) /* Mobile DDR Operation Not Functional */ #define ANOMALY_05000377 (1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 5eb46a77d919..59b4ad4e5b4a 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -57,6 +57,12 @@ #define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ #define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ +#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) +#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS)) +#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS)) +#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) +#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index 82157caa96a2..5c5d7d7d695f 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -2,7 +2,7 @@ * File: include/asm-blackfin/mach-bf561/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2007 Analog Devices Inc. + * Copyright (C) 2004-2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index 7a9628769296..30d90b580f18 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -53,6 +53,12 @@ #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) +#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN diff --git a/include/asm-frv/checksum.h b/include/asm-frv/checksum.h index 9b1689850187..269da09ff637 100644 --- a/include/asm-frv/checksum.h +++ b/include/asm-frv/checksum.h @@ -75,7 +75,7 @@ __sum16 ip_fast_csum(const void *iph, unsigned int ihl) : "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (inc), "=&r"(tmp) : "0" (sum), "1" (iph), "2" (ihl), "3" (4), "m"(*(volatile struct { int _[100]; } *)iph) - : "icc0", "icc1" + : "icc0", "icc1", "memory" ); return (__force __sum16)~sum; diff --git a/include/asm-generic/percpu.h b/include/asm-generic/percpu.h index b0e63c672ebd..36d188f47c98 100644 --- a/include/asm-generic/percpu.h +++ b/include/asm-generic/percpu.h @@ -45,7 +45,12 @@ extern unsigned long __per_cpu_offset[NR_CPUS]; * Only S390 provides its own means of moving the pointer. */ #ifndef SHIFT_PERCPU_PTR -#define SHIFT_PERCPU_PTR(__p, __offset) RELOC_HIDE((__p), (__offset)) +# ifdef CONFIG_HAVE_ZERO_BASED_PER_CPU +# define SHIFT_PERCPU_PTR(__p, __offset) \ + ((__typeof(__p))(((void *)(__p)) + (__offset))) +# else +# define SHIFT_PERCPU_PTR(__p, __offset) RELOC_HIDE((__p), (__offset)) +# endif /* CONFIG_HAVE_ZERO_BASED_PER_CPU */ #endif /* @@ -70,6 +75,8 @@ extern void setup_per_cpu_areas(void); #define per_cpu(var, cpu) (*((void)(cpu), &per_cpu_var(var))) #define __get_cpu_var(var) per_cpu_var(var) #define __raw_get_cpu_var(var) per_cpu_var(var) +#define SHIFT_PERCPU_PTR(__p, __offset) (__p) +#define per_cpu_offset(x) 0L #endif /* SMP */ diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 8feeae1f2369..f697620c3e21 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -9,7 +9,17 @@ extern char __bss_start[], __bss_stop[]; extern char __init_begin[], __init_end[]; extern char _sinittext[], _einittext[]; extern char _end[]; +#ifdef CONFIG_HAVE_ZERO_BASED_PER_CPU +extern char __per_cpu_load[]; +extern char ____per_cpu_size[]; +#define __per_cpu_size ((unsigned long)&____per_cpu_size) +#define __per_cpu_start ((char *)0) +#define __per_cpu_end ((char *)__per_cpu_size) +#else extern char __per_cpu_start[], __per_cpu_end[]; +#define __per_cpu_load __per_cpu_start +#define __per_cpu_size (__per_cpu_end - __per_cpu_start) +#endif extern char __kprobes_text_start[], __kprobes_text_end[]; extern char __initdata_begin[], __initdata_end[]; extern char __start_rodata[], __end_rodata[]; diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index f054778e916c..48fe38276d60 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -67,6 +67,8 @@ *(.rodata1) \ } \ \ + BUG_TABLE \ + \ /* PCI quirks */ \ .pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \ VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \ @@ -84,6 +86,12 @@ VMLINUX_SYMBOL(__start_pci_fixups_resume) = .; \ *(.pci_fixup_resume) \ VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .; \ + *(.pci_fixup_resume_early) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \ + *(.pci_fixup_suspend) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \ } \ \ /* RapidIO route ops */ \ @@ -93,6 +101,8 @@ VMLINUX_SYMBOL(__end_rio_route_ops) = .; \ } \ \ + TRACEDATA \ + \ /* Kernel symbol table: Normal symbols */ \ __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ VMLINUX_SYMBOL(__start___ksymtab) = .; \ @@ -310,6 +320,7 @@ .stab.indexstr 0 : { *(.stab.indexstr) } \ .comment 0 : { *(.comment) } +#ifdef CONFIG_GENERIC_BUG #define BUG_TABLE \ . = ALIGN(8); \ __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \ @@ -317,6 +328,21 @@ *(__bug_table) \ __stop___bug_table = .; \ } +#else +#define BUG_TABLE +#endif + +#ifdef CONFIG_PM_TRACE +#define TRACEDATA \ + . = ALIGN(4); \ + .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \ + __tracedata_start = .; \ + *(.tracedata) \ + __tracedata_end = .; \ + } +#else +#define TRACEDATA +#endif #define NOTES \ .notes : AT(ADDR(.notes) - LOAD_OFFSET) { \ @@ -344,11 +370,28 @@ *(.initcall7.init) \ *(.initcall7s.init) +#ifdef CONFIG_HAVE_ZERO_BASED_PER_CPU +#define PERCPU(align) \ + . = ALIGN(align); \ + percpu : { } :percpu \ + __per_cpu_load = .; \ + .data.percpu 0 : AT(__per_cpu_load - LOAD_OFFSET) { \ + *(.data.percpu.first) \ + *(.data.percpu.shared_aligned) \ + *(.data.percpu) \ + *(.data.percpu.page_aligned) \ + ____per_cpu_size = .; \ + } \ + . = __per_cpu_load + ____per_cpu_size; \ + data : { } :data +#else #define PERCPU(align) \ . = ALIGN(align); \ __per_cpu_start = .; \ .data.percpu : AT(ADDR(.data.percpu) - LOAD_OFFSET) { \ + *(.data.percpu.page_aligned) \ *(.data.percpu) \ *(.data.percpu.shared_aligned) \ } \ __per_cpu_end = .; +#endif diff --git a/include/asm-h8300/cacheflush.h b/include/asm-h8300/cacheflush.h index 71210d141b64..5ffdca217b95 100644 --- a/include/asm-h8300/cacheflush.h +++ b/include/asm-h8300/cacheflush.h @@ -3,7 +3,7 @@ */ #ifndef _ASM_H8300_CACHEFLUSH_H -#define _AMS_H8300_CACHEFLUSH_H +#define _ASM_H8300_CACHEFLUSH_H /* * Cache handling functions diff --git a/include/asm-ia64/Kbuild b/include/asm-ia64/Kbuild index eb24a3f47caa..ccbe8ae47a61 100644 --- a/include/asm-ia64/Kbuild +++ b/include/asm-ia64/Kbuild @@ -5,12 +5,12 @@ header-y += fpu.h header-y += fpswa.h header-y += ia64regs.h header-y += intel_intrin.h -header-y += intrinsics.h header-y += perfmon_default_smpl.h header-y += ptrace_offsets.h header-y += rse.h header-y += ucontext.h unifdef-y += gcc_intrin.h +unifdef-y += intrinsics.h unifdef-y += perfmon.h unifdef-y += ustack.h diff --git a/include/asm-ia64/gcc_intrin.h b/include/asm-ia64/gcc_intrin.h index 2fe292c275fe..0f5b55921758 100644 --- a/include/asm-ia64/gcc_intrin.h +++ b/include/asm-ia64/gcc_intrin.h @@ -32,7 +32,7 @@ extern void ia64_bad_param_for_getreg (void); register unsigned long ia64_r13 asm ("r13") __used; #endif -#define ia64_setreg(regnum, val) \ +#define ia64_native_setreg(regnum, val) \ ({ \ switch (regnum) { \ case _IA64_REG_PSR_L: \ @@ -61,7 +61,7 @@ register unsigned long ia64_r13 asm ("r13") __used; } \ }) -#define ia64_getreg(regnum) \ +#define ia64_native_getreg(regnum) \ ({ \ __u64 ia64_intri_res; \ \ @@ -385,7 +385,7 @@ register unsigned long ia64_r13 asm ("r13") __used; #define ia64_invala() asm volatile ("invala" ::: "memory") -#define ia64_thash(addr) \ +#define ia64_native_thash(addr) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \ @@ -438,10 +438,10 @@ register unsigned long ia64_r13 asm ("r13") __used; #define ia64_set_pmd(index, val) \ asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory") -#define ia64_set_rr(index, val) \ +#define ia64_native_set_rr(index, val) \ asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory"); -#define ia64_get_cpuid(index) \ +#define ia64_native_get_cpuid(index) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \ @@ -477,33 +477,33 @@ register unsigned long ia64_r13 asm ("r13") __used; }) -#define ia64_get_pmd(index) \ +#define ia64_native_get_pmd(index) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \ ia64_intri_res; \ }) -#define ia64_get_rr(index) \ +#define ia64_native_get_rr(index) \ ({ \ __u64 ia64_intri_res; \ asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \ ia64_intri_res; \ }) -#define ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory") +#define ia64_native_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory") #define ia64_sync_i() asm volatile (";; sync.i" ::: "memory") -#define ia64_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory") -#define ia64_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory") +#define ia64_native_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory") +#define ia64_native_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory") #define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory") #define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory") #define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr)) -#define ia64_ptcga(addr, size) \ +#define ia64_native_ptcga(addr, size) \ do { \ asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory"); \ ia64_dv_serialize_data(); \ @@ -608,7 +608,7 @@ do { \ } \ }) -#define ia64_intrin_local_irq_restore(x) \ +#define ia64_native_intrin_local_irq_restore(x) \ do { \ asm volatile (";; cmp.ne p6,p7=%0,r0;;" \ "(p6) ssm psr.i;" \ diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h index 76366dc9c1a0..5c99cbcb8a0d 100644 --- a/include/asm-ia64/hw_irq.h +++ b/include/asm-ia64/hw_irq.h @@ -15,7 +15,11 @@ #include <asm/ptrace.h> #include <asm/smp.h> +#ifndef CONFIG_PARAVIRT typedef u8 ia64_vector; +#else +typedef u16 ia64_vector; +#endif /* * 0 special @@ -104,13 +108,24 @@ DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq); extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ +#ifdef CONFIG_PARAVIRT_GUEST +#include <asm/paravirt.h> +#else +#define ia64_register_ipi ia64_native_register_ipi +#define assign_irq_vector ia64_native_assign_irq_vector +#define free_irq_vector ia64_native_free_irq_vector +#define register_percpu_irq ia64_native_register_percpu_irq +#define ia64_resend_irq ia64_native_resend_irq +#endif + +extern void ia64_native_register_ipi(void); extern int bind_irq_vector(int irq, int vector, cpumask_t domain); -extern int assign_irq_vector (int irq); /* allocate a free vector */ -extern void free_irq_vector (int vector); +extern int ia64_native_assign_irq_vector (int irq); /* allocate a free vector */ +extern void ia64_native_free_irq_vector (int vector); extern int reserve_irq_vector (int vector); extern void __setup_vector_irq(int cpu); extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); -extern void register_percpu_irq (ia64_vector vec, struct irqaction *action); +extern void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action); extern int check_irq_used (int irq); extern void destroy_and_reserve_irq (unsigned int irq); @@ -122,7 +137,7 @@ static inline int irq_prepare_move(int irq, int cpu) { return 0; } static inline void irq_complete_move(unsigned int irq) {} #endif -static inline void ia64_resend_irq(unsigned int vector) +static inline void ia64_native_resend_irq(unsigned int vector) { platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); } diff --git a/include/asm-ia64/intel_intrin.h b/include/asm-ia64/intel_intrin.h index a520d103d808..53cec577558a 100644 --- a/include/asm-ia64/intel_intrin.h +++ b/include/asm-ia64/intel_intrin.h @@ -16,8 +16,8 @@ * intrinsic */ -#define ia64_getreg __getReg -#define ia64_setreg __setReg +#define ia64_native_getreg __getReg +#define ia64_native_setreg __setReg #define ia64_hint __hint #define ia64_hint_pause __hint_pause @@ -39,10 +39,10 @@ #define ia64_invala_fr __invala_fr #define ia64_nop __nop #define ia64_sum __sum -#define ia64_ssm __ssm +#define ia64_native_ssm __ssm #define ia64_rum __rum -#define ia64_rsm __rsm -#define ia64_fc __fc +#define ia64_native_rsm __rsm +#define ia64_native_fc __fc #define ia64_ldfs __ldfs #define ia64_ldfd __ldfd @@ -88,16 +88,17 @@ __setIndReg(_IA64_REG_INDR_PMC, index, val) #define ia64_set_pmd(index, val) \ __setIndReg(_IA64_REG_INDR_PMD, index, val) -#define ia64_set_rr(index, val) \ +#define ia64_native_set_rr(index, val) \ __setIndReg(_IA64_REG_INDR_RR, index, val) -#define ia64_get_cpuid(index) __getIndReg(_IA64_REG_INDR_CPUID, index) -#define __ia64_get_dbr(index) __getIndReg(_IA64_REG_INDR_DBR, index) -#define ia64_get_ibr(index) __getIndReg(_IA64_REG_INDR_IBR, index) -#define ia64_get_pkr(index) __getIndReg(_IA64_REG_INDR_PKR, index) -#define ia64_get_pmc(index) __getIndReg(_IA64_REG_INDR_PMC, index) -#define ia64_get_pmd(index) __getIndReg(_IA64_REG_INDR_PMD, index) -#define ia64_get_rr(index) __getIndReg(_IA64_REG_INDR_RR, index) +#define ia64_native_get_cpuid(index) \ + __getIndReg(_IA64_REG_INDR_CPUID, index) +#define __ia64_get_dbr(index) __getIndReg(_IA64_REG_INDR_DBR, index) +#define ia64_get_ibr(index) __getIndReg(_IA64_REG_INDR_IBR, index) +#define ia64_get_pkr(index) __getIndReg(_IA64_REG_INDR_PKR, index) +#define ia64_get_pmc(index) __getIndReg(_IA64_REG_INDR_PMC, index) +#define ia64_native_get_pmd(index) __getIndReg(_IA64_REG_INDR_PMD, index) +#define ia64_native_get_rr(index) __getIndReg(_IA64_REG_INDR_RR, index) #define ia64_srlz_d __dsrlz #define ia64_srlz_i __isrlz @@ -119,16 +120,16 @@ #define ia64_ld8_acq __ld8_acq #define ia64_sync_i __synci -#define ia64_thash __thash -#define ia64_ttag __ttag +#define ia64_native_thash __thash +#define ia64_native_ttag __ttag #define ia64_itcd __itcd #define ia64_itci __itci #define ia64_itrd __itrd #define ia64_itri __itri #define ia64_ptce __ptce #define ia64_ptcl __ptcl -#define ia64_ptcg __ptcg -#define ia64_ptcga __ptcga +#define ia64_native_ptcg __ptcg +#define ia64_native_ptcga __ptcga #define ia64_ptri __ptri #define ia64_ptrd __ptrd #define ia64_dep_mi _m64_dep_mi @@ -145,13 +146,13 @@ #define ia64_lfetch_fault __lfetch_fault #define ia64_lfetch_fault_excl __lfetch_fault_excl -#define ia64_intrin_local_irq_restore(x) \ +#define ia64_native_intrin_local_irq_restore(x) \ do { \ if ((x) != 0) { \ - ia64_ssm(IA64_PSR_I); \ + ia64_native_ssm(IA64_PSR_I); \ ia64_srlz_d(); \ } else { \ - ia64_rsm(IA64_PSR_I); \ + ia64_native_rsm(IA64_PSR_I); \ } \ } while (0) diff --git a/include/asm-ia64/intrinsics.h b/include/asm-ia64/intrinsics.h index f1135b5b94c3..47d686dba1eb 100644 --- a/include/asm-ia64/intrinsics.h +++ b/include/asm-ia64/intrinsics.h @@ -18,6 +18,17 @@ # include <asm/gcc_intrin.h> #endif +#define ia64_native_get_psr_i() (ia64_native_getreg(_IA64_REG_PSR) & IA64_PSR_I) + +#define ia64_native_set_rr0_to_rr4(val0, val1, val2, val3, val4) \ +do { \ + ia64_native_set_rr(0x0000000000000000UL, (val0)); \ + ia64_native_set_rr(0x2000000000000000UL, (val1)); \ + ia64_native_set_rr(0x4000000000000000UL, (val2)); \ + ia64_native_set_rr(0x6000000000000000UL, (val3)); \ + ia64_native_set_rr(0x8000000000000000UL, (val4)); \ +} while (0) + /* * Force an unresolved reference if someone tries to use * ia64_fetch_and_add() with a bad value. @@ -183,4 +194,48 @@ extern long ia64_cmpxchg_called_with_bad_pointer (void); #endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ #endif + +#ifdef __KERNEL__ +#include <asm/paravirt_privop.h> +#endif + +#ifndef __ASSEMBLY__ +#if defined(CONFIG_PARAVIRT) && defined(__KERNEL__) +#define IA64_INTRINSIC_API(name) pv_cpu_ops.name +#define IA64_INTRINSIC_MACRO(name) paravirt_ ## name +#else +#define IA64_INTRINSIC_API(name) ia64_native_ ## name +#define IA64_INTRINSIC_MACRO(name) ia64_native_ ## name +#endif + +/************************************************/ +/* Instructions paravirtualized for correctness */ +/************************************************/ +/* fc, thash, get_cpuid, get_pmd, get_eflags, set_eflags */ +/* Note that "ttag" and "cover" are also privilege-sensitive; "ttag" + * is not currently used (though it may be in a long-format VHPT system!) + */ +#define ia64_fc IA64_INTRINSIC_API(fc) +#define ia64_thash IA64_INTRINSIC_API(thash) +#define ia64_get_cpuid IA64_INTRINSIC_API(get_cpuid) +#define ia64_get_pmd IA64_INTRINSIC_API(get_pmd) + + +/************************************************/ +/* Instructions paravirtualized for performance */ +/************************************************/ +#define ia64_ssm IA64_INTRINSIC_MACRO(ssm) +#define ia64_rsm IA64_INTRINSIC_MACRO(rsm) +#define ia64_getreg IA64_INTRINSIC_API(getreg) +#define ia64_setreg IA64_INTRINSIC_API(setreg) +#define ia64_set_rr IA64_INTRINSIC_API(set_rr) +#define ia64_get_rr IA64_INTRINSIC_API(get_rr) +#define ia64_ptcga IA64_INTRINSIC_API(ptcga) +#define ia64_get_psr_i IA64_INTRINSIC_API(get_psr_i) +#define ia64_intrin_local_irq_restore \ + IA64_INTRINSIC_API(intrin_local_irq_restore) +#define ia64_set_rr0_to_rr4 IA64_INTRINSIC_API(set_rr0_to_rr4) + +#endif /* !__ASSEMBLY__ */ + #endif /* _ASM_IA64_INTRINSICS_H */ diff --git a/include/asm-ia64/iosapic.h b/include/asm-ia64/iosapic.h index a3a4288daae8..b9c102e15f22 100644 --- a/include/asm-ia64/iosapic.h +++ b/include/asm-ia64/iosapic.h @@ -55,13 +55,27 @@ #define NR_IOSAPICS 256 -static inline unsigned int __iosapic_read(char __iomem *iosapic, unsigned int reg) +#ifdef CONFIG_PARAVIRT_GUEST +#include <asm/paravirt.h> +#else +#define iosapic_pcat_compat_init ia64_native_iosapic_pcat_compat_init +#define __iosapic_read __ia64_native_iosapic_read +#define __iosapic_write __ia64_native_iosapic_write +#define iosapic_get_irq_chip ia64_native_iosapic_get_irq_chip +#endif + +extern void __init ia64_native_iosapic_pcat_compat_init(void); +extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger); + +static inline unsigned int +__ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg) { writel(reg, iosapic + IOSAPIC_REG_SELECT); return readl(iosapic + IOSAPIC_WINDOW); } -static inline void __iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) +static inline void +__ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) { writel(reg, iosapic + IOSAPIC_REG_SELECT); writel(val, iosapic + IOSAPIC_WINDOW); diff --git a/include/asm-ia64/irq.h b/include/asm-ia64/irq.h index a66d26827cbb..3627116fb0e2 100644 --- a/include/asm-ia64/irq.h +++ b/include/asm-ia64/irq.h @@ -13,14 +13,7 @@ #include <linux/types.h> #include <linux/cpumask.h> - -#define NR_VECTORS 256 - -#if (NR_VECTORS + 32 * NR_CPUS) < 1024 -#define NR_IRQS (NR_VECTORS + 32 * NR_CPUS) -#else -#define NR_IRQS 1024 -#endif +#include <asm-ia64/nr-irqs.h> static __inline__ int irq_canonicalize (int irq) diff --git a/include/asm-ia64/kvm_host.h b/include/asm-ia64/kvm_host.h index c082c208c1f3..1efe513a9941 100644 --- a/include/asm-ia64/kvm_host.h +++ b/include/asm-ia64/kvm_host.h @@ -38,6 +38,7 @@ /* memory slots that does not exposed to userspace */ #define KVM_PRIVATE_MEM_SLOTS 4 +#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 /* define exit reasons from vmm to kvm*/ #define EXIT_REASON_VM_PANIC 0 @@ -521,4 +522,6 @@ int kvm_emulate_halt(struct kvm_vcpu *vcpu); int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run); void kvm_sal_emul(struct kvm_vcpu *vcpu); +static inline void kvm_inject_nmi(struct kvm_vcpu *vcpu) {} + #endif diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h index cef2400983fa..040bc87db930 100644 --- a/include/asm-ia64/mmu_context.h +++ b/include/asm-ia64/mmu_context.h @@ -152,11 +152,7 @@ reload_context (nv_mm_context_t context) # endif #endif - ia64_set_rr(0x0000000000000000UL, rr0); - ia64_set_rr(0x2000000000000000UL, rr1); - ia64_set_rr(0x4000000000000000UL, rr2); - ia64_set_rr(0x6000000000000000UL, rr3); - ia64_set_rr(0x8000000000000000UL, rr4); + ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4); ia64_srlz_i(); /* srlz.i implies srlz.d */ } diff --git a/include/asm-ia64/native/inst.h b/include/asm-ia64/native/inst.h new file mode 100644 index 000000000000..c953a2ca4fce --- /dev/null +++ b/include/asm-ia64/native/inst.h @@ -0,0 +1,175 @@ +/****************************************************************************** + * include/asm-ia64/native/inst.h + * + * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#define DO_SAVE_MIN IA64_NATIVE_DO_SAVE_MIN + +#define __paravirt_switch_to ia64_native_switch_to +#define __paravirt_leave_syscall ia64_native_leave_syscall +#define __paravirt_work_processed_syscall ia64_native_work_processed_syscall +#define __paravirt_leave_kernel ia64_native_leave_kernel +#define __paravirt_pending_syscall_end ia64_work_pending_syscall_end +#define __paravirt_work_processed_syscall_target \ + ia64_work_processed_syscall + +#ifdef CONFIG_PARAVIRT_GUEST_ASM_CLOBBER_CHECK +# define PARAVIRT_POISON 0xdeadbeefbaadf00d +# define CLOBBER(clob) \ + ;; \ + movl clob = PARAVIRT_POISON; \ + ;; +#else +# define CLOBBER(clob) /* nothing */ +#endif + +#define MOV_FROM_IFA(reg) \ + mov reg = cr.ifa + +#define MOV_FROM_ITIR(reg) \ + mov reg = cr.itir + +#define MOV_FROM_ISR(reg) \ + mov reg = cr.isr + +#define MOV_FROM_IHA(reg) \ + mov reg = cr.iha + +#define MOV_FROM_IPSR(pred, reg) \ +(pred) mov reg = cr.ipsr + +#define MOV_FROM_IIM(reg) \ + mov reg = cr.iim + +#define MOV_FROM_IIP(reg) \ + mov reg = cr.iip + +#define MOV_FROM_IVR(reg, clob) \ + mov reg = cr.ivr \ + CLOBBER(clob) + +#define MOV_FROM_PSR(pred, reg, clob) \ +(pred) mov reg = psr \ + CLOBBER(clob) + +#define MOV_TO_IFA(reg, clob) \ + mov cr.ifa = reg \ + CLOBBER(clob) + +#define MOV_TO_ITIR(pred, reg, clob) \ +(pred) mov cr.itir = reg \ + CLOBBER(clob) + +#define MOV_TO_IHA(pred, reg, clob) \ +(pred) mov cr.iha = reg \ + CLOBBER(clob) + +#define MOV_TO_IPSR(pred, reg, clob) \ +(pred) mov cr.ipsr = reg \ + CLOBBER(clob) + +#define MOV_TO_IFS(pred, reg, clob) \ +(pred) mov cr.ifs = reg \ + CLOBBER(clob) + +#define MOV_TO_IIP(reg, clob) \ + mov cr.iip = reg \ + CLOBBER(clob) + +#define MOV_TO_KR(kr, reg, clob0, clob1) \ + mov IA64_KR(kr) = reg \ + CLOBBER(clob0) \ + CLOBBER(clob1) + +#define ITC_I(pred, reg, clob) \ +(pred) itc.i reg \ + CLOBBER(clob) + +#define ITC_D(pred, reg, clob) \ +(pred) itc.d reg \ + CLOBBER(clob) + +#define ITC_I_AND_D(pred_i, pred_d, reg, clob) \ +(pred_i) itc.i reg; \ +(pred_d) itc.d reg \ + CLOBBER(clob) + +#define THASH(pred, reg0, reg1, clob) \ +(pred) thash reg0 = reg1 \ + CLOBBER(clob) + +#define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \ + ssm psr.ic | PSR_DEFAULT_BITS \ + CLOBBER(clob0) \ + CLOBBER(clob1) \ + ;; \ + srlz.i /* guarantee that interruption collectin is on */ \ + ;; + +#define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \ + ssm psr.ic \ + CLOBBER(clob0) \ + CLOBBER(clob1) \ + ;; \ + srlz.d + +#define RSM_PSR_IC(clob) \ + rsm psr.ic \ + CLOBBER(clob) + +#define SSM_PSR_I(pred, pred_clob, clob) \ +(pred) ssm psr.i \ + CLOBBER(clob) + +#define RSM_PSR_I(pred, clob0, clob1) \ +(pred) rsm psr.i \ + CLOBBER(clob0) \ + CLOBBER(clob1) + +#define RSM_PSR_I_IC(clob0, clob1, clob2) \ + rsm psr.i | psr.ic \ + CLOBBER(clob0) \ + CLOBBER(clob1) \ + CLOBBER(clob2) + +#define RSM_PSR_DT \ + rsm psr.dt + +#define SSM_PSR_DT_AND_SRLZ_I \ + ssm psr.dt \ + ;; \ + srlz.i + +#define BSW_0(clob0, clob1, clob2) \ + bsw.0 \ + CLOBBER(clob0) \ + CLOBBER(clob1) \ + CLOBBER(clob2) + +#define BSW_1(clob0, clob1) \ + bsw.1 \ + CLOBBER(clob0) \ + CLOBBER(clob1) + +#define COVER \ + cover + +#define RFI \ + rfi diff --git a/include/asm-ia64/native/irq.h b/include/asm-ia64/native/irq.h new file mode 100644 index 000000000000..efe9ff74a3c4 --- /dev/null +++ b/include/asm-ia64/native/irq.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * include/asm-ia64/native/irq.h + * + * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * moved from linux/include/asm-ia64/irq.h. + */ + +#ifndef _ASM_IA64_NATIVE_IRQ_H +#define _ASM_IA64_NATIVE_IRQ_H + +#define NR_VECTORS 256 + +#if (NR_VECTORS + 32 * NR_CPUS) < 1024 +#define IA64_NATIVE_NR_IRQS (NR_VECTORS + 32 * NR_CPUS) +#else +#define IA64_NATIVE_NR_IRQS 1024 +#endif + +#endif /* _ASM_IA64_NATIVE_IRQ_H */ diff --git a/include/asm-ia64/paravirt.h b/include/asm-ia64/paravirt.h new file mode 100644 index 000000000000..1b4df129f579 --- /dev/null +++ b/include/asm-ia64/paravirt.h @@ -0,0 +1,255 @@ +/****************************************************************************** + * include/asm-ia64/paravirt.h + * + * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + + +#ifndef __ASM_PARAVIRT_H +#define __ASM_PARAVIRT_H + +#ifdef CONFIG_PARAVIRT_GUEST + +#define PARAVIRT_HYPERVISOR_TYPE_DEFAULT 0 +#define PARAVIRT_HYPERVISOR_TYPE_XEN 1 + +#ifndef __ASSEMBLY__ + +#include <asm/hw_irq.h> +#include <asm/meminit.h> + +/****************************************************************************** + * general info + */ +struct pv_info { + unsigned int kernel_rpl; + int paravirt_enabled; + const char *name; +}; + +extern struct pv_info pv_info; + +static inline int paravirt_enabled(void) +{ + return pv_info.paravirt_enabled; +} + +static inline unsigned int get_kernel_rpl(void) +{ + return pv_info.kernel_rpl; +} + +/****************************************************************************** + * initialization hooks. + */ +struct rsvd_region; + +struct pv_init_ops { + void (*banner)(void); + + int (*reserve_memory)(struct rsvd_region *region); + + void (*arch_setup_early)(void); + void (*arch_setup_console)(char **cmdline_p); + int (*arch_setup_nomca)(void); + + void (*post_smp_prepare_boot_cpu)(void); +}; + +extern struct pv_init_ops pv_init_ops; + +static inline void paravirt_banner(void) +{ + if (pv_init_ops.banner) + pv_init_ops.banner(); +} + +static inline int paravirt_reserve_memory(struct rsvd_region *region) +{ + if (pv_init_ops.reserve_memory) + return pv_init_ops.reserve_memory(region); + return 0; +} + +static inline void paravirt_arch_setup_early(void) +{ + if (pv_init_ops.arch_setup_early) + pv_init_ops.arch_setup_early(); +} + +static inline void paravirt_arch_setup_console(char **cmdline_p) +{ + if (pv_init_ops.arch_setup_console) + pv_init_ops.arch_setup_console(cmdline_p); +} + +static inline int paravirt_arch_setup_nomca(void) +{ + if (pv_init_ops.arch_setup_nomca) + return pv_init_ops.arch_setup_nomca(); + return 0; +} + +static inline void paravirt_post_smp_prepare_boot_cpu(void) +{ + if (pv_init_ops.post_smp_prepare_boot_cpu) + pv_init_ops.post_smp_prepare_boot_cpu(); +} + +/****************************************************************************** + * replacement of iosapic operations. + */ + +struct pv_iosapic_ops { + void (*pcat_compat_init)(void); + + struct irq_chip *(*get_irq_chip)(unsigned long trigger); + + unsigned int (*__read)(char __iomem *iosapic, unsigned int reg); + void (*__write)(char __iomem *iosapic, unsigned int reg, u32 val); +}; + +extern struct pv_iosapic_ops pv_iosapic_ops; + +static inline void +iosapic_pcat_compat_init(void) +{ + if (pv_iosapic_ops.pcat_compat_init) + pv_iosapic_ops.pcat_compat_init(); +} + +static inline struct irq_chip* +iosapic_get_irq_chip(unsigned long trigger) +{ + return pv_iosapic_ops.get_irq_chip(trigger); +} + +static inline unsigned int +__iosapic_read(char __iomem *iosapic, unsigned int reg) +{ + return pv_iosapic_ops.__read(iosapic, reg); +} + +static inline void +__iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) +{ + return pv_iosapic_ops.__write(iosapic, reg, val); +} + +/****************************************************************************** + * replacement of irq operations. + */ + +struct pv_irq_ops { + void (*register_ipi)(void); + + int (*assign_irq_vector)(int irq); + void (*free_irq_vector)(int vector); + + void (*register_percpu_irq)(ia64_vector vec, + struct irqaction *action); + + void (*resend_irq)(unsigned int vector); +}; + +extern struct pv_irq_ops pv_irq_ops; + +static inline void +ia64_register_ipi(void) +{ + pv_irq_ops.register_ipi(); +} + +static inline int +assign_irq_vector(int irq) +{ + return pv_irq_ops.assign_irq_vector(irq); +} + +static inline void +free_irq_vector(int vector) +{ + return pv_irq_ops.free_irq_vector(vector); +} + +static inline void +register_percpu_irq(ia64_vector vec, struct irqaction *action) +{ + pv_irq_ops.register_percpu_irq(vec, action); +} + +static inline void +ia64_resend_irq(unsigned int vector) +{ + pv_irq_ops.resend_irq(vector); +} + +/****************************************************************************** + * replacement of time operations. + */ + +extern struct itc_jitter_data_t itc_jitter_data; +extern volatile int time_keeper_id; + +struct pv_time_ops { + void (*init_missing_ticks_accounting)(int cpu); + int (*do_steal_accounting)(unsigned long *new_itm); + + void (*clocksource_resume)(void); +}; + +extern struct pv_time_ops pv_time_ops; + +static inline void +paravirt_init_missing_ticks_accounting(int cpu) +{ + if (pv_time_ops.init_missing_ticks_accounting) + pv_time_ops.init_missing_ticks_accounting(cpu); +} + +static inline int +paravirt_do_steal_accounting(unsigned long *new_itm) +{ + return pv_time_ops.do_steal_accounting(new_itm); +} + +#endif /* !__ASSEMBLY__ */ + +#else +/* fallback for native case */ + +#ifndef __ASSEMBLY__ + +#define paravirt_banner() do { } while (0) +#define paravirt_reserve_memory(region) 0 + +#define paravirt_arch_setup_early() do { } while (0) +#define paravirt_arch_setup_console(cmdline_p) do { } while (0) +#define paravirt_arch_setup_nomca() 0 +#define paravirt_post_smp_prepare_boot_cpu() do { } while (0) + +#define paravirt_init_missing_ticks_accounting(cpu) do { } while (0) +#define paravirt_do_steal_accounting(new_itm) 0 + +#endif /* __ASSEMBLY__ */ + + +#endif /* CONFIG_PARAVIRT_GUEST */ + +#endif /* __ASM_PARAVIRT_H */ diff --git a/include/asm-ia64/paravirt_privop.h b/include/asm-ia64/paravirt_privop.h new file mode 100644 index 000000000000..52482e6940ac --- /dev/null +++ b/include/asm-ia64/paravirt_privop.h @@ -0,0 +1,114 @@ +/****************************************************************************** + * include/asm-ia64/paravirt_privops.h + * + * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef _ASM_IA64_PARAVIRT_PRIVOP_H +#define _ASM_IA64_PARAVIRT_PRIVOP_H + +#ifdef CONFIG_PARAVIRT + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> +#include <asm/kregs.h> /* for IA64_PSR_I */ + +/****************************************************************************** + * replacement of intrinsics operations. + */ + +struct pv_cpu_ops { + void (*fc)(unsigned long addr); + unsigned long (*thash)(unsigned long addr); + unsigned long (*get_cpuid)(int index); + unsigned long (*get_pmd)(int index); + unsigned long (*getreg)(int reg); + void (*setreg)(int reg, unsigned long val); + void (*ptcga)(unsigned long addr, unsigned long size); + unsigned long (*get_rr)(unsigned long index); + void (*set_rr)(unsigned long index, unsigned long val); + void (*set_rr0_to_rr4)(unsigned long val0, unsigned long val1, + unsigned long val2, unsigned long val3, + unsigned long val4); + void (*ssm_i)(void); + void (*rsm_i)(void); + unsigned long (*get_psr_i)(void); + void (*intrin_local_irq_restore)(unsigned long flags); +}; + +extern struct pv_cpu_ops pv_cpu_ops; + +extern void ia64_native_setreg_func(int regnum, unsigned long val); +extern unsigned long ia64_native_getreg_func(int regnum); + +/************************************************/ +/* Instructions paravirtualized for performance */ +/************************************************/ + +/* mask for ia64_native_ssm/rsm() must be constant.("i" constraing). + * static inline function doesn't satisfy it. */ +#define paravirt_ssm(mask) \ + do { \ + if ((mask) == IA64_PSR_I) \ + pv_cpu_ops.ssm_i(); \ + else \ + ia64_native_ssm(mask); \ + } while (0) + +#define paravirt_rsm(mask) \ + do { \ + if ((mask) == IA64_PSR_I) \ + pv_cpu_ops.rsm_i(); \ + else \ + ia64_native_rsm(mask); \ + } while (0) + +/****************************************************************************** + * replacement of hand written assembly codes. + */ +struct pv_cpu_asm_switch { + unsigned long switch_to; + unsigned long leave_syscall; + unsigned long work_processed_syscall; + unsigned long leave_kernel; +}; +void paravirt_cpu_asm_init(const struct pv_cpu_asm_switch *cpu_asm_switch); + +#endif /* __ASSEMBLY__ */ + +#define IA64_PARAVIRT_ASM_FUNC(name) paravirt_ ## name + +#else + +/* fallback for native case */ +#define IA64_PARAVIRT_ASM_FUNC(name) ia64_native_ ## name + +#endif /* CONFIG_PARAVIRT */ + +/* these routines utilize privilege-sensitive or performance-sensitive + * privileged instructions so the code must be replaced with + * paravirtualized versions */ +#define ia64_switch_to IA64_PARAVIRT_ASM_FUNC(switch_to) +#define ia64_leave_syscall IA64_PARAVIRT_ASM_FUNC(leave_syscall) +#define ia64_work_processed_syscall \ + IA64_PARAVIRT_ASM_FUNC(work_processed_syscall) +#define ia64_leave_kernel IA64_PARAVIRT_ASM_FUNC(leave_kernel) + +#endif /* _ASM_IA64_PARAVIRT_PRIVOP_H */ diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h index ec5f355fb7e3..2984e262fc6c 100644 --- a/include/asm-ia64/smp.h +++ b/include/asm-ia64/smp.h @@ -15,6 +15,7 @@ #include <linux/kernel.h> #include <linux/cpumask.h> #include <linux/bitops.h> +#include <linux/irqreturn.h> #include <asm/io.h> #include <asm/param.h> @@ -123,6 +124,7 @@ extern void __init smp_build_cpu_map(void); extern void __init init_smp_config (void); extern void smp_do_timer (struct pt_regs *regs); +extern irqreturn_t handle_IPI(int irq, void *dev_id); extern void smp_send_reschedule (int cpu); extern void lock_ipi_calllock(void); extern void unlock_ipi_calllock(void); diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h index 26e250bfb912..927a381c20ca 100644 --- a/include/asm-ia64/system.h +++ b/include/asm-ia64/system.h @@ -26,6 +26,7 @@ */ #define KERNEL_START (GATE_ADDR+__IA64_UL_CONST(0x100000000)) #define PERCPU_ADDR (-PERCPU_PAGE_SIZE) +#define LOAD_OFFSET (KERNEL_START - KERNEL_TR_PAGE_SIZE) #ifndef __ASSEMBLY__ @@ -122,10 +123,16 @@ extern struct ia64_boot_param { * write a floating-point register right before reading the PSR * and that writes to PSR.mfl */ +#ifdef CONFIG_PARAVIRT +#define __local_save_flags() ia64_get_psr_i() +#else +#define __local_save_flags() ia64_getreg(_IA64_REG_PSR) +#endif + #define __local_irq_save(x) \ do { \ ia64_stop(); \ - (x) = ia64_getreg(_IA64_REG_PSR); \ + (x) = __local_save_flags(); \ ia64_stop(); \ ia64_rsm(IA64_PSR_I); \ } while (0) @@ -173,7 +180,7 @@ do { \ #endif /* !CONFIG_IA64_DEBUG_IRQ */ #define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); }) -#define local_save_flags(flags) ({ ia64_stop(); (flags) = ia64_getreg(_IA64_REG_PSR); }) +#define local_save_flags(flags) ({ ia64_stop(); (flags) = __local_save_flags(); }) #define irqs_disabled() \ ({ \ diff --git a/include/asm-m32r/uaccess.h b/include/asm-m32r/uaccess.h index bd8c83765a5c..1c7047bea200 100644 --- a/include/asm-m32r/uaccess.h +++ b/include/asm-m32r/uaccess.h @@ -14,6 +14,7 @@ #include <linux/errno.h> #include <linux/thread_info.h> #include <asm/page.h> +#include <asm/setup.h> #define VERIFY_READ 0 #define VERIFY_WRITE 1 @@ -106,7 +107,6 @@ static inline void set_fs(mm_segment_t s) #else static inline int access_ok(int type, const void *addr, unsigned long size) { - extern unsigned long memory_start, memory_end; unsigned long val = (unsigned long)addr; return ((val >= memory_start) && ((val + size) < memory_end)); diff --git a/include/asm-m68k/apollodma.h b/include/asm-m68k/apollodma.h index 6821e3ba32e9..954adc851adb 100644 --- a/include/asm-m68k/apollodma.h +++ b/include/asm-m68k/apollodma.h @@ -1,4 +1,4 @@ -/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $ +/* * linux/include/asm/dma.h: Defines for using and allocating dma channels. * Written by Hennus Bergman, 1992. * High DMA channel support & info by Hannu Savolainen diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h index 83d1f286230b..3e8106442d5a 100644 --- a/include/asm-m68k/bitops.h +++ b/include/asm-m68k/bitops.h @@ -410,8 +410,49 @@ static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size, res = ext2_find_first_zero_bit (p, size - 32 * (p - addr)); return (p - addr) * 32 + res; } -#define ext2_find_next_bit(addr, size, off) \ - generic_find_next_le_bit((unsigned long *)(addr), (size), (off)) + +static inline int ext2_find_first_bit(const void *vaddr, unsigned size) +{ + const unsigned long *p = vaddr, *addr = vaddr; + int res; + + if (!size) + return 0; + + size = (size >> 5) + ((size & 31) > 0); + while (*p++ == 0UL) { + if (--size == 0) + return (p - addr) << 5; + } + + --p; + for (res = 0; res < 32; res++) + if (ext2_test_bit(res, p)) + break; + return (p - addr) * 32 + res; +} + +static inline int ext2_find_next_bit(const void *vaddr, unsigned size, + unsigned offset) +{ + const unsigned long *addr = vaddr; + const unsigned long *p = addr + (offset >> 5); + int bit = offset & 31UL, res; + + if (offset >= size) + return size; + + if (bit) { + /* Look for one in first longword */ + for (res = bit; res < 32; res++) + if (ext2_test_bit(res, p)) + return (p - addr) * 32 + res; + p++; + } + /* No set bit yet, search remaining full bytes for a set bit */ + res = ext2_find_first_bit(p, size - 32 * (p - addr)); + return (p - addr) * 32 + res; +} #endif /* __KERNEL__ */ diff --git a/include/asm-m68k/dvma.h b/include/asm-m68k/dvma.h index e1112de5a5e3..5d2863164adc 100644 --- a/include/asm-m68k/dvma.h +++ b/include/asm-m68k/dvma.h @@ -1,4 +1,4 @@ -/* $Id: dvma.h,v 1.4 1999/03/27 20:23:41 tsbogend Exp $ +/* * include/asm-m68k/dma.h * * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu) diff --git a/include/asm-m68k/fpu.h b/include/asm-m68k/fpu.h index 59701d7b4e78..ffb6b8cfc6d5 100644 --- a/include/asm-m68k/fpu.h +++ b/include/asm-m68k/fpu.h @@ -7,15 +7,15 @@ */ #if defined(CONFIG_M68020) || defined(CONFIG_M68030) -#define FPSTATESIZE (216/sizeof(unsigned char)) +#define FPSTATESIZE (216) #elif defined(CONFIG_M68040) -#define FPSTATESIZE (96/sizeof(unsigned char)) +#define FPSTATESIZE (96) #elif defined(CONFIG_M68KFPU_EMU) -#define FPSTATESIZE (28/sizeof(unsigned char)) +#define FPSTATESIZE (28) #elif defined(CONFIG_M68060) -#define FPSTATESIZE (12/sizeof(unsigned char)) +#define FPSTATESIZE (12) #else -#define FPSTATESIZE error no_cpu_type_configured +#define FPSTATESIZE (0) #endif #endif /* __M68K_FPU_H */ diff --git a/include/asm-m68k/irq.h b/include/asm-m68k/irq.h index eb29a5260591..226bfc0f21b1 100644 --- a/include/asm-m68k/irq.h +++ b/include/asm-m68k/irq.h @@ -24,7 +24,7 @@ #elif defined(CONFIG_HP300) #define NR_IRQS 8 #else -#error unknown nr of irqs +#define NR_IRQS 0 #endif /* diff --git a/include/asm-m68k/machines.h b/include/asm-m68k/machines.h index da6015a90f24..748a78637fa6 100644 --- a/include/asm-m68k/machines.h +++ b/include/asm-m68k/machines.h @@ -1,4 +1,4 @@ -/* $Id: machines.h,v 1.4 1995/11/25 02:31:58 davem Exp $ +/* * machines.h: Defines for taking apart the machine type value in the * idprom and determining the kind of machine we are on. * diff --git a/include/asm-m68k/md.h b/include/asm-m68k/md.h index 467ea08383e4..d2f78f226f3d 100644 --- a/include/asm-m68k/md.h +++ b/include/asm-m68k/md.h @@ -1,4 +1,4 @@ -/* $Id: md.h,v 1.1 1997/12/15 15:12:04 jj Exp $ +/* * md.h: High speed xor_block operation for RAID4/5 * */ diff --git a/include/asm-m68k/openprom.h b/include/asm-m68k/openprom.h index 869ab9176e9f..d33cdadf78e1 100644 --- a/include/asm-m68k/openprom.h +++ b/include/asm-m68k/openprom.h @@ -1,4 +1,3 @@ -/* $Id: openprom.h,v 1.19 1996/09/25 03:51:08 davem Exp $ */ #ifndef __SPARC_OPENPROM_H #define __SPARC_OPENPROM_H diff --git a/include/asm-m68k/oplib.h b/include/asm-m68k/oplib.h index 06caa2d08451..f082d03336bd 100644 --- a/include/asm-m68k/oplib.h +++ b/include/asm-m68k/oplib.h @@ -1,4 +1,4 @@ -/* $Id: oplib.h,v 1.12 1996/10/31 06:29:13 davem Exp $ +/* * oplib.h: Describes the interface and available routines in the * Linux Prom library. * @@ -19,7 +19,6 @@ enum prom_major_version { PROM_V2, /* sun4c and early sun4m V2 prom */ PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */ PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */ - PROM_AP1000, /* actually no prom at all */ }; extern enum prom_major_version prom_vers; diff --git a/include/asm-m68k/sun3-head.h b/include/asm-m68k/sun3-head.h index e74f384e269f..05af2f18b3bd 100644 --- a/include/asm-m68k/sun3-head.h +++ b/include/asm-m68k/sun3-head.h @@ -1,4 +1,3 @@ -/* $Id: head.h,v 1.32 1996/12/04 00:12:48 ecd Exp $ */ #ifndef __SUN3_HEAD_H #define __SUN3_HEAD_H diff --git a/include/asm-m68k/tlbflush.h b/include/asm-m68k/tlbflush.h index 17707ec315e2..acb6bf21a321 100644 --- a/include/asm-m68k/tlbflush.h +++ b/include/asm-m68k/tlbflush.h @@ -16,7 +16,7 @@ static inline void flush_tlb_kernel_page(void *addr) ".chip 68k" : : "a" (addr)); set_fs(old_fs); - } else + } else if (CPU_IS_020_OR_030) __asm__ __volatile__("pflush #4,#4,(%0)" : : "a" (addr)); } @@ -29,7 +29,7 @@ static inline void __flush_tlb(void) __asm__ __volatile__(".chip 68040\n\t" "pflushan\n\t" ".chip 68k"); - else + else if (CPU_IS_020_OR_030) __asm__ __volatile__("pflush #0,#4"); } @@ -45,7 +45,7 @@ static inline void __flush_tlb_one(unsigned long addr) { if (CPU_IS_040_OR_060) __flush_tlb040_one(addr); - else + else if (CPU_IS_020_OR_030) __asm__ __volatile__("pflush #0,#4,(%0)" : : "a" (addr)); } @@ -60,7 +60,7 @@ static inline void flush_tlb_all(void) __asm__ __volatile__(".chip 68040\n\t" "pflusha\n\t" ".chip 68k"); - else + else if (CPU_IS_020_OR_030) __asm__ __volatile__("pflusha"); } diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h index ad17d7ce516a..44a67bf05dc1 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h +++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h @@ -355,6 +355,7 @@ void au1xxx_dbdma_dump(u32 chanid); u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); +extern void au1xxx_ddma_del_device(u32 devid); void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); /* diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index aa17f658f73c..a46f8e258e6b 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -765,6 +765,9 @@ do { \ #define read_c0_index() __read_32bit_c0_register($0, 0) #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) +#define read_c0_random() __read_32bit_c0_register($1, 0) +#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) + #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 2f597eea4448..6a0edf72ffbc 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -239,9 +239,10 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte.pte_low |= _PAGE_ACCESSED; - if (pte.pte_low & _PAGE_READ) + if (pte.pte_low & _PAGE_READ) { pte.pte_low |= _PAGE_SILENT_READ; pte.pte_high |= _PAGE_SILENT_READ; + } return pte; } #else diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h index 20b666022dcb..4ca3063ed2ce 100644 --- a/include/asm-mips/rtlx.h +++ b/include/asm-mips/rtlx.h @@ -3,7 +3,7 @@ * */ -#ifndef __ASM_RTLX_H +#ifndef __ASM_RTLX_H_ #define __ASM_RTLX_H_ #include <irq.h> diff --git a/include/asm-parisc/checksum.h b/include/asm-parisc/checksum.h index cc3ec1bd8919..e9639ccc3fce 100644 --- a/include/asm-parisc/checksum.h +++ b/include/asm-parisc/checksum.h @@ -65,7 +65,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) "2:\n" : "=r" (sum), "=r" (iph), "=r" (ihl) : "1" (iph), "2" (ihl) - : "r19", "r20", "r21" ); + : "r19", "r20", "r21", "memory"); return (__force __sum16)sum; } diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h index ede38ffe466a..63a55337c2de 100644 --- a/include/asm-powerpc/cpm.h +++ b/include/asm-powerpc/cpm.h @@ -96,6 +96,7 @@ unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); int cpm_muram_free(unsigned long offset); unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); void __iomem *cpm_muram_addr(unsigned long offset); +unsigned long cpm_muram_offset(void __iomem *addr); dma_addr_t cpm_muram_dma(void __iomem *addr); int cpm_command(u32 command, u8 opcode); diff --git a/include/asm-powerpc/dcr-generic.h b/include/asm-powerpc/dcr-generic.h new file mode 100644 index 000000000000..35b71599ec46 --- /dev/null +++ b/include/asm-powerpc/dcr-generic.h @@ -0,0 +1,49 @@ +/* + * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp. + * <benh@kernel.crashing.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + * the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _ASM_POWERPC_DCR_GENERIC_H +#define _ASM_POWERPC_DCR_GENERIC_H +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +enum host_type_t {DCR_HOST_MMIO, DCR_HOST_NATIVE, DCR_HOST_INVALID}; + +typedef struct { + enum host_type_t type; + union { + dcr_host_mmio_t mmio; + dcr_host_native_t native; + } host; +} dcr_host_t; + +extern bool dcr_map_ok_generic(dcr_host_t host); + +extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n, + unsigned int dcr_c); +extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c); + +extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n); + +extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value); + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL__ */ +#endif /* _ASM_POWERPC_DCR_GENERIC_H */ + + diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h index 08532ff1899c..acd491dbd45a 100644 --- a/include/asm-powerpc/dcr-mmio.h +++ b/include/asm-powerpc/dcr-mmio.h @@ -27,20 +27,26 @@ typedef struct { void __iomem *token; unsigned int stride; unsigned int base; -} dcr_host_t; +} dcr_host_mmio_t; -#define DCR_MAP_OK(host) ((host).token != NULL) +static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host) +{ + return host.token != NULL; +} -extern dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n, - unsigned int dcr_c); -extern void dcr_unmap(dcr_host_t host, unsigned int dcr_c); +extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev, + unsigned int dcr_n, + unsigned int dcr_c); +extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c); -static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n) +static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n) { return in_be32(host.token + ((host.base + dcr_n) * host.stride)); } -static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value) +static inline void dcr_write_mmio(dcr_host_mmio_t host, + unsigned int dcr_n, + u32 value) { out_be32(host.token + ((host.base + dcr_n) * host.stride), value); } diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h index f8398ce80372..72d2b72c7390 100644 --- a/include/asm-powerpc/dcr-native.h +++ b/include/asm-powerpc/dcr-native.h @@ -26,14 +26,18 @@ typedef struct { unsigned int base; -} dcr_host_t; +} dcr_host_native_t; -#define DCR_MAP_OK(host) (1) +static inline bool dcr_map_ok_native(dcr_host_native_t host) +{ + return 1; +} -#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) }) -#define dcr_unmap(host, dcr_c) do {} while (0) -#define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base) -#define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base, value) +#define dcr_map_native(dev, dcr_n, dcr_c) \ + ((dcr_host_native_t){ .base = (dcr_n) }) +#define dcr_unmap_native(host, dcr_c) do {} while (0) +#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base) +#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value) /* Device Control Registers */ void __mtdcr(int reg, unsigned int val); diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h index 9338d50538f1..53b283050ab3 100644 --- a/include/asm-powerpc/dcr.h +++ b/include/asm-powerpc/dcr.h @@ -20,14 +20,50 @@ #ifndef _ASM_POWERPC_DCR_H #define _ASM_POWERPC_DCR_H #ifdef __KERNEL__ +#ifndef __ASSEMBLY__ #ifdef CONFIG_PPC_DCR #ifdef CONFIG_PPC_DCR_NATIVE #include <asm/dcr-native.h> -#else +#endif + +#ifdef CONFIG_PPC_DCR_MMIO #include <asm/dcr-mmio.h> #endif + +/* Indirection layer for providing both NATIVE and MMIO support. */ + +#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) + +#include <asm/dcr-generic.h> + +#define DCR_MAP_OK(host) dcr_map_ok_generic(host) +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c) +#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c) +#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n) +#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value) + +#else + +#ifdef CONFIG_PPC_DCR_NATIVE +typedef dcr_host_native_t dcr_host_t; +#define DCR_MAP_OK(host) dcr_map_ok_native(host) +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c) +#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c) +#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n) +#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value) +#else +typedef dcr_host_mmio_t dcr_host_t; +#define DCR_MAP_OK(host) dcr_map_ok_mmio(host) +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c) +#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c) +#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n) +#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value) +#endif + +#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */ + /* * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR * base from the device-tree @@ -41,5 +77,6 @@ extern unsigned int dcr_resource_len(struct device_node *np, #endif /* CONFIG_PPC_MERGE */ #endif /* CONFIG_PPC_DCR */ +#endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_DCR_H */ diff --git a/include/asm-powerpc/fsl_gtm.h b/include/asm-powerpc/fsl_gtm.h new file mode 100644 index 000000000000..8e8c9b5032d3 --- /dev/null +++ b/include/asm-powerpc/fsl_gtm.h @@ -0,0 +1,47 @@ +/* + * Freescale General-purpose Timers Module + * + * Copyright (c) Freescale Semicondutor, Inc. 2006. + * Shlomi Gridish <gridish@freescale.com> + * Jerry Huang <Chang-Ming.Huang@freescale.com> + * Copyright (c) MontaVista Software, Inc. 2008. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_FSL_GTM_H +#define __ASM_FSL_GTM_H + +#include <linux/types.h> + +struct gtm; + +struct gtm_timer { + unsigned int irq; + + struct gtm *gtm; + bool requested; + u8 __iomem *gtcfr; + __be16 __iomem *gtmdr; + __be16 __iomem *gtpsr; + __be16 __iomem *gtcnr; + __be16 __iomem *gtrfr; + __be16 __iomem *gtevr; +}; + +extern struct gtm_timer *gtm_get_timer16(void); +extern struct gtm_timer *gtm_get_specific_timer16(struct gtm *gtm, + unsigned int timer); +extern void gtm_put_timer16(struct gtm_timer *tmr); +extern int gtm_set_timer16(struct gtm_timer *tmr, unsigned long usec, + bool reload); +extern int gtm_set_exact_timer16(struct gtm_timer *tmr, u16 usec, + bool reload); +extern void gtm_stop_timer16(struct gtm_timer *tmr); +extern void gtm_ack_timer16(struct gtm_timer *tmr, u16 events); + +#endif /* __ASM_FSL_GTM_H */ diff --git a/include/asm-powerpc/ftrace.h b/include/asm-powerpc/ftrace.h new file mode 100644 index 000000000000..b1bfa704b6e5 --- /dev/null +++ b/include/asm-powerpc/ftrace.h @@ -0,0 +1,6 @@ +#ifndef _ASM_POWERPC_FTRACE +#define _ASM_POWERPC_FTRACE + +extern void _mcount(void); + +#endif diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h index ad8c9f7fd0e3..f75a5fc64d2e 100644 --- a/include/asm-powerpc/hw_irq.h +++ b/include/asm-powerpc/hw_irq.h @@ -59,6 +59,11 @@ extern void iseries_handle_interrupts(void); get_paca()->hard_enabled = 0; \ } while(0) +static inline int irqs_disabled_flags(unsigned long flags) +{ + return flags == 0; +} + #else #if defined(CONFIG_BOOKE) @@ -113,6 +118,11 @@ static inline void local_irq_save_ptr(unsigned long *flags) #define hard_irq_enable() local_irq_enable() #define hard_irq_disable() local_irq_disable() +static inline int irqs_disabled_flags(unsigned long flags) +{ + return (flags & MSR_EE) == 0; +} + #endif /* CONFIG_PPC64 */ /* diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h index e0062d73db1c..6db422d8e2a0 100644 --- a/include/asm-powerpc/io.h +++ b/include/asm-powerpc/io.h @@ -95,33 +95,60 @@ extern resource_size_t isa_mem_base; #define IO_SET_SYNC_FLAG() #endif -#define DEF_MMIO_IN(name, type, insn) \ -static inline type name(const volatile type __iomem *addr) \ +/* gcc 4.0 and older doesn't have 'Z' constraint */ +#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0) +#define DEF_MMIO_IN_LE(name, size, insn) \ +static inline u##size name(const volatile u##size __iomem *addr) \ { \ - type ret; \ - __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync" \ - : "=r" (ret) : "r" (addr), "m" (*addr)); \ + u##size ret; \ + __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \ + : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \ return ret; \ } -#define DEF_MMIO_OUT(name, type, insn) \ -static inline void name(volatile type __iomem *addr, type val) \ +#define DEF_MMIO_OUT_LE(name, size, insn) \ +static inline void name(volatile u##size __iomem *addr, u##size val) \ { \ - __asm__ __volatile__("sync;" insn \ - : "=m" (*addr) : "r" (val), "r" (addr)); \ - IO_SET_SYNC_FLAG(); \ + __asm__ __volatile__("sync;"#insn" %1,0,%2" \ + : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \ + IO_SET_SYNC_FLAG(); \ } +#else /* newer gcc */ +#define DEF_MMIO_IN_LE(name, size, insn) \ +static inline u##size name(const volatile u##size __iomem *addr) \ +{ \ + u##size ret; \ + __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ + : "=r" (ret) : "Z" (*addr) : "memory"); \ + return ret; \ +} + +#define DEF_MMIO_OUT_LE(name, size, insn) \ +static inline void name(volatile u##size __iomem *addr, u##size val) \ +{ \ + __asm__ __volatile__("sync;"#insn" %1,%y0" \ + : "=Z" (*addr) : "r" (val) : "memory"); \ + IO_SET_SYNC_FLAG(); \ +} +#endif +#define DEF_MMIO_IN_BE(name, size, insn) \ +static inline u##size name(const volatile u##size __iomem *addr) \ +{ \ + u##size ret; \ + __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ + : "=r" (ret) : "m" (*addr) : "memory"); \ + return ret; \ +} -#define DEF_MMIO_IN_BE(name, size, insn) \ - DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2") -#define DEF_MMIO_IN_LE(name, size, insn) \ - DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1") +#define DEF_MMIO_OUT_BE(name, size, insn) \ +static inline void name(volatile u##size __iomem *addr, u##size val) \ +{ \ + __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ + : "=m" (*addr) : "r" (val) : "memory"); \ + IO_SET_SYNC_FLAG(); \ +} -#define DEF_MMIO_OUT_BE(name, size, insn) \ - DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0") -#define DEF_MMIO_OUT_LE(name, size, insn) \ - DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2") DEF_MMIO_IN_BE(in_8, 8, lbz); DEF_MMIO_IN_BE(in_be16, 16, lhz); @@ -333,7 +360,8 @@ static inline unsigned int name(unsigned int port) \ " .long 3b,5b\n" \ ".previous" \ : "=&r" (x) \ - : "r" (port + _IO_BASE)); \ + : "r" (port + _IO_BASE) \ + : "memory"); \ return x; \ } @@ -350,7 +378,8 @@ static inline void name(unsigned int val, unsigned int port) \ " .long 0b,2b\n" \ " .long 1b,2b\n" \ ".previous" \ - : : "r" (val), "r" (port + _IO_BASE)); \ + : : "r" (val), "r" (port + _IO_BASE) \ + : "memory"); \ } __do_in_asm(_rec_inb, "lbzx") diff --git a/include/asm-powerpc/ioctl.h b/include/asm-powerpc/ioctl.h index 8eb99848c402..57d68304218b 100644 --- a/include/asm-powerpc/ioctl.h +++ b/include/asm-powerpc/ioctl.h @@ -1,69 +1,13 @@ #ifndef _ASM_POWERPC_IOCTL_H #define _ASM_POWERPC_IOCTL_H - -/* - * this was copied from the alpha as it's a bit cleaner there. - * -- Cort - */ - -#define _IOC_NRBITS 8 -#define _IOC_TYPEBITS 8 #define _IOC_SIZEBITS 13 #define _IOC_DIRBITS 3 -#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) -#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) -#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) -#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) - -#define _IOC_NRSHIFT 0 -#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) -#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) -#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) - -/* - * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. - * And this turns out useful to catch old ioctl numbers in header - * files for us. - */ #define _IOC_NONE 1U #define _IOC_READ 2U #define _IOC_WRITE 4U -#define _IOC(dir,type,nr,size) \ - (((dir) << _IOC_DIRSHIFT) | \ - ((type) << _IOC_TYPESHIFT) | \ - ((nr) << _IOC_NRSHIFT) | \ - ((size) << _IOC_SIZESHIFT)) - -/* provoke compile error for invalid uses of size argument */ -extern unsigned int __invalid_size_argument_for_IOC; -#define _IOC_TYPECHECK(t) \ - ((sizeof(t) == sizeof(t[1]) && \ - sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ - sizeof(t) : __invalid_size_argument_for_IOC) - -/* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) -#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) - -/* used to decode them.. */ -#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) -#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) -#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) -#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) - -/* various drivers, such as the pcmcia stuff, need these... */ -#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) -#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) -#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) -#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) -#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) +#include <asm-generic/ioctl.h> #endif /* _ASM_POWERPC_IOCTL_H */ diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 5089deb8fec3..1ef8e304e0ea 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -619,6 +619,19 @@ struct pt_regs; #define __ARCH_HAS_DO_SOFTIRQ +#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) +/* + * Per-cpu stacks for handling critical, debug and machine check + * level interrupts. + */ +extern struct thread_info *critirq_ctx[NR_CPUS]; +extern struct thread_info *dbgirq_ctx[NR_CPUS]; +extern struct thread_info *mcheckirq_ctx[NR_CPUS]; +extern void exc_lvl_ctx_init(void); +#else +#define exc_lvl_ctx_init() +#endif + #ifdef CONFIG_IRQSTACKS /* * Per-cpu stacks for handling hard and soft interrupts. diff --git a/include/asm-powerpc/kvm_host.h b/include/asm-powerpc/kvm_host.h index 81a69d711017..2655e2a4831e 100644 --- a/include/asm-powerpc/kvm_host.h +++ b/include/asm-powerpc/kvm_host.h @@ -31,6 +31,8 @@ /* memory slots that does not exposed to userspace */ #define KVM_PRIVATE_MEM_SLOTS 4 +#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 + /* We don't currently support large pages. */ #define KVM_PAGES_PER_HPAGE (1<<31) diff --git a/include/asm-powerpc/kvm_ppc.h b/include/asm-powerpc/kvm_ppc.h index b35a7e3ef978..5a21115228af 100644 --- a/include/asm-powerpc/kvm_ppc.h +++ b/include/asm-powerpc/kvm_ppc.h @@ -57,6 +57,7 @@ extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu, extern int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu); +extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu); extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn, u64 asid, u32 flags); diff --git a/include/asm-powerpc/mediabay.h b/include/asm-powerpc/mediabay.h index df111c362a7f..b2cb0e867cfb 100644 --- a/include/asm-powerpc/mediabay.h +++ b/include/asm-powerpc/mediabay.h @@ -25,7 +25,6 @@ extern int media_bay_count; #ifdef CONFIG_BLK_DEV_IDE_PMAC #include <linux/ide.h> -int check_media_bay_by_base(unsigned long base, int what); /* called by IDE PMAC host driver to register IDE controller for media bay */ int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base, int irq, ide_hwif_t *hwif); diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h index 39c5c5f62bf5..d1dc16afb118 100644 --- a/include/asm-powerpc/mmu-hash64.h +++ b/include/asm-powerpc/mmu-hash64.h @@ -182,6 +182,7 @@ extern int mmu_io_psize; extern int mmu_kernel_ssize; extern int mmu_highuser_ssize; extern u16 mmu_slb_size; +extern unsigned long tce_alloc_start, tce_alloc_end; /* * If the processor supports 64k normal pages but not 64k cache diff --git a/include/asm-powerpc/mpc6xx.h b/include/asm-powerpc/mpc6xx.h new file mode 100644 index 000000000000..effc2291beb2 --- /dev/null +++ b/include/asm-powerpc/mpc6xx.h @@ -0,0 +1,6 @@ +#ifndef __ASM_POWERPC_MPC6xx_H +#define __ASM_POWERPC_MPC6xx_H + +void mpc6xx_enter_standby(void); + +#endif diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index a4d0f876b427..fe566a348a86 100644 --- a/include/asm-powerpc/mpic.h +++ b/include/asm-powerpc/mpic.h @@ -353,6 +353,8 @@ struct mpic #define MPIC_ENABLE_MCK 0x00000200 /* Disable bias among target selection, spread interrupts evenly */ #define MPIC_NO_BIAS 0x00000400 +/* Ignore NIRQS as reported by FRR */ +#define MPIC_BROKEN_FRR_NIRQS 0x00000800 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h index 6526e139a463..3c123990ca2e 100644 --- a/include/asm-powerpc/of_device.h +++ b/include/asm-powerpc/of_device.h @@ -21,8 +21,6 @@ extern struct of_device *of_device_alloc(struct device_node *np, const char *bus_id, struct device *parent); -extern ssize_t of_device_get_modalias(struct of_device *ofdev, - char *str, ssize_t len); extern int of_device_uevent(struct device *dev, struct kobj_uevent_env *env); diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h index 2dbd4e7884fa..ef96bfd4ef4c 100644 --- a/include/asm-powerpc/ppc_asm.h +++ b/include/asm-powerpc/ppc_asm.h @@ -356,6 +356,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #define toreal(rd) #define fromreal(rd) +/* + * We use addis to ensure compatibility with the "classic" ppc versions of + * these macros, which use rs = 0 to get the tophys offset in rd, rather than + * converting the address in r0, and so this version has to do that too + * (i.e. set register rd to 0 when rs == 0). + */ #define tophys(rd,rs) \ addis rd,rs,0 diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index cf83f2d7e2a5..a1deed85f31d 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h @@ -81,6 +81,10 @@ extern struct task_struct *last_task_used_altivec; extern struct task_struct *last_task_used_spe; #ifdef CONFIG_PPC32 + +#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START +#error User TASK_SIZE overlaps with KERNEL_START address +#endif #define TASK_SIZE (CONFIG_TASK_SIZE) /* This decides where the kernel will search for a free chunk of vm diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h index 39023dde1cc4..38d87e5e569d 100644 --- a/include/asm-powerpc/ptrace.h +++ b/include/asm-powerpc/ptrace.h @@ -119,6 +119,7 @@ extern int ptrace_put_reg(struct task_struct *task, int regno, #ifndef __powerpc64__ #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0) #define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0) +#define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0) #endif /* ! __powerpc64__ */ #define TRAP(regs) ((regs)->trap & ~0xF) #ifdef __powerpc64__ diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index c3be6e2e1490..80807fd6a706 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -16,6 +16,8 @@ #define _ASM_POWERPC_QE_H #ifdef __KERNEL__ +#include <linux/spinlock.h> +#include <asm/cpm.h> #include <asm/immap_qe.h> #define QE_NUM_OF_SNUM 28 @@ -74,10 +76,39 @@ enum qe_clock { QE_CLK_DUMMY }; +static inline bool qe_clock_is_brg(enum qe_clock clk) +{ + return clk >= QE_BRG1 && clk <= QE_BRG16; +} + +extern spinlock_t cmxgcr_lock; + /* Export QE common operations */ extern void qe_reset(void); + +/* QE PIO */ +#define QE_PIO_PINS 32 + +struct qe_pio_regs { + __be32 cpodr; /* Open drain register */ + __be32 cpdata; /* Data register */ + __be32 cpdir1; /* Direction register */ + __be32 cpdir2; /* Direction register */ + __be32 cppar1; /* Pin assignment register */ + __be32 cppar2; /* Pin assignment register */ +#ifdef CONFIG_PPC_85xx + u8 pad[8]; +#endif +}; + +extern void __init qe_add_gpiochips(void); extern int par_io_init(struct device_node *np); extern int par_io_of_config(struct device_node *np); +#define QE_PIO_DIR_IN 2 +#define QE_PIO_DIR_OUT 1 +extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, + int dir, int open_drain, int assignment, + int has_irq); extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, int assignment, int has_irq); extern int par_io_data_set(u8 port, u8 pin, u8 val); @@ -89,20 +120,13 @@ unsigned int qe_get_brg_clk(void); int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); int qe_get_snum(void); void qe_put_snum(u8 snum); -unsigned long qe_muram_alloc(int size, int align); -int qe_muram_free(unsigned long offset); -unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); -void qe_muram_dump(void); - -static inline void __iomem *qe_muram_addr(unsigned long offset) -{ - return (void __iomem *)&qe_immr->muram[offset]; -} - -static inline unsigned long qe_muram_offset(void __iomem *addr) -{ - return addr - (void __iomem *)qe_immr->muram; -} +/* we actually use cpm_muram implementation, define this for convenience */ +#define qe_muram_init cpm_muram_init +#define qe_muram_alloc cpm_muram_alloc +#define qe_muram_alloc_fixed cpm_muram_alloc_fixed +#define qe_muram_free cpm_muram_free +#define qe_muram_addr cpm_muram_addr +#define qe_muram_offset cpm_muram_offset /* Structure that defines QE firmware binary files. * @@ -156,6 +180,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware); /* Obtain information on the uploaded firmware */ struct qe_firmware_info *qe_get_firmware_info(void); +/* QE USB */ +int qe_usb_clock_set(enum qe_clock clk, int rate); + /* Buffer descriptors */ struct qe_bd { __be16 status; @@ -166,20 +193,6 @@ struct qe_bd { #define BD_STATUS_MASK 0xffff0000 #define BD_LENGTH_MASK 0x0000ffff -#define BD_SC_EMPTY 0x8000 /* Receive is empty */ -#define BD_SC_READY 0x8000 /* Transmit is ready */ -#define BD_SC_WRAP 0x2000 /* Last buffer descriptor */ -#define BD_SC_INTRPT 0x1000 /* Interrupt on change */ -#define BD_SC_LAST 0x0800 /* Last buffer in frame */ -#define BD_SC_CM 0x0200 /* Continous mode */ -#define BD_SC_ID 0x0100 /* Rec'd too many idles */ -#define BD_SC_P 0x0100 /* xmt preamble */ -#define BD_SC_BR 0x0020 /* Break received */ -#define BD_SC_FR 0x0010 /* Framing error */ -#define BD_SC_PR 0x0008 /* Parity error */ -#define BD_SC_OV 0x0002 /* Overrun */ -#define BD_SC_CD 0x0001 /* ?? */ - /* Alignment */ #define QE_INTR_TABLE_ALIGN 16 /* ??? */ #define QE_ALIGNMENT_OF_BD 8 @@ -254,6 +267,16 @@ enum comm_dir { #define QE_CMXGCR_MII_ENET_MNG 0x00007000 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 #define QE_CMXGCR_USBCS 0x0000000f +#define QE_CMXGCR_USBCS_CLK3 0x1 +#define QE_CMXGCR_USBCS_CLK5 0x2 +#define QE_CMXGCR_USBCS_CLK7 0x3 +#define QE_CMXGCR_USBCS_CLK9 0x4 +#define QE_CMXGCR_USBCS_CLK13 0x5 +#define QE_CMXGCR_USBCS_CLK17 0x6 +#define QE_CMXGCR_USBCS_CLK19 0x7 +#define QE_CMXGCR_USBCS_CLK21 0x8 +#define QE_CMXGCR_USBCS_BRG9 0x9 +#define QE_CMXGCR_USBCS_BRG10 0xa /* QE CECR Commands. */ @@ -283,7 +306,7 @@ enum comm_dir { #define QE_HPAC_START_TX 0x0000060b #define QE_HPAC_START_RX 0x0000070b #define QE_USB_STOP_TX 0x0000000a -#define QE_USB_RESTART_TX 0x0000000b +#define QE_USB_RESTART_TX 0x0000000c #define QE_QMC_STOP_TX 0x0000000c #define QE_QMC_STOP_RX 0x0000000d #define QE_SS7_SU_FIL_RESET 0x0000000e diff --git a/include/asm-powerpc/smp.h b/include/asm-powerpc/smp.h index 505f35bacaa9..1cd43e3d94fb 100644 --- a/include/asm-powerpc/smp.h +++ b/include/asm-powerpc/smp.h @@ -37,6 +37,8 @@ extern void cpu_die(void); extern void smp_send_debugger_break(int cpu); extern void smp_message_recv(int); +DECLARE_PER_CPU(unsigned int, pvr); + #ifdef CONFIG_HOTPLUG_CPU extern void fixup_irqs(cpumask_t map); int generic_cpu_disable(void); diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 2b6559a6d113..df781adac6dd 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -190,6 +190,7 @@ extern struct task_struct *_switch(struct thread_struct *prev, extern unsigned int rtas_data; extern int mem_init_done; /* set on boot once kmalloc can be called */ +extern int init_bootmem_done; /* set on !NUMA once bootmem is available */ extern unsigned long memory_limit; extern unsigned long klimit; diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h index d030f5ce39ad..b705c2a7651a 100644 --- a/include/asm-powerpc/thread_info.h +++ b/include/asm-powerpc/thread_info.h @@ -116,7 +116,6 @@ static inline struct thread_info *current_thread_info(void) #define TIF_SECCOMP 10 /* secure computing */ #define TIF_RESTOREALL 11 /* Restore all regs (implies NOERROR) */ #define TIF_NOERROR 12 /* Force successful syscall return */ -#define TIF_RESTORE_SIGMASK 13 /* Restore signal mask in do_signal */ #define TIF_FREEZE 14 /* Freezing for suspend */ #define TIF_RUNLATCH 15 /* Is the runlatch enabled? */ #define TIF_ABI_PENDING 16 /* 32/64 bit switch needed */ @@ -134,21 +133,33 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SECCOMP (1<<TIF_SECCOMP) #define _TIF_RESTOREALL (1<<TIF_RESTOREALL) #define _TIF_NOERROR (1<<TIF_NOERROR) -#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) #define _TIF_FREEZE (1<<TIF_FREEZE) #define _TIF_RUNLATCH (1<<TIF_RUNLATCH) #define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) #define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP) -#define _TIF_USER_WORK_MASK ( _TIF_SIGPENDING | \ - _TIF_NEED_RESCHED | _TIF_RESTORE_SIGMASK) +#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED) #define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR) /* Bits in local_flags */ /* Don't move TLF_NAPPING without adjusting the code in entry_32.S */ #define TLF_NAPPING 0 /* idle thread enabled NAP mode */ +#define TLF_SLEEPING 1 /* suspend code enabled SLEEP mode */ +#define TLF_RESTORE_SIGMASK 2 /* Restore signal mask in do_signal */ #define _TLF_NAPPING (1 << TLF_NAPPING) +#define _TLF_SLEEPING (1 << TLF_SLEEPING) +#define _TLF_RESTORE_SIGMASK (1 << TLF_RESTORE_SIGMASK) + +#ifndef __ASSEMBLY__ +#define HAVE_SET_RESTORE_SIGMASK 1 +static inline void set_restore_sigmask(void) +{ + struct thread_info *ti = current_thread_info(); + ti->local_flags |= _TLF_RESTORE_SIGMASK; + set_bit(TIF_SIGPENDING, &ti->flags); +} +#endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h index ce5de6e0e690..febd581ec9b0 100644 --- a/include/asm-powerpc/time.h +++ b/include/asm-powerpc/time.h @@ -33,6 +33,7 @@ extern unsigned tb_to_us; struct rtc_time; extern void to_tm(int tim, struct rtc_time * tm); +extern void GregorianDay(struct rtc_time *tm); extern time_t last_rtc_update; extern void generic_calibrate_decr(void); diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h index 88320a05f0a8..5eb8e599e5cc 100644 --- a/include/asm-powerpc/xmon.h +++ b/include/asm-powerpc/xmon.h @@ -12,13 +12,22 @@ #ifdef __KERNEL__ +#include <linux/irqreturn.h> + #ifdef CONFIG_XMON extern void xmon_setup(void); extern void xmon_register_spus(struct list_head *list); +struct pt_regs; +extern int xmon(struct pt_regs *excp); +extern irqreturn_t xmon_irq(int, void *); #else static inline void xmon_setup(void) { }; static inline void xmon_register_spus(struct list_head *list) { }; #endif +#if defined(CONFIG_XMON) && defined(CONFIG_SMP) +extern int cpus_are_in_xmon(void); +#endif + #endif /* __KERNEL __ */ #endif /* __ASM_POWERPC_XMON_H */ diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h deleted file mode 100644 index 4b0e15206006..000000000000 --- a/include/asm-ppc/8xx_immap.h +++ /dev/null @@ -1,564 +0,0 @@ -/* - * MPC8xx Internal Memory Map - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * The I/O on the MPC860 is comprised of blocks of special registers - * and the dual port ram for the Communication Processor Module. - * Within this space are functional units such as the SIU, memory - * controller, system timers, and other control functions. It is - * a combination that I found difficult to separate into logical - * functional files.....but anyone else is welcome to try. -- Dan - */ -#ifdef __KERNEL__ -#ifndef __IMMAP_8XX__ -#define __IMMAP_8XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - uint sc_swt; - char res1[2]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - char res2[0xc]; - uint sc_sdcr; - char res3[0x4c]; -} sysconf8xx_t; - -/* PCMCIA configuration registers. -*/ -typedef struct pcmcia_conf { - uint pcmc_pbr0; - uint pcmc_por0; - uint pcmc_pbr1; - uint pcmc_por1; - uint pcmc_pbr2; - uint pcmc_por2; - uint pcmc_pbr3; - uint pcmc_por3; - uint pcmc_pbr4; - uint pcmc_por4; - uint pcmc_pbr5; - uint pcmc_por5; - uint pcmc_pbr6; - uint pcmc_por6; - uint pcmc_pbr7; - uint pcmc_por7; - char res1[0x20]; - uint pcmc_pgcra; - uint pcmc_pgcrb; - uint pcmc_pscr; - char res2[4]; - uint pcmc_pipr; - char res3[4]; - uint pcmc_per; - char res4[4]; -} pcmconf8xx_t; - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - uint memc_br4; - uint memc_or4; - uint memc_br5; - uint memc_or5; - uint memc_br6; - uint memc_or6; - uint memc_br7; - uint memc_or7; - char res1[0x24]; - uint memc_mar; - uint memc_mcr; - char res2[4]; - uint memc_mamr; - uint memc_mbmr; - ushort memc_mstat; - ushort memc_mptpr; - uint memc_mdr; - char res3[0x80]; -} memctl8xx_t; - -/*----------------------------------------------------------------------- - * BR - Memory Controler: Base Register 16-9 - */ -#define BR_BA_MSK 0xffff8000 /* Base Address Mask */ -#define BR_AT_MSK 0x00007000 /* Address Type Mask */ -#define BR_PS_MSK 0x00000c00 /* Port Size Mask */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PARE 0x00000200 /* Parity Enable */ -#define BR_WP 0x00000100 /* Write Protect */ -#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */ -#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ -#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ -#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */ -#define BR_V 0x00000001 /* Bank Valid */ - -/*----------------------------------------------------------------------- - * OR - Memory Controler: Option Register 16-11 - */ -#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */ -#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ -#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ - /* Address Multiplex */ -#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ -#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ -#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ -#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ -#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ -#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ -#define OR_BI 0x00000100 /* Burst inhibit */ -#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */ -#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ -#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ -#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ -#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ -#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ -#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ -#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ -#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ -#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ -#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ -#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ -#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ -#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ -#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ -#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ -#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ -#define OR_SETA 0x00000008 /* External Transfer Acknowledge */ -#define OR_TRLX 0x00000004 /* Timing Relaxed */ -#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - ushort sit_tbscr; - char res0[0x02]; - uint sit_tbreff0; - uint sit_tbreff1; - char res1[0x14]; - ushort sit_rtcsc; - char res2[0x02]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res3[0x10]; - ushort sit_piscr; - char res4[2]; - uint sit_pitc; - uint sit_pitr; - char res5[0x34]; -} sit8xx_t; - -#define TBSCR_TBIRQ_MASK ((ushort)0xff00) -#define TBSCR_REFA ((ushort)0x0080) -#define TBSCR_REFB ((ushort)0x0040) -#define TBSCR_REFAE ((ushort)0x0008) -#define TBSCR_REFBE ((ushort)0x0004) -#define TBSCR_TBF ((ushort)0x0002) -#define TBSCR_TBE ((ushort)0x0001) - -#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) -#define RTCSC_SEC ((ushort)0x0080) -#define RTCSC_ALR ((ushort)0x0040) -#define RTCSC_38K ((ushort)0x0010) -#define RTCSC_SIE ((ushort)0x0008) -#define RTCSC_ALE ((ushort)0x0004) -#define RTCSC_RTF ((ushort)0x0002) -#define RTCSC_RTE ((ushort)0x0001) - -#define PISCR_PIRQ_MASK ((ushort)0xff00) -#define PISCR_PS ((ushort)0x0080) -#define PISCR_PIE ((ushort)0x0004) -#define PISCR_PTF ((ushort)0x0002) -#define PISCR_PTE ((ushort)0x0001) - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - uint car_rsr; - char res[0x74]; /* Reserved area */ -} car8xx_t; - -/* System Integration Timers keys. -*/ -typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbreff0k; - uint sitk_tbreff1k; - uint sitk_tbk; - char res1[0x10]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[0x10]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[0x38]; -} sitk8xx_t; - -/* Clocks and reset keys. -*/ -typedef struct cark { - uint cark_sccrk; - uint cark_plprcrk; - uint cark_rsrk; - char res[0x474]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* Video interface. MPC823 Only. -*/ -typedef struct vid823 { - ushort vid_vccr; - ushort res1; - u_char vid_vsr; - u_char res2; - u_char vid_vcmr; - u_char res3; - uint vid_vbcb; - uint res4; - uint vid_vfcr0; - uint vid_vfaa0; - uint vid_vfba0; - uint vid_vfcr1; - uint vid_vfaa1; - uint vid_vfba1; - u_char res5[0x18]; -} vid823_t; - -/* LCD interface. 823 Only. -*/ -typedef struct lcd { - uint lcd_lccr; - uint lcd_lchcr; - uint lcd_lcvcr; - char res1[4]; - uint lcd_lcfaa; - uint lcd_lcfba; - char lcd_lcsr; - char res2[0x7]; -} lcd823_t; - -/* I2C -*/ -typedef struct i2c { - u_char i2c_i2mod; - char res1[3]; - u_char i2c_i2add; - char res2[3]; - u_char i2c_i2brg; - char res3[3]; - u_char i2c_i2com; - char res4[3]; - u_char i2c_i2cer; - char res5[3]; - u_char i2c_i2cmr; - char res6[0x8b]; -} i2c8xx_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res1[4]; - uint sdma_sdar; - u_char sdma_sdsr; - char res3[3]; - u_char sdma_sdmr; - char res4[3]; - u_char sdma_idsr1; - char res5[3]; - u_char sdma_idmr1; - char res6[3]; - u_char sdma_idsr2; - char res7[3]; - u_char sdma_idmr2; - char res8[0x13]; -} sdma8xx_t; - -/* Communication Processor Module Interrupt Controller. -*/ -typedef struct cpm_ic { - ushort cpic_civr; - char res[0xe]; - uint cpic_cicr; - uint cpic_cipr; - uint cpic_cimr; - uint cpic_cisr; -} cpic8xx_t; - -/* Input/Output Port control/status registers. -*/ -typedef struct io_port { - ushort iop_padir; - ushort iop_papar; - ushort iop_paodr; - ushort iop_padat; - char res1[8]; - ushort iop_pcdir; - ushort iop_pcpar; - ushort iop_pcso; - ushort iop_pcdat; - ushort iop_pcint; - char res2[6]; - ushort iop_pddir; - ushort iop_pdpar; - char res3[2]; - ushort iop_pddat; - uint utmode; - char res4[4]; -} iop8xx_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - ushort cpmt_tgcr; - char res1[0xe]; - ushort cpmt_tmr1; - ushort cpmt_tmr2; - ushort cpmt_trr1; - ushort cpmt_trr2; - ushort cpmt_tcr1; - ushort cpmt_tcr2; - ushort cpmt_tcn1; - ushort cpmt_tcn2; - ushort cpmt_tmr3; - ushort cpmt_tmr4; - ushort cpmt_trr3; - ushort cpmt_trr4; - ushort cpmt_tcr3; - ushort cpmt_tcr4; - ushort cpmt_tcn3; - ushort cpmt_tcn4; - ushort cpmt_ter1; - ushort cpmt_ter2; - ushort cpmt_ter3; - ushort cpmt_ter4; - char res2[8]; -} cpmtimer8xx_t; - -/* Finally, the Communication Processor stuff..... -*/ -typedef struct scc { /* Serial communication channels */ - uint scc_gsmrl; - uint scc_gsmrh; - ushort scc_psmr; - char res1[2]; - ushort scc_todr; - ushort scc_dsr; - ushort scc_scce; - char res2[2]; - ushort scc_sccm; - char res3; - u_char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - ushort smc_smcmr; - char res2[2]; - u_char smc_smce; - char res3[3]; - u_char smc_smcm; - char res4[5]; -} smc_t; - -/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but - * it fits within the address space. - */ - -typedef struct fec { - uint fec_addr_low; /* lower 32 bits of station address */ - ushort fec_addr_high; /* upper 16 bits of station address */ - ushort res1; /* reserved */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ - uint fec_r_des_start; /* beginning of Rx descriptor ring */ - uint fec_x_des_start; /* beginning of Tx descriptor ring */ - uint fec_r_buff_size; /* Rx buffer size */ - uint res2[9]; /* reserved */ - uint fec_ecntrl; /* ethernet control register */ - uint fec_ievent; /* interrupt event register */ - uint fec_imask; /* interrupt mask register */ - uint fec_ivec; /* interrupt level and vector status */ - uint fec_r_des_active; /* Rx ring updated flag */ - uint fec_x_des_active; /* Tx ring updated flag */ - uint res3[10]; /* reserved */ - uint fec_mii_data; /* MII data register */ - uint fec_mii_speed; /* MII speed control register */ - uint res4[17]; /* reserved */ - uint fec_r_bound; /* end of RAM (read-only) */ - uint fec_r_fstart; /* Rx FIFO start address */ - uint res5[6]; /* reserved */ - uint fec_x_fstart; /* Tx FIFO start address */ - uint res6[17]; /* reserved */ - uint fec_fun_code; /* fec SDMA function code */ - uint res7[3]; /* reserved */ - uint fec_r_cntrl; /* Rx control register */ - uint fec_r_hash; /* Rx hash register */ - uint res8[14]; /* reserved */ - uint fec_x_cntrl; /* Tx control register */ - uint res9[0x1e]; /* reserved */ -} fec_t; - -/* The FEC and LCD color map share the same address space.... - * I guess we will never see an 823T :-). - */ -union fec_lcd { - fec_t fl_un_fec; - u_char fl_un_cmap[0x200]; -}; - -typedef struct comm_proc { - /* General control and status registers. - */ - ushort cp_cpcr; - u_char res1[2]; - ushort cp_rccr; - u_char res2; - u_char cp_rmds; - u_char res3[4]; - ushort cp_cpmcr1; - ushort cp_cpmcr2; - ushort cp_cpmcr3; - ushort cp_cpmcr4; - u_char res4[2]; - ushort cp_rter; - u_char res5[2]; - ushort cp_rtmr; - u_char res6[0x14]; - - /* Baud rate generators. - */ - uint cp_brgc1; - uint cp_brgc2; - uint cp_brgc3; - uint cp_brgc4; - - /* Serial Communication Channels. - */ - scc_t cp_scc[4]; - - /* Serial Management Channels. - */ - smc_t cp_smc[2]; - - /* Serial Peripheral Interface. - */ - ushort cp_spmode; - u_char res7[4]; - u_char cp_spie; - u_char res8[3]; - u_char cp_spim; - u_char res9[2]; - u_char cp_spcom; - u_char res10[2]; - - /* Parallel Interface Port. - */ - u_char res11[2]; - ushort cp_pipc; - u_char res12[2]; - ushort cp_ptpr; - uint cp_pbdir; - uint cp_pbpar; - u_char res13[2]; - ushort cp_pbodr; - uint cp_pbdat; - - /* Port E - MPC87x/88x only. - */ - uint cp_pedir; - uint cp_pepar; - uint cp_peso; - uint cp_peodr; - uint cp_pedat; - - /* Communications Processor Timing Register - - Contains RMII Timing for the FECs on MPC87x/88x only. - */ - uint cp_cptr; - - /* Serial Interface and Time Slot Assignment. - */ - uint cp_simode; - u_char cp_sigmr; - u_char res15; - u_char cp_sistr; - u_char cp_sicmr; - u_char res16[4]; - uint cp_sicr; - uint cp_sirp; - u_char res17[0xc]; - - /* 256 bytes of MPC823 video controller RAM array. - */ - u_char cp_vcram[0x100]; - u_char cp_siram[0x200]; - - /* The fast ethernet controller is not really part of the CPM, - * but it resides in the address space. - * The LCD color map is also here. - */ - union fec_lcd fl_un; -#define cp_fec fl_un.fl_un_fec -#define lcd_cmap fl_un.fl_un_cmap - char res18[0xE00]; - - /* The DUET family has a second FEC here */ - fec_t cp_fec2; -#define cp_fec1 cp_fec /* consistency macro */ - - /* Dual Ported RAM follows. - * There are many different formats for this memory area - * depending upon the devices used and options chosen. - * Some processors don't have all of it populated. - */ - u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ - u_char cp_dparam[0x400]; /* Parameter RAM */ -} cpm8xx_t; - -/* Internal memory map. -*/ -typedef struct immap { - sysconf8xx_t im_siu_conf; /* SIU Configuration */ - pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ - memctl8xx_t im_memctl; /* Memory Controller */ - sit8xx_t im_sit; /* System integration timers */ - car8xx_t im_clkrst; /* Clocks and reset */ - sitk8xx_t im_sitk; /* Sys int timer keys */ - cark8xx_t im_clkrstk; /* Clocks and reset keys */ - vid823_t im_vid; /* Video (823 only) */ - lcd823_t im_lcd; /* LCD (823 only) */ - i2c8xx_t im_i2c; /* I2C control/status */ - sdma8xx_t im_sdma; /* SDMA control/status */ - cpic8xx_t im_cpic; /* CPM Interrupt Controller */ - iop8xx_t im_ioport; /* IO Port control/status */ - cpmtimer8xx_t im_cpmtimer; /* CPM timers */ - cpm8xx_t im_cpm; /* Communication processor */ -} immap_t; - -#endif /* __IMMAP_8XX__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/amigayle.h b/include/asm-ppc/amigayle.h deleted file mode 100644 index 1fe0b87859b0..000000000000 --- a/include/asm-ppc/amigayle.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-m68k/amigayle.h> diff --git a/include/asm-ppc/amipcmcia.h b/include/asm-ppc/amipcmcia.h deleted file mode 100644 index 3f65f63f508f..000000000000 --- a/include/asm-ppc/amipcmcia.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-m68k/amipcmcia.h> diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h deleted file mode 100644 index f6ed77aee328..000000000000 --- a/include/asm-ppc/bootinfo.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Non-machine dependent bootinfo structure. Basic idea - * borrowed from the m68k. - * - * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org> - */ - -#ifdef __KERNEL__ -#ifndef _PPC_BOOTINFO_H -#define _PPC_BOOTINFO_H - -#include <asm/page.h> - -struct bi_record { - unsigned long tag; /* tag ID */ - unsigned long size; /* size of record (in bytes) */ - unsigned long data[0]; /* data */ -}; - -#define BI_FIRST 0x1010 /* first record - marker */ -#define BI_LAST 0x1011 /* last record - marker */ -#define BI_CMD_LINE 0x1012 -#define BI_BOOTLOADER_ID 0x1013 -#define BI_INITRD 0x1014 -#define BI_SYSMAP 0x1015 -#define BI_MACHTYPE 0x1016 -#define BI_MEMSIZE 0x1017 -#define BI_BOARD_INFO 0x1018 - -extern struct bi_record *find_bootinfo(void); -extern void bootinfo_init(struct bi_record *rec); -extern void bootinfo_append(unsigned long tag, unsigned long size, void * data); -extern void parse_bootinfo(struct bi_record *rec); -extern unsigned long boot_mem_size; - -static inline struct bi_record * -bootinfo_addr(unsigned long offset) -{ - - return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1, - (1 << 20)); -} - - -#endif /* _PPC_BOOTINFO_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h deleted file mode 100644 index b0c51b45d7a2..000000000000 --- a/include/asm-ppc/bootx.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file describes the structure passed from the BootX application - * (for MacOS) when it is used to boot Linux. - * - * Written by Benjamin Herrenschmidt. - */ - - -#ifndef __ASM_BOOTX_H__ -#define __ASM_BOOTX_H__ - -#ifdef macintosh -#include <Types.h> -#include "linux_type_defs.h" -#endif - -#ifdef macintosh -/* All this requires PowerPC alignment */ -#pragma options align=power -#endif - -/* On kernel entry: - * - * r3 = 0x426f6f58 ('BooX') - * r4 = pointer to boot_infos - * r5 = NULL - * - * Data and instruction translation disabled, interrupts - * disabled, kernel loaded at physical 0x00000000 on PCI - * machines (will be different on NuBus). - */ - -#define BOOT_INFO_VERSION 5 -#define BOOT_INFO_COMPATIBLE_VERSION 1 - -/* Bit in the architecture flag mask. More to be defined in - future versions. Note that either BOOT_ARCH_PCI or - BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are - set additionally when BOOT_ARCH_NUBUS is set. - */ -#define BOOT_ARCH_PCI 0x00000001UL -#define BOOT_ARCH_NUBUS 0x00000002UL -#define BOOT_ARCH_NUBUS_PDM 0x00000010UL -#define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL -#define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL - -/* Maximum number of ranges in phys memory map */ -#define MAX_MEM_MAP_SIZE 26 - -/* This is the format of an element in the physical memory map. Note that - the map is optional and current BootX will only build it for pre-PCI - machines */ -typedef struct boot_info_map_entry -{ - __u32 physAddr; /* Physical starting address */ - __u32 size; /* Size in bytes */ -} boot_info_map_entry_t; - - -/* Here are the boot informations that are passed to the bootstrap - * Note that the kernel arguments and the device tree are appended - * at the end of this structure. */ -typedef struct boot_infos -{ - /* Version of this structure */ - __u32 version; - /* backward compatible down to version: */ - __u32 compatible_version; - - /* NEW (vers. 2) this holds the current _logical_ base addr of - the frame buffer (for use by early boot message) */ - __u8* logicalDisplayBase; - - /* NEW (vers. 4) Apple's machine identification */ - __u32 machineID; - - /* NEW (vers. 4) Detected hw architecture */ - __u32 architecture; - - /* The device tree (internal addresses relative to the beginning of the tree, - * device tree offset relative to the beginning of this structure). - * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this - * field is 0. - */ - __u32 deviceTreeOffset; /* Device tree offset */ - __u32 deviceTreeSize; /* Size of the device tree */ - - /* Some infos about the current MacOS display */ - __u32 dispDeviceRect[4]; /* left,top,right,bottom */ - __u32 dispDeviceDepth; /* (8, 16 or 32) */ - __u8* dispDeviceBase; /* base address (physical) */ - __u32 dispDeviceRowBytes; /* rowbytes (in bytes) */ - __u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */ - /* Optional offset in the registry to the current - * MacOS display. (Can be 0 when not detected) */ - __u32 dispDeviceRegEntryOffset; - - /* Optional pointer to boot ramdisk (offset from this structure) */ - __u32 ramDisk; - __u32 ramDiskSize; /* size of ramdisk image */ - - /* Kernel command line arguments (offset from this structure) */ - __u32 kernelParamsOffset; - - /* ALL BELOW NEW (vers. 4) */ - - /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag - (non-PCI) only. On PCI, memory is contiguous and it's size is in the - device-tree. */ - boot_info_map_entry_t - physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */ - __u32 physMemoryMapSize; /* How many entries in map */ - - - /* The framebuffer size (optional, currently 0) */ - __u32 frameBufferSize; /* Represents a max size, can be 0. */ - - /* NEW (vers. 5) */ - - /* Total params size (args + colormap + device tree + ramdisk) */ - __u32 totalParamsSize; - -} boot_infos_t; - -/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented - * by 3 short words containing a 16 bits (unsigned) color component. - * Later versions may contain the gamma table for direct-color devices here. - */ -#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL) - -#ifdef macintosh -#pragma options align=reset -#endif - -#endif diff --git a/include/asm-ppc/btext.h b/include/asm-ppc/btext.h deleted file mode 100644 index ed3630251b3b..000000000000 --- a/include/asm-ppc/btext.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Definitions for using the procedures in btext.c. - * - * Benjamin Herrenschmidt <benh@kernel.crashing.org> - */ -#ifndef __PPC_BTEXT_H -#define __PPC_BTEXT_H -#ifdef __KERNEL__ - -#include <asm/bootx.h> - -extern void btext_clearscreen(void); -extern void btext_flushscreen(void); - -extern unsigned long disp_BAT[2]; - -extern boot_infos_t disp_bi; -extern int boot_text_mapped; - -extern void btext_init(boot_infos_t *bi); -extern void btext_welcome(void); -extern void btext_prepare_BAT(void); -extern void btext_setup_display(int width, int height, int depth, int pitch, - unsigned long address); -extern void map_boot_text(void); -extern void btext_update_display(unsigned long phys, int width, int height, - int depth, int pitch); - -extern void btext_drawchar(char c); -extern void btext_drawstring(const char *str); -extern void btext_drawhex(unsigned long v); - -#endif /* __KERNEL__ */ -#endif /* __PPC_BTEXT_H */ diff --git a/include/asm-ppc/cpm1.h b/include/asm-ppc/cpm1.h deleted file mode 100644 index 03035acd85c6..000000000000 --- a/include/asm-ppc/cpm1.h +++ /dev/null @@ -1,688 +0,0 @@ -/* - * MPC8xx Communication Processor Module. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * This file contains structures and information for the communication - * processor channels. Some CPM control and status is available - * throught the MPC8xx internal memory map. See immap.h for details. - * This file only contains what I need for the moment, not the total - * CPM capabilities. I (or someone else) will add definitions as they - * are needed. -- Dan - * - * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 - * bytes of the DP RAM and relocates the I2C parameter area to the - * IDMA1 space. The remaining DP RAM is available for buffer descriptors - * or other use. - */ -#ifndef __CPM1__ -#define __CPM1__ - -#include <asm/8xx_immap.h> -#include <asm/ptrace.h> - -/* CPM Command register. -*/ -#define CPM_CR_RST ((ushort)0x8000) -#define CPM_CR_OPCODE ((ushort)0x0f00) -#define CPM_CR_CHAN ((ushort)0x00f0) -#define CPM_CR_FLG ((ushort)0x0001) - -/* Some commands (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) -#define CPM_CR_SET_GADDR ((ushort)0x0008) -#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR - -/* Channel numbers. -*/ -#define CPM_CR_CH_SCC1 ((ushort)0x0000) -#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ -#define CPM_CR_CH_SCC2 ((ushort)0x0004) -#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ -#define CPM_CR_CH_TIMER CPM_CR_CH_SPI -#define CPM_CR_CH_SCC3 ((ushort)0x0008) -#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ -#define CPM_CR_CH_SCC4 ((ushort)0x000c) -#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ - -#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) - -/* The dual ported RAM is multi-functional. Some areas can be (and are - * being) used for microcode. There is an area that can only be used - * as data ram for buffer descriptors, which is all we use right now. - * Currently the first 512 and last 256 bytes are used for microcode. - */ -#define CPM_DATAONLY_BASE ((uint)0x0800) -#define CPM_DATAONLY_SIZE ((uint)0x0700) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm8xx_t *cpmp; /* Pointer to comm processor */ -extern unsigned long cpm_dpalloc(uint size, uint align); -extern int cpm_dpfree(unsigned long offset); -extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); -extern void cpm_dpdump(void); -extern void *cpm_dpram_addr(unsigned long offset); -extern uint cpm_dpram_phys(u8 *addr); -extern void cpm_setbrg(uint brg, uint rate); - -extern void cpm_load_patch(volatile immap_t *immr); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_UN ((ushort)0x0002) /* Underrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ -#define BD_SC_CL ((ushort)0x0001) /* Collision */ - -/* Parameter RAM offsets. -*/ -#define PROFF_SCC1 ((uint)0x0000) -#define PROFF_IIC ((uint)0x0080) -#define PROFF_SCC2 ((uint)0x0100) -#define PROFF_SPI ((uint)0x0180) -#define PROFF_SCC3 ((uint)0x0200) -#define PROFF_SMC1 ((uint)0x0280) -#define PROFF_SCC4 ((uint)0x0300) -#define PROFF_SMC2 ((uint)0x0380) - -/* Define enough so I can at least use the serial port as a UART. - * The MBX uses SMC1 as the host serial port. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - char res1[8]; /* Reserved */ - ushort smc_rpbase; /* Relocation pointer */ -} smc_uart_t; - -/* Function code bits. -*/ -#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* SMC uart mode register. -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC2 as Centronics parallel printer. It is half duplex, in that - * it can only receive or transmit. The parameter ram values for - * each direction are either unique or properly overlap, so we can - * include them in one structure. - */ -typedef struct smc_centronics { - ushort scent_rbase; - ushort scent_tbase; - u_char scent_cfcr; - u_char scent_smask; - ushort scent_mrblr; - uint scent_rstate; - uint scent_r_ptr; - ushort scent_rbptr; - ushort scent_r_cnt; - uint scent_rtemp; - uint scent_tstate; - uint scent_t_ptr; - ushort scent_tbptr; - ushort scent_t_cnt; - uint scent_ttemp; - ushort scent_max_sl; - ushort scent_sl_cnt; - ushort scent_character1; - ushort scent_character2; - ushort scent_character3; - ushort scent_character4; - ushort scent_character5; - ushort scent_character6; - ushort scent_character7; - ushort scent_character8; - ushort scent_rccm; - ushort scent_rccr; -} smc_cent_t; - -/* Centronics Status Mask Register. -*/ -#define SMC_CENT_F ((u_char)0x08) -#define SMC_CENT_PE ((u_char)0x04) -#define SMC_CENT_S ((u_char)0x02) - -/* SMC Event and Mask register. -*/ -#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ -#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ -#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SI Clock Route Register -*/ -#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) -#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) -#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) -#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) -#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) -#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* Function code bits. -*/ -#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* CPM Ethernet through SCCx. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PMSR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - char res1[8]; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PMSR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0002) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ - char res1[4]; /* Reserved */ - ushort iic_rpbase; /* Relocation pointer */ - char res2[2]; /* Reserved */ -} iic_t; - -#define BD_IIC_START ((ushort)0x0400) - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; - ushort spi_rpbase; /* Relocation pointer */ - ushort spi_res2; -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ -#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ -#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -/* SPIE fields */ -#define SPIE_MME 0x20 -#define SPIE_TXE 0x10 -#define SPIE_BSY 0x04 -#define SPIE_TXB 0x02 -#define SPIE_RXB 0x01 - -/* - * RISC Controller Configuration Register definitons - */ -#define RCCR_TIME 0x8000 /* RISC Timer Enable */ -#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ -#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ - -/* RISC Timer Parameter RAM offset */ -#define PROFF_RTMR ((uint)0x01B0) - -typedef struct risc_timer_pram { - unsigned short tm_base; /* RISC Timer Table Base Address */ - unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ - unsigned short r_tmr; /* RISC Timer Mode Register */ - unsigned short r_tmv; /* RISC Timer Valid Register */ - unsigned long tm_cmd; /* RISC Timer Command Register */ - unsigned long tm_cnt; /* RISC Timer Internal Count */ -} rt_pram_t; - -/* Bits in RISC Timer Command Register */ -#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ -#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ -#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ -#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ -#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ - -/* CPM interrupts. There are nearly 32 interrupts generated by CPM - * channels or devices. All of these are presented to the PPC core - * as a single interrupt. The CPM interrupt handler dispatches its - * own handlers, in a similar fashion to the PPC core handler. We - * use the table as defined in the manuals (i.e. no special high - * priority and SCC1 == SCCa, etc...). - */ -#define CPMVEC_NR 32 -#define CPMVEC_PIO_PC15 ((ushort)0x1f) -#define CPMVEC_SCC1 ((ushort)0x1e) -#define CPMVEC_SCC2 ((ushort)0x1d) -#define CPMVEC_SCC3 ((ushort)0x1c) -#define CPMVEC_SCC4 ((ushort)0x1b) -#define CPMVEC_PIO_PC14 ((ushort)0x1a) -#define CPMVEC_TIMER1 ((ushort)0x19) -#define CPMVEC_PIO_PC13 ((ushort)0x18) -#define CPMVEC_PIO_PC12 ((ushort)0x17) -#define CPMVEC_SDMA_CB_ERR ((ushort)0x16) -#define CPMVEC_IDMA1 ((ushort)0x15) -#define CPMVEC_IDMA2 ((ushort)0x14) -#define CPMVEC_TIMER2 ((ushort)0x12) -#define CPMVEC_RISCTIMER ((ushort)0x11) -#define CPMVEC_I2C ((ushort)0x10) -#define CPMVEC_PIO_PC11 ((ushort)0x0f) -#define CPMVEC_PIO_PC10 ((ushort)0x0e) -#define CPMVEC_TIMER3 ((ushort)0x0c) -#define CPMVEC_PIO_PC9 ((ushort)0x0b) -#define CPMVEC_PIO_PC8 ((ushort)0x0a) -#define CPMVEC_PIO_PC7 ((ushort)0x09) -#define CPMVEC_TIMER4 ((ushort)0x07) -#define CPMVEC_PIO_PC6 ((ushort)0x06) -#define CPMVEC_SPI ((ushort)0x05) -#define CPMVEC_SMC1 ((ushort)0x04) -#define CPMVEC_SMC2 ((ushort)0x03) -#define CPMVEC_PIO_PC5 ((ushort)0x02) -#define CPMVEC_PIO_PC4 ((ushort)0x01) -#define CPMVEC_ERROR ((ushort)0x00) - -/* CPM interrupt configuration vector. -*/ -#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ -#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ -#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ -#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ -#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ -#define CICR_IEN ((uint)0x00000080) /* Int. enable */ -#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ - -extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); -extern void cpm_free_handler(int vec); - -#endif /* __CPM1__ */ diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h deleted file mode 100644 index 4c538228e42f..000000000000 --- a/include/asm-ppc/cpm2.h +++ /dev/null @@ -1,1248 +0,0 @@ -/* - * Communication Processor Module v2. - * - * This file contains structures and information for the communication - * processor channels found in the dual port RAM or parameter RAM. - * All CPM control and status is available through the CPM2 internal - * memory map. See immap_cpm2.h for details. - */ -#ifdef __KERNEL__ -#ifndef __CPM2__ -#define __CPM2__ - -#include <asm/immap_cpm2.h> - -/* CPM Command register. -*/ -#define CPM_CR_RST ((uint)0x80000000) -#define CPM_CR_PAGE ((uint)0x7c000000) -#define CPM_CR_SBLOCK ((uint)0x03e00000) -#define CPM_CR_FLG ((uint)0x00010000) -#define CPM_CR_MCN ((uint)0x00003fc0) -#define CPM_CR_OPCODE ((uint)0x0000000f) - -/* Device sub-block and page codes. -*/ -#define CPM_CR_SCC1_SBLOCK (0x04) -#define CPM_CR_SCC2_SBLOCK (0x05) -#define CPM_CR_SCC3_SBLOCK (0x06) -#define CPM_CR_SCC4_SBLOCK (0x07) -#define CPM_CR_SMC1_SBLOCK (0x08) -#define CPM_CR_SMC2_SBLOCK (0x09) -#define CPM_CR_SPI_SBLOCK (0x0a) -#define CPM_CR_I2C_SBLOCK (0x0b) -#define CPM_CR_TIMER_SBLOCK (0x0f) -#define CPM_CR_RAND_SBLOCK (0x0e) -#define CPM_CR_FCC1_SBLOCK (0x10) -#define CPM_CR_FCC2_SBLOCK (0x11) -#define CPM_CR_FCC3_SBLOCK (0x12) -#define CPM_CR_IDMA1_SBLOCK (0x14) -#define CPM_CR_IDMA2_SBLOCK (0x15) -#define CPM_CR_IDMA3_SBLOCK (0x16) -#define CPM_CR_IDMA4_SBLOCK (0x17) -#define CPM_CR_MCC1_SBLOCK (0x1c) - -#define CPM_CR_FCC_SBLOCK(x) (x + 0x10) - -#define CPM_CR_SCC1_PAGE (0x00) -#define CPM_CR_SCC2_PAGE (0x01) -#define CPM_CR_SCC3_PAGE (0x02) -#define CPM_CR_SCC4_PAGE (0x03) -#define CPM_CR_SMC1_PAGE (0x07) -#define CPM_CR_SMC2_PAGE (0x08) -#define CPM_CR_SPI_PAGE (0x09) -#define CPM_CR_I2C_PAGE (0x0a) -#define CPM_CR_TIMER_PAGE (0x0a) -#define CPM_CR_RAND_PAGE (0x0a) -#define CPM_CR_FCC1_PAGE (0x04) -#define CPM_CR_FCC2_PAGE (0x05) -#define CPM_CR_FCC3_PAGE (0x06) -#define CPM_CR_IDMA1_PAGE (0x07) -#define CPM_CR_IDMA2_PAGE (0x08) -#define CPM_CR_IDMA3_PAGE (0x09) -#define CPM_CR_IDMA4_PAGE (0x0a) -#define CPM_CR_MCC1_PAGE (0x07) -#define CPM_CR_MCC2_PAGE (0x08) - -#define CPM_CR_FCC_PAGE(x) (x + 0x04) - -/* Some opcodes (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) -#define CPM_CR_START_IDMA ((ushort)0x0009) -#define CPM_CR_STOP_IDMA ((ushort)0x000b) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - -/* Dual Port RAM addresses. The first 16K is available for almost - * any CPM use, so we put the BDs there. The first 128 bytes are - * used for SMC1 and SMC2 parameter RAM, so we start allocating - * BDs above that. All of this must change when we start - * downloading RAM microcode. - */ -#define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) -#if defined(CONFIG_8272) -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) -#else -#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) -#endif - -/* The number of pages of host memory we allocate for CPM. This is - * done early in kernel initialization to get physically contiguous - * pages. - */ -#define NUM_CPM_HOST_PAGES 2 - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ - -extern unsigned long cpm_dpalloc(uint size, uint align); -extern int cpm_dpfree(unsigned long offset); -extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); -extern void cpm_dpdump(void); -extern void *cpm_dpram_addr(unsigned long offset); -extern void cpm_setbrg(uint brg, uint rate); -extern void cpm2_fastbrg(uint brg, uint rate, int div16); -extern void cpm2_reset(void); - - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - -/* Function code bits, usually generic to devices. -*/ -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ - -/* Parameter RAM offsets from the base. -*/ -#define PROFF_SCC1 ((uint)0x8000) -#define PROFF_SCC2 ((uint)0x8100) -#define PROFF_SCC3 ((uint)0x8200) -#define PROFF_SCC4 ((uint)0x8300) -#define PROFF_FCC1 ((uint)0x8400) -#define PROFF_FCC2 ((uint)0x8500) -#define PROFF_FCC3 ((uint)0x8600) -#define PROFF_MCC1 ((uint)0x8700) -#define PROFF_SMC1_BASE ((uint)0x87fc) -#define PROFF_IDMA1_BASE ((uint)0x87fe) -#define PROFF_MCC2 ((uint)0x8800) -#define PROFF_SMC2_BASE ((uint)0x88fc) -#define PROFF_IDMA2_BASE ((uint)0x88fe) -#define PROFF_SPI_BASE ((uint)0x89fc) -#define PROFF_IDMA3_BASE ((uint)0x89fe) -#define PROFF_TIMERS ((uint)0x8ae0) -#define PROFF_REVNUM ((uint)0x8af0) -#define PROFF_RAND ((uint)0x8af8) -#define PROFF_I2C_BASE ((uint)0x8afc) -#define PROFF_IDMA4_BASE ((uint)0x8afe) - -#define PROFF_SCC_SIZE ((uint)0x100) -#define PROFF_FCC_SIZE ((uint)0x100) -#define PROFF_SMC_SIZE ((uint)64) - -/* The SMCs are relocated to any of the first eight DPRAM pages. - * We will fix these at the first locations of DPRAM, until we - * get some microcode patches :-). - * The parameter ram space for the SMCs is fifty-some bytes, and - * they are required to start on a 64 byte boundary. - */ -#define PROFF_SMC1 (0) -#define PROFF_SMC2 (64) - - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - uint smc_stmp; /* SDMA Temp */ -} smc_uart_t; - -/* SMC uart mode register (Internal memory map). -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC Event and Mask register. -*/ -#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ -#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ -#define SMCM_TXE ((unsigned char)0x10) -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0002) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* How about some FCCs..... -*/ -#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) -#define FCC_GFMR_DIAG_LE ((uint)0x40000000) -#define FCC_GFMR_DIAG_AE ((uint)0x80000000) -#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) -#define FCC_GFMR_TCI ((uint)0x20000000) -#define FCC_GFMR_TRX ((uint)0x10000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_CDP ((uint)0x04000000) -#define FCC_GFMR_CTSP ((uint)0x02000000) -#define FCC_GFMR_CDS ((uint)0x01000000) -#define FCC_GFMR_CTSS ((uint)0x00800000) -#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) -#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) -#define FCC_GFMR_SYNL_8 ((uint)0x00008000) -#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) -#define FCC_GFMR_RTSM ((uint)0x00002000) -#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) -#define FCC_GFMR_REVD ((uint)0x00000400) -#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) -#define FCC_GFMR_TCRC_16 ((uint)0x00000000) -#define FCC_GFMR_TCRC_32 ((uint)0x00000080) -#define FCC_GFMR_ENR ((uint)0x00000020) -#define FCC_GFMR_ENT ((uint)0x00000010) -#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) -#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) -#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) - -/* Generic FCC parameter ram. -*/ -typedef struct fcc_param { - ushort fcc_riptr; /* Rx Internal temp pointer */ - ushort fcc_tiptr; /* Tx Internal temp pointer */ - ushort fcc_res1; - ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ - uint fcc_rstate; /* Upper byte is Func code, must be set */ - uint fcc_rbase; /* Receive BD base */ - ushort fcc_rbdstat; /* RxBD status */ - ushort fcc_rbdlen; /* RxBD down counter */ - uint fcc_rdptr; /* RxBD internal data pointer */ - uint fcc_tstate; /* Upper byte is Func code, must be set */ - uint fcc_tbase; /* Transmit BD base */ - ushort fcc_tbdstat; /* TxBD status */ - ushort fcc_tbdlen; /* TxBD down counter */ - uint fcc_tdptr; /* TxBD internal data pointer */ - uint fcc_rbptr; /* Rx BD Internal buf pointer */ - uint fcc_tbptr; /* Tx BD Internal buf pointer */ - uint fcc_rcrc; /* Rx temp CRC */ - uint fcc_res2; - uint fcc_tcrc; /* Tx temp CRC */ -} fccp_t; - - -/* Ethernet controller through FCC. -*/ -typedef struct fcc_enet { - fccp_t fen_genfcc; - uint fen_statbuf; /* Internal status buffer */ - uint fen_camptr; /* CAM address */ - uint fen_cmask; /* Constant mask for CRC */ - uint fen_cpres; /* Preset CRC */ - uint fen_crcec; /* CRC Error counter */ - uint fen_alec; /* alignment error counter */ - uint fen_disfc; /* discard frame counter */ - ushort fen_retlim; /* Retry limit */ - ushort fen_retcnt; /* Retry counter */ - ushort fen_pper; /* Persistence */ - ushort fen_boffcnt; /* backoff counter */ - uint fen_gaddrh; /* Group address filter, high 32-bits */ - uint fen_gaddrl; /* Group address filter, low 32-bits */ - ushort fen_tfcstat; /* out of sequence TxBD */ - ushort fen_tfclen; - uint fen_tfcptr; - ushort fen_mflr; /* Maximum frame length (1518) */ - ushort fen_paddrh; /* MAC address */ - ushort fen_paddrm; - ushort fen_paddrl; - ushort fen_ibdcount; /* Internal BD counter */ - ushort fen_ibdstart; /* Internal BD start pointer */ - ushort fen_ibdend; /* Internal BD end pointer */ - ushort fen_txlen; /* Internal Tx frame length counter */ - uint fen_ibdbase[8]; /* Internal use */ - uint fen_iaddrh; /* Individual address filter */ - uint fen_iaddrl; - ushort fen_minflr; /* Minimum frame length (64) */ - ushort fen_taddrh; /* Filter transfer MAC address */ - ushort fen_taddrm; - ushort fen_taddrl; - ushort fen_padptr; /* Pointer to pad byte buffer */ - ushort fen_cftype; /* control frame type */ - ushort fen_cfrange; /* control frame range */ - ushort fen_maxb; /* maximum BD count */ - ushort fen_maxd1; /* Max DMA1 length (1520) */ - ushort fen_maxd2; /* Max DMA2 length (1520) */ - ushort fen_maxd; /* internal max DMA count */ - ushort fen_dmacnt; /* internal DMA counter */ - uint fen_octc; /* Total octect counter */ - uint fen_colc; /* Total collision counter */ - uint fen_broc; /* Total broadcast packet counter */ - uint fen_mulc; /* Total multicast packet count */ - uint fen_uspc; /* Total packets < 64 bytes */ - uint fen_frgc; /* Total packets < 64 bytes with errors */ - uint fen_ospc; /* Total packets > 1518 */ - uint fen_jbrc; /* Total packets > 1518 with errors */ - uint fen_p64c; /* Total packets == 64 bytes */ - uint fen_p65c; /* Total packets 64 < bytes <= 127 */ - uint fen_p128c; /* Total packets 127 < bytes <= 255 */ - uint fen_p256c; /* Total packets 256 < bytes <= 511 */ - uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ - uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ - uint fen_cambuf; /* Internal CAM buffer poiner */ - ushort fen_rfthr; /* Received frames threshold */ - ushort fen_rfcnt; /* Received frames count */ -} fcc_enet_t; - -/* FCC Event/Mask register as used by Ethernet. -*/ -#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ -#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ -#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ -#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* FCC Mode Register (FPSMR) as used by Ethernet. -*/ -#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ -#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ -#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ -#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ -#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ -#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ -#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ -#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ -#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ -#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ -#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ -#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ -#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; /* Tx temp. */ - uint spi_res1[4]; /* SDMA temp. */ -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -#define SPI_EB ((u_char)0x10) /* big endian byte order */ - -#define BD_IIC_START ((ushort)0x0400) - -/* IDMA parameter RAM -*/ -typedef struct idma { - ushort ibase; /* IDMA buffer descriptor table base address */ - ushort dcm; /* DMA channel mode */ - ushort ibdptr; /* IDMA current buffer descriptor pointer */ - ushort dpr_buf; /* IDMA transfer buffer base address */ - ushort buf_inv; /* internal buffer inventory */ - ushort ss_max; /* steady-state maximum transfer size */ - ushort dpr_in_ptr; /* write pointer inside the internal buffer */ - ushort sts; /* source transfer size */ - ushort dpr_out_ptr; /* read pointer inside the internal buffer */ - ushort seob; /* source end of burst */ - ushort deob; /* destination end of burst */ - ushort dts; /* destination transfer size */ - ushort ret_add; /* return address when working in ERM=1 mode */ - ushort res0; /* reserved */ - uint bd_cnt; /* internal byte count */ - uint s_ptr; /* source internal data pointer */ - uint d_ptr; /* destination internal data pointer */ - uint istate; /* internal state */ - u_char res1[20]; /* pad to 64-byte length */ -} idma_t; - -/* DMA channel mode bit fields -*/ -#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ -#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ -#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ -#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ -#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ -#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ -#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ -#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ -#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ -#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ -#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ -#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ -#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ -#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ - -/* IDMA Buffer Descriptors -*/ -typedef struct idma_bd { - uint flags; - uint len; /* data length */ - uint src; /* source data buffer pointer */ - uint dst; /* destination data buffer pointer */ -} idma_bd_t; - -/* IDMA buffer descriptor flag bit fields -*/ -#define IDMA_BD_V ((uint)0x80000000) /* valid */ -#define IDMA_BD_W ((uint)0x20000000) /* wrap */ -#define IDMA_BD_I ((uint)0x10000000) /* interrupt */ -#define IDMA_BD_L ((uint)0x08000000) /* last */ -#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ -#define IDMA_BD_SDN ((uint)0x00400000) /* source done */ -#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ -#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ -#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ -#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ -#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ -#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ -#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ -#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ -#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ - -/* per-channel IDMA registers -*/ -typedef struct im_idma { - u_char idsr; /* IDMAn event status register */ - u_char res0[3]; - u_char idmr; /* IDMAn event mask register */ - u_char res1[3]; -} im_idma_t; - -/* IDMA event register bit fields -*/ -#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ -#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ -#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ -#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ - -/* RISC Controller Configuration Register (RCCR) bit fields -*/ -#define RCCR_TIME ((uint)0x80000000) /* timer enable */ -#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ -#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ -#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ -#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ -#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ -#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ -#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ -#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ -#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ -#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ -#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ -#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ -#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ -#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ -#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ -#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ -#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ -#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ -#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ -#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ -#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ -#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ -#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ -#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ -#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ -#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ -#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ -#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ -#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ -#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ -#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ -#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ -#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ -#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ -#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ -#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ -#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ - -/*----------------------------------------------------------------------- - * CMXFCR - CMX FCC Clock Route Register - */ -#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ -#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ -#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ -#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ -#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ -#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ -#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ -#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ -#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ - -#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ -#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ -#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ -#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ -#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ -#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ -#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ -#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ - -#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ -#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ -#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ -#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ -#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ -#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ -#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ -#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ - -#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ -#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ -#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ -#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ -#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ -#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ -#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ -#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ - -#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ -#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ -#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ -#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ -#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ -#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ -#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ -#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ - -#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ -#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ -#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ -#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ -#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ -#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ -#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ -#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ - -#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ -#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ -#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ -#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ -#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ -#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ -#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ -#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ - -/*----------------------------------------------------------------------- - * CMXSCR - CMX SCC Clock Route Register - */ -#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ -#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ -#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ -#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ -#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ -#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ -#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ -#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ -#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ -#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ -#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ -#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ -#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ -#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ -#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ -#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ - -#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ -#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ -#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ -#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ -#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ -#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ -#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ -#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ -#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ -#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ -#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ -#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ -#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ -#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ -#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ -#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ -#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ -#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ -#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ -#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ -#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ -#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ -#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ -#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ -#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ -#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ -#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ -#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ -#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ -#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ -#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ -#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ -#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ -#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ -#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ -#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ -#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ -#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ -#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ -#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ -#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ -#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ -#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ - -#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ -#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ -#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ -#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ -#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ -#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ -#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ -#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ -#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ -#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ -#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ -#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ -#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ -#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ -#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration Register 4-31 - */ -#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ -#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ -#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ -#define SIUMCR_CDIS 0x10000000 /* Core Disable */ -#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ -#define SIUMCR_DPPC01 0x04000000 /* - " - */ -#define SIUMCR_DPPC10 0x08000000 /* - " - */ -#define SIUMCR_DPPC11 0x0c000000 /* - " - */ -#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ -#define SIUMCR_L2CPC01 0x01000000 /* - " - */ -#define SIUMCR_L2CPC10 0x02000000 /* - " - */ -#define SIUMCR_L2CPC11 0x03000000 /* - " - */ -#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ -#define SIUMCR_LBPC01 0x00400000 /* - " - */ -#define SIUMCR_LBPC10 0x00800000 /* - " - */ -#define SIUMCR_LBPC11 0x00c00000 /* - " - */ -#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ -#define SIUMCR_APPC01 0x00100000 /* - " - */ -#define SIUMCR_APPC10 0x00200000 /* - " - */ -#define SIUMCR_APPC11 0x00300000 /* - " - */ -#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ -#define SIUMCR_CS10PC01 0x00040000 /* - " - */ -#define SIUMCR_CS10PC10 0x00080000 /* - " - */ -#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ -#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ -#define SIUMCR_BCTLC01 0x00010000 /* - " - */ -#define SIUMCR_BCTLC10 0x00020000 /* - " - */ -#define SIUMCR_BCTLC11 0x00030000 /* - " - */ -#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ -#define SIUMCR_MMR01 0x00004000 /* - " - */ -#define SIUMCR_MMR10 0x00008000 /* - " - */ -#define SIUMCR_MMR11 0x0000c000 /* - " - */ -#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control Register 9-8 -*/ -#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ -#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ -#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ -#define SCCR_PCIDF_SHIFT 3 - -#ifndef CPM_IMMR_OFFSET -#define CPM_IMMR_OFFSET 0x101a8 -#endif - -#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ - -/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK - * in order to use clock-computing stuff below for the FCC x - */ - -/* Automatically generates register configurations */ -#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ - -#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ -#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ -#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ -#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ -#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ -#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ - -#define PC_F1RXCLK PC_CLK(F1_RXCLK) -#define PC_F1TXCLK PC_CLK(F1_TXCLK) -#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) -#define CMX1_CLK_MASK ((uint)0xff000000) - -#define PC_F2RXCLK PC_CLK(F2_RXCLK) -#define PC_F2TXCLK PC_CLK(F2_TXCLK) -#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) -#define CMX2_CLK_MASK ((uint)0x00ff0000) - -#define PC_F3RXCLK PC_CLK(F3_RXCLK) -#define PC_F3TXCLK PC_CLK(F3_TXCLK) -#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) -#define CMX3_CLK_MASK ((uint)0x0000ff00) - -#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK) -#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE) - -#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK) - -/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PA1_COL 0x00000001U -#define PA1_CRS 0x00000002U -#define PA1_TXER 0x00000004U -#define PA1_TXEN 0x00000008U -#define PA1_RXDV 0x00000010U -#define PA1_RXER 0x00000020U -#define PA1_TXDAT 0x00003c00U -#define PA1_RXDAT 0x0003c000U -#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) -#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ - PA1_RXDV | PA1_RXER) -#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) -#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) - - -/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PB2_TXER 0x00000001U -#define PB2_RXDV 0x00000002U -#define PB2_TXEN 0x00000004U -#define PB2_RXER 0x00000008U -#define PB2_COL 0x00000010U -#define PB2_CRS 0x00000020U -#define PB2_TXDAT 0x000003c0U -#define PB2_RXDAT 0x00003c00U -#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ - PB2_RXER | PB2_RXDV | PB2_TXER) -#define PB2_PSORB1 (PB2_TXEN) -#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) -#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) - - -/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, - * but there is little variation among the choices. - */ -#define PB3_RXDV 0x00004000U -#define PB3_RXER 0x00008000U -#define PB3_TXER 0x00010000U -#define PB3_TXEN 0x00020000U -#define PB3_COL 0x00040000U -#define PB3_CRS 0x00080000U -#define PB3_TXDAT 0x0f000000U -#define PC3_TXDAT 0x00000010U -#define PB3_RXDAT 0x00f00000U -#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ - PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) -#define PB3_PSORB1 0 -#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) -#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) -#define PC3_DIRC1 (PC3_TXDAT) - -/* Handy macro to specify mem for FCCs*/ -#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) -#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) -#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) -#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2) - -/* Clocks and GRG's */ - -enum cpm_clk_dir { - CPM_CLK_RX, - CPM_CLK_TX, - CPM_CLK_RTX -}; - -enum cpm_clk_target { - CPM_CLK_SCC1, - CPM_CLK_SCC2, - CPM_CLK_SCC3, - CPM_CLK_SCC4, - CPM_CLK_FCC1, - CPM_CLK_FCC2, - CPM_CLK_FCC3 -}; - -enum cpm_clk { - CPM_CLK_NONE = 0, - CPM_BRG1, /* Baud Rate Generator 1 */ - CPM_BRG2, /* Baud Rate Generator 2 */ - CPM_BRG3, /* Baud Rate Generator 3 */ - CPM_BRG4, /* Baud Rate Generator 4 */ - CPM_BRG5, /* Baud Rate Generator 5 */ - CPM_BRG6, /* Baud Rate Generator 6 */ - CPM_BRG7, /* Baud Rate Generator 7 */ - CPM_BRG8, /* Baud Rate Generator 8 */ - CPM_CLK1, /* Clock 1 */ - CPM_CLK2, /* Clock 2 */ - CPM_CLK3, /* Clock 3 */ - CPM_CLK4, /* Clock 4 */ - CPM_CLK5, /* Clock 5 */ - CPM_CLK6, /* Clock 6 */ - CPM_CLK7, /* Clock 7 */ - CPM_CLK8, /* Clock 8 */ - CPM_CLK9, /* Clock 9 */ - CPM_CLK10, /* Clock 10 */ - CPM_CLK11, /* Clock 11 */ - CPM_CLK12, /* Clock 12 */ - CPM_CLK13, /* Clock 13 */ - CPM_CLK14, /* Clock 14 */ - CPM_CLK15, /* Clock 15 */ - CPM_CLK16, /* Clock 16 */ - CPM_CLK17, /* Clock 17 */ - CPM_CLK18, /* Clock 18 */ - CPM_CLK19, /* Clock 19 */ - CPM_CLK20, /* Clock 20 */ - CPM_CLK_DUMMY -}; - -extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode); - -#endif /* __CPM2__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/delay.h b/include/asm-ppc/delay.h deleted file mode 100644 index badde6845af2..000000000000 --- a/include/asm-ppc/delay.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_DELAY_H -#define _PPC_DELAY_H - -#include <asm/param.h> - -/* - * Copyright 1996, Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -extern unsigned long loops_per_jiffy; - -extern void __delay(unsigned int loops); - -/* - * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so - * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32. - * - * The mulhwu instruction gives us loops = (a * b) / 2^32. - * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226 - * because this lets us support a wide range of HZ and - * loops_per_jiffy values without either a or b overflowing 2^32. - * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and - * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280 - * (which corresponds to ~3800 bogomips at HZ = 100). - * -- paulus - */ -#define __MAX_UDELAY (226050910UL/HZ) /* maximum udelay argument */ -#define __MAX_NDELAY (4294967295UL/HZ) /* maximum ndelay argument */ - -extern __inline__ void __udelay(unsigned int x) -{ - unsigned int loops; - - __asm__("mulhwu %0,%1,%2" : "=r" (loops) : - "r" (x), "r" (loops_per_jiffy * 226)); - __delay(loops); -} - -extern __inline__ void __ndelay(unsigned int x) -{ - unsigned int loops; - - __asm__("mulhwu %0,%1,%2" : "=r" (loops) : - "r" (x), "r" (loops_per_jiffy * 5)); - __delay(loops); -} - -extern void __bad_udelay(void); /* deliberately undefined */ -extern void __bad_ndelay(void); /* deliberately undefined */ - -#define udelay(n) (__builtin_constant_p(n)? \ - ((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n) * (19 * HZ))) : \ - __udelay((n) * (19 * HZ))) - -#define ndelay(n) (__builtin_constant_p(n)? \ - ((n) > __MAX_NDELAY? __bad_ndelay(): __ndelay((n) * HZ)) : \ - __ndelay((n) * HZ)) - -#endif /* defined(_PPC_DELAY_H) */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/device.h b/include/asm-ppc/device.h deleted file mode 100644 index d8f9872b0e2d..000000000000 --- a/include/asm-ppc/device.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Arch specific extensions to struct device - * - * This file is released under the GPLv2 - */ -#include <asm-generic/device.h> - diff --git a/include/asm-ppc/floppy.h b/include/asm-ppc/floppy.h deleted file mode 100644 index 7d9b3f430d92..000000000000 --- a/include/asm-ppc/floppy.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Architecture specific parts of the Floppy driver - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 - */ -#ifdef __KERNEL__ -#ifndef __ASM_PPC_FLOPPY_H -#define __ASM_PPC_FLOPPY_H - -#define fd_inb(port) inb_p(port) -#define fd_outb(value,port) outb_p(value,port) - -#define fd_disable_dma() fd_ops->_disable_dma(FLOPPY_DMA) -#define fd_free_dma() fd_ops->_free_dma(FLOPPY_DMA) -#define fd_get_dma_residue() fd_ops->_get_dma_residue(FLOPPY_DMA) -#define fd_dma_setup(addr, size, mode, io) fd_ops->_dma_setup(addr, size, mode, io) -#define fd_enable_irq() enable_irq(FLOPPY_IRQ) -#define fd_disable_irq() disable_irq(FLOPPY_IRQ) -#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); - -static int fd_request_dma(void); - -struct fd_dma_ops { - void (*_disable_dma)(unsigned int dmanr); - void (*_free_dma)(unsigned int dmanr); - int (*_get_dma_residue)(unsigned int dummy); - int (*_dma_setup)(char *addr, unsigned long size, int mode, int io); -}; - -static int virtual_dma_count; -static int virtual_dma_residue; -static char *virtual_dma_addr; -static int virtual_dma_mode; -static int doing_vdma; -static struct fd_dma_ops *fd_ops; - -static irqreturn_t floppy_hardint(int irq, void *dev_id) -{ - unsigned char st; - int lcount; - char *lptr; - - if (!doing_vdma) - return floppy_interrupt(irq, dev_id); - - - st = 1; - for (lcount=virtual_dma_count, lptr=virtual_dma_addr; - lcount; lcount--, lptr++) { - st=inb(virtual_dma_port+4) & 0xa0 ; - if (st != 0xa0) - break; - if (virtual_dma_mode) - outb_p(*lptr, virtual_dma_port+5); - else - *lptr = inb_p(virtual_dma_port+5); - } - virtual_dma_count = lcount; - virtual_dma_addr = lptr; - st = inb(virtual_dma_port+4); - - if (st == 0x20) - return IRQ_HANDLED; - if (!(st & 0x20)) { - virtual_dma_residue += virtual_dma_count; - virtual_dma_count=0; - doing_vdma = 0; - floppy_interrupt(irq, dev_id); - return IRQ_HANDLED; - } - return IRQ_HANDLED; -} - -static void vdma_disable_dma(unsigned int dummy) -{ - doing_vdma = 0; - virtual_dma_residue += virtual_dma_count; - virtual_dma_count=0; -} - -static void vdma_nop(unsigned int dummy) -{ -} - - -static int vdma_get_dma_residue(unsigned int dummy) -{ - return virtual_dma_count + virtual_dma_residue; -} - - -static int fd_request_irq(void) -{ - if (can_use_virtual_dma) - return request_irq(FLOPPY_IRQ, floppy_hardint, - IRQF_DISABLED, "floppy", NULL); - else - return request_irq(FLOPPY_IRQ, floppy_interrupt, - IRQF_DISABLED, "floppy", NULL); -} - -static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io) -{ - doing_vdma = 1; - virtual_dma_port = io; - virtual_dma_mode = (mode == DMA_MODE_WRITE); - virtual_dma_addr = addr; - virtual_dma_count = size; - virtual_dma_residue = 0; - return 0; -} - -static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) -{ - /* actual, physical DMA */ - doing_vdma = 0; - clear_dma_ff(FLOPPY_DMA); - set_dma_mode(FLOPPY_DMA,mode); - set_dma_addr(FLOPPY_DMA,(unsigned int)virt_to_bus(addr)); - set_dma_count(FLOPPY_DMA,size); - enable_dma(FLOPPY_DMA); - return 0; -} - -static struct fd_dma_ops real_dma_ops = -{ - ._disable_dma = disable_dma, - ._free_dma = free_dma, - ._get_dma_residue = get_dma_residue, - ._dma_setup = hard_dma_setup -}; - -static struct fd_dma_ops virt_dma_ops = -{ - ._disable_dma = vdma_disable_dma, - ._free_dma = vdma_nop, - ._get_dma_residue = vdma_get_dma_residue, - ._dma_setup = vdma_dma_setup -}; - -static int fd_request_dma() -{ - if (can_use_virtual_dma & 1) { - fd_ops = &virt_dma_ops; - return 0; - } - else { - fd_ops = &real_dma_ops; - return request_dma(FLOPPY_DMA, "floppy"); - } -} - -static int FDC1 = 0x3f0; -static int FDC2 = -1; - -/* - * Again, the CMOS information not available - */ -#define FLOPPY0_TYPE 6 -#define FLOPPY1_TYPE 0 - -#define N_FDC 2 /* Don't change this! */ -#define N_DRIVE 8 - -/* - * The PowerPC has no problems with floppy DMA crossing 64k borders. - */ -#define CROSS_64KB(a,s) (0) - -#endif /* __ASM_PPC_FLOPPY_H */ - -#define EXTRA_FLOPPY_PARAMS - -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/fs_pd.h b/include/asm-ppc/fs_pd.h deleted file mode 100644 index 8691327653af..000000000000 --- a/include/asm-ppc/fs_pd.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Platform information definitions. - * - * 2006 (c) MontaVista Software, Inc. - * Vitaly Bordug <vbordug@ru.mvista.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef FS_PD_H -#define FS_PD_H - -static inline int uart_baudrate(void) -{ - int baud; - bd_t *bd = (bd_t *) __res; - - if (bd->bi_baudrate) - baud = bd->bi_baudrate; - else - baud = -1; - return baud; -} - -static inline int uart_clock(void) -{ - return (((bd_t *) __res)->bi_intfreq); -} - -#define cpm2_map(member) (&cpm2_immr->member) -#define cpm2_map_size(member, size) (&cpm2_immr->member) -#define cpm2_unmap(addr) do {} while(0) - -#endif diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h deleted file mode 100644 index 341ae55b99fb..000000000000 --- a/include/asm-ppc/gg2.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions - * - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is based on the following documentation: - * - * The VAS96011/12 Chipset, Data Book, Edition 1.0 - * VLSI Technology, Inc. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _ASMPPC_GG2_H -#define _ASMPPC_GG2_H - - /* - * Memory Map (CHRP mode) - */ - -#define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ -#define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ -#define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ -#define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ -#define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ - /* special PCI cycles */ -#define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ -#define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ - - - /* - * GG2 specific PCI Registers - */ - -extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ - -#define GG2_PCI_BUSNO 0x40 /* Bus number */ -#define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ -#define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ -#define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ -#define GG2_PCI_ADDR_MAP 0x5c /* Address map */ -#define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ -#define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ -#define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ -#define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ -#define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ -#define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ -#define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ -#define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ -#define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ -#define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ -#define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ -#define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ -#define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ -#define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ -#define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ - /* Cleared when read */ - -#endif /* _ASMPPC_GG2_H */ diff --git a/include/asm-ppc/gt64260.h b/include/asm-ppc/gt64260.h deleted file mode 100644 index 9e63b3cfffca..000000000000 --- a/include/asm-ppc/gt64260.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - * include/asm-ppc/gt64260.h - * - * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines. - * - * Author: Mark A. Greer <mgreer@mvista.com> - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASMPPC_GT64260_H -#define __ASMPPC_GT64260_H - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/slab.h> - -#include <asm/byteorder.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/uaccess.h> -#include <asm/machdep.h> -#include <asm/pci-bridge.h> -#include <asm/gt64260_defs.h> - - -extern u32 gt64260_base; -extern u32 gt64260_irq_base; /* We handle the next 96 IRQs from here */ -extern u32 gt64260_revision; -extern u8 gt64260_pci_exclude_bridge; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/* IRQs defined by the 64260 */ -#define GT64260_IRQ_MPSC0 40 -#define GT64260_IRQ_MPSC1 42 -#define GT64260_IRQ_SDMA 36 - -/* - * Define a default physical memory map to be set up on the bridge. - * Also define a struct to pass that info from board-specific routines to - * GT64260 generic set up routines. By passing this info in, the board - * support developer can modify it at will. - */ - -/* - * This is the default memory map: - * CPU PCI - * --- --- - * PCI 0 I/O: 0xfa000000-0xfaffffff 0x00000000-0x00ffffff - * PCI 1 I/O: 0xfb000000-0xfbffffff 0x01000000-0x01ffffff - * PCI 0 MEM: 0x80000000-0x8fffffff 0x80000000-0x8fffffff - * PCI 1 MEM: 0x90000000-0x9fffffff 0x90000000-0x9fffffff - */ - -/* Default physical memory map for the GT64260 bridge */ - -/* - * PCI Bus 0 Definitions - */ -#define GT64260_PCI_0_IO_SIZE 0x01000000U -#define GT64260_PCI_0_MEM_SIZE 0x10000000U - -/* Processor Physical addresses */ -#define GT64260_PCI_0_IO_START_PROC 0xfa000000U -#define GT64260_PCI_0_IO_END_PROC (GT64260_PCI_0_IO_START_PROC + \ - GT64260_PCI_0_IO_SIZE - 1) - -/* PCI 0 addresses */ -#define GT64260_PCI_0_IO_START 0x00000000U -#define GT64260_PCI_0_IO_END (GT64260_PCI_0_IO_START + \ - GT64260_PCI_0_IO_SIZE - 1) - -/* Processor Physical addresses */ -#define GT64260_PCI_0_MEM_START_PROC 0x80000000U -#define GT64260_PCI_0_MEM_END_PROC (GT64260_PCI_0_MEM_START_PROC + \ - GT64260_PCI_0_MEM_SIZE - 1) - -/* PCI 0 addresses */ -#define GT64260_PCI_0_MEM_START 0x80000000U -#define GT64260_PCI_0_MEM_END (GT64260_PCI_0_MEM_START + \ - GT64260_PCI_0_MEM_SIZE - 1) - -/* - * PCI Bus 1 Definitions - */ -#define GT64260_PCI_1_IO_SIZE 0x01000000U -#define GT64260_PCI_1_MEM_SIZE 0x10000000U - -/* PCI 1 addresses */ -#define GT64260_PCI_1_IO_START 0x01000000U -#define GT64260_PCI_1_IO_END (GT64260_PCI_1_IO_START + \ - GT64260_PCI_1_IO_SIZE - 1) - -/* Processor Physical addresses */ -#define GT64260_PCI_1_IO_START_PROC 0xfb000000U -#define GT64260_PCI_1_IO_END_PROC (GT64260_PCI_1_IO_START_PROC + \ - GT64260_PCI_1_IO_SIZE - 1) - -/* PCI 1 addresses */ -#define GT64260_PCI_1_MEM_START 0x90000000U -#define GT64260_PCI_1_MEM_END (GT64260_PCI_1_MEM_START + \ - GT64260_PCI_1_MEM_SIZE - 1) - -/* Processor Physical addresses */ -#define GT64260_PCI_1_MEM_START_PROC 0x90000000U -#define GT64260_PCI_1_MEM_END_PROC (GT64260_PCI_1_MEM_START_PROC + \ - GT64260_PCI_1_MEM_SIZE - 1) - -/* Define struct to pass mem-map info into gt64260_common.c code */ -typedef struct { - struct pci_controller *hose_a; - struct pci_controller *hose_b; - - u32 mem_size; - - u32 pci_0_io_start_proc; - u32 pci_0_io_start_pci; - u32 pci_0_io_size; - u32 pci_0_io_swap; - - u32 pci_0_mem_start_proc; - u32 pci_0_mem_start_pci_hi; - u32 pci_0_mem_start_pci_lo; - u32 pci_0_mem_size; - u32 pci_0_mem_swap; - - u32 pci_1_io_start_proc; - u32 pci_1_io_start_pci; - u32 pci_1_io_size; - u32 pci_1_io_swap; - - u32 pci_1_mem_start_proc; - u32 pci_1_mem_start_pci_hi; - u32 pci_1_mem_start_pci_lo; - u32 pci_1_mem_size; - u32 pci_1_mem_swap; -} gt64260_bridge_info_t; - -#define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) { \ - (ip)->mem_size = (ms); \ - \ - (ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC; \ - (ip)->pci_0_io_start_pci = GT64260_PCI_0_IO_START; \ - (ip)->pci_0_io_size = GT64260_PCI_0_IO_SIZE; \ - (ip)->pci_0_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ - \ - (ip)->pci_0_mem_start_proc = GT64260_PCI_0_MEM_START_PROC; \ - (ip)->pci_0_mem_start_pci_hi = 0x00000000; \ - (ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START; \ - (ip)->pci_0_mem_size = GT64260_PCI_0_MEM_SIZE; \ - (ip)->pci_0_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ - \ - (ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC; \ - (ip)->pci_1_io_start_pci = GT64260_PCI_1_IO_START; \ - (ip)->pci_1_io_size = GT64260_PCI_1_IO_SIZE; \ - (ip)->pci_1_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ - \ - (ip)->pci_1_mem_start_proc = GT64260_PCI_1_MEM_START_PROC; \ - (ip)->pci_1_mem_start_pci_hi = 0x00000000; \ - (ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START; \ - (ip)->pci_1_mem_size = GT64260_PCI_1_MEM_SIZE; \ - (ip)->pci_1_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ -} - -/* - ***************************************************************************** - * - * I/O macros to access the 64260's registers - * - ***************************************************************************** - */ - -extern inline uint32_t gt_read(uint32_t offs){ - return (in_le32((volatile uint *)(gt64260_base + offs))); -} -extern inline void gt_write(uint32_t offs, uint32_t d){ - out_le32((volatile uint *)(gt64260_base + offs), d); -} - -#if 0 /* paranoid SMP version */ -extern inline void gt_modify(u32 offs, u32 data, u32 mask) \ -{ - uint32_t reg; - spin_lock(>64260_lock); - reg = gt_read(offs) & (~mask); /* zero any bits we care about*/ - reg |= data & mask; /* set bits from the data */ - gt_write(offs, reg); - spin_unlock(>64260_lock); -} -#else -extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask) -{ - uint32_t reg; - reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/ - reg |= (data) & (mask); /* set bits from the data */ - gt_write(offs, reg); -} -#endif -#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits) - -#define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits) - - -/* - ***************************************************************************** - * - * Function Prototypes - * - ***************************************************************************** - */ - -int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info, - int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char))); -int gt64260_bridge_init(gt64260_bridge_info_t *info); -int gt64260_cpu_scs_set_window(u32 window, - u32 base_addr, - u32 size); -int gt64260_cpu_cs_set_window(u32 window, - u32 base_addr, - u32 size); -int gt64260_cpu_boot_set_window(u32 base_addr, - u32 size); -int gt64260_cpu_set_pci_io_window(u32 pci_bus, - u32 cpu_base_addr, - u32 pci_base_addr, - u32 size, - u32 swap); -int gt64260_cpu_set_pci_mem_window(u32 pci_bus, - u32 window, - u32 cpu_base_addr, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 size, - u32 swap_64bit); -int gt64260_cpu_prot_set_window(u32 window, - u32 base_addr, - u32 size, - u32 access_bits); -int gt64260_cpu_snoop_set_window(u32 window, - u32 base_addr, - u32 size, - u32 snoop_type); -void gt64260_cpu_disable_all_windows(void); -int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits); -int gt64260_pci_slave_scs_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_cs_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_boot_set_window(struct pci_controller *hose, - u32 pci_base_addr, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr, - u32 other_bus_base_addr, - u32 size); -int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose, - u32 pci_base_addr, - u32 other_bus_base_addr, - u32 size); -int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 cpu_base_addr, - u32 size); -int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose, - u32 window, - u32 pci_base_addr_hi, - u32 pci_base_addr_lo, - u32 other_bus_base_addr, - u32 size); -int gt64260_pci_acc_cntl_set_window(u32 pci_bus, - u32 window, - u32 base_addr_hi, - u32 base_addr_lo, - u32 size, - u32 features); -int gt64260_pci_snoop_set_window(u32 pci_bus, - u32 window, - u32 base_addr_hi, - u32 base_addr_lo, - u32 size, - u32 snoop_type); -int gt64260_set_base(u32 new_base); -int gt64260_get_base(u32 *base); -int gt64260_pci_exclude_device(u8 bus, u8 devfn); - -void gt64260_init_irq(void); -int gt64260_get_irq(void); - -void gt64260_mpsc_progress(char *s, unsigned short hex); - -#endif /* __ASMPPC_GT64260_H */ diff --git a/include/asm-ppc/gt64260_defs.h b/include/asm-ppc/gt64260_defs.h deleted file mode 100644 index 6ffd01a5373e..000000000000 --- a/include/asm-ppc/gt64260_defs.h +++ /dev/null @@ -1,1010 +0,0 @@ -/* - * include/asm-ppc/gt64260_defs.h - * - * Register definitions for the Marvell/Galileo GT64260 host bridge. - * - * Author: Mark A. Greer <mgreer@mvista.com> - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASMPPC_GT64260_DEFS_H -#define __ASMPPC_GT64260_DEFS_H - -/* - * Define a macro to represent the supported version of the 64260. - */ -#define GT64260 0x01 -#define GT64260A 0x10 - -/* - ***************************************************************************** - * - * CPU Interface Registers - * - ***************************************************************************** - */ - -/* CPU physical address of 64260's registers */ -#define GT64260_INTERNAL_SPACE_DECODE 0x0068 -#define GT64260_INTERNAL_SPACE_SIZE 0x10000 -#define GT64260_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 - -/* CPU Memory Controller Window Registers (4 windows) */ -#define GT64260_CPU_SCS_DECODE_WINDOWS 4 - -#define GT64260_CPU_SCS_DECODE_0_BOT 0x0008 -#define GT64260_CPU_SCS_DECODE_0_TOP 0x0010 -#define GT64260_CPU_SCS_DECODE_1_BOT 0x0208 -#define GT64260_CPU_SCS_DECODE_1_TOP 0x0210 -#define GT64260_CPU_SCS_DECODE_2_BOT 0x0018 -#define GT64260_CPU_SCS_DECODE_2_TOP 0x0020 -#define GT64260_CPU_SCS_DECODE_3_BOT 0x0218 -#define GT64260_CPU_SCS_DECODE_3_TOP 0x0220 - -/* CPU Device Controller Window Registers (4 windows) */ -#define GT64260_CPU_CS_DECODE_WINDOWS 4 - -#define GT64260_CPU_CS_DECODE_0_BOT 0x0028 -#define GT64260_CPU_CS_DECODE_0_TOP 0x0030 -#define GT64260_CPU_CS_DECODE_1_BOT 0x0228 -#define GT64260_CPU_CS_DECODE_1_TOP 0x0230 -#define GT64260_CPU_CS_DECODE_2_BOT 0x0248 -#define GT64260_CPU_CS_DECODE_2_TOP 0x0250 -#define GT64260_CPU_CS_DECODE_3_BOT 0x0038 -#define GT64260_CPU_CS_DECODE_3_TOP 0x0040 - -#define GT64260_CPU_BOOT_CS_DECODE_0_BOT 0x0238 -#define GT64260_CPU_BOOT_CS_DECODE_0_TOP 0x0240 - -/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ -#define GT64260_PCI_BUSES 2 -#define GT64260_PCI_IO_WINDOWS_PER_BUS 1 -#define GT64260_PCI_MEM_WINDOWS_PER_BUS 4 - -#define GT64260_CPU_PCI_SWAP_BYTE 0x00000000 -#define GT64260_CPU_PCI_SWAP_NONE 0x01000000 -#define GT64260_CPU_PCI_SWAP_BYTE_WORD 0x02000000 -#define GT64260_CPU_PCI_SWAP_WORD 0x03000000 -#define GT64260_CPU_PCI_SWAP_MASK 0x07000000 - -#define GT64260_CPU_PCI_MEM_REQ64 (1<<27) - -#define GT64260_CPU_PCI_0_IO_DECODE_BOT 0x0048 -#define GT64260_CPU_PCI_0_IO_DECODE_TOP 0x0050 -#define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT 0x0058 -#define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP 0x0060 -#define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT 0x0080 -#define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP 0x0088 -#define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT 0x0258 -#define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP 0x0260 -#define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT 0x0280 -#define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP 0x0288 - -#define GT64260_CPU_PCI_0_IO_REMAP 0x00f0 -#define GT64260_CPU_PCI_0_MEM_0_REMAP_LO 0x00f8 -#define GT64260_CPU_PCI_0_MEM_0_REMAP_HI 0x0320 -#define GT64260_CPU_PCI_0_MEM_1_REMAP_LO 0x0100 -#define GT64260_CPU_PCI_0_MEM_1_REMAP_HI 0x0328 -#define GT64260_CPU_PCI_0_MEM_2_REMAP_LO 0x02f8 -#define GT64260_CPU_PCI_0_MEM_2_REMAP_HI 0x0330 -#define GT64260_CPU_PCI_0_MEM_3_REMAP_LO 0x0300 -#define GT64260_CPU_PCI_0_MEM_3_REMAP_HI 0x0338 - -#define GT64260_CPU_PCI_1_IO_DECODE_BOT 0x0090 -#define GT64260_CPU_PCI_1_IO_DECODE_TOP 0x0098 -#define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT 0x00a0 -#define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP 0x00a8 -#define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT 0x00b0 -#define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP 0x00b8 -#define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT 0x02a0 -#define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP 0x02a8 -#define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT 0x02b0 -#define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP 0x02b8 - -#define GT64260_CPU_PCI_1_IO_REMAP 0x0108 -#define GT64260_CPU_PCI_1_MEM_0_REMAP_LO 0x0110 -#define GT64260_CPU_PCI_1_MEM_0_REMAP_HI 0x0340 -#define GT64260_CPU_PCI_1_MEM_1_REMAP_LO 0x0118 -#define GT64260_CPU_PCI_1_MEM_1_REMAP_HI 0x0348 -#define GT64260_CPU_PCI_1_MEM_2_REMAP_LO 0x0310 -#define GT64260_CPU_PCI_1_MEM_2_REMAP_HI 0x0350 -#define GT64260_CPU_PCI_1_MEM_3_REMAP_LO 0x0318 -#define GT64260_CPU_PCI_1_MEM_3_REMAP_HI 0x0358 - -/* CPU Control Registers */ -#define GT64260_CPU_CONFIG 0x0000 -#define GT64260_CPU_MODE 0x0120 -#define GT64260_CPU_MASTER_CNTL 0x0160 -#define GT64260_CPU_XBAR_CNTL_LO 0x0150 -#define GT64260_CPU_XBAR_CNTL_HI 0x0158 -#define GT64260_CPU_XBAR_TO 0x0168 -#define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 -#define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 - -/* CPU Sync Barrier Registers */ -#define GT64260_CPU_SYNC_BARRIER_PCI_0 0x00c0 -#define GT64260_CPU_SYNC_BARRIER_PCI_1 0x00c8 - -/* CPU Access Protection Registers */ -#define GT64260_CPU_PROT_WINDOWS 8 - -#define GT64260_CPU_PROT_ACCPROTECT (1<<16) -#define GT64260_CPU_PROT_WRPROTECT (1<<17) -#define GT64260_CPU_PROT_CACHEPROTECT (1<<18) - -#define GT64260_CPU_PROT_BASE_0 0x0180 -#define GT64260_CPU_PROT_TOP_0 0x0188 -#define GT64260_CPU_PROT_BASE_1 0x0190 -#define GT64260_CPU_PROT_TOP_1 0x0198 -#define GT64260_CPU_PROT_BASE_2 0x01a0 -#define GT64260_CPU_PROT_TOP_2 0x01a8 -#define GT64260_CPU_PROT_BASE_3 0x01b0 -#define GT64260_CPU_PROT_TOP_3 0x01b8 -#define GT64260_CPU_PROT_BASE_4 0x01c0 -#define GT64260_CPU_PROT_TOP_4 0x01c8 -#define GT64260_CPU_PROT_BASE_5 0x01d0 -#define GT64260_CPU_PROT_TOP_5 0x01d8 -#define GT64260_CPU_PROT_BASE_6 0x01e0 -#define GT64260_CPU_PROT_TOP_6 0x01e8 -#define GT64260_CPU_PROT_BASE_7 0x01f0 -#define GT64260_CPU_PROT_TOP_7 0x01f8 - -/* CPU Snoop Control Registers */ -#define GT64260_CPU_SNOOP_WINDOWS 4 - -#define GT64260_CPU_SNOOP_NONE 0x00000000 -#define GT64260_CPU_SNOOP_WT 0x00010000 -#define GT64260_CPU_SNOOP_WB 0x00020000 -#define GT64260_CPU_SNOOP_MASK 0x00030000 -#define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK - -#define GT64260_CPU_SNOOP_BASE_0 0x0380 -#define GT64260_CPU_SNOOP_TOP_0 0x0388 -#define GT64260_CPU_SNOOP_BASE_1 0x0390 -#define GT64260_CPU_SNOOP_TOP_1 0x0398 -#define GT64260_CPU_SNOOP_BASE_2 0x03a0 -#define GT64260_CPU_SNOOP_TOP_2 0x03a8 -#define GT64260_CPU_SNOOP_BASE_3 0x03b0 -#define GT64260_CPU_SNOOP_TOP_3 0x03b8 - -/* CPU Error Report Registers */ -#define GT64260_CPU_ERR_ADDR_LO 0x0070 -#define GT64260_CPU_ERR_ADDR_HI 0x0078 -#define GT64260_CPU_ERR_DATA_LO 0x0128 -#define GT64260_CPU_ERR_DATA_HI 0x0130 -#define GT64260_CPU_ERR_PARITY 0x0138 -#define GT64260_CPU_ERR_CAUSE 0x0140 -#define GT64260_CPU_ERR_MASK 0x0148 - - -/* - ***************************************************************************** - * - * SDRAM Cotnroller Registers - * - ***************************************************************************** - */ - -/* SDRAM Config Registers */ -#define GT64260_SDRAM_CONFIG 0x0448 -#define GT64260_SDRAM_OPERATION_MODE 0x0474 -#define GT64260_SDRAM_ADDR_CNTL 0x047c -#define GT64260_SDRAM_TIMING_PARAMS 0x04b4 -#define GT64260_SDRAM_UMA_CNTL 0x04a4 -#define GT64260_SDRAM_XBAR_CNTL_LO 0x04a8 -#define GT64260_SDRAM_XBAR_CNTL_HI 0x04ac -#define GT64260_SDRAM_XBAR_CNTL_TO 0x04b0 - -/* SDRAM Banks Parameters Registers */ -#define GT64260_SDRAM_BANK_PARAMS_0 0x044c -#define GT64260_SDRAM_BANK_PARAMS_1 0x0450 -#define GT64260_SDRAM_BANK_PARAMS_2 0x0454 -#define GT64260_SDRAM_BANK_PARAMS_3 0x0458 - -/* SDRAM Error Report Registers */ -#define GT64260_SDRAM_ERR_DATA_LO 0x0484 -#define GT64260_SDRAM_ERR_DATA_HI 0x0480 -#define GT64260_SDRAM_ERR_ADDR 0x0490 -#define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 -#define GT64260_SDRAM_ERR_ECC_CALC 0x048c -#define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 -#define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 - - -/* - ***************************************************************************** - * - * Device/BOOT Cotnroller Registers - * - ***************************************************************************** - */ - -/* Device Control Registers */ -#define GT64260_DEV_BANK_PARAMS_0 0x045c -#define GT64260_DEV_BANK_PARAMS_1 0x0460 -#define GT64260_DEV_BANK_PARAMS_2 0x0464 -#define GT64260_DEV_BANK_PARAMS_3 0x0468 -#define GT64260_DEV_BOOT_PARAMS 0x046c -#define GT64260_DEV_IF_CNTL 0x04c0 -#define GT64260_DEV_IF_XBAR_CNTL_LO 0x04c8 -#define GT64260_DEV_IF_XBAR_CNTL_HI 0x04cc -#define GT64260_DEV_IF_XBAR_CNTL_TO 0x04c4 - -/* Device Interrupt Registers */ -#define GT64260_DEV_INTR_CAUSE 0x04d0 -#define GT64260_DEV_INTR_MASK 0x04d4 -#define GT64260_DEV_INTR_ERR_ADDR 0x04d8 - - -/* - ***************************************************************************** - * - * PCI Bridge Interface Registers - * - ***************************************************************************** - */ - -/* PCI Configuration Access Registers */ -#define GT64260_PCI_0_CONFIG_ADDR 0x0cf8 -#define GT64260_PCI_0_CONFIG_DATA 0x0cfc -#define GT64260_PCI_0_IACK 0x0c34 - -#define GT64260_PCI_1_CONFIG_ADDR 0x0c78 -#define GT64260_PCI_1_CONFIG_DATA 0x0c7c -#define GT64260_PCI_1_IACK 0x0cb4 - -/* PCI Control Registers */ -#define GT64260_PCI_0_CMD 0x0c00 -#define GT64260_PCI_0_MODE 0x0d00 -#define GT64260_PCI_0_TO_RETRY 0x0c04 -#define GT64260_PCI_0_RD_BUF_DISCARD_TIMER 0x0d04 -#define GT64260_PCI_0_MSI_TRIGGER_TIMER 0x0c38 -#define GT64260_PCI_0_ARBITER_CNTL 0x1d00 -#define GT64260_PCI_0_XBAR_CNTL_LO 0x1d08 -#define GT64260_PCI_0_XBAR_CNTL_HI 0x1d0c -#define GT64260_PCI_0_XBAR_CNTL_TO 0x1d04 -#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO 0x1d18 -#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI 0x1d1c -#define GT64260_PCI_0_SYNC_BARRIER 0x1d10 -#define GT64260_PCI_0_P2P_CONFIG 0x1d14 -#define GT64260_PCI_0_P2P_SWAP_CNTL 0x1d54 - -#define GT64260_PCI_1_CMD 0x0c80 -#define GT64260_PCI_1_MODE 0x0d80 -#define GT64260_PCI_1_TO_RETRY 0x0c84 -#define GT64260_PCI_1_RD_BUF_DISCARD_TIMER 0x0d84 -#define GT64260_PCI_1_MSI_TRIGGER_TIMER 0x0cb8 -#define GT64260_PCI_1_ARBITER_CNTL 0x1d80 -#define GT64260_PCI_1_XBAR_CNTL_LO 0x1d88 -#define GT64260_PCI_1_XBAR_CNTL_HI 0x1d8c -#define GT64260_PCI_1_XBAR_CNTL_TO 0x1d84 -#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO 0x1d98 -#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI 0x1d9c -#define GT64260_PCI_1_SYNC_BARRIER 0x1d90 -#define GT64260_PCI_1_P2P_CONFIG 0x1d94 -#define GT64260_PCI_1_P2P_SWAP_CNTL 0x1dd4 - -/* PCI Access Control Regions Registers */ -#define GT64260_PCI_ACC_CNTL_WINDOWS 8 - -#define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) -#define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) -#define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) -#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) -#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) -#define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS 0x00000000 -#define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS 0x00100000 -#define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS 0x00200000 -#define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 -#define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 -#define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 -#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 -#define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 -#define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 -#define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) -#define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) - -#define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ - GT64260_PCI_ACC_CNTL_DREADEN | \ - GT64260_PCI_ACC_CNTL_RDPREFETCH | \ - GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ - GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ - GT64260_PCI_ACC_CNTL_MBURST_MASK | \ - GT64260_PCI_ACC_CNTL_SWAP_MASK | \ - GT64260_PCI_ACC_CNTL_ACCPROT| \ - GT64260_PCI_ACC_CNTL_WRPROT) - -#define GT64260_PCI_0_ACC_CNTL_0_BASE_LO 0x1e00 -#define GT64260_PCI_0_ACC_CNTL_0_BASE_HI 0x1e04 -#define GT64260_PCI_0_ACC_CNTL_0_TOP 0x1e08 -#define GT64260_PCI_0_ACC_CNTL_1_BASE_LO 0x1e10 -#define GT64260_PCI_0_ACC_CNTL_1_BASE_HI 0x1e14 -#define GT64260_PCI_0_ACC_CNTL_1_TOP 0x1e18 -#define GT64260_PCI_0_ACC_CNTL_2_BASE_LO 0x1e20 -#define GT64260_PCI_0_ACC_CNTL_2_BASE_HI 0x1e24 -#define GT64260_PCI_0_ACC_CNTL_2_TOP 0x1e28 -#define GT64260_PCI_0_ACC_CNTL_3_BASE_LO 0x1e30 -#define GT64260_PCI_0_ACC_CNTL_3_BASE_HI 0x1e34 -#define GT64260_PCI_0_ACC_CNTL_3_TOP 0x1e38 -#define GT64260_PCI_0_ACC_CNTL_4_BASE_LO 0x1e40 -#define GT64260_PCI_0_ACC_CNTL_4_BASE_HI 0x1e44 -#define GT64260_PCI_0_ACC_CNTL_4_TOP 0x1e48 -#define GT64260_PCI_0_ACC_CNTL_5_BASE_LO 0x1e50 -#define GT64260_PCI_0_ACC_CNTL_5_BASE_HI 0x1e54 -#define GT64260_PCI_0_ACC_CNTL_5_TOP 0x1e58 -#define GT64260_PCI_0_ACC_CNTL_6_BASE_LO 0x1e60 -#define GT64260_PCI_0_ACC_CNTL_6_BASE_HI 0x1e64 -#define GT64260_PCI_0_ACC_CNTL_6_TOP 0x1e68 -#define GT64260_PCI_0_ACC_CNTL_7_BASE_LO 0x1e70 -#define GT64260_PCI_0_ACC_CNTL_7_BASE_HI 0x1e74 -#define GT64260_PCI_0_ACC_CNTL_7_TOP 0x1e78 - -#define GT64260_PCI_1_ACC_CNTL_0_BASE_LO 0x1e80 -#define GT64260_PCI_1_ACC_CNTL_0_BASE_HI 0x1e84 -#define GT64260_PCI_1_ACC_CNTL_0_TOP 0x1e88 -#define GT64260_PCI_1_ACC_CNTL_1_BASE_LO 0x1e90 -#define GT64260_PCI_1_ACC_CNTL_1_BASE_HI 0x1e94 -#define GT64260_PCI_1_ACC_CNTL_1_TOP 0x1e98 -#define GT64260_PCI_1_ACC_CNTL_2_BASE_LO 0x1ea0 -#define GT64260_PCI_1_ACC_CNTL_2_BASE_HI 0x1ea4 -#define GT64260_PCI_1_ACC_CNTL_2_TOP 0x1ea8 -#define GT64260_PCI_1_ACC_CNTL_3_BASE_LO 0x1eb0 -#define GT64260_PCI_1_ACC_CNTL_3_BASE_HI 0x1eb4 -#define GT64260_PCI_1_ACC_CNTL_3_TOP 0x1eb8 -#define GT64260_PCI_1_ACC_CNTL_4_BASE_LO 0x1ec0 -#define GT64260_PCI_1_ACC_CNTL_4_BASE_HI 0x1ec4 -#define GT64260_PCI_1_ACC_CNTL_4_TOP 0x1ec8 -#define GT64260_PCI_1_ACC_CNTL_5_BASE_LO 0x1ed0 -#define GT64260_PCI_1_ACC_CNTL_5_BASE_HI 0x1ed4 -#define GT64260_PCI_1_ACC_CNTL_5_TOP 0x1ed8 -#define GT64260_PCI_1_ACC_CNTL_6_BASE_LO 0x1ee0 -#define GT64260_PCI_1_ACC_CNTL_6_BASE_HI 0x1ee4 -#define GT64260_PCI_1_ACC_CNTL_6_TOP 0x1ee8 -#define GT64260_PCI_1_ACC_CNTL_7_BASE_LO 0x1ef0 -#define GT64260_PCI_1_ACC_CNTL_7_BASE_HI 0x1ef4 -#define GT64260_PCI_1_ACC_CNTL_7_TOP 0x1ef8 - -/* PCI Snoop Control Registers */ -#define GT64260_PCI_SNOOP_WINDOWS 4 - -#define GT64260_PCI_SNOOP_NONE 0x00000000 -#define GT64260_PCI_SNOOP_WT 0x00001000 -#define GT64260_PCI_SNOOP_WB 0x00002000 - -#define GT64260_PCI_0_SNOOP_0_BASE_LO 0x1f00 -#define GT64260_PCI_0_SNOOP_0_BASE_HI 0x1f04 -#define GT64260_PCI_0_SNOOP_0_TOP 0x1f08 -#define GT64260_PCI_0_SNOOP_1_BASE_LO 0x1f10 -#define GT64260_PCI_0_SNOOP_1_BASE_HI 0x1f14 -#define GT64260_PCI_0_SNOOP_1_TOP 0x1f18 -#define GT64260_PCI_0_SNOOP_2_BASE_LO 0x1f20 -#define GT64260_PCI_0_SNOOP_2_BASE_HI 0x1f24 -#define GT64260_PCI_0_SNOOP_2_TOP 0x1f28 -#define GT64260_PCI_0_SNOOP_3_BASE_LO 0x1f30 -#define GT64260_PCI_0_SNOOP_3_BASE_HI 0x1f34 -#define GT64260_PCI_0_SNOOP_3_TOP 0x1f38 - -#define GT64260_PCI_1_SNOOP_0_BASE_LO 0x1f80 -#define GT64260_PCI_1_SNOOP_0_BASE_HI 0x1f84 -#define GT64260_PCI_1_SNOOP_0_TOP 0x1f88 -#define GT64260_PCI_1_SNOOP_1_BASE_LO 0x1f90 -#define GT64260_PCI_1_SNOOP_1_BASE_HI 0x1f94 -#define GT64260_PCI_1_SNOOP_1_TOP 0x1f98 -#define GT64260_PCI_1_SNOOP_2_BASE_LO 0x1fa0 -#define GT64260_PCI_1_SNOOP_2_BASE_HI 0x1fa4 -#define GT64260_PCI_1_SNOOP_2_TOP 0x1fa8 -#define GT64260_PCI_1_SNOOP_3_BASE_LO 0x1fb0 -#define GT64260_PCI_1_SNOOP_3_BASE_HI 0x1fb4 -#define GT64260_PCI_1_SNOOP_3_TOP 0x1fb8 - -/* PCI Error Report Registers */ -#define GT64260_PCI_0_ERR_SERR_MASK 0x0c28 -#define GT64260_PCI_0_ERR_ADDR_LO 0x1d40 -#define GT64260_PCI_0_ERR_ADDR_HI 0x1d44 -#define GT64260_PCI_0_ERR_DATA_LO 0x1d48 -#define GT64260_PCI_0_ERR_DATA_HI 0x1d4c -#define GT64260_PCI_0_ERR_CMD 0x1d50 -#define GT64260_PCI_0_ERR_CAUSE 0x1d58 -#define GT64260_PCI_0_ERR_MASK 0x1d5c - -#define GT64260_PCI_1_ERR_SERR_MASK 0x0ca8 -#define GT64260_PCI_1_ERR_ADDR_LO 0x1dc0 -#define GT64260_PCI_1_ERR_ADDR_HI 0x1dc4 -#define GT64260_PCI_1_ERR_DATA_LO 0x1dc8 -#define GT64260_PCI_1_ERR_DATA_HI 0x1dcc -#define GT64260_PCI_1_ERR_CMD 0x1dd0 -#define GT64260_PCI_1_ERR_CAUSE 0x1dd8 -#define GT64260_PCI_1_ERR_MASK 0x1ddc - -/* PCI Slave Address Decoding Registers */ -#define GT64260_PCI_SCS_WINDOWS 4 -#define GT64260_PCI_CS_WINDOWS 4 -#define GT64260_PCI_BOOT_WINDOWS 1 -#define GT64260_PCI_P2P_MEM_WINDOWS 2 -#define GT64260_PCI_P2P_IO_WINDOWS 1 -#define GT64260_PCI_DAC_SCS_WINDOWS 4 -#define GT64260_PCI_DAC_CS_WINDOWS 4 -#define GT64260_PCI_DAC_BOOT_WINDOWS 1 -#define GT64260_PCI_DAC_P2P_MEM_WINDOWS 2 - -#define GT64260_PCI_0_SLAVE_SCS_0_SIZE 0x0c08 -#define GT64260_PCI_0_SLAVE_SCS_1_SIZE 0x0d08 -#define GT64260_PCI_0_SLAVE_SCS_2_SIZE 0x0c0c -#define GT64260_PCI_0_SLAVE_SCS_3_SIZE 0x0d0c -#define GT64260_PCI_0_SLAVE_CS_0_SIZE 0x0c10 -#define GT64260_PCI_0_SLAVE_CS_1_SIZE 0x0d10 -#define GT64260_PCI_0_SLAVE_CS_2_SIZE 0x0d18 -#define GT64260_PCI_0_SLAVE_CS_3_SIZE 0x0c14 -#define GT64260_PCI_0_SLAVE_BOOT_SIZE 0x0d14 -#define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE 0x0d1c -#define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE 0x0d20 -#define GT64260_PCI_0_SLAVE_P2P_IO_SIZE 0x0d24 -#define GT64260_PCI_0_SLAVE_CPU_SIZE 0x0d28 - -#define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE 0x0e00 -#define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE 0x0e04 -#define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE 0x0e08 -#define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE 0x0e0c -#define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE 0x0e10 -#define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE 0x0e14 -#define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE 0x0e18 -#define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE 0x0e1c -#define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE 0x0e20 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE 0x0e24 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE 0x0e28 -#define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE 0x0e2c - -#define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE 0x0d2c - -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0 (1<<0) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1 (1<<1) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2 (1<<2) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3 (1<<3) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0 (1<<4) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1 (1<<5) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2 (1<<6) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3 (1<<7) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT (1<<8) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM (1<<9) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO (1<<10) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0 (1<<11) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1 (1<<12) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO (1<<13) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU (1<<14) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0 (1<<15) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1 (1<<16) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2 (1<<17) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3 (1<<18) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0 (1<<19) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1 (1<<20) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2 (1<<21) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3 (1<<22) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT (1<<23) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25) -#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU (1<<26) - -#define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES 0x0c3c -#define GT64260_PCI_0_SLAVE_SCS_0_REMAP 0x0c48 -#define GT64260_PCI_0_SLAVE_SCS_1_REMAP 0x0d48 -#define GT64260_PCI_0_SLAVE_SCS_2_REMAP 0x0c4c -#define GT64260_PCI_0_SLAVE_SCS_3_REMAP 0x0d4c -#define GT64260_PCI_0_SLAVE_CS_0_REMAP 0x0c50 -#define GT64260_PCI_0_SLAVE_CS_1_REMAP 0x0d50 -#define GT64260_PCI_0_SLAVE_CS_2_REMAP 0x0d58 -#define GT64260_PCI_0_SLAVE_CS_3_REMAP 0x0c54 -#define GT64260_PCI_0_SLAVE_BOOT_REMAP 0x0d54 -#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c -#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 -#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 -#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 -#define GT64260_PCI_0_SLAVE_P2P_IO_REMAP 0x0d6c -#define GT64260_PCI_0_SLAVE_CPU_REMAP 0x0d70 - -#define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP 0x0f00 -#define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP 0x0f04 -#define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP 0x0f08 -#define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP 0x0f0c -#define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP 0x0f10 -#define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP 0x0f14 -#define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP 0x0f18 -#define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP 0x0f1c -#define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP 0x0f20 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0f24 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0f28 -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0f2c -#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0f30 -#define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP 0x0f34 - -#define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP 0x0f38 -#define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL 0x0d3c - -#define GT64260_PCI_1_SLAVE_SCS_0_SIZE 0x0c88 -#define GT64260_PCI_1_SLAVE_SCS_1_SIZE 0x0d88 -#define GT64260_PCI_1_SLAVE_SCS_2_SIZE 0x0c8c -#define GT64260_PCI_1_SLAVE_SCS_3_SIZE 0x0d8c -#define GT64260_PCI_1_SLAVE_CS_0_SIZE 0x0c90 -#define GT64260_PCI_1_SLAVE_CS_1_SIZE 0x0d90 -#define GT64260_PCI_1_SLAVE_CS_2_SIZE 0x0d98 -#define GT64260_PCI_1_SLAVE_CS_3_SIZE 0x0c94 -#define GT64260_PCI_1_SLAVE_BOOT_SIZE 0x0d94 -#define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE 0x0d9c -#define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE 0x0da0 -#define GT64260_PCI_1_SLAVE_P2P_IO_SIZE 0x0da4 -#define GT64260_PCI_1_SLAVE_CPU_SIZE 0x0da8 - -#define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE 0x0e80 -#define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE 0x0e84 -#define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE 0x0e88 -#define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE 0x0e8c -#define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE 0x0e90 -#define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE 0x0e94 -#define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE 0x0e98 -#define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE 0x0e9c -#define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE 0x0ea0 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE 0x0ea4 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE 0x0ea8 -#define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE 0x0eac - -#define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE 0x0dac - -#define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES 0x0cbc -#define GT64260_PCI_1_SLAVE_SCS_0_REMAP 0x0cc8 -#define GT64260_PCI_1_SLAVE_SCS_1_REMAP 0x0dc8 -#define GT64260_PCI_1_SLAVE_SCS_2_REMAP 0x0ccc -#define GT64260_PCI_1_SLAVE_SCS_3_REMAP 0x0dcc -#define GT64260_PCI_1_SLAVE_CS_0_REMAP 0x0cd0 -#define GT64260_PCI_1_SLAVE_CS_1_REMAP 0x0dd0 -#define GT64260_PCI_1_SLAVE_CS_2_REMAP 0x0dd8 -#define GT64260_PCI_1_SLAVE_CS_3_REMAP 0x0cd4 -#define GT64260_PCI_1_SLAVE_BOOT_REMAP 0x0dd4 -#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc -#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 -#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 -#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 -#define GT64260_PCI_1_SLAVE_P2P_IO_REMAP 0x0dec -#define GT64260_PCI_1_SLAVE_CPU_REMAP 0x0df0 - -#define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP 0x0f80 -#define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP 0x0f84 -#define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP 0x0f88 -#define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP 0x0f8c -#define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP 0x0f90 -#define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP 0x0f94 -#define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP 0x0f98 -#define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP 0x0f9c -#define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP 0x0fa0 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0fa4 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0fa8 -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0fac -#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0fb0 -#define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP 0x0fb4 - -#define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP 0x0fb8 -#define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL 0x0dbc - - -/* - ***************************************************************************** - * - * I2O Controller Interface Registers - * - ***************************************************************************** - */ - -/* FIXME: fill in */ - - - -/* - ***************************************************************************** - * - * DMA Controller Interface Registers - * - ***************************************************************************** - */ - -/* FIXME: fill in */ - - -/* - ***************************************************************************** - * - * Timer/Counter Interface Registers - * - ***************************************************************************** - */ - -/* FIXME: fill in */ - - -/* - ***************************************************************************** - * - * Communications Controller (Enet, Serial, etc.) Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_ENET_0_CNTL_LO 0xf200 -#define GT64260_ENET_0_CNTL_HI 0xf204 -#define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI 0xf208 -#define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI 0xf20c -#define GT64260_ENET_0_RX_DESC_ADDR_HI 0xf210 -#define GT64260_ENET_0_TX_DESC_ADDR_HI 0xf214 -#define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI 0xf218 -#define GT64260_ENET_1_CNTL_LO 0xf220 -#define GT64260_ENET_1_CNTL_HI 0xf224 -#define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI 0xf228 -#define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI 0xf22c -#define GT64260_ENET_1_RX_DESC_ADDR_HI 0xf230 -#define GT64260_ENET_1_TX_DESC_ADDR_HI 0xf234 -#define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI 0xf238 -#define GT64260_ENET_2_CNTL_LO 0xf240 -#define GT64260_ENET_2_CNTL_HI 0xf244 -#define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI 0xf248 -#define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI 0xf24c -#define GT64260_ENET_2_RX_DESC_ADDR_HI 0xf250 -#define GT64260_ENET_2_TX_DESC_ADDR_HI 0xf254 -#define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI 0xf258 - -#define GT64260_MPSC_0_CNTL_LO 0xf280 -#define GT64260_MPSC_0_CNTL_HI 0xf284 -#define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI 0xf288 -#define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI 0xf28c -#define GT64260_MPSC_0_RX_DESC_ADDR_HI 0xf290 -#define GT64260_MPSC_0_TX_DESC_ADDR_HI 0xf294 -#define GT64260_MPSC_1_CNTL_LO 0xf2c0 -#define GT64260_MPSC_1_CNTL_HI 0xf2c4 -#define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI 0xf2c8 -#define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI 0xf2cc -#define GT64260_MPSC_1_RX_DESC_ADDR_HI 0xf2d0 -#define GT64260_MPSC_1_TX_DESC_ADDR_HI 0xf2d4 - -#define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 -#define GT64260_SER_INIT_LAST_DATA 0xf324 -#define GT64260_SER_INIT_CONTROL 0xf328 -#define GT64260_SER_INIT_STATUS 0xf32c - -#define GT64260_COMM_ARBITER_CNTL 0xf300 -#define GT64260_COMM_CONFIG 0xb40c -#define GT64260_COMM_XBAR_TO 0xf304 -#define GT64260_COMM_INTR_CAUSE 0xf310 -#define GT64260_COMM_INTR_MASK 0xf314 -#define GT64260_COMM_ERR_ADDR 0xf318 - - -/* - ***************************************************************************** - * - * Fast Ethernet Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_ENET_PHY_ADDR 0x2000 -#define GT64260_ENET_ESMIR 0x2010 - -#define GT64260_ENET_E0PCR 0x2400 -#define GT64260_ENET_E0PCXR 0x2408 -#define GT64260_ENET_E0PCMR 0x2410 -#define GT64260_ENET_E0PSR 0x2418 -#define GT64260_ENET_E0SPR 0x2420 -#define GT64260_ENET_E0HTPR 0x2428 -#define GT64260_ENET_E0FCSAL 0x2430 -#define GT64260_ENET_E0FCSAH 0x2438 -#define GT64260_ENET_E0SDCR 0x2440 -#define GT64260_ENET_E0SDCMR 0x2448 -#define GT64260_ENET_E0ICR 0x2450 -#define GT64260_ENET_E0IMR 0x2458 -#define GT64260_ENET_E0FRDP0 0x2480 -#define GT64260_ENET_E0FRDP1 0x2484 -#define GT64260_ENET_E0FRDP2 0x2488 -#define GT64260_ENET_E0FRDP3 0x248c -#define GT64260_ENET_E0CRDP0 0x24a0 -#define GT64260_ENET_E0CRDP1 0x24a4 -#define GT64260_ENET_E0CRDP2 0x24a8 -#define GT64260_ENET_E0CRDP3 0x24ac -#define GT64260_ENET_E0CTDP0 0x24e0 -#define GT64260_ENET_E0CTDP1 0x24e4 -#define GT64260_ENET_0_DSCP2P0L 0x2460 -#define GT64260_ENET_0_DSCP2P0H 0x2464 -#define GT64260_ENET_0_DSCP2P1L 0x2468 -#define GT64260_ENET_0_DSCP2P1H 0x246c -#define GT64260_ENET_0_VPT2P 0x2470 -#define GT64260_ENET_0_MIB_CTRS 0x2500 - -#define GT64260_ENET_E1PCR 0x2800 -#define GT64260_ENET_E1PCXR 0x2808 -#define GT64260_ENET_E1PCMR 0x2810 -#define GT64260_ENET_E1PSR 0x2818 -#define GT64260_ENET_E1SPR 0x2820 -#define GT64260_ENET_E1HTPR 0x2828 -#define GT64260_ENET_E1FCSAL 0x2830 -#define GT64260_ENET_E1FCSAH 0x2838 -#define GT64260_ENET_E1SDCR 0x2840 -#define GT64260_ENET_E1SDCMR 0x2848 -#define GT64260_ENET_E1ICR 0x2850 -#define GT64260_ENET_E1IMR 0x2858 -#define GT64260_ENET_E1FRDP0 0x2880 -#define GT64260_ENET_E1FRDP1 0x2884 -#define GT64260_ENET_E1FRDP2 0x2888 -#define GT64260_ENET_E1FRDP3 0x288c -#define GT64260_ENET_E1CRDP0 0x28a0 -#define GT64260_ENET_E1CRDP1 0x28a4 -#define GT64260_ENET_E1CRDP2 0x28a8 -#define GT64260_ENET_E1CRDP3 0x28ac -#define GT64260_ENET_E1CTDP0 0x28e0 -#define GT64260_ENET_E1CTDP1 0x28e4 -#define GT64260_ENET_1_DSCP2P0L 0x2860 -#define GT64260_ENET_1_DSCP2P0H 0x2864 -#define GT64260_ENET_1_DSCP2P1L 0x2868 -#define GT64260_ENET_1_DSCP2P1H 0x286c -#define GT64260_ENET_1_VPT2P 0x2870 -#define GT64260_ENET_1_MIB_CTRS 0x2900 - -#define GT64260_ENET_E2PCR 0x2c00 -#define GT64260_ENET_E2PCXR 0x2c08 -#define GT64260_ENET_E2PCMR 0x2c10 -#define GT64260_ENET_E2PSR 0x2c18 -#define GT64260_ENET_E2SPR 0x2c20 -#define GT64260_ENET_E2HTPR 0x2c28 -#define GT64260_ENET_E2FCSAL 0x2c30 -#define GT64260_ENET_E2FCSAH 0x2c38 -#define GT64260_ENET_E2SDCR 0x2c40 -#define GT64260_ENET_E2SDCMR 0x2c48 -#define GT64260_ENET_E2ICR 0x2c50 -#define GT64260_ENET_E2IMR 0x2c58 -#define GT64260_ENET_E2FRDP0 0x2c80 -#define GT64260_ENET_E2FRDP1 0x2c84 -#define GT64260_ENET_E2FRDP2 0x2c88 -#define GT64260_ENET_E2FRDP3 0x2c8c -#define GT64260_ENET_E2CRDP0 0x2ca0 -#define GT64260_ENET_E2CRDP1 0x2ca4 -#define GT64260_ENET_E2CRDP2 0x2ca8 -#define GT64260_ENET_E2CRDP3 0x2cac -#define GT64260_ENET_E2CTDP0 0x2ce0 -#define GT64260_ENET_E2CTDP1 0x2ce4 -#define GT64260_ENET_2_DSCP2P0L 0x2c60 -#define GT64260_ENET_2_DSCP2P0H 0x2c64 -#define GT64260_ENET_2_DSCP2P1L 0x2c68 -#define GT64260_ENET_2_DSCP2P1H 0x2c6c -#define GT64260_ENET_2_VPT2P 0x2c70 -#define GT64260_ENET_2_MIB_CTRS 0x2d00 - - -/* - ***************************************************************************** - * - * Multi-Protocol Serial Controller Interface Registers - * - ***************************************************************************** - */ - -/* Signal Routing */ -#define GT64260_MPSC_MRR 0xb400 -#define GT64260_MPSC_RCRR 0xb404 -#define GT64260_MPSC_TCRR 0xb408 - -/* Main Configuratino Registers */ -#define GT64260_MPSC_0_MMCRL 0x8000 -#define GT64260_MPSC_0_MMCRH 0x8004 -#define GT64260_MPSC_0_MPCR 0x8008 -#define GT64260_MPSC_0_CHR_1 0x800c -#define GT64260_MPSC_0_CHR_2 0x8010 -#define GT64260_MPSC_0_CHR_3 0x8014 -#define GT64260_MPSC_0_CHR_4 0x8018 -#define GT64260_MPSC_0_CHR_5 0x801c -#define GT64260_MPSC_0_CHR_6 0x8020 -#define GT64260_MPSC_0_CHR_7 0x8024 -#define GT64260_MPSC_0_CHR_8 0x8028 -#define GT64260_MPSC_0_CHR_9 0x802c -#define GT64260_MPSC_0_CHR_10 0x8030 -#define GT64260_MPSC_0_CHR_11 0x8034 - -#define GT64260_MPSC_1_MMCRL 0x9000 -#define GT64260_MPSC_1_MMCRH 0x9004 -#define GT64260_MPSC_1_MPCR 0x9008 -#define GT64260_MPSC_1_CHR_1 0x900c -#define GT64260_MPSC_1_CHR_2 0x9010 -#define GT64260_MPSC_1_CHR_3 0x9014 -#define GT64260_MPSC_1_CHR_4 0x9018 -#define GT64260_MPSC_1_CHR_5 0x901c -#define GT64260_MPSC_1_CHR_6 0x9020 -#define GT64260_MPSC_1_CHR_7 0x9024 -#define GT64260_MPSC_1_CHR_8 0x9028 -#define GT64260_MPSC_1_CHR_9 0x902c -#define GT64260_MPSC_1_CHR_10 0x9030 -#define GT64260_MPSC_1_CHR_11 0x9034 - -#define GT64260_MPSC_0_INTR_CAUSE 0xb804 -#define GT64260_MPSC_0_INTR_MASK 0xb884 -#define GT64260_MPSC_1_INTR_CAUSE 0xb80c -#define GT64260_MPSC_1_INTR_MASK 0xb88c - -#define GT64260_MPSC_UART_CR_TEV (1<<1) -#define GT64260_MPSC_UART_CR_TA (1<<7) -#define GT64260_MPSC_UART_CR_TTCS (1<<9) -#define GT64260_MPSC_UART_CR_REV (1<<17) -#define GT64260_MPSC_UART_CR_RA (1<<23) -#define GT64260_MPSC_UART_CR_CRD (1<<25) -#define GT64260_MPSC_UART_CR_EH (1<<31) - -#define GT64260_MPSC_UART_ESR_CTS (1<<0) -#define GT64260_MPSC_UART_ESR_CD (1<<1) -#define GT64260_MPSC_UART_ESR_TIDLE (1<<3) -#define GT64260_MPSC_UART_ESR_RHS (1<<5) -#define GT64260_MPSC_UART_ESR_RLS (1<<7) -#define GT64260_MPSC_UART_ESR_RLIDL (1<<11) - - -/* - ***************************************************************************** - * - * Serial DMA Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_SDMA_0_SDC 0x4000 -#define GT64260_SDMA_0_SDCM 0x4008 -#define GT64260_SDMA_0_RX_DESC 0x4800 -#define GT64260_SDMA_0_RX_BUF_PTR 0x4808 -#define GT64260_SDMA_0_SCRDP 0x4810 -#define GT64260_SDMA_0_TX_DESC 0x4c00 -#define GT64260_SDMA_0_SCTDP 0x4c10 -#define GT64260_SDMA_0_SFTDP 0x4c14 - -#define GT64260_SDMA_1_SDC 0x6000 -#define GT64260_SDMA_1_SDCM 0x6008 -#define GT64260_SDMA_1_RX_DESC 0x6800 -#define GT64260_SDMA_1_RX_BUF_PTR 0x6808 -#define GT64260_SDMA_1_SCRDP 0x6810 -#define GT64260_SDMA_1_TX_DESC 0x6c00 -#define GT64260_SDMA_1_SCTDP 0x6c10 -#define GT64260_SDMA_1_SFTDP 0x6c14 - -#define GT64260_SDMA_INTR_CAUSE 0xb800 -#define GT64260_SDMA_INTR_MASK 0xb880 - -#define GT64260_SDMA_DESC_CMDSTAT_PE (1<<0) -#define GT64260_SDMA_DESC_CMDSTAT_CDL (1<<1) -#define GT64260_SDMA_DESC_CMDSTAT_FR (1<<3) -#define GT64260_SDMA_DESC_CMDSTAT_OR (1<<6) -#define GT64260_SDMA_DESC_CMDSTAT_BR (1<<9) -#define GT64260_SDMA_DESC_CMDSTAT_MI (1<<10) -#define GT64260_SDMA_DESC_CMDSTAT_A (1<<11) -#define GT64260_SDMA_DESC_CMDSTAT_AM (1<<12) -#define GT64260_SDMA_DESC_CMDSTAT_CT (1<<13) -#define GT64260_SDMA_DESC_CMDSTAT_C (1<<14) -#define GT64260_SDMA_DESC_CMDSTAT_ES (1<<15) -#define GT64260_SDMA_DESC_CMDSTAT_L (1<<16) -#define GT64260_SDMA_DESC_CMDSTAT_F (1<<17) -#define GT64260_SDMA_DESC_CMDSTAT_P (1<<18) -#define GT64260_SDMA_DESC_CMDSTAT_EI (1<<23) -#define GT64260_SDMA_DESC_CMDSTAT_O (1<<31) - -#define GT64260_SDMA_SDC_RFT (1<<0) -#define GT64260_SDMA_SDC_SFM (1<<1) -#define GT64260_SDMA_SDC_BLMR (1<<6) -#define GT64260_SDMA_SDC_BLMT (1<<7) -#define GT64260_SDMA_SDC_POVR (1<<8) -#define GT64260_SDMA_SDC_RIFB (1<<9) - -#define GT64260_SDMA_SDCM_ERD (1<<7) -#define GT64260_SDMA_SDCM_AR (1<<15) -#define GT64260_SDMA_SDCM_STD (1<<16) -#define GT64260_SDMA_SDCM_TXD (1<<23) -#define GT64260_SDMA_SDCM_AT (1<<31) - -#define GT64260_SDMA_0_CAUSE_RXBUF (1<<0) -#define GT64260_SDMA_0_CAUSE_RXERR (1<<1) -#define GT64260_SDMA_0_CAUSE_TXBUF (1<<2) -#define GT64260_SDMA_0_CAUSE_TXEND (1<<3) -#define GT64260_SDMA_1_CAUSE_RXBUF (1<<8) -#define GT64260_SDMA_1_CAUSE_RXERR (1<<9) -#define GT64260_SDMA_1_CAUSE_TXBUF (1<<10) -#define GT64260_SDMA_1_CAUSE_TXEND (1<<11) - - -/* - ***************************************************************************** - * - * Baud Rate Generator Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_BRG_0_BCR 0xb200 -#define GT64260_BRG_0_BTR 0xb204 -#define GT64260_BRG_1_BCR 0xb208 -#define GT64260_BRG_1_BTR 0xb20c -#define GT64260_BRG_2_BCR 0xb210 -#define GT64260_BRG_2_BTR 0xb214 - -#define GT64260_BRG_INTR_CAUSE 0xb834 -#define GT64260_BRG_INTR_MASK 0xb8b4 - - -/* - ***************************************************************************** - * - * Watchdog Timer Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_WDT_WDC 0xb410 -#define GT64260_WDT_WDV 0xb414 - - -/* - ***************************************************************************** - * - * General Purpose Pins Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_GPP_IO_CNTL 0xf100 -#define GT64260_GPP_LEVEL_CNTL 0xf110 -#define GT64260_GPP_VALUE 0xf104 -#define GT64260_GPP_INTR_CAUSE 0xf108 -#define GT64260_GPP_INTR_MASK 0xf10c - - -/* - ***************************************************************************** - * - * Multi-Purpose Pins Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_MPP_CNTL_0 0xf000 -#define GT64260_MPP_CNTL_1 0xf004 -#define GT64260_MPP_CNTL_2 0xf008 -#define GT64260_MPP_CNTL_3 0xf00c -#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 - - -/* - ***************************************************************************** - * - * I2C Controller Interface Registers - * - ***************************************************************************** - */ - -/* FIXME: fill in */ - - -/* - ***************************************************************************** - * - * Interrupt Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_IC_MAIN_CAUSE_LO 0x0c18 -#define GT64260_IC_MAIN_CAUSE_HI 0x0c68 -#define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c -#define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c -#define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 -#define GT64260_IC_PCI_0_INTR_MASK_LO 0x0c24 -#define GT64260_IC_PCI_0_INTR_MASK_HI 0x0c64 -#define GT64260_IC_PCI_0_SELECT_CAUSE 0x0c74 -#define GT64260_IC_PCI_1_INTR_MASK_LO 0x0ca4 -#define GT64260_IC_PCI_1_INTR_MASK_HI 0x0ce4 -#define GT64260_IC_PCI_1_SELECT_CAUSE 0x0cf4 -#define GT64260_IC_CPU_INT_0_MASK 0x0e60 -#define GT64260_IC_CPU_INT_1_MASK 0x0e64 -#define GT64260_IC_CPU_INT_2_MASK 0x0e68 -#define GT64260_IC_CPU_INT_3_MASK 0x0e6c - - -#endif /* __ASMPPC_GT64260_DEFS_H */ diff --git a/include/asm-ppc/harrier.h b/include/asm-ppc/harrier.h deleted file mode 100644 index 7acd7fc126ec..000000000000 --- a/include/asm-ppc/harrier.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Definitions for Motorola MCG Harrier North Bridge & Memory controller - * - * Author: Dale Farnsworth - * dale.farnsworth@mvista.com - * - * Modified by: Randy Vinson - * rvinson@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASMPPC_HARRIER_H -#define __ASMPPC_HARRIER_H - -#include <linux/types.h> -#include <asm/pci-bridge.h> - -struct pci_controller; -int harrier_init(struct pci_controller *hose, - uint ppc_reg_base, - ulong processor_pci_mem_start, - ulong processor_pci_mem_end, - ulong processor_pci_io_start, - ulong processor_pci_io_end, - ulong processor_mpic_base); - -unsigned long harrier_get_mem_size(uint smc_base); - -int harrier_mpic_init(unsigned int pci_mem_offset); - -void harrier_setup_nonmonarch(uint ppc_reg_base, - uint in0_size); -void harrier_release_eready(uint ppc_reg_base); - -void harrier_wait_eready(uint ppc_reg_base); - -#endif /* __ASMPPC_HARRIER_H */ diff --git a/include/asm-ppc/hawk.h b/include/asm-ppc/hawk.h deleted file mode 100644 index f347007d22af..000000000000 --- a/include/asm-ppc/hawk.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * include/asm-ppc/hawk.h - * - * Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * Modified by Randy Vinson (rvinson@mvista.com) - * - * 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __ASMPPC_HAWK_H -#define __ASMPPC_HAWK_H - -#include <asm/pci-bridge.h> -#include <asm/hawk_defs.h> - -extern int hawk_init(struct pci_controller *hose, - unsigned int ppc_reg_base, unsigned long processor_pci_mem_start, - unsigned long processor_pci_mem_end, - unsigned long processor_pci_io_start, - unsigned long processor_pci_io_end, - unsigned long processor_mpic_base); -extern unsigned long hawk_get_mem_size(unsigned int smc_base); -extern int hawk_mpic_init(unsigned int pci_mem_offset); - -#endif /* __ASMPPC_HAWK_H */ diff --git a/include/asm-ppc/hawk_defs.h b/include/asm-ppc/hawk_defs.h deleted file mode 100644 index 6d1d2baf648c..000000000000 --- a/include/asm-ppc/hawk_defs.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * include/asm-ppc/hawk_defs.h - * - * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * Modified by Randy Vinson (rvinson@mvista.com) - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __ASMPPC_HAWK_DEFS_H -#define __ASMPPC_HAWK_DEFS_H - -#include <asm/pci-bridge.h> - -/* - * The Falcon/Raven and HAWK have 4 sets of registers: - * 1) PPC Registers which define the mappings from PPC bus to PCI bus, - * etc. - * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the - * MPIC base address. - * 3) MPIC registers - * 4) System Memory Controller (SMC) registers. - */ - -#define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8 -#define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc - -#define HAWK_MPIC_SIZE 0x00040000U -#define HAWK_SMC_SIZE 0x00001000U - -/* - * Define PPC register offsets. - */ -#define HAWK_PPC_XSADD0_OFF 0x40 -#define HAWK_PPC_XSOFF0_OFF 0x44 -#define HAWK_PPC_XSADD1_OFF 0x48 -#define HAWK_PPC_XSOFF1_OFF 0x4c -#define HAWK_PPC_XSADD2_OFF 0x50 -#define HAWK_PPC_XSOFF2_OFF 0x54 -#define HAWK_PPC_XSADD3_OFF 0x58 -#define HAWK_PPC_XSOFF3_OFF 0x5c - -/* - * Define PCI register offsets. - */ -#define HAWK_PCI_PSADD0_OFF 0x80 -#define HAWK_PCI_PSOFF0_OFF 0x84 -#define HAWK_PCI_PSADD1_OFF 0x88 -#define HAWK_PCI_PSOFF1_OFF 0x8c -#define HAWK_PCI_PSADD2_OFF 0x90 -#define HAWK_PCI_PSOFF2_OFF 0x94 -#define HAWK_PCI_PSADD3_OFF 0x98 -#define HAWK_PCI_PSOFF3_OFF 0x9c - -/* - * Define the System Memory Controller (SMC) register offsets. - */ -#define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10 -#define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11 -#define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12 -#define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13 -#define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */ -#define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */ -#define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */ -#define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */ - -#define FALCON_SMC_REG_COUNT 4 -#define HAWK_SMC_REG_COUNT 8 -#endif /* __ASMPPC_HAWK_DEFS_H */ diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h deleted file mode 100644 index f7b21ee302b4..000000000000 --- a/include/asm-ppc/highmem.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * highmem.h: virtual kernel memory mappings for high memory - * - * PowerPC version, stolen from the i386 version. - * - * Used in CONFIG_HIGHMEM systems for memory pages which - * are not addressable by direct kernel virtual addresses. - * - * Copyright (C) 1999 Gerhard Wichert, Siemens AG - * Gerhard.Wichert@pdb.siemens.de - * - * - * Redesigned the x86 32-bit VM architecture to deal with - * up to 16 Terrabyte physical memory. With current x86 CPUs - * we now support up to 64 Gigabytes physical RAM. - * - * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> - */ - -#ifndef _ASM_HIGHMEM_H -#define _ASM_HIGHMEM_H - -#ifdef __KERNEL__ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <asm/kmap_types.h> -#include <asm/tlbflush.h> -#include <asm/page.h> - -/* undef for production */ -#define HIGHMEM_DEBUG 1 - -extern pte_t *kmap_pte; -extern pgprot_t kmap_prot; -extern pte_t *pkmap_page_table; - -/* - * Right now we initialize only a single pte table. It can be extended - * easily, subsequent pte tables have to be allocated in one physical - * chunk of RAM. - */ -#define PKMAP_BASE CONFIG_HIGHMEM_START -#define LAST_PKMAP (1 << PTE_SHIFT) -#define LAST_PKMAP_MASK (LAST_PKMAP-1) -#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) -#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) - -#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL) - -extern void *kmap_high(struct page *page); -extern void kunmap_high(struct page *page); - -static inline void *kmap(struct page *page) -{ - might_sleep(); - if (!PageHighMem(page)) - return page_address(page); - return kmap_high(page); -} - -static inline void kunmap(struct page *page) -{ - BUG_ON(in_interrupt()); - if (!PageHighMem(page)) - return; - kunmap_high(page); -} - -/* - * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap - * gives a more generic (and caching) interface. But kmap_atomic can - * be used in IRQ contexts, so in some (very limited) cases we need - * it. - */ -static inline void *kmap_atomic(struct page *page, enum km_type type) -{ - unsigned int idx; - unsigned long vaddr; - - /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ - pagefault_disable(); - if (!PageHighMem(page)) - return page_address(page); - - idx = type + KM_TYPE_NR*smp_processor_id(); - vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE; -#ifdef HIGHMEM_DEBUG - BUG_ON(!pte_none(*(kmap_pte+idx))); -#endif - set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot)); - flush_tlb_page(NULL, vaddr); - - return (void*) vaddr; -} - -static inline void kunmap_atomic(void *kvaddr, enum km_type type) -{ -#ifdef HIGHMEM_DEBUG - unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; - unsigned int idx = type + KM_TYPE_NR*smp_processor_id(); - - if (vaddr < KMAP_FIX_BEGIN) { // FIXME - pagefault_enable(); - return; - } - - BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE); - - /* - * force other mappings to Oops if they'll try to access - * this pte without first remap it - */ - pte_clear(&init_mm, vaddr, kmap_pte+idx); - flush_tlb_page(NULL, vaddr); -#endif - pagefault_enable(); -} - -static inline struct page *kmap_atomic_to_page(void *ptr) -{ - unsigned long idx, vaddr = (unsigned long) ptr; - - if (vaddr < KMAP_FIX_BEGIN) - return virt_to_page(ptr); - - idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT; - return pte_page(kmap_pte[idx]); -} - -#define flush_cache_kmaps() flush_cache_all() - -#endif /* __KERNEL__ */ - -#endif /* _ASM_HIGHMEM_H */ diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h deleted file mode 100644 index 1ad4eed07fbe..000000000000 --- a/include/asm-ppc/hydra.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions - * - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is based on the following documentation: - * - * Macintosh Technology in the Common Hardware Reference Platform - * Apple Computer, Inc. - * - * © Copyright 1995 Apple Computer, Inc. All rights reserved. - * - * It's available online from http://chrp.apple.com/MacTech.pdf. - * You can obtain paper copies of this book from computer bookstores or by - * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San - * Francisco, CA 94104. Reference ISBN 1-55860-393-X. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _ASMPPC_HYDRA_H -#define _ASMPPC_HYDRA_H - -#ifdef __KERNEL__ - -struct Hydra { - /* DBDMA Controller Register Space */ - char Pad1[0x30]; - u_int CachePD; - u_int IDs; - u_int Feature_Control; - char Pad2[0x7fc4]; - /* DBDMA Channel Register Space */ - char SCSI_DMA[0x100]; - char Pad3[0x300]; - char SCCA_Tx_DMA[0x100]; - char SCCA_Rx_DMA[0x100]; - char SCCB_Tx_DMA[0x100]; - char SCCB_Rx_DMA[0x100]; - char Pad4[0x7800]; - /* Device Register Space */ - char SCSI[0x1000]; - char ADB[0x1000]; - char SCC_Legacy[0x1000]; - char SCC[0x1000]; - char Pad9[0x2000]; - char VIA[0x2000]; - char Pad10[0x28000]; - char OpenPIC[0x40000]; -}; - -extern volatile struct Hydra __iomem *Hydra; - - - /* - * Feature Control Register - */ - -#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */ -#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */ -#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */ -#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */ -#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */ -#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */ -#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */ -#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */ -#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */ - - - /* - * OpenPIC Interrupt Sources - */ - -#define HYDRA_INT_SIO 0 -#define HYDRA_INT_SCSI_DMA 1 -#define HYDRA_INT_SCCA_TX_DMA 2 -#define HYDRA_INT_SCCA_RX_DMA 3 -#define HYDRA_INT_SCCB_TX_DMA 4 -#define HYDRA_INT_SCCB_RX_DMA 5 -#define HYDRA_INT_SCSI 6 -#define HYDRA_INT_SCCA 7 -#define HYDRA_INT_SCCB 8 -#define HYDRA_INT_VIA 9 -#define HYDRA_INT_ADB 10 -#define HYDRA_INT_ADB_NMI 11 -#define HYDRA_INT_EXT1 12 /* PCI IRQW */ -#define HYDRA_INT_EXT2 13 /* PCI IRQX */ -#define HYDRA_INT_EXT3 14 /* PCI IRQY */ -#define HYDRA_INT_EXT4 15 /* PCI IRQZ */ -#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */ -#define HYDRA_INT_EXT6 17 /* IDE Secondary */ -#define HYDRA_INT_EXT7 18 /* Power Off Request */ -#define HYDRA_INT_SPARE 19 - -extern int hydra_init(void); -extern void macio_adb_init(void); - -#endif /* __KERNEL__ */ - -#endif /* _ASMPPC_HYDRA_H */ diff --git a/include/asm-ppc/ibm403.h b/include/asm-ppc/ibm403.h deleted file mode 100644 index c9c5d539cfdb..000000000000 --- a/include/asm-ppc/ibm403.h +++ /dev/null @@ -1,478 +0,0 @@ -/* - * Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com> - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - - -#ifdef __KERNEL__ -#ifndef __ASM_IBM403_H__ -#define __ASM_IBM403_H__ - - -#if defined(CONFIG_403GCX) - -#define DCRN_BE_BASE 0x090 -#define DCRN_DMA0_BASE 0x0C0 -#define DCRN_DMA1_BASE 0x0C8 -#define DCRN_DMA2_BASE 0x0D0 -#define DCRN_DMA3_BASE 0x0D8 -#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ -#define DCRN_DMASR_BASE 0x0E0 - -#define DCRN_EXIER_BASE 0x042 -#define DCRN_EXISR_BASE 0x040 -#define DCRN_IOCR_BASE 0x0A0 - - -/* ------------------------------------------------------------------------- */ -#endif - - - -#ifdef DCRN_BE_BASE -#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ -#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register*/ -#endif -/* DCRN_BESR */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 - -#ifdef DCRN_CHCR_BASE -#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ -#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ -#endif -#define CHR1_CETE 0x00800000 /* CPU external timer enable */ -#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ - -#ifdef DCRN_CHPSR_BASE -#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ -#endif - -#ifdef DCRN_CIC_BASE -#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ -#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ -#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ -#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ -#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ -#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ -#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ -#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ -#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ -#endif - -#ifdef DCRN_CPMFR_BASE -#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ -#endif - -#ifndef CPM_AUD -#define CPM_AUD 0x00000000 -#endif -#ifndef CPM_BRG -#define CPM_BRG 0x00000000 -#endif -#ifndef CPM_CBS -#define CPM_CBS 0x00000000 -#endif -#ifndef CPM_CPU -#define CPM_CPU 0x00000000 -#endif -#ifndef CPM_DCP -#define CPM_DCP 0x00000000 -#endif -#ifndef CPM_DCRX -#define CPM_DCRX 0x00000000 -#endif -#ifndef CPM_DENC -#define CPM_DENC 0x00000000 -#endif -#ifndef CPM_DMA -#define CPM_DMA 0x00000000 -#endif -#ifndef CPM_DSCR -#define CPM_DSCR 0x00000000 -#endif -#ifndef CPM_EBC -#define CPM_EBC 0x00000000 -#endif -#ifndef CPM_EBIU -#define CPM_EBIU 0x00000000 -#endif -#ifndef CPM_EMAC_MM -#define CPM_EMAC_MM 0x00000000 -#endif -#ifndef CPM_EMAC_RM -#define CPM_EMAC_RM 0x00000000 -#endif -#ifndef CPM_EMAC_TM -#define CPM_EMAC_TM 0x00000000 -#endif -#ifndef CPM_GPIO0 -#define CPM_GPIO0 0x00000000 -#endif -#ifndef CPM_GPT -#define CPM_GPT 0x00000000 -#endif -#ifndef CPM_I1284 -#define CPM_I1284 0x00000000 -#endif -#ifndef CPM_IIC0 -#define CPM_IIC0 0x00000000 -#endif -#ifndef CPM_IIC1 -#define CPM_IIC1 0x00000000 -#endif -#ifndef CPM_MSI -#define CPM_MSI 0x00000000 -#endif -#ifndef CPM_PCI -#define CPM_PCI 0x00000000 -#endif -#ifndef CPM_PLB -#define CPM_PLB 0x00000000 -#endif -#ifndef CPM_SC0 -#define CPM_SC0 0x00000000 -#endif -#ifndef CPM_SC1 -#define CPM_SC1 0x00000000 -#endif -#ifndef CPM_SDRAM0 -#define CPM_SDRAM0 0x00000000 -#endif -#ifndef CPM_SDRAM1 -#define CPM_SDRAM1 0x00000000 -#endif -#ifndef CPM_TMRCLK -#define CPM_TMRCLK 0x00000000 -#endif -#ifndef CPM_UART0 -#define CPM_UART0 0x00000000 -#endif -#ifndef CPM_UART1 -#define CPM_UART1 0x00000000 -#endif -#ifndef CPM_UART2 -#define CPM_UART2 0x00000000 -#endif -#ifndef CPM_UIC -#define CPM_UIC 0x00000000 -#endif -#ifndef CPM_VID2 -#define CPM_VID2 0x00000000 -#endif -#ifndef CPM_XPT27 -#define CPM_XPT27 0x00000000 -#endif -#ifndef CPM_XPT54 -#define CPM_XPT54 0x00000000 -#endif - -#ifdef DCRN_CPMSR_BASE -#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ -#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ -#endif - -#ifdef DCRN_DCP0_BASE -#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) /* Decompression Controller Address */ -#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) /* Decompression Controller Data */ -#endif - -#ifdef DCRN_DCRX_BASE -#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ -#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ -#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ -#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ -#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ -#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ -#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ -#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ -#endif - -#ifdef DCRN_DMA0_BASE -#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */ -#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ -#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */ -#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */ -#endif - -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */ -#endif -#endif - -#ifdef DCRN_DMA1_BASE -#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control Register 1 */ -#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ -#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) /* DMA Destination Address Register 1 */ -#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ - -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) /* DMA Chained Count Register 1 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 1 */ -#endif -#endif - -#ifdef DCRN_DMA2_BASE -#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ -#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ -#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ -#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ -#endif -#endif - -#ifdef DCRN_DMA3_BASE -#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ -#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ -#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ -#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ -#endif -#endif - -#ifdef DCRN_DMASR_BASE -#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ -/* don't know if these two registers always exist if scatter/gather exists */ -#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ -#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ -#endif -#endif - -#ifdef DCRN_EBC_BASE -#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ -#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ -#endif - -#ifdef DCRN_EXIER_BASE -#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ -#endif - -#ifdef DCRN_EBIMC_BASE -#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ -#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ -#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ -#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ -#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ -#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ -#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ -#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ -#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */ -#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */ -#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */ -#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */ -#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */ -#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */ -#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */ -#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */ -#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */ -#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */ -#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */ -#endif - -#ifdef DCRN_EXISR_BASE -#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ -#endif -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ - -#ifdef DCRN_IOCR_BASE -#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ -#endif -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 - -#ifdef DCRN_MAL_BASE -#define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */ -#define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */ -#define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */ -#define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */ -#define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */ -#define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */ -#define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */ -#define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */ -#define DCRN_MALRXCARR (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */ -#define DCRN_MALRXCASR (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */ -#define DCRN_MALRXDEIR (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */ -#define DCRN_MALRXEOBISR (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status */ -#define DCRN_MALRXCTP0R (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP0R (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP1R (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */ -#define DCRN_MALRCBS0 (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */ -#endif -/* DCRN_MALCR */ -#define MALCR_MMSR 0x80000000/* MAL Software reset */ -#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ -#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ -#define MALCR_PLBP_3 0x00C00000 /* highest */ -#define MALCR_GA 0x00200000 /* Guarded Active Bit */ -#define MALCR_OA 0x00100000 /* Ordered Active Bit */ -#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ -#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ -#define MALCR_PLBLT_2 0x00020000 -#define MALCR_PLBLT_3 0x00010000 -#define MALCR_PLBLT_4 0x00008000 -#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ -#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ -#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ -#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ -#define MALCR_LEA 0x00000002 /* Locked Error Active */ -#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ -/* DCRN_MALESR */ -#define MALESR_EVB 0x80000000 /* Error Valid Bit */ -#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ -#define MALESR_DE 0x00100000 /* Descriptor Error */ -#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ -#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ -#define MALESR_OSE 0x00020000 /* OPB Slave Error */ -#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ -#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ -#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ -#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ -#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ -#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ -/* DCRN_MALIER */ -#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ -#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ -#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ -#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ -#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ -/* DCRN_MALTXEOBISR */ -#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ -#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ - -#ifdef DCRN_OCM0_BASE -#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ -#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ -#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ -#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ -#endif - -#ifdef DCRN_PLB0_BASE -#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) -#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) -/* doesn't exist on stb03xxx? */ -#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) -#endif - -#ifdef DCRN_PLB1_BASE -#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) -#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) -/* doesn't exist on stb03xxx? */ -#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) -#endif - -#ifdef DCRN_PLLMR_BASE -#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ -#endif - -#ifdef DCRN_POB0_BASE -#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) -#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) -#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) -#endif - -#ifdef DCRN_SCCR_BASE -#define DCRN_SCCR (DCRN_SCCR_BASE + 0x0) -#endif - -#ifdef DCRN_SDRAM0_BASE -#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */ -#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */ -#endif - -#ifdef DCRN_UIC0_BASE -#define DCRN_UIC0_SR (DCRN_UIC0_BASE + 0x0) -#define DCRN_UIC0_ER (DCRN_UIC0_BASE + 0x2) -#define DCRN_UIC0_CR (DCRN_UIC0_BASE + 0x3) -#define DCRN_UIC0_PR (DCRN_UIC0_BASE + 0x4) -#define DCRN_UIC0_TR (DCRN_UIC0_BASE + 0x5) -#define DCRN_UIC0_MSR (DCRN_UIC0_BASE + 0x6) -#define DCRN_UIC0_VR (DCRN_UIC0_BASE + 0x7) -#define DCRN_UIC0_VCR (DCRN_UIC0_BASE + 0x8) -#endif - -#ifdef DCRN_UIC1_BASE -#define DCRN_UIC1_SR (DCRN_UIC1_BASE + 0x0) -#define DCRN_UIC1_SRS (DCRN_UIC1_BASE + 0x1) -#define DCRN_UIC1_ER (DCRN_UIC1_BASE + 0x2) -#define DCRN_UIC1_CR (DCRN_UIC1_BASE + 0x3) -#define DCRN_UIC1_PR (DCRN_UIC1_BASE + 0x4) -#define DCRN_UIC1_TR (DCRN_UIC1_BASE + 0x5) -#define DCRN_UIC1_MSR (DCRN_UIC1_BASE + 0x6) -#define DCRN_UIC1_VR (DCRN_UIC1_BASE + 0x7) -#define DCRN_UIC1_VCR (DCRN_UIC1_BASE + 0x8) -#endif - -#ifdef DCRN_SDRAM0_BASE -#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ -#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ -#endif - -#ifdef DCRN_OCM0_BASE -#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ -#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ -#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ -#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ -#endif - -#endif /* __ASM_IBM403_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm405.h b/include/asm-ppc/ibm405.h deleted file mode 100644 index 4e5be9e2c153..000000000000 --- a/include/asm-ppc/ibm405.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Author: Armin Kuster <akuster@mvista.com> - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM405_H__ -#define __ASM_IBM405_H__ - -#ifdef DCRN_BE_BASE -#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ -#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ -#endif -/* DCRN_BESR */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 - -/* Clock and power management shifts for emacs */ -#define IBM_CPM_EMMII 0 /* Shift value for MII */ -#define IBM_CPM_EMRX 1 /* Shift value for recv */ -#define IBM_CPM_EMTX 2 /* Shift value for MAC */ - -#ifdef DCRN_CHCR_BASE -#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ -#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ -#endif -#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ - -#ifdef DCRN_CHPSR_BASE -#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ -#endif - -#ifdef DCRN_CPMFR_BASE -#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ -#endif - -#ifdef DCRN_CPMSR_BASE -#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ -#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ -#endif - -#ifdef DCRN_DCP0_BASE -/* Decompression Controller Address */ -#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) -/* Decompression Controller Data */ -#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) -#else -#define DCRN_DCP0_CFGADDR 0x0 -#define DCRN_DCP0_CFGDATA 0x0 -#endif - -#ifdef DCRN_DMA0_BASE -/* DMA Channel Control Register 0 */ -#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) -#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ -/* DMA Destination Address Register 0 */ -#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) -/* DMA Source Address Register 0 */ -#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) -#ifdef DCRNCAP_DMA_CC -/* DMA Chained Count Register 0 */ -#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) -#endif -#ifdef DCRNCAP_DMA_SG -/* DMA Scatter/Gather Descriptor Addr 0 */ -#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) -#endif -#endif - -#ifdef DCRN_DMA1_BASE -/* DMA Channel Control Register 1 */ -#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) -#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ -/* DMA Destination Address Register 1 */ -#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) -/* DMA Source Address Register 1 */ -#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ -#ifdef DCRNCAP_DMA_CC -/* DMA Chained Count Register 1 */ -#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) -#endif -#ifdef DCRNCAP_DMA_SG -/* DMA Scatter/Gather Descriptor Addr 1 */ -#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) -#endif -#endif - -#ifdef DCRN_DMA2_BASE -#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ -#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ -#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ -#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ -#endif -#endif - -#ifdef DCRN_DMA3_BASE -#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ -#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ -#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ -#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ -#ifdef DCRNCAP_DMA_CC -#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ -#endif -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ -#endif -#endif - -#ifdef DCRN_DMASR_BASE -#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ -#ifdef DCRNCAP_DMA_SG -#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ -/* don't know if these two registers always exist if scatter/gather exists */ -#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ -#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ -#endif -#endif - -#ifdef DCRN_EBC_BASE -#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ -#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ -#endif - -#ifdef DCRN_EXIER_BASE -#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ -#endif - -#ifdef DCRN_EXISR_BASE -#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ -#endif - -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ - -#ifdef DCRN_IOCR_BASE -#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ -#endif -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 - -#define DCRN_MALCR(base) (base + 0x0) /* MAL Configuration */ -#define DCRN_MALDBR(base) ((base) + 0x3) /* Debug Register */ -#define DCRN_MALESR(base) ((base) + 0x1) /* Error Status */ -#define DCRN_MALIER(base) ((base) + 0x2) /* Interrupt Enable */ -#define DCRN_MALTXCARR(base) ((base) + 0x5) /* TX Channed Active Reset Register */ -#define DCRN_MALTXCASR(base) ((base) + 0x4) /* TX Channel Active Set Register */ -#define DCRN_MALTXDEIR(base) ((base) + 0x7) /* Tx Descriptor Error Interrupt */ -#define DCRN_MALTXEOBISR(base) ((base) + 0x6) /* Tx End of Buffer Interrupt Status */ -#define DCRN_MALRXCARR(base) ((base) + 0x11) /* RX Channed Active Reset Register */ -#define DCRN_MALRXCASR(base) ((base) + 0x10) /* RX Channel Active Set Register */ -#define DCRN_MALRXDEIR(base) ((base) + 0x13) /* Rx Descriptor Error Interrupt */ -#define DCRN_MALRXEOBISR(base) ((base) + 0x12) /* Rx End of Buffer Interrupt Status */ -#define DCRN_MALRXCTP0R(base) ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */ -#define DCRN_MALRXCTP1R(base) ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */ -#define DCRN_MALTXCTP0R(base) ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP1R(base) ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */ -#define DCRN_MALTXCTP2R(base) ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */ -#define DCRN_MALTXCTP3R(base) ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */ -#define DCRN_MALRCBS0(base) ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */ -#define DCRN_MALRCBS1(base) ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */ - - /* DCRN_MALCR */ -#define MALCR_MMSR 0x80000000 /* MAL Software reset */ -#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ -#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ -#define MALCR_PLBP_3 0x00C00000 /* highest */ -#define MALCR_GA 0x00200000 /* Guarded Active Bit */ -#define MALCR_OA 0x00100000 /* Ordered Active Bit */ -#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ -#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ -#define MALCR_PLBLT_2 0x00020000 -#define MALCR_PLBLT_3 0x00010000 -#define MALCR_PLBLT_4 0x00008000 -#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ -#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ -#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ -#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ -#define MALCR_LEA 0x00000002 /* Locked Error Active */ -#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ -/* DCRN_MALESR */ -#define MALESR_EVB 0x80000000 /* Error Valid Bit */ -#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ -#define MALESR_DE 0x00100000 /* Descriptor Error */ -#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ -#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ -#define MALESR_OSE 0x00020000 /* OPB Slave Error */ -#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ -#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ -#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ -#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ -#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ -#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ -/* DCRN_MALIER */ -#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ -#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ -#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ -#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ -#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ -/* DCRN_MALTXEOBISR */ -#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ -#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ - -#ifdef DCRN_PLB0_BASE -#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) -#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) -/* doesn't exist on stb03xxx? */ -#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) -#endif - -#ifdef DCRN_PLB1_BASE -#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) -#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) -/* doesn't exist on stb03xxx? */ -#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) -#endif - -#ifdef DCRN_PLLMR_BASE -#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ -#endif - -#ifdef DCRN_POB0_BASE -#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) -#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) -#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) -#endif - -#define DCRN_UIC_SR(base) (base + 0x0) -#define DCRN_UIC_ER(base) (base + 0x2) -#define DCRN_UIC_CR(base) (base + 0x3) -#define DCRN_UIC_PR(base) (base + 0x4) -#define DCRN_UIC_TR(base) (base + 0x5) -#define DCRN_UIC_MSR(base) (base + 0x6) -#define DCRN_UIC_VR(base) (base + 0x7) -#define DCRN_UIC_VCR(base) (base + 0x8) - -#ifdef DCRN_SDRAM0_BASE -#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ -#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ -#endif - -#ifdef DCRN_OCM0_BASE -#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ -#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ -#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ -#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ -#endif - -#endif /* __ASM_IBM405_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h deleted file mode 100644 index 7818b54b6e37..000000000000 --- a/include/asm-ppc/ibm44x.h +++ /dev/null @@ -1,674 +0,0 @@ -/* - * include/asm-ppc/ibm44x.h - * - * PPC44x definitions - * - * Matt Porter <mporter@kernel.crashing.org> - * - * Copyright 2002-2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM44x_H__ -#define __ASM_IBM44x_H__ - - -#ifndef NR_BOARD_IRQS -#define NR_BOARD_IRQS 0 -#endif - -#define _IO_BASE isa_io_base -#define _ISA_MEM_BASE isa_mem_base -#define PCI_DRAM_OFFSET pci_dram_offset - -/* TLB entry offset/size used for pinning kernel lowmem */ -#define PPC44x_PIN_SHIFT 28 -#define PPC_PIN_SIZE (1 << PPC44x_PIN_SHIFT) - -/* Lowest TLB slot consumed by the default pinned TLBs */ -#define PPC44x_LOW_SLOT 63 - -/* - * Least significant 32-bits and extended real page number (ERPN) of - * UART0 physical address location for early serial text debug - */ -#if defined(CONFIG_440SP) -#define UART0_PHYS_ERPN 1 -#define UART0_PHYS_IO_BASE 0xf0000200 -#elif defined(CONFIG_440SPE) -#define UART0_PHYS_ERPN 4 -#define UART0_PHYS_IO_BASE 0xf0000200 -#elif defined(CONFIG_440EP) -#define UART0_PHYS_IO_BASE 0xe0000000 -#else -#define UART0_PHYS_ERPN 1 -#define UART0_PHYS_IO_BASE 0x40000200 -#endif - -/* - * XXX This 36-bit trap stuff will move somewhere in syslib/ - * when we rework/abstract the PPC44x PCI-X handling -mdp - */ - -/* - * Standard 4GB "page" definitions - */ -#if defined(CONFIG_440SP) -#define PPC44x_IO_PAGE 0x0000000100000000ULL -#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL -#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE -#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL -#elif defined(CONFIG_440SPE) -#define PPC44x_IO_PAGE 0x0000000400000000ULL -#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL -#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE -#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL -#elif defined(CONFIG_440EP) -#define PPC44x_IO_PAGE 0x0000000000000000ULL -#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL -#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE -#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL -#else -#define PPC44x_IO_PAGE 0x0000000100000000ULL -#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL -#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE -#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL -#endif - -/* - * 36-bit trap ranges - */ -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define PPC44x_IO_LO 0xf0000000UL -#define PPC44x_IO_HI 0xf0000fffUL -#define PPC44x_PCI0CFG_LO 0x0ec00000UL -#define PPC44x_PCI0CFG_HI 0x0ec00007UL -#define PPC44x_PCI1CFG_LO 0x1ec00000UL -#define PPC44x_PCI1CFG_HI 0x1ec00007UL -#define PPC44x_PCI2CFG_LO 0x2ec00000UL -#define PPC44x_PCI2CFG_HI 0x2ec00007UL -#define PPC44x_PCIMEM_LO 0x80000000UL -#define PPC44x_PCIMEM_HI 0xdfffffffUL -#elif defined(CONFIG_440EP) -#define PPC44x_IO_LO 0xef500000UL -#define PPC44x_IO_HI 0xefffffffUL -#define PPC44x_PCI0CFG_LO 0xeec00000UL -#define PPC44x_PCI0CFG_HI 0xeecfffffUL -#define PPC44x_PCIMEM_LO 0xa0000000UL -#define PPC44x_PCIMEM_HI 0xdfffffffUL -#else -#define PPC44x_IO_LO 0x40000000UL -#define PPC44x_IO_HI 0x40000fffUL -#define PPC44x_PCI0CFG_LO 0x0ec00000UL -#define PPC44x_PCI0CFG_HI 0x0ec00007UL -#define PPC44x_PCIMEM_LO 0x80002000UL -#define PPC44x_PCIMEM_HI 0xffffffffUL -#endif - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -#ifndef __ASSEMBLY__ - -/* - * DCRN definitions - */ - - -/* CPRs (440GX and 440SP/440SPe) */ -#define DCRN_CPR_CONFIG_ADDR 0xc -#define DCRN_CPR_CONFIG_DATA 0xd - -#define DCRN_CPR_CLKUPD 0x0020 -#define DCRN_CPR_PLLC 0x0040 -#define DCRN_CPR_PLLD 0x0060 -#define DCRN_CPR_PRIMAD 0x0080 -#define DCRN_CPR_PRIMBD 0x00a0 -#define DCRN_CPR_OPBD 0x00c0 -#define DCRN_CPR_PERD 0x00e0 -#define DCRN_CPR_MALD 0x0100 - -/* CPRs read/write helper macros */ -#define CPR_READ(offset) ({\ - mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ - mfdcr(DCRN_CPR_CONFIG_DATA);}) -#define CPR_WRITE(offset, data) ({\ - mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ - mtdcr(DCRN_CPR_CONFIG_DATA, data);}) - -/* SDRs (440GX and 440SP/440SPe) */ -#define DCRN_SDR_CONFIG_ADDR 0xe -#define DCRN_SDR_CONFIG_DATA 0xf -#define DCRN_SDR_PFC0 0x4100 -#define DCRN_SDR_PFC1 0x4101 -#define DCRN_SDR_PFC1_EPS 0x1c00000 -#define DCRN_SDR_PFC1_EPS_SHIFT 22 -#define DCRN_SDR_PFC1_RMII 0x02000000 -#define DCRN_SDR_MFR 0x4300 -#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ -#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ -#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ -#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */ -#define DCRN_SDR_MFR_T0TXFL 0x00080000 -#define DCRN_SDR_MFR_T0TXFH 0x00040000 -#define DCRN_SDR_MFR_T1TXFL 0x00020000 -#define DCRN_SDR_MFR_T1TXFH 0x00010000 -#define DCRN_SDR_MFR_E0TXFL 0x00008000 -#define DCRN_SDR_MFR_E0TXFH 0x00004000 -#define DCRN_SDR_MFR_E0RXFL 0x00002000 -#define DCRN_SDR_MFR_E0RXFH 0x00001000 -#define DCRN_SDR_MFR_E1TXFL 0x00000800 -#define DCRN_SDR_MFR_E1TXFH 0x00000400 -#define DCRN_SDR_MFR_E1RXFL 0x00000200 -#define DCRN_SDR_MFR_E1RXFH 0x00000100 -#define DCRN_SDR_MFR_E2TXFL 0x00000080 -#define DCRN_SDR_MFR_E2TXFH 0x00000040 -#define DCRN_SDR_MFR_E2RXFL 0x00000020 -#define DCRN_SDR_MFR_E2RXFH 0x00000010 -#define DCRN_SDR_MFR_E3TXFL 0x00000008 -#define DCRN_SDR_MFR_E3TXFH 0x00000004 -#define DCRN_SDR_MFR_E3RXFL 0x00000002 -#define DCRN_SDR_MFR_E3RXFH 0x00000001 -#define DCRN_SDR_UART0 0x0120 -#define DCRN_SDR_UART1 0x0121 - -#ifdef CONFIG_440EP -#define DCRN_SDR_UART2 0x0122 -#define DCRN_SDR_UART3 0x0123 -#define DCRN_SDR_CUST0 0x4000 -#endif - -/* SDR read/write helper macros */ -#define SDR_READ(offset) ({\ - mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ - mfdcr(DCRN_SDR_CONFIG_DATA);}) -#define SDR_WRITE(offset, data) ({\ - mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ - mtdcr(DCRN_SDR_CONFIG_DATA,data);}) - -/* DMA (excluding 440SP/440SPe) */ -#define DCRN_DMA0_BASE 0x100 -#define DCRN_DMA1_BASE 0x108 -#define DCRN_DMA2_BASE 0x110 -#define DCRN_DMA3_BASE 0x118 -#define DCRN_DMASR_BASE 0x120 -#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ -#define DCRN_MAL_BASE 0x180 - -#ifdef CONFIG_440EP -#define DCRN_DMA2P40_BASE 0x300 -#define DCRN_DMA2P41_BASE 0x308 -#define DCRN_DMA2P42_BASE 0x310 -#define DCRN_DMA2P43_BASE 0x318 -#define DCRN_DMA2P4SR_BASE 0x320 -#endif - -/* UIC */ -#define DCRN_UIC0_BASE 0xc0 -#define DCRN_UIC1_BASE 0xd0 -#define UIC0 DCRN_UIC0_BASE -#define UIC1 DCRN_UIC1_BASE - -#ifdef CONFIG_440SPE -#define DCRN_UIC2_BASE 0xe0 -#define DCRN_UIC3_BASE 0xf0 -#define UIC2 DCRN_UIC2_BASE -#define UIC3 DCRN_UIC3_BASE -#else -#define DCRN_UIC2_BASE 0x210 -#define DCRN_UICB_BASE 0x200 -#define UIC2 DCRN_UIC2_BASE -#define UICB DCRN_UICB_BASE -#endif - -#define DCRN_UIC_SR(base) (base + 0x0) -#define DCRN_UIC_ER(base) (base + 0x2) -#define DCRN_UIC_CR(base) (base + 0x3) -#define DCRN_UIC_PR(base) (base + 0x4) -#define DCRN_UIC_TR(base) (base + 0x5) -#define DCRN_UIC_MSR(base) (base + 0x6) -#define DCRN_UIC_VR(base) (base + 0x7) -#define DCRN_UIC_VCR(base) (base + 0x8) - -#define UIC0_UIC1NC 0x00000002 - -#ifdef CONFIG_440SPE -#define UIC0_UIC1NC 0x00000002 -#define UIC0_UIC2NC 0x00200000 -#define UIC0_UIC3NC 0x00008000 -#endif - -#define UICB_UIC0NC 0x40000000 -#define UICB_UIC1NC 0x10000000 -#define UICB_UIC2NC 0x04000000 - -/* 440 MAL DCRs */ -#define DCRN_MALCR(base) (base + 0x0) /* Configuration */ -#define DCRN_MALESR(base) (base + 0x1) /* Error Status */ -#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */ -#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */ -#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */ -#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */ -#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */ -#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */ -#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */ -#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */ -#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */ -#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */ -#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */ -#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */ -#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */ -#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */ -#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */ -#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */ - -/* Compatibility DCRN's */ -#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */ -#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */ -#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */ -#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */ -#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */ -#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */ -#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */ -#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */ - -#define MALCR_MMSR 0x80000000 /* MAL Software reset */ -#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ -#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ -#define MALCR_PLBP_3 0x00C00000 /* highest */ -#define MALCR_GA 0x00200000 /* Guarded Active Bit */ -#define MALCR_OA 0x00100000 /* Ordered Active Bit */ -#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ -#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ -#define MALCR_PLBLT_2 0x00020000 -#define MALCR_PLBLT_3 0x00010000 -#define MALCR_PLBLT_4 0x00008000 -#ifdef CONFIG_440GP -#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */ -#else -#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */ -#endif -#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ -#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ -#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ -#define MALCR_LEA 0x00000002 /* Locked Error Active */ -#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ -/* DCRN_MALESR */ -#define MALESR_EVB 0x80000000 /* Error Valid Bit */ -#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ -#define MALESR_DE 0x00100000 /* Descriptor Error */ -#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ -#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ -#define MALESR_OSE 0x00020000 /* OPB Slave Error */ -#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ -#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ -#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ -#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ -#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ -#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ -/* DCRN_MALIER */ -#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ -#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ -#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ -#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ -#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ -/* DCRN_MALTXEOBISR */ -#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ -#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -/* 440SP/440SPe PLB Arbiter DCRs */ -#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ -#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ - -#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */ -#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */ -#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */ -#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */ -#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */ - -#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */ -#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */ -#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */ -#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */ -#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */ -#else -/* 440GP/GX PLB Arbiter DCRs */ -#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ -#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ -#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ -#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ -#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ -#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ -#endif - -/* 440GP/GX PLB to OPB bridge DCRs */ -#define DCRN_POB0_BESR0 0x090 -#define DCRN_POB0_BESR1 0x094 -#define DCRN_POB0_BEARL 0x092 -#define DCRN_POB0_BEARH 0x093 - -/* 440GP/GX OPB to PLB bridge DCRs */ -#define DCRN_OPB0_BSTAT 0x0a9 -#define DCRN_OPB0_BEARL 0x0aa -#define DCRN_OPB0_BEARH 0x0ab - -/* 440GP Clock, PM, chip control */ -#define DCRN_CPC0_SR 0x0b0 -#define DCRN_CPC0_ER 0x0b1 -#define DCRN_CPC0_FR 0x0b2 -#define DCRN_CPC0_SYS0 0x0e0 -#define DCRN_CPC0_SYS1 0x0e1 -#define DCRN_CPC0_CUST0 0x0e2 -#define DCRN_CPC0_CUST1 0x0e3 -#define DCRN_CPC0_STRP0 0x0e4 -#define DCRN_CPC0_STRP1 0x0e5 -#define DCRN_CPC0_STRP2 0x0e6 -#define DCRN_CPC0_STRP3 0x0e7 -#define DCRN_CPC0_GPIO 0x0e8 -#define DCRN_CPC0_PLB 0x0e9 -#define DCRN_CPC0_CR1 0x0ea -#define DCRN_CPC0_CR0 0x0eb -#define DCRN_CPC0_MIRQ0 0x0ec -#define DCRN_CPC0_MIRQ1 0x0ed -#define DCRN_CPC0_JTAGID 0x0ef - -/* 440GP DMA controller DCRs */ -#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */ -#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */ -#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */ -#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */ -#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */ -#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */ -#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */ -#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */ - -#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */ -#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */ -#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */ -#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */ -#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */ -#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */ -#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */ -#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */ - -#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */ -#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */ -#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */ -#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */ -#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */ -#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */ -#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */ -#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */ - -#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */ -#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */ -#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */ -#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */ -#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */ -#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */ -#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */ -#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */ - -#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ -#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ -#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ -#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ - -/* 440GP/440GX SDRAM controller DCRs */ -#define DCRN_SDRAM0_CFGADDR 0x010 -#define DCRN_SDRAM0_CFGDATA 0x011 - -#define SDRAM0_B0CR 0x40 -#define SDRAM0_B1CR 0x44 -#define SDRAM0_B2CR 0x48 -#define SDRAM0_B3CR 0x4c - -#define SDRAM_CONFIG_BANK_ENABLE 0x00000001 -#define SDRAM_CONFIG_SIZE_MASK 0x000e0000 -#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17) -#define SDRAM_CONFIG_SIZE_8M 0x00000001 -#define SDRAM_CONFIG_SIZE_16M 0x00000002 -#define SDRAM_CONFIG_SIZE_32M 0x00000003 -#define SDRAM_CONFIG_SIZE_64M 0x00000004 -#define SDRAM_CONFIG_SIZE_128M 0x00000005 -#define SDRAM_CONFIG_SIZE_256M 0x00000006 -#define SDRAM_CONFIG_SIZE_512M 0x00000007 -#define PPC44x_MEM_SIZE_8M 0x00800000 -#define PPC44x_MEM_SIZE_16M 0x01000000 -#define PPC44x_MEM_SIZE_32M 0x02000000 -#define PPC44x_MEM_SIZE_64M 0x04000000 -#define PPC44x_MEM_SIZE_128M 0x08000000 -#define PPC44x_MEM_SIZE_256M 0x10000000 -#define PPC44x_MEM_SIZE_512M 0x20000000 -#define PPC44x_MEM_SIZE_1G 0x40000000 -#define PPC44x_MEM_SIZE_2G 0x80000000 - -/* 440SP/440SPe memory controller DCRs */ -#define DCRN_MQ0_BS0BAS 0x40 -#if defined(CONFIG_440SP) -#define MQ0_NUM_BANKS 2 -#elif defined(CONFIG_440SPE) -#define MQ0_NUM_BANKS 4 -#endif - -#define MQ0_CONFIG_SIZE_MASK 0x0000fff0 -#define MQ0_CONFIG_SIZE_8M 0x0000ffc0 -#define MQ0_CONFIG_SIZE_16M 0x0000ff80 -#define MQ0_CONFIG_SIZE_32M 0x0000ff00 -#define MQ0_CONFIG_SIZE_64M 0x0000fe00 -#define MQ0_CONFIG_SIZE_128M 0x0000fc00 -#define MQ0_CONFIG_SIZE_256M 0x0000f800 -#define MQ0_CONFIG_SIZE_512M 0x0000f000 -#define MQ0_CONFIG_SIZE_1G 0x0000e000 -#define MQ0_CONFIG_SIZE_2G 0x0000c000 -#define MQ0_CONFIG_SIZE_4G 0x00008000 - -/* Internal SRAM Controller 440GX/440SP/440SPe */ -#define DCRN_SRAM0_BASE 0x000 - -#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) -#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021) -#define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022) -#define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023) -#define SRAM_SBCR_BAS0 0x80000000 -#define SRAM_SBCR_BAS1 0x80010000 -#define SRAM_SBCR_BAS2 0x80020000 -#define SRAM_SBCR_BAS3 0x80030000 -#define SRAM_SBCR_BU_MASK 0x00000180 -#define SRAM_SBCR_BS_64KB 0x00000800 -#define SRAM_SBCR_BU_RO 0x00000080 -#define SRAM_SBCR_BU_RW 0x00000180 -#define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024) -#define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025) -#define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026) -#define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027) -#define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028) -#define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029) -#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) -#define SRAM_DPC_ENABLE 0x80000000 - -/* L2 Cache Controller 440GX/440SP/440SPe */ -#define DCRN_L2C0_CFG 0x030 -#define L2C_CFG_L2M 0x80000000 -#define L2C_CFG_ICU 0x40000000 -#define L2C_CFG_DCU 0x20000000 -#define L2C_CFG_DCW_MASK 0x1e000000 -#define L2C_CFG_TPC 0x01000000 -#define L2C_CFG_CPC 0x00800000 -#define L2C_CFG_FRAN 0x00200000 -#define L2C_CFG_SS_MASK 0x00180000 -#define L2C_CFG_SS_256 0x00000000 -#define L2C_CFG_CPIM 0x00040000 -#define L2C_CFG_TPIM 0x00020000 -#define L2C_CFG_LIM 0x00010000 -#define L2C_CFG_PMUX_MASK 0x00007000 -#define L2C_CFG_PMUX_SNP 0x00000000 -#define L2C_CFG_PMUX_IF 0x00001000 -#define L2C_CFG_PMUX_DF 0x00002000 -#define L2C_CFG_PMUX_DS 0x00003000 -#define L2C_CFG_PMIM 0x00000800 -#define L2C_CFG_TPEI 0x00000400 -#define L2C_CFG_CPEI 0x00000200 -#define L2C_CFG_NAM 0x00000100 -#define L2C_CFG_SMCM 0x00000080 -#define L2C_CFG_NBRM 0x00000040 -#define DCRN_L2C0_CMD 0x031 -#define L2C_CMD_CLR 0x80000000 -#define L2C_CMD_DIAG 0x40000000 -#define L2C_CMD_INV 0x20000000 -#define L2C_CMD_CCP 0x10000000 -#define L2C_CMD_CTE 0x08000000 -#define L2C_CMD_STRC 0x04000000 -#define L2C_CMD_STPC 0x02000000 -#define L2C_CMD_RPMC 0x01000000 -#define L2C_CMD_HCC 0x00800000 -#define DCRN_L2C0_ADDR 0x032 -#define DCRN_L2C0_DATA 0x033 -#define DCRN_L2C0_SR 0x034 -#define L2C_SR_CC 0x80000000 -#define L2C_SR_CPE 0x40000000 -#define L2C_SR_TPE 0x20000000 -#define L2C_SR_LRU 0x10000000 -#define L2C_SR_PCS 0x08000000 -#define DCRN_L2C0_REVID 0x035 -#define DCRN_L2C0_SNP0 0x036 -#define DCRN_L2C0_SNP1 0x037 -#define L2C_SNP_BA_MASK 0xffff0000 -#define L2C_SNP_SSR_MASK 0x0000f000 -#define L2C_SNP_SSR_32G 0x0000f000 -#define L2C_SNP_ESR 0x00000800 - -/* - * PCI-X definitions - */ -#define PCIX0_CFGA 0x0ec00000UL -#define PCIX1_CFGA 0x1ec00000UL -#define PCIX2_CFGA 0x2ec00000UL -#define PCIX0_CFGD 0x0ec00004UL -#define PCIX1_CFGD 0x1ec00004UL -#define PCIX2_CFGD 0x2ec00004UL - -#define PCIX0_IO_BASE 0x0000000908000000ULL -#define PCIX1_IO_BASE 0x0000000908000000ULL -#define PCIX2_IO_BASE 0x0000000908000000ULL -#define PCIX_IO_SIZE 0x00010000 - -#ifdef CONFIG_440SP -#define PCIX0_REG_BASE 0x000000090ec80000ULL -#else -#define PCIX0_REG_BASE 0x000000020ec80000ULL -#endif -#define PCIX_REG_OFFSET 0x10000000 -#define PCIX_REG_SIZE 0x200 - -#define PCIX0_VENDID 0x000 -#define PCIX0_DEVID 0x002 -#define PCIX0_COMMAND 0x004 -#define PCIX0_STATUS 0x006 -#define PCIX0_REVID 0x008 -#define PCIX0_CLS 0x009 -#define PCIX0_CACHELS 0x00c -#define PCIX0_LATTIM 0x00d -#define PCIX0_HDTYPE 0x00e -#define PCIX0_BIST 0x00f -#define PCIX0_BAR0L 0x010 -#define PCIX0_BAR0H 0x014 -#define PCIX0_BAR1 0x018 -#define PCIX0_BAR2L 0x01c -#define PCIX0_BAR2H 0x020 -#define PCIX0_BAR3 0x024 -#define PCIX0_CISPTR 0x028 -#define PCIX0_SBSYSVID 0x02c -#define PCIX0_SBSYSID 0x02e -#define PCIX0_EROMBA 0x030 -#define PCIX0_CAP 0x034 -#define PCIX0_RES0 0x035 -#define PCIX0_RES1 0x036 -#define PCIX0_RES2 0x038 -#define PCIX0_INTLN 0x03c -#define PCIX0_INTPN 0x03d -#define PCIX0_MINGNT 0x03e -#define PCIX0_MAXLTNCY 0x03f -#define PCIX0_BRDGOPT1 0x040 -#define PCIX0_BRDGOPT2 0x044 -#define PCIX0_ERREN 0x050 -#define PCIX0_ERRSTS 0x054 -#define PCIX0_PLBBESR 0x058 -#define PCIX0_PLBBEARL 0x05c -#define PCIX0_PLBBEARH 0x060 -#define PCIX0_POM0LAL 0x068 -#define PCIX0_POM0LAH 0x06c -#define PCIX0_POM0SA 0x070 -#define PCIX0_POM0PCIAL 0x074 -#define PCIX0_POM0PCIAH 0x078 -#define PCIX0_POM1LAL 0x07c -#define PCIX0_POM1LAH 0x080 -#define PCIX0_POM1SA 0x084 -#define PCIX0_POM1PCIAL 0x088 -#define PCIX0_POM1PCIAH 0x08c -#define PCIX0_POM2SA 0x090 -#define PCIX0_PIM0SAL 0x098 -#define PCIX0_PIM0SA PCIX0_PIM0SAL -#define PCIX0_PIM0LAL 0x09c -#define PCIX0_PIM0LAH 0x0a0 -#define PCIX0_PIM1SA 0x0a4 -#define PCIX0_PIM1LAL 0x0a8 -#define PCIX0_PIM1LAH 0x0ac -#define PCIX0_PIM2SAL 0x0b0 -#define PCIX0_PIM2SA PCIX0_PIM2SAL -#define PCIX0_PIM2LAL 0x0b4 -#define PCIX0_PIM2LAH 0x0b8 -#define PCIX0_OMCAPID 0x0c0 -#define PCIX0_OMNIPTR 0x0c1 -#define PCIX0_OMMC 0x0c2 -#define PCIX0_OMMA 0x0c4 -#define PCIX0_OMMUA 0x0c8 -#define PCIX0_OMMDATA 0x0cc -#define PCIX0_OMMEOI 0x0ce -#define PCIX0_PMCAPID 0x0d0 -#define PCIX0_PMNIPTR 0x0d1 -#define PCIX0_PMC 0x0d2 -#define PCIX0_PMCSR 0x0d4 -#define PCIX0_PMCSRBSE 0x0d6 -#define PCIX0_PMDATA 0x0d7 -#define PCIX0_PMSCRR 0x0d8 -#define PCIX0_CAPID 0x0dc -#define PCIX0_NIPTR 0x0dd -#define PCIX0_CMD 0x0de -#define PCIX0_STS 0x0e0 -#define PCIX0_IDR 0x0e4 -#define PCIX0_CID 0x0e8 -#define PCIX0_RID 0x0ec -#define PCIX0_PIM0SAH 0x0f8 -#define PCIX0_PIM2SAH 0x0fc -#define PCIX0_MSGIL 0x100 -#define PCIX0_MSGIH 0x104 -#define PCIX0_MSGOL 0x108 -#define PCIX0_MSGOH 0x10c -#define PCIX0_IM 0x1f8 - -#define IIC_OWN 0x55 -#define IIC_CLOCK 50 - -#undef NR_UICS -#if defined(CONFIG_440GX) -#define NR_UICS 3 -#elif defined(CONFIG_440SPE) -#define NR_UICS 4 -#else -#define NR_UICS 2 -#endif - -#include <asm/ibm4xx.h> - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_IBM44x_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h deleted file mode 100644 index ed6891af05d3..000000000000 --- a/include/asm-ppc/ibm4xx.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * - * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> - * - * Module name: ibm4xx.h - * - * Description: - * A generic include file which pulls in appropriate include files - * for specific board types based on configuration settings. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM4XX_H__ -#define __ASM_IBM4XX_H__ - -#include <asm/types.h> -#include <asm/dcr.h> - -#ifdef CONFIG_40x - -#if defined(CONFIG_BUBINGA) -#include <platforms/4xx/bubinga.h> -#endif - -#if defined(CONFIG_CPCI405) -#include <platforms/4xx/cpci405.h> -#endif - -#if defined(CONFIG_EP405) -#include <platforms/4xx/ep405.h> -#endif - -#if defined(CONFIG_REDWOOD_5) -#include <platforms/4xx/redwood5.h> -#endif - -#if defined(CONFIG_REDWOOD_6) -#include <platforms/4xx/redwood6.h> -#endif - -#if defined(CONFIG_SYCAMORE) -#include <platforms/4xx/sycamore.h> -#endif - -#if defined(CONFIG_WALNUT) -#include <platforms/4xx/walnut.h> -#endif - -#if defined(CONFIG_XILINX_VIRTEX) -#include <platforms/4xx/virtex.h> -#endif - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_40x -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern bd_t __res; -#endif - -void ppc4xx_setup_arch(void); -void ppc4xx_map_io(void); -void ppc4xx_init_IRQ(void); -void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7); -#endif - -#ifndef PPC4xx_MACHINE_NAME -#define PPC4xx_MACHINE_NAME "Unidentified 4xx class" -#endif - - -/* IO_BASE is for PCI I/O. - * ISA not supported, just here to resolve copilation. - */ - -#ifndef _IO_BASE -#define _IO_BASE 0xe8000000 /* The PCI address window */ -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#endif - -#elif defined(CONFIG_44x) - -#if defined(CONFIG_BAMBOO) -#include <platforms/4xx/bamboo.h> -#endif - -#if defined(CONFIG_EBONY) -#include <platforms/4xx/ebony.h> -#endif - -#if defined(CONFIG_LUAN) -#include <platforms/4xx/luan.h> -#endif - -#if defined(CONFIG_YUCCA) -#include <platforms/4xx/yucca.h> -#endif - -#if defined(CONFIG_OCOTEA) -#include <platforms/4xx/ocotea.h> -#endif - -#if defined(CONFIG_TAISHAN) -#include <platforms/4xx/taishan.h> -#endif - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_40x -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern bd_t __res; -#endif -#endif -#endif /* CONFIG_40x */ - -#endif /* __ASM_IBM4XX_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h deleted file mode 100644 index ddce616f765a..000000000000 --- a/include/asm-ppc/ibm_ocp.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * ibm_ocp.h - * - * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) - * Mipsys - France - * - * Derived from work (c) Armin Kuster akuster@pacbell.net - * - * Additional support and port to 2.6 LDM/sysfs by - * Matt Porter <mporter@kernel.crashing.org> - * Copyright 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#ifdef __KERNEL__ -#ifndef __IBM_OCP_H__ -#define __IBM_OCP_H__ - -#include <asm/types.h> - -/* - * IBM 4xx OCP system information - */ -struct ocp_sys_info_data { - int opb_bus_freq; /* OPB Bus Frequency (Hz) */ - int ebc_bus_freq; /* EBC Bus Frequency (Hz) */ -}; - -extern struct ocp_sys_info_data ocp_sys_info; - -/* - * EMAC additional data and sysfs support - * - * Note about mdio_idx: When you have a zmii, it's usually - * not necessary, it covers the case of the 405EP which has - * the MDIO lines on EMAC0 only - * - * Note about phy_map: Per EMAC map of PHY ids which should - * be probed by emac_probe. Different EMACs can have - * overlapping maps. - * - * Note, this map uses inverse logic for bits: - * 0 - id should be probed - * 1 - id should be ignored - * - * Default value of 0x00000000 - will result in usual - * auto-detection logic. - * - */ - -struct ocp_func_emac_data { - int rgmii_idx; /* RGMII device index or -1 */ - int rgmii_mux; /* RGMII input of this EMAC */ - int zmii_idx; /* ZMII device index or -1 */ - int zmii_mux; /* ZMII input of this EMAC */ - int mal_idx; /* MAL device index */ - int mal_rx_chan; /* MAL rx channel number */ - int mal_tx_chan; /* MAL tx channel number */ - int wol_irq; /* WOL interrupt */ - int mdio_idx; /* EMAC idx of MDIO master or -1 */ - int tah_idx; /* TAH device index or -1 */ - int phy_mode; /* PHY type or configurable mode */ - u8 mac_addr[6]; /* EMAC mac address */ - u32 phy_map; /* EMAC phy map */ - u32 phy_feat_exc; /* Excluded PHY features */ -}; - -/* Sysfs support */ -#define OCP_SYSFS_EMAC_DATA() \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \ -OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_feat_exc)\ - \ -void ocp_show_emac_data(struct device *dev) \ -{ \ - device_create_file(dev, &dev_attr_emac_rgmii_idx); \ - device_create_file(dev, &dev_attr_emac_rgmii_mux); \ - device_create_file(dev, &dev_attr_emac_zmii_idx); \ - device_create_file(dev, &dev_attr_emac_zmii_mux); \ - device_create_file(dev, &dev_attr_emac_mal_idx); \ - device_create_file(dev, &dev_attr_emac_mal_rx_chan); \ - device_create_file(dev, &dev_attr_emac_mal_tx_chan); \ - device_create_file(dev, &dev_attr_emac_wol_irq); \ - device_create_file(dev, &dev_attr_emac_mdio_idx); \ - device_create_file(dev, &dev_attr_emac_tah_idx); \ - device_create_file(dev, &dev_attr_emac_phy_mode); \ - device_create_file(dev, &dev_attr_emac_phy_map); \ - device_create_file(dev, &dev_attr_emac_phy_feat_exc); \ -} - -/* - * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY) - */ -#define PHY_MODE_NA 0 -#define PHY_MODE_MII 1 -#define PHY_MODE_RMII 2 -#define PHY_MODE_SMII 3 -#define PHY_MODE_RGMII 4 -#define PHY_MODE_TBI 5 -#define PHY_MODE_GMII 6 -#define PHY_MODE_RTBI 7 -#define PHY_MODE_SGMII 8 - -#ifdef CONFIG_40x -/* - * Helper function to copy MAC addresses from the bd_t to OCP EMAC - * additions. - * - * The range of EMAC indices (inclusive) to be copied are the arguments. - */ -static inline void ibm_ocp_set_emac(int start, int end) -{ - int i; - struct ocp_def *def; - - /* Copy MAC addresses to EMAC additions */ - for (i=start; i<=end; i++) { - def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); - if (i == 0) - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - __res.bi_enetaddr, 6); -#if defined(CONFIG_405EP) || defined(CONFIG_44x) - else if (i == 1) - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - __res.bi_enet1addr, 6); -#endif -#if defined(CONFIG_440GX) - else if (i == 2) - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - __res.bi_enet2addr, 6); - else if (i == 3) - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - __res.bi_enet3addr, 6); -#endif - } -} -#endif - -/* - * MAL additional data and sysfs support - */ -struct ocp_func_mal_data { - int num_tx_chans; /* Number of TX channels */ - int num_rx_chans; /* Number of RX channels */ - int txeob_irq; /* TX End Of Buffer IRQ */ - int rxeob_irq; /* RX End Of Buffer IRQ */ - int txde_irq; /* TX Descriptor Error IRQ */ - int rxde_irq; /* RX Descriptor Error IRQ */ - int serr_irq; /* MAL System Error IRQ */ - int dcr_base; /* MALx_CFG DCR number */ -}; - -#define OCP_SYSFS_MAL_DATA() \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \ -OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \ - \ -void ocp_show_mal_data(struct device *dev) \ -{ \ - device_create_file(dev, &dev_attr_mal_num_tx_chans); \ - device_create_file(dev, &dev_attr_mal_num_rx_chans); \ - device_create_file(dev, &dev_attr_mal_txeob_irq); \ - device_create_file(dev, &dev_attr_mal_rxeob_irq); \ - device_create_file(dev, &dev_attr_mal_txde_irq); \ - device_create_file(dev, &dev_attr_mal_rxde_irq); \ - device_create_file(dev, &dev_attr_mal_serr_irq); \ - device_create_file(dev, &dev_attr_mal_dcr_base); \ -} - -/* - * IIC additional data and sysfs support - */ -struct ocp_func_iic_data { - int fast_mode; /* IIC fast mode enabled */ -}; - -#define OCP_SYSFS_IIC_DATA() \ -OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \ - \ -void ocp_show_iic_data(struct device *dev) \ -{ \ - device_create_file(dev, &dev_attr_iic_fast_mode); \ -} -#endif /* __IBM_OCP_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm_ocp_pci.h b/include/asm-ppc/ibm_ocp_pci.h deleted file mode 100644 index a81ab6144358..000000000000 --- a/include/asm-ppc/ibm_ocp_pci.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Author: Armin Kuster <akuster@mvista.com> - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IBM_OCP_PCI_H__ -#define __ASM_IBM_OCP_PCI_H__ - -/* PCI 32 */ - -struct pmm_regs { - u32 la; - u32 ma; - u32 pcila; - u32 pciha; -}; - -typedef struct pcil0_regs { - struct pmm_regs pmm[3]; - u32 ptm1ms; - u32 ptm1la; - u32 ptm2ms; - u32 ptm2la; -} pci0_t; - -#endif /* __ASM_IBM_OCP_PCI_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/immap_cpm2.h b/include/asm-ppc/immap_cpm2.h deleted file mode 100644 index 3c23d9cb47a6..000000000000 --- a/include/asm-ppc/immap_cpm2.h +++ /dev/null @@ -1,648 +0,0 @@ -/* - * CPM2 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * The Internal Memory Map for devices with CPM2 on them. This - * is the superset of all CPM2 devices (8260, 8266, 8280, 8272, - * 8560). - */ -#ifdef __KERNEL__ -#ifndef __IMMAP_CPM2__ -#define __IMMAP_CPM2__ - -/* System configuration registers. -*/ -typedef struct sys_82xx_conf { - u32 sc_siumcr; - u32 sc_sypcr; - u8 res1[6]; - u16 sc_swsr; - u8 res2[20]; - u32 sc_bcr; - u8 sc_ppc_acr; - u8 res3[3]; - u32 sc_ppc_alrh; - u32 sc_ppc_alrl; - u8 sc_lcl_acr; - u8 res4[3]; - u32 sc_lcl_alrh; - u32 sc_lcl_alrl; - u32 sc_tescr1; - u32 sc_tescr2; - u32 sc_ltescr1; - u32 sc_ltescr2; - u32 sc_pdtea; - u8 sc_pdtem; - u8 res5[3]; - u32 sc_ldtea; - u8 sc_ldtem; - u8 res6[163]; -} sysconf_82xx_cpm2_t; - -typedef struct sys_85xx_conf { - u32 sc_cear; - u16 sc_ceer; - u16 sc_cemr; - u8 res1[70]; - u32 sc_smaer; - u8 res2[4]; - u32 sc_smevr; - u32 sc_smctr; - u32 sc_lmaer; - u8 res3[4]; - u32 sc_lmevr; - u32 sc_lmctr; - u8 res4[144]; -} sysconf_85xx_cpm2_t; - -typedef union sys_conf { - sysconf_82xx_cpm2_t siu_82xx; - sysconf_85xx_cpm2_t siu_85xx; -} sysconf_cpm2_t; - - - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - u32 memc_br0; - u32 memc_or0; - u32 memc_br1; - u32 memc_or1; - u32 memc_br2; - u32 memc_or2; - u32 memc_br3; - u32 memc_or3; - u32 memc_br4; - u32 memc_or4; - u32 memc_br5; - u32 memc_or5; - u32 memc_br6; - u32 memc_or6; - u32 memc_br7; - u32 memc_or7; - u32 memc_br8; - u32 memc_or8; - u32 memc_br9; - u32 memc_or9; - u32 memc_br10; - u32 memc_or10; - u32 memc_br11; - u32 memc_or11; - u8 res1[8]; - u32 memc_mar; - u8 res2[4]; - u32 memc_mamr; - u32 memc_mbmr; - u32 memc_mcmr; - u8 res3[8]; - u16 memc_mptpr; - u8 res4[2]; - u32 memc_mdr; - u8 res5[4]; - u32 memc_psdmr; - u32 memc_lsdmr; - u8 memc_purt; - u8 res6[3]; - u8 memc_psrt; - u8 res7[3]; - u8 memc_lurt; - u8 res8[3]; - u8 memc_lsrt; - u8 res9[3]; - u32 memc_immr; - u32 memc_pcibr0; - u32 memc_pcibr1; - u8 res10[16]; - u32 memc_pcimsk0; - u32 memc_pcimsk1; - u8 res11[52]; -} memctl_cpm2_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - u8 res1[32]; - u16 sit_tmcntsc; - u8 res2[2]; - u32 sit_tmcnt; - u8 res3[4]; - u32 sit_tmcntal; - u8 res4[16]; - u16 sit_piscr; - u8 res5[2]; - u32 sit_pitc; - u32 sit_pitr; - u8 res6[94]; - u8 res7[390]; -} sit_cpm2_t; - -#define PISCR_PIRQ_MASK ((u16)0xff00) -#define PISCR_PS ((u16)0x0080) -#define PISCR_PIE ((u16)0x0004) -#define PISCR_PTF ((u16)0x0002) -#define PISCR_PTE ((u16)0x0001) - -/* PCI Controller. -*/ -typedef struct pci_ctlr { - u32 pci_omisr; - u32 pci_omimr; - u8 res1[8]; - u32 pci_ifqpr; - u32 pci_ofqpr; - u8 res2[8]; - u32 pci_imr0; - u32 pci_imr1; - u32 pci_omr0; - u32 pci_omr1; - u32 pci_odr; - u8 res3[4]; - u32 pci_idr; - u8 res4[20]; - u32 pci_imisr; - u32 pci_imimr; - u8 res5[24]; - u32 pci_ifhpr; - u8 res6[4]; - u32 pci_iftpr; - u8 res7[4]; - u32 pci_iphpr; - u8 res8[4]; - u32 pci_iptpr; - u8 res9[4]; - u32 pci_ofhpr; - u8 res10[4]; - u32 pci_oftpr; - u8 res11[4]; - u32 pci_ophpr; - u8 res12[4]; - u32 pci_optpr; - u8 res13[8]; - u32 pci_mucr; - u8 res14[8]; - u32 pci_qbar; - u8 res15[12]; - u32 pci_dmamr0; - u32 pci_dmasr0; - u32 pci_dmacdar0; - u8 res16[4]; - u32 pci_dmasar0; - u8 res17[4]; - u32 pci_dmadar0; - u8 res18[4]; - u32 pci_dmabcr0; - u32 pci_dmandar0; - u8 res19[86]; - u32 pci_dmamr1; - u32 pci_dmasr1; - u32 pci_dmacdar1; - u8 res20[4]; - u32 pci_dmasar1; - u8 res21[4]; - u32 pci_dmadar1; - u8 res22[4]; - u32 pci_dmabcr1; - u32 pci_dmandar1; - u8 res23[88]; - u32 pci_dmamr2; - u32 pci_dmasr2; - u32 pci_dmacdar2; - u8 res24[4]; - u32 pci_dmasar2; - u8 res25[4]; - u32 pci_dmadar2; - u8 res26[4]; - u32 pci_dmabcr2; - u32 pci_dmandar2; - u8 res27[88]; - u32 pci_dmamr3; - u32 pci_dmasr3; - u32 pci_dmacdar3; - u8 res28[4]; - u32 pci_dmasar3; - u8 res29[4]; - u32 pci_dmadar3; - u8 res30[4]; - u32 pci_dmabcr3; - u32 pci_dmandar3; - u8 res31[344]; - u32 pci_potar0; - u8 res32[4]; - u32 pci_pobar0; - u8 res33[4]; - u32 pci_pocmr0; - u8 res34[4]; - u32 pci_potar1; - u8 res35[4]; - u32 pci_pobar1; - u8 res36[4]; - u32 pci_pocmr1; - u8 res37[4]; - u32 pci_potar2; - u8 res38[4]; - u32 pci_pobar2; - u8 res39[4]; - u32 pci_pocmr2; - u8 res40[50]; - u32 pci_ptcr; - u32 pci_gpcr; - u32 pci_gcr; - u32 pci_esr; - u32 pci_emr; - u32 pci_ecr; - u32 pci_eacr; - u8 res41[4]; - u32 pci_edcr; - u8 res42[4]; - u32 pci_eccr; - u8 res43[44]; - u32 pci_pitar1; - u8 res44[4]; - u32 pci_pibar1; - u8 res45[4]; - u32 pci_picmr1; - u8 res46[4]; - u32 pci_pitar0; - u8 res47[4]; - u32 pci_pibar0; - u8 res48[4]; - u32 pci_picmr0; - u8 res49[4]; - u32 pci_cfg_addr; - u32 pci_cfg_data; - u32 pci_int_ack; - u8 res50[756]; -} pci_cpm2_t; - -/* Interrupt Controller. -*/ -typedef struct interrupt_controller { - u16 ic_sicr; - u8 res1[2]; - u32 ic_sivec; - u32 ic_sipnrh; - u32 ic_sipnrl; - u32 ic_siprr; - u32 ic_scprrh; - u32 ic_scprrl; - u32 ic_simrh; - u32 ic_simrl; - u32 ic_siexr; - u8 res2[88]; -} intctl_cpm2_t; - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - u32 car_sccr; - u8 res1[4]; - u32 car_scmr; - u8 res2[4]; - u32 car_rsr; - u32 car_rmr; - u8 res[104]; -} car_cpm2_t; - -/* Input/Output Port control/status registers. - * Names consistent with processor manual, although they are different - * from the original 8xx names....... - */ -typedef struct io_port { - u32 iop_pdira; - u32 iop_ppara; - u32 iop_psora; - u32 iop_podra; - u32 iop_pdata; - u8 res1[12]; - u32 iop_pdirb; - u32 iop_pparb; - u32 iop_psorb; - u32 iop_podrb; - u32 iop_pdatb; - u8 res2[12]; - u32 iop_pdirc; - u32 iop_pparc; - u32 iop_psorc; - u32 iop_podrc; - u32 iop_pdatc; - u8 res3[12]; - u32 iop_pdird; - u32 iop_ppard; - u32 iop_psord; - u32 iop_podrd; - u32 iop_pdatd; - u8 res4[12]; -} iop_cpm2_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - u8 cpmt_tgcr1; - u8 res1[3]; - u8 cpmt_tgcr2; - u8 res2[11]; - u16 cpmt_tmr1; - u16 cpmt_tmr2; - u16 cpmt_trr1; - u16 cpmt_trr2; - u16 cpmt_tcr1; - u16 cpmt_tcr2; - u16 cpmt_tcn1; - u16 cpmt_tcn2; - u16 cpmt_tmr3; - u16 cpmt_tmr4; - u16 cpmt_trr3; - u16 cpmt_trr4; - u16 cpmt_tcr3; - u16 cpmt_tcr4; - u16 cpmt_tcn3; - u16 cpmt_tcn4; - u16 cpmt_ter1; - u16 cpmt_ter2; - u16 cpmt_ter3; - u16 cpmt_ter4; - u8 res3[584]; -} cpmtimer_cpm2_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - u8 res0[24]; - u8 sdma_sdsr; - u8 res1[3]; - u8 sdma_sdmr; - u8 res2[3]; - u8 sdma_idsr1; - u8 res3[3]; - u8 sdma_idmr1; - u8 res4[3]; - u8 sdma_idsr2; - u8 res5[3]; - u8 sdma_idmr2; - u8 res6[3]; - u8 sdma_idsr3; - u8 res7[3]; - u8 sdma_idmr3; - u8 res8[3]; - u8 sdma_idsr4; - u8 res9[3]; - u8 sdma_idmr4; - u8 res10[707]; -} sdma_cpm2_t; - -/* Fast controllers -*/ -typedef struct fcc { - u32 fcc_gfmr; - u32 fcc_fpsmr; - u16 fcc_ftodr; - u8 res1[2]; - u16 fcc_fdsr; - u8 res2[2]; - u16 fcc_fcce; - u8 res3[2]; - u16 fcc_fccm; - u8 res4[2]; - u8 fcc_fccs; - u8 res5[3]; - u8 fcc_ftirr_phy[4]; -} fcc_t; - -/* Fast controllers continued - */ -typedef struct fcc_c { - u32 fcc_firper; - u32 fcc_firer; - u32 fcc_firsr_hi; - u32 fcc_firsr_lo; - u8 fcc_gfemr; - u8 res1[15]; -} fcc_c_t; - -/* TC Layer - */ -typedef struct tclayer { - u16 tc_tcmode; - u16 tc_cdsmr; - u16 tc_tcer; - u16 tc_rcc; - u16 tc_tcmr; - u16 tc_fcc; - u16 tc_ccc; - u16 tc_icc; - u16 tc_tcc; - u16 tc_ecc; - u8 res1[12]; -} tclayer_t; - - -/* I2C -*/ -typedef struct i2c { - u8 i2c_i2mod; - u8 res1[3]; - u8 i2c_i2add; - u8 res2[3]; - u8 i2c_i2brg; - u8 res3[3]; - u8 i2c_i2com; - u8 res4[3]; - u8 i2c_i2cer; - u8 res5[3]; - u8 i2c_i2cmr; - u8 res6[331]; -} i2c_cpm2_t; - -typedef struct scc { /* Serial communication channels */ - u32 scc_gsmrl; - u32 scc_gsmrh; - u16 scc_psmr; - u8 res1[2]; - u16 scc_todr; - u16 scc_dsr; - u16 scc_scce; - u8 res2[2]; - u16 scc_sccm; - u8 res3; - u8 scc_sccs; - u8 res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - u8 res1[2]; - u16 smc_smcmr; - u8 res2[2]; - u8 smc_smce; - u8 res3[3]; - u8 smc_smcm; - u8 res4[5]; -} smc_t; - -/* Serial Peripheral Interface. -*/ -typedef struct spi_ctrl { - u16 spi_spmode; - u8 res1[4]; - u8 spi_spie; - u8 res2[3]; - u8 spi_spim; - u8 res3[2]; - u8 spi_spcom; - u8 res4[82]; -} spictl_cpm2_t; - -/* CPM Mux. -*/ -typedef struct cpmux { - u8 cmx_si1cr; - u8 res1; - u8 cmx_si2cr; - u8 res2; - u32 cmx_fcr; - u32 cmx_scr; - u8 cmx_smr; - u8 res3; - u16 cmx_uar; - u8 res4[16]; -} cpmux_t; - -/* SIRAM control -*/ -typedef struct siram { - u16 si_amr; - u16 si_bmr; - u16 si_cmr; - u16 si_dmr; - u8 si_gmr; - u8 res1; - u8 si_cmdr; - u8 res2; - u8 si_str; - u8 res3; - u16 si_rsr; -} siramctl_t; - -typedef struct mcc { - u16 mcc_mcce; - u8 res1[2]; - u16 mcc_mccm; - u8 res2[2]; - u8 mcc_mccf; - u8 res3[7]; -} mcc_t; - -typedef struct comm_proc { - u32 cp_cpcr; - u32 cp_rccr; - u8 res1[14]; - u16 cp_rter; - u8 res2[2]; - u16 cp_rtmr; - u16 cp_rtscr; - u8 res3[2]; - u32 cp_rtsr; - u8 res4[12]; -} cpm_cpm2_t; - -/* USB Controller. -*/ -typedef struct usb_ctlr { - u8 usb_usmod; - u8 usb_usadr; - u8 usb_uscom; - u8 res1[1]; - u16 usb_usep1; - u16 usb_usep2; - u16 usb_usep3; - u16 usb_usep4; - u8 res2[4]; - u16 usb_usber; - u8 res3[2]; - u16 usb_usbmr; - u8 usb_usbs; - u8 res4[7]; -} usb_cpm2_t; - -/* ...and the whole thing wrapped up.... -*/ - -typedef struct immap { - /* Some references are into the unique and known dpram spaces, - * others are from the generic base. - */ -#define im_dprambase im_dpram1 - u8 im_dpram1[16*1024]; - u8 res1[16*1024]; - u8 im_dpram2[4*1024]; - u8 res2[8*1024]; - u8 im_dpram3[4*1024]; - u8 res3[16*1024]; - - sysconf_cpm2_t im_siu_conf; /* SIU Configuration */ - memctl_cpm2_t im_memctl; /* Memory Controller */ - sit_cpm2_t im_sit; /* System Integration Timers */ - pci_cpm2_t im_pci; /* PCI Controller */ - intctl_cpm2_t im_intctl; /* Interrupt Controller */ - car_cpm2_t im_clkrst; /* Clocks and reset */ - iop_cpm2_t im_ioport; /* IO Port control/status */ - cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */ - sdma_cpm2_t im_sdma; /* SDMA control/status */ - - fcc_t im_fcc[3]; /* Three FCCs */ - u8 res4z[32]; - fcc_c_t im_fcc_c[3]; /* Continued FCCs */ - - u8 res4[32]; - - tclayer_t im_tclayer[8]; /* Eight TCLayers */ - u16 tc_tcgsr; - u16 tc_tcger; - - /* First set of baud rate generators. - */ - u8 res[236]; - u32 im_brgc5; - u32 im_brgc6; - u32 im_brgc7; - u32 im_brgc8; - - u8 res5[608]; - - i2c_cpm2_t im_i2c; /* I2C control/status */ - cpm_cpm2_t im_cpm; /* Communication processor */ - - /* Second set of baud rate generators. - */ - u32 im_brgc1; - u32 im_brgc2; - u32 im_brgc3; - u32 im_brgc4; - - scc_t im_scc[4]; /* Four SCCs */ - smc_t im_smc[2]; /* Couple of SMCs */ - spictl_cpm2_t im_spi; /* A SPI */ - cpmux_t im_cpmux; /* CPM clock route mux */ - siramctl_t im_siramctl1; /* First SI RAM Control */ - mcc_t im_mcc1; /* First MCC */ - siramctl_t im_siramctl2; /* Second SI RAM Control */ - mcc_t im_mcc2; /* Second MCC */ - usb_cpm2_t im_usb; /* USB Controller */ - - u8 res6[1153]; - - u16 im_si1txram[256]; - u8 res7[512]; - u16 im_si1rxram[256]; - u8 res8[512]; - u16 im_si2txram[256]; - u8 res9[512]; - u16 im_si2rxram[256]; - u8 res10[512]; - u8 res11[4096]; -} cpm2_map_t; - -extern cpm2_map_t *cpm2_immr; - -#endif /* __IMMAP_CPM2__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h deleted file mode 100644 index a0d409a5d80f..000000000000 --- a/include/asm-ppc/io.h +++ /dev/null @@ -1,502 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_IO_H -#define _PPC_IO_H - -#include <linux/string.h> -#include <linux/types.h> - -#include <asm/page.h> -#include <asm/byteorder.h> -#include <asm/synch.h> -#include <asm/mmu.h> - -#define SIO_CONFIG_RA 0x398 -#define SIO_CONFIG_RD 0x399 - -#define SLOW_DOWN_IO - -#define PMAC_ISA_MEM_BASE 0 -#define PMAC_PCI_DRAM_OFFSET 0 -#define CHRP_ISA_IO_BASE 0xf8000000 -#define CHRP_ISA_MEM_BASE 0xf7000000 -#define CHRP_PCI_DRAM_OFFSET 0 -#define PREP_ISA_IO_BASE 0x80000000 -#define PREP_ISA_MEM_BASE 0xc0000000 -#define PREP_PCI_DRAM_OFFSET 0x80000000 - -#if defined(CONFIG_4xx) -#include <asm/ibm4xx.h> -#elif defined(CONFIG_8xx) -#include <asm/mpc8xx.h> -#elif defined(CONFIG_8260) -#include <asm/mpc8260.h> -#elif !defined(CONFIG_PCI) -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#else /* Everyone else */ -#define _IO_BASE isa_io_base -#define _ISA_MEM_BASE isa_mem_base -#define PCI_DRAM_OFFSET pci_dram_offset -#endif /* Platform-dependent I/O */ - -#define ___IO_BASE ((void __iomem *)_IO_BASE) -extern unsigned long isa_io_base; -extern unsigned long isa_mem_base; -extern unsigned long pci_dram_offset; - -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - * - * Read operations have additional twi & isync to make sure the read - * is actually performed (i.e. the data has come back) before we start - * executing any following instructions. - */ -extern inline int in_8(const volatile unsigned char __iomem *addr) -{ - int ret; - - __asm__ __volatile__( - "sync; lbz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_8(volatile unsigned char __iomem *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} - -extern inline int in_le16(const volatile unsigned short __iomem *addr) -{ - int ret; - - __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline int in_be16(const volatile unsigned short __iomem *addr) -{ - int ret; - - __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le16(volatile unsigned short __iomem *addr, int val) -{ - __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be16(volatile unsigned short __iomem *addr, int val) -{ - __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} - -extern inline unsigned in_le32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} - -extern inline unsigned in_be32(const volatile unsigned __iomem *addr) -{ - unsigned ret; - - __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; -} - -extern inline void out_le32(volatile unsigned __iomem *addr, int val) -{ - __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); -} - -extern inline void out_be32(volatile unsigned __iomem *addr, int val) -{ - __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} -#if defined (CONFIG_8260_PCI9) -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) -#else -static inline __u8 readb(const volatile void __iomem *addr) -{ - return in_8(addr); -} -static inline void writeb(__u8 b, volatile void __iomem *addr) -{ - out_8(addr, b); -} -#endif - -#if defined (CONFIG_8260_PCI9) -/* Use macros if PCI9 workaround enabled */ -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) -#else -static inline __u16 readw(const volatile void __iomem *addr) -{ - return in_le16(addr); -} -static inline __u32 readl(const volatile void __iomem *addr) -{ - return in_le32(addr); -} -static inline void writew(__u16 b, volatile void __iomem *addr) -{ - out_le16(addr, b); -} -static inline void writel(__u32 b, volatile void __iomem *addr) -{ - out_le32(addr, b); -} -#endif /* CONFIG_8260_PCI9 */ - -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) - -static inline __u8 __raw_readb(const volatile void __iomem *addr) -{ - return *(__force volatile __u8 *)(addr); -} -static inline __u16 __raw_readw(const volatile void __iomem *addr) -{ - return *(__force volatile __u16 *)(addr); -} -static inline __u32 __raw_readl(const volatile void __iomem *addr) -{ - return *(__force volatile __u32 *)(addr); -} -static inline void __raw_writeb(__u8 b, volatile void __iomem *addr) -{ - *(__force volatile __u8 *)(addr) = b; -} -static inline void __raw_writew(__u16 b, volatile void __iomem *addr) -{ - *(__force volatile __u16 *)(addr) = b; -} -static inline void __raw_writel(__u32 b, volatile void __iomem *addr) -{ - *(__force volatile __u32 *)(addr) = b; -} - -#define mmiowb() - -/* - * The insw/outsw/insl/outsl macros don't do byte-swapping. - * They are only used in practice for transferring buffers which - * are arrays of bytes, and byte-swapping is not appropriate in - * that case. - paulus - */ -#define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns)) -#define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl)) - -#define readsb(a, b, n) _insb((a), (b), (n)) -#define readsw(a, b, n) _insw_ns((a), (b), (n)) -#define readsl(a, b, n) _insl_ns((a), (b), (n)) -#define writesb(a, b, n) _outsb((a),(b),(n)) -#define writesw(a, b, n) _outsw_ns((a),(b),(n)) -#define writesl(a, b, n) _outsl_ns((a),(b),(n)) - - -/* - * On powermacs and 8xx we will get a machine check exception - * if we try to read data from a non-existent I/O port. Because - * the machine check is an asynchronous exception, it isn't - * well-defined which instruction SRR0 will point to when the - * exception occurs. - * With the sequence below (twi; isync; nop), we have found that - * the machine check occurs on one of the three instructions on - * all PPC implementations tested so far. The twi and isync are - * needed on the 601 (in fact twi; sync works too), the isync and - * nop are needed on 604[e|r], and any of twi, sync or isync will - * work on 603[e], 750, 74xx. - * The twi creates an explicit data dependency on the returned - * value which seems to be needed to make the 601 wait for the - * load to finish. - */ - -#define __do_in_asm(name, op) \ -extern __inline__ unsigned int name(unsigned int port) \ -{ \ - unsigned int x; \ - __asm__ __volatile__( \ - "sync\n" \ - "0:" op " %0,0,%1\n" \ - "1: twi 0,%0,0\n" \ - "2: isync\n" \ - "3: nop\n" \ - "4:\n" \ - ".section .fixup,\"ax\"\n" \ - "5: li %0,-1\n" \ - " b 4b\n" \ - ".previous\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 0b,5b\n" \ - " .long 1b,5b\n" \ - " .long 2b,5b\n" \ - " .long 3b,5b\n" \ - ".previous" \ - : "=&r" (x) \ - : "r" (port + ___IO_BASE)); \ - return x; \ -} - -#define __do_out_asm(name, op) \ -extern __inline__ void name(unsigned int val, unsigned int port) \ -{ \ - __asm__ __volatile__( \ - "sync\n" \ - "0:" op " %0,0,%1\n" \ - "1: sync\n" \ - "2:\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 0b,2b\n" \ - " .long 1b,2b\n" \ - ".previous" \ - : : "r" (val), "r" (port + ___IO_BASE)); \ -} - -__do_out_asm(outb, "stbx") -#if defined (CONFIG_8260_PCI9) -/* in asm cannot be defined if PCI9 workaround is used */ -#define inb(port) in_8((port)+___IO_BASE) -#define inw(port) in_le16((port)+___IO_BASE) -#define inl(port) in_le32((port)+___IO_BASE) -__do_out_asm(outw, "sthbrx") -__do_out_asm(outl, "stwbrx") -#else -__do_in_asm(inb, "lbzx") -__do_in_asm(inw, "lhbrx") -__do_in_asm(inl, "lwbrx") -__do_out_asm(outw, "sthbrx") -__do_out_asm(outl, "stwbrx") - -#endif - -#define inb_p(port) inb((port)) -#define outb_p(val, port) outb((val), (port)) -#define inw_p(port) inw((port)) -#define outw_p(val, port) outw((val), (port)) -#define inl_p(port) inl((port)) -#define outl_p(val, port) outl((val), (port)) - -extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); -extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); -extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); -extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); -extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); -extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); - - -#define IO_SPACE_LIMIT ~0 - -#if defined (CONFIG_8260_PCI9) -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) -#else -static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) -{ - memset((void __force *)addr, val, count); -} -static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count) -{ - memcpy(dst, (void __force *) src, count); -} -static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) -{ - memcpy((void __force *) dst, src, count); -} -#endif - -/* - * Map in an area of physical address space, for accessing - * I/O devices etc. - */ -extern void __iomem *__ioremap(phys_addr_t address, unsigned long size, - unsigned long flags); -extern void __iomem *ioremap(phys_addr_t address, unsigned long size); -#ifdef CONFIG_44x -extern void __iomem *ioremap64(unsigned long long address, unsigned long size); -#endif -#define ioremap_nocache(addr, size) ioremap((addr), (size)) -extern void iounmap(volatile void __iomem *addr); -extern unsigned long iopa(unsigned long addr); -extern void io_block_mapping(unsigned long virt, phys_addr_t phys, - unsigned int size, int flags); - -/* - * The PCI bus is inherently Little-Endian. The PowerPC is being - * run Big-Endian. Thus all values which cross the [PCI] barrier - * must be endian-adjusted. Also, the local DRAM has a different - * address from the PCI point of view, thus buffer addresses also - * have to be modified [mapped] appropriately. - */ -extern inline unsigned long virt_to_bus(volatile void * address) -{ - if (address == (void *)0) - return 0; - return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET; -} - -extern inline void * bus_to_virt(unsigned long address) -{ - if (address == 0) - return NULL; - return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE); -} - -/* - * Change virtual addresses to physical addresses and vv, for - * addresses in the area where the kernel has the RAM mapped. - */ -extern inline unsigned long virt_to_phys(volatile void * address) -{ - return (unsigned long) address - KERNELBASE; -} - -extern inline void * phys_to_virt(unsigned long address) -{ - return (void *) (address + KERNELBASE); -} - -/* - * Change "struct page" to physical address. - */ -#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) -#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) - -/* Enforce in-order execution of data I/O. - * No distinction between read/write on PPC; use eieio for all three. - */ -#define iobarrier_rw() eieio() -#define iobarrier_r() eieio() -#define iobarrier_w() eieio() - -/* - * Here comes the ppc implementation of the IOMAP - * interfaces. - */ -static inline unsigned int ioread8(void __iomem *addr) -{ - return readb(addr); -} - -static inline unsigned int ioread16(void __iomem *addr) -{ - return readw(addr); -} - -static inline unsigned int ioread32(void __iomem *addr) -{ - return readl(addr); -} - -static inline void iowrite8(u8 val, void __iomem *addr) -{ - writeb(val, addr); -} - -static inline void iowrite16(u16 val, void __iomem *addr) -{ - writew(val, addr); -} - -static inline void iowrite32(u32 val, void __iomem *addr) -{ - writel(val, addr); -} - -static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count) -{ - _insb(addr, dst, count); -} - -static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count) -{ - _insw_ns(addr, dst, count); -} - -static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count) -{ - _insl_ns(addr, dst, count); -} - -static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count) -{ - _outsb(addr, src, count); -} - -static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count) -{ - _outsw_ns(addr, src, count); -} - -static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count) -{ - _outsl_ns(addr, src, count); -} - -/* Create a virtual mapping cookie for an IO port range */ -extern void __iomem *ioport_map(unsigned long port, unsigned int nr); -extern void ioport_unmap(void __iomem *); - -/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ -struct pci_dev; -extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); -extern void pci_iounmap(struct pci_dev *dev, void __iomem *); - -#endif /* _PPC_IO_H */ - -#ifdef CONFIG_8260_PCI9 -#include <asm/mpc8260_pci9.h> -#endif - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -/* access ports */ -#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) -#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) - -#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) -#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) - -#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) -#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) - -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/irq_regs.h b/include/asm-ppc/irq_regs.h deleted file mode 100644 index 3dd9c0b70270..000000000000 --- a/include/asm-ppc/irq_regs.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/irq_regs.h> diff --git a/include/asm-ppc/kdebug.h b/include/asm-ppc/kdebug.h deleted file mode 100644 index 6ece1b037665..000000000000 --- a/include/asm-ppc/kdebug.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/kdebug.h> diff --git a/include/asm-ppc/kgdb.h b/include/asm-ppc/kgdb.h deleted file mode 100644 index b617dac82969..000000000000 --- a/include/asm-ppc/kgdb.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * kgdb.h: Defines and declarations for serial line source level - * remote debugging of the Linux kernel using gdb. - * - * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu) - * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - */ -#ifdef __KERNEL__ -#ifndef _PPC_KGDB_H -#define _PPC_KGDB_H - -#ifndef __ASSEMBLY__ - -/* Things specific to the gen550 backend. */ -struct uart_port; - -extern void gen550_progress(char *, unsigned short); -extern void gen550_kgdb_map_scc(void); -extern void gen550_init(int, struct uart_port *); - -/* Things specific to the pmac backend. */ -extern void zs_kgdb_hook(int tty_num); - -/* To init the kgdb engine. (called by serial hook)*/ -extern void set_debug_traps(void); - -/* To enter the debugger explicitly. */ -extern void breakpoint(void); - -/* For taking exceptions - * these are defined in traps.c - */ -extern int (*debugger)(struct pt_regs *regs); -extern int (*debugger_bpt)(struct pt_regs *regs); -extern int (*debugger_sstep)(struct pt_regs *regs); -extern int (*debugger_iabr_match)(struct pt_regs *regs); -extern int (*debugger_dabr_match)(struct pt_regs *regs); -extern void (*debugger_fault_handler)(struct pt_regs *regs); - -/* What we bring to the party */ -int kgdb_bpt(struct pt_regs *regs); -int kgdb_sstep(struct pt_regs *regs); -void kgdb(struct pt_regs *regs); -int kgdb_iabr_match(struct pt_regs *regs); -int kgdb_dabr_match(struct pt_regs *regs); - -/* - * external low-level support routines (ie macserial.c) - */ -extern void kgdb_interruptible(int); /* control interrupts from serial */ -extern void putDebugChar(char); /* write a single character */ -extern char getDebugChar(void); /* read and return a single char */ - -#endif /* !(__ASSEMBLY__) */ -#endif /* !(_PPC_KGDB_H) */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h deleted file mode 100644 index bf9e05dd54b5..000000000000 --- a/include/asm-ppc/m8260_pci.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * include/asm-ppc/m8260_pci.h - * - * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __M8260_PCI_H -#define __M8260_PCI_H - -#include <linux/pci_ids.h> - -/* - * Define the vendor/device ID for the MPC8265. - */ -#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA) -#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA) - -#define M8265_PCIBR0 0x101ac -#define M8265_PCIBR1 0x101b0 -#define M8265_PCIMSK0 0x101c4 -#define M8265_PCIMSK1 0x101c8 - -/* Bit definitions for PCIBR registers */ - -#define PCIBR_ENABLE 0x00000001 - -/* Bit definitions for PCIMSK registers */ - -#define PCIMSK_32KiB 0xFFFF8000 /* Size of window, smallest */ -#define PCIMSK_64KiB 0xFFFF0000 -#define PCIMSK_128KiB 0xFFFE0000 -#define PCIMSK_256KiB 0xFFFC0000 -#define PCIMSK_512KiB 0xFFF80000 -#define PCIMSK_1MiB 0xFFF00000 -#define PCIMSK_2MiB 0xFFE00000 -#define PCIMSK_4MiB 0xFFC00000 -#define PCIMSK_8MiB 0xFF800000 -#define PCIMSK_16MiB 0xFF000000 -#define PCIMSK_32MiB 0xFE000000 -#define PCIMSK_64MiB 0xFC000000 -#define PCIMSK_128MiB 0xF8000000 -#define PCIMSK_256MiB 0xF0000000 -#define PCIMSK_512MiB 0xE0000000 -#define PCIMSK_1GiB 0xC0000000 /* Size of window, largest */ - - -#define M826X_SCCR_PCI_MODE_EN 0x100 - - -/* - * Outbound ATU registers (3 sets). These registers control how 60x bus (local) - * addresses are translated to PCI addresses when the MPC826x is a PCI bus - * master (initiator). - */ - -#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ -#define POTAR_REG1 0x10818 -#define POTAR_REG2 0x10830 - -#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ -#define POBAR_REG1 0x10820 -#define POBAR_REG2 0x10838 - -#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ -#define POCMR_REG1 0x10828 -#define POCMR_REG2 0x10840 - -/* Bit definitions for POMCR registers */ - -#define POCMR_MASK_4KiB 0x000FFFFF -#define POCMR_MASK_8KiB 0x000FFFFE -#define POCMR_MASK_16KiB 0x000FFFFC -#define POCMR_MASK_32KiB 0x000FFFF8 -#define POCMR_MASK_64KiB 0x000FFFF0 -#define POCMR_MASK_128KiB 0x000FFFE0 -#define POCMR_MASK_256KiB 0x000FFFC0 -#define POCMR_MASK_512KiB 0x000FFF80 -#define POCMR_MASK_1MiB 0x000FFF00 -#define POCMR_MASK_2MiB 0x000FFE00 -#define POCMR_MASK_4MiB 0x000FFC00 -#define POCMR_MASK_8MiB 0x000FF800 -#define POCMR_MASK_16MiB 0x000FF000 -#define POCMR_MASK_32MiB 0x000FE000 -#define POCMR_MASK_64MiB 0x000FC000 -#define POCMR_MASK_128MiB 0x000F8000 -#define POCMR_MASK_256MiB 0x000F0000 -#define POCMR_MASK_512MiB 0x000E0000 -#define POCMR_MASK_1GiB 0x000C0000 - -#define POCMR_ENABLE 0x80000000 -#define POCMR_PCI_IO 0x40000000 -#define POCMR_PREFETCH_EN 0x20000000 - -/* Soft PCI reset */ - -#define PCI_GCR_REG 0x10880 - -/* Bit definitions for PCI_GCR registers */ - -#define PCIGCR_PCI_BUS_EN 0x1 - -#define PCI_EMR_REG 0x10888 -/* - * Inbound ATU registers (2 sets). These registers control how PCI addresses - * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. - */ - -#define PITAR_REG1 0x108D0 -#define PIBAR_REG1 0x108D8 -#define PICMR_REG1 0x108E0 -#define PITAR_REG0 0x108E8 -#define PIBAR_REG0 0x108F0 -#define PICMR_REG0 0x108F8 - -/* Bit definitions for PCI Inbound Comparison Mask registers */ - -#define PICMR_MASK_4KiB 0x000FFFFF -#define PICMR_MASK_8KiB 0x000FFFFE -#define PICMR_MASK_16KiB 0x000FFFFC -#define PICMR_MASK_32KiB 0x000FFFF8 -#define PICMR_MASK_64KiB 0x000FFFF0 -#define PICMR_MASK_128KiB 0x000FFFE0 -#define PICMR_MASK_256KiB 0x000FFFC0 -#define PICMR_MASK_512KiB 0x000FFF80 -#define PICMR_MASK_1MiB 0x000FFF00 -#define PICMR_MASK_2MiB 0x000FFE00 -#define PICMR_MASK_4MiB 0x000FFC00 -#define PICMR_MASK_8MiB 0x000FF800 -#define PICMR_MASK_16MiB 0x000FF000 -#define PICMR_MASK_32MiB 0x000FE000 -#define PICMR_MASK_64MiB 0x000FC000 -#define PICMR_MASK_128MiB 0x000F8000 -#define PICMR_MASK_256MiB 0x000F0000 -#define PICMR_MASK_512MiB 0x000E0000 -#define PICMR_MASK_1GiB 0x000C0000 - -#define PICMR_ENABLE 0x80000000 -#define PICMR_NO_SNOOP_EN 0x40000000 -#define PICMR_PREFETCH_EN 0x20000000 - -/* PCI error Registers */ - -#define PCI_ERROR_STATUS_REG 0x10884 -#define PCI_ERROR_MASK_REG 0x10888 -#define PCI_ERROR_CONTROL_REG 0x1088C -#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 -#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 -#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 - -/* PCI error Register bit defines */ - -#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 -#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 -#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 -#define PCI_ERROR_PCI_NO_RSP 0x00000008 -#define PCI_ERROR_PCI_TAR_ABT 0x00000010 -#define PCI_ERROR_PCI_SERR 0x00000020 -#define PCI_ERROR_PCI_PERR_RD 0x00000040 -#define PCI_ERROR_PCI_PERR_WR 0x00000080 -#define PCI_ERROR_I2O_OFQO 0x00000100 -#define PCI_ERROR_I2O_IPQO 0x00000200 -#define PCI_ERROR_IRA 0x00000400 -#define PCI_ERROR_NMI 0x00000800 -#define PCI_ERROR_I2O_DBMC 0x00001000 - -/* - * Register pair used to generate configuration cycles on the PCI bus - * and access the MPC826x's own PCI configuration registers. - */ - -#define PCI_CFG_ADDR_REG 0x10900 -#define PCI_CFG_DATA_REG 0x10904 - -/* Bus parking decides where the bus control sits when idle */ -/* If modifying memory controllers for PCI park on the core */ - -#define PPC_ACR_BUS_PARK_CORE 0x6 -#define PPC_ACR_BUS_PARK_PCI 0x3 - -#endif /* __M8260_PCI_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h deleted file mode 100644 index a20b499b0186..000000000000 --- a/include/asm-ppc/machdep.h +++ /dev/null @@ -1,178 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_MACHDEP_H -#define _PPC_MACHDEP_H - -#include <linux/init.h> -#include <linux/kexec.h> - -#include <asm/setup.h> -#include <asm/page.h> - -struct pt_regs; -struct pci_bus; -struct pci_dev; -struct seq_file; -struct file; - -/* - * This is for compatibility with ARCH=powerpc. - */ -#define machine_is(x) __MACHINE_IS_##x -#define __MACHINE_IS_powermac 0 -#define __MACHINE_IS_chrp 0 -#ifdef CONFIG_PPC_PREP -#define __MACHINE_IS_prep 1 -#else -#define __MACHINE_IS_prep 0 -#endif - -/* We export this macro for external modules like Alsa to know if - * ppc_md.feature_call is implemented or not - */ -#define CONFIG_PPC_HAS_FEATURE_CALLS - -struct machdep_calls { - void (*setup_arch)(void); - /* Optional, may be NULL. */ - int (*show_cpuinfo)(struct seq_file *m); - int (*show_percpuinfo)(struct seq_file *m, int i); - /* Optional, may be NULL. */ - unsigned int (*irq_canonicalize)(unsigned int irq); - void (*init_IRQ)(void); - int (*get_irq)(void); - - /* A general init function, called by ppc_init in init/main.c. - May be NULL. DEPRECATED ! */ - void (*init)(void); - /* For compatibility with merged platforms */ - void (*init_early)(void); - - void (*restart)(char *cmd); - void (*power_off)(void); - void (*halt)(void); - - void (*idle_loop)(void); - void (*power_save)(void); - - long (*time_init)(void); /* Optional, may be NULL */ - int (*set_rtc_time)(unsigned long nowtime); - unsigned long (*get_rtc_time)(void); - unsigned char (*rtc_read_val)(int addr); - void (*rtc_write_val)(int addr, unsigned char val); - void (*calibrate_decr)(void); - - void (*heartbeat)(void); - unsigned long heartbeat_reset; - unsigned long heartbeat_count; - - unsigned long (*find_end_of_memory)(void); - void (*setup_io_mappings)(void); - - void (*early_serial_map)(void); - void (*progress)(char *, unsigned short); - void (*kgdb_map_scc)(void); - - unsigned char (*nvram_read_val)(int addr); - void (*nvram_write_val)(int addr, unsigned char val); - void (*nvram_sync)(void); - - /* - * optional PCI "hooks" - */ - - /* Called after scanning the bus, before allocating resources */ - void (*pcibios_fixup)(void); - - /* Called after PPC generic resource fixup to perform - machine specific fixups */ - void (*pcibios_fixup_resources)(struct pci_dev *); - - /* Called for each PCI bus in the system when it's probed */ - void (*pcibios_fixup_bus)(struct pci_bus *); - - /* Called when pci_enable_device() is called (initial=0) or - * when a device with no assigned resource is found (initial=1). - * Returns 0 to allow assignment/enabling of the device. */ - int (*pcibios_enable_device_hook)(struct pci_dev *, int initial); - - /* For interrupt routing */ - unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *); - int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char); - - /* Called in indirect_* to avoid touching devices */ - int (*pci_exclude_device)(unsigned char, unsigned char); - - /* Called at then very end of pcibios_init() */ - void (*pcibios_after_init)(void); - - /* Get access protection for /dev/mem */ - pgprot_t (*phys_mem_access_prot)(struct file *file, - unsigned long pfn, - unsigned long size, - pgprot_t vma_prot); - - /* Motherboard/chipset features. This is a kind of general purpose - * hook used to control some machine specific features (like reset - * lines, chip power control, etc...). - */ - long (*feature_call)(unsigned int feature, ...); - -#ifdef CONFIG_SMP - /* functions for dealing with other cpus */ - struct smp_ops_t *smp_ops; -#endif /* CONFIG_SMP */ - -#ifdef CONFIG_KEXEC - /* Called to shutdown machine specific hardware not already controlled - * by other drivers. - * XXX Should we move this one out of kexec scope? - */ - void (*machine_shutdown)(void); - - /* Called to do the minimal shutdown needed to run a kexec'd kernel - * to run successfully. - * XXX Should we move this one out of kexec scope? - */ - void (*machine_crash_shutdown)(void); - - /* Called to do what every setup is needed on image and the - * reboot code buffer. Returns 0 on success. - * Provide your own (maybe dummy) implementation if your platform - * claims to support kexec. - */ - int (*machine_kexec_prepare)(struct kimage *image); - - /* Called to handle any machine specific cleanup on image */ - void (*machine_kexec_cleanup)(struct kimage *image); - - /* Called to perform the _real_ kexec. - * Do NOT allocate memory or fail here. We are past the point of - * no return. - */ - void (*machine_kexec)(struct kimage *image); -#endif /* CONFIG_KEXEC */ -}; - -extern struct machdep_calls ppc_md; -extern char cmd_line[COMMAND_LINE_SIZE]; - -extern void setup_pci_ptrs(void); - -#ifdef CONFIG_SMP -struct smp_ops_t { - void (*message_pass)(int target, int msg); - int (*probe)(void); - void (*kick_cpu)(int nr); - void (*setup_cpu)(int nr); - void (*space_timers)(int nr); - void (*take_timebase)(void); - void (*give_timebase)(void); -}; - -/* Poor default implementations */ -extern void __devinit smp_generic_give_timebase(void); -extern void __devinit smp_generic_take_timebase(void); -#endif /* CONFIG_SMP */ - -#endif /* _PPC_MACHDEP_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/md.h b/include/asm-ppc/md.h deleted file mode 100644 index 9a9b6b42b4b4..000000000000 --- a/include/asm-ppc/md.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * md.h: High speed xor_block operation for RAID4/5 - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_MD_H -#define __ASM_MD_H - -/* #define HAVE_ARCH_XORBLOCK */ - -#define MD_XORBLOCK_ALIGNMENT sizeof(long) - -#endif /* __ASM_MD_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mk48t59.h b/include/asm-ppc/mk48t59.h deleted file mode 100644 index 6a0ed6fc2d56..000000000000 --- a/include/asm-ppc/mk48t59.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Registers for the mk48t59 real-time-clock - */ - -#ifndef _PPC_MK48T59_H -#define _PPC_MK48T59_H - -/* RTC Offsets */ - -#define MK48T59_RTC_SECONDS 0x1FF9 -#define MK48T59_RTC_MINUTES 0x1FFA -#define MK48T59_RTC_HOURS 0x1FFB -#define MK48T59_RTC_DAY_OF_WEEK 0x1FFC -#define MK48T59_RTC_DAY_OF_MONTH 0x1FFD -#define MK48T59_RTC_MONTH 0x1FFE -#define MK48T59_RTC_YEAR 0x1FFF - -#define MK48T59_RTC_CONTROLA 0x1FF8 -#define MK48T59_RTC_CA_WRITE 0x80 -#define MK48T59_RTC_CA_READ 0x40 -#define MK48T59_RTC_CA_CALIB_SIGN 0x20 -#define MK48T59_RTC_CA_CALIB_MASK 0x1f - -#define MK48T59_RTC_CONTROLB 0x1FF9 -#define MK48T59_RTC_CB_STOP 0x80 - -#endif /* _PPC_MK48T59_H */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h deleted file mode 100644 index d76ef098ed37..000000000000 --- a/include/asm-ppc/mmu.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * PowerPC memory management structures - */ - -#ifdef __KERNEL__ -#ifndef _PPC_MMU_H_ -#define _PPC_MMU_H_ - - -#ifndef __ASSEMBLY__ - -/* - * Define physical address type. Machines using split size - * virtual/physical addressing like 32-bit virtual / 36-bit - * physical need a larger than native word size type. -Matt - */ -#ifndef CONFIG_PHYS_64BIT -#define PHYS_FMT "%.8lx" -#else -extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t); -#define PHYS_FMT "%16Lx" -#endif - -typedef struct { - unsigned long id; - unsigned long vdso_base; -} mm_context_t; - -/* Hardware Page Table Entry */ -typedef struct _PTE { - unsigned long v:1; /* Entry is valid */ - unsigned long vsid:24; /* Virtual segment identifier */ - unsigned long h:1; /* Hash algorithm indicator */ - unsigned long api:6; /* Abbreviated page index */ - unsigned long rpn:20; /* Real (physical) page number */ - unsigned long :3; /* Unused */ - unsigned long r:1; /* Referenced */ - unsigned long c:1; /* Changed */ - unsigned long w:1; /* Write-thru cache mode */ - unsigned long i:1; /* Cache inhibited */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page protection */ -} PTE; - -/* Values for PP (assumes Ks=0, Kp=1) */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - -/* Segment Register */ -typedef struct _SEGREG { - unsigned long t:1; /* Normal or I/O type */ - unsigned long ks:1; /* Supervisor 'key' (normally 0) */ - unsigned long kp:1; /* User 'key' (normally 1) */ - unsigned long n:1; /* No-execute */ - unsigned long :4; /* Unused */ - unsigned long vsid:24; /* Virtual Segment Identifier */ -} SEGREG; - -/* Block Address Translation (BAT) Registers */ -typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :8; /* unused */ - unsigned long w:1; - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long ks:1; /* Supervisor key (normally 0) */ - unsigned long kp:1; /* User key (normally 1) */ - unsigned long pp:2; /* Page access protections */ -} P601_BATU; - -typedef struct _BATU { /* Upper part of BAT (all except 601) */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :4; /* Unused */ - unsigned long bl:11; /* Block size mask */ - unsigned long vs:1; /* Supervisor valid */ - unsigned long vp:1; /* User valid */ -} BATU; - -typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long v:1; /* Valid bit */ - unsigned long bl:6; /* Block size mask */ -} P601_BATL; - -typedef struct _BATL { /* Lower part of BAT (all except 601) */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long w:1; /* Write-thru cache */ - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded (MBZ in IBAT) */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page access protections */ -} BATL; - -typedef struct _BAT { - BATU batu; /* Upper register */ - BATL batl; /* Lower register */ -} BAT; - -typedef struct _P601_BAT { - P601_BATU batu; /* Upper register */ - P601_BATL batl; /* Lower register */ -} P601_BAT; - -#endif /* __ASSEMBLY__ */ - -/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF - -/* BAT Access Protection */ -#define BPP_XX 0x00 /* No access */ -#define BPP_RX 0x01 /* Read only */ -#define BPP_RW 0x02 /* Read/write */ - -/* Control/status registers for the MPC8xx. - * A write operation to these registers causes serialized access. - * During software tablewalk, the registers used perform mask/shift-add - * operations when written/read. A TLB entry is created when the Mx_RPN - * is written, and the contents of several registers are used to - * create the entry. - */ -#define SPRN_MI_CTR 784 /* Instruction TLB control register */ -#define MI_GPM 0x80000000 /* Set domain manager mode */ -#define MI_PPM 0x40000000 /* Set subpage protection */ -#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MI_RESETVAL 0x00000000 /* Value of register at reset */ - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define SPRN_MI_AP 786 -#define MI_Ks 0x80000000 /* Should not be set */ -#define MI_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MI_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define SPRN_MI_EPN 787 -#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MI_EVALID 0x00000200 /* Entry is valid */ -#define MI_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the instruction TLB, it contains bits that get loaded into the - * TLB entry when the MI_RPN is written. - */ -#define SPRN_MI_TWC 789 -#define MI_APG 0x000001e0 /* Access protection group (0) */ -#define MI_GUARDED 0x00000010 /* Guarded storage */ -#define MI_PSMASK 0x0000000c /* Mask of page size bits */ -#define MI_PS8MEG 0x0000000c /* 8M page size */ -#define MI_PS512K 0x00000004 /* 512K page size */ -#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MI_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the instruction TLB, using - * additional information from the MI_EPN, and MI_TWC registers. - */ -#define SPRN_MI_RPN 790 - -/* Define an RPN value for mapping kernel memory to large virtual - * pages for boot initialization. This has real page number of 0, - * large page size, shared page, cache enabled, and valid. - * Also mark all subpages valid and write access. - */ -#define MI_BOOTINIT 0x000001fd - -#define SPRN_MD_CTR 792 /* Data TLB control register */ -#define MD_GPM 0x80000000 /* Set domain manager mode */ -#define MD_PPM 0x40000000 /* Set subpage protection */ -#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ -#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ -#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MD_RESETVAL 0x04000000 /* Value of register at reset */ - -#define SPRN_M_CASID 793 /* Address space ID (context) to match */ -#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ - - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define SPRN_MD_AP 794 -#define MD_Ks 0x80000000 /* Should not be set */ -#define MD_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MD_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define SPRN_MD_EPN 795 -#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MD_EVALID 0x00000200 /* Entry is valid */ -#define MD_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* The pointer to the base address of the first level page table. - * During a software tablewalk, reading this register provides the address - * of the entry associated with MD_EPN. - */ -#define SPRN_M_TWB 796 -#define M_L1TB 0xfffff000 /* Level 1 table base address */ -#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the data TLB, it contains bits that get loaded into the TLB entry - * when the MD_RPN is written. It is also provides the hardware assist - * for finding the PTE address during software tablewalk. - */ -#define SPRN_MD_TWC 797 -#define MD_L2TB 0xfffff000 /* Level 2 table base address */ -#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ -#define MD_APG 0x000001e0 /* Access protection group (0) */ -#define MD_GUARDED 0x00000010 /* Guarded storage */ -#define MD_PSMASK 0x0000000c /* Mask of page size bits */ -#define MD_PS8MEG 0x0000000c /* 8M page size */ -#define MD_PS512K 0x00000004 /* 512K page size */ -#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MD_WT 0x00000002 /* Use writethrough page attribute */ -#define MD_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the data TLB, using - * additional information from the MD_EPN, and MD_TWC registers. - */ -#define SPRN_MD_RPN 798 - -/* This is a temporary storage register that could be used to save - * a processor working register during a tablewalk. - */ -#define SPRN_M_TW 799 - -/* - * At present, all PowerPC 400-class processors share a similar TLB - * architecture. The instruction and data sides share a unified, - * 64-entry, fully-associative TLB which is maintained totally under - * software control. In addition, the instruction side has a - * hardware-managed, 4-entry, fully- associative TLB which serves as a - * first level to the shared TLB. These two TLBs are known as the UTLB - * and ITLB, respectively. - */ - -#define PPC4XX_TLB_SIZE 64 - -/* - * TLB entries are defined by a "high" tag portion and a "low" data - * portion. On all architectures, the data portion is 32-bits. - * - * TLB entries are managed entirely under software control by reading, - * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx - * instructions. - */ - -#define TLB_LO 1 -#define TLB_HI 0 - -#define TLB_DATA TLB_LO -#define TLB_TAG TLB_HI - -/* Tag portion */ - -#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ -#define TLB_PAGESZ_MASK 0x00000380 -#define TLB_PAGESZ(x) (((x) & 0x7) << 7) -#define PAGESZ_1K 0 -#define PAGESZ_4K 1 -#define PAGESZ_16K 2 -#define PAGESZ_64K 3 -#define PAGESZ_256K 4 -#define PAGESZ_1M 5 -#define PAGESZ_4M 6 -#define PAGESZ_16M 7 -#define TLB_VALID 0x00000040 /* Entry is valid */ - -/* Data portion */ - -#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ -#define TLB_PERM_MASK 0x00000300 -#define TLB_EX 0x00000200 /* Instruction execution allowed */ -#define TLB_WR 0x00000100 /* Writes permitted */ -#define TLB_ZSEL_MASK 0x000000F0 -#define TLB_ZSEL(x) (((x) & 0xF) << 4) -#define TLB_ATTR_MASK 0x0000000F -#define TLB_W 0x00000008 /* Caching is write-through */ -#define TLB_I 0x00000004 /* Caching is inhibited */ -#define TLB_M 0x00000002 /* Memory is coherent */ -#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ - -/* - * PPC440 support - */ -#define PPC44x_MMUCR_TID 0x000000ff -#define PPC44x_MMUCR_STS 0x00010000 - -#define PPC44x_TLB_PAGEID 0 -#define PPC44x_TLB_XLAT 1 -#define PPC44x_TLB_ATTRIB 2 - -/* Page identification fields */ -#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ -#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ -#define PPC44x_TLB_TS 0x00000100 /* Translation address space */ -#define PPC44x_TLB_1K 0x00000000 /* Page sizes */ -#define PPC44x_TLB_4K 0x00000010 -#define PPC44x_TLB_16K 0x00000020 -#define PPC44x_TLB_64K 0x00000030 -#define PPC44x_TLB_256K 0x00000040 -#define PPC44x_TLB_1M 0x00000050 -#define PPC44x_TLB_16M 0x00000070 -#define PPC44x_TLB_256M 0x00000090 - -/* Translation fields */ -#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ -#define PPC44x_TLB_ERPN_MASK 0x0000000f - -/* Storage attribute and access control fields */ -#define PPC44x_TLB_ATTR_MASK 0x0000ff80 -#define PPC44x_TLB_U0 0x00008000 /* User 0 */ -#define PPC44x_TLB_U1 0x00004000 /* User 1 */ -#define PPC44x_TLB_U2 0x00002000 /* User 2 */ -#define PPC44x_TLB_U3 0x00001000 /* User 3 */ -#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ -#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ -#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ -#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ -#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */ - -#define PPC44x_TLB_PERM_MASK 0x0000003f -#define PPC44x_TLB_UX 0x00000020 /* User execution */ -#define PPC44x_TLB_UW 0x00000010 /* User write */ -#define PPC44x_TLB_UR 0x00000008 /* User read */ -#define PPC44x_TLB_SX 0x00000004 /* Super execution */ -#define PPC44x_TLB_SW 0x00000002 /* Super write */ -#define PPC44x_TLB_SR 0x00000001 /* Super read */ - -/* Book-E defined page sizes */ -#define BOOKE_PAGESZ_1K 0 -#define BOOKE_PAGESZ_4K 1 -#define BOOKE_PAGESZ_16K 2 -#define BOOKE_PAGESZ_64K 3 -#define BOOKE_PAGESZ_256K 4 -#define BOOKE_PAGESZ_1M 5 -#define BOOKE_PAGESZ_4M 6 -#define BOOKE_PAGESZ_16M 7 -#define BOOKE_PAGESZ_64M 8 -#define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1GB 10 -#define BOOKE_PAGESZ_4GB 11 -#define BOOKE_PAGESZ_16GB 12 -#define BOOKE_PAGESZ_64GB 13 -#define BOOKE_PAGESZ_256GB 14 -#define BOOKE_PAGESZ_1TB 15 - -#ifndef CONFIG_SERIAL_TEXT_DEBUG -#define PPC44x_EARLY_TLBS 1 -#else -#define PPC44x_EARLY_TLBS 2 -#endif - -/* - * Freescale Book-E MMU support - */ - -#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) -#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) -#define MAS0_NV(x) ((x) & 0x00000FFF) - -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) -#define MAS1_TS 0x00001000 -#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) - -#define MAS2_EPN 0xFFFFF000 -#define MAS2_X0 0x00000040 -#define MAS2_X1 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 - -#define MAS3_RPN 0xFFFFF000 -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 - -#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) -#define MAS4_TIDDSEL 0x000F0000 -#define MAS4_TSIZED(x) MAS1_TSIZE(x) -#define MAS4_X0D 0x00000040 -#define MAS4_X1D 0x00000020 -#define MAS4_WD 0x00000010 -#define MAS4_ID 0x00000008 -#define MAS4_MD 0x00000004 -#define MAS4_GD 0x00000002 -#define MAS4_ED 0x00000001 - -#define MAS6_SPID0 0x3FFF0000 -#define MAS6_SPID1 0x00007FFE -#define MAS6_SAS 0x00000001 -#define MAS6_SPID MAS6_SPID0 - -#define MAS7_RPN 0xFFFFFFFF - -#endif /* _PPC_MMU_H_ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h deleted file mode 100644 index 9f097e25b169..000000000000 --- a/include/asm-ppc/mmu_context.h +++ /dev/null @@ -1,198 +0,0 @@ -#ifdef __KERNEL__ -#ifndef __PPC_MMU_CONTEXT_H -#define __PPC_MMU_CONTEXT_H - -#include <linux/bitops.h> - -#include <asm/atomic.h> -#include <asm/mmu.h> -#include <asm/cputable.h> -#include <asm-generic/mm_hooks.h> - -/* - * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs - * (virtual segment identifiers) for each context. Although the - * hardware supports 24-bit VSIDs, and thus >1 million contexts, - * we only use 32,768 of them. That is ample, since there can be - * at most around 30,000 tasks in the system anyway, and it means - * that we can use a bitmap to indicate which contexts are in use. - * Using a bitmap means that we entirely avoid all of the problems - * that we used to have when the context number overflowed, - * particularly on SMP systems. - * -- paulus. - */ - -/* - * This function defines the mapping from contexts to VSIDs (virtual - * segment IDs). We use a skew on both the context and the high 4 bits - * of the 32-bit virtual address (the "effective segment ID") in order - * to spread out the entries in the MMU hash table. Note, if this - * function is changed then arch/ppc/mm/hashtable.S will have to be - * changed to correspond. - */ -#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \ - & 0xffffff) - -/* - The MPC8xx has only 16 contexts. We rotate through them on each - task switch. A better way would be to keep track of tasks that - own contexts, and implement an LRU usage. That way very active - tasks don't always have to pay the TLB reload overhead. The - kernel pages are mapped shared, so the kernel can run on behalf - of any task that makes a kernel entry. Shared does not mean they - are not protected, just that the ASID comparison is not performed. - -- Dan - - The IBM4xx has 256 contexts, so we can just rotate through these - as a way of "switching" contexts. If the TID of the TLB is zero, - the PID/TID comparison is disabled, so we can use a TID of zero - to represent all kernel pages as shared among all contexts. - -- Dan - */ - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -#ifdef CONFIG_8xx -#define NO_CONTEXT 16 -#define LAST_CONTEXT 15 -#define FIRST_CONTEXT 0 - -#elif defined(CONFIG_4xx) -#define NO_CONTEXT 256 -#define LAST_CONTEXT 255 -#define FIRST_CONTEXT 1 - -#else - -/* PPC 6xx, 7xx CPUs */ -#define NO_CONTEXT ((unsigned long) -1) -#define LAST_CONTEXT 32767 -#define FIRST_CONTEXT 1 -#endif - -/* - * Set the current MMU context. - * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by - * loading up the segment registers for the user part of the address space. - * - * Since the PGD is immediately available, it is much faster to simply - * pass this along as a second parameter, which is required for 8xx and - * can be used for debugging on all processors (if you happen to have - * an Abatron). - */ -extern void set_context(unsigned long contextid, pgd_t *pgd); - -/* - * Bitmap of contexts in use. - * The size of this bitmap is LAST_CONTEXT + 1 bits. - */ -extern unsigned long context_map[]; - -/* - * This caches the next context number that we expect to be free. - * Its use is an optimization only, we can't rely on this context - * number to be free, but it usually will be. - */ -extern unsigned long next_mmu_context; - -/* - * If we don't have sufficient contexts to give one to every task - * that could be in the system, we need to be able to steal contexts. - * These variables support that. - */ -#if LAST_CONTEXT < 30000 -#define FEW_CONTEXTS 1 -extern atomic_t nr_free_contexts; -extern struct mm_struct *context_mm[LAST_CONTEXT+1]; -extern void steal_context(void); -#endif - -/* - * Get a new mmu context for the address space described by `mm'. - */ -static inline void get_mmu_context(struct mm_struct *mm) -{ - unsigned long ctx; - - if (mm->context.id != NO_CONTEXT) - return; -#ifdef FEW_CONTEXTS - while (atomic_dec_if_positive(&nr_free_contexts) < 0) - steal_context(); -#endif - ctx = next_mmu_context; - while (test_and_set_bit(ctx, context_map)) { - ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); - if (ctx > LAST_CONTEXT) - ctx = 0; - } - next_mmu_context = (ctx + 1) & LAST_CONTEXT; - mm->context.id = ctx; -#ifdef FEW_CONTEXTS - context_mm[ctx] = mm; -#endif -} - -/* - * Set up the context for a new address space. - */ -static inline int init_new_context(struct task_struct *t, struct mm_struct *mm) -{ - mm->context.id = NO_CONTEXT; - mm->context.vdso_base = 0; - return 0; -} - -/* - * We're finished using the context for an address space. - */ -static inline void destroy_context(struct mm_struct *mm) -{ - preempt_disable(); - if (mm->context.id != NO_CONTEXT) { - clear_bit(mm->context.id, context_map); - mm->context.id = NO_CONTEXT; -#ifdef FEW_CONTEXTS - atomic_inc(&nr_free_contexts); -#endif - } - preempt_enable(); -} - -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ -#ifdef CONFIG_ALTIVEC - if (cpu_has_feature(CPU_FTR_ALTIVEC)) - asm volatile ("dssall;\n" -#ifndef CONFIG_POWER4 - "sync;\n" /* G4 needs a sync here, G5 apparently not */ -#endif - : : ); -#endif /* CONFIG_ALTIVEC */ - - tsk->thread.pgdir = next->pgd; - - /* No need to flush userspace segments if the mm doesnt change */ - if (prev == next) - return; - - /* Setup new userspace context */ - get_mmu_context(next); - set_context(next->context.id, next->pgd); -} - -#define deactivate_mm(tsk,mm) do { } while (0) - -/* - * After we have set current->mm to a new value, this activates - * the context for the new mm so we see the new mappings. - */ -#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current) - -extern void mmu_context_init(void); - -#endif /* __PPC_MMU_CONTEXT_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h deleted file mode 100644 index b30a6a3b5bd2..000000000000 --- a/include/asm-ppc/mpc10x.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem - * ctlr/EPIC/etc. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __PPC_KERNEL_MPC10X_H -#define __PPC_KERNEL_MPC10X_H - -#include <linux/pci_ids.h> -#include <asm/pci-bridge.h> - -/* - * The values here don't completely map everything but should work in most - * cases. - * - * MAP A (PReP Map) - * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff - * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff - * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 - * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) - * - * MAP B (CHRP Map) - * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff - * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff - * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 - * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) - */ - -/* - * Define the vendor/device IDs for the various bridges--should be added to - * <linux/pci_ids.h> - */ -#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ - PCI_VENDOR_ID_MOTOROLA) -#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) -#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) -#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) - -/* Define the type of map to use */ -#define MPC10X_MEM_MAP_A 1 -#define MPC10X_MEM_MAP_B 2 - -/* Map A (PReP Map) Defines */ -#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 -#define MPC10X_MAPA_CNFG_DATA 0x80000cfc - -#define MPC10X_MAPA_ISA_IO_BASE 0x80000000 -#define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 -#define MPC10X_MAPA_DRAM_OFFSET 0x80000000 - -#define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0 -#define MPC10X_MAPA_PCI_IO_START 0x00000000 -#define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) -#define MPC10X_MAPA_PCI_MEM_START 0x00000000 -#define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) - -#define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ - MPC10X_MAPA_PCI_MEM_START) - -/* Map B (CHRP Map) Defines */ -#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 -#define MPC10X_MAPB_CNFG_DATA 0xfee00000 - -#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 -#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 -#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 - -#define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000 -#define MPC10X_MAPB_PCI_IO_START 0x00000000 -#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) -#define MPC10X_MAPB_PCI_MEM_START 0x80000000 -#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) - -#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ - MPC10X_MAPB_PCI_MEM_START) - -/* Set hose members to values appropriate for the mem map used */ -#define MPC10X_SETUP_HOSE(hose, map) { \ - (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET; \ - (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START; \ - (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END; \ - (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START; \ - (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END; \ - (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE; \ -} - - -/* Miscellaneous Configuration register offsets */ -#define MPC10X_CFG_PIR_REG 0x09 -#define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 -#define MPC10X_CFG_PIR_AGENT 0x01 - -#define MPC10X_CFG_EUMBBAR 0x78 - -#define MPC10X_CFG_PICR1_REG 0xa8 -#define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 -#define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 -#define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 -#define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 -#define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 - -#define MPC10X_CFG_PICR2_REG 0xac -#define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 - -#define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 -#define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ -#define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ -#define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ -#define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ -#define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ - -/* Define offsets for the memory controller registers in the config space */ -#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ -#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ -#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ -#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ - -#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ -#define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ -#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ -#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ - -#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 - -/* Define some offset in the EUMB */ -#define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ - -#define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ -#define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ -#define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ -#define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ -#define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ -#define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ -#define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ -#define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ -#define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ -#define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ -#define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ -#define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ -#define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ -#define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ -#define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ -#define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ - -/* - * Define some recommended places to put the EUMB regs. - * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff. - */ -extern unsigned long ioremap_base; -#define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE) -#define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE - -enum ppc_sys_devices { - MPC10X_IIC1, - MPC10X_DMA0, - MPC10X_DMA1, - MPC10X_UART0, - MPC10X_UART1, - NUM_PPC_SYS_DEVS, -}; - -int mpc10x_bridge_init(struct pci_controller *hose, - uint current_map, - uint new_map, - uint phys_eumb_base); -unsigned long mpc10x_get_mem_size(uint mem_map); -int mpc10x_enable_store_gathering(struct pci_controller *hose); -int mpc10x_disable_store_gathering(struct pci_controller *hose); - -/* For MPC107 boards that use the built-in openpic */ -void mpc10x_set_openpic(void); - -#endif /* __PPC_KERNEL_MPC10X_H */ diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h deleted file mode 100644 index d9d21aa68ba3..000000000000 --- a/include/asm-ppc/mpc52xx.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * include/asm-ppc/mpc52xx.h - * - * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips - * May need to be cleaned as the port goes on ... - * - * - * Maintainer : Sylvain Munaut <tnt@246tNt.com> - * - * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> - * for the 2.4 kernel. - * - * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com> - * Copyright (C) 2003 MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __ASM_MPC52xx_H__ -#define __ASM_MPC52xx_H__ - -#ifndef __ASSEMBLY__ -#include <asm/ppcboot.h> -#include <asm/types.h> - -struct pt_regs; -#endif /* __ASSEMBLY__ */ - - -/* ======================================================================== */ -/* PPC Sys devices definition */ -/* ======================================================================== */ - -enum ppc_sys_devices { - MPC52xx_MSCAN1, - MPC52xx_MSCAN2, - MPC52xx_SPI, - MPC52xx_USB, - MPC52xx_BDLC, - MPC52xx_PSC1, - MPC52xx_PSC2, - MPC52xx_PSC3, - MPC52xx_PSC4, - MPC52xx_PSC5, - MPC52xx_PSC6, - MPC52xx_FEC, - MPC52xx_ATA, - MPC52xx_I2C1, - MPC52xx_I2C2, - NUM_PPC_SYS_DEVS, -}; - - -/* ======================================================================== */ -/* Main registers/struct addresses */ -/* ======================================================================== */ - -/* MBAR position */ -#define MPC52xx_MBAR 0xf0000000 /* Phys address */ -#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */ -#define MPC52xx_MBAR_SIZE 0x00010000 - -#define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x))) -#define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x))) - -/* Registers zone offset/size */ -#define MPC52xx_MMAP_CTL_OFFSET 0x0000 -#define MPC52xx_MMAP_CTL_SIZE 0x068 -#define MPC52xx_SDRAM_OFFSET 0x0100 -#define MPC52xx_SDRAM_SIZE 0x010 -#define MPC52xx_CDM_OFFSET 0x0200 -#define MPC52xx_CDM_SIZE 0x038 -#define MPC52xx_INTR_OFFSET 0x0500 -#define MPC52xx_INTR_SIZE 0x04c -#define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4)) -#define MPC52xx_GPT_SIZE 0x010 -#define MPC52xx_RTC_OFFSET 0x0800 -#define MPC52xx_RTC_SIZE 0x024 -#define MPC52xx_GPIO_OFFSET 0x0b00 -#define MPC52xx_GPIO_SIZE 0x040 -#define MPC52xx_GPIO_WKUP_OFFSET 0x0c00 -#define MPC52xx_GPIO_WKUP_SIZE 0x028 -#define MPC52xx_PCI_OFFSET 0x0d00 -#define MPC52xx_PCI_SIZE 0x100 -#define MPC52xx_SDMA_OFFSET 0x1200 -#define MPC52xx_SDMA_SIZE 0x100 -#define MPC52xx_XLB_OFFSET 0x1f00 -#define MPC52xx_XLB_SIZE 0x100 -#define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00) -#define MPC52xx_PSC_SIZE 0x0a0 - -/* SRAM used for SDMA */ -#define MPC52xx_SRAM_OFFSET 0x8000 -#define MPC52xx_SRAM_SIZE 0x4000 - - -/* ======================================================================== */ -/* IRQ mapping */ -/* ======================================================================== */ -/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change - * this - */ - -#define MPC52xx_CRIT_IRQ_NUM 4 -#define MPC52xx_MAIN_IRQ_NUM 17 -#define MPC52xx_SDMA_IRQ_NUM 17 -#define MPC52xx_PERP_IRQ_NUM 23 - -#define MPC52xx_CRIT_IRQ_BASE 1 -#define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM) -#define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM) -#define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM) - -#define MPC52xx_IRQ0 (MPC52xx_CRIT_IRQ_BASE + 0) -#define MPC52xx_SLICE_TIMER_0_IRQ (MPC52xx_CRIT_IRQ_BASE + 1) -#define MPC52xx_HI_INT_IRQ (MPC52xx_CRIT_IRQ_BASE + 2) -#define MPC52xx_CCS_IRQ (MPC52xx_CRIT_IRQ_BASE + 3) - -#define MPC52xx_IRQ1 (MPC52xx_MAIN_IRQ_BASE + 1) -#define MPC52xx_IRQ2 (MPC52xx_MAIN_IRQ_BASE + 2) -#define MPC52xx_IRQ3 (MPC52xx_MAIN_IRQ_BASE + 3) - -#define MPC52xx_SDMA_IRQ (MPC52xx_PERP_IRQ_BASE + 0) -#define MPC52xx_PSC1_IRQ (MPC52xx_PERP_IRQ_BASE + 1) -#define MPC52xx_PSC2_IRQ (MPC52xx_PERP_IRQ_BASE + 2) -#define MPC52xx_PSC3_IRQ (MPC52xx_PERP_IRQ_BASE + 3) -#define MPC52xx_PSC6_IRQ (MPC52xx_PERP_IRQ_BASE + 4) -#define MPC52xx_IRDA_IRQ (MPC52xx_PERP_IRQ_BASE + 4) -#define MPC52xx_FEC_IRQ (MPC52xx_PERP_IRQ_BASE + 5) -#define MPC52xx_USB_IRQ (MPC52xx_PERP_IRQ_BASE + 6) -#define MPC52xx_ATA_IRQ (MPC52xx_PERP_IRQ_BASE + 7) -#define MPC52xx_PCI_CNTRL_IRQ (MPC52xx_PERP_IRQ_BASE + 8) -#define MPC52xx_PCI_SCIRX_IRQ (MPC52xx_PERP_IRQ_BASE + 9) -#define MPC52xx_PCI_SCITX_IRQ (MPC52xx_PERP_IRQ_BASE + 10) -#define MPC52xx_PSC4_IRQ (MPC52xx_PERP_IRQ_BASE + 11) -#define MPC52xx_PSC5_IRQ (MPC52xx_PERP_IRQ_BASE + 12) -#define MPC52xx_SPI_MODF_IRQ (MPC52xx_PERP_IRQ_BASE + 13) -#define MPC52xx_SPI_SPIF_IRQ (MPC52xx_PERP_IRQ_BASE + 14) -#define MPC52xx_I2C1_IRQ (MPC52xx_PERP_IRQ_BASE + 15) -#define MPC52xx_I2C2_IRQ (MPC52xx_PERP_IRQ_BASE + 16) -#define MPC52xx_MSCAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17) -#define MPC52xx_MSCAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18) -#define MPC52xx_IR_RX_IRQ (MPC52xx_PERP_IRQ_BASE + 19) -#define MPC52xx_IR_TX_IRQ (MPC52xx_PERP_IRQ_BASE + 20) -#define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21) -#define MPC52xx_BDLC_IRQ (MPC52xx_PERP_IRQ_BASE + 22) - - - -/* ======================================================================== */ -/* Structures mapping of some unit register set */ -/* ======================================================================== */ - -#ifndef __ASSEMBLY__ - -/* Memory Mapping Control */ -struct mpc52xx_mmap_ctl { - u32 mbar; /* MMAP_CTRL + 0x00 */ - - u32 cs0_start; /* MMAP_CTRL + 0x04 */ - u32 cs0_stop; /* MMAP_CTRL + 0x08 */ - u32 cs1_start; /* MMAP_CTRL + 0x0c */ - u32 cs1_stop; /* MMAP_CTRL + 0x10 */ - u32 cs2_start; /* MMAP_CTRL + 0x14 */ - u32 cs2_stop; /* MMAP_CTRL + 0x18 */ - u32 cs3_start; /* MMAP_CTRL + 0x1c */ - u32 cs3_stop; /* MMAP_CTRL + 0x20 */ - u32 cs4_start; /* MMAP_CTRL + 0x24 */ - u32 cs4_stop; /* MMAP_CTRL + 0x28 */ - u32 cs5_start; /* MMAP_CTRL + 0x2c */ - u32 cs5_stop; /* MMAP_CTRL + 0x30 */ - - u32 sdram0; /* MMAP_CTRL + 0x34 */ - u32 sdram1; /* MMAP_CTRL + 0X38 */ - - u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */ - - u32 boot_start; /* MMAP_CTRL + 0x4c */ - u32 boot_stop; /* MMAP_CTRL + 0x50 */ - - u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */ - - u32 cs6_start; /* MMAP_CTRL + 0x58 */ - u32 cs6_stop; /* MMAP_CTRL + 0x5c */ - u32 cs7_start; /* MMAP_CTRL + 0x60 */ - u32 cs7_stop; /* MMAP_CTRL + 0x64 */ -}; - -/* SDRAM control */ -struct mpc52xx_sdram { - u32 mode; /* SDRAM + 0x00 */ - u32 ctrl; /* SDRAM + 0x04 */ - u32 config1; /* SDRAM + 0x08 */ - u32 config2; /* SDRAM + 0x0c */ -}; - -/* Interrupt controller */ -struct mpc52xx_intr { - u32 per_mask; /* INTR + 0x00 */ - u32 per_pri1; /* INTR + 0x04 */ - u32 per_pri2; /* INTR + 0x08 */ - u32 per_pri3; /* INTR + 0x0c */ - u32 ctrl; /* INTR + 0x10 */ - u32 main_mask; /* INTR + 0x14 */ - u32 main_pri1; /* INTR + 0x18 */ - u32 main_pri2; /* INTR + 0x1c */ - u32 reserved1; /* INTR + 0x20 */ - u32 enc_status; /* INTR + 0x24 */ - u32 crit_status; /* INTR + 0x28 */ - u32 main_status; /* INTR + 0x2c */ - u32 per_status; /* INTR + 0x30 */ - u32 reserved2; /* INTR + 0x34 */ - u32 per_error; /* INTR + 0x38 */ -}; - -/* SDMA */ -struct mpc52xx_sdma { - u32 taskBar; /* SDMA + 0x00 */ - u32 currentPointer; /* SDMA + 0x04 */ - u32 endPointer; /* SDMA + 0x08 */ - u32 variablePointer;/* SDMA + 0x0c */ - - u8 IntVect1; /* SDMA + 0x10 */ - u8 IntVect2; /* SDMA + 0x11 */ - u16 PtdCntrl; /* SDMA + 0x12 */ - - u32 IntPend; /* SDMA + 0x14 */ - u32 IntMask; /* SDMA + 0x18 */ - - u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ - - u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */ - - u32 cReqSelect; /* SDMA + 0x5c */ - u32 task_size0; /* SDMA + 0x60 */ - u32 task_size1; /* SDMA + 0x64 */ - u32 MDEDebug; /* SDMA + 0x68 */ - u32 ADSDebug; /* SDMA + 0x6c */ - u32 Value1; /* SDMA + 0x70 */ - u32 Value2; /* SDMA + 0x74 */ - u32 Control; /* SDMA + 0x78 */ - u32 Status; /* SDMA + 0x7c */ - u32 PTDDebug; /* SDMA + 0x80 */ -}; - -/* GPT */ -struct mpc52xx_gpt { - u32 mode; /* GPTx + 0x00 */ - u32 count; /* GPTx + 0x04 */ - u32 pwm; /* GPTx + 0x08 */ - u32 status; /* GPTx + 0X0c */ -}; - -/* RTC */ -struct mpc52xx_rtc { - u32 time_set; /* RTC + 0x00 */ - u32 date_set; /* RTC + 0x04 */ - u32 stopwatch; /* RTC + 0x08 */ - u32 int_enable; /* RTC + 0x0c */ - u32 time; /* RTC + 0x10 */ - u32 date; /* RTC + 0x14 */ - u32 stopwatch_intr; /* RTC + 0x18 */ - u32 bus_error; /* RTC + 0x1c */ - u32 dividers; /* RTC + 0x20 */ -}; - -/* GPIO */ -struct mpc52xx_gpio { - u32 port_config; /* GPIO + 0x00 */ - u32 simple_gpioe; /* GPIO + 0x04 */ - u32 simple_ode; /* GPIO + 0x08 */ - u32 simple_ddr; /* GPIO + 0x0c */ - u32 simple_dvo; /* GPIO + 0x10 */ - u32 simple_ival; /* GPIO + 0x14 */ - u8 outo_gpioe; /* GPIO + 0x18 */ - u8 reserved1[3]; /* GPIO + 0x19 */ - u8 outo_dvo; /* GPIO + 0x1c */ - u8 reserved2[3]; /* GPIO + 0x1d */ - u8 sint_gpioe; /* GPIO + 0x20 */ - u8 reserved3[3]; /* GPIO + 0x21 */ - u8 sint_ode; /* GPIO + 0x24 */ - u8 reserved4[3]; /* GPIO + 0x25 */ - u8 sint_ddr; /* GPIO + 0x28 */ - u8 reserved5[3]; /* GPIO + 0x29 */ - u8 sint_dvo; /* GPIO + 0x2c */ - u8 reserved6[3]; /* GPIO + 0x2d */ - u8 sint_inten; /* GPIO + 0x30 */ - u8 reserved7[3]; /* GPIO + 0x31 */ - u16 sint_itype; /* GPIO + 0x34 */ - u16 reserved8; /* GPIO + 0x36 */ - u8 gpio_control; /* GPIO + 0x38 */ - u8 reserved9[3]; /* GPIO + 0x39 */ - u8 sint_istat; /* GPIO + 0x3c */ - u8 sint_ival; /* GPIO + 0x3d */ - u8 bus_errs; /* GPIO + 0x3e */ - u8 reserved10; /* GPIO + 0x3f */ -}; - -#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4 -#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5 -#define MPC52xx_GPIO_PCI_DIS (1<<15) - -/* GPIO with WakeUp*/ -struct mpc52xx_gpio_wkup { - u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */ - u8 reserved1[3]; /* GPIO_WKUP + 0x03 */ - u8 wkup_ode; /* GPIO_WKUP + 0x04 */ - u8 reserved2[3]; /* GPIO_WKUP + 0x05 */ - u8 wkup_ddr; /* GPIO_WKUP + 0x08 */ - u8 reserved3[3]; /* GPIO_WKUP + 0x09 */ - u8 wkup_dvo; /* GPIO_WKUP + 0x0C */ - u8 reserved4[3]; /* GPIO_WKUP + 0x0D */ - u8 wkup_inten; /* GPIO_WKUP + 0x10 */ - u8 reserved5[3]; /* GPIO_WKUP + 0x11 */ - u8 wkup_iinten; /* GPIO_WKUP + 0x14 */ - u8 reserved6[3]; /* GPIO_WKUP + 0x15 */ - u16 wkup_itype; /* GPIO_WKUP + 0x18 */ - u8 reserved7[2]; /* GPIO_WKUP + 0x1A */ - u8 wkup_maste; /* GPIO_WKUP + 0x1C */ - u8 reserved8[3]; /* GPIO_WKUP + 0x1D */ - u8 wkup_ival; /* GPIO_WKUP + 0x20 */ - u8 reserved9[3]; /* GPIO_WKUP + 0x21 */ - u8 wkup_istat; /* GPIO_WKUP + 0x24 */ - u8 reserved10[3]; /* GPIO_WKUP + 0x25 */ -}; - -/* XLB Bus control */ -struct mpc52xx_xlb { - u8 reserved[0x40]; - u32 config; /* XLB + 0x40 */ - u32 version; /* XLB + 0x44 */ - u32 status; /* XLB + 0x48 */ - u32 int_enable; /* XLB + 0x4c */ - u32 addr_capture; /* XLB + 0x50 */ - u32 bus_sig_capture; /* XLB + 0x54 */ - u32 addr_timeout; /* XLB + 0x58 */ - u32 data_timeout; /* XLB + 0x5c */ - u32 bus_act_timeout; /* XLB + 0x60 */ - u32 master_pri_enable; /* XLB + 0x64 */ - u32 master_priority; /* XLB + 0x68 */ - u32 base_address; /* XLB + 0x6c */ - u32 snoop_window; /* XLB + 0x70 */ -}; - -#define MPC52xx_XLB_CFG_PLDIS (1 << 31) -#define MPC52xx_XLB_CFG_SNOOP (1 << 15) - -/* Clock Distribution control */ -struct mpc52xx_cdm { - u32 jtag_id; /* CDM + 0x00 reg0 read only */ - u32 rstcfg; /* CDM + 0x04 reg1 read only */ - u32 breadcrumb; /* CDM + 0x08 reg2 */ - - u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */ - u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */ - u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */ - u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */ - - u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */ - u8 fd_enable; /* CDM + 0x11 reg4 byte1 */ - u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */ - - u32 clk_enables; /* CDM + 0x14 reg5 */ - - u8 osc_disable; /* CDM + 0x18 reg6 byte0 */ - u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */ - - u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */ - u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */ - u8 reserved1; /* CDM + 0x1e reg7 byte2 */ - u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */ - - u8 soft_reset; /* CDM + 0x20 u8 byte0 */ - u8 no_ckstp; /* CDM + 0x21 u8 byte0 */ - u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */ - - u8 pll_lock; /* CDM + 0x24 reg9 byte0 */ - u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */ - u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */ - u8 reserved3; /* CDM + 0x27 reg9 byte3 */ - - u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */ - u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */ - - u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */ - u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */ - - u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */ - u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */ - - u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */ - u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */ -}; - -#endif /* __ASSEMBLY__ */ - - -/* ========================================================================= */ -/* Prototypes for MPC52xx syslib */ -/* ========================================================================= */ - -#ifndef __ASSEMBLY__ - -extern void mpc52xx_init_irq(void); -extern int mpc52xx_get_irq(void); - -extern unsigned long mpc52xx_find_end_of_memory(void); -extern void mpc52xx_set_bat(void); -extern void mpc52xx_map_io(void); -extern void mpc52xx_restart(char *cmd); -extern void mpc52xx_halt(void); -extern void mpc52xx_power_off(void); -extern void mpc52xx_progress(char *s, unsigned short hex); -extern void mpc52xx_calibrate_decr(void); - -extern void mpc52xx_find_bridges(void); - -extern void mpc52xx_setup_cpu(void); - - - - /* Matching of PSC function */ -struct mpc52xx_psc_func { - int id; - char *func; -}; - -extern int mpc52xx_match_psc_function(int psc_idx, const char *func); -extern struct mpc52xx_psc_func mpc52xx_psc_functions[]; - /* This array is to be defined in platform file */ - -#endif /* __ASSEMBLY__ */ - - -/* ========================================================================= */ -/* Platform configuration */ -/* ========================================================================= */ - -/* The U-Boot platform information struct */ -extern bd_t __res; - -/* Platform options */ -#if defined(CONFIG_LITE5200) -#include <platforms/lite5200.h> -#endif - - -#endif /* __ASM_MPC52xx_H__ */ diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h deleted file mode 100644 index 39fcd02cd4e8..000000000000 --- a/include/asm-ppc/mpc52xx_psc.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * include/asm-ppc/mpc52xx_psc.h - * - * Definitions of consts/structs to drive the Freescale MPC52xx OnChip - * PSCs. Theses are shared between multiple drivers since a PSC can be - * UART, AC97, IR, I2S, ... So this header is in asm-ppc. - * - * - * Maintainer : Sylvain Munaut <tnt@246tNt.com> - * - * Based/Extracted from some header of the 2.4 originally written by - * Dale Farnsworth <dfarnsworth@mvista.com> - * - * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> - * Copyright (C) 2003 MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __ASM_MPC52xx_PSC_H__ -#define __ASM_MPC52xx_PSC_H__ - -#include <asm/types.h> - -/* Max number of PSCs */ -#define MPC52xx_PSC_MAXNUM 6 - -/* Programmable Serial Controller (PSC) status register bits */ -#define MPC52xx_PSC_SR_UNEX_RX 0x0001 -#define MPC52xx_PSC_SR_DATA_VAL 0x0002 -#define MPC52xx_PSC_SR_DATA_OVR 0x0004 -#define MPC52xx_PSC_SR_CMDSEND 0x0008 -#define MPC52xx_PSC_SR_CDE 0x0080 -#define MPC52xx_PSC_SR_RXRDY 0x0100 -#define MPC52xx_PSC_SR_RXFULL 0x0200 -#define MPC52xx_PSC_SR_TXRDY 0x0400 -#define MPC52xx_PSC_SR_TXEMP 0x0800 -#define MPC52xx_PSC_SR_OE 0x1000 -#define MPC52xx_PSC_SR_PE 0x2000 -#define MPC52xx_PSC_SR_FE 0x4000 -#define MPC52xx_PSC_SR_RB 0x8000 - -/* PSC Command values */ -#define MPC52xx_PSC_RX_ENABLE 0x0001 -#define MPC52xx_PSC_RX_DISABLE 0x0002 -#define MPC52xx_PSC_TX_ENABLE 0x0004 -#define MPC52xx_PSC_TX_DISABLE 0x0008 -#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010 -#define MPC52xx_PSC_RST_RX 0x0020 -#define MPC52xx_PSC_RST_TX 0x0030 -#define MPC52xx_PSC_RST_ERR_STAT 0x0040 -#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050 -#define MPC52xx_PSC_START_BRK 0x0060 -#define MPC52xx_PSC_STOP_BRK 0x0070 - -/* PSC TxRx FIFO status bits */ -#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040 -#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020 -#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010 -#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008 -#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004 -#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002 -#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 - -/* PSC interrupt mask bits */ -#define MPC52xx_PSC_IMR_TXRDY 0x0100 -#define MPC52xx_PSC_IMR_RXRDY 0x0200 -#define MPC52xx_PSC_IMR_DB 0x0400 -#define MPC52xx_PSC_IMR_IPC 0x8000 - -/* PSC input port change bit */ -#define MPC52xx_PSC_CTS 0x01 -#define MPC52xx_PSC_DCD 0x02 -#define MPC52xx_PSC_D_CTS 0x10 -#define MPC52xx_PSC_D_DCD 0x20 - -/* PSC mode fields */ -#define MPC52xx_PSC_MODE_5_BITS 0x00 -#define MPC52xx_PSC_MODE_6_BITS 0x01 -#define MPC52xx_PSC_MODE_7_BITS 0x02 -#define MPC52xx_PSC_MODE_8_BITS 0x03 -#define MPC52xx_PSC_MODE_BITS_MASK 0x03 -#define MPC52xx_PSC_MODE_PAREVEN 0x00 -#define MPC52xx_PSC_MODE_PARODD 0x04 -#define MPC52xx_PSC_MODE_PARFORCE 0x08 -#define MPC52xx_PSC_MODE_PARNONE 0x10 -#define MPC52xx_PSC_MODE_ERR 0x20 -#define MPC52xx_PSC_MODE_FFULL 0x40 -#define MPC52xx_PSC_MODE_RXRTS 0x80 - -#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 -#define MPC52xx_PSC_MODE_ONE_STOP 0x07 -#define MPC52xx_PSC_MODE_TWO_STOP 0x0f - -#define MPC52xx_PSC_RFNUM_MASK 0x01ff - - -/* Structure of the hardware registers */ -struct mpc52xx_psc { - u8 mode; /* PSC + 0x00 */ - u8 reserved0[3]; - union { /* PSC + 0x04 */ - u16 status; - u16 clock_select; - } sr_csr; -#define mpc52xx_psc_status sr_csr.status -#define mpc52xx_psc_clock_select sr_csr.clock_select - u16 reserved1; - u8 command; /* PSC + 0x08 */ - u8 reserved2[3]; - union { /* PSC + 0x0c */ - u8 buffer_8; - u16 buffer_16; - u32 buffer_32; - } buffer; -#define mpc52xx_psc_buffer_8 buffer.buffer_8 -#define mpc52xx_psc_buffer_16 buffer.buffer_16 -#define mpc52xx_psc_buffer_32 buffer.buffer_32 - union { /* PSC + 0x10 */ - u8 ipcr; - u8 acr; - } ipcr_acr; -#define mpc52xx_psc_ipcr ipcr_acr.ipcr -#define mpc52xx_psc_acr ipcr_acr.acr - u8 reserved3[3]; - union { /* PSC + 0x14 */ - u16 isr; - u16 imr; - } isr_imr; -#define mpc52xx_psc_isr isr_imr.isr -#define mpc52xx_psc_imr isr_imr.imr - u16 reserved4; - u8 ctur; /* PSC + 0x18 */ - u8 reserved5[3]; - u8 ctlr; /* PSC + 0x1c */ - u8 reserved6[3]; - u32 ccr; /* PSC + 0x20 */ - u32 ac97_slots; /* PSC + 0x24 */ - u32 ac97_cmd; /* PSC + 0x28 */ - u32 ac97_data; /* PSC + 0x2c */ - u8 ivr; /* PSC + 0x30 */ - u8 reserved8[3]; - u8 ip; /* PSC + 0x34 */ - u8 reserved9[3]; - u8 op1; /* PSC + 0x38 */ - u8 reserved10[3]; - u8 op0; /* PSC + 0x3c */ - u8 reserved11[3]; - u32 sicr; /* PSC + 0x40 */ - u8 ircr1; /* PSC + 0x44 */ - u8 reserved13[3]; - u8 ircr2; /* PSC + 0x44 */ - u8 reserved14[3]; - u8 irsdr; /* PSC + 0x4c */ - u8 reserved15[3]; - u8 irmdr; /* PSC + 0x50 */ - u8 reserved16[3]; - u8 irfdr; /* PSC + 0x54 */ - u8 reserved17[3]; -}; - -struct mpc52xx_psc_fifo { - u16 rfnum; /* PSC + 0x58 */ - u16 reserved18; - u16 tfnum; /* PSC + 0x5c */ - u16 reserved19; - u32 rfdata; /* PSC + 0x60 */ - u16 rfstat; /* PSC + 0x64 */ - u16 reserved20; - u8 rfcntl; /* PSC + 0x68 */ - u8 reserved21[5]; - u16 rfalarm; /* PSC + 0x6e */ - u16 reserved22; - u16 rfrptr; /* PSC + 0x72 */ - u16 reserved23; - u16 rfwptr; /* PSC + 0x76 */ - u16 reserved24; - u16 rflrfptr; /* PSC + 0x7a */ - u16 reserved25; - u16 rflwfptr; /* PSC + 0x7e */ - u32 tfdata; /* PSC + 0x80 */ - u16 tfstat; /* PSC + 0x84 */ - u16 reserved26; - u8 tfcntl; /* PSC + 0x88 */ - u8 reserved27[5]; - u16 tfalarm; /* PSC + 0x8e */ - u16 reserved28; - u16 tfrptr; /* PSC + 0x92 */ - u16 reserved29; - u16 tfwptr; /* PSC + 0x96 */ - u16 reserved30; - u16 tflrfptr; /* PSC + 0x9a */ - u16 reserved31; - u16 tflwfptr; /* PSC + 0x9e */ -}; - - -#endif /* __ASM_MPC52xx_PSC_H__ */ diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h deleted file mode 100644 index 402ba15c2e80..000000000000 --- a/include/asm-ppc/mpc8260.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Since there are many different boards and no standard configuration, - * we have a unique include file for each. Rather than change every - * file that has to include MPC8260 configuration, they all include - * this one and the configuration switching is done here. - */ -#ifdef __KERNEL__ -#ifndef __ASM_PPC_MPC8260_H__ -#define __ASM_PPC_MPC8260_H__ - - -#ifdef CONFIG_8260 - -#ifdef CONFIG_EST8260 -#include <platforms/est8260.h> -#endif - -#ifdef CONFIG_SBC82xx -#include <platforms/sbc82xx.h> -#endif - -#ifdef CONFIG_SBS8260 -#include <platforms/sbs8260.h> -#endif - -#ifdef CONFIG_RPX8260 -#include <platforms/rpx8260.h> -#endif - -#ifdef CONFIG_WILLOW -#include <platforms/willow.h> -#endif - -#ifdef CONFIG_TQM8260 -#include <platforms/tqm8260.h> -#endif - -#ifdef CONFIG_PCI_8260 -#include <syslib/m82xx_pci.h> -#endif - -/* Make sure the memory translation stuff is there if PCI not used. - */ -#ifndef _IO_BASE -#define _IO_BASE 0 -#endif - -#ifndef _ISA_MEM_BASE -#define _ISA_MEM_BASE 0 -#endif - -#ifndef PCI_DRAM_OFFSET -#define PCI_DRAM_OFFSET 0 -#endif - -/* Map 256MB I/O region - */ -#ifndef IO_PHYS_ADDR -#define IO_PHYS_ADDR 0xe0000000 -#endif -#ifndef IO_VIRT_ADDR -#define IO_VIRT_ADDR IO_PHYS_ADDR -#endif - -enum ppc_sys_devices { - MPC82xx_CPM_FCC1, - MPC82xx_CPM_FCC2, - MPC82xx_CPM_FCC3, - MPC82xx_CPM_I2C, - MPC82xx_CPM_SCC1, - MPC82xx_CPM_SCC2, - MPC82xx_CPM_SCC3, - MPC82xx_CPM_SCC4, - MPC82xx_CPM_SPI, - MPC82xx_CPM_MCC1, - MPC82xx_CPM_MCC2, - MPC82xx_CPM_SMC1, - MPC82xx_CPM_SMC2, - MPC82xx_CPM_USB, - MPC82xx_SEC1, - MPC82xx_MDIO_BB, - NUM_PPC_SYS_DEVS, -}; - -#ifndef __ASSEMBLY__ -/* The "residual" data board information structure the boot loader - * hands to us. - */ -extern unsigned char __res[]; -#endif - -#ifndef BOARD_CHIP_NAME -#define BOARD_CHIP_NAME "" -#endif - -#endif /* CONFIG_8260 */ -#endif /* !__ASM_PPC_MPC8260_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc8260_pci9.h b/include/asm-ppc/mpc8260_pci9.h deleted file mode 100644 index 9f7176881c56..000000000000 --- a/include/asm-ppc/mpc8260_pci9.h +++ /dev/null @@ -1,47 +0,0 @@ -/* include/asm-ppc/mpc8260_pci9.h - * - * Undefine the PCI read* and in* macros so we can define them as functions - * that implement the workaround for the MPC8260 device erratum PCI 9. - * - * This header file should only be included at the end of include/asm-ppc/io.h - * and never included directly anywhere else. - * - * Author: andy_lowe@mvista.com - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef _PPC_IO_H -#error "Do not include mpc8260_pci9.h directly." -#endif - -#ifdef __KERNEL__ -#ifndef __CONFIG_8260_PCI9_DEFS -#define __CONFIG_8260_PCI9_DEFS - -#undef readb -#undef readw -#undef readl -#undef insb -#undef insw -#undef insl -#undef inb -#undef inw -#undef inl -#undef memcpy_fromio - -extern int readb(volatile unsigned char *addr); -extern int readw(volatile unsigned short *addr); -extern unsigned readl(volatile unsigned *addr); -extern void insb(unsigned port, void *buf, int ns); -extern void insw(unsigned port, void *buf, int ns); -extern void insl(unsigned port, void *buf, int nl); -extern int inb(unsigned port); -extern int inw(unsigned port); -extern unsigned inl(unsigned port); -extern void *memcpy_fromio(void *dest, unsigned long src, size_t count); - -#endif /* !__CONFIG_8260_PCI9_DEFS */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h deleted file mode 100644 index b9e3060b0278..000000000000 --- a/include/asm-ppc/mpc8xx.h +++ /dev/null @@ -1,122 +0,0 @@ -/* This is the single file included by all MPC8xx build options. - * Since there are many different boards and no standard configuration, - * we have a unique include file for each. Rather than change every - * file that has to include MPC8xx configuration, they all include - * this one and the configuration switching is done here. - */ -#ifdef __KERNEL__ -#ifndef __CONFIG_8xx_DEFS -#define __CONFIG_8xx_DEFS - - -#ifdef CONFIG_8xx - -#ifdef CONFIG_MBX -#include <platforms/mbx.h> -#endif - -#ifdef CONFIG_FADS -#include <platforms/fads.h> -#endif - -#ifdef CONFIG_RPXLITE -#include <platforms/rpxlite.h> -#endif - -#ifdef CONFIG_BSEIP -#include <platforms/bseip.h> -#endif - -#ifdef CONFIG_RPXCLASSIC -#include <platforms/rpxclassic.h> -#endif - -#if defined(CONFIG_TQM8xxL) -#include <platforms/tqm8xx.h> -#endif - -#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) -#include <platforms/ivms8.h> -#endif - -#if defined(CONFIG_HERMES_PRO) -#include <platforms/hermes.h> -#endif - -#if defined(CONFIG_IP860) -#include <platforms/ip860.h> -#endif - -#if defined(CONFIG_LWMON) -#include <platforms/lwmon.h> -#endif - -#if defined(CONFIG_PCU_E) -#include <platforms/pcu_e.h> -#endif - -#if defined(CONFIG_CCM) -#include <platforms/ccm.h> -#endif - -#if defined(CONFIG_LANTEC) -#include <platforms/lantec.h> -#endif - -/* Currently, all 8xx boards that support a processor to PCI/ISA bridge - * use the same memory map. - */ -#if 0 -#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR) -#define _IO_BASE PCI_ISA_IO_ADDR -#define _ISA_MEM_BASE PCI_ISA_MEM_ADDR -#define PCI_DRAM_OFFSET 0x80000000 -#else -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#endif -#else -#if !defined(_IO_BASE) /* defined in board specific header */ -#define _IO_BASE 0 -#endif -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 -#endif - -#ifndef __ASSEMBLY__ -/* The "residual" data board information structure the boot loader - * hands to us. - */ -extern unsigned char __res[]; - -struct pt_regs; - -enum ppc_sys_devices { - MPC8xx_CPM_FEC1, - MPC8xx_CPM_FEC2, - MPC8xx_CPM_I2C, - MPC8xx_CPM_SCC1, - MPC8xx_CPM_SCC2, - MPC8xx_CPM_SCC3, - MPC8xx_CPM_SCC4, - MPC8xx_CPM_SPI, - MPC8xx_CPM_MCC1, - MPC8xx_CPM_MCC2, - MPC8xx_CPM_SMC1, - MPC8xx_CPM_SMC2, - MPC8xx_CPM_USB, - MPC8xx_MDIO_FEC, - NUM_PPC_SYS_DEVS, -}; - -#define PPC_PIN_SIZE (24 * 1024 * 1024) /* 24Mbytes of data pinned */ - -#ifndef BOARD_CHIP_NAME -#define BOARD_CHIP_NAME "" -#endif - -#endif /* !__ASSEMBLY__ */ -#endif /* CONFIG_8xx */ -#endif /* __CONFIG_8xx_DEFS */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h deleted file mode 100644 index 2963d6aa3ea5..000000000000 --- a/include/asm-ppc/mv64x60.h +++ /dev/null @@ -1,353 +0,0 @@ -/* - * include/asm-ppc/mv64x60.h - * - * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines. - * - * Author: Mark A. Greer <mgreer@mvista.com> - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASMPPC_MV64x60_H -#define __ASMPPC_MV64x60_H - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/slab.h> - -#include <asm/byteorder.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/uaccess.h> -#include <asm/machdep.h> -#include <asm/pci-bridge.h> -#include <asm/mv64x60_defs.h> - -struct platform_device; - -extern u8 mv64x60_pci_exclude_bridge; - -extern spinlock_t mv64x60_lock; - -/* 32-bit Window table entry defines */ -#define MV64x60_CPU2MEM_0_WIN 0 -#define MV64x60_CPU2MEM_1_WIN 1 -#define MV64x60_CPU2MEM_2_WIN 2 -#define MV64x60_CPU2MEM_3_WIN 3 -#define MV64x60_CPU2DEV_0_WIN 4 -#define MV64x60_CPU2DEV_1_WIN 5 -#define MV64x60_CPU2DEV_2_WIN 6 -#define MV64x60_CPU2DEV_3_WIN 7 -#define MV64x60_CPU2BOOT_WIN 8 -#define MV64x60_CPU2PCI0_IO_WIN 9 -#define MV64x60_CPU2PCI0_MEM_0_WIN 10 -#define MV64x60_CPU2PCI0_MEM_1_WIN 11 -#define MV64x60_CPU2PCI0_MEM_2_WIN 12 -#define MV64x60_CPU2PCI0_MEM_3_WIN 13 -#define MV64x60_CPU2PCI1_IO_WIN 14 -#define MV64x60_CPU2PCI1_MEM_0_WIN 15 -#define MV64x60_CPU2PCI1_MEM_1_WIN 16 -#define MV64x60_CPU2PCI1_MEM_2_WIN 17 -#define MV64x60_CPU2PCI1_MEM_3_WIN 18 -#define MV64x60_CPU2SRAM_WIN 19 -#define MV64x60_CPU2PCI0_IO_REMAP_WIN 20 -#define MV64x60_CPU2PCI1_IO_REMAP_WIN 21 -#define MV64x60_CPU_PROT_0_WIN 22 -#define MV64x60_CPU_PROT_1_WIN 23 -#define MV64x60_CPU_PROT_2_WIN 24 -#define MV64x60_CPU_PROT_3_WIN 25 -#define MV64x60_CPU_SNOOP_0_WIN 26 -#define MV64x60_CPU_SNOOP_1_WIN 27 -#define MV64x60_CPU_SNOOP_2_WIN 28 -#define MV64x60_CPU_SNOOP_3_WIN 29 -#define MV64x60_PCI02MEM_REMAP_0_WIN 30 -#define MV64x60_PCI02MEM_REMAP_1_WIN 31 -#define MV64x60_PCI02MEM_REMAP_2_WIN 32 -#define MV64x60_PCI02MEM_REMAP_3_WIN 33 -#define MV64x60_PCI12MEM_REMAP_0_WIN 34 -#define MV64x60_PCI12MEM_REMAP_1_WIN 35 -#define MV64x60_PCI12MEM_REMAP_2_WIN 36 -#define MV64x60_PCI12MEM_REMAP_3_WIN 37 -#define MV64x60_ENET2MEM_0_WIN 38 -#define MV64x60_ENET2MEM_1_WIN 39 -#define MV64x60_ENET2MEM_2_WIN 40 -#define MV64x60_ENET2MEM_3_WIN 41 -#define MV64x60_ENET2MEM_4_WIN 42 -#define MV64x60_ENET2MEM_5_WIN 43 -#define MV64x60_MPSC2MEM_0_WIN 44 -#define MV64x60_MPSC2MEM_1_WIN 45 -#define MV64x60_MPSC2MEM_2_WIN 46 -#define MV64x60_MPSC2MEM_3_WIN 47 -#define MV64x60_IDMA2MEM_0_WIN 48 -#define MV64x60_IDMA2MEM_1_WIN 49 -#define MV64x60_IDMA2MEM_2_WIN 50 -#define MV64x60_IDMA2MEM_3_WIN 51 -#define MV64x60_IDMA2MEM_4_WIN 52 -#define MV64x60_IDMA2MEM_5_WIN 53 -#define MV64x60_IDMA2MEM_6_WIN 54 -#define MV64x60_IDMA2MEM_7_WIN 55 - -#define MV64x60_32BIT_WIN_COUNT 56 - -/* 64-bit Window table entry defines */ -#define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0 -#define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN 1 -#define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN 2 -#define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN 3 -#define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN 4 -#define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN 5 -#define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN 6 -#define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN 7 -#define MV64x60_PCI02MEM_ACC_CNTL_0_WIN 8 -#define MV64x60_PCI02MEM_ACC_CNTL_1_WIN 9 -#define MV64x60_PCI02MEM_ACC_CNTL_2_WIN 10 -#define MV64x60_PCI02MEM_ACC_CNTL_3_WIN 11 -#define MV64x60_PCI12MEM_ACC_CNTL_0_WIN 12 -#define MV64x60_PCI12MEM_ACC_CNTL_1_WIN 13 -#define MV64x60_PCI12MEM_ACC_CNTL_2_WIN 14 -#define MV64x60_PCI12MEM_ACC_CNTL_3_WIN 15 -#define MV64x60_PCI02MEM_SNOOP_0_WIN 16 -#define MV64x60_PCI02MEM_SNOOP_1_WIN 17 -#define MV64x60_PCI02MEM_SNOOP_2_WIN 18 -#define MV64x60_PCI02MEM_SNOOP_3_WIN 19 -#define MV64x60_PCI12MEM_SNOOP_0_WIN 20 -#define MV64x60_PCI12MEM_SNOOP_1_WIN 21 -#define MV64x60_PCI12MEM_SNOOP_2_WIN 22 -#define MV64x60_PCI12MEM_SNOOP_3_WIN 23 - -#define MV64x60_64BIT_WIN_COUNT 24 - -/* - * Define a structure that's used to pass in config information to the - * core routines. - */ -struct mv64x60_pci_window { - u32 cpu_base; - u32 pci_base_hi; - u32 pci_base_lo; - u32 size; - u32 swap; -}; - -struct mv64x60_pci_info { - u8 enable_bus; /* allow access to this PCI bus? */ - - struct mv64x60_pci_window pci_io; - struct mv64x60_pci_window pci_mem[3]; - - u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS]; - u32 snoop_options[MV64x60_CPU2MEM_WINDOWS]; - u16 pci_cmd_bits; - u16 latency_timer; -}; - -struct mv64x60_setup_info { - u32 phys_reg_base; - u32 window_preserve_mask_32_hi; - u32 window_preserve_mask_32_lo; - u32 window_preserve_mask_64; - - u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS]; - u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS]; - u32 enet_options[MV64x60_CPU2MEM_WINDOWS]; - u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS]; - u32 idma_options[MV64x60_CPU2MEM_WINDOWS]; - - struct mv64x60_pci_info pci_0; - struct mv64x60_pci_info pci_1; -}; - -/* Define what the top bits in the extra member of a window entry means. */ -#define MV64x60_EXTRA_INVALID 0x00000000 -#define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000 -#define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000 -#define MV64x60_EXTRA_ENET_ENAB 0x30000000 -#define MV64x60_EXTRA_MPSC_ENAB 0x40000000 -#define MV64x60_EXTRA_IDMA_ENAB 0x50000000 -#define MV64x60_EXTRA_PCIACC_ENAB 0x60000000 - -#define MV64x60_EXTRA_MASK 0xf0000000 - -/* - * Define the 'handle' struct that will be passed between the 64x60 core - * code and the platform-specific code that will use it. The handle - * will contain pointers to chip-specific routines & information. - */ -struct mv64x60_32bit_window { - u32 base_reg; - u32 size_reg; - u8 base_bits; - u8 size_bits; - u32 (*get_from_field)(u32 val, u32 num_bits); - u32 (*map_to_field)(u32 val, u32 num_bits); - u32 extra; -}; - -struct mv64x60_64bit_window { - u32 base_hi_reg; - u32 base_lo_reg; - u32 size_reg; - u8 base_lo_bits; - u8 size_bits; - u32 (*get_from_field)(u32 val, u32 num_bits); - u32 (*map_to_field)(u32 val, u32 num_bits); - u32 extra; -}; - -typedef struct mv64x60_handle mv64x60_handle_t; -struct mv64x60_chip_info { - u32 (*translate_size)(u32 base, u32 size, u32 num_bits); - u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits); - void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus, - u32 window, u32 base); - void (*set_pci2regs_window)(struct mv64x60_handle *bh, - struct pci_controller *hose, u32 bus, u32 base); - u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window); - void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window); - void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window); - void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window); - void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window); - void (*disable_all_windows)(mv64x60_handle_t *bh, - struct mv64x60_setup_info *si); - void (*config_io2mem_windows)(mv64x60_handle_t *bh, - struct mv64x60_setup_info *si, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); - void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base); - void (*chip_specific_init)(mv64x60_handle_t *bh, - struct mv64x60_setup_info *si); - - struct mv64x60_32bit_window *window_tab_32bit; - struct mv64x60_64bit_window *window_tab_64bit; -}; - -struct mv64x60_handle { - u32 type; /* type of bridge */ - u32 rev; /* revision of bridge */ - void __iomem *v_base;/* virtual base addr of bridge regs */ - phys_addr_t p_base; /* physical base addr of bridge regs */ - - u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/ - u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/ - - u32 io_base_a; /* vaddr of pci 0's I/O space */ - u32 io_base_b; /* vaddr of pci 1's I/O space */ - - struct pci_controller *hose_a; - struct pci_controller *hose_b; - - struct mv64x60_chip_info *ci; /* chip/bridge-specific info */ -}; - - -/* Define I/O routines for accessing registers on the 64x60 bridge. */ -extern inline void -mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) { - ulong flags; - - spin_lock_irqsave(&mv64x60_lock, flags); - out_le32(bh->v_base + offset, val); - spin_unlock_irqrestore(&mv64x60_lock, flags); -} - -extern inline u32 -mv64x60_read(struct mv64x60_handle *bh, u32 offset) { - ulong flags; - u32 reg; - - spin_lock_irqsave(&mv64x60_lock, flags); - reg = in_le32(bh->v_base + offset); - spin_unlock_irqrestore(&mv64x60_lock, flags); - return reg; -} - -extern inline void -mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask) -{ - u32 reg; - ulong flags; - - spin_lock_irqsave(&mv64x60_lock, flags); - reg = in_le32(bh->v_base + offs) & (~mask); - reg |= data & mask; - out_le32(bh->v_base + offs, reg); - spin_unlock_irqrestore(&mv64x60_lock, flags); -} - -#define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits) -#define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits) - -#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) -#define MV64XXX_DEV_NAME "mv64xxx" - -struct mv64xxx_pdata { - u32 hs_reg_valid; -}; -#endif - -/* Externally visible function prototypes */ -int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si); -u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type); -void mv64x60_early_init(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si); -void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, - u32 cfg_data, struct pci_controller **hose); -int mv64x60_get_type(struct mv64x60_handle *bh); -int mv64x60_setup_for_chip(struct mv64x60_handle *bh); -void __iomem *mv64x60_get_bridge_vbase(void); -u32 mv64x60_get_bridge_type(void); -u32 mv64x60_get_bridge_rev(void); -void mv64x60_get_mem_windows(struct mv64x60_handle *bh, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); -void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, - struct mv64x60_setup_info *si, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); -void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, - struct mv64x60_pci_info *pi, u32 bus); -void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, - struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); -void mv64x60_config_resources(struct pci_controller *hose, - struct mv64x60_pci_info *pi, u32 io_base); -void mv64x60_config_pci_params(struct pci_controller *hose, - struct mv64x60_pci_info *pi); -void mv64x60_pd_fixup(struct mv64x60_handle *bh, - struct platform_device *pd_devs[], u32 entries); -void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, - u32 *base, u32 *size); -void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base, - u32 size, u32 other_bits); -void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, - u32 *base_hi, u32 *base_lo, u32 *size); -void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, - u32 base_hi, u32 base_lo, u32 size, u32 other_bits); -void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus); -int mv64x60_pci_exclude_device(u8 bus, u8 devfn); - - -void gt64260_init_irq(void); -int gt64260_get_irq(void); -void mv64360_init_irq(void); -int mv64360_get_irq(void); - -u32 mv64x60_mask(u32 val, u32 num_bits); -u32 mv64x60_shift_left(u32 val, u32 num_bits); -u32 mv64x60_shift_right(u32 val, u32 num_bits); -u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh, - u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); - -void mv64x60_progress_init(u32 base); -void mv64x60_mpsc_progress(char *s, unsigned short hex); - -extern struct mv64x60_32bit_window - gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT]; -extern struct mv64x60_64bit_window - gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT]; -extern struct mv64x60_32bit_window - mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT]; -extern struct mv64x60_64bit_window - mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT]; - -#endif /* __ASMPPC_MV64x60_H */ diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h deleted file mode 100644 index 5b0704a3e6ea..000000000000 --- a/include/asm-ppc/mv64x60_defs.h +++ /dev/null @@ -1,976 +0,0 @@ -/* - * include/asm-ppc/mv64x60_defs.h - * - * Register definitions for the Marvell/Galileo GT64260, MV64360, etc. - * host bridges. - * - * Author: Mark A. Greer <mgreer@mvista.com> - * - * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASMPPC_MV64x60_DEFS_H -#define __ASMPPC_MV64x60_DEFS_H - -/* - * Define the Marvell bridges that are supported - */ -#define MV64x60_TYPE_INVALID 0 -#define MV64x60_TYPE_GT64260A 1 -#define MV64x60_TYPE_GT64260B 2 -#define MV64x60_TYPE_MV64360 3 -#define MV64x60_TYPE_MV64361 4 -#define MV64x60_TYPE_MV64362 5 -#define MV64x60_TYPE_MV64460 6 - - -/* Revisions of each supported chip */ -#define GT64260_REV_A 0x10 -#define GT64260_REV_B 0x20 -#define MV64360 0x01 -#define MV64460 0x01 - -/* Minimum window size supported by 64260 is 1MB */ -#define GT64260_WINDOW_SIZE_MIN 0x00100000 -#define MV64360_WINDOW_SIZE_MIN 0x00010000 - -#define MV64x60_TCLK_FREQ_MAX 133333333U - -/* IRQ's for embedded controllers */ -#define MV64x60_IRQ_DEV 1 -#define MV64x60_IRQ_CPU_ERR 3 -#define MV64x60_IRQ_TIMER_0_1 8 -#define MV64x60_IRQ_TIMER_2_3 9 -#define MV64x60_IRQ_TIMER_4_5 10 -#define MV64x60_IRQ_TIMER_6_7 11 -#define MV64x60_IRQ_P1_GPP_0_7 24 -#define MV64x60_IRQ_P1_GPP_8_15 25 -#define MV64x60_IRQ_P1_GPP_16_23 26 -#define MV64x60_IRQ_P1_GPP_24_31 27 -#define MV64x60_IRQ_DOORBELL 28 -#define MV64x60_IRQ_ETH_0 32 -#define MV64x60_IRQ_ETH_1 33 -#define MV64x60_IRQ_ETH_2 34 -#define MV64x60_IRQ_SDMA_0 36 -#define MV64x60_IRQ_I2C 37 -#define MV64x60_IRQ_BRG 39 -#define MV64x60_IRQ_MPSC_0 40 -#define MV64x60_IRQ_MPSC_1 42 -#define MV64x60_IRQ_COMM 43 -#define MV64x60_IRQ_P0_GPP_0_7 56 -#define MV64x60_IRQ_P0_GPP_8_15 57 -#define MV64x60_IRQ_P0_GPP_16_23 58 -#define MV64x60_IRQ_P0_GPP_24_31 59 - -#define MV64360_IRQ_PCI0 12 -#define MV64360_IRQ_SRAM_PAR_ERR 13 -#define MV64360_IRQ_PCI1 16 -#define MV64360_IRQ_SDMA_1 38 - -#define MV64x60_IRQ_GPP0 64 -#define MV64x60_IRQ_GPP1 65 -#define MV64x60_IRQ_GPP2 66 -#define MV64x60_IRQ_GPP3 67 -#define MV64x60_IRQ_GPP4 68 -#define MV64x60_IRQ_GPP5 69 -#define MV64x60_IRQ_GPP6 70 -#define MV64x60_IRQ_GPP7 71 -#define MV64x60_IRQ_GPP8 72 -#define MV64x60_IRQ_GPP9 73 -#define MV64x60_IRQ_GPP10 74 -#define MV64x60_IRQ_GPP11 75 -#define MV64x60_IRQ_GPP12 76 -#define MV64x60_IRQ_GPP13 77 -#define MV64x60_IRQ_GPP14 78 -#define MV64x60_IRQ_GPP15 79 -#define MV64x60_IRQ_GPP16 80 -#define MV64x60_IRQ_GPP17 81 -#define MV64x60_IRQ_GPP18 82 -#define MV64x60_IRQ_GPP19 83 -#define MV64x60_IRQ_GPP20 84 -#define MV64x60_IRQ_GPP21 85 -#define MV64x60_IRQ_GPP22 86 -#define MV64x60_IRQ_GPP23 87 -#define MV64x60_IRQ_GPP24 88 -#define MV64x60_IRQ_GPP25 89 -#define MV64x60_IRQ_GPP26 90 -#define MV64x60_IRQ_GPP27 91 -#define MV64x60_IRQ_GPP28 92 -#define MV64x60_IRQ_GPP29 93 -#define MV64x60_IRQ_GPP30 94 -#define MV64x60_IRQ_GPP31 95 - -/* Offsets for register blocks */ -#define GT64260_ENET_PHY_ADDR 0x2000 -#define GT64260_ENET_ESMIR 0x2010 -#define GT64260_ENET_0_OFFSET 0x2400 -#define GT64260_ENET_1_OFFSET 0x2800 -#define GT64260_ENET_2_OFFSET 0x2c00 -#define MV64x60_SDMA_0_OFFSET 0x4000 -#define MV64x60_SDMA_1_OFFSET 0x6000 -#define MV64x60_MPSC_0_OFFSET 0x8000 -#define MV64x60_MPSC_1_OFFSET 0x9000 -#define MV64x60_MPSC_ROUTING_OFFSET 0xb400 -#define MV64x60_SDMA_INTR_OFFSET 0xb800 -#define MV64x60_BRG_0_OFFSET 0xb200 -#define MV64x60_BRG_1_OFFSET 0xb208 - -/* - ***************************************************************************** - * - * CPU Interface Registers - * - ***************************************************************************** - */ - -/* CPU physical address of bridge's registers */ -#define MV64x60_INTERNAL_SPACE_DECODE 0x0068 -#define MV64x60_INTERNAL_SPACE_SIZE 0x10000 -#define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 - -#define MV64360_CPU_BAR_ENABLE 0x0278 - -/* CPU Memory Controller Window Registers (4 windows) */ -#define MV64x60_CPU2MEM_WINDOWS 4 - -#define MV64x60_CPU2MEM_0_BASE 0x0008 -#define MV64x60_CPU2MEM_0_SIZE 0x0010 -#define MV64x60_CPU2MEM_1_BASE 0x0208 -#define MV64x60_CPU2MEM_1_SIZE 0x0210 -#define MV64x60_CPU2MEM_2_BASE 0x0018 -#define MV64x60_CPU2MEM_2_SIZE 0x0020 -#define MV64x60_CPU2MEM_3_BASE 0x0218 -#define MV64x60_CPU2MEM_3_SIZE 0x0220 - -/* CPU Device Controller Window Registers (4 windows) */ -#define MV64x60_CPU2DEV_WINDOWS 4 - -#define MV64x60_CPU2DEV_0_BASE 0x0028 -#define MV64x60_CPU2DEV_0_SIZE 0x0030 -#define MV64x60_CPU2DEV_1_BASE 0x0228 -#define MV64x60_CPU2DEV_1_SIZE 0x0230 -#define MV64x60_CPU2DEV_2_BASE 0x0248 -#define MV64x60_CPU2DEV_2_SIZE 0x0250 -#define MV64x60_CPU2DEV_3_BASE 0x0038 -#define MV64x60_CPU2DEV_3_SIZE 0x0040 - -#define MV64x60_CPU2BOOT_0_BASE 0x0238 -#define MV64x60_CPU2BOOT_0_SIZE 0x0240 - -#define MV64360_CPU2SRAM_BASE 0x0268 - -/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ -#define MV64x60_PCI_BUSES 2 -#define MV64x60_PCI_IO_WINDOWS_PER_BUS 1 -#define MV64x60_PCI_MEM_WINDOWS_PER_BUS 4 - -#define MV64x60_CPU2PCI_SWAP_BYTE 0x00000000 -#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000 -#define MV64x60_CPU2PCI_SWAP_BYTE_WORD 0x02000000 -#define MV64x60_CPU2PCI_SWAP_WORD 0x03000000 - -#define MV64x60_CPU2PCI_MEM_REQ64 (1<<27) - -#define MV64x60_CPU2PCI0_IO_BASE 0x0048 -#define MV64x60_CPU2PCI0_IO_SIZE 0x0050 -#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058 -#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060 -#define MV64x60_CPU2PCI0_MEM_1_BASE 0x0080 -#define MV64x60_CPU2PCI0_MEM_1_SIZE 0x0088 -#define MV64x60_CPU2PCI0_MEM_2_BASE 0x0258 -#define MV64x60_CPU2PCI0_MEM_2_SIZE 0x0260 -#define MV64x60_CPU2PCI0_MEM_3_BASE 0x0280 -#define MV64x60_CPU2PCI0_MEM_3_SIZE 0x0288 - -#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0 -#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8 -#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320 -#define MV64x60_CPU2PCI0_MEM_1_REMAP_LO 0x0100 -#define MV64x60_CPU2PCI0_MEM_1_REMAP_HI 0x0328 -#define MV64x60_CPU2PCI0_MEM_2_REMAP_LO 0x02f8 -#define MV64x60_CPU2PCI0_MEM_2_REMAP_HI 0x0330 -#define MV64x60_CPU2PCI0_MEM_3_REMAP_LO 0x0300 -#define MV64x60_CPU2PCI0_MEM_3_REMAP_HI 0x0338 - -#define MV64x60_CPU2PCI1_IO_BASE 0x0090 -#define MV64x60_CPU2PCI1_IO_SIZE 0x0098 -#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0 -#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8 -#define MV64x60_CPU2PCI1_MEM_1_BASE 0x00b0 -#define MV64x60_CPU2PCI1_MEM_1_SIZE 0x00b8 -#define MV64x60_CPU2PCI1_MEM_2_BASE 0x02a0 -#define MV64x60_CPU2PCI1_MEM_2_SIZE 0x02a8 -#define MV64x60_CPU2PCI1_MEM_3_BASE 0x02b0 -#define MV64x60_CPU2PCI1_MEM_3_SIZE 0x02b8 - -#define MV64x60_CPU2PCI1_IO_REMAP 0x0108 -#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110 -#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340 -#define MV64x60_CPU2PCI1_MEM_1_REMAP_LO 0x0118 -#define MV64x60_CPU2PCI1_MEM_1_REMAP_HI 0x0348 -#define MV64x60_CPU2PCI1_MEM_2_REMAP_LO 0x0310 -#define MV64x60_CPU2PCI1_MEM_2_REMAP_HI 0x0350 -#define MV64x60_CPU2PCI1_MEM_3_REMAP_LO 0x0318 -#define MV64x60_CPU2PCI1_MEM_3_REMAP_HI 0x0358 - -/* CPU Control Registers */ -#define MV64x60_CPU_CONFIG 0x0000 -#define MV64x60_CPU_MODE 0x0120 -#define MV64x60_CPU_MASTER_CNTL 0x0160 -#define MV64x60_CPU_XBAR_CNTL_LO 0x0150 -#define MV64x60_CPU_XBAR_CNTL_HI 0x0158 -#define MV64x60_CPU_XBAR_TO 0x0168 - -#define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 -#define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 - -#define MV64360_CPU_PADS_CALIBRATION 0x03b4 -#define MV64360_CPU_RESET_SAMPLE_LO 0x03c4 -#define MV64360_CPU_RESET_SAMPLE_HI 0x03d4 - -/* SMP Register Map */ -#define MV64360_WHO_AM_I 0x0200 -#define MV64360_CPU0_DOORBELL 0x0214 -#define MV64360_CPU0_DOORBELL_CLR 0x021c -#define MV64360_CPU0_DOORBELL_MASK 0x0234 -#define MV64360_CPU1_DOORBELL 0x0224 -#define MV64360_CPU1_DOORBELL_CLR 0x022c -#define MV64360_CPU1_DOORBELL_MASK 0x023c -#define MV64360_CPUx_DOORBELL(x) (0x0214 + ((x)*0x10)) -#define MV64360_CPUx_DOORBELL_CLR(x) (0x021c + ((x)*0x10)) -#define MV64360_CPUx_DOORBELL_MASK(x) (0x0234 + ((x)*0x08)) -#define MV64360_SEMAPHORE_0 0x0244 -#define MV64360_SEMAPHORE_1 0x024c -#define MV64360_SEMAPHORE_2 0x0254 -#define MV64360_SEMAPHORE_3 0x025c -#define MV64360_SEMAPHORE_4 0x0264 -#define MV64360_SEMAPHORE_5 0x026c -#define MV64360_SEMAPHORE_6 0x0274 -#define MV64360_SEMAPHORE_7 0x027c - -/* CPU Sync Barrier Registers */ -#define GT64260_CPU_SYNC_BARRIER_PCI0 0x00c0 -#define GT64260_CPU_SYNC_BARRIER_PCI1 0x00c8 - -#define MV64360_CPU0_SYNC_BARRIER_TRIG 0x00c0 -#define MV64360_CPU0_SYNC_BARRIER_VIRT 0x00c8 -#define MV64360_CPU1_SYNC_BARRIER_TRIG 0x00d0 -#define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8 - -/* CPU Deadlock and Ordering registers (Rev B part only) */ -#define GT64260_CPU_DEADLOCK_ORDERING 0x02d0 -#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8 -#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0 - -/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */ -#define MV64x260_CPU_PROT_WINDOWS 4 - -#define GT64260_CPU_PROT_ACCPROTECT (1<<16) -#define GT64260_CPU_PROT_WRPROTECT (1<<17) -#define GT64260_CPU_PROT_CACHEPROTECT (1<<18) - -#define MV64360_CPU_PROT_ACCPROTECT (1<<20) -#define MV64360_CPU_PROT_WRPROTECT (1<<21) -#define MV64360_CPU_PROT_CACHEPROTECT (1<<22) -#define MV64360_CPU_PROT_WIN_ENABLE (1<<31) - -#define MV64x60_CPU_PROT_BASE_0 0x0180 -#define MV64x60_CPU_PROT_SIZE_0 0x0188 -#define MV64x60_CPU_PROT_BASE_1 0x0190 -#define MV64x60_CPU_PROT_SIZE_1 0x0198 -#define MV64x60_CPU_PROT_BASE_2 0x01a0 -#define MV64x60_CPU_PROT_SIZE_2 0x01a8 -#define MV64x60_CPU_PROT_BASE_3 0x01b0 -#define MV64x60_CPU_PROT_SIZE_3 0x01b8 - -#define GT64260_CPU_PROT_BASE_4 0x01c0 -#define GT64260_CPU_PROT_SIZE_4 0x01c8 -#define GT64260_CPU_PROT_BASE_5 0x01d0 -#define GT64260_CPU_PROT_SIZE_5 0x01d8 -#define GT64260_CPU_PROT_BASE_6 0x01e0 -#define GT64260_CPU_PROT_SIZE_6 0x01e8 -#define GT64260_CPU_PROT_BASE_7 0x01f0 -#define GT64260_CPU_PROT_SIZE_7 0x01f8 - -/* CPU Snoop Control Registers (64260 only) */ -#define GT64260_CPU_SNOOP_WINDOWS 4 - -#define GT64260_CPU_SNOOP_NONE 0x00000000 -#define GT64260_CPU_SNOOP_WT 0x00010000 -#define GT64260_CPU_SNOOP_WB 0x00020000 -#define GT64260_CPU_SNOOP_MASK 0x00030000 -#define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK - -#define GT64260_CPU_SNOOP_BASE_0 0x0380 -#define GT64260_CPU_SNOOP_SIZE_0 0x0388 -#define GT64260_CPU_SNOOP_BASE_1 0x0390 -#define GT64260_CPU_SNOOP_SIZE_1 0x0398 -#define GT64260_CPU_SNOOP_BASE_2 0x03a0 -#define GT64260_CPU_SNOOP_SIZE_2 0x03a8 -#define GT64260_CPU_SNOOP_BASE_3 0x03b0 -#define GT64260_CPU_SNOOP_SIZE_3 0x03b8 - -/* CPU Snoop Control Registers (64360 only) */ -#define MV64360_CPU_SNOOP_WINDOWS 4 -#define MV64360_CPU_SNOOP_NONE 0x00000000 -#define MV64360_CPU_SNOOP_WT 0x00010000 -#define MV64360_CPU_SNOOP_WB 0x00020000 -#define MV64360_CPU_SNOOP_MASK 0x00030000 -#define MV64360_CPU_SNOOP_ALL_BITS MV64360_CPU_SNOOP_MASK - - -/* CPU Error Report Registers */ -#define MV64x60_CPU_ERR_ADDR_LO 0x0070 -#define MV64x60_CPU_ERR_ADDR_HI 0x0078 -#define MV64x60_CPU_ERR_DATA_LO 0x0128 -#define MV64x60_CPU_ERR_DATA_HI 0x0130 -#define MV64x60_CPU_ERR_PARITY 0x0138 -#define MV64x60_CPU_ERR_CAUSE 0x0140 -#define MV64x60_CPU_ERR_MASK 0x0148 - -/* - ***************************************************************************** - * - * SRAM Controller Registers - * - ***************************************************************************** - */ - -#define MV64360_SRAM_CONFIG 0x0380 -#define MV64360_SRAM_TEST_MODE 0x03f4 -#define MV64360_SRAM_ERR_CAUSE 0x0388 -#define MV64360_SRAM_ERR_ADDR_LO 0x0390 -#define MV64360_SRAM_ERR_ADDR_HI 0x03f8 -#define MV64360_SRAM_ERR_DATA_LO 0x0398 -#define MV64360_SRAM_ERR_DATA_HI 0x03a0 -#define MV64360_SRAM_ERR_PARITY 0x03a8 - -#define MV64360_SRAM_SIZE 0x00040000 /* 2Mb/256KB SRAM */ - -/* - ***************************************************************************** - * - * SDRAM/MEM Controller Registers - * - ***************************************************************************** - */ - -/* SDRAM Config Registers (64260) */ -#define GT64260_SDRAM_CONFIG 0x0448 - -/* SDRAM Error Report Registers (64260) */ -#define GT64260_SDRAM_ERR_DATA_LO 0x0484 -#define GT64260_SDRAM_ERR_DATA_HI 0x0480 -#define GT64260_SDRAM_ERR_ADDR 0x0490 -#define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 -#define GT64260_SDRAM_ERR_ECC_CALC 0x048c -#define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 -#define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 - -/* SDRAM Config Registers (64360) */ -#define MV64360_SDRAM_CONFIG 0x1400 - -/* SDRAM Control Registers */ -#define MV64360_D_UNIT_CONTROL_LOW 0x1404 -#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64460_D_UNIT_MMASK 0x14b0 - -/* SDRAM Error Report Registers (64360) */ -#define MV64360_SDRAM_ERR_DATA_LO 0x1444 -#define MV64360_SDRAM_ERR_DATA_HI 0x1440 -#define MV64360_SDRAM_ERR_ADDR 0x1450 -#define MV64360_SDRAM_ERR_ECC_RCVD 0x1448 -#define MV64360_SDRAM_ERR_ECC_CALC 0x144c -#define MV64360_SDRAM_ERR_ECC_CNTL 0x1454 -#define MV64360_SDRAM_ERR_ECC_ERR_CNT 0x1458 - -/* - ***************************************************************************** - * - * Device/BOOT Controller Registers - * - ***************************************************************************** - */ - -/* Device Control Registers */ -#define MV64x60_DEV_BANK_PARAMS_0 0x045c -#define MV64x60_DEV_BANK_PARAMS_1 0x0460 -#define MV64x60_DEV_BANK_PARAMS_2 0x0464 -#define MV64x60_DEV_BANK_PARAMS_3 0x0468 -#define MV64x60_DEV_BOOT_PARAMS 0x046c -#define MV64x60_DEV_IF_CNTL 0x04c0 -#define MV64x60_DEV_IF_XBAR_CNTL_LO 0x04c8 -#define MV64x60_DEV_IF_XBAR_CNTL_HI 0x04cc -#define MV64x60_DEV_IF_XBAR_CNTL_TO 0x04c4 - -/* Device Interrupt Registers */ -#define MV64x60_DEV_INTR_CAUSE 0x04d0 -#define MV64x60_DEV_INTR_MASK 0x04d4 -#define MV64x60_DEV_INTR_ERR_ADDR 0x04d8 - -#define MV64360_DEV_INTR_ERR_DATA 0x04dc -#define MV64360_DEV_INTR_ERR_PAR 0x04e0 - -/* - ***************************************************************************** - * - * PCI Bridge Interface Registers - * - ***************************************************************************** - */ - -/* PCI Configuration Access Registers */ -#define MV64x60_PCI0_CONFIG_ADDR 0x0cf8 -#define MV64x60_PCI0_CONFIG_DATA 0x0cfc -#define MV64x60_PCI0_IACK 0x0c34 - -#define MV64x60_PCI1_CONFIG_ADDR 0x0c78 -#define MV64x60_PCI1_CONFIG_DATA 0x0c7c -#define MV64x60_PCI1_IACK 0x0cb4 - -/* PCI Control Registers */ -#define MV64x60_PCI0_CMD 0x0c00 -#define MV64x60_PCI0_MODE 0x0d00 -#define MV64x60_PCI0_TO_RETRY 0x0c04 -#define MV64x60_PCI0_RD_BUF_DISCARD_TIMER 0x0d04 -#define MV64x60_PCI0_MSI_TRIGGER_TIMER 0x0c38 -#define MV64x60_PCI0_ARBITER_CNTL 0x1d00 -#define MV64x60_PCI0_XBAR_CNTL_LO 0x1d08 -#define MV64x60_PCI0_XBAR_CNTL_HI 0x1d0c -#define MV64x60_PCI0_XBAR_CNTL_TO 0x1d04 -#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO 0x1d18 -#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI 0x1d1c -#define MV64x60_PCI0_SYNC_BARRIER 0x1d10 -#define MV64x60_PCI0_P2P_CONFIG 0x1d14 -#define MV64x60_PCI0_INTR_MASK - -#define GT64260_PCI0_P2P_SWAP_CNTL 0x1d54 - -#define MV64x60_PCI1_CMD 0x0c80 -#define MV64x60_PCI1_MODE 0x0d80 -#define MV64x60_PCI1_TO_RETRY 0x0c84 -#define MV64x60_PCI1_RD_BUF_DISCARD_TIMER 0x0d84 -#define MV64x60_PCI1_MSI_TRIGGER_TIMER 0x0cb8 -#define MV64x60_PCI1_ARBITER_CNTL 0x1d80 -#define MV64x60_PCI1_XBAR_CNTL_LO 0x1d88 -#define MV64x60_PCI1_XBAR_CNTL_HI 0x1d8c -#define MV64x60_PCI1_XBAR_CNTL_TO 0x1d84 -#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO 0x1d98 -#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI 0x1d9c -#define MV64x60_PCI1_SYNC_BARRIER 0x1d90 -#define MV64x60_PCI1_P2P_CONFIG 0x1d94 - -#define GT64260_PCI1_P2P_SWAP_CNTL 0x1dd4 - -/* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */ -#define MV64x60_PCIMODE_CONVENTIONAL 0 -#define MV64x60_PCIMODE_PCIX_66 (1 << 4) -#define MV64x60_PCIMODE_PCIX_100 (2 << 4) -#define MV64x60_PCIMODE_PCIX_133 (3 << 4) -#define MV64x60_PCIMODE_MASK (0x3 << 4) - -/* PCI Access Control Regions Registers */ -#define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) -#define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) -#define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) -#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) -#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) -#define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES 0x00000000 -#define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES 0x00100000 -#define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES 0x00200000 -#define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 -#define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 -#define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 -#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 -#define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 -#define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 -#define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) -#define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) - -#define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ - GT64260_PCI_ACC_CNTL_DREADEN | \ - GT64260_PCI_ACC_CNTL_RDPREFETCH | \ - GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ - GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ - GT64260_PCI_ACC_CNTL_MBURST_MASK | \ - GT64260_PCI_ACC_CNTL_SWAP_MASK | \ - GT64260_PCI_ACC_CNTL_ACCPROT| \ - GT64260_PCI_ACC_CNTL_WRPROT) - -#define MV64360_PCI_ACC_CNTL_ENABLE (1<<0) -#define MV64360_PCI_ACC_CNTL_REQ64 (1<<1) -#define MV64360_PCI_ACC_CNTL_SNOOP_NONE 0x00000000 -#define MV64360_PCI_ACC_CNTL_SNOOP_WT 0x00000004 -#define MV64360_PCI_ACC_CNTL_SNOOP_WB 0x00000008 -#define MV64360_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c -#define MV64360_PCI_ACC_CNTL_ACCPROT (1<<4) -#define MV64360_PCI_ACC_CNTL_WRPROT (1<<5) -#define MV64360_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 -#define MV64360_PCI_ACC_CNTL_SWAP_NONE 0x00000040 -#define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080 -#define MV64360_PCI_ACC_CNTL_SWAP_WORD 0x000000c0 -#define MV64360_PCI_ACC_CNTL_SWAP_MASK 0x000000c0 -#define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000 -#define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100 -#define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200 -#define MV64360_PCI_ACC_CNTL_MBURST_MASK 0x00000300 -#define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000 -#define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400 -#define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800 -#define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00 -#define MV64360_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00 - -#define MV64360_PCI_ACC_CNTL_ALL_BITS (MV64360_PCI_ACC_CNTL_ENABLE | \ - MV64360_PCI_ACC_CNTL_REQ64 | \ - MV64360_PCI_ACC_CNTL_SNOOP_MASK | \ - MV64360_PCI_ACC_CNTL_ACCPROT | \ - MV64360_PCI_ACC_CNTL_WRPROT | \ - MV64360_PCI_ACC_CNTL_SWAP_MASK | \ - MV64360_PCI_ACC_CNTL_MBURST_MASK | \ - MV64360_PCI_ACC_CNTL_RDSIZE_MASK) - -#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00 -#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04 -#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08 -#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10 -#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14 -#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18 -#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20 -#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24 -#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28 -#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30 -#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34 -#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38 -#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40 -#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44 -#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48 -#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50 -#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54 -#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58 - -#define GT64260_PCI0_ACC_CNTL_6_BASE_LO 0x1e60 -#define GT64260_PCI0_ACC_CNTL_6_BASE_HI 0x1e64 -#define GT64260_PCI0_ACC_CNTL_6_SIZE 0x1e68 -#define GT64260_PCI0_ACC_CNTL_7_BASE_LO 0x1e70 -#define GT64260_PCI0_ACC_CNTL_7_BASE_HI 0x1e74 -#define GT64260_PCI0_ACC_CNTL_7_SIZE 0x1e78 - -#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80 -#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84 -#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88 -#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90 -#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94 -#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98 -#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0 -#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4 -#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8 -#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0 -#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4 -#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8 -#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0 -#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4 -#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8 -#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0 -#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4 -#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8 - -#define GT64260_PCI1_ACC_CNTL_6_BASE_LO 0x1ee0 -#define GT64260_PCI1_ACC_CNTL_6_BASE_HI 0x1ee4 -#define GT64260_PCI1_ACC_CNTL_6_SIZE 0x1ee8 -#define GT64260_PCI1_ACC_CNTL_7_BASE_LO 0x1ef0 -#define GT64260_PCI1_ACC_CNTL_7_BASE_HI 0x1ef4 -#define GT64260_PCI1_ACC_CNTL_7_SIZE 0x1ef8 - -/* PCI Snoop Control Registers (64260 only) */ -#define GT64260_PCI_SNOOP_NONE 0x00000000 -#define GT64260_PCI_SNOOP_WT 0x00001000 -#define GT64260_PCI_SNOOP_WB 0x00002000 - -#define GT64260_PCI0_SNOOP_0_BASE_LO 0x1f00 -#define GT64260_PCI0_SNOOP_0_BASE_HI 0x1f04 -#define GT64260_PCI0_SNOOP_0_SIZE 0x1f08 -#define GT64260_PCI0_SNOOP_1_BASE_LO 0x1f10 -#define GT64260_PCI0_SNOOP_1_BASE_HI 0x1f14 -#define GT64260_PCI0_SNOOP_1_SIZE 0x1f18 -#define GT64260_PCI0_SNOOP_2_BASE_LO 0x1f20 -#define GT64260_PCI0_SNOOP_2_BASE_HI 0x1f24 -#define GT64260_PCI0_SNOOP_2_SIZE 0x1f28 -#define GT64260_PCI0_SNOOP_3_BASE_LO 0x1f30 -#define GT64260_PCI0_SNOOP_3_BASE_HI 0x1f34 -#define GT64260_PCI0_SNOOP_3_SIZE 0x1f38 - -#define GT64260_PCI1_SNOOP_0_BASE_LO 0x1f80 -#define GT64260_PCI1_SNOOP_0_BASE_HI 0x1f84 -#define GT64260_PCI1_SNOOP_0_SIZE 0x1f88 -#define GT64260_PCI1_SNOOP_1_BASE_LO 0x1f90 -#define GT64260_PCI1_SNOOP_1_BASE_HI 0x1f94 -#define GT64260_PCI1_SNOOP_1_SIZE 0x1f98 -#define GT64260_PCI1_SNOOP_2_BASE_LO 0x1fa0 -#define GT64260_PCI1_SNOOP_2_BASE_HI 0x1fa4 -#define GT64260_PCI1_SNOOP_2_SIZE 0x1fa8 -#define GT64260_PCI1_SNOOP_3_BASE_LO 0x1fb0 -#define GT64260_PCI1_SNOOP_3_BASE_HI 0x1fb4 -#define GT64260_PCI1_SNOOP_3_SIZE 0x1fb8 - -/* PCI Error Report Registers */ -#define MV64x60_PCI0_ERR_SERR_MASK 0x0c28 -#define MV64x60_PCI0_ERR_ADDR_LO 0x1d40 -#define MV64x60_PCI0_ERR_ADDR_HI 0x1d44 -#define MV64x60_PCI0_ERR_DATA_LO 0x1d48 -#define MV64x60_PCI0_ERR_DATA_HI 0x1d4c -#define MV64x60_PCI0_ERR_CMD 0x1d50 -#define MV64x60_PCI0_ERR_CAUSE 0x1d58 -#define MV64x60_PCI0_ERR_MASK 0x1d5c - -#define MV64x60_PCI1_ERR_SERR_MASK 0x0ca8 -#define MV64x60_PCI1_ERR_ADDR_LO 0x1dc0 -#define MV64x60_PCI1_ERR_ADDR_HI 0x1dc4 -#define MV64x60_PCI1_ERR_DATA_LO 0x1dc8 -#define MV64x60_PCI1_ERR_DATA_HI 0x1dcc -#define MV64x60_PCI1_ERR_CMD 0x1dd0 -#define MV64x60_PCI1_ERR_CAUSE 0x1dd8 -#define MV64x60_PCI1_ERR_MASK 0x1ddc - -/* PCI Slave Address Decoding Registers */ -#define MV64x60_PCI0_MEM_0_SIZE 0x0c08 -#define MV64x60_PCI0_MEM_1_SIZE 0x0d08 -#define MV64x60_PCI0_MEM_2_SIZE 0x0c0c -#define MV64x60_PCI0_MEM_3_SIZE 0x0d0c -#define MV64x60_PCI1_MEM_0_SIZE 0x0c88 -#define MV64x60_PCI1_MEM_1_SIZE 0x0d88 -#define MV64x60_PCI1_MEM_2_SIZE 0x0c8c -#define MV64x60_PCI1_MEM_3_SIZE 0x0d8c - -#define MV64x60_PCI0_BAR_ENABLE 0x0c3c -#define MV64x60_PCI1_BAR_ENABLE 0x0cbc - -#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c -#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc - -#define MV64x60_PCI0_SLAVE_MEM_0_REMAP 0x0c48 -#define MV64x60_PCI0_SLAVE_MEM_1_REMAP 0x0d48 -#define MV64x60_PCI0_SLAVE_MEM_2_REMAP 0x0c4c -#define MV64x60_PCI0_SLAVE_MEM_3_REMAP 0x0d4c -#define MV64x60_PCI0_SLAVE_DEV_0_REMAP 0x0c50 -#define MV64x60_PCI0_SLAVE_DEV_1_REMAP 0x0d50 -#define MV64x60_PCI0_SLAVE_DEV_2_REMAP 0x0d58 -#define MV64x60_PCI0_SLAVE_DEV_3_REMAP 0x0c54 -#define MV64x60_PCI0_SLAVE_BOOT_REMAP 0x0d54 -#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c -#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 -#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 -#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 -#define MV64x60_PCI0_SLAVE_P2P_IO_REMAP 0x0d6c -#define MV64x60_PCI0_SLAVE_CPU_REMAP 0x0d70 - -#define MV64x60_PCI1_SLAVE_MEM_0_REMAP 0x0cc8 -#define MV64x60_PCI1_SLAVE_MEM_1_REMAP 0x0dc8 -#define MV64x60_PCI1_SLAVE_MEM_2_REMAP 0x0ccc -#define MV64x60_PCI1_SLAVE_MEM_3_REMAP 0x0dcc -#define MV64x60_PCI1_SLAVE_DEV_0_REMAP 0x0cd0 -#define MV64x60_PCI1_SLAVE_DEV_1_REMAP 0x0dd0 -#define MV64x60_PCI1_SLAVE_DEV_2_REMAP 0x0dd8 -#define MV64x60_PCI1_SLAVE_DEV_3_REMAP 0x0cd4 -#define MV64x60_PCI1_SLAVE_BOOT_REMAP 0x0dd4 -#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc -#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 -#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 -#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 -#define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec -#define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0 - -#define MV64360_PCICFG_CPCI_HOTSWAP 0x68 - -/* - ***************************************************************************** - * - * ENET Controller Interface Registers - * - ***************************************************************************** - */ - -/* ENET Controller Window Registers (6 windows) */ -#define MV64360_ENET2MEM_WINDOWS 6 - -#define MV64360_ENET2MEM_0_BASE 0x2200 -#define MV64360_ENET2MEM_0_SIZE 0x2204 -#define MV64360_ENET2MEM_1_BASE 0x2208 -#define MV64360_ENET2MEM_1_SIZE 0x220c -#define MV64360_ENET2MEM_2_BASE 0x2210 -#define MV64360_ENET2MEM_2_SIZE 0x2214 -#define MV64360_ENET2MEM_3_BASE 0x2218 -#define MV64360_ENET2MEM_3_SIZE 0x221c -#define MV64360_ENET2MEM_4_BASE 0x2220 -#define MV64360_ENET2MEM_4_SIZE 0x2224 -#define MV64360_ENET2MEM_5_BASE 0x2228 -#define MV64360_ENET2MEM_5_SIZE 0x222c - -#define MV64360_ENET2MEM_SNOOP_NONE 0x00000000 -#define MV64360_ENET2MEM_SNOOP_WT 0x00001000 -#define MV64360_ENET2MEM_SNOOP_WB 0x00002000 - -#define MV64360_ENET2MEM_BAR_ENABLE 0x2290 - -#define MV64360_ENET2MEM_ACC_PROT_0 0x2294 -#define MV64360_ENET2MEM_ACC_PROT_1 0x2298 -#define MV64360_ENET2MEM_ACC_PROT_2 0x229c - -/* - ***************************************************************************** - * - * MPSC Controller Interface Registers - * - ***************************************************************************** - */ - -/* MPSC Controller Window Registers (4 windows) */ -#define MV64360_MPSC2MEM_WINDOWS 4 - -#define MV64360_MPSC2MEM_0_BASE 0xf200 -#define MV64360_MPSC2MEM_0_SIZE 0xf204 -#define MV64360_MPSC2MEM_1_BASE 0xf208 -#define MV64360_MPSC2MEM_1_SIZE 0xf20c -#define MV64360_MPSC2MEM_2_BASE 0xf210 -#define MV64360_MPSC2MEM_2_SIZE 0xf214 -#define MV64360_MPSC2MEM_3_BASE 0xf218 -#define MV64360_MPSC2MEM_3_SIZE 0xf21c - -#define MV64360_MPSC_0_REMAP 0xf240 -#define MV64360_MPSC_1_REMAP 0xf244 - -#define MV64360_MPSC2MEM_SNOOP_NONE 0x00000000 -#define MV64360_MPSC2MEM_SNOOP_WT 0x00001000 -#define MV64360_MPSC2MEM_SNOOP_WB 0x00002000 - -#define MV64360_MPSC2MEM_BAR_ENABLE 0xf250 - -#define MV64360_MPSC2MEM_ACC_PROT_0 0xf254 -#define MV64360_MPSC2MEM_ACC_PROT_1 0xf258 - -#define MV64360_MPSC2REGS_BASE 0xf25c - -/* - ***************************************************************************** - * - * Timer/Counter Interface Registers - * - ***************************************************************************** - */ - -#define MV64x60_TIMR_CNTR_0 0x0850 -#define MV64x60_TIMR_CNTR_1 0x0854 -#define MV64x60_TIMR_CNTR_2 0x0858 -#define MV64x60_TIMR_CNTR_3 0x085c -#define MV64x60_TIMR_CNTR_0_3_CNTL 0x0864 -#define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE 0x0868 -#define MV64x60_TIMR_CNTR_0_3_INTR_MASK 0x086c - -#define GT64260_TIMR_CNTR_4 0x0950 -#define GT64260_TIMR_CNTR_5 0x0954 -#define GT64260_TIMR_CNTR_6 0x0958 -#define GT64260_TIMR_CNTR_7 0x095c -#define GT64260_TIMR_CNTR_4_7_CNTL 0x0964 -#define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968 -#define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c - -/* - ***************************************************************************** - * - * Communications Controller - * - ***************************************************************************** - */ - -#define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 -#define GT64260_SER_INIT_LAST_DATA 0xf324 -#define GT64260_SER_INIT_CONTROL 0xf328 -#define GT64260_SER_INIT_STATUS 0xf32c - -#define MV64x60_COMM_ARBITER_CNTL 0xf300 -#define MV64x60_COMM_CONFIG 0xb40c -#define MV64x60_COMM_XBAR_TO 0xf304 -#define MV64x60_COMM_INTR_CAUSE 0xf310 -#define MV64x60_COMM_INTR_MASK 0xf314 -#define MV64x60_COMM_ERR_ADDR 0xf318 - -#define MV64360_COMM_ARBITER_CNTL 0xf300 - -/* - ***************************************************************************** - * - * IDMA Controller Interface Registers - * - ***************************************************************************** - */ - -/* IDMA Controller Window Registers (8 windows) */ -#define MV64360_IDMA2MEM_WINDOWS 8 - -#define MV64360_IDMA2MEM_0_BASE 0x0a00 -#define MV64360_IDMA2MEM_0_SIZE 0x0a04 -#define MV64360_IDMA2MEM_1_BASE 0x0a08 -#define MV64360_IDMA2MEM_1_SIZE 0x0a0c -#define MV64360_IDMA2MEM_2_BASE 0x0a10 -#define MV64360_IDMA2MEM_2_SIZE 0x0a14 -#define MV64360_IDMA2MEM_3_BASE 0x0a18 -#define MV64360_IDMA2MEM_3_SIZE 0x0a1c -#define MV64360_IDMA2MEM_4_BASE 0x0a20 -#define MV64360_IDMA2MEM_4_SIZE 0x0a24 -#define MV64360_IDMA2MEM_5_BASE 0x0a28 -#define MV64360_IDMA2MEM_5_SIZE 0x0a2c -#define MV64360_IDMA2MEM_6_BASE 0x0a30 -#define MV64360_IDMA2MEM_6_SIZE 0x0a34 -#define MV64360_IDMA2MEM_7_BASE 0x0a38 -#define MV64360_IDMA2MEM_7_SIZE 0x0a3c - -#define MV64360_IDMA2MEM_SNOOP_NONE 0x00000000 -#define MV64360_IDMA2MEM_SNOOP_WT 0x00001000 -#define MV64360_IDMA2MEM_SNOOP_WB 0x00002000 - -#define MV64360_IDMA2MEM_BAR_ENABLE 0x0a80 - -#define MV64360_IDMA2MEM_ACC_PROT_0 0x0a70 -#define MV64360_IDMA2MEM_ACC_PROT_1 0x0a74 -#define MV64360_IDMA2MEM_ACC_PROT_2 0x0a78 -#define MV64360_IDMA2MEM_ACC_PROT_3 0x0a7c - -#define MV64x60_IDMA_0_OFFSET 0x0800 -#define MV64x60_IDMA_1_OFFSET 0x0804 -#define MV64x60_IDMA_2_OFFSET 0x0808 -#define MV64x60_IDMA_3_OFFSET 0x080c -#define MV64x60_IDMA_4_OFFSET 0x0900 -#define MV64x60_IDMA_5_OFFSET 0x0904 -#define MV64x60_IDMA_6_OFFSET 0x0908 -#define MV64x60_IDMA_7_OFFSET 0x090c - -#define MV64x60_IDMA_BYTE_COUNT (0x0800 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_SRC_ADDR (0x0810 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_DST_ADDR (0x0820 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_NEXT_DESC (0x0830 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_CUR_DESC (0x0870 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_SRC_PCI_ADDR_HI (0x0890 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_DST_PCI_ADDR_HI (0x08a0 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI (0x08b0 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_CONTROL_LO (0x0840 - MV64x60_IDMA_0_OFFSET) -#define MV64x60_IDMA_CONTROL_HI (0x0880 - MV64x60_IDMA_0_OFFSET) - -#define MV64x60_IDMA_0_3_ARBITER_CNTL 0x0860 -#define MV64x60_IDMA_4_7_ARBITER_CNTL 0x0960 - -#define MV64x60_IDMA_0_3_XBAR_TO 0x08d0 -#define MV64x60_IDMA_4_7_XBAR_TO 0x09d0 - -#define MV64x60_IDMA_0_3_INTR_CAUSE 0x08c0 -#define MV64x60_IDMA_0_3_INTR_MASK 0x08c4 -#define MV64x60_IDMA_0_3_ERROR_ADDR 0x08c8 -#define MV64x60_IDMA_0_3_ERROR_SELECT 0x08cc -#define MV64x60_IDMA_4_7_INTR_CAUSE 0x09c0 -#define MV64x60_IDMA_4_7_INTR_MASK 0x09c4 -#define MV64x60_IDMA_4_7_ERROR_ADDR 0x09c8 -#define MV64x60_IDMA_4_7_ERROR_SELECT 0x09cc - -/* - ***************************************************************************** - * - * Watchdog Timer Interface Registers - * - ***************************************************************************** - */ - -#define MV64x60_WDT_WDC 0xb410 -#define MV64x60_WDT_WDV 0xb414 - - -/* - ***************************************************************************** - * - * General Purpose Pins Controller Interface Registers - * - ***************************************************************************** - */ - -#define MV64x60_GPP_IO_CNTL 0xf100 -#define MV64x60_GPP_LEVEL_CNTL 0xf110 -#define MV64x60_GPP_VALUE 0xf104 -#define MV64x60_GPP_INTR_CAUSE 0xf108 -#define MV64x60_GPP_INTR_MASK 0xf10c -#define MV64x60_GPP_VALUE_SET 0xf118 -#define MV64x60_GPP_VALUE_CLR 0xf11c - - -/* - ***************************************************************************** - * - * Multi-Purpose Pins Controller Interface Registers - * - ***************************************************************************** - */ - -#define MV64x60_MPP_CNTL_0 0xf000 -#define MV64x60_MPP_CNTL_1 0xf004 -#define MV64x60_MPP_CNTL_2 0xf008 -#define MV64x60_MPP_CNTL_3 0xf00c -#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 - -#define MV64x60_ETH_BAR_GAP 0x8 -#define MV64x60_ETH_SIZE_REG_GAP 0x8 -#define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define MV64x60_ETH_PORT_ACCESS_CTRL_GAP 0x4 - -#define MV64x60_EBAR_ATTR_DRAM_CS0 0x00000E00 -#define MV64x60_EBAR_ATTR_DRAM_CS1 0x00000D00 -#define MV64x60_EBAR_ATTR_DRAM_CS2 0x00000B00 -#define MV64x60_EBAR_ATTR_DRAM_CS3 0x00000700 - -#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define MV64x60_EBAR_ATTR_CBS_SRAM 0x00000000 -#define MV64x60_EBAR_ATTR_CBS_CPU_BUS 0x00000800 - - -/* - ***************************************************************************** - * - * Interrupt Controller Interface Registers - * - ***************************************************************************** - */ - -#define GT64260_IC_OFFSET 0x0c18 - -#define GT64260_IC_MAIN_CAUSE_LO 0x0c18 -#define GT64260_IC_MAIN_CAUSE_HI 0x0c68 -#define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c -#define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c -#define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 -#define GT64260_IC_PCI0_INTR_MASK_LO 0x0c24 -#define GT64260_IC_PCI0_INTR_MASK_HI 0x0c64 -#define GT64260_IC_PCI0_SELECT_CAUSE 0x0c74 -#define GT64260_IC_PCI1_INTR_MASK_LO 0x0ca4 -#define GT64260_IC_PCI1_INTR_MASK_HI 0x0ce4 -#define GT64260_IC_PCI1_SELECT_CAUSE 0x0cf4 -#define GT64260_IC_CPU_INT_0_MASK 0x0e60 -#define GT64260_IC_CPU_INT_1_MASK 0x0e64 -#define GT64260_IC_CPU_INT_2_MASK 0x0e68 -#define GT64260_IC_CPU_INT_3_MASK 0x0e6c - -#define MV64360_IC_OFFSET 0x0000 - -#define MV64360_IC_MAIN_CAUSE_LO 0x0004 -#define MV64360_IC_MAIN_CAUSE_HI 0x000c -#define MV64360_IC_CPU0_INTR_MASK_LO 0x0014 -#define MV64360_IC_CPU0_INTR_MASK_HI 0x001c -#define MV64360_IC_CPU0_SELECT_CAUSE 0x0024 -#define MV64360_IC_CPU1_INTR_MASK_LO 0x0034 -#define MV64360_IC_CPU1_INTR_MASK_HI 0x003c -#define MV64360_IC_CPU1_SELECT_CAUSE 0x0044 -#define MV64360_IC_INT0_MASK_LO 0x0054 -#define MV64360_IC_INT0_MASK_HI 0x005c -#define MV64360_IC_INT0_SELECT_CAUSE 0x0064 -#define MV64360_IC_INT1_MASK_LO 0x0074 -#define MV64360_IC_INT1_MASK_HI 0x007c -#define MV64360_IC_INT1_SELECT_CAUSE 0x0084 - -#endif /* __ASMPPC_MV64x60_DEFS_H */ diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h deleted file mode 100644 index 3909a2eec286..000000000000 --- a/include/asm-ppc/ocp.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * ocp.h - * - * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) - * Mipsys - France - * - * Derived from work (c) Armin Kuster akuster@pacbell.net - * - * Additional support and port to 2.6 LDM/sysfs by - * Matt Porter <mporter@kernel.crashing.org> - * Copyright 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * TODO: - Add get/put interface & fixup locking to provide same API for - * 2.4 and 2.5 - * - Rework PM callbacks - */ - -#ifdef __KERNEL__ -#ifndef __OCP_H__ -#define __OCP_H__ - -#include <linux/init.h> -#include <linux/list.h> -#include <linux/device.h> -#include <linux/rwsem.h> - -#include <asm/mmu.h> -#include <asm/ocp_ids.h> - -#ifdef CONFIG_PPC_OCP - -#define OCP_MAX_IRQS 7 -#define MAX_EMACS 4 -#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */ -#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */ -#define OCP_NULL_TYPE -1 /* used to mark end of list */ -#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */ -#define OCP_PADDR_NA 0 /* No MMIO registers */ - -#define OCP_ANY_ID (~0) -#define OCP_ANY_INDEX -1 - -extern struct list_head ocp_devices; -extern struct rw_semaphore ocp_devices_sem; - -struct ocp_device_id { - unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */ - unsigned long driver_data; /* Data private to the driver */ -}; - - -/* - * Static definition of an OCP device. - * - * @vendor: Vendor code. It is _STRONGLY_ discouraged to use - * the vendor code as a way to match a unique device, - * though I kept that possibility open, you should - * really define different function codes for different - * device types - * @function: This is the function code for this device. - * @index: This index is used for mapping the Nth function of a - * given core. This is typically used for cross-driver - * matching, like looking for a given MAL or ZMII from - * an EMAC or for getting to the proper set of DCRs. - * Indices are no longer magically calculated based on - * structure ordering, they have to be actually coded - * into the ocp_def to avoid any possible confusion - * I _STRONGLY_ (again ? wow !) encourage anybody relying - * on index mapping to encode the "target" index in an - * associated structure pointed to by "additions", see - * how it's done for the EMAC driver. - * @paddr: Device physical address (may not mean anything...) - * @irq: Interrupt line for this device (TODO: think about making - * an array with this) - * @pm: Currently, contains the bitmask in CPMFR DCR for the device - * @additions: Optionally points to a function specific structure - * providing additional informations for a given device - * instance. It's currently used by the EMAC driver for MAL - * channel & ZMII port mapping among others. - * @show: Optionally points to a function specific structure - * providing a sysfs show routine for additions fields. - */ -struct ocp_def { - unsigned int vendor; - unsigned int function; - int index; - phys_addr_t paddr; - int irq; - unsigned long pm; - void *additions; - void (*show)(struct device *); -}; - - -/* Struct for a given device instance */ -struct ocp_device { - struct list_head link; - char name[80]; /* device name */ - struct ocp_def *def; /* device definition */ - void *drvdata; /* driver data for this device */ - struct ocp_driver *driver; - u32 current_state; /* Current operating state. In ACPI-speak, - this is D0-D3, D0 being fully functional, - and D3 being off. */ - struct device dev; -}; - -struct ocp_driver { - struct list_head node; - char *name; - const struct ocp_device_id *id_table; /* NULL if wants all devices */ - int (*probe) (struct ocp_device *dev); /* New device inserted */ - void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */ - int (*suspend) (struct ocp_device *dev, pm_message_t state); /* Device suspended */ - int (*resume) (struct ocp_device *dev); /* Device woken up */ - struct device_driver driver; -}; - -#define to_ocp_dev(n) container_of(n, struct ocp_device, dev) -#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver) - -/* Similar to the helpers above, these manipulate per-ocp_dev - * driver-specific data. Currently stored as ocp_dev::ocpdev, - * a void pointer, but it is not present on older kernels. - */ -static inline void * -ocp_get_drvdata(struct ocp_device *pdev) -{ - return pdev->drvdata; -} - -static inline void -ocp_set_drvdata(struct ocp_device *pdev, void *data) -{ - pdev->drvdata = data; -} - -#if defined (CONFIG_PM) -/* - * This is right for the IBM 405 and 440 but will need to be - * generalized if the OCP stuff gets used on other processors. - */ -static inline void -ocp_force_power_off(struct ocp_device *odev) -{ - mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm); -} - -static inline void -ocp_force_power_on(struct ocp_device *odev) -{ - mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm); -} -#else -#define ocp_force_power_off(x) (void)(x) -#define ocp_force_power_on(x) (void)(x) -#endif - -/* Register/Unregister an OCP driver */ -extern int ocp_register_driver(struct ocp_driver *drv); -extern void ocp_unregister_driver(struct ocp_driver *drv); - -/* Build list of devices */ -extern int ocp_early_init(void) __init; - -/* Find a device by index */ -extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index); - -/* Get a def by index */ -extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index); - -/* Add a device by index */ -extern int ocp_add_one_device(struct ocp_def *def); - -/* Remove a device by index */ -extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index); - -/* Iterate over devices and execute a routine */ -extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg); - -/* Sysfs support */ -#define OCP_SYSFS_ADDTL(type, format, name, field) \ -static ssize_t \ -show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf) \ -{ \ - struct ocp_device *odev = to_ocp_dev(dev); \ - type *add = odev->def->additions; \ - \ - return sprintf(buf, format, add->field); \ -} \ -static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL); - -#ifdef CONFIG_IBM_OCP -#include <asm/ibm_ocp.h> -#endif - -#endif /* CONFIG_PPC_OCP */ -#endif /* __OCP_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h deleted file mode 100644 index 8ae4b311a37c..000000000000 --- a/include/asm-ppc/ocp_ids.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * ocp_ids.h - * - * OCP device ids based on the ideas from PCI - * - * The numbers below are almost completely arbitrary, and in fact - * strings might work better. -- paulus - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * Vender device - * [xxxx] [xxxx] - * - * Keep in order, please - */ - -/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */ - -#define OCP_VENDOR_INVALID 0x0000 -#define OCP_VENDOR_ARM 0x0004 -#define OCP_VENDOR_FREESCALE 0x1057 -#define OCP_VENDOR_IBM 0x1014 -#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE -#define OCP_VENDOR_XILINX 0x10ee -#define OCP_VENDOR_UNKNOWN 0xFFFF - -/* device identification */ - -/* define type */ -#define OCP_FUNC_INVALID 0x0000 - -/* system 0x0001 - 0x001F */ - -/* Timers 0x0020 - 0x002F */ - -/* Serial 0x0030 - 0x006F*/ -#define OCP_FUNC_16550 0x0031 -#define OCP_FUNC_IIC 0x0032 -#define OCP_FUNC_USB 0x0033 -#define OCP_FUNC_PSC_UART 0x0034 - -/* Memory devices 0x0090 - 0x009F */ -#define OCP_FUNC_MAL 0x0090 -#define OCP_FUNC_DMA 0x0091 - -/* Display 0x00A0 - 0x00AF */ - -/* Sound 0x00B0 - 0x00BF */ - -/* Mass Storage 0x00C0 - 0xxCF */ -#define OCP_FUNC_IDE 0x00C0 - -/* Misc 0x00D0 - 0x00DF*/ -#define OCP_FUNC_GPIO 0x00D0 -#define OCP_FUNC_ZMII 0x00D1 -#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */ -#define OCP_FUNC_RGMII 0x00D3 -#define OCP_FUNC_TAH 0x00D4 -#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */ - -/* Network 0x0200 - 0x02FF */ -#define OCP_FUNC_EMAC 0x0200 -#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */ - -/* Bridge devices 0xE00 - 0xEFF */ -#define OCP_FUNC_OPB 0x0E00 - -#define OCP_FUNC_UNKNOWN 0xFFFF diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h deleted file mode 100644 index 778d5726212c..000000000000 --- a/include/asm-ppc/open_pic.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling - * - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - */ - -#ifndef _PPC_KERNEL_OPEN_PIC_H -#define _PPC_KERNEL_OPEN_PIC_H - -#include <linux/irq.h> - -#define OPENPIC_SIZE 0x40000 - -/* - * Non-offset'ed vector numbers - */ - -#define OPENPIC_VEC_TIMER 110 /* and up */ -#define OPENPIC_VEC_IPI 118 /* and up */ -#define OPENPIC_VEC_SPURIOUS 255 - -/* Priorities */ -#define OPENPIC_PRIORITY_IPI_BASE 10 -#define OPENPIC_PRIORITY_DEFAULT 4 -#define OPENPIC_PRIORITY_NMI 9 - -/* OpenPIC IRQ controller structure */ -extern struct hw_interrupt_type open_pic; - -/* OpenPIC IPI controller structure */ -#ifdef CONFIG_SMP -extern struct hw_interrupt_type open_pic_ipi; -#endif /* CONFIG_SMP */ - -extern u_int OpenPIC_NumInitSenses; -extern u_char *OpenPIC_InitSenses; -extern void __iomem * OpenPIC_Addr; -extern int epic_serial_mode; - -/* Exported functions */ -extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr); -extern void openpic_init(int linux_irq_offset); -extern void openpic_init_nmi_irq(u_int irq); -extern void openpic_set_irq_priority(u_int irq, u_int pri); -extern void openpic_hookup_cascade(u_int irq, char *name, - int (*cascade_fn)(void)); -extern u_int openpic_irq(void); -extern void openpic_eoi(void); -extern void openpic_request_IPIs(void); -extern void do_openpic_setup_cpu(void); -extern int openpic_get_irq(void); -extern void openpic_reset_processor_phys(u_int cpumask); -extern void openpic_setup_ISU(int isu_num, unsigned long addr); -extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask); -extern void smp_openpic_message_pass(int target, int msg); -extern void openpic_set_k2_cascade(int irq); -extern void openpic_set_priority(u_int pri); -extern u_int openpic_get_priority(void); - -extern inline int openpic_to_irq(int irq) -{ - /* IRQ 0 usually means 'disabled'.. don't mess with it - * exceptions to this (sandpoint maybe?) - * shouldn't use openpic_to_irq - */ - if (irq != 0){ - return irq += NUM_8259_INTERRUPTS; - } else { - return 0; - } -} -/* Support for second openpic on G5 macs */ - -// FIXME: To be replaced by sane cascaded controller management */ - -#define PMAC_OPENPIC2_OFFSET 128 - -#define OPENPIC2_VEC_TIMER 110 /* and up */ -#define OPENPIC2_VEC_IPI 118 /* and up */ -#define OPENPIC2_VEC_SPURIOUS 127 - - -extern void* OpenPIC2_Addr; - -/* Exported functions */ -extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr); -extern void openpic2_init(int linux_irq_offset); -extern void openpic2_init_nmi_irq(u_int irq); -extern u_int openpic2_irq(void); -extern void openpic2_eoi(void); -extern int openpic2_get_irq(void); -extern void openpic2_setup_ISU(int isu_num, unsigned long addr); -#endif /* _PPC_KERNEL_OPEN_PIC_H */ diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h deleted file mode 100644 index 37e4756b6b2d..000000000000 --- a/include/asm-ppc/page.h +++ /dev/null @@ -1,140 +0,0 @@ -#ifndef _PPC_PAGE_H -#define _PPC_PAGE_H - -#include <asm/asm-compat.h> - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT 12 -#define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT) - -/* - * Subtle: this is an int (not an unsigned long) and so it - * gets extended to 64 bits the way want (i.e. with 1s). -- paulus - */ -#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) - -#ifdef __KERNEL__ - -/* This must match what is in arch/ppc/Makefile */ -#define PAGE_OFFSET CONFIG_KERNEL_START -#define KERNELBASE PAGE_OFFSET -#define is_kernel_addr(x) ((x) >= PAGE_OFFSET) - -#ifndef __ASSEMBLY__ - -/* - * The basic type of a PTE - 64 bits for those CPUs with > 32 bit - * physical addressing. For now this just the IBM PPC440. - */ -#ifdef CONFIG_PTE_64BIT -typedef unsigned long long pte_basic_t; -#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */ -#define PTE_FMT "%16Lx" -#else -typedef unsigned long pte_basic_t; -#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */ -#define PTE_FMT "%.8lx" -#endif - -/* align addr on a size boundary - adjust address up/down if needed */ -#define _ALIGN_UP(addr,size) (((addr)+((size)-1))&(~((size)-1))) -#define _ALIGN_DOWN(addr,size) ((addr)&(~((size)-1))) - -/* align addr on a size boundary - adjust address up if needed */ -#define _ALIGN(addr,size) _ALIGN_UP(addr,size) - -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE) - - -#undef STRICT_MM_TYPECHECKS - -#ifdef STRICT_MM_TYPECHECKS -/* - * These are used to make use of C type-checking.. - */ -typedef struct { pte_basic_t pte; } pte_t; -typedef struct { unsigned long pmd; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((x).pmd) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -#else -/* - * .. while these make it easier on the compiler - */ -typedef pte_basic_t pte_t; -typedef unsigned long pmd_t; -typedef unsigned long pgd_t; -typedef unsigned long pgprot_t; - -#define pte_val(x) (x) -#define pmd_val(x) (x) -#define pgd_val(x) (x) -#define pgprot_val(x) (x) - -#define __pte(x) (x) -#define __pmd(x) (x) -#define __pgd(x) (x) -#define __pgprot(x) (x) - -#endif - -struct page; -extern void clear_pages(void *page, int order); -static inline void clear_page(void *page) { clear_pages(page, 0); } -extern void copy_page(void *to, void *from); -extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg); -extern void copy_user_page(void *to, void *from, unsigned long vaddr, - struct page *pg); - -#define PPC_MEMSTART 0 -#define PPC_MEMOFFSET PAGE_OFFSET - -#define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET) -#define ___va(paddr) ((paddr)+PPC_MEMOFFSET) - -extern int page_is_ram(unsigned long pfn); - -#define __pa(x) ___pa((unsigned long)(x)) -#define __va(x) ((void *)(___va((unsigned long)(x)))) - -#define ARCH_PFN_OFFSET 0 -#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) -#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT) - -#define pfn_valid(pfn) ((pfn) < max_mapnr) -#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) - -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int lz; - - size = (size-1) >> PAGE_SHIFT; - asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size)); - return 32 - lz; -} - -typedef struct page *pgtable_t; - -#endif /* __ASSEMBLY__ */ - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */ -#define __HAVE_ARCH_GATE_AREA 1 - -#include <asm-generic/memory_model.h> -#endif /* __KERNEL__ */ -#endif /* _PPC_PAGE_H */ diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h deleted file mode 100644 index 81a2d0fdaf00..000000000000 --- a/include/asm-ppc/pc_serial.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * include/asm-ppc/pc_serial.h - * - * This is basically a copy of include/asm-i386/serial.h. - * It is used on platforms which have an ISA bus and thus are likely - * to have PC-style serial ports at the legacy I/O port addresses. - * It also includes the definitions for the fourport, accent, boca - * and hub6 multiport serial cards, although I have never heard of - * anyone using any of those on a PPC platform. -- paulus - */ - - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD ( 1843200 / 16 ) - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 4 -#endif - -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - -#define SERIAL_PORT_DFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ - { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ - { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h deleted file mode 100644 index 4d35b844bc58..000000000000 --- a/include/asm-ppc/pci-bridge.h +++ /dev/null @@ -1,151 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _ASM_PCI_BRIDGE_H -#define _ASM_PCI_BRIDGE_H - -#include <linux/ioport.h> -#include <linux/pci.h> - -struct device_node; -struct pci_controller; - -/* - * pci_io_base returns the memory address at which you can access - * the I/O space for PCI bus number `bus' (or NULL on error). - */ -extern void __iomem *pci_bus_io_base(unsigned int bus); -extern unsigned long pci_bus_io_base_phys(unsigned int bus); -extern unsigned long pci_bus_mem_base_phys(unsigned int bus); - -/* Allocate a new PCI host bridge structure */ -extern struct pci_controller* pcibios_alloc_controller(void); - -/* Helper function for setting up resources */ -extern void pci_init_resource(struct resource *res, resource_size_t start, - resource_size_t end, int flags, char *name); - -/* Get the PCI host controller for a bus */ -extern struct pci_controller* pci_bus_to_hose(int bus); - -/* Get the PCI host controller for an OF device */ -extern struct pci_controller* -pci_find_hose_for_OF_device(struct device_node* node); - -/* Fill up host controller resources from the OF node */ -extern void -pci_process_bridge_OF_ranges(struct pci_controller *hose, - struct device_node *dev, int primary); - -/* - * Structure of a PCI controller (host bridge) - */ -struct pci_controller { - int index; /* PCI domain number */ - struct pci_controller *next; - struct pci_bus *bus; - void *arch_data; - struct device *parent; - - int first_busno; - int last_busno; - int bus_offset; - - void __iomem *io_base_virt; - resource_size_t io_base_phys; - - /* Some machines (PReP) have a non 1:1 mapping of - * the PCI memory space in the CPU bus space - */ - resource_size_t pci_mem_offset; - - struct pci_ops *ops; - volatile unsigned int __iomem *cfg_addr; - volatile void __iomem *cfg_data; - /* - * If set, indirect method will set the cfg_type bit as - * needed to generate type 1 configuration transactions. - */ - int set_cfg_type; - - /* Currently, we limit ourselves to 1 IO range and 3 mem - * ranges since the common pci_bus structure can't handle more - */ - struct resource io_resource; - struct resource mem_resources[3]; - int mem_resource_count; - - /* Host bridge I/O and Memory space - * Used for BAR placement algorithms - */ - struct resource io_space; - struct resource mem_space; -}; - -static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) -{ - return bus->sysdata; -} - -/* These are used for config access before all the PCI probing - has been done. */ -int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, - int where, u8 *val); -int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, - int where, u16 *val); -int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, - int where, u32 *val); -int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, - int where, u8 val); -int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, - int where, u16 val); -int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, - int where, u32 val); - -extern void setup_indirect_pci_nomap(struct pci_controller* hose, - void __iomem *cfg_addr, void __iomem *cfg_data); -extern void setup_indirect_pci(struct pci_controller* hose, - u32 cfg_addr, u32 cfg_data); -extern void setup_grackle(struct pci_controller *hose); - -extern unsigned char common_swizzle(struct pci_dev *, unsigned char *); - -/* - * The following code swizzles for exactly one bridge. The routine - * common_swizzle below handles multiple bridges. But there are a - * some boards that don't follow the PCI spec's suggestion so we - * break this piece out separately. - */ -static inline unsigned char bridge_swizzle(unsigned char pin, - unsigned char idsel) -{ - return (((pin-1) + idsel) % 4) + 1; -} - -/* - * The following macro is used to lookup irqs in a standard table - * format for those PPC systems that do not already have PCI - * interrupts properly routed. - */ -/* FIXME - double check this */ -#define PCI_IRQ_TABLE_LOOKUP \ -({ long _ctl_ = -1; \ - if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ - _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ - _ctl_; }) - -/* - * Scan the buses below a given PCI host bridge and assign suitable - * resources to all devices found. - */ -extern int pciauto_bus_scan(struct pci_controller *, int); - -#ifdef CONFIG_PCI -extern unsigned long pci_address_to_pio(phys_addr_t address); -#else -static inline unsigned long pci_address_to_pio(phys_addr_t address) -{ - return (unsigned long)-1; -} -#endif - -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h deleted file mode 100644 index d2442cd72a59..000000000000 --- a/include/asm-ppc/pci.h +++ /dev/null @@ -1,156 +0,0 @@ -#ifndef __PPC_PCI_H -#define __PPC_PCI_H -#ifdef __KERNEL__ - -#include <linux/types.h> -#include <linux/slab.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <asm/scatterlist.h> -#include <asm/io.h> -#include <asm/pci-bridge.h> -#include <asm-generic/pci-dma-compat.h> - -struct pci_dev; - -/* Values for the `which' argument to sys_pciconfig_iobase syscall. */ -#define IOBASE_BRIDGE_NUMBER 0 -#define IOBASE_MEMORY 1 -#define IOBASE_IO 2 -#define IOBASE_ISA_IO 3 -#define IOBASE_ISA_MEM 4 - -/* - * Set this to 1 if you want the kernel to re-assign all PCI - * bus numbers - */ -extern int pci_assign_all_buses; - -#define pcibios_assign_all_busses() (pci_assign_all_buses) -#define pcibios_scan_all_fns(a, b) 0 - -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM 0x10000000 - -extern inline void pcibios_set_master(struct pci_dev *dev) -{ - /* No special bus mastering setup handling */ -} - -extern inline void pcibios_penalize_isa_irq(int irq, int active) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - -extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res); - -/* - * The PCI bus bridge can translate addresses issued by the processor(s) - * into a different address on the PCI bus. On 32-bit cpus, we assume - * this mapping is 1-1, but on 64-bit systems it often isn't. - * - * Obsolete ! Drivers should now use pci_resource_to_bus - */ -extern unsigned long phys_to_bus(unsigned long pa); -extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr); -extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr); - -/* The PCI address space does equal the physical memory - * address space. The networking and block device layers use - * this boolean for bounce buffer decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -#ifdef CONFIG_NOT_COHERENT_CACHE -/* - * pci_unmap_{page,single} are NOPs but pci_dma_sync_single_for_cpu() - * and so on are not, so... - */ - -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ - dma_addr_t ADDR_NAME; -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ - __u32 LEN_NAME; -#define pci_unmap_addr(PTR, ADDR_NAME) \ - ((PTR)->ADDR_NAME) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ - (((PTR)->ADDR_NAME) = (VAL)) -#define pci_unmap_len(PTR, LEN_NAME) \ - ((PTR)->LEN_NAME) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ - (((PTR)->LEN_NAME) = (VAL)) - -#else /* coherent */ - -/* pci_unmap_{page,single} is a nop so... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) - -#endif /* CONFIG_NOT_COHERENT_CACHE */ - -#ifdef CONFIG_PCI -static inline void pci_dma_burst_advice(struct pci_dev *pdev, - enum pci_dma_burst_strategy *strat, - unsigned long *strategy_parameter) -{ - *strat = PCI_DMA_BURST_INFINITY; - *strategy_parameter = ~0UL; -} -#endif - -/* Return the index of the PCI controller for device PDEV. */ -#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index - -/* Set the name of the bus as it appears in /proc/bus/pci */ -static inline int pci_proc_domain(struct pci_bus *bus) -{ - return 0; -} - -/* Map a range of PCI memory or I/O space for a device into user space */ -int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, - enum pci_mmap_state mmap_state, int write_combine); - -/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ -#define HAVE_PCI_MMAP 1 - -extern void -pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, - struct resource *res); - -extern void -pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region); - -static inline struct resource * -pcibios_select_root(struct pci_dev *pdev, struct resource *res) -{ - struct resource *root = NULL; - - if (res->flags & IORESOURCE_IO) - root = &ioport_resource; - if (res->flags & IORESOURCE_MEM) - root = &iomem_resource; - - return root; -} - -struct file; -extern pgprot_t pci_phys_mem_access_prot(struct file *file, - unsigned long pfn, - unsigned long size, - pgprot_t prot); - -#define HAVE_ARCH_PCI_RESOURCE_TO_USER -extern void pci_resource_to_user(const struct pci_dev *dev, int bar, - const struct resource *rsrc, - resource_size_t *start, resource_size_t *end); - - -#endif /* __KERNEL__ */ - -#endif /* __PPC_PCI_H */ diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h deleted file mode 100644 index fd4d1d74cfb1..000000000000 --- a/include/asm-ppc/pgalloc.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_PGALLOC_H -#define _PPC_PGALLOC_H - -#include <linux/threads.h> - -extern void __bad_pte(pmd_t *pmd); - -extern pgd_t *pgd_alloc(struct mm_struct *mm); -extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); - -/* - * We don't have any real pmd's, and this code never triggers because - * the pgd will always be present.. - */ -#define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); }) -#define pmd_free(mm, x) do { } while (0) -#define __pmd_free_tlb(tlb,x) do { } while (0) -#define pgd_populate(mm, pmd, pte) BUG() - -#ifndef CONFIG_BOOKE -#define pmd_populate_kernel(mm, pmd, pte) \ - (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) -#define pmd_populate(mm, pmd, pte) \ - (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) -#define pmd_pgtable(pmd) pmd_page(pmd) -#else -#define pmd_populate_kernel(mm, pmd, pte) \ - (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) -#define pmd_populate(mm, pmd, pte) \ - (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) -#define pmd_pgtable(pmd) pmd_page(pmd) -#endif - -extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); -extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr); -extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); -extern void pte_free(struct mm_struct *mm, pgtable_t pte); - -#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) - -#define check_pgt_cache() do { } while (0) - -#endif /* _PPC_PGALLOC_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h deleted file mode 100644 index 55f9d38e3bf8..000000000000 --- a/include/asm-ppc/pgtable.h +++ /dev/null @@ -1,771 +0,0 @@ -#ifdef __KERNEL__ -#ifndef _PPC_PGTABLE_H -#define _PPC_PGTABLE_H - -#include <asm-generic/4level-fixup.h> - - -#ifndef __ASSEMBLY__ -#include <linux/sched.h> -#include <linux/threads.h> -#include <asm/processor.h> /* For TASK_SIZE */ -#include <asm/mmu.h> -#include <asm/page.h> -#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */ -struct mm_struct; - -extern unsigned long va_to_phys(unsigned long address); -extern pte_t *va_to_pte(unsigned long address); -extern unsigned long ioremap_bot, ioremap_base; -#endif /* __ASSEMBLY__ */ - -/* - * The PowerPC MMU uses a hash table containing PTEs, together with - * a set of 16 segment registers (on 32-bit implementations), to define - * the virtual to physical address mapping. - * - * We use the hash table as an extended TLB, i.e. a cache of currently - * active mappings. We maintain a two-level page table tree, much - * like that used by the i386, for the sake of the Linux memory - * management code. Low-level assembler code in hashtable.S - * (procedure hash_page) is responsible for extracting ptes from the - * tree and putting them into the hash table when necessary, and - * updating the accessed and modified bits in the page table tree. - */ - -/* - * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. - * We also use the two level tables, but we can put the real bits in them - * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, - * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has - * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit - * based upon user/super access. The TLB does not have accessed nor write - * protect. We assume that if the TLB get loaded with an entry it is - * accessed, and overload the changed bit for write protect. We use - * two bits in the software pte that are supposed to be set to zero in - * the TLB entry (24 and 25) for these indicators. Although the level 1 - * descriptor contains the guarded and writethrough/copyback bits, we can - * set these at the page level since they get copied from the Mx_TWC - * register when the TLB entry is loaded. We will use bit 27 for guard, since - * that is where it exists in the MD_TWC, and bit 26 for writethrough. - * These will get masked from the level 2 descriptor at TLB load time, and - * copied to the MD_TWC before it gets loaded. - * Large page sizes added. We currently support two sizes, 4K and 8M. - * This also allows a TLB hander optimization because we can directly - * load the PMD into MD_TWC. The 8M pages are only used for kernel - * mapping of well known areas. The PMD (PGD) entries contain control - * flags in addition to the address, so care must be taken that the - * software no longer assumes these are only pointers. - */ - -/* - * At present, all PowerPC 400-class processors share a similar TLB - * architecture. The instruction and data sides share a unified, - * 64-entry, fully-associative TLB which is maintained totally under - * software control. In addition, the instruction side has a - * hardware-managed, 4-entry, fully-associative TLB which serves as a - * first level to the shared TLB. These two TLBs are known as the UTLB - * and ITLB, respectively (see "mmu.h" for definitions). - */ - -/* - * The normal case is that PTEs are 32-bits and we have a 1-page - * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus - * - * For any >32-bit physical address platform, we can use the following - * two level page table layout where the pgdir is 8KB and the MS 13 bits - * are an index to the second level table. The combined pgdir/pmd first - * level has 2048 entries and the second level has 512 64-bit PTE entries. - * -Matt - */ -/* PMD_SHIFT determines the size of the area mapped by the PTE pages */ -#define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT) -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a top-level page table entry can map */ -#define PGDIR_SHIFT PMD_SHIFT -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * entries per page directory level: our page-table tree is two-level, so - * we don't really have any PMD directory. - */ -#define PTRS_PER_PTE (1 << PTE_SHIFT) -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) - -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0 - -#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) -#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e)) -#define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 64MB value just means that there will be a 64MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - * - * We no longer map larger than phys RAM with the BATs so we don't have - * to worry about the VMALLOC_OFFSET causing problems. We do have to worry - * about clashes between our early calls to ioremap() that start growing down - * from ioremap_base being run into the VM area allocations (growing upwards - * from VMALLOC_START). For this reason we have ioremap_bot to check when - * we actually run into our mappings setup in the early boot with the VM - * system. This really does become a problem for machines with good amounts - * of RAM. -- Cort - */ -#define VMALLOC_OFFSET (0x1000000) /* 16M */ -#ifdef PPC_PIN_SIZE -#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) -#else -#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) -#endif -#define VMALLOC_END ioremap_bot - -/* - * Bits in a linux-style PTE. These match the bits in the - * (hardware-defined) PowerPC PTE as closely as possible. - */ - -#if defined(CONFIG_40x) - -/* There are several potential gotchas here. The 40x hardware TLBLO - field looks like this: - - 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - RPN..................... 0 0 EX WR ZSEL....... W I M G - - Where possible we make the Linux PTE bits match up with this - - - bits 20 and 21 must be cleared, because we use 4k pages (40x can - support down to 1k pages), this is done in the TLBMiss exception - handler. - - We use only zones 0 (for kernel pages) and 1 (for user pages) - of the 16 available. Bit 24-26 of the TLB are cleared in the TLB - miss handler. Bit 27 is PAGE_USER, thus selecting the correct - zone. - - PRESENT *must* be in the bottom two bits because swap cache - entries use the top 30 bits. Because 40x doesn't support SMP - anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 - is cleared in the TLB miss handler before the TLB entry is loaded. - - All other bits of the PTE are loaded into TLBLO without - modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for - software PTE bits. We actually use use bits 21, 24, 25, and - 30 respectively for the software bits: ACCESSED, DIRTY, RW, and - PRESENT. -*/ - -/* Definitions for 40x embedded chips. */ -#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ -#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */ -#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ -#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ -#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ -#define _PAGE_USER 0x010 /* matches one of the zone permission bits */ -#define _PAGE_RW 0x040 /* software: Writes permitted */ -#define _PAGE_DIRTY 0x080 /* software: dirty page */ -#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ -#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ -#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ - -#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */ -#define _PMD_BAD 0x802 -#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */ -#define _PMD_SIZE_4M 0x0c0 -#define _PMD_SIZE_16M 0x0e0 -#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4)) - -#elif defined(CONFIG_44x) -/* - * Definitions for PPC440 - * - * Because of the 3 word TLB entries to support 36-bit addressing, - * the attribute are difficult to map in such a fashion that they - * are easily loaded during exception processing. I decided to - * organize the entry so the ERPN is the only portion in the - * upper word of the PTE and the attribute bits below are packed - * in as sensibly as they can be in the area below a 4KB page size - * oriented RPN. This at least makes it easy to load the RPN and - * ERPN fields in the TLB. -Matt - * - * Note that these bits preclude future use of a page size - * less than 4KB. - * - * - * PPC 440 core has following TLB attribute fields; - * - * TLB1: - * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - * RPN................................. - - - - - - ERPN....... - * - * TLB2: - * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR - * - * There are some constrains and options, to decide mapping software bits - * into TLB entry. - * - * - PRESENT *must* be in the bottom three bits because swap cache - * entries use the top 29 bits for TLB2. - * - * - FILE *must* be in the bottom three bits because swap cache - * entries use the top 29 bits for TLB2. - * - * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it - * doesn't support SMP. So we can use this as software bit, like - * DIRTY. - * - * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used - * for memory protection related functions (see PTE structure in - * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the - * above bits. Note that the bit values are CPU specific, not architecture - * specific. - * - * The kernel PTE entry holds an arch-dependent swp_entry structure under - * certain situations. In other words, in such situations some portion of - * the PTE bits are used as a swp_entry. In the PPC implementation, the - * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still - * hold protection values. That means the three protection bits are - * reserved for both PTE and SWAP entry at the most significant three - * LSBs. - * - * There are three protection bits available for SWAP entry: - * _PAGE_PRESENT - * _PAGE_FILE - * _PAGE_HASHPTE (if HW has) - * - * So those three bits have to be inside of 0-2nd LSB of PTE. - * - */ - -#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ -#define _PAGE_RW 0x00000002 /* S: Write permission */ -#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ -#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ -#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ -#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ -#define _PAGE_USER 0x00000040 /* S: User page */ -#define _PAGE_ENDIAN 0x00000080 /* H: E bit */ -#define _PAGE_GUARDED 0x00000100 /* H: G bit */ -#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */ -#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ -#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ - -/* TODO: Add large page lowmem mapping support */ -#define _PMD_PRESENT 0 -#define _PMD_PRESENT_MASK (PAGE_MASK) -#define _PMD_BAD (~PAGE_MASK) - -/* ERPN in a PTE never gets cleared, ignore it */ -#define _PTE_NONE_MASK 0xffffffff00000000ULL - -#elif defined(CONFIG_8xx) -/* Definitions for 8xx embedded chips. */ -#define _PAGE_PRESENT 0x0001 /* Page is valid */ -#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */ -#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ -#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ - -/* These five software bits must be masked out when the entry is loaded - * into the TLB. - */ -#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ -#define _PAGE_GUARDED 0x0010 /* software: guarded access */ -#define _PAGE_DIRTY 0x0020 /* software: page changed */ -#define _PAGE_RW 0x0040 /* software: user write access allowed */ -#define _PAGE_ACCESSED 0x0080 /* software: page referenced */ - -/* Setting any bits in the nibble with the follow two controls will - * require a TLB exception handler change. It is assumed unused bits - * are always zero. - */ -#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ -#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ - -#define _PMD_PRESENT 0x0001 -#define _PMD_BAD 0x0ff0 -#define _PMD_PAGE_MASK 0x000c -#define _PMD_PAGE_8M 0x000c - -#define _PTE_NONE_MASK _PAGE_ACCESSED - -#else /* CONFIG_6xx */ -/* Definitions for 60x, 740/750, etc. */ -#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ -#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ -#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */ -#define _PAGE_USER 0x004 /* usermode access allowed */ -#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ -#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ -#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ -#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ -#define _PAGE_DIRTY 0x080 /* C: page changed */ -#define _PAGE_ACCESSED 0x100 /* R: page referenced */ -#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */ -#define _PAGE_RW 0x400 /* software: user write access allowed */ - -#define _PTE_NONE_MASK _PAGE_HASHPTE - -#define _PMD_PRESENT 0 -#define _PMD_PRESENT_MASK (PAGE_MASK) -#define _PMD_BAD (~PAGE_MASK) -#endif - -/* - * Some bits are only used on some cpu families... - */ -#ifndef _PAGE_HASHPTE -#define _PAGE_HASHPTE 0 -#endif -#ifndef _PTE_NONE_MASK -#define _PTE_NONE_MASK 0 -#endif -#ifndef _PAGE_SHARED -#define _PAGE_SHARED 0 -#endif -#ifndef _PAGE_HWWRITE -#define _PAGE_HWWRITE 0 -#endif -#ifndef _PAGE_HWEXEC -#define _PAGE_HWEXEC 0 -#endif -#ifndef _PAGE_EXEC -#define _PAGE_EXEC 0 -#endif -#ifndef _PMD_PRESENT_MASK -#define _PMD_PRESENT_MASK _PMD_PRESENT -#endif -#ifndef _PMD_SIZE -#define _PMD_SIZE 0 -#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE() -#endif - -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) - -/* - * Note: the _PAGE_COHERENT bit automatically gets set in the hardware - * PTE if CONFIG_SMP is defined (hash_page does this); there is no need - * to have it in the Linux PTE, and in fact the bit could be reused for - * another purpose. -- paulus. - */ - -#ifdef CONFIG_44x -#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED) -#else -#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) -#endif -#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) -#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE) - -#ifdef CONFIG_PPC_STD_MMU -/* On standard PPC MMU, no user access implies kernel read/write access, - * so to write-protect kernel memory we must turn on user access */ -#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER) -#else -#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED) -#endif - -#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) -#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC) - -#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) -/* We want the debuggers to be able to set breakpoints anywhere, so - * don't write protect the kernel text */ -#define _PAGE_RAM_TEXT _PAGE_RAM -#else -#define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC) -#endif - -#define PAGE_NONE __pgprot(_PAGE_BASE) -#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) -#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) -#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) -#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) -#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) -#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) - -#define PAGE_KERNEL __pgprot(_PAGE_RAM) -#define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO) - -/* - * The PowerPC can only do execute protection on a segment (256MB) basis, - * not on a page basis. So we consider execute permission the same as read. - * Also, write permissions imply read permissions. - * This is the closest we can get.. - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY_X -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY_X -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY_X -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY_X - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY_X -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED_X -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY_X -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED_X - -#ifndef __ASSEMBLY__ -/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a - * kernel without large page PMD support */ -extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); - -/* - * Conversions between PTE values and page frame numbers. - */ - -/* in some case we want to additionaly adjust where the pfn is in the pte to - * allow room for more flags */ -#define PFN_SHIFT_OFFSET (PAGE_SHIFT) - -#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) -#define pte_page(x) pfn_to_page(pte_pfn(x)) - -#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\ - pgprot_val(prot)) -#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) - -/* - * ZERO_PAGE is a global shared page that is always zero: used - * for zero-mapped memory areas etc.. - */ -extern unsigned long empty_zero_page[1024]; -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) - -#endif /* __ASSEMBLY__ */ - -#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) -#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) -#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) - -#define pmd_none(pmd) (!pmd_val(pmd)) -#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) -#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) -#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) - -#ifndef __ASSEMBLY__ -/* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) - */ -static inline int pgd_none(pgd_t pgd) { return 0; } -static inline int pgd_bad(pgd_t pgd) { return 0; } -static inline int pgd_present(pgd_t pgd) { return 1; } -#define pgd_clear(xp) do { } while (0) - -#define pgd_page_vaddr(pgd) \ - ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ -static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } -static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } -static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } -static inline int pte_special(pte_t pte) { return 0; } - -static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } -static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } - -static inline pte_t pte_wrprotect(pte_t pte) { - pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } -static inline pte_t pte_mkclean(pte_t pte) { - pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } -static inline pte_t pte_mkold(pte_t pte) { - pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } - -static inline pte_t pte_mkwrite(pte_t pte) { - pte_val(pte) |= _PAGE_RW; return pte; } -static inline pte_t pte_mkdirty(pte_t pte) { - pte_val(pte) |= _PAGE_DIRTY; return pte; } -static inline pte_t pte_mkyoung(pte_t pte) { - pte_val(pte) |= _PAGE_ACCESSED; return pte; } -static inline pte_t pte_mkspecial(pte_t pte) { - return pte; } - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); - return pte; -} - -/* - * When flushing the tlb entry for a page, we also need to flush the hash - * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. - */ -extern int flush_hash_pages(unsigned context, unsigned long va, - unsigned long pmdval, int count); - -/* Add an HPTE to the hash table */ -extern void add_hash_page(unsigned context, unsigned long va, - unsigned long pmdval); - -/* - * Atomic PTE updates. - * - * pte_update clears and sets bit atomically, and returns - * the old pte value. In the 64-bit PTE case we lock around the - * low PTE word since we expect ALL flag bits to be there - */ -#ifndef CONFIG_PTE_64BIT -static inline unsigned long pte_update(pte_t *p, unsigned long clr, - unsigned long set) -{ - unsigned long old, tmp; - - __asm__ __volatile__("\ -1: lwarx %0,0,%3\n\ - andc %1,%0,%4\n\ - or %1,%1,%5\n" - PPC405_ERR77(0,%3) -" stwcx. %1,0,%3\n\ - bne- 1b" - : "=&r" (old), "=&r" (tmp), "=m" (*p) - : "r" (p), "r" (clr), "r" (set), "m" (*p) - : "cc" ); - return old; -} -#else -static inline unsigned long long pte_update(pte_t *p, unsigned long clr, - unsigned long set) -{ - unsigned long long old; - unsigned long tmp; - - __asm__ __volatile__("\ -1: lwarx %L0,0,%4\n\ - lwzx %0,0,%3\n\ - andc %1,%L0,%5\n\ - or %1,%1,%6\n" - PPC405_ERR77(0,%3) -" stwcx. %1,0,%4\n\ - bne- 1b" - : "=&r" (old), "=&r" (tmp), "=m" (*p) - : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) - : "cc" ); - return old; -} -#endif - -/* - * set_pte stores a linux PTE into the linux page table. - * On machines which use an MMU hash table we avoid changing the - * _PAGE_HASHPTE bit. - */ -static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, - pte_t *ptep, pte_t pte) -{ -#if _PAGE_HASHPTE != 0 - pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE); -#else - *ptep = pte; -#endif -} - -/* - * 2.6 calles this without flushing the TLB entry, this is wrong - * for our hash-based implementation, we fix that up here - */ -#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG -static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) -{ - unsigned long old; - old = pte_update(ptep, _PAGE_ACCESSED, 0); -#if _PAGE_HASHPTE != 0 - if (old & _PAGE_HASHPTE) { - unsigned long ptephys = __pa(ptep) & PAGE_MASK; - flush_hash_pages(context, addr, ptephys, 1); - } -#endif - return (old & _PAGE_ACCESSED) != 0; -} -#define ptep_test_and_clear_young(__vma, __addr, __ptep) \ - __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep) - -#define __HAVE_ARCH_PTEP_GET_AND_CLEAR -static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, - pte_t *ptep) -{ - return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); -} - -#define __HAVE_ARCH_PTEP_SET_WRPROTECT -static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, - pte_t *ptep) -{ - pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); -} - -#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS -static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) -{ - unsigned long bits = pte_val(entry) & - (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW); - pte_update(ptep, 0, bits); -} - -#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ -({ \ - int __changed = !pte_same(*(__ptep), __entry); \ - if (__changed) { \ - __ptep_set_access_flags(__ptep, __entry, __dirty); \ - flush_tlb_page_nohash(__vma, __address); \ - } \ - __changed; \ -}) - -/* - * Macro to mark a page protection value as "uncacheable". - */ -#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) - -struct file; -extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, - unsigned long size, pgprot_t vma_prot); -#define __HAVE_PHYS_MEM_ACCESS_PROT - -#define __HAVE_ARCH_PTE_SAME -#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) - -/* - * Note that on Book E processors, the pmd contains the kernel virtual - * (lowmem) address of the pte page. The physical address is less useful - * because everything runs with translation enabled (even the TLB miss - * handler). On everything else the pmd contains the physical address - * of the pte page. -- paulus - */ -#ifndef CONFIG_BOOKE -#define pmd_page_vaddr(pmd) \ - ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) -#define pmd_page(pmd) \ - (mem_map + (pmd_val(pmd) >> PAGE_SHIFT)) -#else -#define pmd_page_vaddr(pmd) \ - ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) -#define pmd_page(pmd) \ - (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT)) -#endif - -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -/* to find an entry in a page-table-directory */ -#define pgd_index(address) ((address) >> PGDIR_SHIFT) -#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) - -/* Find an entry in the second-level page table.. */ -static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) -{ - return (pmd_t *) dir; -} - -/* Find an entry in the third-level page table.. */ -#define pte_index(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset_kernel(dir, addr) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr)) -#define pte_offset_map(dir, addr) \ - ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr)) -#define pte_offset_map_nested(dir, addr) \ - ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr)) - -#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) -#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) - -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; - -extern void paging_init(void); - -/* - * Encode and decode a swap entry. - * Note that the bits we use in a PTE for representing a swap entry - * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the - *_PAGE_HASHPTE bit (if used). -- paulus - */ -#define __swp_type(entry) ((entry).val & 0x1f) -#define __swp_offset(entry) ((entry).val >> 5) -#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) - -/* Encode and decode a nonlinear file mapping entry */ -#define PTE_FILE_MAX_BITS 29 -#define pte_to_pgoff(pte) (pte_val(pte) >> 3) -#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) - -/* Values for nocacheflag and cmode */ -/* These are not used by the APUS kernel_map, but prevents - compilation errors. */ -#define KERNELMAP_FULL_CACHING 0 -#define KERNELMAP_NOCACHE_SER 1 -#define KERNELMAP_NOCACHE_NONSER 2 -#define KERNELMAP_NO_COPYBACK 3 - -/* - * Map some physical address range into the kernel address space. - */ -extern unsigned long kernel_map(unsigned long paddr, unsigned long size, - int nocacheflag, unsigned long *memavailp ); - -/* - * Set cache mode of (kernel space) address range. - */ -extern void kernel_set_cachemode (unsigned long address, unsigned long size, - unsigned int cmode); - -/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ -#define kern_addr_valid(addr) (1) - -#ifdef CONFIG_PHYS_64BIT -extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, - unsigned long paddr, unsigned long size, pgprot_t prot); - -static inline int io_remap_pfn_range(struct vm_area_struct *vma, - unsigned long vaddr, - unsigned long pfn, - unsigned long size, - pgprot_t prot) -{ - phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); - return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot); -} -#else -#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ - remap_pfn_range(vma, vaddr, pfn, size, prot) -#endif - -/* - * No page table caches to initialise - */ -#define pgtable_cache_init() do { } while (0) - -extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep, - pmd_t **pmdp); - -#include <asm-generic/pgtable.h> - -#endif /* !__ASSEMBLY__ */ - -#endif /* _PPC_PGTABLE_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h deleted file mode 100644 index 6f6760b30dd8..000000000000 --- a/include/asm-ppc/pnp.h +++ /dev/null @@ -1,645 +0,0 @@ -#ifdef __KERNEL__ -/* 11/02/95 */ -/*----------------------------------------------------------------------------*/ -/* Plug and Play header definitions */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for PnP on PowerPC Reference Platform */ -/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ -/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ -/* This code has extensions to that specification, namely new short and */ -/* long tag types for platform dependent information */ - -/* Warning: LE notation used throughout this file */ - -/* For enum's: if given in hex then they are bit significant, i.e. */ -/* only one bit is on for each enum */ - -#ifndef _PNP_ -#define _PNP_ - -#ifndef __ASSEMBLY__ -#define MAX_MEM_REGISTERS 9 -#define MAX_IO_PORTS 20 -#define MAX_IRQS 7 -/*#define MAX_DMA_CHANNELS 7*/ - -/* Interrupt controllers */ - -#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ -#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ -#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ -#define PNPinterrupt3 "PNP0003" /* APIC */ -#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ - -/* Timers */ - -#define PNPtimer0 "PNP0100" /* AT Timer */ -#define PNPtimer1 "PNP0101" /* EISA Timer */ -#define PNPtimer2 "PNP0102" /* MCA Timer */ - -/* DMA controllers */ - -#define PNPdma0 "PNP0200" /* AT DMA Controller */ -#define PNPdma1 "PNP0201" /* EISA DMA Controller */ -#define PNPdma2 "PNP0202" /* MCA DMA Controller */ - -/* start of August 15, 1994 additions */ -/* CMOS */ -#define PNPCMOS "IBM0009" /* CMOS */ - -/* L2 Cache */ -#define PNPL2 "IBM0007" /* L2 Cache */ - -/* NVRAM */ -#define PNPNVRAM "IBM0008" /* NVRAM */ - -/* Power Management */ -#define PNPPM "IBM0005" /* Power Management */ -/* end of August 15, 1994 additions */ - -/* Keyboards */ - -#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ -#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ -#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ -#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ -#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ -#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ -#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ -#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ - -/* Parallel port controllers */ - -#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ -#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ -#define PNPepp "IBM001C" /* EPP Parallel Port */ - -/* Serial port controllers */ - -#define PNPserial0 "PNP0500" /* Standard PC Serial port */ -#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ - -/* Disk controllers */ - -#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ -#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ -#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ - -/* Diskette controllers */ - -#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ - -/* Display controllers */ - -#define PNPdisplay0 "PNP0900" /* VGA Compatible */ -#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ -#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ -#define PNPdisplay3 "PNP0903" /* Trident VGA */ -#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ -#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ -#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ -#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ -#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ -#define PNPdisplay9 "PNP0909" /* S3 */ -#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ -#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ -#define PNPdisplayC "PNP090C" /* XGA Compatible */ -#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ -#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ -#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ - -/* Peripheral busses */ - -#define PNPbuses0 "PNP0A00" /* ISA Bus */ -#define PNPbuses1 "PNP0A01" /* EISA Bus */ -#define PNPbuses2 "PNP0A02" /* MCA Bus */ -#define PNPbuses3 "PNP0A03" /* PCI Bus */ -#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ - -/* RTC, BIOS, planar devices */ - -#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ -#define PNPrtc0 "PNP0B00" /* AT RTC */ -#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ -#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ -#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ -#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ - -/* PCMCIA controller */ - -#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ - -/* Mice */ - -#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ -#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ -#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ -#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ -#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ -#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ -#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ -#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ -#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ -#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ -#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ -#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ - -/* Modems */ - -#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ - -/* Network controllers */ - -#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ -#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ -#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ -#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ -#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ -#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ -#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ -#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ - -/* SCSI controllers */ - -#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ -#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ -#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ -#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ -#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ -#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ -#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ - -/* Sound/Video, Multimedia */ - -#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ -#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ -#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ -#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ -#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ -#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ -#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ -#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ - -/* Operator Panel */ -#define PNPopctl "IBM000B" /* Operator's panel */ - -/* Service Processor */ -#define PNPsp "IBM0011" /* IBM Service Processor */ -#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ -#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ - -/* Memory Controller */ -#define PNPmemctl "IBM000A" /* Memory controller */ - -/* Graphics Assist */ -#define PNPg_assist "IBM0014" /* Graphics Assist */ - -/* Miscellaneous Device Controllers */ -#define PNPtablet "IBM0019" /* IBM Tablet Controller */ - -/* PNP Packet Handles */ - -#define S1_Packet 0x0A /* Version resource */ -#define S2_Packet 0x15 /* Logical DEVID (without flags) */ -#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ -#define S3_Packet 0x1C /* Compatible device ID */ -#define S4_Packet 0x22 /* IRQ resource (without flags) */ -#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ -#define S5_Packet 0x2A /* DMA resource */ -#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ -#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ -#define S7_Packet 0x38 /* Depend funct end */ -#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ -#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ -#define S14_Packet 0x71 /* Vendor defined */ -#define S15_Packet 0x78 /* End of resource (w/o checksum) */ -#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ -#define L1_Packet 0x81 /* Memory range */ -#define L1_Shadow 0x20 /* Memory is shadowable */ -#define L1_32bit_mem 0x18 /* 32-bit memory only */ -#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ -#define L1_Decode_Hi 0x04 /* decode supports high address */ -#define L1_Cache 0x02 /* read cacheable, write-through */ -#define L1_Writeable 0x01 /* Memory is writeable */ -#define L2_Packet 0x82 /* ANSI ID string */ -#define L3_Packet 0x83 /* Unicode ID string */ -#define L4_Packet 0x84 /* Vendor defined */ -#define L5_Packet 0x85 /* Large I/O */ -#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ -#define END_TAG 0x78 /* End of resource */ -#define DF_START_TAG 0x30 /* Dependent function start */ -#define DF_START_TAG_priority 0x31 /* Dependent function start */ -#define DF_END_TAG 0x38 /* Dependent function end */ -#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ - -/* Device Base Type Codes */ - -typedef enum _PnP_BASE_TYPE { - Reserved = 0, - MassStorageDevice = 1, - NetworkInterfaceController = 2, - DisplayController = 3, - MultimediaController = 4, - MemoryController = 5, - BridgeController = 6, - CommunicationsDevice = 7, - SystemPeripheral = 8, - InputDevice = 9, - ServiceProcessor = 0x0A, /* 11/2/95 */ - } PnP_BASE_TYPE; - -/* Device Sub Type Codes */ - -typedef enum _PnP_SUB_TYPE { - SCSIController = 0, - IDEController = 1, - FloppyController = 2, - IPIController = 3, - OtherMassStorageController = 0x80, - - EthernetController = 0, - TokenRingController = 1, - FDDIController = 2, - OtherNetworkController = 0x80, - - VGAController= 0, - SVGAController= 1, - XGAController= 2, - OtherDisplayController = 0x80, - - VideoController = 0, - AudioController = 1, - OtherMultimediaController = 0x80, - - RAM = 0, - FLASH = 1, - OtherMemoryDevice = 0x80, - - HostProcessorBridge = 0, - ISABridge = 1, - EISABridge = 2, - MicroChannelBridge = 3, - PCIBridge = 4, - PCMCIABridge = 5, - VMEBridge = 6, - OtherBridgeDevice = 0x80, - - RS232Device = 0, - ATCompatibleParallelPort = 1, - OtherCommunicationsDevice = 0x80, - - ProgrammableInterruptController = 0, - DMAController = 1, - SystemTimer = 2, - RealTimeClock = 3, - L2Cache = 4, - NVRAM = 5, - PowerManagement = 6, - CMOS = 7, - OperatorPanel = 8, - ServiceProcessorClass1 = 9, - ServiceProcessorClass2 = 0xA, - ServiceProcessorClass3 = 0xB, - GraphicAssist = 0xC, - SystemPlanar = 0xF, /* 10/5/95 */ - OtherSystemPeripheral = 0x80, - - KeyboardController = 0, - Digitizer = 1, - MouseController = 2, - TabletController = 3, /* 10/27/95 */ - OtherInputController = 0x80, - - GeneralMemoryController = 0, - } PnP_SUB_TYPE; - -/* Device Interface Type Codes */ - -typedef enum _PnP_INTERFACE { - General = 0, - GeneralSCSI = 0, - GeneralIDE = 0, - ATACompatible = 1, - - GeneralFloppy = 0, - Compatible765 = 1, - NS398_Floppy = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26E_Floppy = 3, /* Ports 26E and 26F */ - NS15C_Floppy = 4, /* Ports 15C and 15D */ - NS2E_Floppy = 5, /* Ports 2E and 2F */ - CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ - - GeneralIPI = 0, - - GeneralEther = 0, - GeneralToken = 0, - GeneralFDDI = 0, - - GeneralVGA = 0, - GeneralSVGA = 0, - GeneralXGA = 0, - - GeneralVideo = 0, - GeneralAudio = 0, - CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ - - GeneralRAM = 0, - GeneralFLASH = 0, - PCIMemoryController = 0, /* PCI Config Method */ - RS6KMemoryController = 1, /* RS6K Config Method */ - - GeneralHostBridge = 0, - GeneralISABridge = 0, - GeneralEISABridge = 0, - GeneralMCABridge = 0, - GeneralPCIBridge = 0, - PCIBridgeDirect = 0, - PCIBridgeIndirect = 1, - PCIBridgeRS6K = 2, - GeneralPCMCIABridge = 0, - GeneralVMEBridge = 0, - - GeneralRS232 = 0, - COMx = 1, - Compatible16450 = 2, - Compatible16550 = 3, - NS398SerPort = 4, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26ESerPort = 5, /* Ports 26E and 26F */ - NS15CSerPort = 6, /* Ports 15C and 15D */ - NS2ESerPort = 7, /* Ports 2E and 2F */ - - GeneralParPort = 0, - LPTx = 1, - NS398ParPort = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ - NS26EParPort = 3, /* Ports 26E and 26F */ - NS15CParPort = 4, /* Ports 15C and 15D */ - NS2EParPort = 5, /* Ports 2E and 2F */ - - GeneralPIC = 0, - ISA_PIC = 1, - EISA_PIC = 2, - MPIC = 3, - RS6K_PIC = 4, - - GeneralDMA = 0, - ISA_DMA = 1, - EISA_DMA = 2, - - GeneralTimer = 0, - ISA_Timer = 1, - EISA_Timer = 2, - GeneralRTC = 0, - ISA_RTC = 1, - - StoreThruOnly = 1, - StoreInEnabled = 2, - RS6KL2Cache = 3, - - IndirectNVRAM = 0, /* Indirectly addressed */ - DirectNVRAM = 1, /* Memory Mapped */ - IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ - - GeneralPowerManagement = 0, - EPOWPowerManagement = 1, - PowerControl = 2, // d1378 - - GeneralCMOS = 0, - - GeneralOPPanel = 0, - HarddiskLight = 1, - CDROMLight = 2, - PowerLight = 3, - KeyLock = 4, - ANDisplay = 5, /* AlphaNumeric Display */ - SystemStatusLED = 6, /* 3 digit 7 segment LED */ - CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ - - GeneralServiceProcessor = 0, - - TransferData = 1, - IGMC32 = 2, - IGMC64 = 3, - - GeneralSystemPlanar = 0, /* 10/5/95 */ - - } PnP_INTERFACE; - -/* PnP resources */ - -/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ - -typedef struct _SERIAL_ID { - unsigned char VendorID0; /* Bit(7)=0 */ - /* Bits(6:2)=1st character in */ - /* compressed ASCII */ - /* Bits(1:0)=2nd character in */ - /* compressed ASCII bits(4:3) */ - unsigned char VendorID1; /* Bits(7:5)=2nd character in */ - /* compressed ASCII bits(2:0) */ - /* Bits(4:0)=3rd character in */ - /* compressed ASCII */ - unsigned char VendorID2; /* Product number - vendor assigned */ - unsigned char VendorID3; /* Product number - vendor assigned */ - -/* Serial number is to provide uniqueness if more than one board of same */ -/* type is in system. Must be "FFFFFFFF" if feature not supported. */ - - unsigned char Serial0; /* Unique serial number bits (7:0) */ - unsigned char Serial1; /* Unique serial number bits (15:8) */ - unsigned char Serial2; /* Unique serial number bits (23:16) */ - unsigned char Serial3; /* Unique serial number bits (31:24) */ - unsigned char Checksum; - } SERIAL_ID; - -typedef enum _PnPItemName { - Unused = 0, - PnPVersion = 1, - LogicalDevice = 2, - CompatibleDevice = 3, - IRQFormat = 4, - DMAFormat = 5, - StartDepFunc = 6, - EndDepFunc = 7, - IOPort = 8, - FixedIOPort = 9, - Res1 = 10, - Res2 = 11, - Res3 = 12, - SmallVendorItem = 14, - EndTag = 15, - MemoryRange = 1, - ANSIIdentifier = 2, - UnicodeIdentifier = 3, - LargeVendorItem = 4, - MemoryRange32 = 5, - MemoryRangeFixed32 = 6, - } PnPItemName; - -/* Define a bunch of access functions for the bits in the tag field */ - -/* Tag type - 0 = small; 1 = large */ -#define tag_type(t) (((t) & 0x80)>>7) -#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) - -/* Small item name is 4 bits - one of PnPItemName enum above */ -#define tag_small_item_name(t) (((t) & 0x78)>>3) -#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) - -/* Small item count is 3 bits - count of further bytes in packet */ -#define tag_small_count(t) ((t) & 0x07) -#define set_tag_count(t,v) (t = (t & 0x78) | (v)) - -/* Large item name is 7 bits - one of PnPItemName enum above */ -#define tag_large_item_name(t) ((t) & 0x7f) -#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) - -/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ - -typedef union _PnP_TAG_PACKET { - struct _S1_Pack{ /* VERSION PACKET */ - unsigned char Tag; /* small tag = 0x0a */ - unsigned char Version[2]; /* PnP version, Vendor version */ - } S1_Pack; - - struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x15 or 0x16 */ - unsigned char DevId[4]; /* Logical device id */ - unsigned char Flags[2]; /* bit(0) boot device; */ - /* bit(7:1) cmd in range x31-x37 */ - /* bit(7:0) cmd in range x28-x3f (opt)*/ - } S2_Pack; - - struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ - unsigned char Tag; /* small tag = 0x1c */ - unsigned char CompatId[4]; /* Compatible device id */ - } S3_Pack; - - struct _S4_Pack{ /* IRQ PACKET */ - unsigned char Tag; /* small tag = 0x22 or 0x23 */ - unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ - /* bit(0) is IRQ8 ... */ - unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ - /* bit(0) - high true edge sensitive */ - /* bit(1) - low true edge sensitive */ - /* bit(2) - high true level sensitive*/ - /* bit(3) - low true level sensitive */ - /* bit(7:4) - must be 0 */ - } S4_Pack; - - struct _S5_Pack{ /* DMA PACKET */ - unsigned char Tag; /* small tag = 0x2a */ - unsigned char DMAMask; /* bit(0) is channel 0 ... */ - unsigned char DMAInfo; - } S5_Pack; - - struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x30 or 0x31 */ - unsigned char Priority; /* Optional; if missing then x01; else*/ - /* x00 = best possible */ - /* x01 = acceptible */ - /* x02 = sub-optimal but functional */ - } S6_Pack; - - struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ - unsigned char Tag; /* small tag = 0x38 */ - } S7_Pack; - - struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ - unsigned char Tag; /* small tag x47 */ - unsigned char IOInfo; /* x0 = decode only bits(9:0); */ -#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ - unsigned char RangeMin[2]; /* Min base address */ - unsigned char RangeMax[2]; /* Max base address */ - unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S8_Pack; - - struct _S9_Pack{ /* FIXED I/O PORT PACKET */ - unsigned char Tag; /* small tag = 0x4b */ - unsigned char Range[2]; /* base address 10 bits */ - unsigned char IONum; /* number of contiguous I/O ports */ - } S9_Pack; - - struct _S14_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* small tag = 0x7m m = 1-7 */ - union _S14_Data{ - unsigned char Data[7]; /* Vendor defined */ - struct _S14_PPCPack{ /* Pr*p s14 pack */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[6]; /* Vendor defined */ - } S14_PPCPack; - } S14_Data; - } S14_Pack; - - struct _S15_Pack{ /* END PACKET */ - unsigned char Tag; /* small tag = 0x78 or 0x79 */ - unsigned char Check; /* optional - checksum */ - } S15_Pack; - - struct _L1_Pack{ /* MEMORY RANGE PACKET */ - unsigned char Tag; /* large tag = 0x81 */ - unsigned char Count0; /* x09 */ - unsigned char Count1; /* x00 */ - unsigned char Data[9]; /* a variable array of bytes, */ - /* count in tag */ - } L1_Pack; - - struct _L2_Pack{ /* ANSI ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x82 */ - unsigned char Count0; /* Length of string */ - unsigned char Count1; - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L2_Pack; - - struct _L3_Pack{ /* UNICODE ID STRING PACKET */ - unsigned char Tag; /* large tag = 0x83 */ - unsigned char Count0; /* Length + 2 of string */ - unsigned char Count1; - unsigned char Country0; /* TBD */ - unsigned char Country1; /* TBD */ - unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ - } L3_Pack; - - struct _L4_Pack{ /* VENDOR DEFINED PACKET */ - unsigned char Tag; /* large tag = 0x84 */ - unsigned char Count0; - unsigned char Count1; - union _L4_Data{ - unsigned char Data[1]; /* a variable array of bytes, */ - /* count in tag */ - struct _L4_PPCPack{ /* Pr*p L4 packet */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[1]; /* a variable array of bytes, */ - /* count in tag */ - } L4_PPCPack; - } L4_Data; - } L4_Pack; - - struct _L5_Pack{ - unsigned char Tag; /* large tag = 0x85 */ - unsigned char Count0; /* Count = 17 */ - unsigned char Count1; - unsigned char Data[17]; - } L5_Pack; - - struct _L6_Pack{ - unsigned char Tag; /* large tag = 0x86 */ - unsigned char Count0; /* Count = 9 */ - unsigned char Count1; - unsigned char Data[9]; - } L6_Pack; - - } PnP_TAG_PACKET; - -#endif /* __ASSEMBLY__ */ -#endif /* ndef _PNP_ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h deleted file mode 100644 index 935d1e05366b..000000000000 --- a/include/asm-ppc/ppc4xx_dma.h +++ /dev/null @@ -1,579 +0,0 @@ -/* - * include/asm-ppc/ppc4xx_dma.h - * - * IBM PPC4xx DMA engine library - * - * Copyright 2000-2004 MontaVista Software Inc. - * - * Cleaned up a bit more, Matt Porter <mporter@kernel.crashing.org> - * - * Original code by Armin Kuster <akuster@mvista.com> - * and Pete Popov <ppopov@mvista.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifdef __KERNEL__ -#ifndef __ASMPPC_PPC4xx_DMA_H -#define __ASMPPC_PPC4xx_DMA_H - -#include <linux/types.h> -#include <asm/mmu.h> -#include <asm/ibm4xx.h> - -#undef DEBUG_4xxDMA - -#define MAX_PPC4xx_DMA_CHANNELS 4 - -/* - * Function return status codes - * These values are used to indicate whether or not the function - * call was successful, or a bad/invalid parameter was passed. - */ -#define DMA_STATUS_GOOD 0 -#define DMA_STATUS_BAD_CHANNEL 1 -#define DMA_STATUS_BAD_HANDLE 2 -#define DMA_STATUS_BAD_MODE 3 -#define DMA_STATUS_NULL_POINTER 4 -#define DMA_STATUS_OUT_OF_MEMORY 5 -#define DMA_STATUS_SGL_LIST_EMPTY 6 -#define DMA_STATUS_GENERAL_ERROR 7 -#define DMA_STATUS_CHANNEL_NOTFREE 8 - -#define DMA_CHANNEL_BUSY 0x80000000 - -/* - * These indicate status as returned from the DMA Status Register. - */ -#define DMA_STATUS_NO_ERROR 0 -#define DMA_STATUS_CS 1 /* Count Status */ -#define DMA_STATUS_TS 2 /* Transfer Status */ -#define DMA_STATUS_DMA_ERROR 3 /* DMA Error Occurred */ -#define DMA_STATUS_DMA_BUSY 4 /* The channel is busy */ - - -/* - * DMA Channel Control Registers - */ - -#ifdef CONFIG_44x -#define PPC4xx_DMA_64BIT -#define DMA_CR_OFFSET 1 -#else -#define DMA_CR_OFFSET 0 -#endif - -#define DMA_CE_ENABLE (1<<31) /* DMA Channel Enable */ -#define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31) -#define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31) - -#define DMA_CIE_ENABLE (1<<30) /* DMA Channel Interrupt Enable */ -#define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30) -#define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30) - -#define DMA_TD (1<<29) -#define SET_DMA_TD(x) (((x)&0x1)<<29) -#define GET_DMA_TD(x) (((x)&DMA_TD)>>29) - -#define DMA_PL (1<<28) /* Peripheral Location */ -#define SET_DMA_PL(x) (((x)&0x1)<<28) -#define GET_DMA_PL(x) (((x)&DMA_PL)>>28) - -#define EXTERNAL_PERIPHERAL 0 -#define INTERNAL_PERIPHERAL 1 - -#define SET_DMA_PW(x) (((x)&0x3)<<(26-DMA_CR_OFFSET)) /* Peripheral Width */ -#define DMA_PW_MASK SET_DMA_PW(3) -#define PW_8 0 -#define PW_16 1 -#define PW_32 2 -#define PW_64 3 -/* FIXME: Add PW_128 support for 440GP DMA block */ -#define GET_DMA_PW(x) (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET)) - -#define DMA_DAI (1<<(25-DMA_CR_OFFSET)) /* Destination Address Increment */ -#define SET_DMA_DAI(x) (((x)&0x1)<<(25-DMA_CR_OFFSET)) - -#define DMA_SAI (1<<(24-DMA_CR_OFFSET)) /* Source Address Increment */ -#define SET_DMA_SAI(x) (((x)&0x1)<<(24-DMA_CR_OFFSET)) - -#define DMA_BEN (1<<(23-DMA_CR_OFFSET)) /* Buffer Enable */ -#define SET_DMA_BEN(x) (((x)&0x1)<<(23-DMA_CR_OFFSET)) - -#define SET_DMA_TM(x) (((x)&0x3)<<(21-DMA_CR_OFFSET)) /* Transfer Mode */ -#define DMA_TM_MASK SET_DMA_TM(3) -#define TM_PERIPHERAL 0 /* Peripheral */ -#define TM_RESERVED 1 /* Reserved */ -#define TM_S_MM 2 /* Memory to Memory */ -#define TM_D_MM 3 /* Device Paced Memory to Memory */ -#define GET_DMA_TM(x) (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET)) - -#define SET_DMA_PSC(x) (((x)&0x3)<<(19-DMA_CR_OFFSET)) /* Peripheral Setup Cycles */ -#define DMA_PSC_MASK SET_DMA_PSC(3) -#define GET_DMA_PSC(x) (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET)) - -#define SET_DMA_PWC(x) (((x)&0x3F)<<(13-DMA_CR_OFFSET)) /* Peripheral Wait Cycles */ -#define DMA_PWC_MASK SET_DMA_PWC(0x3F) -#define GET_DMA_PWC(x) (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET)) - -#define SET_DMA_PHC(x) (((x)&0x7)<<(10-DMA_CR_OFFSET)) /* Peripheral Hold Cycles */ -#define DMA_PHC_MASK SET_DMA_PHC(0x7) -#define GET_DMA_PHC(x) (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET)) - -#define DMA_ETD_OUTPUT (1<<(9-DMA_CR_OFFSET)) /* EOT pin is a TC output */ -#define SET_DMA_ETD(x) (((x)&0x1)<<(9-DMA_CR_OFFSET)) - -#define DMA_TCE_ENABLE (1<<(8-DMA_CR_OFFSET)) -#define SET_DMA_TCE(x) (((x)&0x1)<<(8-DMA_CR_OFFSET)) - -#define DMA_DEC (1<<(2)) /* Address Decrement */ -#define SET_DMA_DEC(x) (((x)&0x1)<<2) -#define GET_DMA_DEC(x) (((x)&DMA_DEC)>>2) - - -/* - * Transfer Modes - * These modes are defined in a way that makes it possible to - * simply "or" in the value in the control register. - */ - -#define DMA_MODE_MM (SET_DMA_TM(TM_S_MM)) /* memory to memory */ - - /* Device-paced memory to memory, */ - /* device is at source address */ -#define DMA_MODE_MM_DEVATSRC (DMA_TD | SET_DMA_TM(TM_D_MM)) - - /* Device-paced memory to memory, */ - /* device is at destination address */ -#define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM)) - -/* 405gp/440gp */ -#define SET_DMA_PREFETCH(x) (((x)&0x3)<<(4-DMA_CR_OFFSET)) /* Memory Read Prefetch */ -#define DMA_PREFETCH_MASK SET_DMA_PREFETCH(3) -#define PREFETCH_1 0 /* Prefetch 1 Double Word */ -#define PREFETCH_2 1 -#define PREFETCH_4 2 -#define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET)) - -#define DMA_PCE (1<<(3-DMA_CR_OFFSET)) /* Parity Check Enable */ -#define SET_DMA_PCE(x) (((x)&0x1)<<(3-DMA_CR_OFFSET)) -#define GET_DMA_PCE(x) (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET)) - -/* stb3x */ - -#define DMA_ECE_ENABLE (1<<5) -#define SET_DMA_ECE(x) (((x)&0x1)<<5) -#define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5) - -#define DMA_TCD_DISABLE (1<<4) -#define SET_DMA_TCD(x) (((x)&0x1)<<4) -#define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4) - -typedef uint32_t sgl_handle_t; - -#ifdef CONFIG_PPC4xx_EDMA - -#define SGL_LIST_SIZE 4096 -#define DMA_PPC4xx_SIZE SGL_LIST_SIZE - -#define SET_DMA_PRIORITY(x) (((x)&0x3)<<(6-DMA_CR_OFFSET)) /* DMA Channel Priority */ -#define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3) -#define PRIORITY_LOW 0 -#define PRIORITY_MID_LOW 1 -#define PRIORITY_MID_HIGH 2 -#define PRIORITY_HIGH 3 -#define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET)) - -/* - * DMA Polarity Configuration Register - */ -#define DMAReq_ActiveLow(chan) (1<<(31-(chan*3))) -#define DMAAck_ActiveLow(chan) (1<<(30-(chan*3))) -#define EOT_ActiveLow(chan) (1<<(29-(chan*3))) /* End of Transfer */ - -/* - * DMA Sleep Mode Register - */ -#define SLEEP_MODE_ENABLE (1<<21) - -/* - * DMA Status Register - */ -#define DMA_CS0 (1<<31) /* Terminal Count has been reached */ -#define DMA_CS1 (1<<30) -#define DMA_CS2 (1<<29) -#define DMA_CS3 (1<<28) - -#define DMA_TS0 (1<<27) /* End of Transfer has been requested */ -#define DMA_TS1 (1<<26) -#define DMA_TS2 (1<<25) -#define DMA_TS3 (1<<24) - -#define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ -#define DMA_CH1_ERR (1<<22) -#define DMA_CH2_ERR (1<<21) -#define DMA_CH3_ERR (1<<20) - -#define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */ -#define DMA_IN_DMA_REQ1 (1<<18) -#define DMA_IN_DMA_REQ2 (1<<17) -#define DMA_IN_DMA_REQ3 (1<<16) - -#define DMA_EXT_DMA_REQ0 (1<<15) /* External DMA Request is pending */ -#define DMA_EXT_DMA_REQ1 (1<<14) -#define DMA_EXT_DMA_REQ2 (1<<13) -#define DMA_EXT_DMA_REQ3 (1<<12) - -#define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */ -#define DMA_CH1_BUSY (1<<10) -#define DMA_CH2_BUSY (1<<9) -#define DMA_CH3_BUSY (1<<8) - -#define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */ -#define DMA_SG1 (1<<6) -#define DMA_SG2 (1<<5) -#define DMA_SG3 (1<<4) - -/* DMA Channel Count Register */ -#define DMA_CTC_BTEN (1<<23) /* Burst Enable/Disable bit */ -#define DMA_CTC_BSIZ_MSK (3<<21) /* Mask of the Burst size bits */ -#define DMA_CTC_BSIZ_2 (0) -#define DMA_CTC_BSIZ_4 (1<<21) -#define DMA_CTC_BSIZ_8 (2<<21) -#define DMA_CTC_BSIZ_16 (3<<21) - -/* - * DMA SG Command Register - */ -#define SSG_ENABLE(chan) (1<<(31-chan)) /* Start Scatter Gather */ -#define SSG_MASK_ENABLE(chan) (1<<(15-chan)) /* Enable writing to SSG0 bit */ - -/* - * DMA Scatter/Gather Descriptor Bit fields - */ -#define SG_LINK (1<<31) /* Link */ -#define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */ -#define SG_ETI_ENABLE (1<<28) /* Enable End of Transfer Interrupt */ -#define SG_ERI_ENABLE (1<<27) /* Enable Error Interrupt */ -#define SG_COUNT_MASK 0xFFFF /* Count Field */ - -#define SET_DMA_CONTROL \ - (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ - SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */\ - SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ - SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ - SET_DMA_PL(p_init->pl) | /* peripheral location */ \ - SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ - SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ - SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ - SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ - SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ - SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ - SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ - SET_DMA_PREFETCH(p_init->pf) /* read prefetch */) - -#define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan)) - -#elif defined(CONFIG_STB03xxx) /* stb03xxx */ - -#define DMA_PPC4xx_SIZE 4096 - -/* - * DMA Status Register - */ - -#define SET_DMA_PRIORITY(x) (((x)&0x00800001)) /* DMA Channel Priority */ -#define DMA_PRIORITY_MASK 0x00800001 -#define PRIORITY_LOW 0x00000000 -#define PRIORITY_MID_LOW 0x00000001 -#define PRIORITY_MID_HIGH 0x00800000 -#define PRIORITY_HIGH 0x00800001 -#define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001)) - -#define DMA_CS0 (1<<31) /* Terminal Count has been reached */ -#define DMA_CS1 (1<<30) -#define DMA_CS2 (1<<29) -#define DMA_CS3 (1<<28) - -#define DMA_TS0 (1<<27) /* End of Transfer has been requested */ -#define DMA_TS1 (1<<26) -#define DMA_TS2 (1<<25) -#define DMA_TS3 (1<<24) - -#define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ -#define DMA_CH1_ERR (1<<22) -#define DMA_CH2_ERR (1<<21) -#define DMA_CH3_ERR (1<<20) - -#define DMA_CT0 (1<<19) /* Chained transfere */ - -#define DMA_IN_DMA_REQ0 (1<<18) /* Internal DMA Request is pending */ -#define DMA_IN_DMA_REQ1 (1<<17) -#define DMA_IN_DMA_REQ2 (1<<16) -#define DMA_IN_DMA_REQ3 (1<<15) - -#define DMA_EXT_DMA_REQ0 (1<<14) /* External DMA Request is pending */ -#define DMA_EXT_DMA_REQ1 (1<<13) -#define DMA_EXT_DMA_REQ2 (1<<12) -#define DMA_EXT_DMA_REQ3 (1<<11) - -#define DMA_CH0_BUSY (1<<10) /* DMA Channel 0 Busy */ -#define DMA_CH1_BUSY (1<<9) -#define DMA_CH2_BUSY (1<<8) -#define DMA_CH3_BUSY (1<<7) - -#define DMA_CT1 (1<<6) /* Chained transfere */ -#define DMA_CT2 (1<<5) -#define DMA_CT3 (1<<4) - -#define DMA_CH_ENABLE (1<<7) -#define SET_DMA_CH(x) (((x)&0x1)<<7) -#define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7) - -/* STBx25xxx dma unique */ -/* enable device port on a dma channel - * example ext 0 on dma 1 - */ - -#define SSP0_RECV 15 -#define SSP0_XMIT 14 -#define EXT_DMA_0 12 -#define SC1_XMIT 11 -#define SC1_RECV 10 -#define EXT_DMA_2 9 -#define EXT_DMA_3 8 -#define SERIAL2_XMIT 7 -#define SERIAL2_RECV 6 -#define SC0_XMIT 5 -#define SC0_RECV 4 -#define SERIAL1_XMIT 3 -#define SERIAL1_RECV 2 -#define SERIAL0_XMIT 1 -#define SERIAL0_RECV 0 - -#define DMA_CHAN_0 1 -#define DMA_CHAN_1 2 -#define DMA_CHAN_2 3 -#define DMA_CHAN_3 4 - -/* end STBx25xx */ - -/* - * Bit 30 must be one for Redwoods, otherwise transfers may receive errors. - */ -#define DMA_CR_MB0 0x2 - -#define SET_DMA_CONTROL \ - (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ - SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ - SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ - SET_DMA_PL(p_init->pl) | /* peripheral location */ \ - SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ - SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ - SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ - SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ - SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ - SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ - SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ - SET_DMA_TCD(p_init->tcd_disable) | /* TC chain mode disable */ \ - SET_DMA_ECE(p_init->ece_enable) | /* ECE chanin mode enable */ \ - SET_DMA_CH(p_init->ch_enable) | /* Chain enable */ \ - DMA_CR_MB0 /* must be one */) - -#define GET_DMA_POLARITY(chan) chan - -#endif - -typedef struct { - unsigned short in_use; /* set when channel is being used, clr when - * available. - */ - /* - * Valid polarity settings: - * DMAReq_ActiveLow(n) - * DMAAck_ActiveLow(n) - * EOT_ActiveLow(n) - * - * n is 0 to max dma chans - */ - unsigned int polarity; - - char buffer_enable; /* Boolean: buffer enable */ - char tce_enable; /* Boolean: terminal count enable */ - char etd_output; /* Boolean: eot pin is a tc output */ - char pce; /* Boolean: parity check enable */ - - /* - * Peripheral location: - * INTERNAL_PERIPHERAL (UART0 on the 405GP) - * EXTERNAL_PERIPHERAL - */ - char pl; /* internal/external peripheral */ - - /* - * Valid pwidth settings: - * PW_8 - * PW_16 - * PW_32 - * PW_64 - */ - unsigned int pwidth; - - char dai; /* Boolean: dst address increment */ - char sai; /* Boolean: src address increment */ - - /* - * Valid psc settings: 0-3 - */ - unsigned int psc; /* Peripheral Setup Cycles */ - - /* - * Valid pwc settings: - * 0-63 - */ - unsigned int pwc; /* Peripheral Wait Cycles */ - - /* - * Valid phc settings: - * 0-7 - */ - unsigned int phc; /* Peripheral Hold Cycles */ - - /* - * Valid cp (channel priority) settings: - * PRIORITY_LOW - * PRIORITY_MID_LOW - * PRIORITY_MID_HIGH - * PRIORITY_HIGH - */ - unsigned int cp; /* channel priority */ - - /* - * Valid pf (memory read prefetch) settings: - * - * PREFETCH_1 - * PREFETCH_2 - * PREFETCH_4 - */ - unsigned int pf; /* memory read prefetch */ - - /* - * Boolean: channel interrupt enable - * NOTE: for sgl transfers, only the last descriptor will be setup to - * interrupt. - */ - char int_enable; - - char shift; /* easy access to byte_count shift, based on */ - /* the width of the channel */ - - uint32_t control; /* channel control word */ - - /* These variabled are used ONLY in single dma transfers */ - unsigned int mode; /* transfer mode */ - phys_addr_t addr; - char ce; /* channel enable */ -#ifdef CONFIG_STB03xxx - char ch_enable; - char tcd_disable; - char ece_enable; - char td; /* transfer direction */ -#endif - - char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */ -} ppc_dma_ch_t; - -/* - * PPC44x DMA implementations have a slightly different - * descriptor layout. Probably moved about due to the - * change to 64-bit addresses and link pointer. I don't - * know why they didn't just leave control_count after - * the dst_addr. - */ -#ifdef PPC4xx_DMA_64BIT -typedef struct { - uint32_t control; - uint32_t control_count; - phys_addr_t src_addr; - phys_addr_t dst_addr; - phys_addr_t next; -} ppc_sgl_t; -#else -typedef struct { - uint32_t control; - phys_addr_t src_addr; - phys_addr_t dst_addr; - uint32_t control_count; - uint32_t next; -} ppc_sgl_t; -#endif - -typedef struct { - unsigned int dmanr; - uint32_t control; /* channel ctrl word; loaded from each descrptr */ - uint32_t sgl_control; /* LK, TCI, ETI, and ERI bits in sgl descriptor */ - dma_addr_t dma_addr; /* dma (physical) address of this list */ - ppc_sgl_t *phead; - dma_addr_t phead_dma; - ppc_sgl_t *ptail; - dma_addr_t ptail_dma; -} sgl_list_info_t; - -typedef struct { - phys_addr_t *src_addr; - phys_addr_t *dst_addr; - phys_addr_t dma_src_addr; - phys_addr_t dma_dst_addr; -} pci_alloc_desc_t; - -extern ppc_dma_ch_t dma_channels[]; - -/* - * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c - */ -extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *); -extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *); -extern int ppc4xx_set_channel_priority(unsigned int, unsigned int); -extern unsigned int ppc4xx_get_peripheral_width(unsigned int); -extern void ppc4xx_set_sg_addr(int, phys_addr_t); -extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int); -extern void ppc4xx_enable_dma_sgl(sgl_handle_t); -extern void ppc4xx_disable_dma_sgl(sgl_handle_t); -extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *); -extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *); -extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int); -extern void ppc4xx_free_dma_handle(sgl_handle_t); -extern int ppc4xx_get_dma_status(void); -extern int ppc4xx_enable_burst(unsigned int); -extern int ppc4xx_disable_burst(unsigned int); -extern int ppc4xx_set_burst_size(unsigned int, unsigned int); -extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr); -extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr); -extern void ppc4xx_enable_dma(unsigned int dmanr); -extern void ppc4xx_disable_dma(unsigned int dmanr); -extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count); -extern int ppc4xx_get_dma_residue(unsigned int dmanr); -extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr, - phys_addr_t dst_dma_addr); -extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr); -extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr); -extern int ppc4xx_clr_dma_status(unsigned int dmanr); -extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); -extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); -extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode); - -/* These are in kernel/dma.c: */ - -/* reserve a DMA channel */ -extern int request_dma(unsigned int dmanr, const char *device_id); -/* release it again */ -extern void free_dma(unsigned int dmanr); -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h deleted file mode 100644 index e44261206f8b..000000000000 --- a/include/asm-ppc/ppc4xx_pic.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * include/asm-ppc/ppc4xx_pic.h - * - * Interrupt controller driver for PowerPC 4xx-based processors. - * - * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> - * - * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> - * Copyright (c) 2004 Zultys Technologies - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PPC4XX_PIC_H__ -#define __PPC4XX_PIC_H__ - -#include <linux/types.h> -#include <linux/irq.h> - -/* "Fixed" UIC settings (they are chip, not board specific), - * e.g. polarity/triggerring for internal interrupt sources. - * - * Platform port should provide NR_UICS-sized array named ppc4xx_core_uic_cfg - * with these "fixed" settings: .polarity contains exact value which will - * be written (masked with "ext_irq_mask") into UICx_PR register, - * .triggering - to UICx_TR. - * - * Settings for external IRQs can be specified separately by the - * board support code. In this case properly sized array of unsigned - * char named ppc4xx_uic_ext_irq_cfg should be filled with correct - * values using IRQ_SENSE_XXXXX and IRQ_POLARITY_XXXXXXX defines. - * - * If these arrays aren't provided, UIC initialization code keeps firmware - * configuration. Also, ppc4xx_uic_ext_irq_cfg implies ppc4xx_core_uic_cfg - * is defined. - * - * Both ppc4xx_core_uic_cfg and ppc4xx_uic_ext_irq_cfg are declared as - * "weak" symbols in ppc4xx_pic.c - * - */ -struct ppc4xx_uic_settings { - u32 polarity; - u32 triggering; - u32 ext_irq_mask; -}; - -extern void ppc4xx_pic_init(void); - -#endif /* __PPC4XX_PIC_H__ */ diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h deleted file mode 100644 index d2fee41d600b..000000000000 --- a/include/asm-ppc/ppc_sys.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * include/asm-ppc/ppc_sys.h - * - * PPC system definitions and library functions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_PPC_SYS_H -#define __ASM_PPC_SYS_H - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/types.h> - -#if defined(CONFIG_8260) -#include <asm/mpc8260.h> -#elif defined(CONFIG_8xx) -#include <asm/mpc8xx.h> -#elif defined(CONFIG_PPC_MPC52xx) -#include <asm/mpc52xx.h> -#elif defined(CONFIG_MPC10X_BRIDGE) -#include <asm/mpc10x.h> -#else -#error "need definition of ppc_sys_devices" -#endif - -#define PPC_SYS_IORESOURCE_FIXUPPED 0x00000001 - -struct ppc_sys_spec { - /* PPC sys is matched via (ID & mask) == value, id could be - * PVR, SVR, IMMR, * etc. */ - u32 mask; - u32 value; - u32 num_devices; - char *ppc_sys_name; - u8 config[NUM_PPC_SYS_DEVS]; - enum ppc_sys_devices *device_list; -}; - -struct platform_notify_dev_map { - const char *bus_id; - void (*rtn)(struct platform_device * pdev, int idx); -}; - -enum platform_device_func { - PPC_SYS_FUNC_DUMMY = 0, - PPC_SYS_FUNC_ETH = 1, - PPC_SYS_FUNC_UART = 2, - PPC_SYS_FUNC_HLDC = 3, - PPC_SYS_FUNC_USB = 4, - PPC_SYS_FUNC_IRDA = 5, -}; - -#define PPC_SYS_CONFIG_DISABLED 1 - -/* describes all specific chips and which devices they have on them */ -extern struct ppc_sys_spec ppc_sys_specs[]; -extern struct ppc_sys_spec *cur_ppc_sys_spec; - -/* determine which specific SOC we are */ -extern void identify_ppc_sys_by_id(u32 id) __init; -extern void identify_ppc_sys_by_name(char *name) __init; -extern void identify_ppc_sys_by_name_and_id(char *name, u32 id) __init; - -/* describes all devices that may exist in a given family of processors */ -extern struct platform_device ppc_sys_platform_devices[]; - -/* allow any platform_device fixup to occur before device is registered */ -extern int (*ppc_sys_device_fixup) (struct platform_device * pdev); - -/* Update all memory resources by paddr, call before platform_device_register */ -extern void ppc_sys_fixup_mem_resource(struct platform_device *pdev, - phys_addr_t paddr) __init; - -/* Get platform_data pointer out of platform device, call before platform_device_register */ -extern void *ppc_sys_get_pdata(enum ppc_sys_devices dev) __init; - -/* remove a device from the system */ -extern void ppc_sys_device_remove(enum ppc_sys_devices dev); - -/* Function assignment stuff */ -void ppc_sys_device_initfunc(void); -void ppc_sys_device_setfunc(enum ppc_sys_devices dev, - enum platform_device_func func); -void ppc_sys_device_set_func_all(enum platform_device_func func); - -void platform_notify_map(const struct platform_notify_dev_map *map, - struct device *dev); - -/* Enable / disable stuff */ -void ppc_sys_device_disable(enum ppc_sys_devices dev); -void ppc_sys_device_enable(enum ppc_sys_devices dev); -void ppc_sys_device_enable_all(void); -void ppc_sys_device_disable_all(void); - -#endif /* __ASM_PPC_SYS_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h deleted file mode 100644 index 3819e17cd7b0..000000000000 --- a/include/asm-ppc/ppcboot.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_PPCBOOT_H__ -#define __ASM_PPCBOOT_H__ - -/* - * Board information passed to kernel from PPCBoot - * - * include/asm-ppc/ppcboot.h - */ - -#ifndef __ASSEMBLY__ -#include <linux/types.h> - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - unsigned long bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) - unsigned long bi_immr_base; /* base of IMMR register */ -#endif -#if defined(CONFIG_PPC_MPC52xx) - unsigned long bi_mbar_base; /* base of internal registers */ -#endif - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* Ethernet address */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#if defined(CONFIG_CPM2) - unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ - unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ - unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ - unsigned long bi_vco; /* VCO Out from PLL, in MHz */ -#endif -#if defined(CONFIG_PPC_MPC52xx) - unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ - unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ -#endif - unsigned long bi_baudrate; /* Console Baudrate */ -#if defined(CONFIG_4xx) - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */ - unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ - unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ -#endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) - /* second onboard ethernet port */ - unsigned char bi_enet1addr[6]; -#endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) - /* third onboard ethernet ports */ - unsigned char bi_enet2addr[6]; -#endif -#if defined(CONFIG_440GX) - /* fourth onboard ethernet ports */ - unsigned char bi_enet3addr[6]; -#endif -#if defined(CONFIG_4xx) - unsigned int bi_opbfreq; /* OB clock in Hz */ - int bi_iic_fast[2]; /* Use fast i2c mode */ -#endif -#if defined(CONFIG_440GX) - int bi_phynum[4]; /* phy mapping */ - int bi_phymode[4]; /* phy mode */ -#endif -} bd_t; - -#define bi_tbfreq bi_intfreq - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_PPCBOOT_H__ */ diff --git a/include/asm-ppc/prep_nvram.h b/include/asm-ppc/prep_nvram.h deleted file mode 100644 index 6dbc36a84df2..000000000000 --- a/include/asm-ppc/prep_nvram.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * PreP compliant NVRAM access - */ - -/* Corey Minyard (minyard@acm.org) - Stolen from PReP book. Per the - license I must say: - (C) Copyright (Corey Minyard), (1998). All rights reserved - */ - -/* Structure map for NVRAM on PowerPC Reference Platform */ -/* All fields are either character/byte strings which are valid either - endian or they are big-endian numbers. - - There are a number of Date and Time fields which are in RTC format, - big-endian. These are stored in UT (GMT). - - For enum's: if given in hex then they are bit significant, i.e. only - one bit is on for each enum. -*/ -#ifdef __KERNEL__ -#ifndef _PPC_PREP_NVRAM_H -#define _PPC_PREP_NVRAM_H - -#define MAX_PREP_NVRAM 0x8000 -#define PREP_NVRAM_AS0 0x74 -#define PREP_NVRAM_AS1 0x75 -#define PREP_NVRAM_DATA 0x77 - -#define NVSIZE 4096 /* size of NVRAM */ -#define OSAREASIZE 512 /* size of OSArea space */ -#define CONFSIZE 1024 /* guess at size of Configuration space */ - -typedef struct _SECURITY { - unsigned long BootErrCnt; /* Count of boot password errors */ - unsigned long ConfigErrCnt; /* Count of config password errors */ - unsigned long BootErrorDT[2]; /* Date&Time from RTC of last error in pw */ - unsigned long ConfigErrorDT[2]; /* Date&Time from RTC of last error in pw */ - unsigned long BootCorrectDT[2]; /* Date&Time from RTC of last correct pw */ - unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */ - unsigned long BootSetDT[2]; /* Date&Time from RTC of last set of pw */ - unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */ - unsigned char Serial[16]; /* Box serial number */ -} SECURITY; - -typedef enum _OS_ID { - Unknown = 0, - Firmware = 1, - AIX = 2, - NT = 3, - MKOS2 = 4, - MKAIX = 5, - Taligent = 6, - Solaris = 7, - MK = 12 -} OS_ID; - -typedef struct _ERROR_LOG { - unsigned char ErrorLogEntry[40]; /* To be architected */ -} ERROR_LOG; - -typedef enum _BOOT_STATUS { - BootStarted = 0x01, - BootFinished = 0x02, - RestartStarted = 0x04, - RestartFinished = 0x08, - PowerFailStarted = 0x10, - PowerFailFinished = 0x20, - ProcessorReady = 0x40, - ProcessorRunning = 0x80, - ProcessorStart = 0x0100 -} BOOT_STATUS; - -typedef struct _RESTART_BLOCK { - unsigned short Version; - unsigned short Revision; - unsigned long ResumeReserve1[2]; - volatile unsigned long BootStatus; - unsigned long CheckSum; /* Checksum of RESTART_BLOCK */ - void * RestartAddress; - void * SaveAreaAddr; - unsigned long SaveAreaLength; -} RESTART_BLOCK; - -typedef enum _OSAREA_USAGE { - Empty = 0, - Used = 1 -} OSAREA_USAGE; - -typedef enum _PM_MODE { - Suspend = 0x80, /* Part of state is in memory */ - Normal = 0x00 /* No power management in effect */ -} PMMODE; - -typedef struct _HEADER { - unsigned short Size; /* NVRAM size in K(1024) */ - unsigned char Version; /* Structure map different */ - unsigned char Revision; /* Structure map the same -may - be new values in old fields - in other words old code still works */ - unsigned short Crc1; /* check sum from beginning of nvram to OSArea */ - unsigned short Crc2; /* check sum of config */ - unsigned char LastOS; /* OS_ID */ - unsigned char Endian; /* B if big endian, L if little endian */ - unsigned char OSAreaUsage; /* OSAREA_USAGE */ - unsigned char PMMode; /* Shutdown mode */ - RESTART_BLOCK RestartBlock; - SECURITY Security; - ERROR_LOG ErrorLog[2]; - - /* Global Environment information */ - void * GEAddress; - unsigned long GELength; - - /* Date&Time from RTC of last change to Global Environment */ - unsigned long GELastWriteDT[2]; - - /* Configuration information */ - void * ConfigAddress; - unsigned long ConfigLength; - - /* Date&Time from RTC of last change to Configuration */ - unsigned long ConfigLastWriteDT[2]; - unsigned long ConfigCount; /* Count of entries in Configuration */ - - /* OS dependent temp area */ - void * OSAreaAddress; - unsigned long OSAreaLength; - - /* Date&Time from RTC of last change to OSAreaArea */ - unsigned long OSAreaLastWriteDT[2]; -} HEADER; - -/* Here is the whole map of the NVRAM */ -typedef struct _NVRAM_MAP { - HEADER Header; - unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)]; - unsigned char OSArea[OSAREASIZE]; - unsigned char ConfigArea[CONFSIZE]; -} NVRAM_MAP; - -/* Routines to manipulate the NVRAM */ -void init_prep_nvram(void); -char *prep_nvram_get_var(const char *name); -char *prep_nvram_first_var(void); -char *prep_nvram_next_var(char *name); - -/* Routines to read and write directly to the NVRAM */ -unsigned char prep_nvram_read_val(int addr); -void prep_nvram_write_val(int addr, - unsigned char val); - -#endif /* _PPC_PREP_NVRAM_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h deleted file mode 100644 index 71f4c996fe75..000000000000 --- a/include/asm-ppc/prom.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Definitions for talking to the Open Firmware PROM on - * Power Macintosh computers. - * - * Copyright (C) 1996 Paul Mackerras. - */ -#ifdef __KERNEL__ -#ifndef _PPC_PROM_H -#define _PPC_PROM_H - -/* This is used in arch/ppc/mm/mem_pieces.h */ -struct reg_property { - unsigned int address; - unsigned int size; -}; - -/* - * These macros assist in performing the address calculations that we - * need to do to access data when the kernel is running at an address - * that is different from the address that the kernel is linked at. - * The reloc_offset() function returns the difference between these - * two addresses and the macros simplify the process of adding or - * subtracting this offset to/from pointer values. - */ -extern unsigned long reloc_offset(void); -extern unsigned long add_reloc_offset(unsigned long); -extern unsigned long sub_reloc_offset(unsigned long); - -#define PTRRELOC(x) ((typeof(x))add_reloc_offset((unsigned long)(x))) -#define PTRUNRELOC(x) ((typeof(x))sub_reloc_offset((unsigned long)(x))) - -/* - * Fallback definitions since we don't support OF in arch/ppc any more. - */ -#define machine_is_compatible(x) 0 -#define of_find_compatible_node(f, t, c) NULL -#define of_get_property(p, n, l) NULL - -#endif /* _PPC_PROM_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/raven.h b/include/asm-ppc/raven.h deleted file mode 100644 index 66f52cc0a03c..000000000000 --- a/include/asm-ppc/raven.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * include/asm-ppc/raven.h -- Raven MPIC chip. - * - * Copyright (C) 1998 Johnnie Peters - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifdef __KERNEL__ -#ifndef _ASMPPC_RAVEN_H -#define _ASMPPC_RAVEN_H - -#define MVME2600_INT_SIO 0 -#define MVME2600_INT_FALCN_ECC_ERR 1 -#define MVME2600_INT_PCI_ETHERNET 2 -#define MVME2600_INT_PCI_SCSI 3 -#define MVME2600_INT_PCI_GRAPHICS 4 -#define MVME2600_INT_PCI_VME0 5 -#define MVME2600_INT_PCI_VME1 6 -#define MVME2600_INT_PCI_VME2 7 -#define MVME2600_INT_PCI_VME3 8 -#define MVME2600_INT_PCI_INTA 9 -#define MVME2600_INT_PCI_INTB 10 -#define MVME2600_INT_PCI_INTC 11 -#define MVME2600_INT_PCI_INTD 12 -#define MVME2600_INT_LM_SIG0 13 -#define MVME2600_INT_LM_SIG1 14 - -extern struct hw_interrupt_type raven_pic; - -extern int raven_init(void); -#endif /* _ASMPPC_RAVEN_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h deleted file mode 100644 index 91e96af88bd8..000000000000 --- a/include/asm-ppc/reg_booke.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Contains register definitions common to the Book E PowerPC - * specification. Notice that while the IBM-40x series of CPUs - * are not true Book E PowerPCs, they borrowed a number of features - * before Book E was finalized, and are included here as well. Unfortunatly, - * they sometimes used different locations than true Book E CPUs did. - */ -#ifdef __KERNEL__ -#ifndef __ASM_PPC_REG_BOOKE_H__ -#define __ASM_PPC_REG_BOOKE_H__ - -#ifndef __ASSEMBLY__ -/* Performance Monitor Registers */ -#define mfpmr(rn) ({unsigned int rval; \ - asm volatile("mfpmr %0," __stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) -#endif /* __ASSEMBLY__ */ - -/* Freescale Book E Performance Monitor APU Registers */ -#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ -#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ -#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ -#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ -#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ -#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ -#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ -#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ - -#define PMLCA_FC 0x80000000 /* Freeze Counter */ -#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ -#define PMLCA_FCU 0x20000000 /* Freeze in User */ -#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ -#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ -#define PMLCA_CE 0x04000000 /* Condition Enable */ - -#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */ -#define PMLCA_EVENT_SHIFT 16 - -#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ -#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ -#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ -#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ - -#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */ -#define PMLCB_THRESHMUL_SHIFT 8 - -#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ -#define PMLCB_THRESHOLD_SHIFT 0 - -#define PMRN_PMGC0 0x190 /* PM Global Control 0 */ - -#define PMGC0_FAC 0x80000000 /* Freeze all Counters */ -#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ -#define PMGC0_FCECE 0x20000000 /* Freeze countes on - Enabled Condition or - Event */ - -#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ -#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ -#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ -#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ -#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ -#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ -#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ -#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ -#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ -#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ -#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ -#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ -#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ - - -/* Machine State Register (MSR) Fields */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ -#define MSR_SPE (1<<25) /* Enable SPE */ -#define MSR_DWE (1<<10) /* Debug Wait Enable */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_IS MSR_IR /* Instruction Space */ -#define MSR_DS MSR_DR /* Data Space */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit */ - -/* Default MSR for kernel mode. */ -#if defined (CONFIG_40x) -#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) -#elif defined(CONFIG_BOOKE) -#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) -#endif - -/* Special Purpose Registers (SPRNs)*/ -#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ -#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ -#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ -#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ -#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ -#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ -#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ -#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ -#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ -#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ -#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ -#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ -#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ -#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ -#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ -#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ -#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ -#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ -#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ -#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ -#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ -#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ -#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ -#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ -#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ -#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ -#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ -#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ -#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ -#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ -#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ -#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ -#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ -#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ -#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ -#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ -#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ -#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ -#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ -#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ -#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ -#define SPRN_MCSR 0x23C /* Machine Check Status Register */ -#define SPRN_MCAR 0x23D /* Machine Check Address Register */ -#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ -#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ -#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ -#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ -#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ -#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ -#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ -#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ -#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ -#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */ -#define SPRN_PID1 0x279 /* Process ID Register 1 */ -#define SPRN_PID2 0x27A /* Process ID Register 2 */ -#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ -#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ -#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ -#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ -#define SPRN_MMUCR 0x3B2 /* MMU Control Register */ -#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ -#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define SPRN_SLER 0x3BB /* Little-endian real mode */ -#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ -#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ -#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ -#define SPRN_SVR 0x3FF /* System Version Register */ - -/* - * SPRs which have conflicting definitions on true Book E versus classic, - * or IBM 40x. - */ -#ifdef CONFIG_BOOKE -#define SPRN_PID 0x030 /* Process ID */ -#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ -#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ -#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ -#define SPRN_DEAR 0x03D /* Data Error Address Register */ -#define SPRN_ESR 0x03E /* Exception Syndrome Register */ -#define SPRN_PIR 0x11E /* Processor Identification Register */ -#define SPRN_DBSR 0x130 /* Debug Status Register */ -#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ -#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ -#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ -#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ -#define SPRN_DAC1 0x13C /* Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Data Address Compare 2 */ -#define SPRN_TSR 0x150 /* Timer Status Register */ -#define SPRN_TCR 0x154 /* Timer Control Register */ -#endif /* Book E */ -#ifdef CONFIG_40x -#define SPRN_PID 0x3B1 /* Process ID */ -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ -#define SPRN_TSR 0x3D8 /* Timer Status Register */ -#define SPRN_TCR 0x3DA /* Timer Control Register */ -#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ -#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ -#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ -#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ -#endif - -/* Bit definitions for CCR1. */ -#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ -#define CCR1_TCS 0x00000080 /* Timer Clock Select */ - -/* Bit definitions for the MCSR. */ -#ifdef CONFIG_4xx -#define MCSR_MCS 0x80000000 /* Machine Check Summary */ -#define MCSR_IB 0x40000000 /* Instruction PLB Error */ -#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ -#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ -#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ -#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ -#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ -#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ -#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ -#endif - -/* Bit definitions for the DBSR. */ -/* - * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. - */ -#ifdef CONFIG_BOOKE -#define DBSR_IC 0x08000000 /* Instruction Completion */ -#define DBSR_BT 0x04000000 /* Branch Taken */ -#define DBSR_TIE 0x01000000 /* Trap Instruction Event */ -#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ -#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ -#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ -#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ -#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ -#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ -#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ -#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ -#endif -#ifdef CONFIG_40x -#define DBSR_IC 0x80000000 /* Instruction Completion */ -#define DBSR_BT 0x40000000 /* Branch taken */ -#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ -#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ -#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ -#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ -#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ -#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ -#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ -#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ -#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ -#endif - -/* Bit definitions related to the ESR. */ -#define ESR_MCI 0x80000000 /* Machine Check - Instruction */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Privileged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_FP 0x01000000 /* Floating Point Operation */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define ESR_ST 0x00800000 /* Store Operation */ -#define ESR_DLK 0x00200000 /* Data Cache Locking */ -#define ESR_ILK 0x00100000 /* Instr. Cache Locking */ -#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ -#define ESR_BO 0x00020000 /* Byte Ordering */ - -/* Bit definitions related to the DBCR0. */ -#define DBCR0_EDM 0x80000000 /* External Debug Mode */ -#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ -#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ -#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ -#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ -#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ -#define DBCR0_RST_NONE 0x00000000 /* No Reset */ -#define DBCR0_IC 0x08000000 /* Instruction Completion */ -#define DBCR0_BT 0x04000000 /* Branch Taken */ -#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ -#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ -#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ -#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ -#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ -#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ -#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ -#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ -#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ -#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ -#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ - -/* Bit definitions related to the TCR. */ -#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ -#define TCR_WP_MASK TCR_WP(3) -#define WP_2_17 0 /* 2^17 clocks */ -#define WP_2_21 1 /* 2^21 clocks */ -#define WP_2_25 2 /* 2^25 clocks */ -#define WP_2_29 3 /* 2^29 clocks */ -#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ -#define TCR_WRC_MASK TCR_WRC(3) -#define WRC_NONE 0 /* No reset will occur */ -#define WRC_CORE 1 /* Core reset will occur */ -#define WRC_CHIP 2 /* Chip reset will occur */ -#define WRC_SYSTEM 3 /* System reset will occur */ -#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ -#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ -#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ -#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ -#define TCR_FP_MASK TCR_FP(3) -#define FP_2_9 0 /* 2^9 clocks */ -#define FP_2_13 1 /* 2^13 clocks */ -#define FP_2_17 2 /* 2^17 clocks */ -#define FP_2_21 3 /* 2^21 clocks */ -#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ -#define TCR_ARE 0x00400000 /* Auto Reload Enable */ - -/* Bit definitions for the TSR. */ -#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ -#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ -#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ -#define WRS_NONE 0 /* No WDT reset occurred */ -#define WRS_CORE 1 /* WDT forced core reset */ -#define WRS_CHIP 2 /* WDT forced chip reset */ -#define WRS_SYSTEM 3 /* WDT forced system reset */ -#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ -#define TSR_DIS TSR_PIS /* DEC Interrupt Status */ -#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ - -/* Bit definitions for the DCCR. */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ - -/* Bit definitions for DCWR. */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ - -/* Bit definitions for ICCR. */ -#define ICCR_NOCACHE 0 /* Noncacheable */ -#define ICCR_CACHE 1 /* Cacheable */ - -/* Bit definitions for L1CSR0. */ -#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ -#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ -#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ -#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ - -/* Bit definitions for L1CSR1. */ -#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ -#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ -#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ - -/* Bit definitions for SGR. */ -#define SGR_NORMAL 0 /* Speculative fetching allowed. */ -#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ - -/* Bit definitions for SPEFSCR. */ -#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ -#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ -#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ -#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ -#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ -#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ -#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ -#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ -#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ -#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ -#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ -#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ -#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ -#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ -#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ -#define SPEFSCR_OV 0x00004000 /* Integer overflow */ -#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ -#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ -#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ -#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ -#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ -#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ -#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ -#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ -#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ -#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ -#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ -#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ - -/* - * The IBM-403 is an even more odd special case, as it is much - * older than the IBM-405 series. We put these down here incase someone - * wishes to support these machines again. - */ -#ifdef CONFIG_403GCX -/* Special Purpose Registers (SPRNs)*/ -#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ -#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_TBHI 0x3DC /* Time Base High */ -#define SPRN_TBLO 0x3DD /* Time Base Low */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ -#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ -#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ -#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ - - -/* Bit definitions for the DBCR. */ -#define DBCR_EDM DBCR0_EDM -#define DBCR_IDM DBCR0_IDM -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ -#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ -#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ -#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ -#endif /* 403GCX */ -#endif /* __ASM_PPC_REG_BOOKE_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h deleted file mode 100644 index 934810d25667..000000000000 --- a/include/asm-ppc/residual.h +++ /dev/null @@ -1,350 +0,0 @@ -/* 7/18/95 */ -/*----------------------------------------------------------------------------*/ -/* Residual Data header definitions and prototypes */ -/*----------------------------------------------------------------------------*/ - -/* Structure map for RESIDUAL on PowerPC Reference Platform */ -/* residual.h - Residual data structure passed in r3. */ -/* Load point passed in r4 to boot image. */ -/* For enum's: if given in hex then they are bit significant, */ -/* i.e. only one bit is on for each enum */ -/* Reserved fields must be filled with zeros. */ - -#ifdef __KERNEL__ -#ifndef _RESIDUAL_ -#define _RESIDUAL_ - -#ifndef __ASSEMBLY__ - -#define MAX_CPUS 32 /* These should be set to the maximum */ -#define MAX_MEMS 64 /* number possible for this system. */ -#define MAX_DEVICES 256 /* Changing these will change the */ -#define AVE_PNP_SIZE 32 /* structure, hence the version of */ -#define MAX_MEM_SEGS 64 /* this header file. */ - -/*----------------------------------------------------------------------------*/ -/* Public structures... */ -/*----------------------------------------------------------------------------*/ - -#include <asm/pnp.h> - -typedef enum _L1CACHE_TYPE { - NoneCAC = 0, - SplitCAC = 1, - CombinedCAC = 2 - } L1CACHE_TYPE; - -typedef enum _TLB_TYPE { - NoneTLB = 0, - SplitTLB = 1, - CombinedTLB = 2 - } TLB_TYPE; - -typedef enum _FIRMWARE_SUPPORT { - Conventional = 0x01, - OpenFirmware = 0x02, - Diagnostics = 0x04, - LowDebug = 0x08, - Multiboot = 0x10, - LowClient = 0x20, - Hex41 = 0x40, - FAT = 0x80, - ISO9660 = 0x0100, - SCSI_InitiatorID_Override = 0x0200, - Tape_Boot = 0x0400, - FW_Boot_Path = 0x0800 - } FIRMWARE_SUPPORT; - -typedef enum _FIRMWARE_SUPPLIERS { - IBMFirmware = 0x00, - MotoFirmware = 0x01, /* 7/18/95 */ - FirmWorks = 0x02, /* 10/5/95 */ - Bull = 0x03, /* 04/03/96 */ - } FIRMWARE_SUPPLIERS; - -typedef enum _ENDIAN_SWITCH_METHODS { - UsePort92 = 0x01, - UsePCIConfigA8 = 0x02, - UseFF001030 = 0x03, - } ENDIAN_SWITCH_METHODS; - -typedef enum _SPREAD_IO_METHODS { - UsePort850 = 0x00, -/*UsePCIConfigA8 = 0x02,*/ - } SPREAD_IO_METHODS; - -typedef struct _VPD { - - /* Box dependent stuff */ - unsigned char PrintableModel[32]; /* Null terminated string. - Must be of the form: - vvv,<20h>,<model designation>,<0x0> - where vvv is the vendor ID - e.g. IBM PPS MODEL 6015<0x0> */ - unsigned char Serial[16]; /* 12/94: - Serial Number; must be of the form: - vvv<serial number> where vvv is the - vendor ID. - e.g. IBM60151234567<20h><20h> */ - unsigned char Reserved[48]; - unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ - unsigned long FirmwareSupports; /* See FirmwareSupport enum */ - unsigned long NvramSize; /* Size of nvram in bytes */ - unsigned long NumSIMMSlots; - unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ - unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ - unsigned long SmpIar; - unsigned long RAMErrLogOffset; /* Heap offset to error log */ - unsigned long Reserved5; - unsigned long Reserved6; - unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ - unsigned long ProcessorBusHz; /* Processor bus clock frequency */ - unsigned long Reserved7; - unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ - unsigned long WordWidth; /* Word width in bits */ - unsigned long PageSize; /* Page size in bytes */ - unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache - for which coherency is maintained; - normally <= CacheLineSize. */ - unsigned long GranuleSize; /* Unit of lock allocation to avoid */ - /* false sharing of locks. */ - - /* L1 Cache variables */ - unsigned long CacheSize; /* L1 Cache size in KB. This is the */ - /* total size of the L1, whether */ - /* combined or split */ - unsigned long CacheAttrib; /* L1CACHE_TYPE */ - unsigned long CacheAssoc; /* L1 Cache associativity. Use this - for combined cache. If split, put - zeros here. */ - unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use - for combined cache. If split, put - zeros here. */ - /* For split L1 Cache: (= combined if combined cache) */ - unsigned long I_CacheSize; - unsigned long I_CacheAssoc; - unsigned long I_CacheLineSize; - unsigned long D_CacheSize; - unsigned long D_CacheAssoc; - unsigned long D_CacheLineSize; - - /* Translation Lookaside Buffer variables */ - unsigned long TLBSize; /* Total number of TLBs on the system */ - unsigned long TLBAttrib; /* Combined I+D or split TLB */ - unsigned long TLBAssoc; /* TLB Associativity. Use this for - combined TLB. If split, put zeros - here. */ - /* For split TLB: (= combined if combined TLB) */ - unsigned long I_TLBSize; - unsigned long I_TLBAssoc; - unsigned long D_TLBSize; - unsigned long D_TLBAssoc; - - unsigned long ExtendedVPD; /* Offset to extended VPD area; - null if unused */ - } VPD; - -typedef enum _DEVICE_FLAGS { - Enabled = 0x4000, /* 1 - PCI device is enabled */ - Integrated = 0x2000, - Failed = 0x1000, /* 1 - device failed POST code tests */ - Static = 0x0800, /* 0 - dynamically configurable - 1 - static */ - Dock = 0x0400, /* 0 - not a docking station device - 1 - is a docking station device */ - Boot = 0x0200, /* 0 - device cannot be used for BOOT - 1 - can be a BOOT device */ - Configurable = 0x0100, /* 1 - device is configurable */ - Disableable = 0x80, /* 1 - device can be disabled */ - PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ - ReadOnly = 0x20, /* 1 - device is read only */ - Removable = 0x10, /* 1 - device is removable */ - ConsoleIn = 0x08, - ConsoleOut = 0x04, - Input = 0x02, - Output = 0x01 - } DEVICE_FLAGS; - -typedef enum _BUS_ID { - ISADEVICE = 0x01, - EISADEVICE = 0x02, - PCIDEVICE = 0x04, - PCMCIADEVICE = 0x08, - PNPISADEVICE = 0x10, - MCADEVICE = 0x20, - MXDEVICE = 0x40, /* Devices on mezzanine bus */ - PROCESSORDEVICE = 0x80, /* Devices on processor bus */ - VMEDEVICE = 0x100, - } BUS_ID; - -typedef struct _DEVICE_ID { - unsigned long BusId; /* See BUS_ID enum above */ - unsigned long DevId; /* Big Endian format */ - unsigned long SerialNum; /* For multiple usage of a single - DevId */ - unsigned long Flags; /* See DEVICE_FLAGS enum above */ - unsigned char BaseType; /* See pnp.h for bit definitions */ - unsigned char SubType; /* See pnp.h for bit definitions */ - unsigned char Interface; /* See pnp.h for bit definitions */ - unsigned char Spare; - } DEVICE_ID; - -typedef union _BUS_ACCESS { - struct _PnPAccess{ - unsigned char CSN; - unsigned char LogicalDevNumber; - unsigned short ReadDataPort; - } PnPAccess; - struct _ISAAccess{ - unsigned char SlotNumber; /* ISA Slot Number generally not - available; 0 if unknown */ - unsigned char LogicalDevNumber; - unsigned short ISAReserved; - } ISAAccess; - struct _MCAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short MCAReserved; - } MCAAccess; - struct _PCMCIAAccess{ - unsigned char SlotNumber; - unsigned char LogicalDevNumber; - unsigned short PCMCIAReserved; - } PCMCIAAccess; - struct _EISAAccess{ - unsigned char SlotNumber; - unsigned char FunctionNumber; - unsigned short EISAReserved; - } EISAAccess; - struct _PCIAccess{ - unsigned char BusNumber; - unsigned char DevFuncNumber; - unsigned short PCIReserved; - } PCIAccess; - struct _ProcBusAccess{ - unsigned char BusNumber; - unsigned char BUID; - unsigned short ProcBusReserved; - } ProcBusAccess; - } BUS_ACCESS; - -/* Per logical device information */ -typedef struct _PPC_DEVICE { - DEVICE_ID DeviceId; - BUS_ACCESS BusAccess; - - /* The following three are offsets into the DevicePnPHeap */ - /* All are in PnP compressed format */ - unsigned long AllocatedOffset; /* Allocated resource description */ - unsigned long PossibleOffset; /* Possible resource description */ - unsigned long CompatibleOffset; /* Compatible device identifiers */ - } PPC_DEVICE; - -typedef enum _CPU_STATE { - CPU_GOOD = 0, /* CPU is present, and active */ - CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ - CPU_OFF = 2, /* CPU is present, but inactive */ - CPU_FAILED = 3, /* CPU is present, but failed POST */ - CPU_NOT_PRESENT = 255 /* CPU not present */ - } CPU_STATE; - -typedef struct _PPC_CPU { - unsigned long CpuType; /* Result of mfspr from Processor - Version Register (PVR). - PVR(0-15) = Version (e.g. 601) - PVR(16-31 = EC Level */ - unsigned char CpuNumber; /* CPU Number for this processor */ - unsigned char CpuState; /* CPU State, see CPU_STATE enum */ - unsigned short Reserved; - } PPC_CPU; - -typedef struct _PPC_MEM { - unsigned long SIMMSize; /* 0 - absent or bad - 8M, 32M (in MB) */ - } PPC_MEM; - -typedef enum _MEM_USAGE { - Other = 0x8000, - ResumeBlock = 0x4000, /* for use by power management */ - SystemROM = 0x2000, /* Flash memory (populated) */ - UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ - IOMemory = 0x0800, - SystemIO = 0x0400, - SystemRegs = 0x0200, - PCIAddr = 0x0100, - PCIConfig = 0x80, - ISAAddr = 0x40, - Unpopulated = 0x20, /* Unpopulated part of System Memory */ - Free = 0x10, /* Free part of System Memory */ - BootImage = 0x08, /* BootImage part of System Memory */ - FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ - FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ - FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ - } MEM_USAGE; - -typedef struct _MEM_MAP { - unsigned long Usage; /* See MEM_USAGE above */ - unsigned long BasePage; /* Page number measured in 4KB pages */ - unsigned long PageCount; /* Page count measured in 4KB pages */ - } MEM_MAP; - -typedef struct _RESIDUAL { - unsigned long ResidualLength; /* Length of Residual */ - unsigned char Version; /* of this data structure */ - unsigned char Revision; /* of this data structure */ - unsigned short EC; /* of this data structure */ - /* VPD */ - VPD VitalProductData; - /* CPU */ - unsigned short MaxNumCpus; /* Max CPUs in this system */ - unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ - /* that there are unpopulated or */ - /* otherwise unusable cpu locations */ - PPC_CPU Cpus[MAX_CPUS]; - /* Memory */ - unsigned long TotalMemory; /* Total amount of memory installed */ - unsigned long GoodMemory; /* Total amount of good memory */ - unsigned long ActualNumMemSegs; - MEM_MAP Segs[MAX_MEM_SEGS]; - unsigned long ActualNumMemories; - PPC_MEM Memories[MAX_MEMS]; - /* Devices */ - unsigned long ActualNumDevices; - PPC_DEVICE Devices[MAX_DEVICES]; - unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; - } RESIDUAL; - - -/* - * Forward declaration - we can't include <linux/pci.h> because it - * breaks the boot loader - */ -struct pci_dev; - -extern RESIDUAL *res; -extern void print_residual_device_info(void); -extern PPC_DEVICE *residual_find_device(unsigned long BusMask, - unsigned char * DevID, int BaseType, - int SubType, int Interface, int n); -extern int residual_pcidev_irq(struct pci_dev *dev); -extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi); -extern unsigned int residual_isapic_addr(void); -extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, - int n); -extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); -extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, - unsigned packet_type, - int n); - -#ifdef CONFIG_PREP_RESIDUAL -#define have_residual_data (res && res->ResidualLength) -#else -#define have_residual_data 0 -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* ndef _RESIDUAL_ */ - -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/rtc.h b/include/asm-ppc/rtc.h deleted file mode 100644 index 6025b46d0a2a..000000000000 --- a/include/asm-ppc/rtc.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * include/asm-ppc/rtc.h - * - * Author: Tom Rini <trini@mvista.com> - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Based on: - * include/asm-m68k/rtc.h - * - * Copyright Richard Zidlicky - * implementation details for genrtc/q40rtc driver - * - * And the old drivers/macintosh/rtc.c which was heavily based on: - * Linux/SPARC Real Time Clock Driver - * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) - * - * With additional work by Paul Mackerras and Franz Sirl. - */ - -#ifndef __ASM_RTC_H__ -#define __ASM_RTC_H__ - -#ifdef __KERNEL__ - -#include <linux/rtc.h> - -#include <asm/machdep.h> -#include <asm/time.h> - -#define RTC_PIE 0x40 /* periodic interrupt enable */ -#define RTC_AIE 0x20 /* alarm interrupt enable */ -#define RTC_UIE 0x10 /* update-finished interrupt enable */ - -/* some dummy definitions */ -#define RTC_BATT_BAD 0x100 /* battery bad */ -#define RTC_SQWE 0x08 /* enable square-wave output */ -#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ -#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ -#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ - -static inline unsigned int get_rtc_time(struct rtc_time *time) -{ - if (ppc_md.get_rtc_time) { - unsigned long nowtime; - - nowtime = (ppc_md.get_rtc_time)(); - - to_tm(nowtime, time); - - time->tm_year -= 1900; - time->tm_mon -= 1; /* Make sure userland has a 0-based month */ - } - return RTC_24H; -} - -/* Set the current date and time in the real time clock. */ -static inline int set_rtc_time(struct rtc_time *time) -{ - if (ppc_md.get_rtc_time) { - unsigned long nowtime; - - nowtime = mktime(time->tm_year+1900, time->tm_mon+1, - time->tm_mday, time->tm_hour, time->tm_min, - time->tm_sec); - - (ppc_md.set_rtc_time)(nowtime); - - return 0; - } else - return -EINVAL; -} - -static inline unsigned int get_rtc_ss(void) -{ - struct rtc_time h; - - get_rtc_time(&h); - return h.tm_sec; -} - -static inline int get_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} -static inline int set_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} - -#endif /* __KERNEL__ */ -#endif /* __ASM_RTC_H__ */ diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h deleted file mode 100644 index d35ed10315b1..000000000000 --- a/include/asm-ppc/serial.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * include/asm-ppc/serial.h - */ - -#ifdef __KERNEL__ -#ifndef __ASM_SERIAL_H__ -#define __ASM_SERIAL_H__ - - -#if defined(CONFIG_EV64260) -#include <platforms/ev64260.h> -#elif defined(CONFIG_CHESTNUT) -#include <platforms/chestnut.h> -#elif defined(CONFIG_POWERPMC250) -#include <platforms/powerpmc250.h> -#elif defined(CONFIG_LOPEC) -#include <platforms/lopec.h> -#elif defined(CONFIG_MVME5100) -#include <platforms/mvme5100.h> -#elif defined(CONFIG_PAL4) -#include <platforms/pal4_serial.h> -#elif defined(CONFIG_PRPMC750) -#include <platforms/prpmc750.h> -#elif defined(CONFIG_PRPMC800) -#include <platforms/prpmc800.h> -#elif defined(CONFIG_SANDPOINT) -#include <platforms/sandpoint.h> -#elif defined(CONFIG_SPRUCE) -#include <platforms/spruce.h> -#elif defined(CONFIG_4xx) -#include <asm/ibm4xx.h> -#elif defined(CONFIG_RADSTONE_PPC7D) -#include <platforms/radstone_ppc7d.h> -#else - -/* - * XXX Assume it has PC-style ISA serial ports - true for PReP at least. - */ -#include <asm/pc_serial.h> - -#endif /* !CONFIG_GEMINI and others */ -#endif /* __ASM_SERIAL_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h deleted file mode 100644 index e75791ea33a6..000000000000 --- a/include/asm-ppc/smp.h +++ /dev/null @@ -1,75 +0,0 @@ -/* smp.h: PPC specific SMP stuff. - * - * Original was a copy of sparc smp.h. Now heavily modified - * for PPC. - * - * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com> - */ -#ifdef __KERNEL__ -#ifndef _PPC_SMP_H -#define _PPC_SMP_H - -#include <linux/kernel.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <linux/cpumask.h> -#include <linux/threads.h> - -#ifdef CONFIG_SMP - -#ifndef __ASSEMBLY__ - -struct cpuinfo_PPC { - unsigned long loops_per_jiffy; - unsigned long pvr; - unsigned long *pgd_cache; - unsigned long *pte_cache; - unsigned long pgtable_cache_sz; -}; - -extern struct cpuinfo_PPC cpu_data[]; -extern cpumask_t cpu_online_map; -extern cpumask_t cpu_possible_map; -extern unsigned long smp_proc_in_lock[]; -extern volatile unsigned long cpu_callin_map[]; -extern int smp_tb_synchronized; -extern struct smp_ops_t *smp_ops; - -extern void smp_send_tlb_invalidate(int); -extern void smp_send_xmon_break(int cpu); -struct pt_regs; -extern void smp_message_recv(int); - -extern int __cpu_disable(void); -extern void __cpu_die(unsigned int cpu); -extern void cpu_die(void) __attribute__((noreturn)); - -#define raw_smp_processor_id() (current_thread_info()->cpu) - -extern int __cpu_up(unsigned int cpu); - -extern int smp_hw_index[]; -#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) -#define get_hard_smp_processor_id(cpu) (smp_hw_index[(cpu)]) -#define set_hard_smp_processor_id(cpu, phys)\ - (smp_hw_index[(cpu)] = (phys)) - -#endif /* __ASSEMBLY__ */ - -#else /* !(CONFIG_SMP) */ - -static inline void cpu_die(void) { } -#define get_hard_smp_processor_id(cpu) 0 -#define set_hard_smp_processor_id(cpu, phys) -#define hard_smp_processor_id() 0 - -#endif /* !(CONFIG_SMP) */ - -#ifndef __ASSEMBLY__ -extern int boot_cpuid; -extern int boot_cpuid_phys; -#endif - -#endif /* !(_PPC_SMP_H) */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h deleted file mode 100644 index fccaf5531e57..000000000000 --- a/include/asm-ppc/spinlock.h +++ /dev/null @@ -1,168 +0,0 @@ -#ifndef __ASM_SPINLOCK_H -#define __ASM_SPINLOCK_H - -#include <asm/system.h> - -/* - * Simple spin lock operations. - * - * (the type definitions are in asm/raw_spinlock_types.h) - */ - -#define __raw_spin_is_locked(x) ((x)->slock != 0) -#define __raw_spin_unlock_wait(lock) \ - do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0) -#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) - -static inline void __raw_spin_lock(raw_spinlock_t *lock) -{ - unsigned long tmp; - - __asm__ __volatile__( - "b 1f # __raw_spin_lock\n\ -2: lwzx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne+ 2b\n\ -1: lwarx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne- 2b\n" - PPC405_ERR77(0,%1) -" stwcx. %2,0,%1\n\ - bne- 2b\n\ - isync" - : "=&r"(tmp) - : "r"(&lock->slock), "r"(1) - : "cr0", "memory"); -} - -static inline void __raw_spin_unlock(raw_spinlock_t *lock) -{ - __asm__ __volatile__("eieio # __raw_spin_unlock": : :"memory"); - lock->slock = 0; -} - -#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock))) - -/* - * Read-write spinlocks, allowing multiple readers - * but only one writer. - * - * NOTE! it is quite common to have readers in interrupts - * but no interrupt writers. For those circumstances we - * can "mix" irq-safe locks - any writer needs to get a - * irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - */ - -#define __raw_read_can_lock(rw) ((rw)->lock >= 0) -#define __raw_write_can_lock(rw) (!(rw)->lock) - -static __inline__ int __raw_read_trylock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( -"2: lwarx %0,0,%1 # read_trylock\n\ - addic. %0,%0,1\n\ - ble- 1f\n" - PPC405_ERR77(0,%1) -" stwcx. %0,0,%1\n\ - bne- 2b\n\ - isync\n\ -1:" - : "=&r"(tmp) - : "r"(&rw->lock) - : "cr0", "memory"); - - return tmp > 0; -} - -static __inline__ void __raw_read_lock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( - "b 2f # read_lock\n\ -1: lwzx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - blt+ 1b\n\ -2: lwarx %0,0,%1\n\ - addic. %0,%0,1\n\ - ble- 1b\n" - PPC405_ERR77(0,%1) -" stwcx. %0,0,%1\n\ - bne- 2b\n\ - isync" - : "=&r"(tmp) - : "r"(&rw->lock) - : "cr0", "memory"); -} - -static __inline__ void __raw_read_unlock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( - "eieio # read_unlock\n\ -1: lwarx %0,0,%1\n\ - addic %0,%0,-1\n" - PPC405_ERR77(0,%1) -" stwcx. %0,0,%1\n\ - bne- 1b" - : "=&r"(tmp) - : "r"(&rw->lock) - : "cr0", "memory"); -} - -static __inline__ int __raw_write_trylock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( -"2: lwarx %0,0,%1 # write_trylock\n\ - cmpwi 0,%0,0\n\ - bne- 1f\n" - PPC405_ERR77(0,%1) -" stwcx. %2,0,%1\n\ - bne- 2b\n\ - isync\n\ -1:" - : "=&r"(tmp) - : "r"(&rw->lock), "r"(-1) - : "cr0", "memory"); - - return tmp == 0; -} - -static __inline__ void __raw_write_lock(raw_rwlock_t *rw) -{ - signed int tmp; - - __asm__ __volatile__( - "b 2f # write_lock\n\ -1: lwzx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne+ 1b\n\ -2: lwarx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne- 1b\n" - PPC405_ERR77(0,%1) -" stwcx. %2,0,%1\n\ - bne- 2b\n\ - isync" - : "=&r"(tmp) - : "r"(&rw->lock), "r"(-1) - : "cr0", "memory"); -} - -static __inline__ void __raw_write_unlock(raw_rwlock_t *rw) -{ - __asm__ __volatile__("eieio # write_unlock": : :"memory"); - rw->lock = 0; -} - -#define _raw_spin_relax(lock) cpu_relax() -#define _raw_read_relax(lock) cpu_relax() -#define _raw_write_relax(lock) cpu_relax() - -#endif /* __ASM_SPINLOCK_H */ diff --git a/include/asm-ppc/suspend.h b/include/asm-ppc/suspend.h deleted file mode 100644 index 3df9f32bd834..000000000000 --- a/include/asm-ppc/suspend.h +++ /dev/null @@ -1,12 +0,0 @@ -static inline int arch_prepare_suspend(void) -{ - return 0; -} - -static inline void save_processor_state(void) -{ -} - -static inline void restore_processor_state(void) -{ -} diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h deleted file mode 100644 index 70ebd333c55b..000000000000 --- a/include/asm-ppc/system.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> - */ -#ifndef __PPC_SYSTEM_H -#define __PPC_SYSTEM_H - -#include <linux/kernel.h> - -#include <asm/hw_irq.h> - -/* - * Memory barrier. - * The sync instruction guarantees that all memory accesses initiated - * by this processor have been performed (with respect to all other - * mechanisms that access memory). The eieio instruction is a barrier - * providing an ordering (separately) for (a) cacheable stores and (b) - * loads and stores to non-cacheable memory (e.g. I/O devices). - * - * mb() prevents loads and stores being reordered across this point. - * rmb() prevents loads being reordered across this point. - * wmb() prevents stores being reordered across this point. - * read_barrier_depends() prevents data-dependent loads being reordered - * across this point (nop on PPC). - * - * We can use the eieio instruction for wmb, but since it doesn't - * give any ordering guarantees about loads, we have to use the - * stronger but slower sync instruction for mb and rmb. - */ -#define mb() __asm__ __volatile__ ("sync" : : : "memory") -#define rmb() __asm__ __volatile__ ("sync" : : : "memory") -#define wmb() __asm__ __volatile__ ("eieio" : : : "memory") -#define read_barrier_depends() do { } while(0) - -#define set_mb(var, value) do { var = value; mb(); } while (0) - -#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */ -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") -#define smp_read_barrier_depends() read_barrier_depends() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) -#endif /* CONFIG_SMP */ - -#ifdef __KERNEL__ -struct task_struct; -struct pt_regs; - -extern void print_backtrace(unsigned long *); -extern void show_regs(struct pt_regs * regs); -extern void flush_instruction_cache(void); -extern void hard_reset_now(void); -extern void poweroff_now(void); -extern int set_dabr(unsigned long dabr); -#ifdef CONFIG_6xx -extern long _get_L2CR(void); -extern long _get_L3CR(void); -extern void _set_L2CR(unsigned long); -extern void _set_L3CR(unsigned long); -#else -#define _get_L2CR() 0L -#define _get_L3CR() 0L -#define _set_L2CR(val) do { } while(0) -#define _set_L3CR(val) do { } while(0) -#endif -extern void via_cuda_init(void); -extern void pmac_nvram_init(void); -extern void chrp_nvram_init(void); -extern void read_rtc_time(void); -extern void pmac_find_display(void); -extern void giveup_fpu(struct task_struct *); -extern void disable_kernel_fp(void); -extern void enable_kernel_fp(void); -extern void flush_fp_to_thread(struct task_struct *); -extern void enable_kernel_altivec(void); -extern void giveup_altivec(struct task_struct *); -extern void load_up_altivec(struct task_struct *); -extern int emulate_altivec(struct pt_regs *); -extern void giveup_spe(struct task_struct *); -extern void load_up_spe(struct task_struct *); -extern int fix_alignment(struct pt_regs *); -extern void cvt_fd(float *from, double *to, struct thread_struct *thread); -extern void cvt_df(double *from, float *to, struct thread_struct *thread); - -#ifndef CONFIG_SMP -extern void discard_lazy_cpu_state(void); -#else -static inline void discard_lazy_cpu_state(void) -{ -} -#endif - -#ifdef CONFIG_ALTIVEC -extern void flush_altivec_to_thread(struct task_struct *); -#else -static inline void flush_altivec_to_thread(struct task_struct *t) -{ -} -#endif - -#ifdef CONFIG_SPE -extern void flush_spe_to_thread(struct task_struct *); -#else -static inline void flush_spe_to_thread(struct task_struct *t) -{ -} -#endif - -extern int call_rtas(const char *, int, int, unsigned long *, ...); -extern void cacheable_memzero(void *p, unsigned int nb); -extern void *cacheable_memcpy(void *, const void *, unsigned int); -extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); -extern void bad_page_fault(struct pt_regs *, unsigned long, int); -extern int die(const char *, struct pt_regs *, long); -extern void _exception(int, struct pt_regs *, int, unsigned long); -void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); - -#ifdef CONFIG_BOOKE_WDT -extern u32 booke_wdt_enabled; -extern u32 booke_wdt_period; -#endif /* CONFIG_BOOKE_WDT */ - -struct device_node; -extern void note_scsi_host(struct device_node *, void *); - -extern struct task_struct *__switch_to(struct task_struct *, - struct task_struct *); -#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) - -struct thread_struct; -extern struct task_struct *_switch(struct thread_struct *prev, - struct thread_struct *next); - -extern unsigned int rtas_data; - -static __inline__ unsigned long -xchg_u32(volatile void *p, unsigned long val) -{ - unsigned long prev; - - __asm__ __volatile__ ("\n\ -1: lwarx %0,0,%2 \n" - PPC405_ERR77(0,%2) -" stwcx. %3,0,%2 \n\ - bne- 1b" - : "=&r" (prev), "=m" (*(volatile unsigned long *)p) - : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) - : "cc", "memory"); - - return prev; -} - -/* - * This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid xchg(). - */ -extern void __xchg_called_with_bad_pointer(void); - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) -{ - switch (size) { - case 4: - return (unsigned long) xchg_u32(ptr, x); -#if 0 /* xchg_u64 doesn't exist on 32-bit PPC */ - case 8: - return (unsigned long) xchg_u64(ptr, x); -#endif /* 0 */ - } - __xchg_called_with_bad_pointer(); - return x; - - -} - -static inline void * xchg_ptr(void * m, void * val) -{ - return (void *) xchg_u32(m, (unsigned long) val); -} - - -#define __HAVE_ARCH_CMPXCHG 1 - -static __inline__ unsigned long -__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) -{ - unsigned int prev; - - __asm__ __volatile__ ("\n\ -1: lwarx %0,0,%2 \n\ - cmpw 0,%0,%3 \n\ - bne 2f \n" - PPC405_ERR77(0,%2) -" stwcx. %4,0,%2 \n\ - bne- 1b\n" -#ifdef CONFIG_SMP -" sync\n" -#endif /* CONFIG_SMP */ -"2:" - : "=&r" (prev), "=m" (*p) - : "r" (p), "r" (old), "r" (new), "m" (*p) - : "cc", "memory"); - - return prev; -} - -static inline unsigned long -__cmpxchg_u32_local(volatile unsigned int *p, unsigned int old, - unsigned int new) -{ - unsigned int prev; - - __asm__ __volatile__ ("\n\ -1: lwarx %0,0,%2 \n\ - cmpw 0,%0,%3 \n\ - bne 2f \n" - PPC405_ERR77(0,%2) -" stwcx. %4,0,%2 \n\ - bne- 1b\n" -"2:" - : "=&r" (prev), "=m" (*p) - : "r" (p), "r" (old), "r" (new), "m" (*p) - : "cc", "memory"); - - return prev; -} - -/* This function doesn't exist, so you'll get a linker error - if something tries to do an invalid cmpxchg(). */ -extern void __cmpxchg_called_with_bad_pointer(void); - -static __inline__ unsigned long -__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, - unsigned int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32(ptr, old, new); -#if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */ - case 8: - return __cmpxchg_u64(ptr, old, new); -#endif /* 0 */ - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - -#define cmpxchg(ptr, o, n) \ - ({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ - (unsigned long)_n_, sizeof(*(ptr))); \ - }) - -#include <asm-generic/cmpxchg-local.h> - -static inline unsigned long __cmpxchg_local(volatile void *ptr, - unsigned long old, - unsigned long new, int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32_local(ptr, old, new); - default: - return __cmpxchg_local_generic(ptr, old, new, size); - } - - return old; -} - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#define arch_align_stack(x) (x) - -#endif /* __KERNEL__ */ -#endif /* __PPC_SYSTEM_H */ diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h deleted file mode 100644 index 81dbcd43a501..000000000000 --- a/include/asm-ppc/time.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Common time prototypes and such for all ppc machines. - * - * Written by Cort Dougan (cort@fsmlabs.com) to merge - * Paul Mackerras' version and mine for PReP and Pmac. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_TIME_H__ -#define __ASM_TIME_H__ - -#include <linux/types.h> -#include <linux/rtc.h> -#include <linux/threads.h> - -#include <asm/reg.h> - -/* time.c */ -extern unsigned tb_ticks_per_jiffy; -extern unsigned tb_to_us; -extern unsigned tb_last_stamp; -extern unsigned long disarm_decr[NR_CPUS]; - -extern void to_tm(int tim, struct rtc_time * tm); -extern time_t last_rtc_update; - -extern void set_dec_cpu6(unsigned int val); - -int via_calibrate_decr(void); - -/* Accessor functions for the decrementer register. - * The 4xx doesn't even have a decrementer. I tried to use the - * generic timer interrupt code, which seems OK, with the 4xx PIT - * in auto-reload mode. The problem is PIT stops counting when it - * hits zero. If it would wrap, we could use it just like a decrementer. - */ -static __inline__ unsigned int get_dec(void) -{ -#if defined(CONFIG_40x) - return (mfspr(SPRN_PIT)); -#else - return (mfspr(SPRN_DEC)); -#endif -} - -static __inline__ void set_dec(unsigned int val) -{ -#if defined(CONFIG_40x) - return; /* Have to let it auto-reload */ -#elif defined(CONFIG_8xx_CPU6) - set_dec_cpu6(val); -#else - mtspr(SPRN_DEC, val); -#endif -} - -/* Accessor functions for the timebase (RTC on 601) registers. */ -/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ -#ifdef CONFIG_6xx -extern __inline__ int __pure __USE_RTC(void) { - return (mfspr(SPRN_PVR)>>16) == 1; -} -#else -#define __USE_RTC() 0 -#endif - -extern __inline__ unsigned long get_tbl(void) { - unsigned long tbl; -#if defined(CONFIG_403GCX) - asm volatile("mfspr %0, 0x3dd" : "=r" (tbl)); -#else - asm volatile("mftb %0" : "=r" (tbl)); -#endif - return tbl; -} - -extern __inline__ unsigned long get_tbu(void) { - unsigned long tbl; -#if defined(CONFIG_403GCX) - asm volatile("mfspr %0, 0x3dc" : "=r" (tbl)); -#else - asm volatile("mftbu %0" : "=r" (tbl)); -#endif - return tbl; -} - -extern __inline__ void set_tb(unsigned int upper, unsigned int lower) -{ - mtspr(SPRN_TBWL, 0); - mtspr(SPRN_TBWU, upper); - mtspr(SPRN_TBWL, lower); -} - -extern __inline__ unsigned long get_rtcl(void) { - unsigned long rtcl; - asm volatile("mfrtcl %0" : "=r" (rtcl)); - return rtcl; -} - -extern __inline__ unsigned long get_rtcu(void) -{ - unsigned long rtcu; - asm volatile("mfrtcu %0" : "=r" (rtcu)); - return rtcu; -} - -extern __inline__ unsigned get_native_tbl(void) { - if (__USE_RTC()) - return get_rtcl(); - else - return get_tbl(); -} - -/* On machines with RTC, this function can only be used safely - * after the timestamp and for 1 second. It is only used by gettimeofday - * however so it should not matter. - */ -extern __inline__ unsigned tb_ticks_since(unsigned tstamp) { - if (__USE_RTC()) { - int delta = get_rtcl() - tstamp; - return delta<0 ? delta + 1000000000 : delta; - } else { - return get_tbl() - tstamp; - } -} - -#if 0 -extern __inline__ unsigned long get_bin_rtcl(void) { - unsigned long rtcl, rtcu1, rtcu2; - asm volatile("\ -1: mfrtcu %0\n\ - mfrtcl %1\n\ - mfrtcu %2\n\ - cmpw %0,%2\n\ - bne- 1b\n" - : "=r" (rtcu1), "=r" (rtcl), "=r" (rtcu2) - : : "cr0"); - return rtcu2*1000000000+rtcl; -} - -extern __inline__ unsigned binary_tbl(void) { - if (__USE_RTC()) - return get_bin_rtcl(); - else - return get_tbl(); -} -#endif - -/* Use mulhwu to scale processor timebase to timeval */ -/* Specifically, this computes (x * y) / 2^32. -- paulus */ -#define mulhwu(x,y) \ -({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) - -unsigned mulhwu_scale_factor(unsigned, unsigned); - -#define account_process_vtime(tsk) do { } while (0) -#define calculate_steal_time() do { } while (0) -#define snapshot_timebases() do { } while (0) - -#endif /* __ASM_TIME_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h deleted file mode 100644 index 937c7dbe6e5c..000000000000 --- a/include/asm-ppc/todc.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Definitions for the M48Txx and mc146818 series of Time of day/Real Time - * Clock chips. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * 2001 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* - * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips. - * Purpose is to make one generic file that handles all of these chips instead - * of every platform implementing the same code over & over again. - */ - -#ifndef __PPC_KERNEL_TODC_H -#define __PPC_KERNEL_TODC_H - -typedef struct { - uint rtc_type; /* your particular chip */ - - /* - * Following are the addresses of the AS0, AS1, and DATA registers - * of these chips. Note that these are board-specific. - */ - unsigned int nvram_as0; - unsigned int nvram_as1; - unsigned int nvram_data; - - /* - * Define bits to stop external set of regs from changing so - * the chip can be read/written reliably. - */ - unsigned char enable_read; - unsigned char enable_write; - - /* - * Following is the number of AS0 address bits. This is normally - * 8 but some bad hardware routes address lines incorrectly. - */ - int as0_bits; - - int nvram_size; /* Size of NVRAM on chip */ - int sw_flags; /* Software control flags */ - - /* Following are the register offsets for the particular chip */ - int year; - int month; - int day_of_month; - int day_of_week; - int hours; - int minutes; - int seconds; - int control_b; - int control_a; - int watchdog; - int interrupts; - int alarm_date; - int alarm_hour; - int alarm_minutes; - int alarm_seconds; - int century; - int flags; - - /* - * Some RTC chips have their NVRAM buried behind a addr/data pair of - * regs on the first level/clock registers. The following fields - * are the addresses for those addr/data regs. - */ - int nvram_addr_reg; - int nvram_data_reg; -} todc_info_t; - -/* - * Define the types of TODC/RTC variants that are supported in - * arch/ppc/kernel/todc_time.c - * Make a new one of these for any chip somehow differs from what's already - * defined. That way, if you ever need to put in code to touch those - * bits/registers in todc_time.c, you can put it inside an - * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break - * anyone else. - */ -#define TODC_TYPE_MK48T35 1 -#define TODC_TYPE_MK48T37 2 -#define TODC_TYPE_MK48T59 3 -#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */ -#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */ -#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */ -#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */ -#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */ -#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */ -#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */ -#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */ -#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */ -#define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */ -#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */ - -/* - * Bit to clear/set to enable reads/writes to the chip - */ -#define TODC_MK48TXX_CNTL_A_R 0x40 -#define TODC_MK48TXX_CNTL_A_W 0x80 -#define TODC_MK48TXX_DAY_CB 0x80 - -#define TODC_DS1501_CNTL_B_TE 0x80 - -/* - * Define flag bits used by todc routines. - */ -#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001 - -/* - * Define the values for the various RTC's that should to into the todc_info - * table. - * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only - * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set. - */ -#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8 -#define TODC_TYPE_MK48T35_SW_FLAGS 0 -#define TODC_TYPE_MK48T35_YEAR 0x7fff -#define TODC_TYPE_MK48T35_MONTH 0x7ffe -#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */ -#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */ -#define TODC_TYPE_MK48T35_HOURS 0x7ffb -#define TODC_TYPE_MK48T35_MINUTES 0x7ffa -#define TODC_TYPE_MK48T35_SECONDS 0x7ff9 -#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9 -#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8 -#define TODC_TYPE_MK48T35_WATCHDOG 0x0000 -#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000 -#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000 -#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000 -#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000 -#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000 -#define TODC_TYPE_MK48T35_CENTURY 0x0000 -#define TODC_TYPE_MK48T35_FLAGS 0x0000 -#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0 -#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0 - -#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0 -#define TODC_TYPE_MK48T37_SW_FLAGS 0 -#define TODC_TYPE_MK48T37_YEAR 0x7fff -#define TODC_TYPE_MK48T37_MONTH 0x7ffe -#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */ -#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */ -#define TODC_TYPE_MK48T37_HOURS 0x7ffb -#define TODC_TYPE_MK48T37_MINUTES 0x7ffa -#define TODC_TYPE_MK48T37_SECONDS 0x7ff9 -#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9 -#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8 -#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7 -#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6 -#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5 -#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4 -#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3 -#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2 -#define TODC_TYPE_MK48T37_CENTURY 0x7ff1 -#define TODC_TYPE_MK48T37_FLAGS 0x7ff0 -#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0 -#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0 - -#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0 -#define TODC_TYPE_MK48T59_SW_FLAGS 0 -#define TODC_TYPE_MK48T59_YEAR 0x1fff -#define TODC_TYPE_MK48T59_MONTH 0x1ffe -#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */ -#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */ -#define TODC_TYPE_MK48T59_HOURS 0x1ffb -#define TODC_TYPE_MK48T59_MINUTES 0x1ffa -#define TODC_TYPE_MK48T59_SECONDS 0x1ff9 -#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9 -#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8 -#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff -#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff -#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff -#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff -#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff -#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff -#define TODC_TYPE_MK48T59_CENTURY 0x1fff -#define TODC_TYPE_MK48T59_FLAGS 0x1fff -#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0 -#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100 -#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM -#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06) -#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05) -#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04) -#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03) -#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02) -#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01) -#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00) -#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f) -#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f) -#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) -#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) -#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b) -#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a) -#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09) -#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08) -#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07) -#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) -#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10 -#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13 - -#define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0 -#define TODC_TYPE_DS1553_SW_FLAGS 0 -#define TODC_TYPE_DS1553_YEAR 0x1fff -#define TODC_TYPE_DS1553_MONTH 0x1ffe -#define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */ -#define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */ -#define TODC_TYPE_DS1553_HOURS 0x1ffb -#define TODC_TYPE_DS1553_MINUTES 0x1ffa -#define TODC_TYPE_DS1553_SECONDS 0x1ff9 -#define TODC_TYPE_DS1553_CNTL_B 0x1ff9 -#define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1553_WATCHDOG 0x1ff7 -#define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6 -#define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5 -#define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4 -#define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3 -#define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2 -#define TODC_TYPE_DS1553_CENTURY 0x1ff8 -#define TODC_TYPE_DS1553_FLAGS 0x1ff0 -#define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1553_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0 -#define TODC_TYPE_DS1557_SW_FLAGS 0 -#define TODC_TYPE_DS1557_YEAR 0x7ffff -#define TODC_TYPE_DS1557_MONTH 0x7fffe -#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */ -#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */ -#define TODC_TYPE_DS1557_HOURS 0x7fffb -#define TODC_TYPE_DS1557_MINUTES 0x7fffa -#define TODC_TYPE_DS1557_SECONDS 0x7fff9 -#define TODC_TYPE_DS1557_CNTL_B 0x7fff9 -#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7 -#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6 -#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5 -#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4 -#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3 -#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2 -#define TODC_TYPE_DS1557_CENTURY 0x7fff8 -#define TODC_TYPE_DS1557_FLAGS 0x7fff0 -#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8 -#define TODC_TYPE_DS1643_SW_FLAGS 0 -#define TODC_TYPE_DS1643_YEAR 0x1fff -#define TODC_TYPE_DS1643_MONTH 0x1ffe -#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */ -#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */ -#define TODC_TYPE_DS1643_HOURS 0x1ffb -#define TODC_TYPE_DS1643_MINUTES 0x1ffa -#define TODC_TYPE_DS1643_SECONDS 0x1ff9 -#define TODC_TYPE_DS1643_CNTL_B 0x1ff9 -#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1643_WATCHDOG 0x1fff -#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff -#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff -#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff -#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff -#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff -#define TODC_TYPE_DS1643_CENTURY 0x1ff8 -#define TODC_TYPE_DS1643_FLAGS 0x1fff -#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */ -#define TODC_TYPE_DS1693_SW_FLAGS 0 -#define TODC_TYPE_DS1693_YEAR 0x09 -#define TODC_TYPE_DS1693_MONTH 0x08 -#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */ -#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */ -#define TODC_TYPE_DS1693_HOURS 0x04 -#define TODC_TYPE_DS1693_MINUTES 0x02 -#define TODC_TYPE_DS1693_SECONDS 0x00 -#define TODC_TYPE_DS1693_CNTL_B 0x0b -#define TODC_TYPE_DS1693_CNTL_A 0x0a -#define TODC_TYPE_DS1693_WATCHDOG 0xff -#define TODC_TYPE_DS1693_INTERRUPTS 0xff -#define TODC_TYPE_DS1693_ALARM_DATE 0x49 -#define TODC_TYPE_DS1693_ALARM_HOUR 0x05 -#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03 -#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01 -#define TODC_TYPE_DS1693_CENTURY 0x48 -#define TODC_TYPE_DS1693_FLAGS 0xff -#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8 -#define TODC_TYPE_DS1743_SW_FLAGS 0 -#define TODC_TYPE_DS1743_YEAR 0x1fff -#define TODC_TYPE_DS1743_MONTH 0x1ffe -#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */ -#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */ -#define TODC_TYPE_DS1743_HOURS 0x1ffb -#define TODC_TYPE_DS1743_MINUTES 0x1ffa -#define TODC_TYPE_DS1743_SECONDS 0x1ff9 -#define TODC_TYPE_DS1743_CNTL_B 0x1ff9 -#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1743_WATCHDOG 0x1fff -#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff -#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff -#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff -#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff -#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff -#define TODC_TYPE_DS1743_CENTURY 0x1ff8 -#define TODC_TYPE_DS1743_FLAGS 0x1fff -#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8 -#define TODC_TYPE_DS1746_SW_FLAGS 0 -#define TODC_TYPE_DS1746_YEAR 0x1ffff -#define TODC_TYPE_DS1746_MONTH 0x1fffe -#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */ -#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */ -#define TODC_TYPE_DS1746_HOURS 0x1fffb -#define TODC_TYPE_DS1746_MINUTES 0x1fffa -#define TODC_TYPE_DS1746_SECONDS 0x1fff9 -#define TODC_TYPE_DS1746_CNTL_B 0x1fff9 -#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1746_WATCHDOG 0x00000 -#define TODC_TYPE_DS1746_INTERRUPTS 0x00000 -#define TODC_TYPE_DS1746_ALARM_DATE 0x00000 -#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000 -#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000 -#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000 -#define TODC_TYPE_DS1746_CENTURY 0x00000 -#define TODC_TYPE_DS1746_FLAGS 0x00000 -#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8 -#define TODC_TYPE_DS1747_SW_FLAGS 0 -#define TODC_TYPE_DS1747_YEAR 0x7ffff -#define TODC_TYPE_DS1747_MONTH 0x7fffe -#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */ -#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */ -#define TODC_TYPE_DS1747_HOURS 0x7fffb -#define TODC_TYPE_DS1747_MINUTES 0x7fffa -#define TODC_TYPE_DS1747_SECONDS 0x7fff9 -#define TODC_TYPE_DS1747_CNTL_B 0x7fff9 -#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */ -#define TODC_TYPE_DS1747_WATCHDOG 0x00000 -#define TODC_TYPE_DS1747_INTERRUPTS 0x00000 -#define TODC_TYPE_DS1747_ALARM_DATE 0x00000 -#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000 -#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000 -#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000 -#define TODC_TYPE_DS1747_CENTURY 0x00000 -#define TODC_TYPE_DS1747_FLAGS 0x00000 -#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0 -#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0 - -#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */ -#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM -#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00) -#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01) -#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02) -#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03) -#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04) -#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05) -#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06) -#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07) -#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08) -#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09) -#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A) -#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B) -#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C) -#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D) -#define TODC_TYPE_DS17285_WATCHDOG 0 -#define TODC_TYPE_DS17285_INTERRUPTS 0 -#define TODC_TYPE_DS17285_ALARM_DATE 0 -#define TODC_TYPE_DS17285_CENTURY 0 -#define TODC_TYPE_DS17285_FLAGS 0 -#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50 -#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53 - -#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */ -#define TODC_TYPE_MC146818_SW_FLAGS 0 -#define TODC_TYPE_MC146818_YEAR 0x09 -#define TODC_TYPE_MC146818_MONTH 0x08 -#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */ -#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */ -#define TODC_TYPE_MC146818_HOURS 0x04 -#define TODC_TYPE_MC146818_MINUTES 0x02 -#define TODC_TYPE_MC146818_SECONDS 0x00 -#define TODC_TYPE_MC146818_CNTL_B 0x0a -#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */ -#define TODC_TYPE_MC146818_WATCHDOG 0 -#define TODC_TYPE_MC146818_INTERRUPTS 0x0c -#define TODC_TYPE_MC146818_ALARM_DATE 0xff -#define TODC_TYPE_MC146818_ALARM_HOUR 0x05 -#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03 -#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01 -#define TODC_TYPE_MC146818_CENTURY 0xff -#define TODC_TYPE_MC146818_FLAGS 0xff -#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0 -#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0 - -#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */ -#define TODC_TYPE_PC97307_SW_FLAGS 0 -#define TODC_TYPE_PC97307_YEAR 0x09 -#define TODC_TYPE_PC97307_MONTH 0x08 -#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */ -#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */ -#define TODC_TYPE_PC97307_HOURS 0x04 -#define TODC_TYPE_PC97307_MINUTES 0x02 -#define TODC_TYPE_PC97307_SECONDS 0x00 -#define TODC_TYPE_PC97307_CNTL_B 0x0a -#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */ -#define TODC_TYPE_PC97307_WATCHDOG 0x0c -#define TODC_TYPE_PC97307_INTERRUPTS 0x0d -#define TODC_TYPE_PC97307_ALARM_DATE 0xff -#define TODC_TYPE_PC97307_ALARM_HOUR 0x05 -#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03 -#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01 -#define TODC_TYPE_PC97307_CENTURY 0xff -#define TODC_TYPE_PC97307_FLAGS 0xff -#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0 -#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0 - -/* - * Define macros to allocate and init the todc_info_t table that will - * be used by the todc_time.c routines. - */ -#define TODC_ALLOC() \ - static todc_info_t todc_info_alloc; \ - todc_info_t *todc_info = &todc_info_alloc; - -#define TODC_INIT(clock_type, as0, as1, data, bits) { \ - todc_info->rtc_type = clock_type; \ - \ - todc_info->nvram_as0 = (unsigned int)(as0); \ - todc_info->nvram_as1 = (unsigned int)(as1); \ - todc_info->nvram_data = (unsigned int)(data); \ - \ - todc_info->as0_bits = (bits); \ - \ - todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \ - todc_info->sw_flags = clock_type ##_SW_FLAGS; \ - \ - todc_info->year = clock_type ##_YEAR; \ - todc_info->month = clock_type ##_MONTH; \ - todc_info->day_of_month = clock_type ##_DOM; \ - todc_info->day_of_week = clock_type ##_DOW; \ - todc_info->hours = clock_type ##_HOURS; \ - todc_info->minutes = clock_type ##_MINUTES; \ - todc_info->seconds = clock_type ##_SECONDS; \ - todc_info->control_b = clock_type ##_CNTL_B; \ - todc_info->control_a = clock_type ##_CNTL_A; \ - todc_info->watchdog = clock_type ##_WATCHDOG; \ - todc_info->interrupts = clock_type ##_INTERRUPTS; \ - todc_info->alarm_date = clock_type ##_ALARM_DATE; \ - todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \ - todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \ - todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \ - todc_info->century = clock_type ##_CENTURY; \ - todc_info->flags = clock_type ##_FLAGS; \ - \ - todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \ - todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \ -} - -extern todc_info_t *todc_info; - -unsigned char todc_direct_read_val(int addr); -void todc_direct_write_val(int addr, unsigned char val); -unsigned char todc_m48txx_read_val(int addr); -void todc_m48txx_write_val(int addr, unsigned char val); -unsigned char todc_mc146818_read_val(int addr); -void todc_mc146818_write_val(int addr, unsigned char val); - -long todc_time_init(void); -unsigned long todc_get_rtc_time(void); -int todc_set_rtc_time(unsigned long nowtime); -void todc_calibrate_decr(void); - -#endif /* __PPC_KERNEL_TODC_H */ diff --git a/include/asm-ppc/traps.h b/include/asm-ppc/traps.h deleted file mode 100644 index 68e7326b56f1..000000000000 --- a/include/asm-ppc/traps.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-m68k/traps.h> diff --git a/include/asm-ppc/zorro.h b/include/asm-ppc/zorro.h deleted file mode 100644 index 1e5fbc65e77b..000000000000 --- a/include/asm-ppc/zorro.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ASM_PPC_ZORRO_H -#define _ASM_PPC_ZORRO_H - -#include <asm/io.h> - -#define z_readb in_8 -#define z_readw in_be16 -#define z_readl in_be32 - -#define z_writeb(val, port) out_8((port), (val)) -#define z_writew(val, port) out_be16((port), (val)) -#define z_writel(val, port) out_be32((port), (val)) - -#define z_memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define z_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define z_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -extern void *__ioremap(unsigned long address, unsigned long size, - unsigned long flags); - -extern void *ioremap(unsigned long address, unsigned long size); -extern void iounmap(void *addr); - -extern void *__ioremap(unsigned long address, unsigned long size, - unsigned long flags); - -#define z_ioremap ioremap -#define z_iounmap iounmap - -#endif /* _ASM_PPC_ZORRO_H */ diff --git a/include/asm-s390/airq.h b/include/asm-s390/airq.h index 41d028cb52a4..1ac80d6b0588 100644 --- a/include/asm-s390/airq.h +++ b/include/asm-s390/airq.h @@ -13,7 +13,7 @@ typedef void (*adapter_int_handler_t)(void *, void *); -void *s390_register_adapter_interrupt(adapter_int_handler_t, void *); -void s390_unregister_adapter_interrupt(void *); +void *s390_register_adapter_interrupt(adapter_int_handler_t, void *, u8); +void s390_unregister_adapter_interrupt(void *, u8); #endif /* _ASM_S390_AIRQ_H */ diff --git a/include/asm-s390/ccwdev.h b/include/asm-s390/ccwdev.h index 066aa70518ce..ba007d8df941 100644 --- a/include/asm-s390/ccwdev.h +++ b/include/asm-s390/ccwdev.h @@ -12,6 +12,7 @@ #include <linux/device.h> #include <linux/mod_devicetable.h> +#include <asm/fcx.h> /* structs from asm/cio.h */ struct irb; @@ -157,6 +158,17 @@ extern int ccw_device_start_timeout_key(struct ccw_device *, struct ccw1 *, extern int ccw_device_resume(struct ccw_device *); extern int ccw_device_halt(struct ccw_device *, unsigned long); extern int ccw_device_clear(struct ccw_device *, unsigned long); +int ccw_device_tm_start_key(struct ccw_device *cdev, struct tcw *tcw, + unsigned long intparm, u8 lpm, u8 key); +int ccw_device_tm_start_key(struct ccw_device *, struct tcw *, + unsigned long, u8, u8); +int ccw_device_tm_start_timeout_key(struct ccw_device *, struct tcw *, + unsigned long, u8, u8, int); +int ccw_device_tm_start(struct ccw_device *, struct tcw *, + unsigned long, u8); +int ccw_device_tm_start_timeout(struct ccw_device *, struct tcw *, + unsigned long, u8, int); +int ccw_device_tm_intrg(struct ccw_device *cdev); extern int ccw_device_set_online(struct ccw_device *cdev); extern int ccw_device_set_offline(struct ccw_device *cdev); diff --git a/include/asm-s390/cio.h b/include/asm-s390/cio.h index 0818ecd30ca6..6dccb071aec3 100644 --- a/include/asm-s390/cio.h +++ b/include/asm-s390/cio.h @@ -16,7 +16,7 @@ #define __MAX_CSSID 0 /** - * struct scsw - subchannel status word + * struct cmd_scsw - command-mode subchannel status word * @key: subchannel key * @sctl: suspend control * @eswf: esw format @@ -38,7 +38,7 @@ * @cstat: subchannel status * @count: residual count */ -struct scsw { +struct cmd_scsw { __u32 key : 4; __u32 sctl : 1; __u32 eswf : 1; @@ -61,6 +61,114 @@ struct scsw { __u32 count : 16; } __attribute__ ((packed)); +/** + * struct tm_scsw - transport-mode subchannel status word + * @key: subchannel key + * @eswf: esw format + * @cc: deferred condition code + * @fmt: format + * @x: IRB-format control + * @q: interrogate-complete + * @ectl: extended control + * @pno: path not operational + * @fctl: function control + * @actl: activity control + * @stctl: status control + * @tcw: TCW address + * @dstat: device status + * @cstat: subchannel status + * @fcxs: FCX status + * @schxs: subchannel-extended status + */ +struct tm_scsw { + u32 key:4; + u32 :1; + u32 eswf:1; + u32 cc:2; + u32 fmt:3; + u32 x:1; + u32 q:1; + u32 :1; + u32 ectl:1; + u32 pno:1; + u32 :1; + u32 fctl:3; + u32 actl:7; + u32 stctl:5; + u32 tcw; + u32 dstat:8; + u32 cstat:8; + u32 fcxs:8; + u32 schxs:8; +} __attribute__ ((packed)); + +/** + * union scsw - subchannel status word + * @cmd: command-mode SCSW + * @tm: transport-mode SCSW + */ +union scsw { + struct cmd_scsw cmd; + struct tm_scsw tm; +} __attribute__ ((packed)); + +int scsw_is_tm(union scsw *scsw); +u32 scsw_key(union scsw *scsw); +u32 scsw_eswf(union scsw *scsw); +u32 scsw_cc(union scsw *scsw); +u32 scsw_ectl(union scsw *scsw); +u32 scsw_pno(union scsw *scsw); +u32 scsw_fctl(union scsw *scsw); +u32 scsw_actl(union scsw *scsw); +u32 scsw_stctl(union scsw *scsw); +u32 scsw_dstat(union scsw *scsw); +u32 scsw_cstat(union scsw *scsw); +int scsw_is_solicited(union scsw *scsw); +int scsw_is_valid_key(union scsw *scsw); +int scsw_is_valid_eswf(union scsw *scsw); +int scsw_is_valid_cc(union scsw *scsw); +int scsw_is_valid_ectl(union scsw *scsw); +int scsw_is_valid_pno(union scsw *scsw); +int scsw_is_valid_fctl(union scsw *scsw); +int scsw_is_valid_actl(union scsw *scsw); +int scsw_is_valid_stctl(union scsw *scsw); +int scsw_is_valid_dstat(union scsw *scsw); +int scsw_is_valid_cstat(union scsw *scsw); +int scsw_cmd_is_valid_key(union scsw *scsw); +int scsw_cmd_is_valid_sctl(union scsw *scsw); +int scsw_cmd_is_valid_eswf(union scsw *scsw); +int scsw_cmd_is_valid_cc(union scsw *scsw); +int scsw_cmd_is_valid_fmt(union scsw *scsw); +int scsw_cmd_is_valid_pfch(union scsw *scsw); +int scsw_cmd_is_valid_isic(union scsw *scsw); +int scsw_cmd_is_valid_alcc(union scsw *scsw); +int scsw_cmd_is_valid_ssi(union scsw *scsw); +int scsw_cmd_is_valid_zcc(union scsw *scsw); +int scsw_cmd_is_valid_ectl(union scsw *scsw); +int scsw_cmd_is_valid_pno(union scsw *scsw); +int scsw_cmd_is_valid_fctl(union scsw *scsw); +int scsw_cmd_is_valid_actl(union scsw *scsw); +int scsw_cmd_is_valid_stctl(union scsw *scsw); +int scsw_cmd_is_valid_dstat(union scsw *scsw); +int scsw_cmd_is_valid_cstat(union scsw *scsw); +int scsw_cmd_is_solicited(union scsw *scsw); +int scsw_tm_is_valid_key(union scsw *scsw); +int scsw_tm_is_valid_eswf(union scsw *scsw); +int scsw_tm_is_valid_cc(union scsw *scsw); +int scsw_tm_is_valid_fmt(union scsw *scsw); +int scsw_tm_is_valid_x(union scsw *scsw); +int scsw_tm_is_valid_q(union scsw *scsw); +int scsw_tm_is_valid_ectl(union scsw *scsw); +int scsw_tm_is_valid_pno(union scsw *scsw); +int scsw_tm_is_valid_fctl(union scsw *scsw); +int scsw_tm_is_valid_actl(union scsw *scsw); +int scsw_tm_is_valid_stctl(union scsw *scsw); +int scsw_tm_is_valid_dstat(union scsw *scsw); +int scsw_tm_is_valid_cstat(union scsw *scsw); +int scsw_tm_is_valid_fcxs(union scsw *scsw); +int scsw_tm_is_valid_schxs(union scsw *scsw); +int scsw_tm_is_solicited(union scsw *scsw); + #define SCSW_FCTL_CLEAR_FUNC 0x1 #define SCSW_FCTL_HALT_FUNC 0x2 #define SCSW_FCTL_START_FUNC 0x4 @@ -303,7 +411,7 @@ struct esw3 { * if applicable). */ struct irb { - struct scsw scsw; + union scsw scsw; union { struct esw0 esw0; struct esw1 esw1; diff --git a/include/asm-s390/elf.h b/include/asm-s390/elf.h index b3ac262c4582..3cad56923815 100644 --- a/include/asm-s390/elf.h +++ b/include/asm-s390/elf.h @@ -113,6 +113,9 @@ typedef s390_fp_regs elf_fpregset_t; typedef s390_regs elf_gregset_t; +typedef s390_fp_regs compat_elf_fpregset_t; +typedef s390_compat_regs compat_elf_gregset_t; + #include <linux/sched.h> /* for task_struct */ #include <asm/system.h> /* for save_access_regs */ #include <asm/mmu_context.h> @@ -123,6 +126,10 @@ typedef s390_regs elf_gregset_t; #define elf_check_arch(x) \ (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \ && (x)->e_ident[EI_CLASS] == ELF_CLASS) +#define compat_elf_check_arch(x) \ + (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \ + && (x)->e_ident[EI_CLASS] == ELF_CLASS) +#define compat_start_thread start_thread31 /* For SVR4/S390 the function pointer to be registered with `atexit` is passed in R14. */ @@ -131,6 +138,7 @@ typedef s390_regs elf_gregset_t; _r->gprs[14] = 0; \ } while (0) +#define CORE_DUMP_USE_REGSET #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 @@ -140,44 +148,6 @@ typedef s390_regs elf_gregset_t; that it will "exec", and that there is sufficient room for the brk. */ #define ELF_ET_DYN_BASE (STACK_TOP / 3 * 2) -/* Wow, the "main" arch needs arch dependent functions too.. :) */ - -/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is - now struct_user_regs, they are different) */ - -static inline int dump_regs(struct pt_regs *ptregs, elf_gregset_t *regs) -{ - memcpy(®s->psw, &ptregs->psw, sizeof(regs->psw)+sizeof(regs->gprs)); - save_access_regs(regs->acrs); - regs->orig_gpr2 = ptregs->orig_gpr2; - return 1; -} - -#define ELF_CORE_COPY_REGS(pr_reg, regs) dump_regs(regs, &pr_reg); - -static inline int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs) -{ - struct pt_regs *ptregs = task_pt_regs(tsk); - memcpy(®s->psw, &ptregs->psw, sizeof(regs->psw)+sizeof(regs->gprs)); - memcpy(regs->acrs, tsk->thread.acrs, sizeof(regs->acrs)); - regs->orig_gpr2 = ptregs->orig_gpr2; - return 1; -} - -#define ELF_CORE_COPY_TASK_REGS(tsk, regs) dump_task_regs(tsk, regs) - -static inline int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs) -{ - if (tsk == current) - save_fp_regs(fpregs); - else - memcpy(fpregs, &tsk->thread.fp_regs, sizeof(elf_fpregset_t)); - return 1; -} - -#define ELF_CORE_COPY_FPREGS(tsk, fpregs) dump_task_fpu(tsk, fpregs) - - /* This yields a mask that user programs can use to figure out what instruction set this CPU supports. */ @@ -204,7 +174,10 @@ do { \ set_personality(PER_SVR4); \ else if (current->personality != PER_LINUX32) \ set_personality(PER_LINUX); \ - clear_thread_flag(TIF_31BIT); \ + if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ + set_thread_flag(TIF_31BIT); \ + else \ + clear_thread_flag(TIF_31BIT); \ } while (0) #endif /* __s390x__ */ diff --git a/include/asm-s390/etr.h b/include/asm-s390/etr.h index b498f19bb9a7..80ef58c61970 100644 --- a/include/asm-s390/etr.h +++ b/include/asm-s390/etr.h @@ -122,7 +122,7 @@ struct etr_aib { } __attribute__ ((packed,aligned(8))); /* ETR interruption parameter */ -struct etr_interruption_parameter { +struct etr_irq_parm { unsigned int _pad0 : 8; unsigned int pc0 : 1; /* port 0 state change */ unsigned int pc1 : 1; /* port 1 state change */ @@ -213,7 +213,46 @@ static inline int etr_ptff(void *ptff_block, unsigned int func) #define ETR_PTFF_SGS 0x43 /* set gross steering rate */ /* Functions needed by the machine check handler */ -extern void etr_switch_to_local(void); -extern void etr_sync_check(void); +void etr_switch_to_local(void); +void etr_sync_check(void); + +/* STP interruption parameter */ +struct stp_irq_parm { + unsigned int _pad0 : 14; + unsigned int tsc : 1; /* Timing status change */ + unsigned int lac : 1; /* Link availability change */ + unsigned int tcpc : 1; /* Time control parameter change */ + unsigned int _pad2 : 15; +} __attribute__ ((packed)); + +#define STP_OP_SYNC 1 +#define STP_OP_CTRL 3 + +struct stp_sstpi { + unsigned int rsvd0; + unsigned int rsvd1 : 8; + unsigned int stratum : 8; + unsigned int vbits : 16; + unsigned int leaps : 16; + unsigned int tmd : 4; + unsigned int ctn : 4; + unsigned int rsvd2 : 3; + unsigned int c : 1; + unsigned int tst : 4; + unsigned int tzo : 16; + unsigned int dsto : 16; + unsigned int ctrl : 16; + unsigned int rsvd3 : 16; + unsigned int tto; + unsigned int rsvd4; + unsigned int ctnid[3]; + unsigned int rsvd5; + unsigned int todoff[4]; + unsigned int rsvd6[48]; +} __attribute__ ((packed)); + +/* Functions needed by the machine check handler */ +void stp_sync_check(void); +void stp_island_check(void); #endif /* __S390_ETR_H */ diff --git a/include/asm-s390/fcx.h b/include/asm-s390/fcx.h new file mode 100644 index 000000000000..8be1f3a58042 --- /dev/null +++ b/include/asm-s390/fcx.h @@ -0,0 +1,311 @@ +/* + * Functions for assembling fcx enabled I/O control blocks. + * + * Copyright IBM Corp. 2008 + * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com> + */ + +#ifndef _ASM_S390_FCX_H +#define _ASM_S390_FCX_H _ASM_S390_FCX_H + +#include <linux/types.h> + +#define TCW_FORMAT_DEFAULT 0 +#define TCW_TIDAW_FORMAT_DEFAULT 0 +#define TCW_FLAGS_INPUT_TIDA 1 << (23 - 5) +#define TCW_FLAGS_TCCB_TIDA 1 << (23 - 6) +#define TCW_FLAGS_OUTPUT_TIDA 1 << (23 - 7) +#define TCW_FLAGS_TIDAW_FORMAT(x) ((x) & 3) << (23 - 9) +#define TCW_FLAGS_GET_TIDAW_FORMAT(x) (((x) >> (23 - 9)) & 3) + +/** + * struct tcw - Transport Control Word (TCW) + * @format: TCW format + * @flags: TCW flags + * @tccbl: Transport-Command-Control-Block Length + * @r: Read Operations + * @w: Write Operations + * @output: Output-Data Address + * @input: Input-Data Address + * @tsb: Transport-Status-Block Address + * @tccb: Transport-Command-Control-Block Address + * @output_count: Output Count + * @input_count: Input Count + * @intrg: Interrogate TCW Address + */ +struct tcw { + u32 format:2; + u32 :6; + u32 flags:24; + u32 :8; + u32 tccbl:6; + u32 r:1; + u32 w:1; + u32 :16; + u64 output; + u64 input; + u64 tsb; + u64 tccb; + u32 output_count; + u32 input_count; + u32 :32; + u32 :32; + u32 :32; + u32 intrg; +} __attribute__ ((packed, aligned(64))); + +#define TIDAW_FLAGS_LAST 1 << (7 - 0) +#define TIDAW_FLAGS_SKIP 1 << (7 - 1) +#define TIDAW_FLAGS_DATA_INT 1 << (7 - 2) +#define TIDAW_FLAGS_TTIC 1 << (7 - 3) +#define TIDAW_FLAGS_INSERT_CBC 1 << (7 - 4) + +/** + * struct tidaw - Transport-Indirect-Addressing Word (TIDAW) + * @flags: TIDAW flags. Can be an arithmetic OR of the following constants: + * %TIDAW_FLAGS_LAST, %TIDAW_FLAGS_SKIP, %TIDAW_FLAGS_DATA_INT, + * %TIDAW_FLAGS_TTIC, %TIDAW_FLAGS_INSERT_CBC + * @count: Count + * @addr: Address + */ +struct tidaw { + u32 flags:8; + u32 :24; + u32 count; + u64 addr; +} __attribute__ ((packed, aligned(16))); + +/** + * struct tsa_iostat - I/O-Status Transport-Status Area (IO-Stat TSA) + * @dev_time: Device Time + * @def_time: Defer Time + * @queue_time: Queue Time + * @dev_busy_time: Device-Busy Time + * @dev_act_time: Device-Active-Only Time + * @sense: Sense Data (if present) + */ +struct tsa_iostat { + u32 dev_time; + u32 def_time; + u32 queue_time; + u32 dev_busy_time; + u32 dev_act_time; + u8 sense[32]; +} __attribute__ ((packed)); + +/** + * struct tsa_ddpcs - Device-Detected-Program-Check Transport-Status Area (DDPC TSA) + * @rc: Reason Code + * @rcq: Reason Code Qualifier + * @sense: Sense Data (if present) + */ +struct tsa_ddpc { + u32 :24; + u32 rc:8; + u8 rcq[16]; + u8 sense[32]; +} __attribute__ ((packed)); + +#define TSA_INTRG_FLAGS_CU_STATE_VALID 1 << (7 - 0) +#define TSA_INTRG_FLAGS_DEV_STATE_VALID 1 << (7 - 1) +#define TSA_INTRG_FLAGS_OP_STATE_VALID 1 << (7 - 2) + +/** + * struct tsa_intrg - Interrogate Transport-Status Area (Intrg. TSA) + * @format: Format + * @flags: Flags. Can be an arithmetic OR of the following constants: + * %TSA_INTRG_FLAGS_CU_STATE_VALID, %TSA_INTRG_FLAGS_DEV_STATE_VALID, + * %TSA_INTRG_FLAGS_OP_STATE_VALID + * @cu_state: Controle-Unit State + * @dev_state: Device State + * @op_state: Operation State + * @sd_info: State-Dependent Information + * @dl_id: Device-Level Identifier + * @dd_data: Device-Dependent Data + */ +struct tsa_intrg { + u32 format:8; + u32 flags:8; + u32 cu_state:8; + u32 dev_state:8; + u32 op_state:8; + u32 :24; + u8 sd_info[12]; + u32 dl_id; + u8 dd_data[28]; +} __attribute__ ((packed)); + +#define TSB_FORMAT_NONE 0 +#define TSB_FORMAT_IOSTAT 1 +#define TSB_FORMAT_DDPC 2 +#define TSB_FORMAT_INTRG 3 + +#define TSB_FLAGS_DCW_OFFSET_VALID 1 << (7 - 0) +#define TSB_FLAGS_COUNT_VALID 1 << (7 - 1) +#define TSB_FLAGS_CACHE_MISS 1 << (7 - 2) +#define TSB_FLAGS_TIME_VALID 1 << (7 - 3) +#define TSB_FLAGS_FORMAT(x) ((x) & 7) +#define TSB_FORMAT(t) ((t)->flags & 7) + +/** + * struct tsb - Transport-Status Block (TSB) + * @length: Length + * @flags: Flags. Can be an arithmetic OR of the following constants: + * %TSB_FLAGS_DCW_OFFSET_VALID, %TSB_FLAGS_COUNT_VALID, %TSB_FLAGS_CACHE_MISS, + * %TSB_FLAGS_TIME_VALID + * @dcw_offset: DCW Offset + * @count: Count + * @tsa: Transport-Status-Area + */ +struct tsb { + u32 length:8; + u32 flags:8; + u32 dcw_offset:16; + u32 count; + u32 :32; + union { + struct tsa_iostat iostat; + struct tsa_ddpc ddpc; + struct tsa_intrg intrg; + } __attribute__ ((packed)) tsa; +} __attribute__ ((packed, aligned(8))); + +#define DCW_INTRG_FORMAT_DEFAULT 0 + +#define DCW_INTRG_RC_UNSPECIFIED 0 +#define DCW_INTRG_RC_TIMEOUT 1 + +#define DCW_INTRG_RCQ_UNSPECIFIED 0 +#define DCW_INTRG_RCQ_PRIMARY 1 +#define DCW_INTRG_RCQ_SECONDARY 2 + +#define DCW_INTRG_FLAGS_MPM 1 < (7 - 0) +#define DCW_INTRG_FLAGS_PPR 1 < (7 - 1) +#define DCW_INTRG_FLAGS_CRIT 1 < (7 - 2) + +/** + * struct dcw_intrg_data - Interrogate DCW data + * @format: Format. Should be %DCW_INTRG_FORMAT_DEFAULT + * @rc: Reason Code. Can be one of %DCW_INTRG_RC_UNSPECIFIED, + * %DCW_INTRG_RC_TIMEOUT + * @rcq: Reason Code Qualifier: Can be one of %DCW_INTRG_RCQ_UNSPECIFIED, + * %DCW_INTRG_RCQ_PRIMARY, %DCW_INTRG_RCQ_SECONDARY + * @lpm: Logical-Path Mask + * @pam: Path-Available Mask + * @pim: Path-Installed Mask + * @timeout: Timeout + * @flags: Flags. Can be an arithmetic OR of %DCW_INTRG_FLAGS_MPM, + * %DCW_INTRG_FLAGS_PPR, %DCW_INTRG_FLAGS_CRIT + * @time: Time + * @prog_id: Program Identifier + * @prog_data: Program-Dependent Data + */ +struct dcw_intrg_data { + u32 format:8; + u32 rc:8; + u32 rcq:8; + u32 lpm:8; + u32 pam:8; + u32 pim:8; + u32 timeout:16; + u32 flags:8; + u32 :24; + u32 :32; + u64 time; + u64 prog_id; + u8 prog_data[0]; +} __attribute__ ((packed)); + +#define DCW_FLAGS_CC 1 << (7 - 1) + +#define DCW_CMD_WRITE 0x01 +#define DCW_CMD_READ 0x02 +#define DCW_CMD_CONTROL 0x03 +#define DCW_CMD_SENSE 0x04 +#define DCW_CMD_SENSE_ID 0xe4 +#define DCW_CMD_INTRG 0x40 + +/** + * struct dcw - Device-Command Word (DCW) + * @cmd: Command Code. Can be one of %DCW_CMD_WRITE, %DCW_CMD_READ, + * %DCW_CMD_CONTROL, %DCW_CMD_SENSE, %DCW_CMD_SENSE_ID, %DCW_CMD_INTRG + * @flags: Flags. Can be an arithmetic OR of %DCW_FLAGS_CC + * @cd_count: Control-Data Count + * @count: Count + * @cd: Control Data + */ +struct dcw { + u32 cmd:8; + u32 flags:8; + u32 :8; + u32 cd_count:8; + u32 count; + u8 cd[0]; +} __attribute__ ((packed)); + +#define TCCB_FORMAT_DEFAULT 0x7f +#define TCCB_MAX_DCW 30 +#define TCCB_MAX_SIZE (sizeof(struct tccb_tcah) + \ + TCCB_MAX_DCW * sizeof(struct dcw) + \ + sizeof(struct tccb_tcat)) +#define TCCB_SAC_DEFAULT 0xf901 +#define TCCB_SAC_INTRG 0xf902 + +/** + * struct tccb_tcah - Transport-Command-Area Header (TCAH) + * @format: Format. Should be %TCCB_FORMAT_DEFAULT + * @tcal: Transport-Command-Area Length + * @sac: Service-Action Code. Can be one of %TCCB_SAC_DEFAULT, %TCCB_SAC_INTRG + * @prio: Priority + */ +struct tccb_tcah { + u32 format:8; + u32 :24; + u32 :24; + u32 tcal:8; + u32 sac:16; + u32 :8; + u32 prio:8; + u32 :32; +} __attribute__ ((packed)); + +/** + * struct tccb_tcat - Transport-Command-Area Trailer (TCAT) + * @count: Transport Count + */ +struct tccb_tcat { + u32 :32; + u32 count; +} __attribute__ ((packed)); + +/** + * struct tccb - (partial) Transport-Command-Control Block (TCCB) + * @tcah: TCAH + * @tca: Transport-Command Area + */ +struct tccb { + struct tccb_tcah tcah; + u8 tca[0]; +} __attribute__ ((packed, aligned(8))); + +struct tcw *tcw_get_intrg(struct tcw *tcw); +void *tcw_get_data(struct tcw *tcw); +struct tccb *tcw_get_tccb(struct tcw *tcw); +struct tsb *tcw_get_tsb(struct tcw *tcw); + +void tcw_init(struct tcw *tcw, int r, int w); +void tcw_finalize(struct tcw *tcw, int num_tidaws); + +void tcw_set_intrg(struct tcw *tcw, struct tcw *intrg_tcw); +void tcw_set_data(struct tcw *tcw, void *data, int use_tidal); +void tcw_set_tccb(struct tcw *tcw, struct tccb *tccb); +void tcw_set_tsb(struct tcw *tcw, struct tsb *tsb); + +void tccb_init(struct tccb *tccb, size_t tccb_size, u32 sac); +void tsb_init(struct tsb *tsb); +struct dcw *tccb_add_dcw(struct tccb *tccb, size_t tccb_size, u8 cmd, u8 flags, + void *cd, u8 cd_count, u32 count); +struct tidaw *tcw_add_tidaw(struct tcw *tcw, int num_tidaws, u8 flags, + void *addr, u32 count); + +#endif /* _ASM_S390_FCX_H */ diff --git a/include/asm-s390/isc.h b/include/asm-s390/isc.h new file mode 100644 index 000000000000..fe56f7b445ea --- /dev/null +++ b/include/asm-s390/isc.h @@ -0,0 +1,24 @@ +#ifndef _ASM_S390_ISC_H +#define _ASM_S390_ISC_H + +#include <linux/types.h> + +/* + * I/O interruption subclasses used by drivers. + * Please add all used iscs here so that it is possible to distribute + * isc usage between drivers. + * Reminder: 0 is highest priority, 7 lowest. + */ +#define MAX_ISC 7 + +/* Regular I/O interrupts. */ +#define IO_SCH_ISC 3 /* regular I/O subchannels */ +#define CONSOLE_ISC 1 /* console I/O subchannel */ +/* Adapter interrupts. */ +#define QDIO_AIRQ_ISC IO_SCH_ISC /* I/O subchannel in qdio mode */ + +/* Functions for registration of I/O interruption subclasses */ +void isc_register(unsigned int isc); +void isc_unregister(unsigned int isc); + +#endif /* _ASM_S390_ISC_H */ diff --git a/include/asm-s390/itcw.h b/include/asm-s390/itcw.h new file mode 100644 index 000000000000..a9bc5c36b32a --- /dev/null +++ b/include/asm-s390/itcw.h @@ -0,0 +1,30 @@ +/* + * Functions for incremental construction of fcx enabled I/O control blocks. + * + * Copyright IBM Corp. 2008 + * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com> + */ + +#ifndef _ASM_S390_ITCW_H +#define _ASM_S390_ITCW_H _ASM_S390_ITCW_H + +#include <linux/types.h> +#include <asm/fcx.h> + +#define ITCW_OP_READ 0 +#define ITCW_OP_WRITE 1 + +struct itcw; + +struct tcw *itcw_get_tcw(struct itcw *itcw); +size_t itcw_calc_size(int intrg, int max_tidaws, int intrg_max_tidaws); +struct itcw *itcw_init(void *buffer, size_t size, int op, int intrg, + int max_tidaws, int intrg_max_tidaws); +struct dcw *itcw_add_dcw(struct itcw *itcw, u8 cmd, u8 flags, void *cd, + u8 cd_count, u32 count); +struct tidaw *itcw_add_tidaw(struct itcw *itcw, u8 flags, void *addr, + u32 count); +void itcw_set_data(struct itcw *itcw, void *addr, int use_tidal); +void itcw_finalize(struct itcw *itcw); + +#endif /* _ASM_S390_ITCW_H */ diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h index a00f79dd323b..4af80af2a88f 100644 --- a/include/asm-s390/processor.h +++ b/include/asm-s390/processor.h @@ -143,11 +143,19 @@ struct stack_frame { /* * Do necessary setup to start up a new thread. */ -#define start_thread(regs, new_psw, new_stackp) do { \ +#define start_thread(regs, new_psw, new_stackp) do { \ set_fs(USER_DS); \ regs->psw.mask = psw_user_bits; \ - regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ - regs->gprs[15] = new_stackp ; \ + regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ + regs->gprs[15] = new_stackp; \ +} while (0) + +#define start_thread31(regs, new_psw, new_stackp) do { \ + set_fs(USER_DS); \ + regs->psw.mask = psw_user32_bits; \ + regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ + regs->gprs[15] = new_stackp; \ + crst_table_downgrade(current->mm, 1UL << 31); \ } while (0) /* Forward declaration, a strange C thing */ @@ -328,16 +336,6 @@ extern void (*s390_base_mcck_handler_fn)(void); extern void (*s390_base_pgm_handler_fn)(void); extern void (*s390_base_ext_handler_fn)(void); -/* - * CPU idle notifier chain. - */ -#define S390_CPU_IDLE 0 -#define S390_CPU_NOT_IDLE 1 - -struct notifier_block; -int register_idle_notifier(struct notifier_block *nb); -int unregister_idle_notifier(struct notifier_block *nb); - #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL #endif diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h index d7d4e2eb3e6f..af2c9ac28a07 100644 --- a/include/asm-s390/ptrace.h +++ b/include/asm-s390/ptrace.h @@ -215,6 +215,12 @@ typedef struct unsigned long addr; } __attribute__ ((aligned(8))) psw_t; +typedef struct +{ + __u32 mask; + __u32 addr; +} __attribute__ ((aligned(8))) psw_compat_t; + #ifndef __s390x__ #define PSW_MASK_PER 0x40000000UL @@ -292,6 +298,15 @@ typedef struct unsigned long orig_gpr2; } s390_regs; +typedef struct +{ + psw_compat_t psw; + __u32 gprs[NUM_GPRS]; + __u32 acrs[NUM_ACRS]; + __u32 orig_gpr2; +} s390_compat_regs; + + #ifdef __KERNEL__ #include <asm/setup.h> #include <asm/page.h> diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h index e0d4500d5f95..819e7d99ca0c 100644 --- a/include/asm-s390/system.h +++ b/include/asm-s390/system.h @@ -315,14 +315,14 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) asm volatile( \ " lctlg %1,%2,0(%0)\n" \ : : "a" (&array), "i" (low), "i" (high), \ - "m" (*(addrtype *)(array))); \ + "m" (*(addrtype *)(&array))); \ }) #define __ctl_store(array, low, high) ({ \ typedef struct { char _[sizeof(array)]; } addrtype; \ asm volatile( \ " stctg %2,%3,0(%1)\n" \ - : "=m" (*(addrtype *)(array)) \ + : "=m" (*(addrtype *)(&array)) \ : "a" (&array), "i" (low), "i" (high)); \ }) @@ -333,14 +333,14 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) asm volatile( \ " lctl %1,%2,0(%0)\n" \ : : "a" (&array), "i" (low), "i" (high), \ - "m" (*(addrtype *)(array))); \ + "m" (*(addrtype *)(&array))); \ }) #define __ctl_store(array, low, high) ({ \ typedef struct { char _[sizeof(array)]; } addrtype; \ asm volatile( \ " stctl %2,%3,0(%1)\n" \ - : "=m" (*(addrtype *)(array)) \ + : "=m" (*(addrtype *)(&array)) \ : "a" (&array), "i" (low), "i" (high)); \ }) diff --git a/include/asm-s390/timer.h b/include/asm-s390/timer.h index adb34860a543..d98d79e35cd6 100644 --- a/include/asm-s390/timer.h +++ b/include/asm-s390/timer.h @@ -48,6 +48,18 @@ extern int del_virt_timer(struct vtimer_list *timer); extern void init_cpu_vtimer(void); extern void vtime_init(void); +#ifdef CONFIG_VIRT_TIMER + +extern void vtime_start_cpu_timer(void); +extern void vtime_stop_cpu_timer(void); + +#else + +static inline void vtime_start_cpu_timer(void) { } +static inline void vtime_stop_cpu_timer(void) { } + +#endif /* CONFIG_VIRT_TIMER */ + #endif /* __KERNEL__ */ #endif /* _ASM_S390_TIMER_H */ diff --git a/include/asm-sh/checksum_32.h b/include/asm-sh/checksum_32.h index 4bc8357e8892..14b7ac2f0a07 100644 --- a/include/asm-sh/checksum_32.h +++ b/include/asm-sh/checksum_32.h @@ -109,7 +109,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) will assume they contain their original values. */ : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1) : "1" (iph), "2" (ihl) - : "t"); + : "t", "memory"); return csum_fold(sum); } diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h index 05092da1aa59..f01449a8d378 100644 --- a/include/asm-sh/elf.h +++ b/include/asm-sh/elf.h @@ -1,10 +1,15 @@ #ifndef __ASM_SH_ELF_H #define __ASM_SH_ELF_H +#include <linux/utsname.h> #include <asm/auxvec.h> #include <asm/ptrace.h> #include <asm/user.h> +/* ELF header e_flags defines */ +#define EF_SH_PIC 0x100 /* -fpic */ +#define EF_SH_FDPIC 0x8000 /* -mfdpic */ + /* SH (particularly SHcompact) relocation types */ #define R_SH_NONE 0 #define R_SH_DIR32 1 @@ -43,6 +48,28 @@ #define R_SH_RELATIVE 165 #define R_SH_GOTOFF 166 #define R_SH_GOTPC 167 + +/* FDPIC relocs */ +#define R_SH_GOT20 70 +#define R_SH_GOTOFF20 71 +#define R_SH_GOTFUNCDESC 72 +#define R_SH_GOTFUNCDESC20 73 +#define R_SH_GOTOFFFUNCDESC 74 +#define R_SH_GOTOFFFUNCDESC20 75 +#define R_SH_FUNCDESC 76 +#define R_SH_FUNCDESC_VALUE 77 + +#if 0 /* XXX - later .. */ +#define R_SH_GOT20 198 +#define R_SH_GOTOFF20 199 +#define R_SH_GOTFUNCDESC 200 +#define R_SH_GOTFUNCDESC20 201 +#define R_SH_GOTOFFFUNCDESC 202 +#define R_SH_GOTOFFFUNCDESC20 203 +#define R_SH_FUNCDESC 204 +#define R_SH_FUNCDESC_VALUE 205 +#endif + /* SHmedia relocs */ #define R_SH_IMM_LOW16 246 #define R_SH_IMM_LOW16_PCREL 247 @@ -77,9 +104,12 @@ typedef struct user_fpu_struct elf_fpregset_t; /* * This is used to ensure we don't load something for the wrong architecture. */ -#define elf_check_arch(x) ( (x)->e_machine == EM_SH ) +#define elf_check_arch(x) ((x)->e_machine == EM_SH) +#define elf_check_fdpic(x) ((x)->e_flags & EF_SH_FDPIC) +#define elf_check_const_displacement(x) ((x)->e_flags & EF_SH_PIC) #define USE_ELF_CORE_DUMP +#define ELF_FDPIC_CORE_EFLAGS EF_SH_FDPIC #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This is the location that an ET_DYN program is loaded if exec'ed. Typical @@ -136,6 +166,27 @@ typedef struct user_fpu_struct elf_fpregset_t; _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \ _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \ _r->sr = SR_FD; } while (0) + +#define ELF_FDPIC_PLAT_INIT(_r, _exec_map_addr, _interp_map_addr, \ + _dynamic_addr) \ +do { \ + _r->regs[0] = 0; \ + _r->regs[1] = 0; \ + _r->regs[2] = 0; \ + _r->regs[3] = 0; \ + _r->regs[4] = 0; \ + _r->regs[5] = 0; \ + _r->regs[6] = 0; \ + _r->regs[7] = 0; \ + _r->regs[8] = _exec_map_addr; \ + _r->regs[9] = _interp_map_addr; \ + _r->regs[10] = _dynamic_addr; \ + _r->regs[11] = 0; \ + _r->regs[12] = 0; \ + _r->regs[13] = 0; \ + _r->regs[14] = 0; \ + _r->sr = SR_FD; \ +} while (0) #endif #define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT) diff --git a/include/asm-sh/mmu.h b/include/asm-sh/mmu.h index eb0358c097d0..fdcb93bc6d11 100644 --- a/include/asm-sh/mmu.h +++ b/include/asm-sh/mmu.h @@ -12,6 +12,10 @@ typedef struct { struct vm_list_struct *vmlist; unsigned long end_brk; #endif +#ifdef CONFIG_BINFMT_ELF_FDPIC + unsigned long exec_fdpic_loadmap; + unsigned long interp_fdpic_loadmap; +#endif } mm_context_t; /* diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h index 304c30b5d947..3b305ca9a00f 100644 --- a/include/asm-sh/page.h +++ b/include/asm-sh/page.h @@ -12,6 +12,8 @@ # define PAGE_SHIFT 12 #elif defined(CONFIG_PAGE_SIZE_8KB) # define PAGE_SHIFT 13 +#elif defined(CONFIG_PAGE_SIZE_16KB) +# define PAGE_SHIFT 14 #elif defined(CONFIG_PAGE_SIZE_64KB) # define PAGE_SHIFT 16 #else diff --git a/include/asm-sh/pgtable_32.h b/include/asm-sh/pgtable_32.h index cbc731d35c25..72ea209195bd 100644 --- a/include/asm-sh/pgtable_32.h +++ b/include/asm-sh/pgtable_32.h @@ -102,7 +102,9 @@ #define _PAGE_FLAGS_HARDWARE_MASK (PHYS_ADDR_MASK & ~(_PAGE_CLEAR_FLAGS)) /* Hardware flags, page size encoding */ -#if defined(CONFIG_X2TLB) +#if !defined(CONFIG_MMU) +# define _PAGE_FLAGS_HARD 0ULL +#elif defined(CONFIG_X2TLB) # if defined(CONFIG_PAGE_SIZE_4KB) # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0) # elif defined(CONFIG_PAGE_SIZE_8KB) diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index b7c7ce80f03e..15d9f92ca383 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -2,6 +2,7 @@ #define __ASM_SH_PROCESSOR_H #include <asm/cpu-features.h> +#include <asm/segment.h> #ifndef __ASSEMBLY__ /* diff --git a/include/asm-sh/processor_32.h b/include/asm-sh/processor_32.h index c09305d6a9d9..81628f144faf 100644 --- a/include/asm-sh/processor_32.h +++ b/include/asm-sh/processor_32.h @@ -113,10 +113,6 @@ struct thread_struct { union sh_fpu_union fpu; }; -typedef struct { - unsigned long seg; -} mm_segment_t; - /* Count of active tasks with UBC settings */ extern int ubc_usercnt; diff --git a/include/asm-sh/processor_64.h b/include/asm-sh/processor_64.h index 88a2edf8fa5d..fc7fc685ba27 100644 --- a/include/asm-sh/processor_64.h +++ b/include/asm-sh/processor_64.h @@ -166,10 +166,6 @@ struct thread_struct { union sh_fpu_union fpu; }; -typedef struct { - unsigned long seg; -} mm_segment_t; - #define INIT_MMAP \ { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h index 8d6c92b3e770..a9f0c3f67f4a 100644 --- a/include/asm-sh/ptrace.h +++ b/include/asm-sh/ptrace.h @@ -87,6 +87,11 @@ struct pt_dspregs { unsigned long mod; }; +#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ + +#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ +#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ + #define PTRACE_GETDSPREGS 55 #define PTRACE_SETDSPREGS 56 #endif diff --git a/include/asm-sh/segment.h b/include/asm-sh/segment.h index e417eab4c7d7..5e2725f4ac49 100644 --- a/include/asm-sh/segment.h +++ b/include/asm-sh/segment.h @@ -1,6 +1,34 @@ #ifndef __ASM_SH_SEGMENT_H #define __ASM_SH_SEGMENT_H -/* Only here because we have some old header files that expect it.. */ +#ifndef __ASSEMBLY__ +typedef struct { + unsigned long seg; +} mm_segment_t; + +#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) + +/* + * The fs value determines whether argument validity checking should be + * performed or not. If get_fs() == USER_DS, checking is performed, with + * get_fs() == KERNEL_DS, checking is bypassed. + * + * For historical reasons, these macros are grossly misnamed. + */ +#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFFUL) +#ifdef CONFIG_MMU +#define USER_DS MAKE_MM_SEG(PAGE_OFFSET) +#else +#define USER_DS KERNEL_DS +#endif + +#define segment_eq(a,b) ((a).seg == (b).seg) + +#define get_ds() (KERNEL_DS) + +#define get_fs() (current_thread_info()->addr_limit) +#define set_fs(x) (current_thread_info()->addr_limit = (x)) + +#endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_SEGMENT_H */ diff --git a/include/asm-sh/sh7763rdp.h b/include/asm-sh/sh7763rdp.h new file mode 100644 index 000000000000..8750cc852977 --- /dev/null +++ b/include/asm-sh/sh7763rdp.h @@ -0,0 +1,54 @@ +#ifndef __ASM_SH_SH7763RDP_H +#define __ASM_SH_SH7763RDP_H + +/* + * linux/include/asm-sh/sh7763drp.h + * + * Copyright (C) 2008 Renesas Solutions + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include <asm/addrspace.h> + +/* clock control */ +#define MSTPCR1 0xFFC80038 + +/* PORT */ +#define PORT_PSEL0 0xFFEF0070 +#define PORT_PSEL1 0xFFEF0072 +#define PORT_PSEL2 0xFFEF0074 +#define PORT_PSEL3 0xFFEF0076 +#define PORT_PSEL4 0xFFEF0078 + +#define PORT_PACR 0xFFEF0000 +#define PORT_PCCR 0xFFEF0004 +#define PORT_PFCR 0xFFEF000A +#define PORT_PGCR 0xFFEF000C +#define PORT_PHCR 0xFFEF000E +#define PORT_PICR 0xFFEF0010 +#define PORT_PJCR 0xFFEF0012 +#define PORT_PKCR 0xFFEF0014 +#define PORT_PLCR 0xFFEF0016 +#define PORT_PMCR 0xFFEF0018 +#define PORT_PNCR 0xFFEF001A + +/* FPGA */ +#define CPLD_BOARD_ID_ERV_REG 0xB1000000 +#define CPLD_CPLD_CMD_REG 0xB1000006 + +/* + * USB SH7763RDP board can use Host only. + */ +#define USB_USBHSC 0xFFEC80f0 + +/* arch/sh/boards/renesas/sh7763rdp/irq.c */ +void init_sh7763rdp_IRQ(void); +int sh7763rdp_irq_demux(int irq); +#define __IO_PREFIX sh7763rdp +#include <asm/io_generic.h> + +#endif /* __ASM_SH_SH7763RDP_H */ diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h index c50e5d35fe84..0f69b4899309 100644 --- a/include/asm-sh/thread_info.h +++ b/include/asm-sh/thread_info.h @@ -38,6 +38,8 @@ struct thread_info { #define THREAD_SIZE_ORDER (1) #elif defined(CONFIG_PAGE_SIZE_8KB) #define THREAD_SIZE_ORDER (1) +#elif defined(CONFIG_PAGE_SIZE_16KB) +#define THREAD_SIZE_ORDER (0) #elif defined(CONFIG_PAGE_SIZE_64KB) #define THREAD_SIZE_ORDER (0) #else diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h index b3440c305b5d..45c2c9b2993d 100644 --- a/include/asm-sh/uaccess.h +++ b/include/asm-sh/uaccess.h @@ -1,12 +1,171 @@ #ifndef __ASM_SH_UACCESS_H #define __ASM_SH_UACCESS_H +#include <linux/errno.h> +#include <linux/sched.h> +#include <asm/segment.h> + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +#define __addr_ok(addr) \ + ((unsigned long __force)(addr) < current_thread_info()->addr_limit.seg) + +/* + * __access_ok: Check if address with size is OK or not. + * + * Uhhuh, this needs 33-bit arithmetic. We have a carry.. + * + * sum := addr + size; carry? --> flag = true; + * if (sum >= addr_limit) flag = true; + */ +#define __access_ok(addr, size) \ + (__addr_ok((addr) + (size))) +#define access_ok(type, addr, size) \ + (__chk_user_ptr(addr), \ + __access_ok((unsigned long __force)(addr), (size))) + +/* + * Uh, these should become the main single-value transfer routines ... + * They automatically use the right size if we just have the right + * pointer type ... + * + * As SuperH uses the same address space for kernel and user data, we + * can just do these as direct assignments. + * + * Careful to not + * (a) re-use the arguments for side effects (sizeof is ok) + * (b) require any knowledge of processes at this stage + */ +#define put_user(x,ptr) __put_user_check((x), (ptr), sizeof(*(ptr))) +#define get_user(x,ptr) __get_user_check((x), (ptr), sizeof(*(ptr))) + +/* + * The "__xxx" versions do not do address space checking, useful when + * doing multiple accesses to the same area (the user has to do the + * checks by hand with "access_ok()") + */ +#define __put_user(x,ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr))) +#define __get_user(x,ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr))) + +struct __large_struct { unsigned long buf[100]; }; +#define __m(x) (*(struct __large_struct __user *)(x)) + +#define __get_user_nocheck(x,ptr,size) \ +({ \ + long __gu_err; \ + unsigned long __gu_val; \ + const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \ + __chk_user_ptr(ptr); \ + __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ + (x) = (__typeof__(*(ptr)))__gu_val; \ + __gu_err; \ +}) + +#define __get_user_check(x,ptr,size) \ +({ \ + long __gu_err = -EFAULT; \ + unsigned long __gu_val = 0; \ + const __typeof__(*(ptr)) *__gu_addr = (ptr); \ + if (likely(access_ok(VERIFY_READ, __gu_addr, (size)))) \ + __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ + (x) = (__typeof__(*(ptr)))__gu_val; \ + __gu_err; \ +}) + +#define __put_user_nocheck(x,ptr,size) \ +({ \ + long __pu_err; \ + __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ + __chk_user_ptr(ptr); \ + __put_user_size((x), __pu_addr, (size), __pu_err); \ + __pu_err; \ +}) + +#define __put_user_check(x,ptr,size) \ +({ \ + long __pu_err = -EFAULT; \ + __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ + if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) \ + __put_user_size((x), __pu_addr, (size), \ + __pu_err); \ + __pu_err; \ +}) + #ifdef CONFIG_SUPERH32 # include "uaccess_32.h" #else # include "uaccess_64.h" #endif +/* Generic arbitrary sized copy. */ +/* Return the number of bytes NOT copied */ +__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n); + +static __always_inline unsigned long +__copy_from_user(void *to, const void __user *from, unsigned long n) +{ + return __copy_user(to, (__force void *)from, n); +} + +static __always_inline unsigned long __must_check +__copy_to_user(void __user *to, const void *from, unsigned long n) +{ + return __copy_user((__force void *)to, from, n); +} + +#define __copy_to_user_inatomic __copy_to_user +#define __copy_from_user_inatomic __copy_from_user + +/* + * Clear the area and return remaining number of bytes + * (on failure. Usually it's 0.) + */ +__kernel_size_t __clear_user(void *addr, __kernel_size_t size); + +#define clear_user(addr,n) \ +({ \ + void __user * __cl_addr = (addr); \ + unsigned long __cl_size = (n); \ + \ + if (__cl_size && access_ok(VERIFY_WRITE, \ + ((unsigned long)(__cl_addr)), __cl_size)) \ + __cl_size = __clear_user(__cl_addr, __cl_size); \ + \ + __cl_size; \ +}) + +/** + * strncpy_from_user: - Copy a NUL terminated string from userspace. + * @dst: Destination address, in kernel space. This buffer must be at + * least @count bytes long. + * @src: Source address, in user space. + * @count: Maximum number of bytes to copy, including the trailing NUL. + * + * Copies a NUL-terminated string from userspace to kernel space. + * + * On success, returns the length of the string (not including the trailing + * NUL). + * + * If access to userspace fails, returns -EFAULT (some data may have been + * copied). + * + * If @count is smaller than the length of the string, copies @count bytes + * and returns @count. + */ +#define strncpy_from_user(dest,src,count) \ +({ \ + unsigned long __sfu_src = (unsigned long)(src); \ + int __sfu_count = (int)(count); \ + long __sfu_res = -EFAULT; \ + \ + if (__access_ok(__sfu_src, __sfu_count)) \ + __sfu_res = __strncpy_from_user((unsigned long)(dest), \ + __sfu_src, __sfu_count); \ + \ + __sfu_res; \ +}) + static inline unsigned long copy_from_user(void *to, const void __user *from, unsigned long n) { @@ -31,4 +190,67 @@ copy_to_user(void __user *to, const void *from, unsigned long n) return __copy_size; } +/** + * strnlen_user: - Get the size of a string in user space. + * @s: The string to measure. + * @n: The maximum valid length + * + * Context: User context only. This function may sleep. + * + * Get the size of a NUL-terminated string in user space. + * + * Returns the size of the string INCLUDING the terminating NUL. + * On exception, returns 0. + * If the string is too long, returns a value greater than @n. + */ +static inline long strnlen_user(const char __user *s, long n) +{ + if (!__addr_ok(s)) + return 0; + else + return __strnlen_user(s, n); +} + +/** + * strlen_user: - Get the size of a string in user space. + * @str: The string to measure. + * + * Context: User context only. This function may sleep. + * + * Get the size of a NUL-terminated string in user space. + * + * Returns the size of the string INCLUDING the terminating NUL. + * On exception, returns 0. + * + * If there is a limit on the length of a valid string, you may wish to + * consider using strnlen_user() instead. + */ +#define strlen_user(str) strnlen_user(str, ~0UL >> 1) + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ +struct exception_table_entry { + unsigned long insn, fixup; +}; + +#if defined(CONFIG_SUPERH64) && defined(CONFIG_MMU) +#define ARCH_HAS_SEARCH_EXTABLE +#endif + +int fixup_exception(struct pt_regs *regs); +/* Returns 0 if exception not found and fixup.unit otherwise. */ +unsigned long search_exception_table(unsigned long addr); +const struct exception_table_entry *search_exception_tables(unsigned long addr); + + #endif /* __ASM_SH_UACCESS_H */ diff --git a/include/asm-sh/uaccess_32.h b/include/asm-sh/uaccess_32.h index 1e41fda74bd3..ae0d24f6653f 100644 --- a/include/asm-sh/uaccess_32.h +++ b/include/asm-sh/uaccess_32.h @@ -1,9 +1,8 @@ -/* $Id: uaccess.h,v 1.11 2003/10/13 07:21:20 lethal Exp $ - * +/* * User space memory access functions * * Copyright (C) 1999, 2002 Niibe Yutaka - * Copyright (C) 2003 Paul Mundt + * Copyright (C) 2003 - 2008 Paul Mundt * * Based on: * MIPS implementation version 1.15 by @@ -13,115 +12,6 @@ #ifndef __ASM_SH_UACCESS_32_H #define __ASM_SH_UACCESS_32_H -#include <linux/errno.h> -#include <linux/sched.h> - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons (Data Segment Register?), these macros are misnamed. - */ - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFFUL) -#define USER_DS MAKE_MM_SEG(PAGE_OFFSET) - -#define segment_eq(a,b) ((a).seg == (b).seg) - -#define get_ds() (KERNEL_DS) - -#if !defined(CONFIG_MMU) -/* NOMMU is always true */ -#define __addr_ok(addr) (1) - -static inline mm_segment_t get_fs(void) -{ - return USER_DS; -} - -static inline void set_fs(mm_segment_t s) -{ -} - -/* - * __access_ok: Check if address with size is OK or not. - * - * If we don't have an MMU (or if its disabled) the only thing we really have - * to look out for is if the address resides somewhere outside of what - * available RAM we have. - */ -static inline int __access_ok(unsigned long addr, unsigned long size) -{ - return 1; -} -#else /* CONFIG_MMU */ -#define __addr_ok(addr) \ - ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg)) - -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -/* - * __access_ok: Check if address with size is OK or not. - * - * Uhhuh, this needs 33-bit arithmetic. We have a carry.. - * - * sum := addr + size; carry? --> flag = true; - * if (sum >= addr_limit) flag = true; - */ -static inline int __access_ok(unsigned long addr, unsigned long size) -{ - unsigned long flag, sum; - - __asm__("clrt\n\t" - "addc %3, %1\n\t" - "movt %0\n\t" - "cmp/hi %4, %1\n\t" - "rotcl %0" - :"=&r" (flag), "=r" (sum) - :"1" (addr), "r" (size), - "r" (current_thread_info()->addr_limit.seg) - :"t"); - return flag == 0; -} -#endif /* CONFIG_MMU */ - -#define access_ok(type, addr, size) \ - (__chk_user_ptr(addr), \ - __access_ok((unsigned long __force)(addr), (size))) - -/* - * Uh, these should become the main single-value transfer routines ... - * They automatically use the right size if we just have the right - * pointer type ... - * - * As SuperH uses the same address space for kernel and user data, we - * can just do these as direct assignments. - * - * Careful to not - * (a) re-use the arguments for side effects (sizeof is ok) - * (b) require any knowledge of processes at this stage - */ -#define put_user(x,ptr) __put_user_check((x), (ptr), sizeof(*(ptr))) -#define get_user(x,ptr) __get_user_check((x), (ptr), sizeof(*(ptr))) - -/* - * The "__xxx" versions do not do address space checking, useful when - * doing multiple accesses to the same area (the user has to do the - * checks by hand with "access_ok()") - */ -#define __put_user(x,ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr))) -#define __get_user(x,ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr))) - -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct __user *)(x)) - #define __get_user_size(x,ptr,size,retval) \ do { \ retval = 0; \ @@ -141,28 +31,7 @@ do { \ } \ } while (0) -#define __get_user_nocheck(x,ptr,size) \ -({ \ - long __gu_err; \ - unsigned long __gu_val; \ - const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \ - __chk_user_ptr(ptr); \ - __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ - (x) = (__typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - -#define __get_user_check(x,ptr,size) \ -({ \ - long __gu_err = -EFAULT; \ - unsigned long __gu_val = 0; \ - const __typeof__(*(ptr)) *__gu_addr = (ptr); \ - if (likely(access_ok(VERIFY_READ, __gu_addr, (size)))) \ - __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ - (x) = (__typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - +#ifdef CONFIG_MMU #define __get_user_asm(x, addr, err, insn) \ ({ \ __asm__ __volatile__( \ @@ -183,6 +52,16 @@ __asm__ __volatile__( \ ".previous" \ :"=&r" (err), "=&r" (x) \ :"m" (__m(addr)), "i" (-EFAULT), "0" (err)); }) +#else +#define __get_user_asm(x, addr, err, insn) \ +do { \ + __asm__ __volatile__ ( \ + "mov." insn " %1, %0\n\t" \ + : "=&r" (x) \ + : "m" (__m(addr)) \ + ); \ +} while (0) +#endif /* CONFIG_MMU */ extern void __get_user_unknown(void); @@ -207,45 +86,41 @@ do { \ } \ } while (0) -#define __put_user_nocheck(x,ptr,size) \ -({ \ - long __pu_err; \ - __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ - __chk_user_ptr(ptr); \ - __put_user_size((x), __pu_addr, (size), __pu_err); \ - __pu_err; \ -}) - -#define __put_user_check(x,ptr,size) \ -({ \ - long __pu_err = -EFAULT; \ - __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ - if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) \ - __put_user_size((x), __pu_addr, (size), \ - __pu_err); \ - __pu_err; \ -}) - -#define __put_user_asm(x, addr, err, insn) \ -({ \ -__asm__ __volatile__( \ - "1:\n\t" \ - "mov." insn " %1, %2\n\t" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3:\n\t" \ - "mov.l 4f, %0\n\t" \ - "jmp @%0\n\t" \ - " mov %3, %0\n\t" \ - ".balign 4\n" \ - "4: .long 2b\n\t" \ - ".previous\n" \ - ".section __ex_table,\"a\"\n\t" \ - ".long 1b, 3b\n\t" \ - ".previous" \ - :"=&r" (err) \ - :"r" (x), "m" (__m(addr)), "i" (-EFAULT), "0" (err) \ - :"memory"); }) +#ifdef CONFIG_MMU +#define __put_user_asm(x, addr, err, insn) \ +do { \ + __asm__ __volatile__ ( \ + "1:\n\t" \ + "mov." insn " %1, %2\n\t" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3:\n\t" \ + "mov.l 4f, %0\n\t" \ + "jmp @%0\n\t" \ + " mov %3, %0\n\t" \ + ".balign 4\n" \ + "4: .long 2b\n\t" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n\t" \ + ".long 1b, 3b\n\t" \ + ".previous" \ + : "=&r" (err) \ + : "r" (x), "m" (__m(addr)), "i" (-EFAULT), \ + "0" (err) \ + : "memory" \ + ); \ +} while (0) +#else +#define __put_user_asm(x, addr, err, insn) \ +do { \ + __asm__ __volatile__ ( \ + "mov." insn " %0, %1\n\t" \ + : /* no outputs */ \ + : "r" (x), "m" (__m(addr)) \ + : "memory" \ + ); \ +} while (0) +#endif /* CONFIG_MMU */ #if defined(CONFIG_CPU_LITTLE_ENDIAN) #define __put_user_u64(val,addr,retval) \ @@ -295,40 +170,7 @@ __asm__ __volatile__( \ extern void __put_user_unknown(void); -/* Generic arbitrary sized copy. */ -/* Return the number of bytes NOT copied */ -__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n); - - -static __always_inline unsigned long -__copy_from_user(void *to, const void __user *from, unsigned long n) -{ - return __copy_user(to, (__force void *)from, n); -} - -static __always_inline unsigned long __must_check -__copy_to_user(void __user *to, const void *from, unsigned long n) -{ - return __copy_user((__force void *)to, from, n); -} - -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user - -/* - * Clear the area and return remaining number of bytes - * (on failure. Usually it's 0.) - */ -extern __kernel_size_t __clear_user(void *addr, __kernel_size_t size); - -#define clear_user(addr,n) ({ \ -void * __cl_addr = (addr); \ -unsigned long __cl_size = (n); \ -if (__cl_size && __access_ok(((unsigned long)(__cl_addr)), __cl_size)) \ -__cl_size = __clear_user(__cl_addr, __cl_size); \ -__cl_size; }) - -static __inline__ int +static inline int __strncpy_from_user(unsigned long __dest, unsigned long __user __src, int __count) { __kernel_size_t res; @@ -367,37 +209,11 @@ __strncpy_from_user(unsigned long __dest, unsigned long __user __src, int __coun return res; } -/** - * strncpy_from_user: - Copy a NUL terminated string from userspace. - * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. - * @src: Source address, in user space. - * @count: Maximum number of bytes to copy, including the trailing NUL. - * - * Copies a NUL-terminated string from userspace to kernel space. - * - * On success, returns the length of the string (not including the trailing - * NUL). - * - * If access to userspace fails, returns -EFAULT (some data may have been - * copied). - * - * If @count is smaller than the length of the string, copies @count bytes - * and returns @count. - */ -#define strncpy_from_user(dest,src,count) ({ \ -unsigned long __sfu_src = (unsigned long) (src); \ -int __sfu_count = (int) (count); \ -long __sfu_res = -EFAULT; \ -if(__access_ok(__sfu_src, __sfu_count)) { \ -__sfu_res = __strncpy_from_user((unsigned long) (dest), __sfu_src, __sfu_count); \ -} __sfu_res; }) - /* * Return the size of a string (including the ending 0 even when we have * exceeded the maximum string length). */ -static __inline__ long __strnlen_user(const char __user *__s, long __n) +static inline long __strnlen_user(const char __user *__s, long __n) { unsigned long res; unsigned long __dummy; @@ -429,61 +245,4 @@ static __inline__ long __strnlen_user(const char __user *__s, long __n) return res; } -/** - * strnlen_user: - Get the size of a string in user space. - * @s: The string to measure. - * @n: The maximum valid length - * - * Context: User context only. This function may sleep. - * - * Get the size of a NUL-terminated string in user space. - * - * Returns the size of the string INCLUDING the terminating NUL. - * On exception, returns 0. - * If the string is too long, returns a value greater than @n. - */ -static __inline__ long strnlen_user(const char __user *s, long n) -{ - if (!__addr_ok(s)) - return 0; - else - return __strnlen_user(s, n); -} - -/** - * strlen_user: - Get the size of a string in user space. - * @str: The string to measure. - * - * Context: User context only. This function may sleep. - * - * Get the size of a NUL-terminated string in user space. - * - * Returns the size of the string INCLUDING the terminating NUL. - * On exception, returns 0. - * - * If there is a limit on the length of a valid string, you may wish to - * consider using strnlen_user() instead. - */ -#define strlen_user(str) strnlen_user(str, ~0UL >> 1) - -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - */ - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -extern int fixup_exception(struct pt_regs *regs); - #endif /* __ASM_SH_UACCESS_32_H */ diff --git a/include/asm-sh/uaccess_64.h b/include/asm-sh/uaccess_64.h index a9b68d094844..81b3d515fcb3 100644 --- a/include/asm-sh/uaccess_64.h +++ b/include/asm-sh/uaccess_64.h @@ -20,87 +20,6 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#include <linux/errno.h> -#include <linux/sched.h> - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons (Data Segment Register?), these macros are misnamed. - */ - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) -#define USER_DS MAKE_MM_SEG(0x80000000) - -#define get_ds() (KERNEL_DS) -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit=(x)) - -#define segment_eq(a,b) ((a).seg == (b).seg) - -#define __addr_ok(addr) ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg)) - -/* - * Uhhuh, this needs 33-bit arithmetic. We have a carry.. - * - * sum := addr + size; carry? --> flag = true; - * if (sum >= addr_limit) flag = true; - */ -#define __range_ok(addr,size) (((unsigned long) (addr) + (size) < (current_thread_info()->addr_limit.seg)) ? 0 : 1) - -#define access_ok(type,addr,size) (__range_ok(addr,size) == 0) -#define __access_ok(addr,size) (__range_ok(addr,size) == 0) - -/* - * Uh, these should become the main single-value transfer routines ... - * They automatically use the right size if we just have the right - * pointer type ... - * - * As MIPS uses the same address space for kernel and user data, we - * can just do these as direct assignments. - * - * Careful to not - * (a) re-use the arguments for side effects (sizeof is ok) - * (b) require any knowledge of processes at this stage - */ -#define put_user(x,ptr) __put_user_check((x),(ptr),sizeof(*(ptr))) -#define get_user(x,ptr) __get_user_check((x),(ptr),sizeof(*(ptr))) - -/* - * The "__xxx" versions do not do address space checking, useful when - * doing multiple accesses to the same area (the user has to do the - * checks by hand with "access_ok()") - */ -#define __put_user(x,ptr) __put_user_nocheck((x),(ptr),sizeof(*(ptr))) -#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr))) - -/* - * The "xxx_ret" versions return constant specified in third argument, if - * something bad happens. These macros can be optimized for the - * case of just returning from the function xxx_ret is used. - */ - -#define put_user_ret(x,ptr,ret) ({ \ -if (put_user(x,ptr)) return ret; }) - -#define get_user_ret(x,ptr,ret) ({ \ -if (get_user(x,ptr)) return ret; }) - -#define __put_user_ret(x,ptr,ret) ({ \ -if (__put_user(x,ptr)) return ret; }) - -#define __get_user_ret(x,ptr,ret) ({ \ -if (__get_user(x,ptr)) return ret; }) - -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) #define __get_user_size(x,ptr,size,retval) \ do { \ @@ -124,26 +43,6 @@ do { \ } \ } while (0) -#define __get_user_nocheck(x,ptr,size) \ -({ \ - long __gu_err, __gu_val; \ - __get_user_size((void *)&__gu_val, (long)(ptr), \ - (size), __gu_err); \ - (x) = (__typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - -#define __get_user_check(x,ptr,size) \ -({ \ - long __gu_addr = (long)(ptr); \ - long __gu_err = -EFAULT, __gu_val; \ - if (__access_ok(__gu_addr, (size))) \ - __get_user_size((void *)&__gu_val, __gu_addr, \ - (size), __gu_err); \ - (x) = (__typeof__(*(ptr))) __gu_val; \ - __gu_err; \ -}) - extern long __get_user_asm_b(void *, long); extern long __get_user_asm_w(void *, long); extern long __get_user_asm_l(void *, long); @@ -171,115 +70,10 @@ do { \ } \ } while (0) -#define __put_user_nocheck(x,ptr,size) \ -({ \ - long __pu_err; \ - __typeof__(*(ptr)) __pu_val = (x); \ - __put_user_size((void *)&__pu_val, (long)(ptr), (size), __pu_err); \ - __pu_err; \ -}) - -#define __put_user_check(x,ptr,size) \ -({ \ - long __pu_err = -EFAULT; \ - long __pu_addr = (long)(ptr); \ - __typeof__(*(ptr)) __pu_val = (x); \ - \ - if (__access_ok(__pu_addr, (size))) \ - __put_user_size((void *)&__pu_val, __pu_addr, (size), __pu_err);\ - __pu_err; \ -}) - extern long __put_user_asm_b(void *, long); extern long __put_user_asm_w(void *, long); extern long __put_user_asm_l(void *, long); extern long __put_user_asm_q(void *, long); extern void __put_user_unknown(void); - -/* Generic arbitrary sized copy. */ -/* Return the number of bytes NOT copied */ -/* XXX: should be such that: 4byte and the rest. */ -extern __kernel_size_t __copy_user(void *__to, const void *__from, __kernel_size_t __n); - -#define copy_to_user_ret(to,from,n,retval) ({ \ -if (copy_to_user(to,from,n)) \ - return retval; \ -}) - -#define __copy_to_user(to,from,n) \ - __copy_user((void *)(to), \ - (void *)(from), n) - -#define __copy_to_user_ret(to,from,n,retval) ({ \ -if (__copy_to_user(to,from,n)) \ - return retval; \ -}) - -#define copy_from_user_ret(to,from,n,retval) ({ \ -if (copy_from_user(to,from,n)) \ - return retval; \ -}) - -#define __copy_from_user(to,from,n) \ - __copy_user((void *)(to), \ - (void *)(from), n) - -#define __copy_from_user_ret(to,from,n,retval) ({ \ -if (__copy_from_user(to,from,n)) \ - return retval; \ -}) - -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user - -/* XXX: Not sure it works well.. - should be such that: 4byte clear and the rest. */ -extern __kernel_size_t __clear_user(void *addr, __kernel_size_t size); - -#define clear_user(addr,n) ({ \ -void * __cl_addr = (addr); \ -unsigned long __cl_size = (n); \ -if (__cl_size && __access_ok(((unsigned long)(__cl_addr)), __cl_size)) \ -__cl_size = __clear_user(__cl_addr, __cl_size); \ -__cl_size; }) - -extern int __strncpy_from_user(unsigned long __dest, unsigned long __src, int __count); - -#define strncpy_from_user(dest,src,count) ({ \ -unsigned long __sfu_src = (unsigned long) (src); \ -int __sfu_count = (int) (count); \ -long __sfu_res = -EFAULT; \ -if(__access_ok(__sfu_src, __sfu_count)) { \ -__sfu_res = __strncpy_from_user((unsigned long) (dest), __sfu_src, __sfu_count); \ -} __sfu_res; }) - -#define strlen_user(str) strnlen_user(str, ~0UL >> 1) - -/* - * Return the size of a string (including the ending 0!) - */ -extern long __strnlen_user(const char *__s, long __n); - -static inline long strnlen_user(const char *s, long n) -{ - if (!__addr_ok(s)) - return 0; - else - return __strnlen_user(s, n); -} - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -#ifdef CONFIG_MMU -#define ARCH_HAS_SEARCH_EXTABLE -#endif - -/* Returns 0 if exception not found and fixup.unit otherwise. */ -extern unsigned long search_exception_table(unsigned long addr); -extern const struct exception_table_entry *search_exception_tables (unsigned long addr); - #endif /* __ASM_SH_UACCESS_64_H */ diff --git a/include/asm-sparc/machines.h b/include/asm-sparc/machines.h index d6c6bf836206..c28c2f248794 100644 --- a/include/asm-sparc/machines.h +++ b/include/asm-sparc/machines.h @@ -17,8 +17,6 @@ struct Sun_Machine_Models { */ #define NUM_SUN_MACHINES 15 -extern struct Sun_Machine_Models Sun_Machines[NUM_SUN_MACHINES]; - /* The machine type in the idprom area looks like this: * * --------------- diff --git a/include/asm-sparc/mbus.h b/include/asm-sparc/mbus.h index bb5ae614b166..69f07a022ee6 100644 --- a/include/asm-sparc/mbus.h +++ b/include/asm-sparc/mbus.h @@ -43,8 +43,6 @@ extern unsigned int viking_rev, swift_rev, cypress_rev; #define HWBUG_SUPERSCALAR_BAD 0x00000080 #define HWBUG_PACINIT_BITROT 0x00000100 -extern unsigned int hwbug_bitmask; - /* First the module type values. To find out which you have, just load * the mmu control register from ASI_M_MMUREG alternate address space and * shift the value right 28 bits. diff --git a/include/asm-sparc/mostek.h b/include/asm-sparc/mostek.h index 29aad11b8f00..c35c916162fc 100644 --- a/include/asm-sparc/mostek.h +++ b/include/asm-sparc/mostek.h @@ -128,8 +128,6 @@ struct mostek48t08 { struct mostek48t02 regs; /* Here is what we are interested in. */ }; -extern enum sparc_clock_type sp_clock_typ; - #ifdef CONFIG_SUN4 enum sparc_clock_type { MSTK48T02, MSTK48T08, \ INTERSIL, MSTK_INVALID }; diff --git a/include/asm-sparc/oplib.h b/include/asm-sparc/oplib.h index 61c3ca6a8ac3..00f487e74d92 100644 --- a/include/asm-sparc/oplib.h +++ b/include/asm-sparc/oplib.h @@ -21,7 +21,6 @@ enum prom_major_version { PROM_V2, /* sun4c and early sun4m V2 prom */ PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */ PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */ - PROM_AP1000, /* actually no prom at all */ PROM_SUN4, /* Old sun4 proms are totally different, but we'll shoehorn it to make it fit */ }; diff --git a/include/asm-sparc/page.h b/include/asm-sparc/page.h index 6aa9e4c910cf..14de518cc38f 100644 --- a/include/asm-sparc/page.h +++ b/include/asm-sparc/page.h @@ -58,8 +58,6 @@ struct cache_palias { int context; }; -extern struct cache_palias *sparc_aliases; - /* passing structs on the Sparc slow us down tremendously... */ /* #define STRICT_MM_TYPECHECKS */ diff --git a/include/asm-sparc/timer.h b/include/asm-sparc/timer.h index d909565f9410..361e53898dd7 100644 --- a/include/asm-sparc/timer.h +++ b/include/asm-sparc/timer.h @@ -84,8 +84,6 @@ struct sun4m_timer_regs { volatile unsigned int cfg; /* equals zero at boot time... */ }; -extern struct sun4m_timer_regs *sun4m_timers; - #define SUN4D_PRM_CNT_L 0x80000000 #define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00 diff --git a/include/asm-sparc64/Kbuild b/include/asm-sparc64/Kbuild index dce1cf9a9313..7e88c1292d10 100644 --- a/include/asm-sparc64/Kbuild +++ b/include/asm-sparc64/Kbuild @@ -4,9 +4,7 @@ ALTARCH := sparc ARCHDEF := defined __sparc__ && defined __arch64__ ALTARCHDEF := defined __sparc__ && !defined __arch64__ -header-y += apb.h header-y += asi.h -header-y += bbc.h header-y += bpp.h header-y += display7seg.h header-y += envctrl.h diff --git a/include/asm-sparc64/fhc.h b/include/asm-sparc64/fhc.h index ddffcdfbc984..788cbc46a116 100644 --- a/include/asm-sparc64/fhc.h +++ b/include/asm-sparc64/fhc.h @@ -118,14 +118,4 @@ struct linux_fhc { int num_fhc_ranges; }; -extern struct linux_central *central_bus; - -extern void apply_central_ranges(struct linux_central *central, - struct linux_prom_registers *regs, - int nregs); - -extern void apply_fhc_ranges(struct linux_fhc *fhc, - struct linux_prom_registers *regs, - int nregs); - #endif /* !(_SPARC64_FHC_H) */ diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h index c299b853b5ba..3158960f3eb5 100644 --- a/include/asm-sparc64/io.h +++ b/include/asm-sparc64/io.h @@ -24,7 +24,8 @@ static inline u8 _inb(unsigned long addr) __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); return ret; } @@ -35,7 +36,8 @@ static inline u16 _inw(unsigned long addr) __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); return ret; } @@ -46,7 +48,8 @@ static inline u32 _inl(unsigned long addr) __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); return ret; } @@ -55,21 +58,24 @@ static inline void _outb(u8 b, unsigned long addr) { __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */" : /* no outputs */ - : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); } static inline void _outw(u16 w, unsigned long addr) { __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */" : /* no outputs */ - : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); } static inline void _outl(u32 l, unsigned long addr) { __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */" : /* no outputs */ - : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); } #define inb(__addr) (_inb((unsigned long)(__addr))) @@ -128,7 +134,8 @@ static inline u8 _readb(const volatile void __iomem *addr) __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); return ret; } @@ -137,7 +144,8 @@ static inline u16 _readw(const volatile void __iomem *addr) __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); return ret; } @@ -147,7 +155,8 @@ static inline u32 _readl(const volatile void __iomem *addr) __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); return ret; } @@ -157,7 +166,8 @@ static inline u64 _readq(const volatile void __iomem *addr) __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); return ret; } @@ -166,28 +176,32 @@ static inline void _writeb(u8 b, volatile void __iomem *addr) { __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */" : /* no outputs */ - : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); } static inline void _writew(u16 w, volatile void __iomem *addr) { __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */" : /* no outputs */ - : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); } static inline void _writel(u32 l, volatile void __iomem *addr) { __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */" : /* no outputs */ - : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); } static inline void _writeq(u64 q, volatile void __iomem *addr) { __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" : /* no outputs */ - : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) + : "memory"); } #define readb(__addr) _readb(__addr) @@ -299,7 +313,8 @@ static inline u8 _sbus_readb(const volatile void __iomem *addr) __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); return ret; } @@ -310,7 +325,8 @@ static inline u16 _sbus_readw(const volatile void __iomem *addr) __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); return ret; } @@ -321,7 +337,8 @@ static inline u32 _sbus_readl(const volatile void __iomem *addr) __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); return ret; } @@ -332,7 +349,8 @@ static inline u64 _sbus_readq(const volatile void __iomem *addr) __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */" : "=r" (ret) - : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); return ret; } @@ -341,28 +359,32 @@ static inline void _sbus_writeb(u8 b, volatile void __iomem *addr) { __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */" : /* no outputs */ - : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); } static inline void _sbus_writew(u16 w, volatile void __iomem *addr) { __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */" : /* no outputs */ - : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); } static inline void _sbus_writel(u32 l, volatile void __iomem *addr) { __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */" : /* no outputs */ - : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); } static inline void _sbus_writeq(u64 l, volatile void __iomem *addr) { __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */" : /* no outputs */ - : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E) + : "memory"); } #define sbus_readb(__addr) _sbus_readb(__addr) diff --git a/include/asm-sparc64/openpromio.h b/include/asm-sparc64/openpromio.h index 847ce2326ad5..122fabda21f1 100644 --- a/include/asm-sparc64/openpromio.h +++ b/include/asm-sparc64/openpromio.h @@ -1,69 +1 @@ -#ifndef _SPARC64_OPENPROMIO_H -#define _SPARC64_OPENPROMIO_H - -#include <linux/compiler.h> -#include <linux/ioctl.h> -#include <linux/types.h> - -/* - * SunOS and Solaris /dev/openprom definitions. The ioctl values - * were chosen to be exactly equal to the SunOS equivalents. - */ - -struct openpromio -{ - u_int oprom_size; /* Actual size of the oprom_array. */ - char oprom_array[1]; /* Holds property names and values. */ -}; - -#define OPROMMAXPARAM 4096 /* Maximum size of oprom_array. */ - -#define OPROMGETOPT 0x20004F01 -#define OPROMSETOPT 0x20004F02 -#define OPROMNXTOPT 0x20004F03 -#define OPROMSETOPT2 0x20004F04 -#define OPROMNEXT 0x20004F05 -#define OPROMCHILD 0x20004F06 -#define OPROMGETPROP 0x20004F07 -#define OPROMNXTPROP 0x20004F08 -#define OPROMU2P 0x20004F09 -#define OPROMGETCONS 0x20004F0A -#define OPROMGETFBNAME 0x20004F0B -#define OPROMGETBOOTARGS 0x20004F0C -/* Linux extensions */ /* Arguments in oprom_array: */ -#define OPROMSETCUR 0x20004FF0 /* int node - Sets current node */ -#define OPROMPCI2NODE 0x20004FF1 /* int pci_bus, pci_devfn - Sets current node to PCI device's node */ -#define OPROMPATH2NODE 0x20004FF2 /* char path[] - Set current node from fully qualified PROM path */ - -/* - * Return values from OPROMGETCONS: - */ - -#define OPROMCONS_NOT_WSCONS 0 -#define OPROMCONS_STDIN_IS_KBD 0x1 /* stdin device is kbd */ -#define OPROMCONS_STDOUT_IS_FB 0x2 /* stdout is a framebuffer */ -#define OPROMCONS_OPENPROM 0x4 /* supports openboot */ - - -/* - * NetBSD/OpenBSD /dev/openprom definitions. - */ - -struct opiocdesc -{ - int op_nodeid; /* PROM Node ID (value-result) */ - int op_namelen; /* Length of op_name. */ - char __user *op_name; /* Pointer to the property name. */ - int op_buflen; /* Length of op_buf (value-result) */ - char __user *op_buf; /* Pointer to buffer. */ -}; - -#define OPIOCGET _IOWR('O', 1, struct opiocdesc) -#define OPIOCSET _IOW('O', 2, struct opiocdesc) -#define OPIOCNEXTPROP _IOWR('O', 3, struct opiocdesc) -#define OPIOCGETOPTNODE _IOR('O', 4, int) -#define OPIOCGETNEXT _IOWR('O', 5, int) -#define OPIOCGETCHILD _IOWR('O', 6, int) - -#endif /* _SPARC64_OPENPROMIO_H */ - +#include <asm-sparc/openpromio.h> diff --git a/include/asm-sparc64/perfctr.h b/include/asm-sparc64/perfctr.h index 836873002b75..52073a9f8e30 100644 --- a/include/asm-sparc64/perfctr.h +++ b/include/asm-sparc64/perfctr.h @@ -1,173 +1 @@ -/*---------------------------------------- - PERFORMANCE INSTRUMENTATION - Guillaume Thouvenin 08/10/98 - David S. Miller 10/06/98 - ---------------------------------------*/ -#ifndef PERF_COUNTER_API -#define PERF_COUNTER_API - -/* sys_perfctr() interface. First arg is operation code - * from enumeration below. The meaning of further arguments - * are determined by the operation code. - * - * int sys_perfctr(int opcode, unsigned long arg0, - * unsigned long arg1, unsigned long arg2) - * - * Pointers which are passed by the user are pointers to 64-bit - * integers. - * - * Once enabled, performance counter state is retained until the - * process either exits or performs an exec. That is, performance - * counters remain enabled for fork/clone children. - */ -enum perfctr_opcode { - /* Enable UltraSparc performance counters, ARG0 is pointer - * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer - * to 64-bit accumulator for D1 counter. ARG2 is a pointer to - * the initial PCR register value to use. - */ - PERFCTR_ON, - - /* Disable UltraSparc performance counters. The PCR is written - * with zero and the user counter accumulator pointers and - * working PCR register value are forgotten. - */ - PERFCTR_OFF, - - /* Add current D0 and D1 PIC values into user pointers given - * in PERFCTR_ON operation. The PIC is cleared before returning. - */ - PERFCTR_READ, - - /* Clear the PIC register. */ - PERFCTR_CLRPIC, - - /* Begin using a new PCR value, the pointer to which is passed - * in ARG0. The PIC is also cleared after the new PCR value is - * written. - */ - PERFCTR_SETPCR, - - /* Store in pointer given in ARG0 the current PCR register value - * being used. - */ - PERFCTR_GETPCR -}; - -/* I don't want the kernel's namespace to be polluted with this - * stuff when this file is included. --DaveM - */ -#ifndef __KERNEL__ - -#define PRIV 0x00000001 -#define SYS 0x00000002 -#define USR 0x00000004 - -/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */ -#define CYCLE_CNT 0x00000000 -#define INSTR_CNT 0x00000010 -#define DISPATCH0_IC_MISS 0x00000020 -#define DISPATCH0_STOREBUF 0x00000030 -#define IC_REF 0x00000080 -#define DC_RD 0x00000090 -#define DC_WR 0x000000A0 -#define LOAD_USE 0x000000B0 -#define EC_REF 0x000000C0 -#define EC_WRITE_HIT_RDO 0x000000D0 -#define EC_SNOOP_INV 0x000000E0 -#define EC_RD_HIT 0x000000F0 - -/* Pic.S0 Selection Bit Field Encoding, Ultra-III */ -#define US3_CYCLE_CNT 0x00000000 -#define US3_INSTR_CNT 0x00000010 -#define US3_DISPATCH0_IC_MISS 0x00000020 -#define US3_DISPATCH0_BR_TGT 0x00000030 -#define US3_DISPATCH0_2ND_BR 0x00000040 -#define US3_RSTALL_STOREQ 0x00000050 -#define US3_RSTALL_IU_USE 0x00000060 -#define US3_IC_REF 0x00000080 -#define US3_DC_RD 0x00000090 -#define US3_DC_WR 0x000000a0 -#define US3_EC_REF 0x000000c0 -#define US3_EC_WR_HIT_RTO 0x000000d0 -#define US3_EC_SNOOP_INV 0x000000e0 -#define US3_EC_RD_MISS 0x000000f0 -#define US3_PC_PORT0_RD 0x00000100 -#define US3_SI_SNOOP 0x00000110 -#define US3_SI_CIQ_FLOW 0x00000120 -#define US3_SI_OWNED 0x00000130 -#define US3_SW_COUNT_0 0x00000140 -#define US3_IU_BR_MISS_TAKEN 0x00000150 -#define US3_IU_BR_COUNT_TAKEN 0x00000160 -#define US3_DISP_RS_MISPRED 0x00000170 -#define US3_FA_PIPE_COMPL 0x00000180 -#define US3_MC_READS_0 0x00000200 -#define US3_MC_READS_1 0x00000210 -#define US3_MC_READS_2 0x00000220 -#define US3_MC_READS_3 0x00000230 -#define US3_MC_STALLS_0 0x00000240 -#define US3_MC_STALLS_2 0x00000250 - -/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */ -#define CYCLE_CNT_D1 0x00000000 -#define INSTR_CNT_D1 0x00000800 -#define DISPATCH0_IC_MISPRED 0x00001000 -#define DISPATCH0_FP_USE 0x00001800 -#define IC_HIT 0x00004000 -#define DC_RD_HIT 0x00004800 -#define DC_WR_HIT 0x00005000 -#define LOAD_USE_RAW 0x00005800 -#define EC_HIT 0x00006000 -#define EC_WB 0x00006800 -#define EC_SNOOP_CB 0x00007000 -#define EC_IT_HIT 0x00007800 - -/* Pic.S1 Selection Bit Field Encoding, Ultra-III */ -#define US3_CYCLE_CNT_D1 0x00000000 -#define US3_INSTR_CNT_D1 0x00000800 -#define US3_DISPATCH0_MISPRED 0x00001000 -#define US3_IC_MISS_CANCELLED 0x00001800 -#define US3_RE_ENDIAN_MISS 0x00002000 -#define US3_RE_FPU_BYPASS 0x00002800 -#define US3_RE_DC_MISS 0x00003000 -#define US3_RE_EC_MISS 0x00003800 -#define US3_IC_MISS 0x00004000 -#define US3_DC_RD_MISS 0x00004800 -#define US3_DC_WR_MISS 0x00005000 -#define US3_RSTALL_FP_USE 0x00005800 -#define US3_EC_MISSES 0x00006000 -#define US3_EC_WB 0x00006800 -#define US3_EC_SNOOP_CB 0x00007000 -#define US3_EC_IC_MISS 0x00007800 -#define US3_RE_PC_MISS 0x00008000 -#define US3_ITLB_MISS 0x00008800 -#define US3_DTLB_MISS 0x00009000 -#define US3_WC_MISS 0x00009800 -#define US3_WC_SNOOP_CB 0x0000a000 -#define US3_WC_SCRUBBED 0x0000a800 -#define US3_WC_WB_WO_READ 0x0000b000 -#define US3_PC_SOFT_HIT 0x0000c000 -#define US3_PC_SNOOP_INV 0x0000c800 -#define US3_PC_HARD_HIT 0x0000d000 -#define US3_PC_PORT1_RD 0x0000d800 -#define US3_SW_COUNT_1 0x0000e000 -#define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800 -#define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000 -#define US3_PC_MS_MISSES 0x0000f800 -#define US3_MC_WRITES_0 0x00010800 -#define US3_MC_WRITES_1 0x00011000 -#define US3_MC_WRITES_2 0x00011800 -#define US3_MC_WRITES_3 0x00012000 -#define US3_MC_STALLS_1 0x00012800 -#define US3_MC_STALLS_3 0x00013000 -#define US3_RE_RAW_MISS 0x00013800 -#define US3_FM_PIPE_COMPLETION 0x00014000 - -struct vcounter_struct { - unsigned long long vcnt0; - unsigned long long vcnt1; -}; - -#endif /* !(__KERNEL__) */ - -#endif /* !(PERF_COUNTER_API) */ +#include <asm-sparc/perfctr.h> diff --git a/include/asm-um/mmu_context.h b/include/asm-um/mmu_context.h index 6686fc524ca1..54f42e8b0105 100644 --- a/include/asm-um/mmu_context.h +++ b/include/asm-um/mmu_context.h @@ -22,16 +22,10 @@ extern void force_flush_all(void); static inline void activate_mm(struct mm_struct *old, struct mm_struct *new) { /* - * This is called by fs/exec.c and fs/aio.c. In the first case, for an - * exec, we don't need to do anything as we're called from userspace - * and thus going to use a new host PID. In the second, we're called - * from a kernel thread, and thus need to go doing the mmap's on the - * host. Since they're very expensive, we want to avoid that as far as - * possible. + * This is called by fs/exec.c and sys_unshare() + * when the new ->mm is used for the first time. */ - if (old != new && (current->flags & PF_BORROWED_MM)) - __switch_mm(&new->context.id); - + __switch_mm(&new->context.id); arch_dup_mmap(old, new); } diff --git a/include/asm-v850/clinkage.h b/include/asm-v850/clinkage.h index 2b622adccae5..c389691d6f86 100644 --- a/include/asm-v850/clinkage.h +++ b/include/asm-v850/clinkage.h @@ -11,7 +11,7 @@ * Written by Miles Bader <miles@gnu.org> */ -#ifndef __CLINKAGE_H__ +#ifndef __V850_CLINKAGE_H__ #define __V850_CLINKAGE_H__ #include <asm/macrology.h> diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h index 14411c9de46f..73ce5b32443f 100644 --- a/include/asm-x86/acpi.h +++ b/include/asm-x86/acpi.h @@ -28,6 +28,7 @@ #include <asm/numa.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/mpspec.h> #define COMPILER_DEPENDENT_INT64 long long #define COMPILER_DEPENDENT_UINT64 unsigned long long diff --git a/include/asm-x86/alternative.h b/include/asm-x86/alternative.h index 1f6a9ca10126..f6aa18eadf71 100644 --- a/include/asm-x86/alternative.h +++ b/include/asm-x86/alternative.h @@ -72,6 +72,8 @@ static inline void alternatives_smp_module_del(struct module *mod) {} static inline void alternatives_smp_switch(int smp) {} #endif /* CONFIG_SMP */ +const unsigned char *const *find_nop_table(void); + /* * Alternative instructions for different CPU types or capabilities. * diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h index be9639a9a186..313bcaf4b6c3 100644 --- a/include/asm-x86/apic.h +++ b/include/asm-x86/apic.h @@ -36,14 +36,10 @@ extern void generic_apic_probe(void); #ifdef CONFIG_X86_LOCAL_APIC extern int apic_verbosity; -extern int timer_over_8254; extern int local_apic_timer_c2_ok; -extern int local_apic_timer_disabled; -extern int apic_runs_main_timer; extern int ioapic_force; extern int disable_apic; -extern int disable_apic_timer; /* * Basic functions accessing APICs. diff --git a/include/asm-x86/atomic_64.h b/include/asm-x86/atomic_64.h index 3e0cd7d38335..fe589c153db8 100644 --- a/include/asm-x86/atomic_64.h +++ b/include/asm-x86/atomic_64.h @@ -11,12 +11,6 @@ * resource counting etc.. */ -#ifdef CONFIG_SMP -#define LOCK "lock ; " -#else -#define LOCK "" -#endif - /* * Make sure gcc doesn't try to be clever and move things around * on us. We need to use _exactly_ the address the user gave us, diff --git a/include/asm-x86/bios_ebda.h b/include/asm-x86/bios_ebda.h index b4a46b7be794..0033e50c13b2 100644 --- a/include/asm-x86/bios_ebda.h +++ b/include/asm-x86/bios_ebda.h @@ -14,4 +14,6 @@ static inline unsigned int get_bios_ebda(void) return address; /* 0 means none */ } +void reserve_ebda_region(void); + #endif /* _MACH_BIOS_EBDA_H */ diff --git a/include/asm-x86/bitops.h b/include/asm-x86/bitops.h index ee4b3ead6a43..7d2494bdc660 100644 --- a/include/asm-x86/bitops.h +++ b/include/asm-x86/bitops.h @@ -43,7 +43,7 @@ * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ -static inline void set_bit(int nr, volatile void *addr) +static inline void set_bit(int nr, volatile unsigned long *addr) { asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory"); } @@ -57,7 +57,7 @@ static inline void set_bit(int nr, volatile void *addr) * If it's called on the same region of memory simultaneously, the effect * may be that only one operation succeeds. */ -static inline void __set_bit(int nr, volatile void *addr) +static inline void __set_bit(int nr, volatile unsigned long *addr) { asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory"); } @@ -72,7 +72,7 @@ static inline void __set_bit(int nr, volatile void *addr) * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() * in order to ensure changes are visible on other processors. */ -static inline void clear_bit(int nr, volatile void *addr) +static inline void clear_bit(int nr, volatile unsigned long *addr) { asm volatile(LOCK_PREFIX "btr %1,%0" : ADDR : "Ir" (nr)); } @@ -85,13 +85,13 @@ static inline void clear_bit(int nr, volatile void *addr) * clear_bit() is atomic and implies release semantics before the memory * operation. It can be used for an unlock. */ -static inline void clear_bit_unlock(unsigned nr, volatile void *addr) +static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr) { barrier(); clear_bit(nr, addr); } -static inline void __clear_bit(int nr, volatile void *addr) +static inline void __clear_bit(int nr, volatile unsigned long *addr) { asm volatile("btr %1,%0" : ADDR : "Ir" (nr)); } @@ -108,7 +108,7 @@ static inline void __clear_bit(int nr, volatile void *addr) * No memory barrier is required here, because x86 cannot reorder stores past * older loads. Same principle as spin_unlock. */ -static inline void __clear_bit_unlock(unsigned nr, volatile void *addr) +static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr) { barrier(); __clear_bit(nr, addr); @@ -126,7 +126,7 @@ static inline void __clear_bit_unlock(unsigned nr, volatile void *addr) * If it's called on the same region of memory simultaneously, the effect * may be that only one operation succeeds. */ -static inline void __change_bit(int nr, volatile void *addr) +static inline void __change_bit(int nr, volatile unsigned long *addr) { asm volatile("btc %1,%0" : ADDR : "Ir" (nr)); } @@ -140,7 +140,7 @@ static inline void __change_bit(int nr, volatile void *addr) * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ -static inline void change_bit(int nr, volatile void *addr) +static inline void change_bit(int nr, volatile unsigned long *addr) { asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr)); } @@ -153,7 +153,7 @@ static inline void change_bit(int nr, volatile void *addr) * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static inline int test_and_set_bit(int nr, volatile void *addr) +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) { int oldbit; @@ -170,7 +170,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) * * This is the same as test_and_set_bit on x86. */ -static inline int test_and_set_bit_lock(int nr, volatile void *addr) +static inline int test_and_set_bit_lock(int nr, volatile unsigned long *addr) { return test_and_set_bit(nr, addr); } @@ -184,7 +184,7 @@ static inline int test_and_set_bit_lock(int nr, volatile void *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_set_bit(int nr, volatile void *addr) +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) { int oldbit; @@ -203,7 +203,7 @@ static inline int __test_and_set_bit(int nr, volatile void *addr) * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static inline int test_and_clear_bit(int nr, volatile void *addr) +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) { int oldbit; @@ -223,7 +223,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) { int oldbit; @@ -235,7 +235,7 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr) } /* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, volatile void *addr) +static inline int __test_and_change_bit(int nr, volatile unsigned long *addr) { int oldbit; @@ -255,7 +255,7 @@ static inline int __test_and_change_bit(int nr, volatile void *addr) * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static inline int test_and_change_bit(int nr, volatile void *addr) +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) { int oldbit; @@ -266,13 +266,13 @@ static inline int test_and_change_bit(int nr, volatile void *addr) return oldbit; } -static inline int constant_test_bit(int nr, const volatile void *addr) +static inline int constant_test_bit(int nr, const volatile unsigned long *addr) { return ((1UL << (nr % BITS_PER_LONG)) & (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0; } -static inline int variable_test_bit(int nr, volatile const void *addr) +static inline int variable_test_bit(int nr, volatile const unsigned long *addr) { int oldbit; diff --git a/include/asm-x86/bootparam.h b/include/asm-x86/bootparam.h index f62f4733606b..caeca78c2f0a 100644 --- a/include/asm-x86/bootparam.h +++ b/include/asm-x86/bootparam.h @@ -40,6 +40,7 @@ struct setup_header { __u8 type_of_loader; __u8 loadflags; #define LOADED_HIGH (1<<0) +#define QUIET_FLAG (1<<5) #define KEEP_SEGMENTS (1<<6) #define CAN_USE_HEAP (1<<7) __u16 setup_move_size; @@ -106,4 +107,7 @@ struct boot_params { __u8 _pad9[276]; /* 0xeec */ } __attribute__((packed)); +void reserve_setup_data(void); +void parse_setup_data(void); + #endif /* _ASM_BOOTPARAM_H */ diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 0d609c837a41..c30213703eb7 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h @@ -79,6 +79,7 @@ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ +#define X86_FEATURE_PCI_EXT_CFG (3*32+19) /* PCI extended cfg access */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ @@ -142,11 +143,11 @@ extern const char * const x86_power_flags[32]; #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) #define setup_clear_cpu_cap(bit) do { \ clear_cpu_cap(&boot_cpu_data, bit); \ - set_bit(bit, cleared_cpu_caps); \ + set_bit(bit, (unsigned long *)cleared_cpu_caps); \ } while (0) #define setup_force_cpu_cap(bit) do { \ set_cpu_cap(&boot_cpu_data, bit); \ - clear_bit(bit, cleared_cpu_caps); \ + clear_bit(bit, (unsigned long *)cleared_cpu_caps); \ } while (0) #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) @@ -187,6 +188,7 @@ extern const char * const x86_power_flags[32]; #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) +#define cpu_has_pci_ext_cfg boot_cpu_has(X86_FEATURE_PCI_EXT_CFG) #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) # define cpu_has_invlpg 1 diff --git a/include/asm-x86/current.h b/include/asm-x86/current.h index d2526d3f7346..7515c19d4988 100644 --- a/include/asm-x86/current.h +++ b/include/asm-x86/current.h @@ -1,5 +1,39 @@ +#ifndef _X86_CURRENT_H +#define _X86_CURRENT_H + #ifdef CONFIG_X86_32 -# include "current_32.h" -#else -# include "current_64.h" -#endif +#include <linux/compiler.h> +#include <asm/percpu.h> + +struct task_struct; + +DECLARE_PER_CPU(struct task_struct *, current_task); +static __always_inline struct task_struct *get_current(void) +{ + return x86_read_percpu(current_task); +} + +#else /* X86_32 */ + +#ifndef __ASSEMBLY__ +#include <asm/pda.h> + +struct task_struct; + +static __always_inline struct task_struct *get_current(void) +{ + return read_pda(pcurrent); +} + +#else /* __ASSEMBLY__ */ + +#include <asm/asm-offsets.h> +#define GET_CURRENT(reg) movq %gs:(pda_pcurrent),reg + +#endif /* __ASSEMBLY__ */ + +#endif /* X86_32 */ + +#define current get_current() + +#endif /* X86_CURRENT_H */ diff --git a/include/asm-x86/current_32.h b/include/asm-x86/current_32.h deleted file mode 100644 index 5af9bdb97a16..000000000000 --- a/include/asm-x86/current_32.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _I386_CURRENT_H -#define _I386_CURRENT_H - -#include <linux/compiler.h> -#include <asm/percpu.h> - -struct task_struct; - -DECLARE_PER_CPU(struct task_struct *, current_task); -static __always_inline struct task_struct *get_current(void) -{ - return x86_read_percpu(current_task); -} - -#define current get_current() - -#endif /* !(_I386_CURRENT_H) */ diff --git a/include/asm-x86/current_64.h b/include/asm-x86/current_64.h deleted file mode 100644 index 2d368ede2fc1..000000000000 --- a/include/asm-x86/current_64.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _X86_64_CURRENT_H -#define _X86_64_CURRENT_H - -#if !defined(__ASSEMBLY__) -struct task_struct; - -#include <asm/pda.h> - -static inline struct task_struct *get_current(void) -{ - struct task_struct *t = read_pda(pcurrent); - return t; -} - -#define current get_current() - -#else - -#ifndef ASM_OFFSET_H -#include <asm/asm-offsets.h> -#endif - -#define GET_CURRENT(reg) movq %gs:(pda_pcurrent),reg - -#endif - -#endif /* !(_X86_64_CURRENT_H) */ diff --git a/include/asm-x86/desc.h b/include/asm-x86/desc.h index 268a012bcd79..b3875d4b4fab 100644 --- a/include/asm-x86/desc.h +++ b/include/asm-x86/desc.h @@ -311,6 +311,28 @@ static inline void set_intr_gate(unsigned int n, void *addr) _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS); } +#define SYS_VECTOR_FREE 0 +#define SYS_VECTOR_ALLOCED 1 + +extern int first_system_vector; +extern char system_vectors[]; + +static inline void alloc_system_vector(int vector) +{ + if (system_vectors[vector] == SYS_VECTOR_FREE) { + system_vectors[vector] = SYS_VECTOR_ALLOCED; + if (first_system_vector > vector) + first_system_vector = vector; + } else + BUG(); +} + +static inline void alloc_intr_gate(unsigned int n, void *addr) +{ + alloc_system_vector(n); + set_intr_gate(n, addr); +} + /* * This routine sets up an interrupt gate at directory privilege level 3. */ diff --git a/include/asm-x86/e820.h b/include/asm-x86/e820.h index 7004251fc66b..8aa32323a182 100644 --- a/include/asm-x86/e820.h +++ b/include/asm-x86/e820.h @@ -2,6 +2,41 @@ #define __ASM_E820_H #define E820MAP 0x2d0 /* our map */ #define E820MAX 128 /* number of entries in E820MAP */ + +/* + * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the + * constrained space in the zeropage. If we have more nodes than + * that, and if we've booted off EFI firmware, then the EFI tables + * passed us from the EFI firmware can list more nodes. Size our + * internal memory map tables to have room for these additional + * nodes, based on up to three entries per node for which the + * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT), + * plus E820MAX, allowing space for the possible duplicate E820 + * entries that might need room in the same arrays, prior to the + * call to sanitize_e820_map() to remove duplicates. The allowance + * of three memory map entries per node is "enough" entries for + * the initial hardware platform motivating this mechanism to make + * use of additional EFI map entries. Future platforms may want + * to allow more than three entries per node or otherwise refine + * this size. + */ + +/* + * Odd: 'make headers_check' complains about numa.h if I try + * to collapse the next two #ifdef lines to a single line: + * #if defined(__KERNEL__) && defined(CONFIG_EFI) + */ +#ifdef __KERNEL__ +#ifdef CONFIG_EFI +#include <linux/numa.h> +#define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES) +#else /* ! CONFIG_EFI */ +#define E820_X_MAX E820MAX +#endif +#else /* ! __KERNEL__ */ +#define E820_X_MAX E820MAX +#endif + #define E820NR 0x1e8 /* # entries in E820MAP */ #define E820_RAM 1 @@ -18,8 +53,51 @@ struct e820entry { struct e820map { __u32 nr_map; - struct e820entry map[E820MAX]; + struct e820entry map[E820_X_MAX]; }; + +extern struct e820map e820; + +extern int e820_any_mapped(u64 start, u64 end, unsigned type); +extern int e820_all_mapped(u64 start, u64 end, unsigned type); +extern void add_memory_region(u64 start, u64 size, int type); +extern void e820_print_map(char *who); +extern int +sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, int *pnr_map); +extern int copy_e820_map(struct e820entry *biosmap, int nr_map); +extern u64 update_memory_range(u64 start, u64 size, unsigned old_type, + unsigned new_type); +extern void update_e820(void); +extern void e820_setup_gap(void); + +#if defined(CONFIG_X86_64) || \ + (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION)) +extern void e820_mark_nosave_regions(unsigned long limit_pfn); +#else +static inline void e820_mark_nosave_regions(unsigned long limit_pfn) +{ +} +#endif + +extern unsigned long end_user_pfn; + +extern u64 find_e820_area(u64 start, u64 end, u64 size, u64 align); +extern u64 find_e820_area_size(u64 start, u64 *sizep, u64 align); +extern void reserve_early(u64 start, u64 end, char *name); +extern void free_early(u64 start, u64 end); +extern void early_res_to_bootmem(u64 start, u64 end); +extern int page_is_reserved_early(unsigned long pagenr); +extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align); + +extern unsigned long e820_end_of_ram(void); +extern int e820_find_active_region(const struct e820entry *ei, + unsigned long start_pfn, + unsigned long last_pfn, + unsigned long *ei_startpfn, + unsigned long *ei_endpfn); +extern void e820_register_active_regions(int nid, unsigned long start_pfn, + unsigned long end_pfn); +extern u64 e820_hole_size(u64 start, u64 end); #endif /* __ASSEMBLY__ */ #define ISA_START_ADDRESS 0xa0000 diff --git a/include/asm-x86/e820_32.h b/include/asm-x86/e820_32.h index a9f7c6ec32bf..212b74c10efc 100644 --- a/include/asm-x86/e820_32.h +++ b/include/asm-x86/e820_32.h @@ -18,33 +18,13 @@ #ifndef __ASSEMBLY__ -extern struct e820map e820; -extern void update_e820(void); +extern void setup_memory_map(void); +extern void finish_e820_parsing(void); -extern int e820_all_mapped(unsigned long start, unsigned long end, - unsigned type); -extern int e820_any_mapped(u64 start, u64 end, unsigned type); -extern void propagate_e820_map(void); -extern void register_bootmem_low_pages(unsigned long max_low_pfn); -extern void add_memory_region(unsigned long long start, - unsigned long long size, int type); -extern void update_memory_range(u64 start, u64 size, unsigned old_type, - unsigned new_type); -extern void e820_register_memory(void); extern void limit_regions(unsigned long long size); -extern void print_memory_map(char *who); extern void init_iomem_resources(struct resource *code_resource, struct resource *data_resource, struct resource *bss_resource); -#if defined(CONFIG_PM) && defined(CONFIG_HIBERNATION) -extern void e820_mark_nosave_regions(void); -#else -static inline void e820_mark_nosave_regions(void) -{ -} -#endif - - #endif/*!__ASSEMBLY__*/ #endif/*__E820_HEADER*/ diff --git a/include/asm-x86/e820_64.h b/include/asm-x86/e820_64.h index 71c4d685d30d..368585daaa42 100644 --- a/include/asm-x86/e820_64.h +++ b/include/asm-x86/e820_64.h @@ -14,43 +14,16 @@ #include <linux/ioport.h> #ifndef __ASSEMBLY__ -extern unsigned long find_e820_area(unsigned long start, unsigned long end, - unsigned long size, unsigned long align); -extern unsigned long find_e820_area_size(unsigned long start, - unsigned long *sizep, - unsigned long align); -extern void add_memory_region(unsigned long start, unsigned long size, - int type); -extern void update_memory_range(u64 start, u64 size, unsigned old_type, - unsigned new_type); extern void setup_memory_region(void); extern void contig_e820_setup(void); -extern unsigned long e820_end_of_ram(void); extern void e820_reserve_resources(void); -extern void e820_mark_nosave_regions(void); -extern int e820_any_mapped(unsigned long start, unsigned long end, - unsigned type); -extern int e820_all_mapped(unsigned long start, unsigned long end, - unsigned type); extern int e820_any_non_reserved(unsigned long start, unsigned long end); extern int is_memory_any_valid(unsigned long start, unsigned long end); extern int e820_all_non_reserved(unsigned long start, unsigned long end); extern int is_memory_all_valid(unsigned long start, unsigned long end); -extern unsigned long e820_hole_size(unsigned long start, unsigned long end); - -extern void e820_setup_gap(void); -extern void e820_register_active_regions(int nid, unsigned long start_pfn, - unsigned long end_pfn); extern void finish_e820_parsing(void); -extern struct e820map e820; -extern void update_e820(void); - -extern void reserve_early(unsigned long start, unsigned long end, char *name); -extern void free_early(unsigned long start, unsigned long end); -extern void early_res_to_bootmem(unsigned long start, unsigned long end); - #endif/*!__ASSEMBLY__*/ #endif/*__E820_HEADER*/ diff --git a/include/asm-x86/efi.h b/include/asm-x86/efi.h index d53004b855cc..7ed2bd7a7f51 100644 --- a/include/asm-x86/efi.h +++ b/include/asm-x86/efi.h @@ -90,7 +90,7 @@ extern void *efi_ioremap(unsigned long addr, unsigned long size); #endif /* CONFIG_X86_32 */ -extern void efi_reserve_bootmem(void); +extern void efi_reserve_early(void); extern void efi_call_phys_prelog(void); extern void efi_call_phys_epilog(void); diff --git a/include/asm-x86/fixmap_32.h b/include/asm-x86/fixmap_32.h index 4b96148e90c1..f0df7ee96816 100644 --- a/include/asm-x86/fixmap_32.h +++ b/include/asm-x86/fixmap_32.h @@ -79,10 +79,6 @@ enum fixed_addresses { FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, #endif -#ifdef CONFIG_ACPI - FIX_ACPI_BEGIN, - FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1, -#endif #ifdef CONFIG_PCI_MMCONFIG FIX_PCIE_MCFG, #endif @@ -103,6 +99,10 @@ enum fixed_addresses { (__end_of_permanent_fixed_addresses & 511), FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_NESTING - 1, FIX_WP_TEST, +#ifdef CONFIG_ACPI + FIX_ACPI_BEGIN, + FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1, +#endif #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT FIX_OHCI1394_BASE, #endif diff --git a/include/asm-x86/gart.h b/include/asm-x86/gart.h index 90958ed993fa..c818b96f936b 100644 --- a/include/asm-x86/gart.h +++ b/include/asm-x86/gart.h @@ -1,10 +1,13 @@ #ifndef _ASM_X8664_IOMMU_H #define _ASM_X8664_IOMMU_H 1 +#include <asm/e820.h> + extern void pci_iommu_shutdown(void); extern void no_iommu_init(void); extern int force_iommu, no_iommu; extern int iommu_detected; +extern int agp_amd64_init(void); #ifdef CONFIG_GART_IOMMU extern void gart_iommu_init(void); extern void gart_iommu_shutdown(void); @@ -31,4 +34,63 @@ static inline void gart_iommu_shutdown(void) #endif +/* PTE bits. */ +#define GPTE_VALID 1 +#define GPTE_COHERENT 2 + +/* Aperture control register bits. */ +#define GARTEN (1<<0) +#define DISGARTCPU (1<<4) +#define DISGARTIO (1<<5) + +/* GART cache control register bits. */ +#define INVGART (1<<0) +#define GARTPTEERR (1<<1) + +/* K8 On-cpu GART registers */ +#define AMD64_GARTAPERTURECTL 0x90 +#define AMD64_GARTAPERTUREBASE 0x94 +#define AMD64_GARTTABLEBASE 0x98 +#define AMD64_GARTCACHECTL 0x9c +#define AMD64_GARTEN (1<<0) + +static inline void enable_gart_translation(struct pci_dev *dev, u64 addr) +{ + u32 tmp, ctl; + + /* address of the mappings table */ + addr >>= 12; + tmp = (u32) addr<<4; + tmp &= ~0xf; + pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp); + + /* Enable GART translation for this hammer. */ + pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); + ctl |= GARTEN; + ctl &= ~(DISGARTCPU | DISGARTIO); + pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); +} + +static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size) +{ + if (!aper_base) + return 0; + + if (aper_base + aper_size > 0x100000000ULL) { + printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n"); + return 0; + } + if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { + printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n"); + return 0; + } + if (aper_size < min_size) { + printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n", + aper_size>>20, min_size>>20); + return 0; + } + + return 1; +} + #endif diff --git a/include/asm-x86/genapic_64.h b/include/asm-x86/genapic_64.h index 1de931b263ce..0f8504627c41 100644 --- a/include/asm-x86/genapic_64.h +++ b/include/asm-x86/genapic_64.h @@ -44,4 +44,6 @@ DECLARE_PER_CPU(int, x2apic_extra_bits); extern void uv_cpu_init(void); extern int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip); +extern void setup_apic_routing(void); + #endif diff --git a/include/asm-x86/hardirq.h b/include/asm-x86/hardirq.h index 314434d664e7..000787df66e6 100644 --- a/include/asm-x86/hardirq.h +++ b/include/asm-x86/hardirq.h @@ -3,3 +3,9 @@ #else # include "hardirq_64.h" #endif + +extern u64 arch_irq_stat_cpu(unsigned int cpu); +#define arch_irq_stat_cpu arch_irq_stat_cpu + +extern u64 arch_irq_stat(void); +#define arch_irq_stat arch_irq_stat diff --git a/include/asm-x86/hw_irq.h b/include/asm-x86/hw_irq.h index bf025399d939..1428b41dcbb9 100644 --- a/include/asm-x86/hw_irq.h +++ b/include/asm-x86/hw_irq.h @@ -1,5 +1,106 @@ +#ifndef _ASM_HW_IRQ_H +#define _ASM_HW_IRQ_H + +/* + * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar + * + * moved some of the old arch/i386/kernel/irq.h to here. VY + * + * IRQ/IPI changes taken from work by Thomas Radke + * <tomsoft@informatik.tu-chemnitz.de> + * + * hacked by Andi Kleen for x86-64. + * unified by tglx + */ + +#include <asm/irq_vectors.h> + +#ifndef __ASSEMBLY__ + +#include <linux/percpu.h> +#include <linux/profile.h> +#include <linux/smp.h> + +#include <asm/atomic.h> +#include <asm/irq.h> +#include <asm/sections.h> + +#define platform_legacy_irq(irq) ((irq) < 16) + +/* Interrupt handlers registered during init_IRQ */ +extern void apic_timer_interrupt(void); +extern void error_interrupt(void); +extern void spurious_interrupt(void); +extern void thermal_interrupt(void); +extern void reschedule_interrupt(void); + +extern void invalidate_interrupt(void); +extern void invalidate_interrupt0(void); +extern void invalidate_interrupt1(void); +extern void invalidate_interrupt2(void); +extern void invalidate_interrupt3(void); +extern void invalidate_interrupt4(void); +extern void invalidate_interrupt5(void); +extern void invalidate_interrupt6(void); +extern void invalidate_interrupt7(void); + +extern void irq_move_cleanup_interrupt(void); +extern void threshold_interrupt(void); + +extern void call_function_interrupt(void); + +/* PIC specific functions */ +extern void disable_8259A_irq(unsigned int irq); +extern void enable_8259A_irq(unsigned int irq); +extern int i8259A_irq_pending(unsigned int irq); +extern void make_8259A_irq(unsigned int irq); +extern void init_8259A(int aeoi); + +/* IOAPIC */ +#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs)) +extern unsigned long io_apic_irqs; + +extern void init_VISWS_APIC_irqs(void); +extern void setup_IO_APIC(void); +extern void disable_IO_APIC(void); +extern void print_IO_APIC(void); +extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn); +extern void setup_ioapic_dest(void); + +#ifdef CONFIG_X86_64 +extern void enable_IO_APIC(void); +#endif + +/* IPI functions */ +extern void send_IPI_self(int vector); +extern void send_IPI(int dest, int vector); + +/* Statistics */ +extern atomic_t irq_err_count; +extern atomic_t irq_mis_count; + +/* EISA */ +extern void eisa_set_level_irq(unsigned int irq); + +/* Voyager functions */ +extern asmlinkage void vic_cpi_interrupt(void); +extern asmlinkage void vic_sys_interrupt(void); +extern asmlinkage void vic_cmn_interrupt(void); +extern asmlinkage void qic_timer_interrupt(void); +extern asmlinkage void qic_invalidate_interrupt(void); +extern asmlinkage void qic_reschedule_interrupt(void); +extern asmlinkage void qic_enable_irq_interrupt(void); +extern asmlinkage void qic_call_function_interrupt(void); + #ifdef CONFIG_X86_32 -# include "hw_irq_32.h" +extern void (*const interrupt[NR_IRQS])(void); #else -# include "hw_irq_64.h" +typedef int vector_irq_t[NR_VECTORS]; +DECLARE_PER_CPU(vector_irq_t, vector_irq); +extern void __setup_vector_irq(int cpu); +extern spinlock_t vector_lock; +#endif + +#endif /* !ASSEMBLY_ */ + #endif diff --git a/include/asm-x86/hw_irq_32.h b/include/asm-x86/hw_irq_32.h deleted file mode 100644 index ea88054e03f3..000000000000 --- a/include/asm-x86/hw_irq_32.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _ASM_HW_IRQ_H -#define _ASM_HW_IRQ_H - -/* - * linux/include/asm/hw_irq.h - * - * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar - * - * moved some of the old arch/i386/kernel/irq.h to here. VY - * - * IRQ/IPI changes taken from work by Thomas Radke - * <tomsoft@informatik.tu-chemnitz.de> - */ - -#include <linux/profile.h> -#include <asm/atomic.h> -#include <asm/irq.h> -#include <asm/sections.h> - -#define NMI_VECTOR 0x02 - -/* - * Various low-level irq details needed by irq.c, process.c, - * time.c, io_apic.c and smp.c - * - * Interrupt entry/exit code at both C and assembly level - */ - -extern void (*const interrupt[NR_IRQS])(void); - -#ifdef CONFIG_SMP -void reschedule_interrupt(void); -void invalidate_interrupt(void); -void call_function_interrupt(void); -#endif - -#ifdef CONFIG_X86_LOCAL_APIC -void apic_timer_interrupt(void); -void error_interrupt(void); -void spurious_interrupt(void); -void thermal_interrupt(void); -#define platform_legacy_irq(irq) ((irq) < 16) -#endif - -void disable_8259A_irq(unsigned int irq); -void enable_8259A_irq(unsigned int irq); -int i8259A_irq_pending(unsigned int irq); -void make_8259A_irq(unsigned int irq); -void init_8259A(int aeoi); -void send_IPI_self(int vector); -void init_VISWS_APIC_irqs(void); -void setup_IO_APIC(void); -void disable_IO_APIC(void); -void print_IO_APIC(void); -int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn); -void send_IPI(int dest, int vector); -void setup_ioapic_dest(void); - -extern unsigned long io_apic_irqs; - -extern atomic_t irq_err_count; -extern atomic_t irq_mis_count; - -#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs)) - -#endif /* _ASM_HW_IRQ_H */ diff --git a/include/asm-x86/hw_irq_64.h b/include/asm-x86/hw_irq_64.h deleted file mode 100644 index 0062ef390f67..000000000000 --- a/include/asm-x86/hw_irq_64.h +++ /dev/null @@ -1,173 +0,0 @@ -#ifndef _ASM_HW_IRQ_H -#define _ASM_HW_IRQ_H - -/* - * linux/include/asm/hw_irq.h - * - * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar - * - * moved some of the old arch/i386/kernel/irq.h to here. VY - * - * IRQ/IPI changes taken from work by Thomas Radke - * <tomsoft@informatik.tu-chemnitz.de> - * - * hacked by Andi Kleen for x86-64. - */ - -#ifndef __ASSEMBLY__ -#include <asm/atomic.h> -#include <asm/irq.h> -#include <linux/profile.h> -#include <linux/smp.h> -#include <linux/percpu.h> -#endif - -#define NMI_VECTOR 0x02 -/* - * IDT vectors usable for external interrupt sources start - * at 0x20: - */ -#define FIRST_EXTERNAL_VECTOR 0x20 - -#define IA32_SYSCALL_VECTOR 0x80 - - -/* Reserve the lowest usable priority level 0x20 - 0x2f for triggering - * cleanup after irq migration. - */ -#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR - -/* - * Vectors 0x30-0x3f are used for ISA interrupts. - */ -#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10) -#define IRQ1_VECTOR (IRQ0_VECTOR + 1) -#define IRQ2_VECTOR (IRQ0_VECTOR + 2) -#define IRQ3_VECTOR (IRQ0_VECTOR + 3) -#define IRQ4_VECTOR (IRQ0_VECTOR + 4) -#define IRQ5_VECTOR (IRQ0_VECTOR + 5) -#define IRQ6_VECTOR (IRQ0_VECTOR + 6) -#define IRQ7_VECTOR (IRQ0_VECTOR + 7) -#define IRQ8_VECTOR (IRQ0_VECTOR + 8) -#define IRQ9_VECTOR (IRQ0_VECTOR + 9) -#define IRQ10_VECTOR (IRQ0_VECTOR + 10) -#define IRQ11_VECTOR (IRQ0_VECTOR + 11) -#define IRQ12_VECTOR (IRQ0_VECTOR + 12) -#define IRQ13_VECTOR (IRQ0_VECTOR + 13) -#define IRQ14_VECTOR (IRQ0_VECTOR + 14) -#define IRQ15_VECTOR (IRQ0_VECTOR + 15) - -/* - * Special IRQ vectors used by the SMP architecture, 0xf0-0xff - * - * some of the following vectors are 'rare', they are merged - * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. - * TLB, reschedule and local APIC vectors are performance-critical. - */ -#define SPURIOUS_APIC_VECTOR 0xff -#define ERROR_APIC_VECTOR 0xfe -#define RESCHEDULE_VECTOR 0xfd -#define CALL_FUNCTION_VECTOR 0xfc -/* fb free - please don't readd KDB here because it's useless - (hint - think what a NMI bit does to a vector) */ -#define THERMAL_APIC_VECTOR 0xfa -#define THRESHOLD_APIC_VECTOR 0xf9 -/* f8 free */ -#define INVALIDATE_TLB_VECTOR_END 0xf7 -#define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */ - -#define NUM_INVALIDATE_TLB_VECTORS 8 - -/* - * Local APIC timer IRQ vector is on a different priority level, - * to work around the 'lost local interrupt if more than 2 IRQ - * sources per level' errata. - */ -#define LOCAL_TIMER_VECTOR 0xef - -/* - * First APIC vector available to drivers: (vectors 0x30-0xee) - * we start at 0x41 to spread out vectors evenly between priority - * levels. (0x80 is the syscall vector) - */ -#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2) -#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */ - - -#ifndef __ASSEMBLY__ - -/* Interrupt handlers registered during init_IRQ */ -void apic_timer_interrupt(void); -void spurious_interrupt(void); -void error_interrupt(void); -void reschedule_interrupt(void); -void call_function_interrupt(void); -void irq_move_cleanup_interrupt(void); -void invalidate_interrupt0(void); -void invalidate_interrupt1(void); -void invalidate_interrupt2(void); -void invalidate_interrupt3(void); -void invalidate_interrupt4(void); -void invalidate_interrupt5(void); -void invalidate_interrupt6(void); -void invalidate_interrupt7(void); -void thermal_interrupt(void); -void threshold_interrupt(void); -void i8254_timer_resume(void); - -typedef int vector_irq_t[NR_VECTORS]; -DECLARE_PER_CPU(vector_irq_t, vector_irq); -extern void __setup_vector_irq(int cpu); -extern spinlock_t vector_lock; - -/* - * Various low-level irq details needed by irq.c, process.c, - * time.c, io_apic.c and smp.c - * - * Interrupt entry/exit code at both C and assembly level - */ - -extern void disable_8259A_irq(unsigned int irq); -extern void enable_8259A_irq(unsigned int irq); -extern int i8259A_irq_pending(unsigned int irq); -extern void make_8259A_irq(unsigned int irq); -extern void init_8259A(int aeoi); -extern void send_IPI_self(int vector); -extern void init_VISWS_APIC_irqs(void); -extern void setup_IO_APIC(void); -extern void enable_IO_APIC(void); -extern void disable_IO_APIC(void); -extern void print_IO_APIC(void); -extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn); -extern void send_IPI(int dest, int vector); -extern void setup_ioapic_dest(void); -extern void native_init_IRQ(void); - -extern unsigned long io_apic_irqs; - -extern atomic_t irq_err_count; -extern atomic_t irq_mis_count; - -#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs)) - -#include <asm/ptrace.h> - -#define IRQ_NAME2(nr) nr##_interrupt(void) -#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) - -/* - * SMP has a few special interrupts for IPI messages - */ - -#define BUILD_IRQ(nr) \ - asmlinkage void IRQ_NAME(nr); \ - asm("\n.p2align\n" \ - "IRQ" #nr "_interrupt:\n\t" \ - "push $~(" #nr ") ; " \ - "jmp common_interrupt"); - -#define platform_legacy_irq(irq) ((irq) < 16) - -#endif - -#endif /* _ASM_HW_IRQ_H */ diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h index 6b722d315936..37672f79dcc8 100644 --- a/include/asm-x86/i387.h +++ b/include/asm-x86/i387.h @@ -193,6 +193,8 @@ static inline int restore_i387(struct _fpstate __user *buf) #else /* CONFIG_X86_32 */ +extern void finit(void); + static inline void tolerant_fwait(void) { asm volatile("fnclex ; fwait"); diff --git a/include/asm-x86/i8259.h b/include/asm-x86/i8259.h index 45d4df3e51e6..2f98df91f1f2 100644 --- a/include/asm-x86/i8259.h +++ b/include/asm-x86/i8259.h @@ -55,4 +55,6 @@ static inline void outb_pic(unsigned char value, unsigned int port) udelay(2); } +extern struct irq_chip i8259A_chip; + #endif /* __ASM_I8259_H__ */ diff --git a/include/asm-x86/io.h b/include/asm-x86/io.h index d5b11f60dbd0..8e9eca93f9b9 100644 --- a/include/asm-x86/io.h +++ b/include/asm-x86/io.h @@ -3,6 +3,62 @@ #define ARCH_HAS_IOREMAP_WC +#include <linux/compiler.h> + +#define build_mmio_read(name, size, type, reg, barrier) \ +static inline type name(const volatile void __iomem *addr) \ +{ type ret; asm volatile("mov" size " %1,%0":"=" reg (ret) \ +:"m" (*(volatile type __force *)addr) barrier); return ret; } + +#define build_mmio_write(name, size, type, reg, barrier) \ +static inline void name(type val, volatile void __iomem *addr) \ +{ asm volatile("mov" size " %0,%1": :reg (val), \ +"m" (*(volatile type __force *)addr) barrier); } + +build_mmio_read(readb, "b", unsigned char, "q", :"memory") +build_mmio_read(readw, "w", unsigned short, "r", :"memory") +build_mmio_read(readl, "l", unsigned int, "r", :"memory") + +build_mmio_read(__readb, "b", unsigned char, "q", ) +build_mmio_read(__readw, "w", unsigned short, "r", ) +build_mmio_read(__readl, "l", unsigned int, "r", ) + +build_mmio_write(writeb, "b", unsigned char, "q", :"memory") +build_mmio_write(writew, "w", unsigned short, "r", :"memory") +build_mmio_write(writel, "l", unsigned int, "r", :"memory") + +build_mmio_write(__writeb, "b", unsigned char, "q", ) +build_mmio_write(__writew, "w", unsigned short, "r", ) +build_mmio_write(__writel, "l", unsigned int, "r", ) + +#define readb_relaxed(a) __readb(a) +#define readw_relaxed(a) __readw(a) +#define readl_relaxed(a) __readl(a) +#define __raw_readb __readb +#define __raw_readw __readw +#define __raw_readl __readl + +#define __raw_writeb __writeb +#define __raw_writew __writew +#define __raw_writel __writel + +#define mmiowb() barrier() + +#ifdef CONFIG_X86_64 +build_mmio_read(readq, "q", unsigned long, "r", :"memory") +build_mmio_read(__readq, "q", unsigned long, "r", ) +build_mmio_write(writeq, "q", unsigned long, "r", :"memory") +build_mmio_write(__writeq, "q", unsigned long, "r", ) + +#define readq_relaxed(a) __readq(a) +#define __raw_readq __readq +#define __raw_writeq writeq + +/* Let people know we have them */ +#define readq readq +#define writeq writeq +#endif + #ifdef CONFIG_X86_32 # include "io_32.h" #else diff --git a/include/asm-x86/io_32.h b/include/asm-x86/io_32.h index 049e81e797a0..d71be8df9797 100644 --- a/include/asm-x86/io_32.h +++ b/include/asm-x86/io_32.h @@ -149,55 +149,6 @@ extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); #define virt_to_bus virt_to_phys #define bus_to_virt phys_to_virt -/* - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the x86 architecture, we just read/write the - * memory location directly. - */ - -static inline unsigned char readb(const volatile void __iomem *addr) -{ - return *(volatile unsigned char __force *)addr; -} - -static inline unsigned short readw(const volatile void __iomem *addr) -{ - return *(volatile unsigned short __force *)addr; -} - -static inline unsigned int readl(const volatile void __iomem *addr) -{ - return *(volatile unsigned int __force *) addr; -} - -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - -static inline void writeb(unsigned char b, volatile void __iomem *addr) -{ - *(volatile unsigned char __force *)addr = b; -} - -static inline void writew(unsigned short b, volatile void __iomem *addr) -{ - *(volatile unsigned short __force *)addr = b; -} - -static inline void writel(unsigned int b, volatile void __iomem *addr) -{ - *(volatile unsigned int __force *)addr = b; -} -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -#define mmiowb() - static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) { diff --git a/include/asm-x86/io_64.h b/include/asm-x86/io_64.h index 0930bedf9e4d..ddd8058a5026 100644 --- a/include/asm-x86/io_64.h +++ b/include/asm-x86/io_64.h @@ -204,77 +204,6 @@ extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); #define virt_to_bus virt_to_phys #define bus_to_virt phys_to_virt -/* - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the x86 architecture, we just read/write the - * memory location directly. - */ - -static inline __u8 __readb(const volatile void __iomem *addr) -{ - return *(__force volatile __u8 *)addr; -} - -static inline __u16 __readw(const volatile void __iomem *addr) -{ - return *(__force volatile __u16 *)addr; -} - -static __always_inline __u32 __readl(const volatile void __iomem *addr) -{ - return *(__force volatile __u32 *)addr; -} - -static inline __u64 __readq(const volatile void __iomem *addr) -{ - return *(__force volatile __u64 *)addr; -} - -#define readb(x) __readb(x) -#define readw(x) __readw(x) -#define readl(x) __readl(x) -#define readq(x) __readq(x) -#define readb_relaxed(a) readb(a) -#define readw_relaxed(a) readw(a) -#define readl_relaxed(a) readl(a) -#define readq_relaxed(a) readq(a) -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl -#define __raw_readq readq - -#define mmiowb() - -static inline void __writel(__u32 b, volatile void __iomem *addr) -{ - *(__force volatile __u32 *)addr = b; -} - -static inline void __writeq(__u64 b, volatile void __iomem *addr) -{ - *(__force volatile __u64 *)addr = b; -} - -static inline void __writeb(__u8 b, volatile void __iomem *addr) -{ - *(__force volatile __u8 *)addr = b; -} - -static inline void __writew(__u16 b, volatile void __iomem *addr) -{ - *(__force volatile __u16 *)addr = b; -} - -#define writeq(val, addr) __writeq((val), (addr)) -#define writel(val, addr) __writel((val), (addr)) -#define writew(val, addr) __writew((val), (addr)) -#define writeb(val, addr) __writeb((val), (addr)) -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel -#define __raw_writeq writeq - void __memcpy_fromio(void *, unsigned long, unsigned); void __memcpy_toio(unsigned long, const void *, unsigned); diff --git a/include/asm-x86/io_apic.h b/include/asm-x86/io_apic.h index d593e14f0341..8b1f5684842e 100644 --- a/include/asm-x86/io_apic.h +++ b/include/asm-x86/io_apic.h @@ -11,6 +11,15 @@ * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar */ +/* I/O Unit Redirection Table */ +#define IO_APIC_REDIR_VECTOR_MASK 0x000FF +#define IO_APIC_REDIR_DEST_LOGICAL 0x00800 +#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000 +#define IO_APIC_REDIR_SEND_PENDING (1 << 12) +#define IO_APIC_REDIR_REMOTE_IRR (1 << 14) +#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15) +#define IO_APIC_REDIR_MASKED (1 << 16) + /* * The structure of the IO-APIC: */ @@ -112,21 +121,32 @@ extern int nr_ioapic_registers[MAX_IO_APICS]; #define MP_MAX_IOAPIC_PIN 127 -struct mp_ioapic_routing { - int apic_id; - int gsi_base; - int gsi_end; - DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); +struct mp_config_ioapic { + unsigned long mp_apicaddr; + unsigned int mp_apicid; + unsigned char mp_type; + unsigned char mp_apicver; + unsigned char mp_flags; +}; + +struct mp_config_intsrc { + unsigned int mp_dstapic; + unsigned char mp_type; + unsigned char mp_irqtype; + unsigned short mp_irqflag; + unsigned char mp_srcbus; + unsigned char mp_srcbusirq; + unsigned char mp_dstirq; }; /* I/O APIC entries */ -extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; +extern struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; /* # of MP IRQ source entries */ extern int mp_irq_entries; /* MP IRQ source entries */ -extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; +extern struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; /* non-0 if default (table-less) MP configuration */ extern int mpc_default_type; @@ -137,6 +157,9 @@ extern int sis_apic_bug; /* 1 if "noapic" boot option passed */ extern int skip_ioapic_setup; +/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */ +extern int timer_through_8259; + static inline void disable_ioapic_setup(void) { skip_ioapic_setup = 1; @@ -162,6 +185,7 @@ extern void ioapic_init_mappings(void); #else /* !CONFIG_X86_IO_APIC */ #define io_apic_assign_pci_irqs 0 +static const int timer_through_8259 = 0; #endif #endif diff --git a/include/asm-x86/ipi.h b/include/asm-x86/ipi.h index ecc80f341f37..bb1c09f7a76c 100644 --- a/include/asm-x86/ipi.h +++ b/include/asm-x86/ipi.h @@ -20,6 +20,7 @@ #include <asm/hw_irq.h> #include <asm/apic.h> +#include <asm/smp.h> /* * the following functions deal with sending IPIs between CPUs. @@ -121,7 +122,7 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector) * - mbligh */ local_irq_save(flags); - for_each_cpu_mask(query_cpu, mask) { + for_each_cpu_mask_nr(query_cpu, mask) { __send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, query_cpu), vector, APIC_DEST_PHYSICAL); } diff --git a/include/asm-x86/irq.h b/include/asm-x86/irq.h index 7ba905465a53..1a2925757317 100644 --- a/include/asm-x86/irq.h +++ b/include/asm-x86/irq.h @@ -1,5 +1,50 @@ -#ifdef CONFIG_X86_32 -# include "irq_32.h" +#ifndef _ASM_IRQ_H +#define _ASM_IRQ_H +/* + * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar + * + * IRQ/IPI changes taken from work by Thomas Radke + * <tomsoft@informatik.tu-chemnitz.de> + */ + +#include <asm/apicdef.h> +#include <asm/irq_vectors.h> + +static inline int irq_canonicalize(int irq) +{ + return ((irq == 2) ? 9 : irq); +} + +#ifdef CONFIG_X86_LOCAL_APIC +# define ARCH_HAS_NMI_WATCHDOG +#endif + +#ifdef CONFIG_4KSTACKS + extern void irq_ctx_init(int cpu); + extern void irq_ctx_exit(int cpu); +# define __ARCH_HAS_DO_SOFTIRQ #else -# include "irq_64.h" +# define irq_ctx_init(cpu) do { } while (0) +# define irq_ctx_exit(cpu) do { } while (0) +# ifdef CONFIG_X86_64 +# define __ARCH_HAS_DO_SOFTIRQ +# endif +#endif + +#ifdef CONFIG_IRQBALANCE +extern int irqbalance_disable(char *str); +#endif + +#ifdef CONFIG_HOTPLUG_CPU +#include <linux/cpumask.h> +extern void fixup_irqs(cpumask_t map); #endif + +extern unsigned int do_IRQ(struct pt_regs *regs); +extern void init_IRQ(void); +extern void native_init_IRQ(void); + +/* Interrupt vector management */ +extern DECLARE_BITMAP(used_vectors, NR_VECTORS); + +#endif /* _ASM_IRQ_H */ diff --git a/include/asm-x86/irq_32.h b/include/asm-x86/irq_32.h deleted file mode 100644 index 0b79f3185243..000000000000 --- a/include/asm-x86/irq_32.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ASM_IRQ_H -#define _ASM_IRQ_H - -/* - * linux/include/asm/irq.h - * - * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar - * - * IRQ/IPI changes taken from work by Thomas Radke - * <tomsoft@informatik.tu-chemnitz.de> - */ - -#include <linux/sched.h> -/* include comes from machine specific directory */ -#include "irq_vectors.h" -#include <asm/thread_info.h> - -static inline int irq_canonicalize(int irq) -{ - return ((irq == 2) ? 9 : irq); -} - -#ifdef CONFIG_X86_LOCAL_APIC -# define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */ -#endif - -#ifdef CONFIG_4KSTACKS - extern void irq_ctx_init(int cpu); - extern void irq_ctx_exit(int cpu); -# define __ARCH_HAS_DO_SOFTIRQ -#else -# define irq_ctx_init(cpu) do { } while (0) -# define irq_ctx_exit(cpu) do { } while (0) -#endif - -#ifdef CONFIG_IRQBALANCE -extern int irqbalance_disable(char *str); -#endif - -#ifdef CONFIG_HOTPLUG_CPU -extern void fixup_irqs(cpumask_t map); -#endif - -unsigned int do_IRQ(struct pt_regs *regs); -void init_IRQ(void); -void __init native_init_IRQ(void); - -/* Interrupt vector management */ -extern DECLARE_BITMAP(used_vectors, NR_VECTORS); - -#endif /* _ASM_IRQ_H */ diff --git a/include/asm-x86/irq_64.h b/include/asm-x86/irq_64.h deleted file mode 100644 index 083d35a62c94..000000000000 --- a/include/asm-x86/irq_64.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _ASM_IRQ_H -#define _ASM_IRQ_H - -/* - * linux/include/asm/irq.h - * - * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar - * - * IRQ/IPI changes taken from work by Thomas Radke - * <tomsoft@informatik.tu-chemnitz.de> - */ - -#define TIMER_IRQ 0 - -/* - * 16 8259A IRQ's, 208 potential APIC interrupt sources. - * Right now the APIC is mostly only used for SMP. - * 256 vectors is an architectural limit. (we can have - * more than 256 devices theoretically, but they will - * have to use shared interrupts) - * Since vectors 0x00-0x1f are used/reserved for the CPU, - * the usable vector space is 0x20-0xff (224 vectors) - */ - -/* - * The maximum number of vectors supported by x86_64 processors - * is limited to 256. For processors other than x86_64, NR_VECTORS - * should be changed accordingly. - */ -#define NR_VECTORS 256 - -#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */ - -#define NR_IRQS (NR_VECTORS + (32 * NR_CPUS)) -#define NR_IRQ_VECTORS NR_IRQS - -static inline int irq_canonicalize(int irq) -{ - return ((irq == 2) ? 9 : irq); -} - -#define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */ - -#ifdef CONFIG_HOTPLUG_CPU -#include <linux/cpumask.h> -extern void fixup_irqs(cpumask_t map); -#endif - -#define __ARCH_HAS_DO_SOFTIRQ 1 - -#endif /* _ASM_IRQ_H */ diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h new file mode 100644 index 000000000000..b58581e2e24e --- /dev/null +++ b/include/asm-x86/irq_vectors.h @@ -0,0 +1,169 @@ +#ifndef _ASM_IRQ_VECTORS_H +#define _ASM_IRQ_VECTORS_H + +#include <linux/threads.h> + +#define NMI_VECTOR 0x02 + +/* + * IDT vectors usable for external interrupt sources start + * at 0x20: + */ +#define FIRST_EXTERNAL_VECTOR 0x20 + +#ifdef CONFIG_X86_32 +# define SYSCALL_VECTOR 0x80 +#else +# define IA32_SYSCALL_VECTOR 0x80 +#endif + +/* + * Reserve the lowest usable priority level 0x20 - 0x2f for triggering + * cleanup after irq migration on 64 bit. + */ +#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR + +/* + * Vectors 0x20-0x2f are used for ISA interrupts on 32 bit. + * Vectors 0x30-0x3f are used for ISA interrupts on 64 bit. + */ +#ifdef CONFIG_X86_32 +#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR) +#else +#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10) +#endif +#define IRQ1_VECTOR (IRQ0_VECTOR + 1) +#define IRQ2_VECTOR (IRQ0_VECTOR + 2) +#define IRQ3_VECTOR (IRQ0_VECTOR + 3) +#define IRQ4_VECTOR (IRQ0_VECTOR + 4) +#define IRQ5_VECTOR (IRQ0_VECTOR + 5) +#define IRQ6_VECTOR (IRQ0_VECTOR + 6) +#define IRQ7_VECTOR (IRQ0_VECTOR + 7) +#define IRQ8_VECTOR (IRQ0_VECTOR + 8) +#define IRQ9_VECTOR (IRQ0_VECTOR + 9) +#define IRQ10_VECTOR (IRQ0_VECTOR + 10) +#define IRQ11_VECTOR (IRQ0_VECTOR + 11) +#define IRQ12_VECTOR (IRQ0_VECTOR + 12) +#define IRQ13_VECTOR (IRQ0_VECTOR + 13) +#define IRQ14_VECTOR (IRQ0_VECTOR + 14) +#define IRQ15_VECTOR (IRQ0_VECTOR + 15) + +/* + * Special IRQ vectors used by the SMP architecture, 0xf0-0xff + * + * some of the following vectors are 'rare', they are merged + * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. + * TLB, reschedule and local APIC vectors are performance-critical. + * + * Vectors 0xf0-0xfa are free (reserved for future Linux use). + */ +#ifdef CONFIG_X86_32 + +# define SPURIOUS_APIC_VECTOR 0xff +# define ERROR_APIC_VECTOR 0xfe +# define INVALIDATE_TLB_VECTOR 0xfd +# define RESCHEDULE_VECTOR 0xfc +# define CALL_FUNCTION_VECTOR 0xfb +# define THERMAL_APIC_VECTOR 0xf0 + +#else + +#define SPURIOUS_APIC_VECTOR 0xff +#define ERROR_APIC_VECTOR 0xfe +#define RESCHEDULE_VECTOR 0xfd +#define CALL_FUNCTION_VECTOR 0xfc +#define THERMAL_APIC_VECTOR 0xfa +#define THRESHOLD_APIC_VECTOR 0xf9 +#define INVALIDATE_TLB_VECTOR_END 0xf7 +#define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */ + +#define NUM_INVALIDATE_TLB_VECTORS 8 + +#endif + +/* + * Local APIC timer IRQ vector is on a different priority level, + * to work around the 'lost local interrupt if more than 2 IRQ + * sources per level' errata. + */ +#define LOCAL_TIMER_VECTOR 0xef + +/* + * First APIC vector available to drivers: (vectors 0x30-0xee) we + * start at 0x31(0x41) to spread out vectors evenly between priority + * levels. (0x80 is the syscall vector) + */ +#ifdef CONFIG_X86_32 +# define FIRST_DEVICE_VECTOR 0x31 +#else +# define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2) +#endif + +#define NR_VECTORS 256 + +#define FPU_IRQ 13 + +#define FIRST_VM86_IRQ 3 +#define LAST_VM86_IRQ 15 +#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15) + +#if !defined(CONFIG_X86_VISWS) && !defined(CONFIG_X86_VOYAGER) + +# if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) + +# define NR_IRQS 224 + +# if (224 >= 32 * NR_CPUS) +# define NR_IRQ_VECTORS NR_IRQS +# else +# define NR_IRQ_VECTORS (32 * NR_CPUS) +# endif + +# else /* IO_APIC || PARAVIRT */ + +# define NR_IRQS 16 +# define NR_IRQ_VECTORS NR_IRQS + +# endif + +#else /* !VISWS && !VOYAGER */ + +# define NR_IRQS 224 +# define NR_IRQ_VECTORS NR_IRQS + +#endif /* VISWS */ + +/* Voyager specific defines */ +/* These define the CPIs we use in linux */ +#define VIC_CPI_LEVEL0 0 +#define VIC_CPI_LEVEL1 1 +/* now the fake CPIs */ +#define VIC_TIMER_CPI 2 +#define VIC_INVALIDATE_CPI 3 +#define VIC_RESCHEDULE_CPI 4 +#define VIC_ENABLE_IRQ_CPI 5 +#define VIC_CALL_FUNCTION_CPI 6 + +/* Now the QIC CPIs: Since we don't need the two initial levels, + * these are 2 less than the VIC CPIs */ +#define QIC_CPI_OFFSET 1 +#define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET) +#define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET) +#define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET) +#define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET) +#define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET) + +#define VIC_START_FAKE_CPI VIC_TIMER_CPI +#define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_CPI + +/* this is the SYS_INT CPI. */ +#define VIC_SYS_INT 8 +#define VIC_CMN_INT 15 + +/* This is the boot CPI for alternate processors. It gets overwritten + * by the above once the system has activated all available processors */ +#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0 +#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8) + + +#endif /* _ASM_IRQ_VECTORS_H */ diff --git a/include/asm-x86/irqflags.h b/include/asm-x86/irqflags.h index c242527f970e..24d71b1eb189 100644 --- a/include/asm-x86/irqflags.h +++ b/include/asm-x86/irqflags.h @@ -179,8 +179,6 @@ static inline void trace_hardirqs_fixup(void) * have a reliable stack. x86_64 only. */ #define SWAPGS_UNSAFE_STACK swapgs -#define ARCH_TRACE_IRQS_ON call trace_hardirqs_on_thunk -#define ARCH_TRACE_IRQS_OFF call trace_hardirqs_off_thunk #define ARCH_LOCKDEP_SYS_EXIT call lockdep_sys_exit_thunk #define ARCH_LOCKDEP_SYS_EXIT_IRQ \ TRACE_IRQS_ON; \ @@ -192,24 +190,6 @@ static inline void trace_hardirqs_fixup(void) TRACE_IRQS_OFF; #else -#define ARCH_TRACE_IRQS_ON \ - pushl %eax; \ - pushl %ecx; \ - pushl %edx; \ - call trace_hardirqs_on; \ - popl %edx; \ - popl %ecx; \ - popl %eax; - -#define ARCH_TRACE_IRQS_OFF \ - pushl %eax; \ - pushl %ecx; \ - pushl %edx; \ - call trace_hardirqs_off; \ - popl %edx; \ - popl %ecx; \ - popl %eax; - #define ARCH_LOCKDEP_SYS_EXIT \ pushl %eax; \ pushl %ecx; \ @@ -223,8 +203,8 @@ static inline void trace_hardirqs_fixup(void) #endif #ifdef CONFIG_TRACE_IRQFLAGS -# define TRACE_IRQS_ON ARCH_TRACE_IRQS_ON -# define TRACE_IRQS_OFF ARCH_TRACE_IRQS_OFF +# define TRACE_IRQS_ON call trace_hardirqs_on_thunk; +# define TRACE_IRQS_OFF call trace_hardirqs_off_thunk; #else # define TRACE_IRQS_ON # define TRACE_IRQS_OFF diff --git a/include/asm-x86/kvm.h b/include/asm-x86/kvm.h index 80eefef2cc76..6f1840812e59 100644 --- a/include/asm-x86/kvm.h +++ b/include/asm-x86/kvm.h @@ -228,5 +228,6 @@ struct kvm_pit_state { #define KVM_TRC_CLTS (KVM_TRC_HANDLER + 0x12) #define KVM_TRC_LMSW (KVM_TRC_HANDLER + 0x13) #define KVM_TRC_APIC_ACCESS (KVM_TRC_HANDLER + 0x14) +#define KVM_TRC_TDP_FAULT (KVM_TRC_HANDLER + 0x15) #endif diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h index 1d8cd01fa514..851184ddff81 100644 --- a/include/asm-x86/kvm_host.h +++ b/include/asm-x86/kvm_host.h @@ -26,6 +26,7 @@ #define KVM_PRIVATE_MEM_SLOTS 4 #define KVM_PIO_PAGE_OFFSET 1 +#define KVM_COALESCED_MMIO_PAGE_OFFSET 2 #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) @@ -78,6 +79,7 @@ #define KVM_MIN_FREE_MMU_PAGES 5 #define KVM_REFILL_PAGES 25 #define KVM_MAX_CPUID_ENTRIES 40 +#define KVM_NR_VAR_MTRR 8 extern spinlock_t kvm_lock; extern struct list_head vm_list; @@ -108,12 +110,12 @@ enum { }; enum { + VCPU_SREG_ES, VCPU_SREG_CS, + VCPU_SREG_SS, VCPU_SREG_DS, - VCPU_SREG_ES, VCPU_SREG_FS, VCPU_SREG_GS, - VCPU_SREG_SS, VCPU_SREG_TR, VCPU_SREG_LDTR, }; @@ -242,6 +244,7 @@ struct kvm_vcpu_arch { gfn_t last_pt_write_gfn; int last_pt_write_count; u64 *last_pte_updated; + gfn_t last_pte_gfn; struct { gfn_t gfn; /* presumed gfn during guest pte update */ @@ -285,6 +288,10 @@ struct kvm_vcpu_arch { struct kvm_vcpu_time_info hv_clock; unsigned int time_offset; struct page *time_page; + + bool nmi_pending; + + u64 mtrr[0x100]; }; struct kvm_mem_alias { @@ -342,6 +349,7 @@ struct kvm_vcpu_stat { u32 mmio_exits; u32 signal_exits; u32 irq_window_exits; + u32 nmi_window_exits; u32 halt_exits; u32 halt_wakeup; u32 request_irq_exits; @@ -377,7 +385,6 @@ struct kvm_x86_ops { void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); void (*vcpu_put)(struct kvm_vcpu *vcpu); - void (*vcpu_decache)(struct kvm_vcpu *vcpu); int (*set_guest_debug)(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg); @@ -495,6 +502,10 @@ int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value); +void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); +int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, + int type_bits, int seg); + int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason); void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); @@ -513,6 +524,8 @@ void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long cr2, u32 error_code); +void kvm_inject_nmi(struct kvm_vcpu *vcpu); + void fx_init(struct kvm_vcpu *vcpu); int emulator_read_std(unsigned long addr, @@ -689,4 +702,28 @@ enum { trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \ vcpu, 0, 0, 0, 0, 0, 0) +#ifdef CONFIG_64BIT +#define KVM_EX_ENTRY ".quad" +#else +#define KVM_EX_ENTRY ".long" +#endif + +/* + * Hardware virtualization extension instructions may fault if a + * reboot turns off virtualization while processes are running. + * Trap the fault and ignore the instruction if that happens. + */ +asmlinkage void kvm_handle_fault_on_reboot(void); + +#define __kvm_handle_fault_on_reboot(insn) \ + "666: " insn "\n\t" \ + ".pushsection .text.fixup, \"ax\" \n" \ + "667: \n\t" \ + "push $666b \n\t" \ + "jmp kvm_handle_fault_on_reboot \n\t" \ + ".popsection \n\t" \ + ".pushsection __ex_table, \"a\" \n\t" \ + KVM_EX_ENTRY " 666b, 667b \n\t" \ + ".popsection" + #endif diff --git a/include/asm-x86/mach-default/irq_vectors.h b/include/asm-x86/mach-default/irq_vectors.h deleted file mode 100644 index 881c63ca61ad..000000000000 --- a/include/asm-x86/mach-default/irq_vectors.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file should contain #defines for all of the interrupt vector - * numbers used by this architecture. - * - * In addition, there are some standard defines: - * - * FIRST_EXTERNAL_VECTOR: - * The first free place for external interrupts - * - * SYSCALL_VECTOR: - * The IRQ vector a syscall makes the user to kernel transition - * under. - * - * TIMER_IRQ: - * The IRQ number the timer interrupt comes in at. - * - * NR_IRQS: - * The total number of interrupt vectors (including all the - * architecture specific interrupts) needed. - * - */ -#ifndef _ASM_IRQ_VECTORS_H -#define _ASM_IRQ_VECTORS_H - -/* - * IDT vectors usable for external interrupt sources start - * at 0x20: - */ -#define FIRST_EXTERNAL_VECTOR 0x20 - -#define SYSCALL_VECTOR 0x80 - -/* - * Vectors 0x20-0x2f are used for ISA interrupts. - */ - -/* - * Special IRQ vectors used by the SMP architecture, 0xf0-0xff - * - * some of the following vectors are 'rare', they are merged - * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. - * TLB, reschedule and local APIC vectors are performance-critical. - * - * Vectors 0xf0-0xfa are free (reserved for future Linux use). - */ -#define SPURIOUS_APIC_VECTOR 0xff -#define ERROR_APIC_VECTOR 0xfe -#define INVALIDATE_TLB_VECTOR 0xfd -#define RESCHEDULE_VECTOR 0xfc -#define CALL_FUNCTION_VECTOR 0xfb - -#define THERMAL_APIC_VECTOR 0xf0 -/* - * Local APIC timer IRQ vector is on a different priority level, - * to work around the 'lost local interrupt if more than 2 IRQ - * sources per level' errata. - */ -#define LOCAL_TIMER_VECTOR 0xef - -/* - * First APIC vector available to drivers: (vectors 0x30-0xee) - * we start at 0x31 to spread out vectors evenly between priority - * levels. (0x80 is the syscall vector) - */ -#define FIRST_DEVICE_VECTOR 0x31 -#define FIRST_SYSTEM_VECTOR 0xef - -#define TIMER_IRQ 0 - -/* - * 16 8259A IRQ's, 208 potential APIC interrupt sources. - * Right now the APIC is mostly only used for SMP. - * 256 vectors is an architectural limit. (we can have - * more than 256 devices theoretically, but they will - * have to use shared interrupts) - * Since vectors 0x00-0x1f are used/reserved for the CPU, - * the usable vector space is 0x20-0xff (224 vectors) - */ - -/* - * The maximum number of vectors supported by i386 processors - * is limited to 256. For processors other than i386, NR_VECTORS - * should be changed accordingly. - */ -#define NR_VECTORS 256 - -#include "irq_vectors_limits.h" - -#define FPU_IRQ 13 - -#define FIRST_VM86_IRQ 3 -#define LAST_VM86_IRQ 15 -#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15) - - -#endif /* _ASM_IRQ_VECTORS_H */ diff --git a/include/asm-x86/mach-default/irq_vectors_limits.h b/include/asm-x86/mach-default/irq_vectors_limits.h deleted file mode 100644 index a90c7a60109f..000000000000 --- a/include/asm-x86/mach-default/irq_vectors_limits.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _ASM_IRQ_VECTORS_LIMITS_H -#define _ASM_IRQ_VECTORS_LIMITS_H - -#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) -#define NR_IRQS 224 -# if (224 >= 32 * NR_CPUS) -# define NR_IRQ_VECTORS NR_IRQS -# else -# define NR_IRQ_VECTORS (32 * NR_CPUS) -# endif -#else -#define NR_IRQS 16 -#define NR_IRQ_VECTORS NR_IRQS -#endif - -#endif /* _ASM_IRQ_VECTORS_LIMITS_H */ diff --git a/include/asm-x86/mach-default/smpboot_hooks.h b/include/asm-x86/mach-default/smpboot_hooks.h index 56d0e1fa0258..b63c52182006 100644 --- a/include/asm-x86/mach-default/smpboot_hooks.h +++ b/include/asm-x86/mach-default/smpboot_hooks.h @@ -41,8 +41,10 @@ static inline void __init smpboot_setup_io_apic(void) */ if (!skip_ioapic_setup && nr_ioapics) setup_IO_APIC(); - else + else { nr_ioapics = 0; + localise_nmi_watchdog(); + } } static inline void smpboot_clear_io_apic(void) diff --git a/include/asm-x86/mach-generic/mach_mpparse.h b/include/asm-x86/mach-generic/mach_mpparse.h index 0d0b5ba2e9d1..586cadbf3787 100644 --- a/include/asm-x86/mach-generic/mach_mpparse.h +++ b/include/asm-x86/mach-generic/mach_mpparse.h @@ -1,7 +1,10 @@ #ifndef _MACH_MPPARSE_H #define _MACH_MPPARSE_H 1 -int mps_oem_check(struct mp_config_table *mpc, char *oem, char *productid); -int acpi_madt_oem_check(char *oem_id, char *oem_table_id); + +extern int mps_oem_check(struct mp_config_table *mpc, char *oem, + char *productid); + +extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id); #endif diff --git a/include/asm-x86/mach-numaq/mach_apic.h b/include/asm-x86/mach-numaq/mach_apic.h index 75a56e5afbe7..d802465e026a 100644 --- a/include/asm-x86/mach-numaq/mach_apic.h +++ b/include/asm-x86/mach-numaq/mach_apic.h @@ -20,8 +20,14 @@ static inline cpumask_t target_cpus(void) #define INT_DELIVERY_MODE dest_LowestPrio #define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */ -#define check_apicid_used(bitmap, apicid) physid_isset(apicid, bitmap) -#define check_apicid_present(bit) physid_isset(bit, phys_cpu_present_map) +static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) +{ + return physid_isset(apicid, bitmap); +} +static inline unsigned long check_apicid_present(int bit) +{ + return physid_isset(bit, phys_cpu_present_map); +} #define apicid_cluster(apicid) (apicid & 0xF0) static inline int apic_id_registered(void) @@ -77,11 +83,6 @@ static inline int cpu_present_to_apicid(int mps_cpu) return BAD_APICID; } -static inline int generate_logical_apicid(int quad, int phys_apicid) -{ - return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1); -} - static inline int apicid_to_node(int logical_apicid) { return logical_apicid >> 4; @@ -95,30 +96,6 @@ static inline physid_mask_t apicid_to_cpu_present(int logical_apicid) return physid_mask_of_physid(cpu + 4*node); } -struct mpc_config_translation { - unsigned char mpc_type; - unsigned char trans_len; - unsigned char trans_type; - unsigned char trans_quad; - unsigned char trans_global; - unsigned char trans_local; - unsigned short trans_reserved; -}; - -static inline int mpc_apic_id(struct mpc_config_processor *m, - struct mpc_config_translation *translation_record) -{ - int quad = translation_record->trans_quad; - int logical_apicid = generate_logical_apicid(quad, m->mpc_apicid); - - printk("Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n", - m->mpc_apicid, - (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, - (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, - m->mpc_apicver, quad, logical_apicid); - return logical_apicid; -} - extern void *xquad_portio; static inline void setup_portio_remap(void) diff --git a/include/asm-x86/mach-numaq/mach_mpparse.h b/include/asm-x86/mach-numaq/mach_mpparse.h index 459b12401187..626aef6b155f 100644 --- a/include/asm-x86/mach-numaq/mach_mpparse.h +++ b/include/asm-x86/mach-numaq/mach_mpparse.h @@ -1,14 +1,7 @@ #ifndef __ASM_MACH_MPPARSE_H #define __ASM_MACH_MPPARSE_H -extern void mpc_oem_bus_info(struct mpc_config_bus *m, char *name, - struct mpc_config_translation *translation); -extern void mpc_oem_pci_bus(struct mpc_config_bus *m, - struct mpc_config_translation *translation); - -/* Hook from generic ACPI tables.c */ -static inline void acpi_madt_oem_check(char *oem_id, char *oem_table_id) -{ -} +extern void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem, + char *productid); #endif /* __ASM_MACH_MPPARSE_H */ diff --git a/include/asm-x86/mach-visws/irq_vectors.h b/include/asm-x86/mach-visws/irq_vectors.h deleted file mode 100644 index cb572d8db505..000000000000 --- a/include/asm-x86/mach-visws/irq_vectors.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef _ASM_IRQ_VECTORS_H -#define _ASM_IRQ_VECTORS_H - -/* - * IDT vectors usable for external interrupt sources start - * at 0x20: - */ -#define FIRST_EXTERNAL_VECTOR 0x20 - -#define SYSCALL_VECTOR 0x80 - -/* - * Vectors 0x20-0x2f are used for ISA interrupts. - */ - -/* - * Special IRQ vectors used by the SMP architecture, 0xf0-0xff - * - * some of the following vectors are 'rare', they are merged - * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. - * TLB, reschedule and local APIC vectors are performance-critical. - * - * Vectors 0xf0-0xfa are free (reserved for future Linux use). - */ -#define SPURIOUS_APIC_VECTOR 0xff -#define ERROR_APIC_VECTOR 0xfe -#define INVALIDATE_TLB_VECTOR 0xfd -#define RESCHEDULE_VECTOR 0xfc -#define CALL_FUNCTION_VECTOR 0xfb - -#define THERMAL_APIC_VECTOR 0xf0 -/* - * Local APIC timer IRQ vector is on a different priority level, - * to work around the 'lost local interrupt if more than 2 IRQ - * sources per level' errata. - */ -#define LOCAL_TIMER_VECTOR 0xef - -/* - * First APIC vector available to drivers: (vectors 0x30-0xee) - * we start at 0x31 to spread out vectors evenly between priority - * levels. (0x80 is the syscall vector) - */ -#define FIRST_DEVICE_VECTOR 0x31 -#define FIRST_SYSTEM_VECTOR 0xef - -#define TIMER_IRQ 0 - -/* - * IRQ definitions - */ -#define NR_VECTORS 256 -#define NR_IRQS 224 -#define NR_IRQ_VECTORS NR_IRQS - -#define FPU_IRQ 13 - -#define FIRST_VM86_IRQ 3 -#define LAST_VM86_IRQ 15 -#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15) - -#endif /* _ASM_IRQ_VECTORS_H */ diff --git a/include/asm-x86/mach-voyager/irq_vectors.h b/include/asm-x86/mach-voyager/irq_vectors.h deleted file mode 100644 index 165421f5821c..000000000000 --- a/include/asm-x86/mach-voyager/irq_vectors.h +++ /dev/null @@ -1,79 +0,0 @@ -/* -*- mode: c; c-basic-offset: 8 -*- */ - -/* Copyright (C) 2002 - * - * Author: James.Bottomley@HansenPartnership.com - * - * linux/arch/i386/voyager/irq_vectors.h - * - * This file provides definitions for the VIC and QIC CPIs - */ - -#ifndef _ASM_IRQ_VECTORS_H -#define _ASM_IRQ_VECTORS_H - -/* - * IDT vectors usable for external interrupt sources start - * at 0x20: - */ -#define FIRST_EXTERNAL_VECTOR 0x20 - -#define SYSCALL_VECTOR 0x80 - -/* - * Vectors 0x20-0x2f are used for ISA interrupts. - */ - -/* These define the CPIs we use in linux */ -#define VIC_CPI_LEVEL0 0 -#define VIC_CPI_LEVEL1 1 -/* now the fake CPIs */ -#define VIC_TIMER_CPI 2 -#define VIC_INVALIDATE_CPI 3 -#define VIC_RESCHEDULE_CPI 4 -#define VIC_ENABLE_IRQ_CPI 5 -#define VIC_CALL_FUNCTION_CPI 6 - -/* Now the QIC CPIs: Since we don't need the two initial levels, - * these are 2 less than the VIC CPIs */ -#define QIC_CPI_OFFSET 1 -#define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET) -#define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET) -#define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET) -#define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET) -#define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET) - -#define VIC_START_FAKE_CPI VIC_TIMER_CPI -#define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_CPI - -/* this is the SYS_INT CPI. */ -#define VIC_SYS_INT 8 -#define VIC_CMN_INT 15 - -/* This is the boot CPI for alternate processors. It gets overwritten - * by the above once the system has activated all available processors */ -#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0 -#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8) - -#define NR_VECTORS 256 -#define NR_IRQS 224 -#define NR_IRQ_VECTORS NR_IRQS - -#define FPU_IRQ 13 - -#define FIRST_VM86_IRQ 3 -#define LAST_VM86_IRQ 15 -#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15) - -#ifndef __ASSEMBLY__ -extern asmlinkage void vic_cpi_interrupt(void); -extern asmlinkage void vic_sys_interrupt(void); -extern asmlinkage void vic_cmn_interrupt(void); -extern asmlinkage void qic_timer_interrupt(void); -extern asmlinkage void qic_invalidate_interrupt(void); -extern asmlinkage void qic_reschedule_interrupt(void); -extern asmlinkage void qic_enable_irq_interrupt(void); -extern asmlinkage void qic_call_function_interrupt(void); -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_IRQ_VECTORS_H */ diff --git a/include/asm-x86/mmconfig.h b/include/asm-x86/mmconfig.h new file mode 100644 index 000000000000..95beda07c6fa --- /dev/null +++ b/include/asm-x86/mmconfig.h @@ -0,0 +1,12 @@ +#ifndef _ASM_MMCONFIG_H +#define _ASM_MMCONFIG_H + +#ifdef CONFIG_PCI_MMCONFIG +extern void __cpuinit fam10h_check_enable_mmcfg(void); +extern void __init check_enable_amd_mmconf_dmi(void); +#else +static inline void fam10h_check_enable_mmcfg(void) { } +static inline void check_enable_amd_mmconf_dmi(void) { } +#endif + +#endif diff --git a/include/asm-x86/mmzone_32.h b/include/asm-x86/mmzone_32.h index cb2cad0b65a7..b2298a227567 100644 --- a/include/asm-x86/mmzone_32.h +++ b/include/asm-x86/mmzone_32.h @@ -12,11 +12,9 @@ extern struct pglist_data *node_data[]; #define NODE_DATA(nid) (node_data[nid]) -#ifdef CONFIG_X86_NUMAQ - #include <asm/numaq.h> -#elif defined(CONFIG_ACPI_SRAT)/* summit or generic arch */ - #include <asm/srat.h> -#endif +#include <asm/numaq.h> +/* summit or generic arch */ +#include <asm/srat.h> extern int get_memcfg_numa_flat(void); /* @@ -26,28 +24,20 @@ extern int get_memcfg_numa_flat(void); */ static inline void get_memcfg_numa(void) { -#ifdef CONFIG_X86_NUMAQ + if (get_memcfg_numaq()) return; -#elif defined(CONFIG_ACPI_SRAT) if (get_memcfg_from_srat()) return; -#endif - get_memcfg_numa_flat(); } extern int early_pfn_to_nid(unsigned long pfn); -extern void numa_kva_reserve(void); #else /* !CONFIG_NUMA */ #define get_memcfg_numa get_memcfg_numa_flat -#define get_zholes_size(n) (0) -static inline void numa_kva_reserve(void) -{ -} #endif /* CONFIG_NUMA */ #ifdef CONFIG_DISCONTIGMEM @@ -55,14 +45,14 @@ static inline void numa_kva_reserve(void) /* * generic node memory support, the following assumptions apply: * - * 1) memory comes in 256Mb contigious chunks which are either present or not + * 1) memory comes in 64Mb contigious chunks which are either present or not * 2) we will not have more than 64Gb in total * * for now assume that 64Gb is max amount of RAM for whole system * 64Gb / 4096bytes/page = 16777216 pages */ #define MAX_NR_PAGES 16777216 -#define MAX_ELEMENTS 256 +#define MAX_ELEMENTS 1024 #define PAGES_PER_ELEMENT (MAX_NR_PAGES/MAX_ELEMENTS) extern s8 physnode_map[]; @@ -87,9 +77,6 @@ static inline int pfn_to_nid(unsigned long pfn) __pgdat->node_start_pfn + __pgdat->node_spanned_pages; \ }) -#ifdef CONFIG_X86_NUMAQ /* we have contiguous memory on NUMA-Q */ -#define pfn_valid(pfn) ((pfn) < num_physpages) -#else static inline int pfn_valid(int pfn) { int nid = pfn_to_nid(pfn); @@ -98,7 +85,6 @@ static inline int pfn_valid(int pfn) return (pfn < node_end_pfn(nid)); return 0; } -#endif /* CONFIG_X86_NUMAQ */ #endif /* CONFIG_DISCONTIGMEM */ diff --git a/include/asm-x86/mpspec.h b/include/asm-x86/mpspec.h index 57a991b9c053..b8ba37496e2d 100644 --- a/include/asm-x86/mpspec.h +++ b/include/asm-x86/mpspec.h @@ -13,6 +13,12 @@ extern int apic_version[MAX_APICS]; extern u8 apicid_2_node[]; extern int pic_mode; +#ifdef CONFIG_X86_NUMAQ +extern int mp_bus_id_to_node[MAX_MP_BUSSES]; +extern int mp_bus_id_to_local[MAX_MP_BUSSES]; +extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; +#endif + #define MAX_APICID 256 #else @@ -21,26 +27,30 @@ extern int pic_mode; /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) +#endif + extern void early_find_smp_config(void); extern void early_get_smp_config(void); -#endif - #if defined(CONFIG_MCA) || defined(CONFIG_EISA) extern int mp_bus_id_to_type[MAX_MP_BUSSES]; #endif extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); -extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES]; - extern unsigned int boot_cpu_physical_apicid; +extern unsigned int max_physical_apicid; extern int smp_found_config; extern int mpc_default_type; extern unsigned long mp_lapic_addr; extern void find_smp_config(void); extern void get_smp_config(void); +#ifdef CONFIG_X86_MPPARSE +extern void early_reserve_e820_mpc_new(void); +#else +static inline void early_reserve_e820_mpc_new(void) { } +#endif void __cpuinit generic_processor_info(int apicid, int version); #ifdef CONFIG_ACPI @@ -49,6 +59,18 @@ extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi); extern void mp_config_acpi_legacy_irqs(void); extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low); +extern void MP_intsrc_info(struct mpc_config_intsrc *m); +#ifdef CONFIG_X86_IO_APIC +extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, + u32 gsi, int triggering, int polarity); +#else +static inline int +mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, + u32 gsi, int triggering, int polarity) +{ + return 0; +} +#endif #endif /* CONFIG_ACPI */ #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h index 09413ad39d3c..44bce773012e 100644 --- a/include/asm-x86/msr-index.h +++ b/include/asm-x86/msr-index.h @@ -111,7 +111,9 @@ #define MSR_K8_TOP_MEM2 0xc001001d #define MSR_K8_SYSCFG 0xc0010010 #define MSR_K8_HWCR 0xc0010015 -#define MSR_K8_ENABLE_C1E 0xc0010055 +#define MSR_K8_INT_PENDING_MSG 0xc0010055 +/* C1E active bits in int pending message */ +#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 #define MSR_K8_TSEG_ADDR 0xc0010112 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ diff --git a/include/asm-x86/nmi.h b/include/asm-x86/nmi.h index 1e363021e72f..28a7f4e4fd4a 100644 --- a/include/asm-x86/nmi.h +++ b/include/asm-x86/nmi.h @@ -38,15 +38,12 @@ static inline void unset_nmi_pm_callback(struct pm_dev *dev) #ifdef CONFIG_X86_64 extern void default_do_nmi(struct pt_regs *); -extern void die_nmi(char *str, struct pt_regs *regs, int do_panic); -extern void nmi_watchdog_default(void); -#else -#define nmi_watchdog_default() do {} while (0) #endif +extern void die_nmi(char *str, struct pt_regs *regs, int do_panic); +extern void nmi_watchdog_default(void); extern int check_nmi_watchdog(void); extern int nmi_watchdog_enabled; -extern int unknown_nmi_panic; extern int avail_to_resrv_perfctr_nmi_bit(unsigned int); extern int avail_to_resrv_perfctr_nmi(unsigned int); extern int reserve_perfctr_nmi(unsigned int); @@ -78,6 +75,11 @@ extern int unknown_nmi_panic; void __trigger_all_cpu_backtrace(void); #define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace() +static inline void localise_nmi_watchdog(void) +{ + if (nmi_watchdog == NMI_IO_APIC) + nmi_watchdog = NMI_LOCAL_APIC; +} #endif void lapic_watchdog_stop(void); diff --git a/include/asm-x86/numa_64.h b/include/asm-x86/numa_64.h index 22e87c9f6a80..b510daf4f4d8 100644 --- a/include/asm-x86/numa_64.h +++ b/include/asm-x86/numa_64.h @@ -14,11 +14,9 @@ extern int compute_hash_shift(struct bootnode *nodes, int numblks, #define ZONE_ALIGN (1UL << (MAX_ORDER+PAGE_SHIFT)) -extern void numa_add_cpu(int cpu); extern void numa_init_array(void); extern int numa_off; -extern void numa_set_node(int cpu, int node); extern void srat_reserve_add_area(int nodeid); extern int hotadd_percent; @@ -31,15 +29,16 @@ extern void setup_node_bootmem(int nodeid, unsigned long start, #ifdef CONFIG_NUMA extern void __init init_cpu_to_node(void); - -static inline void clear_node_cpumask(int cpu) -{ - clear_bit(cpu, (unsigned long *)&node_to_cpumask_map[cpu_to_node(cpu)]); -} - +extern void __cpuinit numa_set_node(int cpu, int node); +extern void __cpuinit numa_clear_node(int cpu); +extern void __cpuinit numa_add_cpu(int cpu); +extern void __cpuinit numa_remove_cpu(int cpu); #else -#define init_cpu_to_node() do {} while (0) -#define clear_node_cpumask(cpu) do {} while (0) +static inline void init_cpu_to_node(void) { } +static inline void numa_set_node(int cpu, int node) { } +static inline void numa_clear_node(int cpu) { } +static inline void numa_add_cpu(int cpu, int node) { } +static inline void numa_remove_cpu(int cpu) { } #endif #endif diff --git a/include/asm-x86/numaq.h b/include/asm-x86/numaq.h index 94b86c31239a..ef068d2465d6 100644 --- a/include/asm-x86/numaq.h +++ b/include/asm-x86/numaq.h @@ -28,6 +28,7 @@ #ifdef CONFIG_X86_NUMAQ +extern int found_numaq; extern int get_memcfg_numaq(void); /* @@ -156,9 +157,10 @@ struct sys_cfg_data { struct eachquadmem eq[MAX_NUMNODES]; /* indexed by quad id */ }; -static inline unsigned long *get_zholes_size(int nid) +#else +static inline int get_memcfg_numaq(void) { - return NULL; + return 0; } #endif /* CONFIG_X86_NUMAQ */ #endif /* NUMAQ_H */ diff --git a/include/asm-x86/page.h b/include/asm-x86/page.h index dc936dddf161..b52ed85f32f5 100644 --- a/include/asm-x86/page.h +++ b/include/asm-x86/page.h @@ -51,8 +51,15 @@ #ifndef __ASSEMBLY__ +typedef struct { pgdval_t pgd; } pgd_t; +typedef struct { pgprotval_t pgprot; } pgprot_t; + extern int page_is_ram(unsigned long pagenr); extern int devmem_is_allowed(unsigned long pagenr); +extern void map_devmem(unsigned long pfn, unsigned long size, + pgprot_t vma_prot); +extern void unmap_devmem(unsigned long pfn, unsigned long size, + pgprot_t vma_prot); extern unsigned long max_pfn_mapped; @@ -74,9 +81,6 @@ static inline void copy_user_page(void *to, void *from, unsigned long vaddr, alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) #define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE -typedef struct { pgdval_t pgd; } pgd_t; -typedef struct { pgprotval_t pgprot; } pgprot_t; - static inline pgd_t native_make_pgd(pgdval_t val) { return (pgd_t) { val }; @@ -160,6 +164,7 @@ static inline pteval_t native_pte_val(pte_t pte) #endif #define pte_val(x) native_pte_val(x) +#define pte_flags(x) native_pte_val(x) #define __pte(x) native_make_pte(x) #endif /* CONFIG_PARAVIRT */ diff --git a/include/asm-x86/page_32.h b/include/asm-x86/page_32.h index 424e82f8ae27..73ed2e4ebf95 100644 --- a/include/asm-x86/page_32.h +++ b/include/asm-x86/page_32.h @@ -13,8 +13,17 @@ */ #define __PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL) +#ifdef CONFIG_4KSTACKS +#define THREAD_ORDER 0 +#else +#define THREAD_ORDER 1 +#endif +#define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER) + + #ifdef CONFIG_X86_PAE -#define __PHYSICAL_MASK_SHIFT 36 +/* 44=32+12, the limit we can fit into an unsigned long pfn */ +#define __PHYSICAL_MASK_SHIFT 44 #define __VIRTUAL_MASK_SHIFT 32 #define PAGETABLE_LEVELS 3 diff --git a/include/asm-x86/paravirt.h b/include/asm-x86/paravirt.h index 0f13b945e240..5ea37a48eecb 100644 --- a/include/asm-x86/paravirt.h +++ b/include/asm-x86/paravirt.h @@ -239,6 +239,7 @@ struct pv_mmu_ops { unsigned long addr, pte_t *ptep); pteval_t (*pte_val)(pte_t); + pteval_t (*pte_flags)(pte_t); pte_t (*make_pte)(pteval_t pte); pgdval_t (*pgd_val)(pgd_t); @@ -996,6 +997,20 @@ static inline pteval_t pte_val(pte_t pte) return ret; } +static inline pteval_t pte_flags(pte_t pte) +{ + pteval_t ret; + + if (sizeof(pteval_t) > sizeof(long)) + ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_flags, + pte.pte, (u64)pte.pte >> 32); + else + ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_flags, + pte.pte); + + return ret; +} + static inline pgd_t __pgd(pgdval_t val) { pgdval_t ret; diff --git a/include/asm-x86/pci-direct.h b/include/asm-x86/pci-direct.h index 5b21485be573..80c775d9fe20 100644 --- a/include/asm-x86/pci-direct.h +++ b/include/asm-x86/pci-direct.h @@ -11,7 +11,11 @@ extern u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset); extern u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset); extern void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, u32 val); extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val); +extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val); extern int early_pci_allowed(void); +extern unsigned int pci_early_dump_regs; +extern void early_dump_pci_device(u8 bus, u8 slot, u8 func); +extern void early_dump_pci_devices(void); #endif diff --git a/include/asm-x86/pci.h b/include/asm-x86/pci.h index 30bbde0cb34b..2db14cf17db8 100644 --- a/include/asm-x86/pci.h +++ b/include/asm-x86/pci.h @@ -18,6 +18,8 @@ struct pci_sysdata { #endif }; +extern int pci_routeirq; + /* scan a bus after allocating a pci_sysdata for it */ extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node); diff --git a/include/asm-x86/pda.h b/include/asm-x86/pda.h index 101fb9e11954..385ffbe4c169 100644 --- a/include/asm-x86/pda.h +++ b/include/asm-x86/pda.h @@ -16,12 +16,12 @@ struct x8664_pda { unsigned long oldrsp; /* 24 user rsp for system call */ int irqcount; /* 32 Irq nesting counter. Starts -1 */ unsigned int cpunumber; /* 36 Logical CPU number */ -#ifdef CONFIG_CC_STACKPROTECTOR unsigned long stack_canary; /* 40 stack canary value */ /* gcc-ABI: this canary MUST be at offset 40!!! */ -#endif char *irqstackptr; + short nodenumber; /* number of current node (32k max) */ + short in_bootmem; /* pda lives in bootmem */ unsigned int __softirq_pending; unsigned int __nmi_count; /* number of NMI on this CPUs */ short mmu_state; @@ -37,8 +37,7 @@ struct x8664_pda { unsigned irq_spurious_count; } ____cacheline_aligned_in_smp; -extern struct x8664_pda *_cpu_pda[]; -extern struct x8664_pda boot_cpu_pda[]; +extern struct x8664_pda **_cpu_pda; extern void pda_init(int); #define cpu_pda(i) (_cpu_pda[i]) diff --git a/include/asm-x86/percpu.h b/include/asm-x86/percpu.h index 736fc3bb8e1e..47d7c7bbe62c 100644 --- a/include/asm-x86/percpu.h +++ b/include/asm-x86/percpu.h @@ -108,6 +108,11 @@ do { \ : "+m" (var) \ : "ri" ((T__)val)); \ break; \ + case 8: \ + asm(op "q %1,"__percpu_seg"%0" \ + : "+m" (var) \ + : "ri" ((T__)val)); \ + break; \ default: __bad_percpu_size(); \ } \ } while (0) @@ -131,16 +136,130 @@ do { \ : "=r" (ret__) \ : "m" (var)); \ break; \ + case 8: \ + asm(op "q "__percpu_seg"%1,%0" \ + : "=r" (ret__) \ + : "m" (var)); \ + break; \ default: __bad_percpu_size(); \ } \ ret__; \ }) -#define x86_read_percpu(var) percpu_from_op("mov", per_cpu__##var) -#define x86_write_percpu(var, val) percpu_to_op("mov", per_cpu__##var, val) -#define x86_add_percpu(var, val) percpu_to_op("add", per_cpu__##var, val) -#define x86_sub_percpu(var, val) percpu_to_op("sub", per_cpu__##var, val) -#define x86_or_percpu(var, val) percpu_to_op("or", per_cpu__##var, val) +#define percpu_addr_op(op, var) \ +({ \ + switch (sizeof(var)) { \ + case 1: \ + asm(op "b "__percpu_seg"%0" \ + : : "m"(var)); \ + break; \ + case 2: \ + asm(op "w "__percpu_seg"%0" \ + : : "m"(var)); \ + break; \ + case 4: \ + asm(op "l "__percpu_seg"%0" \ + : : "m"(var)); \ + break; \ + case 8: \ + asm(op "q "__percpu_seg"%0" \ + : : "m"(var)); \ + break; \ + default: __bad_percpu_size(); \ + } \ +}) + +#define percpu_cmpxchg_op(var, old, new) \ +({ \ + typeof(var) prev; \ + switch (sizeof(var)) { \ + case 1: \ + asm("cmpxchgb %b1, "__percpu_seg"%2" \ + : "=a"(prev) \ + : "q"(new), "m"(var), "0"(old) \ + : "memory"); \ + break; \ + case 2: \ + asm("cmpxchgw %w1, "__percpu_seg"%2" \ + : "=a"(prev) \ + : "r"(new), "m"(var), "0"(old) \ + : "memory"); \ + break; \ + case 4: \ + asm("cmpxchgl %k1, "__percpu_seg"%2" \ + : "=a"(prev) \ + : "r"(new), "m"(var), "0"(old) \ + : "memory"); \ + break; \ + case 8: \ + asm("cmpxchgq %1, "__percpu_seg"%2" \ + : "=a"(prev) \ + : "r"(new), "m"(var), "0"(old) \ + : "memory"); \ + break; \ + default: \ + __bad_percpu_size(); \ + } \ + return prev; \ +}) + +#define x86_read_percpu(var) percpu_from_op("mov", per_cpu_var(var)) +#define x86_write_percpu(var, val) percpu_to_op("mov", per_cpu_var(var), val) +#define x86_add_percpu(var, val) percpu_to_op("add", per_cpu_var(var), val) +#define x86_sub_percpu(var, val) percpu_to_op("sub", per_cpu_var(var), val) +#define x86_inc_percpu(var) percpu_addr_op("inc", per_cpu_var(var)) +#define x86_dec_percpu(var) percpu_addr_op("dec", per_cpu_var(var)) +#define x86_or_percpu(var, val) percpu_to_op("or", per_cpu_var(var), val) +#define x86_xchg_percpu(var, val) percpu_to_op("xchg", per_cpu_var(var), val) +#define x86_cmpxchg_percpu(var, old, new) \ + percpu_cmpxchg_op(per_cpu_var(var), old, new) + #endif /* !__ASSEMBLY__ */ #endif /* !CONFIG_X86_64 */ + +#ifdef CONFIG_SMP + +/* + * Define the "EARLY_PER_CPU" macros. These are used for some per_cpu + * variables that are initialized and accessed before there are per_cpu + * areas allocated. + */ + +#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ + DEFINE_PER_CPU(_type, _name) = _initvalue; \ + __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \ + { [0 ... NR_CPUS-1] = _initvalue }; \ + __typeof__(_type) *_name##_early_ptr = _name##_early_map + +#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ + EXPORT_PER_CPU_SYMBOL(_name) + +#define DECLARE_EARLY_PER_CPU(_type, _name) \ + DECLARE_PER_CPU(_type, _name); \ + extern __typeof__(_type) *_name##_early_ptr; \ + extern __typeof__(_type) _name##_early_map[] + +#define early_per_cpu_ptr(_name) (_name##_early_ptr) +#define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx]) +#define early_per_cpu(_name, _cpu) \ + (early_per_cpu_ptr(_name) ? \ + early_per_cpu_ptr(_name)[_cpu] : \ + per_cpu(_name, _cpu)) + +#else /* !CONFIG_SMP */ +#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ + DEFINE_PER_CPU(_type, _name) = _initvalue + +#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ + EXPORT_PER_CPU_SYMBOL(_name) + +#define DECLARE_EARLY_PER_CPU(_type, _name) \ + DECLARE_PER_CPU(_type, _name) + +#define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu) +#define early_per_cpu_ptr(_name) NULL +/* no early_per_cpu_map() */ + +#endif /* !CONFIG_SMP */ + #endif /* _ASM_X86_PERCPU_H_ */ diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h index 97c271b2910b..bcb5446a08d1 100644 --- a/include/asm-x86/pgtable.h +++ b/include/asm-x86/pgtable.h @@ -20,30 +20,25 @@ #define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */ #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */ -/* - * Note: we use _AC(1, L) instead of _AC(1, UL) so that we get a - * sign-extended value on 32-bit with all 1's in the upper word, - * which preserves the upper pte values on 64-bit ptes: - */ -#define _PAGE_PRESENT (_AC(1, L)<<_PAGE_BIT_PRESENT) -#define _PAGE_RW (_AC(1, L)<<_PAGE_BIT_RW) -#define _PAGE_USER (_AC(1, L)<<_PAGE_BIT_USER) -#define _PAGE_PWT (_AC(1, L)<<_PAGE_BIT_PWT) -#define _PAGE_PCD (_AC(1, L)<<_PAGE_BIT_PCD) -#define _PAGE_ACCESSED (_AC(1, L)<<_PAGE_BIT_ACCESSED) -#define _PAGE_DIRTY (_AC(1, L)<<_PAGE_BIT_DIRTY) -#define _PAGE_PSE (_AC(1, L)<<_PAGE_BIT_PSE) /* 2MB page */ -#define _PAGE_GLOBAL (_AC(1, L)<<_PAGE_BIT_GLOBAL) /* Global TLB entry */ -#define _PAGE_UNUSED1 (_AC(1, L)<<_PAGE_BIT_UNUSED1) -#define _PAGE_UNUSED2 (_AC(1, L)<<_PAGE_BIT_UNUSED2) -#define _PAGE_UNUSED3 (_AC(1, L)<<_PAGE_BIT_UNUSED3) -#define _PAGE_PAT (_AC(1, L)<<_PAGE_BIT_PAT) -#define _PAGE_PAT_LARGE (_AC(1, L)<<_PAGE_BIT_PAT_LARGE) +#define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT) +#define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW) +#define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER) +#define _PAGE_PWT (_AT(pteval_t, 1) << _PAGE_BIT_PWT) +#define _PAGE_PCD (_AT(pteval_t, 1) << _PAGE_BIT_PCD) +#define _PAGE_ACCESSED (_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED) +#define _PAGE_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_DIRTY) +#define _PAGE_PSE (_AT(pteval_t, 1) << _PAGE_BIT_PSE) +#define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL) +#define _PAGE_UNUSED1 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED1) +#define _PAGE_UNUSED2 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED2) +#define _PAGE_UNUSED3 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED3) +#define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT) +#define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE) #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) -#define _PAGE_NX (_AC(1, ULL) << _PAGE_BIT_NX) +#define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX) #else -#define _PAGE_NX 0 +#define _PAGE_NX (_AT(pteval_t, 0)) #endif /* If _PAGE_PRESENT is clear, we use these: */ @@ -164,37 +159,37 @@ extern struct list_head pgd_list; */ static inline int pte_dirty(pte_t pte) { - return pte_val(pte) & _PAGE_DIRTY; + return pte_flags(pte) & _PAGE_DIRTY; } static inline int pte_young(pte_t pte) { - return pte_val(pte) & _PAGE_ACCESSED; + return pte_flags(pte) & _PAGE_ACCESSED; } static inline int pte_write(pte_t pte) { - return pte_val(pte) & _PAGE_RW; + return pte_flags(pte) & _PAGE_RW; } static inline int pte_file(pte_t pte) { - return pte_val(pte) & _PAGE_FILE; + return pte_flags(pte) & _PAGE_FILE; } static inline int pte_huge(pte_t pte) { - return pte_val(pte) & _PAGE_PSE; + return pte_flags(pte) & _PAGE_PSE; } static inline int pte_global(pte_t pte) { - return pte_val(pte) & _PAGE_GLOBAL; + return pte_flags(pte) & _PAGE_GLOBAL; } static inline int pte_exec(pte_t pte) { - return !(pte_val(pte) & _PAGE_NX); + return !(pte_flags(pte) & _PAGE_NX); } static inline int pte_special(pte_t pte) @@ -210,22 +205,22 @@ static inline int pmd_large(pmd_t pte) static inline pte_t pte_mkclean(pte_t pte) { - return __pte(pte_val(pte) & ~(pteval_t)_PAGE_DIRTY); + return __pte(pte_val(pte) & ~_PAGE_DIRTY); } static inline pte_t pte_mkold(pte_t pte) { - return __pte(pte_val(pte) & ~(pteval_t)_PAGE_ACCESSED); + return __pte(pte_val(pte) & ~_PAGE_ACCESSED); } static inline pte_t pte_wrprotect(pte_t pte) { - return __pte(pte_val(pte) & ~(pteval_t)_PAGE_RW); + return __pte(pte_val(pte) & ~_PAGE_RW); } static inline pte_t pte_mkexec(pte_t pte) { - return __pte(pte_val(pte) & ~(pteval_t)_PAGE_NX); + return __pte(pte_val(pte) & ~_PAGE_NX); } static inline pte_t pte_mkdirty(pte_t pte) @@ -250,7 +245,7 @@ static inline pte_t pte_mkhuge(pte_t pte) static inline pte_t pte_clrhuge(pte_t pte) { - return __pte(pte_val(pte) & ~(pteval_t)_PAGE_PSE); + return __pte(pte_val(pte) & ~_PAGE_PSE); } static inline pte_t pte_mkglobal(pte_t pte) @@ -260,7 +255,7 @@ static inline pte_t pte_mkglobal(pte_t pte) static inline pte_t pte_clrglobal(pte_t pte) { - return __pte(pte_val(pte) & ~(pteval_t)_PAGE_GLOBAL); + return __pte(pte_val(pte) & ~_PAGE_GLOBAL); } static inline pte_t pte_mkspecial(pte_t pte) @@ -305,7 +300,7 @@ static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) return __pgprot(preservebits | addbits); } -#define pte_pgprot(x) __pgprot(pte_val(x) & ~PTE_MASK) +#define pte_pgprot(x) __pgprot(pte_flags(x) & ~PTE_MASK) #define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask) @@ -369,8 +364,15 @@ enum { PG_LEVEL_4K, PG_LEVEL_2M, PG_LEVEL_1G, + PG_LEVEL_NUM }; +#ifdef CONFIG_PROC_FS +extern void update_page_count(int level, unsigned long pages); +#else +static inline void update_page_count(int level, unsigned long pages) { } +#endif + /* * Helper function that returns the kernel pagetable entry controlling * the virtual address 'address'. NULL means no pagetable entry present. diff --git a/include/asm-x86/processor-flags.h b/include/asm-x86/processor-flags.h index 199cab107d85..092b39b3a7e6 100644 --- a/include/asm-x86/processor-flags.h +++ b/include/asm-x86/processor-flags.h @@ -88,4 +88,10 @@ #define CX86_ARR_BASE 0xc4 #define CX86_RCR_BASE 0xdc +#ifdef CONFIG_VM86 +#define X86_VM_MASK X86_EFLAGS_VM +#else +#define X86_VM_MASK 0 /* No VM86 support */ +#endif + #endif /* __ASM_I386_PROCESSOR_FLAGS_H */ diff --git a/include/asm-x86/proto.h b/include/asm-x86/proto.h index 6c8b41b03f6d..a9f51472521e 100644 --- a/include/asm-x86/proto.h +++ b/include/asm-x86/proto.h @@ -14,7 +14,7 @@ extern void ia32_syscall(void); extern void ia32_cstar_target(void); extern void ia32_sysenter_target(void); -extern void reserve_bootmem_generic(unsigned long phys, unsigned len); +extern int reserve_bootmem_generic(unsigned long phys, unsigned len, int flags); extern void syscall32_cpu_init(void); diff --git a/include/asm-x86/ptrace.h b/include/asm-x86/ptrace.h index 9f922b0b95d6..8a71db803da6 100644 --- a/include/asm-x86/ptrace.h +++ b/include/asm-x86/ptrace.h @@ -3,7 +3,12 @@ #include <linux/compiler.h> /* For __user */ #include <asm/ptrace-abi.h> +#include <asm/processor-flags.h> +#ifdef __KERNEL__ +#include <asm/ds.h> /* the DS BTS struct is used for ptrace too */ +#include <asm/segment.h> +#endif #ifndef __ASSEMBLY__ @@ -55,9 +60,6 @@ struct pt_regs { unsigned long ss; }; -#include <asm/vm86.h> -#include <asm/segment.h> - #endif /* __KERNEL__ */ #else /* __i386__ */ diff --git a/include/asm-x86/reboot.h b/include/asm-x86/reboot.h index e63741f19392..206f355786dc 100644 --- a/include/asm-x86/reboot.h +++ b/include/asm-x86/reboot.h @@ -14,8 +14,8 @@ struct machine_ops { extern struct machine_ops machine_ops; -void machine_real_restart(unsigned char *code, int length); void native_machine_crash_shutdown(struct pt_regs *regs); void native_machine_shutdown(void); +void machine_real_restart(const unsigned char *code, int length); #endif /* _ASM_REBOOT_H */ diff --git a/include/asm-x86/required-features.h b/include/asm-x86/required-features.h index 7400d3ad75c6..8c387198ca88 100644 --- a/include/asm-x86/required-features.h +++ b/include/asm-x86/required-features.h @@ -19,9 +19,13 @@ #if defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64) # define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) -# define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) #else # define NEED_PAE 0 +#endif + +#ifdef CONFIG_X86_CMPXCHG64 +# define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) +#else # define NEED_CX8 0 #endif diff --git a/include/asm-x86/resume-trace.h b/include/asm-x86/resume-trace.h index 2557514d7ef6..8d9f0b41ee86 100644 --- a/include/asm-x86/resume-trace.h +++ b/include/asm-x86/resume-trace.h @@ -6,7 +6,7 @@ #define TRACE_RESUME(user) \ do { \ if (pm_trace_enabled) { \ - void *tracedata; \ + const void *tracedata; \ asm volatile(_ASM_MOV_UL " $1f,%0\n" \ ".section .tracedata,\"a\"\n" \ "1:\t.word %c1\n\t" \ diff --git a/include/asm-x86/seccomp_32.h b/include/asm-x86/seccomp_32.h index 18da19e89bff..36e71c5f306f 100644 --- a/include/asm-x86/seccomp_32.h +++ b/include/asm-x86/seccomp_32.h @@ -1,4 +1,5 @@ #ifndef _ASM_SECCOMP_H +#define _ASM_SECCOMP_H #include <linux/thread_info.h> diff --git a/include/asm-x86/setup.h b/include/asm-x86/setup.h index fa6763af8d26..9e163fc3e984 100644 --- a/include/asm-x86/setup.h +++ b/include/asm-x86/setup.h @@ -50,19 +50,14 @@ extern struct boot_params boot_params; */ #define LOWMEMSIZE() (0x9f000) -struct e820entry; - char * __init machine_specific_memory_setup(void); char *memory_setup(void); -int __init copy_e820_map(struct e820entry *biosmap, int nr_map); -int __init sanitize_e820_map(struct e820entry *biosmap, char *pnr_map); -void __init add_memory_region(unsigned long long start, - unsigned long long size, int type); - -extern unsigned long init_pg_tables_end; +void __init i386_start_kernel(void); +extern unsigned long init_pg_tables_start; +extern unsigned long init_pg_tables_end; #endif /* __i386__ */ #endif /* _SETUP */ diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h index 1ebaa5cd3112..fc1007321ef6 100644 --- a/include/asm-x86/smp.h +++ b/include/asm-x86/smp.h @@ -29,21 +29,12 @@ extern int smp_num_siblings; extern unsigned int num_processors; extern cpumask_t cpu_initialized; -#ifdef CONFIG_SMP -extern u16 x86_cpu_to_apicid_init[]; -extern u16 x86_bios_cpu_apicid_init[]; -extern void *x86_cpu_to_apicid_early_ptr; -extern void *x86_bios_cpu_apicid_early_ptr; -#else -#define x86_cpu_to_apicid_early_ptr NULL -#define x86_bios_cpu_apicid_early_ptr NULL -#endif - DECLARE_PER_CPU(cpumask_t, cpu_sibling_map); DECLARE_PER_CPU(cpumask_t, cpu_core_map); DECLARE_PER_CPU(u16, cpu_llc_id); -DECLARE_PER_CPU(u16, x86_cpu_to_apicid); -DECLARE_PER_CPU(u16, x86_bios_cpu_apicid); + +DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid); +DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); /* Static state in head.S used to set up a CPU */ extern struct { @@ -201,7 +192,6 @@ extern void cpu_exit_clear(void); extern void cpu_uninit(void); #endif -extern void smp_alloc_memory(void); extern void lock_ipi_call_lock(void); extern void unlock_ipi_call_lock(void); #endif /* __ASSEMBLY__ */ diff --git a/include/asm-x86/srat.h b/include/asm-x86/srat.h index f4bba131d068..456fe0b5a921 100644 --- a/include/asm-x86/srat.h +++ b/include/asm-x86/srat.h @@ -27,11 +27,13 @@ #ifndef _ASM_SRAT_H_ #define _ASM_SRAT_H_ -#ifndef CONFIG_ACPI_SRAT -#error CONFIG_ACPI_SRAT not defined, and srat.h header has been included -#endif - +#ifdef CONFIG_ACPI_SRAT extern int get_memcfg_from_srat(void); -extern unsigned long *get_zholes_size(int); +#else +static inline int get_memcfg_from_srat(void) +{ + return 0; +} +#endif #endif /* _ASM_SRAT_H_ */ diff --git a/include/asm-x86/stackprotector.h b/include/asm-x86/stackprotector.h new file mode 100644 index 000000000000..3baf7ad89be1 --- /dev/null +++ b/include/asm-x86/stackprotector.h @@ -0,0 +1,38 @@ +#ifndef _ASM_STACKPROTECTOR_H +#define _ASM_STACKPROTECTOR_H 1 + +#include <asm/tsc.h> + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + u64 canary; + u64 tsc; + + /* + * If we're the non-boot CPU, nothing set the PDA stack + * canary up for us - and if we are the boot CPU we have + * a 0 stack canary. This is a good place for updating + * it, as we wont ever return from this function (so the + * invalid canaries already on the stack wont ever + * trigger). + * + * We both use the random pool and the current TSC as a source + * of randomness. The TSC only matters for very early init, + * there it already has some randomness on most systems. Later + * on during the bootup the random pool has true entropy too. + */ + get_random_bytes(&canary, sizeof(canary)); + tsc = __native_read_tsc(); + canary += tsc + (tsc << 32UL); + + current->stack_canary = canary; + write_pda(stack_canary, canary); +} + +#endif diff --git a/include/asm-x86/string_32.h b/include/asm-x86/string_32.h index b49369ad9a61..193578cd1fd9 100644 --- a/include/asm-x86/string_32.h +++ b/include/asm-x86/string_32.h @@ -29,81 +29,116 @@ extern char *strchr(const char *s, int c); #define __HAVE_ARCH_STRLEN extern size_t strlen(const char *s); -static __always_inline void * __memcpy(void * to, const void * from, size_t n) +static __always_inline void *__memcpy(void *to, const void *from, size_t n) { -int d0, d1, d2; -__asm__ __volatile__( - "rep ; movsl\n\t" - "movl %4,%%ecx\n\t" - "andl $3,%%ecx\n\t" - "jz 1f\n\t" - "rep ; movsb\n\t" - "1:" - : "=&c" (d0), "=&D" (d1), "=&S" (d2) - : "0" (n/4), "g" (n), "1" ((long) to), "2" ((long) from) - : "memory"); -return (to); + int d0, d1, d2; + asm volatile("rep ; movsl\n\t" + "movl %4,%%ecx\n\t" + "andl $3,%%ecx\n\t" + "jz 1f\n\t" + "rep ; movsb\n\t" + "1:" + : "=&c" (d0), "=&D" (d1), "=&S" (d2) + : "0" (n / 4), "g" (n), "1" ((long)to), "2" ((long)from) + : "memory"); + return to; } /* * This looks ugly, but the compiler can optimize it totally, * as the count is constant. */ -static __always_inline void * __constant_memcpy(void * to, const void * from, size_t n) +static __always_inline void *__constant_memcpy(void *to, const void *from, + size_t n) { long esi, edi; - if (!n) return to; -#if 1 /* want to do small copies with non-string ops? */ + if (!n) + return to; + switch (n) { - case 1: *(char*)to = *(char*)from; return to; - case 2: *(short*)to = *(short*)from; return to; - case 4: *(int*)to = *(int*)from; return to; -#if 1 /* including those doable with two moves? */ - case 3: *(short*)to = *(short*)from; - *((char*)to+2) = *((char*)from+2); return to; - case 5: *(int*)to = *(int*)from; - *((char*)to+4) = *((char*)from+4); return to; - case 6: *(int*)to = *(int*)from; - *((short*)to+2) = *((short*)from+2); return to; - case 8: *(int*)to = *(int*)from; - *((int*)to+1) = *((int*)from+1); return to; -#endif + case 1: + *(char *)to = *(char *)from; + return to; + case 2: + *(short *)to = *(short *)from; + return to; + case 4: + *(int *)to = *(int *)from; + return to; + + case 3: + *(short *)to = *(short *)from; + *((char *)to + 2) = *((char *)from + 2); + return to; + case 5: + *(int *)to = *(int *)from; + *((char *)to + 4) = *((char *)from + 4); + return to; + case 6: + *(int *)to = *(int *)from; + *((short *)to + 2) = *((short *)from + 2); + return to; + case 8: + *(int *)to = *(int *)from; + *((int *)to + 1) = *((int *)from + 1); + return to; } -#endif - esi = (long) from; - edi = (long) to; - if (n >= 5*4) { + + esi = (long)from; + edi = (long)to; + if (n >= 5 * 4) { /* large block: use rep prefix */ int ecx; - __asm__ __volatile__( - "rep ; movsl" - : "=&c" (ecx), "=&D" (edi), "=&S" (esi) - : "0" (n/4), "1" (edi),"2" (esi) - : "memory" + asm volatile("rep ; movsl" + : "=&c" (ecx), "=&D" (edi), "=&S" (esi) + : "0" (n / 4), "1" (edi), "2" (esi) + : "memory" ); } else { /* small block: don't clobber ecx + smaller code */ - if (n >= 4*4) __asm__ __volatile__("movsl" - :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); - if (n >= 3*4) __asm__ __volatile__("movsl" - :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); - if (n >= 2*4) __asm__ __volatile__("movsl" - :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); - if (n >= 1*4) __asm__ __volatile__("movsl" - :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); + if (n >= 4 * 4) + asm volatile("movsl" + : "=&D"(edi), "=&S"(esi) + : "0"(edi), "1"(esi) + : "memory"); + if (n >= 3 * 4) + asm volatile("movsl" + : "=&D"(edi), "=&S"(esi) + : "0"(edi), "1"(esi) + : "memory"); + if (n >= 2 * 4) + asm volatile("movsl" + : "=&D"(edi), "=&S"(esi) + : "0"(edi), "1"(esi) + : "memory"); + if (n >= 1 * 4) + asm volatile("movsl" + : "=&D"(edi), "=&S"(esi) + : "0"(edi), "1"(esi) + : "memory"); } switch (n % 4) { /* tail */ - case 0: return to; - case 1: __asm__ __volatile__("movsb" - :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); - return to; - case 2: __asm__ __volatile__("movsw" - :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); - return to; - default: __asm__ __volatile__("movsw\n\tmovsb" - :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); - return to; + case 0: + return to; + case 1: + asm volatile("movsb" + : "=&D"(edi), "=&S"(esi) + : "0"(edi), "1"(esi) + : "memory"); + return to; + case 2: + asm volatile("movsw" + : "=&D"(edi), "=&S"(esi) + : "0"(edi), "1"(esi) + : "memory"); + return to; + default: + asm volatile("movsw\n\tmovsb" + : "=&D"(edi), "=&S"(esi) + : "0"(edi), "1"(esi) + : "memory"); + return to; } } @@ -117,87 +152,86 @@ static __always_inline void * __constant_memcpy(void * to, const void * from, si * This CPU favours 3DNow strongly (eg AMD Athlon) */ -static inline void * __constant_memcpy3d(void * to, const void * from, size_t len) +static inline void *__constant_memcpy3d(void *to, const void *from, size_t len) { if (len < 512) return __constant_memcpy(to, from, len); return _mmx_memcpy(to, from, len); } -static __inline__ void *__memcpy3d(void *to, const void *from, size_t len) +static inline void *__memcpy3d(void *to, const void *from, size_t len) { if (len < 512) return __memcpy(to, from, len); return _mmx_memcpy(to, from, len); } -#define memcpy(t, f, n) \ -(__builtin_constant_p(n) ? \ - __constant_memcpy3d((t),(f),(n)) : \ - __memcpy3d((t),(f),(n))) +#define memcpy(t, f, n) \ + (__builtin_constant_p((n)) \ + ? __constant_memcpy3d((t), (f), (n)) \ + : __memcpy3d((t), (f), (n))) #else /* * No 3D Now! */ - -#define memcpy(t, f, n) \ -(__builtin_constant_p(n) ? \ - __constant_memcpy((t),(f),(n)) : \ - __memcpy((t),(f),(n))) + +#define memcpy(t, f, n) \ + (__builtin_constant_p((n)) \ + ? __constant_memcpy((t), (f), (n)) \ + : __memcpy((t), (f), (n))) #endif #define __HAVE_ARCH_MEMMOVE -void *memmove(void * dest,const void * src, size_t n); +void *memmove(void *dest, const void *src, size_t n); #define memcmp __builtin_memcmp #define __HAVE_ARCH_MEMCHR -extern void *memchr(const void * cs,int c,size_t count); +extern void *memchr(const void *cs, int c, size_t count); -static inline void * __memset_generic(void * s, char c,size_t count) +static inline void *__memset_generic(void *s, char c, size_t count) { -int d0, d1; -__asm__ __volatile__( - "rep\n\t" - "stosb" - : "=&c" (d0), "=&D" (d1) - :"a" (c),"1" (s),"0" (count) - :"memory"); -return s; + int d0, d1; + asm volatile("rep\n\t" + "stosb" + : "=&c" (d0), "=&D" (d1) + : "a" (c), "1" (s), "0" (count) + : "memory"); + return s; } /* we might want to write optimized versions of these later */ -#define __constant_count_memset(s,c,count) __memset_generic((s),(c),(count)) +#define __constant_count_memset(s, c, count) __memset_generic((s), (c), (count)) /* - * memset(x,0,y) is a reasonably common thing to do, so we want to fill + * memset(x, 0, y) is a reasonably common thing to do, so we want to fill * things 32 bits at a time even when we don't know the size of the * area at compile-time.. */ -static __always_inline void * __constant_c_memset(void * s, unsigned long c, size_t count) +static __always_inline +void *__constant_c_memset(void *s, unsigned long c, size_t count) { -int d0, d1; -__asm__ __volatile__( - "rep ; stosl\n\t" - "testb $2,%b3\n\t" - "je 1f\n\t" - "stosw\n" - "1:\ttestb $1,%b3\n\t" - "je 2f\n\t" - "stosb\n" - "2:" - :"=&c" (d0), "=&D" (d1) - :"a" (c), "q" (count), "0" (count/4), "1" ((long) s) - :"memory"); -return (s); + int d0, d1; + asm volatile("rep ; stosl\n\t" + "testb $2,%b3\n\t" + "je 1f\n\t" + "stosw\n" + "1:\ttestb $1,%b3\n\t" + "je 2f\n\t" + "stosb\n" + "2:" + : "=&c" (d0), "=&D" (d1) + : "a" (c), "q" (count), "0" (count/4), "1" ((long)s) + : "memory"); + return s; } /* Added by Gertjan van Wingerde to make minix and sysv module work */ #define __HAVE_ARCH_STRNLEN -extern size_t strnlen(const char * s, size_t count); +extern size_t strnlen(const char *s, size_t count); /* end of additional stuff */ #define __HAVE_ARCH_STRSTR @@ -207,66 +241,85 @@ extern char *strstr(const char *cs, const char *ct); * This looks horribly ugly, but the compiler can optimize it totally, * as we by now know that both pattern and count is constant.. */ -static __always_inline void * __constant_c_and_count_memset(void * s, unsigned long pattern, size_t count) +static __always_inline +void *__constant_c_and_count_memset(void *s, unsigned long pattern, + size_t count) { switch (count) { + case 0: + return s; + case 1: + *(unsigned char *)s = pattern & 0xff; + return s; + case 2: + *(unsigned short *)s = pattern & 0xffff; + return s; + case 3: + *(unsigned short *)s = pattern & 0xffff; + *((unsigned char *)s + 2) = pattern & 0xff; + return s; + case 4: + *(unsigned long *)s = pattern; + return s; + } + +#define COMMON(x) \ + asm volatile("rep ; stosl" \ + x \ + : "=&c" (d0), "=&D" (d1) \ + : "a" (eax), "0" (count/4), "1" ((long)s) \ + : "memory") + + { + int d0, d1; +#if __GNUC__ == 4 && __GNUC_MINOR__ == 0 + /* Workaround for broken gcc 4.0 */ + register unsigned long eax asm("%eax") = pattern; +#else + unsigned long eax = pattern; +#endif + + switch (count % 4) { case 0: + COMMON(""); return s; case 1: - *(unsigned char *)s = pattern & 0xff; + COMMON("\n\tstosb"); return s; case 2: - *(unsigned short *)s = pattern & 0xffff; + COMMON("\n\tstosw"); return s; - case 3: - *(unsigned short *)s = pattern & 0xffff; - *(2+(unsigned char *)s) = pattern & 0xff; - return s; - case 4: - *(unsigned long *)s = pattern; + default: + COMMON("\n\tstosw\n\tstosb"); return s; + } } -#define COMMON(x) \ -__asm__ __volatile__( \ - "rep ; stosl" \ - x \ - : "=&c" (d0), "=&D" (d1) \ - : "a" (pattern),"0" (count/4),"1" ((long) s) \ - : "memory") -{ - int d0, d1; - switch (count % 4) { - case 0: COMMON(""); return s; - case 1: COMMON("\n\tstosb"); return s; - case 2: COMMON("\n\tstosw"); return s; - default: COMMON("\n\tstosw\n\tstosb"); return s; - } -} - + #undef COMMON } -#define __constant_c_x_memset(s, c, count) \ -(__builtin_constant_p(count) ? \ - __constant_c_and_count_memset((s),(c),(count)) : \ - __constant_c_memset((s),(c),(count))) +#define __constant_c_x_memset(s, c, count) \ + (__builtin_constant_p(count) \ + ? __constant_c_and_count_memset((s), (c), (count)) \ + : __constant_c_memset((s), (c), (count))) -#define __memset(s, c, count) \ -(__builtin_constant_p(count) ? \ - __constant_count_memset((s),(c),(count)) : \ - __memset_generic((s),(c),(count))) +#define __memset(s, c, count) \ + (__builtin_constant_p(count) \ + ? __constant_count_memset((s), (c), (count)) \ + : __memset_generic((s), (c), (count))) #define __HAVE_ARCH_MEMSET -#define memset(s, c, count) \ -(__builtin_constant_p(c) ? \ - __constant_c_x_memset((s),(0x01010101UL*(unsigned char)(c)),(count)) : \ - __memset((s),(c),(count))) +#define memset(s, c, count) \ + (__builtin_constant_p(c) \ + ? __constant_c_x_memset((s), (0x01010101UL * (unsigned char)(c)), \ + (count)) \ + : __memset((s), (c), (count))) /* * find the first occurrence of byte 'c', or 1 past the area if none */ #define __HAVE_ARCH_MEMSCAN -extern void *memscan(void * addr, int c, size_t size); +extern void *memscan(void *addr, int c, size_t size); #endif /* __KERNEL__ */ diff --git a/include/asm-x86/system.h b/include/asm-x86/system.h index a2f04cd79b29..91f3ab98dbaa 100644 --- a/include/asm-x86/system.h +++ b/include/asm-x86/system.h @@ -92,6 +92,8 @@ do { \ ".globl thread_return\n" \ "thread_return:\n\t" \ "movq %%gs:%P[pda_pcurrent],%%rsi\n\t" \ + "movq %P[task_canary](%%rsi),%%r8\n\t" \ + "movq %%r8,%%gs:%P[pda_canary]\n\t" \ "movq %P[thread_info](%%rsi),%%r8\n\t" \ LOCK_PREFIX "btr %[tif_fork],%P[ti_flags](%%r8)\n\t" \ "movq %%rax,%%rdi\n\t" \ @@ -103,7 +105,9 @@ do { \ [ti_flags] "i" (offsetof(struct thread_info, flags)), \ [tif_fork] "i" (TIF_FORK), \ [thread_info] "i" (offsetof(struct task_struct, stack)), \ - [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \ + [task_canary] "i" (offsetof(struct task_struct, stack_canary)),\ + [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)), \ + [pda_canary] "i" (offsetof(struct x8664_pda, stack_canary))\ : "memory", "cc" __EXTRA_CLOBBER) #endif @@ -289,7 +293,7 @@ static inline void native_wbinvd(void) #endif/* CONFIG_PARAVIRT */ -#define stts() write_cr0(8 | read_cr0()) +#define stts() write_cr0(read_cr0() | X86_CR0_TS) #endif /* __KERNEL__ */ @@ -303,7 +307,6 @@ static inline void clflush(volatile void *__p) void disable_hlt(void); void enable_hlt(void); -extern int es7000_plat; void cpu_idle_wait(void); extern unsigned long arch_align_stack(unsigned long sp); diff --git a/include/asm-x86/thread_info.h b/include/asm-x86/thread_info.h index 77244f17993f..895339d2bc0b 100644 --- a/include/asm-x86/thread_info.h +++ b/include/asm-x86/thread_info.h @@ -1,9 +1,253 @@ +/* thread_info.h: low-level thread information + * + * Copyright (C) 2002 David Howells (dhowells@redhat.com) + * - Incorporating suggestions made by Linus Torvalds and Dave Miller + */ + #ifndef _ASM_X86_THREAD_INFO_H +#define _ASM_X86_THREAD_INFO_H + +#include <linux/compiler.h> +#include <asm/page.h> +#include <asm/types.h> + +/* + * low level task data that entry.S needs immediate access to + * - this struct should fit entirely inside of one cache line + * - this struct shares the supervisor stack pages + */ +#ifndef __ASSEMBLY__ +struct task_struct; +struct exec_domain; +#include <asm/processor.h> + +struct thread_info { + struct task_struct *task; /* main task structure */ + struct exec_domain *exec_domain; /* execution domain */ + unsigned long flags; /* low level flags */ + __u32 status; /* thread synchronous flags */ + __u32 cpu; /* current CPU */ + int preempt_count; /* 0 => preemptable, + <0 => BUG */ + mm_segment_t addr_limit; + struct restart_block restart_block; + void __user *sysenter_return; +#ifdef CONFIG_X86_32 + unsigned long previous_esp; /* ESP of the previous stack in + case of nested (IRQ) stacks + */ + __u8 supervisor_stack[0]; +#endif +}; + +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .flags = 0, \ + .cpu = 0, \ + .preempt_count = 1, \ + .addr_limit = KERNEL_DS, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ +} + +#define init_thread_info (init_thread_union.thread_info) +#define init_stack (init_thread_union.stack) + +#else /* !__ASSEMBLY__ */ + +#include <asm/asm-offsets.h> + +#endif + +/* + * thread information flags + * - these are process state flags that various assembly files + * may need to access + * - pending work-to-be-done flags are in LSW + * - other flags in MSW + * Warning: layout of LSW is hardcoded in entry.S + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_SIGPENDING 2 /* signal pending */ +#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ +#define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/ +#define TIF_IRET 5 /* force IRET */ #ifdef CONFIG_X86_32 -# include "thread_info_32.h" +#define TIF_SYSCALL_EMU 6 /* syscall emulation active */ +#endif +#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ +#define TIF_SECCOMP 8 /* secure computing */ +#define TIF_MCE_NOTIFY 10 /* notify userspace of an MCE */ +#define TIF_HRTICK_RESCHED 11 /* reprogram hrtick timer */ +#define TIF_NOTSC 16 /* TSC is not accessible in userland */ +#define TIF_IA32 17 /* 32bit process */ +#define TIF_FORK 18 /* ret_from_fork */ +#define TIF_ABI_PENDING 19 +#define TIF_MEMDIE 20 +#define TIF_DEBUG 21 /* uses debug registers */ +#define TIF_IO_BITMAP 22 /* uses I/O bitmap */ +#define TIF_FREEZE 23 /* is freezing for suspend */ +#define TIF_FORCED_TF 24 /* true if TF in eflags artificially */ +#define TIF_DEBUGCTLMSR 25 /* uses thread_struct.debugctlmsr */ +#define TIF_DS_AREA_MSR 26 /* uses thread_struct.ds_area_msr */ +#define TIF_BTS_TRACE_TS 27 /* record scheduling event timestamps */ + +#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) +#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) +#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) +#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) +#define _TIF_IRET (1 << TIF_IRET) +#ifdef CONFIG_X86_32 +#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU) #else -# include "thread_info_64.h" +#define _TIF_SYSCALL_EMU 0 #endif +#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) +#define _TIF_SECCOMP (1 << TIF_SECCOMP) +#define _TIF_MCE_NOTIFY (1 << TIF_MCE_NOTIFY) +#define _TIF_HRTICK_RESCHED (1 << TIF_HRTICK_RESCHED) +#define _TIF_NOTSC (1 << TIF_NOTSC) +#define _TIF_IA32 (1 << TIF_IA32) +#define _TIF_FORK (1 << TIF_FORK) +#define _TIF_ABI_PENDING (1 << TIF_ABI_PENDING) +#define _TIF_DEBUG (1 << TIF_DEBUG) +#define _TIF_IO_BITMAP (1 << TIF_IO_BITMAP) +#define _TIF_FREEZE (1 << TIF_FREEZE) +#define _TIF_FORCED_TF (1 << TIF_FORCED_TF) +#define _TIF_DEBUGCTLMSR (1 << TIF_DEBUGCTLMSR) +#define _TIF_DS_AREA_MSR (1 << TIF_DS_AREA_MSR) +#define _TIF_BTS_TRACE_TS (1 << TIF_BTS_TRACE_TS) + +/* work to do on interrupt/exception return */ +#define _TIF_WORK_MASK \ + (0x0000FFFF & \ + ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP| \ + _TIF_SECCOMP|_TIF_SYSCALL_EMU)) + +/* work to do on any return to user space */ +#define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP) + +/* Only used for 64 bit */ +#define _TIF_DO_NOTIFY_MASK \ + (_TIF_SIGPENDING|_TIF_SINGLESTEP|_TIF_MCE_NOTIFY|_TIF_HRTICK_RESCHED) + +/* flags to check in __switch_to() */ +#define _TIF_WORK_CTXSW \ + (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS| \ + _TIF_NOTSC) + +#define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW +#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG) + +#define PREEMPT_ACTIVE 0x10000000 + +/* thread information allocation */ +#ifdef CONFIG_DEBUG_STACK_USAGE +#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO) +#else +#define THREAD_FLAGS GFP_KERNEL +#endif + +#define alloc_thread_info(tsk) \ + ((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER)) + +#ifdef CONFIG_X86_32 + +#define STACK_WARN (THREAD_SIZE/8) +/* + * macros/functions for gaining access to the thread information structure + * + * preempt_count needs to be 1 initially, until the scheduler is functional. + */ +#ifndef __ASSEMBLY__ + + +/* how to get the current stack pointer from C */ +register unsigned long current_stack_pointer asm("esp") __used; + +/* how to get the thread information struct from C */ +static inline struct thread_info *current_thread_info(void) +{ + return (struct thread_info *) + (current_stack_pointer & ~(THREAD_SIZE - 1)); +} + +#else /* !__ASSEMBLY__ */ + +/* how to get the thread information struct from ASM */ +#define GET_THREAD_INFO(reg) \ + movl $-THREAD_SIZE, reg; \ + andl %esp, reg + +/* use this one if reg already contains %esp */ +#define GET_THREAD_INFO_WITH_ESP(reg) \ + andl $-THREAD_SIZE, reg + +#endif + +#else /* X86_32 */ + +#include <asm/pda.h> + +/* + * macros/functions for gaining access to the thread information structure + * preempt_count needs to be 1 initially, until the scheduler is functional. + */ +#ifndef __ASSEMBLY__ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + ti = (void *)(read_pda(kernelstack) + PDA_STACKOFFSET - THREAD_SIZE); + return ti; +} + +/* do not use in interrupt context */ +static inline struct thread_info *stack_thread_info(void) +{ + struct thread_info *ti; + asm("andq %%rsp,%0; " : "=r" (ti) : "0" (~(THREAD_SIZE - 1))); + return ti; +} + +#else /* !__ASSEMBLY__ */ + +/* how to get the thread information struct from ASM */ +#define GET_THREAD_INFO(reg) \ + movq %gs:pda_kernelstack,reg ; \ + subq $(THREAD_SIZE-PDA_STACKOFFSET),reg + +#endif + +#endif /* !X86_32 */ + +/* + * Thread-synchronous status. + * + * This is different from the flags in that nobody else + * ever touches our thread-synchronous status, so we don't + * have to worry about atomic accesses. + */ +#define TS_USEDFPU 0x0001 /* FPU was used by this task + this quantum (SMP) */ +#define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ +#define TS_POLLING 0x0004 /* true if in idle loop + and not sleeping */ +#define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal() */ + +#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING) + +#ifndef __ASSEMBLY__ +#define HAVE_SET_RESTORE_SIGMASK 1 +static inline void set_restore_sigmask(void) +{ + struct thread_info *ti = current_thread_info(); + ti->status |= TS_RESTORE_SIGMASK; + set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags); +} +#endif /* !__ASSEMBLY__ */ #ifndef __ASSEMBLY__ extern void arch_task_cache_init(void); diff --git a/include/asm-x86/thread_info_32.h b/include/asm-x86/thread_info_32.h deleted file mode 100644 index b6338829d1a8..000000000000 --- a/include/asm-x86/thread_info_32.h +++ /dev/null @@ -1,205 +0,0 @@ -/* thread_info.h: i386 low-level thread information - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#ifdef __KERNEL__ - -#include <linux/compiler.h> -#include <asm/page.h> - -#ifndef __ASSEMBLY__ -#include <asm/processor.h> -#endif - -/* - * low level task data that entry.S needs immediate access to - * - this struct should fit entirely inside of one cache line - * - this struct shares the supervisor stack pages - * - if the contents of this structure are changed, - * the assembly constants must also be changed - */ -#ifndef __ASSEMBLY__ - -struct thread_info { - struct task_struct *task; /* main task structure */ - struct exec_domain *exec_domain; /* execution domain */ - unsigned long flags; /* low level flags */ - unsigned long status; /* thread-synchronous flags */ - __u32 cpu; /* current CPU */ - int preempt_count; /* 0 => preemptable, - <0 => BUG */ - mm_segment_t addr_limit; /* thread address space: - 0-0xBFFFFFFF user-thread - 0-0xFFFFFFFF kernel-thread - */ - void *sysenter_return; - struct restart_block restart_block; - unsigned long previous_esp; /* ESP of the previous stack in - case of nested (IRQ) stacks - */ - __u8 supervisor_stack[0]; -}; - -#else /* !__ASSEMBLY__ */ - -#include <asm/asm-offsets.h> - -#endif - -#define PREEMPT_ACTIVE 0x10000000 -#ifdef CONFIG_4KSTACKS -#define THREAD_SIZE (4096) -#else -#define THREAD_SIZE (8192) -#endif - -#define STACK_WARN (THREAD_SIZE/8) -/* - * macros/functions for gaining access to the thread information structure - * - * preempt_count needs to be 1 initially, until the scheduler is functional. - */ -#ifndef __ASSEMBLY__ - -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = 1, \ - .addr_limit = KERNEL_DS, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) -#define init_stack (init_thread_union.stack) - - -/* how to get the current stack pointer from C */ -register unsigned long current_stack_pointer asm("esp") __used; - -/* how to get the thread information struct from C */ -static inline struct thread_info *current_thread_info(void) -{ - return (struct thread_info *) - (current_stack_pointer & ~(THREAD_SIZE - 1)); -} - -/* thread information allocation */ -#ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) ((struct thread_info *) \ - __get_free_pages(GFP_KERNEL | __GFP_ZERO, get_order(THREAD_SIZE))) -#else -#define alloc_thread_info(tsk) ((struct thread_info *) \ - __get_free_pages(GFP_KERNEL, get_order(THREAD_SIZE))) -#endif - -#else /* !__ASSEMBLY__ */ - -/* how to get the thread information struct from ASM */ -#define GET_THREAD_INFO(reg) \ - movl $-THREAD_SIZE, reg; \ - andl %esp, reg - -/* use this one if reg already contains %esp */ -#define GET_THREAD_INFO_WITH_ESP(reg) \ - andl $-THREAD_SIZE, reg - -#endif - -/* - * thread information flags - * - these are process state flags that various - * assembly files may need to access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_SIGPENDING 1 /* signal pending */ -#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_SINGLESTEP 3 /* restore singlestep on return to - user mode */ -#define TIF_IRET 4 /* return with iret */ -#define TIF_SYSCALL_EMU 5 /* syscall emulation active */ -#define TIF_SYSCALL_AUDIT 6 /* syscall auditing active */ -#define TIF_SECCOMP 7 /* secure computing */ -#define TIF_HRTICK_RESCHED 9 /* reprogram hrtick timer */ -#define TIF_MEMDIE 16 -#define TIF_DEBUG 17 /* uses debug registers */ -#define TIF_IO_BITMAP 18 /* uses I/O bitmap */ -#define TIF_FREEZE 19 /* is freezing for suspend */ -#define TIF_NOTSC 20 /* TSC is not accessible in userland */ -#define TIF_FORCED_TF 21 /* true if TF in eflags artificially */ -#define TIF_DEBUGCTLMSR 22 /* uses thread_struct.debugctlmsr */ -#define TIF_DS_AREA_MSR 23 /* uses thread_struct.ds_area_msr */ -#define TIF_BTS_TRACE_TS 24 /* record scheduling event timestamps */ - -#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) -#define _TIF_IRET (1 << TIF_IRET) -#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU) -#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) -#define _TIF_SECCOMP (1 << TIF_SECCOMP) -#define _TIF_HRTICK_RESCHED (1 << TIF_HRTICK_RESCHED) -#define _TIF_DEBUG (1 << TIF_DEBUG) -#define _TIF_IO_BITMAP (1 << TIF_IO_BITMAP) -#define _TIF_FREEZE (1 << TIF_FREEZE) -#define _TIF_NOTSC (1 << TIF_NOTSC) -#define _TIF_FORCED_TF (1 << TIF_FORCED_TF) -#define _TIF_DEBUGCTLMSR (1 << TIF_DEBUGCTLMSR) -#define _TIF_DS_AREA_MSR (1 << TIF_DS_AREA_MSR) -#define _TIF_BTS_TRACE_TS (1 << TIF_BTS_TRACE_TS) - -/* work to do on interrupt/exception return */ -#define _TIF_WORK_MASK \ - (0x0000FFFF & ~(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ - _TIF_SECCOMP | _TIF_SYSCALL_EMU)) -/* work to do on any return to u-space */ -#define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP) - -/* flags to check in __switch_to() */ -#define _TIF_WORK_CTXSW \ - (_TIF_IO_BITMAP | _TIF_NOTSC | _TIF_DEBUGCTLMSR | \ - _TIF_DS_AREA_MSR | _TIF_BTS_TRACE_TS) -#define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW -#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW | _TIF_DEBUG) - - -/* - * Thread-synchronous status. - * - * This is different from the flags in that nobody else - * ever touches our thread-synchronous status, so we don't - * have to worry about atomic accesses. - */ -#define TS_USEDFPU 0x0001 /* FPU was used by this task - this quantum (SMP) */ -#define TS_POLLING 0x0002 /* True if in idle loop - and not sleeping */ -#define TS_RESTORE_SIGMASK 0x0004 /* restore signal mask in do_signal() */ - -#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING) - -#ifndef __ASSEMBLY__ -#define HAVE_SET_RESTORE_SIGMASK 1 -static inline void set_restore_sigmask(void) -{ - struct thread_info *ti = current_thread_info(); - ti->status |= TS_RESTORE_SIGMASK; - set_bit(TIF_SIGPENDING, &ti->flags); -} -#endif /* !__ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_THREAD_INFO_H */ diff --git a/include/asm-x86/thread_info_64.h b/include/asm-x86/thread_info_64.h deleted file mode 100644 index cb69f70abba1..000000000000 --- a/include/asm-x86/thread_info_64.h +++ /dev/null @@ -1,195 +0,0 @@ -/* thread_info.h: x86_64 low-level thread information - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#ifdef __KERNEL__ - -#include <asm/page.h> -#include <asm/types.h> -#include <asm/pda.h> - -/* - * low level task data that entry.S needs immediate access to - * - this struct should fit entirely inside of one cache line - * - this struct shares the supervisor stack pages - */ -#ifndef __ASSEMBLY__ -struct task_struct; -struct exec_domain; -#include <asm/processor.h> - -struct thread_info { - struct task_struct *task; /* main task structure */ - struct exec_domain *exec_domain; /* execution domain */ - __u32 flags; /* low level flags */ - __u32 status; /* thread synchronous flags */ - __u32 cpu; /* current CPU */ - int preempt_count; /* 0 => preemptable, - <0 => BUG */ - mm_segment_t addr_limit; - struct restart_block restart_block; -#ifdef CONFIG_IA32_EMULATION - void __user *sysenter_return; -#endif -}; -#endif - -/* - * macros/functions for gaining access to the thread information structure - * preempt_count needs to be 1 initially, until the scheduler is functional. - */ -#ifndef __ASSEMBLY__ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = 1, \ - .addr_limit = KERNEL_DS, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) -#define init_stack (init_thread_union.stack) - -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - ti = (void *)(read_pda(kernelstack) + PDA_STACKOFFSET - THREAD_SIZE); - return ti; -} - -/* do not use in interrupt context */ -static inline struct thread_info *stack_thread_info(void) -{ - struct thread_info *ti; - asm("andq %%rsp,%0; " : "=r" (ti) : "0" (~(THREAD_SIZE - 1))); - return ti; -} - -/* thread information allocation */ -#ifdef CONFIG_DEBUG_STACK_USAGE -#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO) -#else -#define THREAD_FLAGS GFP_KERNEL -#endif - -#define alloc_thread_info(tsk) \ - ((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER)) - -#else /* !__ASSEMBLY__ */ - -/* how to get the thread information struct from ASM */ -#define GET_THREAD_INFO(reg) \ - movq %gs:pda_kernelstack,reg ; \ - subq $(THREAD_SIZE-PDA_STACKOFFSET),reg - -#endif - -/* - * thread information flags - * - these are process state flags that various assembly files - * may need to access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW - * Warning: layout of LSW is hardcoded in entry.S - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/ -#define TIF_IRET 5 /* force IRET */ -#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ -#define TIF_SECCOMP 8 /* secure computing */ -#define TIF_MCE_NOTIFY 10 /* notify userspace of an MCE */ -#define TIF_HRTICK_RESCHED 11 /* reprogram hrtick timer */ -/* 16 free */ -#define TIF_IA32 17 /* 32bit process */ -#define TIF_FORK 18 /* ret_from_fork */ -#define TIF_ABI_PENDING 19 -#define TIF_MEMDIE 20 -#define TIF_DEBUG 21 /* uses debug registers */ -#define TIF_IO_BITMAP 22 /* uses I/O bitmap */ -#define TIF_FREEZE 23 /* is freezing for suspend */ -#define TIF_FORCED_TF 24 /* true if TF in eflags artificially */ -#define TIF_DEBUGCTLMSR 25 /* uses thread_struct.debugctlmsr */ -#define TIF_DS_AREA_MSR 26 /* uses thread_struct.ds_area_msr */ -#define TIF_BTS_TRACE_TS 27 /* record scheduling event timestamps */ -#define TIF_NOTSC 28 /* TSC is not accessible in userland */ - -#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) -#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) -#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_IRET (1 << TIF_IRET) -#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) -#define _TIF_SECCOMP (1 << TIF_SECCOMP) -#define _TIF_MCE_NOTIFY (1 << TIF_MCE_NOTIFY) -#define _TIF_HRTICK_RESCHED (1 << TIF_HRTICK_RESCHED) -#define _TIF_IA32 (1 << TIF_IA32) -#define _TIF_FORK (1 << TIF_FORK) -#define _TIF_ABI_PENDING (1 << TIF_ABI_PENDING) -#define _TIF_DEBUG (1 << TIF_DEBUG) -#define _TIF_IO_BITMAP (1 << TIF_IO_BITMAP) -#define _TIF_FREEZE (1 << TIF_FREEZE) -#define _TIF_FORCED_TF (1 << TIF_FORCED_TF) -#define _TIF_DEBUGCTLMSR (1 << TIF_DEBUGCTLMSR) -#define _TIF_DS_AREA_MSR (1 << TIF_DS_AREA_MSR) -#define _TIF_BTS_TRACE_TS (1 << TIF_BTS_TRACE_TS) -#define _TIF_NOTSC (1 << TIF_NOTSC) - -/* work to do on interrupt/exception return */ -#define _TIF_WORK_MASK \ - (0x0000FFFF & \ - ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP|_TIF_SECCOMP)) -/* work to do on any return to user space */ -#define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP) - -#define _TIF_DO_NOTIFY_MASK \ - (_TIF_SIGPENDING|_TIF_SINGLESTEP|_TIF_MCE_NOTIFY|_TIF_HRTICK_RESCHED) - -/* flags to check in __switch_to() */ -#define _TIF_WORK_CTXSW \ - (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS|_TIF_NOTSC) -#define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW -#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG) - -#define PREEMPT_ACTIVE 0x10000000 - -/* - * Thread-synchronous status. - * - * This is different from the flags in that nobody else - * ever touches our thread-synchronous status, so we don't - * have to worry about atomic accesses. - */ -#define TS_USEDFPU 0x0001 /* FPU was used by this task - this quantum (SMP) */ -#define TS_COMPAT 0x0002 /* 32bit syscall active */ -#define TS_POLLING 0x0004 /* true if in idle loop - and not sleeping */ -#define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal() */ - -#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING) - -#ifndef __ASSEMBLY__ -#define HAVE_SET_RESTORE_SIGMASK 1 -static inline void set_restore_sigmask(void) -{ - struct thread_info *ti = current_thread_info(); - ti->status |= TS_RESTORE_SIGMASK; - set_bit(TIF_SIGPENDING, &ti->flags); -} -#endif /* !__ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_THREAD_INFO_H */ diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h index dcf3f8131d6b..1f97758de4ab 100644 --- a/include/asm-x86/topology.h +++ b/include/asm-x86/topology.h @@ -35,79 +35,88 @@ # endif #endif +/* Node not present */ +#define NUMA_NO_NODE (-1) + #ifdef CONFIG_NUMA #include <linux/cpumask.h> #include <asm/mpspec.h> -/* Mappings between logical cpu number and node number */ #ifdef CONFIG_X86_32 -extern int cpu_to_node_map[]; -#else -/* Returns the number of the current Node. */ -#define numa_node_id() (early_cpu_to_node(raw_smp_processor_id())) -#endif - -DECLARE_PER_CPU(int, x86_cpu_to_node_map); - -#ifdef CONFIG_SMP -extern int x86_cpu_to_node_map_init[]; -extern void *x86_cpu_to_node_map_early_ptr; -#else -#define x86_cpu_to_node_map_early_ptr NULL -#endif +/* Mappings between node number and cpus on that node. */ extern cpumask_t node_to_cpumask_map[]; -#define NUMA_NO_NODE (-1) +/* Mappings between logical cpu number and node number */ +extern int cpu_to_node_map[]; /* Returns the number of the node containing CPU 'cpu' */ -#ifdef CONFIG_X86_32 -#define early_cpu_to_node(cpu) cpu_to_node(cpu) static inline int cpu_to_node(int cpu) { return cpu_to_node_map[cpu]; } +#define early_cpu_to_node(cpu) cpu_to_node(cpu) -#else /* CONFIG_X86_64 */ - -#ifdef CONFIG_SMP -static inline int early_cpu_to_node(int cpu) +/* Returns a bitmask of CPUs on Node 'node'. */ +static inline cpumask_t node_to_cpumask(int node) { - int *cpu_to_node_map = x86_cpu_to_node_map_early_ptr; - - if (cpu_to_node_map) - return cpu_to_node_map[cpu]; - else if (per_cpu_offset(cpu)) - return per_cpu(x86_cpu_to_node_map, cpu); - else - return NUMA_NO_NODE; + return node_to_cpumask_map[node]; } -#else -#define early_cpu_to_node(cpu) cpu_to_node(cpu) -#endif +#else /* CONFIG_X86_64 */ + +/* Mappings between node number and cpus on that node. */ +extern cpumask_t *node_to_cpumask_map; + +/* Mappings between logical cpu number and node number */ +DECLARE_EARLY_PER_CPU(int, x86_cpu_to_node_map); + +/* Returns the number of the current Node. */ +#define numa_node_id() read_pda(nodenumber) + +#ifdef CONFIG_DEBUG_PER_CPU_MAPS +extern int cpu_to_node(int cpu); +extern int early_cpu_to_node(int cpu); +extern cpumask_t *_node_to_cpumask_ptr(int node); +extern cpumask_t node_to_cpumask(int node); + +#else /* !CONFIG_DEBUG_PER_CPU_MAPS */ + +/* Returns the number of the node containing CPU 'cpu' */ static inline int cpu_to_node(int cpu) { -#ifdef CONFIG_DEBUG_PER_CPU_MAPS - if (x86_cpu_to_node_map_early_ptr) { - printk("KERN_NOTICE cpu_to_node(%d): usage too early!\n", - (int)cpu); - dump_stack(); - return ((int *)x86_cpu_to_node_map_early_ptr)[cpu]; - } -#endif return per_cpu(x86_cpu_to_node_map, cpu); } -#ifdef CONFIG_NUMA +/* Same function but used if called before per_cpu areas are setup */ +static inline int early_cpu_to_node(int cpu) +{ + if (early_per_cpu_ptr(x86_cpu_to_node_map)) + return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu]; + + return per_cpu(x86_cpu_to_node_map, cpu); +} /* Returns a pointer to the cpumask of CPUs on Node 'node'. */ +static inline cpumask_t *_node_to_cpumask_ptr(int node) +{ + return &node_to_cpumask_map[node]; +} + +/* Returns a bitmask of CPUs on Node 'node'. */ +static inline cpumask_t node_to_cpumask(int node) +{ + return node_to_cpumask_map[node]; +} + +#endif /* !CONFIG_DEBUG_PER_CPU_MAPS */ + +/* Replace default node_to_cpumask_ptr with optimized version */ #define node_to_cpumask_ptr(v, node) \ - cpumask_t *v = &(node_to_cpumask_map[node]) + cpumask_t *v = _node_to_cpumask_ptr(node) #define node_to_cpumask_ptr_next(v, node) \ - v = &(node_to_cpumask_map[node]) -#endif + v = _node_to_cpumask_ptr(node) #endif /* CONFIG_X86_64 */ @@ -117,20 +126,6 @@ static inline int cpu_to_node(int cpu) */ #define parent_node(node) (node) -/* Returns a bitmask of CPUs on Node 'node'. */ -static inline cpumask_t node_to_cpumask(int node) -{ - return node_to_cpumask_map[node]; -} - -/* Returns the number of the first CPU on Node 'node'. */ -static inline int node_to_first_cpu(int node) -{ - cpumask_t mask = node_to_cpumask(node); - - return first_cpu(mask); -} - #define pcibus_to_node(bus) __pcibus_to_node(bus) #define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus) @@ -180,12 +175,44 @@ extern int __node_distance(int, int); #define node_distance(a, b) __node_distance(a, b) #endif -#else /* CONFIG_NUMA */ +#else /* !CONFIG_NUMA */ +#define numa_node_id() 0 +#define cpu_to_node(cpu) 0 +#define early_cpu_to_node(cpu) 0 + +static inline cpumask_t *_node_to_cpumask_ptr(int node) +{ + return &cpu_online_map; +} +static inline cpumask_t node_to_cpumask(int node) +{ + return cpu_online_map; +} +static inline int node_to_first_cpu(int node) +{ + return first_cpu(cpu_online_map); +} + +/* Replace default node_to_cpumask_ptr with optimized version */ +#define node_to_cpumask_ptr(v, node) \ + cpumask_t *v = _node_to_cpumask_ptr(node) + +#define node_to_cpumask_ptr_next(v, node) \ + v = _node_to_cpumask_ptr(node) #endif #include <asm-generic/topology.h> +#ifdef CONFIG_NUMA +/* Returns the number of the first CPU on Node 'node'. */ +static inline int node_to_first_cpu(int node) +{ + node_to_cpumask_ptr(mask, node); + return first_cpu(*mask); +} +#endif + extern cpumask_t cpu_coregroup_map(int cpu); #ifdef ENABLE_TOPO_DEFINES @@ -193,6 +220,9 @@ extern cpumask_t cpu_coregroup_map(int cpu); #define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id) #define topology_core_siblings(cpu) (per_cpu(cpu_core_map, cpu)) #define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu)) + +/* indicates that pointers to the topology cpumask_t maps are valid */ +#define arch_provides_topology_pointers yes #endif static inline void arch_fix_phys_package_id(int num, u32 slot) @@ -220,4 +250,4 @@ static inline void set_mp_bus_to_node(int busnum, int node) } #endif -#endif +#endif /* _ASM_X86_TOPOLOGY_H */ diff --git a/include/asm-x86/uv/uv_hub.h b/include/asm-x86/uv/uv_hub.h index 26b9240d1e23..65004881de5f 100644 --- a/include/asm-x86/uv/uv_hub.h +++ b/include/asm-x86/uv/uv_hub.h @@ -5,7 +5,7 @@ * * SGI UV architectural definitions * - * Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. */ #ifndef __ASM_X86_UV_HUB_H__ @@ -20,26 +20,49 @@ /* * Addressing Terminology * - * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of - * routers always have low bit of 1, C/MBricks have low bit - * equal to 0. Most addressing macros that target UV hub chips - * right shift the NASID by 1 to exclude the always-zero bit. + * M - The low M bits of a physical address represent the offset + * into the blade local memory. RAM memory on a blade is physically + * contiguous (although various IO spaces may punch holes in + * it).. * - * SNASID - NASID right shifted by 1 bit. + * N - Number of bits in the node portion of a socket physical + * address. + * + * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of + * routers always have low bit of 1, C/MBricks have low bit + * equal to 0. Most addressing macros that target UV hub chips + * right shift the NASID by 1 to exclude the always-zero bit. + * NASIDs contain up to 15 bits. + * + * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead + * of nasids. + * + * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant + * of the nasid for socket usage. + * + * + * NumaLink Global Physical Address Format: + * +--------------------------------+---------------------+ + * |00..000| GNODE | NodeOffset | + * +--------------------------------+---------------------+ + * |<-------53 - M bits --->|<--------M bits -----> + * + * M - number of node offset bits (35 .. 40) * * * Memory/UV-HUB Processor Socket Address Format: - * +--------+---------------+---------------------+ - * |00..0000| SNASID | NodeOffset | - * +--------+---------------+---------------------+ - * <--- N bits --->|<--------M bits -----> + * +----------------+---------------+---------------------+ + * |00..000000000000| PNODE | NodeOffset | + * +----------------+---------------+---------------------+ + * <--- N bits --->|<--------M bits -----> * - * M number of node offset bits (35 .. 40) - * N number of SNASID bits (0 .. 10) + * M - number of node offset bits (35 .. 40) + * N - number of PNODE bits (0 .. 10) * * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). * The actual values are configuration dependent and are set at - * boot time + * boot time. M & N values are set by the hardware/BIOS at boot. + * * * APICID format * NOTE!!!!!! This is the current format of the APICID. However, code @@ -48,14 +71,14 @@ * * 1111110000000000 * 5432109876543210 - * nnnnnnnnnnlc0cch + * pppppppppplc0cch * sssssssssss * - * n = snasid bits + * p = pnode bits * l = socket number on board * c = core * h = hyperthread - * s = bits that are in the socket CSR + * s = bits that are in the SOCKET_ID CSR * * Note: Processor only supports 12 bits in the APICID register. The ACPI * tables hold all 16 bits. Software needs to be aware of this. @@ -74,7 +97,7 @@ * This value is also the value of the maximum number of non-router NASIDs * in the numalink fabric. * - * NOTE: a brick may be 1 or 2 OS nodes. Don't get these confused. + * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. */ #define UV_MAX_NUMALINK_BLADES 16384 @@ -96,8 +119,12 @@ */ struct uv_hub_info_s { unsigned long global_mmr_base; - unsigned short local_nasid; - unsigned short gnode_upper; + unsigned long gpa_mask; + unsigned long gnode_upper; + unsigned long lowmem_remap_top; + unsigned long lowmem_remap_base; + unsigned short pnode; + unsigned short pnode_mask; unsigned short coherency_domain_number; unsigned short numa_blade_id; unsigned char blade_processor_id; @@ -112,83 +139,124 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); * Local & Global MMR space macros. * Note: macros are intended to be used ONLY by inline functions * in this file - not by other kernel code. + * n - NASID (full 15-bit global nasid) + * g - GNODE (full 15-bit global nasid, right shifted 1) + * p - PNODE (local part of nsids, right shifted 1) */ -#define UV_SNASID(n) ((n) >> 1) -#define UV_NASID(n) ((n) << 1) +#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) +#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper) #define UV_LOCAL_MMR_BASE 0xf4000000UL #define UV_GLOBAL_MMR32_BASE 0xf8000000UL #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) -#define UV_GLOBAL_MMR32_SNASID_MASK 0x3ff -#define UV_GLOBAL_MMR32_SNASID_SHIFT 15 -#define UV_GLOBAL_MMR64_SNASID_SHIFT 26 +#define UV_GLOBAL_MMR32_PNODE_SHIFT 15 +#define UV_GLOBAL_MMR64_PNODE_SHIFT 26 -#define UV_GLOBAL_MMR32_NASID_BITS(n) \ - (((UV_SNASID(n) & UV_GLOBAL_MMR32_SNASID_MASK)) << \ - (UV_GLOBAL_MMR32_SNASID_SHIFT)) +#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) -#define UV_GLOBAL_MMR64_NASID_BITS(n) \ - ((unsigned long)UV_SNASID(n) << UV_GLOBAL_MMR64_SNASID_SHIFT) +#define UV_GLOBAL_MMR64_PNODE_BITS(p) \ + ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT) + +#define UV_APIC_PNODE_SHIFT 6 + +/* + * Macros for converting between kernel virtual addresses, socket local physical + * addresses, and UV global physical addresses. + * Note: use the standard __pa() & __va() macros for converting + * between socket virtual and socket physical addresses. + */ + +/* socket phys RAM --> UV global physical address */ +static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) +{ + if (paddr < uv_hub_info->lowmem_remap_top) + paddr += uv_hub_info->lowmem_remap_base; + return paddr | uv_hub_info->gnode_upper; +} + + +/* socket virtual --> UV global physical address */ +static inline unsigned long uv_gpa(void *v) +{ + return __pa(v) | uv_hub_info->gnode_upper; +} + +/* socket virtual --> UV global physical address */ +static inline void *uv_vgpa(void *v) +{ + return (void *)uv_gpa(v); +} + +/* UV global physical address --> socket virtual */ +static inline void *uv_va(unsigned long gpa) +{ + return __va(gpa & uv_hub_info->gpa_mask); +} + +/* pnode, offset --> socket virtual */ +static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) +{ + return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); +} -#define UV_APIC_NASID_SHIFT 6 /* - * Extract a NASID from an APICID (full apicid, not processor subset) + * Extract a PNODE from an APICID (full apicid, not processor subset) */ -static inline int uv_apicid_to_nasid(int apicid) +static inline int uv_apicid_to_pnode(int apicid) { - return (UV_NASID(apicid >> UV_APIC_NASID_SHIFT)); + return (apicid >> UV_APIC_PNODE_SHIFT); } /* * Access global MMRs using the low memory MMR32 space. This region supports * faster MMR access but not all MMRs are accessible in this space. */ -static inline unsigned long *uv_global_mmr32_address(int nasid, +static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) { return __va(UV_GLOBAL_MMR32_BASE | - UV_GLOBAL_MMR32_NASID_BITS(nasid) | offset); + UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); } -static inline void uv_write_global_mmr32(int nasid, unsigned long offset, +static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) { - *uv_global_mmr32_address(nasid, offset) = val; + *uv_global_mmr32_address(pnode, offset) = val; } -static inline unsigned long uv_read_global_mmr32(int nasid, +static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) { - return *uv_global_mmr32_address(nasid, offset); + return *uv_global_mmr32_address(pnode, offset); } /* * Access Global MMR space using the MMR space located at the top of physical * memory. */ -static inline unsigned long *uv_global_mmr64_address(int nasid, +static inline unsigned long *uv_global_mmr64_address(int pnode, unsigned long offset) { return __va(UV_GLOBAL_MMR64_BASE | - UV_GLOBAL_MMR64_NASID_BITS(nasid) | offset); + UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); } -static inline void uv_write_global_mmr64(int nasid, unsigned long offset, +static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) { - *uv_global_mmr64_address(nasid, offset) = val; + *uv_global_mmr64_address(pnode, offset) = val; } -static inline unsigned long uv_read_global_mmr64(int nasid, +static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) { - return *uv_global_mmr64_address(nasid, offset); + return *uv_global_mmr64_address(pnode, offset); } /* - * Access node local MMRs. Faster than using global space but only local MMRs + * Access hub local MMRs. Faster than using global space but only local MMRs * are accessible. */ static inline unsigned long *uv_local_mmr_address(unsigned long offset) @@ -207,15 +275,15 @@ static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) } /* - * Structures and definitions for converting between cpu, node, and blade + * Structures and definitions for converting between cpu, node, pnode, and blade * numbers. */ struct uv_blade_info { - unsigned short nr_posible_cpus; + unsigned short nr_possible_cpus; unsigned short nr_online_cpus; - unsigned short nasid; + unsigned short pnode; }; -struct uv_blade_info *uv_blade_info; +extern struct uv_blade_info *uv_blade_info; extern short *uv_node_to_blade; extern short *uv_cpu_to_blade; extern short uv_possible_blades; @@ -244,16 +312,16 @@ static inline int uv_node_to_blade_id(int nid) return uv_node_to_blade[nid]; } -/* Convert a blade id to the NASID of the blade */ -static inline int uv_blade_to_nasid(int bid) +/* Convert a blade id to the PNODE of the blade */ +static inline int uv_blade_to_pnode(int bid) { - return uv_blade_info[bid].nasid; + return uv_blade_info[bid].pnode; } /* Determine the number of possible cpus on a blade */ static inline int uv_blade_nr_possible_cpus(int bid) { - return uv_blade_info[bid].nr_posible_cpus; + return uv_blade_info[bid].nr_possible_cpus; } /* Determine the number of online cpus on a blade */ @@ -262,16 +330,16 @@ static inline int uv_blade_nr_online_cpus(int bid) return uv_blade_info[bid].nr_online_cpus; } -/* Convert a cpu id to the NASID of the blade containing the cpu */ -static inline int uv_cpu_to_nasid(int cpu) +/* Convert a cpu id to the PNODE of the blade containing the cpu */ +static inline int uv_cpu_to_pnode(int cpu) { - return uv_blade_info[uv_cpu_to_blade_id(cpu)].nasid; + return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; } -/* Convert a node number to the NASID of the blade */ -static inline int uv_node_to_nasid(int nid) +/* Convert a linux node number to the PNODE of the blade */ +static inline int uv_node_to_pnode(int nid) { - return uv_blade_info[uv_node_to_blade_id(nid)].nasid; + return uv_blade_info[uv_node_to_blade_id(nid)].pnode; } /* Maximum possible number of blades */ diff --git a/include/asm-x86/uv/uv_mmrs.h b/include/asm-x86/uv/uv_mmrs.h index 3b69fe6b6376..ac9846076521 100644 --- a/include/asm-x86/uv/uv_mmrs.h +++ b/include/asm-x86/uv/uv_mmrs.h @@ -11,11 +11,46 @@ #ifndef __ASM_X86_UV_MMRS__ #define __ASM_X86_UV_MMRS__ -/* - * AUTO GENERATED - Do not edit - */ +#define UV_MMR_ENABLE (1UL << 63) - #define UV_MMR_ENABLE (1UL << 63) +/* ========================================================================= */ +/* UVH_BAU_DATA_CONFIG */ +/* ========================================================================= */ +#define UVH_BAU_DATA_CONFIG 0x61680UL +#define UVH_BAU_DATA_CONFIG_32 0x0450 + +#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 +#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL +#define UVH_BAU_DATA_CONFIG_DM_SHFT 8 +#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL +#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 +#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL +#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 +#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL +#define UVH_BAU_DATA_CONFIG_P_SHFT 13 +#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL +#define UVH_BAU_DATA_CONFIG_T_SHFT 15 +#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL +#define UVH_BAU_DATA_CONFIG_M_SHFT 16 +#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL +#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 +#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL + +union uvh_bau_data_config_u { + unsigned long v; + struct uvh_bau_data_config_s { + unsigned long vector_ : 8; /* RW */ + unsigned long dm : 3; /* RW */ + unsigned long destmode : 1; /* RW */ + unsigned long status : 1; /* RO */ + unsigned long p : 1; /* RO */ + unsigned long rsvd_14 : 1; /* */ + unsigned long t : 1; /* RO */ + unsigned long m : 1; /* RW */ + unsigned long rsvd_17_31: 15; /* */ + unsigned long apic_id : 32; /* RW */ + } s; +}; /* ========================================================================= */ /* UVH_IPI_INT */ @@ -109,6 +144,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u { /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ /* ========================================================================= */ #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL +#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0aa0 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL @@ -169,6 +205,7 @@ union uvh_lb_bau_intd_software_acknowledge_u { /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ /* ========================================================================= */ #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL +#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0aa8 /* ========================================================================= */ /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ @@ -248,6 +285,331 @@ union uvh_lb_bau_sb_descriptor_base_u { }; /* ========================================================================= */ +/* UVH_LB_MCAST_AOERR0_RPT_ENABLE */ +/* ========================================================================= */ +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL + +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_TIMEOUT_SHFT 22 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_TIMEOUT_MASK 0x0000000000400000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 23 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000000800000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 24 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000001000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 25 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000002000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 26 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000004000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 27 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000008000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 28 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000010000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 29 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000020000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 30 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000040000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 31 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000080000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 32 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000100000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 33 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000200000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 34 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000400000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 35 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000000800000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 36 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000001000000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 37 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000002000000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 38 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000004000000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 39 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000008000000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 40 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000010000000000UL +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 41 +#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000020000000000UL + +union uvh_lb_mcast_aoerr0_rpt_enable_u { + unsigned long v; + struct uvh_lb_mcast_aoerr0_rpt_enable_s { + unsigned long mcast_obese_msg : 1; /* RW */ + unsigned long mcast_data_sb_err : 1; /* RW */ + unsigned long mcast_nack_buff_parity : 1; /* RW */ + unsigned long mcast_timeout : 1; /* RW */ + unsigned long mcast_inactive_reply : 1; /* RW */ + unsigned long mcast_upgrade_error : 1; /* RW */ + unsigned long mcast_reg_count_underflow : 1; /* RW */ + unsigned long mcast_rep_obese_msg : 1; /* RW */ + unsigned long ucache_req_runt_msg : 1; /* RW */ + unsigned long ucache_req_obese_msg : 1; /* RW */ + unsigned long ucache_req_data_sb_err : 1; /* RW */ + unsigned long ucache_rep_runt_msg : 1; /* RW */ + unsigned long ucache_rep_obese_msg : 1; /* RW */ + unsigned long ucache_rep_data_sb_err : 1; /* RW */ + unsigned long ucache_rep_command_err : 1; /* RW */ + unsigned long ucache_pend_timeout : 1; /* RW */ + unsigned long macc_req_runt_msg : 1; /* RW */ + unsigned long macc_req_obese_msg : 1; /* RW */ + unsigned long macc_req_data_sb_err : 1; /* RW */ + unsigned long macc_rep_runt_msg : 1; /* RW */ + unsigned long macc_rep_obese_msg : 1; /* RW */ + unsigned long macc_rep_data_sb_err : 1; /* RW */ + unsigned long macc_timeout : 1; /* RW */ + unsigned long macc_spurious_event : 1; /* RW */ + unsigned long ioh_destination_table_parity : 1; /* RW */ + unsigned long get_had_error_reply : 1; /* RW */ + unsigned long get_timeout : 1; /* RW */ + unsigned long lock_manager_had_error_reply : 1; /* RW */ + unsigned long put_had_error_reply : 1; /* RW */ + unsigned long put_timeout : 1; /* RW */ + unsigned long sb_activation_overrun : 1; /* RW */ + unsigned long completed_gb_activation_had_error_reply : 1; /* RW */ + unsigned long completed_gb_activation_timeout : 1; /* RW */ + unsigned long descriptor_buffer_0_parity : 1; /* RW */ + unsigned long descriptor_buffer_1_parity : 1; /* RW */ + unsigned long socket_destination_table_parity : 1; /* RW */ + unsigned long bau_reply_payload_corruption : 1; /* RW */ + unsigned long io_port_destination_table_parity : 1; /* RW */ + unsigned long intd_soft_ack_timeout : 1; /* RW */ + unsigned long int_rep_obese_msg : 1; /* RW */ + unsigned long int_rep_command_err : 1; /* RW */ + unsigned long int_timeout : 1; /* RW */ + unsigned long rsvd_42_63 : 22; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_LOCAL_INT0_CONFIG */ +/* ========================================================================= */ +#define UVH_LOCAL_INT0_CONFIG 0x61000UL + +#define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0 +#define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL +#define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8 +#define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL +#define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11 +#define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL +#define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12 +#define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL +#define UVH_LOCAL_INT0_CONFIG_P_SHFT 13 +#define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL +#define UVH_LOCAL_INT0_CONFIG_T_SHFT 15 +#define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL +#define UVH_LOCAL_INT0_CONFIG_M_SHFT 16 +#define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL +#define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32 +#define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL + +union uvh_local_int0_config_u { + unsigned long v; + struct uvh_local_int0_config_s { + unsigned long vector_ : 8; /* RW */ + unsigned long dm : 3; /* RW */ + unsigned long destmode : 1; /* RW */ + unsigned long status : 1; /* RO */ + unsigned long p : 1; /* RO */ + unsigned long rsvd_14 : 1; /* */ + unsigned long t : 1; /* RO */ + unsigned long m : 1; /* RW */ + unsigned long rsvd_17_31: 15; /* */ + unsigned long apic_id : 32; /* RW */ + } s; +}; + +/* ========================================================================= */ +/* UVH_LOCAL_INT0_ENABLE */ +/* ========================================================================= */ +#define UVH_LOCAL_INT0_ENABLE 0x65000UL + +#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0 +#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL +#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1 +#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL +#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2 +#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL +#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3 +#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL +#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4 +#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL +#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5 +#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL +#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6 +#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL +#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7 +#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL +#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8 +#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL +#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9 +#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL +#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10 +#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL +#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11 +#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL +#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12 +#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL +#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13 +#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL +#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14 +#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL +#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15 +#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL +#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16 +#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL +#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17 +#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL +#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18 +#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL +#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19 +#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL +#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20 +#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL +#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21 +#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL +#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22 +#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38 +#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL +#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39 +#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL +#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40 +#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL +#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41 +#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL +#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42 +#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL +#define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43 +#define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL +#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44 +#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL + +union uvh_local_int0_enable_u { + unsigned long v; + struct uvh_local_int0_enable_s { + unsigned long lb_hcerr : 1; /* RW */ + unsigned long gr0_hcerr : 1; /* RW */ + unsigned long gr1_hcerr : 1; /* RW */ + unsigned long lh_hcerr : 1; /* RW */ + unsigned long rh_hcerr : 1; /* RW */ + unsigned long xn_hcerr : 1; /* RW */ + unsigned long si_hcerr : 1; /* RW */ + unsigned long lb_aoerr0 : 1; /* RW */ + unsigned long gr0_aoerr0 : 1; /* RW */ + unsigned long gr1_aoerr0 : 1; /* RW */ + unsigned long lh_aoerr0 : 1; /* RW */ + unsigned long rh_aoerr0 : 1; /* RW */ + unsigned long xn_aoerr0 : 1; /* RW */ + unsigned long si_aoerr0 : 1; /* RW */ + unsigned long lb_aoerr1 : 1; /* RW */ + unsigned long gr0_aoerr1 : 1; /* RW */ + unsigned long gr1_aoerr1 : 1; /* RW */ + unsigned long lh_aoerr1 : 1; /* RW */ + unsigned long rh_aoerr1 : 1; /* RW */ + unsigned long xn_aoerr1 : 1; /* RW */ + unsigned long si_aoerr1 : 1; /* RW */ + unsigned long rh_vpi_int : 1; /* RW */ + unsigned long system_shutdown_int : 1; /* RW */ + unsigned long lb_irq_int_0 : 1; /* RW */ + unsigned long lb_irq_int_1 : 1; /* RW */ + unsigned long lb_irq_int_2 : 1; /* RW */ + unsigned long lb_irq_int_3 : 1; /* RW */ + unsigned long lb_irq_int_4 : 1; /* RW */ + unsigned long lb_irq_int_5 : 1; /* RW */ + unsigned long lb_irq_int_6 : 1; /* RW */ + unsigned long lb_irq_int_7 : 1; /* RW */ + unsigned long lb_irq_int_8 : 1; /* RW */ + unsigned long lb_irq_int_9 : 1; /* RW */ + unsigned long lb_irq_int_10 : 1; /* RW */ + unsigned long lb_irq_int_11 : 1; /* RW */ + unsigned long lb_irq_int_12 : 1; /* RW */ + unsigned long lb_irq_int_13 : 1; /* RW */ + unsigned long lb_irq_int_14 : 1; /* RW */ + unsigned long lb_irq_int_15 : 1; /* RW */ + unsigned long l1_nmi_int : 1; /* RW */ + unsigned long stop_clock : 1; /* RW */ + unsigned long asic_to_l1 : 1; /* RW */ + unsigned long l1_to_asic : 1; /* RW */ + unsigned long ltc_int : 1; /* RW */ + unsigned long la_seq_trigger : 1; /* RW */ + unsigned long rsvd_45_63 : 19; /* */ + } s; +}; + +/* ========================================================================= */ /* UVH_NODE_ID */ /* ========================================================================= */ #define UVH_NODE_ID 0x0UL @@ -284,6 +646,73 @@ union uvh_node_id_u { }; /* ========================================================================= */ +/* UVH_NODE_PRESENT_TABLE */ +/* ========================================================================= */ +#define UVH_NODE_PRESENT_TABLE 0x1400UL +#define UVH_NODE_PRESENT_TABLE_DEPTH 16 + +#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 +#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL + +union uvh_node_present_table_u { + unsigned long v; + struct uvh_node_present_table_s { + unsigned long nodes : 64; /* RW */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ +/* ========================================================================= */ +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL + +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL + +union uvh_rh_gam_alias210_redirect_config_0_mmr_u { + unsigned long v; + struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { + unsigned long rsvd_0_23 : 24; /* */ + unsigned long dest_base : 22; /* RW */ + unsigned long rsvd_46_63: 18; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ +/* ========================================================================= */ +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL + +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL + +union uvh_rh_gam_alias210_redirect_config_1_mmr_u { + unsigned long v; + struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { + unsigned long rsvd_0_23 : 24; /* */ + unsigned long dest_base : 22; /* RW */ + unsigned long rsvd_46_63: 18; /* */ + } s; +}; + +/* ========================================================================= */ +/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ +/* ========================================================================= */ +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL + +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 +#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL + +union uvh_rh_gam_alias210_redirect_config_2_mmr_u { + unsigned long v; + struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { + unsigned long rsvd_0_23 : 24; /* */ + unsigned long dest_base : 22; /* RW */ + unsigned long rsvd_46_63: 18; /* */ + } s; +}; + +/* ========================================================================= */ /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ /* ========================================================================= */ #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL @@ -369,5 +798,77 @@ union uvh_si_addr_map_config_u { } s; }; +/* ========================================================================= */ +/* UVH_SI_ALIAS0_OVERLAY_CONFIG */ +/* ========================================================================= */ +#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL + +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24 +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48 +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63 +#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL + +union uvh_si_alias0_overlay_config_u { + unsigned long v; + struct uvh_si_alias0_overlay_config_s { + unsigned long rsvd_0_23: 24; /* */ + unsigned long base : 8; /* RW */ + unsigned long rsvd_32_47: 16; /* */ + unsigned long m_alias : 5; /* RW */ + unsigned long rsvd_53_62: 10; /* */ + unsigned long enable : 1; /* RW */ + } s; +}; + +/* ========================================================================= */ +/* UVH_SI_ALIAS1_OVERLAY_CONFIG */ +/* ========================================================================= */ +#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL + +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24 +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48 +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63 +#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL + +union uvh_si_alias1_overlay_config_u { + unsigned long v; + struct uvh_si_alias1_overlay_config_s { + unsigned long rsvd_0_23: 24; /* */ + unsigned long base : 8; /* RW */ + unsigned long rsvd_32_47: 16; /* */ + unsigned long m_alias : 5; /* RW */ + unsigned long rsvd_53_62: 10; /* */ + unsigned long enable : 1; /* RW */ + } s; +}; + +/* ========================================================================= */ +/* UVH_SI_ALIAS2_OVERLAY_CONFIG */ +/* ========================================================================= */ +#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL + +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24 +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48 +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63 +#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL + +union uvh_si_alias2_overlay_config_u { + unsigned long v; + struct uvh_si_alias2_overlay_config_s { + unsigned long rsvd_0_23: 24; /* */ + unsigned long base : 8; /* RW */ + unsigned long rsvd_32_47: 16; /* */ + unsigned long m_alias : 5; /* RW */ + unsigned long rsvd_53_62: 10; /* */ + unsigned long enable : 1; /* RW */ + } s; +}; + #endif /* __ASM_X86_UV_MMRS__ */ diff --git a/include/asm-x86/vm86.h b/include/asm-x86/vm86.h index 074b357146df..5ce351325e01 100644 --- a/include/asm-x86/vm86.h +++ b/include/asm-x86/vm86.h @@ -14,12 +14,6 @@ #include <asm/processor-flags.h> -#ifdef CONFIG_VM86 -#define X86_VM_MASK X86_EFLAGS_VM -#else -#define X86_VM_MASK 0 /* No VM86 support */ -#endif - #define BIOSSEG 0x0f000 #define CPU_086 0 @@ -121,7 +115,6 @@ struct vm86plus_info_struct { unsigned long is_vm86pus:1; /* for vm86 internal use */ unsigned char vm86dbg_intxxtab[32]; /* for debugger */ }; - struct vm86plus_struct { struct vm86_regs regs; unsigned long flags; @@ -133,6 +126,9 @@ struct vm86plus_struct { }; #ifdef __KERNEL__ + +#include <asm/ptrace.h> + /* * This is the (kernel) stack-layout when we have done a "SAVE_ALL" from vm86 * mode - the main change is that the old segment descriptors aren't @@ -141,7 +137,6 @@ struct vm86plus_struct { * at the end of the structure. Look at ptrace.h to see the "normal" * setup. For user space layout see 'struct vm86_regs' above. */ -#include <asm/ptrace.h> struct kernel_vm86_regs { /* diff --git a/include/asm-x86/vsyscall.h b/include/asm-x86/vsyscall.h index 17b3700949bf..6b66ff905af0 100644 --- a/include/asm-x86/vsyscall.h +++ b/include/asm-x86/vsyscall.h @@ -24,7 +24,8 @@ enum vsyscall_num { ((unused, __section__ (".vsyscall_gtod_data"),aligned(16))) #define __section_vsyscall_clock __attribute__ \ ((unused, __section__ (".vsyscall_clock"),aligned(16))) -#define __vsyscall_fn __attribute__ ((unused,__section__(".vsyscall_fn"))) +#define __vsyscall_fn \ + __attribute__ ((unused, __section__(".vsyscall_fn"))) notrace #define VGETCPU_RDTSCP 1 #define VGETCPU_LSL 2 diff --git a/include/asm-x86/xen/hypercall.h b/include/asm-x86/xen/hypercall.h index c2ccd997ed35..2a4f9b41d684 100644 --- a/include/asm-x86/xen/hypercall.h +++ b/include/asm-x86/xen/hypercall.h @@ -176,9 +176,9 @@ HYPERVISOR_fpu_taskswitch(int set) } static inline int -HYPERVISOR_sched_op(int cmd, unsigned long arg) +HYPERVISOR_sched_op(int cmd, void *arg) { - return _hypercall2(int, sched_op, cmd, arg); + return _hypercall2(int, sched_op_new, cmd, arg); } static inline long @@ -315,6 +315,13 @@ HYPERVISOR_nmi_op(unsigned long op, unsigned long arg) } static inline void +MULTI_fpu_taskswitch(struct multicall_entry *mcl, int set) +{ + mcl->op = __HYPERVISOR_fpu_taskswitch; + mcl->args[0] = set; +} + +static inline void MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va, pte_t new_val, unsigned long flags) { diff --git a/include/asm-x86/xen/page.h b/include/asm-x86/xen/page.h index baf3a4dce28c..377c04591c15 100644 --- a/include/asm-x86/xen/page.h +++ b/include/asm-x86/xen/page.h @@ -26,15 +26,20 @@ typedef struct xpaddr { #define FOREIGN_FRAME_BIT (1UL<<31) #define FOREIGN_FRAME(m) ((m) | FOREIGN_FRAME_BIT) -extern unsigned long *phys_to_machine_mapping; +/* Maximum amount of memory we can handle in a domain in pages */ +#define MAX_DOMAIN_PAGES \ + ((unsigned long)((u64)CONFIG_XEN_MAX_DOMAIN_MEMORY * 1024 * 1024 * 1024 / PAGE_SIZE)) + + +extern unsigned long get_phys_to_machine(unsigned long pfn); +extern void set_phys_to_machine(unsigned long pfn, unsigned long mfn); static inline unsigned long pfn_to_mfn(unsigned long pfn) { if (xen_feature(XENFEAT_auto_translated_physmap)) return pfn; - return phys_to_machine_mapping[(unsigned int)(pfn)] & - ~FOREIGN_FRAME_BIT; + return get_phys_to_machine(pfn) & ~FOREIGN_FRAME_BIT; } static inline int phys_to_machine_mapping_valid(unsigned long pfn) @@ -42,7 +47,7 @@ static inline int phys_to_machine_mapping_valid(unsigned long pfn) if (xen_feature(XENFEAT_auto_translated_physmap)) return 1; - return (phys_to_machine_mapping[pfn] != INVALID_P2M_ENTRY); + return get_phys_to_machine(pfn) != INVALID_P2M_ENTRY; } static inline unsigned long mfn_to_pfn(unsigned long mfn) @@ -106,20 +111,12 @@ static inline unsigned long mfn_to_local_pfn(unsigned long mfn) unsigned long pfn = mfn_to_pfn(mfn); if ((pfn < max_mapnr) && !xen_feature(XENFEAT_auto_translated_physmap) - && (phys_to_machine_mapping[pfn] != mfn)) + && (get_phys_to_machine(pfn) != mfn)) return max_mapnr; /* force !pfn_valid() */ + /* XXX fixme; not true with sparsemem */ return pfn; } -static inline void set_phys_to_machine(unsigned long pfn, unsigned long mfn) -{ - if (xen_feature(XENFEAT_auto_translated_physmap)) { - BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY); - return; - } - phys_to_machine_mapping[pfn] = mfn; -} - /* VIRT <-> MACHINE conversion */ #define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v)))) #define virt_to_mfn(v) (pfn_to_mfn(PFN_DOWN(__pa(v)))) @@ -150,13 +147,9 @@ static inline pte_t __pte_ma(pteval_t x) return (pte_t) { .pte = x }; } -#ifdef CONFIG_X86_PAE #define pmd_val_ma(v) ((v).pmd) #define pud_val_ma(v) ((v).pgd.pgd) #define __pmd_ma(x) ((pmd_t) { (x) } ) -#else /* !X86_PAE */ -#define pmd_val_ma(v) ((v).pud.pgd.pgd) -#endif /* CONFIG_X86_PAE */ #define pgd_val_ma(x) ((x).pgd) diff --git a/include/crypto/algapi.h b/include/crypto/algapi.h index 60d06e784be3..fef272a8ceeb 100644 --- a/include/crypto/algapi.h +++ b/include/crypto/algapi.h @@ -98,6 +98,7 @@ extern const struct crypto_type crypto_ablkcipher_type; extern const struct crypto_type crypto_aead_type; extern const struct crypto_type crypto_blkcipher_type; extern const struct crypto_type crypto_hash_type; +extern const struct crypto_type crypto_ahash_type; void crypto_mod_put(struct crypto_alg *alg); @@ -314,5 +315,40 @@ static inline int crypto_requires_sync(u32 type, u32 mask) return (type ^ CRYPTO_ALG_ASYNC) & mask & CRYPTO_ALG_ASYNC; } +static inline void *crypto_ahash_ctx(struct crypto_ahash *tfm) +{ + return crypto_tfm_ctx(&tfm->base); +} + +static inline struct ahash_alg *crypto_ahash_alg( + struct crypto_ahash *tfm) +{ + return &crypto_ahash_tfm(tfm)->__crt_alg->cra_ahash; +} + +static inline int ahash_enqueue_request(struct crypto_queue *queue, + struct ahash_request *request) +{ + return crypto_enqueue_request(queue, &request->base); +} + +static inline struct ahash_request *ahash_dequeue_request( + struct crypto_queue *queue) +{ + return ahash_request_cast(crypto_dequeue_request(queue)); +} + +static inline void *ahash_request_ctx(struct ahash_request *req) +{ + return req->__ctx; +} + +static inline int ahash_tfm_in_queue(struct crypto_queue *queue, + struct crypto_ahash *tfm) +{ + return crypto_tfm_in_queue(queue, crypto_ahash_tfm(tfm)); +} + + #endif /* _CRYPTO_ALGAPI_H */ diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 41f7ce7edd7a..33adcf91ef41 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -234,6 +234,9 @@ int acpi_check_region(resource_size_t start, resource_size_t n, int acpi_check_mem_region(resource_size_t start, resource_size_t n, const char *name); +#ifdef CONFIG_PM_SLEEP +void __init acpi_old_suspend_ordering(void); +#endif /* CONFIG_PM_SLEEP */ #else /* CONFIG_ACPI */ static inline int early_acpi_boot_init(void) diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h index 1abfe664c444..a08c33a26ca9 100644 --- a/include/linux/bitmap.h +++ b/include/linux/bitmap.h @@ -129,6 +129,7 @@ extern void bitmap_fold(unsigned long *dst, const unsigned long *orig, extern int bitmap_find_free_region(unsigned long *bitmap, int bits, int order); extern void bitmap_release_region(unsigned long *bitmap, int pos, int order); extern int bitmap_allocate_region(unsigned long *bitmap, int pos, int order); +extern void bitmap_copy_le(void *dst, const unsigned long *src, int nbits); #define BITMAP_LAST_WORD_MASK(nbits) \ ( \ diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 05e540d6963a..7ffe03f4693d 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -10,6 +10,7 @@ static inline u8 bitrev8(u8 byte) return byte_rev_table[byte]; } +extern u16 bitrev16(u16 in); extern u32 bitrev32(u32 in); #endif /* _LINUX_BITREV_H */ diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index d2a1b71e93c3..1171abd7eb17 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -623,7 +623,6 @@ extern void generic_make_request(struct bio *bio); extern void blk_rq_init(struct request_queue *q, struct request *rq); extern void blk_put_request(struct request *); extern void __blk_put_request(struct request_queue *, struct request *); -extern void blk_end_sync_rq(struct request *rq, int error); extern struct request *blk_get_request(struct request_queue *, int, gfp_t); extern void blk_insert_request(struct request_queue *, struct request *, int, void *); extern void blk_requeue_request(struct request_queue *, struct request *); diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h index 6a5dbdc8a7dc..686895bacd9d 100644 --- a/include/linux/bootmem.h +++ b/include/linux/bootmem.h @@ -94,7 +94,7 @@ extern unsigned long init_bootmem_node(pg_data_t *pgdat, unsigned long freepfn, unsigned long startpfn, unsigned long endpfn); -extern void reserve_bootmem_node(pg_data_t *pgdat, +extern int reserve_bootmem_node(pg_data_t *pgdat, unsigned long physaddr, unsigned long size, int flags); diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h new file mode 100644 index 000000000000..9b64b6d67873 --- /dev/null +++ b/include/linux/brcmphy.h @@ -0,0 +1,6 @@ +#define PHY_BRCM_WIRESPEED_ENABLE 0x00000001 +#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000002 +#define PHY_BRCM_APD_CLK125_ENABLE 0x00000004 +#define PHY_BRCM_STD_IBND_DISABLE 0x00000008 +#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00000010 +#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00000020 diff --git a/include/linux/byteorder/bitfields.h b/include/linux/byteorder/bitfields.h new file mode 100644 index 000000000000..5a8c2f8a46b1 --- /dev/null +++ b/include/linux/byteorder/bitfields.h @@ -0,0 +1,114 @@ +/* + * Helpers for defining little-endian bitfields + * + * Copyright (C) 2007 Intel Corporation + * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef __LINUX__BYTEORDER__BITFIELDS_H__ +#define __LINUX__BYTEORDER__BITFIELDS_H__ + +#include <asm/byteorder.h> + +/* + * Declare Little Endian bitfields + * + * These macros are used to switch the order of the bitfields when + * packing with Little Endian in mind (ie: for mapping to a hw type + * that you have to send or read from a device). + * + * NOTE: When using multibyte bitfields, you need to convert the data + * from Little Endian to CPU before you can access the bitfield + * (to make it simpler): + * + * union something { + * le16 value; + * DECL_BF_LE3( + * u16 bf0:3, + * u16 bf1:10, + * u16 bf2:3 + * ) __attribute__((packed)); + * }; + * + * ... + * + * union something s; + * + * s.value = le16_to_cpu(something LE read from hw); + * frame_count = s.bf1; + * + */ +#ifdef __LITTLE_ENDIAN_BITFIELD +#define DECL_BF_LE2(a, b) struct { a; b; } +#define DECL_BF_LE3(a, b, c) struct { a; b; c; } +#define DECL_BF_LE4(a, b, c, d) struct { a; b; c; d ; } +#define DECL_BF_LE5(a, b, c, d, e) struct { a; b; c; d; e; } +#define DECL_BF_LE6(a, b, c, d, e, f) struct { a; b; c; d; e; f; } +#define DECL_BF_LE7(a, b, c, d, e, f, g) struct { a; b; c; d; e; f; g; } +#define DECL_BF_LE8(a, b, c, d, e, f, g, h) struct { a; b; c; d; e; f; g; h; } +#define DECL_BF_LE9(a, b, c, d, e, f, g, h, i) \ + struct { a; b; c; d; e; f; g; h; i; } +#define DECL_BF_LE10(a, b, c, d, e, f, g, h, i, j) \ + struct { a; b; c; d; e; f; g; h; i; j; } +#define DECL_BF_LE11(a, b, c, d, e, f, g, h, i, j, k) \ + struct { a; b; c; d; e; f; g; h; i; j; k; } +#define DECL_BF_LE12(a, b, c, d, e, f, g, h, i, j, k, l) \ + struct { a; b; c; d; e; f; g; h; i; j; k; l; } +#define DECL_BF_LE13(a, b, c, d, e, f, g, h, i, j, k, l, m) \ + struct { a; b; c; d; e; f; g; h; i; j; k; l; m; } +#define DECL_BF_LE14(a, b, c, d, e, f, g, h, i, j, k, l, m, n) \ + struct { a; b; c; d; e; f; g; h; i; j; k; l; m; n; } +#define DECL_BF_LE15(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o) \ + struct { a; b; c; d; e; f; g; h; i; j; k; l; m; n; o; } +#define DECL_BF_LE16(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p) \ + struct { a; b; c; d; e; f; g; h; i; j; k; l; m; n; o; p; } + +#else +#ifdef __BIG_ENDIAN_BITFIELD + +#define DECL_BF_LE2(a, b) struct { b; a; } +#define DECL_BF_LE3(a, b, c) struct { c; b; a; } +#define DECL_BF_LE4(a, b, c, d) struct { d; c; b; a; } +#define DECL_BF_LE5(a, b, c, d, e) struct { e; d; c; b; a; } +#define DECL_BF_LE6(a, b, c, d, e, f) struct { f; e; d; c; b; a; } +#define DECL_BF_LE7(a, b, c, d, e, f, g) struct { g; f; e; d; c; b; a; } +#define DECL_BF_LE8(a, b, c, d, e, f, g, h) struct { h; g; f; e; d; c; b; a; } +#define DECL_BF_LE9(a, b, c, d, e, f, g, h, i) \ + struct { i; h; g; f; e; d; c; b; a; } +#define DECL_BF_LE10(a, b, c, d, e, f, g, h, i, j) \ + struct { j; i; h; g; f; e; d; c; b; a; } +#define DECL_BF_LE11(a, b, c, d, e, f, g, h, i, j, k) \ + struct { k; j; i; h; g; f; e; d; c; b; a; } +#define DECL_BF_LE12(a, b, c, d, e, f, g, h, i, j, k, l) \ + struct { l; k; j; i; h; g; f; e; d; c; b; a; } +#define DECL_BF_LE13(a, b, c, d, e, f, g, h, i, j, k, l, m) \ + struct { m; l; k; j; i; h; g; f; e; d; c; b; a; } +#define DECL_BF_LE14(a, b, c, d, e, f, g, h, i, j, k, l, m, n) \ + struct { n; m; l; k; j; i; h; g; f; e; d; c; b; a; } +#define DECL_BF_LE15(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o) \ + struct { o; n; m; l; k; j; i; h; g; f; e; d; c; b; a; } +#define DECL_BF_LE16(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p) \ + struct { p; o; n; m; l; k; j; i; h; g; f; e; d; c; b; a; } + +#else + +#error Unknown endianess for Little Endian bitfield definition + +#endif +#endif + +#endif /* #ifndef __LINUX__BYTEORDER__BITFIELDS_H__ */ diff --git a/include/linux/capability.h b/include/linux/capability.h index f4ea0dd9a618..fa830f8de032 100644 --- a/include/linux/capability.h +++ b/include/linux/capability.h @@ -31,11 +31,11 @@ struct task_struct; #define _LINUX_CAPABILITY_VERSION_1 0x19980330 #define _LINUX_CAPABILITY_U32S_1 1 -#define _LINUX_CAPABILITY_VERSION_2 0x20071026 +#define _LINUX_CAPABILITY_VERSION_2 0x20071026 /* deprecated - use v3 */ #define _LINUX_CAPABILITY_U32S_2 2 -#define _LINUX_CAPABILITY_VERSION _LINUX_CAPABILITY_VERSION_2 -#define _LINUX_CAPABILITY_U32S _LINUX_CAPABILITY_U32S_2 +#define _LINUX_CAPABILITY_VERSION_3 0x20080522 +#define _LINUX_CAPABILITY_U32S_3 2 typedef struct __user_cap_header_struct { __u32 version; @@ -77,10 +77,23 @@ struct vfs_cap_data { } data[VFS_CAP_U32]; }; -#ifdef __KERNEL__ +#ifndef __KERNEL__ + +/* + * Backwardly compatible definition for source code - trapped in a + * 32-bit world. If you find you need this, please consider using + * libcap to untrap yourself... + */ +#define _LINUX_CAPABILITY_VERSION _LINUX_CAPABILITY_VERSION_1 +#define _LINUX_CAPABILITY_U32S _LINUX_CAPABILITY_U32S_1 + +#else + +#define _KERNEL_CAPABILITY_VERSION _LINUX_CAPABILITY_VERSION_3 +#define _KERNEL_CAPABILITY_U32S _LINUX_CAPABILITY_U32S_3 typedef struct kernel_cap_struct { - __u32 cap[_LINUX_CAPABILITY_U32S]; + __u32 cap[_KERNEL_CAPABILITY_U32S]; } kernel_cap_t; #define _USER_CAP_HEADER_SIZE (sizeof(struct __user_cap_header_struct)) @@ -351,7 +364,7 @@ typedef struct kernel_cap_struct { */ #define CAP_FOR_EACH_U32(__capi) \ - for (__capi = 0; __capi < _LINUX_CAPABILITY_U32S; ++__capi) + for (__capi = 0; __capi < _KERNEL_CAPABILITY_U32S; ++__capi) # define CAP_FS_MASK_B0 (CAP_TO_MASK(CAP_CHOWN) \ | CAP_TO_MASK(CAP_DAC_OVERRIDE) \ @@ -361,7 +374,7 @@ typedef struct kernel_cap_struct { # define CAP_FS_MASK_B1 (CAP_TO_MASK(CAP_MAC_OVERRIDE)) -#if _LINUX_CAPABILITY_U32S != 2 +#if _KERNEL_CAPABILITY_U32S != 2 # error Fix up hand-coded capability macro initializers #else /* HAND-CODED capability initializers */ @@ -372,7 +385,7 @@ typedef struct kernel_cap_struct { # define CAP_NFSD_SET ((kernel_cap_t){{ CAP_FS_MASK_B0|CAP_TO_MASK(CAP_SYS_RESOURCE), \ CAP_FS_MASK_B1 } }) -#endif /* _LINUX_CAPABILITY_U32S != 2 */ +#endif /* _KERNEL_CAPABILITY_U32S != 2 */ #define CAP_INIT_INH_SET CAP_EMPTY_SET diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h index 5c8351b859f0..9bf1cf1563ea 100644 --- a/include/linux/compiler-gcc.h +++ b/include/linux/compiler-gcc.h @@ -61,3 +61,22 @@ #define noinline __attribute__((noinline)) #define __attribute_const__ __attribute__((__const__)) #define __maybe_unused __attribute__((unused)) + +/** + * cast_if_type - allow an alternate type + * @expr: the expression to optionally cast + * @oktype: the type to allow. + * @desttype: the type to cast to. + * + * This is used to accept a particular alternate type for an expression: + * because any other types will not be cast, they will cause a warning as + * normal. + * + * Note that the unnecessary trinary forces functions to devolve into + * function pointers as users expect, but means @expr must be a pointer or + * integer. + */ +#define cast_if_type(expr, oktype, desttype) \ + __builtin_choose_expr(__builtin_types_compatible_p(typeof(1?(expr):0),\ + oktype), \ + (desttype)(expr), (expr)) diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h index d8e636e5607d..7e704e6c8a5d 100644 --- a/include/linux/compiler-intel.h +++ b/include/linux/compiler-intel.h @@ -29,3 +29,5 @@ #endif #define uninitialized_var(x) x + +#define cast_if_type(expr, oktype, desttype) ((desttype)(expr)) diff --git a/include/linux/console.h b/include/linux/console.h index a4f27fbdf549..248e6e3b9b73 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -108,6 +108,8 @@ struct console { struct console *next; }; +extern int console_set_on_cmdline; + extern int add_preferred_console(char *name, int idx, char *options); extern int update_console_cmdline(char *name, int idx, char *name_new, int idx_new, char *options); extern void register_console(struct console *); diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index e7e91dbfde0f..2270ca5ec631 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -4,9 +4,6 @@ * Copyright (C) 2001 Russell King * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> * - * - * $Id: cpufreq.h,v 1.36 2003/01/20 17:31:48 db Exp $ - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h index 51e6b1e520e6..dcf77fa826b5 100644 --- a/include/linux/cpuidle.h +++ b/include/linux/cpuidle.h @@ -82,6 +82,7 @@ struct cpuidle_state_kobj { }; struct cpuidle_device { + unsigned int registered:1; unsigned int enabled:1; unsigned int cpu; diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h index 5df3db58fcc6..80226e776143 100644 --- a/include/linux/cpumask.h +++ b/include/linux/cpumask.h @@ -17,6 +17,20 @@ * For details of cpus_onto(), see bitmap_onto in lib/bitmap.c. * For details of cpus_fold(), see bitmap_fold in lib/bitmap.c. * + * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + * Note: The alternate operations with the suffix "_nr" are used + * to limit the range of the loop to nr_cpu_ids instead of + * NR_CPUS when NR_CPUS > 64 for performance reasons. + * If NR_CPUS is <= 64 then most assembler bitmask + * operators execute faster with a constant range, so + * the operator will continue to use NR_CPUS. + * + * Another consideration is that nr_cpu_ids is initialized + * to NR_CPUS and isn't lowered until the possible cpus are + * discovered (including any disabled cpus). So early uses + * will span the entire range of NR_CPUS. + * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + * * The available cpumask operations are: * * void cpu_set(cpu, mask) turn on bit 'cpu' in mask @@ -38,12 +52,14 @@ * int cpus_empty(mask) Is mask empty (no bits sets)? * int cpus_full(mask) Is mask full (all bits sets)? * int cpus_weight(mask) Hamming weigh - number of set bits + * int cpus_weight_nr(mask) Same using nr_cpu_ids instead of NR_CPUS * * void cpus_shift_right(dst, src, n) Shift right * void cpus_shift_left(dst, src, n) Shift left * * int first_cpu(mask) Number lowest set bit, or NR_CPUS * int next_cpu(cpu, mask) Next cpu past 'cpu', or NR_CPUS + * int next_cpu_nr(cpu, mask) Next cpu past 'cpu', or nr_cpu_ids * * cpumask_t cpumask_of_cpu(cpu) Return cpumask with bit 'cpu' set * CPU_MASK_ALL Initializer - all bits set @@ -59,7 +75,8 @@ * void cpus_onto(dst, orig, relmap) *dst = orig relative to relmap * void cpus_fold(dst, orig, sz) dst bits = orig bits mod sz * - * for_each_cpu_mask(cpu, mask) for-loop cpu over mask + * for_each_cpu_mask(cpu, mask) for-loop cpu over mask using NR_CPUS + * for_each_cpu_mask_nr(cpu, mask) for-loop cpu over mask using nr_cpu_ids * * int num_online_cpus() Number of online CPUs * int num_possible_cpus() Number of all possible CPUs @@ -216,15 +233,6 @@ static inline void __cpus_shift_left(cpumask_t *dstp, bitmap_shift_left(dstp->bits, srcp->bits, n, nbits); } -#ifdef CONFIG_SMP -int __first_cpu(const cpumask_t *srcp); -#define first_cpu(src) __first_cpu(&(src)) -int __next_cpu(int n, const cpumask_t *srcp); -#define next_cpu(n, src) __next_cpu((n), &(src)) -#else -#define first_cpu(src) ({ (void)(src); 0; }) -#define next_cpu(n, src) ({ (void)(src); 1; }) -#endif #ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP extern cpumask_t *cpumask_of_cpu_map; @@ -343,15 +351,48 @@ static inline void __cpus_fold(cpumask_t *dstp, const cpumask_t *origp, bitmap_fold(dstp->bits, origp->bits, sz, nbits); } -#if NR_CPUS > 1 -#define for_each_cpu_mask(cpu, mask) \ - for ((cpu) = first_cpu(mask); \ - (cpu) < NR_CPUS; \ - (cpu) = next_cpu((cpu), (mask))) -#else /* NR_CPUS == 1 */ -#define for_each_cpu_mask(cpu, mask) \ +#if NR_CPUS == 1 + +#define nr_cpu_ids 1 +#define first_cpu(src) ({ (void)(src); 0; }) +#define next_cpu(n, src) ({ (void)(src); 1; }) +#define any_online_cpu(mask) 0 +#define for_each_cpu_mask(cpu, mask) \ for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask) -#endif /* NR_CPUS */ + +#else /* NR_CPUS > 1 */ + +extern int nr_cpu_ids; +int __first_cpu(const cpumask_t *srcp); +int __next_cpu(int n, const cpumask_t *srcp); +int __any_online_cpu(const cpumask_t *mask); + +#define first_cpu(src) __first_cpu(&(src)) +#define next_cpu(n, src) __next_cpu((n), &(src)) +#define any_online_cpu(mask) __any_online_cpu(&(mask)) +#define for_each_cpu_mask(cpu, mask) \ + for ((cpu) = -1; \ + (cpu) = next_cpu((cpu), (mask)), \ + (cpu) < NR_CPUS; ) +#endif + +#if NR_CPUS <= 64 + +#define next_cpu_nr(n, src) next_cpu(n, src) +#define cpus_weight_nr(cpumask) cpus_weight(cpumask) +#define for_each_cpu_mask_nr(cpu, mask) for_each_cpu_mask(cpu, mask) + +#else /* NR_CPUS > 64 */ + +int __next_cpu_nr(int n, const cpumask_t *srcp); +#define next_cpu_nr(n, src) __next_cpu_nr((n), &(src)) +#define cpus_weight_nr(cpumask) __cpus_weight(&(cpumask), nr_cpu_ids) +#define for_each_cpu_mask_nr(cpu, mask) \ + for ((cpu) = -1; \ + (cpu) = next_cpu_nr((cpu), (mask)), \ + (cpu) < nr_cpu_ids; ) + +#endif /* NR_CPUS > 64 */ /* * The following particular system cpumasks and operations manage @@ -414,9 +455,9 @@ extern cpumask_t cpu_online_map; extern cpumask_t cpu_present_map; #if NR_CPUS > 1 -#define num_online_cpus() cpus_weight(cpu_online_map) -#define num_possible_cpus() cpus_weight(cpu_possible_map) -#define num_present_cpus() cpus_weight(cpu_present_map) +#define num_online_cpus() cpus_weight_nr(cpu_online_map) +#define num_possible_cpus() cpus_weight_nr(cpu_possible_map) +#define num_present_cpus() cpus_weight_nr(cpu_present_map) #define cpu_online(cpu) cpu_isset((cpu), cpu_online_map) #define cpu_possible(cpu) cpu_isset((cpu), cpu_possible_map) #define cpu_present(cpu) cpu_isset((cpu), cpu_present_map) @@ -431,17 +472,8 @@ extern cpumask_t cpu_present_map; #define cpu_is_offline(cpu) unlikely(!cpu_online(cpu)) -#ifdef CONFIG_SMP -extern int nr_cpu_ids; -#define any_online_cpu(mask) __any_online_cpu(&(mask)) -int __any_online_cpu(const cpumask_t *mask); -#else -#define nr_cpu_ids 1 -#define any_online_cpu(mask) 0 -#endif - -#define for_each_possible_cpu(cpu) for_each_cpu_mask((cpu), cpu_possible_map) -#define for_each_online_cpu(cpu) for_each_cpu_mask((cpu), cpu_online_map) -#define for_each_present_cpu(cpu) for_each_cpu_mask((cpu), cpu_present_map) +#define for_each_possible_cpu(cpu) for_each_cpu_mask_nr((cpu), cpu_possible_map) +#define for_each_online_cpu(cpu) for_each_cpu_mask_nr((cpu), cpu_online_map) +#define for_each_present_cpu(cpu) for_each_cpu_mask_nr((cpu), cpu_present_map) #endif /* __LINUX_CPUMASK_H */ diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 425824bd49f3..b6efe569128d 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -30,15 +30,17 @@ */ #define CRYPTO_ALG_TYPE_MASK 0x0000000f #define CRYPTO_ALG_TYPE_CIPHER 0x00000001 -#define CRYPTO_ALG_TYPE_DIGEST 0x00000002 -#define CRYPTO_ALG_TYPE_HASH 0x00000003 +#define CRYPTO_ALG_TYPE_COMPRESS 0x00000002 +#define CRYPTO_ALG_TYPE_AEAD 0x00000003 #define CRYPTO_ALG_TYPE_BLKCIPHER 0x00000004 #define CRYPTO_ALG_TYPE_ABLKCIPHER 0x00000005 #define CRYPTO_ALG_TYPE_GIVCIPHER 0x00000006 -#define CRYPTO_ALG_TYPE_COMPRESS 0x00000008 -#define CRYPTO_ALG_TYPE_AEAD 0x00000009 +#define CRYPTO_ALG_TYPE_DIGEST 0x00000008 +#define CRYPTO_ALG_TYPE_HASH 0x00000009 +#define CRYPTO_ALG_TYPE_AHASH 0x0000000a #define CRYPTO_ALG_TYPE_HASH_MASK 0x0000000e +#define CRYPTO_ALG_TYPE_AHASH_MASK 0x0000000c #define CRYPTO_ALG_TYPE_BLKCIPHER_MASK 0x0000000c #define CRYPTO_ALG_LARVAL 0x00000010 @@ -102,6 +104,7 @@ struct crypto_async_request; struct crypto_aead; struct crypto_blkcipher; struct crypto_hash; +struct crypto_ahash; struct crypto_tfm; struct crypto_type; struct aead_givcrypt_request; @@ -131,6 +134,18 @@ struct ablkcipher_request { void *__ctx[] CRYPTO_MINALIGN_ATTR; }; +struct ahash_request { + struct crypto_async_request base; + + void *info; + + unsigned int nbytes; + struct scatterlist *src; + u8 *result; + + void *__ctx[] CRYPTO_MINALIGN_ATTR; +}; + /** * struct aead_request - AEAD request * @base: Common attributes for async crypto requests @@ -195,6 +210,17 @@ struct ablkcipher_alg { unsigned int ivsize; }; +struct ahash_alg { + int (*init)(struct ahash_request *req); + int (*update)(struct ahash_request *req); + int (*final)(struct ahash_request *req); + int (*digest)(struct ahash_request *req); + int (*setkey)(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen); + + unsigned int digestsize; +}; + struct aead_alg { int (*setkey)(struct crypto_aead *tfm, const u8 *key, unsigned int keylen); @@ -272,6 +298,7 @@ struct compress_alg { #define cra_cipher cra_u.cipher #define cra_digest cra_u.digest #define cra_hash cra_u.hash +#define cra_ahash cra_u.ahash #define cra_compress cra_u.compress struct crypto_alg { @@ -298,6 +325,7 @@ struct crypto_alg { struct cipher_alg cipher; struct digest_alg digest; struct hash_alg hash; + struct ahash_alg ahash; struct compress_alg compress; } cra_u; @@ -383,6 +411,19 @@ struct hash_tfm { unsigned int digestsize; }; +struct ahash_tfm { + int (*init)(struct ahash_request *req); + int (*update)(struct ahash_request *req); + int (*final)(struct ahash_request *req); + int (*digest)(struct ahash_request *req); + int (*setkey)(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen); + + unsigned int digestsize; + struct crypto_ahash *base; + unsigned int reqsize; +}; + struct compress_tfm { int (*cot_compress)(struct crypto_tfm *tfm, const u8 *src, unsigned int slen, @@ -397,6 +438,7 @@ struct compress_tfm { #define crt_blkcipher crt_u.blkcipher #define crt_cipher crt_u.cipher #define crt_hash crt_u.hash +#define crt_ahash crt_u.ahash #define crt_compress crt_u.compress struct crypto_tfm { @@ -409,6 +451,7 @@ struct crypto_tfm { struct blkcipher_tfm blkcipher; struct cipher_tfm cipher; struct hash_tfm hash; + struct ahash_tfm ahash; struct compress_tfm compress; } crt_u; @@ -441,6 +484,10 @@ struct crypto_hash { struct crypto_tfm base; }; +struct crypto_ahash { + struct crypto_tfm base; +}; + enum { CRYPTOA_UNSPEC, CRYPTOA_ALG, @@ -1264,5 +1311,137 @@ static inline int crypto_comp_decompress(struct crypto_comp *tfm, src, slen, dst, dlen); } +static inline struct crypto_ahash *__crypto_ahash_cast(struct crypto_tfm *tfm) +{ + return (struct crypto_ahash *)tfm; +} + +static inline struct crypto_ahash *crypto_alloc_ahash(const char *alg_name, + u32 type, u32 mask) +{ + type &= ~CRYPTO_ALG_TYPE_MASK; + mask &= ~CRYPTO_ALG_TYPE_MASK; + type |= CRYPTO_ALG_TYPE_AHASH; + mask |= CRYPTO_ALG_TYPE_AHASH_MASK; + + return __crypto_ahash_cast(crypto_alloc_base(alg_name, type, mask)); +} + +static inline struct crypto_tfm *crypto_ahash_tfm(struct crypto_ahash *tfm) +{ + return &tfm->base; +} + +static inline void crypto_free_ahash(struct crypto_ahash *tfm) +{ + crypto_free_tfm(crypto_ahash_tfm(tfm)); +} + +static inline unsigned int crypto_ahash_alignmask( + struct crypto_ahash *tfm) +{ + return crypto_tfm_alg_alignmask(crypto_ahash_tfm(tfm)); +} + +static inline struct ahash_tfm *crypto_ahash_crt(struct crypto_ahash *tfm) +{ + return &crypto_ahash_tfm(tfm)->crt_ahash; +} + +static inline unsigned int crypto_ahash_digestsize(struct crypto_ahash *tfm) +{ + return crypto_ahash_crt(tfm)->digestsize; +} + +static inline u32 crypto_ahash_get_flags(struct crypto_ahash *tfm) +{ + return crypto_tfm_get_flags(crypto_ahash_tfm(tfm)); +} + +static inline void crypto_ahash_set_flags(struct crypto_ahash *tfm, u32 flags) +{ + crypto_tfm_set_flags(crypto_ahash_tfm(tfm), flags); +} + +static inline void crypto_ahash_clear_flags(struct crypto_ahash *tfm, u32 flags) +{ + crypto_tfm_clear_flags(crypto_ahash_tfm(tfm), flags); +} + +static inline struct crypto_ahash *crypto_ahash_reqtfm( + struct ahash_request *req) +{ + return __crypto_ahash_cast(req->base.tfm); +} + +static inline unsigned int crypto_ahash_reqsize(struct crypto_ahash *tfm) +{ + return crypto_ahash_crt(tfm)->reqsize; +} + +static inline int crypto_ahash_setkey(struct crypto_ahash *tfm, + const u8 *key, unsigned int keylen) +{ + struct ahash_tfm *crt = crypto_ahash_crt(tfm); + + return crt->setkey(crt->base, key, keylen); +} + +static inline int crypto_ahash_digest(struct ahash_request *req) +{ + struct ahash_tfm *crt = crypto_ahash_crt(crypto_ahash_reqtfm(req)); + return crt->digest(req); +} + +static inline void ahash_request_set_tfm(struct ahash_request *req, + struct crypto_ahash *tfm) +{ + req->base.tfm = crypto_ahash_tfm(crypto_ahash_crt(tfm)->base); +} + +static inline struct ahash_request *ahash_request_alloc( + struct crypto_ahash *tfm, gfp_t gfp) +{ + struct ahash_request *req; + + req = kmalloc(sizeof(struct ahash_request) + + crypto_ahash_reqsize(tfm), gfp); + + if (likely(req)) + ahash_request_set_tfm(req, tfm); + + return req; +} + +static inline void ahash_request_free(struct ahash_request *req) +{ + kfree(req); +} + +static inline struct ahash_request *ahash_request_cast( + struct crypto_async_request *req) +{ + return container_of(req, struct ahash_request, base); +} + +static inline void ahash_request_set_callback(struct ahash_request *req, + u32 flags, + crypto_completion_t complete, + void *data) +{ + req->base.complete = complete; + req->base.data = data; + req->base.flags = flags; +} + +static inline void ahash_request_set_crypt(struct ahash_request *req, + struct scatterlist *src, u8 *result, + unsigned int nbytes) +{ + req->src = src; + req->nbytes = nbytes; + req->result = result; +} + #endif /* _LINUX_CRYPTO_H */ diff --git a/include/linux/dcache.h b/include/linux/dcache.h index 2a6639407c80..7f16b96e7660 100644 --- a/include/linux/dcache.h +++ b/include/linux/dcache.h @@ -3,6 +3,7 @@ #include <asm/atomic.h> #include <linux/list.h> +#include <linux/rculist.h> #include <linux/spinlock.h> #include <linux/cache.h> #include <linux/rcupdate.h> @@ -229,6 +230,7 @@ extern void d_delete(struct dentry *); extern struct dentry * d_alloc(struct dentry *, const struct qstr *); extern struct dentry * d_alloc_anon(struct inode *); extern struct dentry * d_splice_alias(struct inode *, struct dentry *); +extern struct dentry * d_add_ci(struct inode *, struct dentry *, struct qstr *); extern void shrink_dcache_sb(struct super_block *); extern void shrink_dcache_parent(struct dentry *); extern void shrink_dcache_for_umount(struct super_block *); diff --git a/include/linux/device.h b/include/linux/device.h index 6a2d04c011bc..ab755debf683 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -16,6 +16,7 @@ #include <linux/kobject.h> #include <linux/klist.h> #include <linux/list.h> +#include <linux/lockdep.h> #include <linux/compiler.h> #include <linux/types.h> #include <linux/module.h> @@ -24,17 +25,13 @@ #include <asm/atomic.h> #include <asm/device.h> -#define DEVICE_NAME_SIZE 50 -/* DEVICE_NAME_HALF is really less than half to accommodate slop */ -#define DEVICE_NAME_HALF __stringify(20) -#define DEVICE_ID_SIZE 32 -#define BUS_ID_SIZE KOBJ_NAME_LEN - +#define BUS_ID_SIZE 20 struct device; struct device_driver; struct driver_private; struct class; +struct class_private; struct bus_type; struct bus_type_private; @@ -68,6 +65,8 @@ struct bus_type { int (*resume_early)(struct device *dev); int (*resume)(struct device *dev); + struct pm_ext_ops *pm; + struct bus_type_private *p; }; @@ -131,6 +130,8 @@ struct device_driver { int (*resume) (struct device *dev); struct attribute_group **groups; + struct pm_ops *pm; + struct driver_private *p; }; @@ -182,13 +183,9 @@ struct class { const char *name; struct module *owner; - struct kset subsys; - struct list_head devices; - struct list_head interfaces; - struct kset class_dirs; - struct semaphore sem; /* locks children, devices, interfaces */ struct class_attribute *class_attrs; struct device_attribute *dev_attrs; + struct kobject *dev_kobj; int (*dev_uevent)(struct device *dev, struct kobj_uevent_env *env); @@ -197,13 +194,30 @@ struct class { int (*suspend)(struct device *dev, pm_message_t state); int (*resume)(struct device *dev); + + struct pm_ops *pm; + struct class_private *p; }; -extern int __must_check class_register(struct class *class); +extern struct kobject *sysfs_dev_block_kobj; +extern struct kobject *sysfs_dev_char_kobj; +extern int __must_check __class_register(struct class *class, + struct lock_class_key *key); extern void class_unregister(struct class *class); -extern int class_for_each_device(struct class *class, void *data, + +/* This is a #define to keep the compiler from merging different + * instances of the __key variable */ +#define class_register(class) \ +({ \ + static struct lock_class_key __key; \ + __class_register(class, &__key); \ +}) + +extern int class_for_each_device(struct class *class, struct device *start, + void *data, int (*fn)(struct device *dev, void *data)); -extern struct device *class_find_device(struct class *class, void *data, +extern struct device *class_find_device(struct class *class, + struct device *start, void *data, int (*match)(struct device *, void *)); struct class_attribute { @@ -231,9 +245,19 @@ struct class_interface { extern int __must_check class_interface_register(struct class_interface *); extern void class_interface_unregister(struct class_interface *); -extern struct class *class_create(struct module *owner, const char *name); +extern struct class * __must_check __class_create(struct module *owner, + const char *name, + struct lock_class_key *key); extern void class_destroy(struct class *cls); +/* This is a #define to keep the compiler from merging different + * instances of the __key variable */ +#define class_create(owner, name) \ +({ \ + static struct lock_class_key __key; \ + __class_create(owner, name, &__key); \ +}) + /* * The type of device, "struct device" is embedded in. A class * or bus can contain devices of different types @@ -248,8 +272,11 @@ struct device_type { struct attribute_group **groups; int (*uevent)(struct device *dev, struct kobj_uevent_env *env); void (*release)(struct device *dev); + int (*suspend)(struct device *dev, pm_message_t state); int (*resume)(struct device *dev); + + struct pm_ops *pm; }; /* interface for exporting device attributes */ @@ -458,9 +485,6 @@ extern struct device *device_create_vargs(struct class *cls, void *drvdata, const char *fmt, va_list vargs); -extern struct device *device_create(struct class *cls, struct device *parent, - dev_t devt, const char *fmt, ...) - __attribute__((format(printf, 4, 5))); extern struct device *device_create_drvdata(struct class *cls, struct device *parent, dev_t devt, diff --git a/include/linux/efi.h b/include/linux/efi.h index a5f359a7ad0e..807373d467f7 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -287,7 +287,6 @@ efi_guid_unparse(efi_guid_t *guid, char *out) extern void efi_init (void); extern void *efi_get_pal_addr (void); extern void efi_map_pal_code (void); -extern void efi_map_memmap(void); extern void efi_memmap_walk (efi_freemem_callback_t callback, void *arg); extern void efi_gettimeofday (struct timespec *ts); extern void efi_enter_virtual_mode (void); /* switch EFI to virtual mode, if possible */ @@ -295,14 +294,11 @@ extern u64 efi_get_iobase (void); extern u32 efi_mem_type (unsigned long phys_addr); extern u64 efi_mem_attributes (unsigned long phys_addr); extern u64 efi_mem_attribute (unsigned long phys_addr, unsigned long size); -extern int efi_mem_attribute_range (unsigned long phys_addr, unsigned long size, - u64 attr); extern int __init efi_uart_console_only (void); extern void efi_initialize_iomem_resources(struct resource *code_resource, struct resource *data_resource, struct resource *bss_resource); extern unsigned long efi_get_time(void); extern int efi_set_rtc_mmss(unsigned long nowtime); -extern int is_available_memory(efi_memory_desc_t * md); extern struct efi_memory_map memmap; /** diff --git a/include/linux/eisa.h b/include/linux/eisa.h index fe806b6f030d..e61c0be2a459 100644 --- a/include/linux/eisa.h +++ b/include/linux/eisa.h @@ -40,7 +40,7 @@ struct eisa_device { u64 dma_mask; struct device dev; /* generic device */ #ifdef CONFIG_EISA_NAMES - char pretty_name[DEVICE_NAME_SIZE]; + char pretty_name[50]; #endif }; diff --git a/include/linux/firmware.h b/include/linux/firmware.h index 4d10c7328d2d..5e73f3f896e8 100644 --- a/include/linux/firmware.h +++ b/include/linux/firmware.h @@ -8,7 +8,7 @@ struct firmware { size_t size; - u8 *data; + const u8 *data; }; struct device; diff --git a/include/linux/freezer.h b/include/linux/freezer.h index 08934995c7ab..deddeedf3257 100644 --- a/include/linux/freezer.h +++ b/include/linux/freezer.h @@ -128,6 +128,15 @@ static inline void set_freezable(void) } /* + * Tell the freezer that the current task should be frozen by it and that it + * should send a fake signal to the task to freeze it. + */ +static inline void set_freezable_with_signal(void) +{ + current->flags &= ~(PF_NOFREEZE | PF_FREEZER_NOSIG); +} + +/* * Freezer-friendly wrappers around wait_event_interruptible() and * wait_event_interruptible_timeout(), originally defined in <linux/wait.h> */ @@ -174,6 +183,7 @@ static inline void freezer_do_not_count(void) {} static inline void freezer_count(void) {} static inline int freezer_should_skip(struct task_struct *p) { return 0; } static inline void set_freezable(void) {} +static inline void set_freezable_with_signal(void) {} #define wait_event_freezable(wq, condition) \ wait_event_interruptible(wq, condition) diff --git a/include/linux/fs.h b/include/linux/fs.h index f413085f748e..d490779f18d9 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2000,7 +2000,10 @@ extern int simple_fill_super(struct super_block *, int, struct tree_descr *); extern int simple_pin_fs(struct file_system_type *, struct vfsmount **mount, int *count); extern void simple_release_fs(struct vfsmount **mount, int *count); -extern ssize_t simple_read_from_buffer(void __user *, size_t, loff_t *, const void *, size_t); +extern ssize_t simple_read_from_buffer(void __user *to, size_t count, + loff_t *ppos, const void *from, size_t available); +extern ssize_t memory_read_from_buffer(void *to, size_t count, loff_t *ppos, + const void *from, size_t available); #ifdef CONFIG_MIGRATION extern int buffer_migrate_page(struct address_space *, diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h new file mode 100644 index 000000000000..20e14d0093c7 --- /dev/null +++ b/include/linux/ftrace.h @@ -0,0 +1,140 @@ +#ifndef _LINUX_FTRACE_H +#define _LINUX_FTRACE_H + +#ifdef CONFIG_FTRACE + +#include <linux/linkage.h> +#include <linux/fs.h> + +extern int ftrace_enabled; +extern int +ftrace_enable_sysctl(struct ctl_table *table, int write, + struct file *filp, void __user *buffer, size_t *lenp, + loff_t *ppos); + +typedef void (*ftrace_func_t)(unsigned long ip, unsigned long parent_ip); + +struct ftrace_ops { + ftrace_func_t func; + struct ftrace_ops *next; +}; + +/* + * The ftrace_ops must be a static and should also + * be read_mostly. These functions do modify read_mostly variables + * so use them sparely. Never free an ftrace_op or modify the + * next pointer after it has been registered. Even after unregistering + * it, the next pointer may still be used internally. + */ +int register_ftrace_function(struct ftrace_ops *ops); +int unregister_ftrace_function(struct ftrace_ops *ops); +void clear_ftrace_function(void); + +extern void ftrace_stub(unsigned long a0, unsigned long a1); +extern void mcount(void); + +#else /* !CONFIG_FTRACE */ +# define register_ftrace_function(ops) do { } while (0) +# define unregister_ftrace_function(ops) do { } while (0) +# define clear_ftrace_function(ops) do { } while (0) +#endif /* CONFIG_FTRACE */ + +#ifdef CONFIG_DYNAMIC_FTRACE +# define FTRACE_HASHBITS 10 +# define FTRACE_HASHSIZE (1<<FTRACE_HASHBITS) + +enum { + FTRACE_FL_FREE = (1 << 0), + FTRACE_FL_FAILED = (1 << 1), + FTRACE_FL_FILTER = (1 << 2), + FTRACE_FL_ENABLED = (1 << 3), + FTRACE_FL_NOTRACE = (1 << 4), + FTRACE_FL_CONVERTED = (1 << 5), +}; + +struct dyn_ftrace { + struct hlist_node node; + unsigned long ip; + unsigned long flags; +}; + +int ftrace_force_update(void); +void ftrace_set_filter(unsigned char *buf, int len, int reset); + +/* defined in arch */ +extern int ftrace_ip_converted(unsigned long ip); +extern unsigned char *ftrace_nop_replace(void); +extern unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr); +extern int ftrace_dyn_arch_init(void *data); +extern int ftrace_mcount_set(unsigned long *data); +extern int ftrace_modify_code(unsigned long ip, unsigned char *old_code, + unsigned char *new_code); +extern int ftrace_update_ftrace_func(ftrace_func_t func); +extern void ftrace_caller(void); +extern void ftrace_call(void); +extern void mcount_call(void); + +void ftrace_disable_daemon(void); +void ftrace_enable_daemon(void); + +#else +# define ftrace_force_update() ({ 0; }) +# define ftrace_set_filter(buf, len, reset) do { } while (0) +# define ftrace_disable_daemon() do { } while (0) +# define ftrace_enable_daemon() do { } while (0) +#endif + +/* totally disable ftrace - can not re-enable after this */ +void ftrace_kill(void); + +static inline void tracer_disable(void) +{ +#ifdef CONFIG_FTRACE + ftrace_enabled = 0; +#endif +} + +#ifdef CONFIG_FRAME_POINTER +/* TODO: need to fix this for ARM */ +# define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0)) +# define CALLER_ADDR1 ((unsigned long)__builtin_return_address(1)) +# define CALLER_ADDR2 ((unsigned long)__builtin_return_address(2)) +# define CALLER_ADDR3 ((unsigned long)__builtin_return_address(3)) +# define CALLER_ADDR4 ((unsigned long)__builtin_return_address(4)) +# define CALLER_ADDR5 ((unsigned long)__builtin_return_address(5)) +# define CALLER_ADDR6 ((unsigned long)__builtin_return_address(6)) +#else +# define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0)) +# define CALLER_ADDR1 0UL +# define CALLER_ADDR2 0UL +# define CALLER_ADDR3 0UL +# define CALLER_ADDR4 0UL +# define CALLER_ADDR5 0UL +# define CALLER_ADDR6 0UL +#endif + +#ifdef CONFIG_IRQSOFF_TRACER + extern void time_hardirqs_on(unsigned long a0, unsigned long a1); + extern void time_hardirqs_off(unsigned long a0, unsigned long a1); +#else +# define time_hardirqs_on(a0, a1) do { } while (0) +# define time_hardirqs_off(a0, a1) do { } while (0) +#endif + +#ifdef CONFIG_PREEMPT_TRACER + extern void trace_preempt_on(unsigned long a0, unsigned long a1); + extern void trace_preempt_off(unsigned long a0, unsigned long a1); +#else +# define trace_preempt_on(a0, a1) do { } while (0) +# define trace_preempt_off(a0, a1) do { } while (0) +#endif + +#ifdef CONFIG_TRACING +extern void +ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3); +#else +static inline void +ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3) { } +#endif + +#endif /* _LINUX_FTRACE_H */ diff --git a/include/linux/gameport.h b/include/linux/gameport.h index afad95272841..f64e29c0ef3f 100644 --- a/include/linux/gameport.h +++ b/include/linux/gameport.h @@ -68,7 +68,6 @@ struct gameport_driver { int gameport_open(struct gameport *gameport, struct gameport_driver *drv, int mode); void gameport_close(struct gameport *gameport); -void gameport_rescan(struct gameport *gameport); #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h index c6d3a9de5634..ec6ecd74781d 100644 --- a/include/linux/gpio_keys.h +++ b/include/linux/gpio_keys.h @@ -9,6 +9,7 @@ struct gpio_keys_button { char *desc; int type; /* input event type (EV_KEY, EV_SW) */ int wakeup; /* configure the button as a wake-up source */ + int debounce_interval; /* debounce ticks interval in msecs */ }; struct gpio_keys_platform_data { diff --git a/include/linux/hpet.h b/include/linux/hpet.h index 2dc29ce6c8e4..6d2626b63a9a 100644 --- a/include/linux/hpet.h +++ b/include/linux/hpet.h @@ -37,6 +37,7 @@ struct hpet { #define hpet_compare _u1._hpet_compare #define HPET_MAX_TIMERS (32) +#define HPET_MAX_IRQ (32) /* * HPET general capabilities register @@ -64,7 +65,7 @@ struct hpet { */ #define Tn_INT_ROUTE_CAP_MASK (0xffffffff00000000ULL) -#define Tn_INI_ROUTE_CAP_SHIFT (32UL) +#define Tn_INT_ROUTE_CAP_SHIFT (32UL) #define Tn_FSB_INT_DELCAP_MASK (0x8000UL) #define Tn_FSB_INT_DELCAP_SHIFT (15) #define Tn_FSB_EN_CNF_MASK (0x4000UL) diff --git a/include/linux/i2c-algo-pcf.h b/include/linux/i2c-algo-pcf.h index 77afbb60fd11..0177d280f733 100644 --- a/include/linux/i2c-algo-pcf.h +++ b/include/linux/i2c-algo-pcf.h @@ -33,9 +33,11 @@ struct i2c_algo_pcf_data { int (*getclock) (void *data); void (*waitforpin) (void); - /* local settings */ - int udelay; - int timeout; + /* Multi-master lost arbitration back-off delay (msecs) + * This should be set by the bus adapter or knowledgable client + * if bus is multi-mastered, else zero + */ + unsigned long lab_mdelay; }; int i2c_pcf_add_bus(struct i2c_adapter *); diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h index 580acc93903e..988e566d3ed5 100644 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h @@ -111,7 +111,6 @@ #define I2C_HW_B_RIVA 0x010010 /* Riva based graphics cards */ #define I2C_HW_B_IOC 0x010011 /* IOC bit-wiggling */ #define I2C_HW_B_IXP2000 0x010016 /* GPIO on IXP2000 systems */ -#define I2C_HW_B_S3VIA 0x010018 /* S3Via ProSavage adapter */ #define I2C_HW_B_ZR36067 0x010019 /* Zoran-36057/36067 based boards */ #define I2C_HW_B_PCILYNX 0x01001a /* TI PCILynx I2C adapter */ #define I2C_HW_B_CX2388x 0x01001b /* connexant 2388x based tv cards */ diff --git a/include/linux/i2c.h b/include/linux/i2c.h index fb9af6a0fe9c..0e332ed991e8 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -69,9 +69,8 @@ extern s32 i2c_smbus_xfer (struct i2c_adapter * adapter, u16 addr, union i2c_smbus_data * data); /* Now follow the 'nice' access routines. These also document the calling - conventions of smbus_access. */ + conventions of i2c_smbus_xfer. */ -extern s32 i2c_smbus_write_quick(struct i2c_client * client, u8 value); extern s32 i2c_smbus_read_byte(struct i2c_client * client); extern s32 i2c_smbus_write_byte(struct i2c_client * client, u8 value); extern s32 i2c_smbus_read_byte_data(struct i2c_client * client, u8 command); @@ -350,10 +349,11 @@ static inline void i2c_set_adapdata (struct i2c_adapter *dev, void *data) #define I2C_CLASS_HWMON (1<<0) /* lm_sensors, ... */ #define I2C_CLASS_TV_ANALOG (1<<1) /* bttv + friends */ #define I2C_CLASS_TV_DIGITAL (1<<2) /* dvb cards */ -#define I2C_CLASS_DDC (1<<3) /* i2c-matroxfb ? */ +#define I2C_CLASS_DDC (1<<3) /* DDC bus on graphics adapters */ #define I2C_CLASS_CAM_ANALOG (1<<4) /* camera with analog CCD */ #define I2C_CLASS_CAM_DIGITAL (1<<5) /* most webcams */ #define I2C_CLASS_SOUND (1<<6) /* sound devices */ +#define I2C_CLASS_SPD (1<<7) /* SPD EEPROMs and similar */ #define I2C_CLASS_ALL (UINT_MAX) /* all of the above */ /* i2c_client_address_data is the struct for holding default client @@ -537,7 +537,7 @@ union i2c_smbus_data { /* and one more for user-space compatibility */ }; -/* smbus_access read or write markers */ +/* i2c_smbus_xfer read or write markers */ #define I2C_SMBUS_READ 1 #define I2C_SMBUS_WRITE 0 diff --git a/include/linux/ide.h b/include/linux/ide.h index f8f195c20da2..5ddae9b55b8d 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -153,7 +153,7 @@ enum { ide_unknown, ide_generic, ide_pci, ide_qd65xx, ide_umc8672, ide_ht6560b, ide_rz1000, ide_trm290, ide_cmd646, ide_cy82c693, ide_4drives, - ide_pmac, ide_etrax100, ide_acorn, + ide_pmac, ide_acorn, ide_au1xxx, ide_palm3710 }; @@ -171,7 +171,7 @@ typedef struct hw_regs_s { int irq; /* our irq number */ ide_ack_intr_t *ack_intr; /* acknowledge interrupt */ hwif_chipset_t chipset; - struct device *dev; + struct device *dev, *parent; } hw_regs_t; void ide_init_port_data(struct hwif_s *, unsigned int); @@ -349,7 +349,6 @@ typedef struct ide_drive_s { u8 wcache; /* status of write cache */ u8 acoustic; /* acoustic management */ u8 media; /* disk, cdrom, tape, floppy, ... */ - u8 ctl; /* "normal" value for Control register */ u8 ready_stat; /* min status value for drive ready */ u8 mult_count; /* current multiple sector setting */ u8 mult_req; /* requested multiple sector setting */ @@ -391,8 +390,8 @@ typedef struct ide_drive_s { struct ide_port_info; struct ide_port_ops { - /* host specific initialization of devices on a port */ - void (*port_init_devs)(struct hwif_s *); + /* host specific initialization of a device */ + void (*init_dev)(ide_drive_t *); /* routine to program host for PIO mode */ void (*set_pio_mode)(ide_drive_t *, const u8); /* routine to program host for DMA mode */ @@ -478,7 +477,7 @@ typedef struct hwif_s { void (*ide_dma_clear_irq)(ide_drive_t *drive); void (*OUTB)(u8 addr, unsigned long port); - void (*OUTBSYNC)(ide_drive_t *drive, u8 addr, unsigned long port); + void (*OUTBSYNC)(struct hwif_s *hwif, u8 addr, unsigned long port); u8 (*INB)(unsigned long port); @@ -517,7 +516,6 @@ typedef struct hwif_s { unsigned serialized : 1; /* serialized all channel operation */ unsigned sharing_irq: 1; /* 1 = sharing irq with another hwif */ unsigned sg_mapped : 1; /* sg_table and sg_nents are ready */ - unsigned mmio : 1; /* host uses MMIO */ struct device gendev; struct device *portdev; @@ -589,12 +587,13 @@ enum { PC_FLAG_SUPPRESS_ERROR = (1 << 1), PC_FLAG_WAIT_FOR_DSC = (1 << 2), PC_FLAG_DMA_OK = (1 << 3), - PC_FLAG_DMA_RECOMMENDED = (1 << 4), - PC_FLAG_DMA_IN_PROGRESS = (1 << 5), - PC_FLAG_DMA_ERROR = (1 << 6), - PC_FLAG_WRITING = (1 << 7), + PC_FLAG_DMA_IN_PROGRESS = (1 << 4), + PC_FLAG_DMA_ERROR = (1 << 5), + PC_FLAG_WRITING = (1 << 6), /* command timed out */ - PC_FLAG_TIMEDOUT = (1 << 8), + PC_FLAG_TIMEDOUT = (1 << 7), + PC_FLAG_ZIP_DRIVE = (1 << 8), + PC_FLAG_DRQ_INTERRUPT = (1 << 9), }; struct ide_atapi_pc { @@ -627,8 +626,8 @@ struct ide_atapi_pc { * to change/removal later. */ u8 pc_buf[256]; - void (*idefloppy_callback) (ide_drive_t *); - ide_startstop_t (*idetape_callback) (ide_drive_t *); + + void (*callback)(ide_drive_t *); /* idetape only */ struct idetape_bh *bh; @@ -787,22 +786,6 @@ struct ide_driver_s { int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *, unsigned, unsigned long); -/* - * ide_hwifs[] is the master data structure used to keep track - * of just about everything in ide.c. Whenever possible, routines - * should be using pointers to a drive (ide_drive_t *) or - * pointers to a hwif (ide_hwif_t *), rather than indexing this - * structure directly (the allocation/layout may change!). - * - */ -#ifndef _IDE_C -extern ide_hwif_t ide_hwifs[]; /* master data repository */ -#endif -extern int ide_noacpi; -extern int ide_acpigtf; -extern int ide_acpionboot; -extern int noautodma; - extern int ide_vlb_clk; extern int ide_pci_clk; @@ -842,25 +825,12 @@ int ide_wait_stat(ide_startstop_t *, ide_drive_t *, u8, u8, unsigned long); extern ide_startstop_t ide_do_reset (ide_drive_t *); -extern void ide_init_drive_cmd (struct request *rq); - -/* - * "action" parameter type for ide_do_drive_cmd() below. - */ -typedef enum { - ide_wait, /* insert rq at end of list, and wait for it */ - ide_preempt, /* insert rq in front of current request */ - ide_head_wait, /* insert rq in front of current request and wait for it */ - ide_end /* insert rq at end of list, but don't wait for it */ -} ide_action_t; - -extern int ide_do_drive_cmd(ide_drive_t *, struct request *, ide_action_t); +extern void ide_do_drive_cmd(ide_drive_t *, struct request *); extern void ide_end_drive_cmd(ide_drive_t *, u8, u8); enum { IDE_TFLAG_LBA48 = (1 << 0), - IDE_TFLAG_NO_SELECT_MASK = (1 << 1), IDE_TFLAG_FLAGGED = (1 << 2), IDE_TFLAG_OUT_DATA = (1 << 3), IDE_TFLAG_OUT_HOB_FEATURE = (1 << 4), @@ -965,11 +935,23 @@ typedef struct ide_task_s { void ide_tf_dump(const char *, struct ide_taskfile *); extern void SELECT_DRIVE(ide_drive_t *); +void SELECT_MASK(ide_drive_t *, int); extern int drive_is_ready(ide_drive_t *); void ide_pktcmd_tf_load(ide_drive_t *, u32, u16, u8); +ide_startstop_t ide_pc_intr(ide_drive_t *drive, struct ide_atapi_pc *pc, + ide_handler_t *handler, unsigned int timeout, ide_expiry_t *expiry, + void (*update_buffers)(ide_drive_t *, struct ide_atapi_pc *), + void (*retry_pc)(ide_drive_t *), void (*dsc_handle)(ide_drive_t *), + void (*io_buffers)(ide_drive_t *, struct ide_atapi_pc *, unsigned int, + int)); +ide_startstop_t ide_transfer_pc(ide_drive_t *, struct ide_atapi_pc *, + ide_handler_t *, unsigned int, ide_expiry_t *); +ide_startstop_t ide_issue_pc(ide_drive_t *, struct ide_atapi_pc *, + ide_handler_t *, unsigned int, ide_expiry_t *); + ide_startstop_t do_rw_taskfile(ide_drive_t *, ide_task_t *); void task_end_request(ide_drive_t *, struct request *, u8); @@ -981,8 +963,6 @@ int ide_taskfile_ioctl(ide_drive_t *, unsigned int, unsigned long); int ide_cmd_ioctl(ide_drive_t *, unsigned int, unsigned long); int ide_task_ioctl(ide_drive_t *, unsigned int, unsigned long); -extern int system_bus_clock(void); - extern int ide_driveid_update(ide_drive_t *); extern int ide_config_drive_speed(ide_drive_t *, u8); extern u8 eighty_ninty_three (ide_drive_t *); @@ -1264,16 +1244,43 @@ static inline int ide_dev_is_sata(struct hd_driveid *id) u64 ide_get_lba_addr(struct ide_taskfile *, int); u8 ide_dump_status(ide_drive_t *, const char *, u8); -typedef struct ide_pio_timings_s { - int setup_time; /* Address setup (ns) minimum */ - int active_time; /* Active pulse (ns) minimum */ - int cycle_time; /* Cycle time (ns) minimum = */ - /* active + recovery (+ setup for some chips) */ -} ide_pio_timings_t; +struct ide_timing { + u8 mode; + u8 setup; /* t1 */ + u16 act8b; /* t2 for 8-bit io */ + u16 rec8b; /* t2i for 8-bit io */ + u16 cyc8b; /* t0 for 8-bit io */ + u16 active; /* t2 or tD */ + u16 recover; /* t2i or tK */ + u16 cycle; /* t0 */ + u16 udma; /* t2CYCTYP/2 */ +}; + +enum { + IDE_TIMING_SETUP = (1 << 0), + IDE_TIMING_ACT8B = (1 << 1), + IDE_TIMING_REC8B = (1 << 2), + IDE_TIMING_CYC8B = (1 << 3), + IDE_TIMING_8BIT = IDE_TIMING_ACT8B | IDE_TIMING_REC8B | + IDE_TIMING_CYC8B, + IDE_TIMING_ACTIVE = (1 << 4), + IDE_TIMING_RECOVER = (1 << 5), + IDE_TIMING_CYCLE = (1 << 6), + IDE_TIMING_UDMA = (1 << 7), + IDE_TIMING_ALL = IDE_TIMING_SETUP | IDE_TIMING_8BIT | + IDE_TIMING_ACTIVE | IDE_TIMING_RECOVER | + IDE_TIMING_CYCLE | IDE_TIMING_UDMA, +}; + +struct ide_timing *ide_timing_find_mode(u8); +u16 ide_pio_cycle_time(ide_drive_t *, u8); +void ide_timing_merge(struct ide_timing *, struct ide_timing *, + struct ide_timing *, unsigned int); +int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int); + +int ide_scan_pio_blacklist(char *); -unsigned int ide_pio_cycle_time(ide_drive_t *, u8); u8 ide_get_best_pio_mode(ide_drive_t *, u8, u8); -extern const ide_pio_timings_t ide_pio_timings[6]; int ide_set_pio_mode(ide_drive_t *, u8); int ide_set_dma_mode(ide_drive_t *, u8); @@ -1334,7 +1341,8 @@ static inline void ide_set_irq(ide_drive_t *drive, int on) { ide_hwif_t *hwif = drive->hwif; - hwif->OUTB(drive->ctl | (on ? 0 : 2), hwif->io_ports.ctl_addr); + hwif->OUTBSYNC(hwif, ATA_DEVCTL_OBS | (on ? 0 : 2), + hwif->io_ports.ctl_addr); } static inline u8 ide_read_status(ide_drive_t *drive) diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h index 0b5e03eae6d2..2998e3b5f166 100644 --- a/include/linux/ieee80211.h +++ b/include/linux/ieee80211.h @@ -98,6 +98,7 @@ #define IEEE80211_MAX_SSID_LEN 32 #define IEEE80211_MAX_MESH_ID_LEN 32 +#define IEEE80211_QOS_CTL_LEN 2 struct ieee80211_hdr { __le16 frame_control; @@ -109,6 +110,355 @@ struct ieee80211_hdr { u8 addr4[6]; } __attribute__ ((packed)); +/** + * ieee80211_has_tods - check if IEEE80211_FCTL_TODS is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_tods(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_TODS)) != 0; +} + +/** + * ieee80211_has_fromds - check if IEEE80211_FCTL_FROMDS is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_fromds(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FROMDS)) != 0; +} + +/** + * ieee80211_has_a4 - check if IEEE80211_FCTL_TODS and IEEE80211_FCTL_FROMDS are set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_a4(__le16 fc) +{ + __le16 tmp = cpu_to_le16(IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS); + return (fc & tmp) == tmp; +} + +/** + * ieee80211_has_morefrags - check if IEEE80211_FCTL_MOREFRAGS is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_morefrags(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) != 0; +} + +/** + * ieee80211_has_retry - check if IEEE80211_FCTL_RETRY is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_retry(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_RETRY)) != 0; +} + +/** + * ieee80211_has_pm - check if IEEE80211_FCTL_PM is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_pm(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_PM)) != 0; +} + +/** + * ieee80211_has_moredata - check if IEEE80211_FCTL_MOREDATA is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_moredata(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) != 0; +} + +/** + * ieee80211_has_protected - check if IEEE80211_FCTL_PROTECTED is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_protected(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_PROTECTED)) != 0; +} + +/** + * ieee80211_has_order - check if IEEE80211_FCTL_ORDER is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_has_order(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_ORDER)) != 0; +} + +/** + * ieee80211_is_mgmt - check if type is IEEE80211_FTYPE_MGMT + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_mgmt(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT); +} + +/** + * ieee80211_is_ctl - check if type is IEEE80211_FTYPE_CTL + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_ctl(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL); +} + +/** + * ieee80211_is_data - check if type is IEEE80211_FTYPE_DATA + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_data(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE)) == + cpu_to_le16(IEEE80211_FTYPE_DATA); +} + +/** + * ieee80211_is_data_qos - check if type is IEEE80211_FTYPE_DATA and IEEE80211_STYPE_QOS_DATA is set + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_data_qos(__le16 fc) +{ + /* + * mask with QOS_DATA rather than IEEE80211_FCTL_STYPE as we just need + * to check the one bit + */ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_STYPE_QOS_DATA)) == + cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA); +} + +/** + * ieee80211_is_data_present - check if type is IEEE80211_FTYPE_DATA and has data + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_data_present(__le16 fc) +{ + /* + * mask with 0x40 and test that that bit is clear to only return true + * for the data-containing substypes. + */ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | 0x40)) == + cpu_to_le16(IEEE80211_FTYPE_DATA); +} + +/** + * ieee80211_is_assoc_req - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_ASSOC_REQ + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_assoc_req(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_ASSOC_REQ); +} + +/** + * ieee80211_is_assoc_resp - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_ASSOC_RESP + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_assoc_resp(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_ASSOC_RESP); +} + +/** + * ieee80211_is_reassoc_req - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_REASSOC_REQ + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_reassoc_req(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_REASSOC_REQ); +} + +/** + * ieee80211_is_reassoc_resp - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_REASSOC_RESP + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_reassoc_resp(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_REASSOC_RESP); +} + +/** + * ieee80211_is_probe_req - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_PROBE_REQ + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_probe_req(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_PROBE_REQ); +} + +/** + * ieee80211_is_probe_resp - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_PROBE_RESP + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_probe_resp(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_PROBE_RESP); +} + +/** + * ieee80211_is_beacon - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_BEACON + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_beacon(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON); +} + +/** + * ieee80211_is_atim - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_ATIM + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_atim(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_ATIM); +} + +/** + * ieee80211_is_disassoc - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_DISASSOC + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_disassoc(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_DISASSOC); +} + +/** + * ieee80211_is_auth - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_AUTH + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_auth(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_AUTH); +} + +/** + * ieee80211_is_deauth - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_DEAUTH + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_deauth(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_DEAUTH); +} + +/** + * ieee80211_is_action - check if IEEE80211_FTYPE_MGMT && IEEE80211_STYPE_ACTION + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_action(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_ACTION); +} + +/** + * ieee80211_is_back_req - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_BACK_REQ + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_back_req(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_BACK_REQ); +} + +/** + * ieee80211_is_back - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_BACK + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_back(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_BACK); +} + +/** + * ieee80211_is_pspoll - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_PSPOLL + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_pspoll(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_PSPOLL); +} + +/** + * ieee80211_is_rts - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_RTS + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_rts(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS); +} + +/** + * ieee80211_is_cts - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_CTS + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_cts(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS); +} + +/** + * ieee80211_is_ack - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_ACK + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_ack(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_ACK); +} + +/** + * ieee80211_is_cfend - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_CFEND + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_cfend(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CFEND); +} + +/** + * ieee80211_is_cfendack - check if IEEE80211_FTYPE_CTL && IEEE80211_STYPE_CFENDACK + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_cfendack(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CFENDACK); +} + +/** + * ieee80211_is_nullfunc - check if FTYPE=IEEE80211_FTYPE_DATA and STYPE=IEEE80211_STYPE_NULLFUNC + * @fc: frame control bytes in little-endian byteorder + */ +static inline int ieee80211_is_nullfunc(__le16 fc) +{ + return (fc & cpu_to_le16(IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == + cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC); +} struct ieee80211s_hdr { u8 flags; @@ -306,20 +656,33 @@ struct ieee80211_ht_addt_info { #define IEEE80211_HT_CAP_SGI_40 0x0040 #define IEEE80211_HT_CAP_DELAY_BA 0x0400 #define IEEE80211_HT_CAP_MAX_AMSDU 0x0800 +/* 802.11n HT capability AMPDU settings */ #define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03 #define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C +/* 802.11n HT capability MSC set */ +#define IEEE80211_SUPP_MCS_SET_UEQM 4 +#define IEEE80211_HT_CAP_MAX_STREAMS 4 +#define IEEE80211_SUPP_MCS_SET_LEN 10 +/* maximum streams the spec allows */ +#define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01 +#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02 +#define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C +#define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10 /* 802.11n HT IE masks */ #define IEEE80211_HT_IE_CHA_SEC_OFFSET 0x03 +#define IEEE80211_HT_IE_CHA_SEC_NONE 0x00 +#define IEEE80211_HT_IE_CHA_SEC_ABOVE 0x01 +#define IEEE80211_HT_IE_CHA_SEC_BELOW 0x03 #define IEEE80211_HT_IE_CHA_WIDTH 0x04 #define IEEE80211_HT_IE_HT_PROTECTION 0x0003 #define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004 #define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010 /* MIMO Power Save Modes */ -#define WLAN_HT_CAP_MIMO_PS_STATIC 0 -#define WLAN_HT_CAP_MIMO_PS_DYNAMIC 1 -#define WLAN_HT_CAP_MIMO_PS_INVALID 2 -#define WLAN_HT_CAP_MIMO_PS_DISABLED 3 +#define WLAN_HT_CAP_MIMO_PS_STATIC 0 +#define WLAN_HT_CAP_MIMO_PS_DYNAMIC 1 +#define WLAN_HT_CAP_MIMO_PS_INVALID 2 +#define WLAN_HT_CAP_MIMO_PS_DISABLED 3 /* Authentication algorithms */ #define WLAN_AUTH_OPEN 0 @@ -540,63 +903,57 @@ enum ieee80211_back_parties { #define WLAN_MAX_KEY_LEN 32 /** + * ieee80211_get_qos_ctl - get pointer to qos control bytes + * @hdr: the frame + * + * The qos ctrl bytes come after the frame_control, duration, seq_num + * and 3 or 4 addresses of length ETH_ALEN. + * 3 addr: 2 + 2 + 2 + 3*6 = 24 + * 4 addr: 2 + 2 + 2 + 4*6 = 30 + */ +static inline u8 *ieee80211_get_qos_ctl(struct ieee80211_hdr *hdr) +{ + if (ieee80211_has_a4(hdr->frame_control)) + return (u8 *)hdr + 30; + else + return (u8 *)hdr + 24; +} + +/** * ieee80211_get_SA - get pointer to SA + * @hdr: the frame * * Given an 802.11 frame, this function returns the offset * to the source address (SA). It does not verify that the * header is long enough to contain the address, and the * header must be long enough to contain the frame control * field. - * - * @hdr: the frame */ static inline u8 *ieee80211_get_SA(struct ieee80211_hdr *hdr) { - u8 *raw = (u8 *) hdr; - u8 tofrom = (*(raw+1)) & 3; /* get the TODS and FROMDS bits */ - - switch (tofrom) { - case 2: - return hdr->addr3; - case 3: - return hdr->addr4; - } + if (ieee80211_has_a4(hdr->frame_control)) + return hdr->addr4; + if (ieee80211_has_fromds(hdr->frame_control)) + return hdr->addr3; return hdr->addr2; } /** * ieee80211_get_DA - get pointer to DA + * @hdr: the frame * * Given an 802.11 frame, this function returns the offset * to the destination address (DA). It does not verify that * the header is long enough to contain the address, and the * header must be long enough to contain the frame control * field. - * - * @hdr: the frame */ static inline u8 *ieee80211_get_DA(struct ieee80211_hdr *hdr) { - u8 *raw = (u8 *) hdr; - u8 to_ds = (*(raw+1)) & 1; /* get the TODS bit */ - - if (to_ds) + if (ieee80211_has_tods(hdr->frame_control)) return hdr->addr3; - return hdr->addr1; -} - -/** - * ieee80211_get_morefrag - determine whether the MOREFRAGS bit is set - * - * This function determines whether the "more fragments" bit is set - * in the frame. - * - * @hdr: the frame - */ -static inline int ieee80211_get_morefrag(struct ieee80211_hdr *hdr) -{ - return (le16_to_cpu(hdr->frame_control) & - IEEE80211_FCTL_MOREFRAGS) != 0; + else + return hdr->addr1; } #endif /* IEEE80211_H */ diff --git a/include/linux/if_bridge.h b/include/linux/if_bridge.h index 950e13d09e06..6badb3e2c4e4 100644 --- a/include/linux/if_bridge.h +++ b/include/linux/if_bridge.h @@ -4,8 +4,6 @@ * Authors: * Lennert Buytenhek <buytenh@gnu.org> * - * $Id: if_bridge.h,v 1.1 2000/02/18 16:47:01 davem Exp $ - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version diff --git a/include/linux/if_ppp.h b/include/linux/if_ppp.h index 0f2f70d4e48c..c3b1f8562709 100644 --- a/include/linux/if_ppp.h +++ b/include/linux/if_ppp.h @@ -1,5 +1,3 @@ -/* $Id: if_ppp.h,v 1.21 2000/03/27 06:03:36 paulus Exp $ */ - /* * if_ppp.h - Point-to-Point Protocol definitions. * diff --git a/include/linux/if_tun.h b/include/linux/if_tun.h index 8c71fe2fb1f5..18f31b6187a3 100644 --- a/include/linux/if_tun.h +++ b/include/linux/if_tun.h @@ -11,8 +11,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * $Id: if_tun.h,v 1.2 2001/06/01 18:39:47 davem Exp $ */ #ifndef __IF_TUN_H diff --git a/include/linux/in_route.h b/include/linux/in_route.h index 61f25c30a2a0..b261b8c915f0 100644 --- a/include/linux/in_route.h +++ b/include/linux/in_route.h @@ -10,19 +10,19 @@ #define RTCF_NOPMTUDISC RTM_F_NOPMTUDISC #define RTCF_NOTIFY 0x00010000 -#define RTCF_DIRECTDST 0x00020000 +#define RTCF_DIRECTDST 0x00020000 /* unused */ #define RTCF_REDIRECTED 0x00040000 -#define RTCF_TPROXY 0x00080000 +#define RTCF_TPROXY 0x00080000 /* unused */ -#define RTCF_FAST 0x00200000 -#define RTCF_MASQ 0x00400000 -#define RTCF_SNAT 0x00800000 +#define RTCF_FAST 0x00200000 /* unused */ +#define RTCF_MASQ 0x00400000 /* unused */ +#define RTCF_SNAT 0x00800000 /* unused */ #define RTCF_DOREDIRECT 0x01000000 #define RTCF_DIRECTSRC 0x04000000 #define RTCF_DNAT 0x08000000 #define RTCF_BROADCAST 0x10000000 #define RTCF_MULTICAST 0x20000000 -#define RTCF_REJECT 0x40000000 +#define RTCF_REJECT 0x40000000 /* unused */ #define RTCF_LOCAL 0x80000000 #define RTCF_NAT (RTCF_DNAT|RTCF_SNAT) diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h index 7009b0cdd06f..c6f51ad52d5b 100644 --- a/include/linux/inetdevice.h +++ b/include/linux/inetdevice.h @@ -117,7 +117,6 @@ struct in_ifaddr __be32 ifa_address; __be32 ifa_mask; __be32 ifa_broadcast; - __be32 ifa_anycast; unsigned char ifa_scope; unsigned char ifa_flags; unsigned char ifa_prefixlen; diff --git a/include/linux/init.h b/include/linux/init.h index 21d658cdfa27..b1ed48ddf73f 100644 --- a/include/linux/init.h +++ b/include/linux/init.h @@ -142,6 +142,7 @@ extern initcall_t __security_initcall_start[], __security_initcall_end[]; extern char __initdata boot_command_line[]; extern char *saved_command_line; extern unsigned int reset_devices; +extern int initmem_now_dynamic; /* used by init/main.c */ void setup_arch(char **); diff --git a/include/linux/input.h b/include/linux/input.h index 28a094fcfe20..3e86b61d2e4c 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -373,6 +373,8 @@ struct input_absinfo { #define KEY_WIMAX 246 +/* Range 248 - 255 is reserved for special needs of AT keyboard driver */ + #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 @@ -637,7 +639,9 @@ struct input_absinfo { #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ -#define SW_RADIO 0x03 /* set = radio enabled */ +#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" + set = radio enabled */ +#define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) @@ -1213,11 +1217,6 @@ struct input_handle { struct list_head h_node; }; -#define to_dev(n) container_of(n, struct input_dev, node) -#define to_handler(n) container_of(n, struct input_handler, node) -#define to_handle(n) container_of(n, struct input_handle, d_node) -#define to_handle_h(n) container_of(n, struct input_handle, h_node) - struct input_dev *input_allocate_device(void); void input_free_device(struct input_dev *dev); diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index f1fc7470d26c..62aa4f895abe 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -104,8 +104,11 @@ extern void enable_irq(unsigned int irq); #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) +extern cpumask_t irq_default_affinity; + extern int irq_set_affinity(unsigned int irq, cpumask_t cpumask); extern int irq_can_set_affinity(unsigned int irq); +extern int irq_select_affinity(unsigned int irq); #else /* CONFIG_SMP */ @@ -119,6 +122,8 @@ static inline int irq_can_set_affinity(unsigned int irq) return 0; } +static inline int irq_select_affinity(unsigned int irq) { return 0; } + #endif /* CONFIG_SMP && CONFIG_GENERIC_HARDIRQS */ #ifdef CONFIG_GENERIC_HARDIRQS @@ -285,12 +290,11 @@ enum struct softirq_action { void (*action)(struct softirq_action *); - void *data; }; asmlinkage void do_softirq(void); asmlinkage void __do_softirq(void); -extern void open_softirq(int nr, void (*action)(struct softirq_action*), void *data); +extern void open_softirq(int nr, void (*action)(struct softirq_action *)); extern void softirq_init(void); #define __raise_softirq_irqoff(nr) do { or_softirq_pending(1UL << (nr)); } while (0) extern void raise_softirq_irqoff(unsigned int nr); diff --git a/include/linux/ioport.h b/include/linux/ioport.h index d5d40a9f7929..c6801bffe76d 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -53,14 +53,14 @@ struct resource_list { #define IORESOURCE_AUTO 0x40000000 #define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ -/* ISA PnP IRQ specific bits (IORESOURCE_BITS) */ +/* PnP IRQ specific bits (IORESOURCE_BITS) */ #define IORESOURCE_IRQ_HIGHEDGE (1<<0) #define IORESOURCE_IRQ_LOWEDGE (1<<1) #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) #define IORESOURCE_IRQ_LOWLEVEL (1<<3) #define IORESOURCE_IRQ_SHAREABLE (1<<4) -/* ISA PnP DMA specific bits (IORESOURCE_BITS) */ +/* PnP DMA specific bits (IORESOURCE_BITS) */ #define IORESOURCE_DMA_TYPE_MASK (3<<0) #define IORESOURCE_DMA_8BIT (0<<0) #define IORESOURCE_DMA_8AND16BIT (1<<0) @@ -76,7 +76,7 @@ struct resource_list { #define IORESOURCE_DMA_TYPEB (2<<6) #define IORESOURCE_DMA_TYPEF (3<<6) -/* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */ +/* PnP memory I/O specific bits (IORESOURCE_BITS) */ #define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ #define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ #define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ diff --git a/include/linux/ip6_tunnel.h b/include/linux/ip6_tunnel.h index af3f4a70f3df..1e7cc4af40de 100644 --- a/include/linux/ip6_tunnel.h +++ b/include/linux/ip6_tunnel.h @@ -1,7 +1,3 @@ -/* - * $Id$ - */ - #ifndef _IP6_TUNNEL_H #define _IP6_TUNNEL_H diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index 10b666b61add..cde056e08181 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -396,8 +396,10 @@ static inline struct request_sock *inet6_reqsk_alloc(struct request_sock_ops *op { struct request_sock *req = reqsk_alloc(ops); - if (req != NULL) + if (req != NULL) { inet_rsk(req)->inet6_rsk_offset = inet6_rsk_offset(req); + inet6_rsk(req)->pktopts = NULL; + } return req; } diff --git a/include/linux/irq.h b/include/linux/irq.h index 552e0ec269c9..8ccb462ea42c 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -244,15 +244,6 @@ static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) } #endif -#ifdef CONFIG_AUTO_IRQ_AFFINITY -extern int select_smp_affinity(unsigned int irq); -#else -static inline int select_smp_affinity(unsigned int irq) -{ - return 1; -} -#endif - extern int no_irq_affinity; static inline int irq_balancing_disabled(unsigned int irq) diff --git a/include/linux/irqflags.h b/include/linux/irqflags.h index e600c4e9b8c5..2b1c2e58566e 100644 --- a/include/linux/irqflags.h +++ b/include/linux/irqflags.h @@ -12,10 +12,10 @@ #define _LINUX_TRACE_IRQFLAGS_H #ifdef CONFIG_TRACE_IRQFLAGS - extern void trace_hardirqs_on(void); - extern void trace_hardirqs_off(void); extern void trace_softirqs_on(unsigned long ip); extern void trace_softirqs_off(unsigned long ip); + extern void trace_hardirqs_on(void); + extern void trace_hardirqs_off(void); # define trace_hardirq_context(p) ((p)->hardirq_context) # define trace_softirq_context(p) ((p)->softirq_context) # define trace_hardirqs_enabled(p) ((p)->hardirqs_enabled) @@ -41,6 +41,15 @@ # define INIT_TRACE_IRQFLAGS #endif +#if defined(CONFIG_IRQSOFF_TRACER) || \ + defined(CONFIG_PREEMPT_TRACER) + extern void stop_critical_timings(void); + extern void start_critical_timings(void); +#else +# define stop_critical_timings() do { } while (0) +# define start_critical_timings() do { } while (0) +#endif + #ifdef CONFIG_TRACE_IRQFLAGS_SUPPORT #include <asm/irqflags.h> diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h index 05e2b307161a..ec9cadf58227 100644 --- a/include/linux/jbd2.h +++ b/include/linux/jbd2.h @@ -168,6 +168,8 @@ struct commit_header { unsigned char h_chksum_size; unsigned char h_padding[2]; __be32 h_chksum[JBD2_CHECKSUM_BYTES]; + __be64 h_commit_sec; + __be32 h_commit_nsec; }; /* @@ -919,6 +921,9 @@ struct journal_s struct proc_dir_entry *j_proc_entry; struct transaction_stats_s j_stats; + /* Failed journal commit ID */ + unsigned int j_failed_commit; + /* * An opaque pointer to fs-private information. ext3 puts its * superblock pointer here diff --git a/include/linux/jffs2.h b/include/linux/jffs2.h index 6b563cae23df..da720bc3eb15 100644 --- a/include/linux/jffs2.h +++ b/include/linux/jffs2.h @@ -7,9 +7,6 @@ * * For licensing information, see the file 'LICENCE' in the * jffs2 directory. - * - * $Id: jffs2.h,v 1.38 2005/09/26 11:37:23 havasi Exp $ - * */ #ifndef __LINUX_JFFS2_H__ diff --git a/include/linux/joystick.h b/include/linux/joystick.h index e2d3a18af456..b5e051295a67 100644 --- a/include/linux/joystick.h +++ b/include/linux/joystick.h @@ -2,8 +2,6 @@ #define _LINUX_JOYSTICK_H /* - * $Id: joystick.h,v 1.3 2000/11/30 11:07:05 vojtech Exp $ - * * Copyright (C) 1996-2000 Vojtech Pavlik * * Sponsored by SuSE diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 792bf0aa779b..945348313b09 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -184,9 +184,6 @@ asmlinkage int vprintk(const char *fmt, va_list args) __attribute__ ((format (printf, 1, 0))); asmlinkage int printk(const char * fmt, ...) __attribute__ ((format (printf, 1, 2))) __cold; -extern int log_buf_get_len(void); -extern int log_buf_read(int idx); -extern int log_buf_copy(char *dest, int idx, int len); extern int printk_ratelimit_jiffies; extern int printk_ratelimit_burst; @@ -202,9 +199,6 @@ static inline int vprintk(const char *s, va_list args) { return 0; } static inline int printk(const char *s, ...) __attribute__ ((format (printf, 1, 2))); static inline int __cold printk(const char *s, ...) { return 0; } -static inline int log_buf_get_len(void) { return 0; } -static inline int log_buf_read(int idx) { return 0; } -static inline int log_buf_copy(char *dest, int idx, int len) { return 0; } static inline int printk_ratelimit(void) { return 0; } static inline int __printk_ratelimit(int ratelimit_jiffies, \ int ratelimit_burst) { return 0; } @@ -506,4 +500,39 @@ struct sysinfo { #define NUMA_BUILD 0 #endif +/* If fn is of type ok1 or ok2, cast to desttype */ +#define __typesafe_cb(desttype, fn, ok1, ok2) \ + cast_if_type(cast_if_type((fn), ok1, desttype), ok2, desttype) + +/** + * typesafe_cb - cast a callback function if it matches the arg + * @rettype: the return type of the callback function + * @fn: the callback function to cast + * @arg: the (pointer) argument to hand to the callback function. + * + * If a callback function takes a single argument, this macro does + * appropriate casts to a function which takes a single void * argument if the + * callback provided matches the @arg (or a const or volatile version). + * + * It is assumed that @arg is of pointer type: usually @arg is passed + * or assigned to a void * elsewhere anyway. + */ +#define typesafe_cb(rettype, fn, arg) \ + __typesafe_cb(rettype (*)(void *), (fn), \ + rettype (*)(const typeof(arg)), \ + rettype (*)(typeof(arg))) + +/** + * typesafe_cb_preargs - cast a callback function if it matches the arg + * @rettype: the return type of the callback function + * @fn: the callback function to cast + * @arg: the (pointer) argument to hand to the callback function. + * + * This is a version of typesafe_cb() for callbacks that take other arguments + * before the @arg. + */ +#define typesafe_cb_preargs(rettype, fn, arg, ...) \ + __typesafe_cb(rettype (*)(__VA_ARGS__, void *), (fn), \ + rettype (*)(__VA_ARGS__, const typeof(arg)), \ + rettype (*)(__VA_ARGS__, typeof(arg))) #endif diff --git a/include/linux/kernel_stat.h b/include/linux/kernel_stat.h index e8ffce898bf9..cf9f40a91c9c 100644 --- a/include/linux/kernel_stat.h +++ b/include/linux/kernel_stat.h @@ -1,11 +1,11 @@ #ifndef _LINUX_KERNEL_STAT_H #define _LINUX_KERNEL_STAT_H -#include <asm/irq.h> #include <linux/smp.h> #include <linux/threads.h> #include <linux/percpu.h> #include <linux/cpumask.h> +#include <asm/irq.h> #include <asm/cputime.h> /* diff --git a/include/linux/kobject.h b/include/linux/kobject.h index 39e709f88aa0..60f0d418ae32 100644 --- a/include/linux/kobject.h +++ b/include/linux/kobject.h @@ -26,7 +26,6 @@ #include <linux/wait.h> #include <asm/atomic.h> -#define KOBJ_NAME_LEN 20 #define UEVENT_HELPER_PATH_LEN 256 #define UEVENT_NUM_ENVP 32 /* number of env pointers */ #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */ @@ -59,12 +58,12 @@ enum kobject_action { struct kobject { const char *name; - struct kref kref; struct list_head entry; struct kobject *parent; struct kset *kset; struct kobj_type *ktype; struct sysfs_dirent *sd; + struct kref kref; unsigned int state_initialized:1; unsigned int state_in_sysfs:1; unsigned int state_add_uevent_sent:1; diff --git a/include/linux/kthread.h b/include/linux/kthread.h index 00dd957e245b..3152c1ef1d08 100644 --- a/include/linux/kthread.h +++ b/include/linux/kthread.h @@ -4,9 +4,32 @@ #include <linux/err.h> #include <linux/sched.h> -struct task_struct *kthread_create(int (*threadfn)(void *data), - void *data, - const char namefmt[], ...); +/** + * kthread_create - create a kthread. + * @threadfn: the function to run until signal_pending(current). + * @data: data ptr for @threadfn. + * @namefmt: printf-style name for the thread. + * + * Description: This helper function creates and names a kernel + * thread. The thread will be stopped: use wake_up_process() to start + * it. See also kthread_run(), kthread_create_on_cpu(). + * + * When woken, the thread will run @threadfn() with @data as its + * argument. @threadfn() can either call do_exit() directly if it is a + * standalone thread for which noone will call kthread_stop(), or + * return when 'kthread_should_stop()' is true (which means + * kthread_stop() has been called). The return value should be zero + * or a negative error number; it will be passed to kthread_stop(). + * + * Returns a task_struct or ERR_PTR(-ENOMEM). + */ +#define kthread_create(threadfn, data, namefmt...) \ + __kthread_create(typesafe_cb(int,(threadfn),(data)), (data), namefmt) + +struct task_struct *__kthread_create(int (*threadfn)(void *data), + void *data, + const char namefmt[], ...) + __attribute__((format(printf, 3, 4))); /** * kthread_run - create and wake a thread. diff --git a/include/linux/kvm.h b/include/linux/kvm.h index a281afeddfbb..0ea064cbfbc8 100644 --- a/include/linux/kvm.h +++ b/include/linux/kvm.h @@ -173,6 +173,30 @@ struct kvm_run { }; }; +/* for KVM_REGISTER_COALESCED_MMIO / KVM_UNREGISTER_COALESCED_MMIO */ + +struct kvm_coalesced_mmio_zone { + __u64 addr; + __u32 size; + __u32 pad; +}; + +struct kvm_coalesced_mmio { + __u64 phys_addr; + __u32 len; + __u32 pad; + __u8 data[8]; +}; + +struct kvm_coalesced_mmio_ring { + __u32 first, last; + struct kvm_coalesced_mmio coalesced_mmio[0]; +}; + +#define KVM_COALESCED_MMIO_MAX \ + ((PAGE_SIZE - sizeof(struct kvm_coalesced_mmio_ring)) / \ + sizeof(struct kvm_coalesced_mmio)) + /* for KVM_TRANSLATE */ struct kvm_translation { /* in */ @@ -294,14 +318,14 @@ struct kvm_trace_rec { __u32 vcpu_id; union { struct { - __u32 cycle_lo, cycle_hi; + __u64 cycle_u64; __u32 extra_u32[KVM_TRC_EXTRA_MAX]; } cycle; struct { __u32 extra_u32[KVM_TRC_EXTRA_MAX]; } nocycle; } u; -}; +} __attribute__((packed)); #define KVMIO 0xAE @@ -346,6 +370,7 @@ struct kvm_trace_rec { #define KVM_CAP_NOP_IO_DELAY 12 #define KVM_CAP_PV_MMU 13 #define KVM_CAP_MP_STATE 14 +#define KVM_CAP_COALESCED_MMIO 15 /* * ioctls for VM fds @@ -371,6 +396,10 @@ struct kvm_trace_rec { #define KVM_CREATE_PIT _IO(KVMIO, 0x64) #define KVM_GET_PIT _IOWR(KVMIO, 0x65, struct kvm_pit_state) #define KVM_SET_PIT _IOR(KVMIO, 0x66, struct kvm_pit_state) +#define KVM_REGISTER_COALESCED_MMIO \ + _IOW(KVMIO, 0x67, struct kvm_coalesced_mmio_zone) +#define KVM_UNREGISTER_COALESCED_MMIO \ + _IOW(KVMIO, 0x68, struct kvm_coalesced_mmio_zone) /* * ioctls for vcpu fds diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 398978972b7a..d220b4926c4a 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -33,6 +33,7 @@ #define KVM_REQ_REPORT_TPR_ACCESS 2 #define KVM_REQ_MMU_RELOAD 3 #define KVM_REQ_TRIPLE_FAULT 4 +#define KVM_REQ_PENDING_TIMER 5 struct kvm_vcpu; extern struct kmem_cache *kvm_vcpu_cache; @@ -51,7 +52,8 @@ struct kvm_io_bus { void kvm_io_bus_init(struct kvm_io_bus *bus); void kvm_io_bus_destroy(struct kvm_io_bus *bus); -struct kvm_io_device *kvm_io_bus_find_dev(struct kvm_io_bus *bus, gpa_t addr); +struct kvm_io_device *kvm_io_bus_find_dev(struct kvm_io_bus *bus, + gpa_t addr, int len, int is_write); void kvm_io_bus_register_dev(struct kvm_io_bus *bus, struct kvm_io_device *dev); @@ -115,6 +117,10 @@ struct kvm { struct kvm_vm_stat stat; struct kvm_arch arch; atomic_t users_count; +#ifdef KVM_COALESCED_MMIO_PAGE_OFFSET + struct kvm_coalesced_mmio_dev *coalesced_mmio_dev; + struct kvm_coalesced_mmio_ring *coalesced_mmio_ring; +#endif }; /* The guest did something we don't support. */ @@ -134,9 +140,6 @@ void kvm_vcpu_uninit(struct kvm_vcpu *vcpu); void vcpu_load(struct kvm_vcpu *vcpu); void vcpu_put(struct kvm_vcpu *vcpu); -void decache_vcpus_on_cpu(int cpu); - - int kvm_init(void *opaque, unsigned int vcpu_size, struct module *module); void kvm_exit(void); @@ -297,7 +300,7 @@ static inline gpa_t gfn_to_gpa(gfn_t gfn) return (gpa_t)gfn << PAGE_SHIFT; } -static inline void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) +static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu) { set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests); } diff --git a/include/linux/libata.h b/include/linux/libata.h index 4a92fbafce9d..5b247b8a6b3b 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -27,6 +27,7 @@ #define __LINUX_LIBATA_H__ #include <linux/delay.h> +#include <linux/jiffies.h> #include <linux/interrupt.h> #include <linux/dma-mapping.h> #include <linux/scatterlist.h> @@ -111,14 +112,11 @@ enum { /* various global constants */ LIBATA_MAX_PRD = ATA_MAX_PRD / 2, LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4, /* Worst case */ - ATA_MAX_PORTS = 8, ATA_DEF_QUEUE = 1, /* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */ ATA_MAX_QUEUE = 32, ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1, - ATA_MAX_BUS = 2, - ATA_DEF_BUSY_WAIT = 10000, - ATA_SHORT_PAUSE = (HZ >> 6) + 1, + ATA_SHORT_PAUSE = 16, ATAPI_MAX_DRAIN = 16 << 10, @@ -171,6 +169,7 @@ enum { ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB, ATA_LFLAG_NO_RETRY = (1 << 5), /* don't retry this link */ ATA_LFLAG_DISABLED = (1 << 6), /* link is disabled */ + ATA_LFLAG_SW_ACTIVITY = (1 << 7), /* keep activity stats */ /* struct ata_port flags */ ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */ @@ -193,6 +192,10 @@ enum { ATA_FLAG_AN = (1 << 18), /* controller supports AN */ ATA_FLAG_PMP = (1 << 19), /* controller supports PMP */ ATA_FLAG_IPM = (1 << 20), /* driver can handle IPM */ + ATA_FLAG_EM = (1 << 21), /* driver supports enclosure + * management */ + ATA_FLAG_SW_ACTIVITY = (1 << 22), /* driver supports sw activity + * led */ /* The following flag belongs to ap->pflags but is kept in * ap->flags because it's referenced in many LLDs and will be @@ -237,17 +240,16 @@ enum { /* bits 24:31 of host->flags are reserved for LLD specific flags */ /* various lengths of time */ - ATA_TMOUT_BOOT = 30 * HZ, /* heuristic */ - ATA_TMOUT_BOOT_QUICK = 7 * HZ, /* heuristic */ - ATA_TMOUT_INTERNAL = 30 * HZ, - ATA_TMOUT_INTERNAL_QUICK = 5 * HZ, + ATA_TMOUT_BOOT = 30000, /* heuristic */ + ATA_TMOUT_BOOT_QUICK = 7000, /* heuristic */ + ATA_TMOUT_INTERNAL_QUICK = 5000, /* FIXME: GoVault needs 2s but we can't afford that without * parallel probing. 800ms is enough for iVDR disk * HHD424020F7SV00. Increase to 2secs when parallel probing * is in place. */ - ATA_TMOUT_FF_WAIT = 4 * HZ / 5, + ATA_TMOUT_FF_WAIT = 800, /* Spec mandates to wait for ">= 2ms" before checking status * after reset. We wait 150ms, because that was the magic @@ -259,14 +261,14 @@ enum { * * Old drivers/ide uses the 2mS rule and then waits for ready. */ - ATA_WAIT_AFTER_RESET_MSECS = 150, + ATA_WAIT_AFTER_RESET = 150, /* If PMP is supported, we have to do follow-up SRST. As some * PMPs don't send D2H Reg FIS after hardreset, LLDs are * advised to wait only for the following duration before * doing SRST. */ - ATA_TMOUT_PMP_SRST_WAIT = 1 * HZ, + ATA_TMOUT_PMP_SRST_WAIT = 1000, /* ATA bus states */ BUS_UNKNOWN = 0, @@ -343,6 +345,11 @@ enum { SATA_PMP_RW_TIMEOUT = 3000, /* PMP read/write timeout */ + /* This should match the actual table size of + * ata_eh_cmd_timeout_table in libata-eh.c. + */ + ATA_EH_CMD_TIMEOUT_TABLE_SIZE = 5, + /* Horkage types. May be set by libata or controller on drives (some horkage may be drive/controller pair dependant */ @@ -444,6 +451,15 @@ enum link_pm { MEDIUM_POWER, }; extern struct device_attribute dev_attr_link_power_management_policy; +extern struct device_attribute dev_attr_em_message_type; +extern struct device_attribute dev_attr_em_message; +extern struct device_attribute dev_attr_sw_activity; + +enum sw_activity { + OFF, + BLINK_ON, + BLINK_OFF, +}; #ifdef CONFIG_ATA_SFF struct ata_ioports { @@ -600,10 +616,14 @@ struct ata_eh_info { struct ata_eh_context { struct ata_eh_info i; int tries[ATA_MAX_DEVICES]; + int cmd_timeout_idx[ATA_MAX_DEVICES] + [ATA_EH_CMD_TIMEOUT_TABLE_SIZE]; unsigned int classes[ATA_MAX_DEVICES]; unsigned int did_probe_mask; unsigned int saved_ncq_enabled; u8 saved_xfer_mode[ATA_MAX_DEVICES]; + /* timestamp for the last reset attempt or success */ + unsigned long last_reset; }; struct ata_acpi_drive @@ -695,6 +715,7 @@ struct ata_port { struct timer_list fastdrain_timer; unsigned long fastdrain_cnt; + int em_message_type; void *private_data; #ifdef CONFIG_ATA_ACPI @@ -786,6 +807,12 @@ struct ata_port_operations { u8 (*bmdma_status)(struct ata_port *ap); #endif /* CONFIG_ATA_SFF */ + ssize_t (*em_show)(struct ata_port *ap, char *buf); + ssize_t (*em_store)(struct ata_port *ap, const char *message, + size_t size); + ssize_t (*sw_activity_show)(struct ata_device *dev, char *buf); + ssize_t (*sw_activity_store)(struct ata_device *dev, + enum sw_activity val); /* * Obsolete */ @@ -898,8 +925,7 @@ extern void ata_host_resume(struct ata_host *host); #endif extern int ata_ratelimit(void); extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val, - unsigned long interval_msec, - unsigned long timeout_msec); + unsigned long interval, unsigned long timeout); extern int atapi_cmd_type(u8 opcode); extern void ata_tf_to_fis(const struct ata_taskfile *tf, u8 pmp, int is_cmd, u8 *fis); @@ -1392,6 +1418,12 @@ static inline int ata_check_ready(u8 status) return 0; } +static inline unsigned long ata_deadline(unsigned long from_jiffies, + unsigned long timeout_msecs) +{ + return from_jiffies + msecs_to_jiffies(timeout_msecs); +} + /************************************************************************** * PMP - drivers/ata/libata-pmp.c @@ -1435,7 +1467,8 @@ extern void ata_sff_qc_prep(struct ata_queued_cmd *qc); extern void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc); extern void ata_sff_dev_select(struct ata_port *ap, unsigned int device); extern u8 ata_sff_check_status(struct ata_port *ap); -extern u8 ata_sff_altstatus(struct ata_port *ap); +extern void ata_sff_pause(struct ata_port *ap); +extern void ata_sff_dma_pause(struct ata_port *ap); extern int ata_sff_busy_sleep(struct ata_port *ap, unsigned long timeout_pat, unsigned long timeout); extern int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline); @@ -1496,19 +1529,6 @@ extern int ata_pci_sff_init_one(struct pci_dev *pdev, #endif /* CONFIG_PCI */ /** - * ata_sff_pause - Flush writes and pause 400 nanoseconds. - * @ap: Port to wait for. - * - * LOCKING: - * Inherited from caller. - */ -static inline void ata_sff_pause(struct ata_port *ap) -{ - ata_sff_altstatus(ap); - ndelay(400); -} - -/** * ata_sff_busy_wait - Wait for a port status register * @ap: Port to wait for. * @bits: bits that must be clear diff --git a/include/linux/libps2.h b/include/linux/libps2.h index f6f301e2b0f5..afc413369101 100644 --- a/include/linux/libps2.h +++ b/include/linux/libps2.h @@ -43,7 +43,6 @@ void ps2_init(struct ps2dev *ps2dev, struct serio *serio); int ps2_sendbyte(struct ps2dev *ps2dev, unsigned char byte, int timeout); void ps2_drain(struct ps2dev *ps2dev, int maxbytes, int timeout); int ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command); -int ps2_schedule_command(struct ps2dev *ps2dev, unsigned char *param, int command); int ps2_handle_ack(struct ps2dev *ps2dev, unsigned char data); int ps2_handle_response(struct ps2dev *ps2dev, unsigned char data); void ps2_cmd_aborted(struct ps2dev *ps2dev); diff --git a/include/linux/linkage.h b/include/linux/linkage.h index 2119610b24f8..14f329c64ba8 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -3,6 +3,8 @@ #include <asm/linkage.h> +#define notrace __attribute__((no_instrument_function)) + #ifdef __cplusplus #define CPP_ASMLINKAGE extern "C" #else diff --git a/include/linux/list.h b/include/linux/list.h index 08cf4f651889..139ec41d9c2e 100644 --- a/include/linux/list.h +++ b/include/linux/list.h @@ -85,65 +85,6 @@ static inline void list_add_tail(struct list_head *new, struct list_head *head) } /* - * Insert a new entry between two known consecutive entries. - * - * This is only for internal list manipulation where we know - * the prev/next entries already! - */ -static inline void __list_add_rcu(struct list_head * new, - struct list_head * prev, struct list_head * next) -{ - new->next = next; - new->prev = prev; - smp_wmb(); - next->prev = new; - prev->next = new; -} - -/** - * list_add_rcu - add a new entry to rcu-protected list - * @new: new entry to be added - * @head: list head to add it after - * - * Insert a new entry after the specified head. - * This is good for implementing stacks. - * - * The caller must take whatever precautions are necessary - * (such as holding appropriate locks) to avoid racing - * with another list-mutation primitive, such as list_add_rcu() - * or list_del_rcu(), running on this same list. - * However, it is perfectly legal to run concurrently with - * the _rcu list-traversal primitives, such as - * list_for_each_entry_rcu(). - */ -static inline void list_add_rcu(struct list_head *new, struct list_head *head) -{ - __list_add_rcu(new, head, head->next); -} - -/** - * list_add_tail_rcu - add a new entry to rcu-protected list - * @new: new entry to be added - * @head: list head to add it before - * - * Insert a new entry before the specified head. - * This is useful for implementing queues. - * - * The caller must take whatever precautions are necessary - * (such as holding appropriate locks) to avoid racing - * with another list-mutation primitive, such as list_add_tail_rcu() - * or list_del_rcu(), running on this same list. - * However, it is perfectly legal to run concurrently with - * the _rcu list-traversal primitives, such as - * list_for_each_entry_rcu(). - */ -static inline void list_add_tail_rcu(struct list_head *new, - struct list_head *head) -{ - __list_add_rcu(new, head->prev, head); -} - -/* * Delete a list entry by making the prev/next entries * point to each other. * @@ -174,36 +115,6 @@ extern void list_del(struct list_head *entry); #endif /** - * list_del_rcu - deletes entry from list without re-initialization - * @entry: the element to delete from the list. - * - * Note: list_empty() on entry does not return true after this, - * the entry is in an undefined state. It is useful for RCU based - * lockfree traversal. - * - * In particular, it means that we can not poison the forward - * pointers that may still be used for walking the list. - * - * The caller must take whatever precautions are necessary - * (such as holding appropriate locks) to avoid racing - * with another list-mutation primitive, such as list_del_rcu() - * or list_add_rcu(), running on this same list. - * However, it is perfectly legal to run concurrently with - * the _rcu list-traversal primitives, such as - * list_for_each_entry_rcu(). - * - * Note that the caller is not permitted to immediately free - * the newly deleted entry. Instead, either synchronize_rcu() - * or call_rcu() must be used to defer freeing until an RCU - * grace period has elapsed. - */ -static inline void list_del_rcu(struct list_head *entry) -{ - __list_del(entry->prev, entry->next); - entry->prev = LIST_POISON2; -} - -/** * list_replace - replace old entry by new one * @old : the element to be replaced * @new : the new element to insert @@ -227,25 +138,6 @@ static inline void list_replace_init(struct list_head *old, } /** - * list_replace_rcu - replace old entry by new one - * @old : the element to be replaced - * @new : the new element to insert - * - * The @old entry will be replaced with the @new entry atomically. - * Note: @old should not be empty. - */ -static inline void list_replace_rcu(struct list_head *old, - struct list_head *new) -{ - new->next = old->next; - new->prev = old->prev; - smp_wmb(); - new->next->prev = new; - new->prev->next = new; - old->prev = LIST_POISON2; -} - -/** * list_del_init - deletes entry from list and reinitialize it. * @entry: the element to delete from the list. */ @@ -369,62 +261,6 @@ static inline void list_splice_init(struct list_head *list, } /** - * list_splice_init_rcu - splice an RCU-protected list into an existing list. - * @list: the RCU-protected list to splice - * @head: the place in the list to splice the first list into - * @sync: function to sync: synchronize_rcu(), synchronize_sched(), ... - * - * @head can be RCU-read traversed concurrently with this function. - * - * Note that this function blocks. - * - * Important note: the caller must take whatever action is necessary to - * prevent any other updates to @head. In principle, it is possible - * to modify the list as soon as sync() begins execution. - * If this sort of thing becomes necessary, an alternative version - * based on call_rcu() could be created. But only if -really- - * needed -- there is no shortage of RCU API members. - */ -static inline void list_splice_init_rcu(struct list_head *list, - struct list_head *head, - void (*sync)(void)) -{ - struct list_head *first = list->next; - struct list_head *last = list->prev; - struct list_head *at = head->next; - - if (list_empty(head)) - return; - - /* "first" and "last" tracking list, so initialize it. */ - - INIT_LIST_HEAD(list); - - /* - * At this point, the list body still points to the source list. - * Wait for any readers to finish using the list before splicing - * the list body into the new list. Any new readers will see - * an empty list. - */ - - sync(); - - /* - * Readers are finished with the source list, so perform splice. - * The order is important if the new list is global and accessible - * to concurrent RCU readers. Note that RCU readers are not - * permitted to traverse the prev pointers without excluding - * this function. - */ - - last->next = at; - smp_wmb(); - head->next = first; - first->prev = head; - at->prev = last; -} - -/** * list_entry - get the struct for this entry * @ptr: the &struct list_head pointer. * @type: the type of the struct this is embedded in. @@ -629,57 +465,6 @@ static inline void list_splice_init_rcu(struct list_head *list, &pos->member != (head); \ pos = n, n = list_entry(n->member.prev, typeof(*n), member)) -/** - * list_for_each_rcu - iterate over an rcu-protected list - * @pos: the &struct list_head to use as a loop cursor. - * @head: the head for your list. - * - * This list-traversal primitive may safely run concurrently with - * the _rcu list-mutation primitives such as list_add_rcu() - * as long as the traversal is guarded by rcu_read_lock(). - */ -#define list_for_each_rcu(pos, head) \ - for (pos = rcu_dereference((head)->next); \ - prefetch(pos->next), pos != (head); \ - pos = rcu_dereference(pos->next)) - -#define __list_for_each_rcu(pos, head) \ - for (pos = rcu_dereference((head)->next); \ - pos != (head); \ - pos = rcu_dereference(pos->next)) - -/** - * list_for_each_entry_rcu - iterate over rcu list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - * - * This list-traversal primitive may safely run concurrently with - * the _rcu list-mutation primitives such as list_add_rcu() - * as long as the traversal is guarded by rcu_read_lock(). - */ -#define list_for_each_entry_rcu(pos, head, member) \ - for (pos = list_entry(rcu_dereference((head)->next), typeof(*pos), member); \ - prefetch(pos->member.next), &pos->member != (head); \ - pos = list_entry(rcu_dereference(pos->member.next), typeof(*pos), member)) - - -/** - * list_for_each_continue_rcu - * @pos: the &struct list_head to use as a loop cursor. - * @head: the head for your list. - * - * Iterate over an rcu-protected list, continuing after current point. - * - * This list-traversal primitive may safely run concurrently with - * the _rcu list-mutation primitives such as list_add_rcu() - * as long as the traversal is guarded by rcu_read_lock(). - */ -#define list_for_each_continue_rcu(pos, head) \ - for ((pos) = rcu_dereference((pos)->next); \ - prefetch((pos)->next), (pos) != (head); \ - (pos) = rcu_dereference((pos)->next)) - /* * Double linked lists with a single pointer list head. * Mostly useful for hash tables where the two pointer list head is @@ -730,31 +515,6 @@ static inline void hlist_del(struct hlist_node *n) n->pprev = LIST_POISON2; } -/** - * hlist_del_rcu - deletes entry from hash list without re-initialization - * @n: the element to delete from the hash list. - * - * Note: list_unhashed() on entry does not return true after this, - * the entry is in an undefined state. It is useful for RCU based - * lockfree traversal. - * - * In particular, it means that we can not poison the forward - * pointers that may still be used for walking the hash list. - * - * The caller must take whatever precautions are necessary - * (such as holding appropriate locks) to avoid racing - * with another list-mutation primitive, such as hlist_add_head_rcu() - * or hlist_del_rcu(), running on this same list. - * However, it is perfectly legal to run concurrently with - * the _rcu list-traversal primitives, such as - * hlist_for_each_entry(). - */ -static inline void hlist_del_rcu(struct hlist_node *n) -{ - __hlist_del(n); - n->pprev = LIST_POISON2; -} - static inline void hlist_del_init(struct hlist_node *n) { if (!hlist_unhashed(n)) { @@ -763,27 +523,6 @@ static inline void hlist_del_init(struct hlist_node *n) } } -/** - * hlist_replace_rcu - replace old entry by new one - * @old : the element to be replaced - * @new : the new element to insert - * - * The @old entry will be replaced with the @new entry atomically. - */ -static inline void hlist_replace_rcu(struct hlist_node *old, - struct hlist_node *new) -{ - struct hlist_node *next = old->next; - - new->next = next; - new->pprev = old->pprev; - smp_wmb(); - if (next) - new->next->pprev = &new->next; - *new->pprev = new; - old->pprev = LIST_POISON2; -} - static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) { struct hlist_node *first = h->first; @@ -794,38 +533,6 @@ static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) n->pprev = &h->first; } - -/** - * hlist_add_head_rcu - * @n: the element to add to the hash list. - * @h: the list to add to. - * - * Description: - * Adds the specified element to the specified hlist, - * while permitting racing traversals. - * - * The caller must take whatever precautions are necessary - * (such as holding appropriate locks) to avoid racing - * with another list-mutation primitive, such as hlist_add_head_rcu() - * or hlist_del_rcu(), running on this same list. - * However, it is perfectly legal to run concurrently with - * the _rcu list-traversal primitives, such as - * hlist_for_each_entry_rcu(), used to prevent memory-consistency - * problems on Alpha CPUs. Regardless of the type of CPU, the - * list-traversal primitive must be guarded by rcu_read_lock(). - */ -static inline void hlist_add_head_rcu(struct hlist_node *n, - struct hlist_head *h) -{ - struct hlist_node *first = h->first; - n->next = first; - n->pprev = &h->first; - smp_wmb(); - if (first) - first->pprev = &n->next; - h->first = n; -} - /* next must be != NULL */ static inline void hlist_add_before(struct hlist_node *n, struct hlist_node *next) @@ -847,63 +554,6 @@ static inline void hlist_add_after(struct hlist_node *n, next->next->pprev = &next->next; } -/** - * hlist_add_before_rcu - * @n: the new element to add to the hash list. - * @next: the existing element to add the new element before. - * - * Description: - * Adds the specified element to the specified hlist - * before the specified node while permitting racing traversals. - * - * The caller must take whatever precautions are necessary - * (such as holding appropriate locks) to avoid racing - * with another list-mutation primitive, such as hlist_add_head_rcu() - * or hlist_del_rcu(), running on this same list. - * However, it is perfectly legal to run concurrently with - * the _rcu list-traversal primitives, such as - * hlist_for_each_entry_rcu(), used to prevent memory-consistency - * problems on Alpha CPUs. - */ -static inline void hlist_add_before_rcu(struct hlist_node *n, - struct hlist_node *next) -{ - n->pprev = next->pprev; - n->next = next; - smp_wmb(); - next->pprev = &n->next; - *(n->pprev) = n; -} - -/** - * hlist_add_after_rcu - * @prev: the existing element to add the new element after. - * @n: the new element to add to the hash list. - * - * Description: - * Adds the specified element to the specified hlist - * after the specified node while permitting racing traversals. - * - * The caller must take whatever precautions are necessary - * (such as holding appropriate locks) to avoid racing - * with another list-mutation primitive, such as hlist_add_head_rcu() - * or hlist_del_rcu(), running on this same list. - * However, it is perfectly legal to run concurrently with - * the _rcu list-traversal primitives, such as - * hlist_for_each_entry_rcu(), used to prevent memory-consistency - * problems on Alpha CPUs. - */ -static inline void hlist_add_after_rcu(struct hlist_node *prev, - struct hlist_node *n) -{ - n->next = prev->next; - n->pprev = &prev->next; - smp_wmb(); - prev->next = n; - if (n->next) - n->next->pprev = &n->next; -} - #define hlist_entry(ptr, type, member) container_of(ptr,type,member) #define hlist_for_each(pos, head) \ @@ -964,21 +614,4 @@ static inline void hlist_add_after_rcu(struct hlist_node *prev, ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ pos = n) -/** - * hlist_for_each_entry_rcu - iterate over rcu list of given type - * @tpos: the type * to use as a loop cursor. - * @pos: the &struct hlist_node to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the hlist_node within the struct. - * - * This list-traversal primitive may safely run concurrently with - * the _rcu list-mutation primitives such as hlist_add_head_rcu() - * as long as the traversal is guarded by rcu_read_lock(). - */ -#define hlist_for_each_entry_rcu(tpos, pos, head, member) \ - for (pos = rcu_dereference((head)->first); \ - pos && ({ prefetch(pos->next); 1;}) && \ - ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ - pos = rcu_dereference(pos->next)) - #endif diff --git a/include/linux/magic.h b/include/linux/magic.h index 1fa0c2ce4dec..74e68e201166 100644 --- a/include/linux/magic.h +++ b/include/linux/magic.h @@ -42,4 +42,5 @@ #define FUTEXFS_SUPER_MAGIC 0xBAD1DEA #define INOTIFYFS_SUPER_MAGIC 0x2BAD1DEA +#define STACK_END_MAGIC 0x57AC6E9D #endif /* __LINUX_MAGIC_H__ */ diff --git a/include/linux/marker.h b/include/linux/marker.h index 430f6adf9762..1290653f9241 100644 --- a/include/linux/marker.h +++ b/include/linux/marker.h @@ -44,8 +44,8 @@ struct marker { */ char state; /* Marker state. */ char ptype; /* probe type : 0 : single, 1 : multi */ - void (*call)(const struct marker *mdata, /* Probe wrapper */ - void *call_private, const char *fmt, ...); + /* Probe wrapper */ + void (*call)(const struct marker *mdata, void *call_private, ...); struct marker_probe_closure single; struct marker_probe_closure *multi; } __attribute__((aligned(8))); @@ -58,8 +58,12 @@ struct marker { * Make sure the alignment of the structure in the __markers section will * not add unwanted padding between the beginning of the section and the * structure. Force alignment to the same alignment as the section start. + * + * The "generic" argument controls which marker enabling mechanism must be used. + * If generic is true, a variable read is used. + * If generic is false, immediate values are used. */ -#define __trace_mark(name, call_private, format, args...) \ +#define __trace_mark(generic, name, call_private, format, args...) \ do { \ static const char __mstrtab_##name[] \ __attribute__((section("__markers_strings"))) \ @@ -72,15 +76,14 @@ struct marker { __mark_check_format(format, ## args); \ if (unlikely(__mark_##name.state)) { \ (*__mark_##name.call) \ - (&__mark_##name, call_private, \ - format, ## args); \ + (&__mark_##name, call_private, ## args);\ } \ } while (0) extern void marker_update_probe_range(struct marker *begin, struct marker *end); #else /* !CONFIG_MARKERS */ -#define __trace_mark(name, call_private, format, args...) \ +#define __trace_mark(generic, name, call_private, format, args...) \ __mark_check_format(format, ## args) static inline void marker_update_probe_range(struct marker *begin, struct marker *end) @@ -88,15 +91,30 @@ static inline void marker_update_probe_range(struct marker *begin, #endif /* CONFIG_MARKERS */ /** - * trace_mark - Marker + * trace_mark - Marker using code patching * @name: marker name, not quoted. * @format: format string * @args...: variable argument list * - * Places a marker. + * Places a marker using optimized code patching technique (imv_read()) + * to be enabled when immediate values are present. */ #define trace_mark(name, format, args...) \ - __trace_mark(name, NULL, format, ## args) + __trace_mark(0, name, NULL, format, ## args) + +/** + * _trace_mark - Marker using variable read + * @name: marker name, not quoted. + * @format: format string + * @args...: variable argument list + * + * Places a marker using a standard memory read (_imv_read()) to be + * enabled. Should be used for markers in code paths where instruction + * modification based enabling is not welcome. (__init and __exit functions, + * lockdep, some traps, printk). + */ +#define _trace_mark(name, format, args...) \ + __trace_mark(1, name, NULL, format, ## args) /** * MARK_NOARGS - Format string for a marker with no argument. @@ -117,9 +135,9 @@ static inline void __printf(1, 2) ___mark_check_format(const char *fmt, ...) extern marker_probe_func __mark_empty_function; extern void marker_probe_cb(const struct marker *mdata, - void *call_private, const char *fmt, ...); + void *call_private, ...); extern void marker_probe_cb_noarg(const struct marker *mdata, - void *call_private, const char *fmt, ...); + void *call_private, ...); /* * Connect a probe to a marker. diff --git a/include/linux/math64.h b/include/linux/math64.h index c1a5f81501ff..c87f1528703a 100644 --- a/include/linux/math64.h +++ b/include/linux/math64.h @@ -81,4 +81,25 @@ static inline s64 div_s64(s64 dividend, s32 divisor) } #endif +u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder); + +static __always_inline u32 +__iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder) +{ + u32 ret = 0; + + while (dividend >= divisor) { + /* The following asm() prevents the compiler from + optimising this loop into a modulo operation. */ + asm("" : "+rm"(dividend)); + + dividend -= divisor; + ret++; + } + + *remainder = dividend; + + return ret; +} + #endif /* _LINUX_MATH64_H */ diff --git a/include/linux/memory_hotplug.h b/include/linux/memory_hotplug.h index 73e358612eaf..ea9f5ad9ec8e 100644 --- a/include/linux/memory_hotplug.h +++ b/include/linux/memory_hotplug.h @@ -77,14 +77,6 @@ extern int __add_pages(struct zone *zone, unsigned long start_pfn, extern int __remove_pages(struct zone *zone, unsigned long start_pfn, unsigned long nr_pages); -/* - * Walk through all memory which is registered as resource. - * arg is (start_pfn, nr_pages, private_arg_pointer) - */ -extern int walk_memory_resource(unsigned long start_pfn, - unsigned long nr_pages, void *arg, - int (*func)(unsigned long, unsigned long, void *)); - #ifdef CONFIG_NUMA extern int memory_add_physaddr_to_nid(u64 start); #else @@ -199,6 +191,14 @@ static inline void register_page_bootmem_info_node(struct pglist_data *pgdat) #endif /* ! CONFIG_MEMORY_HOTPLUG */ +/* + * Walk through all memory which is registered as resource. + * arg is (start_pfn, nr_pages, private_arg_pointer) + */ +extern int walk_memory_resource(unsigned long start_pfn, + unsigned long nr_pages, void *arg, + int (*func)(unsigned long, unsigned long, void *)); + extern int add_memory(int nid, u64 start, u64 size); extern int arch_add_memory(int nid, u64 start, u64 size); extern int remove_memory(u64 start, u64 size); diff --git a/include/linux/mm.h b/include/linux/mm.h index c31a9cd2a30e..77b5ec63a303 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -760,16 +760,17 @@ unsigned long unmap_vmas(struct mmu_gather **tlb, * (see walk_page_range for more details) */ struct mm_walk { - int (*pgd_entry)(pgd_t *, unsigned long, unsigned long, void *); - int (*pud_entry)(pud_t *, unsigned long, unsigned long, void *); - int (*pmd_entry)(pmd_t *, unsigned long, unsigned long, void *); - int (*pte_entry)(pte_t *, unsigned long, unsigned long, void *); - int (*pte_hole)(unsigned long, unsigned long, void *); + int (*pgd_entry)(pgd_t *, unsigned long, unsigned long, struct mm_walk *); + int (*pud_entry)(pud_t *, unsigned long, unsigned long, struct mm_walk *); + int (*pmd_entry)(pmd_t *, unsigned long, unsigned long, struct mm_walk *); + int (*pte_entry)(pte_t *, unsigned long, unsigned long, struct mm_walk *); + int (*pte_hole)(unsigned long, unsigned long, struct mm_walk *); + struct mm_struct *mm; + void *private; }; -int walk_page_range(const struct mm_struct *, unsigned long addr, - unsigned long end, const struct mm_walk *walk, - void *private); +int walk_page_range(unsigned long addr, unsigned long end, + struct mm_walk *walk); void free_pgd_range(struct mmu_gather **tlb, unsigned long addr, unsigned long end, unsigned long floor, unsigned long ceiling); void free_pgtables(struct mmu_gather **tlb, struct vm_area_struct *start_vma, @@ -997,8 +998,7 @@ extern void free_area_init_node(int nid, pg_data_t *pgdat, extern void free_area_init_nodes(unsigned long *max_zone_pfn); extern void add_active_range(unsigned int nid, unsigned long start_pfn, unsigned long end_pfn); -extern void shrink_active_range(unsigned int nid, unsigned long old_end_pfn, - unsigned long new_end_pfn); +extern void shrink_active_range(unsigned int nid, unsigned long new_end_pfn); extern void push_node_boundaries(unsigned int nid, unsigned long start_pfn, unsigned long end_pfn); extern void remove_all_active_ranges(void); @@ -1023,6 +1023,7 @@ extern void mem_init(void); extern void show_mem(void); extern void si_meminfo(struct sysinfo * val); extern void si_meminfo_node(struct sysinfo *val, int nid); +extern int after_bootmem; #ifdef CONFIG_NUMA extern void setup_per_cpu_pageset(void); diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 0d508ac17d64..85dda43eb904 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -94,6 +94,7 @@ struct mmc_card { #define MMC_STATE_READONLY (1<<1) /* card is read-only */ #define MMC_STATE_HIGHSPEED (1<<2) /* card is in high speed mode */ #define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */ +#define MMC_STATE_LOCKED (1<<4) /* card is currently locked */ u32 raw_cid[4]; /* raw card CID */ u32 raw_csd[4]; /* raw card CSD */ @@ -121,11 +122,13 @@ struct mmc_card { #define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) #define mmc_card_highspeed(c) ((c)->state & MMC_STATE_HIGHSPEED) #define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR) +#define mmc_card_locked(c) ((c)->state & MMC_STATE_LOCKED) #define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) #define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED) #define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) +#define mmc_card_set_locked(c) ((c)->state |= MMC_STATE_LOCKED) #define mmc_card_name(c) ((c)->cid.prod_name) #define mmc_card_id(c) ((c)->dev.bus_id) diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 7ab962fa1d73..ef3b773cec91 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -51,8 +51,18 @@ struct mmc_ios { struct mmc_host_ops { void (*request)(struct mmc_host *host, struct mmc_request *req); + /* + * Avoid calling these three functions too often or in a "fast path", + * since underlaying controller might implement them in an expensive + * and/or slow way. + * + * .get_ro and .get_cd should return >= 0 for their logical values, + * or negative errno value in case of error. + */ void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); int (*get_ro)(struct mmc_host *host); + int (*get_cd)(struct mmc_host *host); + void (*enable_sdio_irq)(struct mmc_host *host, int enable); }; @@ -94,6 +104,7 @@ struct mmc_host { #define MMC_CAP_SD_HIGHSPEED (1 << 3) /* Can do SD high-speed timing */ #define MMC_CAP_SDIO_IRQ (1 << 4) /* Can signal pending SDIO IRQs */ #define MMC_CAP_SPI (1 << 5) /* Talks only SPI protocols */ +#define MMC_CAP_NEEDS_POLL (1 << 6) /* Needs polling for card-detection */ /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index 4236fbf0b6fb..a9de8e988798 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -16,7 +16,6 @@ * Based strongly on code by: * * Author: Yong-iL Joh <tolkien@mizi.com> - * Date : $Date: 2002/06/18 12:37:30 $ * * Author: Andrew Christian * 15 May 2002 @@ -280,5 +279,13 @@ struct _mmc_csd { #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ +/* + * MMC_LOCK_UNLOCK modes + */ +#define MMC_LOCK_MODE_ERASE (1<<3) +#define MMC_LOCK_MODE_UNLOCK (1<<2) +#define MMC_LOCK_MODE_CLR_PWD (1<<1) +#define MMC_LOCK_MODE_SET_PWD (1<<0) + #endif /* MMC_MMC_PROTOCOL_H */ diff --git a/include/linux/mmiotrace.h b/include/linux/mmiotrace.h new file mode 100644 index 000000000000..61d19e1b7a0b --- /dev/null +++ b/include/linux/mmiotrace.h @@ -0,0 +1,85 @@ +#ifndef MMIOTRACE_H +#define MMIOTRACE_H + +#include <linux/types.h> +#include <linux/list.h> + +struct kmmio_probe; +struct pt_regs; + +typedef void (*kmmio_pre_handler_t)(struct kmmio_probe *, + struct pt_regs *, unsigned long addr); +typedef void (*kmmio_post_handler_t)(struct kmmio_probe *, + unsigned long condition, struct pt_regs *); + +struct kmmio_probe { + struct list_head list; /* kmmio internal list */ + unsigned long addr; /* start location of the probe point */ + unsigned long len; /* length of the probe region */ + kmmio_pre_handler_t pre_handler; /* Called before addr is executed. */ + kmmio_post_handler_t post_handler; /* Called after addr is executed */ + void *private; +}; + +/* kmmio is active by some kmmio_probes? */ +static inline int is_kmmio_active(void) +{ + extern unsigned int kmmio_count; + return kmmio_count; +} + +extern int register_kmmio_probe(struct kmmio_probe *p); +extern void unregister_kmmio_probe(struct kmmio_probe *p); + +/* Called from page fault handler. */ +extern int kmmio_handler(struct pt_regs *regs, unsigned long addr); + +/* Called from ioremap.c */ +#ifdef CONFIG_MMIOTRACE +extern void mmiotrace_ioremap(resource_size_t offset, unsigned long size, + void __iomem *addr); +extern void mmiotrace_iounmap(volatile void __iomem *addr); +#else +static inline void mmiotrace_ioremap(resource_size_t offset, + unsigned long size, void __iomem *addr) +{ +} + +static inline void mmiotrace_iounmap(volatile void __iomem *addr) +{ +} +#endif /* CONFIG_MMIOTRACE_HOOKS */ + +enum mm_io_opcode { + MMIO_READ = 0x1, /* struct mmiotrace_rw */ + MMIO_WRITE = 0x2, /* struct mmiotrace_rw */ + MMIO_PROBE = 0x3, /* struct mmiotrace_map */ + MMIO_UNPROBE = 0x4, /* struct mmiotrace_map */ + MMIO_MARKER = 0x5, /* raw char data */ + MMIO_UNKNOWN_OP = 0x6, /* struct mmiotrace_rw */ +}; + +struct mmiotrace_rw { + resource_size_t phys; /* PCI address of register */ + unsigned long value; + unsigned long pc; /* optional program counter */ + int map_id; + unsigned char opcode; /* one of MMIO_{READ,WRITE,UNKNOWN_OP} */ + unsigned char width; /* size of register access in bytes */ +}; + +struct mmiotrace_map { + resource_size_t phys; /* base address in PCI space */ + unsigned long virt; /* base virtual address */ + unsigned long len; /* mapping size */ + int map_id; + unsigned char opcode; /* MMIO_PROBE or MMIO_UNPROBE */ +}; + +/* in kernel/trace/trace_mmiotrace.c */ +extern void enable_mmiotrace(void); +extern void disable_mmiotrace(void); +extern void mmio_trace_rw(struct mmiotrace_rw *rw); +extern void mmio_trace_mapping(struct mmiotrace_map *map); + +#endif /* MMIOTRACE_H */ diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 69b2342d5ebb..1fd03e732e07 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -159,6 +159,15 @@ struct ap_device_id { #define AP_DEVICE_ID_MATCH_DEVICE_TYPE 0x01 +/* s390 css bus devices (subchannels) */ +struct css_device_id { + __u8 type; /* subchannel type */ + __u8 pad1; + __u16 pad2; + __u32 pad3; + kernel_ulong_t driver_data; +}; + #define ACPI_ID_LEN 16 /* only 9 bytes needed here, 16 bytes are used */ /* to workaround crosscompile issues */ diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h index b03b27457413..81cd36b735b0 100644 --- a/include/linux/msdos_fs.h +++ b/include/linux/msdos_fs.h @@ -57,12 +57,6 @@ #define MSDOS_DOT ". " /* ".", padded to MSDOS_NAME chars */ #define MSDOS_DOTDOT ".. " /* "..", padded to MSDOS_NAME chars */ -/* media of boot sector */ -static inline int fat_valid_media(u8 media) -{ - return 0xf8 <= media || media == 0xf0; -} - #define FAT_FIRST_ENT(s, x) ((MSDOS_SB(s)->fat_bits == 32 ? 0x0FFFFF00 : \ MSDOS_SB(s)->fat_bits == 16 ? 0xFF00 : 0xF00) | (x)) @@ -334,6 +328,12 @@ static inline void fatwchar_to16(__u8 *dst, const wchar_t *src, size_t len) #endif } +/* media of boot sector */ +static inline int fat_valid_media(u8 media) +{ + return 0xf8 <= media || media == 0xf0; +} + /* fat/cache.c */ extern void fat_cache_inval_inode(struct inode *inode); extern int fat_get_cluster(struct inode *inode, int cluster, diff --git a/include/linux/msg.h b/include/linux/msg.h index 6f3b8e79a991..56abf1558fdd 100644 --- a/include/linux/msg.h +++ b/include/linux/msg.h @@ -64,11 +64,11 @@ struct msginfo { #define MSGMNB 16384 /* <= INT_MAX */ /* default max size of a message queue */ /* unused */ -#define MSGPOOL (MSGMNI * MSGMNB) /* size in bytes of message pool */ +#define MSGPOOL (MSGMNI * MSGMNB / 1024) /* size in kbytes of message pool */ #define MSGTQL MSGMNB /* number of system message headers */ #define MSGMAP MSGMNB /* number of entries in message map */ #define MSGSSZ 16 /* message segment size */ -#define __MSGSEG (MSGPOOL / MSGSSZ) /* max no. of segments */ +#define __MSGSEG ((MSGPOOL * 1024) / MSGSSZ) /* max no. of segments */ #define MSGSEG (__MSGSEG <= 0xffff ? __MSGSEG : 0xffff) #ifdef __KERNEL__ diff --git a/include/linux/mtd/blktrans.h b/include/linux/mtd/blktrans.h index 9a6e2f953cba..310e61606415 100644 --- a/include/linux/mtd/blktrans.h +++ b/include/linux/mtd/blktrans.h @@ -1,6 +1,4 @@ /* - * $Id: blktrans.h,v 1.6 2005/11/07 11:14:54 gleixner Exp $ - * * (C) 2003 David Woodhouse <dwmw2@infradead.org> * * Interface to Linux block layer for MTD 'translation layers'. diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index b0ddf4b25862..d6fb115f5a07 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -1,7 +1,6 @@ /* Common Flash Interface structures * See http://support.intel.com/design/flash/technote/index.htm - * $Id: cfi.h,v 1.57 2005/11/15 23:28:17 tpoynor Exp $ */ #ifndef __MTD_CFI_H__ diff --git a/include/linux/mtd/cfi_endian.h b/include/linux/mtd/cfi_endian.h index 25724f7d3867..d802f7736be3 100644 --- a/include/linux/mtd/cfi_endian.h +++ b/include/linux/mtd/cfi_endian.h @@ -1,8 +1,3 @@ -/* - * $Id: cfi_endian.h,v 1.11 2002/01/30 23:20:48 awozniak Exp $ - * - */ - #include <asm/byteorder.h> #ifndef CONFIG_MTD_CFI_ADV_OPTIONS diff --git a/include/linux/mtd/concat.h b/include/linux/mtd/concat.h index ed8dc6755219..c02f3d264ecf 100644 --- a/include/linux/mtd/concat.h +++ b/include/linux/mtd/concat.h @@ -4,8 +4,6 @@ * (C) 2002 Robert Kaiser <rkaiser@sysgo.de> * * This code is GPL - * - * $Id: concat.h,v 1.1 2002/03/08 16:34:36 rkaiser Exp $ */ #ifndef MTD_CONCAT_H diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h index 9addd073bf15..0a6d516ab71d 100644 --- a/include/linux/mtd/doc2000.h +++ b/include/linux/mtd/doc2000.h @@ -6,8 +6,6 @@ * Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com> * Copyright (C) 2002-2003 SnapGear Inc * - * $Id: doc2000.h,v 1.25 2005/11/07 11:14:54 gleixner Exp $ - * * Released under GPL */ diff --git a/include/linux/mtd/flashchip.h b/include/linux/mtd/flashchip.h index 39e7d2a1be9a..08dd131301c1 100644 --- a/include/linux/mtd/flashchip.h +++ b/include/linux/mtd/flashchip.h @@ -5,9 +5,6 @@ * Contains information about the location and state of a given flash device * * (C) 2000 Red Hat. GPLd. - * - * $Id: flashchip.h,v 1.18 2005/11/07 11:14:54 gleixner Exp $ - * */ #ifndef __MTD_FLASHCHIP_H__ diff --git a/include/linux/mtd/ftl.h b/include/linux/mtd/ftl.h index d99609113307..0be442f881dd 100644 --- a/include/linux/mtd/ftl.h +++ b/include/linux/mtd/ftl.h @@ -1,6 +1,4 @@ /* - * $Id: ftl.h,v 1.7 2005/11/07 11:14:54 gleixner Exp $ - * * Derived from (and probably identical to): * ftl.h 1.7 1999/10/25 20:23:17 * diff --git a/include/linux/mtd/gen_probe.h b/include/linux/mtd/gen_probe.h index 256e7342ed1e..df362ddf2949 100644 --- a/include/linux/mtd/gen_probe.h +++ b/include/linux/mtd/gen_probe.h @@ -1,7 +1,6 @@ /* * (C) 2001, 2001 Red Hat, Inc. * GPL'd - * $Id: gen_probe.h,v 1.4 2005/11/07 11:14:54 gleixner Exp $ */ #ifndef __LINUX_MTD_GEN_PROBE_H__ diff --git a/include/linux/mtd/inftl.h b/include/linux/mtd/inftl.h index 85fd041d44ad..64ee53ce95a9 100644 --- a/include/linux/mtd/inftl.h +++ b/include/linux/mtd/inftl.h @@ -2,8 +2,6 @@ * inftl.h -- defines to support the Inverse NAND Flash Translation Layer * * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) - * - * $Id: inftl.h,v 1.7 2005/06/13 13:08:45 sean Exp $ */ #ifndef __MTD_INFTL_H__ @@ -52,8 +50,6 @@ struct INFTLrecord { int INFTL_mount(struct INFTLrecord *s); int INFTL_formatblock(struct INFTLrecord *s, int block); -extern char inftlmountrev[]; - void INFTL_dumptables(struct INFTLrecord *s); void INFTL_dumpVUchains(struct INFTLrecord *s); diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h index a9fae032ba81..85e3939cf487 100644 --- a/include/linux/mtd/map.h +++ b/include/linux/mtd/map.h @@ -1,6 +1,5 @@ /* Overhauled routines for dealing with different mmap regions of flash */ -/* $Id: map.h,v 1.54 2005/11/07 11:14:54 gleixner Exp $ */ #ifndef __LINUX_MTD_MAP_H__ #define __LINUX_MTD_MAP_H__ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 245f9098e171..31ed234b2a74 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -1,6 +1,4 @@ /* - * $Id: mtd.h,v 1.61 2005/11/07 11:14:54 gleixner Exp $ - * * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al. * * Released under GPL diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index c42bc7f533a5..863e22a0ddb5 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -1,12 +1,10 @@ /* * linux/include/linux/mtd/nand.h * - * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> + * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> * Steven J. Hill <sjhill@realitydiluted.com> * Thomas Gleixner <tglx@linutronix.de> * - * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $ - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h index 12c5bc342ead..090da505425d 100644 --- a/include/linux/mtd/nand_ecc.h +++ b/include/linux/mtd/nand_ecc.h @@ -3,8 +3,6 @@ * * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) * - * $Id: nand_ecc.h,v 1.4 2004/06/17 02:35:02 dbrown Exp $ - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h index 001eec50cac6..dcaf611ed748 100644 --- a/include/linux/mtd/nftl.h +++ b/include/linux/mtd/nftl.h @@ -1,6 +1,4 @@ /* - * $Id: nftl.h,v 1.16 2004/06/30 14:49:00 dbrown Exp $ - * * (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> */ diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index 7c37d7e55abc..5014f7a9f5df 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -4,8 +4,6 @@ * (C) 2000 Nicolas Pitre <nico@cam.org> * * This code is GPL - * - * $Id: partitions.h,v 1.17 2005/11/07 11:14:55 gleixner Exp $ */ #ifndef MTD_PARTITIONS_H diff --git a/include/linux/mtd/physmap.h b/include/linux/mtd/physmap.h index 0dc07d5f3354..c8e63a5ee72e 100644 --- a/include/linux/mtd/physmap.h +++ b/include/linux/mtd/physmap.h @@ -2,8 +2,6 @@ * For boards with physically mapped flash and using * drivers/mtd/maps/physmap.c mapping driver. * - * $Id: physmap.h,v 1.4 2005/11/07 11:14:55 gleixner Exp $ - * * Copyright (C) 2003 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * diff --git a/include/linux/mtd/plat-ram.h b/include/linux/mtd/plat-ram.h index 0e37ad07bce2..e07890aff1cf 100644 --- a/include/linux/mtd/plat-ram.h +++ b/include/linux/mtd/plat-ram.h @@ -6,8 +6,6 @@ * * Generic platform device based RAM map * - * $Id: plat-ram.h,v 1.2 2005/01/24 00:37:40 bjd Exp $ - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. diff --git a/include/linux/mtd/pmc551.h b/include/linux/mtd/pmc551.h index 5cc070c24d88..27ad40aed19f 100644 --- a/include/linux/mtd/pmc551.h +++ b/include/linux/mtd/pmc551.h @@ -1,6 +1,4 @@ /* - * $Id: pmc551.h,v 1.6 2005/11/07 11:14:55 gleixner Exp $ - * * PMC551 PCI Mezzanine Ram Device * * Author: @@ -17,7 +15,7 @@ #include <linux/mtd/mtd.h> -#define PMC551_VERSION "$Id: pmc551.h,v 1.6 2005/11/07 11:14:55 gleixner Exp $\n"\ +#define PMC551_VERSION \ "Ramix PMC551 PCI Mezzanine Ram Driver. (C) 1999,2000 Nortel Networks.\n" /* diff --git a/include/linux/mtd/xip.h b/include/linux/mtd/xip.h index e9d40bdde48c..36efcba15ecd 100644 --- a/include/linux/mtd/xip.h +++ b/include/linux/mtd/xip.h @@ -11,8 +11,6 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * $Id: xip.h,v 1.5 2005/11/07 11:14:55 gleixner Exp $ */ #ifndef __LINUX_MTD_XIP_H__ diff --git a/include/linux/mutex.h b/include/linux/mutex.h index bc6da10ceee0..c1f5b3f9fe2d 100644 --- a/include/linux/mutex.h +++ b/include/linux/mutex.h @@ -141,10 +141,6 @@ extern int __must_check mutex_lock_killable(struct mutex *lock); # define mutex_lock_killable_nested(lock, subclass) mutex_lock_killable(lock) #endif -/* - * NOTE: mutex_trylock() follows the spin_trylock() convention, - * not the down_trylock() convention! - */ extern int mutex_trylock(struct mutex *lock); extern void mutex_unlock(struct mutex *lock); diff --git a/include/linux/netfilter/nfnetlink_conntrack.h b/include/linux/netfilter/nfnetlink_conntrack.h index 0a383ac083cb..759bc043dc65 100644 --- a/include/linux/netfilter/nfnetlink_conntrack.h +++ b/include/linux/netfilter/nfnetlink_conntrack.h @@ -81,6 +81,7 @@ enum ctattr_protoinfo { CTA_PROTOINFO_UNSPEC, CTA_PROTOINFO_TCP, CTA_PROTOINFO_DCCP, + CTA_PROTOINFO_SCTP, __CTA_PROTOINFO_MAX }; #define CTA_PROTOINFO_MAX (__CTA_PROTOINFO_MAX - 1) @@ -103,6 +104,15 @@ enum ctattr_protoinfo_dccp { }; #define CTA_PROTOINFO_DCCP_MAX (__CTA_PROTOINFO_DCCP_MAX - 1) +enum ctattr_protoinfo_sctp { + CTA_PROTOINFO_SCTP_UNSPEC, + CTA_PROTOINFO_SCTP_STATE, + CTA_PROTOINFO_SCTP_VTAG_ORIGINAL, + CTA_PROTOINFO_SCTP_VTAG_REPLY, + __CTA_PROTOINFO_SCTP_MAX +}; +#define CTA_PROTOINFO_SCTP_MAX (__CTA_PROTOINFO_SCTP_MAX - 1) + enum ctattr_counters { CTA_COUNTERS_UNSPEC, CTA_COUNTERS_PACKETS, /* old 64bit counters */ diff --git a/include/linux/netfilter_bridge/ebt_ip6.h b/include/linux/netfilter_bridge/ebt_ip6.h new file mode 100644 index 000000000000..2273c3ae33ca --- /dev/null +++ b/include/linux/netfilter_bridge/ebt_ip6.h @@ -0,0 +1,40 @@ +/* + * ebt_ip6 + * + * Authors: + * Kuo-Lang Tseng <kuo-lang.tseng@intel.com> + * Manohar Castelino <manohar.r.castelino@intel.com> + * + * Jan 11, 2008 + * + */ + +#ifndef __LINUX_BRIDGE_EBT_IP6_H +#define __LINUX_BRIDGE_EBT_IP6_H + +#define EBT_IP6_SOURCE 0x01 +#define EBT_IP6_DEST 0x02 +#define EBT_IP6_TCLASS 0x04 +#define EBT_IP6_PROTO 0x08 +#define EBT_IP6_SPORT 0x10 +#define EBT_IP6_DPORT 0x20 +#define EBT_IP6_MASK (EBT_IP6_SOURCE | EBT_IP6_DEST | EBT_IP6_TCLASS |\ + EBT_IP6_PROTO | EBT_IP6_SPORT | EBT_IP6_DPORT) +#define EBT_IP6_MATCH "ip6" + +/* the same values are used for the invflags */ +struct ebt_ip6_info +{ + struct in6_addr saddr; + struct in6_addr daddr; + struct in6_addr smsk; + struct in6_addr dmsk; + uint8_t tclass; + uint8_t protocol; + uint8_t bitmask; + uint8_t invflags; + uint16_t sport[2]; + uint16_t dport[2]; +}; + +#endif diff --git a/include/linux/netfilter_bridge/ebt_log.h b/include/linux/netfilter_bridge/ebt_log.h index 96e231ae7554..b76e653157e5 100644 --- a/include/linux/netfilter_bridge/ebt_log.h +++ b/include/linux/netfilter_bridge/ebt_log.h @@ -4,7 +4,8 @@ #define EBT_LOG_IP 0x01 /* if the frame is made by ip, log the ip information */ #define EBT_LOG_ARP 0x02 #define EBT_LOG_NFLOG 0x04 -#define EBT_LOG_MASK (EBT_LOG_IP | EBT_LOG_ARP) +#define EBT_LOG_IP6 0x08 +#define EBT_LOG_MASK (EBT_LOG_IP | EBT_LOG_ARP | EBT_LOG_IP6) #define EBT_LOG_PREFIX_SIZE 30 #define EBT_LOG_WATCHER "log" diff --git a/include/linux/netfilter_ipv4.h b/include/linux/netfilter_ipv4.h index 650318b0c405..29c7727ff0e8 100644 --- a/include/linux/netfilter_ipv4.h +++ b/include/linux/netfilter_ipv4.h @@ -60,6 +60,7 @@ enum nf_ip_hook_priorities { NF_IP_PRI_MANGLE = -150, NF_IP_PRI_NAT_DST = -100, NF_IP_PRI_FILTER = 0, + NF_IP_PRI_SECURITY = 50, NF_IP_PRI_NAT_SRC = 100, NF_IP_PRI_SELINUX_LAST = 225, NF_IP_PRI_CONNTRACK_CONFIRM = INT_MAX, diff --git a/include/linux/netfilter_ipv6.h b/include/linux/netfilter_ipv6.h index 3475a65dae9b..fd50988b83ec 100644 --- a/include/linux/netfilter_ipv6.h +++ b/include/linux/netfilter_ipv6.h @@ -64,6 +64,7 @@ enum nf_ip6_hook_priorities { NF_IP6_PRI_MANGLE = -150, NF_IP6_PRI_NAT_DST = -100, NF_IP6_PRI_FILTER = 0, + NF_IP6_PRI_SECURITY = 50, NF_IP6_PRI_NAT_SRC = 100, NF_IP6_PRI_SELINUX_LAST = 225, NF_IP6_PRI_LAST = INT_MAX, diff --git a/include/linux/netlink.h b/include/linux/netlink.h index bec1062a25a1..9ff1b54908f3 100644 --- a/include/linux/netlink.h +++ b/include/linux/netlink.h @@ -193,7 +193,7 @@ extern int netlink_unregister_notifier(struct notifier_block *nb); /* finegrained unicast helpers: */ struct sock *netlink_getsockbyfilp(struct file *filp); -int netlink_attachskb(struct sock *sk, struct sk_buff *skb, int nonblock, +int netlink_attachskb(struct sock *sk, struct sk_buff *skb, long *timeo, struct sock *ssk); void netlink_detachskb(struct sock *sk, struct sk_buff *skb); int netlink_sendskb(struct sock *sk, struct sk_buff *skb); diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h index 8726491de154..ea0366769484 100644 --- a/include/linux/nfs4.h +++ b/include/linux/nfs4.h @@ -65,9 +65,6 @@ #define NFS4_ACE_SUCCESSFUL_ACCESS_ACE_FLAG 0x00000010 #define NFS4_ACE_FAILED_ACCESS_ACE_FLAG 0x00000020 #define NFS4_ACE_IDENTIFIER_GROUP 0x00000040 -#define NFS4_ACE_OWNER 0x00000080 -#define NFS4_ACE_GROUP 0x00000100 -#define NFS4_ACE_EVERYONE 0x00000200 #define NFS4_ACE_READ_DATA 0x00000001 #define NFS4_ACE_LIST_DIRECTORY 0x00000001 diff --git a/include/linux/nfsd/nfsd.h b/include/linux/nfsd/nfsd.h index 41d30c9c9de6..88d85b964429 100644 --- a/include/linux/nfsd/nfsd.h +++ b/include/linux/nfsd/nfsd.h @@ -54,6 +54,7 @@ typedef int (*nfsd_dirop_t)(struct inode *, struct dentry *, int, int); extern struct svc_program nfsd_program; extern struct svc_version nfsd_version2, nfsd_version3, nfsd_version4; +extern struct mutex nfsd_mutex; extern struct svc_serv *nfsd_serv; extern struct seq_operations nfs_exports_op; diff --git a/include/linux/nfsd/state.h b/include/linux/nfsd/state.h index db348f749376..d0fe2e378452 100644 --- a/include/linux/nfsd/state.h +++ b/include/linux/nfsd/state.h @@ -98,8 +98,6 @@ struct nfs4_callback { u32 cb_ident; /* RPC client info */ atomic_t cb_set; /* successful CB_NULL call */ - struct rpc_program cb_program; - struct rpc_stat cb_stat; struct rpc_clnt * cb_client; }; diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h index ea6517e58b04..aa8411e2a160 100644 --- a/include/linux/nl80211.h +++ b/include/linux/nl80211.h @@ -122,13 +122,13 @@ enum nl80211_commands { NL80211_CMD_NEW_STATION, NL80211_CMD_DEL_STATION, - /* add commands here */ - NL80211_CMD_GET_MPATH, NL80211_CMD_SET_MPATH, NL80211_CMD_NEW_MPATH, NL80211_CMD_DEL_MPATH, + /* add commands here */ + /* used to define NL80211_CMD_MAX below */ __NL80211_CMD_AFTER_LAST, NL80211_CMD_MAX = __NL80211_CMD_AFTER_LAST - 1 @@ -230,13 +230,13 @@ enum nl80211_attrs { NL80211_ATTR_MNTR_FLAGS, - /* add attributes here, update the policy in nl80211.c */ - NL80211_ATTR_MESH_ID, NL80211_ATTR_STA_PLINK_ACTION, NL80211_ATTR_MPATH_NEXT_HOP, NL80211_ATTR_MPATH_INFO, + /* add attributes here, update the policy in nl80211.c */ + __NL80211_ATTR_AFTER_LAST, NL80211_ATTR_MAX = __NL80211_ATTR_AFTER_LAST - 1 }; diff --git a/include/linux/of_device.h b/include/linux/of_device.h index afe338217d91..d3a74e00a3e1 100644 --- a/include/linux/of_device.h +++ b/include/linux/of_device.h @@ -24,4 +24,7 @@ static inline void of_device_free(struct of_device *dev) of_release_dev(&dev->dev); } +extern ssize_t of_device_get_modalias(struct of_device *ofdev, + char *str, ssize_t len); + #endif /* _LINUX_OF_DEVICE_H */ diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h index 590cff32415d..0d2a4e7012aa 100644 --- a/include/linux/page-flags.h +++ b/include/linux/page-flags.h @@ -157,6 +157,7 @@ PAGEFLAG(Active, active) __CLEARPAGEFLAG(Active, active) __PAGEFLAG(Slab, slab) PAGEFLAG(Checked, owner_priv_1) /* Used by some filesystems */ PAGEFLAG(Pinned, owner_priv_1) TESTSCFLAG(Pinned, owner_priv_1) /* Xen */ +PAGEFLAG(SavePinned, dirty); /* Xen */ PAGEFLAG(Reserved, reserved) __CLEARPAGEFLAG(Reserved, reserved) PAGEFLAG(Private, private) __CLEARPAGEFLAG(Private, private) __SETPAGEFLAG(Private, private) @@ -306,5 +307,29 @@ static inline void __ClearPageTail(struct page *page) } #endif /* !PAGEFLAGS_EXTENDED */ + +#define PAGE_FLAGS (1 << PG_lru | 1 << PG_private | 1 << PG_locked | \ + 1 << PG_buddy | 1 << PG_writeback | \ + 1 << PG_slab | 1 << PG_swapcache | 1 << PG_active) + +/* + * Flags checked in bad_page(). Pages on the free list should not have + * these flags set. It they are, there is a problem. + */ +#define PAGE_FLAGS_CLEAR_WHEN_BAD (PAGE_FLAGS | 1 << PG_reclaim | 1 << PG_dirty) + +/* + * Flags checked when a page is freed. Pages being freed should not have + * these flags set. It they are, there is a problem. + */ +#define PAGE_FLAGS_CHECK_AT_FREE (PAGE_FLAGS | 1 << PG_reserved) + +/* + * Flags checked when a page is prepped for return by the page allocator. + * Pages being prepped should not have these flags set. It they are, there + * is a problem. + */ +#define PAGE_FLAGS_CHECK_AT_PREP (PAGE_FLAGS | 1 << PG_reserved | 1 << PG_dirty) + #endif /* !__GENERATING_BOUNDS_H */ #endif /* PAGE_FLAGS_H */ diff --git a/include/linux/pageblock-flags.h b/include/linux/pageblock-flags.h index e875905f7b12..e8c06122be36 100644 --- a/include/linux/pageblock-flags.h +++ b/include/linux/pageblock-flags.h @@ -25,13 +25,11 @@ #include <linux/types.h> -/* Macro to aid the definition of ranges of bits */ -#define PB_range(name, required_bits) \ - name, name ## _end = (name + required_bits) - 1 - /* Bit indices that affect a whole block of pages */ enum pageblock_bits { - PB_range(PB_migrate, 3), /* 3 bits required for migrate types */ + PB_migrate, + PB_migrate_end = PB_migrate + 3 - 1, + /* 3 bits required for migrate types */ NR_PAGEBLOCK_BITS }; diff --git a/include/linux/pci.h b/include/linux/pci.h index 509159bcd4e7..f9d070b62d43 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -17,8 +17,7 @@ #ifndef LINUX_PCI_H #define LINUX_PCI_H -/* Include the pci register defines */ -#include <linux/pci_regs.h> +#include <linux/pci_regs.h> /* The pci register defines */ /* * The PCI interface treats multi-function devices as independent @@ -49,12 +48,22 @@ #include <linux/list.h> #include <linux/compiler.h> #include <linux/errno.h> +#include <linux/kobject.h> #include <asm/atomic.h> #include <linux/device.h> /* Include the ID list */ #include <linux/pci_ids.h> +/* pci_slot represents a physical slot */ +struct pci_slot { + struct pci_bus *bus; /* The bus this slot is on */ + struct list_head list; /* node in list of slots on this bus */ + struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ + unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ + struct kobject kobj; +}; + /* File state for mmap()s on /proc/bus/pci/X/Y */ enum pci_mmap_state { pci_mmap_io, @@ -142,6 +151,7 @@ struct pci_dev { void *sysdata; /* hook for sys-specific extension */ struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ + struct pci_slot *slot; /* Physical slot this device is in */ unsigned int devfn; /* encoded device & function index */ unsigned short vendor; @@ -206,6 +216,7 @@ struct pci_dev { struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ int rom_attr_enabled; /* has display of the rom attribute been enabled? */ struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ + struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ #ifdef CONFIG_PCI_MSI struct list_head msi_list; #endif @@ -266,6 +277,7 @@ struct pci_bus { struct list_head children; /* list of child buses */ struct list_head devices; /* list of devices on this bus */ struct pci_dev *self; /* bridge device as seen by parent */ + struct list_head slots; /* list of slots on this bus */ struct resource *resource[PCI_BUS_NUM_RESOURCES]; /* address space routed to this bus */ @@ -389,7 +401,7 @@ struct pci_driver { int (*resume_early) (struct pci_dev *dev); int (*resume) (struct pci_dev *dev); /* Device woken up */ void (*shutdown) (struct pci_dev *dev); - + struct pm_ext_ops *pm; struct pci_error_handlers *err_handler; struct device_driver driver; struct pci_dynids dynids; @@ -488,6 +500,10 @@ struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata); struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr); +struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, + const char *name); +void pci_destroy_slot(struct pci_slot *slot); +void pci_update_slot_number(struct pci_slot *slot, int slot_nr); int pci_scan_slot(struct pci_bus *bus, int devfn); struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); @@ -976,9 +992,9 @@ static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) /* If you want to know what to call your pci_dev, ask this function. * Again, it's a wrapper around the generic device. */ -static inline char *pci_name(struct pci_dev *pdev) +static inline const char *pci_name(struct pci_dev *pdev) { - return pdev->dev.bus_id; + return dev_name(&pdev->dev); } @@ -1013,7 +1029,9 @@ enum pci_fixup_pass { pci_fixup_header, /* After reading configuration header */ pci_fixup_final, /* Final phase of device fixups */ pci_fixup_enable, /* pci_enable_device() time */ - pci_fixup_resume, /* pci_enable_device() time */ + pci_fixup_resume, /* pci_device_resume() */ + pci_fixup_suspend, /* pci_device_suspend */ + pci_fixup_resume_early, /* pci_device_resume_early() */ }; /* Anonymous variables would be nice... */ @@ -1035,6 +1053,12 @@ enum pci_fixup_pass { #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ resume##vendor##device##hook, vendor, device, hook) +#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ + DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ + resume_early##vendor##device##hook, vendor, device, hook) +#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ + DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ + suspend##vendor##device##hook, vendor, device, hook) void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); @@ -1059,7 +1083,10 @@ extern int pci_pci_problems; extern unsigned long pci_cardbus_io_size; extern unsigned long pci_cardbus_mem_size; -extern int pcibios_add_platform_entries(struct pci_dev *dev); +int pcibios_add_platform_entries(struct pci_dev *dev); +void pcibios_disable_device(struct pci_dev *dev); +int pcibios_set_pcie_reset_state(struct pci_dev *dev, + enum pcie_reset_state state); #ifdef CONFIG_PCI_MMCONFIG extern void __init pci_mmcfg_early_init(void); diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index 8f67e8f2a3cc..a08cd06b541a 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -95,9 +95,6 @@ struct hotplug_slot_attribute { * @get_adapter_status: Called to get see if an adapter is present in the slot or not. * If this field is NULL, the value passed in the struct hotplug_slot_info * will be used when this value is requested by a user. - * @get_address: Called to get pci address of a slot. - * If this field is NULL, the value passed in the struct hotplug_slot_info - * will be used when this value is requested by a user. * @get_max_bus_speed: Called to get the max bus speed for a slot. * If this field is NULL, the value passed in the struct hotplug_slot_info * will be used when this value is requested by a user. @@ -120,7 +117,6 @@ struct hotplug_slot_ops { int (*get_attention_status) (struct hotplug_slot *slot, u8 *value); int (*get_latch_status) (struct hotplug_slot *slot, u8 *value); int (*get_adapter_status) (struct hotplug_slot *slot, u8 *value); - int (*get_address) (struct hotplug_slot *slot, u32 *value); int (*get_max_bus_speed) (struct hotplug_slot *slot, enum pci_bus_speed *value); int (*get_cur_bus_speed) (struct hotplug_slot *slot, enum pci_bus_speed *value); }; @@ -140,7 +136,6 @@ struct hotplug_slot_info { u8 attention_status; u8 latch_status; u8 adapter_status; - u32 address; enum pci_bus_speed max_bus_speed; enum pci_bus_speed cur_bus_speed; }; @@ -166,15 +161,14 @@ struct hotplug_slot { /* Variables below this are for use only by the hotplug pci core. */ struct list_head slot_list; - struct kobject kobj; + struct pci_slot *pci_slot; }; #define to_hotplug_slot(n) container_of(n, struct hotplug_slot, kobj) -extern int pci_hp_register (struct hotplug_slot *slot); -extern int pci_hp_deregister (struct hotplug_slot *slot); +extern int pci_hp_register(struct hotplug_slot *, struct pci_bus *, int nr); +extern int pci_hp_deregister(struct hotplug_slot *slot); extern int __must_check pci_hp_change_slot_info (struct hotplug_slot *slot, struct hotplug_slot_info *info); -extern struct kset *pci_hotplug_slots_kset; /* PCI Setting Record (Type 0) */ struct hpp_type0 { @@ -227,9 +221,9 @@ struct hotplug_params { #include <acpi/acpi.h> #include <acpi/acpi_bus.h> #include <acpi/actypes.h> -extern acpi_status acpi_run_oshp(acpi_handle handle); extern acpi_status acpi_get_hp_params_from_firmware(struct pci_bus *bus, struct hotplug_params *hpp); +int acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev, u32 flags); int acpi_root_bridge(acpi_handle handle); #endif #endif diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 9b940e644179..ebf32717b35d 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -716,6 +716,7 @@ #define PCI_DEVICE_ID_HP_CISSA 0x3220 #define PCI_DEVICE_ID_HP_CISSC 0x3230 #define PCI_DEVICE_ID_HP_CISSD 0x3238 +#define PCI_DEVICE_ID_HP_CISSE 0x323a #define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031 #define PCI_VENDOR_ID_PCTECH 0x1042 @@ -1980,6 +1981,7 @@ #define PCI_DEVICE_ID_TIGON3_5787M 0x1693 #define PCI_DEVICE_ID_TIGON3_5782 0x1696 #define PCI_DEVICE_ID_TIGON3_5784 0x1698 +#define PCI_DEVICE_ID_TIGON3_5785 0x1699 #define PCI_DEVICE_ID_TIGON3_5786 0x169a #define PCI_DEVICE_ID_TIGON3_5787 0x169b #define PCI_DEVICE_ID_TIGON3_5788 0x169c @@ -2186,6 +2188,7 @@ #define PCI_DEVICE_ID_JMICRON_JMB366 0x2366 #define PCI_DEVICE_ID_JMICRON_JMB368 0x2368 #define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381 +#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382 #define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383 #define PCI_VENDOR_ID_KORENIX 0x1982 diff --git a/include/linux/percpu.h b/include/linux/percpu.h index 4cdd393e71e1..3d1a7f6cc738 100644 --- a/include/linux/percpu.h +++ b/include/linux/percpu.h @@ -23,13 +23,35 @@ __attribute__((__section__(SHARED_ALIGNED_SECTION))) \ PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name \ ____cacheline_aligned_in_smp + +#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name) \ + __attribute__((__section__(".data.percpu.page_aligned"))) \ + PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name + +#ifdef CONFIG_HAVE_ZERO_BASED_PER_CPU +#define DEFINE_PER_CPU_FIRST(type, name) \ + __attribute__((__section__(".data.percpu.first"))) \ + PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name #else +#define DEFINE_PER_CPU_FIRST(type, name) \ + DEFINE_PER_CPU(type, name) +#endif + +#else /* !CONFIG_SMP */ + #define DEFINE_PER_CPU(type, name) \ PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name #define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \ DEFINE_PER_CPU(type, name) -#endif + +#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name) \ + DEFINE_PER_CPU(type, name) + +#define DEFINE_PER_CPU_FIRST(type, name) \ + DEFINE_PER_CPU(type, name) + +#endif /* !CONFIG_SMP */ #define EXPORT_PER_CPU_SYMBOL(var) EXPORT_SYMBOL(per_cpu__##var) #define EXPORT_PER_CPU_SYMBOL_GPL(var) EXPORT_SYMBOL_GPL(per_cpu__##var) diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 3261681c82a4..95ac21ab3a09 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -53,6 +53,7 @@ struct platform_driver { int (*suspend_late)(struct platform_device *, pm_message_t state); int (*resume_early)(struct platform_device *); int (*resume)(struct platform_device *); + struct pm_ext_ops *pm; struct device_driver driver; }; diff --git a/include/linux/pm.h b/include/linux/pm.h index 39a7ee859b67..4ad9de94449a 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -112,7 +112,9 @@ typedef struct pm_message { int event; } pm_message_t; -/* +/** + * struct pm_ops - device PM callbacks + * * Several driver power state transitions are externally visible, affecting * the state of pending I/O queues and (for drivers that touch hardware) * interrupts, wakeups, DMA, and other hardware state. There may also be @@ -120,6 +122,284 @@ typedef struct pm_message { * to the rest of the driver stack (such as a driver that's ON gating off * clocks which are not in active use). * + * The externally visible transitions are handled with the help of the following + * callbacks included in this structure: + * + * @prepare: Prepare the device for the upcoming transition, but do NOT change + * its hardware state. Prevent new children of the device from being + * registered after @prepare() returns (the driver's subsystem and + * generally the rest of the kernel is supposed to prevent new calls to the + * probe method from being made too once @prepare() has succeeded). If + * @prepare() detects a situation it cannot handle (e.g. registration of a + * child already in progress), it may return -EAGAIN, so that the PM core + * can execute it once again (e.g. after the new child has been registered) + * to recover from the race condition. This method is executed for all + * kinds of suspend transitions and is followed by one of the suspend + * callbacks: @suspend(), @freeze(), or @poweroff(). + * The PM core executes @prepare() for all devices before starting to + * execute suspend callbacks for any of them, so drivers may assume all of + * the other devices to be present and functional while @prepare() is being + * executed. In particular, it is safe to make GFP_KERNEL memory + * allocations from within @prepare(). However, drivers may NOT assume + * anything about the availability of the user space at that time and it + * is not correct to request firmware from within @prepare() (it's too + * late to do that). [To work around this limitation, drivers may + * register suspend and hibernation notifiers that are executed before the + * freezing of tasks.] + * + * @complete: Undo the changes made by @prepare(). This method is executed for + * all kinds of resume transitions, following one of the resume callbacks: + * @resume(), @thaw(), @restore(). Also called if the state transition + * fails before the driver's suspend callback (@suspend(), @freeze(), + * @poweroff()) can be executed (e.g. if the suspend callback fails for one + * of the other devices that the PM core has unsuccessfully attempted to + * suspend earlier). + * The PM core executes @complete() after it has executed the appropriate + * resume callback for all devices. + * + * @suspend: Executed before putting the system into a sleep state in which the + * contents of main memory are preserved. Quiesce the device, put it into + * a low power state appropriate for the upcoming system state (such as + * PCI_D3hot), and enable wakeup events as appropriate. + * + * @resume: Executed after waking the system up from a sleep state in which the + * contents of main memory were preserved. Put the device into the + * appropriate state, according to the information saved in memory by the + * preceding @suspend(). The driver starts working again, responding to + * hardware events and software requests. The hardware may have gone + * through a power-off reset, or it may have maintained state from the + * previous suspend() which the driver may rely on while resuming. On most + * platforms, there are no restrictions on availability of resources like + * clocks during @resume(). + * + * @freeze: Hibernation-specific, executed before creating a hibernation image. + * Quiesce operations so that a consistent image can be created, but do NOT + * otherwise put the device into a low power device state and do NOT emit + * system wakeup events. Save in main memory the device settings to be + * used by @restore() during the subsequent resume from hibernation or by + * the subsequent @thaw(), if the creation of the image or the restoration + * of main memory contents from it fails. + * + * @thaw: Hibernation-specific, executed after creating a hibernation image OR + * if the creation of the image fails. Also executed after a failing + * attempt to restore the contents of main memory from such an image. + * Undo the changes made by the preceding @freeze(), so the device can be + * operated in the same way as immediately before the call to @freeze(). + * + * @poweroff: Hibernation-specific, executed after saving a hibernation image. + * Quiesce the device, put it into a low power state appropriate for the + * upcoming system state (such as PCI_D3hot), and enable wakeup events as + * appropriate. + * + * @restore: Hibernation-specific, executed after restoring the contents of main + * memory from a hibernation image. Driver starts working again, + * responding to hardware events and software requests. Drivers may NOT + * make ANY assumptions about the hardware state right prior to @restore(). + * On most platforms, there are no restrictions on availability of + * resources like clocks during @restore(). + * + * All of the above callbacks, except for @complete(), return error codes. + * However, the error codes returned by the resume operations, @resume(), + * @thaw(), and @restore(), do not cause the PM core to abort the resume + * transition during which they are returned. The error codes returned in + * that cases are only printed by the PM core to the system logs for debugging + * purposes. Still, it is recommended that drivers only return error codes + * from their resume methods in case of an unrecoverable failure (i.e. when the + * device being handled refuses to resume and becomes unusable) to allow us to + * modify the PM core in the future, so that it can avoid attempting to handle + * devices that failed to resume and their children. + * + * It is allowed to unregister devices while the above callbacks are being + * executed. However, it is not allowed to unregister a device from within any + * of its own callbacks. + */ + +struct pm_ops { + int (*prepare)(struct device *dev); + void (*complete)(struct device *dev); + int (*suspend)(struct device *dev); + int (*resume)(struct device *dev); + int (*freeze)(struct device *dev); + int (*thaw)(struct device *dev); + int (*poweroff)(struct device *dev); + int (*restore)(struct device *dev); +}; + +/** + * struct pm_ext_ops - extended device PM callbacks + * + * Some devices require certain operations related to suspend and hibernation + * to be carried out with interrupts disabled. Thus, 'struct pm_ext_ops' below + * is defined, adding callbacks to be executed with interrupts disabled to + * 'struct pm_ops'. + * + * The following callbacks included in 'struct pm_ext_ops' are executed with + * the nonboot CPUs switched off and with interrupts disabled on the only + * functional CPU. They also are executed with the PM core list of devices + * locked, so they must NOT unregister any devices. + * + * @suspend_noirq: Complete the operations of ->suspend() by carrying out any + * actions required for suspending the device that need interrupts to be + * disabled + * + * @resume_noirq: Prepare for the execution of ->resume() by carrying out any + * actions required for resuming the device that need interrupts to be + * disabled + * + * @freeze_noirq: Complete the operations of ->freeze() by carrying out any + * actions required for freezing the device that need interrupts to be + * disabled + * + * @thaw_noirq: Prepare for the execution of ->thaw() by carrying out any + * actions required for thawing the device that need interrupts to be + * disabled + * + * @poweroff_noirq: Complete the operations of ->poweroff() by carrying out any + * actions required for handling the device that need interrupts to be + * disabled + * + * @restore_noirq: Prepare for the execution of ->restore() by carrying out any + * actions required for restoring the operations of the device that need + * interrupts to be disabled + * + * All of the above callbacks return error codes, but the error codes returned + * by the resume operations, @resume_noirq(), @thaw_noirq(), and + * @restore_noirq(), do not cause the PM core to abort the resume transition + * during which they are returned. The error codes returned in that cases are + * only printed by the PM core to the system logs for debugging purposes. + * Still, as stated above, it is recommended that drivers only return error + * codes from their resume methods if the device being handled fails to resume + * and is not usable any more. + */ + +struct pm_ext_ops { + struct pm_ops base; + int (*suspend_noirq)(struct device *dev); + int (*resume_noirq)(struct device *dev); + int (*freeze_noirq)(struct device *dev); + int (*thaw_noirq)(struct device *dev); + int (*poweroff_noirq)(struct device *dev); + int (*restore_noirq)(struct device *dev); +}; + +/** + * PM_EVENT_ messages + * + * The following PM_EVENT_ messages are defined for the internal use of the PM + * core, in order to provide a mechanism allowing the high level suspend and + * hibernation code to convey the necessary information to the device PM core + * code: + * + * ON No transition. + * + * FREEZE System is going to hibernate, call ->prepare() and ->freeze() + * for all devices. + * + * SUSPEND System is going to suspend, call ->prepare() and ->suspend() + * for all devices. + * + * HIBERNATE Hibernation image has been saved, call ->prepare() and + * ->poweroff() for all devices. + * + * QUIESCE Contents of main memory are going to be restored from a (loaded) + * hibernation image, call ->prepare() and ->freeze() for all + * devices. + * + * RESUME System is resuming, call ->resume() and ->complete() for all + * devices. + * + * THAW Hibernation image has been created, call ->thaw() and + * ->complete() for all devices. + * + * RESTORE Contents of main memory have been restored from a hibernation + * image, call ->restore() and ->complete() for all devices. + * + * RECOVER Creation of a hibernation image or restoration of the main + * memory contents from a hibernation image has failed, call + * ->thaw() and ->complete() for all devices. + */ + +#define PM_EVENT_ON 0x0000 +#define PM_EVENT_FREEZE 0x0001 +#define PM_EVENT_SUSPEND 0x0002 +#define PM_EVENT_HIBERNATE 0x0004 +#define PM_EVENT_QUIESCE 0x0008 +#define PM_EVENT_RESUME 0x0010 +#define PM_EVENT_THAW 0x0020 +#define PM_EVENT_RESTORE 0x0040 +#define PM_EVENT_RECOVER 0x0080 + +#define PM_EVENT_SLEEP (PM_EVENT_SUSPEND | PM_EVENT_HIBERNATE) + +#define PMSG_FREEZE ((struct pm_message){ .event = PM_EVENT_FREEZE, }) +#define PMSG_QUIESCE ((struct pm_message){ .event = PM_EVENT_QUIESCE, }) +#define PMSG_SUSPEND ((struct pm_message){ .event = PM_EVENT_SUSPEND, }) +#define PMSG_HIBERNATE ((struct pm_message){ .event = PM_EVENT_HIBERNATE, }) +#define PMSG_RESUME ((struct pm_message){ .event = PM_EVENT_RESUME, }) +#define PMSG_THAW ((struct pm_message){ .event = PM_EVENT_THAW, }) +#define PMSG_RESTORE ((struct pm_message){ .event = PM_EVENT_RESTORE, }) +#define PMSG_RECOVER ((struct pm_message){ .event = PM_EVENT_RECOVER, }) +#define PMSG_ON ((struct pm_message){ .event = PM_EVENT_ON, }) + +/** + * Device power management states + * + * These state labels are used internally by the PM core to indicate the current + * status of a device with respect to the PM core operations. + * + * DPM_ON Device is regarded as operational. Set this way + * initially and when ->complete() is about to be called. + * Also set when ->prepare() fails. + * + * DPM_PREPARING Device is going to be prepared for a PM transition. Set + * when ->prepare() is about to be called. + * + * DPM_RESUMING Device is going to be resumed. Set when ->resume(), + * ->thaw(), or ->restore() is about to be called. + * + * DPM_SUSPENDING Device has been prepared for a power transition. Set + * when ->prepare() has just succeeded. + * + * DPM_OFF Device is regarded as inactive. Set immediately after + * ->suspend(), ->freeze(), or ->poweroff() has succeeded. + * Also set when ->resume()_noirq, ->thaw_noirq(), or + * ->restore_noirq() is about to be called. + * + * DPM_OFF_IRQ Device is in a "deep sleep". Set immediately after + * ->suspend_noirq(), ->freeze_noirq(), or + * ->poweroff_noirq() has just succeeded. + */ + +enum dpm_state { + DPM_INVALID, + DPM_ON, + DPM_PREPARING, + DPM_RESUMING, + DPM_SUSPENDING, + DPM_OFF, + DPM_OFF_IRQ, +}; + +struct dev_pm_info { + pm_message_t power_state; + unsigned can_wakeup:1; + unsigned should_wakeup:1; + enum dpm_state status; /* Owned by the PM core */ +#ifdef CONFIG_PM_SLEEP + struct list_head entry; +#endif +}; + +/* + * The PM_EVENT_ messages are also used by drivers implementing the legacy + * suspend framework, based on the ->suspend() and ->resume() callbacks common + * for suspend and hibernation transitions, according to the rules below. + */ + +/* Necessary, because several drivers use PM_EVENT_PRETHAW */ +#define PM_EVENT_PRETHAW PM_EVENT_QUIESCE + +/* * One transition is triggered by resume(), after a suspend() call; the * message is implicit: * @@ -164,35 +444,13 @@ typedef struct pm_message { * or from system low-power states such as standby or suspend-to-RAM. */ -#define PM_EVENT_ON 0 -#define PM_EVENT_FREEZE 1 -#define PM_EVENT_SUSPEND 2 -#define PM_EVENT_HIBERNATE 4 -#define PM_EVENT_PRETHAW 8 - -#define PM_EVENT_SLEEP (PM_EVENT_SUSPEND | PM_EVENT_HIBERNATE) - -#define PMSG_FREEZE ((struct pm_message){ .event = PM_EVENT_FREEZE, }) -#define PMSG_PRETHAW ((struct pm_message){ .event = PM_EVENT_PRETHAW, }) -#define PMSG_SUSPEND ((struct pm_message){ .event = PM_EVENT_SUSPEND, }) -#define PMSG_HIBERNATE ((struct pm_message){ .event = PM_EVENT_HIBERNATE, }) -#define PMSG_ON ((struct pm_message){ .event = PM_EVENT_ON, }) - -struct dev_pm_info { - pm_message_t power_state; - unsigned can_wakeup:1; - unsigned should_wakeup:1; - bool sleeping:1; /* Owned by the PM core */ -#ifdef CONFIG_PM_SLEEP - struct list_head entry; -#endif -}; +#ifdef CONFIG_PM_SLEEP +extern void device_pm_lock(void); +extern void device_power_up(pm_message_t state); +extern void device_resume(pm_message_t state); +extern void device_pm_unlock(void); extern int device_power_down(pm_message_t state); -extern void device_power_up(void); -extern void device_resume(void); - -#ifdef CONFIG_PM_SLEEP extern int device_suspend(pm_message_t state); extern int device_prepare_suspend(pm_message_t state); diff --git a/include/linux/poison.h b/include/linux/poison.h index 9f31683728fd..0d105a56e668 100644 --- a/include/linux/poison.h +++ b/include/linux/poison.h @@ -1,14 +1,20 @@ #ifndef _LINUX_POISON_H #define _LINUX_POISON_H +#ifdef CONFIG_ILLEGAL_POINTER_VALUE +#define POISON_POINTER_DELTA CONFIG_ILLEGAL_POINTER_VALUE +#else +#define POISON_POINTER_DELTA 0L +#endif + /********** include/linux/list.h **********/ /* * These are non-NULL pointers that will result in page faults * under normal circumstances, used to verify that nobody uses * non-initialized list entries. */ -#define LIST_POISON1 ((void *) 0x00100100) -#define LIST_POISON2 ((void *) 0x00200200) +#define LIST_POISON1 ((void *) 0x00100100 + POISON_POINTER_DELTA) +#define LIST_POISON2 ((void *) 0x00200200 + POISON_POINTER_DELTA) /********** include/linux/timer.h **********/ /* diff --git a/include/linux/ppp-comp.h b/include/linux/ppp-comp.h index e86a7a5cf355..b8d4ddd22736 100644 --- a/include/linux/ppp-comp.h +++ b/include/linux/ppp-comp.h @@ -23,8 +23,6 @@ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, * OR MODIFICATIONS. - * - * $Id: ppp-comp.h,v 1.6 1997/11/27 06:04:44 paulus Exp $ */ /* diff --git a/include/linux/ppp_defs.h b/include/linux/ppp_defs.h index c6b13ff85028..6e8adc77522c 100644 --- a/include/linux/ppp_defs.h +++ b/include/linux/ppp_defs.h @@ -1,5 +1,3 @@ -/* $Id: ppp_defs.h,v 1.2 1994/09/21 01:31:06 paulus Exp $ */ - /* * ppp_defs.h - PPP definitions. * diff --git a/include/linux/preempt.h b/include/linux/preempt.h index 23f0c54175cd..72b1a10a59b6 100644 --- a/include/linux/preempt.h +++ b/include/linux/preempt.h @@ -10,7 +10,7 @@ #include <linux/linkage.h> #include <linux/list.h> -#ifdef CONFIG_DEBUG_PREEMPT +#if defined(CONFIG_DEBUG_PREEMPT) || defined(CONFIG_PREEMPT_TRACER) extern void add_preempt_count(int val); extern void sub_preempt_count(int val); #else @@ -52,6 +52,34 @@ do { \ preempt_check_resched(); \ } while (0) +/* For debugging and tracer internals only! */ +#define add_preempt_count_notrace(val) \ + do { preempt_count() += (val); } while (0) +#define sub_preempt_count_notrace(val) \ + do { preempt_count() -= (val); } while (0) +#define inc_preempt_count_notrace() add_preempt_count_notrace(1) +#define dec_preempt_count_notrace() sub_preempt_count_notrace(1) + +#define preempt_disable_notrace() \ +do { \ + inc_preempt_count_notrace(); \ + barrier(); \ +} while (0) + +#define preempt_enable_no_resched_notrace() \ +do { \ + barrier(); \ + dec_preempt_count_notrace(); \ +} while (0) + +/* preempt_check_resched is OK to trace */ +#define preempt_enable_notrace() \ +do { \ + preempt_enable_no_resched_notrace(); \ + barrier(); \ + preempt_check_resched(); \ +} while (0) + #else #define preempt_disable() do { } while (0) @@ -59,6 +87,10 @@ do { \ #define preempt_enable() do { } while (0) #define preempt_check_resched() do { } while (0) +#define preempt_disable_notrace() do { } while (0) +#define preempt_enable_no_resched_notrace() do { } while (0) +#define preempt_enable_notrace() do { } while (0) + #endif #ifdef CONFIG_PREEMPT_NOTIFIERS diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h index 9883bc942262..fff1d27ddb4c 100644 --- a/include/linux/proc_fs.h +++ b/include/linux/proc_fs.h @@ -9,6 +9,8 @@ struct net; struct completion; +struct mm_struct; + /* * The proc filesystem constants/structures */ @@ -101,8 +103,6 @@ extern spinlock_t proc_subdir_lock; extern void proc_root_init(void); extern void proc_misc_init(void); -struct mm_struct; - void proc_flush_task(struct task_struct *task); struct dentry *proc_pid_lookup(struct inode *dir, struct dentry * dentry, struct nameidata *); int proc_pid_readdir(struct file * filp, void * dirent, filldir_t filldir); diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h index f98501ba557e..c6f5f9dd0cee 100644 --- a/include/linux/ptrace.h +++ b/include/linux/ptrace.h @@ -95,8 +95,12 @@ extern void __ptrace_link(struct task_struct *child, struct task_struct *new_parent); extern void __ptrace_unlink(struct task_struct *child); extern void ptrace_untrace(struct task_struct *child); -extern int ptrace_may_attach(struct task_struct *task); -extern int __ptrace_may_attach(struct task_struct *task); +#define PTRACE_MODE_READ 1 +#define PTRACE_MODE_ATTACH 2 +/* Returns 0 on success, -errno on denial. */ +extern int __ptrace_may_access(struct task_struct *task, unsigned int mode); +/* Returns true on success, false on denial. */ +extern bool ptrace_may_access(struct task_struct *task, unsigned int mode); static inline int ptrace_reparented(struct task_struct *child) { diff --git a/include/linux/pwm.h b/include/linux/pwm.h new file mode 100644 index 000000000000..3945f803d514 --- /dev/null +++ b/include/linux/pwm.h @@ -0,0 +1,31 @@ +#ifndef __LINUX_PWM_H +#define __LINUX_PWM_H + +struct pwm_device; + +/* + * pwm_request - request a PWM device + */ +struct pwm_device *pwm_request(int pwm_id, const char *label); + +/* + * pwm_free - free a PWM device + */ +void pwm_free(struct pwm_device *pwm); + +/* + * pwm_config - change a PWM device configuration + */ +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns); + +/* + * pwm_enable - start a PWM output toggling + */ +int pwm_enable(struct pwm_device *pwm); + +/* + * pwm_disable - stop a PWM output toggling + */ +void pwm_disable(struct pwm_device *pwm); + +#endif /* __ASM_ARCH_PWM_H */ diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h new file mode 100644 index 000000000000..7a9754c96775 --- /dev/null +++ b/include/linux/pwm_backlight.h @@ -0,0 +1,17 @@ +/* + * Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c + */ +#ifndef __LINUX_PWM_BACKLIGHT_H +#define __LINUX_PWM_BACKLIGHT_H + +struct platform_pwm_backlight_data { + int pwm_id; + unsigned int max_brightness; + unsigned int dft_brightness; + unsigned int pwm_period_ns; + int (*init)(struct device *dev); + int (*notify)(int brightness); + void (*exit)(struct device *dev); +}; + +#endif diff --git a/include/linux/rcuclassic.h b/include/linux/rcuclassic.h index b3aa05baab8a..8c774905dcfe 100644 --- a/include/linux/rcuclassic.h +++ b/include/linux/rcuclassic.h @@ -151,7 +151,10 @@ extern struct lockdep_map rcu_lock_map; #define __synchronize_sched() synchronize_rcu() +#define call_rcu_sched(head, func) call_rcu(head, func) + extern void __rcu_init(void); +#define rcu_init_sched() do { } while (0) extern void rcu_check_callbacks(int cpu, int user); extern void rcu_restart_cpu(int cpu); diff --git a/include/linux/rculist.h b/include/linux/rculist.h new file mode 100644 index 000000000000..b0f39be08b6c --- /dev/null +++ b/include/linux/rculist.h @@ -0,0 +1,373 @@ +#ifndef _LINUX_RCULIST_H +#define _LINUX_RCULIST_H + +#ifdef __KERNEL__ + +/* + * RCU-protected list version + */ +#include <linux/list.h> +#include <linux/rcupdate.h> + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_add_rcu(struct list_head *new, + struct list_head *prev, struct list_head *next) +{ + new->next = next; + new->prev = prev; + rcu_assign_pointer(prev->next, new); + next->prev = new; +} + +/** + * list_add_rcu - add a new entry to rcu-protected list + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as list_add_rcu() + * or list_del_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * list_for_each_entry_rcu(). + */ +static inline void list_add_rcu(struct list_head *new, struct list_head *head) +{ + __list_add_rcu(new, head, head->next); +} + +/** + * list_add_tail_rcu - add a new entry to rcu-protected list + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as list_add_tail_rcu() + * or list_del_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * list_for_each_entry_rcu(). + */ +static inline void list_add_tail_rcu(struct list_head *new, + struct list_head *head) +{ + __list_add_rcu(new, head->prev, head); +} + +/** + * list_del_rcu - deletes entry from list without re-initialization + * @entry: the element to delete from the list. + * + * Note: list_empty() on entry does not return true after this, + * the entry is in an undefined state. It is useful for RCU based + * lockfree traversal. + * + * In particular, it means that we can not poison the forward + * pointers that may still be used for walking the list. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as list_del_rcu() + * or list_add_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * list_for_each_entry_rcu(). + * + * Note that the caller is not permitted to immediately free + * the newly deleted entry. Instead, either synchronize_rcu() + * or call_rcu() must be used to defer freeing until an RCU + * grace period has elapsed. + */ +static inline void list_del_rcu(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->prev = LIST_POISON2; +} + +/** + * list_replace_rcu - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * The @old entry will be replaced with the @new entry atomically. + * Note: @old should not be empty. + */ +static inline void list_replace_rcu(struct list_head *old, + struct list_head *new) +{ + new->next = old->next; + new->prev = old->prev; + rcu_assign_pointer(new->prev->next, new); + new->next->prev = new; + old->prev = LIST_POISON2; +} + +/** + * list_splice_init_rcu - splice an RCU-protected list into an existing list. + * @list: the RCU-protected list to splice + * @head: the place in the list to splice the first list into + * @sync: function to sync: synchronize_rcu(), synchronize_sched(), ... + * + * @head can be RCU-read traversed concurrently with this function. + * + * Note that this function blocks. + * + * Important note: the caller must take whatever action is necessary to + * prevent any other updates to @head. In principle, it is possible + * to modify the list as soon as sync() begins execution. + * If this sort of thing becomes necessary, an alternative version + * based on call_rcu() could be created. But only if -really- + * needed -- there is no shortage of RCU API members. + */ +static inline void list_splice_init_rcu(struct list_head *list, + struct list_head *head, + void (*sync)(void)) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + struct list_head *at = head->next; + + if (list_empty(head)) + return; + + /* "first" and "last" tracking list, so initialize it. */ + + INIT_LIST_HEAD(list); + + /* + * At this point, the list body still points to the source list. + * Wait for any readers to finish using the list before splicing + * the list body into the new list. Any new readers will see + * an empty list. + */ + + sync(); + + /* + * Readers are finished with the source list, so perform splice. + * The order is important if the new list is global and accessible + * to concurrent RCU readers. Note that RCU readers are not + * permitted to traverse the prev pointers without excluding + * this function. + */ + + last->next = at; + rcu_assign_pointer(head->next, first); + first->prev = head; + at->prev = last; +} + +/** + * list_for_each_rcu - iterate over an rcu-protected list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + * + * This list-traversal primitive may safely run concurrently with + * the _rcu list-mutation primitives such as list_add_rcu() + * as long as the traversal is guarded by rcu_read_lock(). + */ +#define list_for_each_rcu(pos, head) \ + for (pos = rcu_dereference((head)->next); \ + prefetch(pos->next), pos != (head); \ + pos = rcu_dereference(pos->next)) + +#define __list_for_each_rcu(pos, head) \ + for (pos = rcu_dereference((head)->next); \ + pos != (head); \ + pos = rcu_dereference(pos->next)) + +/** + * list_for_each_entry_rcu - iterate over rcu list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * This list-traversal primitive may safely run concurrently with + * the _rcu list-mutation primitives such as list_add_rcu() + * as long as the traversal is guarded by rcu_read_lock(). + */ +#define list_for_each_entry_rcu(pos, head, member) \ + for (pos = list_entry(rcu_dereference((head)->next), typeof(*pos), member); \ + prefetch(pos->member.next), &pos->member != (head); \ + pos = list_entry(rcu_dereference(pos->member.next), typeof(*pos), member)) + + +/** + * list_for_each_continue_rcu + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + * + * Iterate over an rcu-protected list, continuing after current point. + * + * This list-traversal primitive may safely run concurrently with + * the _rcu list-mutation primitives such as list_add_rcu() + * as long as the traversal is guarded by rcu_read_lock(). + */ +#define list_for_each_continue_rcu(pos, head) \ + for ((pos) = rcu_dereference((pos)->next); \ + prefetch((pos)->next), (pos) != (head); \ + (pos) = rcu_dereference((pos)->next)) + +/** + * hlist_del_rcu - deletes entry from hash list without re-initialization + * @n: the element to delete from the hash list. + * + * Note: list_unhashed() on entry does not return true after this, + * the entry is in an undefined state. It is useful for RCU based + * lockfree traversal. + * + * In particular, it means that we can not poison the forward + * pointers that may still be used for walking the hash list. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as hlist_add_head_rcu() + * or hlist_del_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * hlist_for_each_entry(). + */ +static inline void hlist_del_rcu(struct hlist_node *n) +{ + __hlist_del(n); + n->pprev = LIST_POISON2; +} + +/** + * hlist_replace_rcu - replace old entry by new one + * @old : the element to be replaced + * @new : the new element to insert + * + * The @old entry will be replaced with the @new entry atomically. + */ +static inline void hlist_replace_rcu(struct hlist_node *old, + struct hlist_node *new) +{ + struct hlist_node *next = old->next; + + new->next = next; + new->pprev = old->pprev; + rcu_assign_pointer(*new->pprev, new); + if (next) + new->next->pprev = &new->next; + old->pprev = LIST_POISON2; +} + +/** + * hlist_add_head_rcu + * @n: the element to add to the hash list. + * @h: the list to add to. + * + * Description: + * Adds the specified element to the specified hlist, + * while permitting racing traversals. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as hlist_add_head_rcu() + * or hlist_del_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * hlist_for_each_entry_rcu(), used to prevent memory-consistency + * problems on Alpha CPUs. Regardless of the type of CPU, the + * list-traversal primitive must be guarded by rcu_read_lock(). + */ +static inline void hlist_add_head_rcu(struct hlist_node *n, + struct hlist_head *h) +{ + struct hlist_node *first = h->first; + + n->next = first; + n->pprev = &h->first; + rcu_assign_pointer(h->first, n); + if (first) + first->pprev = &n->next; +} + +/** + * hlist_add_before_rcu + * @n: the new element to add to the hash list. + * @next: the existing element to add the new element before. + * + * Description: + * Adds the specified element to the specified hlist + * before the specified node while permitting racing traversals. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as hlist_add_head_rcu() + * or hlist_del_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * hlist_for_each_entry_rcu(), used to prevent memory-consistency + * problems on Alpha CPUs. + */ +static inline void hlist_add_before_rcu(struct hlist_node *n, + struct hlist_node *next) +{ + n->pprev = next->pprev; + n->next = next; + rcu_assign_pointer(*(n->pprev), n); + next->pprev = &n->next; +} + +/** + * hlist_add_after_rcu + * @prev: the existing element to add the new element after. + * @n: the new element to add to the hash list. + * + * Description: + * Adds the specified element to the specified hlist + * after the specified node while permitting racing traversals. + * + * The caller must take whatever precautions are necessary + * (such as holding appropriate locks) to avoid racing + * with another list-mutation primitive, such as hlist_add_head_rcu() + * or hlist_del_rcu(), running on this same list. + * However, it is perfectly legal to run concurrently with + * the _rcu list-traversal primitives, such as + * hlist_for_each_entry_rcu(), used to prevent memory-consistency + * problems on Alpha CPUs. + */ +static inline void hlist_add_after_rcu(struct hlist_node *prev, + struct hlist_node *n) +{ + n->next = prev->next; + n->pprev = &prev->next; + rcu_assign_pointer(prev->next, n); + if (n->next) + n->next->pprev = &n->next; +} + +/** + * hlist_for_each_entry_rcu - iterate over rcu list of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct hlist_node to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the hlist_node within the struct. + * + * This list-traversal primitive may safely run concurrently with + * the _rcu list-mutation primitives such as hlist_add_head_rcu() + * as long as the traversal is guarded by rcu_read_lock(). + */ +#define hlist_for_each_entry_rcu(tpos, pos, head, member) \ + for (pos = rcu_dereference((head)->first); \ + pos && ({ prefetch(pos->next); 1; }) && \ + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); \ + pos = rcu_dereference(pos->next)) + +#endif /* __KERNEL__ */ +#endif diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index d42dbec06083..e8b4039cfb2f 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -40,6 +40,7 @@ #include <linux/cpumask.h> #include <linux/seqlock.h> #include <linux/lockdep.h> +#include <linux/completion.h> /** * struct rcu_head - callback structure for use with RCU @@ -168,6 +169,27 @@ struct rcu_head { (p) = (v); \ }) +/* Infrastructure to implement the synchronize_() primitives. */ + +struct rcu_synchronize { + struct rcu_head head; + struct completion completion; +}; + +extern void wakeme_after_rcu(struct rcu_head *head); + +#define synchronize_rcu_xxx(name, func) \ +void name(void) \ +{ \ + struct rcu_synchronize rcu; \ + \ + init_completion(&rcu.completion); \ + /* Will wake me after RCU finished. */ \ + func(&rcu.head, wakeme_after_rcu); \ + /* Wait for it. */ \ + wait_for_completion(&rcu.completion); \ +} + /** * synchronize_sched - block until all CPUs have exited any non-preemptive * kernel code sequences. @@ -224,8 +246,8 @@ extern void call_rcu_bh(struct rcu_head *head, /* Exported common interfaces */ extern void synchronize_rcu(void); extern void rcu_barrier(void); -extern long rcu_batches_completed(void); -extern long rcu_batches_completed_bh(void); +extern void rcu_barrier_bh(void); +extern void rcu_barrier_sched(void); /* Internal to kernel */ extern void rcu_init(void); diff --git a/include/linux/rcupreempt.h b/include/linux/rcupreempt.h index 8a05c7e20bc4..f04b64eca636 100644 --- a/include/linux/rcupreempt.h +++ b/include/linux/rcupreempt.h @@ -40,10 +40,39 @@ #include <linux/cpumask.h> #include <linux/seqlock.h> -#define rcu_qsctr_inc(cpu) +struct rcu_dyntick_sched { + int dynticks; + int dynticks_snap; + int sched_qs; + int sched_qs_snap; + int sched_dynticks_snap; +}; + +DECLARE_PER_CPU(struct rcu_dyntick_sched, rcu_dyntick_sched); + +static inline void rcu_qsctr_inc(int cpu) +{ + struct rcu_dyntick_sched *rdssp = &per_cpu(rcu_dyntick_sched, cpu); + + rdssp->sched_qs++; +} #define rcu_bh_qsctr_inc(cpu) #define call_rcu_bh(head, rcu) call_rcu(head, rcu) +/** + * call_rcu_sched - Queue RCU callback for invocation after sched grace period. + * @head: structure to be used for queueing the RCU updates. + * @func: actual update function to be invoked after the grace period + * + * The update function will be invoked some time after a full + * synchronize_sched()-style grace period elapses, in other words after + * all currently executing preempt-disabled sections of code (including + * hardirq handlers, NMI handlers, and local_irq_save() blocks) have + * completed. + */ +extern void call_rcu_sched(struct rcu_head *head, + void (*func)(struct rcu_head *head)); + extern void __rcu_read_lock(void) __acquires(RCU); extern void __rcu_read_unlock(void) __releases(RCU); extern int rcu_pending(int cpu); @@ -55,6 +84,7 @@ extern int rcu_needs_cpu(int cpu); extern void __synchronize_sched(void); extern void __rcu_init(void); +extern void rcu_init_sched(void); extern void rcu_check_callbacks(int cpu, int user); extern void rcu_restart_cpu(int cpu); extern long rcu_batches_completed(void); @@ -81,20 +111,20 @@ extern struct rcupreempt_trace *rcupreempt_trace_cpu(int cpu); struct softirq_action; #ifdef CONFIG_NO_HZ -DECLARE_PER_CPU(long, dynticks_progress_counter); +DECLARE_PER_CPU(struct rcu_dyntick_sched, rcu_dyntick_sched); static inline void rcu_enter_nohz(void) { smp_mb(); /* CPUs seeing ++ must see prior RCU read-side crit sects */ - __get_cpu_var(dynticks_progress_counter)++; - WARN_ON(__get_cpu_var(dynticks_progress_counter) & 0x1); + __get_cpu_var(rcu_dyntick_sched).dynticks++; + WARN_ON(__get_cpu_var(rcu_dyntick_sched).dynticks & 0x1); } static inline void rcu_exit_nohz(void) { - __get_cpu_var(dynticks_progress_counter)++; smp_mb(); /* CPUs seeing ++ must see later RCU read-side crit sects */ - WARN_ON(!(__get_cpu_var(dynticks_progress_counter) & 0x1)); + __get_cpu_var(rcu_dyntick_sched).dynticks++; + WARN_ON(!(__get_cpu_var(rcu_dyntick_sched).dynticks & 0x1)); } #else /* CONFIG_NO_HZ */ diff --git a/include/linux/resume-trace.h b/include/linux/resume-trace.h index f3f4f28c6960..c9ba2fdf807d 100644 --- a/include/linux/resume-trace.h +++ b/include/linux/resume-trace.h @@ -8,7 +8,7 @@ extern int pm_trace_enabled; struct device; extern void set_trace_device(struct device *); -extern void generate_resume_trace(void *tracedata, unsigned int user); +extern void generate_resume_trace(const void *tracedata, unsigned int user); #define TRACE_DEVICE(dev) do { \ if (pm_trace_enabled) \ diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index 44c81c744538..b358c704d102 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -246,6 +246,7 @@ enum rt_class_t { RT_TABLE_UNSPEC=0, /* User defined values */ + RT_TABLE_COMPAT=252, RT_TABLE_DEFAULT=253, RT_TABLE_MAIN=254, RT_TABLE_LOCAL=255, @@ -267,10 +268,10 @@ enum rtattr_type_t RTA_PREFSRC, RTA_METRICS, RTA_MULTIPATH, - RTA_PROTOINFO, + RTA_PROTOINFO, /* no longer used */ RTA_FLOW, RTA_CACHEINFO, - RTA_SESSION, + RTA_SESSION, /* no longer used */ RTA_MP_ALGO, /* no longer used */ RTA_TABLE, __RTA_MAX diff --git a/include/linux/sched.h b/include/linux/sched.h index ae0be3c62375..239df23ad857 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -134,7 +134,6 @@ extern unsigned long nr_running(void); extern unsigned long nr_uninterruptible(void); extern unsigned long nr_active(void); extern unsigned long nr_iowait(void); -extern unsigned long weighted_cpuload(const int cpu); struct seq_file; struct cfs_rq; @@ -246,6 +245,8 @@ extern asmlinkage void schedule_tail(struct task_struct *prev); extern void init_idle(struct task_struct *idle, int cpu); extern void init_idle_bootup_task(struct task_struct *idle); +extern int runqueue_is_locked(void); + extern cpumask_t nohz_cpu_mask; #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ) extern int select_nohz_load_balancer(int cpu); @@ -294,10 +295,11 @@ extern void softlockup_tick(void); extern void spawn_softlockup_task(void); extern void touch_softlockup_watchdog(void); extern void touch_all_softlockup_watchdogs(void); -extern unsigned long softlockup_thresh; +extern unsigned int softlockup_panic; extern unsigned long sysctl_hung_task_check_count; extern unsigned long sysctl_hung_task_timeout_secs; extern unsigned long sysctl_hung_task_warnings; +extern int softlockup_thresh; #else static inline void softlockup_tick(void) { @@ -823,23 +825,6 @@ extern int arch_reinit_sched_domains(void); #endif /* CONFIG_SMP */ -/* - * A runqueue laden with a single nice 0 task scores a weighted_cpuload of - * SCHED_LOAD_SCALE. This function returns 1 if any cpu is laden with a - * task of nice 0 or enough lower priority tasks to bring up the - * weighted_cpuload - */ -static inline int above_background_load(void) -{ - unsigned long cpu; - - for_each_online_cpu(cpu) { - if (weighted_cpuload(cpu) >= SCHED_LOAD_SCALE) - return 1; - } - return 0; -} - struct io_context; /* See blkdev.h */ #define NGROUPS_SMALL 32 #define NGROUPS_PER_BLOCK ((unsigned int)(PAGE_SIZE / sizeof(gid_t))) @@ -921,8 +906,8 @@ struct sched_class { void (*set_cpus_allowed)(struct task_struct *p, const cpumask_t *newmask); - void (*join_domain)(struct rq *rq); - void (*leave_domain)(struct rq *rq); + void (*rq_online)(struct rq *rq); + void (*rq_offline)(struct rq *rq); void (*switched_from) (struct rq *this_rq, struct task_struct *task, int running); @@ -1039,6 +1024,7 @@ struct task_struct { #endif int prio, static_prio, normal_prio; + unsigned int rt_priority; const struct sched_class *sched_class; struct sched_entity se; struct sched_rt_entity rt; @@ -1095,10 +1081,9 @@ struct task_struct { pid_t pid; pid_t tgid; -#ifdef CONFIG_CC_STACKPROTECTOR /* Canary value for the -fstack-protector gcc feature */ unsigned long stack_canary; -#endif + /* * pointers to (original) parent process, youngest child, younger sibling, * older sibling, respectively. (p->father can be replaced with @@ -1122,7 +1107,6 @@ struct task_struct { int __user *set_child_tid; /* CLONE_CHILD_SETTID */ int __user *clear_child_tid; /* CLONE_CHILD_CLEARTID */ - unsigned int rt_priority; cputime_t utime, stime, utimescaled, stimescaled; cputime_t gtime; cputime_t prev_utime, prev_stime; @@ -1141,12 +1125,12 @@ struct task_struct { gid_t gid,egid,sgid,fsgid; struct group_info *group_info; kernel_cap_t cap_effective, cap_inheritable, cap_permitted, cap_bset; - unsigned securebits; struct user_struct *user; + unsigned securebits; #ifdef CONFIG_KEYS + unsigned char jit_keyring; /* default keyring to attach requested keys to */ struct key *request_key_auth; /* assumed request_key authority */ struct key *thread_keyring; /* keyring private to this thread */ - unsigned char jit_keyring; /* default keyring to attach requested keys to */ #endif char comm[TASK_COMM_LEN]; /* executable name excluding path - access with [gs]et_task_comm (which lock @@ -1233,8 +1217,8 @@ struct task_struct { # define MAX_LOCK_DEPTH 48UL u64 curr_chain_key; int lockdep_depth; - struct held_lock held_locks[MAX_LOCK_DEPTH]; unsigned int lockdep_recursion; + struct held_lock held_locks[MAX_LOCK_DEPTH]; #endif /* journalling filesystem info */ @@ -1262,10 +1246,6 @@ struct task_struct { u64 acct_vm_mem1; /* accumulated virtual memory usage */ cputime_t acct_stimexpd;/* stime since last update */ #endif -#ifdef CONFIG_NUMA - struct mempolicy *mempolicy; - short il_next; -#endif #ifdef CONFIG_CPUSETS nodemask_t mems_allowed; int cpuset_mems_generation; @@ -1285,6 +1265,10 @@ struct task_struct { struct list_head pi_state_list; struct futex_pi_state *pi_state_cache; #endif +#ifdef CONFIG_NUMA + struct mempolicy *mempolicy; + short il_next; +#endif atomic_t fs_excl; /* holding fs exclusive resources */ struct rcu_head rcu; @@ -1504,9 +1488,11 @@ static inline void put_task_struct(struct task_struct *t) #define PF_SWAPWRITE 0x00800000 /* Allowed to write to swap */ #define PF_SPREAD_PAGE 0x01000000 /* Spread page cache over cpuset */ #define PF_SPREAD_SLAB 0x02000000 /* Spread some slab caches over cpuset */ +#define PF_THREAD_BOUND 0x04000000 /* Thread bound to specific cpu */ #define PF_MEMPOLICY 0x10000000 /* Non-default NUMA mempolicy */ #define PF_MUTEX_TESTER 0x20000000 /* Thread belongs to the rt mutex tester */ #define PF_FREEZER_SKIP 0x40000000 /* Freezer should not count it as freezeable */ +#define PF_FREEZER_NOSIG 0x80000000 /* Freezer won't send signals to it */ /* * Only the _current_ task can read/write to tsk->flags, but other @@ -1971,6 +1957,19 @@ static inline unsigned long *end_of_stack(struct task_struct *p) extern void thread_info_cache_init(void); +#ifdef CONFIG_DEBUG_STACK_USAGE +static inline unsigned long stack_not_used(struct task_struct *p) +{ + unsigned long *n = end_of_stack(p); + + do { /* Skip over canary */ + n++; + } while (!*n); + + return (unsigned long)n - (unsigned long)end_of_stack(p); +} +#endif + /* set thread flags in other task's structures * - see asm/thread_info.h for TIF_xxxx flags available */ @@ -2026,6 +2025,19 @@ static inline int fatal_signal_pending(struct task_struct *p) return signal_pending(p) && __fatal_signal_pending(p); } +static inline int signal_pending_state(long state, struct task_struct *p) +{ + if (!(state & (TASK_INTERRUPTIBLE | TASK_WAKEKILL))) + return 0; + if (!signal_pending(p)) + return 0; + + if (state & (__TASK_STOPPED | __TASK_TRACED)) + return 0; + + return (state & TASK_INTERRUPTIBLE) || __fatal_signal_pending(p); +} + static inline int need_resched(void) { return unlikely(test_thread_flag(TIF_NEED_RESCHED)); @@ -2118,6 +2130,18 @@ static inline void arch_pick_mmap_layout(struct mm_struct *mm) } #endif +#ifdef CONFIG_TRACING +extern void +__trace_special(void *__tr, void *__data, + unsigned long arg1, unsigned long arg2, unsigned long arg3); +#else +static inline void +__trace_special(void *__tr, void *__data, + unsigned long arg1, unsigned long arg2, unsigned long arg3) +{ +} +#endif + extern long sched_setaffinity(pid_t pid, const cpumask_t *new_mask); extern long sched_getaffinity(pid_t pid, cpumask_t *mask); @@ -2212,6 +2236,8 @@ static inline void mm_init_owner(struct mm_struct *mm, struct task_struct *p) } #endif /* CONFIG_MM_OWNER */ +#define TASK_STATE_TO_CHAR_STR "RSDTtZX" + #endif /* __KERNEL__ */ #endif diff --git a/include/linux/security.h b/include/linux/security.h index 50737c70e78e..62bd80cb7f87 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -46,7 +46,8 @@ struct audit_krule; */ extern int cap_capable(struct task_struct *tsk, int cap); extern int cap_settime(struct timespec *ts, struct timezone *tz); -extern int cap_ptrace(struct task_struct *parent, struct task_struct *child); +extern int cap_ptrace(struct task_struct *parent, struct task_struct *child, + unsigned int mode); extern int cap_capget(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); extern int cap_capset_check(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); extern void cap_capset_set(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); @@ -1170,6 +1171,7 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts) * attributes would be changed by the execve. * @parent contains the task_struct structure for parent process. * @child contains the task_struct structure for child process. + * @mode contains the PTRACE_MODE flags indicating the form of access. * Return 0 if permission is granted. * @capget: * Get the @effective, @inheritable, and @permitted capability sets for @@ -1295,7 +1297,8 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts) struct security_operations { char name[SECURITY_NAME_MAX + 1]; - int (*ptrace) (struct task_struct *parent, struct task_struct *child); + int (*ptrace) (struct task_struct *parent, struct task_struct *child, + unsigned int mode); int (*capget) (struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); @@ -1573,7 +1576,8 @@ extern struct dentry *securityfs_create_dir(const char *name, struct dentry *par extern void securityfs_remove(struct dentry *dentry); /* Security operations */ -int security_ptrace(struct task_struct *parent, struct task_struct *child); +int security_ptrace(struct task_struct *parent, struct task_struct *child, + unsigned int mode); int security_capget(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, @@ -1755,9 +1759,11 @@ static inline int security_init(void) return 0; } -static inline int security_ptrace(struct task_struct *parent, struct task_struct *child) +static inline int security_ptrace(struct task_struct *parent, + struct task_struct *child, + unsigned int mode) { - return cap_ptrace(parent, child); + return cap_ptrace(parent, child, mode); } static inline int security_capget(struct task_struct *target, diff --git a/include/linux/semaphore.h b/include/linux/semaphore.h index 7415839ac890..6ea742cac203 100644 --- a/include/linux/semaphore.h +++ b/include/linux/semaphore.h @@ -42,8 +42,12 @@ static inline void sema_init(struct semaphore *sem, int val) extern void down(struct semaphore *sem); extern int __must_check down_interruptible(struct semaphore *sem); extern int __must_check down_killable(struct semaphore *sem); -extern int __must_check down_trylock(struct semaphore *sem); +extern int __must_check down_try(struct semaphore *sem); +/* Old down_trylock() returned the opposite of what was expected. */ +static inline int __deprecated down_trylock(struct semaphore *sem) +{ + return !down_try(sem); +} extern int __must_check down_timeout(struct semaphore *sem, long jiffies); extern void up(struct semaphore *sem); - #endif /* __LINUX_SEMAPHORE_H */ diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index d32123ae08ad..d8f31de632c5 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -192,6 +192,7 @@ struct uart_ops { void (*shutdown)(struct uart_port *); void (*set_termios)(struct uart_port *, struct ktermios *new, struct ktermios *old); + void (*set_ldisc)(struct uart_port *); void (*pm)(struct uart_port *, unsigned int state, unsigned int oldstate); int (*set_wake)(struct uart_port *, unsigned int state); diff --git a/include/linux/slab.h b/include/linux/slab.h index 805ed4b92f9a..c2ad35016599 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -276,6 +276,17 @@ static inline void *kzalloc(size_t size, gfp_t flags) return kmalloc(size, flags | __GFP_ZERO); } +/** + * kzalloc_node - allocate zeroed memory from a particular memory node. + * @size: how many bytes of memory are required. + * @flags: the type of memory to allocate (see kmalloc). + * @node: memory node from which to allocate + */ +static inline void *kzalloc_node(size_t size, gfp_t flags, int node) +{ + return kmalloc_node(size, flags | __GFP_ZERO, node); +} + #ifdef CONFIG_SLABINFO extern const struct seq_operations slabinfo_op; ssize_t slabinfo_write(struct file *, const char __user *, size_t, loff_t *); diff --git a/include/linux/smc911x.h b/include/linux/smc911x.h new file mode 100644 index 000000000000..b58f54c24183 --- /dev/null +++ b/include/linux/smc911x.h @@ -0,0 +1,12 @@ +#ifndef __SMC911X_H__ +#define __SMC911X_H__ + +#define SMC911X_USE_16BIT (1 << 0) +#define SMC911X_USE_32BIT (1 << 1) + +struct smc911x_platdata { + unsigned long flags; + unsigned long irq_flags; /* IRQF_... */ +}; + +#endif /* __SMC911X_H__ */ diff --git a/include/linux/spi/mmc_spi.h b/include/linux/spi/mmc_spi.h index e9bbe3ebd721..a3626aedaec9 100644 --- a/include/linux/spi/mmc_spi.h +++ b/include/linux/spi/mmc_spi.h @@ -1,6 +1,8 @@ #ifndef __LINUX_SPI_MMC_SPI_H #define __LINUX_SPI_MMC_SPI_H +#include <linux/interrupt.h> + struct device; struct mmc_host; @@ -21,6 +23,15 @@ struct mmc_spi_platform_data { /* sense switch on sd cards */ int (*get_ro)(struct device *); + /* + * If board does not use CD interrupts, driver can optimize polling + * using this function. + */ + int (*get_cd)(struct device *); + + /* Capabilities to pass into mmc core (e.g. MMC_CAP_NEEDS_POLL). */ + unsigned long caps; + /* how long to debounce card detect, in msecs */ u16 detect_delay; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 387e428f1cdf..b9a76c972084 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -733,7 +733,7 @@ struct spi_board_info { * controller_data goes to spi_device.controller_data, * irq is copied too */ - char modalias[KOBJ_NAME_LEN]; + char modalias[32]; const void *platform_data; void *controller_data; int irq; diff --git a/include/linux/ssb/ssb_driver_gige.h b/include/linux/ssb/ssb_driver_gige.h index 01fbdf5fef22..942e38736901 100644 --- a/include/linux/ssb/ssb_driver_gige.h +++ b/include/linux/ssb/ssb_driver_gige.h @@ -100,7 +100,7 @@ extern char * nvram_get(const char *name); /* Get the device MAC address */ static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr) { -#ifdef CONFIG_BCM947XX +#ifdef CONFIG_BCM47XX char *res = nvram_get("et0macaddr"); if (res) memcpy(macaddr, res, 6); diff --git a/include/linux/stackprotector.h b/include/linux/stackprotector.h new file mode 100644 index 000000000000..6f3e54c704c0 --- /dev/null +++ b/include/linux/stackprotector.h @@ -0,0 +1,16 @@ +#ifndef _LINUX_STACKPROTECTOR_H +#define _LINUX_STACKPROTECTOR_H 1 + +#include <linux/compiler.h> +#include <linux/sched.h> +#include <linux/random.h> + +#ifdef CONFIG_CC_STACKPROTECTOR +# include <asm/stackprotector.h> +#else +static inline void boot_init_stack_canary(void) +{ +} +#endif + +#endif diff --git a/include/linux/stop_machine.h b/include/linux/stop_machine.h index 5bfc553bdb21..23c1b0d0f020 100644 --- a/include/linux/stop_machine.h +++ b/include/linux/stop_machine.h @@ -5,14 +5,18 @@ (and more). So the "read" side to such a lock is anything which diables preeempt. */ #include <linux/cpu.h> +#include <linux/compiler.h> #include <asm/system.h> -#if defined(CONFIG_STOP_MACHINE) && defined(CONFIG_SMP) +#define ALL_CPUS ~0U + /** * stop_machine_run: freeze the machine on all CPUs and run this function * @fn: the function to run * @data: the data ptr for the @fn() - * @cpu: the cpu to run @fn() on (or any, if @cpu == NR_CPUS. + * @cpu: if @cpu == n, run @fn() on cpu n + * if @cpu == NR_CPUS, run @fn() on any cpu + * if @cpu == ALL_CPUS, run @fn() on every online CPU. * * Description: This causes a thread to be scheduled on every other cpu, * each of which disables interrupts, and finally interrupts are disabled @@ -21,7 +25,11 @@ * * This can be thought of as a very heavy write lock, equivalent to * grabbing every spinlock in the kernel. */ -int stop_machine_run(int (*fn)(void *), void *data, unsigned int cpu); +#define stop_machine_run(fn, data, cpu) \ + stop_machine_run_notype(typesafe_cb(int, (fn), (data)), (data), (cpu)) + +#if defined(CONFIG_STOP_MACHINE) && defined(CONFIG_SMP) +int stop_machine_run_notype(int (*fn)(void *), void *data, unsigned int cpu); /** * __stop_machine_run: freeze the machine on all CPUs and run this function @@ -29,17 +37,14 @@ int stop_machine_run(int (*fn)(void *), void *data, unsigned int cpu); * @data: the data ptr for the @fn * @cpu: the cpu to run @fn on (or any, if @cpu == NR_CPUS. * - * Description: This is a special version of the above, which returns the - * thread which has run @fn(): kthread_stop will return the return value - * of @fn(). Used by hotplug cpu. + * Description: This is a special version of the above, which assumes cpus + * won't come or go while it's being called. Used by hotplug cpu. */ -struct task_struct *__stop_machine_run(int (*fn)(void *), void *data, - unsigned int cpu); - +int __stop_machine_run(int (*fn)(void *), void *data, unsigned int cpu); #else -static inline int stop_machine_run(int (*fn)(void *), void *data, - unsigned int cpu) +static inline int stop_machine_run_notype(int (*fn)(void *), void *data, + unsigned int cpu) { int ret; local_irq_disable(); diff --git a/include/linux/sunrpc/auth_gss.h b/include/linux/sunrpc/auth_gss.h index fec6899bf355..d48d4e605f74 100644 --- a/include/linux/sunrpc/auth_gss.h +++ b/include/linux/sunrpc/auth_gss.h @@ -7,8 +7,6 @@ * Andy Adamson <andros@umich.edu> * Bruce Fields <bfields@umich.edu> * Copyright (c) 2000 The Regents of the University of Michigan - * - * $Id$ */ #ifndef _LINUX_SUNRPC_AUTH_GSS_H diff --git a/include/linux/sunrpc/gss_api.h b/include/linux/sunrpc/gss_api.h index 459c5fc11d51..03f33330ece2 100644 --- a/include/linux/sunrpc/gss_api.h +++ b/include/linux/sunrpc/gss_api.h @@ -7,8 +7,6 @@ * Andy Adamson <andros@umich.edu> * Bruce Fields <bfields@umich.edu> * Copyright (c) 2000 The Regents of the University of Michigan - * - * $Id$ */ #ifndef _LINUX_SUNRPC_GSS_API_H diff --git a/include/linux/sunrpc/gss_krb5.h b/include/linux/sunrpc/gss_krb5.h index a10f1fb0bf7c..5bb227e00b41 100644 --- a/include/linux/sunrpc/gss_krb5.h +++ b/include/linux/sunrpc/gss_krb5.h @@ -40,6 +40,12 @@ #include <linux/sunrpc/gss_err.h> #include <linux/sunrpc/gss_asn1.h> +/* Maximum checksum function output for the supported crypto algorithms */ +#define GSS_KRB5_MAX_CKSUM_LEN (20) + +/* Maximum blocksize for the supported crypto algorithms */ +#define GSS_KRB5_MAX_BLOCKSIZE (16) + struct krb5_ctx { int initiate; /* 1 = initiating, 0 = accepting */ struct crypto_blkcipher *enc; @@ -51,6 +57,9 @@ struct krb5_ctx { extern spinlock_t krb5_seq_lock; +/* The length of the Kerberos GSS token header */ +#define GSS_KRB5_TOK_HDR_LEN (16) + #define KG_TOK_MIC_MSG 0x0101 #define KG_TOK_WRAP_MSG 0x0201 @@ -110,6 +119,22 @@ enum seal_alg { #define ENCTYPE_DES3_CBC_SHA1 0x0010 #define ENCTYPE_UNKNOWN 0x01ff +/* + * This compile-time check verifies that we will not exceed the + * slack space allotted by the client and server auth_gss code + * before they call gss_wrap(). + */ +#define GSS_KRB5_SLACK_CHECK \ + BUILD_BUG_ON(GSS_KRB5_TOK_HDR_LEN /* gss token header */ \ + + GSS_KRB5_MAX_CKSUM_LEN /* gss token checksum */ \ + + GSS_KRB5_MAX_BLOCKSIZE /* confounder */ \ + + GSS_KRB5_MAX_BLOCKSIZE /* possible padding */ \ + + GSS_KRB5_TOK_HDR_LEN /* encrypted hdr in v2 token */\ + + GSS_KRB5_MAX_CKSUM_LEN /* encryption hmac */ \ + + 4 + 4 /* RPC verifier */ \ + + GSS_KRB5_TOK_HDR_LEN \ + + GSS_KRB5_MAX_CKSUM_LEN > RPC_MAX_AUTH_SIZE) + s32 make_checksum(char *, char *header, int hdrlen, struct xdr_buf *body, int body_offset, struct xdr_netobj *cksum); @@ -154,3 +179,6 @@ s32 krb5_get_seq_num(struct crypto_blkcipher *key, unsigned char *cksum, unsigned char *buf, int *direction, u32 *seqnum); + +int +shift_head_data(struct xdr_buf *buf, unsigned int base, unsigned int shiftlen); diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h index 4b54c5fdcfd9..dc69068d94c7 100644 --- a/include/linux/sunrpc/svc.h +++ b/include/linux/sunrpc/svc.h @@ -22,7 +22,7 @@ /* * This is the RPC server thread function prototype */ -typedef void (*svc_thread_fn)(struct svc_rqst *); +typedef int (*svc_thread_fn)(void *); /* * @@ -80,7 +80,6 @@ struct svc_serv { struct module * sv_module; /* optional module to count when * adding threads */ svc_thread_fn sv_function; /* main function for threads */ - int sv_kill_signal; /* signal to kill threads */ }; /* @@ -388,8 +387,8 @@ struct svc_rqst *svc_prepare_thread(struct svc_serv *serv, struct svc_pool *pool); void svc_exit_thread(struct svc_rqst *); struct svc_serv * svc_create_pooled(struct svc_program *, unsigned int, - void (*shutdown)(struct svc_serv*), - svc_thread_fn, int sig, struct module *); + void (*shutdown)(struct svc_serv*), svc_thread_fn, + struct module *); int svc_set_num_threads(struct svc_serv *, struct svc_pool *, int); void svc_destroy(struct svc_serv *); int svc_process(struct svc_rqst *); diff --git a/include/linux/sunrpc/svc_rdma.h b/include/linux/sunrpc/svc_rdma.h index 05eb4664d0dd..ef2e3a20bf3b 100644 --- a/include/linux/sunrpc/svc_rdma.h +++ b/include/linux/sunrpc/svc_rdma.h @@ -72,7 +72,7 @@ extern atomic_t rdma_stat_sq_prod; */ struct svc_rdma_op_ctxt { struct svc_rdma_op_ctxt *read_hdr; - struct list_head free_list; + int hdr_count; struct xdr_buf arg; struct list_head dto_q; enum ib_wr_opcode wr_op; @@ -86,6 +86,31 @@ struct svc_rdma_op_ctxt { struct page *pages[RPCSVC_MAXPAGES]; }; +/* + * NFS_ requests are mapped on the client side by the chunk lists in + * the RPCRDMA header. During the fetching of the RPC from the client + * and the writing of the reply to the client, the memory in the + * client and the memory in the server must be mapped as contiguous + * vaddr/len for access by the hardware. These data strucures keep + * these mappings. + * + * For an RDMA_WRITE, the 'sge' maps the RPC REPLY. For RDMA_READ, the + * 'sge' in the svc_rdma_req_map maps the server side RPC reply and the + * 'ch' field maps the read-list of the RPCRDMA header to the 'sge' + * mapping of the reply. + */ +struct svc_rdma_chunk_sge { + int start; /* sge no for this chunk */ + int count; /* sge count for this chunk */ +}; +struct svc_rdma_req_map { + unsigned long count; + union { + struct kvec sge[RPCSVC_MAXPAGES]; + struct svc_rdma_chunk_sge ch[RPCSVC_MAXPAGES]; + }; +}; + #define RDMACTXT_F_LAST_CTXT 2 struct svcxprt_rdma { @@ -93,7 +118,6 @@ struct svcxprt_rdma { struct rdma_cm_id *sc_cm_id; /* RDMA connection id */ struct list_head sc_accept_q; /* Conn. waiting accept */ int sc_ord; /* RDMA read limit */ - wait_queue_head_t sc_read_wait; int sc_max_sge; int sc_sq_depth; /* Depth of SQ */ @@ -104,12 +128,8 @@ struct svcxprt_rdma { struct ib_pd *sc_pd; + atomic_t sc_dma_used; atomic_t sc_ctxt_used; - struct list_head sc_ctxt_free; - int sc_ctxt_cnt; - int sc_ctxt_bump; - int sc_ctxt_max; - spinlock_t sc_ctxt_lock; struct list_head sc_rq_dto_q; spinlock_t sc_rq_dto_lock; struct ib_qp *sc_qp; @@ -173,6 +193,8 @@ extern int svc_rdma_post_recv(struct svcxprt_rdma *); extern int svc_rdma_create_listen(struct svc_serv *, int, struct sockaddr *); extern struct svc_rdma_op_ctxt *svc_rdma_get_context(struct svcxprt_rdma *); extern void svc_rdma_put_context(struct svc_rdma_op_ctxt *, int); +extern struct svc_rdma_req_map *svc_rdma_get_req_map(void); +extern void svc_rdma_put_req_map(struct svc_rdma_req_map *); extern void svc_sq_reap(struct svcxprt_rdma *); extern void svc_rq_reap(struct svcxprt_rdma *); extern struct svc_xprt_class svc_rdma_class; diff --git a/include/linux/sunrpc/svcauth_gss.h b/include/linux/sunrpc/svcauth_gss.h index 417a1def56db..c9165d9771a8 100644 --- a/include/linux/sunrpc/svcauth_gss.h +++ b/include/linux/sunrpc/svcauth_gss.h @@ -3,9 +3,6 @@ * * Bruce Fields <bfields@umich.edu> * Copyright (c) 2002 The Regents of the Unviersity of Michigan - * - * $Id$ - * */ #ifndef _LINUX_SUNRPC_SVCAUTH_GSS_H diff --git a/include/linux/suspend.h b/include/linux/suspend.h index a6977423baf7..e8e69159af71 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -86,6 +86,11 @@ typedef int __bitwise suspend_state_t; * that implement @begin(), but platforms implementing @begin() should * also provide a @end() which cleans up transitions aborted before * @enter(). + * + * @recover: Recover the platform from a suspend failure. + * Called by the PM core if the suspending of devices fails. + * This callback is optional and should only be implemented by platforms + * which require special recovery actions in that situation. */ struct platform_suspend_ops { int (*valid)(suspend_state_t state); @@ -94,6 +99,7 @@ struct platform_suspend_ops { int (*enter)(suspend_state_t state); void (*finish)(void); void (*end)(void); + void (*recover)(void); }; #ifdef CONFIG_SUSPEND @@ -149,7 +155,7 @@ extern void mark_free_pages(struct zone *zone); * The methods in this structure allow a platform to carry out special * operations required by it during a hibernation transition. * - * All the methods below must be implemented. + * All the methods below, except for @recover(), must be implemented. * * @begin: Tell the platform driver that we're starting hibernation. * Called right after shrinking memory and before freezing devices. @@ -189,6 +195,11 @@ extern void mark_free_pages(struct zone *zone); * @restore_cleanup: Clean up after a failing image restoration. * Called right after the nonboot CPUs have been enabled and before * thawing devices (runs with IRQs on). + * + * @recover: Recover the platform from a failure to suspend devices. + * Called by the PM core if the suspending of devices during hibernation + * fails. This callback is optional and should only be implemented by + * platforms which require special recovery actions in that situation. */ struct platform_hibernation_ops { int (*begin)(void); @@ -200,6 +211,7 @@ struct platform_hibernation_ops { void (*leave)(void); int (*pre_restore)(void); void (*restore_cleanup)(void); + void (*recover)(void); }; #ifdef CONFIG_HIBERNATION diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h index 7858eac40aa7..84d92bb06333 100644 --- a/include/linux/sysfs.h +++ b/include/linux/sysfs.h @@ -20,6 +20,8 @@ struct kobject; struct module; +extern int kobject_set_name(struct kobject *kobj, const char *name, ...) + __attribute__((format(printf, 2, 3))); /* FIXME * The *owner field is no longer used, but leave around * until the tree gets cleaned up fully. @@ -115,6 +117,7 @@ void sysfs_remove_file_from_group(struct kobject *kobj, const struct attribute *attr, const char *group); void sysfs_notify(struct kobject *kobj, char *dir, char *attr); +void sysfs_printk_last_file(void); extern int __must_check sysfs_init(void); @@ -137,7 +140,7 @@ static inline void sysfs_remove_dir(struct kobject *kobj) static inline int sysfs_rename_dir(struct kobject *kobj, const char *new_name) { - return 0; + return kobject_set_name(kobj, "%s", new_name); } static inline int sysfs_move_dir(struct kobject *kobj, @@ -221,6 +224,10 @@ static inline int __must_check sysfs_init(void) return 0; } +static inline void sysfs_printk_last_file(void) +{ +} + #endif /* CONFIG_SYSFS */ #endif /* _SYSFS_H_ */ diff --git a/include/linux/tcp.h b/include/linux/tcp.h index 18e62e3d406f..07e79bdb9cdf 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -239,11 +239,6 @@ static inline struct tcp_request_sock *tcp_rsk(const struct request_sock *req) return (struct tcp_request_sock *)req; } -struct tcp_deferred_accept_info { - struct sock *listen_sk; - struct request_sock *request; -}; - struct tcp_sock { /* inet_connection_sock has to be the first member of tcp_sock */ struct inet_connection_sock inet_conn; @@ -296,10 +291,9 @@ struct tcp_sock { u32 rcv_ssthresh; /* Current window clamp */ u32 frto_highmark; /* snd_nxt when RTO occurred */ - u8 reordering; /* Packet reordering metric. */ + u16 advmss; /* Advertised MSS */ u8 frto_counter; /* Number of new acks after RTO */ u8 nonagle; /* Disable Nagle algorithm? */ - u8 keepalive_probes; /* num of allowed keep alive probes */ /* RTT measurement */ u32 srtt; /* smoothed round trip time << 3 */ @@ -310,6 +304,10 @@ struct tcp_sock { u32 packets_out; /* Packets which are "in flight" */ u32 retrans_out; /* Retransmitted packets out */ + + u16 urg_data; /* Saved octet of OOB data and control flags */ + u8 urg_mode; /* In urgent mode */ + u8 ecn_flags; /* ECN status bits. */ /* * Options received (usually on last packet, some only on SYN packets). */ @@ -325,13 +323,24 @@ struct tcp_sock { u32 snd_cwnd_used; u32 snd_cwnd_stamp; - struct sk_buff_head out_of_order_queue; /* Out of order segments go here */ - u32 rcv_wnd; /* Current receiver window */ u32 write_seq; /* Tail(+1) of data held in tcp send buffer */ u32 pushed_seq; /* Last pushed seq, required to talk to windows */ + u32 lost_out; /* Lost packets */ + u32 sacked_out; /* SACK'd packets */ + u32 fackets_out; /* FACK'd packets */ + u32 tso_deferred; + u32 bytes_acked; /* Appropriate Byte Counting - RFC3465 */ -/* SACKs data */ + /* from STCP, retrans queue hinting */ + struct sk_buff* lost_skb_hint; + struct sk_buff *scoreboard_skb_hint; + struct sk_buff *retransmit_skb_hint; + struct sk_buff *forward_skb_hint; + + struct sk_buff_head out_of_order_queue; /* Out of order segments go here */ + + /* SACKs data, these 2 need to be together (see tcp_build_and_update_options) */ struct tcp_sack_block duplicate_sack[1]; /* D-SACK block */ struct tcp_sack_block selective_acks[4]; /* The SACKS themselves*/ @@ -342,23 +351,14 @@ struct tcp_sock { * sacked_out > 0) */ - /* from STCP, retrans queue hinting */ - struct sk_buff* lost_skb_hint; - - struct sk_buff *scoreboard_skb_hint; - struct sk_buff *retransmit_skb_hint; - struct sk_buff *forward_skb_hint; - int lost_cnt_hint; int retransmit_cnt_hint; u32 lost_retrans_low; /* Sent seq after any rxmit (lowest) */ - u16 advmss; /* Advertised MSS */ + u8 reordering; /* Packet reordering metric. */ + u8 keepalive_probes; /* num of allowed keep alive probes */ u32 prior_ssthresh; /* ssthresh saved at recovery start */ - u32 lost_out; /* Lost packets */ - u32 sacked_out; /* SACK'd packets */ - u32 fackets_out; /* FACK'd packets */ u32 high_seq; /* snd_nxt at onset of congestion */ u32 retrans_stamp; /* Timestamp of the last retransmit, @@ -366,25 +366,16 @@ struct tcp_sock { * the first SYN. */ u32 undo_marker; /* tracking retrans started here. */ int undo_retrans; /* number of undoable retransmissions. */ + u32 total_retrans; /* Total retransmits for entire connection */ + u32 urg_seq; /* Seq of received urgent pointer */ - u16 urg_data; /* Saved octet of OOB data and control flags */ - u8 urg_mode; /* In urgent mode */ - u8 ecn_flags; /* ECN status bits. */ u32 snd_up; /* Urgent pointer */ - u32 total_retrans; /* Total retransmits for entire connection */ - u32 bytes_acked; /* Appropriate Byte Counting - RFC3465 */ - unsigned int keepalive_time; /* time before keep alive takes place */ unsigned int keepalive_intvl; /* time interval between keep alive probes */ - int linger2; - - struct tcp_deferred_accept_info defer_tcp_accept; unsigned long last_synq_overflow; - u32 tso_deferred; - /* Receiver side RTT estimation */ struct { u32 rtt; @@ -412,6 +403,8 @@ struct tcp_sock { /* TCP MD5 Signagure Option information */ struct tcp_md5sig_info *md5sig_info; #endif + + int linger2; }; static inline struct tcp_sock *tcp_sk(const struct sock *sk) diff --git a/include/linux/time.h b/include/linux/time.h index d32ef0ad4c0a..e15206a7e82e 100644 --- a/include/linux/time.h +++ b/include/linux/time.h @@ -6,6 +6,7 @@ #ifdef __KERNEL__ # include <linux/cache.h> # include <linux/seqlock.h> +# include <linux/math64.h> #endif #ifndef _STRUCT_TIMESPEC @@ -169,18 +170,13 @@ extern struct timeval ns_to_timeval(const s64 nsec); * timespec_add_ns - Adds nanoseconds to a timespec * @a: pointer to timespec to be incremented * @ns: unsigned nanoseconds value to be added + * + * This must always be inlined because its used from the x86-64 vdso, + * which cannot call other kernel functions. */ -static inline void timespec_add_ns(struct timespec *a, u64 ns) +static __always_inline void timespec_add_ns(struct timespec *a, u64 ns) { - ns += a->tv_nsec; - while(unlikely(ns >= NSEC_PER_SEC)) { - /* The following asm() prevents the compiler from - * optimising this loop into a modulo operation. */ - asm("" : "+r"(ns)); - - ns -= NSEC_PER_SEC; - a->tv_sec++; - } + a->tv_sec += __iter_div_u64_rem(a->tv_nsec + ns, NSEC_PER_SEC, &ns); a->tv_nsec = ns; } #endif /* __KERNEL__ */ diff --git a/include/linux/timer.h b/include/linux/timer.h index d4ba79248a27..1baf40162b8c 100644 --- a/include/linux/timer.h +++ b/include/linux/timer.h @@ -25,12 +25,22 @@ struct timer_list { extern struct tvec_base boot_tvec_bases; -#define TIMER_INITIALIZER(_function, _expires, _data) { \ - .entry = { .prev = TIMER_ENTRY_STATIC }, \ - .function = (_function), \ - .expires = (_expires), \ - .data = (_data), \ - .base = &boot_tvec_bases, \ +/* + * For historic reasons the timer function takes an unsigned long, so + * we use this variant of typesafe_cb. data is converted to an unsigned long + * if it is another integer type, by adding 0UL. + */ +#define typesafe_timerfn(fn, data) \ + __typesafe_cb(void (*)(unsigned long), (fn), \ + void (*)(const typeof((data)+0UL)), \ + void (*)(typeof((data)+0UL))) + +#define TIMER_INITIALIZER(_function, _expires, _data) { \ + .entry = { .prev = TIMER_ENTRY_STATIC }, \ + .function = typesafe_timerfn((_function), (_data)), \ + .expires = (_expires), \ + .data = (unsigned long)(_data), \ + .base = &boot_tvec_bases, \ } #define DEFINE_TIMER(_name, _function, _expires, _data) \ @@ -51,9 +61,13 @@ static inline void init_timer_on_stack(struct timer_list *timer) } #endif -static inline void setup_timer(struct timer_list * timer, - void (*function)(unsigned long), - unsigned long data) +#define setup_timer(timer, function, data) \ + __setup_timer((timer), typesafe_timerfn((function), (data)), \ + (unsigned long)(data)) + +static inline void __setup_timer(struct timer_list *timer, + void (*function)(unsigned long), + unsigned long data) { timer->function = function; timer->data = data; diff --git a/include/linux/tipc_config.h b/include/linux/tipc_config.h index b0c916d1f375..2bc6fa4adeb5 100644 --- a/include/linux/tipc_config.h +++ b/include/linux/tipc_config.h @@ -2,7 +2,7 @@ * include/linux/tipc_config.h: Include file for TIPC configuration interface * * Copyright (c) 2003-2006, Ericsson AB - * Copyright (c) 2005, Wind River Systems + * Copyright (c) 2005-2007, Wind River Systems * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -136,6 +136,14 @@ #define TIPC_CMD_SET_NETID 0x800B /* tx unsigned, rx none */ /* + * Reserved commands: + * May not be issued by any process. + * Used internally by TIPC. + */ + +#define TIPC_CMD_NOT_NET_ADMIN 0xC001 /* tx none, rx none */ + +/* * TLV types defined for TIPC */ diff --git a/include/linux/topology.h b/include/linux/topology.h index 24f3d2282e11..2158fc0d5a56 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -179,4 +179,17 @@ void arch_update_cpu_topology(void); #endif #endif /* CONFIG_NUMA */ +#ifndef topology_physical_package_id +#define topology_physical_package_id(cpu) ((void)(cpu), -1) +#endif +#ifndef topology_core_id +#define topology_core_id(cpu) ((void)(cpu), 0) +#endif +#ifndef topology_thread_siblings +#define topology_thread_siblings(cpu) cpumask_of_cpu(cpu) +#endif +#ifndef topology_core_siblings +#define topology_core_siblings(cpu) cpumask_of_cpu(cpu) +#endif + #endif /* _LINUX_TOPOLOGY_H */ diff --git a/include/linux/tty.h b/include/linux/tty.h index 7f7121f9c968..324a3b231d40 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -36,7 +36,7 @@ #define N_6PACK 7 #define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */ #define N_R3964 9 /* Reserved for Simatic R3964 module */ -#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */ +#define N_PROFIBUS_FDL 10 /* Reserved for Profibus */ #define N_IRDA 11 /* Linux IrDa - http://irda.sourceforge.net/ */ #define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data */ /* cards about SMS messages */ diff --git a/include/linux/uio_driver.h b/include/linux/uio_driver.h index 973386d439da..cdf338d94b7f 100644 --- a/include/linux/uio_driver.h +++ b/include/linux/uio_driver.h @@ -36,7 +36,7 @@ struct uio_mem { struct uio_map *map; }; -#define MAX_UIO_MAPS 5 +#define MAX_UIO_MAPS 5 struct uio_device; @@ -53,6 +53,7 @@ struct uio_device; * @mmap: mmap operation for this uio device * @open: open operation for this uio device * @release: release operation for this uio device + * @irqcontrol: disable/enable irqs when 0/1 is written to /dev/uioX */ struct uio_info { struct uio_device *uio_dev; @@ -66,6 +67,7 @@ struct uio_info { int (*mmap)(struct uio_info *info, struct vm_area_struct *vma); int (*open)(struct uio_info *info, struct inode *inode); int (*release)(struct uio_info *info, struct inode *inode); + int (*irqcontrol)(struct uio_info *info, s32 irq_on); }; extern int __must_check @@ -80,11 +82,11 @@ static inline int __must_check extern void uio_unregister_device(struct uio_info *info); extern void uio_event_notify(struct uio_info *info); -/* defines for uio_device->irq */ +/* defines for uio_info->irq */ #define UIO_IRQ_CUSTOM -1 #define UIO_IRQ_NONE -2 -/* defines for uio_device->memtype */ +/* defines for uio_mem->memtype */ #define UIO_MEM_NONE 0 #define UIO_MEM_PHYS 1 #define UIO_MEM_LOGICAL 2 diff --git a/include/linux/usb.h b/include/linux/usb.h index c08689ea9b4b..6e6adde7523d 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -293,7 +293,7 @@ struct usb_devmap { struct usb_bus { struct device *controller; /* host/master side hardware */ int busnum; /* Bus number (in order of reg) */ - char *bus_name; /* stable id (PCI slot_name etc) */ + const char *bus_name; /* stable id (PCI slot_name etc) */ u8 uses_dma; /* Does the host controller use DMA? */ u8 otg_port; /* 0, or number of OTG/HNP port */ unsigned is_b_host:1; /* true during some HNP roleswitches */ @@ -375,6 +375,7 @@ struct usb_tt; * FIXME -- complete doc * @authenticated: Crypto authentication passed * @wusb: device is Wireless USB + * @delayed_reset: delayed reset is in progress, or not * @string_langid: language ID for strings * @product: iProduct string, if present (static) * @manufacturer: iManufacturer string, if present (static) @@ -442,6 +443,7 @@ struct usb_device { unsigned authorized:1; unsigned authenticated:1; unsigned wusb:1; + unsigned delayed_reset:1; int string_langid; /* static strings from the device */ @@ -491,7 +493,7 @@ extern void usb_put_dev(struct usb_device *dev); /* USB device locking */ #define usb_lock_device(udev) down(&(udev)->dev.sem) #define usb_unlock_device(udev) up(&(udev)->dev.sem) -#define usb_trylock_device(udev) down_trylock(&(udev)->dev.sem) +#define usb_trylock_device(udev) down_try(&(udev)->dev.sem) extern int usb_lock_device_for_reset(struct usb_device *udev, const struct usb_interface *iface); @@ -499,6 +501,7 @@ extern int usb_lock_device_for_reset(struct usb_device *udev, extern int usb_reset_device(struct usb_device *dev); extern int usb_reset_composite_device(struct usb_device *dev, struct usb_interface *iface); +extern void usb_dev_reset_delayed(struct usb_device *usb_dev); extern struct usb_device *usb_find_device(u16 vendor_id, u16 product_id); @@ -972,6 +975,8 @@ struct usbdrv_wrap { * added to this driver by preventing the sysfs file from being created. * @supports_autosuspend: if set to 0, the USB core will not allow autosuspend * for interfaces bound to this driver. + * @soft_unbind: if set to 1, the USB core will not kill URBs and disable + * endpoints before calling the driver's disconnect method. * * USB interface drivers must provide a name, probe() and disconnect() * methods, and an id_table. Other driver fields are optional. @@ -1012,6 +1017,7 @@ struct usb_driver { struct usbdrv_wrap drvwrap; unsigned int no_dynamic_id:1; unsigned int supports_autosuspend:1; + unsigned int soft_unbind:1; }; #define to_usb_driver(d) container_of(d, struct usb_driver, drvwrap.driver) diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h new file mode 100644 index 000000000000..747c3a49cdc9 --- /dev/null +++ b/include/linux/usb/composite.h @@ -0,0 +1,338 @@ +/* + * composite.h -- framework for usb gadgets which are composite devices + * + * Copyright (C) 2006-2008 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __LINUX_USB_COMPOSITE_H +#define __LINUX_USB_COMPOSITE_H + +/* + * This framework is an optional layer on top of the USB Gadget interface, + * making it easier to build (a) Composite devices, supporting multiple + * functions within any single configuration, and (b) Multi-configuration + * devices, also supporting multiple functions but without necessarily + * having more than one function per configuration. + * + * Example: a device with a single configuration supporting both network + * link and mass storage functions is a composite device. Those functions + * might alternatively be packaged in individual configurations, but in + * the composite model the host can use both functions at the same time. + */ + +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> + + +struct usb_configuration; + +/** + * struct usb_function - describes one function of a configuration + * @name: For diagnostics, identifies the function. + * @strings: tables of strings, keyed by identifiers assigned during bind() + * and by language IDs provided in control requests + * @descriptors: Table of full (or low) speed descriptors, using interface and + * string identifiers assigned during @bind(). If this pointer is null, + * the function will not be available at full speed (or at low speed). + * @hs_descriptors: Table of high speed descriptors, using interface and + * string identifiers assigned during @bind(). If this pointer is null, + * the function will not be available at high speed. + * @config: assigned when @usb_add_function() is called; this is the + * configuration with which this function is associated. + * @bind: Before the gadget can register, all of its functions bind() to the + * available resources including string and interface identifiers used + * in interface or class descriptors; endpoints; I/O buffers; and so on. + * @unbind: Reverses @bind; called as a side effect of unregistering the + * driver which added this function. + * @set_alt: (REQUIRED) Reconfigures altsettings; function drivers may + * initialize usb_ep.driver data at this time (when it is used). + * Note that setting an interface to its current altsetting resets + * interface state, and that all interfaces have a disabled state. + * @get_alt: Returns the active altsetting. If this is not provided, + * then only altsetting zero is supported. + * @disable: (REQUIRED) Indicates the function should be disabled. Reasons + * include host resetting or reconfiguring the gadget, and disconnection. + * @setup: Used for interface-specific control requests. + * @suspend: Notifies functions when the host stops sending USB traffic. + * @resume: Notifies functions when the host restarts USB traffic. + * + * A single USB function uses one or more interfaces, and should in most + * cases support operation at both full and high speeds. Each function is + * associated by @usb_add_function() with a one configuration; that function + * causes @bind() to be called so resources can be allocated as part of + * setting up a gadget driver. Those resources include endpoints, which + * should be allocated using @usb_ep_autoconfig(). + * + * To support dual speed operation, a function driver provides descriptors + * for both high and full speed operation. Except in rare cases that don't + * involve bulk endpoints, each speed needs different endpoint descriptors. + * + * Function drivers choose their own strategies for managing instance data. + * The simplest strategy just declares it "static', which means the function + * can only be activated once. If the function needs to be exposed in more + * than one configuration at a given speed, it needs to support multiple + * usb_function structures (one for each configuration). + * + * A more complex strategy might encapsulate a @usb_function structure inside + * a driver-specific instance structure to allows multiple activations. An + * example of multiple activations might be a CDC ACM function that supports + * two or more distinct instances within the same configuration, providing + * several independent logical data links to a USB host. + */ +struct usb_function { + const char *name; + struct usb_gadget_strings **strings; + struct usb_descriptor_header **descriptors; + struct usb_descriptor_header **hs_descriptors; + + struct usb_configuration *config; + + /* REVISIT: bind() functions can be marked __init, which + * makes trouble for section mismatch analysis. See if + * we can't restructure things to avoid mismatching. + * Related: unbind() may kfree() but bind() won't... + */ + + /* configuration management: bind/unbind */ + int (*bind)(struct usb_configuration *, + struct usb_function *); + void (*unbind)(struct usb_configuration *, + struct usb_function *); + + /* runtime state management */ + int (*set_alt)(struct usb_function *, + unsigned interface, unsigned alt); + int (*get_alt)(struct usb_function *, + unsigned interface); + void (*disable)(struct usb_function *); + int (*setup)(struct usb_function *, + const struct usb_ctrlrequest *); + void (*suspend)(struct usb_function *); + void (*resume)(struct usb_function *); + + /* internals */ + struct list_head list; +}; + +int usb_add_function(struct usb_configuration *, struct usb_function *); + +int usb_interface_id(struct usb_configuration *, struct usb_function *); + +/** + * ep_choose - select descriptor endpoint at current device speed + * @g: gadget, connected and running at some speed + * @hs: descriptor to use for high speed operation + * @fs: descriptor to use for full or low speed operation + */ +static inline struct usb_endpoint_descriptor * +ep_choose(struct usb_gadget *g, struct usb_endpoint_descriptor *hs, + struct usb_endpoint_descriptor *fs) +{ + if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH) + return hs; + return fs; +} + +#define MAX_CONFIG_INTERFACES 16 /* arbitrary; max 255 */ + +/** + * struct usb_configuration - represents one gadget configuration + * @label: For diagnostics, describes the configuration. + * @strings: Tables of strings, keyed by identifiers assigned during @bind() + * and by language IDs provided in control requests. + * @descriptors: Table of descriptors preceding all function descriptors. + * Examples include OTG and vendor-specific descriptors. + * @bind: Called from @usb_add_config() to allocate resources unique to this + * configuration and to call @usb_add_function() for each function used. + * @unbind: Reverses @bind; called as a side effect of unregistering the + * driver which added this configuration. + * @setup: Used to delegate control requests that aren't handled by standard + * device infrastructure or directed at a specific interface. + * @bConfigurationValue: Copied into configuration descriptor. + * @iConfiguration: Copied into configuration descriptor. + * @bmAttributes: Copied into configuration descriptor. + * @bMaxPower: Copied into configuration descriptor. + * @cdev: assigned by @usb_add_config() before calling @bind(); this is + * the device associated with this configuration. + * + * Configurations are building blocks for gadget drivers structured around + * function drivers. Simple USB gadgets require only one function and one + * configuration, and handle dual-speed hardware by always providing the same + * functionality. Slightly more complex gadgets may have more than one + * single-function configuration at a given speed; or have configurations + * that only work at one speed. + * + * Composite devices are, by definition, ones with configurations which + * include more than one function. + * + * The lifecycle of a usb_configuration includes allocation, initialization + * of the fields described above, and calling @usb_add_config() to set up + * internal data and bind it to a specific device. The configuration's + * @bind() method is then used to initialize all the functions and then + * call @usb_add_function() for them. + * + * Those functions would normally be independant of each other, but that's + * not mandatory. CDC WMC devices are an example where functions often + * depend on other functions, with some functions subsidiary to others. + * Such interdependency may be managed in any way, so long as all of the + * descriptors complete by the time the composite driver returns from + * its bind() routine. + */ +struct usb_configuration { + const char *label; + struct usb_gadget_strings **strings; + const struct usb_descriptor_header **descriptors; + + /* REVISIT: bind() functions can be marked __init, which + * makes trouble for section mismatch analysis. See if + * we can't restructure things to avoid mismatching... + */ + + /* configuration management: bind/unbind */ + int (*bind)(struct usb_configuration *); + void (*unbind)(struct usb_configuration *); + int (*setup)(struct usb_configuration *, + const struct usb_ctrlrequest *); + + /* fields in the config descriptor */ + u8 bConfigurationValue; + u8 iConfiguration; + u8 bmAttributes; + u8 bMaxPower; + + struct usb_composite_dev *cdev; + + /* internals */ + struct list_head list; + struct list_head functions; + u8 next_interface_id; + unsigned highspeed:1; + unsigned fullspeed:1; + struct usb_function *interface[MAX_CONFIG_INTERFACES]; +}; + +int usb_add_config(struct usb_composite_dev *, + struct usb_configuration *); + +/** + * struct usb_composite_driver - groups configurations into a gadget + * @name: For diagnostics, identifies the driver. + * @dev: Template descriptor for the device, including default device + * identifiers. + * @strings: tables of strings, keyed by identifiers assigned during bind() + * and language IDs provided in control requests + * @bind: (REQUIRED) Used to allocate resources that are shared across the + * whole device, such as string IDs, and add its configurations using + * @usb_add_config(). This may fail by returning a negative errno + * value; it should return zero on successful initialization. + * @unbind: Reverses @bind(); called as a side effect of unregistering + * this driver. + * + * Devices default to reporting self powered operation. Devices which rely + * on bus powered operation should report this in their @bind() method. + * + * Before returning from @bind, various fields in the template descriptor + * may be overridden. These include the idVendor/idProduct/bcdDevice values + * normally to bind the appropriate host side driver, and the three strings + * (iManufacturer, iProduct, iSerialNumber) normally used to provide user + * meaningful device identifiers. (The strings will not be defined unless + * they are defined in @dev and @strings.) The correct ep0 maxpacket size + * is also reported, as defined by the underlying controller driver. + */ +struct usb_composite_driver { + const char *name; + const struct usb_device_descriptor *dev; + struct usb_gadget_strings **strings; + + /* REVISIT: bind() functions can be marked __init, which + * makes trouble for section mismatch analysis. See if + * we can't restructure things to avoid mismatching... + */ + + int (*bind)(struct usb_composite_dev *); + int (*unbind)(struct usb_composite_dev *); +}; + +extern int usb_composite_register(struct usb_composite_driver *); +extern void usb_composite_unregister(struct usb_composite_driver *); + + +/** + * struct usb_composite_device - represents one composite usb gadget + * @gadget: read-only, abstracts the gadget's usb peripheral controller + * @req: used for control responses; buffer is pre-allocated + * @bufsiz: size of buffer pre-allocated in @req + * @config: the currently active configuration + * + * One of these devices is allocated and initialized before the + * associated device driver's bind() is called. + * + * OPEN ISSUE: it appears that some WUSB devices will need to be + * built by combining a normal (wired) gadget with a wireless one. + * This revision of the gadget framework should probably try to make + * sure doing that won't hurt too much. + * + * One notion for how to handle Wireless USB devices involves: + * (a) a second gadget here, discovery mechanism TBD, but likely + * needing separate "register/unregister WUSB gadget" calls; + * (b) updates to usb_gadget to include flags "is it wireless", + * "is it wired", plus (presumably in a wrapper structure) + * bandgroup and PHY info; + * (c) presumably a wireless_ep wrapping a usb_ep, and reporting + * wireless-specific parameters like maxburst and maxsequence; + * (d) configurations that are specific to wireless links; + * (e) function drivers that understand wireless configs and will + * support wireless for (additional) function instances; + * (f) a function to support association setup (like CBAF), not + * necessarily requiring a wireless adapter; + * (g) composite device setup that can create one or more wireless + * configs, including appropriate association setup support; + * (h) more, TBD. + */ +struct usb_composite_dev { + struct usb_gadget *gadget; + struct usb_request *req; + unsigned bufsiz; + + struct usb_configuration *config; + + /* internals */ + struct usb_device_descriptor desc; + struct list_head configs; + struct usb_composite_driver *driver; + u8 next_string_id; + + spinlock_t lock; + + /* REVISIT use and existence of lock ... */ +}; + +extern int usb_string_id(struct usb_composite_dev *c); + +/* messaging utils */ +#define DBG(d, fmt, args...) \ + dev_dbg(&(d)->gadget->dev , fmt , ## args) +#define VDBG(d, fmt, args...) \ + dev_vdbg(&(d)->gadget->dev , fmt , ## args) +#define ERROR(d, fmt, args...) \ + dev_err(&(d)->gadget->dev , fmt , ## args) +#define WARN(d, fmt, args...) \ + dev_warn(&(d)->gadget->dev , fmt , ## args) +#define INFO(d, fmt, args...) \ + dev_info(&(d)->gadget->dev , fmt , ## args) + +#endif /* __LINUX_USB_COMPOSITE_H */ diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index cf468fbdbf8e..0460a746480c 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -33,7 +33,8 @@ struct usb_ep; * @short_not_ok: When reading data, makes short packets be * treated as errors (queue stops advancing till cleanup). * @complete: Function called when request completes, so this request and - * its buffer may be re-used. + * its buffer may be re-used. The function will always be called with + * interrupts disabled, and it must not sleep. * Reads terminate with a short packet, or when the buffer fills, * whichever comes first. When writes terminate, some data bytes * will usually still be in flight (often in a hardware fifo). @@ -271,7 +272,10 @@ static inline void usb_ep_free_request(struct usb_ep *ep, * (Note that some USB device controllers disallow protocol stall responses * in some cases.) When control responses are deferred (the response is * written after the setup callback returns), then usb_ep_set_halt() may be - * used on ep0 to trigger protocol stalls. + * used on ep0 to trigger protocol stalls. Depending on the controller, + * it may not be possible to trigger a status-stage protocol stall when the + * data stage is over, that is, from within the response's completion + * routine. * * For periodic endpoints, like interrupt or isochronous ones, the usb host * arranges to poll once per interval, and the gadget driver usually will @@ -858,6 +862,25 @@ int usb_descriptor_fillbuf(void *, unsigned, int usb_gadget_config_buf(const struct usb_config_descriptor *config, void *buf, unsigned buflen, const struct usb_descriptor_header **desc); +/* copy a NULL-terminated vector of descriptors */ +struct usb_descriptor_header **usb_copy_descriptors( + struct usb_descriptor_header **); + +/* return copy of endpoint descriptor given original descriptor set */ +struct usb_endpoint_descriptor *usb_find_endpoint( + struct usb_descriptor_header **src, + struct usb_descriptor_header **copy, + struct usb_endpoint_descriptor *match); + +/** + * usb_free_descriptors - free descriptors returned by usb_copy_descriptors() + * @v: vector of descriptors + */ +static inline void usb_free_descriptors(struct usb_descriptor_header **v) +{ + kfree(v); +} + /*-------------------------------------------------------------------------*/ /* utility wrapping a simple endpoint selection policy */ diff --git a/include/linux/usb/irda.h b/include/linux/usb/irda.h new file mode 100644 index 000000000000..e345ceaf72d6 --- /dev/null +++ b/include/linux/usb/irda.h @@ -0,0 +1,151 @@ +/* + * USB IrDA Bridge Device Definition + */ + +#ifndef __LINUX_USB_IRDA_H +#define __LINUX_USB_IRDA_H + +/* This device should use Application-specific class */ + +#define USB_SUBCLASS_IRDA 0x02 + +/*-------------------------------------------------------------------------*/ + +/* Class-Specific requests (bRequest field) */ + +#define USB_REQ_CS_IRDA_RECEIVING 1 +#define USB_REQ_CS_IRDA_CHECK_MEDIA_BUSY 3 +#define USB_REQ_CS_IRDA_RATE_SNIFF 4 +#define USB_REQ_CS_IRDA_UNICAST_LIST 5 +#define USB_REQ_CS_IRDA_GET_CLASS_DESC 6 + +/*-------------------------------------------------------------------------*/ + +/* Class-Specific descriptor */ + +#define USB_DT_CS_IRDA 0x21 + +/*-------------------------------------------------------------------------*/ + +/* Data sizes */ + +#define USB_IRDA_DS_2048 (1 << 5) +#define USB_IRDA_DS_1024 (1 << 4) +#define USB_IRDA_DS_512 (1 << 3) +#define USB_IRDA_DS_256 (1 << 2) +#define USB_IRDA_DS_128 (1 << 1) +#define USB_IRDA_DS_64 (1 << 0) + +/* Window sizes */ + +#define USB_IRDA_WS_7 (1 << 6) +#define USB_IRDA_WS_6 (1 << 5) +#define USB_IRDA_WS_5 (1 << 4) +#define USB_IRDA_WS_4 (1 << 3) +#define USB_IRDA_WS_3 (1 << 2) +#define USB_IRDA_WS_2 (1 << 1) +#define USB_IRDA_WS_1 (1 << 0) + +/* Min turnaround times in usecs */ + +#define USB_IRDA_MTT_0 (1 << 7) +#define USB_IRDA_MTT_10 (1 << 6) +#define USB_IRDA_MTT_50 (1 << 5) +#define USB_IRDA_MTT_100 (1 << 4) +#define USB_IRDA_MTT_500 (1 << 3) +#define USB_IRDA_MTT_1000 (1 << 2) +#define USB_IRDA_MTT_5000 (1 << 1) +#define USB_IRDA_MTT_10000 (1 << 0) + +/* Baud rates */ + +#define USB_IRDA_BR_4000000 (1 << 8) +#define USB_IRDA_BR_1152000 (1 << 7) +#define USB_IRDA_BR_576000 (1 << 6) +#define USB_IRDA_BR_115200 (1 << 5) +#define USB_IRDA_BR_57600 (1 << 4) +#define USB_IRDA_BR_38400 (1 << 3) +#define USB_IRDA_BR_19200 (1 << 2) +#define USB_IRDA_BR_9600 (1 << 1) +#define USB_IRDA_BR_2400 (1 << 0) + +/* Additional BOFs */ + +#define USB_IRDA_AB_0 (1 << 7) +#define USB_IRDA_AB_1 (1 << 6) +#define USB_IRDA_AB_2 (1 << 5) +#define USB_IRDA_AB_3 (1 << 4) +#define USB_IRDA_AB_6 (1 << 3) +#define USB_IRDA_AB_12 (1 << 2) +#define USB_IRDA_AB_24 (1 << 1) +#define USB_IRDA_AB_48 (1 << 0) + +/* IRDA Rate Sniff */ + +#define USB_IRDA_RATE_SNIFF 1 + +/*-------------------------------------------------------------------------*/ + +struct usb_irda_cs_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 bcdSpecRevision; + __u8 bmDataSize; + __u8 bmWindowSize; + __u8 bmMinTurnaroundTime; + __le16 wBaudRate; + __u8 bmAdditionalBOFs; + __u8 bIrdaRateSniff; + __u8 bMaxUnicastList; +} __attribute__ ((packed)); + +/*-------------------------------------------------------------------------*/ + +/* Data Format */ + +#define USB_IRDA_STATUS_MEDIA_BUSY (1 << 7) + +/* The following is a 4-bit value used for both + * inbound and outbound headers: + * + * 0 - speed ignored + * 1 - 2400 bps + * 2 - 9600 bps + * 3 - 19200 bps + * 4 - 38400 bps + * 5 - 57600 bps + * 6 - 115200 bps + * 7 - 576000 bps + * 8 - 1.152 Mbps + * 9 - 5 mbps + * 10..15 - Reserved + */ +#define USB_IRDA_STATUS_LINK_SPEED 0x0f + +/* The following is a 4-bit value used only for + * outbound header: + * + * 0 - No change (BOF ignored) + * 1 - 48 BOFs + * 2 - 24 BOFs + * 3 - 12 BOFs + * 4 - 6 BOFs + * 5 - 3 BOFs + * 6 - 2 BOFs + * 7 - 1 BOFs + * 8 - 0 BOFs + * 9..15 - Reserved + */ +#define USB_IRDA_EXTRA_BOFS 0xf0 + +struct usb_irda_inbound_header { + __u8 bmStatus; +}; + +struct usb_irda_outbound_header { + __u8 bmChange; +}; + +#endif /* __LINUX_USB_IRDA_H */ + diff --git a/include/linux/usb/wusb-wa.h b/include/linux/usb/wusb-wa.h new file mode 100644 index 000000000000..c0743a2b69f8 --- /dev/null +++ b/include/linux/usb/wusb-wa.h @@ -0,0 +1,281 @@ +/* + * Wireless USB Wire Adapter constants and structures. + * + * Copyright (C) 2005-2006 Intel Corporation. + * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * + * FIXME: docs + * FIXME: organize properly, group logically + * + * All the event structures are defined in uwb/spec.h, as they are + * common to the WHCI and WUSB radio control interfaces. + * + * References: + * [WUSB] Wireless Universal Serial Bus Specification, revision 1.0, ch8 + */ +#ifndef __LINUX_USB_WUSB_WA_H +#define __LINUX_USB_WUSB_WA_H + +/** + * Radio Command Request for the Radio Control Interface + * + * Radio Control Interface command and event codes are the same as + * WHCI, and listed in include/linux/uwb.h:UWB_RC_{CMD,EVT}_* + */ +enum { + WA_EXEC_RC_CMD = 40, /* Radio Control command Request */ +}; + +/* Wireless Adapter Requests ([WUSB] table 8-51) */ +enum { + WUSB_REQ_ADD_MMC_IE = 20, + WUSB_REQ_REMOVE_MMC_IE = 21, + WUSB_REQ_SET_NUM_DNTS = 22, + WUSB_REQ_SET_CLUSTER_ID = 23, + WUSB_REQ_SET_DEV_INFO = 24, + WUSB_REQ_GET_TIME = 25, + WUSB_REQ_SET_STREAM_IDX = 26, + WUSB_REQ_SET_WUSB_MAS = 27, +}; + + +/* Wireless Adapter WUSB Channel Time types ([WUSB] table 8-52) */ +enum { + WUSB_TIME_ADJ = 0, + WUSB_TIME_BPST = 1, + WUSB_TIME_WUSB = 2, +}; + +enum { + WA_ENABLE = 0x01, + WA_RESET = 0x02, + RPIPE_PAUSE = 0x1, +}; + +/* Responses from Get Status request ([WUSB] section 8.3.1.6) */ +enum { + WA_STATUS_ENABLED = 0x01, + WA_STATUS_RESETTING = 0x02 +}; + +enum rpipe_crs { + RPIPE_CRS_CTL = 0x01, + RPIPE_CRS_ISO = 0x02, + RPIPE_CRS_BULK = 0x04, + RPIPE_CRS_INTR = 0x08 +}; + +/** + * RPipe descriptor ([WUSB] section 8.5.2.11) + * + * FIXME: explain rpipes + */ +struct usb_rpipe_descriptor { + u8 bLength; + u8 bDescriptorType; + __le16 wRPipeIndex; + __le16 wRequests; + __le16 wBlocks; /* rw if 0 */ + __le16 wMaxPacketSize; /* rw? */ + u8 bHSHubAddress; /* reserved: 0 */ + u8 bHSHubPort; /* ??? FIXME ??? */ + u8 bSpeed; /* rw: xfer rate 'enum uwb_phy_rate' */ + u8 bDeviceAddress; /* rw: Target device address */ + u8 bEndpointAddress; /* rw: Target EP address */ + u8 bDataSequence; /* ro: Current Data sequence */ + __le32 dwCurrentWindow; /* ro */ + u8 bMaxDataSequence; /* ro?: max supported seq */ + u8 bInterval; /* rw: */ + u8 bOverTheAirInterval; /* rw: */ + u8 bmAttribute; /* ro? */ + u8 bmCharacteristics; /* ro? enum rpipe_attr, supported xsactions */ + u8 bmRetryOptions; /* rw? */ + __le16 wNumTransactionErrors; /* rw */ +} __attribute__ ((packed)); + +/** + * Wire Adapter Notification types ([WUSB] sections 8.4.5 & 8.5.4) + * + * These are the notifications coming on the notification endpoint of + * an HWA and a DWA. + */ +enum wa_notif_type { + DWA_NOTIF_RWAKE = 0x91, + DWA_NOTIF_PORTSTATUS = 0x92, + WA_NOTIF_TRANSFER = 0x93, + HWA_NOTIF_BPST_ADJ = 0x94, + HWA_NOTIF_DN = 0x95, +}; + +/** + * Wire Adapter notification header + * + * Notifications coming from a wire adapter use a common header + * defined in [WUSB] sections 8.4.5 & 8.5.4. + */ +struct wa_notif_hdr { + u8 bLength; + u8 bNotifyType; /* enum wa_notif_type */ +} __attribute__((packed)); + +/** + * HWA DN Received notification [(WUSB] section 8.5.4.2) + * + * The DNData is specified in WUSB1.0[7.6]. For each device + * notification we received, we just need to dispatch it. However, + * note a WUSB1.0 errata from Dec'06 (page 24) says that the + * notification data doesn't have to include the WUSB header. As there + * are still firmwares out there that don't comply w/ the errata, we + * leave the option to have it. + * + * @dndata: this is really an array of notifications, but all start + * with the same header. + */ +struct hwa_notif_dn { + struct wa_notif_hdr hdr; + u8 bSourceDeviceAddr; /* from errata 2005/07 */ + union { + u8 bmAttributes; + DECL_BF_LE2( + u8 reserved:7, + u8 secure:1 + ) __attribute__((packed)); + }; + struct wusb_dn_hdr dndata[]; +} __attribute__((packed)); + +/* [WUSB] section 8.3.3 */ +enum wa_xfer_type { + WA_XFER_TYPE_CTL = 0x80, + WA_XFER_TYPE_BI = 0x81, /* bulk/interrupt */ + WA_XFER_TYPE_ISO = 0x82, + WA_XFER_RESULT = 0x83, + WA_XFER_ABORT = 0x84, +}; + +/* [WUSB] section 8.3.3 */ +struct wa_xfer_hdr { + u8 bLength; /* 0x18 */ + u8 bRequestType; /* 0x80 WA_REQUEST_TYPE_CTL */ + __le16 wRPipe; /* RPipe index */ + __le32 dwTransferID; /* Host-assigned ID */ + __le32 dwTransferLength; /* Length of data to xfer */ + u8 bTransferSegment; +} __attribute__((packed)); + +struct wa_xfer_ctl { + struct wa_xfer_hdr hdr; + u8 bmAttribute; + __le16 wReserved; + struct usb_ctrlrequest baSetupData; +} __attribute__((packed)); + +struct wa_xfer_bi { + struct wa_xfer_hdr hdr; + u8 bReserved; + __le16 wReserved; +} __attribute__((packed)); + +struct wa_xfer_hwaiso { + struct wa_xfer_hdr hdr; + u8 bReserved; + __le16 wPresentationTime; + __le32 dwNumOfPackets; + /* FIXME: u8 pktdata[]? */ +} __attribute__((packed)); + +/* [WUSB] section 8.3.3.5 */ +struct wa_xfer_abort { + u8 bLength; + u8 bRequestType; + __le16 wRPipe; /* RPipe index */ + __le32 dwTransferID; /* Host-assigned ID */ +} __attribute__((packed)); + +/** + * WA Transfer Complete notification ([WUSB] section 8.3.3.3) + * + */ +struct wa_notif_xfer { + struct wa_notif_hdr hdr; + u8 bEndpoint; + u8 Reserved; +} __attribute__((packed)); + +/** Transfer result basic codes [WUSB] table 8-15 */ +enum { + WA_XFER_STATUS_SUCCESS, + WA_XFER_STATUS_HALTED, + WA_XFER_STATUS_DATA_BUFFER_ERROR, + WA_XFER_STATUS_BABBLE, + WA_XFER_RESERVED, + WA_XFER_STATUS_NOT_FOUND, + WA_XFER_STATUS_INSUFFICIENT_RESOURCE, + WA_XFER_STATUS_TRANSACTION_ERROR, + WA_XFER_STATUS_ABORTED, + WA_XFER_STATUS_RPIPE_NOT_READY, + WA_XFER_INVALID_FORMAT, + WA_XFER_UNEXPECTED_SEGMENT_NUMBER, + WA_XFER_STATUS_RPIPE_TYPE_MISMATCH, +}; + +/** [WUSB] section 8.3.3.4 */ +struct wa_xfer_result { + struct wa_notif_hdr hdr; + __le32 dwTransferID; + __le32 dwTransferLength; + u8 bTransferSegment; + u8 bTransferStatus; + __le32 dwNumOfPackets; +} __attribute__((packed)); + +/** + * Wire Adapter Class Descriptor ([WUSB] section 8.5.2.7). + * + * NOTE: u16 fields are read Little Endian from the hardware. + * + * @bNumPorts is the original max number of devices that the host can + * connect; we might chop this so the stack can handle + * it. In case you need to access it, use wusbhc->ports_max + * if it is a Wireless USB WA. + */ +struct usb_wa_descriptor { + u8 bLength; + u8 bDescriptorType; + u16 bcdWAVersion; + u8 bNumPorts; /* don't use!! */ + u8 bmAttributes; /* Reserved == 0 */ + u16 wNumRPipes; + u16 wRPipeMaxBlock; + u8 bRPipeBlockSize; + u8 bPwrOn2PwrGood; + u8 bNumMMCIEs; + u8 DeviceRemovable; /* FIXME: in DWA this is up to 16 bytes */ +} __attribute__((packed)); + +/** + * HWA Device Information Buffer (WUSB1.0[T8.54]) + */ +struct hwa_dev_info { + u8 bmDeviceAvailability[32]; /* FIXME: ignored for now */ + u8 bDeviceAddress; + __le16 wPHYRates; + u8 bmDeviceAttribute; +} __attribute__((packed)); + +#endif /* #ifndef __LINUX_USB_WUSB_WA_H */ diff --git a/include/linux/usb/wusb.h b/include/linux/usb/wusb.h new file mode 100644 index 000000000000..248354ab48ac --- /dev/null +++ b/include/linux/usb/wusb.h @@ -0,0 +1,419 @@ +/* + * Wireless USB Standard Definitions + * Event Size Tables + * + * Copyright (C) 2005-2006 Intel Corporation + * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * + * FIXME: docs + * FIXME: organize properly, group logically + * + * All the event structures are defined in uwb/spec.h, as they are + * common to the WHCI and WUSB radio control interfaces. + */ + +#ifndef __WUSB_H__ +#define __WUSB_H__ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/uwb/spec.h> +#include <linux/usb/ch9.h> +#include <linux/param.h> + +/** + * WUSB Information Element header + * + * I don't know why, they decided to make it different to the MBOA MAC + * IE Header; beats me. + */ +struct wuie_hdr { + u8 bLength; + u8 bIEIdentifier; +} __attribute__((packed)); + +enum { + WUIE_ID_WCTA = 0x80, + WUIE_ID_CONNECTACK, + WUIE_ID_HOST_INFO, + WUIE_ID_CHANGE_ANNOUNCE, + WUIE_ID_DEVICE_DISCONNECT, + WUIE_ID_HOST_DISCONNECT, + WUIE_ID_KEEP_ALIVE = 0x89, + WUIE_ID_ISOCH_DISCARD, + WUIE_ID_RESET_DEVICE, +}; + +/** + * Maximum number of array elements in a WUSB IE. + * + * WUSB1.0[7.5 before table 7-38] says that in WUSB IEs that + * are "arrays" have to limited to 4 elements. So we define it + * like that to ease up and submit only the neeed size. + */ +#define WUIE_ELT_MAX 4 + +/** + * Wrapper for the data that defines a CHID, a CDID or a CK + * + * WUSB defines that CHIDs, CDIDs and CKs are a 16 byte string of + * data. In order to avoid confusion and enforce types, we wrap it. + * + * Make it packed, as we use it in some hw defintions. + */ +struct wusb_ckhdid { + u8 data[16]; +} __attribute__((packed)); + +const static +struct wusb_ckhdid wusb_ckhdid_zero = { .data = { 0 } }; + +#define WUSB_CKHDID_STRSIZE (3 * sizeof(struct wusb_ckhdid) + 1) + +/** + * WUSB IE: Host Information (WUSB1.0[7.5.2]) + * + * Used to provide information about the host to the Wireless USB + * devices in range (CHID can be used as an ASCII string). + * + * NOTE that because so far, bits 6 to 15 of bmAttributes are + * reserved, I just declare 8 bits and play with that so we don't have + * to do endianess conversion. + */ +struct wuie_host_info { + struct wuie_hdr hdr; + DECL_BF_LE5( + u8 connect_avail:2, + u8 p2p_drd:1, + u8 stream_index:3, + u8 reserved1:2, + ) __attribute__((packed)); + u8 reserved2; /* See NOTE */ + struct wusb_ckhdid CHID; +} __attribute__((packed)); + +/** + * WUSB IE: Connect Ack (WUSB1.0[7.5.1]) + * + * Used to acknowledge device connect requests. See note for + * WUIE_ELT_MAX. + */ +struct wuie_connect_ack { + struct wuie_hdr hdr; + struct { + struct wusb_ckhdid CDID; + u8 bDeviceAddress; /* 0 means unused */ + u8 bReserved; + } blk[WUIE_ELT_MAX]; +} __attribute__((packed)); + +/** + * WUSB IE Host Information Element, Connect Availability + * + * WUSB1.0[7.5.2], bmAttributes description + */ +enum { + WUIE_HI_CAP_RECONNECT = 0, + WUIE_HI_CAP_LIMITED, + WUIE_HI_CAP_RESERVED, + WUIE_HI_CAP_ALL, +}; + +/** + * WUSB IE: Channel Stop (WUSB1.0[7.5.8]) + * + * Tells devices the host is going to stop sending MMCs and will dissapear. + */ +struct wuie_channel_stop { + struct wuie_hdr hdr; + union { + u8 bmAttributes; + DECL_BF_LE2( + u8 RemoteWakeup:1, + u8 reserved:1 + ) __attribute__((packed)); + }; + u8 timestamp[3]; +} __attribute__((packed)); + +/** + * WUSB IE: Keepalive (WUSB1.0[7.5.9]) + * + * Ask device(s) to send keepalives. + */ +struct wuie_keep_alive { + struct wuie_hdr hdr; + u8 bDeviceAddress[WUIE_ELT_MAX]; +} __attribute__((packed)); + +/** + * WUSB IE: Reset device (WUSB1.0[7.5.11]) + * + * Tell device to reset; in all truth, we can fit 4 CDIDs, but we only + * use it for one at the time... + * + * In any case, this request is a wee bit silly: why don't they target + * by address?? + */ +struct wuie_reset { + struct wuie_hdr hdr; + struct wusb_ckhdid CDID; +} __attribute__((packed)); + +/** + * WUSB IE: Disconnect device (WUSB1.0[7.5.11]) + * + * Tell device to disconnect; we can fit 4 addresses, but we only use + * it for one at the time... + */ +struct wuie_disconnect { + struct wuie_hdr hdr; + u8 bDeviceAddress; + u8 padding; +} __attribute__((packed)); + +/** + * WUSB IE: Host disconnect ([WUSB] section 7.5.5) + * + * Tells all connected devices to disconnect. + */ +struct wuie_host_disconnect { + struct wuie_hdr hdr; +} __attribute__((packed)); + +/** + * Device notification header + * + * WUSB1.0[5.1] and [7.6] + * + * This is the most common parts of the header; depending on the value + * of @pid, some other stuff might be added. + * + * This is a WIRE FORMAT header--check 'struct wa_notif_hdr' + */ +struct wusb_pkt_hdr { + union { + u8 bmAttributes; + DECL_BF_LE3( + u8 endp_number:4, + u8 pid:3, + u8 direction:1 + ) __attribute__((packed)); + }; + union { + u8 bmStatus; + DECL_BF_LE2( + u8 seq_number:5, + u8 flags_hshk:3 + ) __attribute__((packed)); + }; +} __attribute__((packed)); + +/** + * WUSB Device Notification header (WUSB1.0[7.6]) + */ +struct wusb_dn_hdr { + u8 bType; + u8 notifdata[]; +} __attribute__((packed)); + +/** Device Notification codes (WUSB1.0[Table 7-54]) */ +enum WUSB_DN { + WUSB_DN_CONNECT = 0x01, + WUSB_DN_DISCONNECT = 0x02, + WUSB_DN_EPRDY = 0x03, + WUSB_DN_MASAVAILCHANGED = 0x04, + WUSB_DN_RWAKE = 0x05, + WUSB_DN_SLEEP = 0x06, + WUSB_DN_ALIVE = 0x07, +}; + +/** WUSB Device Notification Connect */ +struct wusb_dn_connect { + struct wusb_dn_hdr hdr; + union { + u16 bmAttributes; + __le16 bmAttributes_le; + DECL_BF_LE4( + u8 prev_dev_addr:8, + u8 new_connection:1, + u8 beacon_behaviour:2, + u8 reserved:5 + ) __attribute__((packed)); + }; + struct wusb_ckhdid CDID; +} __attribute__((packed)); + +/** Device is alive (aka: pong) (WUSB1.0[7.6.7]) */ +struct wusb_dn_alive { + struct wusb_dn_hdr hdr; +} __attribute__((packed)); + +/** Device is disconnecting (WUSB1.0[7.6.2]) */ +struct wusb_dn_disconnect { + struct wusb_dn_hdr hdr; +} __attribute__((packed)); + +/* General constants */ +enum { + WUSB_TRUST_TIMEOUT_MS = 4000, /* [WUSB] section 4.15.1 */ +}; + +static inline size_t ckhdid_printf(char *pr_ckhdid, size_t size, + const struct wusb_ckhdid *ckhdid) +{ + return scnprintf(pr_ckhdid, size, + "%02hx %02hx %02hx %02hx %02hx %02hx %02hx %02hx " + "%02hx %02hx %02hx %02hx %02hx %02hx %02hx %02hx", + ckhdid->data[0], ckhdid->data[1], + ckhdid->data[2], ckhdid->data[3], + ckhdid->data[4], ckhdid->data[5], + ckhdid->data[6], ckhdid->data[7], + ckhdid->data[8], ckhdid->data[9], + ckhdid->data[10], ckhdid->data[11], + ckhdid->data[12], ckhdid->data[13], + ckhdid->data[14], ckhdid->data[15]); +} + +/* + * WUSB Crypto stuff (WUSB1.0[6]) + */ + +extern const char *wusb_et_name(u8); + +/** + * WUSB key index WUSB1.0[7.3.2.4], for usage when setting keys for + * the host or the device. + */ +union wusb_key_index { + u8 value; + DECL_BF_LE4( + u8 index:4, + u8 type:2, + u8 originator:1, + u8 reserved:1 + ); +} __attribute__((packed)); + +#define WUSB_KEY_INDEX_TYPE_PTK 0 /* for HWA only */ +#define WUSB_KEY_INDEX_TYPE_ASSOC 1 +#define WUSB_KEY_INDEX_TYPE_GTK 2 +#define WUSB_KEY_INDEX_ORIGINATOR_HOST 0 +#define WUSB_KEY_INDEX_ORIGINATOR_DEVICE 1 + +/* A CCM Nonce, defined in WUSB1.0[6.4.1] */ +struct aes_ccm_nonce { + u8 sfn[6]; /* Little Endian */ + u8 tkid[3]; /* LE */ + struct uwb_dev_addr dest_addr; + struct uwb_dev_addr src_addr; +} __attribute__((packed)); + +/* A CCM operation label, defined on WUSB1.0[6.5.x] */ +struct aes_ccm_label { + u8 data[14]; +} __attribute__((packed)); + +/* + * Input to the key derivation sequence defined in + * WUSB1.0[6.5.1]. Rest of the data is in the CCM Nonce passed to the + * PRF function. + */ +struct wusb_keydvt_in { + u8 hnonce[16]; + u8 dnonce[16]; +} __attribute__((packed)); + +/* + * Output from the key derivation sequence defined in + * WUSB1.0[6.5.1]. + */ +struct wusb_keydvt_out { + u8 kck[16]; + u8 ptk[16]; +} __attribute__((packed)); + +/* Pseudo Random Function WUSB1.0[6.5] */ +extern int wusb_crypto_init(void); +extern void wusb_crypto_exit(void); +extern ssize_t wusb_prf(void *out, size_t out_size, + const u8 key[16], const struct aes_ccm_nonce *_n, + const struct aes_ccm_label *a, + const void *b, size_t blen, size_t len); + +static inline int wusb_prf_64(void *out, size_t out_size, const u8 key[16], + const struct aes_ccm_nonce *n, + const struct aes_ccm_label *a, + const void *b, size_t blen) +{ + return wusb_prf(out, out_size, key, n, a, b, blen, 64); +} + +static inline int wusb_prf_128(void *out, size_t out_size, const u8 key[16], + const struct aes_ccm_nonce *n, + const struct aes_ccm_label *a, + const void *b, size_t blen) +{ + return wusb_prf(out, out_size, key, n, a, b, blen, 128); +} + +static inline int wusb_prf_256(void *out, size_t out_size, const u8 key[16], + const struct aes_ccm_nonce *n, + const struct aes_ccm_label *a, + const void *b, size_t blen) +{ + return wusb_prf(out, out_size, key, n, a, b, blen, 256); +} + +/* Key derivation WUSB1.0[6.5.1] */ +static inline int wusb_key_derive(struct wusb_keydvt_out *keydvt_out, + const u8 key[16], + const struct aes_ccm_nonce *n, + const struct wusb_keydvt_in *keydvt_in) +{ + const struct aes_ccm_label a = { .data = "Pair-wise keys" }; + return wusb_prf_256(keydvt_out, sizeof(*keydvt_out), key, n, &a, + keydvt_in, sizeof(*keydvt_in)); +} + +/* + * Out-of-band MIC Generation WUSB1.0[6.5.2] + * + * Compute the MIC over @key, @n and @hs and place it in @mic_out. + * + * @mic_out: Where to place the 8 byte MIC tag + * @key: KCK from the derivation process + * @n: CCM nonce, n->sfn == 0, TKID as established in the + * process. + * @hs: Handshake struct for phase 2 of the 4-way. + * hs->bStatus and hs->bReserved are zero. + * hs->bMessageNumber is 2 (WUSB1.0[7.3.2.5.2] + * hs->dest_addr is the device's USB address padded with 0 + * hs->src_addr is the hosts's UWB device address + * hs->mic is ignored (as we compute that value). + */ +static inline int wusb_oob_mic(u8 mic_out[8], const u8 key[16], + const struct aes_ccm_nonce *n, + const struct usb_handshake *hs) +{ + const struct aes_ccm_label a = { .data = "out-of-bandMIC" }; + return wusb_prf_64(mic_out, 8, key, n, &a, + hs, sizeof(*hs) - sizeof(hs->MIC)); +} + +#endif /* #ifndef __WUSB_H__ */ diff --git a/include/linux/usbdevice_fs.h b/include/linux/usbdevice_fs.h index 3118ede2c67b..0044d9b4cb85 100644 --- a/include/linux/usbdevice_fs.h +++ b/include/linux/usbdevice_fs.h @@ -22,8 +22,6 @@ * * History: * 0.1 04.01.2000 Created - * - * $Id: usbdevice_fs.h,v 1.1 2000/01/06 18:40:41 tom Exp $ */ /*****************************************************************************/ diff --git a/include/linux/uwb.h b/include/linux/uwb.h new file mode 100644 index 000000000000..c1562d7dc304 --- /dev/null +++ b/include/linux/uwb.h @@ -0,0 +1,759 @@ +/* + * Ultra Wide Band + * UWB API + * + * Copyright (C) 2005-2006 Intel Corporation + * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * + * FIXME: doc: overview of the API, different parts and pointers + */ + +#ifndef __LINUX__UWB_H__ +#define __LINUX__UWB_H__ + +#include <linux/limits.h> +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/timer.h> +#include <linux/workqueue.h> +#include <linux/uwb/spec.h> + +struct uwb_dev; +struct uwb_beca_e; +struct uwb_rc; +struct uwb_rsv; +struct uwb_dbg; + +/** + * UWB Device + * + * Each device is part of a beacon group. + * + * @rc: UWB Radio Controller that discovered the device (kind + * of its parent). + * + * @bce: protected by @uwb_beca->mutex. Always alive as long as + * uwb_dev is alive. Note that a local radio controller might or + * might not have a bce entry (if there is another radio + * controller that saw him, then it might--FIXME). + * + * @streams: bitmap of streams allocated to reservations targeted at + * this device. For an RC, this is the streams allocated + * for reservations targeted at DevAddrs. + * + * It's possible that we have in a same machine more than one radio + * controller + */ +struct uwb_dev { + struct mutex mutex; + struct list_head list_node; + struct device dev; + struct uwb_rc *rc; /* radio controller */ + struct uwb_beca_e *bce; /* Beacon Cache Entry */ + + struct uwb_mac_addr mac_addr; + struct uwb_dev_addr dev_addr; + DECLARE_BITMAP(streams, UWB_NUM_STREAMS); +}; +#define to_uwb_dev(d) container_of(d, struct uwb_dev, dev) + +/** + * UWB HWA/WHCI Radio Control {Command|Event} Block context IDs + * + * RC[CE]Bs have a 'context ID' field that matches the command with + * the event received to confirm it. + * + * Maximum number of context IDs + */ +enum { UWB_RC_CTX_MAX = 256 }; + + +/** Notification chain head for UWB generated events to listeners */ +struct uwb_notifs_chain { + struct list_head list; + struct mutex mutex; +}; + +/** + * struct uwb_mas_bm - a bitmap of all MAS in a superframe + * @bm: a bitmap of length #UWB_NUM_MAS + */ +struct uwb_mas_bm { + DECLARE_BITMAP(bm, UWB_NUM_MAS); +}; + +/** + * uwb_rsv_state - UWB Reservation state. + * + * NONE - reservation is not active (no DRP IE being transmitted). + * + * Owner reservation states: + * + * INITIATED - owner has sent an initial DRP request. + * PENDING - target responded with pending Reason Code. + * MODIFIED - reservation manager is modifying an established + * reservation with a different MAS allocation. + * ESTABLISHED - the reservation has been successfully negotiated. + * + * Target reservation states: + * + * DENIED - request is denied. + * ACCEPTED - request is accepted. + * PENDING - PAL has yet to make a decision to whether to accept or + * deny. + * + * FIXME: further target states TBD. + */ +enum uwb_rsv_state { + UWB_RSV_STATE_NONE, + UWB_RSV_STATE_O_INITIATED, + UWB_RSV_STATE_O_PENDING, + UWB_RSV_STATE_O_MODIFIED, + UWB_RSV_STATE_O_ESTABLISHED, + UWB_RSV_STATE_T_ACCEPTED, + UWB_RSV_STATE_T_DENIED, + UWB_RSV_STATE_T_PENDING, + + UWB_RSV_STATE_LAST, +}; + +enum uwb_rsv_target_type { + UWB_RSV_TARGET_DEV, + UWB_RSV_TARGET_DEVADDR, +}; + +/** + * struct uwb_rsv_target - the target of a reservation. + * + * Reservations unicast and targeted at a single device + * (UWB_RSV_TARGET_DEV); or (e.g., in the case of WUSB) targeted at a + * specific (private) DevAddr (UWB_RSV_TARGET_DEVADDR). + */ +struct uwb_rsv_target { + enum uwb_rsv_target_type type; + union { + struct uwb_dev *dev; + struct uwb_dev_addr devaddr; + }; +}; + +/* + * Number of streams reserved for reservations targeted at DevAddrs. + */ +#define UWB_NUM_GLOBAL_STREAMS 1 + +typedef void (*uwb_rsv_cb_f)(struct uwb_rsv *rsv); + +/** + * struct uwb_rsv - a DRP reservation + * + * Data structure management: + * + * @rc: the radio controller this reservation is for + * (as target or owner) + * @rc_node: a list node for the RC + * @pal_node: a list node for the PAL + * + * Owner and target parameters: + * + * @owner: the UWB device owning this reservation + * @target: the target UWB device + * @type: reservation type + * + * Owner parameters: + * + * @max_mas: maxiumum number of MAS + * @min_mas: minimum number of MAS + * @sparsity: owner selected sparsity + * @is_multicast: true iff multicast + * + * @callback: callback function when the reservation completes + * @pal_priv: private data for the PAL making the reservation + * + * Reservation status: + * + * @status: negotiation status + * @stream: stream index allocated for this reservation + * @mas: reserved MAS + * @drp_ie: the DRP IE + * @ie_valid: true iff the DRP IE matches the reservation parameters + * + * DRP reservations are uniquely identified by the owner, target and + * stream index. However, when using a DevAddr as a target (e.g., for + * a WUSB cluster reservation) the responses may be received from + * devices with different DevAddrs. In this case, reservations are + * uniquely identified by just the stream index. A number of stream + * indexes (UWB_NUM_GLOBAL_STREAMS) are reserved for this. + */ +struct uwb_rsv { + struct uwb_rc *rc; + struct list_head rc_node; + struct list_head pal_node; + + struct uwb_dev *owner; + struct uwb_rsv_target target; + enum uwb_drp_type type; + int max_mas; + int min_mas; + int sparsity; + bool is_multicast; + + uwb_rsv_cb_f callback; + void *pal_priv; + + enum uwb_rsv_state state; + u8 stream; + struct uwb_mas_bm mas; + struct uwb_ie_drp *drp_ie; + bool ie_valid; + struct timer_list timer; + bool expired; +}; + +static const +struct uwb_mas_bm uwb_mas_bm_zero = { .bm = { 0 } }; + +static inline void uwb_mas_bm_copy_le(void *dst, const struct uwb_mas_bm *mas) +{ + bitmap_copy_le(dst, mas->bm, UWB_NUM_MAS); +} + +/** + * struct uwb_drp_avail - a radio controller's view of MAS usage + * @global: MAS unused by neighbors (excluding reservations targetted + * or owned by the local radio controller) or the beaon period + * @local: MAS unused by local established reservations + * @pending: MAS unused by local pending reservations + * @ie: DRP Availability IE to be included in the beacon + * @ie_valid: true iff @ie is valid and does not need to regenerated from + * @global and @local + * + * Each radio controller maintains a view of MAS usage or + * availability. MAS available for a new reservation are determined + * from the intersection of @global, @local, and @pending. + * + * The radio controller must transmit a DRP Availability IE that's the + * intersection of @global and @local. + * + * A set bit indicates the MAS is unused and available. + * + * rc->rsvs_mutex should be held before accessing this data structure. + * + * [ECMA-368] section 17.4.3. + */ +struct uwb_drp_avail { + DECLARE_BITMAP(global, UWB_NUM_MAS); + DECLARE_BITMAP(local, UWB_NUM_MAS); + DECLARE_BITMAP(pending, UWB_NUM_MAS); + struct uwb_ie_drp_avail ie; + bool ie_valid; +}; + + +const char *uwb_rsv_state_str(enum uwb_rsv_state state); +const char *uwb_rsv_type_str(enum uwb_drp_type type); + +struct uwb_rsv *uwb_rsv_create(struct uwb_rc *rc, uwb_rsv_cb_f cb, + void *pal_priv); +void uwb_rsv_destroy(struct uwb_rsv *rsv); + +int uwb_rsv_establish(struct uwb_rsv *rsv); +int uwb_rsv_modify(struct uwb_rsv *rsv, + int max_mas, int min_mas, int sparsity); +void uwb_rsv_terminate(struct uwb_rsv *rsv); + +void uwb_rsv_accept(struct uwb_rsv *rsv, uwb_rsv_cb_f cb, void *pal_priv); + +/** + * Radio Control Interface instance + * + * + * Life cycle rules: those of the UWB Device. + * + * FIXME: move most fields that are not continuously accessed to + * bitfields to pack the info a wee bit. Channels go from 0 to + * 46, for example. + * + * @version: version of protocol supported by this device + * @priv: Backend implementation; rw with uwb_dev.dev.sem taken. + * @cmd: Backend implementation to execute commands; rw and call + * only with uwb_dev.dev.sem taken. + * @filter: Backend implementation to manipulate data to and from device + * to be compliant to specification assumed by driver (WHCI + * 0.95). + * + * uwb_dev.dev.mutex is used to execute commands and update + * the corresponding structures; can't use a spinlock + * because rc->cmd() can sleep. + * @ies: This is a dynamically allocated array cacheing the + * IEs (settable by the host) that the beacon of this + * radio controller is currently sending. + * + * In reality, we store here the full command we set to + * the radio controller (which is basically a command + * prefix followed by all the IEs the beacon currently + * contains). This way we don't have to realloc and + * memcpy when setting it. + * + * We set this up in uwb_rc_ie_setup(), where we alloc + * this struct, call get_ie() [so we know which IEs are + * currently being sent, if any]. + * + * @ies_capacity:Amount of space (in bytes) allocated in @ies. The + * amount used is given by sizeof(*ies) plus ies->wIELength + * (which is a little endian quantity all the time). + * @ies_mutex: protect the IE cache + * @dbg: information for the debug interface + */ +struct uwb_rc { + struct uwb_dev uwb_dev; + u16 version; + + void *priv; + int (*cmd)(struct uwb_rc *, const struct uwb_rccb *, size_t); + int (*filter_cmd)(struct uwb_rc *, struct uwb_rccb **, size_t *); + int (*filter_event)(struct uwb_rc *, struct uwb_rceb **, const size_t, + size_t *, size_t *); + + spinlock_t neh_lock; /* protects neh_* and ctx_* */ + struct list_head neh_list; /* Open NE handles */ + unsigned long ctx_bm[UWB_RC_CTX_MAX / 8 / sizeof(unsigned long)]; + u8 ctx_roll; + + int beaconing; /* Beaconing state [channel number] */ + int scanning; + enum uwb_scan_type scan_type:3; + unsigned ready:1; + struct uwb_notifs_chain notifs_chain; + + struct uwb_drp_avail drp_avail; + struct list_head reservations; + struct mutex rsvs_mutex; + struct workqueue_struct *rsv_workq; + struct work_struct rsv_update_work; + + struct mutex ies_mutex; + struct uwb_rc_cmd_set_ie *ies; + size_t ies_capacity; + + spinlock_t pal_lock; + struct list_head pals; + + struct uwb_dbg *dbg; +}; + + +/** + * struct uwb_pal - a UWB PAL + * @new_rsv: called when a peer requests a reservation (may be NULL if + * the PAL cannot accept reservation requests). + * + * A Protocol Adaptation Layer (PAL) is a user of the WiMedia UWB + * radio platform (e.g., WUSB, WLP or Bluetooth UWB AMP). + * + * The PALs using a radio controller must register themselves to + * permit the UWB stack to coordinate usage of the radio between the + * various PALs or to allow PALs to response to certain requests from + * peers. + * + * A struct uwb_pal should be embedded in a containing structure + * belonging to the PAL and initialized with uwb_pal_init()). Fields + * should be set appropriately by the PAL before registering the PAL + * with uwb_pal_register(). + */ +struct uwb_pal { + struct list_head node; + + void (*new_rsv)(struct uwb_rsv *rsv); +}; + +void uwb_pal_init(struct uwb_pal *pal); +int uwb_pal_register(struct uwb_rc *rc, struct uwb_pal *pal); +void uwb_pal_unregister(struct uwb_rc *rc, struct uwb_pal *pal); + +/* + * General public API + * + * This API can be used by UWB device drivers or by those implementing + * UWB Radio Controllers + */ +struct uwb_dev *uwb_dev_get_by_devaddr(struct uwb_rc *rc, + const struct uwb_dev_addr *devaddr); +extern struct uwb_dev *uwb_dev_get_by_rc(struct uwb_dev *, struct uwb_rc *); +static inline void uwb_dev_get(struct uwb_dev *uwb_dev) +{ + get_device(&uwb_dev->dev); +} +static inline void uwb_dev_put(struct uwb_dev *uwb_dev) +{ + put_device(&uwb_dev->dev); +} +struct uwb_dev *uwb_dev_try_get(struct uwb_rc *rc, struct uwb_dev *uwb_dev); + +/** + * Callback function for 'uwb_{dev,rc}_foreach()'. + * + * @dev: Linux device instance + * 'uwb_dev = container_of(dev, struct uwb_dev, dev)' + * @priv: Data passed by the caller to 'uwb_{dev,rc}_foreach()'. + * + * @returns: 0 to continue the iterations, any other val to stop + * iterating and return the value to the caller of + * _foreach(). + */ +typedef int (*uwb_dev_for_each_f)(struct device *dev, void *priv); +int uwb_dev_for_each(struct uwb_rc *rc, uwb_dev_for_each_f func, void *priv); + +extern struct uwb_rc *uwb_rc_alloc(void); +extern struct uwb_rc *uwb_rc_get_by_dev(const struct uwb_dev_addr *); +extern struct uwb_rc *uwb_rc_get_by_grandpa(const struct device *); +extern void uwb_rc_put(struct uwb_rc *rc); + + +extern ssize_t uwb_rc_cmd(struct uwb_rc *rc, const char *cmd_name, + struct uwb_rccb *cmd, size_t cmd_size, + struct uwb_rceb *reply, size_t reply_size); +extern ssize_t uwb_rc_vcmd(struct uwb_rc *rc, const char *cmd_name, + struct uwb_rccb *cmd, size_t cmd_size, + u8 expected_type, u16 expected_event, + struct uwb_rceb **preply); +extern ssize_t uwb_rc_get_ie(struct uwb_rc *, struct uwb_rc_evt_get_ie **); +extern int uwb_bg_joined(struct uwb_rc *rc); + +extern size_t __uwb_addr_print(char *, size_t, const unsigned char *, int); + +extern int uwb_rc_dev_addr_set(struct uwb_rc *, const struct uwb_dev_addr *); +extern int uwb_rc_dev_addr_get(struct uwb_rc *, struct uwb_dev_addr *); +extern int uwb_rc_mac_addr_set(struct uwb_rc *, const struct uwb_mac_addr *); +extern int uwb_rc_mac_addr_get(struct uwb_rc *, struct uwb_mac_addr *); +extern int __uwb_mac_addr_assigned_check(struct device *, void *); +extern int __uwb_dev_addr_assigned_check(struct device *, void *); + +/* Print in @buf a pretty repr of @addr */ +static inline size_t uwb_dev_addr_print(char *buf, size_t buf_size, + const struct uwb_dev_addr *addr) +{ + return __uwb_addr_print(buf, buf_size, addr->data, 0); +} + +/* Print in @buf a pretty repr of @addr */ +static inline size_t uwb_mac_addr_print(char *buf, size_t buf_size, + const struct uwb_mac_addr *addr) +{ + return __uwb_addr_print(buf, buf_size, addr->data, 1); +} + +/* @returns 0 if device addresses @addr2 and @addr1 are equal */ +static inline int uwb_dev_addr_cmp(const struct uwb_dev_addr *addr1, + const struct uwb_dev_addr *addr2) +{ + return memcmp(addr1, addr2, sizeof(*addr1)); +} + +/* @returns 0 if MAC addresses @addr2 and @addr1 are equal */ +static inline int uwb_mac_addr_cmp(const struct uwb_mac_addr *addr1, + const struct uwb_mac_addr *addr2) +{ + return memcmp(addr1, addr2, sizeof(*addr1)); +} + +/* @returns !0 if a MAC @addr is a broadcast address */ +static inline int uwb_mac_addr_bcast(const struct uwb_mac_addr *addr) +{ + struct uwb_mac_addr bcast = { + .data = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } + }; + return !uwb_mac_addr_cmp(addr, &bcast); +} + +/* @returns !0 if a MAC @addr is all zeroes*/ +static inline int uwb_mac_addr_unset(const struct uwb_mac_addr *addr) +{ + struct uwb_mac_addr unset = { + .data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } + }; + return !uwb_mac_addr_cmp(addr, &unset); +} + +/* @returns !0 if the address is in use. */ +static inline unsigned __uwb_dev_addr_assigned(struct uwb_rc *rc, + struct uwb_dev_addr *addr) +{ + return uwb_dev_for_each(rc, __uwb_dev_addr_assigned_check, addr); +} + +/* + * UWB Radio Controller API + * + * This API is used (in addition to the general API) to implement UWB + * Radio Controllers. + */ +extern void uwb_rc_init(struct uwb_rc *); +extern int uwb_rc_add(struct uwb_rc *, struct device *dev, void *rc_priv, + int (*cmd)(struct uwb_rc *, const struct uwb_rccb *, + size_t), + int (*filter_cmd)(struct uwb_rc *, struct uwb_rccb **, + size_t *), + int (*filter_event)(struct uwb_rc *, struct uwb_rceb **, + const size_t, size_t *, size_t *)); +extern void uwb_rc_rm(struct uwb_rc *); +extern void uwb_rc_neh_grok(struct uwb_rc *, void *, size_t); +extern void uwb_rc_neh_error(struct uwb_rc *, int); + +/** + * uwb_rsv_is_owner - is the owner of this reservation the RC? + * @rsv: the reservation + */ +static inline bool uwb_rsv_is_owner(struct uwb_rsv *rsv) +{ + return rsv->owner == &rsv->rc->uwb_dev; +} + +/** + * Events generated by UWB that can be passed to any listeners + * + * Higher layers can register callback functions with the radio + * controller using uwb_notifs_register(). The radio controller + * maintains a list of all registered handlers and will notify all + * nodes when an event occurs. + */ +enum uwb_notifs { + UWB_NOTIF_BG_JOIN = 0, /* radio controller joined a beacon group */ + UWB_NOTIF_BG_LEAVE = 1, /* radio controller left a beacon group */ + UWB_NOTIF_ONAIR, + UWB_NOTIF_OFFAIR, +}; + +/* Callback function registered with UWB */ +struct uwb_notifs_handler { + struct list_head list_node; + void (*cb)(void *, struct uwb_dev *, enum uwb_notifs); + void *data; +}; + +extern int uwb_notifs_register(struct uwb_rc *, struct uwb_notifs_handler *); +extern int uwb_notifs_deregister(struct uwb_rc *, struct uwb_notifs_handler *); + + +/** + * UWB radio controller Event Size Entry (for creating entry tables) + * + * WUSB and WHCI define events and notifications, and they might have + * fixed or variable size. + * + * Each event/notification has a size which is not necessarily known + * in advance based on the event code. As well, vendor specific + * events/notifications will have a size impossible to determine + * unless we know about the device's specific details. + * + * It was way too smart of the spec writers not to think that it would + * be impossible for a generic driver to skip over vendor specific + * events/notifications if there are no LENGTH fields in the HEADER of + * each message...the transaction size cannot be counted on as the + * spec does not forbid to pack more than one event in a single + * transaction. + * + * Thus, we guess sizes with tables (or for events, when you know the + * size ahead of time you can use uwb_rc_neh_extra_size*()). We + * register tables with the known events and their sizes, and then we + * traverse those tables. For those with variable length, we provide a + * way to lookup the size inside the event/notification's + * payload. This allows device-specific event size tables to be + * registered. + * + * @size: Size of the payload + * + * @offset: if != 0, at offset @offset-1 starts a field with a length + * that has to be added to @size. The format of the field is + * given by @type. + * + * @type: Type and length of the offset field. Most common is LE 16 + * bits (that's why that is zero); others are there mostly to + * cover for bugs and weirdos. + */ +struct uwb_est_entry { + size_t size; + unsigned offset; + enum { UWB_EST_16 = 0, UWB_EST_8 = 1 } type; +}; + +extern int uwb_est_register(u8 type, u8 code_high, u16 vendor, u16 product, + const struct uwb_est_entry *, size_t entries); +extern int uwb_est_unregister(u8 type, u8 code_high, u16 vendor, u16 product, + const struct uwb_est_entry *, size_t entries); +extern ssize_t uwb_est_find_size(struct uwb_rc *, const struct uwb_rceb *, + size_t); + +/* -- Misc */ + +enum { + EDC_MAX_ERRORS = 10, + EDC_ERROR_TIMEFRAME = HZ, +}; + +/* error density counter */ +struct edc { + unsigned long timestart; + u16 errorcount; +}; + +static inline +void edc_init(struct edc *edc) +{ + edc->timestart = jiffies; +} + +/* Called when an error occured. + * This is way to determine if the number of acceptable errors per time + * period has been exceeded. It is not accurate as there are cases in which + * this scheme will not work, for example if there are periodic occurences + * of errors that straddle updates to the start time. This scheme is + * sufficient for our usage. + * + * @returns 1 if maximum acceptable errors per timeframe has been exceeded. + */ +static inline int edc_inc(struct edc *err_hist, u16 max_err, u16 timeframe) +{ + unsigned long now; + + now = jiffies; + if (now - err_hist->timestart > timeframe) { + err_hist->errorcount = 1; + err_hist->timestart = now; + } else if (++err_hist->errorcount > max_err) { + err_hist->errorcount = 0; + err_hist->timestart = now; + return 1; + } + return 0; +} + + +/* Information Element handling */ + +/* For representing the state of writing to a buffer when iterating */ +struct uwb_buf_ctx { + char *buf; + size_t bytes, size; +}; + +typedef int (*uwb_ie_f)(struct uwb_dev *, const struct uwb_ie_hdr *, + size_t, void *); +struct uwb_ie_hdr *uwb_ie_next(void **ptr, size_t *len); +ssize_t uwb_ie_for_each(struct uwb_dev *uwb_dev, uwb_ie_f fn, void *data, + const void *buf, size_t size); +int uwb_ie_dump_hex(struct uwb_dev *, const struct uwb_ie_hdr *, + size_t, void *); +int uwb_rc_set_ie(struct uwb_rc *, struct uwb_rc_cmd_set_ie *); +struct uwb_ie_hdr *uwb_ie_next(void **ptr, size_t *len); + + +/* + * Transmission statistics + * + * UWB uses LQI and RSSI (one byte values) for reporting radio signal + * strength and line quality indication. We do quick and dirty + * averages of those. They are signed values, btw. + * + * For 8 bit quantities, we keep the min, the max, an accumulator + * (@sigma) and a # of samples. When @samples gets to 255, we compute + * the average (@sigma / @samples), place it in @sigma and reset + * @samples to 1 (so we use it as the first sample). + * + * Now, statistically speaking, probably I am kicking the kidneys of + * some books I have in my shelves collecting dust, but I just want to + * get an approx, not the Nobel. + * + * LOCKING: there is no locking per se, but we try to keep a lockless + * schema. Only _add_samples() modifies the values--as long as you + * have other locking on top that makes sure that no two calls of + * _add_sample() happen at the same time, then we are fine. Now, for + * resetting the values we just set @samples to 0 and that makes the + * next _add_sample() to start with defaults. Reading the values in + * _show() currently can race, so you need to make sure the calls are + * under the same lock that protects calls to _add_sample(). FIXME: + * currently unlocked (It is not ultraprecise but does the trick. Bite + * me). + */ +struct stats { + s8 min, max; + s16 sigma; + atomic_t samples; +}; + +static inline +void stats_init(struct stats *stats) +{ + atomic_set(&stats->samples, 0); + wmb(); +} + +static inline +void stats_add_sample(struct stats *stats, s8 sample) +{ + s8 min, max; + s16 sigma; + unsigned samples = atomic_read(&stats->samples); + if (samples == 0) { /* it was zero before, so we initialize */ + min = 127; + max = -128; + sigma = 0; + } else { + min = stats->min; + max = stats->max; + sigma = stats->sigma; + } + + if (sample < min) /* compute new values */ + min = sample; + else if (sample > max) + max = sample; + sigma += sample; + + stats->min = min; /* commit */ + stats->max = max; + stats->sigma = sigma; + if (atomic_add_return(1, &stats->samples) > 255) { + /* wrapped around! reset */ + stats->sigma = sigma / 256; + atomic_set(&stats->samples, 1); + } +} + +static inline ssize_t stats_show(struct stats *stats, char *buf) +{ + int min, max, avg; + int samples = atomic_read(&stats->samples); + if (samples == 0) + min = max = avg = 0; + else { + min = stats->min; + max = stats->max; + avg = stats->sigma / samples; + } + return scnprintf(buf, PAGE_SIZE, "%d %d %d\n", min, max, avg); +} + +static inline ssize_t stats_store(struct stats *stats, const char *buf, + size_t size) +{ + stats_init(stats); + return size; +} + +#endif /* #ifndef __LINUX__UWB_H__ */ diff --git a/include/linux/uwb/debug-cmd.h b/include/linux/uwb/debug-cmd.h new file mode 100644 index 000000000000..1141f41bab5c --- /dev/null +++ b/include/linux/uwb/debug-cmd.h @@ -0,0 +1,57 @@ +/* + * Ultra Wide Band + * Debug interface commands + * + * Copyright (C) 2008 Cambridge Silicon Radio Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __LINUX__UWB__DEBUG_CMD_H__ +#define __LINUX__UWB__DEBUG_CMD_H__ + +#include <linux/types.h> + +/* + * Debug interface commands + * + * UWB_DBG_CMD_RSV_ESTABLISH: Establish a new unicast reservation. + * + * UWB_DBG_CMD_RSV_TERMINATE: Terminate the Nth reservation. + */ + +enum uwb_dbg_cmd_type { + UWB_DBG_CMD_RSV_ESTABLISH = 1, + UWB_DBG_CMD_RSV_TERMINATE = 2, +}; + +struct uwb_dbg_cmd_rsv_establish { + __u8 target[6]; + __u8 type; + __u16 max_mas; + __u16 min_mas; + __u8 sparsity; +}; + +struct uwb_dbg_cmd_rsv_terminate { + int index; +}; + +struct uwb_dbg_cmd { + __u32 type; + union { + struct uwb_dbg_cmd_rsv_establish rsv_establish; + struct uwb_dbg_cmd_rsv_terminate rsv_terminate; + }; +}; + +#endif /* #ifndef __LINUX__UWB__DEBUG_CMD_H__ */ diff --git a/include/linux/uwb/debug.h b/include/linux/uwb/debug.h new file mode 100644 index 000000000000..6a898bda4359 --- /dev/null +++ b/include/linux/uwb/debug.h @@ -0,0 +1,82 @@ +/* + * Ultra Wide Band + * Debug Support + * + * Copyright (C) 2005-2006 Intel Corporation + * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * + * FIXME: doc + * Invoke like: + * + * #define D_LOCAL 4 + * #include <linux/uwb/debug.h> + * + * At the end of your include files. + */ +#include <linux/types.h> + +struct device; +extern void dump_bytes(struct device *dev, const void *_buf, size_t rsize); + +/* Master debug switch; !0 enables, 0 disables */ +#define D_MASTER !0 + +/* Local (per-file) debug switch; #define before #including */ +#ifndef D_LOCAL +#define D_LOCAL 0 +#endif + +#undef __d_printf +#undef d_fnstart +#undef d_fnend +#undef d_printf +#undef d_dump + +#define __d_printf(l, _tag, _dev, f, a...) \ +do { \ + struct device *__dev = (_dev); \ + if (D_MASTER && D_LOCAL >= (l)) { \ + char __head[64] = ""; \ + if (_dev != NULL) { \ + if ((unsigned long)__dev < 4096) \ + printk(KERN_ERR "E: Corrupt dev %p\n", \ + __dev); \ + else \ + snprintf(__head, sizeof(__head), \ + "%s %s: ", \ + dev_driver_string(__dev), \ + dev_name(__dev)); \ + } \ + printk(KERN_ERR "%s%s" _tag ": " f, __head, \ + __func__, ## a); \ + } \ +} while (0 && _dev) + +#define d_fnstart(l, _dev, f, a...) \ + __d_printf(l, " FNSTART", _dev, f, ## a) +#define d_fnend(l, _dev, f, a...) \ + __d_printf(l, " FNEND", _dev, f, ## a) +#define d_printf(l, _dev, f, a...) \ + __d_printf(l, "", _dev, f, ## a) +#define d_dump(l, _dev, ptr, size) \ +do { \ + struct device *__dev = _dev; \ + if (D_MASTER && D_LOCAL >= (l)) \ + dump_bytes(__dev, ptr, size); \ +} while (0 && _dev) +#define d_test(l) (D_MASTER && D_LOCAL >= (l)) diff --git a/include/linux/uwb/spec.h b/include/linux/uwb/spec.h new file mode 100644 index 000000000000..102425903090 --- /dev/null +++ b/include/linux/uwb/spec.h @@ -0,0 +1,625 @@ +/* + * Ultra Wide Band + * UWB Standard definitions + * + * Copyright (C) 2005-2006 Intel Corporation + * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * + * All these definitions are based on the ECMA-368 standard. + * + * Note all definitions are Little Endian in the wire, and we will + * convert them to host order before operating on the bitfields (that + * yes, we use extensively). + */ + +#ifndef __LINUX__UWB_SPEC_H__ +#define __LINUX__UWB_SPEC_H__ + +#include <linux/types.h> +#include <linux/bitmap.h> +#include <linux/byteorder/bitfields.h> + +#define i1480_FW 0x00000303 +/* #define i1480_FW 0x00000302 */ + +/** + * Number of Medium Access Slots in a superframe. + * + * UWB divides time in SuperFrames, each one divided in 256 pieces, or + * Medium Access Slots. See MBOA MAC[5.4.5] for details. The MAS is the + * basic bandwidth allocation unit in UWB. + */ +enum { UWB_NUM_MAS = 256 }; + +/** + * Number of Zones in superframe. + * + * UWB divides the superframe into zones with numbering starting from BPST. + * See MBOA MAC[16.8.6] + */ +enum { UWB_NUM_ZONES = 16 }; + +/* + * Number of MAS in a zone. + */ +#define UWB_MAS_PER_ZONE (UWB_NUM_MAS / UWB_NUM_ZONES) + +/* + * Number of streams per DRP reservation between a pair of devices. + * + * [ECMA-368] section 16.8.6. + */ +enum { UWB_NUM_STREAMS = 8 }; + +/* + * mMasLength + * + * The length of a MAS in microseconds. + * + * [ECMA-368] section 17.16. + */ +enum { UWB_MAS_LENGTH_US = 256 }; + +/* + * mBeaconSlotLength + * + * The length of the beacon slot in microseconds. + * + * [ECMA-368] section 17.16 + */ +enum { UWB_BEACON_SLOT_LENGTH_US = 85 }; + +/* + * mMaxLostBeacons + * + * The number beacons missing in consecutive superframes before a + * device can be considered as unreachable. + * + * [ECMA-368] section 17.16 + */ +enum { UWB_MAX_LOST_BEACONS = 3 }; + +/* + * Length of a superframe in microseconds. + */ +#define UWB_SUPERFRAME_LENGTH_US (UWB_MAS_LENGTH_US * UWB_NUM_MAS) + +/** + * UWB MAC address + * + * It is *imperative* that this struct is exactly 6 packed bytes (as + * it is also used to define headers sent down and up the wire/radio). + */ +struct uwb_mac_addr { + u8 data[6]; +} __attribute__((packed)); + + +/** + * UWB device address + * + * It is *imperative* that this struct is exactly 6 packed bytes (as + * it is also used to define headers sent down and up the wire/radio). + */ +struct uwb_dev_addr { + u8 data[2]; +} __attribute__((packed)); + + +/** + * Types of UWB addresses + * + * Order matters (by size). + */ +enum uwb_addr_type { + UWB_ADDR_DEV = 0, + UWB_ADDR_MAC = 1, +}; + + +/** Size of a char buffer for printing a MAC/device address */ +enum { UWB_ADDR_STRSIZE = 32 }; + + +/** UWB WiMedia protocol IDs. */ +enum uwb_prid { + UWB_PRID_WLP_RESERVED = 0x0000, + UWB_PRID_WLP = 0x0001, + UWB_PRID_WUSB_BOT = 0x0010, + UWB_PRID_WUSB = 0x0010, + UWB_PRID_WUSB_TOP = 0x001F, +}; + + +/** PHY Rate (MBOA MAC[7.8.12, Table 61]) */ +enum uwb_phy_rate { + UWB_PHY_RATE_53 = 0, + UWB_PHY_RATE_80, + UWB_PHY_RATE_106, + UWB_PHY_RATE_160, + UWB_PHY_RATE_200, + UWB_PHY_RATE_320, + UWB_PHY_RATE_400, + UWB_PHY_RATE_480, + UWB_PHY_RATE_INVALID +}; + + +/** + * Different ways to scan (MBOA MAC[6.2.2, Table 8], WUSB[Table 8-78]) + */ +enum uwb_scan_type { + UWB_SCAN_ONLY = 0, + UWB_SCAN_OUTSIDE_BP, + UWB_SCAN_WHILE_INACTIVE, + UWB_SCAN_DISABLED, + UWB_SCAN_ONLY_STARTTIME, + UWB_SCAN_TOP +}; + + +/** ACK Policy types (MBOA MAC[7.2.1.3]) */ +enum uwb_ack_pol { + UWB_ACK_NO = 0, + UWB_ACK_INM = 1, + UWB_ACK_B = 2, + UWB_ACK_B_REQ = 3, +}; + + +/** DRP reservation types ([ECMA-368 table 106) */ +enum uwb_drp_type { + UWB_DRP_TYPE_ALIEN_BP = 0, + UWB_DRP_TYPE_HARD, + UWB_DRP_TYPE_SOFT, + UWB_DRP_TYPE_PRIVATE, + UWB_DRP_TYPE_PCA, +}; + + +/** DRP Reason Codes ([ECMA-368] table 107) */ +enum uwb_drp_reason { + UWB_DRP_REASON_ACCEPTED = 0, + UWB_DRP_REASON_CONFLICT, + UWB_DRP_REASON_PENDING, + UWB_DRP_REASON_DENIED, + UWB_DRP_REASON_MODIFIED, +}; + +/** + * DRP Notification Reason Codes (WHCI 0.95 [3.1.4.9]) + */ +enum uwb_drp_notif_reason { + UWB_DRP_NOTIF_DRP_IE_RCVD = 0, + UWB_DRP_NOTIF_CONFLICT, + UWB_DRP_NOTIF_TERMINATE, +}; + + +/** Allocation of MAS slots in a DRP request MBOA MAC[7.8.7] */ +struct uwb_drp_alloc { + __le16 zone_bm; + __le16 mas_bm; +} __attribute__((packed)); + + +/** General MAC Header format (ECMA-368[16.2]) */ +struct uwb_mac_frame_hdr { + union { + __le16 Frame_Control; + DECL_BF_LE7( + u16 Protocol_Version:3, + u16 Secure:1, + u16 ACK_Policy:2, + u16 Frame_Type:2, + u16 Frame_Subtype:4, + u16 Retry:1, + u16 Reserved:2 + ) __attribute__((packed)); + }; + struct uwb_dev_addr DestAddr; + struct uwb_dev_addr SrcAddr; + union { + __le16 Sequence_Control; + DECL_BF_LE4( + u16 Fragment_Number:3, + u16 Sequence_Number:11, + u16 More_Fragments:1, + u16 Reserved:1 + ) __attribute__((packed)); + }; + union { + __le16 Access_Information; + DECL_BF_LE3( + u16 Duration:14, + u16 More_Frames:1, + u16 Access_Method:1 + ) __attribute__((packed)); + }; +} __attribute__((packed)); + + +/** + * uwb_beacon_frame - a beacon frame including MAC headers + * + * [ECMA] section 16.3. + */ +struct uwb_beacon_frame { + struct uwb_mac_frame_hdr hdr; + struct uwb_mac_addr Device_Identifier; /* may be a NULL EUI-48 */ + u8 Beacon_Slot_Number; + union { + u8 Device_Control; + DECL_BF_LE3( + u8 Movable:1, + u8 Security_Mode:2, + u8 Reserved:5 + ) __attribute__((packed)); + }; + u8 IEData[]; +} __attribute__((packed)); + + +/** Information Element codes (MBOA MAC[T54]) */ +enum uwb_ie { + UWB_PCA_AVAILABILITY = 2, + UWB_IE_DRP_AVAILABILITY = 8, + UWB_IE_DRP = 9, + UWB_BP_SWITCH_IE = 11, + UWB_MAC_CAPABILITIES_IE = 12, + UWB_PHY_CAPABILITIES_IE = 13, + UWB_APP_SPEC_PROBE_IE = 15, + UWB_IDENTIFICATION_IE = 19, + UWB_MASTER_KEY_ID_IE = 20, + UWB_IE_WLP = 250, /* WiMedia Logical Link Control Protocol WLP 0.99 */ + UWB_APP_SPEC_IE = 255, +}; + + +/** + * Header common to all Information Elements (IEs) + */ +struct uwb_ie_hdr { + u8 element_id; /* enum uwb_ie */ + u8 length; +} __attribute__((packed)); + + +/** Dynamic Reservation Protocol IE (MBOA MAC[7.8.6]) */ +struct uwb_ie_drp { + struct uwb_ie_hdr hdr; + union { + __le16 DRP_Control; + DECL_BF_LE8( + enum uwb_drp_type type:3, + u8 stream_index:3, + enum uwb_drp_reason reason_code:3, + u8 status:1, + u8 owner:1, + u8 tiebreaker:1, + u8 unsafe:1, + u8 reserved:3 + ) __attribute__((packed)); + }; + struct uwb_dev_addr dev_addr; + struct uwb_drp_alloc allocs[]; +} __attribute__((packed)); + +/** Dynamic Reservation Protocol IE (MBOA MAC[7.8.7]) */ +struct uwb_ie_drp_avail { + struct uwb_ie_hdr hdr; + DECLARE_BITMAP(bmp, UWB_NUM_MAS); +} __attribute__((packed)); + +/** + * The Vendor ID is set to an OUI that indicates the vendor of the device. + * ECMA-368 [16.8.10] + */ +struct uwb_vendor_id { + u8 data[3]; +} __attribute__((packed)); + +/** + * The device type ID + * FIXME: clarify what this means + * ECMA-368 [16.8.10] + */ +struct uwb_device_type_id { + u8 data[3]; +} __attribute__((packed)); + + +/** + * UWB device information types + * ECMA-368 [16.8.10] + */ +enum uwb_dev_info_type { + UWB_DEV_INFO_VENDOR_ID = 0, + UWB_DEV_INFO_VENDOR_TYPE, + UWB_DEV_INFO_NAME, +}; + +/** + * UWB device information found in Identification IE + * ECMA-368 [16.8.10] + */ +struct uwb_dev_info { + u8 type; /* enum uwb_dev_info_type */ + u8 length; + u8 data[]; +} __attribute__((packed)); + +/** + * UWB Identification IE + * ECMA-368 [16.8.10] + */ +struct uwb_identification_ie { + struct uwb_ie_hdr hdr; + struct uwb_dev_info info[]; +} __attribute__((packed)); + +/* + * UWB Radio Controller + * + * These definitions are common to the Radio Control layers as + * exported by the WUSB1.0 HWA and WHCI interfaces. + */ + +/** Radio Control Command Block (WUSB1.0[Table 8-65] and WHCI 0.95) */ +struct uwb_rccb { + u8 bCommandType; /* enum hwa_cet */ + __le16 wCommand; /* Command code */ + u8 bCommandContext; /* Context ID */ +} __attribute__((packed)); + + +/** Radio Control Event Block (WUSB[table 8-66], WHCI 0.95) */ +struct uwb_rceb { + u8 bEventType; /* enum hwa_cet */ + __le16 wEvent; /* Event code */ + u8 bEventContext; /* Context ID */ +} __attribute__((packed)); + + +enum { + UWB_RC_CET_GENERAL = 0, /* General Command/Event type */ +}; + +/* Commands to the radio controller */ +enum uwb_rc_cmd { + UWB_RC_CMD_CHANNEL_CHANGE = 16, + UWB_RC_CMD_DEV_ADDR_MGMT = 17, /* Device Address Management */ + UWB_RC_CMD_GET_IE = 18, /* GET Information Elements */ + UWB_RC_CMD_RESET = 19, + UWB_RC_CMD_SCAN = 20, /* Scan management */ + UWB_RC_CMD_SET_BEACON_FILTER = 21, + UWB_RC_CMD_SET_DRP_IE = 22, /* Dynamic Reservation Protocol IEs */ + UWB_RC_CMD_SET_IE = 23, /* Information Element management */ + UWB_RC_CMD_START_BEACON = 27, + UWB_RC_CMD_STOP_BEACON = 28, + UWB_RC_CMD_BP_MERGE = 29, + UWB_RC_CMD_SEND_COMMAND_FRAME = 30, + UWB_RC_CMD_SET_ASIE_NOTIF = 31, +}; + + +/* Notifications from the radio controller */ +enum uwb_rc_evt { + UWB_RC_EVT_BEACON = 1, + UWB_RC_EVT_BEACON_SIZE = 2, + UWB_RC_EVT_BPOIE_CHANGE = 3, + UWB_RC_EVT_BP_SLOT_CHANGE = 4, + UWB_RC_EVT_DEV_ADDR_CONFLICT = 6, + UWB_RC_EVT_DRP_AVAIL = 7, + UWB_RC_EVT_DRP = 8, + UWB_RC_EVT_BP_SWITCH_STATUS = 9, + UWB_RC_EVT_CMD_FRAME_RCV = 10, + UWB_RC_EVT_CHANNEL_CHANGE_IE_RCV = 11, + /* Events (command responses) use the same code as the command */ +}; + + +/** Confirm event structure */ +struct uwb_rc_evt_confirm { + struct uwb_rceb rceb; + u8 bResultCode; +} __attribute__((packed)); + + +/** Device Address Management event */ +struct uwb_rc_evt_dev_addr_mgmt { + struct uwb_rceb rceb; + u8 baAddr[6]; + u8 bResultCode; +} __attribute__((packed)); + + +/** Get IE Event structure (response to Get IE command). */ +struct uwb_rc_evt_get_ie { + struct uwb_rceb rceb; + __le16 wIELength; + u8 IEData[]; +} __attribute__((packed)); + +/** + * SET DRP IE Event structure + * + * WHCI 0.95 [3.1.3.7] + */ +struct uwb_rc_evt_set_drp_ie { + struct uwb_rceb rceb; + __le16 wRemainingSpace; + u8 bResultCode; +} __attribute__((packed)); + +/** + * SET IE Event structure (response to SET IE command). + * + * WHCI 0.95 [3.1.3.8] + */ +struct uwb_rc_evt_set_ie { + struct uwb_rceb rceb; + __le16 RemainingSpace; + u8 bResultCode; +} __attribute__((packed)); + + +/** + * Type of the received beacon. WHCI 0.95 [3.1.4.2] + */ +enum uwb_rc_beacon_type { + UWB_RC_BEACON_TYPE_SCAN = 0, + UWB_RC_BEACON_TYPE_NEIGHBOR, + UWB_RC_BEACON_TYPE_OL_ALIEN, + UWB_RC_BEACON_TYPE_NOL_ALIEN, +}; + +/** Radio Control Result Code (WHCI 0.95[Table 3-3])*/ +enum { + UWB_RC_RES_SUCCESS = 0, + UWB_RC_RES_FAIL, + UWB_RC_RES_FAIL_HARDWARE, + UWB_RC_RES_FAIL_NO_SLOTS, + UWB_RC_RES_FAIL_BEACON_TOO_LARGE, + UWB_RC_RES_FAIL_INVALID_PARAMETER, + UWB_RC_RES_FAIL_UNSUPPORTED_PWR_LEVEL, + UWB_RC_RES_FAIL_INVALID_IE_DATA, + UWB_RC_RES_FAIL_BEACON_SIZE_EXCEEDED, + UWB_RC_RES_FAIL_CANCELLED, + UWB_RC_RES_FAIL_INVALID_STATE, + UWB_RC_RES_FAIL_INVALID_SIZE, + UWB_RC_RES_FAIL_ACK_NOT_RECEIVED, + UWB_RC_RES_FAIL_NO_MORE_ASIE_NOTIF, + UWB_RC_RES_FAIL_TIME_OUT = 255, +}; +/** + * Beacon received notification + * WHCI 0.95 [3.1.4.2] + */ +struct uwb_rc_evt_beacon { + struct uwb_rceb rceb; + u8 bChannelNumber; + u8 bBeaconType; + __le16 wBPSTOffset; + u8 bLQI; + u8 bRSSI; + __le16 wBeaconInfoLength; + u8 BeaconInfo[]; +} __attribute__((packed)); + + +/** Beacon Size notification */ +struct uwb_rc_evt_beacon_size { + struct uwb_rceb rceb; + __le16 wNewBeaconSize; +} __attribute__((packed)); + + +/** BPOIE Change notification */ +struct uwb_rc_evt_bpoie_change { + struct uwb_rceb rceb; + __le16 wBPOIELength; + u8 BPOIE[]; +} __attribute__((packed)); + + +/** + * Beacon slot change notification + * WHCI 0.95 [3.1.4.5] + */ +struct uwb_rc_evt_bp_slot_change { + struct uwb_rceb rceb; + DECL_BF_LE2( + u8 bSlotNumber:7, + u8 bNoSlot:1 + ) __attribute__((packed)); +} __attribute__((packed)); + + +/** + * DRP notification + * WHCI 0.95 [3.1.4.9] + */ +struct uwb_rc_evt_drp { + struct uwb_rceb rceb; + struct uwb_dev_addr wSrcAddr; + DECL_BF_LE2( + u8 Reserved:4, + enum uwb_drp_notif_reason Reason:4 + )__attribute__((packed)); + u8 bBeaconSlotNumber; + __le16 wIELength; + u8 IEData[]; +} __attribute__((packed)); + + +/** + * DRP Availability change notification + * WHCI 0.95 [3.1.4.8] + */ +struct uwb_rc_evt_drp_avail { + struct uwb_rceb rceb; + DECLARE_BITMAP(bmp, UWB_NUM_MAS); +} __attribute__((packed)); + +/** + * Scan Command + * WHCI 0.95 [3.1.3.5] + */ +struct uwb_rc_cmd_scan { + struct uwb_rccb rccb; + u8 bChannelNumber; + u8 bScanState; + __le16 wStartTime; +} __attribute__((packed)); + +/** + * SET DRP IE Command structure + * + * WHCI 0.95 [3.1.3.7] + */ +struct uwb_rc_cmd_set_drp_ie { + struct uwb_rccb rccb; + __le16 wIELength; + struct uwb_ie_drp IEData[]; +} __attribute__((packed)); + +/** + * SET IE Command structure + * + * WHCI 0.95 [3.1.3.8] + */ +struct uwb_rc_cmd_set_ie { + struct uwb_rccb rccb; + __le16 wIELength; + u8 IEData[]; +} __attribute__((packed)); + + +/** + * Radio Control Interface Class Descriptor + * + * WUSB 1.0 [8.6.1.2] + */ +struct uwb_rc_control_intf_class_desc { + u8 bLength; + u8 bDescriptorType; + __le16 bcdRCIVersion; +} __attribute__((packed)); + +#endif /* #ifndef __LINUX__UWB_SPEC_H__ */ diff --git a/include/linux/uwb/umc.h b/include/linux/uwb/umc.h new file mode 100644 index 000000000000..071224df9347 --- /dev/null +++ b/include/linux/uwb/umc.h @@ -0,0 +1,194 @@ +/* + * UWB Multi-interface Controller support. + * + * Copyright (C) 2007 Cambridge Silicon Radio Ltd. + * + * This file is released under the GPLv2 + * + * UMC (UWB Multi-interface Controller) capabilities (e.g., radio + * controller, host controller) are presented as devices on the "umc" + * bus. + * + * The radio controller is not strictly a UMC capability but it's + * useful to present it as such. + * + * References: + * + * [WHCI] Wireless Host Controller Interface Specification for + * Certified Wireless Universal Serial Bus, revision 0.95. + * + * How this works is kind of convoluted but simple. The whci.ko driver + * loads when WHCI devices are detected. These WHCI devices expose + * many devices in the same PCI function (they couldn't have reused + * functions, no), so for each PCI function that exposes these many + * devices, whci ceates a umc_dev [whci_probe() -> whci_add_cap()] + * with umc_device_create() and adds it to the bus with + * umc_device_register(). + * + * umc_device_register() calls device_register() which will push the + * bus management code to load your UMC driver's somehting_probe() + * that you have registered for that capability code. + * + * Now when the WHCI device is removed, whci_remove() will go over + * each umc_dev assigned to each of the PCI function's capabilities + * and through whci_del_cap() call umc_device_unregister() each + * created umc_dev. Of course, if you are bound to the device, your + * driver's something_remove() will be called. + */ + +#ifndef _LINUX_UWB_UMC_H_ +#define _LINUX_UWB_UMC_H_ + +#include <linux/device.h> +#include <linux/pci.h> + +/* + * UMC capability IDs. + * + * 0x00 is reserved so use it for the radio controller device. + * + * [WHCI] table 2-8 + */ +#define UMC_CAP_ID_WHCI_RC 0x00 /* radio controller */ +#define UMC_CAP_ID_WHCI_WUSB_HC 0x01 /* WUSB host controller */ + +/** + * struct umc_dev - UMC capability device + * + * @version: version of the specification this capability conforms to. + * @cap_id: capability ID. + * @bar: PCI Bar (64 bit) where the resource lies + * @resource: register space resource. + * @irq: interrupt line. + */ +struct umc_dev { + u16 version; + u8 cap_id; + u8 bar; + struct resource resource; + unsigned irq; + struct device dev; +}; + +#define to_umc_dev(d) container_of(d, struct umc_dev, dev) + +/** + * struct umc_driver - UMC capability driver + * @cap_id: supported capability ID. + * @match: driver specific capability matching function. + * @match_data: driver specific data for match() (e.g., a + * table of pci_device_id's if umc_match_pci_id() is used). + */ +struct umc_driver { + char *name; + u8 cap_id; + int (*match)(struct umc_driver *, struct umc_dev *); + const void *match_data; + + int (*probe)(struct umc_dev *); + void (*remove)(struct umc_dev *); + int (*suspend)(struct umc_dev *, pm_message_t state); + int (*resume)(struct umc_dev *); + + struct device_driver driver; +}; + +#define to_umc_driver(d) container_of(d, struct umc_driver, driver) + +extern struct bus_type umc_bus_type; + +struct umc_dev *umc_device_create(struct device *parent, int n); +int __must_check umc_device_register(struct umc_dev *umc); +void umc_device_unregister(struct umc_dev *umc); + +int __must_check __umc_driver_register(struct umc_driver *umc_drv, + struct module *mod, + const char *mod_name); + +/** + * umc_driver_register - register a UMC capabiltity driver. + * @umc_drv: pointer to the driver. + */ +static inline int __must_check umc_driver_register(struct umc_driver *umc_drv) +{ + return __umc_driver_register(umc_drv, THIS_MODULE, KBUILD_MODNAME); +} +void umc_driver_unregister(struct umc_driver *umc_drv); + +/* + * Utility function you can use to match (umc_driver->match) against a + * null-terminated array of 'struct pci_device_id' in + * umc_driver->match_data. + */ +int umc_match_pci_id(struct umc_driver *umc_drv, struct umc_dev *umc); + +/** + * umc_parent_pci_dev - return the UMC's parent PCI device or NULL if none + * @umc_dev: UMC device whose parent PCI device we are looking for + * + * DIRTY!!! DON'T RELY ON THIS + * + * FIXME: This is as dirty as it gets, but we need some way to check + * the correct type of umc_dev->parent (so that for example, we can + * cast to pci_dev). Casting to pci_dev is necesary because at some + * point we need to request resources from the device. Mapping is + * easily over come (ioremap and stuff are bus agnostic), but hooking + * up to some error handlers (such as pci error handlers) might need + * this. + * + * THIS might (probably will) be removed in the future, so don't count + * on it. + */ +static inline struct pci_dev *umc_parent_pci_dev(struct umc_dev *umc_dev) +{ + struct pci_dev *pci_dev = NULL; + if (umc_dev->dev.parent->bus == &pci_bus_type) + pci_dev = to_pci_dev(umc_dev->dev.parent); + return pci_dev; +} + +/** + * umc_dev_get() - reference a UMC device. + * @umc_dev: Pointer to UMC device. + * + * NOTE: we are assuming in this whole scheme that the parent device + * is referenced at _probe() time and unreferenced at _remove() + * time by the parent's subsystem. + */ +static inline struct umc_dev *umc_dev_get(struct umc_dev *umc_dev) +{ + get_device(&umc_dev->dev); + return umc_dev; +} + +/** + * umc_dev_put() - unreference a UMC device. + * @umc_dev: Pointer to UMC device. + */ +static inline void umc_dev_put(struct umc_dev *umc_dev) +{ + put_device(&umc_dev->dev); +} + +/** + * umc_set_drvdata - set UMC device's driver data. + * @umc_dev: Pointer to UMC device. + * @data: Data to set. + */ +static inline void umc_set_drvdata(struct umc_dev *umc_dev, void *data) +{ + dev_set_drvdata(&umc_dev->dev, data); +} + +/** + * umc_get_drvdata - recover UMC device's driver data. + * @umc_dev: Pointer to UMC device. + */ +static inline void *umc_get_drvdata(struct umc_dev *umc_dev) +{ + return dev_get_drvdata(&umc_dev->dev); +} + +int umc_match_pci_id(struct umc_driver *umc_drv, struct umc_dev *umc); + +#endif /* #ifndef _LINUX_UWB_UMC_H_ */ diff --git a/include/linux/uwb/whci.h b/include/linux/uwb/whci.h new file mode 100644 index 000000000000..915ec23042d4 --- /dev/null +++ b/include/linux/uwb/whci.h @@ -0,0 +1,117 @@ +/* + * Wireless Host Controller Interface for Ultra-Wide-Band and Wireless USB + * + * Copyright (C) 2005-2006 Intel Corporation + * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * + * + * References: + * [WHCI] Wireless Host Controller Interface Specification for + * Certified Wireless Universal Serial Bus, revision 0.95. + */ +#ifndef _LINUX_UWB_WHCI_H_ +#define _LINUX_UWB_WHCI_H_ + +#include <linux/pci.h> + +/* + * UWB interface capability registers (offsets from UWBBASE) + * + * [WHCI] section 2.2 + */ +#define UWBCAPINFO 0x00 /* == UWBCAPDATA(0) */ +# define UWBCAPINFO_TO_N_CAPS(c) (((c) >> 0) & 0xFull) +#define UWBCAPDATA(n) (8*(n)) +# define UWBCAPDATA_TO_VERSION(c) (((c) >> 32) & 0xFFFFull) +# define UWBCAPDATA_TO_OFFSET(c) (((c) >> 18) & 0x3FFFull) +# define UWBCAPDATA_TO_BAR(c) (((c) >> 16) & 0x3ull) +# define UWBCAPDATA_TO_SIZE(c) ((((c) >> 8) & 0xFFull) * sizeof(u32)) +# define UWBCAPDATA_TO_CAP_ID(c) (((c) >> 0) & 0xFFull) + +/* Size of the WHCI capability data (including the RC capability) for + a device with n capabilities. */ +#define UWBCAPDATA_SIZE(n) (8 + 8*(n)) + + +/* + * URC registers (offsets from URCBASE) + * + * [WHCI] section 2.3 + */ +#define URCCMD 0x00 +# define URCCMD_RESET (1 << 31) /* UMC Hardware reset */ +# define URCCMD_RS (1 << 30) /* Run/Stop */ +# define URCCMD_EARV (1 << 29) /* Event Address Register Valid */ +# define URCCMD_ACTIVE (1 << 15) /* Command is active */ +# define URCCMD_IWR (1 << 14) /* Interrupt When Ready */ +# define URCCMD_SIZE_MASK 0x00000fff /* Command size mask */ +#define URCSTS 0x04 +# define URCSTS_EPS (1 << 17) /* Event Processing Status */ +# define URCSTS_HALTED (1 << 16) /* RC halted */ +# define URCSTS_HSE (1 << 10) /* Host System Error...fried */ +# define URCSTS_ER (1 << 9) /* Event Ready */ +# define URCSTS_RCI (1 << 8) /* Ready for Command Interrupt */ +# define URCSTS_INT_MASK 0x00000700 /* URC interrupt sources */ +# define URCSTS_ISI 0x000000ff /* Interrupt Source Identification */ +#define URCINTR 0x08 +# define URCINTR_EN_ALL 0x000007ff /* Enable all interrupt sources */ +#define URCCMDADDR 0x10 +#define URCEVTADDR 0x18 +# define URCEVTADDR_OFFSET_MASK 0xfff /* Event pointer offset mask */ + + +/** Write 32 bit @value to little endian register at @addr */ +static inline +void le_writel(u32 value, void __iomem *addr) +{ + iowrite32(value, addr); +} + + +/** Read from 32 bit little endian register at @addr */ +static inline +u32 le_readl(void __iomem *addr) +{ + return ioread32(addr); +} + + +/** Write 64 bit @value to little endian register at @addr */ +static inline +void le_writeq(u64 value, void __iomem *addr) +{ + iowrite32(value, addr); + iowrite32(value >> 32, addr + 4); +} + + +/** Read from 64 bit little endian register at @addr */ +static inline +u64 le_readq(void __iomem *addr) +{ + u64 value; + value = ioread32(addr); + value |= (u64)ioread32(addr + 4) << 32; + return value; +} + +extern int whci_wait_for(struct device *dev, u32 __iomem *reg, + u32 mask, u32 result, + unsigned long max_ms, const char *tag); + +#endif /* #ifndef _LINUX_UWB_WHCI_H_ */ diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index c1411189ba6c..9385c823a978 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h @@ -246,6 +246,7 @@ struct v4l2_capability #define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 /* Is a sliced VBI output device */ #define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */ #define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 /* Can do video output overlay */ +#define V4L2_CAP_HW_FREQ_SEEK 0x00000400 /* Can do hardware frequency seek */ #define V4L2_CAP_TUNER 0x00010000 /* has a tuner */ #define V4L2_CAP_AUDIO 0x00020000 /* has audio support */ @@ -865,9 +866,9 @@ struct v4l2_querymenu #define V4L2_CID_HFLIP (V4L2_CID_BASE+20) #define V4L2_CID_VFLIP (V4L2_CID_BASE+21) -/* Deprecated, use V4L2_CID_PAN_RESET and V4L2_CID_TILT_RESET */ -#define V4L2_CID_HCENTER_DEPRECATED (V4L2_CID_BASE+22) -#define V4L2_CID_VCENTER_DEPRECATED (V4L2_CID_BASE+23) +/* Deprecated; use V4L2_CID_PAN_RESET and V4L2_CID_TILT_RESET */ +#define V4L2_CID_HCENTER (V4L2_CID_BASE+22) +#define V4L2_CID_VCENTER (V4L2_CID_BASE+23) #define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24) enum v4l2_power_line_frequency { @@ -1156,6 +1157,14 @@ struct v4l2_frequency __u32 reserved[8]; }; +struct v4l2_hw_freq_seek { + __u32 tuner; + enum v4l2_tuner_type type; + __u32 seek_upward; + __u32 wrap_around; + __u32 reserved[8]; +}; + /* * A U D I O */ @@ -1441,6 +1450,7 @@ struct v4l2_chip_ident { #define VIDIOC_G_CHIP_IDENT _IOWR ('V', 81, struct v4l2_chip_ident) #endif +#define VIDIOC_S_HW_FREQ_SEEK _IOW ('V', 82, struct v4l2_hw_freq_seek) #ifdef __OLD_VIDIOC_ /* for compatibility, will go away some day */ diff --git a/include/linux/virtio_blk.h b/include/linux/virtio_blk.h index d4695a3356d0..52b593213f77 100644 --- a/include/linux/virtio_blk.h +++ b/include/linux/virtio_blk.h @@ -10,21 +10,25 @@ #define VIRTIO_BLK_F_SIZE_MAX 1 /* Indicates maximum segment size */ #define VIRTIO_BLK_F_SEG_MAX 2 /* Indicates maximum # of segments */ #define VIRTIO_BLK_F_GEOMETRY 4 /* Legacy geometry available */ +#define VIRTIO_BLK_F_RO 5 /* Disk is read-only */ +#define VIRTIO_BLK_F_BLK_SIZE 6 /* Block size of disk is available*/ struct virtio_blk_config { /* The capacity (in 512-byte sectors). */ - __le64 capacity; + __u64 capacity; /* The maximum segment size (if VIRTIO_BLK_F_SIZE_MAX) */ - __le32 size_max; + __u32 size_max; /* The maximum number of segments (if VIRTIO_BLK_F_SEG_MAX) */ - __le32 seg_max; + __u32 seg_max; /* geometry the device (if VIRTIO_BLK_F_GEOMETRY) */ struct virtio_blk_geometry { - __le16 cylinders; + __u16 cylinders; __u8 heads; __u8 sectors; } geometry; + /* block size of device (if VIRTIO_BLK_F_BLK_SIZE) */ + __u32 blk_size; } __attribute__((packed)); /* These two define direction. */ diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 50db245c81ad..59a65e33cfa2 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -15,6 +15,17 @@ /* We've given up on this device. */ #define VIRTIO_CONFIG_S_FAILED 0x80 +/* Some virtio feature bits (currently bits 28 through 31) are reserved for the + * transport being used (eg. virtio_ring), the rest are per-device feature + * bits. */ +#define VIRTIO_TRANSPORT_F_START 28 +#define VIRTIO_TRANSPORT_F_END 32 +#define VIRTIO_TRANSPORT_F_MASK 0xF0000000 + +/* Do we get callbacks when the ring is completely used, even if we've + * suppressed them? */ +#define VIRTIO_F_NOTIFY_ON_EMPTY 24 + #ifdef __KERNEL__ #include <linux/virtio.h> @@ -99,7 +110,7 @@ static inline bool virtio_has_feature(const struct virtio_device *vdev, * The return value is -ENOENT if the feature doesn't exist. Otherwise * the config value is copied into whatever is pointed to by v. */ #define virtio_config_val(vdev, fbit, offset, v) \ - virtio_config_buf((vdev), (fbit), (offset), (v), sizeof(v)) + virtio_config_buf((vdev), (fbit), (offset), (v), sizeof(*v)) static inline int virtio_config_buf(struct virtio_device *vdev, unsigned int fbit, diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h index 9405aa6cdf26..38c0571820fb 100644 --- a/include/linux/virtio_net.h +++ b/include/linux/virtio_net.h @@ -38,7 +38,7 @@ struct virtio_net_hdr #define VIRTIO_NET_HDR_GSO_ECN 0x80 // TCP has ECN set __u8 gso_type; __u16 hdr_len; /* Ethernet + IP + tcp/udp hdrs */ - __u16 gso_size; /* Bytes to append to gso_hdr_len per frame */ + __u16 gso_size; /* Bytes to append to hdr_len per frame */ __u16 csum_start; /* Position to start checksumming from */ __u16 csum_offset; /* Offset after that to place checksum */ }; diff --git a/include/linux/virtio_ring.h b/include/linux/virtio_ring.h index abe481ed990e..65fae97ccc69 100644 --- a/include/linux/virtio_ring.h +++ b/include/linux/virtio_ring.h @@ -24,6 +24,9 @@ * optimization. */ #define VRING_AVAIL_F_NO_INTERRUPT 1 +/* We publish our last-seen used index at the end of the avail ring. */ +#define VIRTIO_RING_F_PUBLISH_INDICES 28 + /* Virtio ring descriptors: 16 bytes. These can chain together via "next". */ struct vring_desc { @@ -82,6 +85,7 @@ struct vring { * __u16 avail_flags; * __u16 avail_idx; * __u16 available[num]; + * __u16 last_used_idx; * * // Padding to the next page boundary. * char pad[]; @@ -90,6 +94,7 @@ struct vring { * __u16 used_flags; * __u16 used_idx; * struct vring_used_elem used[num]; + * __u16 last_avail_idx; * }; */ static inline void vring_init(struct vring *vr, unsigned int num, void *p, @@ -106,9 +111,14 @@ static inline unsigned vring_size(unsigned int num, unsigned long pagesize) { return ((sizeof(struct vring_desc) * num + sizeof(__u16) * (2 + num) + pagesize - 1) & ~(pagesize - 1)) - + sizeof(__u16) * 2 + sizeof(struct vring_used_elem) * num; + + sizeof(__u16) * 2 + sizeof(struct vring_used_elem) * num + 2; } +/* We publish the last-seen used index at the end of the available ring, and + * vice-versa. These are at the end for backwards compatibility. */ +#define vring_last_used(vr) ((vr)->avail->ring[(vr)->num]) +#define vring_last_avail(vr) (*(__u16 *)&(vr)->used->ring[(vr)->num]) + #ifdef __KERNEL__ #include <linux/irqreturn.h> struct virtio_device; @@ -121,6 +131,9 @@ struct virtqueue *vring_new_virtqueue(unsigned int num, void (*callback)(struct virtqueue *vq)); void vring_del_virtqueue(struct virtqueue *vq); +/* Filter out unsupported transport-specific feature bits. */ +u32 vring_transport_features(u32 features); + irqreturn_t vring_interrupt(int irq, void *_vq); #endif /* __KERNEL__ */ #endif /* _LINUX_VIRTIO_RING_H */ diff --git a/include/linux/virtio_rng.h b/include/linux/virtio_rng.h new file mode 100644 index 000000000000..331afb6c9f62 --- /dev/null +++ b/include/linux/virtio_rng.h @@ -0,0 +1,8 @@ +#ifndef _LINUX_VIRTIO_RNG_H +#define _LINUX_VIRTIO_RNG_H +#include <linux/virtio_config.h> + +/* The ID for virtio_rng */ +#define VIRTIO_ID_RNG 4 + +#endif /* _LINUX_VIRTIO_RNG_H */ diff --git a/include/linux/wanrouter.h b/include/linux/wanrouter.h index 3add87465b1f..e0aa39612eba 100644 --- a/include/linux/wanrouter.h +++ b/include/linux/wanrouter.h @@ -522,7 +522,7 @@ extern int wanrouter_proc_init(void); extern void wanrouter_proc_cleanup(void); extern int wanrouter_proc_add(struct wan_device *wandev); extern int wanrouter_proc_delete(struct wan_device *wandev); -extern int wanrouter_ioctl( struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg); +extern long wanrouter_ioctl(struct file *file, unsigned int cmd, unsigned long arg); /* Public Data */ /* list of registered devices */ diff --git a/include/linux/wireless.h b/include/linux/wireless.h index 0a9b5b41ed67..4a95a0e5eeca 100644 --- a/include/linux/wireless.h +++ b/include/linux/wireless.h @@ -611,6 +611,7 @@ #define IW_ENCODE_ALG_WEP 1 #define IW_ENCODE_ALG_TKIP 2 #define IW_ENCODE_ALG_CCMP 3 +#define IW_ENCODE_ALG_PMK 4 /* struct iw_encode_ext ->ext_flags */ #define IW_ENCODE_EXT_TX_SEQ_VALID 0x00000001 #define IW_ENCODE_EXT_RX_SEQ_VALID 0x00000002 @@ -630,6 +631,7 @@ #define IW_ENC_CAPA_WPA2 0x00000002 #define IW_ENC_CAPA_CIPHER_TKIP 0x00000004 #define IW_ENC_CAPA_CIPHER_CCMP 0x00000008 +#define IW_ENC_CAPA_4WAY_HANDSHAKE 0x00000010 /* Event capability macros - in (struct iw_range *)->event_capa * Because we have more than 32 possible events, we use an array of diff --git a/include/linux/wlp.h b/include/linux/wlp.h new file mode 100644 index 000000000000..62d7cf443b41 --- /dev/null +++ b/include/linux/wlp.h @@ -0,0 +1,728 @@ +/* + * WiMedia Logical Link Control Protocol (WLP) + * + * Copyright (C) 2005-2006 Intel Corporation + * Reinette Chatre <reinette.chatre@intel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * + * FIXME: docs + * + * - Does not (yet) include support for WLP control frames + * WLP Draft 0.99 [6.5]. + * + * A visual representation of the data structures. + * + * wssidB wssidB + * ^ ^ + * | | + * wssidA wssidA + * wlp interface { ^ ^ + * ... | | + * ... ... wssid wssid ... + * wlp --- ... | | + * }; neighbors --> neighbA --> neighbB + * ... + * wss + * ... + * eda cache --> neighborA --> neighborB --> neighborC ... + */ + +#ifndef __LINUX__WLP_H_ +#define __LINUX__WLP_H_ + +#include <linux/netdevice.h> +#include <linux/skbuff.h> +#include <linux/list.h> +#include <linux/uwb.h> + +/** + * WLP Protocol ID + * WLP Draft 0.99 [6.2] + * + * The MUX header for all WLP frames + */ +#define WLP_PROTOCOL_ID 0x0100 + +/** + * WLP Version + * WLP version placed in the association frames (WLP 0.99 [6.6]) + */ +#define WLP_VERSION 0x10 + +/** + * Bytes needed to print UUID as string + */ +#define WLP_WSS_UUID_STRSIZE 48 + +/** + * Bytes needed to print nonce as string + */ +#define WLP_WSS_NONCE_STRSIZE 48 + + +/** + * Size used for WLP name size + * + * The WSS name is set to 65 bytes, 1 byte larger than the maximum + * allowed by the WLP spec. This is to have a null terminated string + * for display to the user. A maximum of 64 bytes will still be used + * when placing the WSS name field in association frames. + */ +#define WLP_WSS_NAME_SIZE 65 + +/** + * Number of bytes added by WLP to data frame + * + * A data frame transmitted from a host will be placed in a Standard or + * Abbreviated WLP frame. These have an extra 4 bytes of header (struct + * wlp_frame_std_abbrv_hdr). + * When the stack sends this data frame for transmission it needs to ensure + * there is enough headroom for this header. + */ +#define WLP_DATA_HLEN 4 + +/** + * State of device regarding WLP Service Set + * + * WLP_WSS_STATE_NONE: the host does not participate in any WSS + * WLP_WSS_STATE_PART_ENROLLED: used as part of the enrollment sequence + * ("Partial Enroll"). This state is used to + * indicate the first part of enrollment that is + * unsecure. If the WSS is unsecure then the + * state will promptly go to WLP_WSS_STATE_ENROLLED, + * if the WSS is not secure then the enrollment + * procedure is a few more steps before we are + * enrolled. + * WLP_WSS_STATE_ENROLLED: the host is enrolled in a WSS + * WLP_WSS_STATE_ACTIVE: WSS is activated + * WLP_WSS_STATE_CONNECTED: host is connected to neighbor in WSS + * + */ +enum wlp_wss_state { + WLP_WSS_STATE_NONE = 0, + WLP_WSS_STATE_PART_ENROLLED, + WLP_WSS_STATE_ENROLLED, + WLP_WSS_STATE_ACTIVE, + WLP_WSS_STATE_CONNECTED, +}; + +/** + * WSS Secure status + * WLP 0.99 Table 6 + * + * Set to one if the WSS is secure, zero if it is not secure + */ +enum wlp_wss_sec_status { + WLP_WSS_UNSECURE = 0, + WLP_WSS_SECURE, +}; + +/** + * WLP frame type + * WLP Draft 0.99 [6.2 Table 1] + */ +enum wlp_frame_type { + WLP_FRAME_STANDARD = 0, + WLP_FRAME_ABBREVIATED, + WLP_FRAME_CONTROL, + WLP_FRAME_ASSOCIATION, +}; + +/** + * WLP Association Message Type + * WLP Draft 0.99 [6.6.1.2 Table 8] + */ +enum wlp_assoc_type { + WLP_ASSOC_D1 = 2, + WLP_ASSOC_D2 = 3, + WLP_ASSOC_M1 = 4, + WLP_ASSOC_M2 = 5, + WLP_ASSOC_M3 = 7, + WLP_ASSOC_M4 = 8, + WLP_ASSOC_M5 = 9, + WLP_ASSOC_M6 = 10, + WLP_ASSOC_M7 = 11, + WLP_ASSOC_M8 = 12, + WLP_ASSOC_F0 = 14, + WLP_ASSOC_E1 = 32, + WLP_ASSOC_E2 = 33, + WLP_ASSOC_C1 = 34, + WLP_ASSOC_C2 = 35, + WLP_ASSOC_C3 = 36, + WLP_ASSOC_C4 = 37, +}; + +/** + * WLP Attribute Type + * WLP Draft 0.99 [6.6.1 Table 6] + */ +enum wlp_attr_type { + WLP_ATTR_AUTH = 0x1005, /* Authenticator */ + WLP_ATTR_DEV_NAME = 0x1011, /* Device Name */ + WLP_ATTR_DEV_PWD_ID = 0x1012, /* Device Password ID */ + WLP_ATTR_E_HASH1 = 0x1014, /* E-Hash1 */ + WLP_ATTR_E_HASH2 = 0x1015, /* E-Hash2 */ + WLP_ATTR_E_SNONCE1 = 0x1016, /* E-SNonce1 */ + WLP_ATTR_E_SNONCE2 = 0x1017, /* E-SNonce2 */ + WLP_ATTR_ENCR_SET = 0x1018, /* Encrypted Settings */ + WLP_ATTR_ENRL_NONCE = 0x101A, /* Enrollee Nonce */ + WLP_ATTR_KEYWRAP_AUTH = 0x101E, /* Key Wrap Authenticator */ + WLP_ATTR_MANUF = 0x1021, /* Manufacturer */ + WLP_ATTR_MSG_TYPE = 0x1022, /* Message Type */ + WLP_ATTR_MODEL_NAME = 0x1023, /* Model Name */ + WLP_ATTR_MODEL_NR = 0x1024, /* Model Number */ + WLP_ATTR_PUB_KEY = 0x1032, /* Public Key */ + WLP_ATTR_REG_NONCE = 0x1039, /* Registrar Nonce */ + WLP_ATTR_R_HASH1 = 0x103D, /* R-Hash1 */ + WLP_ATTR_R_HASH2 = 0x103E, /* R-Hash2 */ + WLP_ATTR_R_SNONCE1 = 0x103F, /* R-SNonce1 */ + WLP_ATTR_R_SNONCE2 = 0x1040, /* R-SNonce2 */ + WLP_ATTR_SERIAL = 0x1042, /* Serial number */ + WLP_ATTR_UUID_E = 0x1047, /* UUID-E */ + WLP_ATTR_UUID_R = 0x1048, /* UUID-R */ + WLP_ATTR_PRI_DEV_TYPE = 0x1054, /* Primary Device Type */ + WLP_ATTR_SEC_DEV_TYPE = 0x1055, /* Secondary Device Type */ + WLP_ATTR_PORT_DEV = 0x1056, /* Portable Device */ + WLP_ATTR_APP_EXT = 0x1058, /* Application Extension */ + WLP_ATTR_WLP_VER = 0x2000, /* WLP Version */ + WLP_ATTR_WSSID = 0x2001, /* WSSID */ + WLP_ATTR_WSS_NAME = 0x2002, /* WSS Name */ + WLP_ATTR_WSS_SEC_STAT = 0x2003, /* WSS Secure Status */ + WLP_ATTR_WSS_BCAST = 0x2004, /* WSS Broadcast Address */ + WLP_ATTR_WSS_M_KEY = 0x2005, /* WSS Master Key */ + WLP_ATTR_ACC_ENRL = 0x2006, /* Accepting Enrollment */ + WLP_ATTR_WSS_INFO = 0x2007, /* WSS Information */ + WLP_ATTR_WSS_SEL_MTHD = 0x2008, /* WSS Selection Method */ + WLP_ATTR_ASSC_MTHD_LIST = 0x2009, /* Association Methods List */ + WLP_ATTR_SEL_ASSC_MTHD = 0x200A, /* Selected Association Method */ + WLP_ATTR_ENRL_HASH_COMM = 0x200B, /* Enrollee Hash Commitment */ + WLP_ATTR_WSS_TAG = 0x200C, /* WSS Tag */ + WLP_ATTR_WSS_VIRT = 0x200D, /* WSS Virtual EUI-48 */ + WLP_ATTR_WLP_ASSC_ERR = 0x200E, /* WLP Association Error */ + WLP_ATTR_VNDR_EXT = 0x200F, /* Vendor Extension */ +}; + +/** + * WLP Category ID of primary/secondary device + * WLP Draft 0.99 [6.6.1.8 Table 12] + */ +enum wlp_dev_category_id { + WLP_DEV_CAT_COMPUTER = 1, + WLP_DEV_CAT_INPUT, + WLP_DEV_CAT_PRINT_SCAN_FAX_COPIER, + WLP_DEV_CAT_CAMERA, + WLP_DEV_CAT_STORAGE, + WLP_DEV_CAT_INFRASTRUCTURE, + WLP_DEV_CAT_DISPLAY, + WLP_DEV_CAT_MULTIM, + WLP_DEV_CAT_GAMING, + WLP_DEV_CAT_TELEPHONE, + WLP_DEV_CAT_OTHER = 65535, +}; + +/** + * WLP WSS selection method + * WLP Draft 0.99 [6.6.1.6 Table 10] + */ +enum wlp_wss_sel_mthd { + WLP_WSS_ENRL_SELECT = 1, /* Enrollee selects */ + WLP_WSS_REG_SELECT, /* Registrar selects */ +}; + +/** + * WLP association error values + * WLP Draft 0.99 [6.6.1.5 Table 9] + */ +enum wlp_assc_error { + WLP_ASSOC_ERROR_NONE, + WLP_ASSOC_ERROR_AUTH, /* Authenticator Failure */ + WLP_ASSOC_ERROR_ROGUE, /* Rogue activity suspected */ + WLP_ASSOC_ERROR_BUSY, /* Device busy */ + WLP_ASSOC_ERROR_LOCK, /* Setup Locked */ + WLP_ASSOC_ERROR_NOT_READY, /* Registrar not ready */ + WLP_ASSOC_ERROR_INV, /* Invalid WSS selection */ + WLP_ASSOC_ERROR_MSG_TIME, /* Message timeout */ + WLP_ASSOC_ERROR_ENR_TIME, /* Enrollment session timeout */ + WLP_ASSOC_ERROR_PW, /* Device password invalid */ + WLP_ASSOC_ERROR_VER, /* Unsupported version */ + WLP_ASSOC_ERROR_INT, /* Internal error */ + WLP_ASSOC_ERROR_UNDEF, /* Undefined error */ + WLP_ASSOC_ERROR_NUM, /* Numeric comparison failure */ + WLP_ASSOC_ERROR_WAIT, /* Waiting for user input */ +}; + +/** + * WLP Parameters + * WLP 0.99 [7.7] + */ +enum wlp_parameters { + WLP_PER_MSG_TIMEOUT = 15, /* Seconds to wait for response to + association message. */ +}; + +/** + * WLP IE + * + * The WLP IE should be included in beacons by all devices. + * + * The driver can set only a few of the fields in this information element, + * most fields are managed by the device self. When the driver needs to set + * a field it will only provide values for the fields of interest, the rest + * will be filled with zeroes. The fields of interest are: + * + * Element ID + * Length + * Capabilities (only to include WSSID Hash list length) + * WSSID Hash List fields + * + * WLP 0.99 [6.7] + * + * Only the fields that will be used are detailed in this structure, rest + * are not detailed or marked as "notused". + */ +struct wlp_ie { + struct uwb_ie_hdr hdr; + union { + __le16 capabilities; + DECL_BF_LE2( + u16 notused:12, + u16 hash_length:4 + ) __attribute__((packed)); + }; + __le16 cycle_param; + __le16 acw_anchor_addr; + u8 wssid_hash_list[]; +} __attribute__((packed)); + +/** + * WLP nonce + * WLP Draft 0.99 [6.6.1 Table 6] + * + * A 128-bit random number often used (E-SNonce1, E-SNonce2, Enrollee + * Nonce, Registrar Nonce, R-SNonce1, R-SNonce2). It is passed to HW so + * it is packed. + */ +struct wlp_nonce { + u8 data[16]; +} __attribute__((packed)); + +/** + * WLP UUID + * WLP Draft 0.99 [6.6.1 Table 6] + * + * Universally Unique Identifier (UUID) encoded as an octet string in the + * order the octets are shown in string representation in RFC4122. A UUID + * is often used (UUID-E, UUID-R, WSSID). It is passed to HW so it is packed. + */ +struct wlp_uuid { + u8 data[16]; +} __attribute__((packed)); + + +/** + * Primary and secondary device type attributes + * WLP Draft 0.99 [6.6.1.8] + */ +struct wlp_dev_type { + enum wlp_dev_category_id category:16; + u8 OUI[3]; + u8 OUIsubdiv; + __le16 subID; +} __attribute__((packed)); + +/** + * WLP frame header + * WLP Draft 0.99 [6.2] + */ +struct wlp_frame_hdr { + __le16 mux_hdr; /* WLP_PROTOCOL_ID */ + enum wlp_frame_type type:8; +} __attribute__((packed)); + +/** + * WLP attribute field header + * WLP Draft 0.99 [6.6.1] + * + * Header of each attribute found in an association frame + */ +struct wlp_attr_hdr { + __le16 type; + __le16 length; +} __attribute__((packed)); + +/** + * Device information commonly used together + * + * Each of these device information elements has a specified range in which it + * should fit (WLP 0.99 [Table 6]). This range provided in the spec does not + * include the termination null '\0' character (when used in the + * association protocol the attribute fields are accompanied + * with a "length" field so the full range from the spec can be used for + * the value). We thus allocate an extra byte to be able to store a string + * of max length with a terminating '\0'. + */ +struct wlp_device_info { + char name[33]; + char model_name[33]; + char manufacturer[65]; + char model_nr[33]; + char serial[33]; + struct wlp_dev_type prim_dev_type; +}; + +/** + * Macros for the WLP attributes + * + * There are quite a few attributes (total is 43). The attribute layout can be + * in one of three categories: one value, an array, an enum forced to 8 bits. + * These macros help with their definitions. + */ +#define wlp_attr(type, name) \ +struct wlp_attr_##name { \ + struct wlp_attr_hdr hdr; \ + type name; \ +} __attribute__((packed)); + +#define wlp_attr_array(type, name) \ +struct wlp_attr_##name { \ + struct wlp_attr_hdr hdr; \ + type name[]; \ +} __attribute__((packed)); + +/** + * WLP association attribute fields + * WLP Draft 0.99 [6.6.1 Table 6] + * + * Attributes appear in same order as the Table in the spec + * FIXME Does not define all attributes yet + */ + +/* Device name: Friendly name of sending device */ +wlp_attr_array(u8, dev_name) + +/* Enrollee Nonce: Random number generated by enrollee for an enrollment + * session */ +wlp_attr(struct wlp_nonce, enonce) + +/* Manufacturer name: Name of manufacturer of the sending device */ +wlp_attr_array(u8, manufacturer) + +/* WLP Message Type */ +wlp_attr(u8, msg_type) + +/* WLP Model name: Model name of sending device */ +wlp_attr_array(u8, model_name) + +/* WLP Model number: Model number of sending device */ +wlp_attr_array(u8, model_nr) + +/* Registrar Nonce: Random number generated by registrar for an enrollment + * session */ +wlp_attr(struct wlp_nonce, rnonce) + +/* Serial number of device */ +wlp_attr_array(u8, serial) + +/* UUID of enrollee */ +wlp_attr(struct wlp_uuid, uuid_e) + +/* UUID of registrar */ +wlp_attr(struct wlp_uuid, uuid_r) + +/* WLP Primary device type */ +wlp_attr(struct wlp_dev_type, prim_dev_type) + +/* WLP Secondary device type */ +wlp_attr(struct wlp_dev_type, sec_dev_type) + +/* WLP protocol version */ +wlp_attr(u8, version) + +/* WLP service set identifier */ +wlp_attr(struct wlp_uuid, wssid) + +/* WLP WSS name */ +wlp_attr_array(u8, wss_name) + +/* WLP WSS Secure Status */ +wlp_attr(u8, wss_sec_status) + +/* WSS Broadcast Address */ +wlp_attr(struct uwb_mac_addr, wss_bcast) + +/* WLP Accepting Enrollment */ +wlp_attr(u8, accept_enrl) + +/** + * WSS information attributes + * WLP Draft 0.99 [6.6.3 Table 15] + */ +struct wlp_wss_info { + struct wlp_attr_wssid wssid; + struct wlp_attr_wss_name name; + struct wlp_attr_accept_enrl accept; + struct wlp_attr_wss_sec_status sec_stat; + struct wlp_attr_wss_bcast bcast; +} __attribute__((packed)); + +/* WLP WSS Information */ +wlp_attr_array(struct wlp_wss_info, wss_info) + +/* WLP WSS Selection method */ +wlp_attr(u8, wss_sel_mthd) + +/* WLP WSS tag */ +wlp_attr(u8, wss_tag) + +/* WSS Virtual Address */ +wlp_attr(struct uwb_mac_addr, wss_virt) + +/* WLP association error */ +wlp_attr(u8, wlp_assc_err) + +/** + * WLP standard and abbreviated frames + * + * WLP Draft 0.99 [6.3] and [6.4] + * + * The difference between the WLP standard frame and the WLP + * abbreviated frame is that the standard frame includes the src + * and dest addresses from the Ethernet header, the abbreviated frame does + * not. + * The src/dest (as well as the type/length and client data) are already + * defined as part of the Ethernet header, we do not do this here. + * From this perspective the standard and abbreviated frames appear the + * same - they will be treated differently though. + * + * The size of this header is also captured in WLP_DATA_HLEN to enable + * interfaces to prepare their headroom. + */ +struct wlp_frame_std_abbrv_hdr { + struct wlp_frame_hdr hdr; + u8 tag; +} __attribute__((packed)); + +/** + * WLP association frames + * + * WLP Draft 0.99 [6.6] + */ +struct wlp_frame_assoc { + struct wlp_frame_hdr hdr; + enum wlp_assoc_type type:8; + struct wlp_attr_version version; + struct wlp_attr_msg_type msg_type; + u8 attr[]; +} __attribute__((packed)); + +/* Ethernet to dev address mapping */ +struct wlp_eda { + spinlock_t lock; + struct list_head cache; /* Eth<->Dev Addr cache */ +}; + +/** + * WSS information temporary storage + * + * This information is only stored temporarily during discovery. It should + * not be stored unless the device is enrolled in the advertised WSS. This + * is done mainly because we follow the letter of the spec in this regard. + * See WLP 0.99 [7.2.3]. + * When the device does become enrolled in a WSS the WSS information will + * be stored as part of the more comprehensive struct wlp_wss. + */ +struct wlp_wss_tmp_info { + char name[WLP_WSS_NAME_SIZE]; + u8 accept_enroll; + u8 sec_status; + struct uwb_mac_addr bcast; +}; + +struct wlp_wssid_e { + struct list_head node; + struct wlp_uuid wssid; + struct wlp_wss_tmp_info *info; +}; + +/** + * A cache entry of WLP neighborhood + * + * @node: head of list is wlp->neighbors + * @wssid: list of wssids of this neighbor, element is wlp_wssid_e + * @info: temporary storage for information learned during discovery. This + * storage is used together with the wssid_e temporary storage + * during discovery. + */ +struct wlp_neighbor_e { + struct list_head node; + struct wlp_uuid uuid; + struct uwb_dev *uwb_dev; + struct list_head wssid; /* Elements are wlp_wssid_e */ + struct wlp_device_info *info; +}; + +struct wlp; +/** + * Information for an association session in progress. + * + * @exp_message: The type of the expected message. Both this message and a + * F0 message (which can be sent in response to any + * association frame) will be accepted as a valid message for + * this session. + * @cb: The function that will be called upon receipt of this + * message. + * @cb_priv: Private data of callback + * @data: Data used in association process (always a sk_buff?) + * @neighbor: Address of neighbor with which association session is in + * progress. + */ +struct wlp_session { + enum wlp_assoc_type exp_message; + void (*cb)(struct wlp *); + void *cb_priv; + void *data; + struct uwb_dev_addr neighbor_addr; +}; + +/** + * WLP Service Set + * + * @mutex: used to protect entire WSS structure. + * + * @name: The WSS name is set to 65 bytes, 1 byte larger than the maximum + * allowed by the WLP spec. This is to have a null terminated string + * for display to the user. A maximum of 64 bytes will still be used + * when placing the WSS name field in association frames. + * + * @accept_enroll: Accepting enrollment: Set to one if registrar is + * accepting enrollment in WSS, or zero otherwise. + * + * Global and local information for each WSS in which we are enrolled. + * WLP 0.99 Section 7.2.1 and Section 7.2.2 + */ +struct wlp_wss { + struct mutex mutex; + struct kobject kobj; + /* Global properties. */ + struct wlp_uuid wssid; + u8 hash; + char name[WLP_WSS_NAME_SIZE]; + struct uwb_mac_addr bcast; + u8 secure_status:1; + u8 master_key[16]; + /* Local properties. */ + u8 tag; + struct uwb_mac_addr virtual_addr; + /* Extra */ + u8 accept_enroll:1; + enum wlp_wss_state state; +}; + +/** + * WLP main structure + * @mutex: protect changes to WLP structure. We only allow changes to the + * uuid, so currently this mutex only protects this field. + */ +struct wlp { + struct mutex mutex; + struct uwb_rc *rc; /* UWB radio controller */ + struct uwb_pal pal; + struct wlp_eda eda; + struct wlp_uuid uuid; + struct wlp_session *session; + struct wlp_wss wss; + struct mutex nbmutex; /* Neighbor mutex protects neighbors list */ + struct list_head neighbors; /* Elements are wlp_neighbor_e */ + struct uwb_notifs_handler uwb_notifs_handler; + struct wlp_device_info *dev_info; + void (*fill_device_info)(struct wlp *wlp, struct wlp_device_info *info); + int (*xmit_frame)(struct wlp *, struct sk_buff *, + struct uwb_dev_addr *); + void (*stop_queue)(struct wlp *); + void (*start_queue)(struct wlp *); +}; + +/* sysfs */ + + +struct wlp_wss_attribute { + struct attribute attr; + ssize_t (*show)(struct wlp_wss *wss, char *buf); + ssize_t (*store)(struct wlp_wss *wss, const char *buf, size_t count); +}; + +#define WSS_ATTR(_name, _mode, _show, _store) \ +static struct wlp_wss_attribute wss_attr_##_name = __ATTR(_name, _mode, \ + _show, _store) + +extern int wlp_setup(struct wlp *, struct uwb_rc *); +extern void wlp_remove(struct wlp *); +extern ssize_t wlp_neighborhood_show(struct wlp *, char *); +extern int wlp_wss_setup(struct net_device *, struct wlp_wss *); +extern void wlp_wss_remove(struct wlp_wss *); +extern ssize_t wlp_wss_activate_show(struct wlp_wss *, char *); +extern ssize_t wlp_wss_activate_store(struct wlp_wss *, const char *, size_t); +extern ssize_t wlp_eda_show(struct wlp *, char *); +extern ssize_t wlp_eda_store(struct wlp *, const char *, size_t); +extern ssize_t wlp_uuid_show(struct wlp *, char *); +extern ssize_t wlp_uuid_store(struct wlp *, const char *, size_t); +extern ssize_t wlp_dev_name_show(struct wlp *, char *); +extern ssize_t wlp_dev_name_store(struct wlp *, const char *, size_t); +extern ssize_t wlp_dev_manufacturer_show(struct wlp *, char *); +extern ssize_t wlp_dev_manufacturer_store(struct wlp *, const char *, size_t); +extern ssize_t wlp_dev_model_name_show(struct wlp *, char *); +extern ssize_t wlp_dev_model_name_store(struct wlp *, const char *, size_t); +extern ssize_t wlp_dev_model_nr_show(struct wlp *, char *); +extern ssize_t wlp_dev_model_nr_store(struct wlp *, const char *, size_t); +extern ssize_t wlp_dev_serial_show(struct wlp *, char *); +extern ssize_t wlp_dev_serial_store(struct wlp *, const char *, size_t); +extern ssize_t wlp_dev_prim_category_show(struct wlp *, char *); +extern ssize_t wlp_dev_prim_category_store(struct wlp *, const char *, + size_t); +extern ssize_t wlp_dev_prim_OUI_show(struct wlp *, char *); +extern ssize_t wlp_dev_prim_OUI_store(struct wlp *, const char *, size_t); +extern ssize_t wlp_dev_prim_OUI_sub_show(struct wlp *, char *); +extern ssize_t wlp_dev_prim_OUI_sub_store(struct wlp *, const char *, + size_t); +extern ssize_t wlp_dev_prim_subcat_show(struct wlp *, char *); +extern ssize_t wlp_dev_prim_subcat_store(struct wlp *, const char *, + size_t); +extern int wlp_receive_frame(struct device *, struct wlp *, struct sk_buff *, + struct uwb_dev_addr *); +extern int wlp_prepare_tx_frame(struct device *, struct wlp *, + struct sk_buff *, struct uwb_dev_addr *); + +/** + * Initialize WSS + */ +static inline +void wlp_wss_init(struct wlp_wss *wss) +{ + mutex_init(&wss->mutex); +} + +static inline +void wlp_init(struct wlp *wlp) +{ + INIT_LIST_HEAD(&wlp->neighbors); + mutex_init(&wlp->mutex); + mutex_init(&wlp->nbmutex); + wlp_wss_init(&wlp->wss); +} + + +#endif /* #ifndef __LINUX__WLP_H_ */ diff --git a/include/linux/wm97xx.h b/include/linux/wm97xx.h index 4d13732e9cf0..6f69968eab24 100644 --- a/include/linux/wm97xx.h +++ b/include/linux/wm97xx.h @@ -100,6 +100,7 @@ #define WM9713_ADCSEL_Y 0x0004 /* Y measurement */ #define WM9713_ADCSEL_PRES 0x0008 /* Pressure measurement */ #define WM9713_COO 0x0001 /* enable coordinate mode */ +#define WM9713_45W 0x1000 /* set for 5 wire panel */ #define WM9713_PDEN 0x0800 /* measure only when pen down */ #define WM9713_ADCSEL_MASK 0x00fe /* ADC selection mask */ #define WM9713_WAIT 0x0200 /* coordinate wait */ diff --git a/include/linux/writeback.h b/include/linux/writeback.h index f462439cc288..bd91987c065f 100644 --- a/include/linux/writeback.h +++ b/include/linux/writeback.h @@ -105,6 +105,8 @@ extern int vm_highmem_is_dirtyable; extern int block_dump; extern int laptop_mode; +extern unsigned long determine_dirtyable_memory(void); + extern int dirty_ratio_handler(struct ctl_table *table, int write, struct file *filp, void __user *buffer, size_t *lenp, loff_t *ppos); diff --git a/include/media/cx25840.h b/include/media/cx25840.h index cd599ad29fb2..db431d513f2f 100644 --- a/include/media/cx25840.h +++ b/include/media/cx25840.h @@ -32,12 +32,16 @@ enum cx25840_video_input { CX25840_COMPOSITE7, CX25840_COMPOSITE8, - /* S-Video inputs consist of one luma input (In1-In4) ORed with one + /* S-Video inputs consist of one luma input (In1-In8) ORed with one chroma input (In5-In8) */ CX25840_SVIDEO_LUMA1 = 0x10, CX25840_SVIDEO_LUMA2 = 0x20, CX25840_SVIDEO_LUMA3 = 0x30, CX25840_SVIDEO_LUMA4 = 0x40, + CX25840_SVIDEO_LUMA5 = 0x50, + CX25840_SVIDEO_LUMA6 = 0x60, + CX25840_SVIDEO_LUMA7 = 0x70, + CX25840_SVIDEO_LUMA8 = 0x80, CX25840_SVIDEO_CHROMA4 = 0x400, CX25840_SVIDEO_CHROMA5 = 0x500, CX25840_SVIDEO_CHROMA6 = 0x600, diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index a807d2f86ee8..3beba8b9177c 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -40,7 +40,6 @@ #define VFL_TYPE_VTX 3 /* Video standard functions */ -extern unsigned int v4l2_video_std_fps(struct v4l2_standard *vs); extern char *v4l2_norm_to_name(v4l2_std_id id); extern int v4l2_video_std_construct(struct v4l2_standard *vs, int id, char *name); @@ -119,74 +118,76 @@ struct video_device enum v4l2_priority p); /* VIDIOC_ENUM_FMT handlers */ - int (*vidioc_enum_fmt_cap) (struct file *file, void *fh, + int (*vidioc_enum_fmt_vid_cap) (struct file *file, void *fh, struct v4l2_fmtdesc *f); - int (*vidioc_enum_fmt_overlay) (struct file *file, void *fh, + int (*vidioc_enum_fmt_vid_overlay) (struct file *file, void *fh, struct v4l2_fmtdesc *f); - int (*vidioc_enum_fmt_vbi) (struct file *file, void *fh, + int (*vidioc_enum_fmt_vid_out) (struct file *file, void *fh, struct v4l2_fmtdesc *f); - int (*vidioc_enum_fmt_vbi_capture) (struct file *file, void *fh, - struct v4l2_fmtdesc *f); - int (*vidioc_enum_fmt_video_output)(struct file *file, void *fh, - struct v4l2_fmtdesc *f); - int (*vidioc_enum_fmt_output_overlay) (struct file *file, void *fh, - struct v4l2_fmtdesc *f); - int (*vidioc_enum_fmt_vbi_output) (struct file *file, void *fh, +#if 1 + /* deprecated, will be removed in 2.6.28 */ + int (*vidioc_enum_fmt_vbi_cap) (struct file *file, void *fh, struct v4l2_fmtdesc *f); +#endif int (*vidioc_enum_fmt_type_private)(struct file *file, void *fh, struct v4l2_fmtdesc *f); /* VIDIOC_G_FMT handlers */ - int (*vidioc_g_fmt_cap) (struct file *file, void *fh, + int (*vidioc_g_fmt_vid_cap) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_g_fmt_overlay) (struct file *file, void *fh, + int (*vidioc_g_fmt_vid_overlay)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_g_fmt_vbi) (struct file *file, void *fh, + int (*vidioc_g_fmt_vid_out) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_g_fmt_vbi_output) (struct file *file, void *fh, + int (*vidioc_g_fmt_vid_out_overlay)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_g_fmt_vbi_capture)(struct file *file, void *fh, + int (*vidioc_g_fmt_vbi_cap) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_g_fmt_video_output)(struct file *file, void *fh, + int (*vidioc_g_fmt_vbi_out) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_g_fmt_output_overlay) (struct file *file, void *fh, + int (*vidioc_g_fmt_sliced_vbi_cap)(struct file *file, void *fh, + struct v4l2_format *f); + int (*vidioc_g_fmt_sliced_vbi_out)(struct file *file, void *fh, struct v4l2_format *f); int (*vidioc_g_fmt_type_private)(struct file *file, void *fh, struct v4l2_format *f); /* VIDIOC_S_FMT handlers */ - int (*vidioc_s_fmt_cap) (struct file *file, void *fh, + int (*vidioc_s_fmt_vid_cap) (struct file *file, void *fh, struct v4l2_format *f); - - int (*vidioc_s_fmt_overlay) (struct file *file, void *fh, + int (*vidioc_s_fmt_vid_overlay)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_s_fmt_vbi) (struct file *file, void *fh, + int (*vidioc_s_fmt_vid_out) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_s_fmt_vbi_output) (struct file *file, void *fh, + int (*vidioc_s_fmt_vid_out_overlay)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_s_fmt_vbi_capture)(struct file *file, void *fh, + int (*vidioc_s_fmt_vbi_cap) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_s_fmt_video_output)(struct file *file, void *fh, + int (*vidioc_s_fmt_vbi_out) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_s_fmt_output_overlay) (struct file *file, void *fh, + int (*vidioc_s_fmt_sliced_vbi_cap)(struct file *file, void *fh, + struct v4l2_format *f); + int (*vidioc_s_fmt_sliced_vbi_out)(struct file *file, void *fh, struct v4l2_format *f); int (*vidioc_s_fmt_type_private)(struct file *file, void *fh, struct v4l2_format *f); /* VIDIOC_TRY_FMT handlers */ - int (*vidioc_try_fmt_cap) (struct file *file, void *fh, + int (*vidioc_try_fmt_vid_cap) (struct file *file, void *fh, + struct v4l2_format *f); + int (*vidioc_try_fmt_vid_overlay)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_try_fmt_overlay) (struct file *file, void *fh, + int (*vidioc_try_fmt_vid_out) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_try_fmt_vbi) (struct file *file, void *fh, + int (*vidioc_try_fmt_vid_out_overlay)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_try_fmt_vbi_output) (struct file *file, void *fh, + int (*vidioc_try_fmt_vbi_cap) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_try_fmt_vbi_capture)(struct file *file, void *fh, + int (*vidioc_try_fmt_vbi_out) (struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_try_fmt_video_output)(struct file *file, void *fh, + int (*vidioc_try_fmt_sliced_vbi_cap)(struct file *file, void *fh, struct v4l2_format *f); - int (*vidioc_try_fmt_output_overlay)(struct file *file, void *fh, + int (*vidioc_try_fmt_sliced_vbi_out)(struct file *file, void *fh, struct v4l2_format *f); int (*vidioc_try_fmt_type_private)(struct file *file, void *fh, struct v4l2_format *f); @@ -213,8 +214,9 @@ struct video_device int (*vidioc_streamoff)(struct file *file, void *fh, enum v4l2_buf_type i); /* Standard handling - G_STD and ENUMSTD are handled by videodev.c + ENUMSTD is handled by videodev.c */ + int (*vidioc_g_std) (struct file *file, void *fh, v4l2_std_id *norm); int (*vidioc_s_std) (struct file *file, void *fh, v4l2_std_id *norm); int (*vidioc_querystd) (struct file *file, void *fh, v4l2_std_id *a); @@ -225,7 +227,7 @@ struct video_device int (*vidioc_s_input) (struct file *file, void *fh, unsigned int i); /* Output handling */ - int (*vidioc_enumoutput) (struct file *file, void *fh, + int (*vidioc_enum_output) (struct file *file, void *fh, struct v4l2_output *a); int (*vidioc_g_output) (struct file *file, void *fh, unsigned int *i); int (*vidioc_s_output) (struct file *file, void *fh, unsigned int i); @@ -307,6 +309,8 @@ struct video_device /* Log status ioctl */ int (*vidioc_log_status) (struct file *file, void *fh); + int (*vidioc_s_hw_freq_seek) (struct file *file, void *fh, + struct v4l2_hw_freq_seek *a); /* Debugging ioctls */ #ifdef CONFIG_VIDEO_ADV_DEBUG diff --git a/include/mtd/inftl-user.h b/include/mtd/inftl-user.h index 9b1e2526b45e..e17eda302b2d 100644 --- a/include/mtd/inftl-user.h +++ b/include/mtd/inftl-user.h @@ -1,6 +1,4 @@ /* - * $Id: inftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $ - * * Parts of INFTL headers shared with userspace * */ diff --git a/include/mtd/jffs2-user.h b/include/mtd/jffs2-user.h index d508ef0ae091..001685d7fa88 100644 --- a/include/mtd/jffs2-user.h +++ b/include/mtd/jffs2-user.h @@ -1,6 +1,4 @@ /* - * $Id: jffs2-user.h,v 1.1 2004/05/05 11:57:54 dwmw2 Exp $ - * * JFFS2 definitions for use in user space only */ diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index 615072c4da04..c6c61cd5a254 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -1,6 +1,4 @@ /* - * $Id: mtd-abi.h,v 1.13 2005/11/07 11:14:56 gleixner Exp $ - * * Portions of MTD ABI definition which are shared by kernel and user space */ diff --git a/include/mtd/mtd-user.h b/include/mtd/mtd-user.h index 713f34d3e62e..170ceca3b2d0 100644 --- a/include/mtd/mtd-user.h +++ b/include/mtd/mtd-user.h @@ -1,6 +1,4 @@ /* - * $Id: mtd-user.h,v 1.2 2004/05/05 14:44:57 dwmw2 Exp $ - * * MTD ABI header for use by user space only. */ diff --git a/include/mtd/nftl-user.h b/include/mtd/nftl-user.h index b2bca18e7311..390d21c080aa 100644 --- a/include/mtd/nftl-user.h +++ b/include/mtd/nftl-user.h @@ -1,6 +1,4 @@ /* - * $Id: nftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $ - * * Parts of NFTL headers shared with userspace * */ diff --git a/include/net/addrconf.h b/include/net/addrconf.h index 0a2f0372df31..06b28142b3ab 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -94,12 +94,35 @@ extern void addrconf_join_solict(struct net_device *dev, extern void addrconf_leave_solict(struct inet6_dev *idev, struct in6_addr *addr); +static inline unsigned long addrconf_timeout_fixup(u32 timeout, + unsigned unit) +{ + if (timeout == 0xffffffff) + return ~0UL; + + /* + * Avoid arithmetic overflow. + * Assuming unit is constant and non-zero, this "if" statement + * will go away on 64bit archs. + */ + if (0xfffffffe > LONG_MAX / unit && timeout > LONG_MAX / unit) + return LONG_MAX / unit; + + return timeout; +} + +static inline int addrconf_finite_timeout(unsigned long timeout) +{ + return ~timeout; +} + /* * IPv6 Address Label subsystem (addrlabel.c) */ extern int ipv6_addr_label_init(void); extern void ipv6_addr_label_rtnl_register(void); -extern u32 ipv6_addr_label(const struct in6_addr *addr, +extern u32 ipv6_addr_label(struct net *net, + const struct in6_addr *addr, int type, int ifindex); /* diff --git a/include/net/genetlink.h b/include/net/genetlink.h index decdda546829..747c255d1df0 100644 --- a/include/net/genetlink.h +++ b/include/net/genetlink.h @@ -162,9 +162,9 @@ static inline int genlmsg_end(struct sk_buff *skb, void *hdr) * @skb: socket buffer the message is stored in * @hdr: generic netlink message header */ -static inline int genlmsg_cancel(struct sk_buff *skb, void *hdr) +static inline void genlmsg_cancel(struct sk_buff *skb, void *hdr) { - return nlmsg_cancel(skb, hdr - GENL_HDRLEN - NLMSG_HDRLEN); + nlmsg_cancel(skb, hdr - GENL_HDRLEN - NLMSG_HDRLEN); } /** diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h index 529816bfbc52..b31399e1fd83 100644 --- a/include/net/ieee80211.h +++ b/include/net/ieee80211.h @@ -1262,9 +1262,6 @@ extern int ieee80211_set_encryption(struct ieee80211_device *ieee); /* ieee80211_tx.c */ extern int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev); extern void ieee80211_txb_free(struct ieee80211_txb *); -extern int ieee80211_tx_frame(struct ieee80211_device *ieee, - struct ieee80211_hdr *frame, int hdr_len, - int total_len, int encrypt_mpdu); /* ieee80211_rx.c */ extern void ieee80211_rx_any(struct ieee80211_device *ieee, @@ -1312,14 +1309,6 @@ extern int ieee80211_wx_set_encodeext(struct ieee80211_device *ieee, extern int ieee80211_wx_get_encodeext(struct ieee80211_device *ieee, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); -extern int ieee80211_wx_set_auth(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, - char *extra); -extern int ieee80211_wx_get_auth(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, - char *extra); static inline void ieee80211_increment_scans(struct ieee80211_device *ieee) { diff --git a/include/net/if_inet6.h b/include/net/if_inet6.h index b2cfc4927257..db66c7927743 100644 --- a/include/net/if_inet6.h +++ b/include/net/if_inet6.h @@ -148,7 +148,6 @@ struct ifacaddr6 #define IFA_HOST IPV6_ADDR_LOOPBACK #define IFA_LINK IPV6_ADDR_LINKLOCAL #define IFA_SITE IPV6_ADDR_SITELOCAL -#define IFA_GLOBAL 0x0000U struct ipv6_devstat { struct proc_dir_entry *proc_dir_entry; diff --git a/include/net/inet_sock.h b/include/net/inet_sock.h index a42cd63d241a..9fabe5b38912 100644 --- a/include/net/inet_sock.h +++ b/include/net/inet_sock.h @@ -197,4 +197,14 @@ static inline int inet_iif(const struct sk_buff *skb) return skb->rtable->rt_iif; } +static inline struct request_sock *inet_reqsk_alloc(struct request_sock_ops *ops) +{ + struct request_sock *req = reqsk_alloc(ops); + + if (req != NULL) + inet_rsk(req)->opt = NULL; + + return req; +} + #endif /* _INET_SOCK_H */ diff --git a/include/net/inetpeer.h b/include/net/inetpeer.h index ad8404b56113..15e1f8fe4c1f 100644 --- a/include/net/inetpeer.h +++ b/include/net/inetpeer.h @@ -1,8 +1,6 @@ /* * INETPEER - A storage for permanent information about peers * - * Version: $Id: inetpeer.h,v 1.2 2002/01/12 07:54:56 davem Exp $ - * * Authors: Andrey V. Savochkin <saw@msu.ru> */ diff --git a/include/net/ip6_tunnel.h b/include/net/ip6_tunnel.h index 6512d85f11b3..83b4e008b16d 100644 --- a/include/net/ip6_tunnel.h +++ b/include/net/ip6_tunnel.h @@ -1,7 +1,3 @@ -/* - * $Id$ - */ - #ifndef _NET_IP6_TUNNEL_H #define _NET_IP6_TUNNEL_H @@ -19,7 +15,6 @@ struct ip6_tnl { struct ip6_tnl *next; /* next tunnel in list */ struct net_device *dev; /* virtual device associated with tunnel */ - struct net_device_stats stat; /* statistics for tunnel device */ int recursion; /* depth of hard_start_xmit recursion */ struct ip6_tnl_parm parms; /* tunnel configuration parameters */ struct flowi fl; /* flowi template for xmit */ diff --git a/include/net/ipconfig.h b/include/net/ipconfig.h index 3924d7d2cb11..c74cc1bd5a02 100644 --- a/include/net/ipconfig.h +++ b/include/net/ipconfig.h @@ -1,6 +1,4 @@ /* - * $Id: ipconfig.h,v 1.4 2001/04/30 04:51:46 davem Exp $ - * * Copyright (C) 1997 Martin Mares * * Automatic IP Layer Configuration diff --git a/include/net/ipip.h b/include/net/ipip.h index 633ed4def8e3..a85bda64b852 100644 --- a/include/net/ipip.h +++ b/include/net/ipip.h @@ -11,7 +11,6 @@ struct ip_tunnel { struct ip_tunnel *next; struct net_device *dev; - struct net_device_stats stat; int recursion; /* Depth of hard_start_xmit recursion */ int err_count; /* Number of arrived ICMP errors */ diff --git a/include/net/ipv6.h b/include/net/ipv6.h index e0a612bc9c4e..7f7db8d57934 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -4,8 +4,6 @@ * Authors: * Pedro Roque <roque@di.fc.ul.pt> * - * $Id: ipv6.h,v 1.1 2002/05/20 15:13:07 jgrimm Exp $ - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version diff --git a/include/net/mac80211.h b/include/net/mac80211.h index dae3f9ec1154..7ab4ff6159a2 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h @@ -98,6 +98,18 @@ struct ieee80211_ht_bss_info { }; /** + * enum ieee80211_max_queues - maximum number of queues + * + * @IEEE80211_MAX_QUEUES: Maximum number of regular device queues. + * @IEEE80211_MAX_AMPDU_QUEUES: Maximum number of queues usable + * for A-MPDU operation. + */ +enum ieee80211_max_queues { + IEEE80211_MAX_QUEUES = 16, + IEEE80211_MAX_AMPDU_QUEUES = 16, +}; + +/** * struct ieee80211_tx_queue_params - transmit queue configuration * * The information provided in this structure is required for QoS @@ -117,58 +129,18 @@ struct ieee80211_tx_queue_params { }; /** - * struct ieee80211_tx_queue_stats_data - transmit queue statistics + * struct ieee80211_tx_queue_stats - transmit queue statistics * * @len: number of packets in queue * @limit: queue length limit * @count: number of frames sent */ -struct ieee80211_tx_queue_stats_data { +struct ieee80211_tx_queue_stats { unsigned int len; unsigned int limit; unsigned int count; }; -/** - * enum ieee80211_tx_queue - transmit queue number - * - * These constants are used with some callbacks that take a - * queue number to set parameters for a queue. - * - * @IEEE80211_TX_QUEUE_DATA0: data queue 0 - * @IEEE80211_TX_QUEUE_DATA1: data queue 1 - * @IEEE80211_TX_QUEUE_DATA2: data queue 2 - * @IEEE80211_TX_QUEUE_DATA3: data queue 3 - * @IEEE80211_TX_QUEUE_DATA4: data queue 4 - * @IEEE80211_TX_QUEUE_SVP: ?? - * @NUM_TX_DATA_QUEUES: number of data queues - * @IEEE80211_TX_QUEUE_AFTER_BEACON: transmit queue for frames to be - * sent after a beacon - * @IEEE80211_TX_QUEUE_BEACON: transmit queue for beacon frames - * @NUM_TX_DATA_QUEUES_AMPDU: adding more queues for A-MPDU - */ -enum ieee80211_tx_queue { - IEEE80211_TX_QUEUE_DATA0, - IEEE80211_TX_QUEUE_DATA1, - IEEE80211_TX_QUEUE_DATA2, - IEEE80211_TX_QUEUE_DATA3, - IEEE80211_TX_QUEUE_DATA4, - IEEE80211_TX_QUEUE_SVP, - - NUM_TX_DATA_QUEUES, - -/* due to stupidity in the sub-ioctl userspace interface, the items in - * this struct need to have fixed values. As soon as it is removed, we can - * fix these entries. */ - IEEE80211_TX_QUEUE_AFTER_BEACON = 6, - IEEE80211_TX_QUEUE_BEACON = 7, - NUM_TX_DATA_QUEUES_AMPDU = 16 -}; - -struct ieee80211_tx_queue_stats { - struct ieee80211_tx_queue_stats_data data[NUM_TX_DATA_QUEUES_AMPDU]; -}; - struct ieee80211_low_level_stats { unsigned int dot11ACKFailureCount; unsigned int dot11RTSFailureCount; @@ -229,91 +201,128 @@ struct ieee80211_bss_conf { }; /** - * enum mac80211_tx_control_flags - flags to describe Tx configuration for - * the Tx frame - * - * These flags are used with the @flags member of &ieee80211_tx_control - * - * @IEEE80211_TXCTL_REQ_TX_STATUS: request TX status callback for this frame. - * @IEEE80211_TXCTL_DO_NOT_ENCRYPT: send this frame without encryption; - * e.g., for EAPOL frame - * @IEEE80211_TXCTL_USE_RTS_CTS: use RTS-CTS before sending frame - * @IEEE80211_TXCTL_USE_CTS_PROTECT: use CTS protection for the frame (e.g., - * for combined 802.11g / 802.11b networks) - * @IEEE80211_TXCTL_NO_ACK: tell the low level not to wait for an ack - * @IEEE80211_TXCTL_RATE_CTRL_PROBE - * @EEE80211_TXCTL_CLEAR_PS_FILT: clear powersave filter - * for destination station - * @IEEE80211_TXCTL_REQUEUE: - * @IEEE80211_TXCTL_FIRST_FRAGMENT: this is a first fragment of the frame - * @IEEE80211_TXCTL_LONG_RETRY_LIMIT: this frame should be send using the - * through set_retry_limit configured long - * retry value - * @IEEE80211_TXCTL_EAPOL_FRAME: internal to mac80211 - * @IEEE80211_TXCTL_SEND_AFTER_DTIM: send this frame after DTIM beacon - * @IEEE80211_TXCTL_AMPDU: this frame should be sent as part of an A-MPDU - * @IEEE80211_TXCTL_OFDM_HT: this frame can be sent in HT OFDM rates. number - * of streams when this flag is on can be extracted - * from antenna_sel_tx, so if 1 antenna is marked - * use SISO, 2 antennas marked use MIMO, n antennas - * marked use MIMO_n. - * @IEEE80211_TXCTL_GREEN_FIELD: use green field protection for this frame - * @IEEE80211_TXCTL_40_MHZ_WIDTH: send this frame using 40 Mhz channel width - * @IEEE80211_TXCTL_DUP_DATA: duplicate data frame on both 20 Mhz channels - * @IEEE80211_TXCTL_SHORT_GI: send this frame using short guard interval + * enum mac80211_tx_flags - flags to transmission information/status + * + * These flags are used with the @flags member of &ieee80211_tx_info + * + * @IEEE80211_TX_CTL_REQ_TX_STATUS: request TX status callback for this frame. + * @IEEE80211_TX_CTL_DO_NOT_ENCRYPT: send this frame without encryption; + * e.g., for EAPOL frame + * @IEEE80211_TX_CTL_USE_RTS_CTS: use RTS-CTS before sending frame + * @IEEE80211_TX_CTL_USE_CTS_PROTECT: use CTS protection for the frame (e.g., + * for combined 802.11g / 802.11b networks) + * @IEEE80211_TX_CTL_NO_ACK: tell the low level not to wait for an ack + * @IEEE80211_TX_CTL_RATE_CTRL_PROBE + * @IEEE80211_TX_CTL_CLEAR_PS_FILT: clear powersave filter for destination + * station + * @IEEE80211_TX_CTL_REQUEUE: + * @IEEE80211_TX_CTL_FIRST_FRAGMENT: this is a first fragment of the frame + * @IEEE80211_TX_CTL_LONG_RETRY_LIMIT: this frame should be send using the + * through set_retry_limit configured long retry value + * @IEEE80211_TX_CTL_EAPOL_FRAME: internal to mac80211 + * @IEEE80211_TX_CTL_SEND_AFTER_DTIM: send this frame after DTIM beacon + * @IEEE80211_TX_CTL_AMPDU: this frame should be sent as part of an A-MPDU + * @IEEE80211_TX_CTL_OFDM_HT: this frame can be sent in HT OFDM rates. number + * of streams when this flag is on can be extracted from antenna_sel_tx, + * so if 1 antenna is marked use SISO, 2 antennas marked use MIMO, n + * antennas marked use MIMO_n. + * @IEEE80211_TX_CTL_GREEN_FIELD: use green field protection for this frame + * @IEEE80211_TX_CTL_40_MHZ_WIDTH: send this frame using 40 Mhz channel width + * @IEEE80211_TX_CTL_DUP_DATA: duplicate data frame on both 20 Mhz channels + * @IEEE80211_TX_CTL_SHORT_GI: send this frame using short guard interval + * @IEEE80211_TX_STAT_TX_FILTERED: The frame was not transmitted + * because the destination STA was in powersave mode. + * @IEEE80211_TX_STAT_ACK: Frame was acknowledged + * @IEEE80211_TX_STAT_AMPDU: The frame was aggregated, so status + * is for the whole aggregation. */ enum mac80211_tx_control_flags { - IEEE80211_TXCTL_REQ_TX_STATUS = (1<<0), - IEEE80211_TXCTL_DO_NOT_ENCRYPT = (1<<1), - IEEE80211_TXCTL_USE_RTS_CTS = (1<<2), - IEEE80211_TXCTL_USE_CTS_PROTECT = (1<<3), - IEEE80211_TXCTL_NO_ACK = (1<<4), - IEEE80211_TXCTL_RATE_CTRL_PROBE = (1<<5), - IEEE80211_TXCTL_CLEAR_PS_FILT = (1<<6), - IEEE80211_TXCTL_REQUEUE = (1<<7), - IEEE80211_TXCTL_FIRST_FRAGMENT = (1<<8), - IEEE80211_TXCTL_SHORT_PREAMBLE = (1<<9), - IEEE80211_TXCTL_LONG_RETRY_LIMIT = (1<<10), - IEEE80211_TXCTL_EAPOL_FRAME = (1<<11), - IEEE80211_TXCTL_SEND_AFTER_DTIM = (1<<12), - IEEE80211_TXCTL_AMPDU = (1<<13), - IEEE80211_TXCTL_OFDM_HT = (1<<14), - IEEE80211_TXCTL_GREEN_FIELD = (1<<15), - IEEE80211_TXCTL_40_MHZ_WIDTH = (1<<16), - IEEE80211_TXCTL_DUP_DATA = (1<<17), - IEEE80211_TXCTL_SHORT_GI = (1<<18), + IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0), + IEEE80211_TX_CTL_DO_NOT_ENCRYPT = BIT(1), + IEEE80211_TX_CTL_USE_RTS_CTS = BIT(2), + IEEE80211_TX_CTL_USE_CTS_PROTECT = BIT(3), + IEEE80211_TX_CTL_NO_ACK = BIT(4), + IEEE80211_TX_CTL_RATE_CTRL_PROBE = BIT(5), + IEEE80211_TX_CTL_CLEAR_PS_FILT = BIT(6), + IEEE80211_TX_CTL_REQUEUE = BIT(7), + IEEE80211_TX_CTL_FIRST_FRAGMENT = BIT(8), + IEEE80211_TX_CTL_SHORT_PREAMBLE = BIT(9), + IEEE80211_TX_CTL_LONG_RETRY_LIMIT = BIT(10), + IEEE80211_TX_CTL_EAPOL_FRAME = BIT(11), + IEEE80211_TX_CTL_SEND_AFTER_DTIM = BIT(12), + IEEE80211_TX_CTL_AMPDU = BIT(13), + IEEE80211_TX_CTL_OFDM_HT = BIT(14), + IEEE80211_TX_CTL_GREEN_FIELD = BIT(15), + IEEE80211_TX_CTL_40_MHZ_WIDTH = BIT(16), + IEEE80211_TX_CTL_DUP_DATA = BIT(17), + IEEE80211_TX_CTL_SHORT_GI = BIT(18), + IEEE80211_TX_CTL_INJECTED = BIT(19), + IEEE80211_TX_STAT_TX_FILTERED = BIT(20), + IEEE80211_TX_STAT_ACK = BIT(21), + IEEE80211_TX_STAT_AMPDU = BIT(22), }; -/* Transmit control fields. This data structure is passed to low-level driver - * with each TX frame. The low-level driver is responsible for configuring - * the hardware to use given values (depending on what is supported). */ -struct ieee80211_tx_control { - struct ieee80211_vif *vif; - struct ieee80211_rate *tx_rate; - - /* Transmit rate for RTS/CTS frame */ - struct ieee80211_rate *rts_cts_rate; - - /* retry rate for the last retries */ - struct ieee80211_rate *alt_retry_rate; - - u32 flags; /* tx control flags defined above */ - u8 key_idx; /* keyidx from hw->set_key(), undefined if - * IEEE80211_TXCTL_DO_NOT_ENCRYPT is set */ - u8 retry_limit; /* 1 = only first attempt, 2 = one retry, .. - * This could be used when set_retry_limit - * is not implemented by the driver */ - u8 antenna_sel_tx; /* 0 = default/diversity, otherwise bit - * position represents antenna number used */ - u8 icv_len; /* length of the ICV/MIC field in octets */ - u8 iv_len; /* length of the IV field in octets */ - u8 queue; /* hardware queue to use for this frame; - * 0 = highest, hw->queues-1 = lowest */ - u16 aid; /* Station AID */ - int type; /* internal */ +#define IEEE80211_TX_INFO_DRIVER_DATA_SIZE \ + (sizeof(((struct sk_buff *)0)->cb) - 8) +#define IEEE80211_TX_INFO_DRIVER_DATA_PTRS \ + (IEEE80211_TX_INFO_DRIVER_DATA_SIZE / sizeof(void *)) + +/** + * struct ieee80211_tx_info - skb transmit information + * + * This structure is placed in skb->cb for three uses: + * (1) mac80211 TX control - mac80211 tells the driver what to do + * (2) driver internal use (if applicable) + * (3) TX status information - driver tells mac80211 what happened + * + * @flags: transmit info flags, defined above + * @retry_count: number of retries + * @excessive_retries: set to 1 if the frame was retried many times + * but not acknowledged + * @ampdu_ack_len: number of aggregated frames. + * relevant only if IEEE80211_TX_STATUS_AMPDU was set. + * @ampdu_ack_map: block ack bit map for the aggregation. + * relevant only if IEEE80211_TX_STATUS_AMPDU was set. + * @ack_signal: signal strength of the ACK frame + */ +struct ieee80211_tx_info { + /* common information */ + u32 flags; + u8 band; + s8 tx_rate_idx; + u8 antenna_sel_tx; + + /* 1 byte hole */ + + union { + struct { + struct ieee80211_vif *vif; + struct ieee80211_key_conf *hw_key; + unsigned long jiffies; + int ifindex; + u16 aid; + s8 rts_cts_rate_idx, alt_retry_rate_idx; + u8 retry_limit; + u8 icv_len; + u8 iv_len; + } control; + struct { + u64 ampdu_ack_map; + int ack_signal; + u8 retry_count; + bool excessive_retries; + u8 ampdu_ack_len; + } status; + void *driver_data[IEEE80211_TX_INFO_DRIVER_DATA_PTRS]; + }; }; +static inline struct ieee80211_tx_info *IEEE80211_SKB_CB(struct sk_buff *skb) +{ + return (struct ieee80211_tx_info *)skb->cb; +} + /** * enum mac80211_rx_flags - receive flags @@ -353,13 +362,16 @@ enum mac80211_rx_flags { * The low-level driver should provide this information (the subset * supported by hardware) to the 802.11 code with each received * frame. + * * @mactime: value in microseconds of the 64-bit Time Synchronization Function * (TSF) timer when the first data symbol (MPDU) arrived at the hardware. * @band: the active band when this frame was received * @freq: frequency the radio was tuned to when receiving this frame, in MHz - * @ssi: signal strength when receiving this frame - * @signal: used as 'qual' in statistics reporting - * @noise: PHY noise when receiving this frame + * @signal: signal strength when receiving this frame, either in dBm, in dB or + * unspecified depending on the hardware capabilities flags + * @IEEE80211_HW_SIGNAL_* + * @noise: noise when receiving this frame, in dBm. + * @qual: overall signal quality indication, in percent (0-100). * @antenna: antenna used * @rate_idx: index of data rate into band's supported rates * @flag: %RX_FLAG_* @@ -368,64 +380,15 @@ struct ieee80211_rx_status { u64 mactime; enum ieee80211_band band; int freq; - int ssi; int signal; int noise; + int qual; int antenna; int rate_idx; int flag; }; /** - * enum ieee80211_tx_status_flags - transmit status flags - * - * Status flags to indicate various transmit conditions. - * - * @IEEE80211_TX_STATUS_TX_FILTERED: The frame was not transmitted - * because the destination STA was in powersave mode. - * @IEEE80211_TX_STATUS_ACK: Frame was acknowledged - * @IEEE80211_TX_STATUS_AMPDU: The frame was aggregated, so status - * is for the whole aggregation. - */ -enum ieee80211_tx_status_flags { - IEEE80211_TX_STATUS_TX_FILTERED = 1<<0, - IEEE80211_TX_STATUS_ACK = 1<<1, - IEEE80211_TX_STATUS_AMPDU = 1<<2, -}; - -/** - * struct ieee80211_tx_status - transmit status - * - * As much information as possible should be provided for each transmitted - * frame with ieee80211_tx_status(). - * - * @control: a copy of the &struct ieee80211_tx_control passed to the driver - * in the tx() callback. - * @flags: transmit status flags, defined above - * @retry_count: number of retries - * @excessive_retries: set to 1 if the frame was retried many times - * but not acknowledged - * @ampdu_ack_len: number of aggregated frames. - * relevant only if IEEE80211_TX_STATUS_AMPDU was set. - * @ampdu_ack_map: block ack bit map for the aggregation. - * relevant only if IEEE80211_TX_STATUS_AMPDU was set. - * @ack_signal: signal strength of the ACK frame - * @queue_length: ?? REMOVE - * @queue_number: ?? REMOVE - */ -struct ieee80211_tx_status { - struct ieee80211_tx_control control; - u8 flags; - u8 retry_count; - bool excessive_retries; - u8 ampdu_ack_len; - u64 ampdu_ack_map; - int ack_signal; - int queue_length; - int queue_number; -}; - -/** * enum ieee80211_conf_flags - configuration flags * * Flags to define PHY configuration options @@ -580,7 +543,6 @@ struct ieee80211_if_conf { u8 *ssid; size_t ssid_len; struct sk_buff *beacon; - struct ieee80211_tx_control *beacon_control; }; /** @@ -610,11 +572,14 @@ enum ieee80211_key_alg { * @IEEE80211_KEY_FLAG_GENERATE_MMIC: This flag should be set by * the driver for a TKIP key if it requires Michael MIC * generation in software. + * @IEEE80211_KEY_FLAG_PAIRWISE: Set by mac80211, this flag indicates + * that the key is pairwise rather then a shared key. */ enum ieee80211_key_flags { IEEE80211_KEY_FLAG_WMM_STA = 1<<0, IEEE80211_KEY_FLAG_GENERATE_IV = 1<<1, IEEE80211_KEY_FLAG_GENERATE_MMIC= 1<<2, + IEEE80211_KEY_FLAG_PAIRWISE = 1<<3, }; /** @@ -721,6 +686,25 @@ enum ieee80211_tkip_key_type { * @IEEE80211_HW_2GHZ_SHORT_PREAMBLE_INCAPABLE: * Hardware is not capable of receiving frames with short preamble on * the 2.4 GHz band. + * + * @IEEE80211_HW_SIGNAL_UNSPEC: + * Hardware can provide signal values but we don't know its units. We + * expect values between 0 and @max_signal. + * If possible please provide dB or dBm instead. + * + * @IEEE80211_HW_SIGNAL_DB: + * Hardware gives signal values in dB, decibel difference from an + * arbitrary, fixed reference. We expect values between 0 and @max_signal. + * If possible please provide dBm instead. + * + * @IEEE80211_HW_SIGNAL_DBM: + * Hardware gives signal values in dBm, decibel difference from + * one milliwatt. This is the preferred method since it is standardized + * between different devices. @max_signal does not need to be set. + * + * @IEEE80211_HW_NOISE_DBM: + * Hardware can provide noise (radio interference) values in units dBm, + * decibel difference from one milliwatt. */ enum ieee80211_hw_flags { IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE = 1<<0, @@ -728,6 +712,10 @@ enum ieee80211_hw_flags { IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING = 1<<2, IEEE80211_HW_2GHZ_SHORT_SLOT_INCAPABLE = 1<<3, IEEE80211_HW_2GHZ_SHORT_PREAMBLE_INCAPABLE = 1<<4, + IEEE80211_HW_SIGNAL_UNSPEC = 1<<5, + IEEE80211_HW_SIGNAL_DB = 1<<6, + IEEE80211_HW_SIGNAL_DBM = 1<<7, + IEEE80211_HW_NOISE_DBM = 1<<8, }; /** @@ -758,15 +746,18 @@ enum ieee80211_hw_flags { * * @channel_change_time: time (in microseconds) it takes to change channels. * - * @max_rssi: Maximum value for ssi in RX information, use - * negative numbers for dBm and 0 to indicate no support. - * - * @max_signal: like @max_rssi, but for the signal value. - * - * @max_noise: like @max_rssi, but for the noise value. + * @max_signal: Maximum value for signal (rssi) in RX information, used + * only when @IEEE80211_HW_SIGNAL_UNSPEC or @IEEE80211_HW_SIGNAL_DB * * @queues: number of available hardware transmit queues for - * data packets. WMM/QoS requires at least four. + * data packets. WMM/QoS requires at least four, these + * queues need to have configurable access parameters. + * + * @ampdu_queues: number of available hardware transmit queues + * for A-MPDU packets, these have no access parameters + * because they're used only for A-MPDU frames. Note that + * mac80211 will not currently use any of the regular queues + * for aggregation. * * @rate_control_algorithm: rate control algorithm for this hardware. * If unset (NULL), the default algorithm will be used. Must be @@ -785,10 +776,8 @@ struct ieee80211_hw { unsigned int extra_tx_headroom; int channel_change_time; int vif_data_size; - u8 queues; - s8 max_rssi; + u16 queues, ampdu_queues; s8 max_signal; - s8 max_noise; }; /** @@ -813,6 +802,51 @@ static inline void SET_IEEE80211_PERM_ADDR(struct ieee80211_hw *hw, u8 *addr) memcpy(hw->wiphy->perm_addr, addr, ETH_ALEN); } +static inline int ieee80211_num_regular_queues(struct ieee80211_hw *hw) +{ +#ifdef CONFIG_MAC80211_QOS + return hw->queues; +#else + return 1; +#endif +} + +static inline int ieee80211_num_queues(struct ieee80211_hw *hw) +{ +#ifdef CONFIG_MAC80211_QOS + return hw->queues + hw->ampdu_queues; +#else + return 1; +#endif +} + +static inline struct ieee80211_rate * +ieee80211_get_tx_rate(const struct ieee80211_hw *hw, + const struct ieee80211_tx_info *c) +{ + if (WARN_ON(c->tx_rate_idx < 0)) + return NULL; + return &hw->wiphy->bands[c->band]->bitrates[c->tx_rate_idx]; +} + +static inline struct ieee80211_rate * +ieee80211_get_rts_cts_rate(const struct ieee80211_hw *hw, + const struct ieee80211_tx_info *c) +{ + if (c->control.rts_cts_rate_idx < 0) + return NULL; + return &hw->wiphy->bands[c->band]->bitrates[c->control.rts_cts_rate_idx]; +} + +static inline struct ieee80211_rate * +ieee80211_get_alt_retry_rate(const struct ieee80211_hw *hw, + const struct ieee80211_tx_info *c) +{ + if (c->control.alt_retry_rate_idx < 0) + return NULL; + return &hw->wiphy->bands[c->band]->bitrates[c->control.alt_retry_rate_idx]; +} + /** * DOC: Hardware crypto acceleration * @@ -970,8 +1004,10 @@ enum ieee80211_ampdu_mlme_action { * @tx: Handler that 802.11 module calls for each transmitted frame. * skb contains the buffer starting from the IEEE 802.11 header. * The low-level driver should send the frame out based on - * configuration in the TX control data. Must be implemented and - * atomic. + * configuration in the TX control data. This handler should, + * preferably, never fail and stop queues appropriately, more + * importantly, however, it must never fail for A-MPDU-queues. + * Must be implemented and atomic. * * @start: Called before the first netdevice attached to the hardware * is enabled. This should turn on the hardware and must turn on @@ -1063,15 +1099,13 @@ enum ieee80211_ampdu_mlme_action { * of assocaited station or AP. * * @conf_tx: Configure TX queue parameters (EDCF (aifs, cw_min, cw_max), - * bursting) for a hardware TX queue. The @queue parameter uses the - * %IEEE80211_TX_QUEUE_* constants. Must be atomic. + * bursting) for a hardware TX queue. Must be atomic. * * @get_tx_stats: Get statistics of the current TX queue status. This is used * to get number of currently queued packets (queue length), maximum queue * size (limit), and total number of packets sent using each TX queue - * (count). This information is used for WMM to find out which TX - * queues have room for more packets and by hostapd to provide - * statistics about the current queueing state to external programs. + * (count). The 'stats' pointer points to an array that has hw->queues + + * hw->ampdu_queues items. * * @get_tsf: Get the current TSF timer value from firmware/hardware. Currently, * this is only used for IBSS mode debugging and, as such, is not a @@ -1107,8 +1141,7 @@ enum ieee80211_ampdu_mlme_action { * that TX/RX_STOP can pass NULL for this parameter. */ struct ieee80211_ops { - int (*tx)(struct ieee80211_hw *hw, struct sk_buff *skb, - struct ieee80211_tx_control *control); + int (*tx)(struct ieee80211_hw *hw, struct sk_buff *skb); int (*start)(struct ieee80211_hw *hw); void (*stop)(struct ieee80211_hw *hw); int (*add_interface)(struct ieee80211_hw *hw, @@ -1145,15 +1178,14 @@ struct ieee80211_ops { u32 short_retry, u32 long_retr); void (*sta_notify)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, enum sta_notify_cmd, const u8 *addr); - int (*conf_tx)(struct ieee80211_hw *hw, int queue, + int (*conf_tx)(struct ieee80211_hw *hw, u16 queue, const struct ieee80211_tx_queue_params *params); int (*get_tx_stats)(struct ieee80211_hw *hw, struct ieee80211_tx_queue_stats *stats); u64 (*get_tsf)(struct ieee80211_hw *hw); void (*reset_tsf)(struct ieee80211_hw *hw); int (*beacon_update)(struct ieee80211_hw *hw, - struct sk_buff *skb, - struct ieee80211_tx_control *control); + struct sk_buff *skb); int (*tx_last_beacon)(struct ieee80211_hw *hw); int (*ampdu_action)(struct ieee80211_hw *hw, enum ieee80211_ampdu_mlme_action action, @@ -1349,13 +1381,9 @@ void ieee80211_rx_irqsafe(struct ieee80211_hw *hw, * * @hw: the hardware the frame was transmitted by * @skb: the frame that was transmitted, owned by mac80211 after this call - * @status: status information for this frame; the status pointer need not - * be valid after this function returns and is not freed by mac80211, - * it is recommended that it points to a stack area */ void ieee80211_tx_status(struct ieee80211_hw *hw, - struct sk_buff *skb, - struct ieee80211_tx_status *status); + struct sk_buff *skb); /** * ieee80211_tx_status_irqsafe - irq-safe transmit status callback @@ -1368,13 +1396,9 @@ void ieee80211_tx_status(struct ieee80211_hw *hw, * * @hw: the hardware the frame was transmitted by * @skb: the frame that was transmitted, owned by mac80211 after this call - * @status: status information for this frame; the status pointer need not - * be valid after this function returns and is not freed by mac80211, - * it is recommended that it points to a stack area */ void ieee80211_tx_status_irqsafe(struct ieee80211_hw *hw, - struct sk_buff *skb, - struct ieee80211_tx_status *status); + struct sk_buff *skb); /** * ieee80211_beacon_get - beacon generation function @@ -1390,8 +1414,7 @@ void ieee80211_tx_status_irqsafe(struct ieee80211_hw *hw, * is responsible of freeing it. */ struct sk_buff *ieee80211_beacon_get(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - struct ieee80211_tx_control *control); + struct ieee80211_vif *vif); /** * ieee80211_rts_get - RTS frame generation function @@ -1399,7 +1422,7 @@ struct sk_buff *ieee80211_beacon_get(struct ieee80211_hw *hw, * @vif: &struct ieee80211_vif pointer from &struct ieee80211_if_init_conf. * @frame: pointer to the frame that is going to be protected by the RTS. * @frame_len: the frame length (in octets). - * @frame_txctl: &struct ieee80211_tx_control of the frame. + * @frame_txctl: &struct ieee80211_tx_info of the frame. * @rts: The buffer where to store the RTS frame. * * If the RTS frames are generated by the host system (i.e., not in @@ -1409,7 +1432,7 @@ struct sk_buff *ieee80211_beacon_get(struct ieee80211_hw *hw, */ void ieee80211_rts_get(struct ieee80211_hw *hw, struct ieee80211_vif *vif, const void *frame, size_t frame_len, - const struct ieee80211_tx_control *frame_txctl, + const struct ieee80211_tx_info *frame_txctl, struct ieee80211_rts *rts); /** @@ -1417,7 +1440,7 @@ void ieee80211_rts_get(struct ieee80211_hw *hw, struct ieee80211_vif *vif, * @hw: pointer obtained from ieee80211_alloc_hw(). * @vif: &struct ieee80211_vif pointer from &struct ieee80211_if_init_conf. * @frame_len: the length of the frame that is going to be protected by the RTS. - * @frame_txctl: &struct ieee80211_tx_control of the frame. + * @frame_txctl: &struct ieee80211_tx_info of the frame. * * If the RTS is generated in firmware, but the host system must provide * the duration field, the low-level driver uses this function to receive @@ -1425,7 +1448,7 @@ void ieee80211_rts_get(struct ieee80211_hw *hw, struct ieee80211_vif *vif, */ __le16 ieee80211_rts_duration(struct ieee80211_hw *hw, struct ieee80211_vif *vif, size_t frame_len, - const struct ieee80211_tx_control *frame_txctl); + const struct ieee80211_tx_info *frame_txctl); /** * ieee80211_ctstoself_get - CTS-to-self frame generation function @@ -1433,7 +1456,7 @@ __le16 ieee80211_rts_duration(struct ieee80211_hw *hw, * @vif: &struct ieee80211_vif pointer from &struct ieee80211_if_init_conf. * @frame: pointer to the frame that is going to be protected by the CTS-to-self. * @frame_len: the frame length (in octets). - * @frame_txctl: &struct ieee80211_tx_control of the frame. + * @frame_txctl: &struct ieee80211_tx_info of the frame. * @cts: The buffer where to store the CTS-to-self frame. * * If the CTS-to-self frames are generated by the host system (i.e., not in @@ -1444,7 +1467,7 @@ __le16 ieee80211_rts_duration(struct ieee80211_hw *hw, void ieee80211_ctstoself_get(struct ieee80211_hw *hw, struct ieee80211_vif *vif, const void *frame, size_t frame_len, - const struct ieee80211_tx_control *frame_txctl, + const struct ieee80211_tx_info *frame_txctl, struct ieee80211_cts *cts); /** @@ -1452,7 +1475,7 @@ void ieee80211_ctstoself_get(struct ieee80211_hw *hw, * @hw: pointer obtained from ieee80211_alloc_hw(). * @vif: &struct ieee80211_vif pointer from &struct ieee80211_if_init_conf. * @frame_len: the length of the frame that is going to be protected by the CTS-to-self. - * @frame_txctl: &struct ieee80211_tx_control of the frame. + * @frame_txctl: &struct ieee80211_tx_info of the frame. * * If the CTS-to-self is generated in firmware, but the host system must provide * the duration field, the low-level driver uses this function to receive @@ -1461,7 +1484,7 @@ void ieee80211_ctstoself_get(struct ieee80211_hw *hw, __le16 ieee80211_ctstoself_duration(struct ieee80211_hw *hw, struct ieee80211_vif *vif, size_t frame_len, - const struct ieee80211_tx_control *frame_txctl); + const struct ieee80211_tx_info *frame_txctl); /** * ieee80211_generic_frame_duration - Calculate the duration field for a frame @@ -1500,8 +1523,7 @@ __le16 ieee80211_generic_frame_duration(struct ieee80211_hw *hw, * use common code for all beacons. */ struct sk_buff * -ieee80211_get_buffered_bc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - struct ieee80211_tx_control *control); +ieee80211_get_buffered_bc(struct ieee80211_hw *hw, struct ieee80211_vif *vif); /** * ieee80211_get_hdrlen_from_skb - get header length from data @@ -1513,7 +1535,7 @@ ieee80211_get_buffered_bc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, * * @skb: the frame */ -int ieee80211_get_hdrlen_from_skb(const struct sk_buff *skb); +unsigned int ieee80211_get_hdrlen_from_skb(const struct sk_buff *skb); /** * ieee80211_get_hdrlen - get header length from frame control @@ -1526,6 +1548,12 @@ int ieee80211_get_hdrlen_from_skb(const struct sk_buff *skb); int ieee80211_get_hdrlen(u16 fc); /** + * ieee80211_hdrlen - get header length in bytes from frame control + * @fc: frame control field in little-endian format + */ +unsigned int ieee80211_hdrlen(__le16 fc); + +/** * ieee80211_get_tkip_key - get a TKIP rc4 for skb * * This function computes a TKIP rc4 key for an skb. It computes @@ -1559,14 +1587,6 @@ void ieee80211_wake_queue(struct ieee80211_hw *hw, int queue); void ieee80211_stop_queue(struct ieee80211_hw *hw, int queue); /** - * ieee80211_start_queues - start all queues - * @hw: pointer to as obtained from ieee80211_alloc_hw(). - * - * Drivers should use this function instead of netif_start_queue. - */ -void ieee80211_start_queues(struct ieee80211_hw *hw); - -/** * ieee80211_stop_queues - stop all queues * @hw: pointer as obtained from ieee80211_alloc_hw(). * diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h index aa540e6be502..8df751b3be55 100644 --- a/include/net/net_namespace.h +++ b/include/net/net_namespace.h @@ -201,8 +201,11 @@ extern void unregister_pernet_gen_device(int id, struct pernet_operations *); struct ctl_path; struct ctl_table; struct ctl_table_header; + extern struct ctl_table_header *register_net_sysctl_table(struct net *net, const struct ctl_path *path, struct ctl_table *table); +extern struct ctl_table_header *register_net_sysctl_rotable( + const struct ctl_path *path, struct ctl_table *table); extern void unregister_net_sysctl_table(struct ctl_table_header *header); #endif /* __NET_NET_NAMESPACE_H */ diff --git a/include/net/netfilter/ipv4/nf_conntrack_ipv4.h b/include/net/netfilter/ipv4/nf_conntrack_ipv4.h index 9bf059817aec..7573d52a4346 100644 --- a/include/net/netfilter/ipv4/nf_conntrack_ipv4.h +++ b/include/net/netfilter/ipv4/nf_conntrack_ipv4.h @@ -9,8 +9,6 @@ #ifndef _NF_CONNTRACK_IPV4_H #define _NF_CONNTRACK_IPV4_H -/* Returns new sk_buff, or NULL */ -struct sk_buff *nf_ct_ipv4_ct_gather_frags(struct sk_buff *skb); extern struct nf_conntrack_l3proto nf_conntrack_l3proto_ipv4; diff --git a/include/net/netfilter/nf_conntrack.h b/include/net/netfilter/nf_conntrack.h index 2dbd6c015b94..d77dec768dc2 100644 --- a/include/net/netfilter/nf_conntrack.h +++ b/include/net/netfilter/nf_conntrack.h @@ -223,6 +223,25 @@ static inline void nf_ct_refresh(struct nf_conn *ct, __nf_ct_refresh_acct(ct, 0, skb, extra_jiffies, 0); } +extern void __nf_ct_kill_acct(struct nf_conn *ct, + enum ip_conntrack_info ctinfo, + const struct sk_buff *skb, + int do_acct); + +/* kill conntrack and do accounting */ +static inline void nf_ct_kill_acct(struct nf_conn *ct, + enum ip_conntrack_info ctinfo, + const struct sk_buff *skb) +{ + __nf_ct_kill_acct(ct, ctinfo, skb, 1); +} + +/* kill conntrack without accounting */ +static inline void nf_ct_kill(struct nf_conn *ct) +{ + __nf_ct_kill_acct(ct, 0, NULL, 0); +} + /* These are for NAT. Icky. */ /* Update TCP window tracking data when NAT mangles the packet */ extern void nf_conntrack_tcp_update(const struct sk_buff *skb, diff --git a/include/net/netlink.h b/include/net/netlink.h index 112dcdf7e34e..dfc3701dfcc3 100644 --- a/include/net/netlink.h +++ b/include/net/netlink.h @@ -556,14 +556,12 @@ static inline void *nlmsg_get_pos(struct sk_buff *skb) * @skb: socket buffer the message is stored in * @mark: mark to trim to * - * Trims the message to the provided mark. Returns -1. + * Trims the message to the provided mark. */ -static inline int nlmsg_trim(struct sk_buff *skb, const void *mark) +static inline void nlmsg_trim(struct sk_buff *skb, const void *mark) { if (mark) skb_trim(skb, (unsigned char *) mark - skb->data); - - return -1; } /** @@ -572,11 +570,11 @@ static inline int nlmsg_trim(struct sk_buff *skb, const void *mark) * @nlh: netlink message header * * Removes the complete netlink message including all - * attributes from the socket buffer again. Returns -1. + * attributes from the socket buffer again. */ -static inline int nlmsg_cancel(struct sk_buff *skb, struct nlmsghdr *nlh) +static inline void nlmsg_cancel(struct sk_buff *skb, struct nlmsghdr *nlh) { - return nlmsg_trim(skb, nlh); + nlmsg_trim(skb, nlh); } /** @@ -775,7 +773,7 @@ static inline int __nla_parse_nested_compat(struct nlattr *tb[], int maxtype, int nested_len = nla_len(nla) - NLA_ALIGN(len); if (nested_len < 0) - return -1; + return -EINVAL; if (nested_len >= nla_attr_size(0)) return nla_parse(tb, maxtype, nla_data(nla) + NLA_ALIGN(len), nested_len, policy); @@ -1080,11 +1078,11 @@ static inline int nla_nest_compat_end(struct sk_buff *skb, struct nlattr *start) * @start: container attribute * * Removes the container attribute and including all nested - * attributes. Returns -1. + * attributes. Returns -EMSGSIZE */ -static inline int nla_nest_cancel(struct sk_buff *skb, struct nlattr *start) +static inline void nla_nest_cancel(struct sk_buff *skb, struct nlattr *start) { - return nlmsg_trim(skb, start); + nlmsg_trim(skb, start); } /** diff --git a/include/net/netns/ipv4.h b/include/net/netns/ipv4.h index 34ee348a2cf2..6ef90b5fafb3 100644 --- a/include/net/netns/ipv4.h +++ b/include/net/netns/ipv4.h @@ -36,6 +36,7 @@ struct netns_ipv4 { struct xt_table *iptable_mangle; struct xt_table *iptable_raw; struct xt_table *arptable_filter; + struct xt_table *iptable_security; #endif int sysctl_icmp_echo_ignore_all; diff --git a/include/net/netns/ipv6.h b/include/net/netns/ipv6.h index ac053be6c256..5bacd838e88b 100644 --- a/include/net/netns/ipv6.h +++ b/include/net/netns/ipv6.h @@ -35,6 +35,7 @@ struct netns_ipv6 { struct xt_table *ip6table_filter; struct xt_table *ip6table_mangle; struct xt_table *ip6table_raw; + struct xt_table *ip6table_security; #endif struct rt6_info *ip6_null_entry; struct rt6_statistics *rt6_stats; diff --git a/include/net/request_sock.h b/include/net/request_sock.h index b220b5f624de..0c96e7bed5db 100644 --- a/include/net/request_sock.h +++ b/include/net/request_sock.h @@ -115,8 +115,8 @@ struct request_sock_queue { struct request_sock *rskq_accept_head; struct request_sock *rskq_accept_tail; rwlock_t syn_wait_lock; - u16 rskq_defer_accept; - /* 2 bytes hole, try to pack */ + u8 rskq_defer_accept; + /* 3 bytes hole, try to pack */ struct listen_sock *listen_opt; }; diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h index 90b1e8d23b16..5672d489e924 100644 --- a/include/net/sctp/sctp.h +++ b/include/net/sctp/sctp.h @@ -179,6 +179,8 @@ int sctp_eps_proc_init(void); void sctp_eps_proc_exit(void); int sctp_assocs_proc_init(void); void sctp_assocs_proc_exit(void); +int sctp_remaddr_proc_init(void); +void sctp_remaddr_proc_exit(void); /* diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index 0ce0443c5b79..fbc27ac8a09e 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -300,6 +300,7 @@ struct sctp_sock { /* The default SACK delay timeout for new associations. */ __u32 sackdelay; + __u32 sackfreq; /* Flags controlling Heartbeat, SACK delay, and Path MTU Discovery. */ __u32 param_flags; @@ -548,7 +549,8 @@ struct sctp_af { struct dst_entry *(*get_dst) (struct sctp_association *asoc, union sctp_addr *daddr, union sctp_addr *saddr); - void (*get_saddr) (struct sctp_association *asoc, + void (*get_saddr) (struct sctp_sock *sk, + struct sctp_association *asoc, struct dst_entry *dst, union sctp_addr *daddr, union sctp_addr *saddr); @@ -587,6 +589,7 @@ struct sctp_af { int (*is_ce) (const struct sk_buff *sk); void (*seq_dump_addr)(struct seq_file *seq, union sctp_addr *addr); + void (*ecn_capable)(struct sock *sk); __u16 net_header_len; int sockaddr_len; sa_family_t sa_family; @@ -901,7 +904,10 @@ struct sctp_transport { * calculation completes (i.e. the DATA chunk * is SACK'd) clear this flag. */ - int rto_pending; + __u8 rto_pending; + + /* Flag to track the current fast recovery state */ + __u8 fast_recovery; /* * These are the congestion stats. @@ -920,6 +926,9 @@ struct sctp_transport { /* Data that has been sent, but not acknowledged. */ __u32 flight_size; + /* TSN marking the fast recovery exit point */ + __u32 fast_recovery_exit; + /* Destination */ struct dst_entry *dst; /* Source address. */ @@ -938,6 +947,7 @@ struct sctp_transport { /* SACK delay timeout */ unsigned long sackdelay; + __u32 sackfreq; /* When was the last time (in jiffies) that we heard from this * transport? We use this to pick new active and retran paths. @@ -1044,7 +1054,7 @@ void sctp_transport_route(struct sctp_transport *, union sctp_addr *, struct sctp_sock *); void sctp_transport_pmtu(struct sctp_transport *); void sctp_transport_free(struct sctp_transport *); -void sctp_transport_reset_timers(struct sctp_transport *); +void sctp_transport_reset_timers(struct sctp_transport *, int); void sctp_transport_hold(struct sctp_transport *); void sctp_transport_put(struct sctp_transport *); void sctp_transport_update_rto(struct sctp_transport *, __u32); @@ -1134,6 +1144,9 @@ struct sctp_outq { /* How many unackd bytes do we have in-flight? */ __u32 outstanding_bytes; + /* Are we doing fast-rtx on this queue */ + char fast_rtx; + /* Corked? */ char cork; @@ -1542,6 +1555,7 @@ struct sctp_association { * : SACK's are not delayed (see Section 6). */ __u8 sack_needed; /* Do we need to sack the peer? */ + __u32 sack_cnt; /* These are capabilities which our peer advertised. */ __u8 ecn_capable; /* Can peer do ECN? */ @@ -1651,6 +1665,7 @@ struct sctp_association { /* SACK delay timeout */ unsigned long sackdelay; + __u32 sackfreq; unsigned long timeouts[SCTP_NUM_TIMEOUT_TYPES]; diff --git a/include/net/sctp/user.h b/include/net/sctp/user.h index 9619b9d35c9e..f205b10f0ab9 100644 --- a/include/net/sctp/user.h +++ b/include/net/sctp/user.h @@ -93,8 +93,9 @@ enum sctp_optname { #define SCTP_STATUS SCTP_STATUS SCTP_GET_PEER_ADDR_INFO, #define SCTP_GET_PEER_ADDR_INFO SCTP_GET_PEER_ADDR_INFO - SCTP_DELAYED_ACK_TIME, -#define SCTP_DELAYED_ACK_TIME SCTP_DELAYED_ACK_TIME + SCTP_DELAYED_ACK, +#define SCTP_DELAYED_ACK_TIME SCTP_DELAYED_ACK +#define SCTP_DELAYED_ACK SCTP_DELAYED_ACK SCTP_CONTEXT, /* Receive Context */ #define SCTP_CONTEXT SCTP_CONTEXT SCTP_FRAGMENT_INTERLEAVE, @@ -136,12 +137,14 @@ enum sctp_optname { #define SCTP_GET_LOCAL_ADDRS_NUM_OLD SCTP_GET_LOCAL_ADDRS_NUM_OLD SCTP_GET_LOCAL_ADDRS_OLD, /* Get all local addresss. */ #define SCTP_GET_LOCAL_ADDRS_OLD SCTP_GET_LOCAL_ADDRS_OLD - SCTP_SOCKOPT_CONNECTX, /* CONNECTX requests. */ -#define SCTP_SOCKOPT_CONNECTX SCTP_SOCKOPT_CONNECTX + SCTP_SOCKOPT_CONNECTX_OLD, /* CONNECTX old requests. */ +#define SCTP_SOCKOPT_CONNECTX_OLD SCTP_SOCKOPT_CONNECTX_OLD SCTP_GET_PEER_ADDRS, /* Get all peer addresss. */ #define SCTP_GET_PEER_ADDRS SCTP_GET_PEER_ADDRS SCTP_GET_LOCAL_ADDRS, /* Get all local addresss. */ #define SCTP_GET_LOCAL_ADDRS SCTP_GET_LOCAL_ADDRS + SCTP_SOCKOPT_CONNECTX, /* CONNECTX requests. */ +#define SCTP_SOCKOPT_CONNECTX SCTP_SOCKOPT_CONNECTX }; /* @@ -618,13 +621,26 @@ struct sctp_authkeyid { }; -/* 7.1.23. Delayed Ack Timer (SCTP_DELAYED_ACK_TIME) +/* + * 7.1.23. Get or set delayed ack timer (SCTP_DELAYED_SACK) * - * This options will get or set the delayed ack timer. The time is set - * in milliseconds. If the assoc_id is 0, then this sets or gets the - * endpoints default delayed ack timer value. If the assoc_id field is - * non-zero, then the set or get effects the specified association. + * This option will effect the way delayed acks are performed. This + * option allows you to get or set the delayed ack time, in + * milliseconds. It also allows changing the delayed ack frequency. + * Changing the frequency to 1 disables the delayed sack algorithm. If + * the assoc_id is 0, then this sets or gets the endpoints default + * values. If the assoc_id field is non-zero, then the set or get + * effects the specified association for the one to many model (the + * assoc_id field is ignored by the one to one model). Note that if + * sack_delay or sack_freq are 0 when setting this option, then the + * current values will remain unchanged. */ +struct sctp_sack_info { + sctp_assoc_t sack_assoc_id; + uint32_t sack_delay; + uint32_t sack_freq; +}; + struct sctp_assoc_value { sctp_assoc_t assoc_id; uint32_t assoc_value; diff --git a/include/net/snmp.h b/include/net/snmp.h index ce2f48507510..57c93628695f 100644 --- a/include/net/snmp.h +++ b/include/net/snmp.h @@ -14,8 +14,6 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * - * $Id: snmp.h,v 1.19 2001/06/14 13:40:46 davem Exp $ - * */ #ifndef _SNMP_H diff --git a/include/net/sock.h b/include/net/sock.h index dc42b44c2aa1..0a80961a83c0 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -524,7 +524,7 @@ struct proto { int (*ioctl)(struct sock *sk, int cmd, unsigned long arg); int (*init)(struct sock *sk); - int (*destroy)(struct sock *sk); + void (*destroy)(struct sock *sk); void (*shutdown)(struct sock *sk, int how); int (*setsockopt)(struct sock *sk, int level, int optname, char __user *optval, diff --git a/include/net/tcp.h b/include/net/tcp.h index 633147cb6bbc..6b827cc6c52f 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -139,7 +139,6 @@ extern void tcp_time_wait(struct sock *sk, int state, int timeo); #define MAX_TCP_KEEPINTVL 32767 #define MAX_TCP_KEEPCNT 127 #define MAX_TCP_SYNCNT 127 -#define MAX_TCP_ACCEPT_DEFERRED 65535 #define TCP_SYNQ_INTERVAL (HZ/5) /* Period of SYNACK timer */ @@ -399,6 +398,8 @@ extern void tcp_parse_options(struct sk_buff *skb, struct tcp_options_received *opt_rx, int estab); +extern u8 *tcp_parse_md5sig_option(struct tcphdr *th); + /* * TCP v4 functions exported for the inet6 API */ @@ -433,7 +434,6 @@ extern struct sk_buff * tcp_make_synack(struct sock *sk, extern int tcp_disconnect(struct sock *sk, int flags); -extern void tcp_unhash(struct sock *sk); /* From syncookies.c */ extern __u32 syncookie_secret[2][16-4+SHA_DIGEST_WORDS]; @@ -1115,13 +1115,19 @@ struct tcp_md5sig_pool { #define TCP_MD5SIG_MAXKEYS (~(u32)0) /* really?! */ /* - functions */ +extern int tcp_calc_md5_hash(char *md5_hash, + struct tcp_md5sig_key *key, + int bplen, + struct tcphdr *th, + unsigned int tcplen, + struct tcp_md5sig_pool *hp); + extern int tcp_v4_calc_md5_hash(char *md5_hash, struct tcp_md5sig_key *key, struct sock *sk, struct dst_entry *dst, struct request_sock *req, struct tcphdr *th, - int protocol, unsigned int tcplen); extern struct tcp_md5sig_key *tcp_v4_md5_lookup(struct sock *sk, struct sock *addr_sk); @@ -1134,6 +1140,16 @@ extern int tcp_v4_md5_do_add(struct sock *sk, extern int tcp_v4_md5_do_del(struct sock *sk, __be32 addr); +#ifdef CONFIG_TCP_MD5SIG +#define tcp_twsk_md5_key(twsk) ((twsk)->tw_md5_keylen ? \ + &(struct tcp_md5sig_key) { \ + .key = (twsk)->tw_md5_key, \ + .keylen = (twsk)->tw_md5_keylen, \ + } : NULL) +#else +#define tcp_twsk_md5_key(twsk) NULL +#endif + extern struct tcp_md5sig_pool **tcp_alloc_md5sig_pool(void); extern void tcp_free_md5sig_pool(void); @@ -1350,7 +1366,7 @@ extern void tcp_proc_unregister(struct net *net, struct tcp_seq_afinfo *afinfo); extern struct request_sock_ops tcp_request_sock_ops; extern struct request_sock_ops tcp6_request_sock_ops; -extern int tcp_v4_destroy_sock(struct sock *sk); +extern void tcp_v4_destroy_sock(struct sock *sk); extern int tcp_v4_gso_send_check(struct sk_buff *skb); extern struct sk_buff *tcp_tso_segment(struct sk_buff *skb, int features); @@ -1371,7 +1387,6 @@ struct tcp_sock_af_ops { struct dst_entry *dst, struct request_sock *req, struct tcphdr *th, - int protocol, unsigned int len); int (*md5_add) (struct sock *sk, struct sock *addr_sk, diff --git a/include/net/tipc/tipc_port.h b/include/net/tipc/tipc_port.h index 11105bcc4457..9923e41a8215 100644 --- a/include/net/tipc/tipc_port.h +++ b/include/net/tipc/tipc_port.h @@ -84,7 +84,8 @@ struct tipc_port { u32 tipc_createport_raw(void *usr_handle, u32 (*dispatcher)(struct tipc_port *, struct sk_buff *), void (*wakeup)(struct tipc_port *), - const u32 importance); + const u32 importance, + struct tipc_port **tp_ptr); int tipc_reject_msg(struct sk_buff *buf, u32 err); diff --git a/include/net/transp_v6.h b/include/net/transp_v6.h index 27394e0447d8..876b6f2bb4fd 100644 --- a/include/net/transp_v6.h +++ b/include/net/transp_v6.h @@ -40,7 +40,8 @@ extern int datagram_recv_ctl(struct sock *sk, struct msghdr *msg, struct sk_buff *skb); -extern int datagram_send_ctl(struct msghdr *msg, +extern int datagram_send_ctl(struct net *net, + struct msghdr *msg, struct flowi *fl, struct ipv6_txoptions *opt, int *hlimit, int *tclass); @@ -52,7 +53,7 @@ extern int datagram_send_ctl(struct msghdr *msg, */ extern struct inet_connection_sock_af_ops ipv4_specific; -extern int inet6_destroy_sock(struct sock *sk); +extern void inet6_destroy_sock(struct sock *sk); #endif diff --git a/include/net/udp.h b/include/net/udp.h index 3e55a99b0ba3..7a8684855245 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -135,6 +135,7 @@ extern void udp_err(struct sk_buff *, u32); extern int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg, size_t len); +extern void udp_flush_pending_frames(struct sock *sk); extern int udp_rcv(struct sk_buff *skb); extern int udp_ioctl(struct sock *sk, int cmd, unsigned long arg); @@ -195,8 +196,8 @@ struct udp_seq_afinfo { struct udp_iter_state { struct seq_net_private p; sa_family_t family; - struct hlist_head *hashtable; int bucket; + struct hlist_head *hashtable; }; #ifdef CONFIG_PROC_FS diff --git a/include/net/wireless.h b/include/net/wireless.h index 667b4080d30f..9324f8dd183e 100644 --- a/include/net/wireless.h +++ b/include/net/wireless.h @@ -39,12 +39,18 @@ enum ieee80211_band { * on this channel. * @IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel. * @IEEE80211_CHAN_RADAR: Radar detection is required on this channel. + * @IEEE80211_CHAN_NO_FAT_ABOVE: extension channel above this channel + * is not permitted. + * @IEEE80211_CHAN_NO_FAT_BELOW: extension channel below this channel + * is not permitted. */ enum ieee80211_channel_flags { IEEE80211_CHAN_DISABLED = 1<<0, IEEE80211_CHAN_PASSIVE_SCAN = 1<<1, IEEE80211_CHAN_NO_IBSS = 1<<2, IEEE80211_CHAN_RADAR = 1<<3, + IEEE80211_CHAN_NO_FAT_ABOVE = 1<<4, + IEEE80211_CHAN_NO_FAT_BELOW = 1<<5, }; /** diff --git a/include/rdma/ib_addr.h b/include/rdma/ib_addr.h index c36750ff6ae8..b42bdd000419 100644 --- a/include/rdma/ib_addr.h +++ b/include/rdma/ib_addr.h @@ -2,29 +2,33 @@ * Copyright (c) 2005 Voltaire Inc. All rights reserved. * Copyright (c) 2005 Intel Corporation. All rights reserved. * - * This Software is licensed under one of the following licenses: + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: * - * 1) under the terms of the "Common Public License 1.0" a copy of which is - * available from the Open Source Initiative, see - * http://www.opensource.org/licenses/cpl.php. + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: * - * 2) under the terms of the "The BSD License" a copy of which is - * available from the Open Source Initiative, see - * http://www.opensource.org/licenses/bsd-license.php. + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. * - * 3) under the terms of the "GNU General Public License (GPL) Version 2" a - * copy of which is available from the Open Source Initiative, see - * http://www.opensource.org/licenses/gpl-license.php. - * - * Licensee has the right to choose one of the above licenses. - * - * Redistributions of source code must retain the above copyright - * notice and one of the license notices. - * - * Redistributions in binary form must reproduce both the above copyright - * notice, one of the license notices in the documentation - * and/or other materials provided with the distribution. + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. */ #if !defined(IB_ADDR_H) diff --git a/include/rdma/ib_cache.h b/include/rdma/ib_cache.h index f179d233ffc3..00a2b8ec327f 100644 --- a/include/rdma/ib_cache.h +++ b/include/rdma/ib_cache.h @@ -30,8 +30,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_cache.h 1349 2004-12-16 21:09:43Z roland $ */ #ifndef _IB_CACHE_H diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h index a627c8682d2f..ec7c6d99ed3f 100644 --- a/include/rdma/ib_cm.h +++ b/include/rdma/ib_cm.h @@ -31,8 +31,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_cm.h 4311 2005-12-05 18:42:01Z sean.hefty $ */ #if !defined(IB_CM_H) #define IB_CM_H diff --git a/include/rdma/ib_fmr_pool.h b/include/rdma/ib_fmr_pool.h index 00dadbf94e1d..f62b842e6596 100644 --- a/include/rdma/ib_fmr_pool.h +++ b/include/rdma/ib_fmr_pool.h @@ -29,8 +29,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_fmr_pool.h 2730 2005-06-28 16:43:03Z sean.hefty $ */ #if !defined(IB_FMR_POOL_H) @@ -61,7 +59,7 @@ struct ib_fmr_pool_param { int pool_size; int dirty_watermark; void (*flush_function)(struct ib_fmr_pool *pool, - void * arg); + void *arg); void *flush_arg; unsigned cache:1; }; diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h index 7228c056b9e9..5f6c40fffcf4 100644 --- a/include/rdma/ib_mad.h +++ b/include/rdma/ib_mad.h @@ -32,11 +32,9 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_mad.h 5596 2006-03-03 01:00:07Z sean.hefty $ */ -#if !defined( IB_MAD_H ) +#if !defined(IB_MAD_H) #define IB_MAD_H #include <linux/list.h> @@ -194,8 +192,7 @@ struct ib_vendor_mad { u8 data[IB_MGMT_VENDOR_DATA]; }; -struct ib_class_port_info -{ +struct ib_class_port_info { u8 base_version; u8 class_version; __be16 capability_mask; @@ -614,11 +611,11 @@ int ib_process_mad_wc(struct ib_mad_agent *mad_agent, * any class specific header, and MAD data area. * If @rmpp_active is set, the RMPP header will be initialized for sending. */ -struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent, - u32 remote_qpn, u16 pkey_index, - int rmpp_active, - int hdr_len, int data_len, - gfp_t gfp_mask); +struct ib_mad_send_buf *ib_create_send_mad(struct ib_mad_agent *mad_agent, + u32 remote_qpn, u16 pkey_index, + int rmpp_active, + int hdr_len, int data_len, + gfp_t gfp_mask); /** * ib_is_mad_class_rmpp - returns whether given management class diff --git a/include/rdma/ib_pack.h b/include/rdma/ib_pack.h index f926020d6331..d7fc45c4eba9 100644 --- a/include/rdma/ib_pack.h +++ b/include/rdma/ib_pack.h @@ -28,8 +28,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_pack.h 1349 2004-12-16 21:09:43Z roland $ */ #ifndef IB_PACK_H diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h index 942692b0b92e..3841c1aff692 100644 --- a/include/rdma/ib_sa.h +++ b/include/rdma/ib_sa.h @@ -30,8 +30,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_sa.h 2811 2005-07-06 18:11:43Z halr $ */ #ifndef IB_SA_H diff --git a/include/rdma/ib_smi.h b/include/rdma/ib_smi.h index f29af135ba83..aaca0878668f 100644 --- a/include/rdma/ib_smi.h +++ b/include/rdma/ib_smi.h @@ -32,11 +32,9 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_smi.h 1389 2004-12-27 22:56:47Z roland $ */ -#if !defined( IB_SMI_H ) +#if !defined(IB_SMI_H) #define IB_SMI_H #include <rdma/ib_mad.h> diff --git a/include/rdma/ib_user_cm.h b/include/rdma/ib_user_cm.h index 37650afb982c..bd3d380781e0 100644 --- a/include/rdma/ib_user_cm.h +++ b/include/rdma/ib_user_cm.h @@ -29,8 +29,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_user_cm.h 4019 2005-11-11 00:33:09Z sean.hefty $ */ #ifndef IB_USER_CM_H diff --git a/include/rdma/ib_user_mad.h b/include/rdma/ib_user_mad.h index 29d2c7205a90..d6fce1cbdb90 100644 --- a/include/rdma/ib_user_mad.h +++ b/include/rdma/ib_user_mad.h @@ -29,8 +29,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_user_mad.h 2814 2005-07-06 19:14:09Z halr $ */ #ifndef IB_USER_MAD_H diff --git a/include/rdma/ib_user_verbs.h b/include/rdma/ib_user_verbs.h index 8d65bf0a625b..a17f77106149 100644 --- a/include/rdma/ib_user_verbs.h +++ b/include/rdma/ib_user_verbs.h @@ -31,8 +31,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_user_verbs.h 4019 2005-11-11 00:33:09Z sean.hefty $ */ #ifndef IB_USER_VERBS_H @@ -291,7 +289,10 @@ struct ib_uverbs_wc { __u32 opcode; __u32 vendor_err; __u32 byte_len; - __u32 imm_data; + union { + __u32 imm_data; + __u32 invalidate_rkey; + } ex; __u32 qp_num; __u32 src_qp; __u32 wc_flags; diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index 911a661b7278..4c3c76b03c8c 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -34,8 +34,6 @@ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. - * - * $Id: ib_verbs.h 1349 2004-12-16 21:09:43Z roland $ */ #if !defined(IB_VERBS_H) @@ -105,7 +103,7 @@ enum ib_device_cap_flags { */ IB_DEVICE_UD_IP_CSUM = (1<<18), IB_DEVICE_UD_TSO = (1<<19), - IB_DEVICE_SEND_W_INV = (1<<21), + IB_DEVICE_MEM_MGT_EXTENSIONS = (1<<21), }; enum ib_atomic_cap { @@ -151,6 +149,7 @@ struct ib_device_attr { int max_srq; int max_srq_wr; int max_srq_sge; + unsigned int max_fast_reg_page_list_len; u16 max_pkeys; u8 local_ca_ack_delay; }; @@ -414,6 +413,8 @@ enum ib_wc_opcode { IB_WC_FETCH_ADD, IB_WC_BIND_MW, IB_WC_LSO, + IB_WC_LOCAL_INV, + IB_WC_FAST_REG_MR, /* * Set value of IB_WC_RECV so consumers can test if a completion is a * receive by testing (opcode & IB_WC_RECV). @@ -424,7 +425,8 @@ enum ib_wc_opcode { enum ib_wc_flags { IB_WC_GRH = 1, - IB_WC_WITH_IMM = (1<<1) + IB_WC_WITH_IMM = (1<<1), + IB_WC_WITH_INVALIDATE = (1<<2), }; struct ib_wc { @@ -434,7 +436,10 @@ struct ib_wc { u32 vendor_err; u32 byte_len; struct ib_qp *qp; - __be32 imm_data; + union { + __be32 imm_data; + u32 invalidate_rkey; + } ex; u32 src_qp; int wc_flags; u16 pkey_index; @@ -628,6 +633,9 @@ enum ib_wr_opcode { IB_WR_ATOMIC_FETCH_AND_ADD, IB_WR_LSO, IB_WR_SEND_WITH_INV, + IB_WR_RDMA_READ_WITH_INV, + IB_WR_LOCAL_INV, + IB_WR_FAST_REG_MR, }; enum ib_send_flags { @@ -644,6 +652,12 @@ struct ib_sge { u32 lkey; }; +struct ib_fast_reg_page_list { + struct ib_device *device; + u64 *page_list; + unsigned int max_page_list_len; +}; + struct ib_send_wr { struct ib_send_wr *next; u64 wr_id; @@ -676,6 +690,16 @@ struct ib_send_wr { u16 pkey_index; /* valid for GSI only */ u8 port_num; /* valid for DR SMPs on switch only */ } ud; + struct { + u64 iova_start; + struct ib_fast_reg_page_list *page_list; + unsigned int page_shift; + unsigned int page_list_len; + unsigned int first_byte_offset; + u32 length; + int access_flags; + u32 rkey; + } fast_reg; } wr; }; @@ -778,7 +802,7 @@ struct ib_cq { struct ib_uobject *uobject; ib_comp_handler comp_handler; void (*event_handler)(struct ib_event *, void *); - void * cq_context; + void *cq_context; int cqe; atomic_t usecnt; /* count number of work queues */ }; @@ -884,7 +908,7 @@ struct ib_dma_mapping_ops { void (*sync_single_for_cpu)(struct ib_device *dev, u64 dma_handle, size_t size, - enum dma_data_direction dir); + enum dma_data_direction dir); void (*sync_single_for_device)(struct ib_device *dev, u64 dma_handle, size_t size, @@ -1014,6 +1038,11 @@ struct ib_device { int (*query_mr)(struct ib_mr *mr, struct ib_mr_attr *mr_attr); int (*dereg_mr)(struct ib_mr *mr); + struct ib_mr * (*alloc_fast_reg_mr)(struct ib_pd *pd, + int max_page_list_len); + struct ib_fast_reg_page_list * (*alloc_fast_reg_page_list)(struct ib_device *device, + int page_list_len); + void (*free_fast_reg_page_list)(struct ib_fast_reg_page_list *page_list); int (*rereg_phys_mr)(struct ib_mr *mr, int mr_rereg_mask, struct ib_pd *pd, @@ -1808,6 +1837,54 @@ int ib_query_mr(struct ib_mr *mr, struct ib_mr_attr *mr_attr); int ib_dereg_mr(struct ib_mr *mr); /** + * ib_alloc_fast_reg_mr - Allocates memory region usable with the + * IB_WR_FAST_REG_MR send work request. + * @pd: The protection domain associated with the region. + * @max_page_list_len: requested max physical buffer list length to be + * used with fast register work requests for this MR. + */ +struct ib_mr *ib_alloc_fast_reg_mr(struct ib_pd *pd, int max_page_list_len); + +/** + * ib_alloc_fast_reg_page_list - Allocates a page list array + * @device - ib device pointer. + * @page_list_len - size of the page list array to be allocated. + * + * This allocates and returns a struct ib_fast_reg_page_list * and a + * page_list array that is at least page_list_len in size. The actual + * size is returned in max_page_list_len. The caller is responsible + * for initializing the contents of the page_list array before posting + * a send work request with the IB_WC_FAST_REG_MR opcode. + * + * The page_list array entries must be translated using one of the + * ib_dma_*() functions just like the addresses passed to + * ib_map_phys_fmr(). Once the ib_post_send() is issued, the struct + * ib_fast_reg_page_list must not be modified by the caller until the + * IB_WC_FAST_REG_MR work request completes. + */ +struct ib_fast_reg_page_list *ib_alloc_fast_reg_page_list( + struct ib_device *device, int page_list_len); + +/** + * ib_free_fast_reg_page_list - Deallocates a previously allocated + * page list array. + * @page_list - struct ib_fast_reg_page_list pointer to be deallocated. + */ +void ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list); + +/** + * ib_update_fast_reg_key - updates the key portion of the fast_reg MR + * R_Key and L_Key. + * @mr - struct ib_mr pointer to be updated. + * @newkey - new key to be used. + */ +static inline void ib_update_fast_reg_key(struct ib_mr *mr, u8 newkey) +{ + mr->lkey = (mr->lkey & 0xffffff00) | newkey; + mr->rkey = (mr->rkey & 0xffffff00) | newkey; +} + +/** * ib_alloc_mw - Allocates a memory window. * @pd: The protection domain associated with the memory window. */ diff --git a/include/rdma/iw_cm.h b/include/rdma/iw_cm.h index aeefa9b740dc..cbb822e8d791 100644 --- a/include/rdma/iw_cm.h +++ b/include/rdma/iw_cm.h @@ -62,7 +62,7 @@ struct iw_cm_event { struct sockaddr_in remote_addr; void *private_data; u8 private_data_len; - void* provider_data; + void *provider_data; }; /** diff --git a/include/rdma/rdma_cm.h b/include/rdma/rdma_cm.h index 010f876f41d8..22bb2e7bab1a 100644 --- a/include/rdma/rdma_cm.h +++ b/include/rdma/rdma_cm.h @@ -2,29 +2,33 @@ * Copyright (c) 2005 Voltaire Inc. All rights reserved. * Copyright (c) 2005 Intel Corporation. All rights reserved. * - * This Software is licensed under one of the following licenses: + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: * - * 1) under the terms of the "Common Public License 1.0" a copy of which is - * available from the Open Source Initiative, see - * http://www.opensource.org/licenses/cpl.php. + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: * - * 2) under the terms of the "The BSD License" a copy of which is - * available from the Open Source Initiative, see - * http://www.opensource.org/licenses/bsd-license.php. + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. * - * 3) under the terms of the "GNU General Public License (GPL) Version 2" a - * copy of which is available from the Open Source Initiative, see - * http://www.opensource.org/licenses/gpl-license.php. - * - * Licensee has the right to choose one of the above licenses. - * - * Redistributions of source code must retain the above copyright - * notice and one of the license notices. - * - * Redistributions in binary form must reproduce both the above copyright - * notice, one of the license notices in the documentation - * and/or other materials provided with the distribution. + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. */ #if !defined(RDMA_CM_H) @@ -57,11 +61,11 @@ enum rdma_cm_event_type { }; enum rdma_port_space { - RDMA_PS_SDP = 0x0001, - RDMA_PS_IPOIB= 0x0002, - RDMA_PS_TCP = 0x0106, - RDMA_PS_UDP = 0x0111, - RDMA_PS_SCTP = 0x0183 + RDMA_PS_SDP = 0x0001, + RDMA_PS_IPOIB = 0x0002, + RDMA_PS_TCP = 0x0106, + RDMA_PS_UDP = 0x0111, + RDMA_PS_SCTP = 0x0183 }; struct rdma_addr { diff --git a/include/rdma/rdma_cm_ib.h b/include/rdma/rdma_cm_ib.h index 950424b38f16..2389c3b45404 100644 --- a/include/rdma/rdma_cm_ib.h +++ b/include/rdma/rdma_cm_ib.h @@ -1,29 +1,33 @@ /* * Copyright (c) 2006 Intel Corporation. All rights reserved. * - * This Software is licensed under one of the following licenses: - * - * 1) under the terms of the "Common Public License 1.0" a copy of which is - * available from the Open Source Initiative, see - * http://www.opensource.org/licenses/cpl.php. - * - * 2) under the terms of the "The BSD License" a copy of which is - * available from the Open Source Initiative, see - * http://www.opensource.org/licenses/bsd-license.php. - * - * 3) under the terms of the "GNU General Public License (GPL) Version 2" a - * copy of which is available from the Open Source Initiative, see - * http://www.opensource.org/licenses/gpl-license.php. - * - * Licensee has the right to choose one of the above licenses. - * - * Redistributions of source code must retain the above copyright - * notice and one of the license notices. - * - * Redistributions in binary form must reproduce both the above copyright - * notice, one of the license notices in the documentation - * and/or other materials provided with the distribution. - * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. */ #if !defined(RDMA_CM_IB_H) diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h index e19e58423166..16be12f1cbe8 100644 --- a/include/scsi/iscsi_if.h +++ b/include/scsi/iscsi_if.h @@ -50,6 +50,7 @@ enum iscsi_uevent_e { ISCSI_UEVENT_TGT_DSCVR = UEVENT_BASE + 15, ISCSI_UEVENT_SET_HOST_PARAM = UEVENT_BASE + 16, ISCSI_UEVENT_UNBIND_SESSION = UEVENT_BASE + 17, + ISCSI_UEVENT_CREATE_BOUND_SESSION = UEVENT_BASE + 18, /* up events */ ISCSI_KEVENT_RECV_PDU = KEVENT_BASE + 1, @@ -78,6 +79,12 @@ struct iscsi_uevent { uint16_t cmds_max; uint16_t queue_depth; } c_session; + struct msg_create_bound_session { + uint64_t ep_handle; + uint32_t initial_cmdsn; + uint16_t cmds_max; + uint16_t queue_depth; + } c_bound_session; struct msg_destroy_session { uint32_t sid; } d_session; @@ -250,42 +257,49 @@ enum iscsi_param { ISCSI_PARAM_PING_TMO, ISCSI_PARAM_RECV_TMO, + + ISCSI_PARAM_IFACE_NAME, + ISCSI_PARAM_ISID, + ISCSI_PARAM_INITIATOR_NAME, /* must always be last */ ISCSI_PARAM_MAX, }; -#define ISCSI_MAX_RECV_DLENGTH (1 << ISCSI_PARAM_MAX_RECV_DLENGTH) -#define ISCSI_MAX_XMIT_DLENGTH (1 << ISCSI_PARAM_MAX_XMIT_DLENGTH) -#define ISCSI_HDRDGST_EN (1 << ISCSI_PARAM_HDRDGST_EN) -#define ISCSI_DATADGST_EN (1 << ISCSI_PARAM_DATADGST_EN) -#define ISCSI_INITIAL_R2T_EN (1 << ISCSI_PARAM_INITIAL_R2T_EN) -#define ISCSI_MAX_R2T (1 << ISCSI_PARAM_MAX_R2T) -#define ISCSI_IMM_DATA_EN (1 << ISCSI_PARAM_IMM_DATA_EN) -#define ISCSI_FIRST_BURST (1 << ISCSI_PARAM_FIRST_BURST) -#define ISCSI_MAX_BURST (1 << ISCSI_PARAM_MAX_BURST) -#define ISCSI_PDU_INORDER_EN (1 << ISCSI_PARAM_PDU_INORDER_EN) -#define ISCSI_DATASEQ_INORDER_EN (1 << ISCSI_PARAM_DATASEQ_INORDER_EN) -#define ISCSI_ERL (1 << ISCSI_PARAM_ERL) -#define ISCSI_IFMARKER_EN (1 << ISCSI_PARAM_IFMARKER_EN) -#define ISCSI_OFMARKER_EN (1 << ISCSI_PARAM_OFMARKER_EN) -#define ISCSI_EXP_STATSN (1 << ISCSI_PARAM_EXP_STATSN) -#define ISCSI_TARGET_NAME (1 << ISCSI_PARAM_TARGET_NAME) -#define ISCSI_TPGT (1 << ISCSI_PARAM_TPGT) -#define ISCSI_PERSISTENT_ADDRESS (1 << ISCSI_PARAM_PERSISTENT_ADDRESS) -#define ISCSI_PERSISTENT_PORT (1 << ISCSI_PARAM_PERSISTENT_PORT) -#define ISCSI_SESS_RECOVERY_TMO (1 << ISCSI_PARAM_SESS_RECOVERY_TMO) -#define ISCSI_CONN_PORT (1 << ISCSI_PARAM_CONN_PORT) -#define ISCSI_CONN_ADDRESS (1 << ISCSI_PARAM_CONN_ADDRESS) -#define ISCSI_USERNAME (1 << ISCSI_PARAM_USERNAME) -#define ISCSI_USERNAME_IN (1 << ISCSI_PARAM_USERNAME_IN) -#define ISCSI_PASSWORD (1 << ISCSI_PARAM_PASSWORD) -#define ISCSI_PASSWORD_IN (1 << ISCSI_PARAM_PASSWORD_IN) -#define ISCSI_FAST_ABORT (1 << ISCSI_PARAM_FAST_ABORT) -#define ISCSI_ABORT_TMO (1 << ISCSI_PARAM_ABORT_TMO) -#define ISCSI_LU_RESET_TMO (1 << ISCSI_PARAM_LU_RESET_TMO) -#define ISCSI_HOST_RESET_TMO (1 << ISCSI_PARAM_HOST_RESET_TMO) -#define ISCSI_PING_TMO (1 << ISCSI_PARAM_PING_TMO) -#define ISCSI_RECV_TMO (1 << ISCSI_PARAM_RECV_TMO) +#define ISCSI_MAX_RECV_DLENGTH (1ULL << ISCSI_PARAM_MAX_RECV_DLENGTH) +#define ISCSI_MAX_XMIT_DLENGTH (1ULL << ISCSI_PARAM_MAX_XMIT_DLENGTH) +#define ISCSI_HDRDGST_EN (1ULL << ISCSI_PARAM_HDRDGST_EN) +#define ISCSI_DATADGST_EN (1ULL << ISCSI_PARAM_DATADGST_EN) +#define ISCSI_INITIAL_R2T_EN (1ULL << ISCSI_PARAM_INITIAL_R2T_EN) +#define ISCSI_MAX_R2T (1ULL << ISCSI_PARAM_MAX_R2T) +#define ISCSI_IMM_DATA_EN (1ULL << ISCSI_PARAM_IMM_DATA_EN) +#define ISCSI_FIRST_BURST (1ULL << ISCSI_PARAM_FIRST_BURST) +#define ISCSI_MAX_BURST (1ULL << ISCSI_PARAM_MAX_BURST) +#define ISCSI_PDU_INORDER_EN (1ULL << ISCSI_PARAM_PDU_INORDER_EN) +#define ISCSI_DATASEQ_INORDER_EN (1ULL << ISCSI_PARAM_DATASEQ_INORDER_EN) +#define ISCSI_ERL (1ULL << ISCSI_PARAM_ERL) +#define ISCSI_IFMARKER_EN (1ULL << ISCSI_PARAM_IFMARKER_EN) +#define ISCSI_OFMARKER_EN (1ULL << ISCSI_PARAM_OFMARKER_EN) +#define ISCSI_EXP_STATSN (1ULL << ISCSI_PARAM_EXP_STATSN) +#define ISCSI_TARGET_NAME (1ULL << ISCSI_PARAM_TARGET_NAME) +#define ISCSI_TPGT (1ULL << ISCSI_PARAM_TPGT) +#define ISCSI_PERSISTENT_ADDRESS (1ULL << ISCSI_PARAM_PERSISTENT_ADDRESS) +#define ISCSI_PERSISTENT_PORT (1ULL << ISCSI_PARAM_PERSISTENT_PORT) +#define ISCSI_SESS_RECOVERY_TMO (1ULL << ISCSI_PARAM_SESS_RECOVERY_TMO) +#define ISCSI_CONN_PORT (1ULL << ISCSI_PARAM_CONN_PORT) +#define ISCSI_CONN_ADDRESS (1ULL << ISCSI_PARAM_CONN_ADDRESS) +#define ISCSI_USERNAME (1ULL << ISCSI_PARAM_USERNAME) +#define ISCSI_USERNAME_IN (1ULL << ISCSI_PARAM_USERNAME_IN) +#define ISCSI_PASSWORD (1ULL << ISCSI_PARAM_PASSWORD) +#define ISCSI_PASSWORD_IN (1ULL << ISCSI_PARAM_PASSWORD_IN) +#define ISCSI_FAST_ABORT (1ULL << ISCSI_PARAM_FAST_ABORT) +#define ISCSI_ABORT_TMO (1ULL << ISCSI_PARAM_ABORT_TMO) +#define ISCSI_LU_RESET_TMO (1ULL << ISCSI_PARAM_LU_RESET_TMO) +#define ISCSI_HOST_RESET_TMO (1ULL << ISCSI_PARAM_HOST_RESET_TMO) +#define ISCSI_PING_TMO (1ULL << ISCSI_PARAM_PING_TMO) +#define ISCSI_RECV_TMO (1ULL << ISCSI_PARAM_RECV_TMO) +#define ISCSI_IFACE_NAME (1ULL << ISCSI_PARAM_IFACE_NAME) +#define ISCSI_ISID (1ULL << ISCSI_PARAM_ISID) +#define ISCSI_INITIATOR_NAME (1ULL << ISCSI_PARAM_INITIATOR_NAME) /* iSCSI HBA params */ enum iscsi_host_param { @@ -296,20 +310,13 @@ enum iscsi_host_param { ISCSI_HOST_PARAM_MAX, }; -#define ISCSI_HOST_HWADDRESS (1 << ISCSI_HOST_PARAM_HWADDRESS) -#define ISCSI_HOST_INITIATOR_NAME (1 << ISCSI_HOST_PARAM_INITIATOR_NAME) -#define ISCSI_HOST_NETDEV_NAME (1 << ISCSI_HOST_PARAM_NETDEV_NAME) -#define ISCSI_HOST_IPADDRESS (1 << ISCSI_HOST_PARAM_IPADDRESS) +#define ISCSI_HOST_HWADDRESS (1ULL << ISCSI_HOST_PARAM_HWADDRESS) +#define ISCSI_HOST_INITIATOR_NAME (1ULL << ISCSI_HOST_PARAM_INITIATOR_NAME) +#define ISCSI_HOST_NETDEV_NAME (1ULL << ISCSI_HOST_PARAM_NETDEV_NAME) +#define ISCSI_HOST_IPADDRESS (1ULL << ISCSI_HOST_PARAM_IPADDRESS) #define iscsi_ptr(_handle) ((void*)(unsigned long)_handle) #define iscsi_handle(_ptr) ((uint64_t)(unsigned long)_ptr) -#define hostdata_session(_hostdata) (iscsi_ptr(*(unsigned long *)_hostdata)) - -/** - * iscsi_hostdata - get LLD hostdata from scsi_host - * @_hostdata: pointer to scsi host's hostdata - **/ -#define iscsi_hostdata(_hostdata) ((void*)_hostdata + sizeof(unsigned long)) /* * These flags presents iSCSI Data-Path capabilities. diff --git a/include/scsi/iscsi_proto.h b/include/scsi/iscsi_proto.h index e0593bfae622..f2a2c1169486 100644 --- a/include/scsi/iscsi_proto.h +++ b/include/scsi/iscsi_proto.h @@ -22,6 +22,7 @@ #define ISCSI_PROTO_H #include <linux/types.h> +#include <scsi/scsi.h> #define ISCSI_DRAFT20_VERSION 0x00 @@ -156,7 +157,7 @@ struct iscsi_ecdb_ahdr { uint8_t ahstype; uint8_t reserved; /* 4-byte aligned extended CDB spillover */ - uint8_t ecdb[260 - ISCSI_CDB_SIZE]; + uint8_t ecdb[SCSI_MAX_VARLEN_CDB_SIZE - ISCSI_CDB_SIZE]; }; /* SCSI Response Header */ diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h index cd3ca63d4fb1..5e75bb7f311c 100644 --- a/include/scsi/libiscsi.h +++ b/include/scsi/libiscsi.h @@ -24,6 +24,7 @@ #define LIBISCSI_H #include <linux/types.h> +#include <linux/wait.h> #include <linux/mutex.h> #include <linux/timer.h> #include <linux/workqueue.h> @@ -31,6 +32,7 @@ #include <scsi/iscsi_if.h> struct scsi_transport_template; +struct scsi_host_template; struct scsi_device; struct Scsi_Host; struct scsi_cmnd; @@ -40,6 +42,7 @@ struct iscsi_cls_session; struct iscsi_cls_conn; struct iscsi_session; struct iscsi_nopin; +struct device; /* #define DEBUG_SCSI */ #ifdef DEBUG_SCSI @@ -49,9 +52,7 @@ struct iscsi_nopin; #endif #define ISCSI_DEF_XMIT_CMDS_MAX 128 /* must be power of 2 */ -#define ISCSI_MGMT_CMDS_MAX 16 /* must be power of 2 */ - -#define ISCSI_MGMT_ITT_OFFSET 0xa00 +#define ISCSI_MGMT_CMDS_MAX 15 #define ISCSI_DEF_CMD_PER_LUN 32 #define ISCSI_MAX_CMD_PER_LUN 128 @@ -69,7 +70,10 @@ enum { /* Connection suspend "bit" */ #define ISCSI_SUSPEND_BIT 1 -#define ISCSI_ITT_MASK (0xfff) +#define ISCSI_ITT_MASK (0x1fff) +#define ISCSI_TOTAL_CMDS_MAX 4096 +/* this must be a power of two greater than ISCSI_MGMT_CMDS_MAX */ +#define ISCSI_TOTAL_CMDS_MIN 16 #define ISCSI_AGE_SHIFT 28 #define ISCSI_AGE_MASK (0xf << ISCSI_AGE_SHIFT) @@ -82,18 +86,6 @@ enum { ISCSI_DIGEST_SIZE = sizeof(__u32), }; -struct iscsi_mgmt_task { - /* - * Becuae LLDs allocate their hdr differently, this is a pointer to - * that storage. It must be setup at session creation time. - */ - struct iscsi_hdr *hdr; - char *data; /* mgmt payload */ - unsigned data_count; /* counts data to be sent */ - uint32_t itt; /* this ITT */ - void *dd_data; /* driver/transport data */ - struct list_head running; -}; enum { ISCSI_TASK_COMPLETED, @@ -101,7 +93,7 @@ enum { ISCSI_TASK_RUNNING, }; -struct iscsi_cmd_task { +struct iscsi_task { /* * Because LLDs allocate their hdr differently, this is a pointer * and length to that storage. It must be setup at session @@ -118,6 +110,7 @@ struct iscsi_cmd_task { /* offset in unsolicited stream (bytes); */ unsigned unsol_offset; unsigned data_count; /* remaining Data-Out */ + char *data; /* mgmt payload */ struct scsi_cmnd *sc; /* associated SCSI cmd*/ struct iscsi_conn *conn; /* used connection */ @@ -128,9 +121,9 @@ struct iscsi_cmd_task { void *dd_data; /* driver/transport data */ }; -static inline void* iscsi_next_hdr(struct iscsi_cmd_task *ctask) +static inline void* iscsi_next_hdr(struct iscsi_task *task) { - return (void*)ctask->hdr + ctask->hdr_len; + return (void*)task->hdr + task->hdr_len; } /* Connection's states */ @@ -146,11 +139,6 @@ struct iscsi_conn { void *dd_data; /* iscsi_transport data */ struct iscsi_session *session; /* parent session */ /* - * LLDs should set this lock. It protects the transport recv - * code - */ - rwlock_t *recv_lock; - /* * conn_stop() flag: stop to recover, stop to terminate */ int stop_stage; @@ -159,7 +147,7 @@ struct iscsi_conn { unsigned long last_ping; int ping_timeout; int recv_timeout; - struct iscsi_mgmt_task *ping_mtask; + struct iscsi_task *ping_task; /* iSCSI connection-wide sequencing */ uint32_t exp_statsn; @@ -175,9 +163,8 @@ struct iscsi_conn { * should always fit in this buffer */ char *data; - struct iscsi_mgmt_task *login_mtask; /* mtask used for login/text */ - struct iscsi_mgmt_task *mtask; /* xmit mtask in progress */ - struct iscsi_cmd_task *ctask; /* xmit ctask in progress */ + struct iscsi_task *login_task; /* mtask used for login/text */ + struct iscsi_task *task; /* xmit task in progress */ /* xmit */ struct list_head mgmtqueue; /* mgmt (control) xmit queue */ @@ -208,9 +195,6 @@ struct iscsi_conn { /* remote portal currently connected to */ int portal_port; char portal_address[ISCSI_ADDRESS_BUF_LEN]; - /* local address */ - int local_port; - char local_address[ISCSI_ADDRESS_BUF_LEN]; /* MIB-statistics */ uint64_t txdata_octets; @@ -246,6 +230,7 @@ enum { }; struct iscsi_session { + struct iscsi_cls_session *cls_session; /* * Syncs up the scsi eh thread with the iscsi eh thread when sending * task management functions. This must be taken before the session @@ -281,10 +266,8 @@ struct iscsi_session { char *password; char *password_in; char *targetname; + char *ifacename; char *initiatorname; - /* hw address or netdev iscsi connection is bound to */ - char *hwaddress; - char *netdev; /* control data */ struct iscsi_transport *tt; struct Scsi_Host *host; @@ -298,12 +281,20 @@ struct iscsi_session { int state; /* session state */ int age; /* counts session re-opens */ + int scsi_cmds_max; /* max scsi commands */ int cmds_max; /* size of cmds array */ - struct iscsi_cmd_task **cmds; /* Original Cmds arr */ + struct iscsi_task **cmds; /* Original Cmds arr */ struct iscsi_pool cmdpool; /* PDU's pool */ - int mgmtpool_max; /* size of mgmt array */ - struct iscsi_mgmt_task **mgmt_cmds; /* Original mgmt arr */ - struct iscsi_pool mgmtpool; /* Mgmt PDU's pool */ +}; + +struct iscsi_host { + char *initiatorname; + /* hw address or netdev iscsi connection is bound to */ + char *hwaddress; + char *netdev; + /* local address */ + int local_port; + char local_address[ISCSI_ADDRESS_BUF_LEN]; }; /* @@ -316,42 +307,44 @@ extern int iscsi_eh_device_reset(struct scsi_cmnd *sc); extern int iscsi_queuecommand(struct scsi_cmnd *sc, void (*done)(struct scsi_cmnd *)); - /* * iSCSI host helpers. */ +#define iscsi_host_priv(_shost) \ + (shost_priv(_shost) + sizeof(struct iscsi_host)) + extern int iscsi_host_set_param(struct Scsi_Host *shost, enum iscsi_host_param param, char *buf, int buflen); extern int iscsi_host_get_param(struct Scsi_Host *shost, enum iscsi_host_param param, char *buf); +extern int iscsi_host_add(struct Scsi_Host *shost, struct device *pdev); +extern struct Scsi_Host *iscsi_host_alloc(struct scsi_host_template *sht, + int dd_data_size, uint16_t qdepth); +extern void iscsi_host_remove(struct Scsi_Host *shost); +extern void iscsi_host_free(struct Scsi_Host *shost); /* * session management */ extern struct iscsi_cls_session * -iscsi_session_setup(struct iscsi_transport *, struct scsi_transport_template *, - uint16_t, uint16_t, int, int, uint32_t, uint32_t *); +iscsi_session_setup(struct iscsi_transport *, struct Scsi_Host *shost, + uint16_t, int, uint32_t, unsigned int); extern void iscsi_session_teardown(struct iscsi_cls_session *); -extern struct iscsi_session *class_to_transport_session(struct iscsi_cls_session *); extern void iscsi_session_recovery_timedout(struct iscsi_cls_session *); extern int iscsi_set_param(struct iscsi_cls_conn *cls_conn, enum iscsi_param param, char *buf, int buflen); extern int iscsi_session_get_param(struct iscsi_cls_session *cls_session, enum iscsi_param param, char *buf); -#define session_to_cls(_sess) \ - hostdata_session(_sess->host->hostdata) - #define iscsi_session_printk(prefix, _sess, fmt, a...) \ - iscsi_cls_session_printk(prefix, \ - (struct iscsi_cls_session *)session_to_cls(_sess), fmt, ##a) + iscsi_cls_session_printk(prefix, _sess->cls_session, fmt, ##a) /* * connection management */ extern struct iscsi_cls_conn *iscsi_conn_setup(struct iscsi_cls_session *, - uint32_t); + int, uint32_t); extern void iscsi_conn_teardown(struct iscsi_cls_conn *); extern int iscsi_conn_start(struct iscsi_cls_conn *); extern void iscsi_conn_stop(struct iscsi_cls_conn *, int); @@ -360,25 +353,29 @@ extern int iscsi_conn_bind(struct iscsi_cls_session *, struct iscsi_cls_conn *, extern void iscsi_conn_failure(struct iscsi_conn *conn, enum iscsi_err err); extern int iscsi_conn_get_param(struct iscsi_cls_conn *cls_conn, enum iscsi_param param, char *buf); +extern void iscsi_suspend_tx(struct iscsi_conn *conn); #define iscsi_conn_printk(prefix, _c, fmt, a...) \ - iscsi_cls_conn_printk(prefix, _c->cls_conn, fmt, ##a) + iscsi_cls_conn_printk(prefix, ((struct iscsi_conn *)_c)->cls_conn, \ + fmt, ##a) /* * pdu and task processing */ extern void iscsi_update_cmdsn(struct iscsi_session *, struct iscsi_nopin *); -extern void iscsi_prep_unsolicit_data_pdu(struct iscsi_cmd_task *, +extern void iscsi_prep_unsolicit_data_pdu(struct iscsi_task *, struct iscsi_data *hdr); extern int iscsi_conn_send_pdu(struct iscsi_cls_conn *, struct iscsi_hdr *, char *, uint32_t); extern int iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *, char *, int); -extern int iscsi_verify_itt(struct iscsi_conn *, struct iscsi_hdr *, - uint32_t *); -extern void iscsi_requeue_ctask(struct iscsi_cmd_task *ctask); -extern void iscsi_free_mgmt_task(struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask); +extern int __iscsi_complete_pdu(struct iscsi_conn *, struct iscsi_hdr *, + char *, int); +extern int iscsi_verify_itt(struct iscsi_conn *, itt_t); +extern struct iscsi_task *iscsi_itt_to_ctask(struct iscsi_conn *, itt_t); +extern void iscsi_requeue_task(struct iscsi_task *task); +extern void iscsi_put_task(struct iscsi_task *task); +extern void __iscsi_get_task(struct iscsi_task *task); /* * generic helpers diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h index 32742c4563de..2b5b9356c314 100644 --- a/include/scsi/scsi.h +++ b/include/scsi/scsi.h @@ -400,6 +400,7 @@ struct scsi_lun { #define SOFT_ERROR 0x2005 #define ADD_TO_MLQUEUE 0x2006 #define TIMEOUT_ERROR 0x2007 +#define SCSI_RETURN_NOT_HANDLED 0x2008 /* * Midlevel queue return values. diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h index f6a9fe0ef09c..6467f78b191f 100644 --- a/include/scsi/scsi_device.h +++ b/include/scsi/scsi_device.h @@ -134,6 +134,7 @@ struct scsi_device { unsigned no_start_on_add:1; /* do not issue start on add */ unsigned allow_restart:1; /* issue START_UNIT in error handler */ unsigned manage_start_stop:1; /* Let HLD (sd) manage start/stop */ + unsigned start_stop_pwr_cond:1; /* Set power cond. in START_STOP_UNIT */ unsigned no_uld_attach:1; /* disable connecting to upper level drivers */ unsigned select_no_atn:1; unsigned fix_capacity:1; /* READ_CAPACITY is too high by 1 */ @@ -161,9 +162,29 @@ struct scsi_device { struct execute_work ew; /* used to get process context on put */ + struct scsi_dh_data *scsi_dh_data; enum scsi_device_state sdev_state; unsigned long sdev_data[0]; } __attribute__((aligned(sizeof(unsigned long)))); + +struct scsi_device_handler { + /* Used by the infrastructure */ + struct list_head list; /* list of scsi_device_handlers */ + struct notifier_block nb; + + /* Filled by the hardware handler */ + struct module *module; + const char *name; + int (*check_sense)(struct scsi_device *, struct scsi_sense_hdr *); + int (*activate)(struct scsi_device *); + int (*prep_fn)(struct scsi_device *, struct request *); +}; + +struct scsi_dh_data { + struct scsi_device_handler *scsi_dh; + char buf[0]; +}; + #define to_scsi_device(d) \ container_of(d, struct scsi_device, sdev_gendev) #define class_to_sdev(d) \ @@ -230,7 +251,9 @@ extern struct scsi_device *__scsi_add_device(struct Scsi_Host *, uint, uint, uint, void *hostdata); extern int scsi_add_device(struct Scsi_Host *host, uint channel, uint target, uint lun); +extern int scsi_register_device_handler(struct scsi_device_handler *scsi_dh); extern void scsi_remove_device(struct scsi_device *); +extern int scsi_unregister_device_handler(struct scsi_device_handler *scsi_dh); extern int scsi_device_get(struct scsi_device *); extern void scsi_device_put(struct scsi_device *); diff --git a/include/scsi/scsi_dh.h b/include/scsi/scsi_dh.h new file mode 100644 index 000000000000..04d0d8495c83 --- /dev/null +++ b/include/scsi/scsi_dh.h @@ -0,0 +1,59 @@ +/* + * Header file for SCSI device handler infrastruture. + * + * Modified version of patches posted by Mike Christie <michaelc@cs.wisc.edu> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright IBM Corporation, 2007 + * Authors: + * Chandra Seetharaman <sekharan@us.ibm.com> + * Mike Anderson <andmike@linux.vnet.ibm.com> + */ + +#include <scsi/scsi_device.h> + +enum { + SCSI_DH_OK = 0, + /* + * device errors + */ + SCSI_DH_DEV_FAILED, /* generic device error */ + SCSI_DH_DEV_TEMP_BUSY, + SCSI_DH_DEVICE_MAX, /* max device blkerr definition */ + + /* + * transport errors + */ + SCSI_DH_NOTCONN = SCSI_DH_DEVICE_MAX + 1, + SCSI_DH_CONN_FAILURE, + SCSI_DH_TRANSPORT_MAX, /* max transport blkerr definition */ + + /* + * driver and generic errors + */ + SCSI_DH_IO = SCSI_DH_TRANSPORT_MAX + 1, /* generic error */ + SCSI_DH_INVALID_IO, + SCSI_DH_RETRY, /* retry the req, but not immediately */ + SCSI_DH_IMM_RETRY, /* immediately retry the req */ + SCSI_DH_TIMED_OUT, + SCSI_DH_RES_TEMP_UNAVAIL, + SCSI_DH_DEV_OFFLINED, + SCSI_DH_NOSYS, + SCSI_DH_DRIVER_MAX, +}; + +extern int scsi_dh_activate(struct request_queue *); +extern int scsi_dh_handler_exist(const char *); diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h index 1834fdfe82a7..a594bac4a77d 100644 --- a/include/scsi/scsi_host.h +++ b/include/scsi/scsi_host.h @@ -623,7 +623,7 @@ struct Scsi_Host { /* * Optional work queue to be utilized by the transport */ - char work_q_name[KOBJ_NAME_LEN]; + char work_q_name[20]; struct workqueue_struct *work_q; /* diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h index 06f72bab9df0..878373c32ef7 100644 --- a/include/scsi/scsi_transport_fc.h +++ b/include/scsi/scsi_transport_fc.h @@ -489,9 +489,9 @@ struct fc_host_attrs { u16 npiv_vports_inuse; /* work queues for rport state manipulation */ - char work_q_name[KOBJ_NAME_LEN]; + char work_q_name[20]; struct workqueue_struct *work_q; - char devloss_work_q_name[KOBJ_NAME_LEN]; + char devloss_work_q_name[20]; struct workqueue_struct *devloss_work_q; }; diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h index aab1eae2ec4c..8b6c91df4c7a 100644 --- a/include/scsi/scsi_transport_iscsi.h +++ b/include/scsi/scsi_transport_iscsi.h @@ -30,11 +30,11 @@ struct scsi_transport_template; struct iscsi_transport; +struct iscsi_endpoint; struct Scsi_Host; struct iscsi_cls_conn; struct iscsi_conn; -struct iscsi_cmd_task; -struct iscsi_mgmt_task; +struct iscsi_task; struct sockaddr; /** @@ -58,19 +58,22 @@ struct sockaddr; * @stop_conn: suspend/recover/terminate connection * @send_pdu: send iSCSI PDU, Login, Logout, NOP-Out, Reject, Text. * @session_recovery_timedout: notify LLD a block during recovery timed out - * @init_cmd_task: Initialize a iscsi_cmd_task and any internal structs. - * Called from queuecommand with session lock held. - * @init_mgmt_task: Initialize a iscsi_mgmt_task and any internal structs. - * Called from iscsi_conn_send_generic with xmitmutex. - * @xmit_cmd_task: Requests LLD to transfer cmd task. Returns 0 or the + * @init_task: Initialize a iscsi_task and any internal structs. + * When offloading the data path, this is called from + * queuecommand with the session lock, or from the + * iscsi_conn_send_pdu context with the session lock. + * When not offloading the data path, this is called + * from the scsi work queue without the session lock. + * @xmit_task Requests LLD to transfer cmd task. Returns 0 or the * the number of bytes transferred on success, and -Exyz - * value on error. - * @xmit_mgmt_task: Requests LLD to transfer mgmt task. Returns 0 or the - * the number of bytes transferred on success, and -Exyz - * value on error. - * @cleanup_cmd_task: requests LLD to fail cmd task. Called with xmitmutex - * and session->lock after the connection has been - * suspended and terminated during recovery. If called + * value on error. When offloading the data path, this + * is called from queuecommand with the session lock, or + * from the iscsi_conn_send_pdu context with the session + * lock. When not offloading the data path, this is called + * from the scsi work queue without the session lock. + * @cleanup_task: requests LLD to fail task. Called with session lock + * and after the connection has been suspended and + * terminated during recovery. If called * from abort task then connection is not suspended * or terminated but sk_callback_lock is held * @@ -83,17 +86,9 @@ struct iscsi_transport { /* LLD sets this to indicate what values it can export to sysfs */ uint64_t param_mask; uint64_t host_param_mask; - struct scsi_host_template *host_template; - /* LLD connection data size */ - int conndata_size; - /* LLD session data size */ - int sessiondata_size; - int max_lun; - unsigned int max_conn; - unsigned int max_cmd_len; - struct iscsi_cls_session *(*create_session) (struct iscsi_transport *it, - struct scsi_transport_template *t, uint16_t, uint16_t, - uint32_t sn, uint32_t *hn); + struct iscsi_cls_session *(*create_session) (struct iscsi_endpoint *ep, + uint16_t cmds_max, uint16_t qdepth, + uint32_t sn, uint32_t *hn); void (*destroy_session) (struct iscsi_cls_session *session); struct iscsi_cls_conn *(*create_conn) (struct iscsi_cls_session *sess, uint32_t cid); @@ -118,20 +113,15 @@ struct iscsi_transport { char *data, uint32_t data_size); void (*get_stats) (struct iscsi_cls_conn *conn, struct iscsi_stats *stats); - int (*init_cmd_task) (struct iscsi_cmd_task *ctask); - void (*init_mgmt_task) (struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask); - int (*xmit_cmd_task) (struct iscsi_conn *conn, - struct iscsi_cmd_task *ctask); - void (*cleanup_cmd_task) (struct iscsi_conn *conn, - struct iscsi_cmd_task *ctask); - int (*xmit_mgmt_task) (struct iscsi_conn *conn, - struct iscsi_mgmt_task *mtask); + int (*init_task) (struct iscsi_task *task); + int (*xmit_task) (struct iscsi_task *task); + void (*cleanup_task) (struct iscsi_conn *conn, + struct iscsi_task *task); void (*session_recovery_timedout) (struct iscsi_cls_session *session); - int (*ep_connect) (struct sockaddr *dst_addr, int non_blocking, - uint64_t *ep_handle); - int (*ep_poll) (uint64_t ep_handle, int timeout_ms); - void (*ep_disconnect) (uint64_t ep_handle); + struct iscsi_endpoint *(*ep_connect) (struct sockaddr *dst_addr, + int non_blocking); + int (*ep_poll) (struct iscsi_endpoint *ep, int timeout_ms); + void (*ep_disconnect) (struct iscsi_endpoint *ep); int (*tgt_dscvr) (struct Scsi_Host *shost, enum iscsi_tgt_dscvr type, uint32_t enable, struct sockaddr *dst_addr); }; @@ -172,9 +162,10 @@ enum { ISCSI_SESSION_FREE, }; +#define ISCSI_MAX_TARGET -1 + struct iscsi_cls_session { struct list_head sess_list; /* item in session_list */ - struct list_head host_list; struct iscsi_transport *transport; spinlock_t lock; struct work_struct block_work; @@ -186,7 +177,7 @@ struct iscsi_cls_session { int recovery_tmo; struct delayed_work recovery_work; - int target_id; + unsigned int target_id; int state; int sid; /* session id */ @@ -203,12 +194,20 @@ struct iscsi_cls_session { #define starget_to_session(_stgt) \ iscsi_dev_to_session(_stgt->dev.parent) -struct iscsi_host { - struct list_head sessions; +struct iscsi_cls_host { atomic_t nr_scans; struct mutex mutex; struct workqueue_struct *scan_workq; - char scan_workq_name[KOBJ_NAME_LEN]; + char scan_workq_name[20]; +}; + +extern void iscsi_host_for_each_session(struct Scsi_Host *shost, + void (*fn)(struct iscsi_cls_session *)); + +struct iscsi_endpoint { + void *dd_data; /* LLD private data */ + struct device dev; + unsigned int id; }; /* @@ -222,22 +221,26 @@ struct iscsi_host { extern int iscsi_session_chkready(struct iscsi_cls_session *session); extern struct iscsi_cls_session *iscsi_alloc_session(struct Scsi_Host *shost, - struct iscsi_transport *transport); + struct iscsi_transport *transport, int dd_size); extern int iscsi_add_session(struct iscsi_cls_session *session, unsigned int target_id); extern int iscsi_session_event(struct iscsi_cls_session *session, enum iscsi_uevent_e event); extern struct iscsi_cls_session *iscsi_create_session(struct Scsi_Host *shost, struct iscsi_transport *t, + int dd_size, unsigned int target_id); extern void iscsi_remove_session(struct iscsi_cls_session *session); extern void iscsi_free_session(struct iscsi_cls_session *session); extern int iscsi_destroy_session(struct iscsi_cls_session *session); extern struct iscsi_cls_conn *iscsi_create_conn(struct iscsi_cls_session *sess, - uint32_t cid); + int dd_size, uint32_t cid); extern int iscsi_destroy_conn(struct iscsi_cls_conn *conn); extern void iscsi_unblock_session(struct iscsi_cls_session *session); extern void iscsi_block_session(struct iscsi_cls_session *session); extern int iscsi_scan_finished(struct Scsi_Host *shost, unsigned long time); +extern struct iscsi_endpoint *iscsi_create_endpoint(int dd_size); +extern void iscsi_destroy_endpoint(struct iscsi_endpoint *ep); +extern struct iscsi_endpoint *iscsi_lookup_endpoint(u64 handle); #endif diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h index 049edc5e6461..9c309daf492b 100644 --- a/include/sound/ac97_codec.h +++ b/include/sound/ac97_codec.h @@ -505,6 +505,7 @@ struct snd_ac97 { unsigned short pcmreg[3]; // PCM registers unsigned short codec_cfg[3]; // CODEC_CFG bits unsigned char swap_mic_linein; // AD1986/AD1986A only + unsigned char lo_as_master; /* LO as master */ } ad18xx; unsigned int dev_flags; /* device specific */ } spec; diff --git a/include/sound/control.h b/include/sound/control.h index 3dc1291f52db..4721b4bba053 100644 --- a/include/sound/control.h +++ b/include/sound/control.h @@ -129,9 +129,6 @@ int snd_ctl_unregister_ioctl_compat(snd_kctl_ioctl_func_t fcn); #define snd_ctl_unregister_ioctl_compat(fcn) #endif -int snd_ctl_elem_read(struct snd_card *card, struct snd_ctl_elem_value *control); -int snd_ctl_elem_write(struct snd_card *card, struct snd_ctl_file *file, struct snd_ctl_elem_value *control); - static inline unsigned int snd_ctl_get_ioffnum(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id) { return id->numid - kctl->id.numid; diff --git a/include/sound/core.h b/include/sound/core.h index 695ee53488a3..558b96284bd2 100644 --- a/include/sound/core.h +++ b/include/sound/core.h @@ -412,13 +412,13 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...) #endif /* CONFIG_SND_DEBUG */ -#ifdef CONFIG_SND_DEBUG_DETECT +#ifdef CONFIG_SND_DEBUG_VERBOSE /** * snd_printdd - debug printk * @format: format string * * Works like snd_printk() for debugging purposes. - * Ignored when CONFIG_SND_DEBUG_DETECT is not set. + * Ignored when CONFIG_SND_DEBUG_VERBOSE is not set. */ #define snd_printdd(format, args...) snd_printk(format, ##args) #else @@ -442,7 +442,7 @@ struct snd_pci_quirk { unsigned short subvendor; /* PCI subvendor ID */ unsigned short subdevice; /* PCI subdevice ID */ int value; /* value */ -#ifdef CONFIG_SND_DEBUG_DETECT +#ifdef CONFIG_SND_DEBUG_VERBOSE const char *name; /* name of the device (optional) */ #endif }; @@ -450,7 +450,7 @@ struct snd_pci_quirk { #define _SND_PCI_QUIRK_ID(vend,dev) \ .subvendor = (vend), .subdevice = (dev) #define SND_PCI_QUIRK_ID(vend,dev) {_SND_PCI_QUIRK_ID(vend, dev)} -#ifdef CONFIG_SND_DEBUG_DETECT +#ifdef CONFIG_SND_DEBUG_VERBOSE #define SND_PCI_QUIRK(vend,dev,xname,val) \ {_SND_PCI_QUIRK_ID(vend, dev), .value = (val), .name = (xname)} #else diff --git a/include/sound/cs4231-regs.h b/include/sound/cs4231-regs.h index e8d1f3e31f9e..92647532c454 100644 --- a/include/sound/cs4231-regs.h +++ b/include/sound/cs4231-regs.h @@ -177,4 +177,12 @@ #define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ #define CS4236_VERSION 0x9c /* chip version and ID */ +/* definitions for extended registers - OPTI93X */ +#define OPTi931_AUX_LEFT_INPUT 0x10 +#define OPTi931_AUX_RIGHT_INPUT 0x11 +#define OPTi93X_MIC_LEFT_INPUT 0x14 +#define OPTi93X_MIC_RIGHT_INPUT 0x15 +#define OPTi93X_OUT_LEFT 0x16 +#define OPTi93X_OUT_RIGHT 0x17 + #endif /* __SOUND_CS4231_REGS_H */ diff --git a/include/sound/cs4231.h b/include/sound/cs4231.h index 66055d702aa3..f0785f9f4ae4 100644 --- a/include/sound/cs4231.h +++ b/include/sound/cs4231.h @@ -58,6 +58,7 @@ /* compatible, but clones */ #define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */ #define CS4231_HW_OPL3SA2 0x1101 /* OPL3-SA2 chip, similar to cs4231 */ +#define CS4231_HW_OPTI93X 0x1102 /* Opti 930/931/933 */ /* defines for codec.hwshare */ #define CS4231_HWSHARE_IRQ (1<<0) @@ -120,6 +121,8 @@ unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg); void snd_cs4231_mce_up(struct snd_cs4231 *chip); void snd_cs4231_mce_down(struct snd_cs4231 *chip); +void snd_cs4231_overrange(struct snd_cs4231 *chip); + irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id); const char *snd_cs4231_chip_id(struct snd_cs4231 *chip); diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h index 7b7b9b13b4dd..10ee28eac018 100644 --- a/include/sound/emu10k1.h +++ b/include/sound/emu10k1.h @@ -1670,6 +1670,7 @@ struct snd_emu_chip_details { unsigned char spi_dac; /* SPI interface for DAC */ unsigned char i2c_adc; /* I2C interface for ADC */ unsigned char adc_1361t; /* Use Philips 1361T ADC */ + unsigned char invert_shared_spdif; /* analog/digital switch inverted */ const char *driver; const char *name; const char *id; /* for backward compatibility - can be NULL if not needed */ diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index a105b01e06d5..f8223fae5804 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h @@ -193,6 +193,7 @@ struct snd_soc_dapm_widget; enum snd_soc_dapm_type; struct snd_soc_dapm_path; struct snd_soc_dapm_pin; +struct snd_soc_dapm_route; /* dapm controls */ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, @@ -205,17 +206,23 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); int snd_soc_dapm_new_control(struct snd_soc_codec *codec, const struct snd_soc_dapm_widget *widget); +int snd_soc_dapm_new_controls(struct snd_soc_codec *codec, + const struct snd_soc_dapm_widget *widget, + int num); /* dapm path setup */ -int snd_soc_dapm_connect_input(struct snd_soc_codec *codec, +int __deprecated snd_soc_dapm_connect_input(struct snd_soc_codec *codec, const char *sink_name, const char *control_name, const char *src_name); int snd_soc_dapm_new_widgets(struct snd_soc_codec *codec); void snd_soc_dapm_free(struct snd_soc_device *socdev); +int snd_soc_dapm_add_routes(struct snd_soc_codec *codec, + const struct snd_soc_dapm_route *route, int num); /* dapm events */ int snd_soc_dapm_stream_event(struct snd_soc_codec *codec, char *stream, int event); -int snd_soc_dapm_device_event(struct snd_soc_device *socdev, int event); +int snd_soc_dapm_set_bias_level(struct snd_soc_device *socdev, + enum snd_soc_bias_level level); /* dapm sys fs - used by the core */ int snd_soc_dapm_sys_add(struct device *dev); @@ -223,6 +230,8 @@ int snd_soc_dapm_sys_add(struct device *dev); /* dapm audio endpoint control */ int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec, char *pin, int status); +int snd_soc_dapm_get_endpoint_status(struct snd_soc_codec *codec, + char *pin); int snd_soc_dapm_sync_endpoints(struct snd_soc_codec *codec); /* dapm widget types */ @@ -245,6 +254,18 @@ enum snd_soc_dapm_type { snd_soc_dapm_post, /* machine specific post widget - exec last */ }; +/* + * DAPM audio route definition. + * + * Defines an audio route originating at source via control and finishing + * at sink. + */ +struct snd_soc_dapm_route { + const char *sink; + const char *control; + const char *source; +}; + /* dapm audio path between two widgets */ struct snd_soc_dapm_path { char *name; diff --git a/include/sound/soc.h b/include/sound/soc.h index d3c8c033dff8..340223a8f24c 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -73,6 +73,15 @@ .get = snd_soc_get_volsw_2r, .put = snd_soc_put_volsw_2r, \ .private_value = (reg_left) | ((shift) << 8) | \ ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) } +#define SOC_DOUBLE_S8_TLV(xname, reg, min, max, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_s8, .get = snd_soc_get_volsw_s8, \ + .put = snd_soc_put_volsw_s8, \ + .private_value = (reg) | (((signed char)max) << 16) | \ + (((signed char)min) << 24) } #define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, xtexts) \ { .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ .mask = xmask, .texts = xtexts } @@ -91,6 +100,15 @@ .info = snd_soc_info_volsw, \ .get = xhandler_get, .put = xhandler_put, \ .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) } +#define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmask, xinvert,\ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) } #define SOC_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_soc_info_bool_ext, \ @@ -103,6 +121,24 @@ .private_value = (unsigned long)&xenum } /* + * Bias levels + * + * @ON: Bias is fully on for audio playback and capture operations. + * @PREPARE: Prepare for audio operations. Called before DAPM switching for + * stream start and stop operations. + * @STANDBY: Low power standby state when no playback/capture operations are + * in progress. NOTE: The transition time between STANDBY and ON + * should be as fast as possible and no longer than 10ms. + * @OFF: Power Off. No restrictions on transition times. + */ +enum snd_soc_bias_level { + SND_SOC_BIAS_ON, + SND_SOC_BIAS_PREPARE, + SND_SOC_BIAS_STANDBY, + SND_SOC_BIAS_OFF, +}; + +/* * Digital Audio Interface (DAI) types */ #define SND_SOC_DAI_AC97 0x1 @@ -249,6 +285,12 @@ int snd_soc_get_volsw_2r(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); int snd_soc_put_volsw_2r(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int snd_soc_info_volsw_s8(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_get_volsw_s8(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_volsw_s8(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); /* SoC PCM stream information */ struct snd_soc_pcm_stream { @@ -272,9 +314,9 @@ struct snd_soc_ops { int (*trigger)(struct snd_pcm_substream *, int); }; -/* ASoC codec DAI ops */ -struct snd_soc_codec_ops { - /* codec DAI clocking configuration */ +/* ASoC DAI ops */ +struct snd_soc_dai_ops { + /* DAI clocking configuration */ int (*set_sysclk)(struct snd_soc_codec_dai *codec_dai, int clk_id, unsigned int freq, int dir); int (*set_pll)(struct snd_soc_codec_dai *codec_dai, @@ -282,7 +324,7 @@ struct snd_soc_codec_ops { int (*set_clkdiv)(struct snd_soc_codec_dai *codec_dai, int div_id, int div); - /* CPU DAI format configuration */ + /* DAI format configuration */ int (*set_fmt)(struct snd_soc_codec_dai *codec_dai, unsigned int fmt); int (*set_tdm_slot)(struct snd_soc_codec_dai *codec_dai, @@ -293,24 +335,6 @@ struct snd_soc_codec_ops { int (*digital_mute)(struct snd_soc_codec_dai *, int mute); }; -/* ASoC cpu DAI ops */ -struct snd_soc_cpu_ops { - /* CPU DAI clocking configuration */ - int (*set_sysclk)(struct snd_soc_cpu_dai *cpu_dai, - int clk_id, unsigned int freq, int dir); - int (*set_clkdiv)(struct snd_soc_cpu_dai *cpu_dai, - int div_id, int div); - int (*set_pll)(struct snd_soc_cpu_dai *cpu_dai, - int pll_id, unsigned int freq_in, unsigned int freq_out); - - /* CPU DAI format configuration */ - int (*set_fmt)(struct snd_soc_cpu_dai *cpu_dai, - unsigned int fmt); - int (*set_tdm_slot)(struct snd_soc_cpu_dai *cpu_dai, - unsigned int mask, int slots); - int (*set_tristate)(struct snd_soc_cpu_dai *, int tristate); -}; - /* SoC Codec DAI */ struct snd_soc_codec_dai { char *name; @@ -328,7 +352,7 @@ struct snd_soc_codec_dai { /* ops */ struct snd_soc_ops ops; - struct snd_soc_codec_ops dai_ops; + struct snd_soc_dai_ops dai_ops; /* DAI private data */ void *private_data; @@ -343,8 +367,10 @@ struct snd_soc_cpu_dai { unsigned char type; /* DAI callbacks */ - int (*probe)(struct platform_device *pdev); - void (*remove)(struct platform_device *pdev); + int (*probe)(struct platform_device *pdev, + struct snd_soc_cpu_dai *dai); + void (*remove)(struct platform_device *pdev, + struct snd_soc_cpu_dai *dai); int (*suspend)(struct platform_device *pdev, struct snd_soc_cpu_dai *cpu_dai); int (*resume)(struct platform_device *pdev, @@ -352,7 +378,7 @@ struct snd_soc_cpu_dai { /* ops */ struct snd_soc_ops ops; - struct snd_soc_cpu_ops dai_ops; + struct snd_soc_dai_ops dai_ops; /* DAI capabilities */ struct snd_soc_pcm_stream capture; @@ -374,7 +400,8 @@ struct snd_soc_codec { struct mutex mutex; /* callbacks */ - int (*dapm_event)(struct snd_soc_codec *codec, int event); + int (*set_bias_level)(struct snd_soc_codec *, + enum snd_soc_bias_level level); /* runtime */ struct snd_card *card; @@ -396,8 +423,8 @@ struct snd_soc_codec { /* dapm */ struct list_head dapm_widgets; struct list_head dapm_paths; - unsigned int dapm_state; - unsigned int suspend_dapm_state; + enum snd_soc_bias_level bias_level; + enum snd_soc_bias_level suspend_bias_level; struct delayed_work delayed_work; /* codec DAI's */ @@ -467,7 +494,8 @@ struct snd_soc_machine { int (*resume_post)(struct platform_device *pdev); /* callbacks */ - int (*dapm_event)(struct snd_soc_machine *, int event); + int (*set_bias_level)(struct snd_soc_machine *, + enum snd_soc_bias_level level); /* CPU <--> Codec DAI links */ struct snd_soc_dai_link *dai_link; @@ -482,6 +510,7 @@ struct snd_soc_device { struct snd_soc_codec *codec; struct snd_soc_codec_device *codec_dev; struct delayed_work delayed_work; + struct work_struct deferred_resume_work; void *codec_data; }; diff --git a/include/sound/uda1341.h b/include/sound/uda1341.h index 2e564bfb37fe..110d5dc3a2be 100644 --- a/include/sound/uda1341.h +++ b/include/sound/uda1341.h @@ -15,8 +15,6 @@ * features support */ -/* $Id: uda1341.h,v 1.8 2005/11/17 14:17:21 tiwai Exp $ */ - #define UDA1341_ALSA_NAME "snd-uda1341" /* diff --git a/include/sound/version.h b/include/sound/version.h index ed6fb2eb1eac..2474b8ee99f9 100644 --- a/include/sound/version.h +++ b/include/sound/version.h @@ -1,3 +1,3 @@ -/* include/version.h. Generated by alsa/ksync script. */ -#define CONFIG_SND_VERSION "1.0.16" +/* include/version.h */ +#define CONFIG_SND_VERSION "1.0.17rc1" #define CONFIG_SND_DATE "" diff --git a/include/xen/events.h b/include/xen/events.h index acd8e062c85f..67c4436554a9 100644 --- a/include/xen/events.h +++ b/include/xen/events.h @@ -32,6 +32,7 @@ void unbind_from_irqhandler(unsigned int irq, void *dev_id); void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector); int resend_irq_on_evtchn(unsigned int irq); +void rebind_evtchn_irq(int evtchn, int irq); static inline void notify_remote_via_evtchn(int port) { @@ -40,4 +41,7 @@ static inline void notify_remote_via_evtchn(int port) } extern void notify_remote_via_irq(int irq); + +extern void xen_irq_resume(void); + #endif /* _XEN_EVENTS_H */ diff --git a/include/xen/grant_table.h b/include/xen/grant_table.h index 466204846121..a40f1cd91be1 100644 --- a/include/xen/grant_table.h +++ b/include/xen/grant_table.h @@ -51,6 +51,9 @@ struct gnttab_free_callback { u16 count; }; +int gnttab_suspend(void); +int gnttab_resume(void); + int gnttab_grant_foreign_access(domid_t domid, unsigned long frame, int readonly); diff --git a/include/xen/hvc-console.h b/include/xen/hvc-console.h index 21c0ecfd786d..98b79bc404dd 100644 --- a/include/xen/hvc-console.h +++ b/include/xen/hvc-console.h @@ -3,4 +3,13 @@ extern struct console xenboot_console; +#ifdef CONFIG_HVC_XEN +void xen_console_resume(void); +#else +static inline void xen_console_resume(void) { } +#endif + +void xen_raw_console_write(const char *str); +void xen_raw_printk(const char *fmt, ...); + #endif /* XEN_HVC_CONSOLE_H */ diff --git a/include/xen/interface/elfnote.h b/include/xen/interface/elfnote.h index a64d3df5bd95..7a8262c375cc 100644 --- a/include/xen/interface/elfnote.h +++ b/include/xen/interface/elfnote.h @@ -120,6 +120,26 @@ */ #define XEN_ELFNOTE_BSD_SYMTAB 11 +/* + * The lowest address the hypervisor hole can begin at (numeric). + * + * This must not be set higher than HYPERVISOR_VIRT_START. Its presence + * also indicates to the hypervisor that the kernel can deal with the + * hole starting at a higher address. + */ +#define XEN_ELFNOTE_HV_START_LOW 12 + +/* + * List of maddr_t-sized mask/value pairs describing how to recognize + * (non-present) L1 page table entries carrying valid MFNs (numeric). + */ +#define XEN_ELFNOTE_L1_MFN_VALID 13 + +/* + * Whether or not the guest supports cooperative suspend cancellation. + */ +#define XEN_ELFNOTE_SUSPEND_CANCEL 14 + #endif /* __XEN_PUBLIC_ELFNOTE_H__ */ /* diff --git a/include/xen/interface/io/fbif.h b/include/xen/interface/io/fbif.h index 5a934dd7796d..974a51ed9165 100644 --- a/include/xen/interface/io/fbif.h +++ b/include/xen/interface/io/fbif.h @@ -49,11 +49,27 @@ struct xenfb_update { int32_t height; /* rect height */ }; +/* + * Framebuffer resize notification event + * Capable backend sets feature-resize in xenstore. + */ +#define XENFB_TYPE_RESIZE 3 + +struct xenfb_resize { + uint8_t type; /* XENFB_TYPE_RESIZE */ + int32_t width; /* width in pixels */ + int32_t height; /* height in pixels */ + int32_t stride; /* stride in bytes */ + int32_t depth; /* depth in bits */ + int32_t offset; /* start offset within framebuffer */ +}; + #define XENFB_OUT_EVENT_SIZE 40 union xenfb_out_event { uint8_t type; struct xenfb_update update; + struct xenfb_resize resize; char pad[XENFB_OUT_EVENT_SIZE]; }; @@ -105,15 +121,18 @@ struct xenfb_page { * Each directory page holds PAGE_SIZE / sizeof(*pd) * framebuffer pages, and can thus map up to PAGE_SIZE * * PAGE_SIZE / sizeof(*pd) bytes. With PAGE_SIZE == 4096 and - * sizeof(unsigned long) == 4, that's 4 Megs. Two directory - * pages should be enough for a while. + * sizeof(unsigned long) == 4/8, that's 4 Megs 32 bit and 2 + * Megs 64 bit. 256 directories give enough room for a 512 + * Meg framebuffer with a max resolution of 12,800x10,240. + * Should be enough for a while with room leftover for + * expansion. */ - unsigned long pd[2]; + unsigned long pd[256]; }; /* - * Wart: xenkbd needs to know resolution. Put it here until a better - * solution is found, but don't leak it to the backend. + * Wart: xenkbd needs to know default resolution. Put it here until a + * better solution is found, but don't leak it to the backend. */ #ifdef __KERNEL__ #define XENFB_WIDTH 800 diff --git a/include/xen/interface/io/kbdif.h b/include/xen/interface/io/kbdif.h index fb97f4284ffd..8066c7849fbe 100644 --- a/include/xen/interface/io/kbdif.h +++ b/include/xen/interface/io/kbdif.h @@ -49,6 +49,7 @@ struct xenkbd_motion { uint8_t type; /* XENKBD_TYPE_MOTION */ int32_t rel_x; /* relative X motion */ int32_t rel_y; /* relative Y motion */ + int32_t rel_z; /* relative Z motion (wheel) */ }; struct xenkbd_key { @@ -61,6 +62,7 @@ struct xenkbd_position { uint8_t type; /* XENKBD_TYPE_POS */ int32_t abs_x; /* absolute X position (in FB pixels) */ int32_t abs_y; /* absolute Y position (in FB pixels) */ + int32_t rel_z; /* relative Z motion (wheel) */ }; #define XENKBD_IN_EVENT_SIZE 40 diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h index da768469aa92..af36ead16817 100644 --- a/include/xen/interface/memory.h +++ b/include/xen/interface/memory.h @@ -29,7 +29,7 @@ struct xen_memory_reservation { * OUT: GMFN bases of extents that were allocated * (NB. This command also updates the mach_to_phys translation table) */ - ulong extent_start; + GUEST_HANDLE(ulong) extent_start; /* Number of extents, and size/alignment of each (2^extent_order pages). */ unsigned long nr_extents; @@ -50,6 +50,7 @@ struct xen_memory_reservation { domid_t domid; }; +DEFINE_GUEST_HANDLE_STRUCT(xen_memory_reservation); /* * Returns the maximum machine frame number of mapped RAM in this system. @@ -85,7 +86,7 @@ struct xen_machphys_mfn_list { * any large discontiguities in the machine address space, 2MB gaps in * the machphys table will be represented by an MFN base of zero. */ - ulong extent_start; + GUEST_HANDLE(ulong) extent_start; /* * Number of extents written to the above array. This will be smaller @@ -93,6 +94,7 @@ struct xen_machphys_mfn_list { */ unsigned int nr_extents; }; +DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mfn_list); /* * Sets the GPFN at which a particular page appears in the specified guest's @@ -115,6 +117,7 @@ struct xen_add_to_physmap { /* GPFN where the source mapping page should appear. */ unsigned long gpfn; }; +DEFINE_GUEST_HANDLE_STRUCT(xen_add_to_physmap); /* * Translates a list of domain-specific GPFNs into MFNs. Returns a -ve error @@ -129,13 +132,14 @@ struct xen_translate_gpfn_list { unsigned long nr_gpfns; /* List of GPFNs to translate. */ - ulong gpfn_list; + GUEST_HANDLE(ulong) gpfn_list; /* * Output list to contain MFN translations. May be the same as the input * list (in which case each input GPFN is overwritten with the output MFN). */ - ulong mfn_list; + GUEST_HANDLE(ulong) mfn_list; }; +DEFINE_GUEST_HANDLE_STRUCT(xen_translate_gpfn_list); #endif /* __XEN_PUBLIC_MEMORY_H__ */ diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h index 10ddfe0142d0..a706d6a78960 100644 --- a/include/xen/xen-ops.h +++ b/include/xen/xen-ops.h @@ -5,4 +5,10 @@ DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu); +void xen_pre_suspend(void); +void xen_post_suspend(int suspend_cancelled); + +void xen_mm_pin_all(void); +void xen_mm_unpin_all(void); + #endif /* INCLUDE_XEN_OPS_H */ |