| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-11-09 | riscv: Rearrange hwcap.h and cpufeature.h | Xiao Wang |
| 2023-11-07 | RISC-V: Probe misaligned access speed in parallel | Evan Green |
| 2023-11-05 | Merge patch series "Add support to handle misaligned accesses in S-mode" | Palmer Dabbelt |
| 2023-11-01 | riscv: report misaligned accesses emulation to hwprobe | Clément Léger |
| 2023-09-21 | RISC-V: Enable cbo.zero in usermode | Andrew Jones |
| 2023-09-01 | RISC-V: Probe for unaligned access speed | Evan Green |
| 2023-06-19 | RISC-V: Track ISA extensions per hart | Evan Green |
| 2023-04-18 | RISC-V: hwprobe: Support probing of misaligned access performance | Evan Green |
| 2023-04-18 | RISC-V: Move struct riscv_cpuinfo to new header | Evan Green |
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index : bcachefs.git | |
| Unnamed repository; edit this file 'description' to name the repository. | Kent Overstreet |
| summaryrefslogtreecommitdiff |