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Age
Commit message (
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Author
2023-02-21
RISC-V: fix ordering of Zbb extension
Heiko Stuebner
2023-01-31
RISC-V: add zbb support to string functions
Heiko Stuebner
2023-01-19
Merge patch series "Putting some basic order on isa extension lists"
Palmer Dabbelt
2023-01-17
RISC-V: resort all extensions in consistent orders
Conor Dooley
2023-01-17
RISC-V: clarify ISA string ordering rules in cpu.c
Conor Dooley
2022-12-14
Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
2022-10-27
RISC-V: Fix /proc/cpuinfo cpumask warning
Andrew Jones
2022-10-27
RISC-V: Cache SBI vendor values
Heiko Stuebner
2022-10-14
Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
2022-10-13
RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output
Palmer Dabbelt
2022-10-11
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Linus Torvalds
2022-10-06
RISC-V: Print SSTC in canonical order
Palmer Dabbelt
2022-10-03
RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output
Anup Patel
2022-10-02
RISC-V: Probe Svinval extension form ISA string
Mayuresh Chitale
2022-08-11
RISC-V: Add Sstc extension support
Palmer Dabbelt
2022-08-11
RISC-V: Enable sstc extension parsing from DT
Atish Patra
2022-08-11
arch/riscv: add Zihintpause support
Dao Lu
2022-08-10
riscv: implement Zicbom-based CMO instructions + the t-head variant
Palmer Dabbelt
2022-07-28
riscv: Add support for non-coherent devices using zicbom extension
Heiko Stuebner
2022-07-19
riscv: cpu: Add 64bit hartid support on RV64
Sunil V L
2022-05-21
riscv: Don't output a bogus mmu-type on a no MMU kernel
Niklas Cassel
2022-05-11
riscv: add RISC-V Svpbmt extension support
Heiko Stuebner
2022-03-31
riscv: cpu.c: don't use kernel-doc markers for comments
Randy Dunlap
2022-03-30
RISC-V: Fix a comment typo in riscv_of_parent_hartid()
Atish Patra
2022-03-21
perf: RISC-V: Add support for SBI PMU and Sscofpmf
Palmer Dabbelt
2022-03-21
RISC-V: Add sscofpmf extension support
Atish Patra
2022-03-17
RISC-V: Provide a fraemework for RISC-V ISA extensions
Palmer Dabbelt
2022-03-17
RISC-V: Improve /proc/cpuinfo output for ISA extensions
Atish Patra
2022-02-14
riscv: mm: Set sv57 on defaultly
Qinglin Pan
2022-01-19
riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo
Alexandre Ghiti
2021-10-20
riscv: Use of_get_cpu_hwid()
Rob Herring
2020-06-09
RISC-V: Rename and move plic_find_hart_id() to arch directory
Anup Patel
2019-10-28
RISC-V: Remove unsupported isa string info print
Atish Patra
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
Thomas Gleixner
2019-04-30
RISC-V: Add RISC-V specific arch_match_cpu_phys_id
Atish Patra
2019-03-04
RISC-V: Remove NR_CPUs check during hartid search from DT
Atish Patra
2019-02-11
riscv: treat cpu devicetree nodes without status as enabled
Johan Hovold
2019-02-11
riscv: fix riscv_of_processor_hartid() comment
Johan Hovold
2019-02-11
riscv: add missing newlines to printk messages
Johan Hovold
2018-12-21
RISC-V: Fix of_node_* refcount
Atish Patra
2018-11-20
RISC-V: recognize S/U mode bits in print_isa
Patrick Stählin
2018-10-22
RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo
Anup Patel
2018-10-22
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
2018-10-22
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Palmer Dabbelt
2018-10-22
RISC-V: Filter ISA and MMU values in cpuinfo
Palmer Dabbelt
2017-09-26
RISC-V: Init and Halt Code
Palmer Dabbelt