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Kent Overstreet
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path:
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/
drivers
/
clk
/
tegra
/
clk-pll.c
Age
Commit message (
Expand
)
Author
2021-05-31
clk: tegra: Don't allow zero clock rate for PLLs
Dmitry Osipenko
2021-05-31
clk: tegra: Ensure that PLLU configuration is applied properly
Dmitry Osipenko
2021-03-24
clk: tegra: Don't enable PLLE HW sequencer at init
JC Kuo
2020-09-21
clk: tegra: Always program PLL_E when enabled
Thierry Reding
2020-09-21
clk: tegra: Capitalization fixes
Thierry Reding
2020-07-27
clk: tegra: pll: Improve PLLM enable-state detection
Dmitry Osipenko
2020-05-12
clk: tegra: pll: Add pre/post rate-change hooks
Dmitry Osipenko
2019-11-11
clk: tegra: pll: Save and restore pll context
Sowjanya Komatineni
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Thomas Gleixner
2019-04-25
clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
Dmitry Osipenko
2019-04-19
clk: tegra: Don't enable already enabled PLLs
Dmitry Osipenko
2018-12-14
clk: tegra: Return the exact clock rate from clk_round_rate
Robert Yang
2018-03-12
clk: tegra: Fix pll_u rate configuration
Marcel Ziswiler
2017-08-23
clk: tegra: Fix T210 PLLRE registration
Alex Frid
2017-08-23
clk: tegra: Update T210 PLLSS (D2/DP) registration
Alex Frid
2017-08-23
clk: tegra: Re-factor T210 PLLX registration
Alex Frid
2017-08-23
clk: tegra: change post IDDQ release delay to 5us
Peter De Schrijver
2017-08-23
clk: tegra: Init cfg structure in _get_pll_mnp
Peter De Schrijver
2017-08-23
clk: tegra: Enable PLL_SS for Tegra210
Peter De Schrijver
2017-08-23
clk: tegra: fix SS control on PLL enable/disable
Peter De Schrijver
2017-03-20
clk: tegra: Rework pll_u
Peter De Schrijver
2016-06-30
clk: tegra: Initialize UTMI PLL when enabling PLLU
Andrew Bresticker
2016-04-28
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Rhyland Klein
2016-02-02
clk: tegra: Fix PLLE SS coefficients
Mark Kuo
2016-02-02
clk: tegra: Fix typos around clearing PLLE bits during enable
Rhyland Klein
2016-02-02
clk: tegra: Do not disable PLLE when under hardware control
Mark Kuo
2016-02-02
clk: tegra: pll: Fix potential sleeping-while-atomic
Andrew Bresticker
2015-12-17
clk: tegra: Read correct IDDQ register in PLL_SS registration
Bill Huang
2015-12-17
clk: tegra: Fix WARN_ON in PLL_RE registration
Bill Huang
2015-12-17
clk: tegra: pll: Fix issues with rates for VCO PLLs
Andrew Bresticker
2015-12-17
clk: tegra: Add support for Tegra210 clocks
Rhyland Klein
2015-12-17
clk: tegra: pll: Add logic for SS
Bill Huang
2015-12-17
clk: tegra: pll: Add dyn_ramp callback
Rhyland Klein
2015-12-17
clk: tegra: pll: Add Set_default logic
Bill Huang
2015-12-17
clk: tegra: pll: Adjust vco_min if SDM present
Bill Huang
2015-12-17
clk: tegra: pll: Add support for PLLMB for Tegra210
Rhyland Klein
2015-12-17
clk: tegra: pll: Add specialized logic for Tegra210
Rhyland Klein
2015-11-20
clk: tegra: pll: Update PLLM handling
Danny Huang
2015-11-20
clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate
Rhyland Klein
2015-11-20
clk: tegra: pll: Add code to handle if resets are supported by PLL
Bill Huang
2015-11-20
clk: tegra: pll: Add logic for out-of-table rates for T210
Rhyland Klein
2015-11-20
clk: tegra: pll: Add logic for handling SDM data
Rhyland Klein
2015-11-20
clk: tegra: pll: Don't unconditionally set LOCK flags
Rhyland Klein
2015-11-20
clk: tegra: pll: Update warning message
Rhyland Klein
2015-11-20
clk: tegra: pll: Simplify clk_enable_path
Rhyland Klein
2015-11-20
clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header
Rhyland Klein
2015-11-20
clk: tegra: Constify pdiv-to-hw mappings
Thierry Reding
2015-11-18
clk: tegra: Miscellaneous coding style cleanups
Thierry Reding
2015-08-24
clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
Stephen Boyd
2015-08-24
clk: tegra: Convert to clk_hw based provider APIs
Stephen Boyd
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