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path:
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drivers
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clk
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tegra
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clk-tegra210.c
Age
Commit message (
Expand
)
Author
2017-04-04
clk: tegra: Don't reset PLL-CX if it is already enabled
Jon Hunter
2017-04-04
clk: tegra: Add missing Tegra210 clocks
Peter De Schrijver
2017-03-20
clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on
Peter De Schrijver
2017-03-20
clk: tegra: Add SATA seq input control
Peter De Schrijver
2017-03-20
clk: tegra: Add Tegra210 special resets
Peter De Schrijver
2017-03-20
clk: tegra: Rework pll_u
Peter De Schrijver
2017-03-20
clk: tegra: Handle UTMIPLL IDDQ
Peter De Schrijver
2017-03-20
clk: tegra: Add aclk
Peter De Schrijver
2017-03-20
clk: tegra: Define Tegra210 DMIC clocks
Peter De Schrijver
2017-03-20
clk: tegra: Define Tegra210 DMIC sync clocks
Peter De Schrijver
2017-03-20
clk: tegra: Add CEC clock
Peter De Schrijver
2017-03-20
clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation
Peter De Schrijver
2017-03-20
clk: tegra: Don't warn for PLL defaults unnecessarily
Peter De Schrijver
2017-03-20
clk: tegra: Remove non-existing pll_m_out1 clock
Peter De Schrijver
2017-03-20
clk: tegra: Fix ISP clock modelling
Peter De Schrijver
2017-03-20
clk: tegra: Fix pll_a1 iddq register, add pll_a1
Peter De Schrijver
2016-06-30
clk: tegra: Initialize UTMI PLL when enabling PLLU
Andrew Bresticker
2016-06-23
clk: tegra: Micro-optimize Tegra210 clock setup
Thierry Reding
2016-06-23
clk: tegra: Make sor_safe the parent of dpaux and dpaux1
Thierry Reding
2016-06-17
clk: tegra: Enable sor1 and sor1_src on Tegra210
Thierry Reding
2016-06-17
clk: tegra: Disable spread spectrum on pll_d2
Thierry Reding
2016-06-10
clk: tegra: Fixup post dividers on Tegra210
Thierry Reding
2016-05-27
remove lots of IS_ERR_VALUE abuses
Arnd Bergmann
2016-04-28
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Rhyland Klein
2016-04-28
clk: tegra: Add sor_safe clock
Thierry Reding
2016-04-28
clk: tegra: dpaux and dpaux1 are fixed factor clocks
Thierry Reding
2016-04-28
clk: tegra: Add dpaux1 clock
Thierry Reding
2016-04-28
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
Andrew Bresticker
2016-02-02
clk: tegra: Fix sparse warnings for functions not declared as static
Jon Hunter
2016-02-02
clk: tegra: Fix sparse warning for pll_m
Jon Hunter
2016-02-02
clk: tegra: Use definition for pll_u override bit
Jon Hunter
2016-02-02
clk: tegra: Fix warning caused by pll_u failing to lock
Jon Hunter
2016-02-02
clk: tegra: Fix clock sources for Tegra210 EMC
Jon Hunter
2016-02-02
clk: tegra: Add the APB2APE audio clock on Tegra210
Jon Hunter
2016-02-02
clk: tegra: Fix pllx dyn step calculation
Rhyland Klein
2016-02-02
clk: tegra: Fix naming of MISC registers
Rhyland Klein
2016-01-25
clk: tegra: Remove improper flags for lock_enable
Rhyland Klein
2015-12-17
clk: tegra: Add support for Tegra210 clocks
Rhyland Klein