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path: root/drivers/clk
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2017-08-02Merge tag 'sunxi-clk-fixes-for-4.13' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull one Allwinner clock fix from Chen-Yu Tsai: One critical clock fix for sun5i (A10s/A13/R8) which enables propagation of clock rate changes from the "cpu" clock to it's parent PLL clock. This fixes cpufreq related crashes that have been observed on KernelCI with the C.H.I.P. and multi_v7_defconfig. * tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
2017-08-02Merge tag 'meson-clk-fixes-for-4.13-rc4-v2' of ↵Stephen Boyd
git://github.com/baylibre/clk-meson into clk-fixes Pull one Meson clock fix from Neil Armstrong * tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-meson: clk: meson: mpll: fix mpll0 fractional part ignored
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet
mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-01clk: sunxi-ng: Wait for lock when using fractional modeJernej Škrabec
Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be set before returning. Because of that, unstable clock may be used. Add a wait for lock in the helper function. Fixes: 89a3dfb78707 ("clk: sunxi-ng: Add fractional lib") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-01clk: sunxi-ng: Make fractional helper less chattyJernej Škrabec
ccu_frac_helper_read_rate() prints some info which is not really helpful except during debugging. Replace printk() with pr_debug(). Fixes: 89a3dfb78707 ("clk: sunxi-ng: Add fractional lib") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-01clk: sunxi-ng: multiplier: Fix fractional modeJernej Škrabec
Driver for multiplier clock is missing a call to ccu_frac_helper_enable() when fractional mode is selected. Add a call to ccu_frac_helper_enable(). Fixes: d77e8135b340 ("clk: sunxi-ng: multiplier: Add fractional support") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-01clk: sunxi-ng: Fix fractional mode for N-M clocksJernej Škrabec
N-M factor clock driver is missing a call to ccu_frac_helper_enable() when fractional mode is used. Additionally, most SoCs require that M factor must be set to 0 when fractional mode is used. Without this patch, clock keeps the old value and clk_set_rate() returns without error. Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support") CC: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-07-31clk: samsung: exynos5420: The EPLL rate table correctionsSylwester Nawrocki
This patch fixes values of the EPLL K coefficient and changes the EPLL output frequency values to match exactly what is possible to achieve with given M, P, S, K coefficients. This allows to avoid rounding errors and unexpected frequency being set with clk_set_rate(), due to recalc_rate returning different values than the PLL rate specified in the exynos5420_epll_24mhz_tbl table. E.g. this prevents a case where two consecutive clk_set_rate() calls with same argument result in different PLL output frequency. The PLL output frequencies have been calculated with formula: f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16 where fxtal = 24000000. Fixes: 9842452acd ("clk: samsung: exynos542x: Add EPLL rate table") Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-27clk: sunxi-ng: Fix header guard of ccu-sun8i-r.hMatthias Kaehlcke
Remove trailing extra underscore in definition of _CCU_SUN8I_R_H Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-07-24clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clockMaxime Ripard
The current CPU clock is missing the option to change the rate of its parents, leading to improper rates calculated by cpufreq, and eventually crashes. Cc: <stable@vger.kernel.org> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver") Reported-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21clk: qoriq: add pll clock to clock lookup tableYuantian Tang
Register each PLL and its division clocks to clock lookup table to facilitate the clock look up for clock consumer. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21clk: qoriq: add clock configuration for ls1088a socYuantian Tang
Clock on ls1088a chip takes primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-19clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang
Do the checks for accessing the SD divider table only when the rate gets updated, namely on init and set_rate. In all other cases, reuse the last value. This simplifies code, runtime load, and error reporting. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-19clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang
'rate' is not used, so we can use 'parent_rate' directly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-18Merge branch 'clk-fixes' into clk-nextStephen Boyd
* clk-fixes: clk: x86: Do not gate clocks enabled by the firmware clk: gemini: Fix reset regression
2017-07-18clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione
Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Darren Hart (VMware) <dvhart@infradead.org> Signed-off-by: Carlo Caione <carlo@endlessm.com> Fixes: 282a4e4ce5f9 ("platform/x86: Enable Atom PMC platform clocks") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: mmp: Drop unnecessary staticJulia Lawall
Drop static on a local variable, when the variable is initialized before any possible use. Thus, the static has no benefit. The semantic patch that fixes this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: moxart: remove unnecessary staticsGustavo A. R. Silva
Remove unnecessary static on local variable _base_ in both functions moxart_of_pll_clk_init() and moxart_of_apb_clk_init(). Such variables are initialized before being used, on every execution path throughout the mentioned functions. The statics have no benefit and, removing them reduce the code size. This issue was detected using Coccinelle and the following semantic patch: @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; In the following log you can see the difference in the code size. Also, notice that the bss segment is reduced down to zero. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 1724 384 128 2236 8bc drivers/clk/clk-moxart.o after: text data bss dec hex filename 1697 240 0 1937 791 drivers/clk/clk-moxart.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: qcom: clk-smd-rpm: Fix the reported rate of branchesGeorgi Djakov
As there is no way to actually query the hardware for the current clock rate, now racalc_rate() just returns the last rate that was previously set. But if the rate was not set yet, we return the bogus rate of 1000Hz. The branch clocks have the same rate as their parent, so in this case we just need to remove recalc_rate ops and then the core framework will handle this automagically. The round_rate() is unused, so remove it as well. Reported-by: Archit Taneja <architt@codeaurora.org> Fixes: 00f64b58874e ("clk: qcom: Add support for SMD-RPM Clocks") Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: mediatek: fixed static checker warning in clk_cpumux_get_parent callSean Wang
Fixed the signedness bug returning '(-22)' on the return type as u8 with removing the sanity checker in clk_cpumux_get_parent() since clk_cpumux_set_parent() always ensures validity in clk_cpumux_get_parent() got called. Fixes: 1e17de9049da ("clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: gemini: Fix reset regressionLinus Walleij
commit e2860e1f62f2 ("serial: 8250_of: Add reset support") introduced reset support for the 8250_of driver. However it unconditionally uses the assert/deassert pair to deassert reset on the device at probe and assert it at remove. This does not work with systems that have a self-deasserting reset controller, such as Gemini, that recently added a reset controller. As a result, the console will not probe on the Gemini with this message: Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled of_serial: probe of 42000000.serial failed with error -524 This (-ENOTSUPP) is the error code returned by the deassert() operation on self-deasserting reset controllers. To work around this, implement dummy .assert() and .deassert() operations in the Gemini combined clock and reset controller. This fixes the issue on this system. Cc: Joel Stanley <joel@jms.id.au> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-serial@vger.kernel.org Fixes: e2860e1f62f2 ("serial: 8250_of: Add reset support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V5925Vladimir Barinov
Update IDT VersaClock 5 driver to support 5P49V5925. This chip has only external clock input, four fractional dividers (FODs) and five clock outputs (four universal clock outputs and one reference clock output at OUT0_SELB_I2C). Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V6901Marek Vasut
Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901. This chip has two clock inputs (external XTAL or external CLKIN), four fractional dividers (FODs) and five clock outputs (four universal clock outputs and one reference clock output at OUT0_SELB_I2C). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> on Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Add support for the input frequency doublerMarek Vasut
The VersaClock 6 has an input frequency doubler between the input clock mux and the predivider. Add new capability flag and support for this frequency doubler block into the driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> on Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Split clock input mux and predividerMarek Vasut
Split the VC5 clock input mux and the predivider to more accurately model the hardware and fix the previously incorrect assumption that both the OUT_SEL_I2CB and the PLL are fed from the predivider. It is in fact the clock input mux output which is directly feeding the clock into the OUT_SEL_I2CB output, while the clock input mux output first passes through the predivider before it is fed into the PLL. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> on Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Configure the output buffer input mux on prepareMarek Vasut
The output buffer input mux can be configured in either of three states -- disabled, input from FOD, input from previous output. Once the .prepare() callback of the output buffer is called, the output buffer input mux must be set to either input from FOD or input from previous output, it cannot be set to Disabled anymore or the output won't work. Default to the input from FOD if the output buffer input mux was Disabled and the .prepare() was called on it. Note that we do not set the output buffer input mux back to Disabled in the .unprepare() callback as there is no obvious benefit of doing so. We disable the entire output buffer in the .unprepare() callback already. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Do not warn about disabled output buffer input muxesMarek Vasut
The output buffer input mux can be configured in either of three states -- disabled, input from FOD, input from previous output. If the output buffer input mux is set to disabled, the code in vc5_clk_out_get_parent() would consider this an invalid setting and warn about it, which is not necessarily the case. In case the output buffer input mux is disabled, default to input from FOD to have some parent and don't print the warning. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Fix trivial typoMarek Vasut
Fix trivial typo in vc5_clk_out_unprepare() , s/Enable/Disable/ . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Prevent division by zero on unconfigured outputsMarek Vasut
In case the initial values of the FOD registers are not configured in the OTP or by the bootloader, it is possible that the FOD registers will contain zeroes. The code in vc5_fod_recalc_rate() immediately feeds the FOD divider value obtained from the FOD registers into the div64_u64() and if the FOD divider value is zero, triggers division by zero exception. Check if the FOD divider value is zero and return the frequency of the FOD output as 0 Hz if it is so. This prevents the division by zero exception. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: axs10x: introduce AXS10X pll driverEugeniy Paltsev
AXS10X boards manages it's clocks using various PLLs. These PLL has same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the following devices: * ARC core on AXC CPU tiles. * ARC PGU on ARC SDP Mainboard. and more to come later. By this patch we add support for two plls (arc core pll and pgu pll), so we had to use two different init types: CLK_OF_DECLARE for arc core pll and regular probing for pgu pll. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Signed-off-by: Jose Abreu <joabreu@synopsys.com> [sboyd@codeaurora.org: Silence dubious !x & y sparse warning, make of_axs10x_pll_clk_setup() unregister clk on failure] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: renesas: Allow compile-testing of all (sub)driversGeert Uytterhoeven
Enable compile-testing of the remaining clock drivers and subdrivers, now dummies are available for of_clk_get_from_provider(), of_device_compatible_match(), and rcar_rst_read_mode_pins(), and the CPG/MSSR driver core has been converted from of_match_node() to of_device_get_match_data(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocksGeert Uytterhoeven
Add the module clocks for the Image Renderer Light (SRAM) Extended 3 (IMR-LX3/LSX3) Distortion Correction Engines on R-Car V2H. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17clk: renesas: div6: Document fields used for parent selectionGeert Uytterhoeven
Add the missing documentation for the fields in struct div6_clock related to parent selection for DIV6 clocks with selectable parents, as found in R/SH-Mobile SoCs. Fixes: c6d67fb037f4eaaf ("clk: shmobile: div6: support selectable-input clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-15Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds
Pull MIPS updates from Ralf Baechle: "Boston platform support: - Document DT bindings - Add CLK driver for board clocks CM: - Avoid per-core locking with CM3 & higher - WARN on attempt to lock invalid VP, not BUG CPS: - Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 - Prevent multi-core with dcache aliasing - Handle cores not powering down more gracefully - Handle spurious VP starts more gracefully DSP: - Add lwx & lhx missaligned access support eBPF: - Add MIPS support along with many supporting change to add the required infrastructure Generic arch code: - Misc sysmips MIPS_ATOMIC_SET fixes - Drop duplicate HAVE_SYSCALL_TRACEPOINTS - Negate error syscall return in trace - Correct forced syscall errors - Traced negative syscalls should return -ENOSYS - Allow samples/bpf/tracex5 to access syscall arguments for sane traces - Cleanup from old Kconfig options in defconfigs - Fix PREF instruction usage by memcpy for MIPS R6 - Fix various special cases in the FPU eulation - Fix some special cases in MIPS16e2 support - Fix MIPS I ISA /proc/cpuinfo reporting - Sort MIPS Kconfig alphabetically - Fix minimum alignment requirement of IRQ stack as required by ABI / GCC - Fix special cases in the module loader - Perform post-DMA cache flushes on systems with MAARs - Probe the I6500 CPU - Cleanup cmpxchg and add support for 1 and 2 byte operations - Use queued read/write locks (qrwlock) - Use queued spinlocks (qspinlock) - Add CPU shared FTLB feature detection - Handle tlbex-tlbp race condition - Allow storing pgd in C0_CONTEXT for MIPSr6 - Use current_cpu_type() in m4kc_tlbp_war() - Support Boston in the generic kernel Generic platform: - yamon-dt: Pull YAMON DT shim code out of SEAD-3 board - yamon-dt: Support > 256MB of RAM - yamon-dt: Use serial* rather than uart* aliases - Abstract FDT fixup application - Set RTC_ALWAYS_BCD to 0 - Add a MAINTAINERS entry core kernel: - qspinlock.c: include linux/prefetch.h Loongson 3: - Add support Perf: - Add I6500 support SEAD-3: - Remove GIC timer from DT - Set interrupt-parent per-device, not at root node - Fix GIC interrupt specifiers SMP: - Skip IPI setup if we only have a single CPU VDSO: - Make comment match reality - Improvements to time code in VDSO" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits) locking/qspinlock: Include linux/prefetch.h MIPS: Fix MIPS I ISA /proc/cpuinfo reporting MIPS: Fix minimum alignment requirement of IRQ stack MIPS: generic: Support MIPS Boston development boards MIPS: DTS: img: Don't attempt to build-in all .dtb files clk: boston: Add a driver for MIPS Boston board clocks dt-bindings: Document img,boston-clock binding MIPS: Traced negative syscalls should return -ENOSYS MIPS: Correct forced syscall errors MIPS: Negate error syscall return in trace MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select MIPS16e2: Provide feature overrides for non-MIPS16 systems MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions MIPS: MIPS16e2: Identify ASE presence MIPS: VDSO: Fix a mismatch between comment and preprocessor constant MIPS: VDSO: Add implementation of gettimeofday() fallback MIPS: VDSO: Add implementation of clock_gettime() fallback MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() MIPS: Use current_cpu_type() in m4kc_tlbp_war() ...
2017-07-11clk: boston: Add a driver for MIPS Boston board clocksPaul Burton
Add a driver for the clocks provided by the MIPS Boston board from Imagination Technologies. 2 clocks are provided - the system clock & the CPU clock - and each is a simple fixed rate clock whose frequency can be determined by reading a register provided by the board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-06-29clk: gemini: Read status before using the valueJoel Stanley
The probe does a shift and mask of val without having read it from the hardware. Fixes: 846423f96721 ("clk: Add Gemini SoC clock controller") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-29clk: scpi: error when clock fails to registerJerome Brunet
Current implementation of scpi_clk_add just print a warning when clock fails to register but then keep going as if nothing happened. The provider is then registered with bogus data. This may latter lead to an Oops in __clk_create_clk when hlist_add_head(&clk->clks_node, &hw->core->clks) is called. This patch fixes the issue and errors if a clock fails to register. Fixes: cd52c2a4b5c4 ("clk: add support for clocks provided by SCP(System Control Processor)") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-29clk: at91: Add sama5d2 suspend/resumeAlexandre Belloni
On sama5d2, VDD core maybe be cut while in suspend. This means registers will be lost. Ensure they are saved and restored properly. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-22clk: keystone: TI_SCI_PROTOCOL is needed for clk driverArnd Bergmann
CONFIG_COMPILE_TEST allows building a configuration without TI_SCI_PROTOCOL, which then fails to link: drivers/clk/keystone/sci-clk.o: In function `ti_sci_clk_probe': sci-clk.c:(.text.ti_sci_clk_probe+0x4c): undefined reference to `devm_ti_sci_get_handle' This makes it a hard dependency. Right now, that means we can't actually compile-test the driver unless ARCH_KEYSTONE is set as well, but we can fix that by allowing TI_MESSAGE_MANAGER to be selected for COMPILE_TEST as well. Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-22clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLLKrzysztof Kozlowski
Similarly to commit f1e9203e2366 ("clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated") for Exynos5420, the Exynos4412 also requires that EPLL is not disabled. Otherwise any access to MAUDIO block will silently halt. This was not visible before because EPLL on Exynos4 could not be disabled before commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks"). After this commit, on Odroid U3 board one can see silent hang, usually with last (but unrelated) messages: [ 2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0 [ 2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci [ 2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653) Mark Exynos4 variant as also needed EPLL to be enabled all the time. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: uniphier: provide NAND controller clock rateMasahiro Yamada
This allows the NAND driver to get the clock rate via clk_get_rate(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue
Add usb2 clocks for hi3798cv200 SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: Add Gemini SoC clock controllerLinus Walleij
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [sboyd@codeaurora.org: Fix devm_ioremap_resource() return value checking] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: iproc: Remove __init marking on iproc_pll_clk_setup()Stephen Boyd
Now that this function is called from driver probe routines, it needs to drop the __init marking because it isn't just called from init code. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Cc: Anup Patel <anup.patel@broadcom.com> Cc: Ray Jui <ray.jui@broadcom.com> Cc: Scott Branden <scott.branden@broadcom.com> Fixes: 654cdd3229cd ("clk: bcm: Add clocks for Stingray SOC") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: bcm: Add clocks for Stingray SOCSandeep Tripathy
This patch adds support for Stingray clocks in iproc ccf. The Stingray SOC has various plls based on iproc pll architecture. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: export cpu multiplexer clock for MT8173 SoCsSean Wang
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't workSean Wang
This patch adds CPU multiplexer clocks which are essential for Mediatek cpufreq driver. It would use the CPU clock multiplexer to switch to the intermediate clock source temporarily and then wait for the primary clock changing getting stable. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: renesas: cpg-mssr: Use of_device_get_match_data() helperGeert Uytterhoeven
If CONFIG_OF=n: drivers/clk/renesas/renesas-cpg-mssr.c: In function ‘cpg_mssr_probe’: drivers/clk/renesas/renesas-cpg-mssr.c:702: warning: dereferencing ‘void *’ pointer drivers/clk/renesas/renesas-cpg-mssr.c:702: error: request for member ‘data’ in something not a structure or union To fix this, use the of_device_get_match_data() helper, for which a dummy version is provided if CONFIG_OF=n. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-04 21:51:51 +0000