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path: root/drivers/gpu/drm/amd/display/dc
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2018-11-07drm/amdgpu/display/dce11: only enable FBC when selectedAlex Deucher
Causes a black screen on a Stoney laptop. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108577 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-07drm/amdgpu/display/dc: add FBC to dc_configAlex Deucher
Add FBC to the list of features that can be enabled from the DM. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-07drm/amdgpu/display: check if fbc is available in set_static_screen_control (v2)Alex Deucher
The value is dependent on whether fbc is available. v2: only check if num_pipes is valid Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06drm/amd/display: Fix misleading buffer informationShaokun Zhang
RETIMER_REDRIVER_INFO shows the buffer as a decimal value with a '0x' prefix, which is somewhat misleading. Fix it to print hexadecimal, as was intended. Fixes: 2f14bc89("drm/amd/display: add retimer log for HWQ tuning use.") Cc: Charlene Liu <charlene.liu@amd.com> Cc: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Add condition to sync eDP SW status and HW statusLewis Huang
[Why] Need to disable EDP backlight when enter S4 with EDP only and resume from S4 with secondary only. [How] Align the real hw and sw state via vBios scratch register in function enable_accelerated_mode when resume from S4. Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Remove the check to see if pp_display_cfg is changedFatemeh Darbehani
[Why] When going to full-screen mode commit_planes_for_stream tries to decrease dcf_deep_sleep value, but safe_to_lower is false, so we don't send the new value to SMU but dc context gets updated. Later when dc_post_update_surfaces_to_stream tries to lower dcf_ds when safe_to_lower is true, this check prevents the message from being sent. [How] Remove the check that compares new value with what is stored in dc_context. This check is not necessary as dcn1_update_clocks already checks if the value is different from the current dcf_dp value. Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: remove CRTC_3D_STRUCTURE_V_UPDATE_MODE bit programming.Charlene Liu
[Description] This is based on HW programming guide update. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Expose target backlight levelAnthony Koo
[Why] DM may want to understand any backlight optimizations applied, so DM needs a way to query from the HW both the real current backlight, which may be value during transition. And also target backlight, which may be after some backlight optimizations applied. [How] Add interface to query current and target backlight levels Target level may indicate backlight level after backlight optimization and reductions are applied. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: fix mirror rotation scaling mathDmytro Laktyushkin
Curretly dc will incorrectly calculate viewport when there is rotation or mirror being applied Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Su Chung <Su.Chung@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part4Fatemeh Darbehani
[Why] In DCN we want direct DC to SMU calls, with minimal interference from pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in DC and shared across different OS's. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 4: Change clock units so they match the values PPLib sends to SMU. Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Remove program_csc_matrixKrunoslav Kovac
[Why] On DCN1/DCE, There are two functions programming OCSC: program_csc_matrix and program_output_csc. They do the same thing. [How] Consolidate to use only program_output_csc. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Fix some backlight variable stylingAnthony Koo
variableNamingsLikeSo aren't to convention. use_this_instead. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Expand dc to use 16.16 bit backlightAnthony Koo
[Why] We want to increase precision for backlight setting. But DC interface takes 8 bit backlight level value only. [How] DMCU already takes 16 bit backlight level. Expand the DC interface to take 16.16 bit value. Max 32 bit backlight value (0xFFFF) will represent max backlight (100%) Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Remove some old TODO'sEric Bernstein
They are no longer relevant Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: 3.2.04Steven Chiu
Signed-off-by: Steven Chiu <steven.chiu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Fix up coverity issuesAric Cyr
[Why] Coverity found various high-impact issues that need resolving. [How] Fix some buffer overruns and uninitialized variables. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: remove interlace scaling adjustmentDmytro Laktyushkin
We do not need to adjust surface scaling when p2i is enabled and we do not support interlaced timing otherwise Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Add missing pipes registers for VGA enable/disableNevenko Stupar
Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: fix dml max voltage stateDmytro Laktyushkin
Gabe's formula sometimes uses values from non-existent 'unsupported' state to do validation. This change adds this extra state so validation can work correctly. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: 3.2.03SivapiriyanKumarasamy
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Set gamma not working on MPO planesKrunoslav Kovac
[Why] Set gamma not working on certain planes in MPO configuration Root cause is that video format (YUV-420) isn't allowed for IGAM where gamma is applied. Fix is not easy though: 1. allowing will not work because IGAM is before ICSC so RGB gamma would be applied on YUV pixels. 2. Moving OS gamma to DGAM or RGAM resulted in weird artifacts. Ultimately the root cause for these artifacts was due to handling end points and the fact that YUV->RGB conversion will frequently "overshoot" FP 1.0 value. DCE has a single end point and slope, so we would take max. In nightlight mode, blue channel is reduced, sometimes to flat 0 line, but red is virtually unchanged. Any "overshot" in blue will be clipped to 1 (max R,G,B) instead of max blue value. [How] Fortunately, this can be fixed on DCN where we have end point and slope for all three color channels. We cannot fix this problem on DCE. Other things fixed: - switch (back) to using RGAM for OS gamma instead of IGAM - add coeffs for 709 YUV->RGB (we used RGB->YUV for both conversions) - switch color temperature method to scaled bradford - otherwise we would have clipping problems that caused us to switch to IGAM for OS gamma in the first place. - comments and some minor improvements - there are some more issues but they will be addressed in separate commits. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Check if hubp function hooks exist before calling themCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part3Fatemeh Darbehani
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Separate the set_hard_min_fclk_by_freq message from the SMU messages that are sent as part of pp_rv_set_display_requirement. directly notify min dcfclk to smu part 2 Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Remove stream_res tg null check in commit planesSivapiriyanKumarasamy
[Why] TG in pipe_ctx stream resource is not null where used in commit_planes_do_stream_update since it is assigned the same time the stream is set in pipe_ctx - when the pipe is acquired. This null check produced a static code analysis warning and should be removed to avoid similar unnecessary checks in the future. [How] Remove the null check. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: rename cstate_pstate_watermarks_st1Bhawanpreet Lakha
cstate_pstate_watermarks_st1 -> cstate_pstate_watermarks_st Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: explicit uint64_t castingBhawanpreet Lakha
explicitly cast uint64_t in div64_u64_rem() Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: dc 3.2.02SivapiriyanKumarasamy
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: add dccg blockDmytro Laktyushkin
This adds the hw block as well as hooks up dppclk dto programming Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: rename dccg to clk_mgrDmytro Laktyushkin
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part2Fatemeh Darbehani
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 2: Separate set_min_deep_sleep_dcfclk message from the SMU messages that are sent as part of dm_pp_apply_clock_for_voltage_request. Directly notify min dcfclk to smu Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part1Fatemeh Darbehani
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 1: Separate set_min_deep_Sleep_dcfclk message from the SMU messages that are sent as part of dcn10_pplib_apply_display_requirements. Notify deep sleep dcfclk to smu directly Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Add link encoder dp_ycbcr420_supported feature flagEric Bernstein
[Why] Need separate feature flag for DP 4:2:0 support, since existing flag is used for HDMI [How] Added dp_ycbcr420_supported to struct encoder_feature_support Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: fix report display count logicEric Yang
[Why] Previous logic to update display count in commit_planes_do_stream_update doesn't cover all cases. [How] Update display count as part of clock updates. Count virtual stream as active to work around headless situation. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: expose hwseq functions and add registersNevenko Stupar
Make these functions non static and define registers for future use is_lower_pipe_tree_visible(); is_upper_pipe_tree_visible(); is_pipe_tree_visible(); dcn10_program_pte_vm(); set_hdr_multiplier(); update_dchubp_dpp() find_top_pipe_for_stream() Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: initialize dc_transfer_func->ctxDavid Francis
[Why] dc_transfer_func structs were being passed around with a null pointer, waiting for unsuspecting programmers to dereference it. [How] Initialize it Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Add support for Freesync 2 HDR and Content to Display MappingSivapiriyanKumarasamy
[Why] Freesync 2 HDR and support for HDR content outside the range of the HDR display require implementation on Dal 3 to better match Dal2. [How] Add support for Freesync HDR and mapping of source content to display ranges for better representation of HDR content. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: split dccg clock manager into asic foldersDmytro Laktyushkin
Currently dccg contains code related to every dcn revision in a single file. This change splits out the dcn parts of code into correct folders Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: clean up base dccg structDmytro Laktyushkin
Move things not accessed outside dccg block into dce specific struct Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: remove safe_to_lower flag from dc, use 2 functions insteadDmytro Laktyushkin
This is done to keep things more readable, avoids a true/false flag in dc interface layer. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: move pplib/smu notification to dccg blockDmytro Laktyushkin
This is done to clear up the clock programming sequence since the only time we need to notify pplib is after clock update. This also renames the clk block to dccg, at the moment this block contains both clock management and dccg functionality. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: handle max_vstartup larger than vblank_endDmytro Laktyushkin
When vstartup is larger than vblank end we need to set v_fp2 to allow for this early start Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: dc 3.2.01Fatemeh Darbehani
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-02Merge tag 'drm-next-2018-11-02' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
Pull drm fixes from Dave Airlie: "Pretty much a normal fixes pull pre-rc1, mostly amdgpu fixes, one i915 link training regression fix, and a couple of minor panel/bridge fixes and a panel quirk" * tag 'drm-next-2018-11-02' of git://anongit.freedesktop.org/drm/drm: (37 commits) drm/amdgpu: revert "enable gfxoff in non-sriov and stutter mode by default" drm/amd/pp: Print warning if od_sclk/mclk out of range drm/amd/pp: Fix pp_sclk/mclk_od not work on Vega10 drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7 drm/amd/powerplay: no MGPU fan boost enablement on DPM disabled drm/amdgpu: Fix skipping hangged job reset during gpu recover. drm/amd/powerplay: revise Vega20 pptable version check drm/amd/display: set backlight level limit to 1 drm/panel: simple: Innolux TV123WAM is actually P120ZDG-BF1 dt-bindings: drm/panel: simple: Innolux TV123WAM is actually P120ZDG-BF1 drm/bridge: ti-sn65dsi86: Remove the mystery delay drm/panel: simple: Add "no-hpd" delay for Innolux TV123WAM drm/panel: simple: Support panels with HPD where HPD isn't connected dt-bindings: drm/panel: simple: Add no-hpd property drm/edid: Add 6 bpc quirk for BOE panel. drm/amdgpu: fix reporting of failed msg sent to SMU (v2) drm/amdgpu: Fix compute ring 1.0.0 failure after reset drm/amdgpu: fix VM leaf walking drm/amdgpu: fix amdgpu_vm_fini drm/amd/powerplay: commonize the API for retrieving current clocks ...
2018-11-01Merge branch 'work.afs' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs Pull AFS updates from Al Viro: "AFS series, with some iov_iter bits included" * 'work.afs' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: (26 commits) missing bits of "iov_iter: Separate type from direction and use accessor functions" afs: Probe multiple fileservers simultaneously afs: Fix callback handling afs: Eliminate the address pointer from the address list cursor afs: Allow dumping of server cursor on operation failure afs: Implement YFS support in the fs client afs: Expand data structure fields to support YFS afs: Get the target vnode in afs_rmdir() and get a callback on it afs: Calc callback expiry in op reply delivery afs: Fix FS.FetchStatus delivery from updating wrong vnode afs: Implement the YFS cache manager service afs: Remove callback details from afs_callback_break struct afs: Commit the status on a new file/dir/symlink afs: Increase to 64-bit volume ID and 96-bit vnode ID for YFS afs: Don't invoke the server to read data beyond EOF afs: Add a couple of tracepoints to log I/O errors afs: Handle EIO from delivery function afs: Fix TTL on VL server and address lists afs: Implement VL server rotation afs: Improve FS server rotation error handling ...
2018-10-24drm/amd/display: Disable 4k 60 HDMI on DCE11David Francis
[Why] Carrizo and Stoney have severe corruption when trying to power 4k 60 monitors over HDMI connectors that support 4k 60. Carrizo and Stoney require retimers and redrivers to support 4k 60 over HDMI. This driver does not currently support these. Thus, 4k 60 HDMI (and all other modes requiring over 300MHz) should be disabled. [How] Reduce the dce11 HDMI pixel clock cap to 300000kHz. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-24amd-gpu: Don't undefine READ and WRITEDavid Howells
Remove the undefinition of READ and WRITE because these constants may be used elsewhere in subsequently included header files, thus breaking them. These constants don't actually appear to be used in the driver, so the undefinition seems pointless. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: David Howells <dhowells@redhat.com>
2018-10-10drm/amd/display: RV2 DP MST 2nd display within daisy chain not light upHersen Wu
RV2 resource is limit to 3 pipes. Limitation should apply to all HW blocks instead of front pipe. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10drm/amd/display: Fix warning storm on Raven2Roman Li
[Why] Wrong index for pstate debug test register [How] Add correct index value for dcn1_01 in hubbub1_construct() Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amd/display: Use proper enums in process_channel_replyNathan Chancellor
Clang warns when one enumerated type is implicitly converted to another. drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:315:19: warning: implicit conversion from enumeration type 'enum aux_channel_operation_result' to different enumeration type 'enum aux_transaction_reply' [-Wenum-conversion] reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/i2caux/dce110/aux_engine_dce110.c:349:19: warning: implicit conversion from enumeration type 'enum aux_channel_operation_result' to different enumeration type 'enum aux_transaction_reply' [-Wenum-conversion] reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The current enum is incorrect, it should be from aux_transaction_reply, so use AUX_TRANSACTION_REPLY_HPD_DISCON. Reported-by: Nick Desaulniers <ndesaulniers@google.com> Suggested-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09drm/amd/display: Raise dispclk value for dce_update_clocksNicholas Kazlauskas
[Why] The DISPCLK value was previously requested to be 15% higher for all ASICS that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and dce110 set_bandwidth this was removed for power saving considerations. This changed caused corruption under certain display configurations. Originally thought to be Vega specific, it was also observed on Polaris. [How] The 15% is brought back but its placement differs from the original patch. This boost should only be enable while DFS bypass is inactive. This (like the Vega patch) is also a workaround that should be removed after the root cause is identified. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-08-03 04:10:31 +0000