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intel_runtime_pm.c
Age
Commit message (
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Author
2015-11-07
Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/...
Dave Airlie
2015-11-06
drm/i915/skl: disable display side power well support for now
Imre Deak
2015-10-20
Merge tag 'drm-intel-next-2015-10-10' of git://anongit.freedesktop.org/drm-in...
Dave Airlie
2015-10-16
Merge commit '06d1ee32a4d25356a710b49d5e95dbdd68bdf505' of git://git.kernel.o...
Dave Airlie
2015-10-06
drm/i915: Skip CHV PHY asserts until PHY has been fully reset
Ville Syrjälä
2015-09-30
drm/i915: fixup runtime PM handling v2
Jesse Barnes
2015-09-30
drm/i915/skl: Block disable call for pw1 if dmc firmware is present.
Animesh Manna
2015-09-28
drm/i915/skl: Don't call intel_prepare_ddi when encoder list isn't yet initia...
Rodrigo Vivi
2015-09-14
drm/i915: make CSR firmware messages less verbose
Jesse Barnes
2015-09-02
Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
Daniel Vetter
2015-09-01
drm/i915: Add CHV PHY LDO power sanity checks
Ville Syrjälä
2015-09-01
drm/i915: Add some CHV DPIO lane power state asserts
Ville Syrjälä
2015-08-31
drm/i915/skl: Adding DDI_E power well domain
Xiong Zhang
2015-08-26
drm/i915: Force CL2 off in CHV x1 PHY
Ville Syrjälä
2015-08-26
drm/i915: Enable DPIO SUS clock gating on CHV
Ville Syrjälä
2015-08-26
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Ville Syrjälä
2015-08-26
drm/i915: Implement PHY lane power gating for CHV
Ville Syrjälä
2015-08-26
drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
Ville Syrjälä
2015-08-26
drm/i915: Add locking around chv_phy_control_init()
Ville Syrjälä
2015-08-05
drm/i915: Extract a intel_power_well_disable() function
Damien Lespiau
2015-08-05
drm/i915: Extract a intel_power_well_enable() function
Damien Lespiau
2015-07-13
drm/i915: Refactor VLV display power well init/deinit
Ville Syrjälä
2015-07-13
drm/i915: Simplify CHV pipe A power well code
Ville Syrjälä
2015-07-13
drm/i915: Apply OCD to VLV/CHV DPLL defines
Ville Syrjälä
2015-07-13
drm/i915: Keep GMCH DPLL VGA mode always disabled
Ville Syrjälä
2015-05-28
drm/i915: Throw out WIP CHV power well definitions
Ville Syrjälä
2015-05-28
drm/i915: Use the default 600ns LDO programming sequence delay
Ville Syrjälä
2015-05-20
drm/i915: Fix typo in intel_runtime_pm.c
Masanari Iida
2015-05-08
Revert "drm/i915: Hack to tie both common lanes together on chv"
Ville Syrjälä
2015-05-08
drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
Ville Syrjälä
2015-05-08
drm/i915/skl: Make the Misc I/O power well part of the PLLS domain
Damien Lespiau
2015-05-08
drm/i915/skl: Add the INIT power domain to the MISC I/O power well
Damien Lespiau
2015-05-08
drm/i915/skl: Assert the requirements to enter or exit DC6.
Suketu Shah
2015-05-08
Implement enable/disable for Display C6 state
A.Sunil Kamath
2015-05-08
drm/i915/skl: Add DC6 Trigger sequence.
Suketu Shah
2015-05-08
drm/i915/skl: Assert the requirements to enter or exit DC5.
Suketu Shah
2015-05-08
drm/i915/skl: Implement enable/disable for Display C5 state.
A.Sunil Kamath
2015-05-08
drm/i915/skl: Add DC5 Trigger Sequence
Suketu Shah
2015-04-16
drm/i915/bxt: Implement enable/disable for Display C9 state
A.Sunil Kamath
2015-04-14
drm/i915/bxt: Define BXT power domains
Satheeshakrishna M
2015-03-17
drm/i915: Spelling s/auxilliary/auxiliary/
Geert Uytterhoeven
2015-03-17
drm/i915/skl: Restore the DDI translation tables when enabling PW1
Damien Lespiau
2015-03-17
drm/i915: Remove unused condition in hsw_power_well_post_enable()
Damien Lespiau
2015-03-17
drm/i915/skl: Restore pipe interrupt registers after power well enabling
Damien Lespiau
2015-03-17
drm/i915/skl: Mirror what we do on HSW for the power well enable log message
Damien Lespiau
2015-03-17
drm/i915/skl: Introduce enable_requested and is_enabled in the power well code
Damien Lespiau
2015-03-17
drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
Damien Lespiau
2015-02-13
drm/i915/skl: Implementation of SKL display power well support
Satheeshakrishna M
2015-01-27
drm/i915/skl: Adding power domains for AUX controllers
Satheeshakrishna M
2015-01-12
Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queued
Daniel Vetter
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