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2015-12-09Merge branch 'linux-4.4' of https://github.com/skeggsb/linux into drm-fixesDave Airlie
Just the one commit I mentioned earlier, making the PGOB workaround the default. * 'linux-4.4' of https://github.com/skeggsb/linux: drm/nouveau/pmu: remove whitelist for PGOB-exit WAR, enable by default
2015-12-09drm/nouveau/pmu: remove whitelist for PGOB-exit WAR, enable by defaultBen Skeggs
NVIDIA have indicated that the workaround is required on all GK10[467] boards that have the PGOB fuse set. I've left the commandline option in place for now, as paranoia. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-12-04drm/nouveau: Fix pre-nv50 pageflip events (v4)Daniel Vetter
Apparently pre-nv50 pageflip events happen before the actual vblank period. Therefore that functionality got semi-disabled in commit af4870e406126b7ac0ae7c7ce5751f25ebe60f28 Author: Mario Kleiner <mario.kleiner.de@gmail.com> Date: Tue May 13 00:42:08 2014 +0200 drm/nouveau/kms/nv04-nv40: fix pageflip events via special case. Unfortunately that hack got uprooted in commit cc1ef118fc099295ae6aabbacc8af94d8d8885eb Author: Thierry Reding <treding@nvidia.com> Date: Wed Aug 12 17:00:31 2015 +0200 drm/irq: Make pipe unsigned and name consistent Triggering a warning when trying to sample the vblank timestamp for a non-existing pipe. There's a few ways to fix this: - Open-code the old behaviour, which just enshrines this slight breakage of the userspace ABI. - Revert Mario's commit and again inflict broken timestamps, again not pretty. - Fix this for real by delaying the pageflip TS until the next vblank interrupt, thereby making it accurate. This patch implements the third option. Since having a page flip interrupt that happens when the pageflip gets armed and not when it completes in the next vblank seems to be fairly common (older i915 hw works very similarly) create a new helper to arm vblank events for such drivers. v2 (Mario Kleiner): - Fix function prototypes in drmP.h - Add missing vblank_put() for pageflip completion without pageflip event. - Initialize sequence number for queued pageflip event to avoid trouble in drm_handle_vblank_events(). - Remove dead code and spelling fix. v3 (Mario Kleiner): - Add a signed-off-by and cc stable tag per Ilja's advice. v4 (Thierry Reding): - Fix kerneldoc typo, discovered by Michel Dänzer - Rearrange tags and changelog Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=106431 Cc: Thierry Reding <treding@nvidia.com> Cc: Mario Kleiner <mario.kleiner.de@gmail.com> Acked-by: Ben Skeggs <bskeggs@redhat.com> Cc: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: stable@vger.kernel.org # v4.3 Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-28Merge branch 'linux-4.4' of ↵Dave Airlie
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes Ben Skeggs wrote: A couple of regression fixes, some more boards whitelisted for a hw bug workaround, gr/ucode fixes for hangs a user is seeing. The changes look larger than they actually are due to the ucode binaries (*.fucN.h) being regenerated. * 'linux-4.4' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau/volt/pwm/gk104: fix an off-by-one resulting in the voltage not being set drm/nouveau/nvif: allow userspace access to its own client object drm/nouveau/gr/gf100-: fix oops when calling zbc methods drm/nouveau/gr/gf117-: assume no PPC if NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK is zero drm/nouveau/gr/gf117-: read NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK from correct GPC drm/nouveau/gr/gf100-: split out per-gpc address calculation macro drm/nouveau/bios: return actual size of the buffer retrieved via _ROM drm/nouveau/instmem: protect instobj list with a spinlock drm/nouveau/pci: enable c800 magic for some unknown Samsung laptop drm/nouveau/pci: enable c800 magic for Clevo P157SM
2015-11-25drm/nouveau/volt/pwm/gk104: fix an off-by-one resulting in the voltage not ↵Martin Peres
being set Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-25drm/nouveau/nvif: allow userspace access to its own client objectBen Skeggs
Regression from "abi16: implement limited interoperability with usif/nvif". Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/gr/gf100-: fix oops when calling zbc methodsBen Skeggs
Somehow missed these two when removing dodgy void casts during the rework. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/gr/gf117-: assume no PPC if NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK ↵Ben Skeggs
is zero fdo#92761 Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/gr/gf117-: read NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK from ↵Ben Skeggs
correct GPC Each GPCCS unit was reading the mask from GPC0, which causes problems on boards where some GPCs are missing PPCs. Part of the fix for fdo#92761. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/gr/gf100-: split out per-gpc address calculation macroBen Skeggs
There's a few places where we need to access a GPC register from ucode, but outside of the falcon's io address space. To do this we need to calculate the offset based on which GPC we're executing on. This used to be done manually, but we've since found a "base" offset that can be added by the hardware. To use this, an extra bit needs to be set in the register address, which is what this macro achieves. There should be no functional change from this commit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/bios: return actual size of the buffer retrieved via _ROMBen Skeggs
Fixes detection of a failed attempt at fetching the entire ROM image in one-shot (a violation of the spec, that works a lot of the time). Tested on a HP Zbook 15 G2. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/instmem: protect instobj list with a spinlockBen Skeggs
No locking is required for the traversal of this list, as it only happens during suspend/resume where nothing else can be executing. Fixes some of the issues noticed during parallel piglit runs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/pci: enable c800 magic for some unknown Samsung laptopBen Skeggs
fdo#70354 - comment #88. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25drm/nouveau/pci: enable c800 magic for Clevo P157SMKarol Herbst
this is needed for my gpu Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-10Merge branch 'akpm' (patches from Andrew)Linus Torvalds
Merge final patch-bomb from Andrew Morton: "Various leftovers, mainly Christoph's pci_dma_supported() removals" * emailed patches from Andrew Morton <akpm@linux-foundation.org>: pci: remove pci_dma_supported usbnet: remove ifdefed out call to dma_supported kaweth: remove ifdefed out call to dma_supported sfc: don't call dma_supported nouveau: don't call pci_dma_supported netup_unidvb: use pci_set_dma_mask insted of pci_dma_supported cx23885: use pci_set_dma_mask insted of pci_dma_supported cx25821: use pci_set_dma_mask insted of pci_dma_supported cx88: use pci_set_dma_mask insted of pci_dma_supported saa7134: use pci_set_dma_mask insted of pci_dma_supported saa7164: use pci_set_dma_mask insted of pci_dma_supported tw68-core: use pci_set_dma_mask insted of pci_dma_supported pcnet32: use pci_set_dma_mask insted of pci_dma_supported lib/string.c: add ULL suffix to the constant definition hugetlb: trivial comment fix selftests/mlock2: add ULL suffix to 64-bit constants selftests/mlock2: add missing #define _GNU_SOURCE
2015-11-11drm/nouveau: fix build failures on all non ARM.Dave Airlie
gk20a is an ARM only GPU, so we can just do the correct thing on ARM but fail on other architectures. The other option was to use SWIOTLB as the define, which means phys_to_page exists, but this seems clearer. Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-11-10nouveau: don't call pci_dma_supportedChristoph Hellwig
Just try to set a 64-bit DMA mask first and retry with the smaller dma_mask if dma_set_mask failed. Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: David Airlie <airlied@linux.ie> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Thierry Reding <treding@nvidia.com> Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-11-03drm/nouveau: bump patchlevel to indicate availability of abi16/nvif interopBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/abi16: implement limited interoperability with usif/nvifBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/abi16: introduce locked variant of nouveau_abi16_get()Ben Skeggs
USIF already takes the client mutex, but will need access to ABI16 data in order to provide some limited interoperability. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/abi16: remove unused argument from nouveau_abi16_get()Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci: enable c800 magic for Medion Erazer X7827Ilia Mirkin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91557 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci: enable c800 magic for Lenovo Y510PIlia Mirkin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70354#c75 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pll/gk104: fix PLL instability due to bad configuration with gddr5Karol Herbst
This patch uses an approach closer to the nvidia driver to configure both PLLs for high gddr5 memory clocks (usually above 2400MHz) Previously nouveau used the one PLL as it was used for the lower clocks and just adjusted the second PLL to get as close as possible to the requested clock. This means for my card, that I got a 4050 MHz clock although 4008 MHz was requested. Now the driver iterates over a list of PLL configuration also used by the nvidia driver and then adjust the second PLL to get near the requested clock. Also it hold to some restriction I found while analyzing the PLL configurations This won't fix all gddr5 high clock issues itself, but it should be fine on hybrid gpu systems as found on many laptops these days. Also switching while normal desktop usage should be a lot more stable than before. v2: move the pll code into ramgk104 Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/clk/g84: Enable reclocking for GDDR3 G94-G200Roy Spliet
Your milage may vary, as it's only been tested on a single G94 and one G96. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristicRoy Spliet
Avoids waiting for VBLANKS that never arrive on headless or otherwise unconventional set-ups. Strategy taken from MEMX. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/fb/ramnv50: Script changes for G94 and upRoy Spliet
10053c is not even read on some cards, and I have no idea exactly what the criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables all features that are never used. The practical effect should be the same as this implementation though. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/fb/ramnv50: Deal with cards without timing entriesRoy Spliet
Like Pierre's G94. We might want to structure Kepler similarly in a follow-up. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/fb/ramnv50: Voltage GPIOsRoy Spliet
Does not seem to be necessary for NVA0, hence untested by me. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/fb/ramgt215: Restructure r111100 calculation for DDR2Roy Spliet
Seems to be mostly equal to DDR3 on < GT218, should improve stability for DDR2 reclocks. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for itRoy Spliet
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific ↵Roy Spliet
to generic In preparation of changing FBVDDQ, as observed on at least one GDDR3 card. While at it, adhere to func.log[1] properly for consistency. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/bios/rammap: Identify DLLoff for >= GF100Roy Spliet
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci: Handle 5-bit and 8-bit tag fieldPierre Moreau
If the hardware supports extended tag field (8-bit ones), then enable it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible number of requests to 32. Apparently bits 7:0 of 0x08841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 v2: Restrict changes to chipsets >= 0x84 v3: * Add nvkm_pci_mask to pci.h * Mask bit 8 before setting it v4: * Rename `add` argument of nvkm_pci_mask to `value` * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset checks v5: * Rebase code on latest PCI structure * Restore PCIe check * Fix namings in nvkm_pci_mask * Rephrase part of the commit message Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/disp,pm: constify nvkm_object_func structuresJulia Lawall
These nvkm_object_func structures are never modified. All other nvkm_object_func structures are declared as const. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gr: add FERMI_COMPUTE_B class to GF110+Ilia Mirkin
GF110+ supports both the A and B compute classes, make sure to accept both. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gr: document mp error 0x10Ilia Mirkin
NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE, which apparently happens when trying to use an atomic operation on local or shared memory (instead of global memory). Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau: fix memory leakSudip Mukherjee
If pm_runtime_get_sync() we were going to "out" but we missed freeing vma. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau: remove unused functionSudip Mukherjee
coverity.com reported that memset was using a buffer of size 0, on checking the code it turned out that the function was not being used. So remove it. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pmu/gk107: enable PGOB codepathsBen Skeggs
Reported to be needed as per fdo#70354 comment #61. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pmu/gk104: check fuse to determine presence of PGOBBen Skeggs
Not 100% confirmed, but seems to match from the few boards I've looked at so far. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci: prepare for chipset-specific initialisation tasksBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by defaultBen Skeggs
Was not able to obtain a trace of NVRM due to kernel version annoyances, however, experimentally confirmed that the WAR we use on NV50/G8x boards works here too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/g94: split implementation from nv40Ben Skeggs
An upcoming patch will implement functionality that we don't use on any NV40 chipset. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pci/g84: split implementation from nv50Ben Skeggs
An upcoming patch will implement functionality that we don't use on the original NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ibus/gf100: increase wait timeout to avoid read faultsSamuel Pitoiset
Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gm204/6: add voltage control using the new gk104 volt classMartin Peres
I got confirmation that we can read and change the voltage with the same code. The divider is also computed correctly on the gm204 we got our hands on. Thanks to Yoshimo on IRC for executing the tests on his gm204! Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gm107: add voltage control using the new gk104 volt classMartin Peres
Let's ignore the other desktop Maxwells until I get my hands on one and confirm that we still can change the voltage. Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03drm/nouveau/volt/gk104: add support for pwm and gpio modesMartin Peres
Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03drm/nouveau/volt: add support for non-vid-based voltage controllersMartin Peres
This patch is not ideal but it definitely beats a rewrite of the current interface and is very self-contained. Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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