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path:
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irqchip
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irq-sifive-plic.c
Age
Commit message (
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Author
2020-11-01
irqchip/sifive-plic: Fix chip_data access within a hierarchy
Greentime Hu
2020-10-25
irqchip/sifive-plic: Fix broken irq_set_affinity() callback
Greentime Hu
2020-06-09
irqchip: RISC-V per-HART local interrupt controller driver
Anup Patel
2020-06-09
RISC-V: Rename and move plic_find_hart_id() to arch directory
Anup Patel
2020-05-25
irqchip/sifive-plic: Improve boot prints for multiple PLIC instances
Anup Patel
2020-05-25
irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present
Anup Patel
2020-05-25
irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()
Anup Patel
2020-05-18
irqchip/sifive-plic: Remove incorrect requirement about number of irq contexts
Wesley W. Terpstra
2020-04-17
irqchip/sifive-plic: Fix maximum priority threshold value
Atish Patra
2020-03-16
irqchip/sifive-plic: Add support for multiple PLICs
Atish Patra
2020-03-16
irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline
Atish Patra
2020-01-24
Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...
irq-core-2020-01-28
Thomas Gleixner
2020-01-20
irqchip/sifive-plic: Support irq domain hierarchy
Yash Shah
2020-01-04
riscv: prefix IRQ_ macro names with an RV_ namespace
Paul Walmsley
2019-11-05
riscv: abstract out CSR names for supervisor vs machine mode
Christoph Hellwig
2019-10-25
Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...
Thomas Gleixner
2019-10-25
irqchip/sifive-plic: Skip contexts except supervisor in plic_init()
Alan Mikhak
2019-10-14
Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...
Thomas Gleixner
2019-09-18
irqchip/sifive-plic: Switch to fasteoi flow
Marc Zyngier
2019-09-05
irqchip/sifive-plic: set max threshold for ignored handlers
Christoph Hellwig
2019-02-21
irqchip/sifive-plic: Implement irq_set_affinity() for SMP host
Anup Patel
2019-02-21
irqchip/sifive-plic: Differentiate between PLIC handler and context
Anup Patel
2019-02-21
irqchip/sifive-plic: Add warning in plic_init() if handler already present
Anup Patel
2019-02-21
irqchip/sifive-plic: Pre-compute context hart base and enable base
Anup Patel
2019-02-14
irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.
Atish Patra
2018-10-22
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
2018-10-22
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Palmer Dabbelt
2018-08-13
irqchip: add a SiFive PLIC driver
Christoph Hellwig