| Age | Commit message (Collapse) | Author |
|---|
|
Delete/fixup few includes in anticipation of global -isystem compile
option removal.
Note: crypto/aegis128-neon-inner.c keeps <stddef.h> due to redefinition
of uintptr_t error (one definition comes from <stddef.h>, another from
<linux/types.h>).
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
|
|
AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces.
Current pinctrl driver only define the first sgpio master and slave
interfaces.
The second SGPIO master and slave interfaces should be added in
pinctrl driver as well.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210525055308.31069-4-steven_lee@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Commit 6726fbff19bf ("pinctrl: aspeed: Fix GPI only function problem.")
fixes access to GPIO banks T and U on the AST2600. Both banks contain
input-only pins and the GPIO pin function is named GPITx and GPIUx
respectively. Unfortunately the fix had a negative impact on GPIO banks
D and E for the AST2400 and AST2500 where the GPIO pass-through
functions take similar "GPI"-style names. The net effect on the older
SoCs was that when the GPIO subsystem requested a pin in banks D or E be
muxed for GPIO, they were instead muxed for pass-through mode.
Mistakenly muxing pass-through mode e.g. breaks booting the host on
IBM's Witherspoon (AC922) platform where GPIOE0 is used for FSI.
Further exploit the names in the provided expression structure to
differentiate pass-through from pin-specific GPIO modes.
This follow-up fix gives the expected behaviour for the following tests:
Witherspoon BMC (AST2500):
1. Power-on the Witherspoon host
2. Request GPIOD1 be muxed via /sys/class/gpio/export
3. Request GPIOE1 be muxed via /sys/class/gpio/export
4. Request the balls for GPIOs E2 and E3 be muxed as GPIO pass-through
("GPIE2" mode) via a pinctrl hog in the devicetree
Rainier BMC (AST2600):
5. Request GPIT0 be muxed via /sys/class/gpio/export
6. Request GPIU0 be muxed via /sys/class/gpio/export
Together the tests demonstrate that all three pieces of functionality
(general GPIOs via 1, 2 and 3, input-only GPIOs via 5 and 6, pass-through
mode via 4) operate as desired across old and new SoCs.
Fixes: 9b92f5c51e9a ("pinctrl: aspeed: Fix GPI only function problem.")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cc: Billy Tsai <billy_tsai@aspeedtech.com>
Cc: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20201126063337.489927-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
AST2600 has two USB ports, A, B:
Port A supports 4 distinct modes:
1. PCIe EHCI to Hub
2. Hub to PHY
3. BMC EHCI to PHY
4. PCIe EHCI to PHY
Port B support 3 modes:
1. USB1.1 HID controller
2. USB2.0 Device controller
3. BMC EHCI port2
Implement pinmux support by mapping each ports' functions onto a single
pin group for each port.
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191202061432.3996-4-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit),
corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8
Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-8-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Signal descriptors can represent multi-bit bitfields and so have
explicit "enable" and "disable" states. However many descriptor
instances only describe a single bit, and so the SIG_DESC_SET() macro is
provides an abstraction for the single-bit cases: Its expansion
configures the "enable" state to set the bit and "disable" to clear.
SIG_DESC_CLEAR() was introduced to provide a similar single-bit
abstraction for for descriptors to clear the bit of interest. However
its behaviour was defined as the literal inverse of SIG_DESC_SET() - the
impact is the bit of interest is set in the disable path. This behaviour
isn't intuitive and doesn't align with how we want to use the macro in
practice, so make it clear the bit for both the enable and disable
paths.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-6-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.4 kernel cycle:
Core changes:
- Fix errors in example code in the documentation.
New drivers:
- Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
Ingenic driver.
- Support Cirrus Logic Madera CS47L92 and CS47L15.
- Support Allwinner Sunxi V3S.
- Support Aspeed 2600 BMC.
- Support Qualcomm SC7180.
- Support Marvell MVEBU CS115.
Driver improvements:
- Clean up a few drivers to use the devm_platform_ioremap_resource()
helper.
- Pass the irqchip when registering the gpio_chip in some pin
controllers that are also GPIO controllers.
- Support suspend/resume in the Tegra driver.
- Support pull-up on the Broadcom BCM2711.
- The Intel driver can now request locked pads.
- Fix the UFS reset pin in the Qualcomm SDM845 driver"
* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
pinctrl: bcm: remove redundant assignment to pointer log
pinctrl: iproc: Add 'get_direction' support
pinctrl: iproc-gpio: Handle interrupts for multiple instances
pinctrl: iproc-gpio: Fix incorrect pinconf configurations
pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
pinctrl: qcom: sdm845: Fix UFS_RESET pin
pinctrl: mvebu: add additional variant for standalone CP115
pinctrl: mvebu: Add CP110 missing pin functionality
dt-bindings: cp110: document the new CP115 pinctrl compatible
pinctrl: bcm2835: Pass irqchip when adding gpiochip
pinctrl: meson: meson: Add of_node_put() before return
pinctrl/gpio: Take MUX usage into account
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
pinctrl: amd: disable spurious-firing GPIO IRQs
pinctrl: rza2: Include the appropriate headers
pinctrl: rza2: Drop driver use of consumer flags
...
|
|
Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps")
was determined to be a partial fix to the problem of acquiring the LPC
Host Controller and GFX regmaps: The AST2500 pin controller may need to
fetch syscon regmaps during expression evaluation as well as when
setting mux state. For example, this case is hit by attempting to export
pins exposing the LPC Host Controller as GPIOs.
An optional eval() hook is added to the Aspeed pinmux operation struct
and called from aspeed_sig_expr_eval() if the pointer is set by the
SoC-specific driver. This enables the AST2500 to perform the custom
action of acquiring its regmap dependencies as required.
John Wang tested the fix on an Inspur FP5280G2 machine (AST2500-based)
where the issue was found, and I've booted the fix on Witherspoon
(AST2500) and Palmetto (AST2400) machines, and poked at relevant pins
under QEMU by forcing mux configurations via devmem before exporting
GPIOs to exercise the driver.
Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers")
Fixes: 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps")
Reported-by: John Wang <wangzqbj@inspur.com>
Tested-by: John Wang <wangzqbj@inspur.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190829071738.2523-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Linux 5.3-rc5
|
|
The complement of SIG_DESC_SET().
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190729055604.13239-6-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The AST2400 and AST2500 SoCs only exposed one pin group per function.
Lone pin groups drove some implementation simplifications in the ASPEED
pinmux infrastructure that is now invalid for the AST2600, which
supports multiple groups per function for some functions on the chip
(SMBus Alert pins and UARTs among others).
This patch reworks the macro jungle to enable support for multiple pin
groups. In the process we inflict some collateral damage on the existing
AST2400 and AST2500 drivers, but the rework is mostly a relatively
straight-forward, automated transform of adding the pin name as an
argument to some macro calls and implementing wrappers to paper over
groups in the cases where there aren't multiple.
As previously documented, the macro infrastructure exposes mux
configuration as symbols in the source file which are used to detect
accidental duplication. Previously these symbols were named in terms of
the signal for a given expression. As the AST2600 supports multiple pin
groups for a function, the signal name on its own is no-longer unique,
and we must switch to the (signal, group) tuple. However, this means
that we can no-longer derive the signal expression symbol name from the
signal name alone, which among other cases, impacts the operation of the
PIN_DECL_x() macros.
To fix that and avoid requiring we awkwardly provide the associated
group name for every signal for every PIN_DECL_x() invocation, instead
opportunistically alias the name of the signal expression symbol from
the unique (signal, group) tuple to the also unique (pin, signal) tuple,
then reference the alias symbol in the tables generated by PIN_DECL_x().
This way we do not require extra group parameters for PIN_DECL_x() as
the pin name was already provided as an argument, and instead simply
require that the pin name be provided to the expression declaration
macros in order to generate the alias symbol.
The patch implements the alias strategy and fixes up all the expression
definition macro calls in the AST2400 and AST2500 drivers to account for
pin groups. Given the implementation strategy has the property that
compilation either fails or loudly warns for bad pin descriptions, this
patch is theoretically tested by successfully compiling both affected
drivers. For a more practical test I've inspected the diff of the
content of the pinctrl debugfs entries before and after the patch under
qemu; all pins, functions and groups match.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
This case is common in the AST2600, so add to the collection.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190729055604.13239-4-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Rename macros as follows:
* s/SS_PIN_DECL()/PIN_DECL_1()/
* s/MS_PIN_DECL()/PIN_DECL_2()/
* s/MS_PIN_DECL_()/PIN_DECL_()/
This is in preparation for adding PIN_DECL_3(). We could clean this up
with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far
given how much of a macro jungle we already have.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
While sorting out some devicetree issues I found that the pinctrl driver
was failing to acquire its GFX regmap even though the phandle was
present in the devicetree:
[ 0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail
Without access to the GFX regmap we fail to configure the mux for the
VPO function:
[ 1.548866] pinctrl core: add 1 pinctrl maps
[ 1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO
[ 1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display
[ 1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display
...
[ 1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display
[ 1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display
[ 1.563113] Muxing pin 144 for VPO
[ 1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000
[ 1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back
This turned out to be a simple problem of timing: The ASPEED pinctrl
driver is probed during arch_initcall(), while GFX is processed much
later. As such the GFX syscon is not yet registered during the pinctrl
probe() and we get an -EPROBE_DEFER when we try to look it up, however
we must not defer probing the pinctrl driver for the inability to mux
some GFX-related functions.
Switch to lazily grabbing the regmaps when they're first required by the
mux configuration. This generates a bit of noise in the patch as we have
to drop the `const` qualifier on arguments for several function
prototypes, but has the benefit of working.
I've smoke tested this for the ast2500-evb under qemu with a dummy
graphics device. We now succeed in our attempts to configure the SoC's
VPO pinmux function.
Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The ASPEED pinctrl driver implementations make heavy use of macros to
minimise tedium of implementation and maximise the chance that the
compiler will catch errors in defining signal and pin configurations.
While the goal of minimising errors is achieved, it is at the cost of
the complexity of the macros.
Document examples of the expanded form of pin declarations to
demonstrate the operation of the macros.
Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-9-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
ASPEED have completely rearranged the System Control Unit register
layout with the AST2600. The existing code took advantage of the fact
that the AST2400 and AST2500 had layouts that were similar enough to
have little impact on the pinmux infrastructure (though there is a wart
with read-modify-write vs write-1-clear semantics of the hardware
strapping registers between the two).
Given that any similarity has been thrown out with the AST2600, separate
out the function applying an expression state to be driver-specific.
With it, extract out the pinmux macro jungle to its own header and
implementation so the pieces can be composed without dependency cycles.
Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
