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2018-12-31Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Misc driver updates for platforms, many of them power related. - Rockchip adds power domain support for rk3066 and rk3188 - Amlogic adds a power measurement driver - Allwinner adds SRAM support for three platforms (F1C100, H5, A64 C1) - Wakeup and ti-sysc (platform bus) fixes for OMAP/DRA7 - Broadcom fixes suspend/resume with Thumb2 kernels, and improves stability of a handful of firmware/platform interfaces - PXA completes their conversion to dmaengine framework - Renesas does a bunch of PM cleanups across many platforms - Tegra adds support for suspend/resume on T186/T194, which includes some driver cleanups and addition of wake events - Tegra also adds a driver for memory controller (EMC) on Tegra2 - i.MX tweaks power domain bindings, and adds support for i.MX8MQ in GPC - Atmel adds identifiers and LPDDR2 support for a new SoC, SAM9X60 and misc cleanups across several platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (73 commits) ARM: at91: add support in soc driver for new SAM9X60 ARM: at91: add support in soc driver for LPDDR2 SiP memory: omap-gpmc: Use of_node_name_eq for node name comparisons bus: ti-sysc: Check for no-reset and no-idle flags at the child level ARM: OMAP2+: Check also the first dts child for hwmod flags soc: amlogic: meson-clk-measure: Add missing REGMAP_MMIO dependency soc: imx: gpc: Increase GPC_CLK_MAX to 7 soc: renesas: rcar-sysc: Fix power domain control after system resume soc: renesas: rcar-sysc: Merge PM Domain registration and linking soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B} dt-bindings: sram: sunxi: Add compatible for the A64 SRAM C1 dt-bindings: sram: sunxi: Add bindings for the H5 with SRAM C1 dt-bindings: sram: Add Allwinner suniv F1C100s soc: sunxi: sram: Add support for the H5 SoC system control soc: sunxi: sram: Enable EMAC clock access for H3 variant soc: imx: gpcv2: add support for i.MX8MQ SoC soc: imx: gpcv2: move register access table to domain data soc: imx: gpcv2: prefix i.MX7 specific defines dmaengine: pxa: make the filter function internal ...
2018-12-14soc/tegra: pmc: Drop SMP dependency from CPU APIsJon Hunter
When CONFIG_SMP is disabled, the tegra clk driver now fails to build: drivers/clk/tegra/clk-tegra30.c: In function ‘tegra30_cpu_rail_off_ready’: drivers/clk/tegra/clk-tegra30.c:1151:2: error: implicit declaration of function ‘tegra_pmc_cpu_is_powered’ [-Werror=implicit-function-declaration] cpu_pwr_status = tegra_pmc_cpu_is_powered(1) || ^ Fix the above error by removing the CONFIG_SMP ifdef around the declaration around the PMC CPU APIs because although these are not needed for non-SMP configurations, there is no harm in including these for non-SMP builds either. Fixes: 61866523ed6e ("clk: tegra30: Use Tegra CPU powergate helper function") Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-11-28soc/tegra: pmc: Add initial Tegra194 wake eventsThierry Reding
Tegra194 supports 96 wake events in total. Many of them are never used, so only the most common ones (RTC alarm and power key) are currently defined. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-28soc/tegra: pmc: Add initial Tegra186 wake eventsThierry Reding
Tegra186 support 96 wake events in total. Many of them are never used, so only the most common ones (RTC alarm and power key) are currently defined. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-28soc/tegra: pmc: Add wake event supportThierry Reding
The power management controller has top-level controls that allow certain interrupts (such as from the RTC or a subset of GPIOs) to wake the system from sleep. Implement infrastructure to support these wake events. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-28soc/tegra: pmc: Add Tegra194 supportThierry Reding
The PMC controller on Tegra194 has a couple of new I/O pads and drops others compared to Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-22soc/tegra: pmc: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-22soc/tegra: Don't leak device tree node referenceYangtao Li
of_find_node_by_path() acquires a reference to the node returned by it and that reference needs to be dropped by its caller. soc_is_tegra() doesn't do that, so fix it. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> [treding: slightly rewrite to avoid inline comparison] Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-08soc/tegra: pmc: Drop locking from tegra_powergate_is_powered()Dmitry Osipenko
This fixes splats like the one below if CONFIG_DEBUG_ATOMIC_SLEEP=y and machine (Tegra30) booted with SMP=n or all secondary CPU's are put offline. Locking isn't needed because it protects atomic operation. BUG: sleeping function called from invalid context at kernel/locking/mutex.c:254 in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/0 CPU: 0 PID: 0 Comm: swapper/0 Tainted: G C 4.18.0-next-20180821-00180-gc3ebb6544e44-dirty #823 Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [<c01134f4>] (unwind_backtrace) from [<c010db2c>] (show_stack+0x20/0x24) [<c010db2c>] (show_stack) from [<c0bd0f3c>] (dump_stack+0x94/0xa8) [<c0bd0f3c>] (dump_stack) from [<c0151df8>] (___might_sleep+0x13c/0x174) [<c0151df8>] (___might_sleep) from [<c0151ea0>] (__might_sleep+0x70/0xa8) [<c0151ea0>] (__might_sleep) from [<c0bec2b8>] (mutex_lock+0x2c/0x70) [<c0bec2b8>] (mutex_lock) from [<c0589844>] (tegra_powergate_is_powered+0x44/0xa8) [<c0589844>] (tegra_powergate_is_powered) from [<c0581a60>] (tegra30_cpu_rail_off_ready+0x30/0x74) [<c0581a60>] (tegra30_cpu_rail_off_ready) from [<c0122244>] (tegra30_idle_lp2+0xa0/0x108) [<c0122244>] (tegra30_idle_lp2) from [<c0853438>] (cpuidle_enter_state+0x140/0x540) [<c0853438>] (cpuidle_enter_state) from [<c08538a4>] (cpuidle_enter+0x40/0x4c) [<c08538a4>] (cpuidle_enter) from [<c01595e0>] (call_cpuidle+0x30/0x48) [<c01595e0>] (call_cpuidle) from [<c01599f8>] (do_idle+0x238/0x28c) [<c01599f8>] (do_idle) from [<c0159d28>] (cpu_startup_entry+0x28/0x2c) [<c0159d28>] (cpu_startup_entry) from [<c0be76c8>] (rest_init+0xd8/0xdc) [<c0be76c8>] (rest_init) from [<c1200f50>] (start_kernel+0x41c/0x430) Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-08soc/tegra: pmc: Add sysfs entries for reset infoSandipan Patra
Implement read-only reset_reason and reset_level sysfs attributes that can be used to query the reset reason and level at runtime. Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-11-08soc/tegra: pmc: Don't power-up XUSB power-domainsJon Hunter
Now that the Tegra xHCI driver manages the XUSB power-domains itself, remove the code to power-up the power-domains used by the xHCI device from the PMC driver on boot. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-10-29Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "The most noteworthy SoC driver changes this time include: - The TEE subsystem gains an in-kernel interface to access the TEE from device drivers. - The reset controller subsystem gains a driver for the Qualcomm Snapdragon 845 Power Domain Controller. - The Xilinx Zynq platform now has a firmware interface for its platform management unit. This contains a firmware "ioctl" interface that was a little controversial at first, but the version we merged solved that by not exposing arbitrary firmware calls to user space. - The Amlogic Meson platform gains a "canvas" driver that is used for video processing and shared between different high-level drivers. The rest is more of the usual, mostly related to SoC specific power management support and core drivers in drivers/soc: - Several Renesas SoCs (RZ/G1N, RZ/G2M, R-Car V3M, RZ/A2M) gain new features related to power and reset control. - The Mediatek mt8183 and mt6765 SoC platforms gain support for their respective power management chips. - A new driver for NXP i.MX8, which need a firmware interface for power management. - The SCPI firmware interface now contains support estimating power usage of performance states - The NVIDIA Tegra "pmc" driver gains a few new features, in particular a pinctrl interface for configuring the pads. - Lots of small changes for Qualcomm, in particular the "smem" device driver. - Some cleanups for the TI OMAP series related to their sysc controller. Additional cleanups and bugfixes in SoC specific drivers include the Meson, Keystone, NXP, AT91, Sunxi, Actions, and Tegra platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (129 commits) firmware: tegra: bpmp: Implement suspend/resume support drivers: clk: Add ZynqMP clock driver dt-bindings: clock: Add bindings for ZynqMP clock driver firmware: xilinx: Add zynqmp IOCTL API for device control Documentation: xilinx: Add documentation for eemi APIs MAINTAINERS: imx: include drivers/firmware/imx path firmware: imx: add misc svc support firmware: imx: add SCU firmware driver support reset: Fix potential use-after-free in __of_reset_control_get() dt-bindings: arm: fsl: add scu binding doc soc: fsl: qbman: add interrupt coalesce changing APIs soc: fsl: bman_portals: defer probe after bman's probe soc: fsl: qbman: Use last response to determine valid bit soc: fsl: qbman: Add 64 bit DMA addressing requirement to QBMan soc: fsl: qbman: replace CPU 0 with any online CPU in hotplug handlers soc: fsl: qbman: Check if CPU is offline when initializing portals reset: qcom: PDC Global (Power Domain Controller) reset controller dt-bindings: reset: Add PDC Global binding for SDM845 SoCs reset: Grammar s/more then once/more than once/ bus: ti-sysc: Just use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS ...
2018-10-04soc: Convert to using %pOFn instead of device_node.nameRob Herring
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Li Yang <leoyang.li@nxp.com> Cc: David Brown <david.brown@linaro.org> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-soc@vger.kernel.org Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Qiang Zhao <qiang.zhao@nxp.com> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
2018-08-27soc/tegra: pmc: Implement pad configuration via pinctrlAapo Vienamo
Register a pinctrl device and implement get and set functions for PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27soc/tegra: pmc: Remove public pad voltage APIsAapo Vienamo
Make tegra_io_pad_set_voltage() and tegra_io_pad_get_voltage() static and remove the prototypes from pmc.h. Remove enum tegra_io_pad_voltage and use the defines from <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> instead. These functions aren't used outside of the pmc driver and new use cases should use the pinctrl interface instead. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27soc/tegra: pmc: Use X macro to generate IO pad tablesAapo Vienamo
Refactor the IO pad tables into macro tables so that they can be reused to generate pinctrl pin descriptors. Also add a name field which is needed by pinctrl. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27soc/tegra: pmc: Implement tegra_io_pad_is_powered()Aapo Vienamo
Implement a function to query whether a pad is in deep power down mode. This is needed by the pinctrl callbacks. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27soc/tegra: pmc: Factor out DPD register bit calculationAapo Vienamo
Factor out the the code to calculate the correct DPD register and bit number for a given pad. This logic will be needed to query the status register. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27soc/tegra: pmc: Fix pad voltage configuration for Tegra186Aapo Vienamo
Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table and the AO_HV pad. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-08-27soc/tegra: pmc: Fix child-node lookupJohan Hovold
Fix child-node lookup during probe, which ended up searching the whole device tree depth-first starting at the parent rather than just matching on its children. To make things worse, the parent pmc node could end up being prematurely freed as of_find_node_by_name() drops a reference to its first argument. Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC") Cc: stable <stable@vger.kernel.org> # 4.0 Cc: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Johan Hovold <johan@kernel.org> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-06-09Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time we have a good set of changes to the core framework that do some general cleanups, but nothing too major. The majority of the diff goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is introduced for Actions Semi so it takes up some lines to add all the different types, and the Qualcomm diff is there because we add support for two SoCs and it's quite a bit of data. Otherwise the big driver updates are on TI Davinci and Amlogic platforms. And then the long tail of driver updates for various fixes and stuff follows after that. Core: - debugfs cleanups removing error checking and an unused provider API - Removal of a clk init typedef that isn't used - Usage of match_string() to simplify parent string name matching - OF clk helpers moved to their own file (linux/of_clk.h) - Make clk warnings more readable across kernel versions New Drivers: - Qualcomm SDM845 GCC and Video clk controllers - Qualcomm MSM8998 GCC - Actions Semi S900 SoC support - Nuvoton npcm750 microcontroller clks - Amlogic axg AO clock controller Removed Drivers: - Deprecated Rockchip clk-gate driver Updates: - debugfs functions stopped checking return values - Support for the MSIOF module clocks on Rensas R-Car M3-N - Support for the new Rensas RZ/G1C and R-Car E3 SoCs - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs - Berlin and Amlogic SPDX tagging - Usage of of_clk_get_parent_count() in more places - Proper implementation of the CDEV1/2 clocks on Tegra20 - Allwinner H6 PRCM clock support and R40 EMAC support - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet - Round closest support for meson's mpll driver - Support for meson8b nand clocks and gxbb video decoder clocks - Mediatek mali clks - STM32MP1 fixes - Uniphier LD11/LD20 stream demux system clock" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) clk: qcom: Export clk_fabia_pll_configure() clk: bcm: Update and add Stingray clock entries dt-bindings: clk: Update Stingray binding doc clk-si544: Properly round requested frequency to nearest match clk: ingenic: jz4770: Add 150us delay after enabling VPU clock clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle clk: ingenic: jz4770: Change OTG from custom to standard gated clock clk: ingenic: Support specifying "wait for clock stable" delay clk: ingenic: Add support for clocks whose gate bit is inverted clk: use match_string() helper clk: bcm2835: use match_string() helper clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions clk: imx6: add EPIT clock support clk: mvebu: use correct bit for 98DX3236 NAND ...
2018-05-08soc/tegra: pmc: Don't allocate struct tegra_powergate on stackViresh Kumar
With a later commit an instance of the struct device will be added to struct genpd and with that the size of the struct tegra_powergate will be over 1024 bytes. That generates following warning: drivers/soc/tegra/pmc.c:579:1: warning: the frame size of 1200 bytes is larger than 1024 bytes [-Wframe-larger-than=] Avoid such warnings by allocating the structure dynamically. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com>
2018-05-02soc/tegra: pmc: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven
As of_clk_get_parent_count() returns zero on failure, while of_count_phandle_with_args() might return a negative error code, this also fixes the issue of possibly using a very big number in the allocation below. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-19soc/tegra: pmc: Use the new reset APIs to manage reset controllersVivek Gautam
Make use of of_reset_control_array_get_exclusive() to manage an array of reset controllers available with the device. Cc: Jon Hunter <jonathanh@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> [p.zabel@pengutronix.de: switch to hidden reset control array] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08soc/tegra: pmc: Pass PMC to tegra_powergate_power_up()Thierry Reding
tegra_powergate_sequence_power_up() makes up a struct tegra_powergate from scratch in order to reuse the same code as used by the generic PM domain implementation. However, subsequent patches will need to access the struct tegra_pmc * embedded in the powergate structure, so we need to make sure we always pass it in. Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08soc/tegra: pmc: MBIST work around for Tegra210Peter De Schrijver
Apply the memory built-in self test work around when ungating certain Tegra210 power domains. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08soc/tegra: pmc: Add Tegra194 compatibility stringMikko Perttunen
The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08soc/tegra: Add Tegra194 SoC configuration optionMikko Perttunen
Add the configuration option to enable support for the Tegra194 system- on-chip. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21soc/tegra: fuse: Explicitly request DMA channel from APB DMA driverDmitry Osipenko
Currently fuse driver requests DMA channel from an arbitrary DMA device, it is not a problem since there is only one DMA provider for Tegra20 yet, but it may become troublesome if another provider will appear. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21soc/tegra: fuse: Fix reading registers using DMA on Tegra20Dmitry Osipenko
FUSE driver doesn't configure DMA channel properly, because of it DMA transfer is never issued and tegra20_fuse_read() always return 0x0. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: pmc: Consolidate Tegra186 supportThierry Reding
Move Tegra186 support to the consolidated PMC driver to reduce some of the duplication and also gain I/O pad functionality on the new SoC as a side-effect. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: pmc: Parameterize driverThierry Reding
Parameterize some aspects of the driver in preparation for Tegra186 PMC support. Initially the Tegra186 driver had been split off into an extra driver, but it turns out the backwards-compatibility break isn't as bad as originally assumed, so with a little parameterization the same code can be used to keep supporting all SoC generations. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: fuse: Add Tegra186 chip ID supportThierry Reding
The register region containing chip ID information has been relocated in Tegra186 and changed in backwards-incompatible ways. Add a compatible string to allow the driver to make the distinction. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: fuse: Warn if accessing unmapped registersThierry Reding
If the FUSE registers are accessed but the region is not mapped, warn and return 0. This potentially catches hard to diagnose bugs because the accesses happen before any kernel log output. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: fuse: Move register mapping checkThierry Reding
The tegra_read_chipid() function can be called from places other than tegra_get_chip_id(), so the check for a valid mapping of the MISC registers needs to be moved to tegra_read_chipid() to catch all potential accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: fuse: Add Tegra186 supportTimo Alho
Tegra210 and Tegra186 are mostly compatible from a fuses point of view. However, speedo support is implemented in the BPMP firmware, hence the implementation needs to be skipped in the fuses driver. Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> [treding@nvidia.com: reword commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-11-16Merge tag 'armsoc-drivers' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "This branch contains platform-related driver updates for ARM and ARM64, these are the areas that bring the changes: New drivers: - driver support for Renesas R-Car V3M (R8A77970) - power management support for Amlogic GX - a new driver for the Tegra BPMP thermal sensor - a new bus driver for Technologic Systems NBUS Changes for subsystems that prefer to merge through arm-soc: - the usual updates for reset controller drivers from Philipp Zabel, with five added drivers for SoCs in the arc, meson, socfpa, uniphier and mediatek families - updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla, Heiner Kallweit and Lorenzo Pieralisi Changes specific to some ARM-based SoC - the Freescale/NXP DPAA QBMan drivers from PowerPC can now work on ARM as well - several changes for power management on Broadcom SoCs - various improvements on Qualcomm, Broadcom, Amlogic, Atmel, Mediatek - minor Cleanups for Samsung, TI OMAP SoCs" [ NOTE! This doesn't work without the previous ARM SoC device-tree pull, because the R8A77970 driver is missing a header file that came from that pull. The fact that this got merged afterwards only fixes it at this point, and bisection of that driver will fail if/when you walk into the history of that driver. - Linus ] * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (96 commits) soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader bus: add driver for the Technologic Systems NBUS memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg() soc: qcom: remove unused label soc: amlogic: gx pm domain: add PM and OF dependencies drivers/firmware: psci_checker: Add missing destroy_timer_on_stack() dt-bindings: power: add amlogic meson power domain bindings soc: amlogic: add Meson GX VPU Domains driver soc: qcom: Remote filesystem memory driver dt-binding: soc: qcom: Add binding for rmtfs memory of: reserved_mem: Accessor for acquiring reserved_mem of/platform: Generalize /reserved-memory handling soc: mediatek: pwrap: fix fatal compiler error soc: mediatek: pwrap: fix compiler errors arm64: mediatek: cleanup message for platform selection soc: Allow test-building of MediaTek drivers soc: mediatek: place Kconfig for all SoC drivers under menu soc: mediatek: pwrap: add support for MT7622 SoC soc: mediatek: pwrap: add common way for setup CS timing extenstion soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap ..
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-10-19soc/tegra: bpmp: Check BPMP response return codeTimo Alho
Add checks for the return code in BPMP response messages. Signed-off-by: Timo Alho <talho@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-23soc/tegra: fuse: Add missing semi-colonThierry Reding
Commit 8a46828e623c ("soc/tegra: Register SoC device") added a new initcall, but forgot to terminate the line with a semi-colon. Some recent versions of GCC seem to report this as an error. Fixes: 8a46828e623c ("soc/tegra: Register SoC device") Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-08-23soc/tegra: Restrict SoC device registration to TegraThierry Reding
Commit 8a46828e623c ("soc/tegra: Register SoC device") added an initcall to register the SoC device on Tegra. However, that code is unrestricted and will run on all platforms, causing unwanted warnings. Fix this by first checking that we're running on hardware that supports the fuses block that we use to provide SoC information. Fixes: 8a46828e623c ("soc/tegra: Register SoC device") Reported-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-08-17soc/tegra: Register SoC deviceThierry Reding
Move this code from arch/arm/mach-tegra and make it common among 32-bit and 64-bit Tegra SoCs. This is slightly complicated by the fact that on 32-bit Tegra, the SoC device is used as the parent for all devices that are instantiated from device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-07-31soc/tegra: Fix bad of_node_put() in powergate initTuomas Tynkkynen
The for_each_child_of_node macro itself maintains the correct reference count of the nodes so the explicit of_node_put() call causes a warning: [ 0.098960] OF: ERROR: Bad of_node_put() on /pmc@7000e400/powergates/xusba [ 0.098981] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.3 #1-NixOS [ 0.098996] Hardware name: NVIDIA Jetson TX1 Developer Kit (DT) [ 0.099011] Call trace: [ 0.099034] [<ffff00000808a048>] dump_backtrace+0x0/0x2a0 [ 0.099051] [<ffff00000808a30c>] show_stack+0x24/0x30 [ 0.099069] [<ffff0000084a6494>] dump_stack+0x9c/0xc0 [ 0.099090] [<ffff000008992214>] of_node_release+0xa4/0xa8 [ 0.099107] [<ffff0000084a9270>] kobject_put+0x90/0x1f8 [ 0.099124] [<ffff0000089914ac>] of_node_put+0x24/0x30 [ 0.099140] [<ffff00000898cec4>] __of_get_next_child+0x4c/0x70 [ 0.099155] [<ffff00000898cf28>] of_get_next_child+0x40/0x68 [ 0.099173] [<ffff0000090a099c>] tegra_pmc_early_init+0x4e8/0x5ac [ 0.099189] [<ffff00000808399c>] do_one_initcall+0x5c/0x168 [ 0.099206] [<ffff000009050c98>] kernel_init_freeable+0xd4/0x240 [ 0.099224] [<ffff000008b2d658>] kernel_init+0x18/0x108 [ 0.099238] [<ffff0000080836c0>] ret_from_fork+0x10/0x50 (It's not very apparent from the OF documentation that of_node_put() is not needed; the macro itself has no docstring and of_get_next_child() used in the implementation begins with "Returns a node pointer with refcount incremented" but then only at the very end of the docstring the crucial part "Decrements the refcount of prev" is mentioned.) Fixes: a38045121bf42 ("soc/tegra: pmc: Add generic PM domain support") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-13soc/tegra: flowctrl: Fix error handlingChristophe Jaillet
It is likely that returning returned by 'devm_ioremap_resource()' is expected here instead of something related to 'base' which should be a valid pointer at this point. Fixes: 841fd94c43a4 ("soc/tegra: flowctrl: Add basic platform driver") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-13soc/tegra: bpmp: Implement generic PM domainsThierry Reding
The BPMP firmware, found on Tegra186 and later, provides an ABI that can be used to enable and disable power to several power partitions in Tegra SoCs. The ABI allows for enumeration of the available power partitions, so the driver can be reused on future generations, provided the BPMP ABI remains stable. Based on work by Stefan Kristiansson <stefank@nvidia.com> and Mikko Perttunen <mperttunen@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04soc/tegra: Add initial flowctrl support for Tegra132/210Jon Hunter
Tegra132 and Tegra210 support the flowctrl module and so add initial support for these devices. Please note that Tegra186 does not support the flowctrl module, so update the initialisation function such that we do not fall back and attempt to map the 'hardcoded' address range for Tegra186. Furthermore 64-bit Tegra devices have always had the flowctrl node defined in their device-tree and so only use the 'hardcoded' addresses for 32-bit Tegra devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04soc/tegra: flowctrl: Add basic platform driverJon Hunter
Add a simple platform driver for the flowctrl module so that it gets registered as a proper device. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04soc/tegra: Move Tegra flowctrl driverJon Hunter
The flowctrl driver is required for both ARM and ARM64 Tegra devices and in order to enable support for it for ARM64, move the Tegra flowctrl driver into drivers/soc/tegra. By moving the flowctrl driver, tegra_flowctrl_init() is now called by via an early initcall and to prevent this function from attempting to mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()' is also added. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04soc: tegra: make fuse-tegra explicitly non-modularPaul Gortmaker
The Makefiles currently controlling compilation of this code is: drivers/soc/tegra/Makefile:obj-y += fuse/ drivers/soc/tegra/fuse/Makefile:obj-y += fuse-tegra.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modularity so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04soc/tegra: Implement Tegra186 PMC supportThierry Reding
The power management controller on Tegra186 has changed in backwards- incompatible ways with respect to earlier generations. This implements a new driver that supports inversion of the PMU interrupt as well as the "recovery", "bootloader" and "forced-recovery" reboot commands. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>